Designing Bipolar Transistor Radio Frequency Integrated Circuits (Artech House Microwave Library)

Designing Bipolar Transistor Radio Frequency Integrated Circuits

For a listing of recent titles in the Artech House Microwave Library, turn to the back of this book.

Designing Bipolar Transistor Radio Frequency Integrated Circuits Allen A. Sweet

artechhouse.com

Library of Congress Cataloging-in-Publication Data A catalog record of this book is available from the Library of Congress.

British Library Cataloguing in Publication Data A catalogue record of this book is available from the British Library.

ISBN 13: 978-1-59693-128-2 ISBN 10: 1-59693-128-0

Cover design by Igor Valdman

© 2008 ARTECH HOUSE, INC. 685 Canton Street Norwood, MA 02062 All rights reserved. Printed and bound in the United States of America. No part of this book may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage and retrieval system, without permission in writing from the publisher. All terms mentioned in this book that are known to be trademarks or service marks have been appropriately capitalized. Artech House cannot attest to the accuracy of this information. Use of a term in this book should not be regarded as affecting the validity of any trademark or service mark.

10 9 8 7 6 5 4 3 2 1

FUNDAMENTAL PHYSICAL CONSTANTS

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.

10

Speed of light in a vacuum: c=3x10 cm/s Permittivity of a vacuum: ε0=8.89x10–14 F/cm Permeability of a vacuum: µ0=1260 nH/meter Planck’s constant: h=6.63x10–34 J-seconds Boltzmann’s constant: k=1.38x10–23 J/degrees Kelvin Charge of an electron: q=1.6x10–19 C Rest mass of an electron: me=9.11x10–31 Kg Thermal voltage: VT=kT/q=0.0259 volts at T=300 degrees Kelvin Bandgap energy of Silicon= 1.12 eV Bandgap energy of GaAs = 1.42 eV Dielectric constant of Silicon: 11.7 Dielectric constant of GaAs: 12.5

IMPORTANT UNIT CONVERSIONS

1. 2. 3. 4.

–8

Angstrom (Å): 1Å=1x10 cm Nanometer (nm): 1 nm =1x10–7 cm Micron (µm): 1 µm=1x10–4 cm Electron-Volt (eV): 1 eV=1.6x10–19 J

Contents Acknowledgments

ix

CHAPTER 1 Introduction

1

References CHAPTER 2 Applications 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.9 2.10

Cellular/PCS Handsets Cellular/PCS Infrastructure WLANs Bluetooth UWB WiMax Digital TV and Set-Top Boxes Cognitive Radio Spectrum Allocation in the United States (All Frequencies in Megahertz) Physical Layer Standards References

CHAPTER 3 RFIC Architectures 3.1 3.2 3.3 3.4 3.5

I/Q Receivers I/Q Modulators Nonzero IF Receivers Zero IF Receivers Differential versus Single-Ended Topologies References

11

13 13 15 16 17 18 19 20 20 21 22 24

25 25 30 32 37 41 41

CHAPTER 4 InGaP/GaAs HBT Fabrication Technology

43

4.1 Transistor Structures 4.2 Device Models 4.3 Passive Structures, Their Electrical Models, and Layout Design Rules 4.3.1 Microstrip Lines 4.3.2 TFR Resistors

43 45 48 53 55

vii

viii

Contents

4.3.3 M1-to-M2 Vias 4.3.4 MIM Capacitors 4.3.5 Substrate Vias 4.3.6 Bonding Pads 4.3.7 Crossover Capacitances 4.3.8 Spiral Inductors 4.3.9 Transistor Dummy Cells 4.3.10 Significant Layout Parasitic Elements 4.3.11 Simple Layout Example 4.4 Maximum Electrical Ratings 4.5 CAD Layout Tools References

57 57 58 60 61 62 64 65 65 67 70 70

CHAPTER 5 SiGe HBT Fabrication Technology

71

5.1 5.2 5.3 5.4 5.5

SiGe HBT Transistor Structures Transistor Device Models Passive Device Structures and Models Design Rules CAD Layout References

CHAPTER 6 Passive Circuit Design 6.1 6.2 6.3 6.4 6.5 6.6 6.7

Low-Pass Filters High-Pass Filters Band-Pass Filters Differential Filters Technology and Substrates Splitters/Dividers Phase Shifters and Baluns References

CHAPTER 7 Amplifier Design Basics 7.1 7.2 7.3 7.4 7.5 7.6 7.7

71 79 81 86 86 87

89 89 93 93 95 99 99 102 104

105

Matching Techniques Gain Compensation Fano’s Limit Stability Noise Match Differential Amplifiers Cascode Amplifiers References

105 106 106 107 109 109 111 113

CHAPTER 8 Low-Noise Amplifier Design

115

8.1 Noise Figure Concepts

115

Contents

8.2 8.3 8.4 8.5 8.6 8.7 8.7

ix

Noise Temperature Front-end Attenuation and LNAs Multistage Noise Figure Contributions Circuit Topologies for Low Noise Design Example 1: Single-Ended PCS LNA Design Example 2: Three-Transistor Hybrid Darlington Differential LNA Using SiGe Technology References

CHAPTER 9 Power Amplifier Design 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12

Loadline Concepts Maximum Power and Efficiency Class AB Power Amplifiers Definitions of Nonlinear Performance Metrics Adjacent Channel Power Ratio Error Vector Magnitude Circuit Topologies for PAs Matching Circuit Options Stability Bias Circuits Design Example 3: Wideband Gain Block Darlington Amplifier Design Example 4: Feedback Power Amplifier Design References

CHAPTER 10 Designing Multistage Amplifiers 10.1 10.2 10.3 10.4 10.5

Multistage LNAs Multistage Power Amplifiers Gain and Power Allocations Active Device Sizing Design Example 5: A Differential PCS PA References

CHAPTER 11 Mixer/Modulator Design 11.1 11.2 11.3 11.4 11.5 11.6 11.7

Mixer Basics Diode Mixers Single-Balanced Active Multiplying Mixers Fully Balanced Active Multiplying Mixers (Gilbert cell) I/Q Mixers I/Q Modulators Design Example 6: Cellular/PCS Downconverting Mixer RFIC References

CHAPTER 12 Frequency Multiplier Design

116 117 117 118 126 127 132

133 134 136 139 141 145 146 147 149 150 150 154 164 171

173 173 175 177 177 181 194

195 195 197 200 205 217 219 221 230

231

x

Contents

12.1 Frequency Doublers 12.2 Frequency Triplers 12.3 Frequency Translators References

231 233 235 239

CHAPTER 13 Voltage-Controlled Oscillator Design

241

13.1 13.2 13.3 13.4

Varactor Diode Basics Negative-Resistance Concepts Types of Resonators Feedback Circuit Topologies for Producing Negative Resistance 13.4.1 Negative-Resistance Oscillator Circuits 13.4.2 The Colpitts Oscillator Circuit 13.5 Frequency-Temperature Stability 13.6 Phase Noise 13.7 Quadrature Phase-Shifting Networks 13.8 Ring Oscillators 13.9 Design Example 7: 802.11a (Wi-Fi A) Differential VCO 13.10 Figure of Merit 13.11 Electronic Tuning and a Differential VCO Topology References

242 248 252 252 252 258 261 263 266 267 272 278 279 281

CHAPTER 14 Layout Design Strategies

283

14.1 14.2 14.3 14.4 14.5 14.6 14.7

283 283 284 285 286 287 289

Minimum Area “On-Chip” versus “Off-Chip” Component Decisions Minimizing Parasitics Testability Types of CAD Systems Foundry Comparison Reticle Assembly

CHAPTER 15 RFIC Economics

293

15.1 15.2 15.3 15.4 15.5 15.6 15.7

293 294 295 296 297 298 298

Levels of Integration Single-Ended versus Differential Topologies Process Technology Choices Area versus Performance Trade-offs Electrical Yield Prototype Costs Production Costs

Acronyms

301

About the Author

305

Index

307

Acknowledgments I wish to acknowledge all of my ELEN 351, ELEN 354, and ELEM359 graduate students at Santa Clara University. Your probing questions, your well-executed class projects, and your sense of excitement about the material has helped me greatly to clarify many of the design concepts that are discussed in this book. In this regard, my special thanks go to Amer Droubi and Calvin Chien for contributing excellent design material, based on their class projects, to this book. I wish all of you much success in your design careers. I would also like to thank my faithful teaching assistant Yiching Chen, who has added so much to these classes. I am deeply indebted to Professor Shoba Krishnan and Professor Samiha Mourad of the Electrical Engineering Department of Santa Clara University, for making possible the creation of a sequence of RFIC graduate design classes at Santa Clara University. It is out of these classes that this book has grown. To Barbara Lovenvirth of Artech House Publishing, goes my heart felt thanks for your constant encouragement and support (especially when I needed it the most) during the creation process of this book. My special thanks to Agilent Corporation for making their ADS simulation tool set available to the students and facility of Santa Clara University. I wish to give my special thanks to Ron Parrott and his staff at Vida Products Inc., for supplying design material for this book, and making time available for our many interesting discussion about the operation of Vida Product’s YIG tuned ring oscillators. Many thanks to Taka Shinomiya with whom I have enjoyed many lively discussions on power amplifer design. Finally, I want most especially to thank my wife Fran Sweet, whose patience and support during our many discussions about the book’s preparation; for her word processing talents and editing skills, and for her “advanced word smithing” magic acts. Everything that you have done on behalf of the book has helped in so many ways to bring us to this successful conclusion of our 18-month book-writing project. With all my love I thanks you Fran for being my faithful and constant partner and companion in this endeavor. Lastly, I wish to thank my father, Norman A Sweet, for giving me a crystal radio kit as a present on my 10th Christmas. It was this crystal radio that started me on a life long odyssey of discovery into the joys and wonder of radio electronics; which lives in this book and continues on.

xi

CHAPTER 1

Introduction Over the past three decades, radio frequency (RF) and microwave circuits have come through a period of rapid evolution and growth. Until the early 1960s, most RF and microwave circuits made use of vacuum tubes such as “lighthouse” tubes, klystrons, magnetrons, backward wave oscillators (BWOs), and traveling-wave tubes (TWTs) [1]. By the mid-1960s, all this was beginning to change as even more dramatic changes were rapidly approaching on the horizon in the form of new solid-state devices capable of working at RF and microwave frequency ranges. The first of these new technologies to present itself was the silicon (Si) bipolar transistor, which had been scaled to operate up to a frequency of about 1 GHz. And that was only the beginning of a wave of development during which time such unique solid-state devices as Gunn diodes, Impatt diodes, PIN diodes, and varactor diodes became available [2]. These two-terminal solid-state devices had the ability to push the upper frequency limit of solid-state electronics from under 1 GHz to well over 10 GHz. The rush was on. All eyes were watching to see whose efforts would deliver the next highest operating frequency, the highest power output, the lowest noise, and the best temperature stability. As the Vietnam War came to an end, this process accelerated even more because of the availability of federal research money. Because much of the basic RF and microwave research was funded by the federal government, a sharp focus was placed on military applications. RF and microwave technology had become a very important element in the cold war strategy of the time. Since then, the RF and microwave field has evolved over four distinct periods. Figure 1.1 provides a map of the way these developing technologies emerged over time. The first period, from the mid-1960s to the mid-1970s, is characterized by the use of diode-active devices and waveguide transmission lines and resonators. The great technology push during this period provided a replacement for vacuum tubes in both military and commercial communications systems. Reliability was a major motivating factor. Vacuum tube systems were famous for failing at the worst possible time, and it was widely felt in the 1960s that a switch to solid state, even with reduced performance, would significantly improve system reliability [3]. The question of the day became, what vacuum tubes can realistically be replaced by solid-state devices? Since solid-state devices could not generate the RF power of the magnitude that vacuum tubes were capable of, the first targets were applications not requiring high RF power levels. Examples of these include receiver local oscillators and low power transmitters. Most mixers in this period were already using solid-state designs employing point contact diodes, or Schottky diodes, as the active devices. It was therefore very natural to include a solid-state local oscillator as an

1

2

Introduction

Figure 1.1 A timeline showing how the RF and microwave electronics field has evolved through four distinct phases during the last forty years.

integral part of these mixers, forming a nearly complete solid-state receiver. This need was filled by replacing klystron vacuum tubes with Gunn diode oscillators. The exception to the trend toward solid state within receiver systems was the low-noise amplifier, which remained a TWT until gallium arsenide (GaAs) metal-semiconductor field-effect transistors (MESFETs) became more widely available. Low- and medium-power transmitters evolved into solid-state designs; Impatt diode oscillators were used as replacements for klystron, TWT, and magnetron vacuum tubes in these applications. Along with reliability, the new solid-state hardware offered the systems designer further advantages of lower power dissipation (no vacuum tube filaments needing heater power) and lower operating voltages, eliminating complex high-voltage power supplies. The RF/microwave industry very rapidly became sold on the virtues of solid-state hardware. We were ready for the next important period of development. The second major period is characterized by the availability of GaAs MESFET devices [4]. With the arrival of GaAs MESFET devices, three terminal devices were at long last available to the RF/microwave circuit designer. Microstrip transmission lines were introduced during this period [5]. Microstrip transmission lines are usually patterned on thin film ceramic substrates. Using photolithographic techniques [4], the circuit designer can fabricate an entire network of microstrip transmission lines on a single thin film ceramic substrate, and using so-called hybrid assembly techniques, circuits may be assembled by connecting active devices such as GaAs MESFETs and diodes to the patterned ceramic substrates using wire-bonding techniques. The field was revolutionized with the development of these RF/microwave thin film hybrid circuits. It was now possible to construct an entire subsystem within a single small mechanical housing. When compared to the old technologies using vacuum tube equipment or even the diode/waveguide solid-state equipment from the recent past, the savings in terms of size, weight, and power consumption were dramatic. During the cold war military buildup following the end of the Vietnam War, considerable research and development funding for this type of work became avail-

Introduction

3

able from the U.S. government. For this reason, many of the applications addressed by the emerging solid-state RF/microwave technology were military in nature. In fact, RF/microwave technology development coincided with a major cold war arms buildup in both the United States and the Soviet Union. The compact hardware, made possible by the use of ceramic microstrip circuits and GaAs transistors and diodes, found ready application in newly designed radar, electronic warfare, and missile systems. This period extended from the mid-1970s to the mid-1990s. It was a very intense and exciting two decades of design progress. The domain of solid-state circuits was growing by leaps and bounds. With the advent of GaAs MESFET devices, both low-noise and medium-power TWTs were at last replaced by solid-state transistor amplifiers [7]. These ceramic microstrip hybrid circuits were capable of extremely wide bandwidth operation. This was a great advance for electronic warfare systems, which depend on the ability to acquire random signals over a wide range of possible input frequencies. TWT amplifiers were no longer needed in such systems. The elimination of TWTs created an opportunity for tremendous savings in terms of cost, power, and weight in many airborne systems. All of these technological advances worked in combination with advances in other areas, such as engine design, new materials, and life support, to make possible the high-performance military aircraft that became available toward the end of the cold war period. The third significant period of RF/microwave technological development grew out of the desire to reduce the cost, size, and weight of RF/microwave solid-state circuits. The path to cost and size reduction followed the same route as that followed by both digital and low-frequency analog circuits: the implementation of integrated circuit (IC) techniques. Since GaAs MESFET devices had very quickly become the most important solid-state active device at these frequencies, an integrated circuit technology was needed that would build on GaAs MESFETs. Fabrication technology for GaAs integrated circuits became available in the mid-1980s [8]. At first, these so-called microwave monolithic integrated circuits (MMICs) were limited to perhaps two transistors and some matching elements, but over time MMICs grew to include enough components to make up entire amplifiers and even simple subsystems. MMICs made use of a particular property of undoped GaAs substrates: their high natural resistance. In fact, undoped GaAs, unlike undoped silicon, is an excellent insulator. This means that the undoped GaAs substrates used in MMIC circuits are excellent media for microstrip lines. Furthermore, since the dielectric constant of GaAs is 12.5, such transmission lines are physically short, reducing size, weight, and total cost. As cost depends heavily on total die area, this unique new MMIC technology held the promise of replacing much of the then existing ceramic microstrip hybrid hardware with low-cost, fully monolithic, MMIC-integrated circuits. This promise has been only partially fulfilled because of two factors: First, there is the issue of tuning (or tweaking). Hybrid ceramic circuits had always required a moderate amount of expensive hand alignment. This alignment, known in the industry as “tweaking,” accounted for much of the hardware’s cost. However, in the case of MMIC circuits, it was no longer possible to tweak the circuit because it is an integrated circuit and too small for any hands-on alignment (even if the insulating passivation layer were to be left off in processing) to be practical. This means

4

Introduction

that either MMICs work or they don’t. However, it’s not quite that simple. Variations in the fabrication process occur from wafer to wafer, which can significantly affect the performance of an MMIC circuit. Wafer-to-wafer variations reduce the overall yield of MMIC devices, and depending on the degree of difficulty of the electrical specifications, the yield may be quite low, which tends to cancel out the cost advantages of using an MMIC approach in the first place. Two possible solutions to these problems were attempted. The first was more exact modeling, and the second was improved process uniformity. The first solution made use of models that allowed the simulation of a wide range of electrical parameters, not just the small-signal S-parameters, which were customarily used in hybrid ceramic circuit simulations. The new models created for MMIC applications had to be able to function over a large range of signal levels, including dc behavior. These models, generically called large-signal models, were far more complex than the small-signal S-parameter models that preceded them. Considerable effort and expense went into the development of these large-signal models, with the hope that if the new MMIC circuits could be modeled accurately and completely, their yields would increase. The effort was only partially successful because of a second major issue: wafer-to-wafer variations during fabrication. All the modeling precision in the world won’t increase yield if the model parameters keep changing in unpredictable ways. To improve this situation, the foundries (fabrication facilities) attempted to use more repeatable processes. The most significant change was a switch from wet etch processing (involving placing the wafers into chemical baths) to a dry etch process (which makes use of a plasma that impinges very uniformly onto the wafer in a specially designed vacuum chamber). However, not all etching processes could be switched to dry etch. In particular, the gate recess etch step in fabricating the MESFET device’s gates could not be done by dry etch and had to remain a wet etch process step. A lot of device variation is experienced in this one step, and it is a challenge to model developers and circuit designers alike to deal with this variation. This situation has never been totally resolved. MESFET circuits today still experience significant process variations that affect yield, sometimes profoundly. By necessity, designers have developed ways of optimizing their circuits for process variations so that yield number can be increased. However, to date no universal solution to this problem has been identified. History intervened at this point to create a shift in emphasis and application. In 1991, the Soviet Union ceased to exist, and the cold war ended. As a result, the ongoing demand for improved military hardware came to an abrupt end, and government-sponsored research and development funding sharply declined. This global political change created temporary hard times for companies and individuals working in RF and microwaves throughout the 1990s. However, just as the RF/microwave electronics field descended into decline with the end of the cold war, the technology quickly came back to life with the arrival of the wireless revolution, which began gaining energy in the second part of the 1990s. The emergence of wireless technology signaled the beginning of a fourth period of technology development, and work in wireless research and development continues today. This period signaled the emergence of radio frequency integrated circuits (RFICs) as a major driver of progress in RF and microwaves. The timeline presented in Figure 1.2 focuses on the applications in each time period. Wireless applications

Introduction

5

Figure 1.2 A timeline showing the most important application associated with each phase in the development of the RF and microwave electronics field.

are the latest period. In many ways, wireless applications feel like “back to the future.” The focus is changing to narrowband applications at relatively low frequencies (1 to 4 GHz). This is a dramatic shift from ceramic/hybrid and MMIC technologies, where the focus was on very broadband applications at high frequencies (up to 25 GHz). However, the concept of RFIC was born out of the need to serve these applications. New high-frequency fabrication technologies began to appear. All during the purely microwave–millimeter-wave period (late 1960s to mid-1990s), the dominant high-frequency fabrication technology was GaAs MESFET. However, by the late 1990s, GaAs MESFET was joined by the GaAs heterojunction bipolar transistor (HBT) [9] whose advantages relative to GaAs MESFET are discussed throughout the present book. MMIC designers were quick to perceive the advantages of GaAs HBT, and many designers changed technologies, especially for cellular infrastructure applications. Within a short period, designers began designing PAs for mobile handsets using GaAs HBT. During this largely III–V compound semiconductor design period of the late 1980s, MMIC designers gave considerable attention to cellular applications. Due to the low-frequency (0.80 to 1.9 GHz) operations associated with cellular applications, these new integrated circuits came to be called RFICs, rather than MMICs. RFICs have operating frequencies more in keeping with traditional RF frequencies than with the higher microwave frequencies associated with MMICs. Then, the world changed again, in many ways, all at once. First, new silicon-based fabrication technologies [silicon germanium (SiGe), BiCMOS, and RFCMOS] became available [10]. Second, in order to reduce cost and size, there was a major push toward higher levels of integration. This trend toward high IC integration was the key ingredient responsible for morphing the “brick” cellular telephone of the 1990s into the palm-sized “clam shell” phone of today. Today, everyone, young children included, uses cell phones. This is true not only in the United States but worldwide. In terms of availability, cell phones are to this decade what personal computers were to the 1980s and 1990s. Mobile cellular phones have indeed changed the world, and these emerging IC technologies had a lot to do with

6

Introduction

it. These new product trends were driven by the availability of new and highly integrated RFICs. Transceiver designs moved away from realizations involving separate components attached to a common PCB, to one (or a few) RF chips based on one of the new silicon technologies. Currently, many low-frequency analog designers are entering the field in order to apply their craft of designing very large integrated circuits to the RF frequency range. Most of the GaAs technologies have been ignored by these analog designers (because of cost) when designing the new, highly integrated transceiver chips. There are two exceptions to this trend. The first is infrastructure amplifiers and mixers, which remain mostly in GaAs. The second exception includes handset PAs and T/R switches, which also remain in GaAs. The scope of this book is chiefly those designs made in support of cellular infrastructure and instrument applications. So, the question remains, are these cellular infrastructure (and instrument) amplifiers, mixers, voltage-controlled oscillators (VCOs), and switches, strictly speaking, RFICs or MMICs? Good question. It all depends on how one defines MMIC and RFIC technologies. In many ways, RFIC devices are replacements for discrete circuits. Their frequencies are low enough and their bandwidth is narrow enough that, in general, transmission line parasitic elements do not greatly affect performance. This is a big relief to the designer, who is not facing the difficult goals of wide-bandwidth, high-frequency operation where designs require modeling every transmission line like parasitic elements in order to succeed. RFICs have always relied on the same circuit elements used in MMICs use, such as spiral inductors and metal insulator metal (MIM) capacitors. These elements naturally have complicated models, each of which must be carefully analyzed in a top-notch simulator in order to predict performance accurately. Like the MMIC before it, the RFIC cannot be tuned, or “tweaked.” Once it is fabricated, “what you see is what you get.” To avoid a costly series of design “spins,” it is very important to model and simulate an RFIC accurately. However, these concerns can be mitigated to some degree by using feedback (both digital and analog) to control performance parameters. Some examples are variable bias circuits and automatic gain-control circuits. Concurrent with the wireless revolution of the late 1980s and early 1990s, a similar revolution was happening in device and fabrication technology. For many years, the only transistor technologies available to the RFIC/MMIC designer had been silicon bipolar or GaAs MESFET. That situation changed drastically during this period for two important reasons. The first was the exploration and exploitation of heterojunctions, and the second was the availability of CMOS devices operating at RF/microwave frequencies. Heterojunction devices were first proposed in the late 1950s by Herb Kromer, who ultimately won a Nobel Prize for this work [11]. Heterojunctions significantly increase the degrees of freedom available to the device designer. No longer are device parameters adjustable only with doping gradients; with heterojunctions, the dissimilar material’s energy band gap becomes a controlling aspect for determining performance The Ft performance of nonheterojunction transistors (i.e., homojunction transistors) is dependent on the ratio of the donor concentrated in the emitter to the acceptor concentration in the

Introduction

7

base. To increase Ft, the acceptor concentration must be kept low, raising the base resistance. This all changes in heterojunction transistors, where energy band gradients maintain high emitter injection efficiency, allowing the acceptor concentration to rise. With this newfound design freedom, device designers were able to make great improvements in the design of traditional devices and also to come up with some totally new device types. GaAs MESFETs were transformed into GaAs/AlGaAs PHEMTs. Silicon bipolar transistors became SiGe heterojunction transistors. For the first time, it became possible to make GaAs bipolar transistor in the form of InGaP/GaAs HBTs. Later on, indium phosphide (InP) HBTs became available. All of these devices offer significant performance improvements over their nonheterojunction cousins [12]. At the same time that these advances were being made with heterojunctions, the world of CMOS was moving up in frequency. By the late 1990s, CMOS performance had improved to the point that it also became a major player in RFIC fabrication technology. Instead of having only two transistor technologies available, RF/microwave circuit designers started exploring at least six options. The RFIC field had become a new world. This revolution was most profound in the area of bipolar technologies. It had long been known that bipolar devices held significant advantages for designing certain circuit types, such as low phase noise VCOs. Singular polarity bias is also a big plus with bipolar devices. Also, bipolar devices are often significantly more linear than their field-effect transistor (FET) cousins. Linearity is a key specification in many wireless components, like power amplifiers. The main problem had been what to do at high frequencies where silicon bipolar devices do not function well. Then, the InGaP/GaAs HBT transistor entered the scene, and the frequency barrier was knocked aside. Now, bipolar designs could be produced for any wireless frequency that was being addressed. However, performance was not the only advantage offered by the heterojunction bipolar devices. High fabrication yield was also a significant factor. The yield for this class of device was far superior to the yield experienced with field-effect transistors, such as GaAs MESFET. The vastly improved yield of InGaP/GaAs HBTs is simply related to their required metal line dimensions. GaAs MESFET and PHEMT devices require very narrow gates with lengths in the 0.15–0.30µm range. As discussed above, such narrow gates are very difficult to fabricate consistently at high yields, as a result of the wafer-to-wafer variation associated with the necessary wet processing steps. The situation changes radically with InGaP/GaAs HBTs, where the minimum required metal width is about 2µm, a relatively large dimension for an RF/microwave device. No longer does the metal patterning step control performance and yield, but the actual epitaxial deposition step is now responsible for determining both performance and yield. Epitaxial processes such as MBE and MOCVD are very well controlled and are uniform [13]. Therefore, InGaP/GaAs HBT devices enjoy a remarkably uniform fabrication, and electrical yields are usually in the high 90 percent range. In fact, yields are so high with these devices that designing for yield, as has been done for years by GaAs MESFET designers, is no longer required. HBT designers simply design to meet a specification and enjoy the advantage that if one circuit works to specification, all the rest will too.

8

Introduction

Another major advantage of bipolar devices is their significantly improved large-signal models relative to FET-type devices. Initially, all HBT devices were modeled using the same Gummel Poon model originally developed for modeling low-frequency silicon bipolar transistors. This model worked very well for InGaP/GaAs HBTs. In fact, Gummel Poon models produced simulations that were far more accurate than those previously performed using available GaAs MESFET device models, such as the Curtice model or the Statz model. For the first time in the experience of many RF/microwave designers, it became possible to simulate a component’s small-signal gain and match, dc parameters, power output, harmonics, and two-tone intermodulation performance, as well as to get results that closely agreed with measurements—consistently. Since from a designer’s point of view RFICs are a what-you-see-is-what-you-get experience, having a simulator model that really works is an enormous advantage. In spite of early successes, the Gummel Poon models had certain flaws when applied to GaAs devices. These deficiencies included the lack of a self-heating model (which is very significant in GaAs), the lack of Early voltage effect models, and the lack of avalanche multiplication modeling. These deficiencies were addressed in an improved model developed specifically for GaAs HBT devices: the Vertical Bipolar Industrial Committee (VBIC) model. Today, most HBT circuit designers use both VBIC and Gummel Poon models, enjoying accurate simulations with either model. In my experience, both models do an excellent job at low frequencies, but the VBIC model does seem to agree more closely with measurements at higher frequencies. In the end, the choice of model may depend on what models are available at the foundry with which you are working. Be sure to check with the foundry for verification of model accuracy. Since the introduction of InGaP/GaAs HBTs, two other very significant HBT technologies have been introduced. These are silicon germanium (SiGe) and indium phosphide (InP). SiGe HBT transistors use a SiGe base layer that bends the energy bands within the silicon. Local bending of the energy bands increases carrier mobility in this region of the transistor. The high carrier mobility within the narrow base region of the SiGe transistor offers profound performance advantages in terms of Ft and Fmax, relative to its all-silicon cousins. Today’s SiGe transistors offer an Ft of well over 200 GHz. However, they have inherently low breakdown voltages, and therefore the high Ft devices must be operated at low voltage. This is both good news and bad news, when compared to their higher-voltage InGaP/GaAs HBT brothers and sisters. The good news is that since SiGe devices operate naturally at lower bias voltages, they are naturals for a wide range of circuit designs intended for battery-operated mobile applications. The bad news is that their inherently low breakdown voltages may limit their usefulness as power amplifiers. Of course, breakdown voltage can be traded off with Ft as a part of the device design process. A third HBT technology looming on the horizon is InP HBT. This type of device combines high breakdown voltage with high Ft and Fmax. Currently, InP HBT is the most expensive of these three HBT technologies. However, if demand develops for the performance offered by InP HBT, surely its cost will go down. Figure 1.3 shows a comparison of the three HBT technologies. SiGe offers the lowest cost in production but is somewhat limited by its low breakdown voltage. InP HBT has the highest performance in terms of Fmax, Ft, and breakdown voltage. However, as mentioned

Introduction

9

Figure 1.3 A chart comparing the collector-to-emitter breakdown voltage and the frequency of unity current gain (Ft) for three heterojunction bipolar technologies.

above, right now InP HBT is very expensive. InGaP/GaAs is midway in terms of performance and cost and may be the ideal solution in many applications. However, InGaP/GaAs has a significant disadvantage for battery-powered wireless applications because its Vbe is relatively high (1.4V). There is almost a factor of two difference in Vbe between these two technologies, with SiGe having a Vbe = 0.70V. This is very significant in battery-powered applications where +3.0V is the maximum supply voltage available. In devices such as Gilbert cell mixers, where three devices are schematically “stacked” on top of each other, the device’s Vbe values will multiply by the number of stacked devices to determine a bias requirement, which must be less than the supply voltage. For InGaP/GaAs HBT, Vbe is 1.4V, which means for a mixer with three stacked devices, the supply voltage must be at least 3 × 1.4 = 4.2V, which will not work with many popular batteries. However, for SiGe, the value of Vbe is 0.70V, so the minimum supply voltage for a similar Gilbert cell mixer is 3 × 0.7 = 2.1V, which is completely compatible with a lithium ion battery operating at 3.3V. SiGe has the additional advantage of being available as a BiCMOS process at some additional cost. This means that in addition to the SiGe HBT bipolar devices, the designer has access to a full set of CMOS devices that are useful for designing digital control circuits and low-frequency analog circuits. This added flexibility offers a very significant advantage for SiGe technology because of the ability of the CMOS devices to serve as switches and digital control elements. Currently, the RFIC world seems to be heading in the direction of using RF CMOS designs, where the lowest possible production cost is the most important consideration. However, if performance (or time to market determined by reducing the number of design spins) is also a key consideration, then SiGe technology holds considerable advantages, especially in designs where low-phase-noise VCOs are of paramount importance. Since the 1/f noise corner frequency for SiGe is about 800 Hz, VCOs using SiGe offer the lowest possible phase noise and phase jitter for a given resonator Q. By comparison, the 1/f noise corner frequency for RF CMOS is

10

Introduction

between 1 and 10 MHz, which is an inherent disadvantage in extremely phase-sensitive applications, such as higher-order phase modulations like N–quadrature amplitude modulation (N-QAM), where a maximum number of bits per symbol is required to produce a high data rate. As the number of phase states, N, increases, the effects of phase noise become profound. For 16-QAM and above, LO phase noise can be a serious limiting factor relative to bit-error rate (BER) and, most importantly, on data rate. SiGe technology may well be the answer to these problems as wireless technology moves to higher and higher data rates. InGaP/GaAs HBT technology is the prime fabrication technology for gain block amplifiers and power amplifiers. This situation is not likely to change any time soon. InGaP/GaAs HBT has a rare combination of high linearity and the ability to produce high dc-to-RF conversion efficiency, making it ideal for the design of stand-alone RF/microwave amplifiers. Since it is very difficult to design efficient power amplifiers at low supply voltages, it is likely that power amplifiers, even in battery-operated equipment, will remain in InGaP/GaAs HBT technology for the foreseeable future. In spite of its high cost, InP HBT is a rapidly expanding technology for use at high frequencies, especially at millimeter-wavelengths (25 to 70 GHz). These devices bring the advantages of bipolar transistors to a region of the spectrum that has long been dominated by the field-effect PHEMT technology. With the combination of SiGe HBT, InGaP/GaAs HBT, and InP HBT, the wireless communications industry now has available the process technologies to bring the bipolar advantages to all parts of the radio spectrum. Since circuit topologies are common for a given device type, circuits developed for one of these technologies are easily transferable to another technology simply by making model changes in the simulator. Where the highest possible performance, and shortest time to market are required, these three bipolar technologies are poised to satisfy the needs of the RFIC industry both today and in the future. This book is dedicated to equipping the circuit designer with all the necessary tools to be successful at RF/microwave RFIC design using HBT bipolar devices. There are several good books available for designing RFICs with CMOS technology [14, 15]. A book is urgently needed to support the designer who is working with heterojunction bipolar RFIC technologies. This book is designed to fulfill a similar need for designers working with RFICs based on heterojunction bipolar transistors. Applications for RFICs, along with typical chip architectures for fulfilling the needs of these applications, are discussed within the book. Both InGaP/GaAs HBT and SiGe HBT process technologies are presented in order to provide the process knowledge the designer needs to achieve her or his goals. Several design techniques for passive circuits, including filters, couplers, splitters, and phase shifters, are presented. Amplifier design concepts are discussed, including specific approaches to the design of low-noise amplifiers (LNAs), PAs, and wideband gain blocks. Following the amplifier design material, there is a chapter on mixer design and a chapter on frequency multiplier design. The design of VCOs is covered in Chapter 13. Throughout Chapter 13, numerous VCO design examples are presented. Phase-noise concepts are discussed in detail, and examples of low-phase-noise VCO design are given. All designs are simulated using the Agilent Advanced Design System (ADS®) simulation tool set.

Introduction

11

The final two chapters disclose, in a general way, the considerations that the designer must keep in mind when approaching the circuit layout, as well as economic considerations and how they effect many design decisions.

References [1] Milnes, A., Semiconductor Devices and Integrated Electronics, New York: Van Nostrand Reinhold, 1980. [2] Gunn, J., “Microwave Oscillations of Current in III–V Semiconductors,” Solid State Communications, Vol. 1, September 1963, pp. 88–91. [3] Freeman, R., Telecommunication Transmission Handbook, New York: John Wiley and Sons, 1981. [4] Vendelin, G. V., Design of Amplifiers and Oscillators by the S-Parameter Method, New York: John Wiley and Sons, 1982. [5] Edwards, T., Foundations for Microstrip Circuit Design, New York: John Wiley and Sons, 1983. [6] Sweet, A., MIC and MMIC Amplifier and Oscillator Circuit Design, Norwood, MA: Artech House, 1990. [7] Johnson, E., “Physical Limitations on Frequency and Power Parameters of Transistors,” RCA Review, Vol. 26, June 1965. [8] Williams, R., Gallium Arsenide Processing Techniques, Boston: Artech House, 1984. [9] Liu, W., Handbook of III–V Heterojunction Bipolar Transistors,” New York: John Wiley and Sons, 1998. [10] Cressler, J. D., and Niu, G., Silicon-Germanium Heterojunction Bipolar Transistors, Norwood, MA: Artech House, 2003. [11] Kromer, H., “Theory of a Wide-Gap Emitter for Transistors,” Proc. IRE, Vol. 45, No. 11, November 1957, pp. 1535–1537. [12] Singh, R., Harame, D., and Oprysko, M., Silicon Germanium Technology, Modeling, and Design, New York: IEEE Press and Wiley Interscience, 2004. [13] Liu, W. Fundamentals of III–V Devices, HBTs, MESFETS, HFETS/HEMTs, New York: John Wiley and Sons, 1999. [14] Lee, Designing CMOS RF Integrated Circuits, Cambridge: Cambridge University Press, 1998. [15] Razavi, B., RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.

CHAPTER 2

Applications 2.1

Cellular/PCS Handsets Almost all applications for RFIC devices lie within the family of technologies that have come to be known as wireless communications. Although “wireless” is an old term that goes way back to the early days of the development of radio, it has in the last few years been rediscovered, dusted off, and applied to a menagerie of handheld, battery-operated, portable applications that use radio signals instead of wires to carry voice and digital information. But when you say the word “wireless” to laypeople today, their immediate reaction reveals that they are thinking about cell phones. For well over fifteen years, cellular telephones have become an increasingly important fixture in modern life. In the summer of 2005, my wife and I vacationed in Alaska. Our cruise ship’s first port of call in Alaska was Ketchikan. Eager to see everything, we walked around the downtown area near where the cruise ships dock. There were countless little shops, tearooms, and such, and we wanted to look in each one. One shop sold Russian handicrafts, icons, Babushka dolls, and the like. I asked the saleslady where she was from. She told me that everyone who worked in the shop was from Russia, and her home was in a region of central Russia just north of the Caspian Sea. She showed me her hometown on the map of Russia hanging behind the cash register. I remarked that living so far from home must be very lonely for her. She brightened up and said that although she missed her family very much, every afternoon at 5 p.m., she used her cell phone to speak with her mother in Russia. It made her happy to be able to stay in touch with her family while so far from home. At home in Russia, her mother also used a cell phone to communicate with her daughter. If ever I needed proof that cell phones (and all wireless technology) have truly changed the world, there it was. Cellular telephone technology has quickly moved from a novelty or luxury to an important accessory throughout the world. Cell phones have made it possible for families and friends to stay in touch regardless of the distance separating them. Wireless technology as applied to cellular telephones has produced a worldwide revolution in the lives of so many that its impact is comparable to the revolution caused by the printing press and later by personal computers. Oddly enough, although cellular telephone technology was originally developed in the United States in the 1960s, cellular telephone service was not considered commercially viable in the U.S. at the time, and was first put into commercial service in Finland and Sweden. Europe and, more recently, Asia have become leaders in cellular technology development. Much of the world looks to these geographic regions to buy both equipment and technology. Today, throughout the world are

13

14

Applications

communities are rushing to install cellular systems within their countries in order to have access to modern telecommunications with quality that compares favorably to that of the wire line phone services available in industrialized countries. The first cell phones were for use in the car only (known as car phones) and consisted of a transceiver box permanently mounted under the driver’s seat with a handset attached to the steering column. An outside antenna had to be mounted on the top of the car or on the rear trunk lid. Later, as development proceeded, a small transceiver and handset were placed in a carrying bag (about the size of a camera bag), along with an antenna mounted on suction cups and a rechargeable battery. The bag phone was a big step forward in terms of mobility, but it was still heavy and cumbersome. Next, on the scene was the handheld unit. Not much larger than a wired phone everyone was accustomed to, this diminutive phone included a builtin antenna and a self-contained, built-in battery pack, and it demonstrated a major step forward in the ongoing demand for smaller and smaller phones. Because of its weight, this new model quickly became known as “the brick.” Integrated RF circuits have played a major role in the ongoing miniaturization of cellular telephone equipment, enabling cell phones to shrink down to the size they are today. Future developments in RFIC technology will make it possible for a single cellular telephone to have the flexibility to operate at many different frequencies using many different transmission standards. Future cellular phones, using ultraflexible RFICs, will be capable of being instantly and automatically configured to adapt to different operating systems, using a concept called cognitive radio, which is discussed in more detail in Section 2.8 [1]. The first cell phone systems used analog frequency modulation (FM) and operated in the 800–900 MHz region of the radio spectrum. These systems worked quite well, especially considering just how new and revolutionary the technology was. But they had numerous problems with noise and interference as a result of the FM system’s analog nature. In the United States, a standard called the Advanced Mobile Phone Service (AMPS) [2] was developed to cover these first analog phone systems. Today, the AMPS system is regarded as the first-generation (1G) of cellular telephone technology. AMPS phones had problems with “handoffs” between cell sites and system capacity, which limited the spacing between cellular base stations and the maximum number of users who could be on the system at the same time. In order to resolve these problems, the cellular telephone industry next adopted digital technology with the introduction of what is now known as second-generation technology (2G). Digital cellular technology uses digital phase modulation [3] for improved signal-to-noise ratio (SNR) and improved interference rejection. Digital cellular technology also offers some form of “multiple access,” enabling higher system capacity than would have ever been achievable with the analog AMPS systems. These digital multiple-access techniques fall into two basic approaches: the first is time domain multiple access (TDMA), and the second is code domain multiple access (CDMA). With TDMA, the digitized voice signals are grouped into packets of bits transmitted by each mobile unit within a prearranged time slot. At the end of its assigned time slot, the mobile unit listens for a retuning packet from the cellular base station. All system users repeat this process within their own time slots, and at the end of the list of users, the process repeats. This process works in a way that is something like a

2.2 Cellular/PCS Infrastructure

15

group of people moving through a revolving door one person at a time (each person represents one digital information packet). Two examples of TDMA-based systems standards are the North American Digital Cellular (NADC) and the Global System for Mobile Communications (GSM) [4]. TDMA systems operate at frequencies of 800 MHz, 1,800 MHz, and 1,900 MHz. The second major multiple-access technique is CDMA. In CDMA systems, a prearranged code modulates the signal from the mobile unit so that it can be distinguished from the other mobile units (which are transmitting at the same frequency) when received by the base station. The code used to distinguish mobile units is called a spreading code because the code is applied to the signal as modulation, which “spreads” the signals in the frequency domain, creating what is called a spread-spectrum transmission. In a spread-spectrum signal, the transmitted power in a given narrowband frequency segment is very low, but when all of the transmitted power is integrated over frequency (at the base station’s receiver by using the identical spreading code), the total received power is quite high. The base station’s receiver will reject an interfering signal that does not have the right code modulation. The amount of interference rejection available in a CDMA system is called the system’s process gain. By taking advantage of process gain, the use of spreading codes in CDMA systems allows them to distinguish between mobile units and, at the same time, provide a high degree of interference rejection.

2.2

Cellular/PCS Infrastructure All cellular/PCS systems require that a base station be located in each of the system’s cells. The total of all base stations in a given system is called the system’s infrastructure. The infrastructure must contain a set of high-level, omnidirectional antennas, a high-power transmitter, a highly selective receiver, and a connection to the telephone system’s wire lines. Although size is not the critical factor in infrastructure applications that it is with mobile handsets, many, if not most, of the RF circuits in modern cellular infrastructures are now RFICs. The architecture of the base station’s receiver and transmitter is very similar to the architecture used in handsets; the primary difference is found in the higher power of the transmitter and in the higher selectivity of the receiver. In both the receiver and the transmitter, it is absolutely essential that all components have the best possible linearity in order to keep distortions in the presence of multiple signals at a minimum. Relative to the RFICs used in these applications, the linearity requirements usually translate into an intermodulation intercept point specification, or an adjacent channel power ratio (ACPR) specification. In particular, infrastructure transmitters often have long, cascaded chains of gain block amplifiers with excellent linearity, as indicated by their high intermodulation intercept point performance. Cellular base station transmit powers often exceed 50W, making it necessary to use LDMOS devices in the last stage or two to achieve the final transmit power. Base station mixers must also be capable of linearity performance similar to that required of the base station amplifiers. Many signals simultaneously arrive at the mixer, which is located within the receiver’s front end. In order for the system to remain highly selective under these conditions, it is necessary for the receiver mixer

16

Applications

to have excellent linearity, as indicated by its intermodulation intercept point. Likewise, the receiver’s LNA and its accompanying intermediate-frequency (IF) amplifiers also must have a high degree of linearity in order for the receiver to remain selective in the face of so many input signals. In Europe and Asia, there is growing demand for a class of systems called cellular repeaters. Cellular repeaters are located in areas where cellular reception is poor because of shading, multipath cancellation, or poor signal penetration. These repeaters can bring high-quality cellular service into areas previously considered to be in the “fringe area” of service. Cellular repeaters are often located in office buildings, high-rise apartment buildings, and subways. Cellular repeaters are particularly popular in those parts of Asia where population densities are very high and cellular phone usage is much higher than wire line service. Cellular repeaters are of less importance in North America, where population densities are much lower than in Asia. Cellular repeaters come in one of two types: straight amplifier chains and downconverting/upconverting chains. Straight amplifier chains have the advantage of simplicity but are subject to instability under certain conditions (i.e., “leakage” from the transmitting antenna to the receiving antenna). Downconverting/ upconverting chains are less susceptible to instability but are more complex and more expensive. The trend in repeaters is toward smaller and smaller units that can be mounted almost anywhere (such as an office window). For this reason, repeaters are experiencing some of the same miniaturizing demands that affect the RFICs for mobile handsets. Recent advances in third-generation (3G) cellular technology offer higher data rates and the associated auxiliary services using higher data rates, such as text messaging and multimedia. At present, there are many kinds of 3G systems under development, and it is likely that many different standards will be rolled out worldwide in the next few years. The first such systems are now available in Asia, but it may take some time before similar service becomes available in North America. 3G systems require even higher degrees of component linearity than the equivalent 2G systems. Also, the 3G frequencies will be higher, and the bandwidth requirements will be wider. This means that RFIC designs for 3G systems will be even more challenging that those already developed for present 2G cellular systems.

2.3

WLANs Wireless local-area networks (WLANs) provide computer users with high-speed wireless networks that operate very similarly to wired Ethernet. WiFi (802.11a/b/g) [5] operates in the unlicensed (ISM) bands at 2.4 GHz and 5.1–5.8 GHz. The Institute of Electrical and Electronics Engineers (IEEE) standard for WLANs is 802.11, whose three versions are called “a,” “b,” and “g.” Version a operates at frequencies in the range of 5.1 to 5.8 GHz with a data rate of 50 Mbps. Version “b” operates at a frequency of 2.4 GHz with a data rate of 11 Mbps. Version “g” operates at a frequency of 2.4 GHz with a data rate of 50 Mbps. The 802.11 standards of operation are often collectively called WiFi (i.e., wireless fidelity).

2.4 Bluetooth

17

Most WiFi equipment takes the form of a PCMCIA card inserted into a laptop personal computer. WiFi operation may involve connecting through an “access point,” making a computer part of a wireless network, or a WiFi operation may link only two computers, which is called “peer to peer.” WiFi equipment is capable of connecting a computer to an access point (or a computer to another computer) over a range of 100m indoors, or up to a quarter-mile line of site. There are fourteen WiFi channels, and most installations automatically search for the channel with the minimum amount of interference at any given time. WiFi transmit power is typically 10 to 100 mW. The signal bandwidth is approximately 20 MHz wide as a direct result of the broadband nature of the information being transmitted. WiFi systems generate and transmit “packets” of data. After the data packet is transmitted, the transceiver system will automatically be switched to receiver mode for reception of a data packet from the other computer or from an access point. In its low-speed modes, WiFi makes use of quadrature phase-shift keying (QPSK) modulation, operating in a direct-sequence, spread-spectrum mode using a Baker spreading code. For high data rates (up to 50 Mbps), WiFi uses orthogonal frequency division multiplexing (OFDM) modulation. OFDM modulation makes use of a number of subcarrier frequencies, each carrying information that is multiplexed onto this array of carrier frequencies. It is the multiplexed combination of these OFDM subcarrier channels that makes the high data rates possible. WiFi uses relatively high transmit power (up to 100 mW), and as a result, most WiFi devices consume a relatively large amount of dc power. Although this factor does not preclude the use of WiFi in small battery-operated, handheld equipment, most WiFi devices are powered from the larger power sources found in personal computers. These devices are commercially available in the form of PCMCIA cards for personal computers (both desktop and laptop). These devices are also available in USB interface form for the same purposes. The use of external antennas can extend the range of WiFi equipment; however, most installations simply use the miniature antennas that are directly attached to the WiFi device’s PCB. In most cases, users rely on working through access points available at “hot spots” located at coffee shops, hotels, airports, and so forth. In some cases, communities are installing hot spots in many locations in order to provide the residences with WiFi services throughout the community. WiFi is increasingly offering the mobile PC user a true high-speed wireless network connection where ever he or she may go. While WiFi equipment is available in both the 2.4 GHz band and the 5.1–5.8 GHz band, the radio hardware in the higher band (802.11a) does not offer a significant data-rate advantage over what is already available on the lower band (i.e., 802.11g). Since the higher-frequency equipment is more expensive and has less range, it is not finding the same level of market acceptance as are the two 2.4 GHz standards (802.11b and 802.11g).

2.4

Bluetooth Bluetooth is named for the Danish king Harald I Bluetooth, who lived from ad 940 to 986. The reason for selecting King Bluetooth’s name for a wireless service derives from his successful uniting of the kingdoms of Denmark and Norway. This accom-

18

Applications

plishment reminds developers of their goal of providing a wireless network capable of uniting computers with their peripheral devices. The name Bluetooth also is a reminder of the importance of wireless development’s originating in Scandinavian countries. In many ways, the Bluetooth wireless standard [6] is the mirror image of the WiFi wireless standards. WiFi offers extremely high data rates, while Bluetooth offers relatively low data rates. WiFi offers relatively long range (up to 100m inside a building), but Bluetooth offers very short range (3 to 10 ft.). WiFi consumes a relatively large amount of dc power, while Bluetooth consumes a relatively small amount of dc power. While WiFi is primarily applied to the networking of personal computers over relative long distances, Bluetooth is most often used to link devices that are close together, requiring relatively low data rates. Also, Bluetooth is a natural for low-battery-powered, handheld mobile devices. Some examples of Bluetooth applications are cordless earpieces for cellular phones, wireless keyboards, wireless mice, linking wireless PDAs to computers, and computer-to-printer wireless connections. Bluetooth operates in the same unlicensed (ISM) 2.4 GHz band as WiFi. The type of modulation used in Bluetooth is called Gaussian frequency-shift keying (GFSK), and Bluetooth makes use of time division duplexing of its data stream. Although relatively high-power versions of Bluetooth are allowed within the standard, the most common applications are for very short ranges, where battery life (i.e., low dc power consumption) is of primary importance.

2.5

UWB The ultrawideband (UWB) transmission draft standard [7] is designed to provide short-range wireless communications with extremely high data rates (100 to 500 Mbps). These high data rates in effect make UWB a wireless USB (WUSB) standard. The primary application of UWB is the wireless transmission of video programming. For instance, UWB can be used for the wireless transmission of movies between the hard drives of two computers over a reasonable time. UWB can also be used to transmit video in real time from a digital camcorder to a personal computer for storage. In effect, UWB has the potential to replace the highest-speed Ethernet cables. UWB fills the need for higher-data-rate wireless transmission than can be provided by WiFi g (above 50 Mbps). As originally conceived, UWB technology would make use of extremely short-duration impulses of RF energy. In the frequency domain, these pulses would have energy spread over a very wide bandwidth (thus, the name ultrawide bandwidth). The energy at any one frequency would be very small, so UWB would not interfere with narrowband services operating within the same band. Integration over a wide range of frequencies is required to produce sufficient signal energy to provide a useful signal-to-noise ratio. However, the hardware needed to create and receive impulse UWB signals is quite challenging to design. The original concept of UWB is still in use; however, a second approach to UWB has gained considerable acceptance over the last few years. In this alternate approach, a series of OFDM subchannels in the frequency domain are tied together and multiplexed in such a way that the total data rate of using all RF channels work-

2.6 WiMax

19

ing together is extremely high. A UWB standard has evolved along both this new frequency-multiplexed concept, as has a separate standard covering the original short-impulse concept. Both UWB standards operate in the 3–10 GHz frequency range. Out of concern for the possibility of interference to Global Positioning Services (GPS) signals at 1.5 GHz, the Federal Communications Commission (FCC) in the United States has set a lower frequency limit on UWB transmissions of 3.1 GHz. The FCC has also set the high-frequency limit for UWB transmission at 10.6 GHz. The FCC’s frequency limits are relatively easy to observe in the multichannel approach to UWB, but they require considerable filtering in the impulse approach. For this reason, today more attention is being paid to the multichannel approach to UWB. Two new standards are under development for this multichannel approach to UWB (two versions of 802.15.3a). One version uses a high-speed pulse-modulation approach to generating UWB signals; the second uses a multiband OFDM approach. Of the two, the multiband OFDM approach seems to be gaining wider acceptance. With this standard, there is a series of fifteen simultaneously operating, 500 MHz–wide RF bands available, covering the 3.1–10.6 GHz range. The equipment designer is free to use any number of these bands (up to the full fifteen). The highest data rates are achieved by using the maximum number of RF bands. Each RF band itself is divided into a series of QPSK modulated subcarriers multiplexed together according to OFDM techniques. Therefore, there are two types of multiplexing going on simultaneously: multiplexing of the subcarriers within each RF band and multiplexing of the RF bands. If all RF bands are used, the potential data rate could be as high as 500 Mbps. In order to prevent interference with narrowband service operation in the 3.1–10.6 GHz portion of the spectrum, the FCC requires that UWB transmission have a total integrated power of less than 90 mW and a power density in any 1 MHz bandwidth of less than –40 dBm. If the entire transmitted spectrum is evenly spread over frequency, this is not a difficult standard to meet. However, if any narrowband signal, such as the LO carrier frequency (i.e., mixer LO leakage), is transmitted due to imperfect mixer isolations, the –40 dBm per MHz bandwidth becomes a challenging specification. With its ability to transmit video over reasonable time periods, UWB has high potential for the future and ultimately may replace WiFi in many high-speed applications. For instance, UWB holds the promise of a WUSB connection between computers, with the simplicity of no wires and the high data rate associated with USB.

2.6

WiMax WiMax is the name of a family of transmission standards that covers a wide range of possible frequencies, modulations, and duplex types [8, 9]. These standards are presently lumped under the heading of 802.16a, called broadband wireless access for worldwide interoperability. The basic idea of WiMax is to provide broadband wireless connection for both fixed and mobile users that will link to the Internet through base stations in a similar way as cellular base stations. The maximum range between the user and the base station will be as great as 30 mi. This kind of service

20

Applications

will let users access true high-speed Internet that could be available to them anywhere within a very wide-ranging geographical area (i.e., 10–30 mi. radius). Frequencies between 2 and 66 GHz are possible locations for WiMax transmission. The maximum anticipated data rate is 70 Mbps. It is possible that users who are not located in “line of sight” from a base station antenna tower may have to accept lower data rate as a necessary trade-off for achieving a usable signal-to-noise ratio to produce an acceptable bit-error rate. WiMax is still in its infancy as far as hardware development is concerned. There is great potential for RFIC development in support of WiMax. In fact, WiMax may become the number one driver of RFIC development at frequencies above 10 GHz.

2.7

Digital TV and Set-Top Boxes At this writing, the TV industry is approximately sixty years old and is embarking on its first major technical revolution. Digital TV is beginning to emerge, and an eager general public is ready and waiting. If events proceed according to plan, most of the U.S. television-watching population will convert to receiving digital TV transmission sometime over the next five years. Digital conversion will require the purchase of a new (and, at first, very expensive) digital TV receiver or, alternatively, living with the existing analog TV receiver supplemented by an additional “set-top box.” A set-top box contains digital tuners and all the necessary electronics for converting digital video and audio signals into a format that can be processed and displayed by an existing analog television receiver. It is expected that there will be a mass market for set-top boxes as more and better digital programming becomes widely available to the consumer. Set-top boxes will include a number of RFIC devices, such as digital tuners, amplifiers, and switches. With the expected future popularity of set-top boxes as digital TV takes off, a significant RFIC development in support of digital TV is anticipated to take place over the next several years.

2.8

Cognitive Radio In recent years, the pace of rolling out new wireless services has become breathtaking. Today, the worldwide number of wireless standards and services is truly amazing, and for most of us, it has become difficult to keep up with all of the changes. This situation is particularly hard on equipment manufacturers, who must at regular intervals redesign their equipment to accommodate this flood of emerging standards. In order to prevent these redesigns from placing impossible-to-fulfill demands on designers and manufacturers alike, a desire has recently arisen on the part of many in the wireless industry to design equipment hardware that is sufficiently flexible to be reprogrammed to instantly accommodate new standards operating in new frequency allocations. An additional advantage of these cognitive (or software-defined) radios [10, 11] would be their ability to quickly assume a new standard identity, making use of free spectrum on the fly, in order to best serve the real-time needs of users. In fact, it is conceivable that such a cognitive radio system

2.9 Spectrum Allocation in the United States (All Frequencies in Megahertz)

21

might switch from one standard to another in short order, changing frequency with each standard’s change, in response to free-spectrum opportunities. But what kind of hardware might be required to implement these cognitive radios? Because of their inherent frequency agility, cognitive radios’ RF circuits must respond over a wide variety of frequencies. Such frequency agility will require RF circuits with broadband designs. In spite of this broad-banding requirement, cognitive radio components will be required to operate at the same level of performance as their narrowband cousins. This is because each standard by itself is demanding in terms of performance and cannot be compromised. Therefore, performance factors such as power output, noise figure (NF), linearity, and phase noise must be of the same level of quality as is experienced with narrowband equipment, operating to a given standard. In particular, frequency-generating equipment, such as VCOs, will be required to cover a wide range of frequencies (perhaps an octave or more), while maintaining extremely low phase noise. This is a very tall order for varactor-tuned VCOs. However, magnetically tuned yittrium iron garnet (YIG)–tuned oscillators (YTOs) are capable of simultaneously tuning over a wide frequency range (more than an octave), while maintaining extremely low phase noise. A YTO design example is discussed in Chapter 13. This YTO is capable of octave band tuning with phase noise typically 40 dB lower than is achievable with the best varactor-tuned VCO. Cognitive radio development will require similar creative approaches to all of its component designs. A possible alternative approach to a cognitive radio receiver is to use an all-digital architecture connecting the antenna directly to an extremely broadband analog digital converter (ADC). For example, in order to achieve eleven bits of precision, a 6 GHz ADC would have to be clocked at 12 GHz and, most importantly, from a clock oscillator with RMS jitter on the order of 10 to 100 fs. Recent research findings suggest that this jitter requirement could be relaxed to 1.0 ps [12]. At present, the 10 fs requirement cannot be achieved with existing VCOs. However, the miniature YTO design discussed in Chapter 13 is capable of about 100 fs of jitter at 12 GHz. Perhaps with device improvements and/or increased YIG resonator Qs, this class of oscillators could approach 10 fs performance. Using such techniques, it is conceivable that a cognitive radio could be designed whose only analog content would consist of an LNA and a PA. Such an all-digital radio would be truly software defined in every sense of the word. Sections 2.9 and 2.10 list frequency allocations and physical layer standards for a number of popular wireless standards for which RFICs represent an essential enabling technology.

2.9 Spectrum Allocation in the United States (All Frequencies in Megahertz) • • • • •

Land mobile radio (LMR): 150, 450, 850 PCS: 1,850–1,990 Paging: 901–1,990 ISM (unlicensed): 800, 2,400, 5,700 (Part 15) Multipoint Microwave Distribution System (MMDS): ~5,000

22

Applications

• • •

2.10

LMDS: 16,000–30,000 3G mobile transmit: 1,710–1,755 3G base transmit: 2,110–2,155

Physical Layer Standards •

•

•

•

GSM (Global System Mobile, digital cellular) • Transmission time: 260 Kbps • TDMA structure: eight time slots per radio carrier • Time slot: 0.577 ms • Bits/time slot: 156 • Frame interval: eight time slots = 4.615 ms • Number of radio carriers: 124 • (935–960 MHz down link, 890–915 MHz up link) • Modulation: GMSK with BT = 0.3 • Frequency hopping: slow hopping (217 hops/s) • Equalizer: equalization up to 16 µs time dispersion NA-TDMA (IS-136 digital cellular) • 800/1,900 MHz band • Channel bandwidth: 30 KHz • TDMA frame structure: 40 ms frame in six time slots • Channel data rates: first slot, half data rate; second, third, fifth, and sixth slots, double data rate CDMA (IS-95 digital cellular) • Data rate: 9,600 bps • PN chip rate: 1.2288 Mcps • Code rate: one-third bits/code symbol • Code symbol repetition: two symbols/code symbol • Transmit duty cycle: 100 percent • Code symbol rate: 28,800 sps • Modulation: six code symbols/modulation symbols • Modulation symbol rate: 4,800 sps • Walsh chip rate: 307.20 kcps • Modulation symbol duration: 208.33 µs • PN chips/code symbol: 42.67 PN chip/code symbol • PN chips/modulation symbol: 256 PN chip/modulation symbol • PN chip/Walsh chip: 4 PN chip/Walsh chip MMDS • 2,500–2,700 MHz • 6 MHz channel bandwidth • Thirty-three channels • Range: 35 mi. • Tx power: 1–100W

2.10 Physical Layer Standards

•

•

•

•

23

Bluetooth: • System type: frequency-hopping spread spectrum • Frequency: 2,402–2,480 MHz (ISM unlicensed band) • Modulation: GFSK, +/– 160 KHz frequency shift • Channels: 79 • Frequency hopping: 1,600 hops/s • Power: Class 1: +20 dBm Class 2: +4 dBm Class 3: 0 dBm • Duplexing: TDD • Range: 10m • Voice: up to three synchronous voice channels of 64 Kbps ZigBee (IEEE 802.15.4) [13] • System type: DSSS (Direct sequence spread spectrum) • Data rate: 20–250 Kbps • 2,400 MHz, 868 MHz, 915 MHz • Range: 30m • Channels: 16 • Power: 0 dBm • Nodes: 64,000 on one network • Sleep mode: 15 ms transition time • Beacon mode: periodic “wake up” to receive beacon from network control mode UWB (IEEE 802.15.3a) • Subbands: 3,168–3,613 MHz; 3,616–4,224 MHz; 4,224–4,752 MHz • Transmission: OFDM • Modulation: QPSK • Data rate: 100–200 Mbps • Tx power: 93 mW • Rx power: 155 µW (at 110 Mbps) • Rx power: 169 µW (200 Mbps) • Range: 20m • Power density: less than –40 dBm in any 1 MHz band-pass window WiFi (IEEE 802.11a/b/g/n) • 802.11a: 5.15–5.35/5.47–5.725/5.725–5.875 GHz • 802.11b: 2.400–2.500 GHz • 802.11g: 2.400–2.500 GHz • 802.11n: 2.4 and 5 GHz bands • Maximum data rate, 802.11a: 54 Mbps • Maximum data rate, 802.11b: 11 Mbps • Maximum data rate, 802.11g: 54 Mbps • Maximum data rate, 802.11n: 540 Mbps • Range: 25–50m indoors, depending on version

24

Applications

•

•

Modulation type: binary phase-shift keying (BPSK)/QPSK/OFDM, depending on data rate Tx power: +15 dBm to +30 dBm, depending on version

References [1] Bagheri, R., et al., “Software-Defined Radio Receiver: Dream to Reality,” IEEE Communications Magazine, Vol. 44, 2006, pp. 111–118. [2] Dixon, R., Spread Spectrum Systems with Commercial Application, New York: John Wiley and Sons, 1994. [3] Lee, W., Wireless and Cellular Telecommunication, New York: McGraw-Hill, 2006. [4] DeRose, J., The Wireless Data Handbook, New York: John Wiley and Sons, 1999. [5] IEEE Standards Working Group Committee 802.11 (WiFi). [6] IEEE Standards Working Group Committee 802.15.1 (Bluetooth). [7] IEEE Standards Working Group Committee 802.15.3a (UWB). [8] IEEE Standards Working Group Committee 802.16 (WiMAX). [9] Vaughan-Nichols, S., “Achieving Wireless Broadband with WiMAX,” IEEE Comp., Vol. 37, No. 6, June 2004, pp. 10–13. [10] Klumperink, E., et al., “Polyphase Multipath Radio Circuits for Dynamic Spectrum Access,” IEEE Communications Magazine, Vol. 45, No. 5, May 2007, pp. 104–111. [11] IEEE Standards Working Group Committee 802.22 (Cognitive Radio). [12] Hu, W., et al., “Dynamic Frequency Hopping Communities for Efficient IEEE 802.22 Operation,” IEEE Communications Magazine, Vol. 45, No. 5, May 2007, pp. 80–87. [13] IEEE Standards Working Group Committee 802.15.4 (ZigBee).

CHAPTER 3

RFIC Architectures 3.1

I/Q Receivers In today’s wireless communications industry, most systems make use of some form of phase modulation. Phase modulation has been found to be superior to other forms of modulation in terms of supporting high data rates with superior signal-to-noise ratios at high data rates. Given the paramount importance of phase modulation, the RFIC field has had to find circuit techniques to receive and transmit various types of phase modulations. These types of modulations can be compared and contrasted by considering their performance relative to three important criteria: 1. Bit-error rate (BER) = error bits/total bits per unit time 2. Spectral efficiency (compared to Shannon’s information capacity of a noisy channel) [1] 3. dc power efficiency (related to battery life) Criterion 2 relates to perhaps the most important relationship in the mathematical theory of information, developed by Claude Shannon [2]. Shannon’s equation for the information capacity (maximum data rate) of any noisy channel is given by C (bits per second) = BW log2(1 + S/N)

(3.1)

where BW is the channel’s bandwidth in hertz. S/N is the channel’s signal-to-noise ratio expressed as a number. All real communications channels observe (3.1) as an upper bound on their performance. When dealing with phase modulations of various kinds, it is very convenient to consider the signal divided into two components, called the I (for in-phase) component and the Q (for quadrature-phase) component. The I component can be thought of as a cosine-like signal, and the Q component can be thought of as a sine-like signal. A plot of various modulation phase states on a two-dimensional graph (with the I component playing the role of the x axis and the Q component playing the role of the y axis) is called a signal constellation diagram. Signal constellations are very important tools for understanding phase-modulated digital signals because each of the phase states on the constellation diagram corresponds to a digital signal level. If there are N phase states in a given modulation’s constellation, the amount of information carried by each clock cycle (i.e., each symbol) will be Information per symbol = log2(N)

(3.2)

25

26

RFIC Architectures

The information rate associated with this form of modulation is R (bits per second) = (1/ ) log2(N)

(3.3)

where is one clock period. A simple example of phase modulation is binary phase-shift keying (BPSK). A simple circuit for generating BPSK is shown in Figure 3.1. There are two generators in Figure 3.1: the first is Acos( 1t), and the second is –Acos( 1t). An SP2T switch, which is activated by the data stream, switches back and forth between the two generators. We will associate a digital 1 with Acos( 1t) and a digital 0 with –Acos( 1t). The only difference between a digital 1 and a digital 0 is a 180° phase shift of the signal. Figure 3.2 shows the constellation diagram for a BPSK signal. Both signal states lie along the I axis. With this type of modulation, there are no phase states lying along the Q axis. The signal is simply shifted back and forth between the Acos( 1t) state and the –Acos( 1t), creating a digital 1 or a digital 0 within each clock period. Since there are two digital choices (N = 2) with BPSK modulation, the data per symbol (one clock period) is equal to log2(2) = 1 bit.

Figure 3.1

An idealized generator of BPSK phase modulation.

Figure 3.2

A constellation diagram of BPSK modulation.

3.1 I/Q Receivers

27

If significant phase noise exists in a system using BPSK modulation, the two phase states change from points at A and –A to noise balls centered around the points A and –A. If these noise balls become large enough to reach all the way to the Q axis, an ambiguity develops between what is a digital 1 and what is a digital 0. When this situation develops, significant bit errors may occur. Therefore, in this case the Q axis becomes what is called a decision boundary. Once the phase-noise balls associated with each of the phase states reaches the decision boundary, the BER increases significantly. This situation must be avoided by maintaining a high signal-to-noise ratio within the radio system and maintaining low phase noise in all signal sources. BPSK signals can also be generated by using the circuit shown in Figure 3.3. In the case of this circuit, a mixer is used to enable the data input to modulate a local oscillator signal. The data is cast into bipolar form so that a digital 1 becomes 1V and a digital 0 becomes –1V. Since the mixer acts as a mathematical multiplier, the 1V data levels produce an output signal of A, and the –1V data levels produce an output signal of –A. This process is an exact duplication of how BPSK modulation was produced by the circuit shown in Figure 3.1. Mixers are often used as both modulators and receiving downconverters in phase-modulated systems. In Figure 3.4, we see how two mixers can be combined with a serial-to-parallel data converter to generate another type of phase modulation called quadrature phase-shift keying (QPSK). The data stream is broken up into two parallel components, which are used to drive separate mixers. The first mixer is driven by an LO signal, which is cosinelike in terms of its phase. The second mixer is driven by an LO signal, which is sinelike in terms of its phase relationship to the first LO signal. As before, the cosinelike LO signal produces an output from the first mixer, which has two phase states, A and –A. The second sinelike LO signal produces an output from the second mixer, which has two phase states, +jA and –jA. By combining these four possibilities, the final four QPSK phase states, A+jA, –A+jA, –A–jA, and A–jA, are arrived at, as shown in the constellation diagram in Figure 3.5. Since the number of phase states is now four instead of two, as in the case of BPSK, the bits per clock period associated with QPSK is log2(4) = 2 bits. This means that for the same clock period, the information rate has doubled. Another way to run QPSK is to divide the clock rate by two, which improves spectral efficiency by reducing the spectra’s width by a factor of two while preserving the same data rate associated with BPSK modulation. Either way you look at it, QPSK is a 2:1 improvement relative to BPSK.

Figure 3.3

An analog multiplying mixer may act as a BPSK modulator.

28

RFIC Architectures

Figure 3.4

A block diagram of a QPSK modulator.

Figure 3.5

A constellation diagram of QPSK modulation.

Next, we turn our attention to the reception and detection of phase-modulated signals. A very natural way to accomplish this task is to design a receiver that has a natural ability to receive the in-phase (I) component of the received signal separately from the quadrature-phase (Q) component of the signal. This task is accomplished in the following way: a mixer is used as a downconverter and takes the signal at RF frequencies, mixing it with an LO signal to produce an IF frequency signal sufficiently low in frequency that it can be converted into digital form by an ADC data converter. The phase of the LO signal holds the key to whether this device will downconvert the I component of the incoming signal or the Q component of the incoming signal. If the LO signal is cosinelike, the I component will be downconverted. However, if the LO signal is sinelike (i.e., a cosinelike signal that has been advanced by 90º in phase), the Q component of the signal will be downconverted. A block diagram of this I/Q downconverter is shown in Figure 3.6. The mixers are often of the Gilbert cell type (see Chapter 11). Both the I and Q out-

3.1 I/Q Receivers

Figure 3.6

29

A block diagram of an I/Q demodulator.

puts will be filtered before further amplification. In high-IF-frequency systems, this filter will most likely be an off-chip band-pass filter. In low- (or zero) IF-frequency systems, this filter will most likely be an on-chip low-pass filter. A key element in making an I/Q mixer work properly is generating the 90º phase shift between the two LO signals. There are several ways to achieve this goal (see Chapter 6). The most straightforward way to accomplish this is to use a circuit called a polyphase network. This network has a single input but two outputs, one of which is phase-shifted relative to the other input by exactly 90º. A circuit schematic diagram for a polyphase network is shown in Figure 3.7. A simple single-section, low- or high-pass filter of the type discussed in Chapter 6 may also be used to generate a 90º phase shift between two LO signals in an I/Q downconverting mixer. Other possibilities include the use of a quadrature VCO (see Chapter 13), whose architecture is shown in Figure 3.8, and the use of a digital frequency divider circuit, which naturally can produce several outputs in various phase configurations by using digital techniques. Whatever technique is employed, creating a 90º phase shift

Figure 3.7 A schematic diagram of a polyphase circuit useful for shifting the LO signal by 90º in I/Q modulator and demodulator applications.

30

RFIC Architectures

Figure 3.8

The block diagram of a quadrature phase VCO.

between LO signals of the same amplitude and frequency is an absolute necessity in designing I/Q downconverters. The mixers themselves are likely to be Gilbert cell mixers because this class of mixers has high natural isolation, high conversion gain, and relatively low LO power and dc power requirements [3]. See Chapter 11 for more details on Gilbert cell mixers. An important design criterion for this class of mixers is the necessity for both sides of the mixer to be absolutely balanced. If any imbalance occurs, the performance of the mixer in terms of isolation, gain, linearity, and noise figure will suffer greatly. For this reason, it is important when laying out a Gilbert cell mixer to take special care to ensure that the two sides of the mixer are truly mirror images of each other. Even small amounts of imbalance (perhaps as physically small as a tiny piece of metal on one side of the mixer that is not reflected on the other side of the mixer) will cause significant loss in performance, especially performance relative to the true reproduction of I and Q information, which is essential to the high-quality reception of phase-modulated digital signals. This ability of the I/Q receiver to not distort the digital phase information is measured by a parameter called error vector magnitude (EVM). EVM combines the effects of mixer nonidealness and LO phase noise into one parameter that measures a receiver’s ability to reproduce the information contained in a digital phase-modulated signal without introducing significant distortion causing bit errors. Only by combining a very low-noise-figure LNA with an extremely well-balanced pair of Gilbert cell mixers and a low-phase-noise LO signal split into an in-phase component and a quadrature-phase component (phase-shifted by 90º) can low EVM and low BER be achieved for any or type of phase modulation.

3.2

I/Q Modulators I/Q modulators, which are used in transmitters, are the dual of the I/Q downconverting mixer, that are used in receivers. The I/Q modulator in fact simply turns the functions around and produces an output signal at RF frequencies based on an LO input (also at RF frequencies) and a baseband input containing the modu-

3.2 I/Q Modulators

31

lating information in I/Q form. The architecture of an I/Q modulator is shown in Figure 3.9(a) and is easily recognized as an I/Q downconverting mixer running backwards. A second version of the I/Q modulator is shown in Figure 3.9(b). This version of the I/Q modulator makes use of a frequency-translating upconverting mixer to prevent PA leakage [as shown in Figure 3.9(a)] from pulling the frequency of the VCO. A very interesting feature of an I/Q modulator is that, due to the extremely high LO to output isolation of a Gilbert cell mixer, very little, if any, LO

Figure 3.9(a) paths.

The block diagram of a direct-conversion transmitter showing PA-to-VCO leakage

Figure 3.9(b) The block diagram of a double-conversion transmitter, which solves the PA-to-VCO leakage problem.

32

RFIC Architectures

signal is present at the mixer’s output. This means properly designed I/Q modulators produce output only in response to modulation inputs. These inputs come in the form of an I signal line and a Q signal line, which are connected to the two modulation mixers in the same way as the serial data inputs are connected to the two mixers in the QPSK generator shown in Figure 3.4. In fact, the I/Q modulator is simply a generalization of the QPSK generator discussed previously. However, instead of being modulated with only digital 1’s and digital 0’s, as was the case in the QPSK generator, the I/Q modulator is capable of being modulated with an analog signal on both its I input and its Q input. This generalized modulation input allows the I/Q modulator to cover a wide variety of phase and amplitude states. In the simplest case, it can produce BPSK if no Q input is applied and the I input is toggled by the data stream between +A and –A. Next, QPSK is produced if both the I and Q inputs are toggled by their respective streams by +A and –A (in exactly the same way as the QPSK generator in Figure 3.4 operates). However, since the modulator is capable of responding to a wide range of I and Q input signals, it is capable in general of producing a wide variety of what is called N-QAM modulations (QAM stands for “quadrature amplitude modulation”). The modulator’s linearity is an important issue in determining signal integrity. Like the receiving I/Q downconverter, phase errors resulting from the nonlinear responses of the mixers, or phase noise associated with the LO signal, will result in bit errors. Performance metrics such as EVM, I/Q phase imbalance, and various signal-to-noise ratios are used in evaluating the quality of an I/Q modulator. As the modulation becomes progressively more complex (i.e., N increases in the N-QAM signal constellation), the decision boundaries between phase states get closer together, making the overall system BER more sensitive to smaller values of EVM and signal-to-noise ratio. This is the inevitable price that must be paid for obtaining the higher data rates associated with higher-order phase modulations.

3.3

Nonzero IF Receivers Superheterodyne receivers have been in use since the 1920s. In many ways, they remain the gold standard of receiver technology for a number of important reasons. To understand the performance trade-offs encountered with nonzero IF receivers (i.e., superheterodyne receivers) and receivers in general, we must first discuss the primary goals of all radio receivers. Since the early days of radio, it has been widely recognized that any radio receiver must have two important attributes: the first is sensitivity, and the second is selectivity. Sensitivity refers to a receiver’s ability to detect weak signals and is closely linked to the concept of signal-to-noise ratio. It is for reasons of sensitivity that most receiver architectures begin with a low-noise amplifier (LNA) connected between the receiving antenna and the rest of the receiver (see Chapter 8). The LNA’s purpose is to build up the weak signals coming from the antenna to the point where they may be effectively processed by the rest of the receiver, while contributing little if any noise to the amplification process. A good LNA will have very little effect on the signal-to-noise ratio of received signals; it will simply amplify their levels while adding little if any noise on its own. The design of a good LNA is the key ingredient in attaining good receiver sensitivity.

3.3 Nonzero IF Receivers

33

From this point of view, receiver sensitivity is the overall goal that is most easily achieved. Selectivity is not so easily achieved. The second primary goal of all receivers, selectivity, is defined as a receiver’s ability to distinguish between received signals and to pick out the desired signal and reject all others. A highly selective receiver will have the ability to detect the information carried by only one signal, which it focuses on to the exclusion of all other signals. In reality, this is a very tall order. Selectivity is difficult to obtain because of interference and interferers. Interference is defined as any received signal, other than the desired signal, that has an ability to degrade a receiver’s ability to receive the intended signal. Some interferers may be very strong relative to the desired signal. Some interferers may simultaneously be very close in frequency to the desired signal. Some interferers may be very strong and very close in frequency to the desired signal. All of these situations pose great challenges for any receiver. In general, there are two circuit characteristics that the receiver’s components must have in order to reject interferers: the first is highly effective filtering, and the second is high linearity, even at large input signal levels. Figure 3.10 shows the heart of a superheterodyne receiver, that is a downconverting mixer preceded by an “image-rejection” filter. Consider filtering first. Filtering is the first line of defense against interference and interferers. Since the early days of radio, improvements in filtering techniques went hand in hand with the ability of receivers to distinguish between radio stations in an ever increasingly crowded broadcast radio spectrum. In general, it is easier to build high-performance filters at low frequencies than at high frequencies due to construction techniques and the effects of parasitic elements at high frequencies. For this reason, as radio advanced to ever higher frequencies, it became more difficult to achieve the kind of filter selectivity that is achievable at lower frequencies. For these reasons and others, which we will discuss shortly, Erwin Armstrong (1890–1954) [4] invented the superheterodyne receiver in 1919, during his World War I military research. Armstrong’s new receiver used the then revolutionary technique of downconverting a high-frequency input signal to a much lower frequency, called the IF frequency (i.e., intermediate frequency). To make this technique a reality, Armstrong pioneered the use of mixers and local oscillators to enable the downconversion process. In return for the additional circuit complication, he got

Figure 3.10 The block diagram of a downconverting receiver mixer together with an image-rejecting band-pass filter.

34

RFIC Architectures

a receiver whose major filter selectivity was achieved at a much lower frequency than the received frequency, meaning that inexpensive high-performance filters could be used to determine the selectivity of receivers tuned to very high-frequency signals (such as the newly opened FM band). Armstrong’s superheterodyne receivers had razor-sharp selectivity even at very high frequencies, which proved revolutionary for receiver technology. There are two other advantages to using the downconversion process associated with the superheterodyne receiver. First, it provides most of the receiver’s gain at the IF frequency, after frequency conversion, where amplifiers are small, cheap, and perform very well, as opposed to amplifiers at the RF frequency, which may be large and expensive and perform less well. The other advantage comes about in the detector and the audio amplifier, which follows the detector, where the information contained in the modulation is removed from the carrier signal and amplified before driving a speaker. Before superheterodyne techniques became widespread, this detection was done directly at the RF frequency, and a great deal of audio gain was applied after the detector to build up the signal strength to drive the speaker. Prior to superheterodyne, the detector was operating at relatively low signals, requiring a great deal of audio gain to build signal strength. Such an architecture is highly vulnerable to 1/f noise in either the detector or the audio amplifiers. Superheterodyne techniques solve this problem by using a great deal of gain at the IF frequency to build the signal up so that when it reaches the detector, the signal-to-noise ratio is already very high, and 1/f noise effects do not impact the signal. It should be pointed out that very little 1/f noise is generated in the IF amplifiers because these amplifiers are operating at sufficiently high frequencies to avoid most of the 1/f noise, which is by nature concentrated at much lower frequencies. Figure 3.11 shows the complete block diagram of a single-conversion superheterodyne receiver [5]. Understanding the behavior of the band-pass filters is critical to understanding the operation of the whole receiver. The first band-pass filter (before the LNA) is the first line of defense against interferers that may be located outside of, but close to, the band of interest. For this reason, a highly selective band-pass filter in the receiver’s front end will help greatly with removing out-of-band interference. If this interference is not removed by filtering, it is very possible that two strong interfering signals could be intermodulated within the LNA to produce new signals that could be located in the band of interest. This front-end filter is critical to achieving high selectivity in any receiver design. A second band-pass filter follows the LNA. This filter is called the image filter. Referring to Figure 3.12, it is possible in a downconverting receiver to encounter a

Figure 3.11

The block diagram of a single-conversion superheterodyne receiver.

3.3 Nonzero IF Receivers

35

Figure 3.12 The spectrum of a downconverting receiving mixer showing the frequency components associated with frequency conversion and with the image problem.

situation called the image problem. Assume the LO signal is higher in frequency than the RF input signal (by the IF frequency). Unfortunately, the chance appearance of an interfering signal at a frequency equal to the LO frequency plus the IF frequency will also deliver a signal at the same IF output frequency as the signal that we intend to receive. Such an interfering signal is called an image signal, and its frequency (Flo + Fif) is called the image frequency. To guard against interference from image frequency signals, it is necessary to use a second band-pass filter to provide sufficient rejection at the image frequency so that any interfering signal appearing at that frequency will be suppressed to a large enough degree that it will be rendered undetectable. To accomplish the filtering of the image frequency, we encounter a problem. If the IF frequency is very high, it is not difficult to filter the image with a simple band-pass filter, as shown in Figure 3.13. However, the requirement of a high IF frequency means that the band-pass filters in the receiver’s IF section must operate at very high frequencies, which means these filters will require difficult and expensive designs. However, consider the alternative. The IF frequency can be reduced to frequencies where the IF filters become easy to design, and even inexpen-

Figure 3.13 A wideband (i.e., low Q) image-rejection filter is used with receivers that operate with a high IF frequency.

36

RFIC Architectures

Figure 3.14 A narrowband (i.e., high Q) image-rejection filter is used with receivers that operate with a low IF frequency.

sive filters perform very well. But the burden is now placed on the image filter because, as shown in Figure 3.14, the image frequency, the LO frequency, and the RF input frequency are now very close together. This means that in order to be truly effective, the image filter must be very sharp so that it can pass the RF input signal with little or no attenuation but still have adequate rejection at the now close by image frequency. This no-win filter dilemma led receiver designers to an architectural concept called the double-conversion superheterodyne receiver. A block diagram of the double-conversion receiver is shown in Figure 3.15. With the double-conversion superheterodyne, it is possible to “have our cake and eat it too.” With this architecture, there are two frequency downconversions and two IF frequencies. This means it is possible to choose the first IF frequency to be high in order to simplify the design of the image filter and, at the same time, to choose the second IF frequency to be low in order to allow the channel-select filter to be simple, inexpensive, and effective as the ultimate determiner of the channel bandwidth and interference rejection. The double-conversion superheterodyne receiver is truly the gold standard of all communications receiver architectures, and it has remained in this enviable position for many years. I/Q demodulation is done at the second IF frequency, taking advantage of the razor-sharp IF filters to reject interfering signals. However, there are certain practical problems with a double-conversion superheterodyne architecture in RFIC applications. The basic problem is the requirement for too many off-chip com-

Figure 3.15 The block diagram of a double-conversion superheterodyne receiver. This architecture solves the high-IF-versus-low-IF-frequency dilemma that must be confronted when choosing an image-rejecting band-pass filter for a single-conversion superheterodyne receiver.

3.4 Zero IF Receivers

37

ponents. Both the input band-pass filter and the image filter are too selective (high Q) to be realized on-chip. Therefore, they must be treated as off-chip components and attached to the PCB next to the RFIC chip. Also, the requirement for two IF frequencies means the necessity for two IF band-pass filters, as well as two downconverting mixers and two local oscillators. Some of this circuitry can be located on-chip, but much of it (like both of the IF filters) may be more effectively located off-chip. Also, two different frequency reference oscillators may be necessary for the phase-locked loops composing the two local oscillators. These reference oscillators will be located off-chip, adding to the collection of off-chip components. Because of the large number of off-chip components needed to support a double-conversion superheterodyne architecture, designers of RFIC circuits are looking for simpler alternative architectures capable of reducing the required number of off-chip components. The answer to this search is the so-called zero IF receiver.

3.4

Zero IF Receivers The basic architecture of a zero IF receiver is shown in Figure 3.16. Zero IF receivers are a kind of superheterodyne receiver in which the IF frequency has been reduced to zero. This is done in a very clever way by combining an I/Q downconverter with a front-end LNA and band-pass filter [6]. By using this technique, the I/Q downconverter is both a frequency-converting device from RF to base band, as well as a demodulating device that resolves a modulated signal into its in-phase and quadrature-phase components [7]. By using zero IF techniques, the IF filters take the form of low-pass filters (which filter base band) rather than the customary band-pass filters used in nonzero IF receivers. Also, only one frequency downconverter is required, and because the RF and the LO frequencies are the same, there is no image frequency, eliminating the need for an image filter. These considerations greatly simplify the architecture of a zero IF receiver relative to non-

Figure 3.16

The block diagram of a zero IF, direct-conversion receiver.

38

RFIC Architectures

zero IF receivers. An additional simplification is in the LO. Since the LO frequency is the same as the RF input frequency, in most cases where there is a common RF frequency for both transmitting and receiving, the LO signal can be used for both transmitting and receiving. This consideration alone greatly simplifies the architecture of a combined receiver and transmitter, called a transceiver. With all of these advantages, why are any receivers built with a nonzero IF architecture? The answer is that to gain all of the advantages of a zero IF receiver, it is necessary to live with its short, but significant, list of shortcomings. The leading disadvantage of a zero IF receiver is the problem of dc offsets. This is a particularly difficult problem to live with because of all the gain available at dc in the variable gain amplifiers at the receiver’s back end. These relatively low-frequency amplifiers are responsible for most of the receiver’s overall gain. Most receivers must have 80 to 90 dB gain between the antenna and the detector to effectively receive the extremely weak signals that reach the antenna in any realistic wireless link. If the LNA has 30 dB gain (to overcome the mixer’s second-stage contribution to noise figure), and the mixer has 10 dB gain, that is only 40 dB of a required 80 to 90 dB total. This means that the variable gain amplifier (VGA) must contribute a gain of 40 to 50 dB. This includes dc because, in effect, with this class of receiver, dc is the IF frequency. The high-frequency limit of the VGA is determined by the low-pass filter (which plays the same role as the IF-band selecting filter in a nonzero architecture). Ultimately, the upper frequency limit of both the low-pass filter and the VGA are determined by the modulation information rate of the data passing through the receiver. For instance, in a WiFi receiver, the filter’s upper frequency is about 11 MHz, corresponding to a data rate of about 22 Mbps with QPSK modulation (two bits per symbol). Should a significant (or, for that matter, insignificant) dc imbalance develop within the mixer, the VGA will immediately go to the rail and become saturated by this dc offset. It does not take much input dc offset to saturate a 50 dB gain dc-coupled amplifier. Let’s examine the root causes of dc offset. One of the causes of dc offset is LO leakage from the mixer’s input port. Such leakage is also a problem from a different perspective: if this leakage reaches the antenna, the receiver can be acting as a transmitter by radiating the LO signal. Such LO radiation can act as an interfering signal to other receivers located close by. However, this LO radiation is partially reflected by the antenna and reenters the LNA input, where it experiences gain before entering the mixer’s input with a different phase relationship than the LO signal, which is being supplied by the LO circuits to the mixer’s LO port. Since the LO leakage has a unique phase relationship (which may even depend on objects close by the antenna), it mixes with the LO in unpredictable ways. Since both the leakage signal and the intentional LO are at the same frequency, the result of their interaction can only be a dc output from the mixer. In effect, the mixer is functioning as a phase detector, measuring the phase relationship of the leakage to the intended LO’s phase. The unpredictable dc offsets produced by this LO leakage can potentially send the VGA into saturation and severely disable the receiver. Figure 3.17(a) gives a block diagram presentation of how LO leakage affects the performance of a zero IF receiver. Before we present solutions to the dc-offset problem, let us consider a second source of dc offsets. If strong in band interfering signals are amplified by the LNA

3.4 Zero IF Receivers

39

Figure 3.17(a) LO leakage paths associated with a direct-conversion receiver may cause dc offsets at the receiver’s output and LO radiation from the system’s antenna.

Figure 3.17(b)

Self-mixing strong interfering signals may also cause dc offsets at the receiver’s output.

and enter the mixer’s input, these interfering signals, if they are strong enough, can act as spurious LO signals as they are transferred to the mixer’s LO port as a result of imperfect R to L isolation. In effect, these strong spurious signals (they must be close enough in frequency to be passed by the front-end band-pass filter) serve as self-mixing signals that are downconverted to dc by the mixer. As with LO leakage, the strong interferer becomes the cause of unpredictable dc offsets at the mixer’s output with the potential to send the VGA into saturation, as shown in Figure 3.17(b). VGA saturation is a very serious situation because of gain saturation

40

RFIC Architectures

and the potential for intermodulation to create serious limitations on receiver performance. There are two possible solutions to the dc-offset problems in zero IF receivers. The first solution to the dc-offset problem is simply to ac-couple the outputs of the low-pass filters to the VGAs with series capacitors, as shown in Figure 3.18. This simple technique completely eliminates the dc offsets and solves the problem. However, this simple solution comes with its own penalties, the most important being the loss of signal-to-noise ratio because the signal energy contained in each symbol is effectively being high-pass-filtered by the capacitors. Also, to keep loss of signal-to-noise ratio to a minimum, it may be necessary to locate the capacitors off-chip as surface-mounted capacitor chips, in order to accomodate their values. A second technique for eliminating dc offsets is to use feedback around the VGA to cancel out any dc-offset voltages that may develop. This technique is demanding in terms of circuit design; however, it has the advantage of being entirely on-chip and does not contribute to any loss of signal-to-noise ratio. However, it must be emphasized that in order to make such a feedback loop work, the designer must take special care to ensure that the loop is stable over a wide range of frequencies. Insuring stability can be a difficult task, considering that the VGA’s gain is between 40 and 50 dB and its bandwidth is dc to perhaps 100 MHz. The effectiveness of a zero IF receiver is measured by two metrics called signal-to-noise (S/N) and error vector magnitude (EVM) [8]. The phase-modulated signal passing through the receiver is changed from its original form to a modified form that is observed in the output of the receiver. The modified form is a result of LO phase noise, which tends to draw phase state points into arcs, and phase nonlinearity, which offsets the relative position of the phase state vectors. To function in a fully nondistorting way and to assure the receiver’s user of a very low

Figure 3.18 ac coupling of a direct-conversion receiver’s output solves the dc-offset problem at the price of reducing the received signal’s signal-to-noise ratio.

3.5 Differential versus Single-Ended Topologies

41

bit-error rate, it is necessary that the EVM specification be less than 15 to 20 percent. To realize this goal, a zero IF receiver must have extremely low LO phase noise, very accurate 90º offset of the LO signal between mixer 1 and mixer 2, and very low phase nonlinearity throughout. These requirements can pose a difficult challenge to the RFIC designer; however, the zero IF receiver has the powerful advantage of requiring few, if any, off-chip components. About the only components that are certain to be off-chip are the front-end band-pass filter and the dc-blocking capacitors, which prevent dc offsets from saturating the VGA. If feedback techniques are used in the VGA to cancel the dc offsets, the off-chip capacitors are eliminated. This reduces the set of off-chip components to only the front-end band-pass filter. Even though the double-conversion superheterodyne receiver is hard to beat in terms of performance, it requires a great many off-chip components, which are serious cost and size drivers. Because of all of these considerations, the wireless industry has embraced the zero IF architecture over the last decade, and it has become the de facto standard for most RFICs used in today’s wireless applications.

3.5

Differential versus Single-Ended Topologies Gilbert cell mixers (see Chapter 11) form the heart of both receivers and transmitters in the wireless industry. Because these mixers have fully differential inputs and outputs, it is very tempting to configure all of the components connected to Gilbert cell mixers as fully differential. This means that LNAs, buffer amplifiers, and filters must also be differential if an on-chip conversion from single-ended to differential is to be avoided. In fact, if all of the on-chip circuits are in differential form, the conversion to single-ended need never be done on-chip but can be put off until a signal input or output allows the use of an off-chip balun, which can be mounted on the same circuit board that the RFIC is connected to. In fact, it makes no sense to be constantly making differential-to-single conversions on-chip. Since the Gilbert cell mixers are naturally differential, it makes a great deal of sense to remain in a completely differential format on-chip, converting to single-ended when necessary, using off-chip baluns. A second advantage to using all differential topologies with the on-chip components is the avoidance of common mode problems. If grounds are for any reason incomplete or inconsistent, no common mode problem will result with a differential topology. However, if some of the on-chip circuits are single-ended, it is possible that grounding problems may affect the LO leakage paths associated with a direct-conversion receiver and may cause dc offsets at the receiver’s output and LO radiation from the system’s antenna. Problems such as these can be difficult to understand and troubleshoot.

References [1]

Shannon, C., and Weaver, W., A Mathematical Theory of Communications, Urbana: University of Illinois Press, 1949.

42

RFIC Architectures [2] [3] [4] [5] [6] [7] [8]

Shannon, C., “A Mathematical Theory of Communications,” Bell Sys. Technical J., Vol. 27, July 1948, pp. 379–423, and October 1948, pp. 623–656. Armstrong, E., “Some Recent Developments in the Audion Receiver,” Proc. IRE, Vol. 3, 1915, pp. 215–247. Maas, S., Microwave Mixers, Boston: Artech House, 1986. Razavi, B., RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998. Lee, T., The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge: Cambridge University Press, 1998. Tiebout, M., “Low Power, Low Phase Noise Differential Quadrature VCO in CMOS,” IEEE J. of Solid State Circuits, Vol. 36, July 2001, pp. 1018–1024. Ristenbatt, M., “Alternatives in Digital Communications,” Proc. IEEE, Vol. 61, June 1973.

CHAPTER 4

InGaP/GaAs HBT Fabrication Technology 4.1

Transistor Structures In order to fabricate RFIC circuits, it is necessary to adhere to a strict set of design rules and device models supplied to the designer by the foundry. In the case of InGaP/GaAs HBT technology, the design rules give the designer a complete set of layout rules, which in effect tell what physical limitations have been encountered by the fabrication equipment at the foundry’s wafer-fabrication facility. For example, a design rule requiring a minimum line width for a particular metal layer informs the designer of the foundry’s photolithographic equipment’s resolution limits for that particular layer. Design rules assure the designer that his or her RFIC design can be fabricated to the dimensions and tolerances required by the design. To be sure that the design information is conveyed to the foundry in the most unambiguous way, it is important that both foundries and designers agree upon a common set of units to assure clear communications of design data. The following is a set of units universally accepted by GaAs HBT foundries (and foundries in most other technologies). 1. Spatial dimensions are measured in microns or µm (1E–6m). 2. The smallest grid used in computer-aided design (CAD) layout tools is 0.5 µm. 3. Capacitance is measured in either pF or fF. 4. Inductance is measured in nH. 5. Resistance is measured in ohms. Two distinct IC structures are fabricated by the foundry. The first set of structures involves all of the necessary layers for the fabrication of transistors. The second set of structures includes all of the metal and dielectric layers that make up the metal interconnects, resistors, capacitors, and inductors. With regard to transistor fabrication, every foundry is unique in its approach to transistor layout and fabrication. Some foundries will allow the designer complete control over the geometry of the transistor’s design, while other foundries simply supply what, in effect, is an appliqué containing all of the necessary layers to fabricate a single-emitter-finger transistor. In the case of the appliqué transistor, the designer is free to make larger transistors by connecting a number of these appliqué “unit cell” transistors in parallel. This is a very common approach, and some foundries simply provide the designer with a “dummy” unit cell, with all of its inputs and output at the proper locations. In this case, at the time of mask making, the foundry

43

44

InGaP/GaAs HBT Fabrication Technology

will read into each dummy cell all of the layers needed to fabricate the unit cell transistor that resides in the dummy cell. Let us go back to the beginning of the wafer-fabrication process to see how the transistors are processed. The first step is called deposition of the epitaxial layer on the top surface of the wafer. The word “epitaxial” is derived from the Latin root words “epidermis,” meaning the outer layer of skin, and “taxial,” referring to crystals. In effect, “epitaxial” means “the skin of the crystal,” which is exactly what it is. Only a very thin top surface of an epitaxial wafer is electrically conductive, but it is these thin layers that completely determine the electrical characteristics of the transistors that will be fabricated on the wafer. The wafer itself is semi-insulating, which means its electrical conductivity is very low, in effect making it behave like an insulator, such as glass or quartz. On top of this insulating substrate, several (five) conductive layers are deposited, as shown in Figure 4.1. The bottom layer is an N+ GaAs subcollector, the next is an N GaAs collector, the next is a P+ GaAs base, the next is a N InGaP emitter, and the topmost layer is a N+ GaAs emitter contact. Because of the presence of the InGaP emitter layer, the transistors formed by this process are known as heterojunction bipolar transistors (HBTs). HBTs have superior electrical characteristics at high frequencies, making them ideal devices for RFICs operating at the frequencies of wireless communications. The initial photolithographic wafer fabrication of GaAs HBT RFIC circuits consists of patterning and fabricating the HBT devices themselves. This process involves successive steps involving selective etching of the wafer’s epitaxial layers. Upon etching these layers into a mesa structure with collector, base, and emitter structures formed with the proper length and width dimensions, a metal contact layer is patterned and deposited on top of the corresponding semiconductor layer. The finished transistor structure is shown in Figure 4.2, including all contact metals. Foundries supply designers with layout “applicas,” which include all of the necessary layers for patterning and fabricating single-emitter-finger unit cell transistors. At the periphery of each unit cell transistor are first-metal (M1) pads, where connections to the greater circuit must be made. Larger transistors are made by combining many unit cell transistors in order to create a device properly sized with the number of emitter fingers called for by the requirements of the design. Once all transistors and diodes (devices that use only the base-to-emitter junction of a transistor, with the collector and base terminals hardwired together) have been fabricated, any remaining epitaxial layer material is stripped off, exposing

N+ EMITTER CONTACT N InGaP EMITTER P+ GaAs BASE N GaAs COLLECTOR N+ GaAs SUB COLLECTOR S.I. GaAs SUBSTRATE Figure 4.1 Cross section of a GaAs HBT wafer showing the various epitaxial layers associated with the transistor’s structure.

4.2 Device Models

Figure 4.2

45

Cross section of an InGaP/GaAs heterojunction bipolar transistor.

the bare GaAs semi-insulting substrate in preparation for deposition of the metals and insulators that will define all of the passive and interconnecting elements within the RFIC.

4.2

Device Models InGaP/GaAs HBT devices make use of one of two possible device large-signal electrical models. Large-signal models make it possible for designers to literally simulate all device and circuit performance parameters that can be measured in the laboratory. The oldest of these models is the Gummel Poon model [1], and the more recent model is the VBIC [2] model. The Gummel Poon model was originally developed for use in single-element silicon bipolar devices. It is an excellent model and is used widely in bipolar circuit design for a wide variety of device and material technologies, but it has a few shortcomings related to GaAs HBT devices. The first limitation of the Gummel Poon model is its lack of a way to account for the effects of self-heating. In silicon devices, this is not a major factor because of the high thermal conductivity of silicon, but in GaAs it is a different story. GaAs devices experience considerable self-heating as a direct result of this material’s low thermal conductivity. This means a GaAs HBT transistor will experience significant temperature rise when operating near its maximum power ratings. Such temperature rise will affect the elements in the model’s equivalent circuit and, if not accounted for, may prove to be the cause of significant error when modeled circuits which are compared to experimental measurements. A second shortcoming of the Gummel Poon model is its inability to model the electrical behavior of a transistor on the verge of avalanche breakdown. Avalanche breakdown occurs when electrons and holes receive sufficient energy from the device’s internal electric fields to cause a chain reaction to occur, releasing additional electrons and holes that add to a growing wave of excess current. Left unchecked, this avalanching current will destroy the device in a phenomenon called breakdown. If breakdown is only approached on the peak of each RF cycle, this phenomenon can serve as a waveform-modifying mechanism that contributes to the nonlinear behavior of an HBT device operating at large-signal levels. As with self-heating, breakdown phenomena are not accounted for in the Gummel Poon model. The intent of the developers of the VBIC model was to correct these deficiencies and to create a more accurate model for all types of GaAs HBT transistors. A generic Gummel Poon model for a single-finger unit cell device with

46

InGaP/GaAs HBT Fabrication Technology

an emitter measuring 2µm × 15µm is shown in Figures 4.3(a–c). A generic VBIC model for a similar unit cell device is shown in Figures 4.4(a–c). Simulated DC IV curves and small signal s-parameters for each model are shown in Figure 4.3(b,c) and Figure 4.4 (b,c). These generic device models are used to simulate many of the circuits which are presented in the following chapters. The generic models describe device behavior that is very similar to current foundry devices. Large transistors can be conveniently sized in simulations either by paralleling a number of unit cells in the simulator’s schematic diagram or by simply increasing the area (in steps of integer numbers of emitter fingers) in the schematic symbol for the transistor, as shown for ADS [3] schematic symbols given in Figure 4.5. These large-signal device models give the designer all the information necessary to accurately model transistor behavior to simulate dc conditions, small-signal RF conditions, and large-signal RF conditions (including several measures of nonlinearity). The modeling of nonlinear device behavior is extremely important in the design of PAs. The Gummel Poon and VBIC models both contain ways of modeling thermal noise and 1/f noise. The ambi-

Figure 4.3 An ADS schematic diagram for generating the dc IV curves of a bipolar transistor using a Gummel Poon device model.

Figure 4.3(a) HBT.

A generic Gummel Poon large-signal scalable device model for a single unit cell

4.2 Device Models

Figure 4.3(b)

Figure 4.3(c)

47

Simulated dc IV curves for a single unit cell Gummel Poon HBT device model.

Single unit cell S-parameters simulated using the Gummel Poon HBT device model.

ent temperature can be specified, like any other variable in both models. This capability makes it possible for a designer to check how a particular design will function at temperature extremes. This vital capability, which is offered only by these large-signal device models, is critical to the design of LNAs and low-phase-noise VCOs.

48

InGaP/GaAs HBT Fabrication Technology

Figure 4.4 An ADS schematic diagram for generating the dc IV curves of a bipolar transistor using a VBIC device model.

Figure 4.4(a)

A generic VBIC large-signal scalable device model for a single unit cell HBT.

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules Once the transistors are patterned and fabricated, the process of patterning and fabricating the metal and dielectric layers, which define the RFIC’s passive devices and interconnections, can begin. It is in this area that most of the elements associated with circuit design will be defined and fabricated. Figure 4.6 gives a cross-sectional view of the sequence of metal and dielectric layers that define a typical InGaP/GaAs HBT RFIC structure. This picture is realistic but simplified. Each foundry has its own process, which will represent some variation on the basic theme presented here. It is very important that the designer become intimately familiar with the foundry’s design rules and regard the material that follows as a typical, but simplified, general

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules

Figure 4.4(b)

Figure 4.4(c)

49

Simulated dc IV curves for a single unit cell VBIC HBT device model.

Single unit cell S-parameters simulated using the VBIC HBT device model.

process for this technology. The design rule parameters presented in this book are typical of many foundries but are not specific to any one foundry. The fabrication layers, starting up from the semi-insulting GaAs substrate are: 1. Thin film resistor (TFR) 2. Collector contact metal (CM): used in some processes as an alternate resistor material and an adhesion layer under bonding pads, adding additional mechanical strength

50

InGaP/GaAs HBT Fabrication Technology

Figure 4.5

Transistor model ADS schematic symbols.

Figure 4.6 The cross section of an InGaP/GaAs HBT wafer showing the metal and dielectric layers, which are used to form circuit elements and interconnects.

3. First metal (M1): used for interconnects, resistor and transistor contacts, inductors, and capacitor bottom plates 4. Nitride: a thin dielectric material forming capacitors 5. Polyimide: a thick dielectric material providing low coupling capacitance separation between the first metal and the second metal. 6. Second metal (M2): used for overpass interconnects and capacitor top plates 7. Scratch protection: passivating and protection dielectric material that coats the entire chip In addition to these metal and dielectric layers, there are also four vias associated with this process that open holes in the dielectrics to allow metal to be deposited in the next process step to flow though the via in order to establish a metal-to-metal contact or to make a capacitor top plate. These three four are 1. Nitride via (NV) used in forming M1-to-M2 vias and bonding pads 2. Polyimide via (PV) used in forming M1-to-M2 vias, bonding pads, and capacitor tops

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules

51

3. Scratch protect via (SPV) to open holes in the scratch protect layer to form bonding pad contacts 4. Substrate via (SV), a metalized via opened from the chip’s backside and running through the substrate for the purpose of bring a ground contact up to the top side of the chip from the grounded back of the chip By combining the deposited metal layers with the dielectric vias, we arrive at a set of layout levels that must be determined by the designer as the final layout step of the design process. It is important to realize that in the design process, the designer defines the pattern of the metal layers, but the designer also defines the holes (vias) in a particular dielectric layers. If nothing appears in the artwork for a given dielectric via layer, this particular dielectric material will extend over the entire chip area, without holes or breaks. Figure 4.7 shows a list of the eight metal and dielectric via layers that comprise an RFIC design in InGaP/GaAs technology. This list applys to the building blocks of passive circuit elements only, and does not cover transistor fabrication, which is handled separately, as discussed above. The layer numbers and color choices are particular to a given CAD layout system and are in no way general. The designer is free to use his or her own choice of layer colors and layer numbers. The designer should set up the CAD system to use a set of colors that attract the designer’s eye quickly and provide the designer with unambiguous, quickly perceived layer information. The foundry design rules will provide the designer with information about the thickness and resistivity of each metal and dielectric layer. Typical design rule information of this kind is shown in Figures 4.8 and 4.9. Figures 4.10 and 4.11 give the minimum metal and dielectric via widths and spacings. These parameters in effect specify the maximum capability of the foundry’s process to pattern small structures. Using a narrower line than the minimum width specified in Figure 4.10 will risk a break in the line. A closer line spacing than that specified in Figure 4.11 will risk a short circuit between lines. Two items to note: the minimum diameter and spacing of substrate vias are based on mechanical problems that can occur if too many holes in the substrate are spaced too closely. Such a situation can weaken the substrate and possibly causing cracking. Also, the reference to donuts refers to a problem that can arise with the lift-off metal photolithography process, which is used to define layers M1 and M2 [4]. If an unwanted piece of metal in an interior pattern (donut hole) is not connected to the greater body of metal that is to be removed by “lifting off,” it could possibly be left behind to cause problems like short circuits. For safety

Figure 4.7

A table of layer names and possible color assignments to be used with the layout tool.

52

InGaP/GaAs HBT Fabrication Technology

Figure 4.8

A table of InGaP/GaAs process layer thickness.

Figure 4.9

A table of InGaP/GaAs process layer resistivity.

Figure 4.10

Design rules for InGaP/GaAs process minimum layer line widths.

Figure 4.11

Design rules for InGaP/GaAs process minimum layer line spacing.

reasons, it is always best to avoid donuts. If you inadvertently include a donut in your design, the foundry will flag the problem in a design rule correction (DRC) report. Next, we look at various circuit structures that can be patterned with this process.

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules

4.3.1

53

Microstrip Lines

The first structure is a microstrip line [5], which is shown in cross section in Figures 4.12(b) and Figure 4.13, and from the top in Figure 4.12(a). Microstrip transmission lines can be formed with either M1 or M2. They are both equivalent in this respect because the dielectric layers between them are so thin compared to the substrate thickness that dominates the microstrip line’s dielectric thickness, as shown in Figure 4.14. All the designer need specify in the design of a microstrip line is its length L and its width W. The electrical behavior of the microstrip line can be communicated to a simulator, such as the Agilent ADS system, by entering the lines length L and width W, along with entering the substrate and line thickness information in the simulator’s MSUB controller block. See Figure 4.15 for an example of entering the microstrip line parameters into an ADS circuit schematic diagram. The ADS element for a microstrip line is MLIN. Microstrip lines may be an intentional part of a design, or they may be regarded as a parasitic effect resulting from the necessity of connecting two points in an RFIC layout together with a metal line. In either case, these metal traces should be modeled as microstrip lines in all simulator models. This is especially true at high frequencies. At 900 GHz, short microstrip lines may have little effect on electrical performance, but above 2.0 GHz, the effects, depending on line length and width, can become very significant.

Figure 4.12(a)

The electrically critical dimensions of any microstrip metal line.

Figure 4.12(b)

Cross section of microstrip metal (either M1 or M2) interconnect lines.

54

InGaP/GaAs HBT Fabrication Technology

Figure 4.13

The layouts of microstrip interconnect metal lines using either M1 or M2.

Figure 4.14

A table of dielectric layer thickness.

Figure 4.15

An ADS schematic symbol for microstrip metal lines.

Two microstrip lines running parallel to each other are called coupled lines because energy can be coupled from one line to the other if they are close enough together. Coupled lines may cause unwanted cross talk to occur between unconnected portions of a circuit and, in most cases, should be avoided if possible. Of course, this requirement is at odds with the general desire to reduce the overall chip area for economic reasons. If a parallel run of either M1 or M2 is unavoidable in a given design; as shown in Figure 4.16, it is necessary to include this parallel

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules

Figure 4.16

55

The layouts of coupled microstrip interconnect metal lines using either M1 or M2.

microstrip line section as a part of the simulation schematic. In ADS, the element that models parallel microstrip lines is MCLIN, which is shown in Figure 4.17. 4.3.2

TFR Resistors

Resistors are formed by using a combination of M1 (as a contact on both sides of the resistor trace) and thin film 50 ohms per square resistor (TFR) as the resistor element. The structure of a TFR resistor is shown in Figure 4.18. Notice that for proper contacting, M1 must overlap the TFR material by at least 2µm. The resulting resistor will have a dc resistance of R = (L/W) 50 ohms

(4.1)

The cross section of a TFR resistor is shown in Figure 4.19. If the resistor is to be a part of the high-frequency RF circuit, then its length and width will act as a parasitic microstrip element, which must be modeled in simulation. Therefore, the complete model for a TFR resistor is a lumped-element resistor based on (4.1) in series

Figure 4.17

An ADS schematic symbol for coupled microstrip metal lines.

56

InGaP/GaAs HBT Fabrication Technology

Figure 4.18

The layout of a TFR.

Figure 4.19

The cross section of a thin film resistor.

Figure 4.20

Simulator model of a thin film resistor.

with a microstrip line with the same length and width (L and W) that define the resistor. The simulator schematic for a TFR element is shown in Figure 4.20.

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules

4.3.3

57

M1-to-M2 Vias

Interconnections between the M1 and M2 layers must be accomplished by an M1-to-M2 via. The layout details of the M1-to-M2 via are shown in Figure 4.21, and the via is shown in cross section in Figure 4.22. This via is formed by opening holes in both the polyimide dielectric and the nitride dielectric layers. Once these holes are opened in the dielectric layers, while M2 is being deposited by sputtering, M2 metal will flow down through the holes and come into intimate electrical contact with M1 at the bottom of the hole. All M1-to-M2 connections must be accomplished by using an M1-to-M2 via. 4.3.4

MIM Capacitors

The layout of an MIM capacitor is shown in Figure 4.23. The fabrication of an MIM capacitor is actually very similar to that of an M1-to-M2 via, differing only in the lack of a nitride via (NV) opening in the case of a capacitor. The capacitor is shown in cross section in Figure 4.24. During fabrication, M2 is deposited into the hole that has been opened in the polyimide layer (PV) and comes to rest on top of the nitride dielectric. It is the “sandwich” of M1/nitride/M2 that forms the capacitor. The nitride dielectric layer is kept intentionally thin (about 2,000 angstroms) in

Figure 4.21

The layout of an M1-to-M2 via.

Figure 4.22

Cross section of an M1-to-M2 via.

58

InGaP/GaAs HBT Fabrication Technology

Figure 4.23

The layout of an MIM capacitor.

Figure 4.24

Cross section of an MIM capacitor.

order to insure high capacitance per unit area. The capacitor’s value may be calculated from the relationship C = LW (0.300) fF

(4.2)

where L and W are the length and width of the M2 top plate in microns. Capacitors need not be square, and if required may be designed with a wide range of aspect ratios. Because the M1 bottom plate is in contact with the substrate, it forms an open-circuit microstrip stub and must be modeled as such in simulations. Figure 4.25 gives the ADS simulator schematic for an MIM capacitor, including the microstrip stub created by the M1 back plate. It is important always to remember that one capacitor contact is the M1 back plate, and the other contact is the M2 top plate. Attention to this detail will save the designer much trouble from hard-to-spot layout errors. 4.3.5

Substrate Vias

It is possible to create excellent grounds at any point in a RFIC layout by using a substrate via. Substrate vias are metalized holes that reach from the top side of the chip to the bottom side. Since the metal on the chip’s bottom side is the truest ground reference, these vias provide the designer with an easy and fool proof way to ground any portion of the circuit without having to rely on attaching bond wire from the

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules

Figure 4.25

59

Simulator model of an MIM capacitor.

edge of the chip to a ground pad in the chip’s package. By using substrate vias to create low-inductance grounds, a whole class of parasitic problems can be avoided. The layout of a substrate via is shown in Figure 4.26. The central circle is the metalized hole, which extends from the bottom side to the top side of the chip. All metal layers (including collector metal) and all dielectric vias are present in the structure of a substrate via. This is to add mechanical strength in this important structure. For safety reasons, substrate vias must not be placed too closely together, and they cannot be placed too close to the edge of a chip. The design rules given in Figures 4.8 to 4.11 specify the limits of these dimensions. The cross section of the substrate via is shown in Figure 4.27. To first approximation, a substrate via is a perfect ground contact. However, at higher frequencies, the metal in the backside to topside hole will have some small amount of inductance, which will act as a parasitic element. There are existing simulator elements for substrate vias that can be used in the simulator schematic when the operating frequency is sufficiently high (above 5 GHz).

Figure 4.26

The layout of a substrate via that provides direct grounding to the backside metal.

60

InGaP/GaAs HBT Fabrication Technology

Figure 4.27

4.3.6

Cross section of a substrate via.

Bonding Pads

In order to connect external inputs and outputs to the RFIC, it is necessary to provide metal bending pads where these wires can be connected using thermocompression bonding techniques [3]. Mechanical strength is extremely important in the structure of bond pads because the process of attaching a bond wire to a pad is so forceful that it can crack or delaminate the metal layers forming the pad. For this reason, all metal layers (including collector metal, which has excellent adhesion properties) and all dielectric vias are included in bonding pads. The layout of a bonding pad is shown in Figure 4.28, and its cross section is shown in Figure 4.29. In addition, bonding pads, and bonding pads alone, require the presence of the scratch protection via (SPV) layer to insure that an opening in the scratch protection dielectric has been made to allow the bond wire to contact M2 directly.

Figure 4.28

The layout of a bonding pad.

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules

Figure 4.29

61

Cross section of a bonding pad.

Bonding pads also play an important role in on-wafer testing. This powerful test technique uses a carefully prepared set of RF probes that contact the inputs and outputs of an RFIC die before it is separated from its wafer. In order to make this useful and powerful test system work, a set of two (in the case of a signal-ground test probe configuration) or three (in the case of a ground-signal-ground test probe configuration) bond pads must be arranged in an array at each input/output to act as contacts for the probes. Because of standard probe dimensions in use within the industry, the bond pads need to be 100µm × 100µm square and spaced at 150µm center to center. This probe-ready pad pattern is shown in Figure 4.30. Each RF input and RF output needs to be supplied with this probe pattern if on-wafer probe testing is to be done after wafer fabrication, but before die separation. 4.3.7

Crossover Capacitances

Whenever an M2 line crosses over either an M1 line or a TFR line, there will be some amount of crossover coupling capacitance. This capacitance is kept to a mini-

Figure 4.30 A pattern of input/output bonding pads that allows for convenient on-wafer RF probe testing.

62

InGaP/GaAs HBT Fabrication Technology

mum by the presence of the thick polyimide dielectric layer in this technology. Just as in the case of the intended capacitance of an MIM capacitor (Section 4.3.4), the crossover capacitances are calculated by multiplying the overlap area between the two lines by the crossover capacitance per unit area of 0.15 fF/µm2. Figures 4.31 and 4.32 show the layout and electrical model for M1-to-M2 overlap capacitance. Figures 4.33 and 4.34 show the layout and electrical model for TFR-to-M2 overlap capacitance. This capacitance is to be avoided whenever possible, even if it means “necking down” the lines in the region of overlap to avoid high overlap area. Of course, circuit simulations will be the final determinant as to whether a given crossover capacitance is excessive or not. 4.3.8

Spiral Inductors

RFIC’s inductor elements must be fabricated with a planar geometry. This need translates into spirals. Square spirals are most popular because they are the easiest to

Figure 4.31

The layout of an M1-to-M2 crossover.

Figure 4.32

An electrical model for simulating the M1-to-M2 crossover capacitance.

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules

Figure 4.33

The layout of an M2-to-TFR crossover.

Figure 4.34

An electrical model for simulating the M2-to-TFR crossover capacitance.

63

create in layout; however, round spirals are also used extensively. Any spiral with more than one turn must use a metal crossover in order to be attachable to the rest of the circuit. If the spiral is formed from M1, this crossover will be an M2 “overpass.” If the spiral is formed from M2, the crossover will be an M1 “underpass.” Both techniques work well, and both metals work well as inductors. Perhaps M2 forms slightly higher-Q inductors owing to its slightly greater thickness. Of course, in both cases, an M1-to-M2 via will be required to transition from the spiral metal to the overpass or underpass metal. Figure 4.35(a) shows the layout of an M1 spiral inductor using an M2 overpass and an M1-to-M2 via. An ADS spiral inductor element (MRIND) is shown in Figure 4.35. Spiral inductors are very important elements in RFIC designs because they are an integral part of all filtering and matching circuits. Also, spiral inductors can form resonator elements in VCO designs. For this reason, special attention needs to be focused on their design. It is important to remember that there is no requirement that spiral inductors be square. Any combination of length and width will serve as well as the better-known square lay-

64

InGaP/GaAs HBT Fabrication Technology

Figure 4.35

The layout of a spiral inductor using M1 metal.

Figure 4.35(a)

An electrical model for simulating a spiral inductor.

out. This can be a valuable asset in the layout portion of any design because spiral inductors can become area drivers, and it is a big help for keeping chip area within reasonable bounds to make the inductors fit the available space by changing their aspect ratios. 4.3.9

Transistor Dummy Cells

In the case of some foundries, a transistor dummy cell will be provided for the designer to use for the purpose of keeping specific areas available for the insertion by the foundry of all layers necessary to define a transistor’s unit cell. Such a dummy cell is shown in Figure 4.36. All that needs to be done with the dummy cell is to locate it within the circuit’s layout wherever a transistor unit cell is required and to contact the dummy cell with M1 metal lines connecting it to other parts of the circuit as required.

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules

Figure 4.36

4.3.10

65

The layout of a single-emitter-finger unit cell (dummy cell).

Significant Layout Parasitic Elements

At low frequencies, it is possible to ignore many or most layout parasitic elements and still produce a successful simulation. However, as the frequency increases, the situation changes, and it becomes increasingly important to include a wider variety of layout parasitic elements. Most simulators include a wide variety of these elements, and it takes considerable skill and experience to know which parasitic elements must be included and which can be safely ignored. My own experience is that 5 GHz serves as a kind of dividing line in frequency. Below 5 GHz, only a few parasitic elements need be included in simulation files. However, above 5 GHz, the designer cannot get away with ignoring certain additional elements. Figure 4.37 shows the basic set of parasitic elements that need to be included for frequencies below 5 GHz, and Figure 4.38 shows those additional layout parasitic elements that must be included for designs operating above 5 GHz. 4.3.11

Simple Layout Example

Figures 4.39 to 4.42 give simple layout examples using the concepts that have been developed in this chapter. The first example structure is a three-finger transistor using three unit dummy cells. The second example is a simple one-finger transistor feedback amplifier with wafer probable bonding pads at the design’s input an output terminals. Notice the use and placement of M1-to-M2 vias where ever an M1-to-M2 connection is needed. Also, note the use of M2 base and collector bus lines in the case of the three-finger transistor.

66

InGaP/GaAs HBT Fabrication Technology

Figure 4.37 Significant layout parasitic elements that must be included in simulator models to support operation below 5 GHz.

Figure 4.38 Additional layout parasitic elements that must be included in simulator models to support operation above 5 GHz.

4.4 Maximum Electrical Ratings

Figure 4.39

67

The layout of a three unit cell transistor.

4.3 Passive Structures, Their Electrical Models, and Layout Design Rules

Figure 4.40 Details of three unit cell transistor layout showing how the collector contacts are connected together.

4.4

Maximum Electrical Ratings It is very important in all IC designs that maximum current limits in all conductors be observed. This is, first and foremost, a reliability issue. The major reliability problem encountered with conductors carrying current is metal migration. Figure 4.43 presents a table showing the maximum current density, expressed in milliamperes per micron of line width for each conductor layer. These limits must be strictly observed to avoid any reliability problems that can shorten the lifetime of a chip once it is in the field. The current referred to in Figure 4.43 is dc current; ac current, although it may be much higher that the dc current on peaks, does not cause the

68

InGaP/GaAs HBT Fabrication Technology

Figure 4.41

The layout of a simple single transistor feedback amplifier.

Figure 4.42 Layout details of the simple feedback amplifier layout example, showing interconnecting metal lines and M1-to-M2 vias.

Figure 4.43 A table of maximum metal current densities, in milliamperes per unit metal width (measured in microns).

same level of metal migration to occur and, therefore, does not pose the same threat to reliability. Metal migration may be understood in the following way. Referring to Figure 4.44, we can envision that a current-carrying conductor is like a stream of water with a sandy bottom. We associate the water with the stream of flowing charge, which is the electrical current, and the sand on the bottom of the stream with the

4.4 Maximum Electrical Ratings

Figure 4.44 metal line.

69

A diagram depicting the process of metal migration that occurs in a current-carrying

atoms at the conductor’s lattice sites. As the steam flows more rapidly, sand is picked up from the bottom by the fast-moving water and deposited downstream. This process creates a series of holes (which, as all fisherman know, make good homes for trout and other game fish), where the water has scooped out the sand, and sand bars, where a buildup of sand occurs as it is carried to be deposited downstream. In the same way, some metal atoms at lattice sites within the conductor are dislodged from their positions within the crystal lattice and transported “downstream” by the steam of flowing electric charge, which forms the current. Just as in the case of the steam of water, holes are formed where large groups of atoms are dislodged, and accumulations of atoms form “downstream” where these dislodged atoms come to rest. The danger to reliability comes from the holes, where the conductor’s width is locally reduced by the “scooping out” of atoms from their lattice sites. These areas of metallic “Swiss cheese” have increased resistivity relative to the unaffected portions of the conductor. Heating can occur locally at these “weaknesses” within the conductor; over time, with sufficient current, the local temperature rise can be sufficient to cause a failure. For this reason, all foundries provide a list of maximum dc current densities for each conductor layer within their design rules, much like the table given in Figure 4.43. A safety factor has already been built into this design rule. So, to produce a reliable device, all the designer need do is observe these maximum current densities for all conductors within a design. Problems sometime arise in resistors whose maximum current density is often less than conductor lines, and with spiral inductors, which are often required to carry the large collector currents needed in power amplifiers. In the case of the resistor, the problem can usually be solved by simply increasing the resistors width and recalculating the resistors length using (4.1). Spiral inductors are more difficult to deal with relative to current limits. The straightforward approach is simply to increase the inductor’s width until the current density limit is observed. The problem with this approach is that it often leads to the design of a very large inductor, which can become an area driver for the overall RFIC. An alternative that should be considered, but is not always practical, is to place high-current carrying choke inductors off-chip. Many excellent surface-mount technology (SMT) inductors exist that occupy very little board space and carry high dc currents. Designers will need to make this decision on a case-by-case basis.

70

InGaP/GaAs HBT Fabrication Technology

The transistor unit cell also has current limits based on reliability considerations. These limits are based both on metal migration considerations, as discussed above, and on self-heating due to power dissipation. The ultimate reliability of the RFIC’s transistors is a complicated function of temperature, time, and current. Most foundries perform extensive life tests of their IC transistors to insure that they will meet their customers’ needs in this regard. It is very important for the designer to become familiar with the latest reliability tests published by the chosen foundry.

4.5

CAD Layout Tools A CAD layout system is an absolute necessity for RFIC design layout. Many designers do their own layout, while other designers rely on the services of companies with in-house departments that specialize in producing high-quality IC layouts. Whether you do the layout yourself or use a service is largely a choice determined by how your organization does business. Both approaches can be made to work. If you do the work yourself, it will be necessary for you to obtain the proper design tools for this purpose. While layouts can be produced on any CAD software that allows for multiple overlapping layers (such as AutoCAD®), it is more preferable to use a tool set specifically developed for IC layout. Excellent, but very expensive, layout tool packages are available from Cadence Design and Mentor Graphics. A medium-priced layout tool is available from IC Editors. The IC Editors layout tool set was used to produce all of the RFIC layout shown in this book. I have personally used the IC Editors tools for several years with excellent results. Generally speaking, once a designer has experience with one set of IC layout tools, it is relatively easy to “come up to speed” on another tool. This is because most of the layout functions used in IC layout are common to all tools, and all it takes to translate to another tool set is simply learning how to use these functions in a new environment.

References [1] [2] [3] [4] [5]

Matthias, M., Introduction to Modeling HBTs, Norwood, MA: Artech House, 2006. Liu, W., Fundamentals of III–V Devices, HBTs, MESFETS, HFETS/HEMTs, New York: John Wiley and Sons, 1999. Sweet, A., MIC and MMIC Amplifier and Oscillator Circuit Design, Norwood, MA: Artech House, 1990. Ghandi, S., VLSI Fabrication Principles, Silicon and Gallium Arsenide, New York: John Wiley and Sons, 1983. Edwards, T., Foundations for Microstrip Circuit Design, New York: John Wiley and Sons, 1983.

CHAPTER 5

SiGe HBT Fabrication Technology 5.1

SiGe HBT Transistor Structures Unlike GaAs HBT devices that represented a radical departure from the traditional design of GaAs MESFET RF/microwave transistor devices, SiGe HBT devices have evolved as the next logical step in the development of silicon BJT devices and BiCMOS fabrication [1]. The pure silicon BJT devices of the late 1980s were limited to a Ft performance level of less than 40 GHz without any noticeable improvement as a function of time [2]. Ft represents the frequency at which the device’s current gain has fallen to unity. One problem contributing to this lagging performance was related to how the base layer was formed. In those days, BJT base layers were fabricated by an ion implantation process [3] that introduced a very thin layer of boron doping to establish the boundaries of the base layer. The fabrication of a thinner base layer was needed to improve the device’s Ft significantly. The problem with this approach was related to how the layers were heat-treated during the annealing process (activating the boron acceptor sites) after the implantation of the base layer. Unfortunately, every attempt to maintain a very thin boron doping profile (i.e., a very thin base layer) during ion implantation was countered by a diffusion of the boron atoms during the annealing heat-treating process [4], effectively broadening the base layer and reducing Ft. Any attempt to raise the performance of the device (i.e., increase Ft) was self-defeating due to high-temperature wafer processing. A new paradigm for the design and fabrication of Si BJT devices was needed to achieve significant improvement in performance. The new paradigm for Si BJT device design and fabrication came at IBM’s T. J. Watson Research Center in the mid-1980s [5]. Until this point, all BJT fabrication had involved process steps that often reached over 1,000°C. It is these high temperatures that cause boron diffusion, which broadens the base layer, lowering RF performance. Also, high-temperature fabrication can significantly impact the purity of the silicon by introducing dislocations and other electrically active impurities. Device designers reasoned that to achieve the twin goals of a thinner base layer (to raise Ft) and higher-purity silicon, an inherently lower-temperature process would be needed. But what were the alternatives? Since the 1960s, ion implantation had been the tried-and-true approach to fabricating high-performance RF BJTs. The answer came in two separate pieces to the puzzle. The first major change was to replace the ion-implanted base-fabrication process with a low-temperature epitaxial base process. The second major change called for the introduction of a small amount of SiGe into the epitaxial base. This SiGe-Si alloy base had its own special properties that led to spectacular improvements in performance.

71

72

SiGe HBT Fabrication Technology

It was low-temperature epitaxy that really made the ultimate improvements possible. A process called ultrahigh vacuum chemical vapor deposition (UHV/CVD) [6] was developed at IBM for this part of the device-fabrication process. Workers at IBM found that wafers fabricated by UHV/CVD epitaxy could be processed at temperatures below 500ºC and still reach a purity exceeding that of wafers that had been processed traditionally at temperatures exceeding 1,000°C. When treated with a hydrofluoric acid (HF) solution, these wafers proved to be highly hydrophobic (i.e., would not wet). This condition was understood to mean that the wafer had acquired hydrogen-terminated silicon bonds across its surface [7]. This intrinsic dewetting behavior made wafers thus treated thirteen orders of magnitude less reactive with the air. It is this reluctance to react with air that gives UHV/CVD epitaxial wafers their ability to maintain high purity in spite of their ultimate processing at temperatures less than 500ºC. By achieving this low-temperature epitaxial base process, extremely thin, high-purity base layers became possible [8]. We return now to the reasons for introducing a SiGe-Si alloy into the device’s base layer. The introduction of a SiGe-Si alloy into the base layer produces heterojunctions at both the emitter-base junction and the collector-base junction, unlike GaAs/InGaP HBT devices, which have a single heterojunction at their emitter-base junction; resulting from their InGaP emitters. In the case of the dual heterojunction SiGe HBTs, the valance-to-conduction band-gap energy is significantly reduced by the introduction of as little as 4 percent SiGe into the base layer. Since the band-gap energy in the base layer is reduced, the potential barrier encountered by electrons moving across the emitter-base junction is lowered; therefore, for a given base-hole current flowing into the emitter, the electron current flowing from the emitter through the base (and into the collector) is substantially increased by the presence of SiGe in the base layer. This increase in electron flow translates into higher collector current, which means that collector current is increased by the presence of SiGe in the base with no increase in the base current. The net effect is to directly increase the transistor’s current gain, . Both hole and electron mobilities are increased by the addition of SiGe to the base layer. In addition to improvements in and mobility, Ft and Fmax (the frequency at which the transistor’s power gain becomes unity) are each increased by the presence of SiGe in the base. Also, the device’s Early voltage is increased, and its output conductance is decreased. Both changes represent significant performance improvements. Since is largely determined by the base’s SiGe content, it is possible to boron-dope the base heavily in order to lower the base resistance without affecting . This technique further raises both Ft and Fmax. Figure 5.1 shows the energy band structure of a pure Si BJT overlaid with that of a SiGe HBT. Best device performance is achieved when the germanium (Ge) concentration in the base is graded toward the collector-base junction. Figure 5.2 shows the profile of a typical SiGe HBT device, indicating the shape of both the doping profile and the epitaxial SiGe concentration. Figure 5.3 gives a Gummel plot (a log-log plot of base current and collector current versus base-to-emitter voltage) for a SiGe transistor showing dramatically how the transistor’s full is realized at Vbe values in the range of 0.70V to 0.80V. This low value of Vbe is achieved because of the relatively low band-gap energy of Si and SiGe compared to the high band-gap energy of GaAs (which leads to a Vbe of 1.4V to 1.5V in similar GaAs HBT devices). A plot of Ft versus collector current (for an emitter size

5.1 SiGe HBT Transistor Structures

73

Figure 5.1 An energy band diagram within an NPN transistor showing how the introduction of a graded germanium profile within the base region causes the conduction band energy to decrease between the emitter-to-base junction and the base-to-collector junction. This sloping conduction band energy greatly enhances the emitter electron injection efficiency of a SiGe HBT relative to that of a pure silicon BJT.

Figure 5.2 A diagram of typical doping type and concentration (and percentage of graded germanium within the base region) for an NPN SiGe transistor.

of 0.5m × 2.5m) is given in Figure 5.4 [9]. Excellent Ft is available over a wide range of collector currents. Ft reaches its maximum value at a collector current of 1.0 mA and decreases for higher collector currents. This decrease of Ft for higher collector currents is called the Kirk effect [10] and is related to the shifting of the electric fields within the transistor’s junctions under high-current conditions. The user of the device has the option of obtaining the highest frequency and gain capability of the device when operating it at 1.0 mA collector current, or the user may accept a slightly lower maximum frequency and gain at a given frequency by reducing the collector current (by as much as a factor of five) in order to reduce dc power. A major issue in the fabrication of epitaxial SiGe base layers is associated with the stability of thin SiGe films that are grown onto a pure silicon crystal. Both sili-

74

SiGe HBT Fabrication Technology

Figure 5.3 A Gummel plot comparing the collector and base currents of a standard silicon BJT with that of a SiGe HBT. This diagram indicates the presence of significantly higher beta with the SiGe HBT device relative to a standard silicon BJT.

Figure 5.4 A plot of Ft and Fmax of a SiGe HBT as a function of current density, demonstrating the Kirk effect as maximum performance is reached at some critical current density.

con and germanium crystals have a diamond crystal lattice structure. However, instability in the SiGe layer may result because a lattice constant mismatch of about four percent exists between silicon and germanium at room temperature. Pure silicon has a lattice constant of 5.43 Angstroms, while pure germanium has a lattice constant of 5.66 Angstroms [11]. The question is, does the resulting SiGe film assume the lattice constant of the pure silicon crystal (upon which it is grown), or does it revert to its natural lattice constant, which is midway between 5.43 Angstroms and 5.66 Angstroms (depending upon the relative germanium concentration)? The answer is that as long as the SiGe film is quite thin, the film retains the lattice constant of pure silicon up to a certain critical thickness, at which point instability begins. A natural strain energy is built into such a film as a natural result of this lattice constant mismatch. Such films are called “pseudomorphic,” a term derived from the Latin words meaning “false form.” Pseudomorphic films, under stress, assume the lattice constant of the substrate host. However, once a critical film thick-

5.1 SiGe HBT Transistor Structures

75

ness has been reached, the SiGe film can no longer conform to the lattice constant of silicon and must “relax” to its natural value, causing crystal defects, called dislocations, to form at the Si-SiGe interface. Such defects act as impurities that limit the usefulness of the base film as a part of the transistor as a whole. Therefore, it is of paramount importance that the epitaxial base layer thickness not exceed the critical thickness for stability. The critical thickness for maintaining stability depends on both the germanium concentration and on the “grading” of the germanium concentration within the base film. In very rough terms, to remain stable, the SiGe base film must have a thickness that remains less than about 100 nm for an average germanium concentration between 5 and 10 percent. It is possible to increase the stable thickness of the SiGe base layer by the epitaxial growth of a pure silicon cap on top of the SiGe base film. However, since device performance (i.e., Ft) is enhanced by a thinner base, every effort is made during fabrication to keep the base as thin as possible for both stability and performance reasons. Figure 5.5 shows how the critical film thickness for stability varies with both germanium concentration and silicon cap thickness. By fully exploiting the techniques described above, it has been possible to increase the Ft of a BJT device from under 40 GHz in the late 1980s to more than 200 GHz today [12]. These amazing improvements are directly attributable to the use of low-temperature UHV/CVD epitaxial SiGe base films. These epitaxial films may be grown at any point in the fabrication process and need not be associated with pre-photolithographically processed wafers only, as is the case with GaAs/InGaP HBT technology, where HBT device isolation is often achieved by etching away all of the initial epitaxial film, except at the locations of a device “mesa.” Next, let us turn our attention to the structure of an NPN HBT device. The cross section of a latest-generation SiGe HBT device structure is shown in Figure 5.6. It should be noted that today almost no stand-alone SiGe fabrication facilities exist. All foundries offering a SiGe process make use of a BiCMOS process that uses the SiGe HBT devices as the “Bi” part of the fabrication process by integrating them into an existing CMOS “backbone” process. This BiCMOS approach has the

Figure 5.5 Maximum stable SiGe base thickness as a function of germanium concentration with a silicon cap thickness as a parameter.

76

SiGe HBT Fabrication Technology

Figure 5.6

The cross section of a high-performance, raised, extrinsic-base SiGe HBT.

advantage to the designer of offering a full range of CMOS components that can be used for digital control and low-frequency analog circuits, while the SiGe devices are used for the high-speed/high-frequency portions of the RFIC’s system. The SiGe bipolar devices may be introduced into the otherwise CMOS process in one of two ways. The first approach is called “base during gate” (BDG), referring to the ability of this process to use a common process step to fabricate both CMOS gates and HBT bases simultaneously. The second approach is called “base after gate” (BAG), referring to the ability of this process to fabricate the CMOS gates first, and then, as a separate process step, to fabricate the SiGe HBT base layer. The BAG technique has the advantage that since the HBT base fabrication comes after the CMOS gate fabrication, the base epitaxial films do not experience the high-temperature portions of the CMOS fabrication process. Therefore, the base’s boron doping experiences fewer diffusion effects that could broaden the base’s width, lowering Ft. For this reason, the BAG technique has become increasingly popular in the latest generation of SiGe devices as a way of increasing device speeds. Areas of critical importance in the design of the HBT device are the necessity for device-to-device isolation structures (since mesas are not used in a BiCMOS process) and finding ways to minimize the effects on the SiGe base epitaxial layer resulting from ion implantation of the extrinsic base and its electrical parasitic effects. In terms of the base structure, best results have been obtained [13] using a raised extrinsic base. This technique shields the epitaxial intrinsic base film from crystal damage caused by implantation of the extrinsic base. Another useful technique for

5.1 SiGe HBT Transistor Structures

77

minimizing the depth of the base layer is the introduction of some carbon doping into the base layer (along with the germanium and boron). These carbon atoms have the ability to suppress out-diffusion of the boron doping atoms within the base during fabrication, with the net effect of keeping the width of the base film razor thin. Device-to-device isolation is provided by an array of shallow and deep polysilicon-filled “trenches” that act as electromagnetic shields around the HBT device. The trenches must be deep enough to completely surround the device’s subcollector down to the conductive substrate, or device-to-device coupling could occur via the subcollectors. As it is, the potential of coupling through the conductive silicon substrate is always a possibility that must be dealt with. Silicide contacts are grown on the emitter, base, and collector regions of the device in order to facilitate low-contact-resistance interconnects to the rest of the circuit. The emitter itself consists of an in situ doped polysilicon structure of a type that has achieved Ft’s greater than 200 GHz [14]. These extremely high-frequency devices have found application in a wide variety of microwave, millimeter-wave, and optical applications. A useful expression for the Ft of a SiGe HBT device is based on diffusion capacitance charging is given as [3] 1/2 Ft = (kT/qIe) (Ceb + Ccb) + RcCcb +

b

+

c

(5.1)

where k T q Ie Ccb Ceb Rc b c

is Boltzman’s constant (1.38E–23 J/K). is the temperature in degrees kelvin. is the charge of an electron. is the emitter current. is the collector-base diffusion capacitance. is the emitter-base diffusion capacitance. is the collector resistance. is the base transit time. is the collector space charge transit time.

An expression for Fmax is given as follows: Fmax = Ft / 8πR bb C cb

(5.2)

where Rbb is the parasitic base resistance. Another important issue in many applications (such as power amplifiers) is breakdown voltage. From an applications viewpoint, the most important breakdown voltage is BVceo. BVceo is the breakdown voltage from collector-to-emitter with zero base current. This breakdown voltage determines the maximum useful

78

SiGe HBT Fabrication Technology

range of collector-to-emitter voltages for a given application. Power amplifiers are a good example of applications where this breakdown voltage is of critical importance. The cause of this breakdown voltage is a phenomenon called avalanche multiplication [15]. During avalanche multiplication, a process called impact ionization occurs when carriers are accelerated to sufficiently high energies by the electric field such that, upon impact with a lattice site, these carriers become capable of elevating an electron from the material’s valence band to its conduction band. Such an impact can set off a chain reaction whereby the newly generated free electrons and holes themselves acquire enough energy from the electric field to generate more electrons and holes. This process creates a chain reaction (similar to the chain reaction set up during nuclear fission). Under these conditions, device current becomes very high and threatens to destroy the device. Avalanche multiplication is caused by the peak electric field within these devices. In devices with very thin base layers, the peak electric field can become high, especially if the doping level is high in the collector region. Therefore, the combination of very thin layers and high doping can add up to very low values of BVceo, which can be in the range of 1.5V to 3.0V with the highest Ft devices. There is a fundamental device limitation relationship between a device’s Ft and its breakdown voltage called the Johnson power limit [16]. The simplest statement of the Johnson limit is (BVceo) Ft = Emax Vs/2

(5.3)

where BVceo is the device’s collector-to-emitter breakdown voltage. Ft

is the frequency at unity current gain.

Emax is the maximum electric field within the device. Vs

is the maximum carrier drift velocity.

For SiGe devices, the value of the Johnson limit is approximately 200 GHz-V. This limit implies that for a device with an Ft of 50 GHz, the value of BVceo is 4V, a device with an Ft of 100 GHz would have a BVceo of 2V, and a device with an Ft of 200 GHz would have a BVceo of 1V. The Johnson limit strongly implies that an absolute limit exists on the power-generating capability of a SiGe device (and any other type of device) that is strongly frequency dependant. The Johnson limit describes a fundamental device trade-off between breakdown voltage (related to power-generating capability) and Ft (related to maximum frequency of operation). A third element in the trade-off is gain, which for a given frequency increases with increasing Ft, which in turn decreases BVceo. Therefore, a three-way trade-off exists between RF power-generation capability, maximum usable frequency, and gain at a given frequency. For a given device design, the maximum usable frequency and gain can be raised (by reducing the width of the base layer for instance), but only at the expense of breakdown voltage and power-generation capability for a given overall device size [17].

5.2 Transistor Device Models

5.2

79

Transistor Device Models Like all bipolar transistors, the SiGe HBT was originally modeled using Gummel Poon SPICE models (SPG) of the same kind that are used with GaAs/InGaP HBT devices. These models were found to be deficient in several areas, including Early voltage modeling, output conductance modeling, avalanche multiplication (breakdown voltage), thermal self-heating, and transit-time modeling. The later VBIC models were successfully applied to SiGe HBT, with significant improvements resulting in all of the areas where the SPG models are deficient. Today, most SiGe foundry design kits include HBT models that effectively integrate the SPG and VBIC models. The net result is a scalable large-signal device model that very effectively simulates all of the dc, small-signal, and large-signal performance characteristics of the SiGe HBT device. Two additional bipolar models (HiCUM and MEXSTRAM) are under evaluation at IBM and other foundries in order to increase model accuracy relative to what is available right now with the VBIC models. A generic SPG SiGe model is given in Figures 5.7(a–c). Device S-parameters derived from the SPG model are shown in Figure 5.8. These models can be used directly in the Agilent ADS simulation tool and other similar tools. The model may also be used with the Cadence tool set that integrates the schematic capture, simulation, and layout functions. Since all SiGe foundry processes are BiCMOS, it is important that the designer’s choice of CAD tool set be capable of working easily with all of the foundry’s CMOS models in addition to the bipolar models. These CMOS devices come along as freebies, and most, if not all, designers will want to take full advantage of the design flexibility and capability these CMOS devices offer. The Cadence tools have become increasingly popular for designing SiGe circuits because of their ability to integrate the functions of simulation and layout when

Figure 5.7(a) An ADS circuit schematic diagram for simulating the IV curves of a generic Gummel Poon model for a unit cell SiGe NPN HBT.

80

SiGe HBT Fabrication Technology

Figure 5.7(b) cell.

Generic, large-signal, scalable, Gummel Poon device model for a SiGe HBT unit

Figure 5.7(c) model.

Simulated IV curves for the generic unit cell SiGe HBT using the Gummel Poon

using a large number of highly specialized CMOS models and passive device models in addition to the HBT device models. The complex BiCMOS nature of all SiGe foundry processes makes the use of a highly integrated CAD tool set, such as Cadence, a necessity. The Cadence Spectra RF® simulation tool is based on a periodic steady state time domain simulator. In this regard, a third-party harmonicbalance-based simulation tool (Golden Gate®) is available from Xpedion Design,

5.3 Passive Device Structures and Models

Figure 5.8

81

Simulated small-signal S-parameters using the generic SiGe unit cell Gummel Poon model.

Inc., an independent company (now part of Agilent, Inc.) whose simulation tool can be integrated into the Cadence tool set. The Golden Gate harmonic-balance simulator works directly with the Cadence tool set, giving the designer a harmonic-balance simulation capability, rather than the periodic steady state time domain simulation that normally is available with the Cadence tools. Golden Gate also offers a full set of transmission line elements that are very useful for modeling parasitic effects at high frequencies. The use of a harmonic-balance simulator has certain advantages in RF applications. In addition to simulation speed, harmonic-balance techniques yield more robust convergence and greater accuracy at high signal levels, which are significant advantages in power amplifier and modulator design.

5.3

Passive Device Structures and Models It is in the area of passive devices that SiGe and GaAs/InGaP technologies differ most profoundly. This technology difference is based on three areas of uniqueness. The first concerns the nature of substrates, the second concerns the number and types of interconnect metals, and the third has to do with the many unique passive device structures that come along with SiGe’s CMOS backbone process. Substrate characteristics in the case of the GaAs/InGaP process are straightforward and easy to work with. After patterning and photolithography fabrication, the individual HBT devices in those regions of the wafer where epitaxial material remains are etched away to expose the underlying semi-insulating GaAs substrate. This underlying substrate is an almost perfect medium for patterning and fabricating gold metalized microstrip lines. The substrate’s resistivity is similar to that of ceramic or glass, which means the dielectric loss of any microstrip line making use of this substrate material is very low—almost zero loss. The GaAs substrate’s dielectric constant is 12.5. Therefore, even at very high frequencies, all microstrip lines making use of this substrate are essentially lossless (except for the metal loss in the topside gold traces). These highly ideal IC microstrip lines make excellent, high-quality, low-loss, low-parasitic interconnects at high frequencies. In fact, the

82

SiGe HBT Fabrication Technology

electrical behavior of the GaAs/InGaP interconnect lines can be very accurately modeled by making use of the various microstrip transmission line elements in ADS® and similar simulators (see Chapter 4). From the viewpoint of modeling such a circuit, the situation is no different from modeling a metalized ceramic substrate or an FR4 PCB. Microstrip elements determine the reactive portion of the interconnection’s behavior. Even cross-coupling between various parts of a circuit can be accurately modeled by using coupled microstrip transmission line simulator models. (See Chapter 4 for details of the modeling process with GaAs/InGaP technology.) Since their line loss is very low, the net effect of the microstrip interconnects is to introduce reactive elements between the circuit nodes being connected. These reactive elements must be included in any matching structures that are designed to match the devices being interconnected. Especially at high frequencies, it becomes very important (and straightforward in application) to include the metal interconnect elements within the total circuit model as some form of ideal microstrip transmission line. When contrasting the nature of a GaAs substrate with a silicon substrate as is encountered in SiGe technology, the following conclusions may be drawn: In silicon technology there is no equivalent to the semi-insulating substrate that is available with GaAs technology. Most commonly, SiGe wafers use an underlying P+ substrate. Since there is doping within the substrate, there will always be some dielectric loss associated with any passive device fabricated on this substrate. For example, resistors fabricated on these substrates will have some backside coupling to the substrate through the parasitic parallel plate capacitance to the substrate. This coupling will be inherently lossy due to the conductive nature of the P+ substrate. Therefore, unlike corresponding resistors in GaAs technology, resistors in SiGe technology will always experience some amount of frequency-dependent loss associated with their capacitive coupling to the lossy substrate. It is the same situation with capacitors of all kinds. The bottom plate of the capacitor will have a parasitic capacitor that couples it to the lossy substrate. This substrate coupling will introduce lossy elements into the capacitor’s equivalent circuit. The same situation exists with spiral inductors, where the issue can be particularly profound owing to the size of inductors compared to resistors and capacitors. Diodes (including varactor diodes) and interconnecting metal lines (including microstrip transmission lines) suffer from the same situation. The backside metallization is coupled (via the equivalent circuit capacitors) to the lossy substrate, introducing lossy elements into the device’s overall model. The equivalent circuit of a SiGe technology resistor is shown in Figure 5.9, and the equivalent circuit of a SiGe technology capacitor is shown in Figure 5.10. The equivalent circuit of a SiGe technology inductor is shown in Figure 5.11. Models contained in a foundry design kit will always account for substrate effects. Therefore, it is critical to use only these models during the design process. The P+ substrate introduces some additional problems into the circuit model. First, because it is somewhat conductive, all circuit elements are connected (or coupled via capacitance) to each other. This coupling can introduce a highly objectionable loss of isolation between certain parts of the circuit. For example, low levels of cross-coupled LO’s signal arriving at a mixer’s input can be highly objectionable in certain applications. To isolate one region of the circuit from another may require the introduction of conductive trenches and guard rings into the design in order to

5.3 Passive Device Structures and Models

Figure 5.9

Figure 5.10

83

Simulator model for a resistor in a SiGe BiCMOS process.

Simulator model for a capacitor in a SiGe BiCMOS process.

counter the conductive substrate’s tendency to couple all parts of the circuit, one to another. In addition to the ability to introduce signals into circuit nodes where they don’t belong, there is a second negative side to this coupling issue, which is the ability of a conductive substrate to couple noise from digital portions of the circuit (i.e., CMOS control circuits) into the RF/analog portions of the circuit. Such noise coupling can cause some potentially very troublesome noise modulations. In many cases, especially at high frequencies, standard circuit simulation tools are unable to simulate these substrate-coupling effects accurately. However, substrate effects can often cause serious problems, making additional design iterations necessary at significant cost and schedule slippage. Therefore, it may become necessary (and time and money will be well spent) to model the substrate effects using three-dimensional electromagnetic simulators such as those available from Sonnet Software, Inc. Electromagnetic simulations for a general set of metal and dielectric conditions are possible but require a lot of effort. However, if substrate effects are to be simulated accurately, this approach must at least be considered and probably followed since

84

SiGe HBT Fabrication Technology

Figure 5.11

Simulator model for a spiral inductor in a SiGe BiCMOS process.

the circuit element simulation tools (such as ADS® and CADENCE®) are not capable of handling the required degree of geometric uniqueness. This is especially true at high frequencies, where coupling effects become much stronger than in the 1–3 GHz range of most wireless applications. However, it is at these very high frequencies that SiGe HBT devices hold their greatest promise because of extremely high Ft. SiGe technology has the ability to fabricate a large number of metal layers (as many as six), some of them quite thick. However, SiGe technology makes use of an aluminum metal system (there is a recent trend toward the use of copper metal for some layers, but this change is still in the early stages). Aluminum metal and even aluminum metal plus copper do not possess the same low resistivity as the gold metal system used in GaAs technology. Table 5.1 lists the typical metal layer options along with their resistivity in milliohms per square. Since thick metals are often used to fabricate spiral inductors, the approximate Q of a 1 nH inductor fabricated from a given metal layer is also listed in Table 5.1. In some cases these metal layers can be “stacked” on top of each other to increase the Q of the resulting structure. However, even with thick metal layers, inductor Q’s may be limited by the effect of the lossy substrate. Some foundries offer metal ground layers (Faraday shields) between the inductor and the lossy substrate. These structures have the ability to increase Q, but they also add to the designer’s problems in terms of scaling the inductor’s size. Because the foundry typically models only a few different sizes of inductors, the designer is placed in the uncomfortable

Table 5.1

Typical Metal Layer Parameters for a SiGe BiCMOS Process

Metal

Rs in milliohms

Inductor Q at 4 GHz

2 um Al 4 um Al 4 um Al/3 um Cu

14 7 3

7 18 28

5.3 Passive Device Structures and Models

85

position of having only a limited range of inductor sizes with associated simulator models. If the designer wishes to use an inductor whose value lies outside of the modeled range, there is uncertainty about the model’s applicability. The same situation exists for intermediate values of inductors; the exact model may not exist, forcing the designer to guess the intermediate model values. For this reason, designers often feel their range of inductor-value options is significantly limited in comparison to GaAs technology, where just about any size inductor may be accurately modeled using standard simulator spiral inductor models. Quite often, the solution to this problem is to fall back on electromagnetic simulations to provide an accurate model for an inductor whose size or shape does not fit with the standard foundry inductor models. Even with careful modeling of a nonstandard inductor, the designer may find it is a hard sell to convince the foundry to include such nonstandard inductors in their final design. Because SiGe technology is built around a CMOS fabrication backbone, quite a number of CMOS passive devices become available to the designer as options that can be used whenever it makes sense for a given design. Table 5.2 lists the resistor options a SiGe designer can call upon as needed. Table 5.2 includes each resistor’s sheet resistance, its TCR, its parasitic capacitance, and its maximum current. Likewise, a family of capacitor options is also available. These capacitors are listed in Table 5.3, along with the capacitance per unit area, tolerance, and TCC for each option. Some foundries are now offering advanced capacitor options, such as vertical plate capacitors with high breakdown voltages. Families of varactor diodes are also available with SiGe technology. These varactor diodes are used as tuning elements for the VCO circuits used in phase-locked loops. Some varactor diodes have more available tuning range than others. The three varactor diode options available with most SiGe fabrication processes are listed in Table 5.4, with their approximate available tuning ratio. It is important for the designer to check carefully the degree of tuning linearity available with each varactor option. The required varactor tuning linearity is very application dependent. Most foundries provide excellent models for their varactor diode

Table 5.2

Typical Resistor Options with Electrical Parameters for a SiGe BiCMOS Process

Resistor

Resistance (Ohm/sq.)

TCR (ppm/c)

Para cap (fF/sq. um)

Max I (mA/um)

P+ polysilicon P polysilicon N+ diffusion N subcollector TaN

270 1,600 72 8 142

21 –1,105 1,751 1,460 –728

0.11 0.09 1 0.12 0.03

0.6 0.1 1 1 0.5

Table 5.3

Typical Capacitor Options with Electrical Parameters for a SiGe BiCMOS Process

Capacitor

C0 (fF/sq. m)

Tolerance (%)

TCC (ppm/C)

MOSCAP Poly-poly MIM

1.5 1.6 0.7

10 25 15

48 21 –57

86

SiGe HBT Fabrication Technology Table 5.4

Varactor Diode Options for a Typical SiGe BiCMOS Process

Varactor Type

Tuning Ratio

Collector-base Hyperabrupt MOS accumulation

1.3:1 3.4:1 2.5:1

options. However, in general, there is a lot of variability from foundry to foundry in terms of scalable models and substrate options. Some foundries supply the designer a full set of scalable models, including spiral inductors. Others do not. Also, substrate options such as ground shield and deep trenches are available from some foundries but not from others.

5.4

Design Rules The design rules associated with a SiGe technology process are, by their very nature, extremely complex. It is more than is reasonable to expect any designer to keep track manually of the whole interwoven set of geometric rules that determine the possible relationships (and their violations) within and among all of the metal and dielectric layers of a SiGe BiCMOS process. Thus, it is necessary for designers to have available to them a set of CAD tools that internalize and automate the complete set of design rules. This implies that an ideal tool set is one that can at any time perform a DRC on the whole circuit or any part of the circuit. It is also important that the tool set make available to the designer all foundry device models with computationally easy ways to modify and scale these models. In most cases, the foundry will provide the designer with a process design kit (PDK) that installs inside the software tools all of the necessary models for characterizing the foundry’s available devices, including both active devices, such as transistors, and passive devices, such as resistors, capacitors, inductors, and varactor diodes.

5.5

CAD Layout Once the lumped-element circuit design has been completed, it is necessary to turn the new design into a layout. With SiGe technology, this can be a difficult and exacting process. A major concern is the need for component-to-component isolation within the circuit. Some techniques for providing this isolation include using guard rings and deep and shallow conductive trenches around specific devices. It can also be helpful to provide an RF ground layer under some or all of the RF circuit in order to reduce digital noise and increase the isolation of stray device-to-device paths. Figure 5.12 shows a diagram of the various techniques for increasing isolations within a design. None of these techniques is completely foolproof, and all should be regarded as suggestions rather that requirements [18, 19]. Sometimes electromagnetic simulations can raise confidence that a given isolation technique is truly as effective as the designer hopes. Without this kind of confirmation, the designer is forced to go back through wafer fabrication yet another time to confirm experimentally that a given set of isolation techniques is truly effective. The designer’s best defense against hav-

5.5 CAD Layout

87

Figure 5.12 Isolation device structures for reducing substrate noise and cross talk substrate coupling with SiGe BiCMOS device technology.

ing to make an excessive number of prototype wafer-fabrication iterations is to have an excellent CAD tool set that, to the highest degree possible, automates the design process, freeing the designer to concentrate on thinking through concepts and evaluating circuit options. Additionally, the designer must have access to a threedimensional electromagnetic simulator with the ability to provide insight into the effectiveness of a given structure relative to combating stray isolation and substrate noise problems. Generally speaking, the CAD tools pay for themselves in terms of reducing the number of prototype “spins” required in order to ensure that a new design meets all of its specifications. This goal is not unreasonable, considering that prototype wafer-fabrication costs can run in the range of $70,000 to $100,000, depending on process speed (i.e., Ft). If you are able to reduce the number of prototype spins by two, the potential savings are as much as $200,000, not to mention a significantly accelerated time to market. The bottom line is that designing SiGe RFICs is an CAD-intensive enterprise. There seems to be no way of avoiding a large tool budget and high prototype engineering costs.

References [1]

Groves, R., et al., “High Q Inductors in SiGe BiCMOS Process Utilizing a Thick Metal Add-on Module,” Proc. 1999 BCTM, 1999. [2] Rieh, J., et al., “SiGe HBTs with Cut-off Frequency of 350 GHz,” International Electron Device Meeting, December 2002, pp. 771–774. [3] Singh, R., Harame, D., and Oprysko, M., Silicon Germanium Technology, Modeling, and Design, New York: IEEE Press and Wiley Interscience, 2004. [4] Ashok, K., et al., Polysilicon Emitter Bipolar Transistors, New York: IEEE Press, 1989. [5] Meyerson, B., “Low Temperature Silicon Epitaxy for Ultra-High Vacuum/Chemical Vapor Deposition,” Applied Physics Letters, Vol. 48, 1986, pp. 797–799. [6] Patton, G., et al., “Graded SiGe Base Poly-Emitter Heterojunction Bipolar Transistors,” IEEE Electron Device Letters, Vol. 10, No. 12, 1989, pp. 534–536.

88

SiGe HBT Fabrication Technology [7] Meyerson, B., “Bistable Conditions for Low Temperature Silicon Epitaxy,” Applied Physics Letters, Vol. 57, 1990, pp. 1034–1036. [8] Stiffler, S., et al., “The Thermal Stability of SiGe Films Deposited by Ultra-High Vacuum Chemical Vapor Deposition,” J. Applied Physics, No. 70, 1991, p. 1416. [9] Patton, G., et al., “Graded SiGe Base Poly-Emitter Heterojunction Bipolar Transistors,” IEEE Electron Device Letters, Vol. 10, No. 12, 1989, pp. 534–536. [10] King, C., et al., “Bandgap and Transport Properties of Si1-xGex by Analysis of Nealy Ideal Si/Si1-xGex/Si Heterojunction Bipolar Transistors,” IEEE Transactions of Electron Devices, Vol. 36, No.10, October 1989, pp. 2093–2104. [11] Patton, G., et al., “Graded SiGe Base Poly-Emitter Heterojunction Bipolar Transistors,” IEEE Electron Device Letters, Vol. 10, No. 12, 1989, pp. 534–536. [12] Koester, S., et al., “High Ft n-MODFETs Fabrication on Si/SiGe Heterostructures Grown by UHV-CVD,” IEEE Electron Device Letters, Vol. 21, No. 3, March 2000. [13] Singh, R., Harame, D., and Oprysko, M., Silicon Germanium Technology, Modeling, and Design, New York: IEEE Press and Wiley Interscience, 2004. [14] Cressler, J. D., and Niu, G., Silicon-Germanium Heterojunction Bipolar Transistors, Norwood, MA: Artech House, 2003. [15] Rickelt, M., et al., “Influence of Impact-Ionization-Induced Instabilities on the Maximum Usable Output Voltage of Si Bipolar Transistors,” IEEE Transactions on Electron Devices, Vol. 48, No. 4, April 2001, pp. 774–783. [16] Johnson, E., “Physical Limitations on Frequency and Power Parameters of Transistors,” RCA Review, Vol. 26, June 1965. [17] Veenstra, H., et al., “Analysis and Design of Bias Circuits Tolerating Output Voltages above BVceo,” IEEE J. Solid State Circuits, Vol. 40, No. 10, October 2005, pp. 2008–2018. [18] Casalta, J., et al., “Substrate Coupling Evaluation in BiCMOS Technology,” IEEE J. Solid State Circuits, Vol. 28, 1997, pp. 598–603. [19] Mayaram, K., “Substrate Noise Coupling Modeling and Applications to RF VCOs,” IEEE SCV SSC Meeting, November 2000.

CHAPTER 6

Passive Circuit Design 6.1

Low-Pass Filters RFICs are capable of fabricating a wide variety of passive RF/microwave circuits. The most important class of passive devices is filters (low pass, high pass, and band pass). However, phase shifters and power splitters (and couplers) are also designed and fabricated successfully on RFICs. This chapter is devoted to the details of passive circuit designs. Armed with this capability, the designer will be in a position to realize a significant portion of a system, on-chip; or perhaps the whole system. We first consider the design of low-pass filters. Figure 6.1 gives the schematic diagram of a single-section low-pass filter (LPF). The inductors are easy to realize in an RFIC by using spiral inductors, and the capacitor is simply an MIM capacitor in an RFIC environment. Of course, all layout parasitic elements must be accounted for to ensure close agreement between simulations and measurements. The basic design equations for a single-section LPF are given below. The design method used here is that of artificial transmission lines [1] of the kind used in distributed- or traveling-wave amplifiers [2]. To obtain higher rejection at high frequencies, it may be necessary to add additional filter sections. This is a straightforward matter of calculating how much rejection at a given frequency is available from a single section, then estimating how many sections will be needed to realize the desired rejection [3]. First, the filter’s characteristic impedance, which should be set to match the impedance of surrounding circuits, is calculated as Z0 =

L/C

(6.1)

Fc = 1/ Z0C

(6.2)

The filter’s cutoff frequency is

Figure 6.1 A schematic diagram of an ideal single-section low-pass filter based on an artificial transmission line structure.

89

90

Passive Circuit Design

The value of the filter’s inductors, L, is L = (Z0)2C

(6.3)

The time delay per section is given as τ=

LC

(6.4)

and the phase shift in degrees is = –360 F0

(6.5)

The approximate frequency where filter roll-off begins is Fh = Fc/2

(6.6)

Of course, this roll-off frequency is only an approximation and must be verified by simulation. Filter phase shift at Fh is about –90° per section, and filter rejection at Fc (i.e., 2 × Fh) is about 10 dB per section. As an example, consider the design of a single-section low-pass filter, assuming that Fh Z0 Fc L

= 3 GHz. = 50Ω. = 2 × 3 = 6 GHz, which means C = 1/ (50)(6 GHz) = 1.06 pF. = (50)2(1.06E–12) = 2.65 nH.

The filter’s time delay is calculated as τ = (2.65E) − 9(106 . E − 12) = 53pS The phase shift per section is calculated to be φ = 360(3 GHz) (53 pS) = –57º A simulator schematic for this LPF in lumped-element (prelayout) form is shown in Figure 6.2. The filter’s simulated performance is shown in Figure 6.3. Notice that the simulated performance closely matches the performance predicted by using (6.1) to (6.6). All that needs to be done to turn this filter into a real design is to convert its inductors into spiral inductors and add the parasitic open-circuited stub associated with the shunt capacitor. Figures 6.4 and 6.5 show a very useful technique for converting a lumped-element inductor into a spiral inductor. A two-stage low-pass filter, including spiral inductors, is shown schematically in Figure 6.6. This filter was designed for an Fh frequency of 3.0 GHz (i.e., Fc = 6 GHz). The simulated performance of this filter is given in Figure 6.7. The simulations come out to be very close to the estimated performance per stage (rejection at Fc = 20 dB, phase shift at Fh =

6.1 Low-Pass Filters

Figure 6.2 quency.

Figure 6.3

91

A schematic diagram for a single-section low-pass filter with a 3 GHz roll-off fre-

The simulated S-parameters of a single-section low-pass filter.

Figure 6.4 A simulator schematic diagram for transforming an ideal inductor into a spiral inductor based on comparing the value of inductive reactance at the frequency (or frequencies) of interest.

–180°), demonstrating that even after conversion to a layout-ready spiral inductor, the estimated performance of a multistage LPF is very similar to the performance calculated from the design equations.

92

Passive Circuit Design

Figure 6.5 A comparison of the simulated reactance of an ideal inductor with that of a physical spiral inductor, making it possible for the spiral inductor to replace the ideal inductor when their reactance is made equal at the frequency (frequencies) of interest.

Figure 6.6 The schematic diagram of a two-section, 3 GHz, roll-off-frequency, low-pass filter with spiral inductors replacing the ideal inductors.

Figure 6.7

The simulated S-parameters of the two-section low-pass filter using spiral inductors.

6.2 High-Pass Filters

6.2

93

High-Pass Filters A schematic diagram of a single-section high-pass filter (HPF) is shown in Figure 6.8. We recognize that this filter is simply the inverted dual of the LPF discussed above. Therefore, the filter parameters calculated with (6.1) to (6.6) may also be applied to the design of its dual high-pass filter with the schematic shown in Figure 6.8. In the case of the high-pass filter, Fh is still the frequency where filter roll-off begins. However, it is at Fh/2 that a single-section HPF achieves 10 dB rejection relative to Fh. The phase shift at Fh with the high-pass filter is +90°, instead of the –90° associated with the equivalent LPF dual. This characteristic makes it possible to design a balun (a single-ended-to-differential conversion device with 180° phase shift) by using an equivalent LPF/HPF pair fed at a common point and designed to operate at Fh (see section 6.7). One stage of a two-stage HPF designed for Fh = 3 GHz is shown schematically in Figure 6.9. This filter can use spiral inductors and is “buildable” in InGaP/GaAs technology by simply including the back plate parasitic element associated with each capacitor. Figure 6.10 shows the simulated performance of this filter. The filter’s insertion loss is under 0.1 dB at Fh, and its rejection at Fh/2 is nearly 30 dB. The total phase shift is 180°. Like the two-stage LPF, the two-stage HPF design has simulated performance very near what is calculated from the design equations multiplied by two.

6.3

Band-Pass Filters There are two ways to construct RF band-pass filters (BPFs). The first is simply to cascade the low-pass and high-pass filter designs discussed above. The pass band of

Figure 6.8 A schematic diagram of an ideal single-section high-pass filter based on an artificial transmission line structure.

Figure 6.9 The schematic diagram of a 3 GHz, roll-off-frequency, two-section high-pass filter with spiral inductors replacing ideal inductors.

94

Passive Circuit Design

Figure 6.10 The simulated S-parameters of a 3 GHz, roll-off-frequency, two-section high-pass filter using spiral inductors.

the resulting filter will be determined by the difference between the Fh of the low-pass filter and the Fh of the high-pass filter. High-end rejection at the 2Fh associated with the low-pass filter will depend upon the number of LPF stages (it will be approximately N × 10 dB, where N is the number of LPF sections). Low-end rejection at Fh/2 associated with the high-pass filter will depend on the number of HPF stages (again, approximately N × 10 dB, where N is the number of HPF sections). This technique is very effective in designing band-pass filters because the filter’s bandwidth and the high-frequency and low-frequency roll-offs are determined independently and are controlled by different design parameters. This is a powerful plus for choosing this kind of BPF topology in RFIC designs. Figure 6.11 shows a schematic diagram of a BPF designed using this technique for combining the two-stage LPFs and HPFs discussed above. The simulated performance of the resulting BPF is shown in Figure 6.12. The high- and low-end filter rejection is almost exactly what was already simulated for the LPF and HPF operating separately, demonstrating how independently these filters behave, even when combined into a BPF cascade. Notice also that the LPF and HPF phase shifts nearly cancel each other out to about 0°. A second technique for designing lumped-element band-pass filters involves the use of multiple parallel LC resonator sections loosely coupled together with small series capacitors. The LC resonator sections may be “stagger-tuned” in order to achieve the desired BPF bandwidth. Of course, increased resonant-frequency separation between the resonators will result in increased pass-band ripple. The trick is to use enough resonators so that the in-band ripple is not too great, while achieving the desired roll-off characteristics. Too many resonators will increase the chip’s area and add insertion loss, while two few resonators will result in excessive band ripple.

6.4 Differential Filters

95

Figure 6.11 The schematic diagram of a two-section low-pass filter cascaded with a two-section high-pass filter forming a band-pass filter. This filter uses spiral inductors throughout.

Figure 6.12 The simulated S-parameters of a two-section high-pass filter cascaded with a two-section low-pass filter to form a band-pass filter. The center frequency of this band-pass filter is 3.0 GHz, with approximately 800 MHz of flat bandwidth.

The schematic diagram for this type of BPF is shown in Figure 6.13, and its simulated performance is given in Figure 6.14. While this type of filter is highly interactive, making it difficult to design, it can yield excellent performance with few parts in a very compact layout.

6.4

Differential Filters Often RFICs use a totally differential topology because components such as Gilbert cell mixers, differential VCOs, and differential amplifiers are naturally suited to a completely differential environment. To remain consistent with this technique, components such as filters must also be designed in a differential format. If all com-

96

Passive Circuit Design

Figure 6.13

Figure 6.14 Simulated S-parameters of a two-section parallel LC resonator band-pass filter. This band-pass filter has a center frequency of 2.2 GHz and a flat bandwidth of 600 MHz.

ponents can be kept strictly differential, the only differential-to-single-ended transformations that need be made can be done off-chip, using surface-mounted baluns. Fortunately, it is not difficult to convert filter designs from single-ended to differential. This requires only that, during the simulations of these filters, the designer provide two center-tapped transformers (whose center taps represent the filter’s virtual ground) and place between them two single-ended filters whose ground reference becomes the virtual grounds, which are determined by the transformer’s center taps. The center taps may be connected to system ground, or they may float; in either case, they determine the virtual ground for the filters. At the transformer’s sec-

6.4 Differential Filters

97

ondary winding, the differential filter is converted back to single-ended input and output if this is needed in simulating a number of cascaded components. Figure 6.15(a) shows two such transformers connected together at their differential secondary windings. Notice that the center of the circuit is at the virtual ground potential. The impedance from each side to ground is exactly 50 ohms, meaning that the total impedance of the secondary is 100 ohms. The correct impedances are achievable by setting both of the transformers’ turn ratios to exactly 1.41. Figure 6.15(b) gives the overall insertion loss of the two back-to-back connected transformers. Once this is done, the secondary-to-secondary connections may be replaced by two 50 ohms, matched, single-ended filters as shown in Figures 6.16(a, b). If the filter has shunt components connected to the virtual ground (capacitors in LPFs and inductors in HPFs), these components may be considered to be in series, and converted into a single capacitor or a single inductor connected between the sides of the differential filter (see Figure 6.17). The simulation of the low-pass differential filter is shown in Figure 6.18. Notice that the differential filter behaves exactly as the single-ended filter did. If the differential filter is intended to be placed in an area of the circuit where the impedance is significantly different than 50 ohms, it may make sense in the initial design of the single-ended filters to start off with the non-50 ohms impedance as a design goal, rather than to try to match the surrounding circuits to the 50 ohms filters.

Figure 6.15(a) The schematic diagram of two back-to-back center-tapped transformers, which are used to facilitate the simulation of a wide variety of differential circuits.

Figure 6.15(b) The simulated insertion loss of the back-to-back transformer pair shown in Figure 6.15(a). The simulated loss is vanishingly small, meaning that this technique for simulating a differential circuit has no inherent loss by itself.

98

Passive Circuit Design

1.06 pF 2.65 nH

2.65 nH

2.65 nH

2.65 nH 1.06 pF

Figure 6.16(a) The schematic diagram of a differential low-pass filter formed by combining two single-ended low-pass filters inside a pair of back-to-back center-tapped transformers.

Figure 6.16(b) The simulated S-parameters of the differential low-pass filter shown in Figure 6.16(a). The S-parameter performance of the differential filter is absolutely identical to that of its equivalent single-ended filter, which is shown in Figure 6.3.

Figure 6.17 The schematic diagram of a differential low-pass filter with series-combined shunt elements at the virtual ground common point.

6.5 Technology and Substrates

Figure 6.18 ments.

6.5

99

The simulated S-parameters of a differential low-pass filter with series-combined shunt ele-

Technology and Substrates InGaP/GaAs technology provides an ideal substrate for passive circuits. In this type of process, the substrate is a true lossless insulator with an approximate thickness of 100µm. Metal traces on this type of substrate will behave as standard (and highly predictable) microstrip transmission lines [4]. However, this is not the case with SiGe BiCMOS technology (see Chapter 5) because the silicon substrates used by this technology are not lossless, and their proximity may affect the behavior of spiral inductors and other metal traces in ways that are not ideal. In the case of SiGe circuits, the designer has several choices in approaching this dilemma. The first choice is simply to rely on the validity (including substrate effects) of the foundry electrical models for resistors, capacitors, and inductors. These foundry models may or may not include metal traces. A second approach is to use one of the BiCMOS process’s metal layers as a ground plane, essentially shielding the traces on the substrate from losses deep in the underlying substrate. The difficulty with this approach is that the effective dielectric thickness may be very thin (less than 5µm), leading to narrow, therefore lossy (based on metal loss), 50 ohm lines. The designer must be prepared to exercise judgment to settle this issue.

6.6

Splitters/Dividers Power splitters and power dividers are important components in most RFICs. Two of the more popular designs are called in-phase splitters (Wilkinsons) and resistive dividers. The Wilkinson in-phase power splitter has approximately 3 dB insertion

100

Passive Circuit Design

loss in each of its two outputs, producing an almost perfect half-power division. As the name implies, the in-phase Wilkinson divider has no differential phase shift between the two outputs. All inputs and outputs are well matched to 50 ohms with a Wilkinson. On the other hand, the resistive power divider uses dissipative resistor components to accomplish power division. This means that power will be lost, and there will be additional attenuation beyond the natural half division of the Wilkinson. Most resistive power dividers have a 6 dB loss between input and each output. Like the Wilkinson, they are well matched to 50 ohms and have zero differential phase shift between the outputs. Figure 6.19 gives the circuit schematic of a basic Wilkinson power splitter using quarter-wavelength microstrip transmission lines. Since these lines may become quite long at low frequencies, it is a good idea to “wrap them up” into spiral inductors, as shown in Figure 6.20. Figure 6.21 gives the simulated performance of

Figure 6.19 The schematic diagram of a Wilkinson power combiner/splitter using quarter-wavelength microstrip lines.

Figure 6.20 inductors.

The schematic diagram of a Wilkinson power combiner/splitter using spiral

6.6 Splitters/Dividers

101

Figure 6.21 The simulated three-port S-parameters of a Wilkinson power combiner/splitter using spiral inductors.

the Wilkinson power splitter using spiral inductors. The performance is very similar to that obtained with quarter-wavelength transmission lines, but the spiral splitter is much smaller in layout. Performance peaks up at the frequency corresponding to the quarter-wavelength frequency associated with the spiral inductors. Figure 6.22 shows the schematic diagram of a resistive power splitter. This is a very simple structure, using three 17 ohm resistors in a “Y” configuration. As seen in Figure 6.23, the resistive splitter offers perfect 6 dB power split with a perfect match and no differential phase shift over a very wide frequency range. Both kinds of power splitters can be “run backwards” as power combiners. The Wilkinson combiner will almost perfectly add the two input powers, whereas the resistive power combiner will suffer a 3 dB loss in total power relative to its inputs because of its dissipative nature.

Figure 6.22

The schematic diagram of a 6 dB resistive power combiner/splitter.

102

Passive Circuit Design

Figure 6.23 The simulated three port S-parameters of a 6 dB resistive power combiner/splitter. The insertion loss in both paths is exactly 6.0 dB. There is no frequency dependence because the circuit contains no reactive elements.

In general, all splitters and combiners will be designed to have a 50 ohm impedances at their inputs and outputs. As such, it makes good sense to interconnect these circuits (and also filters) with metal traces whose characteristic impedance is also 50 ohms. Tables of microstrip design data for various line lengths and widths can be found in several references. Whenever spiral inductors are a part of any circuit element (especially when they are in series with an input or output), it is good practice to use an inductor line width that translates into a 50 ohm characteristic impedance for the metal trace functioning as a micro strip transmission line. By following this suggestion, impedance mismatches between filters/splitters and their interconnecting metal lines can be avoided.

6.7

Phase Shifters and Baluns It is possible to use filter structures to achieve certain kinds of advantageous phase shifts for certain applications. For instance, as we have seen, a LPF provides exactly –90° of phase shift at Fh, whereas its dual HPF provides exactly +90° phase shift at the same frequency. If we combine these two filters into a two-channel structure as shown in Figure 6.24, the outputs will be have 180° of phase shift relative to each other. This is exactly the performance required of a balun (short for “balancedunbalanced”), which is used to translate from single-ended transmission to

6.7 Phase Shifters and Baluns

103

Figure 6.24 The schematic diagram of an HPF/LPF balun (single-ended input and 180º phase shift between its two differential outputs).

differential transmission. Although baluns are often located off-chip, by using the dual LPF/HPF phase shifter, it is possible to achieve balun function in a compact on-chip environment. Figure 6.25 gives the schematic diagram of a 90° phase shifter that makes use of a single-section high-pass filter and a resistive splitter. This circuit can serve the role of an LO quadrature-phase shifter in an I/Q mixer or an I/Q modulator applications (see Chapter 11). In the case of a differential LO line driving a mixer with a differential LO input (such as a Gilbert cell mixer), the block diagram in Figure 6.26 shows how to connect two 90° phase shifters in order to provide 90° of phase shift at the Q mixer. An alternate 90° phase-shifter circuit using a single-section low-pass filter is shown in Figure 6.27. The low-pass, high-pass, and polyphase circuits (shown in Chapter 3) are equally useful for shifting the phase of an LO signal by 90° (over a narrow band of frequencies). If a quadrature phase shift is required over a broad band of frequencies, it is best to use a digital frequency divider circuit to output a half frequency with quadrature outputs. The price paid for this approach is the necessity to design a VCO to operate at two times the desired frequency.

Figure 6.25 The schematic diagram of an HPF 90º phase shifter. This circuit is useful for shifting the phase of an LO signal by 90º in I/Q mixer/modulator applications.

104

Passive Circuit Design

Figure 6.26 The block diagram of a differential I/Q phase-shifting network. This network produces two differential outputs that are 90º apart from each other in order to shift the phase of a differential LO in I/Q mixer/modulator applications.

Figure 6.27

The schematic diagram of an LPF 90º phase shifter.

References [1] [2] [3] [4]

Beyer, J., et al., “MESFET Distributed Amplifier Design Guide Lines,” IEEE Transactions on Microwave Theory and Technique, MTT-32, March 1984. Sweet, A., MIC and MMIC Amplifier and Oscillator Circuit Design, Norwood, MA: Artech House, 1990. Nilsson, J., and Riedel, S., Electric Circuits, Upper Saddle River, NJ: Prentice Hall, 2005. Edwards, T. C., Foundations for Microstrip Circuit Design, New York: John Wiley and Sons, 1983.

CHAPTER 7

Amplifier Design Basics 7.1

Matching Techniques All RF/microwave transistor amplifiers rely on some form of matching to achieve flat gain over a desired frequency range [1]. We mathematically define a conjugate match as Γl = Γ*g, where Γg is the transistor’s reflection coefficient, and Γl is the load’s reflection coefficient. Transistors have a maximum gain that decreases as a function of frequency. Any amplifier is designed to operate from fl to fh, with a theoretical maximum available gain (MAG) at fh and flat gain at all frequencies between fl and fh. Matching for flat gain becomes a matter of providing the best possible match into and out of the transistor at fh (in order to achieve a gain at fh that is as close as possible to MAG) and providing selective mismatch between fl and fh to “throw away” gain at frequencies between fl and fh to provide flat gain, which is gain as close as possible in value to MAG at fh. Selective mismatching compensates for the transistor’s increasing MAG as frequency decreases. Figure 7.1 graphically portrays the gain-compensation process over a band of frequencies from fl to fh. If an amplifier is to operate over a narrow bandwidth, the matching problem becomes a simple matter of achieving a good match at fh. But if a broad bandwidth is needed, the selective mismatch concept must be employed to ensure flat, broad bandwidth gain. Mismatch loss, Mc, is defined as the ratio of the power available from a generator to the power delivered to the load:

Figure 7.1 Amplifier gain equalization with the introduction of a selective mismatch loss, Lm. This equalization process achieves flat gain over a wide bandwidth.

105

106

Amplifier Design Basics

Mc = [1 – ΓlΓg]2/(1 – Γl2) (1 – Γg2)

(7.1)

where Γl is the load’s reflection coefficient. Γg is the generator’s reflection coefficient. Mismatch may be applied at either the transistor’s input or the transistor’s output, or both.

7.2

Gain Compensation The selective mismatch concept can be applied to either the circuit between the generator and the input to the transistor or to the circuit between the transistor’s output and its load. It is common practice, however, to provide a selective mismatch only at the transistor’s input and to provide a conjugate match at the transistor’s output to maximize the transistor’s power transfer to the load. Figure 7.2 shows a Smith chart diagram [2] displaying how the input and the output matching circuits provide a selective mismatch to the transistor’s input (S11) and a conjugate match to the transistor’s output (S22). Notice that the conjugate match is provided only to the transistor’s input at the highest operating frequency, fh. However, the transistor’s output is closely matched to the load over the entire frequency range, fl to fh.

7.3

Fano’s Limit Calculations by Fano [3] have shown there is a bandwidth limit for reactively matched amplifiers. Assuming that the input matching is provided by a high-pass

F2

Zin*

S11

Zout*

F1 S22

F2

F1

Figure 7.2 amplifier.

A Smith chart displaying the selective mismatch process of a wideband transistor

7.4 Stability

107

network and the output matching is provided by a low-pass network, the gain of a transistor amplifier is given by Ga (f) = G0 (f/fh)–k

(7.2)

and the mismatch loss for flat gain from fL to fH is LM(f)=K(f/fH)k where k is the gain reduction factor, which predicts how far below MAG, at the high end, the gain must be to realize flat gain over the bandwidth fl to fh. If the high-pass input matching network is lossless and reciprocal, Fano has shown that πτhp >

∫ (1 / Ω ) ln[1 / Γin]dΩ ∞

2

(7.3)

0

where Ω = f/fh = normalized frequency. hp = 2 fhRinCin. Rin = the transistor’s input resistance. Cin = the transistor’s input capacitance. Γin = input reflection coefficient. Equation (7.3) indicates that Γin cannot be zero over any finite bandwidth. If Γin is sloped with frequency such that it is lower at fh (the high-end frequency) than at fl (the low-end frequency), it can be shown that

∫ (1 / Ω ) ln[1 / (1 − K( f / fh) )]dΩ < 2 πτ 1

2

K

fl

hp

(7.4)

Figure 7.3 shows how much bandwidth is achievable with no high-end gain reduction for various degrees of input-circuit frequency slope. For the output circuit, it can be shown that

∫

1

fl

[ (

ln 1 / 1 − K( f / fh) K

)]dΩ < 2π / τ

lp

(7.5)

where = 2 fhRoutCout. lp Rout = the transistor’s output resistance. Cout = the transistor’s output resistance. Figure 7.4 shows how much bandwidth is achievable with no high-end gain reduction for various degrees of output-circuit frequency slope.

7.4

Stability Any amplifier is unconditionally stable if the source or load impedances necessary to cause instability are outside of the Γ = 1.0 circle (that is, unachievable without

108

Amplifier Design Basics

Figure 7.3 Maximum Fano bandwidth of an amplifier that is limited by its input (high-pass) circuit. No reduction in gain relative to MAG can occur at the high-frequency limit. The most common input-circuit roll-off slope is 6 dB per octave per stage.

Figure 7.4 Maximum Fano bandwidth for an amplifier that is limited by its output (low-pass) circuit. No reduction in gain relative to MAG can occur at the high-frequency limit. The most common input-circuit roll-off slope is 0 dB per octave per stage.

some form of negative resistance). An amplifier is conditionally stable if the impedances that produce instability do not include 50 ohms pure real at either the input or the output ports. A stability factor, k, of an amplifier is defined in terms of the amplifier’s S-parameters as [4] k = (1 – (MAGS11)2 – (MAGS22)2 + D2)/2(MAGS11)(MAGS22)

(7.6)

7.5 Noise Match

109

where S11 and S22 are the amplifier’s complex input and output S-parameters. D = (S11S22 – S12S21) For unconditional stability, k > 1.0. For conditional stability, 0 < k < 1.0. If the designer is to be sure that an amplifier design is unconditionally stable at all frequencies, it is very important to test stability over a very broad range of frequencies, not just the frequencies within the specified bandwidth. Oftentimes, instability problems occur at frequencies far below the intended operating range.

7.5

Noise Match Matching a transistor amplifier for lowest possible noise figure over a band of frequencies requires that a particular impedance be presented to the transistor’s input. The noise-optimized source impedance is called Γopt, which may be obtained from measurements or from the transistors manufacturer’s data sheet. The noise figure of a transistor amplifier with an arbitrary source reflection coefficient, Γ, is given by [5] F = Fmin + 4Rn[Γ – Γopt]2/[1 – (sq MAGΓ)][1 + Γopt]2

(7.7)

where Fmin = the transistor’s minimum noise figure. Rn is the transistor’s noise resistance, normalized to 50Ù. Γ is the source’s reflection coefficient. Γopt is the ideal source reflection coefficient for minimum noise figure.

7.6

Differential Amplifiers Differential amplifiers are of great general value in RFIC design because so many of the current RFIC architectures are built around Gilbert cell mixers, which require a completely differential circuit approach. For this reason, many LO buffer amplifiers and gain block amplifiers that interface directly to Gilbert cell mixers are required to be differential. It is usually very desirable for these amplifiers to have high reverse isolation so that mixing products generated in the Gilbert cell are not transferred back into the rest of the system, where they can cause self-generated spurious responses. An example of a basic differential amplifier topology is shown in Figure 7.5. As shown in Figure 7.5, a differential amplifier circuit makes use of two emitter-coupled transistors, Q1 and Q2, whose dc current is controlled by a “tail” transistor. The tail transistor acts as a source of dc current and, at the same time, as a

110

Amplifier Design Basics

Figure 7.5 The schematic diagram (transistor level only) of a basic differential amplifier circuit. The tail transistor controls the dc current of the two “top” amplifying transistors. The 5K feedback resistors connected from the transistor’s base to its collector are for promoting stability.

high-RF impedance, suppressing the common mode signal. The resistors, Rb (typically about 5k), are a part of the base-biasing circuit. From the Eber-Moll equation [6], it can be shown that for identical transistors Ic1/Ic2 = exp(Vid/VT)

(7.8)

where Vid = (Vin+ − Vin− ). VT = thermal voltage (25 mV at 300K). The output voltages are + = Vcc – Ic1Rc Vout

(7.9)

− = Vcc – Ic2Rc Vout

(7.10)

The differential output voltage is + − Vod = (Vout – Vout )=

I Rctanh(–Vid/2VT)

f tail

(7.11)

where F1 = F2 = F (assuring identical transistors), and Rc is the collector load resistance. Since Vid is zero when Vod is zero, if identical transistors and resistors are used, this circuit allows direct coupling of identical stages without creating offset voltages. If a differential RF signal is presented to the differential amplifier’s input, a voltage gain may be calculated for the amplifier. By representing the transistor as a transconductance, Gm, it can be shown that Vod = –2GmRc(Vid/2)

(7.12)

7.7 Cascode Amplifiers

111

It follows that the amplifier’s differential voltage gain is given as Ad = Vod/Vid = –GmRc

(7.13)

Referring to Figure 7.5, transformers are used to create and uncreate the differential signals. Figure 7.6 shows the simulated gain of the differential amplifier as a function of frequency. The amplifier consists simply of a differential pair of identical transistors whose currents are controlled by the “tail” transistor. The collector terminations are purely resistive. In many cases, differential amplifiers can become unstable at high gains. For this reason, a resistor network provides parallel feedback between the collector and the base of each transistor in the differential pair. The values of the feedback elements are chosen to ensure unconditional stability over a wide frequency range while maintaining high gain. Typical performance of a differential amplifier is shown in Figure 7.6. If the amplifier is placed in front of a receiving mixer, noise figure will become a very important consideration. Differential amplifiers are capable of achieving very low noise figures and can serve as LNAs.

7.7

Cascode Amplifiers Cascode amplifiers derive their name from the original vacuum-tube version of the circuit, which consists of the “cascade” of two vacuum tubes in such a way that a common cathode tube and a common grid tube are joined such that the “anode” of the first tube is connected to the cathode of the second tube (i.e., the tubes are “cascoded”). This arrangement has the ability to increase output resistance and, at the same time, reduce unwanted feedback associated with parasitic capacitance. Cascode amplifiers may be constructed in either single-ended or differential form. A differential version of a cascode amplifier is shown in Figure 7.7. For an equivalent single-ended cascode amplifier, the input resistance is

Figure 7.6 The simulated gain and stability for the basic differential amplifier circuit shown in Figure 7.5.

112

Amplifier Design Basics

Figure 7.7 The schematic diagram (transistor level only) of a differential cascode amplifier circuit. Notice the common-base connection of the “top” two transistors and that large capacitors are used to connect the top transistors’ bases to ground in order to achieve common-base operation over a wide range of frequencies.

Ri = r

1

(7.14)

Following P. Gray it can be shown that the cascode amplifier’s output resistance is Ro = r02(1 + Gm2 r02/ )

(7.15)

where = (1 + Gm2 r01/ 0). r01 is the common emitter transistor’s (Q1,Q2) output resistance. r02 is the common-base transistor’s (Q3,Q4) output resistance. Gm2 is the common-base transistor’s (Q3,Q4) transconductance. 0 is the transistor’s dc current gain. If Gm2 r01 >>

0

and

0

>>1, (7.15) reduces to R0 =

r02

(7.16)

Therefore, the two transistors connected in cascode have an output resistance that is larger by a factor of 0 than the output resistance (r02) of the common emitter transistor alone. If we assume a very high collector load resistance, Rc, the cascode amplifier has a voltage gain of Av = Vo/Vi = –GmRo = –Gm 0r02

(7.17)

Therefore, a cascode amplifier has a voltage gain that is higher than the voltage gain of a single transistor amplifier (–Gm r02) by a factor of 0. This additional gain can be very useful in a wide variety of applications. Figure 7.8 shows the simulated power gain for this circuit, while working into a high impedance load (similar to voltage amplification).

7.7 Cascode Amplifiers

113

Figure 7.8 The simulated gain, reverse isolation, and stability of the differential cascode amplifier shown in Figure 7.7 Notice that with the cascode-amplifier circuit configuration, the gain is higher, the isolation is higher, and the stability is improved relative to a basic differential amplifier circuit.

References [1] [2] [3] [4] [5] [6]

Vendelin, G., Design of Amplifiers and Oscillators by the S-Parameter Method, New York: John Wiley and Sons, 1982. Smith, P., Electronic Applications of the Smith Chart, New York: McGraw-Hill, 1969. Fano, R., “Theoretical Limitations on the Broadband Matching of Arbitrary Impedances,” J. Franklin Institute, Vol. 249, January 1960, pp. 57–83, and February 1960, pp. 139–155. Vendelin, G., et al., Microwave Circuit Design Using Linear and Nonlinear Techniques, New York: John Wiley and Sons, 1990. Razavi, B., RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998. Gray, P., et al., Analysis and Design of Analog Integrated Circuits, New York: John Wiley and Sons, 2001.

CHAPTER 8

Low-Noise Amplifier Design 8.1

Noise Figure Concepts It is the purpose of low-noise amplifiers (LNAs) to amplify weak signals being received directly from an antenna and to amplify them sufficiently, adding a minimum of additional noise, so that the signals may be efficiently processed and their information content extracted with a minimum of errors. LNAs are usually located as the first stage of a receiver; therefore, they receive input signals directly from the antenna. The effectiveness of a low-noise amplifier is specified by an important metric called noise figure (NF). Figure 8.1 provides a plot of signal level and noise level as a function of frequency to help explain the concept of noise figure. At the receiver’s input, the signal level, S, is above the noise level, N, by a ratio called the signal-to-noise ratio, S/N. Typically, thermal noise power at the input of a receiver is given by N = kTB

(8.1)

where k = 1.38E–23 J/K. T is the ambient temperature in degrees kelvin. B is the receiver’s bandwidth in hertz.

Figure 8.1 The noise figure of an LNA is defined as the ratio of SNR at the amplifier’s input to the SNR at the amplifier’s output. A perfect LNA (one that adds no noise to the signal it is amplifying) would have a noise figure of 1.0 (or 0.0 in decibels).

115

116

Low-Noise Amplifier Design

The LNA’s noise figure is defined as the ratio of signal-to-noise power at the input of the LNA, divided by the ratio of signal-to-noise power at the output of the LNA. NF = (S/N)in/(S/N)out

(8.2a)

Noise figure may be expressed in decibels by using the following expression: NF (dB) = 10log[(S/N)in/(S/N)out]

(8.2b)

If the LNA internally generated absolutely no noise, NF would equal exactly 1.0 in numbers (or 0.0 dB). This is because both the signal and the noise are amplified by the amplifier’s gain, and their ratio will be unchanged. However, in any real amplifier, the electronics within the LNA will contribute some amount of noise output, making the signal-to-noise ratio at the output less than the signal-to-noise ratio at the LNA’s input. This situation is demonstrated graphically in Figure 8.1. Any signal passing through a realistic (nonideal) LNA encounters noise generated within the LNA’s circuitry. The signal-to-noise ratio at the LNA’s output is degraded by this noise, raising the noise figure. An elevated noise figure means that, at the output, the noise power will be greater than simply the noise input times the amplifier’s gain. In fact, the noise output from a low-noise amplifier is given by Nout = (NF) GkTB

(8.3)

where G is the amplifier’s gain.

8.2

Noise Temperature In certain highly specialized applications, such as radio astronomy and deep-space communications, LNAs must have extremely low noise figures in order to receive the weak signals required by these applications. The difference between an 0.80 and 0.60 dB noise figure may make a great deal of difference in overall system performance. Since, numerically, such small differences are difficult to measure, a different system of specifying noise has evolved within these highly specialized applications which is called noise temperature [1]. Noise temperature is simply a measure of what the ambient temperature of the environment would have to be to account fully for all noise sources with in the LNA. Since many internal noise sources within the LNA are directly related to the ambient temperature of the LNA’s components, in many cases the physical temperature of these “super LNAs” is reduced with cooling (liquid nitrogen or liquid helium). Cooled LNA’s for radio astronomy applications may have noise temperatures as low as 30°K. It is much easier to compare and understand the difference between 30°K and 100°K than to comprehend the difference between 0.35 and 0.70 dB. Noise figure can be converted to noise temperature using the following equation Tn = T0 (NF – 1)

(8.4)

8.3 Front-end Attenuation and LNAs

117

where T0 is the ambient temperature of the environment (about 290ºK). Noise temperature may be converted back to noise figure with the following expression NF = (1 + Tn/T0)

8.3

(8.5)

Front-end Attenuation and LNAs Sometimes there is signal attenuation between the antenna and the LNA in many receiver systems. Connectors and transmission lines all have some degree of attenuation. Also, devices such as band-pass filters and switches may precede the LNA and add to the overall noise figure. Such attenuation affects noise figure profoundly because the attenuation reduces the signal level, but not the noise level, which always remains at kTB. Figure 8.2 shows how a signal from an antenna passing through a front-end attenuation (A) will already experience a decrease in signal-to-noise ratio in direct proportion to A. Therefore, A will reduce the signal-to-noise ratio of the receiver’s front end by reducing the signal level into the LNA, and the LNA will reduce the front end’s signal-to-noise ratio by raising the noise power associated with the signal. The combined effect will yield a noise figure expressed in decibels as NF (attenuation plus LNA) = [A + NF (LNA only)]

8.4

(8.6)

Multistage Noise Figure Contributions In the multistage amplifier shown in Figure 8.3, the opposite situation to front-end attenuation is encountered. The first stage amplifies the signal to a level significantly above the noise level in the second stage. For this reason, the second stage’s contribution to the LNA’s noise figure is diminished by the gain of the first stage. In the same way, the noise-figure contribution of the third stage is diminished by the gain

Figure 8.2 Attenuation in front of an LNA reduces overall SNR by reducing the signal that reaches the LNA. The reduction in SNR, caused by attenuation, raises the overall noise figure of the attenuator plus the LNA by exactly the amount of attenuation. If calculated in decibels, the overall noise figure is simply the noise figure of the LNA, in decibels, plus the attenuation in decibels.

118

Low-Noise Amplifier Design

Figure 8.3 Second- and third-stage contributions to the noise figure of a multistage LNA are reduced by the gains of the first and second stages. Therefore, it is important for at least the first stage of a cascaded LNA to have the highest possible gain.

of the first and the second stages. The total noise figure (in numbers) for a multistage amplifier is given below. NF (total) = NF1 + (NF2 – 1)/G1 + (NF3 – 1)/G1G2 + …

(8.7)

Equation (8.7) tells us that the first stage is absolutely critical in determining an LNA’s noise figure, both in terms of its noise figure but also in terms of its gain. The second stage’s contribution to total noise is divided by the gain of the first stage. All following stages have noise-figure contributions that are divided by factors even larger than the second stage. It is good practice to design the first stage of an LNA with over 10 dB of gain. This ensures that the second- and all-subsequent-stage contributions will be reduced by a factor of ten as a minimum. Referring to Figure 8.4, we see that second-stage contributions can also be calculated for LNAs that are specified in terms of a noise temperature. The total noise temperature of a multistage LNA is Tn (total) = Tn1 + Tn2/G1 + Tn3/G1G2 + …

8.5

(8.8)

Circuit Topologies for Low Noise Before discussing LNA circuit topologies, it is necessary to discuss physical sources of noise in the transistors that comprise the active devices in these amplifiers [2]. There are three principle physical sources of noise in bipolar transistors: 1. Thermal noise: Pn = kTB (8.9) 2. Shot noise: mean square noise current = qIdcB

(8.10)

3. 1/f or flicker noise: mean square noise current = qIdcB/f

(8.11)

Figure 8.4 Noise temperature is an alternative way to express noise figure. Noise temperature is often used to express the noise performance of extremely low-noise LNAs, such as those used in radio astronomy.

8.5 Circuit Topologies for Low Noise

119

where k is Boltzmann’s constant, and q is the charge on an electron. Figure 8.5 shows the spectrum of each physical source of noise. Notice that both thermal and shot noise are white noise sources, meaning that their noise power density does not change with frequency. However, as its name implies, 1/f noise becomes quite strong at low frequencies and gradually declines as frequency increases. Figure 8.6 is a typical LNA noise figure plotted against frequency, showing how these physical sources of noise are affected by the filtering effects at work in the amplifier’s matching circuits. An important frequency is the 1/f noise corner frequency. The corner frequency is that frequency where the 1/f noise contribution becomes just equal to the “white” sources of noise, like thermal noise and shot noise. At frequencies below the corner frequency, the amplifier’s noise figure is dominated by 1/f noise, but above the corner frequency, the amplifier’s noise figure becomes dominated by one or both of the “white” noise sources. We now briefly discuss the physics of these three noise sources. 1/f noise is a result of so-called trapping states that exist just below the conduction band energy level in the semiconductor’s energy band structure. These energy states are located in the so-called forbidden band and are not available for conduction. Trapping levels are often associated with impurity atoms in the crystal structure of the transistor. Often, these impurities are located on the surface of the crystal, although they may

Figure 8.5 The spectrum of the three most important physical sources of noise in electronic circuits: thermal noise, shot noise, and 1/f noise.

Figure 8.6 The noise-figure spectrum of a typical LNA, showing a 1/f region at low frequencies and a thermal noise (or shot noise) region at high frequencies. The high-frequency region has increasing noise figure as a result of increasing circuit attenuation at higher frequencies. The frequency where minimum noise figure occurs is called the noise corner frequency.

120

Low-Noise Amplifier Design

be found in the bulk of the crystal as well. Referring to Figure 8.7, we see that the trapping states can “capture” conduction electrons and hold them hostage for a very long time. While hostage, these electrons are not available for conduction, so a current spike occurs whenever one of these “trapped” electrons is either trapped or released from a trap. The time constant of the trap depends on how far below the conduction band energy, Ec, the trap is located. Traps with energies nearly equal to Ec are very slow and release their captured electrons after a very long time. Traps with energies significantly below Ec are much faster and capture and release their electrons much more quickly. The net effect is for many time constants to be at work at the same time, making a “smear” of noise power within frequency, with the greater power appearing at low frequency. 1/f noise can be a big problem with many kinds of transistors, especially transistors in the field-effect family. However, bipolar transistors have much less susceptibility to 1/f noise than their field-effect cousins. Saying this in numbers means that field-effect transistors have corner frequencies ranging from 10 to 500 MHz, while bipolar transistors have a corner frequency that ranges from 100 Hz to 100 KHz—a difference of almost five orders of magnitude. In applications where low 1/f noise is of critical importance (like low-phase-noise VCOs), bipolar transistors have a distinct advantage over their field-effect cousins. Thermal noise is a direct result of the thermal agitation of the electron gas within any conductor. This noise source is also called resistor noise because it was first observed in resistors. Thermal noise is associated with any resistive region or structure within an RFIC. In general, it is not the dominant source of noise in bipolar devices. That distinction is left for shot noise. Referring to Figure 8.8, we see that, in a bipolar transistor, carriers fall through the potential gradients at both the collector-to-base junction and the base-to-emitter junction. The electrons in these regions behave like individual charged particles, and as they pass through the junction, the effect of each one’s contribution to current is a little like big rain drops falling on a tin roof in a heavy rain storm. They create a loud noise as their individual impacts blend with all of the other electron impacts all around them. This so-called shot noise (the name association is with bird shot falling on a roof like rain drops, but louder) has a mean square current intensity proportional to the average dc current

Figure 8.7 1/f noise in electronic devices is caused by trapping states on the surface of the semiconductor, alternately capturing and releasing carriers, with a distribution of time constants. These overlapping noise spectra, with wide distributions of corner frequencies (the inverse of the time constants), tend to average out to a 1/f-behaving spectrum over a wide frequency range.

8.5 Circuit Topologies for Low Noise

121

Figure 8.8 With bipolar transistors, the primary noise source is the shot noise generated in both the base region and the collector region. Both Gummel Poon and VBIC device models allow accurate simulation of shot noise effects.

multiplied by the charge e of a single electron times the measurement bandwidth, as given in (8.10). It turns out that shot noise is the dominant noise source in bipolar transistors, and since shot noise is proportional to dc current, it is vary advantageous in bipolar LNA circuits to keep the dc bias current in all transistors to an absolute minimum. In bipolar transistors, both base current and collector current can serve as the source of shot noise. While shot noise sources are at a minimum, the noise figure also includes the transfer function of the transistor since noise figure depends on the ratio of the total noise compared to the noise of the input source. Noise due to collector shot noise increases more slowly than noise from the input source as the collector current increases [3]. Therefore, higher collector current may reduce the effect of collector shot noise on overall noise figure. Noise due to base shot noise increases more rapidly than noise from the input source as the base current increases, so, in this case, low dc base current helps to reduce overall noise figure. Noise associated with the base resistance increases at the same rate as noise from the input source. Therefore, at low dc current, the noise figure may be improved by raising the dc current to decrease the effects of collector shot noise. As the dc current increases, eventually the base shot noise dominates, and the overall noise figure increases. For any particular transistor size, there is an optimum dc current for achieving the lowest possible noise figure. The input impedance for achieving a minimum noise figure depends on device size. Often, an optimum device size can be determined that simultaneously produces minimum noise figure and matches the transistor to a 50 ohm load for maximum gain. LNAs are like any other amplifier circuit requiring input and output matching for maximum gain; in addition, however, LNAs require input mismatch to insure the lowest possible noise figure in the first stage. In Figure 8.9, we see that the match for minimum noise figure is somewhat displaced from the match for maximum gain (conjugate of S11). This displaced matching impedance is called Γopt and is located at about the same angle as conjugate S11, but at about half the magnitude of S11. This is only a rule of thumb, and the exact impedance of lowest noise figure can only be found by using the device’s large-signal model to predict gain and noise figure

122

Low-Noise Amplifier Design

Figure 8.9 The input match for achieving a transistor’s minimum noise figure (Γopt) may not be the same as the input match for achieving the transistor’s maximum gain (S11*).

based on the exact impedance presented to the transistor’s input and output by the matching networks. A low-noise amplifier requires matching circuits like any other amplifier. The output matching network is normally designed for maximum gain, minimum S22, based on small-signal conditions. The exception is so-called high dynamic range applications, which require an LNA that has both a low noise figure and a relatively high third-order intermodulation intercept point (OIP3). This type of amplifier should be designed like an LNA at its input and like a PA at its output. A more conventional LNA requires a certain amount of intentional mismatch at its input in order to present Γopt to the transistor’s input. In many cases, it is purely a matter of choosing a well-understood matching topology and adjusting it carefully until the transistor’s minimum noise figure is obtained. This process is not as easy as it sounds and can sometimes be quite challenging. A key point to remember is that any loss element in front of the LNA’s transistor will serve to introduce attenuation at the LNA’s input, which adds directly to the overall noise figure. For this reason alone, elements with high loss should be avoided in the LNA’s input matching structure. Matching elements, such as spiral inductors, can be major contributors to noise figure because of the metal loss associated with their structure. In designs seeking the lowest possible noise figure, it sometimes makes sense to use off-chip matching inductors in the amplifier’s input circuit to avoid losses in this critical area. Many excellent surface-mount inductors are available with practically no electrical loss. A brief word about device models is in order at this point [4]. Both the Gummel Poon and VBIC devices include all noise mechanisms within their parameter set. So long as the factory has measured the device’s 1/f noise and included parameters in the device model, both types of scalable large-signal device models will fully account for the effects of thermal, shot, and 1/f noise, However, not all foundry models include 1/f parameters, so the designer must check with the foundry to be sure. The actual matching topology may be one of the standard types, such as low-pass and high-pass matching. Figure 8.10 shows the topology of a low-pass-matched LNA. Both the amplifier’s input and output use nearly identical single-section low-pass-matching structures. Base bias is provided by an RF choke connected to a high-value resistor and a low-voltage base-bias supply. Collector bias is provided by a single RF choke. Optimization of this circuit proceeds from the

8.5 Circuit Topologies for Low Noise

123

Figure 8.10 The schematic diagram of a single-stage LNA, making use of low-pass filter elements in both its input and output matching circuits.

input to the output. The first step is to adjust the input matching network for minimum noise figure and, at the same time, the maximum gain that can be associated with minimum noise figure. The simulator’s optimization function can be very useful in this regard, but the designer must be very careful to set the goal in a reasonable fashion to be sure that the best compromise between minimum noise figure and maximum gain is actually accomplished. Once the input matching network has been optimized, the output matching network is tuned to provide a minimum value of MAG[S22], which corresponds to matching for maximum gain in the amplifier’s output circuit. Once both input and output matching circuits have been optimized, the amplifier needs to be analyzed for stability. If there are problems, stabilization elements, such as series RL and series RC networks, must be introduced into the topology to cure these problems. It is very important to be very careful not to compromise noise figure when adding stabilization networks (see Chapter 9). Sometimes feedback can be helpful in stabilizing an LNA. Figure 8.11 gives the schematic diagram of an LNA similar to the one that has just been described but with the addition of parallel feedback. These feedback elements must be applied “sparingly” to avoid the feedback resistor’s loss contributing to the LNA’s noise figure. This is best accomplished by maintaining this resistor at a high value. However, properly applied, parallel feedback can be a powerful tool in achieving excellent overall LNA performance. The alternative form of feedback is series feedback in the form of an inductor placed between the transistor’s emitter and ground. This circuit option is shown in Figure 8.12. This particular type of series feedback is called emitter degeneration and is of particular interest in LNA design because emitter degeneration has the capacity to move Γopt closer to conjugate [S11], which means that by applying this type of feedback, the designer may have the freedom to have his or her cake and eat it too in the sense that minimum noise figure and maximum gain may be achievable at the same time with this technique. In addition, because the match is moving closer to achieving a perfect match relative to S11, it is possible by using this technique to achieve excellent MAG[S11] at the same time as achieving minimum noise figure and maximum gain. Of course, as always, stability remains an issue, and only when the optimum matching conditions for best performance and unconditional stability have been achieved simultaneously is a final, successful design produced.

124

Low-Noise Amplifier Design

Figure 8.11 The schematic diagram of a single-stage LNA making use of both low-pass input and output matching elements and parallel feedback to achieve maximum gain, minimum noise figure, best match, and good stability—all simultaneously.

Figure 8.12 The input circuit of an LNA that is used to calculate the effects of emitter inductance series feedback (emitter degeneration) on gain and noise figure.

Following B. Razavi [5], it is possible to analyze how to obtain the lowest noise figure and an excellent input match to 50 ohm simultaneously by using inductive emitter degeneration. Refer to Figure 8.13 for a schematic diagram of this LNA’s circuit. The input-referred mean-squared noise voltage per unit bandwidth for this circuit is (based on the input circuit shown in Figure 8.12) Vn2 = 4kT(Rb + 1/2Gm)

(8.12)

where k is Boltzmann’s constant (1.38E–23 J/K). T is the temperature in degrees kelvin. Rb is the transistor’s base resistance. Gm is the transistor’s transconductance. This expression may be expanded to include the base shot noise for an input-referred noise source resistance including that of Rs, as

8.5 Circuit Topologies for Low Noise

125

Figure 8.13 The schematic diagram of a single-stage LNA that uses an inductive emitter degeneration technique to achieve improved balance between lowest noise figure and maximum gain at a given frequency.

Vnt2 = 4kT(Rs + Rb + 1/2Gm + GmRs2/2 )

(8.13)

where is the transistor’s current gain. The input impedance of this circuit is Zin = Rb + GmLe/C + Le – 1/ C

(8.14)

where Le is the emitter degeneration inductance. C is the transistor’s shunt input capacitance. ω is 2π times frequency By making the proper selection of Le and C it is possible to make the last two terms in (8.14) cancel out, leaving the input impedance as simply Zin = Rb + GmLe/C

(8.15)

By correctly choosing Rb, Gm, Le, and C , Zin can be set to exactly 50 ohms, to provide an excellent input match. The LNA’s noise figure is calculated as the ratio of the amplifier’s input referred noise voltage Vnt, divided by the source’s thermal noise. NF = Vnt2 /4kTRs = 1 + Rb/Rs + 1/2GmRs + GmRs/2

(8.16)

The LNA’s noise figure reaches a minimum of NFmin = 1+sqr[(1 + 2GmRb)/ ]

(8.17)

When the source’s resistance is set to its optimized value, Rs opt, Rs opt = sqr[ (1 + 2GmRb)]/Gm

This result ignores the effect of parasitic capacitance.

(8.18)

126

Low-Noise Amplifier Design

An estimate of the transistor’s high frequency = Ft/F

can be made as follows: (8.19)

where Ft is the transistor’s current gain cutoff frequency, and F is the frequency of operation. Of course, accurate values of noise figure, match, and gain as a function of frequency must ultimately be obtained from simulations. LNA projects must balance the sometimes conflicting demands of noise figure, gain, match, intermodulation intercept point, and stability with the device’s size. Ordinarily, a small device with minimum collector current is used in LNAs in order to minimize both shot noise and 1/f noise. However, this straightforward approach does not always yield the best overall performance. Sometimes a slightly larger device with less-than-usual current per finger gives better overall results. Some experimentation on the designer’s part is necessary to arrive at the final best combination of factors that contribute to an optimized final design. The simultaed performance of the amplifier circuit shown in Figure 8.13 is given in Figure 8.14.

8.6

Design Example 1: Single-Ended PCS LNA Very effective LNAs can be designed using a combination of input and output matching and parallel feedback. This amplifier’s topology is shown in Figure 8.15. The amplifier uses low-pass matching circuit elements consisting of a single series

Figure 8.14 The simulated S-parameters and noise-figure performance of the LNA circuit shown in Figure 8.13. The design frequency is 3.8 GHz.

8.7 Design Example 2

127

Figure 8.15 The schematic diagram of a single-stage LNA for PCS applications. This LNA makes use of parallel feedback and low-pass matching circuits. The input and output series matching inductors are located off-chip in order to achieve maximum Q to minimize noise figure by minimizing front-end losses. This circuit uses InGaP/GaAs technology.

inductor and a single shunt capacitor at both its input and its output. The series inductors could be on-chip spiral inductors for compactness; however, in the case of an LNA, it makes more sense to have at least the input inductor placed off-chip since off-chip, surface-mounted, wire-wounded inductors have significantly higher Q than on-chip spiral inductors can possibly have. The reason for the inherently low-Q nature of the “on-chip” inductors is that the spiral inductor winding trace metal is very thin, and is subject the high metal losses associated with skin effects. An additional key circuit element in this LNA is a parallel feedback network provided by a series RC circuit connected between the transistor’s base and its collector. This network enhances stability and improves the amplifier’s input and output match. The amplifier’s transistor is sized to be very small in order to keep the dc collector current as low as possible in order to minimize the shot noise contribution to noise figure. For this design, a single-finger InGaP/GaAs transistor is the only transistor in the LNA. During simulations, both the input and output matching elements and the feedback network may be optimized to achieve the best combination of gain, noise figure, and match over the band of interest. In the case of this design, performance has been optimized for the 1.7–2.5 GHz band, which includes the PCS, 3G, and WiFi b bands. Simulated gain is about 15 dB over this frequency range, with a noise figure of about 2.8 dB. The input and output match (S11 and S22) are –10 to –15 dB across this frequency band. Graphs of simulated gain, noise figure, and match as a function of frequency are shown in Figure 8.16. Details of the amplifier’s layout (showing the placement of the transistor, the resistors, and the capacitors) are shown in Figure 8.17.

8.7 Design Example 2: Three-Transistor Hybrid Darlington Differential LNA Using SiGe Technology An excellent single-ended (or as an option differential) broadband LNA can be designed using just three transistors and four resistors. The single-ended topology for this hybrid Darlington LNA is shown in Figure 8.18. The amplifier is capable of

128

Low-Noise Amplifier Design

Figure 8.16 The simulated S-parameter and noise figure of the single-stage PCS LNA shown in Figure 8.15.

Figure 8.17

The layout of the PCS LNA shown in Figure 8.15.

30 dB gain from dc to over 6 GHz with InGaP/GaAs technology and over 30 dB from dc to 12 GHz with SiGe technology. The LNA’s noise figure ranges from about 1.5 dB at 2 GHz to 2.5 dB at 6 GHz. The SiGe designs operate at 3.0V dc, while InGaP/GaAs designs operate at 4.0V to 5.0V. The following design rules apply in determining the values of R1, R2, R3, and R4. All three transistors are of equal size. For lowest noise figure, use very small (perhaps minimum-size) transistors. If power output and/or OIP3 (see Chapter 9) are

8.7 Design Example 2

129 10 pF

R1=500

IN

10 pF

Q1

Q2

A=2

OUT

Q3 A=2

A=2 10 nH

R2=800

R4=10 R3=250 Vcc=3.0 V

Figure 8.18 The schematic diagram of a single-ended, “Darlington-like,” broadband LNA using three transistors and InGaP/GaAs technology.

important considerations, the size of Q1, Q2, and Q3 must be increased until the desired value of P – 1 dB and/or OIP3 is obtained. The values of R1, R2, R3, and R4 should be adjusted to make all transistor dc currents approximately equal. For lowest possible noise figure, very low dc current should be used in all transistors. For highest possible power output and OIP3, the transistor’s dc current should be set close to the maximum allowable current. The value of R1 determines the dc currents in transistors Q1 and Q2. Values of R3 and R4 determine the current in transistor Q3. As a starting point, R3 is approximately equal to Vbe/IQ2. Once the dc levels are set, the design can proceed to simulating RF performance. These simulations, using SiGe technology, are shown in Figure 8.19. The microstrip transmission line MLIN should be adjusted to achieve the best possible S11 over the

Figure 8.19 The simulated S-parameters and noise figure of the “Darlington-like” LNA shown in Figure 8.18.

130

Low-Noise Amplifier Design

desired band of interest. With the single-ended LNA, it is very important to take much care in determining the amplifier’s stability. With this topology, any common mode inductance between the amplifier’s ground and system ground will degrade stability significantly and must be avoided. For this reason, this particular topology is best suited to be used as a differential LNA, where common mode inductance is virtually nonexistent. For receiver architectures using Gilbert cell mixers, the differential LNA is an ideal situation because the mixer’s input terminals are naturally differential, exactly matching the differential outputs of the LNA. A layout of the single-ended LNA (using InGaP/GaAs technology) is shown in Figure 8.20. Figure 8.21 shows a block diagram for the differential LNA. Notice that all grounding points tie together at a common “virtual” ground, preventing stability problems caused by stray common mode inductance. Figure 8.22 shows the small-signal performance of the differential LNA using SiGe technology device models. Notice that owing to the higher Ft of the SiGe devices, the LNA’s gain using this technology is relatively flat from dc to 15 GHz. The SiGe version of this LNA can only be modeled here using ideal lumped-element

Figure 8.20 The layout of the three-transistor “Darlington-like” LNA shown in Figure 8.18. Input is on the left.

Figure 8.21 The block diagram of a differential broadband, “Darlington-like” LNA using SiGe technology.

8.7 Design Example 2

131

Figure 8.22 The simulated S-parameters and noise figure of the differential “Darlington-like” SiGe LNA shown in Figure 8.21.

devices because of a lack of foundry models based on the normally conductive SiGe substrate. Actual foundry models, including lossy substrate effects, may reduce performance. A simulation of Pin versus Pout, showing the P – 1 dB point is given in Figure 8.23. Also, a simulation of OIP3 versus frequency is shown in Figure 8.28. Notice that the simulated value of OIP3 and P – 1 dB are both approximately +15

Figure 8.23 The simulated Pin versus Pout and 1 dB compression point of the “Darlington-like” SiGe LNA shown in Figure 8.21.

132

Low-Noise Amplifier Design

dBm. This is an unusual situation since most amplifiers have at least a 10 dB spread between OIP3 and P – 1 dB. However, in the case of this particular LNA, linearity has been sacrificed for noise figure, gain, and bandwidth. In some applications, this may be a good trade-off; in other applications, more robust linearity is demanded by a difficult multisignal environment. This particular LNA topology is very strong in its wideband gain and noise-figure capabilities but relatively weak in terms of its linearity performance. It is very important for the designer to keep these limitations in mind before deciding to use this particular topology.

References [1] [2] [3] [4] [5]

Lee, T., The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge: Cambridge University Press, 1998. Van Der Ziel, Fluctuation Phenomena in Semi-Conductors, London: Butterworth’s Scientific Publications, 1959. Gray, P., et al., Analysis and Design of Analog Integrated Circuits, New York: John Wiley and Sons, 2001. Matthias, M., Introduction to Modeling HBTs, Norwood, MA: Artech House, 2006. Razavi, B., RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.

CHAPTER 9

Power Amplifier Design Power amplifiers are used in wireless telecommunications systems to boost the power of transmitted signals to a sufficiently high level for “on-the-air” transmission. This means that power amplifier output power levels must be high enough to overcome antenna path losses such that sufficient signal-to-noise ratio is available at the receiver’s input to support the desired range. For mobile handheld equipment, power amplifier output is typically in the range of 100 mW to 5W. Base station power amplifiers are often required to have power outputs in the range of 10W to 50W. Often, power amplifiers are composed of a cascade of individual power amplifier stages, each of which elevates the transmitted power to a yet higher level. With infrastructure power amplifiers, as many as ten stages may be necessary to generate the required full-transmit power. A very important fundamental trade-off exists with power amplifiers between their dc-to-RF conversion efficiency and their linearity. Both conversion efficiency and linearity are important performance specifications in many applications. Efficiency is inversely related to dc current, so the battery life of a handheld device depends critically on conversion efficiency. On the other hand, a power amplifier’s linearity is a principle factor in determining the bit-error rate of the overall radio link because of the potential for signal distortion inherent in amplifier nonlinearity. Such distortions lead directly to bit errors, which compromises the radio link. Some modulation types, such as CDMA, are more sensitive to the effects of nonlinearity than are other modulations (GSM modulation, for example, is quite insensitive to PA nonlinearity). Therefore, CDMA systems require that some sacrifice be made in the conversion efficiency of PAs in order to assure the highest possible PA linearity. For this reason, CDMA handsets are directed by their cellular base stations to use the minimum transmitted power for acceptable signal-to-noise ratio in an effort to improve battery life. However, GSM power amplifiers (in mobile units) are typically run at high, constant power output (2W to 4W) because the high conversion efficiency of PAs designed for GSM service reduces dc current consumption and therefore extends battery life. These trade-offs between conversion efficiency and linearity are a direct result of the kind of current and voltage waveforms developed in a particular amplifier design. If these waveforms are very nearly sine waves, the amplifier will be highly linear since no new frequencies are being created within these waveforms. This type of operation is called “class A” and is characterized by a high level of amplifier linearity but not the highest possible conversion efficiency. In class A operation, the

133

134

Power Amplifier Design

perfectly symmetric sinusoidal RF waveforms are incapable of reducing losses during the “unproductive” portion of the RF cycle. Therefore, in pure class A operation, a power amplifier’s conversion efficiency is limited to a theoretical maximum of 50 percent. Higher classes of power amplifiers (classes AB, B, C, D, E, and F) make use of nonsinusoidal RF waveforms to reduce the losses during “unproductive” portions of the RF cycle. However, these higher amplifier classes pay the price of inherently higher nonlinearity associated with their nonsinusoidal waveforms. Today, most wireless telecommunications equipment makes use some form of phase modulation. As discussed in Chapter 3, these various phase modulations require a highly linear power amplifier to minimize distortions and their resulting bit errors. For these reasons, most wireless telecommunications power amplifiers operate in pure class A, or in those cases where a little more nonlinearity can be tolerated, in class AB. As a result of the paramount important of class A in most wireless applications, it will be this class of amplifiers that is discussed in greatest detail in this chapter. However, a brief discussion of class AB amplifiers will be presented due to the favorable trade-off they offer between efficiency and linearity.

9.1

Loadline Concepts In order to achieve maximum RF power, maximum dc-to-RF conversion efficiency, and best linearity at the same time, it is important to make use of an approach to PA design that requires the use of an optimum device loadline that determines the details of the transistor’s collector matching network [1]. These loadlines may be calculated directly from the device’s static IV curves, or they may be inferred from the dynamic behavior of the device’s voltages and currents under large-signal simulation. It is by careful application of the loadline concept that an RF power amplifier can be designed to achieve high power output, high efficiency, and high linearity simultaneously. Power amplifiers are often distinguished according to classes. The following is a brief list of the properties of a number of power amplifier classes [2]: 1. Class A: Class A is the most popular class of power amplifiers for wireless communications applications. This is the most linear mode of power amplifier operation. Class A power amplifiers have a maximum dc-to-RF conversion efficiency of 50 percent. 2. Class AB: Class AB power amplifiers are a hybrid between the highly linear class A amplifiers and the more efficient, but more nonlinear, class B amplifiers. Class AB power amplifiers can have up to 60 percent efficiency. 3. Class B: Class B power amplifiers are somewhat nonlinear but have impressive dc-to-RF conversion efficiencies—up to 75 percent. 4. Class C: Class C amplifiers are very efficient (up to 85 percent) but are highly nonlinear.

9.1 Loadline Concepts

135

5. Class D, E, and F: Class D, E, and F amplifiers are switching-mode amplifiers. These highly efficient amplifiers (85 to 95 percent) are so nonlinear that they may not even have a small-signal gain region in their operating characteristics. A widely accepted form for expressing dc-to-RF conversion efficiency in a power amplifier is power-added efficiency (PAE), expressed as PAE = (Pout – Pin)/Pdc

(9.1)

where Pdc = Vdc × Idc. Vdc and Idc are the total dc voltage and dc current supplied to the amplifier by the power supply. As with all amplifiers, maximum gain is obtained with a power amplifier when its device’s input and output are matched to the external source and load impedances (encountered by the amplifier’s connection to its surrounding system). Figure 9.1 gives a simplified circuit diagram showing how the input and output matching networks are designed to provide conjugate match to the input of the device (S11) and the output of the device (S22). These matches for high gain may not be the best matches for maximum power and efficiency. At the output, they definitely are not the best match for maximum power and efficiency (see Figure 9.2). Figure 9.2 contains a Smith chart display of the input and output matches with “contours” of constant power output. These impedance contours show how the match affects power. It turns out that in most cases, the input match has very little effect on power output and efficiency. But the opposite is true with the output match. The conjugate match at the output for maximum gain relative to the device’s small-signal output impedance (S22) is displaced considerably from the impedance where maximum power is obtained. Notice that the impedance for maximum power is on the real axis of the Smith chart and has a relatively low value. This is typical of class A power amplifiers. Next, we consider ways to estimate the optimum load impedance of a transistor to achieve maximum power and efficiency.

Figure 9.1 When matching an amplifier for narrowband operation, networks M1 and M2 provide a conjugate match to the transistor’s input and output in order to realize maximum gain at a given frequency.

136

Power Amplifier Design

Figure 9.2 When matching for maximum gain, the conjugate matches (S11* at the input and S22* at the output) must be provided by networks M1 and M2. However, when matching for maximum power output, it is found that maximum power output occurs for an output match that is considerably different from S22* and is often pure real and quite low in value.

9.2

Maximum Power and Efficiency Maximum power and efficiency can be obtained only by providing the correct load to a power amplifier’s transistor. This correct load for obtaining maximum power and efficiency is called the loadline resistance. A loadline resistance may be calculated directly from the device’s static IV curves. Figure 9.3 gives an example of a bipolar transistor’s dc IV characteristic curves. This particular set of curves was generated using a large-signal VBIC device model. Gummel Poon device models can also be used for this purpose. Now, we consider the construction of a loadline for maximum power and efficiency in class A operation. This graphical construction is shown in Figure 9.4. The loadline must be centered on the device’s dc operating point, which is at Vce = Vdc

Figure 9.3 The simulated IV curves of a single emitter cell in a InGaP/GaAs transistor based on a generic VBIC device model.

9.2 Maximum Power and Efficiency

Figure 9.4 in class A.

137

The graphical construction of an output loadline, Rl, for a bipolar transistor operating

along the collector-to-emitter voltage axis and at Ic=Idc along the collector current axis. In order to maintain best-possible power output, efficiency, and linearity, it is critical that the RF voltage and current swings always stay in the “saturated current” portion of the device’s IV curves. This means the RF voltage must never swing into the resistive region that exists below the knee voltage (Vk). At the high-voltage, low-current extreme of the RF signal swing, the instantaneous voltage must never exceed the device’s collector-to-emitter breakdown voltage (BVceo). If these two conditions are met, the device will remain in a very linear portion of its characteristic curves. The purpose of the output matching circuit is to present an optimum loadline resistance to the device’s collector-to-emitter terminals so that the above conditions are always in force. The slope of the loadline resistance is determined by connecting the highest current that does not fall into the resistive region below the knee voltage, Vk, and the highest possible RF voltage that does not enter the breakdown region, BVceo. In order to center this loadline resistance, it is necessary to determine the dc operating point’s voltage and current. The dc voltage will be determined by the available power-supply voltage in a given application, while the current will be determined by the maximum safe and reliable collector current based on the chosen device’s size. If the device has to be resized in order to increase its power output, the loadline resistance must be recalculated. In the same way, if the dc voltage is changed for any reason, the loadline resistance must be recalculated. Figure 9.5 shows the completed loadline construction, including sine wave voltage and current waveforms. It is important that the output waveform always be a sine wave because sine waves contain only one frequency, which is the condition for optimum linearity in the overall amplifier. We are now in a position to develop a set of equations that define a power amplifier’s loadline resistance plus the resulting power output and efficiency. Based on the above graphical constructions, the loadline resistance is Rl = (Vdc – Vk)/Idc

(9.2)

Pdc = Vdc × Idc

(9.3)

And the dc power is

138

Power Amplifier Design

Figure 9.5 The voltage and current waveforms associated with the class A loadline at the signal amplitude level where power output reaches its maximum value. Notice that both waveforms remain perfect sine waves up to this point. At higher signal levels, both the voltage and the current waveforms will suffer clipping, causing considerable distortion and nonlinearity in the output signal.

The output power is equal to Pout = Vrms × Irms cos(phase angle)

(9.4)

Assuming a phase angle of zero (that is a pure real load), Pout = (Vdc – Vk)2/2Rl

(9.5)

And the dc-to-RF conversion efficiency (collector efficiency) is EFF = Pout/Pdc = (Vdc – Vk)/2Vdc

(9.6)

For Vdc much greater than Vk, (9.6) tells us that a class A power amplifier’s efficiency approaches 50 percent in the limit. Power amplifiers always benefit from high supply voltage in terms of both power output and efficiency. If the supply voltage is low, the value of the loadline resistance is reduced accordingly, placing a burden on the output matching network to perform a higher transformation ratio from the external system impedance, which is usually 50 ohms. While a supply voltage of 3.0V is often all that is available in battery-powered, handheld wireless equipment, from the viewpoint of power amplifier design, it is a liability that must be overcome with clever design techniques. For a given power output, such a low-voltage power

9.3 Class AB Power Amplifiers

139

amplifier would have to operate at very high current swings to make up for the low voltage swings constrained by the low supply voltage. An additional liability with low supply voltage is lowered dc-to-RF conversion efficiency as a direct result of the considerations in (9.6). When operating with low supply voltages, the resistive region of the device’s characteristic curves becomes an increasingly higher percentage of the overall voltage swing, decreasing both power output and efficiency. The peaking of power output, efficiency, and linearity at the optimum loadline resistance is shown graphically in Figure 9.6. Since (9.4) tells us that power is maximized for zero phase angle between Vrf and Irf (i.e., cos(phase angle) = 1.0), we see in Figure 9.7 that when Rl is placed on a Smith chart, it is always on the real axis, and in many cases it assumes a low resistive value that is very close to a short circuit.

9.3

Class AB Power Amplifiers Many applications, such as GSM mobile phones, require power amplifiers with higher power-added efficiencies normally achievable with class A amplifiers. These amplifiers are able to make the corresponding sacrifices in linearity because of the relaxed linearity requirements of their application. Class AB is an excellent compromise since it offers realistic efficiencies of up to 60 percent with only minor reductions in linearity.

Figure 9.6 The maximum power output, maximum power-added efficiency, and best linearity (as measured by OIP3 and ACPR) will occur when the amplifier’s RF amplifier transistor is connected to a load resistance of Rlopt.

Figure 9.7 To insure that the product of the voltage and current waveforms generates the maximum possible available power, Rlopt must be pure real (being on the real axis of the Smith chart).

140

Power Amplifier Design

In class A operation [3], the RF transistors are turned on for 100 percent of the RF cycle (i.e., the conduction angle for class A is a full 360°). This high-duty condition leads to high collector current and a correspondingly reduced efficiency. On the other hand, in class AB the collector current is reduced somewhat, and it is anticipated that the RF transistors will be turned on for less that 360°. This implies that in class AB, the RF transistors will be turned off for some phase interval, which is typically somewhere between 0° and 180°. The quiescent collector current in class AB operation lies somewhere between 0 and 0.50 Imax, whereas the quiescent current for class A operation is always 0.50 Imax (see Section 9.2). Since the class AB collector current is turned off for some portion of the RF cycle, the RF current waveform is “clipped” during the downward-going part of the cycle. This clipped current waveform approaches a half-wave-rectified sine wave in the limit of 180° of turned-off angle. In this limit, class AB smoothly approaches class B operation. At the other extreme, class AB operation smoothly approaches class A operation in the limit as the turned-off phase angle approaches 0° (see Table 9.1 for a summary of PA classes of operation). Since the class AB current waveform is distorted by its current waveform clipping, it is necessary to perform a Fourier analysis on the waveform to determine the peak sinusoidal current at the fundamental frequency. Also, the dc current must be determined in a similar way by Fourier analysis. It can be shown that ∝

δ

  I dc = ( Imax / π )∫ dθ + ∫ (Vq + Vs cos θ)dθ 0  ∝

(9.7)

where Imax is the transistor’s maximum collector current, and θ is the phase angle. Following S. Cripps [2], is the clipping angle defined as cos( = (1 – Vq)/Vs and cos( δ) = −Vq / Vs

Vs is the signal voltage amplitude for maximum “unclipped” operation, and Vq = 1 – Vs. is the “turned-on” phase angle. In a similar way, the fundamental component of the current waveform is ∝

δ

  I1 = (2 Imax / π )∫ cos θdθ + ∫ Vq + Vs cos θ cos θdθ 0  ∝

[

]

(9.8)

As in the case of class A operation, the dc power, loadline resistance, RF power output, and power-added efficiency of a class AB amplifier are given by Table 9.1

PA Modes of Operation

Class

Conduction Angle in Degrees

Quiescent Current

A AB B C

Exactly 360 180–360 Exactly 180 0–180

0.5 IMAX 0–0.5 IMAX 0 0

9.4 Definitions of Nonlinear Performance Metrics

141

Pdc = Vdc Idc

(9.9)

Rl = V1/I1

(9.10)

Prf = (Vdc – Vk) I1/2

(9.11)

Efficiency = I1/2 Idc

(9.12)

where V1 = (V dc − V k )

9.4

Definitions of Nonlinear Performance Metrics Most RFIC amplifiers for wireless communications applications require a high degree of linearity to fulfill their architectural role within an advanced digital communications system. It is very important that we devise a set of linearity metrics that specify the linearity of a power amplifier [4]. Also, it is important when comparing alternative approaches to power amplifier design to have available certain linearity metrics that can be used to compare design options. The first linearity metric to be considered is power saturation. As shown in Figure 9.8, a power amplifier’s input power is plotted against its output power. As the power level increases, a phenomenon known as saturation occurs. Saturation causes the output power to no longer to follow the input power in an exact 1:1 fashion [5]. Above a certain power, called the N dB compression point, the power output no longer responds to increases in the power input and assumes a nearly constant value. While the choice of N is arbitrary, the most popular value for N is 1 dB. Quite often, an amplifier’s saturation is described in terms of its 1 dB compressed power output and its ultimate saturation power output. In certain applications, it may be meaningful to use other values for N, such as 3 dB. Another important linearity metric is harmonic distortion of the kind shown in Figure 9.9. As the signal level increases, the amplifier’s transistors are exercised into their nonlinear regions, generating harmonics, sometimes to the fourth or fifth order. These harmonic pow-

Figure 9.8 A graph of power input versus power output for a typical class A power amplifier, showing the regions of gain compression and power saturation.

142

Power Amplifier Design

Figure 9.9 Harmonic output power increases as a power amplifier is driven harder in order to approach its maximum power output. This is one of the symptoms associated with the increasing nonlinearity encountered as the signal levels increase.

ers become increasingly strong as the power input to the amplifier approaches the saturation level. We clearly see this behavior at work in the plots of the second and third harmonic shown in Figure 9.9. As a practical matter, harmonics are rarely a problem in wireless applications because of the inherently narrowband nature of these applications. Therefore, any harmonics can easily be eliminated by placing a low-pass filter at the power amplifier’s output. However, in some applications, such as UWB systems, it may not be so easy to eliminate harmonics by filtering. In this case, the amplifier’s power level may need to be reduced to avoid the detrimental effects of high harmonic power in the amplifier’s output [6]. We next consider the phenomenon of intermodulation. Intermodulation occurs when two input signals are amplified simultaneously by a common power amplifier. These signals will mix within the amplifier’s nonlinearity to create new signals at frequencies above and below the input frequencies. Figure 9.10 shows an experimental setup for measuring two-tone intermodulation. The two input signals (the two “tones”) are of equal power and separated in frequency by a small delta (∆ = F1 – F2). When these two signals are amplified, an output spectrum, as shown in Figure 9.11, is generated that contains the two amplified “tones,” plus third-order, fifth-order,

Figure 9.10 The experimental setup for measuring two-tone intermodulation products and the OIP3 of a power amplifier.

9.4 Definitions of Nonlinear Performance Metrics

143

Figure 9.11 The two-tone intermodulation spectrum at the output of a power amplifier, showing the third- and fifth-order intermodulation products.

and perhaps seventh-order intermodulation sidebands. The intermodulation process produces only odd-order products in frequency due to their mathematical origins in a general power-series description of the device’s nonlinearity. Notice that in the amplifier’s output spectrum, new frequencies (the intermodulation products) are arranged both above and below the two original tones in frequency. All products are spaced in frequency by ∆ = F1 – F2, both above and below the two original “tones.” The amplified two-tones are far stronger than either the third- or fifth-order intermodulation products. As the input power is increased, this ratio decreases because (due to its nonlinear nature) the intermodulation process produces intermodulation products that increase more quickly than the linear two-tone power. We can plot power input versus power output for both the two-tones and their intermodulation products, as shown in Figure 9.12. In the case of third-order intermodulation products (which in practice are the highest and most troublesome), the intermodulation increases at a 3:1 rate with increasing input power, whereas the linear two-tone power increases at a 1:1 rate. This difference in rate of increase means that if we project the third-order products to high input powers (using a straight line projection), these projected intermodulation products will, at some point, intersect the more slowly increasing two-tone power. This point of intersection, called the intercept point, is shown in Figure 9.12. On the output side of the amplifier, the intercept point is called OIP3 for third-order products, and OIP5 for

Figure 9.12

A graphical construction often used to calculate a power amplifier’s OIP3.

144

Power Amplifier Design

the fifth-order products. Once the intercept point has been determined, the ratio between the two-tone output power and the intermodulation product output power can be calculated from the following equation: /2 = OIP3 – Pout

(9.13a)

where is the ratio in decibels between the third-order intermodulation products and the two-tone power, and Pout is the power output of the two-tones. In a similar way, the fifth-order intercept point can be used to determine the ratio between the fifth-order products and the two-tone power by using the following equation: /4 = OIP5 – Pout

(9.13b)

Having determined OIP3 (and/or OIP5) by measurement or simulation, two additional important metrics can be defined. These metrics are very useful for comparing and contrasting power amplifiers of different designs. The first metric is called scaled linearity and is defined as Scaled linearity = (OIP3 – P – 1 dB)

(9.14)

Scaled linearity offers a way to specify how linear an amplifier is, independent of its power output. Therefore, by using the scaled linearity metric, one can compare the relative linearity of two power amplifiers of greatly different power outputs. This is a very useful technique for projecting the usefulness of a given amplifier circuit to higher or lower powers than were encountered in the original design. A second important linearity metric is called linear efficiency. Linear efficiency is defined as Linear efficiency = 10log(OIP3/Pdc)

(9.15)

where OIP3 is the third-order output intercept point given in numbers (watts or milliwatts), and Pdc is the amplifier’s dc input power expressed in units of watts or milliwatts. Linear efficiency is a measure of how effectively the dc power input to a power amplifier is used for producing linear amplification. Of course, different applications are better characterized by the use of one metric over another, but all are important [7]. There is no set of rules governing which set of metrics is best to use in a specific application. This selection will be made by the designer after a careful review of the requirements and specifications of a particular application. It is important to know what level of performance metrics can be expected with different types of bipolar power amplifiers. Amplifiers with input and output matching and/or feedback can be expected to deliver efficiencies (PAE) of 40 to 50 percent when operating in class A. Darlington (unmatched) amplifiers can deliver 15 to 25 percent PAE. Both kinds of amplifiers can be expected to deliver scaled linearity in the 10–15 dB range (depending on frequency). Matched amplifiers are capable of having linear efficiency in the 5–15 dB range; however, Darlington amplifiers operate with significantly lower linear efficiencies (on the order of 0 to 5 dB). GaAs HBT

9.5 Adjacent Channel Power Ratio

145

and SiGe devices operate in very similar ways except for supply voltage. Because of the much lower Vbe associated with SiGe (approximately 0.70V as opposed to 1.40V with GaAs HBT), these devices may have significant performance advantages at low supply voltages.

9.5

Adjacent Channel Power Ratio In many kinds of wireless systems, there is a type of linearity metric called adjacent channel power ratio (ACPR) that is very closely linked to overall system performance [8]. An ACPR specification must be met if the equipment containing the power amplifier is to meet the goals of the system as a whole. ACPR is a measure of how efficiently a power amplifier (as well as other system components such as mixers) can suppress its nonlinear tendency to create intermodulation sidebands from the complex modulation spectrums associated with the standard system formats currently used in wireless communications. The level of intermodulation is of vital importance because, when transmitted, this energy represents noise to the users of adjacent channels. In order to prevent these noisy sidebands from becoming the limiting factor of the system’s overall signal-to-noise ratio, restrictions must be placed on their strength within the various network standards. In particular, the standards for CDMA systems contain very challenging ACPR specifications directly affecting the linearity requirement of the system’s transmitting power amplifiers. This is true of both base station power amplifiers and mobile (handset) power amplifiers. ACPR has come to be regarded as one of the key system specifications in many wireless systems and is of paramount concern for power amplifier designers. Figure 9.13 shows the spectrum of a power amplifier that is driven by a CDMA source. At low input power, the spectrum of output signal has adjacent channel sidebands that are far below the power contained in the main channel’s spectrum. However, at high

Figure 9.13 The spectrum of CDMA modulation as it appears for small-signal PA operation and for large-signal PA operation. The power levels in the adjacent channel sidebands increase profoundly at large-signal levels.

146

Power Amplifier Design

input (and output) power, the power contained in these adjacent channels increases quickly relative to the main channel power. In some cases, it may be necessary to turn down the amplifier’s power output (called “back-off”) in order to meet a given ACPR specification. Typical ACPR specifications for CDMA applications are on the order of –45 dBc for the first adjacent channel and –55 dBc for the second adjacent channel. Although ACPR is related to two-tone intermodulation, it is only correlated with OIP3 in practice and must be measured and simulated in its own right, not inferred from two-tone intermodulation data (see Chapter 10).

9.6

Error Vector Magnitude Error vector magnitude (EVM) provides a measure of how much phase distortion is occurring when an I/Q signal containing digital information is passed through a component or through a complete system. Within the constellation diagram of a phase-modulated signal (such as BPSK to QPSK), there are a number of phase states whose selection encodes the information contained in each symbol. This information remains undistorted only if the system’s output phase vectors arrive in exactly the same position on the constellation diagram as did the phase vectors at the input of the system. If the output signal has “shifted in phase” significantly relative to the input vectors (as shown in Figure 9.14), an error vector is generated that can cause bit errors. Since the error vector is of arbitrary phase, it is specified as a magnitude, which can be thought of as a fixed-length vector sweeping out in a circle centered on the original phase state locations. EVM is caused by both phase nonlinearity within the device or system and phase noise that is added to the output vector. Phase noise appears as a noise arc surrounding the initial phase state. Both phase nonlinearity and phase noise can cause bit errors. EVM is a very important metric in specifying the performance of WiFi and UWB systems. All high-data-rate, phase-modulated systems are subject to the limitations posed by the error vector magnitude of the system’s components.

Figure 9.14 A graphical representation of EVM as a vector whose magnitude represents the differences between an ideal phase vector at the input of a power amplifier and the actual phase vector that appears at the amplifier’s output.

9.7 Circuit Topologies for PAs

9.7

147

Circuit Topologies for PAs The typical unit of measure for power amplifier output power is the milliwatt. Expressed in decibels, the power output relative to a 1 mW reference is given by dBm = 10log(power in milliwatts)

(9.16)

Most applications specify RF power in dBms. The first step in determining a choice of circuit for a power amplifier is to determine the load resistance that the output matching circuit must present to the collector terminals of the amplifier’s RF transistor. This step requires knowledge of both the supply voltage and the transistor’s IV curves. It is also important to know the transistor’s dc current limit, based on reliability considerations, and its collector-to-emitter breakdown voltage. Given this information, the load resistance for the transistor may be determined graphically as shown in Figure 9.15 or by using (9.2). As demonstrated in Figure 9.15, it is sometimes useful to calculate the loadline resistance for the unit transistor (just one emitter), then scale the loadline resistance to larger transistors by simply dividing the unit cell loadline resistance by the total number of unit cells (number of emitter fingers). Once Rl is determined, the designer is in a position to synthesize an output matching network to provide the optimum output match to the transistor for obtaining maximum power output, best linearity, and highest efficiency. As an example, let us consider the design procedure of a simple power amplifier. We assume an output power of 1W is needed for the application. Let us assume that our amplifier will be operating in Class A at maximum efficiency for that class, which is 50 percent. This means the dc supply power must be 2W. Let us assume the availability of a 6.0V dc power source. This implies the amplifier’s dc current (Ic) is equal to 2W divided by 6V, which is 333 mA. If we assume a GaAs HBT process that has a maximum current per transistor unit cell of 10 mA, we know that our amplifier must have at least 333/10 = 33 transistor unit cells (emitter fingers) in the final amplifier stage. Based on the single-emitter-finger loadline calculation given in

Figure 9.15 Using IV curves generated by a generic Gummel Poon model for a single unit cell InGaP/GaAs transistor, the loadline resistance is determined to equal 580 ohms per cell for operation at Vcc = 6.0V and Ic = 10 mA. For a larger transistor, consisting of N unit cells in parallel, the loadline resistance is calculated as 580/N ohms.

148

Power Amplifier Design

Figure 9.15, we can calculate the loadline resistance necessary for our amplifier to produce maximum power and efficiency, as 580/33 = 17.5 ohms. This simple calculation tells us that based on 6V operation in class A, our amplifier must use a transistor with at least thirty-three emitter fingers in the final stage, and the output matching network must transform the 50 ohms external load impedance down to 17.5 ohms to be presented to the transistor’s collector-to-emitter terminals. The schematic shown in Figure 9.16 may be used to synthesize an output matching circuit to provide a loadline resistance of 17.5 ohms. Let us assume a simple series L, shunt C matching network as shown in Figure 9.16. Assuming an operating frequency of 2.5 GHz, it only takes a couple of iterations to home in on the final values for this simple matching circuit. The final choices are a series inductor of 1.5 nH and a shunt capacitor of 1.7 pF. Figure 9.17 shows a Smith chart display of the impedances produced at 2.5 GHz by selecting these matching element values.

Figure 9.16 A schematic diagram useful for synthesizing a matching circuit that provides the required loadline resistance at the transistor’s collector terminal.

Figure 9.17 The Smith chart display of the simulated loadline resistance provided by the matching network shown in Figure 9.16.

9.8 Matching Circuit Options

9.8

149

Matching Circuit Options Although the simple series L, shunt C matching network worked well in the previous example, it is important to be aware of various matching topologies that can be very useful in a wide variety of power amplifier applications. Roughly speaking, these matching networks are grouped into three types: low-pass-like, high-pass-like, and band pass. Examples of low-pass matching networks are shown in Figure 9.18. Examples of high-pass matching networks are shown in Figure 9.19. Examples of band-pass matching networks are shown in Figure 9.20. All of these networks may contain multiple sections with the accompanying increase in complexity. It should be said from the beginning that the best matching circuit is the simplest one. If you can get full performance with only a series inductor and a shunt capacitor, why not stay with that topology? Increasing the complexity of any circuit greatly increases the chance of problems, thereby greatly decreasing the likelihood of success. For this reason, it is very important to always, as a matter of course, stay with the simplest design. Add components or sections only when you have become convinced that the circuit cannot be made to work in any other way.

Figure 9.18

Two examples of low-pass output matching networks.

Figure 9.19

Two examples of high-pass output matching networks.

150

Power Amplifier Design

Figure 9.20

9.9

An example of a band-pass output matching network.

Stability Stability (and instability) is a major issue with any kind of amplifier. Positive feedback paths within an amplifier’s circuitry may cause the amplifier to become unstable at some frequency, possibly far removed from the design frequency. Instability of any kind is a major problem with amplifiers since these oscillations in effect render the amplifier useless for its designated purpose of amplification. Stability is measured by using a metric called the “k” factor (see Chapter 7). An amplifier is said to be unconditionally stable if its k factor is greater than 1.0 at all frequencies. If the amplifier’s k factor is less than 1.0 but greater than 0, the amplifier is said to be conditionally stable (it will not oscillate with 50 ohm source and load impedances, but with other impedances, it may oscillate). However, if the amplifier’s k factor is less than zero (i.e., negative), then the amplifier is said to be unstable and can expected to oscillate spontaneously at some frequency, even with 50 ohm source and load impedances. It is very important to test an amplifier for stability over a wide range of frequencies, particularly low frequencies. It is often at frequencies well below the design’s operating frequency that oscillations may occur. If oscillations do occur, there are several circuit techniques that can be used to correct the problem. First, if there is a problem with low-frequency instability, a series RL network (as shown in Figure 9.21) must be placed in shunt with the amplifier’s input to combat low-frequency instabilities effectively. If the stability problem is at frequencies higher than the operating frequency, a series RC network (as shown in Figure 9.22) placed in shunt with the amplifier’s input is very effective in curing high-frequency stability problems. If the stability problem is near the intended operating frequency, a simple technique for increasing stability is to place a low-value resistor in series with the transistor’s base. This resistor will reduce overall gain, improving stability accordingly. Other effective stabilizing techniques involve the addition of parallel or series “negative feedback.” These feedback networks, which are discussed in more detail in Section 9.12, are highly effective for improving stability, controlling gain, and improving linearity.

9.10

Bias Circuits In order to provide the necessary dc bias to a power amplifier’s RF transistors, it is necessary to provide certain circuits that can insert bias voltages and currents without disturbing the RF circuit’s basic behavior. The first such circuit, shown in Figure 9.23, is very useful for connecting supply voltage and current to the RF transistor’s

9.10 Bias Circuits

151

Figure 9.21

An input circuit for stabilizing a bipolar amplifier at low frequencies.

Figure 9.22

An input circuit for stabilizing a bipolar amplifier at high frequencies.

collector. This simple circuit makes use of one inductor, called a choke, and two capacitors. The series capacitor is called a dc block, and the shunt capacitor is called a bypass capacitor. It is the purpose of both capacitors to provide very low reactance at the operating frequency but very high reactance at low frequencies (infinite reactance at dc, of course). It is the purpose of the choke inductor to provide very high reactance at the operating frequency but very low reactance at low frequencies (zero reactance at dc, of course). It is important, especially in the case of RF transistors, which require very high dc currents, to choose a choke inductor with very low dc resistance so that little or no dc voltage drop develops across the choke. This requirement often means that on-chip spiral inductors are unsuitable for high-current choke applications because of their relatively high dc resistance. If this is the case, the designer must acknowledge the necessity of placing this choke inductor off-chip, as undesirable as that may sound. In terms of inductance values, a common condition for choosing the choke inductor is to be sure its reactance at the operating frequency is high compared to a 50 ohm load impedance. This requirement is usually met if the choke’s inductance is greater than 100 ohm at the operating frequency, Fo, which means, 2 FoLc > 100 ohm

(9.17)

152

Power Amplifier Design

Figure 9.23 The combination of a choke inductor, a blocking capacitor, and a bypass capacitor supplies collector bias to a bipolar power amplifier.

In a similar fashion, the dc-blocking capacitor and the bypass capacitor must have reactance below about 1 ohm at the operating frequency, Fo, which means, 1/2 FoCb < 1 ohm

(9.18)

As in the case of the choke inductor, these capacitors may or may not be located on-chip, depending on their size and how much chip area is occupied by a capacitor of this size. The final decision is often purely economic. Now we consider the circuit requirement for base biasing. Referring to Figure 9.24, we see the simplest of all base-biasing circuits. This circuit is nothing more than a resistor attached between the transistor’s base and a voltage source. If the voltage source exceeds the transistor’s turn-on voltage, Vbe, current will flow in the base-to-emitter junction, biasing the transistor with a base current of Ibase = (Vdc – Vbe)/Rbase

(9.19)

where Ibase is the RF transistor’s base current. Vdc is the base supply voltage. Rbase is the circuit’s resistance.

Figure 9.24 A simple base-biasing network composed of a resistor, a blocking capacitor, and a dc voltage supply.

9.10 Bias Circuits

153

Ibase should be set to produce the desired dc collector current, Ic, according to the relationship Icollector =

× Ibase

(9.20)

where is the transistor’s current gain (about 100 with most RF transistors). Icollector is the transistor’s saturated collector current. With this circuit, Vdc acts as a direct controlling element for setting Icollector, which can be extraordinarily convenient. However, this simple circuit is not very stable over temperature since Vbe shifts at high and low temperatures causing changes in Ibase and Icollector. For this reason, more stable base-biasing circuits have been developed with the intention of overcoming these temperature-drift problems. The simplest of these alternative base-bias circuits, as shown in Figure 9.25, involves the use of a second resistor, RB1, connected from the base node to ground. In this case, the series combination of the two resistors forms a voltage divider, which maintains a more constant voltage at the transistor’s base terminals. This circuit stabilization of the base voltage will stabilize the base and collector currents over a wide temperature range. In order to make this circuit work effectively, it is necessary that the current flowing through the resistor divider be somewhat greater than the current flowing into the transistor’s base. Resistor values must be chosen accordingly to insure that this condition is met. The trade-off here is that lowering the resistor values improves base voltage stabilization but increases the amplifier’s overall current consumption. In handheld, battery-powered applications, where the requirements are sensitive to all sources of current, base bias current can become a problem for overall current budgets. A second method for stabilizing base and collector currents is called current mirror biasing. The schematic diagram showing a current mirror circuit is presented in Figure 9.26. In current mirror circuits, a second transistor (area = A2), which is smaller than the RF transistor (area = A1), is configured so that its base-to-emitter junction is connected from ground to the base-to-emitter junction of the RF transis-

Figure 9.25 A slightly more complex base-biasing circuit for stabilizing the transistor’s base current and collector current over temperature.

154

Power Amplifier Design

Figure 9.26 A current mirror base-biasing circuit that stabilizes an RF transistor’s collector current against temperature and process variations. The ratio of the mirror transistor current, Im, to the RF transistor’s collector current, Ic, is simply equal to the ratio of the two device areas. The mirror transistor’s control voltage may be used as a collector current adjustment for power-output control purposes.

tor though an RF choke. Current is supplied to the mirror transistor via a resistor, Rm, and a voltage source, Vmirror. Since the base-to-emitter junctions of the two transistors are hardwired together (at dc), the two devices track each other over temperature, and as a result, temperature variations in the RF transistor’s collector current are cancelled out. However, the absolute level of the RF transistor’s collector current is controllable with the voltage source, Vmirror. This gives the supply Vmirror the ability to control Icollector, which can be very useful in certain applications. Power amplifiers requiring the ability to control their power output can be designed in this way. The value of the mirror current, Im, is calculated with the following expression: Im = (Vmirror – Vbe)/Rm

(9.21)

where Vbe is the base-to-emitter turn-on voltage for the A2 transistor (1.40V for InGaP/GaAs and 0.70V for SiGe). Under these conditions, the RF transistor’s collector current may be calculated from Icollector/Im = A1/A2

(9.22)

Notice that (9.22) does not contain any dependence on temperature but is a simple ratio between collector current and mirror current that depends on just the ratio of the area of the RF transistor (A1) and the mirror transistor (A2). Current mirror biasing is used extensively in many applications and is a straightforward way to ensure stability of the device’s operating point, while at the same time offering the ability to control the amplifier’s dc current from an external voltage source.

9.11

Design Example 3: Wideband Gain Block Darlington Amplifier Darlington amplifiers are a unique class of RF amplifier having some very important properties, making them well suited for a wide variety of applications. In particular,

9.11 Design Example 3: Wideband Gain Block Darlington Amplifier

155

Darlington amplifiers are often found in cellular and PCS infrastructure applications. The most important advantage of the Darlington amplifier circuit is its extreme simplicity. The basic Darlington amplifier circuit consists of only two transistors, four resistors, no capacitors, and no inductors. A second major advantage of the Darlington circuit is its extremely broadband frequency coverage. Darlingtons are often designed to produce a flat gain response from dc to well over 10 GHz. However, P – 1 dB and OIP3 may roll-off over the amplifier’s useful bandwidth, making Darlington amplifiers less suitable for operation at high frequencies than at low frequencies. The gain of a Darlington is controlled to the first order by a single resistor R1, which controls the amount of negative feedback at work within the amplifier. By selecting R1 to be 1,000 ohms or more, a Darlington amplifier working into 50 ohms source and load impedances will have a flat gain of 20 dB or more. However, this high gain trades off with linearity (OIP3), which is degraded from its optimum value if the feedback resistor is set for high gain. If the value of R1 is less than 500 ohms, the gain is reduced to 12 to 15 dB; however, linearity (OIP3) may improve by as much as 3 to 4 dB. The designer needs to be aware of this trade-off to properly tailor a Darlington amplifier’s design for the requirements of a given application. Depending on transistor size, the power output of a Darlington (operating at low frequencies) may be as high as +25 dBm, and its OIP3 may be as high as +40 dBm. These performances trade off with the maximum frequency for flat gain through the sizing of the transistors. The transistors in a Darlington amplifier usually have a 1:3 area ratio between the first and the second transistor. However, this rule is not hard and fast, and many Darlington amplifiers are successfully designed with area ratios from 1:2 to 1:5. Figure 9.27 shows the schematic of a basic Darlington amplifier circuit. Resistor R3 is used to create a voltage drop, which biases the base of the second transistor up to Vbe in order to turn it on. It is straightforward to calculate the value of R3 based on Vbe of the technology choice (about 1.4V for GaAs HBT and 0.70V for SiGe) and the maximum allowable dc current in the first transistor (I q1max). R3 = Vbe/Iq1max

(9.23)

R2 is calculated from the condition that the base of the first device (Q1) must be biased to at least 2Vbe above ground (since its emitter is attached to R3, which is already above ground by Vbe), and the current that flows through R1 is approximately the same as the current that flows through R2. This condition takes the form of the following equation: R2 = 2VbeR1/(Vcc – 2Vbe)

(9.24)

where Vcc is the dc supply voltage. The value of R4 should be in the range of 5 ohms to 10 ohms, and its final selection will depend on obtaining a minimum value for S22 during simulation. A first estimate of the amplifier’s gain in its flat region can be made by treating the Darlington amplifier just like any other amplifier with internal negative feedback. Assuming the source impedance is 50 ohms, the feedback resistor, R1, will determine the amplifier’s gain according to

156

Power Amplifier Design

Figure 9.27 The basic schematic diagram of a wideband Darlington amplifier using InGaP/GaAs technology.

G = 20log(R1/50)

(9.25)

If R1 assumes a value of 1,000 ohms, (9.25) predicts a gain of 26 dB, which can be approached in certain very ideal situations. Device sizing is more of an exercise in determining what frequency range the application requires and what its power and OIP3 requirements are. Darlington amplifiers typically have a PAE of 15 to 25 percent, which means that in order to increase the power output to some desired level, the devices must be sized accordingly. Assuming a 1:3 area ratio between the first and the second device, it will be necessary to increase device current sufficiently so that the device’s overall power consumption is greater than Pout/PAE, where we can estimate that PAE is about 20 percent. The trade-off here is that for higher power output, the larger devices needed to supply the power will have much larger parasitic elements than the smaller, lower-power devices. The larger device size will accordingly limit the highest useful frequency of the amplifier as a result of the parasitic effects. Therefore, we recognize that another basic trade-off with Darlington amplifiers exists between power (and OIP3) and upper useful frequency. For practical experience it appears that about +25dbm is an upper limit on a Darlington’s power output, if wideband operation is to be maintained. As an example of a Darlington amplifier design, consider the schematic diagram for the transistor-level circuit (including all element values) of a simple Darlington amplifier shown in Figure 9.28. This amplifier will operate from a supply voltage of 5.0V. The element values are based on choosing R1 to be 1,000 ohms (for high gain), a first transistor area of one emitter finger, and a second-transistor area of three emitter fingers. Additionally, we assume the maximum dc current is 10 mA per transistor emitter finger, and Vbe = 1.4V (GaAs HBT). R2 is calculated from (9.24) to be 1,500 ohms. R3 is calculated from (9.23) to be 140 ohms. Based on these circuit choices (plus choosing R4 to be 1 ohm), we obtain simulated small-signal S-parameters in the purely lumped-element case, as shown in Figure 9.29. Notice that the gain at 2 GHz is slightly over 20 dB, which is an excellent gain for such a simple amplifier circuit. However, the noise figure at 2 GHz is 4.4 dB, which is only a fair noise-figure performance at this frequency. The reason for the fair noise-figure performance is the placement of resistors R1 and R2, which are directly connected the amplifier’s input. These two resistors function as an attenuator, directly adding

9.11 Design Example 3: Wideband Gain Block Darlington Amplifier

Figure 9.28

157

The schematic diagram of a wideband lumped-element Darlington amplifier.

to the amplifier’s noise figure. For this reason, Darlington amplifiers are not recommended for low-noise amplifier applications. In a similar fashion, the Darlington amplifier’s power output and OIP3 can be simulated based on the lumped-element schematic shown in Figure 9.28. These simulations are shown in Figures 9.30 (Pin versus Pout) and 9.31 (OIP3). The next step in the process of designing this Darlington amplifier is to perform an IC layout for its circuit using the design rules for the foundry that has been chosen to perform the wafer fabrication. We will do this layout based on the InGaP/GaAs HBT process design rules outlined in Chapter 4. Figures 9.32 and 9.33 show the layout of one such amplifier, including “blow-ups” of critical areas.

Figure 9.29 The simulated S-parameters and noise figure for the lumped-element Darlington amplifier shown in Figure 9.28.

158

Power Amplifier Design

Figure 9.30 The simulated power input versus power output for the lumped-element Darlington amplifier shown in Figure 9.28.

Figure 9.31 The simulated third-order intermodulation intercept point for the lumped-element Darlington amplifier shown in Figure 9.28.

As a result of performing the layout, the designer becomes aware of certain areas of the circuit that have become subject to parasitic effects. For instance, the bonding pads at the amplifier’s input and output are in fact short microstrip transmission lines. Also, the resistors have physical length in the layout, and this length must also be modeled, indicating a microstrip transmission line parasitic elements in series with each resistor. For this amplifier, we stop the parasitic element identification process at this point, but in reality we could also add transmission line associated with some of the interconnecting metal lines, such as the line connecting the emitter of the first transistor to the base of the second transistor. Figure 9.34 shows the amplifier’s transistor-level schematic diagram, including parasitic elements. After rerunning the simulations (i.e., postlayout simulations), the resulting simulations for small-signal S-parameters, power output, and OIP3 are shown in Figures 9.35 to 9.37, respectively.

9.11 Design Example 3: Wideband Gain Block Darlington Amplifier

159

Figure 9.32 The layout of the Darlington amplifier whose lumped-element schematic diagram is shown in Figure 9.28. Input is on the left.

Figure 9.33

A blow-up of a portion of the Darlington amplifier’s layout.

In fact, in this particular case there is not much change in performance associated with the introduction of the parasitic elements created by performing the layout, as compared to the purely lumped-element case. In Figure 9.35, there is some tendency toward increased high-frequency gain roll-off, but at 2 GHz (we assume 2 GHz is the application’s frequency of primary interest), the gain remains about 20 dB, the power output at 1 dB gain compression remains about +15 dBm, and OIP3 remains about +27 dBm. Next, consider an alternative approach for this amplifier. The previous Darlington amplifier layout used an approach with all transistor emitter fingers arranged in a vertical orientation (as shown semischematically in Figure 9.38). An example layout using a vertical emitter finger orientation is shown in Figure 9.39. As an alternative, consider a layout with horizontally arranged transistor emitter fingers, shown semischematically in Figure 9.40. An example layout using a horizontal emitter ori-

160

Power Amplifier Design

Figure 9.34 The schematic diagram of the Darlington amplifier in Figure 9.28, including layout parasitic elements.

Figure 9.35 The simulated S-parameters and noise figure for the Darlington amplifier shown in Figure 9.34 (including layout parasitic elements). Notice the high-end gain reduction.

entation is shown in Figure 9.41. The advantage of this approach is its ability to decrease the overall distance between the individual transistor unit cells, potentially reducing parasitic effects. However, in some cases, these parasitic effects are useful for enhancing certain performance parameters. For instance, the metal line between the first transistor’s emitter and the second transistor’s base can be optimized to create a gain peaking effect, which may be useful for increasing the amplifier’s overall bandwidth. As shown in Figure 9.42, for the zero parasitic case, the amplifier’s gain as a function of frequency is very flat until a certain critical frequency is reached (about 5GHz), above which the gain rolls off smoothly. However, if the length of the

9.11 Design Example 3: Wideband Gain Block Darlington Amplifier

161

Figure 9.36 The simulated power input versus power output for the Darlington amplifier shown in Figure 9.34 (including layout parasitic elements).

Figure 9.37 The simulated OIP3 as a function of frequency for the Darlington amplifier shown in Figure 9.34 (including layout parasitic elements).

line from emitter 1 to base 2 is increased and optimized, the amplifier’s gain may be peaked at the critical frequency in such a way that the overall bandwidth is increased by as much as 30 percent. In this case, we say the Darlington amplifier is experiencing “parasitic-enhanced” performance. Another example of parasitic-enhanced performance is the optimization of the inductive line length associated with the connection between the second transistor’s emitter and ground (through resistor R4). If this inductive line length parasitic is optimized, the amplifier’s S11 and S22 may be reduced in magnitude by as much as 6 dB relative to the lumped-element case, as shown in Figure 9.43. This inductance may be created in one of three possible ways (or a combination of all three). The first is the natural transmission line behavior of the layout of R4. The second is a metal line connecting the emitter of the second transistor to R4, then connecting R4 to ground. The third method of increasing this

162

Power Amplifier Design

Figure 9.38 A semischematic layout of a Darlington amplifier with its transistor emitter fingers aligned in a vertical direction. This layout is intended to reduce performance-limiting layout parasitic elements.

Figure 9.39 A layout example of a Darlington amplifier with vertically aligned emitter fingers. The spiral inductor in the emitter of Q2 is a series feedback element for improving the input and output match. Input is on the left.

Figure 9.40 Semischematic layout of a Darlington amplifier with its transistor emitter fingers aligned in a horizontal direction. This layout is intended to reduce performance-limiting layout parasitic elements.

emitter-to-ground inductance is to use a spiral inductance (as shown in Figure 9.39), whose value is optimized to provide the lowest value of the magnitude of S11 and

9.11 Design Example 3: Wideband Gain Block Darlington Amplifier

163

Figure 9.41 A layout example of a Darlington amplifier with horizontally aligned emitter fingers. Metal emitter extension lines provide inductive series feedback to improve match. Input is on the left.

Figure 9.42 The simulated S-parameter performance of a typical Darlington amplifier without layout parasitic elements. Notice that the input and output matches degrade at high frequencies as a result of parasitic elements in the transistor’s model.

S22. This inductance is also helpful in terms of enhancing the amplifier’s stability, as shown in Figure 9.44. The right amount of this inductive parasitic element helps the performance of the amplifier in more than one way and should definitely be considered when performing the amplifier’s layout. A parasitic element that degrades stability and should be avoided is the parasitic shunt capacitance to ground at the second transistor’s emitter. This element may be a natural result of the physical area of the resistor R4 and its connecting metal. Unfortunately, stability is compromised by the presence of this parasitic shunt capacitance. In order to keep this element to a minimum and to keep stability high, it is very important to keep the width of R4 to a minimum and avoid any wide metal interconnects between the transistor’s emitter and R4 and/or the connection of R4 to ground. All of these parasitic elements must be carefully modeled as part of the postlayout simulation process to ensure that the parasitic elements are of such dimensions that they work in favor of enhanced performance and do not degrade overall performance.

164

Power Amplifier Design

Figure 9.43 The simulated S-parameter performance of the same Darlington amplifier, including the effect of parasitic inductance resulting from Q2’s emitter resistor’s length (le2x). As the emitter resistor is made longer (raising the inductance), the input and output match improve at high frequencies because of the presence of inductive series feedback.

9.12

Design Example 4: Feedback Power Amplifier Design Feedback amplifier circuits are very popular topologies for RF power amplifiers [9]. Feedback amplifiers offer the best overall power, efficiency, stability, and linearity among all power amplifier topologies. They also have the ability to suppress harmonics and other spurious products. However, they are often inherently narrowband and are typically suitable only for single-frequency operation. Feedback amplifiers can achieve nearly 50 percent efficiency in class A operation. Power output with a feedback amplifier can easily exceed +33 dBm, and OIP3 can be over +50 dBm. Feedback can be applied in one of two ways [10]. Parallel feedback is usually applied as a series resistor-capacitor combination that connects the RF transistor’s base to its collector. The main purpose of the capacitor is to provide a dc block so that the high voltage at the collector does not disturb the base-biasing circuit. The

Figure 9.44 The simulated stability (k factor) performance of the Darlington amplifier associated with Figure 9.42. This simulation demonstrates how parasitic inductance associated with emitter resistor length (lng) can improve an amplifier’s stability.

9.12 Design Example 4: Feedback Power Amplifier Design

165

value of the resistor in a feedback network controls the amount of feedback that is applied. This feedback resistor plays a very similar role as R1 in the Darlington amplifier. If the feedback resistor is high in value, the gain of the amplifier will be high, but the linearity (i.e., OIP3) will suffer. If the feedback resistor’s value is lower, more feedback will be applied, and the amplifier’s linearity (OIP3) will increase; however, this reduction in the feedback resistor’s value will cause the amplifier’s gain to suffer. This gain-versus-OIP3 trade-off is very fundamental and cannot be significantly altered. A second form of feedback is called series feedback, which often consists of placing an inductor between the RF transistor’s emitter and ground. This form of series feedback is highly effective in providing enhanced stability for an amplifier that is marginal in this respect. However, a major drawback to this kind of feedback is that the inductor placed between the RF transistor and ground is required to carry the amplifier’s full dc collector current, which can be over 1A in the case of transmitting amplifiers in wireless applications. This high dc collector current will require a very wide metal trace if an on-chip spiral inductor structure is to be used. For this reason alone, it is best not to use series feedback in amplifiers whose power output is higher than about +25 dBm. The basic feedback amplifier circuit schematic diagram, containing both types of feedback, is shown in Figure 9.45. This circuit contains only feedback and bias elements; no matching elements are included. Such a circuit is often too simple to be useful. In particular, the output circuit needs to contain matching capabilities in order to provide the proper Rl for maximum power and maximum efficiency at the RF device’s collector-to-emitter terminals. The matching circuit topologies of a feedback amplifier are often the same topologies that have already been developed in Section 9.8. With little or no feedback applied to the circuit, the design process should begin with proper matching elements attached to the collector terminals in order to provide the correct Rl without the presence of feedback. As feedback is applied, these element values may have to be modified to achieve peak performance. However, most successful feedback amplifier designs begin as a simple matched amplifier design. Feedback amplifiers often use RF transistors that are quite large. This is especially true in power amplifiers required to operate from low-voltage supplies, such as power amplifiers for handheld, battery-operated applications where the supply voltage is 3.3V. These transistors must be large because they provide the high RF current swings required to generate high power output at such low supply voltage (low RF voltage swings are associated with low dc supply voltage). Such RF transistors may contain between fifty and one hundred emitter fingers. It is very important that such transistors be laid out in a careful way in order to avoid a kind of internal instability within the transistor’s own structure. This instability, which is often called the even-odd mode instability, is associated with the transmission line properties of the metal lines that interconnect the transistor unit cells. In particular, in very large transistors, the unit cells farthest away from each other in the layout may operate at different RF voltage potentials. Such behavior will lead to a kind of signal teeter-totter behavior that causes oscillations to occur at frequencies significantly higher than the design’s operating frequency (5 to 8 GHz is the usual range for these oscillations). The best way to

166

Power Amplifier Design

Figure 9.45 The schematic diagram of a power amplifier that makes use of both parallel and series feedback.

avoid these problems is to place a limit on the number of transistor unit cells connected together in a row to less than fifteen. For instance, in a typical large transistor, only twelve unit cells are connected together in a single row. The transistor’s emitter contacts are all connected together via a first-metal contact, which is grounded directly to a substrate via. In order to increase the overall count of unit cells to that required by the design, it is good practice to have many rows of unit cells that are connected in parallel. In this example, we have only two rows; however, this could be easily increased to four rows simply by copying the initial two rows and reproducing this pattern as many times as necessary. It is good practice that all the collector contacts from both rows are connected together at common collector “manifold.” It is very important for stability reasons that these collector manifolds electrically close around the entire transistor in order to prevent even-odd mode oscillations from developing between opposite ends of the transistor. The collector manifold can be “closed” on the left-hand side of the transistor if the closing connection uses metal 1 (using two M1-to-M2 vias). In any event, the key to avoiding the kind of instabilities associated with the transistor’s layout is to be sure there are no more than fifteen unit cells in any row and that all collector connections are made directly to a common “manifold” that always electrically closes on itself, ensuring that all unit cell collectors are at the same potential. Another important issue to consider in the design of large transistors for power amplifier service is ballasting. Conceptually, ballasting is closely related to the requirement that a heavy lead weight be built into sailboats’ keels to prevent the boat from tipping too far one way or another in heavy wind or high seas. Consider the schematic diagram of a large RF transistor shown in Figure 9.46. If the most distant unit cells within the transistor’s layout are operating at slightly different temperatures, there will be small differences between these cell ’s by virtue of their temperature differences. Now if increases with increasing temperature, the unit cell with a slightly higher temperature than the other cell transistors will experience slightly higher collector current. Higher collector current will mean a still further increase in temperature within this “hot” unit cell, leading to a situation called thermal runaway. It is also called current hogging because, ultimately, one of the unit cells (the one that was initially slightly hotter than the others) will carry most of the current, becoming very hot, and will surely fail. To avoid failures of this kind, it is necessary to include what are called ballasting resistors between the emitter and ground of each unit cell. When the current in a particular cell increases due to current hogging, the voltage drop

9.12 Design Example 4: Feedback Power Amplifier Design

167

across the ballasting resistor will reduce the cell’s Vbe, reducing its current and returning the transistor to thermal stability. Ballasting resistors are usually designed to provide about twice the thermal voltage (i.e., thermal voltage = kT/q = 25 mV at room temperature, where k is Boltzmann’s constant, and q is the charge on an electron). This means the value of the ballast resistor associated with each unit cell (for InGaP/GaAs) is Runitcell = 50 mV/10 mA = 5 ohms

(9.26)

The total ballasting resistance, Rballast, that must be placed in the simulation schematic will be the ballasting resistance per unit cell calculated from (9.26) divided by N, the total number of unit cells that make up the transistor (since they are all connected in parallel). Rballast = Runitcell/N

(9.27)

It is only necessary to include ballasting resistors if the number of unit cells in an RF power transistor exceeds ten. For transistors with fewer than ten unit cells, the temperature difference between unit cells is too small to create thermal instability problems. In practice, ballasting resistor layouts are often configured in the form of interdigitated resistors, as shown in Figure 9.47. With this technique, each emitter M1 contact is interdigitated with an equal number of M1 ground fingers. A line of TFR material is drawn across this array of emitter and ground contacts to form an array of ballasting resistors. Each resistor has a value of Runit = (L/W) 50 ohms

(9.28)

where L is the spacing between the emitter fingers and the ground fingers. W is the width of the TFR material.

Figure 9.46 The schematic diagram of a large transistor, including ballasting resistors that connect each unit cell’s emitter contact to ground. These ballast resistors prevent a dc instability called current hogging and thermal run away.

168

Power Amplifier Design

Figure 9.47 A ballast resistor layout example showing how the M1 and TFR configurations work together to create a series of interdigitated ballast resistors for use in large multi-emitter-finger transistors.

Since each transistor unit cell has two of these interdigitated resistors associated with it, the total ballast resistance associated with each transistor is Runit/2. This means that if Runit is 10 ohms, then Runitcell = 5 ohms. An example of a feedback power amplifier design is shown in the transistor-level schematic of Figure 9.48. This amplifier makes use of parallel negative feedback, which is provided by a series combination of a 1,000 ohms resistor and a 10 pF capacitor connected between the amplifier’s base and its collector. The amplifier has been uniquely designed to have a loadline resistance of 50 ohms under 5V operation, which means that no output matching (i.e., transformation of the 50 ohms load) is required to produce the maximum output power, which is about +24 dBm. The amplifier has been designed to operate at 2.45 GHz for WiFi b and g applications. The only matching elements in this amplifier are in the input circuit and consist of a single-section low-pass circuit. This amplifier can immediately be converted to a layout-ready schematic using spiral inductors, as shown in Figure 9.49. The amplifier’s layout is given in Figure 9.50. The major parasitic elements associated with this layout is the conversion from the lumped inductors in the input matching circuit to physical spiral inductors. The ADS MRIND element is used to model the spiral inductor. By using simulations to associate ideal lumped inductors with spiral inductors (see Chapter 6), the element values in MRIND are adjusted to produce exactly the impedance value of the lumped-element inductor at the operating frequency. It is good practice to design the width of the inductor’s metal trace (W) to be consistent with the maximum dc current that could flow in the inductor. The inductor may be either metal 1 or metal 2. The only difference is that if the inductor is metal 1, it will require a metal 2 “overpass” to complete the path (as shown in Figure 9.50), and if it is metal 2, it will require a metal 1 “underpass” to complete the path. Usual practice is to use a trace spacing (S) equal to the metal width (W). However, if S is made less than W, some additional inductance can be achieved for a given spiral area by increasing the mutual inductance between the windings.

9.12 Design Example 4: Feedback Power Amplifier Design

169

Figure 9.48 A lumped-element circuit schematic for a feedback power amplifier example, which contains low-pass input matching and parallel feedback. Since the optimum loadline resistance for this amplifier is 50 ohms, no output matching elements are required to achieve maximum power and efficiency. The inductors associated with the input matching circuit each have an internal resistance of 10 ohms.

Figure 9.49 The schematic diagram for the circuit shown in Figure 9.48 after modification to include spiral inductors in the input matching network to model the parasitic effects of layout.

The post layout simulated S-parameters are given in Figure 9.51. It turns out that the input match and the gain have all improved relative to the lumped-element case. This is because in the lumped-element case, a 10 ohms series resistor was associated with each lumped-element inductor in order to create acceptable stability and input match (S11). However, by switching to spiral inductors for the layout phase, the natural loss associated with the spiral inductors is just sufficient to provide acceptable stability and S11 without degrading gain as much as was done by the 10 ohms resistors in the lumped-element case. This is another example of how layout parasitics can improve, and do not always degrade, performance. Figures 9.52 and 9.53 show the post layout Pin versus Pout and OIP3. About 1 dB of performance was lost in both P – 1 dB and OIP3 due the presence of the spiral inductors in the layout. This can only be understood by recalling that in a feedback amplifier design, a significant amount of the amplifier’s output power is recirculated to the amplifier’s input as part of the negative feedback process. This loss of about 1 dB in power output performance between the lumped-element case and the post layout simulations is not unusual, and in fact, it is best to plan on this level of performance degradation.

170

Power Amplifier Design

Figure 9.50

The layout of the feedback power amplifier circuit shown in Figure 9.49.

Figure 9.51 The simulated S-parameters of the modified feedback power amplifier, including layout parasitic elements (i.e., spiral inductors in this case).

9.12 Design Example 4: Feedback Power Amplifier Design

171

Figure 9.52 The simulated power input versus power output and 1 dB gain-compression point for the feedback power amplifier, including layout parasitic elements.

Figure 9.53 The simulated OIP3 versus frequency for the feedback power amplifier, including layout parasitic elements.

References [1] [2] [3] [4] [5] [6]

Sweet, A., MIC and MMIC Amplifier and Oscillator Circuit Design, Norwood, MA: Artech House, 1990. Cripps, S., RF Power Amplifiers for Wireless Communication, Second Edition, Norwood, MA: Artech House, 2006. Cripps, S., Advanced Techniques in RF Power Amplifier Design, Norwood, MA: Artech House, 2002. Kenington, P., High Linearity RF Amplifier Design, Norwood, MA: Artech House, 2000. Maas, S., Nonlinear Microwave Circuits, Norwood, MA: Artech House, 1998. Niclas, K., “Reflective Match, Lossy Match, Feedback and Distributed Amplifiers: A Comparison of Multi-Octave Performance Characteristics,” IEEE MTT-S Symp. Digest, 1984, pp. 215–217.

172

Power Amplifier Design [7] Cripps, S., “A Method for the Prediction of Load-Pull Power Contours in GaAs MESFETs,” Proc. IEEE Intl. Microwave Symp., MTT-S, 1983, pp. 221–223. [8] Kenney, J., and Lake, A., “Simulation of Spectral Regrowth, Adjacent Channel Power, and Error Vector Magnitude in Digital Cellular and PCS Amplifier Design,” Microwave J., October 1995. [9] Gupta, M., “Power Gain in Feedback Amplifiers, a Classic Revisited,” IEEE Transactions on MTT, MTT-40, May 1992, pp. 864–879. [10] Vendelin, G., et al., Microwave Circuit Design Using Linear and Nonlinear Techniques, New York: John Wiley and Sons, 1990.

CHAPTER 10

Designing Multistage Amplifiers 10.1

Multistage LNAs Multistage amplifiers hold unique challenges in making sure that each stage in a cascade is designed just right to provide sufficient power output and OIP3 in order to drive the following stage to its full output capabilities. However, it is very important that no stage be overdesigned so that its power output and OIP3 capabilities go to waste, degrading overall efficiency by draining more dc current than is absolutely necessary for achieving full performance. In particular, LNA’s require that multistaging achieve certain important specialized goals. The first stage of any multistage LNA is of critical importance for determining the LNA’s overall performance. The first stage is the primary determiner of overall LNA noise figure. Also, second-stage noise-figure contributions are inversely proportional to the gain of the first stage. Therefore, it is of paramount importance to make the noise figure of the first stage as low as possible, while at the same time making the gain of the first stage as high as possible [1]. If the first-stage gain is very high (above 12 dB), the second stage will make only a minimal contribution to the overall noise figure of the cascaded LNA, providing its noise figure is not excessively high. All low-noise amplifiers have an input match, called Γopt, which represents the impedance that must be presented to the device’s input terminals in order to realize that device’s minimum noise figure. In an ideal low-noise amplifier, the Γopt of each stage would be presented to the input of that stage’s device, as shown in Figure 10.1. In order to do this, it will be necessary to configure the output matching of each stage so that it provides just the right impedance at its output terminal, enabling the following stage to experience the right Γopt at its input. Figure 10.2 shows how this requirement is played out at the transistor level. M1 is the LNA’s input matching circuit providing Γopt1 to the first stage. The interstage matching network between stages one and two is M2. At its output, M2 provides Γopt2 for the second-stage device. The same process is repeated at the third and any subsequent following stages. As shown in Figure 10.3, the matching process for an LNA always starts at the input and works towards the output. First, M1 is designed to apply the best match for both noise figure (Γopt1) and gain to transistor Q1. Next, M2 is synthesized to provide both the best output match for gain at Q1 and also to present Γopt2 to the input of Q2 to optimize the noise figure and gain of transistor Q2. The same process can be repeated for any number of following stages, but in practice, most multistage LNA noise-figure contributions come from the first and second stage (primarily from the first stage), so it is very rare to need to continue this design

173

174

Designing Multistage Amplifiers

Figure 10.1 To achieve the minimum noise figure with a cascaded low-noise amplifier, it is necessary to provide the correct Γopt at the input of each stage’s transistor.

Figure 10.2 Interstage matching networks M2 and M3 provide the correct Γopt to the input of the transistors in stages 2 and 3. Network M1 provides the correct Γopt to the transistor in stage 1.

Figure 10.3 The matching process in a multistage LNA starts at the input and proceeds to the output. Because of second-stage contribution effects, for most LNAs it is only necessary to provide Γopt to stage 1 (and possibly stage 2), provided that the gain of stage 1 is high.

procedure past the second stage. In most cases, an LNA with more than two stages would have stages three, four, and so on, designed strictly for maximum gain. A software tool that is most valuable in designing multistage LNA’s is AppCAD from Agilent, Inc. This downloadable program allows the user to fill in the noise figure, gain, and OIP3 of each stage, and the program calculates the total performance of the cascade. While AppCAD will not provide impedance matching information, it will allow the designer to determine quickly if a given architectural lineup of stages can meet a given set of top-level specifications for a particular application. An example of an AppCAD calculation is shown in Figure 10.4. In AppCAD, filters and other passive devices are treated as amplifiers with negative gains equal to their loss and a noise figure also equal to their loss. In most cases, passive devices will be represented by a very high value of OIP3 (above +50 dBm), unless there is reason to think a particular passive device will have a lower OIP3 for unique reasons.

10.2 Multistage Power Amplifiers

175

Figure 10.4 An AppCAD calculation of the gain, noise figure, and intermodulation intercept point of a single-conversion superheterodyne receiver.

10.2

Multistage Power Amplifiers In the case of multistage power amplifiers, it is very important to predetermine the exact value for the loadline resistance for maximum power output associated with each stage. It is this knowledge of the stage-by-stage loadline resistance that allows a designer to tailor each stage of a multistage power amplifier so that every stage is running at its correct maximum power output and efficiency for its particular place in the cascade. To facilitate this process, it is always a good practice to start a multistage power amplifier’s design at the output and work toward the input. The first step is to calculate the loadline resistance of a single-emitter-finger unit cell transistor operating at the supply voltage, as shown in Figure 10.5. Once this is accomplished, it is relatively easy to size the loadline resistance for the various stages of the amplifier by simply dividing the unit cell loadline resistance by the number of unit cells needed to achieve the required power level at a given stage. As shown in Figure 10.6, each stage must have its proper loadline resistance presented to the collector terminals of its transistor, starting with the final stage (the Nth stage) and progressing backwards to the first stage. As seen in Figure 10.7, each stage’s input impedance is transformed through an interstage matching network in order to present the required loadline resistance to the preceding stage. This process starts with the matching elements that transform the ultimate 50 ohms output load impedance to the correct loadline resistance for the last stage, then proceeds back through the entire amplifier chain, ensuring that the RF transistor in each stage will be terminated into its optimum loadline resistance based on its size. The next step in the

176

Designing Multistage Amplifiers

Figure 10.5 Using the generic Gummel Poon device model for an InGaP/GaAs unit cell transistor, the class A loadline resistance for the unit cell operating at Vcc = 3.0V and Ic = 10 mA is calculated to be 225 ohms. Under these bias conditions, the parallel combination of N such unit cells would have a class A loadline resistance of 225/N.

Figure 10.6 In order for a multistage power amplifier to generate its maximum possible power output, it is necessary that the correct loadline resistances (RL3, RL2, and RL1) be presented to the

Figure 10.7 In a three-stage power amplifier example, an interstage matching network transforms the base impedance of the third stage’s transistor into the correct loadline resistance for the collector of the second-stage transistor (to maximize the power output from the second stage). The same procedure is followed for the first stage.

design process will be to determine the sizing rules for scaling the transistors on a stage-by-stage basis.

10.3 Gain and Power Allocations

10.3

177

Gain and Power Allocations In order to size each stage’s device properly in a multistage power amplifier, it is necessary to create a gain/power allocation budget for the overall amplifier [2]. This allocation process is determined by the relationship between the gain and power of each stage and the power output of the stage immediately preceding this stage. As shown in Figure 10.8, the power output and OIP3 requirement of any stage is determined (to the first order) by taking the next stage’s power and OIP3 requirements, then subtracting from them that stage’s gain. For instance, if a final stage with 10 dB gain is designed to deliver +30 dBm to the load with an OIP3 of +45 dBm, then the immediately preceding stage must have the ability to deliver +30 dBm – 10 dB = +20 dBm to the input of the final stage with an OIP3 of at least +45 dBm – 10 dB = +35 dBm. Figure 10.9 shows how the input impedance of each stage must be transformed into the ideal loadline resistance for the stage immediately preceding it. By using a set of interstage matching networks based on the calculated ideal loadline resistances for each stage, it is possible to create an overall amplifier schematic diagram that allows each stage to function to its full capabilities and design a cascaded amplifier that produces the desired overall performance without any of the stages’ acting as weak links in the process. All of these calculations are done on a “best-first-guess” basis. In reality, OIP3 is determined by spurious intermodulation products that are created independently in each stage and may phase together in ways that are hard to predict. The method presented here assumes that the third-order intermodulation products are added together simply as powers and not as interfering waves. In fact, they are almost certain to add as interfering waves, meaning that at least in the case of OIP3, what we are calculating with this method is only a rough first guess.

10.4

Active Device Sizing Given the cautions and caveats discussed above, we begin the device-sizing process realizing that this is not an exact science. Nevertheless, useful results are expected

Figure 10.8 Starting from the output of a cascade power amplifier, the power output and OIP3 requirements for each stage are calculated by subtracting the gain of all stages from the stage of interest to the output from the ultimate power output requirement and the ultimate OIP3 requirement.

178

Designing Multistage Amplifiers

Figure 10.9 A multistage power amplifier is broken down into a cascade of interstage matching networks that insure the input resistance of a given stage is transformed into the correct Rlopt for the preceding stage.

from this process, so we will proceed. Figure 10.10(a) shows the partitioning of RF power, dc current, and device size within a multistage power amplifier. Figures 10.10(b, c) show simulator plots that are useful in determining the load resistance presented to the transistor’s collector by a matching network. It is useful to make up spreadsheets (as shown in Figures 10.10(c, d) containing the gain, 1 dB compressed power output, OIP3, loadline resistance, and dc current associated with each stage of the multistage amplifier. The final item in the spreadsheet will be the size of the device. Device size is determined by the need for the device to generate that amount of power sufficient to drive the next stage in the chain to its full power output. If we overdesign a given stage, that stage is never called upon to deliver its maximum power; therefore, dc power is wasted. However, if a given stage is underdesigned, there will not be enough power to drive the following stage to its full power capabili-

Figure 10.10(a) The dc current requirement for each stage is determined from its RF power output requirements and its estimated PAE. Based on this calculated value of Ic, the size of each stage’s transistor, Ni, is calculated. This analysis allows the determination of Pout, OIP3, Pdc, Ic, and Ni for each stage.

10.4 Active Device Sizing

179

Figure 10.10(b) A possible matching network for using a simulator to set the element value that provides the correct Rlopt for each stage of a cascaded power amplifier.

Figure 10.10(c) A Smith chart showing the loadline impedance (pure real at 2.5 GHz) presented at the transistor’s collector terminals by the matching network shown in Figure 10.10(b).

Figure 10.10(d) An example of a spreadsheet for keeping track of the power output and OIP3 requirements for each stage in a multistage cascaded power amplifier.

ties. This will cause a lowering of the overall power of the amplifier, making a particular stage the weak link in the amplifier chain.

180

Designing Multistage Amplifiers

Figure 10.10(e) An example of a spreadsheet useful for systematically calculating the dc power requirements, class A loadline resistance, and transistor size for each stage in a multistage power amplifier.

In order to avoid the extremes of both overdesign and underdesign at any given stage, it is very important to achieve the target values accurately for each stage in terms of its power, OIP3, and gain. This is best accomplished by sizing each stage’s device according to the following rules. First, upon determining the power requirements of a given stage based on the considerations discussed above, the device’s collector current may be calculated according to Ic = Po/(Vcc × PAE)

(10.1)

Second, it is now necessary to make an estimate of PAE for a given amplifier type. If the amplifier is a feedback type, operating with high voltage (i.e., above 5.0V), the resulting PAE can be expected to exceed 40 percent. If the amplifier is a Darlington type or operating from a low-voltage power source, the value of PAE may be in the range of 20 to 30 percent (see Chapter 9). The designer needs to make some judgments at this point. To be safe, it is generally best to estimate PAE on the low side. Third, once PAE is estimated, the number of unit cells required for each stage is calculated as N = Ic/Imax (unit cell)

(10.2)

where Ic is the collector current. Imax is the maximum safe unit cell collector current. In summary, the complete design procedure for distributing performance and device size within a multistage power amplifier is as follows: 1. From the estimated gain for each stage, calculate the required power output and OIP3 of each stage, based on the overall output power and OIP3 of the cascaded amplifier, referenced to each stage (based on the preceding stage’s gain.)

10.5 Design Example 5: A Differential PCS PA

181

2. Based on estimated PAE efficiency (remember that 50 percent is the absolute maximum PAE for class A amplifiers), calculate the dc current requirements for each stage. 3. Determine the maximum dc current for a unit cell device based on reliability data obtained from the foundry. 4. Size the RF transistor device in each stage based on its dc current and the maximum dc current of the unit cell. Size is expressed as a number N of unit cell emitter fingers. 5. Use the loadline resistance of a unit cell (a single-emitter-finger transistor) to determine the overall loadline resistance for each stage (i.e., RL (per stage) = RL (unit cell)/N. 6. Synthesize interstage matching networks between stages to ensure that the exact loadline resistance required by each stage is presented to the collector terminals of the RF transistor in a given stage. As an example, consider the design of a two-stage amplifier that must meet a requirement to produce 0.50W of power output at 50 percent efficiency with 20 dB overall gain. Based on 10 dB gain per stage, the output power of the first stage must be 0.05W. Assuming a supply voltage of 3.0V, the second stage must have a collector current of 0.50W/3(50 percent) = 330 mA. Assuming 10 mA is the maximum safe dc current for each unit cell, the size of the second-stage device is calculated as 330/10 = 33 unit cells (emitter fingers). The first stage is handled in the same way. The first-stage collector current is 0.05W/3(50 percent) = 33 mA. Again, assuming 10 mA maximum dc current in each unit cell, the size of the first stage’s device is 33/10 = 3.3 (always round up to the larger number of unit cells, which is four in this case). Assuming a unit cell loadline resistance of 225 ohms (based on 3V operation), the second stage’s loadline resistance is 225/33 = 6.8 ohms (pure real). The first stage’s loadline resistance is 225/4 = 56.3 ohms (pure real). The next step in the design procedure is to synthesize an output matching network that provides the 6.8 ohms loadline resistance to the collector terminals of the second-stage device and an interstage matching network that provides a 56.3 ohms loadline resistance to the collector terminals of the first-stage device. See Chapter 9 for suggested matching networks for providing these impedances.

10.5

Design Example 5: A Differential PCS PA We next consider the design of a two-stage differential power amplifier for service in GSM and CDMA handsets1. The fabrication technology will be InGaP/GaAs HBT in order to ensure a high breakdown voltage. Handset power amplifiers operate at +3.0V dc; however, the RF voltage swings can often exceed 8V, making this class of amplifiers unsuitable for fabrication in SiGe technology. Important advantages can be realized by using a differential topology for high-power amplifiers in battery-powered mobile applications. The most important advantage is the ability to divide the power transistors in two by splitting them between the two sides of a differential pair. This factor-of-two size reduction will make each power transistor more manageable both in terms of ease of layout and reduction in layout parasitic

182

Designing Multistage Amplifiers

effects. Consider the design of a differential 2W power amplifier for mobile GSM applications. Because this amplifier is used in a handheld mobile unit, the battery voltage will be confined to 3.0V, forcing the size of the transistors to be very large, resulting in very low load impedance. Designing matching networks to provide such low impedances is a significant challenge. This is an area in which an all-differential design has significant advantages. Since the two amplifiers’ 180 phase-shifted outputs must be combined at an off-chip balun, the high collector bias current may conveniently be inserted at this balun. This is of great advantage because it eliminates the need to design on-chip bias chokes, which may not be able to handle safely the high dc collector currents needed to generate this high level of RF power output. Also, a differential amplifier naturally suppresses all even harmonics at its output. The first step in the design process is to calculate the size of the output stage’s (stage 2) transistors and their optimum loadline resistance. For 3V operation, the loadline impedance for a single emitter finger is 225 ohms. We first calculate the collector current of the second-stage (output) device, recognizing that in the differential form, there are two output transistors, each of identical size and current level. To calculate collector current, simply divide the required power in half (1W), then divide it by the dc voltage (3V) times the anticipated PAE. In this case, we estimate PAE to be 40 percent; therefore, Icollector = 1W/(3.0V)(40 percent) = 800 mA. The number of emitter fingers in each second-stage transistor is equal to 800 mA divided by 10 mA maximum current in each emitter finger, which is equal to eighty emitter fingers for the second-stage device. The loadline resistance of the second stage is equal to 225 ohms per emitter finger divided by eighty fingers, which is 2.8 ohms. An output impedance matching network must be designed to provide a transformation from the customary 50 ohms output impedance to the required 2.8 ohms loadline resistance. This transformation could be accomplished in the output balun, or it can be performed with a simple low-pass matching network where the shunt capacitors from each side of the amplifier are connected together at the virtual ground point at the electrical center of the circuit (see Chapter 6). Next, we perform a similar calculation for the amplifier’s first stage based on an assumed second-stage gain of 10 dB. The required output power of the first stage is 1W (i.e., +30 dBm) minus 10 dB, which is 100 mW (i.e., +20 dBm). This power is divided by a factor of two to account for the two differential transistors used in stage 1. Therefore, the collector current of the first stage is equal to 0.05W/(3.0V)(40 percent) = 40 mA. The number of emitter fingers in each of the first-stage transistors is equal to 40 mA divided by 10 mA (the maximum safe dc current per emitter finger), which equals four fingers. The loadline resistance of the first stage is equal to 225 ohms per emitter finger divided by four emitter fingers, which is equal to 56 ohms. A low-pass matching network similar to that used in the second stage can be used here. However, in the simulations, the base of the second-stage transistor must serve as the output impedance for the matching network of the first stage. Base bias is provided to the first and second stages by current mirror circuits. Collector bias is supplied to the first-stage transistors by RF chokes and to the second-stage transistors by an off-chip balun. The input signal is supplied to the first stage by a balun, which can serve as an input matching network from 50 ohms to the desired input impedance (for maximum gain) at the base of the first-stage transistors. The

10.5 Design Example 5: A Differential PCS PA

183

block diagram of the amplifier is given in Figure 10.11, and the schematic diagrams for the first and second stages are shown in Figures 10.12 and 10.13, respectively. The simulated small-signal S-parameter for the two-stage PCS amplifier is shown in Figure 10.14. Notice that the amplifier’s small-signal gain (S21) is about 40 dB, flat from 700 to 1,000 MHz. The input and output match is good from 800 to 1,000 MHz. The stability factor k is above 1.0 (indicating unconditional stability) over most of the frequency range, only dipping slightly at about 650 MHz. This dip in the k factor can be easily cured by including some stabilizing RL circuits in the input circuit of one or both stages. Notice that the simulated total dc current in the first stage is 100 mA and 2.0A in the second stage, which is consistent with the initial hand calculation. A graph of the simulated power output versus power input is shown in Figure 10.15. The 1 dB compression point is above +33 dBm, indicating that a total power output of 2W is being achieved in the amplifier’s linear region. Figure 10.16 shows the simulated fundamental and harmonic power outputs as a function of power input. Notice that the second-harmonic output is very low, which is a direct result of the amplifier’s differential design (second-harmonic energy is cancelled out at the balun combined output port). However, the third harmonic, which is not naturally cancelled at the amplifier’s output, is still down by 55 dB relative to the fundamen-

Figure 10.11 The block diagram of a two-stage PCS power amplifier using InGaP/GaAs technology and operating at a supply voltage of 3.0V. This two-stage differential PCS power amplifier operates at 900 MHz with a power output of +33 dBm.

Figure 10.12 amplifier.

The schematic diagram of the first stage of a two-stage differential PCS power

184

Designing Multistage Amplifiers

Figure 10.13 amplifier.

The schematic diagram of the second stage of a two-stage differential PCS power

Figure 10.14

The simulated S-parameters of the cascaded two-stage differential PCS amplifier.

tal power at the amplifier’s 1 dB compression point. Again these extremely low harmonic levels indicate the operation of a very linear power amplifier. To gain insight into the fine-grained linearity of the output transistors, it is possible to insert an RF current probe into the collector circuit of the second-stage transistors and to use this probe, along with a named collector node voltage, to simulate the large-signal collector voltage and collector current in stage 2. The sche-

10.5 Design Example 5: A Differential PCS PA

Figure 10.15 amplifier.

185

The simulated power input versus power output of the two-stage differential PCS

Figure 10.16 The simulated third-harmonic output from the two-stage differential PCS amplifier. At full power output, the simulated third harmonic is more than 50 dB below the fundamental signal.

matic showing the insertion of the RF current probe is shown in Figure 10.17. The simulated voltage and current waveforms are shown in Figure 10.18. Notice that the RF voltage has some tendency to “clip” at the bottom of the cycle, indicating the presence of second-harmonic energy in the transistor’s output voltage. However, as a direct result of the amplifier’s differential configuration, these second-harmonic signals are cancelled at the balun’s output and never “escape” from the amplifier. The simulated RF collector voltage and collector current may be plotted against each other to form what is called a dynamic loadline, as shown in Figure 10.19. The dynamic loadline is very interesting because it shows the full extent of the voltage and current excursions experienced by the transistor in each RF cycle at a given power level. The slight “looping” behavior of the dynamic loadline indicates the presence of unresonated reactance within the transistor’s large-signal model. This reactance may be resonated by the output matching elements that follow the transistors. Notice that a straight line drawn through the set of dynamic loadlines is nearly

186

Designing Multistage Amplifiers

Figure 10.17 A schematic diagram of the output transistor showing the placement of an RF current probe, making possible the simulation of both the voltage waveform and the current waveform of the output transistor.

Figure 10.18 The simulated voltage and current waveforms of the PCS amplifier’s output transistors at a number of progressively increasing power inputs.

equal to the calculated loadline resistance for the transistor (5 ohms dynamic versus 2.8 ohms calculated). Figure 10.20 shows the amplifier’s simulated OIP3 as a function of frequency. Figure 10.21 also shows the ADS schematic for the n-tone source and har-

10.5 Design Example 5: A Differential PCS PA

187

Figure 10.19 The simulated dynamic loadline for the PCS amplifier’s output transistors with a 5 ohm “static” loadline superimposed on the dynamic curves. Looping is due to unresonated reactance within the transistors. Notice that the primary axis of the dynamic loadline fits closely to the calculated 5 ohm static loadline.

Figure 10.20

The simulated OIP3 versus frequency for the two-stage differential PCS amplifier.

monic-balance controller for simulating OIP3. The amplifier’s value of OIP3 is nearly flat at +47 dBm from 800 to 1,000 MHz. This value of OIP3 indicates a scaled linearity metric of 47 dBm – 33 dBm = +14 dB, which is a really excellent linearity performance indicator. The linear efficiency of the entire amplifier may be calculated by first calculating the dc power consumption (3V × 2.1A = 6.3W or +37 dBm), then subtracting the dc power consumption from the amplifier’s OIP3 (+47 dBm – 37 dBm = 10 dB), which is also an excellent number, especially for a multistage amplifier, which suffers from the inefficiency of a first stage that consumes dc power in order to raise the overall gain but contributes nothing to raising the overall OIP3 of the amplifier. Next, we simulate the amplifier’s response to various types of modulation used in cellular/PCS systems. The first modulation type tested is GSM [3]. GSM is a con-

188

Designing Multistage Amplifiers

Figure 10.21 An ADS harmonic-balance controller and the n-tone signal source, which are used to simulate both the two-tone intermodulation and OIP3.

stant envelope phase modulation and has no zero crossings in its constellation diagram. As a result, GSM modulation is more tolerant of nonlinearity in power amplifiers than other types of modulations used in cellular/PCS systems. Figure 10.22 shows the use of an ADS GSM source and the associated envelope-simulation controller. Envelope simulation is a very useful technique in the case of modulated signals because envelope simulations run much faster than standard harmonicbalance simulations. This is because, in effect, the simulator subtracts out the sine wave associated with the carrier and concentrates its attention entirely on the modulation envelope associated with the output signal. Figure 10.23 shows the envelope simulation of the GSM source driving the two-stage PCS amplifier to its full +33 dBm output power. Notice that the constellation diagram is a circle with no zero crossings. This type of modulation is relatively tolerant of the nonlinearity of the amplifier when it is driven to full power output. Notice that most of the signal’s spectrum is located within +/–150 KHz of the center frequency, and the adjacent channel power ratio (ACPR) is about –25 dBC in both the upper and lower first adjacent channels. These ACPR numbers are acceptable for GSM operation. Next, the output power is backed off by 10 dB to +23 dBm, and the envelope simulations at this power output are shown in Figure 10.24. Notice that neither the constellation diagram nor the first adjacent channel ACPR changes significantly at reduced power output. This is very consistent with the nature of GSM modulation and, in fact, is one of the advantages of this form of modulation (as opposed to CDMA modulation, whose ACPR is very sensitive to power amplifier output level). Figure 10.25 shows the envelope source parameters for CDMA modulations. We now repeat the envelope-simulation process using CDMA modulation. In the case of CDMA, the amplifier’s power output will be increased gradually to observe

10.5 Design Example 5: A Differential PCS PA

189

Figure 10.22 A schematic diagram showing the ADS GSM signal source and an envelope-simulation controller, which are used together to simulate a power amplifier’s performance in GSM service.

Figure 10.23 The simulated GSM spectrum, constellation diagram, and ACPR for the two-stage differential PCS power amplifier driven by a GSM input signal to an output power of +33 dBm at 900 MHz.

the effect on ACPR and the constellation diagram at each power output level. Figure 10.26 shows the simulations of signal spectrum and constellation using a CDMA-modulated source driving the PCS amplifier to an output of +17 dBm.

190

Designing Multistage Amplifiers

Figure 10.24 The simulated GSM spectrum, constellation diagram, and ACPR for the two-stage differential PCS power amplifier driven by a GSM input signal to an output power of +23 dBm at 900 MHz. Notice that in GSM service, the amplifier’s ACPR performance does not change significantly as its power output is backed off from +33 dBm to +23 dBm.

Figure 10.25 A schematic diagram showing the ADS CDMA (IS-95) signal source and envelope-simulation controller, which are used to simulate a power amplifier’s performance in this form of CDMA service.

ACPR is about –60 dBC for both upper and lower first adjacent channels. These are excellent numbers and exceed the IS-95 CDMA standard specification by a wide margin. The constellation diagram indicates multiple zero crossings, meaning

10.5 Design Example 5: A Differential PCS PA

191

Figure 10.26 The simulated CDMA spectrum, constellation diagram, and ACPR for the two-stage differential PCS power amplifier driven by a CDMA input signal to an output power of +17 dBm at 900 MHz.

CDMA-modulated signals are expected to be very sensitive to power amplifier nonlinearity. However, the price paid for outstanding linearity is very low power output relative to the amplifier’s full capabilities. Figure 10.27 shows a blow-up of the constellation diagram with the amplifier operating with a CDMA-modulated signal. It is clear from this diagram that CDMA signals have a basic QPSK form with many zero crossings, making them unsuitable for use with very nonlinear amplifiers. Consider next what happens as the amplifier’s power output is increased. Figure 10.28 shows the spectrum and constellation diagram for the CDMA output signal at a power of +31 dBm. The ACPR for the upper and lower first adjacent channels is –48 dBC, which approaches the IS-95 standard specifica-

Figure 10.27 The simulated constellation diagram of CDMA modulation showing a basic QPSK modulation structure with multiple zero crossings.

192

Designing Multistage Amplifiers

Figure 10.28 The simulated CDMA spectrum, constellation diagram, and ACPR for the two-stage differential PCS power amplifier driven by a CDMA input signal to an output power of +31 dBm at 900 MHz. Notice that ACPR degrades by 12 dB as the power output is increased to +31 dBm relative to the ACPR at +17 dBm power output. This level of ACPR is barely acceptable in most cellular applications.

tion of –45 dBC. Figure 10.29 shows the simulations of the CDMA signal at the amplifier’s full output power of +33 dBm. At its full 2W power output, the amplifier’s ACPR has dropped to –40 dBC in both first adjacent channels, as expected. Therefore, clearly, CDMA service, unlike GSM service, requires that the amplifier’s output power be backed off from its full power capability by 2 to 5 dB in order to meet the ACPR specification. This amount of back-off significantly reduces the PAE of the amplifier. Most handset power amplifiers in CDMA service operate at efficiencies less than 30 percent. In order to conserve battery life, CDMA power amplifiers in handset applications are only required to operate at a power output of +28 dBm, as opposed to GSM power amplifiers, which must operate at +33 dBm or higher. The layout for the two-stage PCS amplifier’s layout is shown in Figure 10.30. Optimizations and simulations of this design example were performed by Calvin Chien in partial fulfillment of the requirements of the course ELEN 359A (“Advanced RFIC Design”) at Santa Clara University, Santa Clara, California. The only off-chip components required for operation are the input and the output baluns. An important challenge with this amplifier is ensuring that all metal traces carrying the dc collector current associated with the final stage transistors are sufficiently wide to be safe, relative to the process design rules (based on metal migration considerations). An excellent way to ensure compliance is simply to connect the final transistor’s collector contacts to a pair of bonding pads, which will in turn be con-

10.5 Design Example 5: A Differential PCS PA

193

Figure 10.29 The simulated CDMA spectrum, constellation diagram, and ACPR for the two-stage differential PCS power amplifier driven by a CDMA input signal to an output power of +33 dBm at 900 MHz. Notice that ACPR degrades by 7 dB as the power output is increased to +33 dBm (which is the amplifier’s 1 dB compressed power output) relative to the ACPR at +31 dBm power output. This level of ACPR is no longer acceptable in most cellular applications.

Figure 10.30 The layout of the two-stage differential PCS power amplifier for +33 dBm power output at 900 MHz. The two differential input pads are on the left, and the six (two sets of three each) differential output pads are on the right. The bias circuit for stage 1 is in the lower left-hand corner of the die. The bias circuit for stage 2 is in the lower center portion of the die. Overall die size is 3.0 × 3.5 mm.

nected (via the package) to an off-chip balun. The balun can be used as an impedance matching device and a bias insertion point at its secondary’s center tap.

194

Designing Multistage Amplifiers

Endnote 1.

The original concept for this design example came out of a collaboration between the author and Taka Shinomiya of MCT, Inc.

References [1] [2] [3]

Vendelin, G., et al., Microwave Circuit Design Using Linear and Nonlinear Techniques, New York: John Wiley and Sons, 1990. Wilson, S., “Evaluate the Distortion of Modular Cascades,” Microwaves, Vol. 20, No. 3, 1981, p. 67. Dixon, R., Spread Spectrum Systems with Commercial Application, New York: John Wiley and Sons, 1994.

CHAPTER 11

Mixer/Modulator Design 11.1

Mixer Basics Mixers are inherently nonlinear devices [1]. Mixers use the nonlinearity of their devices to convert input frequencies to new output frequencies. Most mixers are either downconverting mixers that produce, at their output, a difference frequency between two input frequencies, or they are upconverting mixers, which produce at their output a sum (or difference frequency) of their two inputs, raising the frequency of the output, which is regarded as the signal. In general, the output frequency of a mixer is Fout = Fr +/– Fl

(11.1)

where Fr is the RF input frequency, and Fl is the LO input frequency. A basic mixer is shown symbolically in Figure 11.1. By virtue of their inherent nonlinearity, mixers internally produce harmonics of their Fr and Fl input frequencies. These internally generated harmonic frequencies mix with each other to produce unwanted output frequencies called N × M spurs [2]. A general expression of the N × M spur frequencies is Fout (N × M) = NFR +/– MFL

(11.2)

Since a mixer is a frequency-conversion device, its primary electrical specification is called conversion gain (or loss). Since the input Fr and Fl frequencies are unwanted at the output port (and at each other’s input ports), isolation specifications are important for understanding the degree to which unconverted signals are suppressed at the mixer’s various inputs and outputs. The three most important isolations are L-to-R isolation, L-to-I (where I is the output port), and R-to-I isola-

Figure 11.1

The basic schematic symbol for a mixer function.

195

196

Mixer/Modulator Design

tion. It is important that these isolations be high enough to assure that the frequency-converted output signal is much stronger than non-frequency-converted signals from the mixer’s inputs. Noise figure is also an important specification for a mixer. In the case of passive mixers (mixers that use diodes rather than transistors and inherently exhibit conversion loss), the mixer’s noise figure is always equal to its conversion loss [3]. In the case of active mixers (mixers using transistor devices), their noise figure may assume a value similar to, or higher than, that of an amplifier using the same transistor and operating at the Fr frequency (downconverted noise from the image frequency may increase overall NF.) As with amplifiers, mixers generate two-tone intermodulation spurs. Like amplifiers, two-tone intermodulation spurs represent an important performance parameter. In the case of mixers, two-tone intermodulation performance is specified in terms of an input intermodulation intercept point called IIP3. IIP3 is closely related to the concept of OIP3 in an amplifier. The relationship between IIP3 and OIP3 is simply IIP3 = OIP3 – Gconv

(11.3)

LO power level for proper operation is also an important mixer specification. As mentioned above, it is necessary to specify the N × M spurs of a mixer. Any mixer can be understood by performing a mathematical power-series analysis on its nonlinear device in the presence of two input signals of different frequencies. The power-series expression of the nonlinear behavior of a generalized active device may be written as I(t) = I0 + K1V + K2V2 + K3V3 + …

(11.4)

Assuming that V = V1cos

1

t + V2cos

2

t

(11.5)

where V1cos V2cos

t is the R port signal. 2t is the L port signal. 1

Applying (11.4) to (11.5), we obtain an expanded expression for the second-order term as I(t) = K2[(V1cos

1

t)2 + (V1cos

1

t)(V2cos

2

t) + (V1cos

1

t)2]

(11.6)

where the first and the third term are responsible for generating the second harmonic of the R and the L signals respectively. It is the center term that is responsible for mixer action. By using a well-known trigonometric identity [4], it can be shown that the center term can be expanded as I(t) = K2[(V1V2)/2]([cos( 1 – 2)t] + [cos( 1 + 2)t])

(11.7)

11.2 Diode Mixers

197

where The first term is associated with the difference mixing frequency. The second term is associated with the sum mixing frequency. Both sum and difference frequencies are always present at a mixer’s output port. To eliminate one or the other, it will be necessary to filter out the undesirable output. An example of output filtering applied to downconverting and upconverting mixers is shown in Figures 11.2 and 11.3, respectively. This filtering process is most often accomplished by connecting a low-pass filter to the mixer’s output to suppress the sum frequency output or by connecting a high-pass filter to the mixer’s output to suppress the difference frequency output. See Chapter 6 for more detailed informatio on filter design.

11.2

Diode Mixers Diode mixers having conversion loss rather than conversion gain are known as passive mixers. Passive mixers use diodes as their nonlinear mixing devices. There are several kinds of diode mixers, depending on configuration and complexity. The simplest is called the single-ended diode mixer. The basic circuit schematic for a single- ended diode mixer is shown in Figure 11.4. The diode is shunted to ground across a transmission line that delivers both the R and L signal to the diode. An RF choke connecting the ungrounded terminal of the diode to dc ground provides a conduction path so that dc current may flow within the diode in response to R and L

Figure 11.2

The block diagram and spectrum of a downconverting mixer.

Figure 11.3

The block diagram and spectrum of an upconverting mixer.

198

Mixer/Modulator Design

Figure 11.4

The schematic diagram of a simple single-diode mixer.

input signal powers. By controlling the flow of dc current (using L power) to just the right current (where the diode’s operating point provides the maximum nonlinearity) it is possible to keep the mixer’s conversion loss to a minimum. In well-performing mixers of this class, conversion loss is expected to be in the 5–10 dB range. High isolation is difficult to achieve with this type of mixer. Since the R and L ports are essentially hardwired, the L-to-R isolation is nearly zero, unless a diplexer device is provided at one or both ports. In practice, such a diplexer will be effective only if the frequency separation between Fr and Fl is fairly large, which is not always the case. The L-to-I and the R-to-I isolations can be quite good, depending on the quality of the output port’s low pass filter. Since this mixer always experiences conversion loss, its noise figure is equal to the conversion loss (as described in Section 8.3). The L power requirement is approximately 3 mW per diode. IIP3 for this class of mixer is approximately equal to the L power. To increase its IIP3, the mixer’s L power can be increased accompanied by adding two or more diodes in series, increasing the total forward voltage, Vf , which appears across the diode when it is stimulated into forward conduction, by the L power. An important variation on the single-ended diode mixer is the single-balanced mixer, whose schematic diagram is shown in Figure 11.5. This type of mixer achieves a naturally high amount of L-to-I and L-to-R isolation by making use of a technique called a virtual ground. When using a virtual ground, the L signal is split into two paths with a 180° phase difference, using a transformer (or a balun). The out-of-phase secondary ports of the transformer are connected to the top and bottom of a series combination of two identical diodes. If the transformer has a grounded center tap, the center point of the diode pair is fixed at ground potential

Figure 11.5

The schematic diagram of a single-balanced two-diode mixer.

11.2 Diode Mixers

199

for the L signal by the virtual ground process. By connecting the R and I ports to this point in the circuit, the mixer achieves a naturally high amount of L-to-R and L-to-I isolation as a direct result of the transformer’s virtual ground. The mixer’s R-to-I isolation may be increased with the proper use of a low-pass (or a high-pass in the case of upconversion) filter connected between the mixer’s R and I ports. Because there are two diodes in this mixer, the LO power and IIP3 are raised by 3 dB relative to those in the single-diode mixer previously discussed. The final type of passive diode mixer we shall discuss is the double-balanced diode mixer, whose schematic diagram is shown in Figure 11.6. In this mixer, as in the single-balanced mixer, virtual ground techniques are used to achieve high isolation by canceling the R and I signals at output ports from which we don’t wish them to escape. In the double-balanced case, two transformers (baluns) are used to achieve this goal. One transformer is connected to the R port, and the second one is connected to the L port. By arranging four diodes in a ring configuration and connecting two transformers to the diode ring, we create a situation where the L port energy is cancelled by virtual ground effects before it can reach either the R or I ports. Likewise, the R power is cancelled by its transformer before it can reach either the L or I port. The double-balanced mixer naturally achieves high L-to-R and L-to-I isolations without the need for filters. Another benefit of this kind of mixer is that by using a four-diode architecture, L power and IIP3 are increased by a factor of four relative to the single-diode case. The double-balanced diode mixer is about as good as a passive mixer can get. For RFICs transistors can be easily configured to operate as diodes, as shown in Figure 11.7. By connecting the base and

Figure 11.6

The schematic diagram of a double-balanced four-diode mixer.

Figure 11.7 The collector and base terminals of a transistor are connected together in order to make the transistor operate as a diode based on its emitter-base junction.

200

Mixer/Modulator Design

collector terminals together, the transistor’s base-to-emitter junction acts as a diode, which may be used in a wide range of mixer applications.

11.3

Single-Balanced Active Multiplying Mixers Active mixers use transistors as mixing devices to simultaneously achieve nonlinearity for the mixing process and gain to create conversion gain. As with the passive mixers we have already discussed, active mixers can make use of differential balancing techniques to obtain excellent isolation. Following T. Lee [5], the conversion gain of a single bipolar transistor may be analyzed as follows. Using the exponential law for a bipolar transistor, expressing Ic in terms of Vbe results in Ic = Is exp(Vbe/VT)

(11.8)

where Is is the transistor’s saturation current. VT is the thermal voltage (25 mV at 25 C). Expanding (11.8) to yield up to the second-order term for analyzing a mixer gives Ic = Idc [1 + Vin/VT + 1/2 (Vin/VT)2]

(11.9)

The coefficient of the second-order term is given by C2 = Gm1/2VT

(11.10)

where Gm1 = ( Ic/ Vbe). Comparing with (11.7), we see that the voltage conversion gain is then given by CG =

C 2 Vin VLo = C2 Vlo = Gm1 (Vlo/2VT) Vin

(11.11)

Equation (11.11) indicates that for a single bipolar transistor, mixer conversion gain is proportional to both Gm and Vlo. This conclusion indicates that conversion gain may be increased by increasing either the transistor’s size (to increase Gm) or by increasing Vlo, or some combination of size and Vlo. Although there is a variety of active mixer topologies, the most popular version today is the so-called multiplying mixer. This simple mixer consists of a pair of differential amplifier transistors (see Chapter 7) whose current is controlled by a single “tail” transistor. The tail transistor acts as a gain control for the differential pair, and in so doing, it serves as a port whose inputsignal is multiplied mathematically by the signal being amplified by the differential pair. If the tail transistor is controlled by a dc base current, this dc signal will simply act as a gain control since the signal being amplified by the differential pair will be multiplied by a constant (i.e. dc). However, if the input to the tail transistor is an ac signal, then the signal input to the

11.3 Single-Balanced Active Multiplying Mixers

201

tail transistor will be mathematically multiplied by the signal amplified by the differential pair. This condition is exactly what is needed to construct a perfect mixer. Next, we consider an analysis of the single-balanced bipolar mixer shown in Figure 11.8. Rs is the input source resistance, and Re is the emitter degeneration resistor connected to the “bottom” (tail like) transistor. The small-signal collector current of Q1 can be calculated as Ic1 = Vrf/(Rs + Re + 1/Gm1)

(11.12)

Following B. Razavi [6], if the LO waveform has a 50 percent duty cycle (the top transistors act as switches), Ic2 – Ic3 is equal to the product of Ic1 and a square-wave toggling between +1 and –1, giving Vout = (Vrf Rc) (4/ )(cosωLot)/(Rs + RE + 1/GM1)

(11.13)

where Rc is the collector resistor of the “top” transistors. Multiplying Vrf by cos lot is equivalent to shifting Vrf in frequency by dividing Vout by a factor of two. By calling the output voltage Vif, we obtain Vif = (2VrfRc/ )(Rs + Re + 1/Gm1)

lo

and

(11.14)

It follows that the voltage conversion gain is obtained by dividing Vif by Vrf, which is CGv = (2Rc/ )(Rs + Re + 1/Gm1)/(Re + 1/Gm1) (Rs + Re + 1/Gm1)

(11.15)

and with some simplification, CGv = (2Rc/ )/(Re + 1/Gm1)

For a matched input, Rs = Re + 1/Gm1. Therefore, with a matched input, the voltage conversion gain becomes

Figure 11.8

The schematic diagram of a single-balanced active transistor mixer.

(11.16)

202

Mixer/Modulator Design

CGv = 2Rc/ Rs

(11.17)

The power conversion gain can be calculated by expressing the IF power based on Vif rms appearing across 2Rc as Pif = V2rfrmsRc(2/ 2)/(Rs + Re + 1/Gm1)2

(11.18)

The input power is given as 2 Pin = Vrfrms / 4R s

(11.19)

Therefore, the power conversion gain is CGp = Pif/Pin = 8RsRc/ 2(Rs + Re + 1/Gm1)2

(11.20)

If the input is matched (i.e., Rs = Re + 1/Gm1), the power conversion gain simplifies to CGp = 2Rc/ 2Rs

(11.21)

The power conversion gain may be related to the voltage conversion gain as CGp = (CGv)2 (Rs/Rl)

(11.22)

where Rl = 2Rc. Therefore, the gain-control function of a differential pair forms the functional basis of an ideal multiplying mixer. The schematic diagrams of a single-balanced multiplying mixer are shown in Figures 11.7 and 11.9 (the mixer’s bias circuit, which uses a “totem pole” of three diodes). Notice that this mixer is single-ended only in the R port, with the L and output (I) ports being differential. This means the mixer’s L-to-R isolation and R-to-I isolation will be excellent. However, its L-to-I isolation will be poor since the differential pair of transistors naturally amplifies the L signal, with the L port acting as an input and the I port acting as an output. There

Figure 11.9

“Totem pole” bias supply for the single-balanced transitor mixer.

11.3 Single-Balanced Active Multiplying Mixers

203

is no virtual ground effect at work with these two ports, so the L signal appears at the output (I port) unsuppressed. In the next section, we will discuss a fully differential multiplying mixer (Gilbert cell), which solves this problem, but for now we must live with the poor L-to-I isolation. In downconverting mixer applications, the L signal appearing at the output (I port) can be suppressed by a low-pass filter following the mixer. In upconverting mixer applications, the L signal can be suppressed with a band-pass filter, but the effectiveness of this technique depends heavily on how high in frequency the R signal is. If the R signal is very low in frequency, a filter of a very narrow bandwidth will be needed in order to suppress the L signal at the output. The mixer’s layout (using InGaP/GaAs technology) is shown in Figures 11.10 to 11.12. The layout of the mixer’s bias circuit is shown in Figure 11.12.

Figure 11.10

The layout of the single-balanced transistor mixer.

Figure 11.11

Close-up of the transistor layout in the single-balanced transistor mixer.

204

Mixer/Modulator Design

Figure 11.12 The layout of the mixer’s bias tree. LO+, LO–, and RF pads correspond to connecting points within the mixer’s layout.

Figure 11.13 The simulated output spectrum, conversion loss, isolations, and waveform of a downconverting single-balanced transistor mixer.

Figure 11.13 shows the simulated output spectrum of the single-ended downconverting multiplying mixer using a Gummel Poon InGaP/GaAs HBT device

11.4 Fully Balanced Active Multiplying Mixers (Gilbert cell)

205

model. The conversion gain of the mixer is about 5 dB for R and L signals of approximately 2.0 GHz. The number of N × M spurs depends on the harmonic order used by the simulator. In this case, an order of seven was applied to the L signal, and an order of three was applied to the R signal. Notice that the L-to-R isolation and the R-to-I isolation are excellent. However, as mentioned above, the L-to-I isolation is nonexistent (there is gain). This mixer also works well as an upconverter with approximately the same 5 dB conversion gain and isolations similar to those experienced with downconversion. In the next section, we will discuss the extension of the multiplying mixer concept to a fully (three-port) differential mixer configuration.

11.4

Fully Balanced Active Multiplying Mixers (Gilbert cell) A natural extension of the multiplying mixer discussed in Section 11.3 is a fully differential multiplying mixer, normally called a Gilbert cell mixer. A Gilbert cell mixer uses two of the single-ended mixers whose outputs are combined, as shown in the block diagram given in Figure 11.14, to cancel out the L signal at the mixer’s combined output. This technique makes the Gilbert cell mixer fully differential in all three ports. Therefore, using this special mixer topology, we achieve extremely high L-to-R isolation, L-to-I isolation, and R-to-I isolation simultaneously. The Gilbert cell mixer has become the mixer topology of choice for most RFIC designs intended for wireless communications due to its small size, high conversion gain, high natural isolations, and low LO power requirements. Today, almost all upconverting and downconverting IC mixers use some version of a Gilbert cell topology. The basic schematic diagram of a Gilbert cell mixer is shown in Figure 11.15. A variant on this design, shown in Figure 11.16, uses inductor loads instead of resistor loads between the LO differential pairs of transistors and the power supply. The use of inductors is very helpful in maximizing conversion gain and power output, but since the inductors are often chosen for their ability to “resonate out” other capacitive components in the schematic, such mixers are often narrowband in performance. The use of resistor loads is usually reserved for less-demanding applications where wide bandwidth is an important requirement.

Figure 11.14 A schematic diagram of a Gilbert cell mixer (represented as a pair of singlebalanced transistor multiplying mixers) showing how the LO signal currents cancel to zero at the mixer’s output load. This canceling of LO currents in the mixer’s output creates extremely high L-to-I isolation (and high L-to-R and R-to-I isolations) in this class of mixers.

206

Mixer/Modulator Design

Figure 11.15 The schematic diagram of a Gilbert cell mixer circuit with resistor loads and a transformer output circuit. All element values to allow simulation are included in the diagram. Gilbert

Figure 11.16 The schematic diagram of a Gilbert cell mixer circuit with inductive loads and a transformer output circuit. All element values to allow simulation are included in the diagram. The inductive loads increase the mixer performance because they create little or no dc voltage drop at the top transistor’s collectors relative to Vcc. However, wide bandwidth operation may be limited by making this choice. Gilbert cell mixers with inductive loads are often used in upconverting transmitting modulator applications.

11.4 Fully Balanced Active Multiplying Mixers (Gilbert cell)

207

The four transistors that respond to the LO signals (called the top transistors) in effect act as switches that “commutate” (alternately change the direction of the differential signal as it enters the load) the mixer’s output signal to the differential load at a rate determined by the LO frequency. This commutation process is shown schematically in Figures 11.17 and 11.18. The top transistors act as ideal switches (that is, if the LO signal is of sufficient strength to cause the transistors to be either fully on or fully off), then only two transistors at a time are a part of the conduction path of the mixed signal flowing to the load, as shown in Figure 11.17. The signal applied to the two transistors that are driven at the input frequency (called the bottom transistors) is conducted through the two “turned-on” top transistors, where mixing with the LO signal occurs. These mixing product currents flow into the differential load and appear at the load as a superposition of new frequencies. However, as shown in Figure 11.14, the LO signal currents, which are not commutated at the load (unlike the mixed output signals, which are commutated), are always added up (and cancelled) at the load in two equal amounts, which are exactly 180º out of phase (flowing out of the collectors of the two “turned-on” top transistors). This means that, ideally, the LO signals are completely cancelled in the load. In actual physical mixers, several nonideal situations can lead to reintroduction of the LO signal at the load. Chief among these LO regenerators are imbalance in the physical layout of the Gilbert cell, differences in gain between the left-hand and right-hand bottom transistors, and side-to-side imbalance in the stray base-to-collector capacitance in the top and bottom transistors. It doesn’t take

Figure 11.17 A schematic diagram of a Gilbert cell mixer showing how the LO transistors play the role of switches during alternating half–LO cycles. During this commutation process, the direction of the mixer’s output current alternatively changes direction as it flows into the transformer load.

208

Mixer/Modulator Design

Figure 11.18 A schematic diagram of a Gilbert cell mixer showing how the top transistors play the role of switches during the second half-cycle. The output current reverses direction in the transformer load during this second half of the commutation process.

much imbalance to cause a significant amount of LO regeneration. If the bottom transistors have the equivalent of as little as 2 mV difference in their Vbe, the LO-signal-to-mixed-output-signal ratio may be as high as –25 dB. Also, if the imbalance in base-to-collector stray capacitance is as much as 10 fF, the LO-signal-to-mixed-output-signal ratio can be as high as –25 dB. Therefore, it is important to be sure the ultimate layout of Gilbert cell mixers is extremely symmetric and totally free from imbalance in parasitic capacitances. Much care must be taken at the layout level to ensure that these conditions are met. In some applications, in particular transmitting mixers (modulators), excessive LO regeneration can become a significant problem. In these cases, provided all precautions have been taken during layout, an alternative way might be to provide some form of gain adjustment in the bottom transistors to ensure perfect side-to-side balance. This technique works if the root cause of the LO regeneration is gain imbalance. However, if the root cause is imbalance in the base-to-collector capacitance, gain adjustments will not be effective in canceling the regenerated LO signal because of the inherent 90º phase shift between the conductive currents associated with gain control and the reactive currents associated with the unbalanced stray capacitance. In this case, layout modifications are the only recourse. This subject requires very careful attention by the designer. Next we will proceed with a small signal analysis (in contrast to the switching mixer descriptions given above) of a Gilbert cell mixer. Following P. Gray [7], the following is a small-signal analysis of a multiplying-type Gilbert cell mixer. Consider the emitter-coupled pair shown in Figure 11.19(a). The collector currents of Q1 and Q2 are given as

11.4 Fully Balanced Active Multiplying Mixers (Gilbert cell)

Figure 11.19(a)

209

The schematic diagram of a differential pair of transistors.

Ic1 = Ie/[1 + exp(–Vid/VT)]

(11.23)

Ic2 = Ie/[1 + exp(+Vid/VT)]

(11.24)

where Vid is the differential input voltage, and VT is the thermal voltage, and Ie is the total emitter current of the differential pair. The differential collector current, Icd, is Icd = Ic1 – Ic2 = Ie tanh(Vid/2VT)

(11.25)

As an approximation, tanh(Vid/2VT) = Vid/2VT for Vid/2VT 1.0). Impedances that lie outside of the MAG(S11) = 1.0 contain negative resistance and can start oscillators at the frequency of the circuit’s reactive reso-

13.4 Feedback Circuit Topologies for Producing Negative Resistance

255

Figure 13.17 A schematic diagram of a common-base, negative-resistance oscillator (including biasing elements and values for elements) using a Gummel Poon transistor model and InGaP/GaAs HBT technology.

Figure 13.18 The simulated impedance of the common-base, negative-resistance oscillator at the transistor’s emitter terminals. This impedance is plotted on an “expanded” Smith chart. Notice that negative resistance is available with this circuit over a frequency range of 2.8 to 8.7 GHz. A peak negative resistance of –43 ohms occurs at 5.0 GHz.

nance. As can be seen in Figure 13.18, the circuit’s negative resistance disappears at frequencies below 2.8 GHz and above 8.7 GHz, which is consistent with a negative resistance that is expected to disappear below a first critical frequency and above a second critical frequency. The maximum value of negative resistance is encountered at mid-band and is equal to about –45 ohms. In the region of negative resistance, the overall impedance is always inductive, which means that the oscillator’s resonator may simply be a capacitor. A VCO may be naturally designed using a negative-resistance circuit simply by making use of a varactor diode as its resonator. The inductive component of the circuit’s resonator is supplied by the transistor and the series feedback inductance that is connected between the transistor’s base and ground. Now compare the negative resistance simulated with a Gummel Poon model for the transistor with the negative resistance obtained with the CCCS-plus-Cbc model

256

Voltage-Controlled Oscillator Design

for the transistor that is discussed above. Cbc stands alone as the only element in the transistor’s equivalent circuit (other than the controlled current source itself) that is important in determining the circuit’s negative behavior. The model for the negative-resistance oscillator using this equivalent circuit for the transistor is shown in Figure 13.19. The oscillator’s model contains an ideal current source, with a beta of 100, the input base resistance set idealistically to 2 ohms, and the current source’s

Figure 13.19 The common-base, negative-resistance oscillator’s transistor may be modeled as a CCCS plus a parasitic capacitance, Cbc, which is connected between the transistor’s base and collector terminals. The oscillator’s 5 nH feedback inductor is connected from the transistor’s base terminal to ground. The current source’s beta is set to 100, which is consistent with Gummel Poon models. The base resistance is set to a low value (1ohm), and the collector resistance is set to a high value (10k).

Figure 13.20 The simulated impedance of the modeled (see Figure 13.19) common-base, negative-resistance oscillator as it appears at its transistor’s emitter terminals. This impedance is plotted on an “expanded” Smith chart. Notice that negative resistance is available over a frequency range of 1.7 to 8.1 GHz. A peak negative resistance of –45 ohms is obtained at 6.0 GHz. These simulated results are almost identical to the simulations using a Gummel Poon large-signal transistor model, as shown in Figure 13.18. We conclude from this result that common-base, negative-resistance oscillators make use of two feedback elements: the first is the inductor connect between the transistor’s base and ground, and the second is an internal capacitance feedback element, Cbc, which is connected internally from the transistor’s base to its collector. Without having both of these elements in the oscillator’s circuit, negative resistance entirely disappears. Other internal feedback elements, such as Cbe and Cce, have almost no effect on negative resistance and may be safely ignored in this application.

13.4 Feedback Circuit Topologies for Producing Negative Resistance

257

output shunt resistance set to 10,000 ohms. As in the Gummel Poon example, the inductor is set to 5 nH, and the load is set to 50 ohms. The value of Cbc is assumed to be 0.07 pF (typical for a single-finger transistor) is connected between the base and the collector terminals. As shown in Figure 13.21, the locus of impedances, Zin, is plotted on an enlarged Smith chart. As in the previous Gummel Poon simulation, the simulated negative resistance of the equivalent circuit model begins at 2.8 GHz and continues up to 8.4 GHz. The maximum value of negative resistance is –43 ohms at 5.9 GHz. These results are almost identical to those obtain by using a fully biased Gummel Poon model for the transistor, clearly indicating that a current-controlled current source plus a parasitic capacitor Cbc is a sufficiently accurate equivalent circuit for analyzing the behavior of negative-resistance oscillators. Since the transistor’s Cbc cannot be directly controlled by the designer, it may be necessary, especially at low frequencies, to use a larger-area device (which can still be biased at low current densities to reduce power consumption, as well as the shot noise and 1/f noise that contribute to phase noise) in order to achieve a required value of Cbc and insure strong values of negative resistance at the low end of the band of interest. In the case of the common-base inductive circuit, we understand the feedback inductance, together with parasitic capacitances in the transistor’s model, working together to form a circuit linkage between the RF current flowing into the load and a feedback “input” voltage applied between the base and the emitter terminals of the transistor. The value of this inductance determines the bandwidth of the negative resistance, with high values of inductance associated with operation at low frequencies and low values of inductance associated with operation at high frequencies. Using a simultaor’s optimization function it is possible to optimize this circuit to produce negative resistance over at least two octaves in frequency. The negative resistance appearing at the emitter-to-ground terminals is an impedance consisting of the negative resistor in series with an inductive reactance. In most cases, the value of this inductive reactance is very nearly equal to 2 F0Lf, where F0 is the operating frequency and Lf is the feedback inductor, which is connected between the transistor’s base and ground. As a simple electrical model for the active

Figure 13.21 A schematic diagram of a common-base Colpitts oscillator using a Gummel Poon transistor model and InGaP/GaAs HBT technology.

258

Voltage-Controlled Oscillator Design

part of this oscillator, the designer may use a negative resistance (created by the transistor plus its feedback) in series with the inductance, which is connected between the transistor’s base and ground. This circuit has significant advantages for VCO design because the base inductor can also function as the inductive portion of the VCO’s LC resonator. Of course, a varactor diode functions as the capacitance portion of the LC resonator and is completely responsible for electronic tuning. As shown in Figure 13.13, the varactor diode must be connected between the transistor’s emitter terminal and RF ground. Because the varactor diode’s capacitance is electronically tunable, the VCO’s frequency is controlled by the dc voltage applied to the varactor. The question that needs to be answered is, what is the bandwidth of the negative resistance? The best way to answer this question is to use simulator tools the exact values of the negative resistance as a function of frequency. A VCO circuit may first be optimized to maximize small-signal negative resistance over the frequency range of interest and later simulated in large-signal mode (i.e., harmonic balance) to calculate power output, exact frequency of oscillator at steady state, waveform shape, and phase noise. Loss in the resonator (i.e., the varactor diode’s series resistance) will work to prevent the oscillations from starting. Therefore, any successful VCO design must have a negative resistance that is significantly greater than the varactor diode’s series resistance at all frequencies of operation. To maximize the robustness of any oscillator, it is important to maximize both the negative resistance and the bandwidth of the negative resistance. Often, increased negative resistance and enlarged bandwidth can be achieved simultaneously by adding a reactive output matching network between the transistor’s collector and the load. This output matching network may simply be a shunt L and a series C. Or it could be a series L and a shunt C. The designer should experiment with several options. The same simple matching networks used within amplifier circuits can also be considered for use in oscillators. The simulator’s optimizer can be helpful for evaluating options. Both the resistance and reactance of the resonator must be accounted for in the circuit model if this process is to be meaningful. It is not unusual to simulate the forward gain of an oscillator. Such gain is important because excessive loss in the resonator must be made up for by gain if the oscillator’s circuit is to deliver a reasonable level of power output to the load under all conditions. If the gain is low (i.e., high loss exists between the resonator and the load) oscillator power may not be efficiently transferred from the resonator to the load, even if oscillations do start. Some gain, or at the least very little loss, is necessary to ensure that good power output is delivered into the load. 13.4.2

The Colpitts Oscillator Circuit

One of the oldest oscillator circuit topologies is called the Colpitts oscillator after its inventor Edwin H. Colpitts (1872–1949) [8]. The Colpitts circuit remains a very important class of oscillator circuits, and they are used today in a wide variety of RFIC applications. Figure 13.15 shows the schematic diagram of a common-base Colpitts oscillator (a common-collector version of the Colpitts oscillator is shown in Figure 13.14). The Colpitts circuit consists of a transistor Q1, a load resistor R, two capacitors (C1 and C2), and an inductor L.

13.4 Feedback Circuit Topologies for Producing Negative Resistance

259

As shown in Figure 13.21, a fully biased Colpitts oscillator circuit may be configured to allow the simulation of its input impedance, Zin, in order to test for a strong region of negative resistance over a band of frequencies. This reconfiguration involves the removal of the inductor, L, from the circuit and inserting a test port where the inductor had been connected. The reason for this change is the recognition that the inductor L represents the resonating element in a Colpitts oscillator circuit, and in order to produce oscillators, the rest of the oscillator’s circuit must present a negative resistance (that is, the real part of Zin must be negative) at the inductor’s terminals. For this purpose, we may follow the same procedure that was applied above to the negative-resistance oscillator. The schematic diagram for a fully biased common-base Colpitts oscillator using an InGaP/GaAs HBT Gummel Poon transistor model is shown in Figure 13.21. The equivalent schematic for its common-collector version is shown in Figure 13.22. The values of C1, C2, and L are chosen from experience to provide a negative resistance in the 3–6 GHz band of frequencies. The load resistor is lightly coupled to the oscillator circuit with a small value coupling capacitor. The simulation of Zin for this circuit is shown in Figure 13.23, and the common-collector circuit simulation is shown in Figure 13.24. The circuit’s maximum negative resistance is –33.5 ohms (overall Zin is capacitive, which means the oscillator will resonate when the inductor L is reconnected to the circuit) and occurs at a frequency of 2.4 GHz. The common-collector version of the Colpitts oscillator circuit has nearly identical negative-resistance performance to the common-base version. The transistor Q1 chosen for this oscillator is a ten-finger transistor. This larger transistor performs better that a smaller-size transistor because its Cbc is large, providing increased internal base-to-collector feedback, which is necessary for producing strong negative resistance with this class of oscillators. We next replace the transistor’s Gummel Poon simulator model with a current-controlled current source plus the parasitic capacitance, Ccb, in order to test the usefulness of this simple transistor equivalent circuit in Colpitts oscillator circuit

Figure 13.22 A schematic diagram of a common-collector Colpitts oscillator using a Gummel Poon transistor model and InGaP/GaAs HBT technology.

260

Voltage-Controlled Oscillator Design

Figure 13.23 The simulated impedance of the common-base Colpitts oscillator at its resonator terminals. This impedance is plotted on an “expanded” Smith chart. Notice that negative resistance is available over a frequency range of 1.0 to 10.0 GHz. A peak negative resistance of –33Ω occurs at 2.4 GHz.

Figure 13.24 The simulated impedance of the common-collector Colpitts oscillator at its resonator terminals. This impedance is plotted on an “expanded” Smith chart. Notice that negative resistance is available over a frequency range of 1.0 to 10.0 GHz. A peak negative resistance of –41Ω is obtained at 2.4 GHz. This result is almost identical to the simulated impedance of a common-base Colpitts oscillator shown in Figure 13.23.

simulations. Because we are dealing with a larger-size transistor (by a factor of ten) than in the case of the negative-resistance oscillator, the value of Cbc in the device model will increase by a factor of ten to about 1.0 pF. The circuit schematic for a

13.5 Frequency-Temperature Stability

261

Colpitts oscillator (common collector) with the simplified device model is shown in Figure 13.25. The simulated values of Zin over a band of frequencies is shown in Figure 13.26. The peak negative resistance is –17 ohms, which occurs at 15 GHz (as in the case of the Gummel Poon device model, Zin is capacitive). However, the value of Zin at increasingly higher frequencies agrees less well with that predicted using the Gummel Poon model. This result indicates that the simple CCCS-plus-Cbc model is not sufficiently accurate to predict the behavior of a Colpitts oscillator, and real design exercises will require the use of either Gummel Poon or VBIC device models. It is important to note that even if the device is made large to achieve strong negative resistance over a desired band of frequencies, the dc current should be kept low simply by adjusting the base-biasing circuit. By keeping the base current and the collector current low, the shot noise and 1/f noise (which is also current driven) contribution to the oscillator’s phase noise will be minimized.

13.5

Frequency-Temperature Stability The stability of an oscillator’s frequency over a range of temperatures is an important issue in many applications. Temperature stability of the resonator is controlled by factors such as differential thermal expansion of the materials used to construct the oscillator and the temperature-capacitance drift of the varactor diode itself. Varactor diode capacitance drifts considerably with temperature (see Section 13.1), so some means must be provided to prevent excessive temperature-frequency drift in varactor-tuned VCOs. The most common method involves the use of a phase-locked loop to hold the VCO’s frequency constant, as determined by an external high-stability frequency standard. Often, this standard operates at a much lower frequency. The VCO’s frequency must be divided down so that it can be compared with the reference signal under closed-loop conditions. The resulting overall frequency stability is determined by the reference oscillator and not by the VCO as

Figure 13.25 Modeling the common-collector Colpitts oscillator’s transistor as a CCCS with a parasitic capacitance Cbc connected between its base and collector terminals. The current source’s beta is set to a value of 100, which is consistent with Gummel Poon models. The base resistance is set to a low value (20 ohms), and the device’s collector resistance is set to a high value (10k).

262

Voltage-Controlled Oscillator Design

Figure 13.26 The simulated impedance of the modeled common-collector Colpitts oscillator. The frequency of the simulated negative resistance ranges from 5 GHz to over 15 GHz, with a value of –18 ohms obtained at 15 GHz. This result does not agree with its equivalent Gummel Poon model as well as the results obtained with the common-base, negative-resistance oscillator, shown in Figure 13.20. We conclude that there are additional important parasitic elements, which are accurately captured by the Gummel Poon transistor model, that are not present in the simplified model shown in Figure 13.25.

long as the VCO has sufficient electronic tuning (plus a good safety margin) to allow the phase-locked loop to “hold” the VCO’s frequency constant relative to the reference signal over the full required range of temperatures. The designer needs to make sure that a VCO design has ample electronic tuning so that the phase locked loop is not required to tune the oscillator into regions of low power or high phase noise at temperature extremes. Some basic trade-offs must be observed. For a particular varactor diode with a given tuning-voltage range, the only way to increase the amount of electronic tuning is to decrease the resonator’s Q. This can be done by decreasing the Q of the resonator’s inductance or by coupling the varactor diode more tightly to the inductor. However, when Q is reduced to increase the VCO’s electronic tuning range, the net effect is to cause an increase in phase noise since phase noise depends on the inverse square of the resonator’s Q. However, in the case of YIG-tuned oscillators (see Section 13.8), the oscillator’s resonator is tuned by an external magnetic field (generated by either a permanent magnet or by an electromagnet) acting on specialized magnetic properties of the YIG material (quantum mechanical spin precession), and in this case, no such trade-off exists between the resonator’s Q and the oscillator’s electronic tuning range. However, as is the case with all magnetically tunable oscillators, some amount of tuning power is required, in contrast to varactor diodes, which are voltage-tunable devices requiring no tuning current, therefore no tuning power.

13.6 Phase Noise

13.6

263

Phase Noise Noise sources within the transistor and varactor diode that form a VCO will modulate the output signal, producing low-level noise sidebands lying on either side of the main “carrier” signal. These noisy sidebands are called either amplitude modulation (AM) noise or phase noise. AM noise results from the noisy amplitude modulation of the oscillator by the noise sources. Phase noise results from the noisy phase modulation of the oscillator by the same noise sources. The spectra for oscillator phase noise is shown in Figure 13.27. Most systems are capable of cancelling AM noise, but phase noise remains a fundamental limitation on the performance of most wireless communications systems. Three kinds of noise sources are at work in the transistors and varactor diodes. The first is a low-frequency noise source called 1/f noise, which originates in surface-trapping states on the semiconductor material from which the devices are fabricated (see Chapter 8). The second noise source is called thermal noise. Thermal noise is a direct result of the thermal agitation of the charge carriers within the electron gas that comprises the current flowing within semiconductor devices. The third noise source is called shot noise, which is a noise source related to the discreteness of electronic charge. First, consider what happens in the case of thermal noise [9]. Thermal noise sources modulate the oscillator’s frequency and phase such that a mean square frequency deviation, ∆ 2 is created. This frequency deviation modulates the carrier.

Figure 13.27 The phase-noise spectrum of any oscillator is divided into three distinct frequency regions. The lowest of these regions is called the 1/f region and is a result of upconverted 1/f noise generated within the transistor. Phase noise in the 1/f region has a slope of 30 dB per decade with offset frequency. The middle region is called the thermal noise region. Thermal phase noise is a direct result of thermal noise (i.e., kTB) noise effects within the transistor. In bipolar transistors, shot-noise-generated phase noise behaves in much the same way as thermal phase noise. Thermal phase noise has a slope of 20 dB per decade with offset frequency. The frequency where 1/f phase noise transitions to thermal phase noise is called the 1/f corner frequency. With bipolar transistors, the 1/f corner frequency is in the range of 1 to 100 KHz. At the highest frequencies, phase noise becomes flat with offset frequency as it enters the background region. Background phase noise is a result of the noise figure of components external to the oscillator, such as buffer amplifiers.

264

Voltage-Controlled Oscillator Design

The value of this mean square frequency deviation may be calculated from the expression ∆

2

=

0

2

kTnB/4Qr2Pout

(13.25)

where is the oscillator’s angular center frequency. k is Boltzmann’s constant (1.38 × 10–23 J/K). Tn is the transistor equivalent noise temperature. B is the bandwidth of measurement. Qr is the resonator’s quality factor (the energy stored per cycle divided by the energy dissipated per cycle). Pout is the oscillator’s power output. ∆ 2 is the oscillator’s thermal mean square frequency deviation. 0

A similar expression to the above equation (13.25) can be derived for the phase noise associated with shot noise sources. In bipolar devices, shot noise, like thermal noise, is flat with frequency. but unlike thermal noise, it is proportional to dc current. Both base and collector currents make independent contributions to shot phase noise. As in the case of LNAs (see Chapter 8), bipolar VCOs will exhibit their lowest phase noise far from the carriers if their base and collector currents are kept to a minimum. Of course, there is a trade-off between shot noise intensity and the Pout term in the denominator of (13.25). Some intermediate current will deliver the best noise. The mean-squared frequency deviation can be converted into a phase-noise power-to-carrier power ratio in units of dBc per hertz by using the equation N/C (dBc) = ∆

2

/

2 m

(13.26)

where m is the frequency offset from the carrier (i.e., the modulation frequency). Because of the inverse square dependence of (13.26) on m, the phase-noise spectrum of any oscillator far from the carrier (i.e., beyond the effect of 1/f noise) decreases at a 20 dB per decade rate. Thermal noise dominates phase noise far from the carrier. However, upconverted 1/f noise dominates phase noise at frequencies close to the carrier [10]. The upconverted, mean-squared frequency deviation of a transistor oscillator is given by ∆

2

=[

o

(∂Cd/∂V0)/2QrGr]2Sv0(

)B

m

(13.27)

where is the oscillator’s angular center frequency. ∂Cd/∂V0 is the active device’s capacitance change with voltage (i.e., the change in emitter base capacitance with Vbe). Qr is the resonator’s quality factor. Gr is the resonator’s equivalent parallel conductance. o

13.6 Phase Noise

265

Sv0( m) is the spectrum of the low-frequency noise fluctuations. m is the offset angular frequency. B is the bandwidth of measurement. The phase noise, in terms of a noise-to-carrier ratio associated with (13.27), is given by applying (13.26) to (13.27). Since the cause of the low-frequency phase noise is 1/f noise, the spectrum Sv0( m) has a 1/f shape in frequency and assumes the form of Sv0(

)B = N/(

m

)

m

(13.28)

where N is a noise strength parameter. is a spectrum shape coefficient (close to 1.0). The upconverted 1/f phase noise has a 1/( m)3 dependence on m, based on the inverse square term from (13.17) and the inverse frequency dependence of Sv0( m) from (13.28). The total effect is to predict (as shown in Figure 13.27) a phase-noise-to-carrier ratio that falls at a 30 dB per decade rate (i.e., 1/( m)3), in the same way that the thermal phase noise found far from the carrier falls at a rate of 20 dB per decade. Every oscillator has a point in offset frequency ( c) where the close-in, upconverted 1/f noise exactly equals the thermal noise. This point is called the corner frequency, Fc. For offset frequencies less than the corner frequency, the phase-noise spectrum decreases at a 30 dB per decade rate. For offset frequencies greater than the corner frequency, the phase-noise spectrum decreases at a 20 dB per decade rate. A 30 dB per decade region (associated with upconverted 1/f noise) is clearly seen at low offset frequencies, and a 20 dB per decade region (associated with thermal noise) is clearly seen at high offset frequencies. All oscillators have a noise spectrum that follows this general shape. Notice that both the expression for thermal phase noise (13.25) and the expression for upconverted 1/f phase noise (13.27) depend inversely on the square of the resonator’s quality factor. This factor is the single most important circuit parameter for controlling phase noise. Qr must be maximized to ensure low phase noise both close to and far from the carrier. A problem that develops in the design of VCOs comes about because the amount of electronic tuning range also depends inversely on the square of the resonator’s quality factor. This means everything that is done to reduce phase noise will also reduce the VCO’s electronic tuning range, and everything that is done to increase the VCO’s electronic tuning range will also increase its phase noise. Not much can be done to improve this situation except to pick an active device with minimum noise temperature and minimum 1/f noise. Bipolar devices are always the best choice in this regard because their vertical structure is not influenced by the surface-trapping states that cause 1/f noise. The lowest noise bipolar transistors offer excellent phase noise in VCO applications because their 1/f corner frequency is so low (about 50 KHz for InGaP/GaAs HBT and 1 KHz for SiGe.)

266

13.7

Voltage-Controlled Oscillator Design

Quadrature Phase-Shifting Networks Because nearly all wireless applications rely on I/Q upconverting mixers in transmitter architectures and I/Q downconverting mixers in receiver architectures, it is necessary to phase-shift the LO signals for these mixers by 90° when applying the LO signal to the Q mixer’s LO port. If LO frequency division is used in the overall system architecture, this quadrature phase shift can be accomplished digitally by the divider circuits. However, if the LO signal is planned to be at the same frequency as the VCO’s output, it becomes necessary to design a circuit that provides an accurate 90° phase shift of one LO output relative to the other. Since the mixer inputs are differential, in reality it becomes necessary to produce four LO signals, each one separated by 90° (see Chapter 6). The I mixer LO signals will be at phases of 0° and 180°. The Q mixer LO signals will be at phases of 90° and 270°. There are three circuit types that can provide the required quadrature phase shift, as discussed in Chapter 6. These are a polyphase network, a low-pass network, and a high-pass network. The low-pass and high-pass filter networks are identical to those described in Sections 6.1 and 6.2. As discussed in these sections, a single-section low-pass filter circuit has exactly –90° phase shift at Fh, and the single-section high-pass filter circuit has exactly +90° phase shift at Fh. Therefore, either circuit will phase-shift the input LO signal by the required 90°, at a single frequency, Fh. With both the low-pass and the high-pass filter circuits, the zero phase-shifted LO output will simply be the input signal, and the 90° phase-shifted LO signal will be the filter’s output. If operation over a broadband of frequencies is required, it is best to consider using the digital divider approach for quadrature phase-shifting since passive filtering networks are inherently narrowband. The polyphase circuit has two outputs that are shifted in phase by +/–45°, again at a single frequency. Because of impedance interactions it may be necessary in the case of the low-pass and the high-pass filter networks to split the input power with a resistive power splitter (see Chapter 6).This technique is used to split the two output LO signals while maintaining a good 50 ohm match at the filter’s inputs. At the filter’s output, it is assumed the mixer’s LO terminals will provide a good 50 ohm match to the phase-shifting networks. However, if this is not the case, it may be necessary to load the phase shifter’s output with a shunt resistor to ensure the existence of a good 50 ohm match. Achieving a good match is important because the filter’s design requires a known output impedance to ensure that the performance of the network is consistent with its design. The filter design (see Chapter 6) was based on a particular value of impedance. Figure 6.26 provides a block diagram showing a demonstration for converting single-ended phase shifters into differential phase shifters, provided the VCO’s output is in differential form (see the design example below). It is for this reason that the design of a differential VCO becomes important. Without a differential VCO output, it would become necessary to provide an on-chip balun to accomplish the single-ended-to-differential conversion. If necessary, this can be done by using the combination of a low-pass filter and a high-pass filter, as shown in Figure 6.24. However, the use of a naturally differential VCO will prevent having to deal with the design and real estate requirements of an on-chip balun.

13.8 Ring Oscillators

13.8

267

Ring Oscillators Traditional YIG-tuned oscillators (YTOs) have made use of a negative-resistance-type circuit and very large magnetic structures to produce microwave sources with extremely linear magnetic tuning and excellent phase noise over an electronic tuning range of one to two octaves. In many important ways, YTOs offer superior performance relative to other types of oscillators, such as VCOs and dielectrically tuned oscillators (DTOs); however, size and weight considerations have long prevented the adoption of YTOs by many areas of the electronics industry. This is especially true of YTOs operating in the Ku band or higher, where the traditional YTO magnetic structures are very large. Varactor-tuned VCOs are small and light but lack the wide linear tuning range and low phase noise of YTOs. DTOs have excellent phase noise but are limited to fixed-tuned applications. Also, DTOs remain expensive due to the high cost of the skilled alignment labor required for their manufacture. Recently, a significant advance in the YTO field has been made by R. Parrott at Vida Products [11, 12], offering superior performance by making use of a patented (U.S. patent # 5,801,591) highly refined miniature magnetic structure tuning a single-sphere YIG filter that completes a feedback loop as part of a InGaP/GaAs HBT ring oscillator circuit topology of the kind described by A. Hajimiri and T. Lee [13]. The magnetic structure is less than one-quarter the size and weight of traditional YTOs but is capable of tuning the oscillator to 18 GHz and beyond. The ring oscillator circuit topology uses a InGaP/GaAs HBT Darlington amplifier circuit (see Chapter 9) providing nearly flat gain from dc to 15 GHz. Ring oscillator circuits use positive feedback, which can start oscillations over the full operating bandwidth of the amplifier, providing the parallel feedback around the amplifier produces an open-loop gain greater than 0 dB and an open-loop phase of N(2 ), where N is an integer. As long as these conditions are met, the resulting oscillator can potentially be tuned over the entire bandwidth of the amplifier, which, in the case of an HBT Darlington amplifier, could exceed one decade (see Chapter 9). Traditionally, YTOs use silicon bipolar transistors for applications up to 10 GHz and GaAs MESFET transistors above 10 GHz. In both cases, negative-resistance circuits are used. The silicon bipolar circuit makes use of a common-base configuration with an inductive feedback element connecting the transistor’s base to ground (see Section 13.4.1). The GaAs MESFET circuit uses a common source configuration with a capacitive feedback element connecting the transistor’s source to ground. Both types of negative-resistance circuits are limited at high and low frequencies because of reactance shifts within their inductor and capacitor feedback elements. Because of these considerations, negative-resistance oscillators are inherently limited to one to two octaves of bandwidth. In terms of phase noise, the silicon bipolar circuits are quite good as a direct result of the low 1/f noise associated with this class of transistor. However, in the case of GaAs MESFET devices, which are most often used at high frequencies, the close-in phase noise (in the 1/f3 region) is often poor due to up conversion of the 1/f noise produced by surface-trapping states associated with this class of transistor. The result is that traditional YTOs can produce excellent phase noise up to 10 GHz, but at higher frequencies, their phase noise may be compromised.

268

Voltage-Controlled Oscillator Design

We now compare these YTO characteristics with what can be obtained with the ring oscillator topology shown in Figure 13.28. The ring oscillator is made up of a InGaP/GaAs HBT Darlington amplifier and a YIG-tuned filter closing a parallel feedback path around the amplifier. A second, identical Darlington amplifier serves as a buffer amplifier, reducing load-pulling effects and raising the output power. As long as the open-loop gain and phase requirements for oscillation are satisfied, this circuit can oscillate over the full frequency range of the amplifier. In terms of phase noise, like their silicon bipolar counterparts, GaAs HBTs are bipolar transistors and are far less subject to 1/f noise than are GaAs MESFETs, which usually exhibit strong 1/f noise created by surface-trapping states. Therefore, we expect this circuit topology to yield excellent phase noise up to 20 GHz and beyond. The ring oscillator is composed of a wideband Darlington amplifier plus a YIG-tuned filter. This filter, which is configured as two half-loops offset by 90°, is a natural differential circuit. The filter’s behavior is critical to the overall operation of the YTO because it is this magnetically tunability of the filter that selects the frequency at which oscillation starts. In the YIG-tuned ring oscillator, the filter consists of two half–wire loops, one running under the YIG sphere and the other running over the top of the sphere. The clearance between the sphere and the loops is 10 mil. YIG resonance is a direct result of a quantum mechanical phenomenon called spin precession. Unlike circuit element resonators, such as those found in varactor-tuned VCOs, YIG resonators, by virtue of their quantum mechanical nature, maintain high Q factors to extremely high frequencies. The result is low phase noise over extremely wide tuning bandwidths. The spin-precession resonant frequency of YIG is set by a z-directed dc magnetic field, Hdc. The RF magnetic field vector, which is in the x-y plane, rotates at right angles to the dc magnetic field, which is aligned along the z axis. Hrfx and Hrfy are the x- and y-directed components of the rotating RF magnetic field associated with spin precession. Because RF currents flow in opposite directions within the two (top and bottom) coupling loops, a natural 180° phase shift occurs between the same-sided filter inputs and outputs. Since the physical plane of the top loop is rotated by 90° relative to the physical plane of the bottom loop, a natural 90° phase shift occurs between the loops because one of them is always experiencing a peak of the RF magnetic field occurring at 90° relative to the other. Therefore, a total phase shift of 270° is directly BUFFER AMP OUT

YIG SPHERE STUB

YIG RESONATOR

OSCILLATOR AMP FB LOOP BLOCKING CAP

Figure 13.28 The block diagram of a YIG-tuned ring oscillator using a Darlington amplifier (see Chapter 9) to produce loop gain and an identical Darlington amplifier used as a buffer stage.

13.8 Ring Oscillators

269

associated with the YIG filter. The measured S21 of this YIG filter at F0 = 12 GHz is shown in Figure 13.29. The filter’s 3 dB bandwidth is about 25 MHz. For simulation purposes, this YIG filter is modeled as a differential Bessel filter coupled to the surrounding loop elements by two ideal transformers. The bandwidth of each filter is set to 25 MHz, which implies a Q factor of about 600 at 12 GHz. Identical wideband Darlington gain block amplifiers are used in the ring loop and as a buffer amplifier. The gain block amplifier makes use of a Darlington topology and GaAs/InGaP HBT fabrication technology. The amplifier’s two bipolar transistors have emitter dimensions of 2 × 20 µm and 2 × 40 µm, respectively. This amplifier, whose overall dimensions are 350 × 500 µm, has nearly flat gain from dc to 15 GHz and almost constant phase shift over frequency. The amplifier’s outstanding performance is due to its small size and freedom from parasitic elements. The amplifier’s measured S-parameters are shown in Figure 13.30. A model for the Darlington amplifier, including layout parasitic elements, is used to simulate the performance of the ring oscillator. Agreement between the measured and simulated amplifier performance is excellent. The amplifier’s dc bias conditions are set by design to 5.0V at 50 mA. The oscillator’s open-loop gain and phase may be analyzed in the following way: The elements of the open-loop oscillator circuit are connected in a way that the loop is opened for analysis. The open-loop gain and phase of the oscillator may now be simulated to determine the conditions necessary for the start of oscillation. If we simply add up the individual phase contributions around the loop, we get 2 plus 90°. However, component interactions and the effect of stub tuning reduce this total to 360° (i.e., 2π). Simulations of the open-loop gain and phase at 12 GHz are shown in Figure 13.31.

Figure 13.29 The measured S-parameters (S21) of a YIG resonator, showing a bandwidth of about 25 MHz at 12 GHz. This measured performance corresponds to a Q of about 500. (Source: Courtesy of Vida Products, Inc.)

270

Voltage-Controlled Oscillator Design

Figure 13.30

The measured S-parameters of the Darlington loop (and buffer) amplifier.

Figure 13.31 Simulated open-loop gain and open-loop phase of the YIG-tuned ring oscillator as evaluated at 12 GHz. Since there is net gain around the loop and the open-loop phase at is zero, start-oscillation conditions are fulfilled at 12 GHz.

Notice that the open-loop gain is greater than 0 dB, and the phase shift is centered at 0° (i.e.,0 × 2 ) and is adjustable with the length of a coplanar wave-guide stub connected to one port of the YIG filter. This transmission-line stub serves as a phase adjustment, providing an easy way to set the center frequency of the desired band of oscillations. At 12 GHz, the open-loop phase shift may be adjusted by +/–40° with this stub. Adjustment of the stub’s length is the only alignment step required during the manufacture of this YTO, leading to low manufacturing costs. The simulated open-loop gain and phase fulfill all of the conditions for start oscillation as stated in Section 13.2. In the physical realization, the circuit elements are

13.8 Ring Oscillators

271

mounted on a ceramic substrate, which has a cutout allowing the YIG sphere to be mounted in the middle of two orthogonal half–coupling loops (one on the top and one on the bottom of the YIG sphere). A diagram of the YTO’s magnetic structure is shown in Figure 13.32. This miniature YTO uses a permanent magnet ring and field focuser to define a narrow air gap, typically 100 mil, in which the YIG sphere is located. The permanent magnetic determines the center of the band operating frequency. The main tuning coil surrounding the permanent magnet has 2,200 turns, providing a tuning rate of 25 MHz per mA. Tuning current will raise or lower the frequency relative to band center. A shield magnet above the field focuser prevents magnetic flux from flowing in the outer shell. These magnetic shielding techniques greatly reduce the effects of mechanical vibration and “phase hits” that occur at temperature extremes or under mechanical shock or vibration. The YTO’s overall size (including outer shell) is 0.75 in. in diameter and 0.60 in. in height. Its weight is 25g. This structure can easily be adapted to surface-mounted technology. By closing the loop, it is possible to simulate the YTO’s power output, waveform, and phase noise over a range of frequencies. According to Hajimiri and Lee, it is important with ring oscillators to maintain a highly symmetric output waveform in order to keep the phase noise associated with upconverted 1/f noise to a minimum. Since the GaAs/InGaP HBT devices generate very little low-frequency 1/f noise due to their bulk effect structure, the presence of a highly symmetric waveform will provide double protection against 1/f3 low-frequency phase noise associ-

Tuning coil

Ring magnet Shield magnet

YIG

Field focuser

Figure 13.32 A mechanical cross section of the miniature YIG-tuned ring oscillator. (Source: Courtesy of Vida Products, Inc.)

272

Voltage-Controlled Oscillator Design

ated with upconverted 1/f noise. Simulations have demonstrated that this oscillator’s output waveform is nearly sinusoidal over a wide range of operating frequencies, fulfilling the Hajimiri, Lee conditions. The oscillator’s simulated power output is shown in Figure 13.33. Strong oscillations are predicted over an octave from 7 to 14 GHz, with power output in access of +10 dBm. Under closed-loop conditions, the simulated phase noise at 12 GHz, which is shown in Figure 13.34, is less than –125 dBC per hertz at 100 KHz. This phase-noise performance represents greater than 10 dB improvement over MESFET YTOs operating at this frequency. Simulations of frequency pulling into a 2:1 VSWR load rotating through all phases indicates a +/–10 KHz frequency shift, and simulated frequency pushing is on the order of 500 KHz/V. The measured power output as a function of tuning is shown in Figure 13.35. Measured power is about +10 dBm, closely following the simulated power output. Tuning bandwidth can be adjusted inversely with stub length. Measured phase noise at 12 GHz, given in Figure 13.36, was found to be in close agreement with the simulated phase noise. The measured phase noise of this oscillator is a significant step forward in improving YTO performance at the X and Ku bands.

13.9

Design Example 7: 802.11a (Wi-Fi A) Differential VCO The following example shows a procedure for designing a differential RFIC VCOs for wireless communications applications [14–16]. This particular VCO is designed to operate in the 6 GHz range for 802.11a applications. However, a similar procedure could be followed for any desired band of operation. For 5V supply operation,

Figure 13.33 The simulations of the YIG-tuned ring oscillator’s power output, exact center frequency, and voltage and current waveforms, when the circuit’s YIG resonator is tuned to 18.0 GHz.

13.9 Design Example 7: 802.11a (Wi-Fi A) Differential VCO

273

Figure 13.34 The simulated phase and amplitude noise for the YIG-tuned ring oscillator operating at 18 GHz. Notice that the phase noise at 10 KHz offset frequency is –103 dBc, which is approximately 30 dB lower than what can be obtained with the best varactor-tuned VCO operating at this frequency.

Figure 13.35 The measured power output of a YIG-tuned ring oscillator operating from 7 to 14 GHz. The adjustable parameter is the open stub’s length. (Source: Courtesy of Vida Products, Inc.)

the technology of choice is InGaP/GaAs. For 3V supply operation, the technology of choice is SiGe.

274

Voltage-Controlled Oscillator Design

Figure 13.36 A chart comparing the measured and simulated phase noise of a YIG-tuned ring oscillator operating at 12 GHz. (Source: Courtesy of Vida Products, Inc.)

The VCO’s top-level schematic diagram is similar to that shown in Figure 13.16. The return side of the varactor resonator is connected to a terminated test port. S11 measured at this port will give an indication of the magnitude and frequency range of the oscillator’s negative resistance. For this design, 5V operation will be used, so the technology of choice is GaAs/InGaP HBT. Component blocks on the top-level schematic contain the transistor-level oscillator schematic diagram and the varactor diode resonator. Both the transistor and the varactor diodes have large-signal models associated with them. Figure 13.37 contains the transistor-level schematic diagram of the oscillator circuit, including common-base inductive feedback and all of the necessary bias control resistors. Spiral inductors are used for feedback and collector bias current injection, and the emitter dc ground return. The three ports of the oscillator block are RF output, varactor resonator, and dc bias. Figure 13.38 contains the elements in the varactor resonator component block, including the

Figure 13.37 The schematic diagram of the transistor-level varactor-tuned VCO circuit using a negative-resistance oscillator circuit topology and InGaP/GaAs HBT technology.

13.9 Design Example 7: 802.11a (Wi-Fi A) Differential VCO

275

Figure 13.38 The schematic diagram of a varactor resonator, including a blocking capacitor and a bias choke inductor.

varactor’s model. A layout of this VCO is shown in Figure 13.39. This layout provides for an off-chip varactor diode since these devices are rarely available in InGaP/GaAs foundry processes. However, if the VCO were fabricated in SiGe technology, the varactor diode would be on-chip (see Chapter 5). Initial simulations are used to determine start-oscillation conditions. The simulated S-parameters (S11) at the resonator’s return port (which is electrically equivalent to an open-loop condition with a feedback amplifier) are found in Figure 13.40. These parameters are displayed as both magnitude (in decibels) and angle, and also as a reflection coefficient plotted on a Smith chart. In the Smith chart presentation, the negative-resistive region, as a function of frequency, is clearly seen as lying output side of the normal (magnitude S11 = 1.0 circle) Smith chart. That is, the com-

Figure 13.39

The layout of the varactor-tuned negative-resistance oscillator.

276

Voltage-Controlled Oscillator Design

Figure 13.40 The simulated S-parameters of the varactor-tuned VCO are shown, predicting that start oscillation will occur at a frequency of 6.0 GHz. The oscillator’s net negative resistance, including losses in the varactor, is –25ohms at 6.0 GHz.

bined oscillator/resonator circuit will present a net negative resistance as a function of frequency for all S11 that lie beyond a reflection coefficient of 1.0. Notice that for the chosen tuning voltage, the resonance in phase shift occurs at 6 GHz, and the negative resistance at that frequency is about –26Ω in magnitude. This is a strong negative resistance, and oscillations will start once the resonator’s return port is attached to ground. By adjusting the tuning voltage on the top-level schematic (Figure 13.37), the resonant frequency may be varied from 5 to 6 GHz, covering all of the 802.11a band. Next, the oscillator’s steady-state performance is simulated by using large-signal simulator analysis. Notice that a component block called “oscport” must be added to the schematic diagram between the oscillator circuit block and the varactor diode resonator circuit block for ADS simulations. The purpose of oscport element block is to allow the simulator (ADS) to sense the frequency and signal levels as oscillations build up. There is some art to properly locating the oscport block in the overall schematic diagram. The best insertion point seems to be at a break in the circuit where the resonator connects to the negative-resistance portion of the oscillator, but there are many other possibilities. In theory, any connection within the oscillator’s circuit should work as an oscport location. However, experience has shown that some locations are better than others in terms of successful convergence of the final large-signal performance parameters. Figure 13.41 shows the simulated large-signal performance of the oscillator. Parameters given in Figure 13.41 are the oscillator’s power output at its fundamental frequency and also at several harmonic frequencies. (The oscillator’s spectrum is

13.9 Design Example 7: 802.11a (Wi-Fi A) Differential VCO

277

Figure 13.41 Simulations of the varactor-tuned VCO’s power output, frequency, and output voltage waveform. Simulated dc base and collector currents are shown.

displayed in terms of a harmonic number index.) The fundamental frequency and all harmonics frequencies are also given. The waveform of the output voltage is plotted versus time. There is a little high-voltage clipping of the waveform, which is an indication of how the saturation process is occurring for this oscillator. Notice that the oscillation frequency has increased (7.3 GHz versus 6 GHz) relative to the small-signal plots shown in Figure 13.40. This is a demonstration of how large-signal reactive effects can occur as the oscillator’s signal builds up. The oscillator may require frequency retuning to account for these effects. The oscillator’s phase noise may be simulated with the help of the slightly modified top-level schematic diagram. In Figure 13.42, the simulated phase noise is shown plotted as a function of offset frequency. It is often helpful when plotting phase noise to use a log scale on the x axis, which is the offset (or modulation) frequency. By plotting the log of offset frequency, it is possible to display up to six or more decades in frequency on a single plot. Such a graphical display can be very meaningful with phase-noise simulations. The universal units of phase noise are dBc per hertz calculated at each offset frequency. The ADS simulator uses two different algorithms to calculate phase noise. The first is a frequency-modulation algorithm; the second is a noise-mixing algorithm. Experience indicates that the frequencymodulation algorithm yields results that are closer to actual measured data. In addition to phase noise, ADS also calculates the oscillator’s amplitude noise. This noise is of less practical interest because most balanced mixers naturally cancel any LO amplitude noise. Notice that phase noise (using the frequency-modulation algorithm) rolls off at an unchanging 20 dB per decade over at least six decades of offset frequency. This is because the Gummel Poon model used for the oscillator’s transistor contains only thermal noise and shot noise parameters and no 1/f noise (because

278

Voltage-Controlled Oscillator Design

Figure 13.42 The simulated phase noise of the varactor-tuned negative-resistance VCO operating at an output frequency of 6.9 GHz.

the 1/f noise parameters have been set to zero). Had 1/f noise parameters been present in the Gummel Poon model, at offset frequencies below the 1/f corner frequency, the rate of descent would have become 30 dB per decade.

13.10

Figure of Merit A metric called the figure of merit (FOM) of an oscillator has been developed to allow designers to calculate a single number that characterizes an oscillator’s phase noise performance in order to easily compare the relative phase-noise performance of a number of oscillators [17]. The calculation of FOM relies on the fact that thermal phase noise depends on the square of the oscillator’s center frequency, F0, and the inverse square of the offset frequency of measurement, Fm. Also, phase noise depends inversely on the oscillator’s output power. Taking into account these three natural behaviors, any oscillator’s phase noise can be “normalized” in terms of center frequency, offset frequency, and power output (this item is handled by using the oscillator’s dc power in order to include the oscillator’s dc-to-RF conversion efficiency within the final metric). The final FOM value for a given oscillator characterizes that oscillator’s resonator Q, dc-to-RF conversion efficiency, and device noise temperature (noise figure). An equation for FOM is the following FOM = 20log(F0/Fm) – 10log(Pdc) – [measured phase-noise (at F0, Fm)]

(13.29)

13.11 Electronic Tuning and a Differential VCO Topology

279

As an example, consider the calculation of the FOM for the VCO shown in Figure 13.42. In the case of this VCO, its phase noise is –55 dBC for Fm = 10 KHz. The oscillator’s dc power is 0.02W(5V × 4 mA), and the VCO’s center frequency is 7.0 GHz. In this case, FOM is calculated as FOM = 20log(7E9/10E3) –10log(0.02) – (–55) FOM = 117 + 17 + 55 = 189 dBc/Hz

The result of 189 is an excellent FOM for a VCO and indicates that this particular VCO design is highly competitive in terms of phase-noise performance with other types of VCOs. Since 1/f phase noise is greater than thermal phase noise at all offset frequencies below the corner frequency, it follows that FOM values calculated at low offset frequencies will exhibit strong 1/f characteristics, which will negatively affect FOM compared to FOM predictions calculated for higher offset frequencies (i.e., beyond the corner frequency). Although the intent of FOM is to calculate a single number that characterizes an oscillator’s behavior, in reality, it is necessary either to specify which Fm was used in making the calculation or to always ensure that Fm is well beyond the corner frequency so that the phase noise being compared is always purely thermal (or shot) in its origin.

13.11

Electronic Tuning and a Differential VCO Topology It is possible to reconfigure ADS’s harmonic-balance controller in such a way that simulation parameters will sweep across the oscillator’s tuning range so that power output and frequency are graphically plotted as a function of tuning voltage. By setting the tuning voltage to sweep from 0V to 3V, the simulation can demonstrate (as shown in Figure 13.43) that the oscillator’s frequency is tuned from 5.7 to 6.8 GHz. Also, over this tuning range, the oscillator’s output power varies from –1.5 dBm at the low end (consistent with the higher varactor loss at lower voltage) to 0.0 dBm at the high end (consistent with the lower varactor loss at higher voltage). The ability to sweep varactor voltage is useful for simulating the final performance of a VCO circuit. This ability to sweep power and frequency as a function of tuning voltage allows the designer to know instantly how much electronic tuning range is available with a given design and how much output power will vary across the VCO’s tuning range. Since most mixers (e.g., Gilbert cell mixers) require a differential LO input, it would be useful to design a differential VCO [18]. By placing two oscillator transistors in this VCO topology we can accomplish this goal in much the same way as when two amplifier transistors are placed in parallel within a differential amplifier topology. A tail transistor is attached to the common emitter connection of the two oscillator transistors to control dc current. The tail transistor is used as a gain control for starting oscillations and for setting the oscillator’s dc current. A schematic diagram for the entire differential oscillator is shown in Figure 13.44. The base of each of the oscillator transistors is connected to a feedback inductor, whose other end is attached to an RF ground, which is also connected to a dc base-biasing net-

280

Voltage-Controlled Oscillator Design

Figure 13.43 The simulated sweeped power output and sweeped frequency of the negative-resistance VCO as a function of varactor tuning voltage (from 0.0V to 3.0V). Under these conditions, the simulated power output ranges from –1.5 dBm at 0.0V to 0.0 dBm at 3.0V. The frequency ranges from 5.8 GHz at 0.0V to 6.9 GHz at 3.0V. This behavior is consistent with the typical behavior of an abrupt-junction varactor diode, with the expected high capacitance and high series resistance at low voltages (corresponding to low frequency and low power) and low capacitance and low series resistance at high voltages (corresponding to high frequency and high power).

Figure 13.44 The schematic diagram of a differential varactor-tuned VCO circuit. This circuit uses SiGe technology.

work. A back-to-back pair of tuning varactor diodes is connected from the collector of one transistor to the collector of the second transistor. Where the varactor diodes meet along the oscillator’s centerline, tuning voltage is applied in such a way that the total voltage drop across each diode is equal to the (Vcc – Vtuning). This means that when Vtuning is equal to Vcc, the varactor diode’s voltage is zero (i.e., Vcc – Vcc). However, if Vtuning is equal to zero, the varactor diode voltage is equal to Vcc in the reverse direction because of the direction of diode connection. Also, connected across the pair of varactor diodes is an inductor, which serves as a resonator element (which is helpful in setting the center frequency) within the differential oscillator. All of the

13.11 Electronic Tuning and a Differential VCO Topology

281

base-bias circuits are supplied from separate bias supplies. The oscport block is connected between one of the transistor’s bases and RF ground (through a 100 pF capacitor). This choice of oscport block placement is just a guess that worked well, but other placements may work equally well. The simulated performance of the complete differential oscillator is shown in Figure 13.45. Notice that the waveforms at the Vout+ and Vout– ports are exactly 180° out of phase, as is expected with any differential signal. The fundamental power output is –3.8 dBm, and the fundamental operating frequency is 8.9 GHz. The dc operating current of this oscillator is low (4 mA). By creating this differential oscillator, we avoid the necessity of including an on-chip balun for converting the single-ended output of a conventional oscillator into a differential output for connection to the differential LO port of a Gilbert cell mixer. The one disadvantage of this type of oscillator is the extra chip area that it occupies. However, the differential form of this VCO is likely to pay for itself in terms of avoiding the headaches associated with designing and laying out a broadband on-chip balun.

Figure 13.45 The simulation of a differential varactor-tuned VCO circuit showing its power output, frequency (8.9 GHz), dc current, and voltage waveforms at the oscillator’s two outputs. Inspection of the waveforms demonstrates that the two outputs are exactly 180º out of phase.

References [1] Sweet, A., MIC and MMIC Amplifier and Oscillator Circuit Design, Norwood, MA: Artech House, 1990. [2] Razavi, B., RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.

282

Voltage-Controlled Oscillator Design [3] Uwano, T., et al., “Design of a Low Phase Noise VCO for an Analog Cellular Portable Radio Application,” Vol. 77 (part 2), No. 3, 1994, pp. 58–65. [4] Milnes, A., Semiconductor Devices and Integrated Electronics, New York: Van Nostrand Reinhold, 1980. [5] Shin, H., et al., “A 1.8V, 6/9-GHz Switchable Dual-Band Quadrature LC VCO in SiGe BiCMOS Technology,” IEEE Radio Frequency Integrated Circuits (RFIC) Symp., Seattle, WA, 2002. [6] Soyuer, M., et al., “Low-Power Multi-GHz and Multi-Gbps SiGe BiCMOS Circuits,” Proc. IEEE, Vol. 88, No. 10, October 2000, pp. 1572–1582. [7] Gray, P., et al., Analysis and Design of Analog Integrated Circuits, New York: John Wiley and Sons, 2001. [8] Lee, T., The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge: Cambridge University Press, 1998. [9] Leeson, D., “A Simple Model of Feedback Oscillator Noise Spectrum,” Proc. IEEE, Vol. 54, February 1966, pp. 329–330. [10] Sweet, A., “A General Analysis of Noise in Gunn Oscillators,” Proc. IEEE, Vol. 60, No. 8, August 1972. [11] Sweet, A., and Parrott, R., “A Novel Miniature YIG-Tuned Oscillator Achieves Octave Tuning Bandwidth with Ultra Low Phase Noise in X and Ku Bands,” IEEE Microwave Symp., San Francisco, CA, June 2006. [12] Sweet, A., and Parrott, R., “A Miniature YIG-Tuned Oscillator/Frequency Divider Achieves Octave Tuning Bandwidth with Ultra Low Phase Noise in S, C X and Ku Bands,” European Microwave Conf., Manchester, UK, September 2006[[AQ: dates?]]. [13] Hajimiri, A., and Lee, T., “A General Theory of Phase Noise in Electrical Oscillators,” IEEE J. Solid State Circuits, Vol. 33, No. 2, 1998, pp. 179–194. [14] Rael, J., and Abidi, A., “Physical Processes of Phase Noise in Differential LC Oscillators,” Proc. CICC 2000, pp. 569–572. [15] Lai, P., and Long, S., “A 2.4 GHz SiGe Low Phase Noise VCO Using On-Chip Tapped Inductor,” IEEE ESSCIC 2003, pp. 505–508. [16] Zhang, L., “A 37~50 GHz InP HBT VCO IC for OC-768 Fiber Optic Communication Applications,” 2002 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., Seattle, WA, June 2002. [17] Lai, P., and Long, S., “A 5-0GHz pHEMT Transformer-Coupled VCO,” 2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symp.,” Long Beach, CA, June 2005. [18] Tiebour, M., “Low-Power Low-Phase Noise Differentially Tuned Quadrature VCO Design in Standard CMOS,” IEEE J. Solid State Circuits, Vol. 36, No.7, July 2001, pp. 1018–1024.

CHAPTER 14

Layout Design Strategies 14.1

Minimum Area It is an economic fact of life that the product cost of an RFIC chip is directly proportional to its area. Therefore, there are strong forces pushing the designer to minimize the ultimate layout area of any given design. This is not all bad from an electrical-performance viewpoint because minimizing chip area often minimizes the performance-robbing parasitic elements, such as interconnecting metal lines and capacitor bottom plates. There is no hard-and-fast rule to determine the optimum area for a given RFIC requirement. There are so many factors influencing this decision that it is more of an art than a science to arrive at a final value. In the end, the successful design addresses a number of trade-offs and balances all of the important determining factors to come up with the simplest possible design that will meet all requirements. Let us now consider some of the factors that must be considered in coming up with a successful design layout.

14.2

“On-Chip” versus “Off-Chip” Component Decisions The designer must constantly wrestle with the decision making relative to placing a component on-chip or relying on the chip’s ultimate customer to place a key component “off-chip” on the circuit board and make connections to the packaged chip through circuit board traces. The on-chip-versus-off-chip question is never an easy one to address, but it is very necessary. Here are some general guidelines that may help in making these difficult decisions: 1. Capacitors: Capacitors should be placed off-chip when their values make them physically too large if placed on-chip. The question to be answered here is, how large is too large? The best way of approaching this question is to recognize that semiconductor chips are not a good economic way to manufacture capacitors. If the capacitor in question is large enough to occupy a substantial fraction of the chip’s area, it is best moved off-chip, where tiny surface-mount capacitors are readily available to extremely high values of capacitance. On rule of thumb is never to let the total on-chip capacitance occupy more that half the chip’s total area. If the “half” rule is approached, it may be a signal to the designer to consider moving the largest capacitors off-chip. 2. Inductors: Inductors are always realized on-chip as spiral inductors. Off-chip inductors will be in the form of surface-mounted devices, which 283

284

Layout Design Strategies

have considerably lower loss than on-chip spiral inductors and can handle much higher currents without compromising reliability. Spiral inductors, like MIM capacitors, can be major chip-area drivers. Therefore, the main motives for moving inductors off-chip are to reduce losses, increase current limits, and save chip area. All of these reasons are good and need to be considered seriously. There is some interaction between the reasons; for instance, an on-chip spiral inductor that is required to carry high dc current must have a trace wide enough to carry this level of dc current safely (see Chapter 4) without compromising reliability. Therefore, the requirements for high current will inflate the area of a spiral inductor, providing two reasons to consider moving this device off-chip. In terms of area, the designer should consider, as in the case of the capacitor, moving one or more of the spiral inductors off-chip if the total area occupied by all spiral inductors becomes greater than 50 percent of the total chip area. Again, it is a case of recognizing that semiconductors are not the most economically efficient way of manufacturing inductors. However, in the case of inductors, it may be necessary to place certain key inductors off-chip simply because these devices may be located in a critical area of the chip’s circuit requiring extremely low loss (as in the front-end matching elements of an LNA). Another reason to locate an inductor off-chip is to take advantage of an off-chip inductor’s ability to carry large currents without the need to resort to extremely wide metal traces if the inductor is realized on-chip. One might also use off-chip inductors as very high-Q inductors that may only be available as off-chip devices. Such high-Q inductors can be frequency-determining components in VCOs, for example. On-chip spiral inductors, which are naturally low Q, may not be capable of achieving the level of Q needed in certain low-phase-noise VCO applications. 3. Resistors: Most resistors can be realized on-chip, but there are some exceptions. For instance, high-precision resistors are often hard to realize on-chip. Also, high-value resistors can be hard to realize on-chip, even using so-called interdigitated techniques. This is particularly true with a foundry process that has only a 50 ohms-per-square available TFR resistor option. 4. Specialized components: Certain components are not easily realized on-chip or simply may not exist in an on-chip format. This category includes, but is not limited to, transformers, baluns, Lange couplers, high-Q filters, varactor diodes, PIN diodes, and transistors from other technologies. While the best rule to follow is to avoid components like these in your designs, it is sometimes impossible not to use such components because of the nature of a given requirement. Therefore, these specialized off-chip components must be always be treated on a case-by-case basis.

14.3

Minimizing Parasitics Minimizing parasitic elements is always a good idea in any design. However, sometimes these parasitic elements can be used to advantage as circuit matching elements. Since they are often unavoidable, it is a very good plan to include them in your cir-

14.4 Testability

285

cuit schematic in a way that will do some good. This is not always possible, but the designer needs to be aware of the potential and take advantage of any and all opportunities to put unavoidable parasitic elements to good use. An example of putting a parasitic element to good use is in the design of Darlington amplifiers, where the metal line connecting the emitter of the first transistor to the base of the second transistor can be used to peak up the amplifier’s high-frequency gain. This connection has to be made anyway, so why not put it to good use. Unfortunately, many, and perhaps most, parasitic elements will only degrade performance and should be minimized or, better still, avoided all together. There is no by-the-numbers technique to make this happen. Probably the best step to take in this direction is to use the simplest possible circuit schematic and the simplest possible layout. Complications in the schematic will only lead to additional interconnections, which inevitably bring with them additional parasitic elements. The art of a successful design often means maintaining simplicity in both circuit design and layout. In terms of layout, try initially to place all major components in positions where the signal paths flow naturally from one device to another with a minimum of interconnecting metal. In most designs, it is good practice to place all of the input pads on one side of the chip (conventionally, this is the left side) and all of the outputs on the other (right) side of the chip. In a large, multifunction chip, this may not always be possible, but if it is possible, this convention is very helpful in maintaining the signal flow paths of minimum length, thereby minimizing parasitic effects. In general, a meandering back and fourth of the signal flow path is to be avoided in layouts. Such back-and-fourth signal flows are certain to add to the parasitic content of the circuit and degrade overall performance. It pays big dividends for the designer to consider carefully the signal flow paths from device to device within the chip and to plan accordingly for the placement of each device in such a way that the overall signal path flow is as natural and direct as possible.

14.4

Testability Testability is of paramount importance with RFIC chips because there is no easy way to modify them once they are fabricated, making diagnostics of any problems difficult. Testability is accomplished in two ways. The first consideration is to be sure that bonding pads pair of a standard size and spacing are provided at all RF inputs and outputs. These pad pairs, as discussed in Chapter 4, are useful when using a measurement device called an on-wafer probe station to test RFIC designs before they have been packaged—in fact, before the die are separated from the wafer. On-wafer probe equipment has tiny contacts that have been designed to provide a very accurate 50 ohm impedance test point at the probe ends. In this way, any measurement device, such as a network or spectrum analyzer, may be connected directly to the RFIC chip’s input and output terminals while the chip is still part of an overall wafer. This type of testing is very useful and time saving in the prototype stage of development because it allows the designer to obtain performance data as soon as wafer fabrication has been completed without having to wait for the individual die to be separated from the wafer, packaged, and electrically evaluated on a test board.

286

Layout Design Strategies

A second valuable technique for testability is to make use of test cells. Test cells are critical portions of the overall circuit that have been cut out of the layout and placed, together with sets of on-wafer probe test pads, in separate layouts. The test cell is used to trouble-shoot a design that does not function as expected. Since the fabricated chip cannot be cut up for testing purposes, it may be impossible to test certain internal functions within the chip. If the RFIC has performance problems thought to be linked to one of these internal functions, it will be very difficult to evaluate the problem if you only have the input and output pads of the entire chip to test. However, by placing one or more of these critical circuits in a “test cell,” they can be evaluated piecemeal using the same on-wafer probing techniques as are used to test the design as a whole. At a minimum, all sizes of transistors that appear in the design should be included in their test cells. Test cells, of course, occupy wafer area that could be used for the complete RFIC or second versions of the complete RFIC. For this reason, it is not desirable to “go wild” and place every little subcircuit in its own test cell. Again, like most design choices made in the RFIC world, it is very important to choose wisely which and how many subcircuits will appear in test cells. Probably the best rule of thumb is to make choices based on which circuits you think are most likely to cause problems. This is the same as saying, be aware during the initial design process which subcircuits have the most difficulty in achieving their goals. It is these critical subcircuits that should be placed in test cells for evaluation on a stand-alone basis. While you must always bet on success, it is wise to make special arrangement to test separately those subcircuits or devices that you suspect may cause problems for the performance of the overall design.

14.5

Types of CAD Systems RFIC circuits have become so massive that it is impossible to consider doing an RFIC layout without using CAD software tools. Many fine tool packages available in the industry allow the designer to make use of a wide variety of editorial features that simplify the layout process. However, all CAD layout tools share the ability to output the final layout in a stream file language called Graphic Data System II Stream Format (GDSII). Since GDSII represents a common language among CAD layout tools, it makes it possible to develop a layout with one tool set and then transfer the layout easily via GDSII to a different tool set. This is of critical importance if you are constructing a layout on one tool set, and the foundry is using a different tool set to perform DRC checks and to make masks. Before purchasing a set of CAD tools, be sure to check with the foundry to insure file compatibility. You may want to send test files generated on the CAD tools that you are considering purchasing and asking the foundry to verify that they can read these files. The price of CAD layout tools varies widely depending on the supplier. Some CAD layout tools come bundled with simulation software, while some do not. Some simulators come bundled with a layout tool. You may or may not want to use the bundled tool combination. The advantage is instant compatibility between the schematic diagrams in the simulator and the layout elements showing up on the layout tools screen. This feature can be of great help when you are making editorial

14.6 Foundry Comparison

287

changes because it automatically updates the schematic if you make a layout change and may update the layout if you make a schematic change. Some tool packages do not have the capability to make updates in both directions (i.e., changes to the layout may be reflected in the schematic, but changes to the schematic may not be reflected in the layout). Your foundry may supply you with “applicas” for certain structures like transistors and inductors. These applicas should always be used instead of creating the device from scratch because in some cases, like transistors, many levels are involved in the process of creating the layout, and the applicas can save you a lot of work and uncertainty in getting the layout right. Some foundries also offer design IP for sale. Such IP contains certain subcircuits that may be very difficult and/ or time-consuming to design. By purchasing the foundry’s IP for, say, a phaselocked loop, the designer is in effect trading money for the time necessary to do the design him- or herself. A second advantage of using an IP subcircuit is the assurance that the foundry has completely evaluated this subcircuit design, and you can depend on its working correctly. The foundry will usually supply you with test data taken during verification. Some examples of the leading CAD layout-tool suppliers include Cadence, Inc., Mentor Graphics, and IC Editors. All of these tool sets have proven track records in the industry and can be counted on to do an excellent job for the designer. As a designer, you may want to do your own layouts, or you may want to outsource the layout work (or, in a large company, you may make use of the services of a central layout group that serves design engineers in many parts of the company). The advantage to doing the layout yourself is the detailed knowledge that you have concerning layout routing decisions and basic floor planning. However, layout is a time-consuming process, and many designers prefer to work with a well-known and trusted layout specialist. As the designer, you may need to spend considerable time with the layout specialist to insure that the layout proceeds according to your own vision. However, once the major decisions have been made and the process becomes more or less mechanical, you, the designer, are freed up to return to what you do best, which is circuit design. Layout specialists do layout every day of their working week, so they become very good at what they do. In most cases, the layout specialist can complete a layout in less time than a designer, who does not have the daily experience with the tools to gain the same level of expertise that the specialists has. Both techniques can be made to work quite well, and the choice may, in the end, depend on practical considerations like budgets and the availability of company resources.

14.6

Foundry Comparison There are a number of excellent foundries for both InGaP/GaAs HBT and SiGe processes in the United States, Europe, and Asia. At present, the most widely used GaAs HBT foundries are located in Asia. The Asian foundries offer larger wafer sizes and lower wafer-fabrication costs than those found elsewhere, adding to their popularity. Some examples of these foundries are Win Semiconductor Corporation in Taiwan and Knowledge On, Inc., in Korea. In the United States, Triquint Semiconductor, Inc., and GCS Corporation offer GaAs HBT foundry services. At present

288

Layout Design Strategies

most of the leading SiGe foundries are in the United States. The chief examples are IBM and Jazz Semiconductors, Inc. Because SiGe is usually part of a BiCMOS process, it is always offered by a company that already has CMOS foundry capability. In Asia, TMSC offers a SiGe BiCMOS process. When shopping for a foundry, the designer should, if possible, visit the foundry and talk personally to the foundry’s engineers. In a relationship with any foundry, it is very important to know whom to contact for technical help. All foundries have an excellent staff of modeling engineers and designers, like yourself. It is very important to get to know these people so they can help you when problems arise. Also, take the time to get to know the foundry’s CAD operators, these are the people who will be processing your designs. If problems arise with either DRC errors or last minute corrections or additions, these are the people you will be working with. When getting to know a foundry, ask about the details of their electrical models. These models include both transistors and passive devices, like thin film resistors, MIM capacitors, and spiral inductors. Be sure to check the model verification data to assure yourself that the foundry’s models are accurate, especially at high frequencies. Also, become familiar with the foundry’s reliability data. Ask questions about how they arrived at the data. What experiments and life tests have they performed, and are any of these tests ongoing? If they are ongoing, ask for updates of results as they become available. Become familiar with the maximum current conditions in each class of components based on reliability considerations. Often trade-offs will develop in the course of a design between performance and reliability. You need to understand completely the implications of these trade-offs so that you can make informed choices. Many foundries will have alternative ways of forming resistors, capacitors, and inductors. While there is no fixed rule about which type of resistor, capacitor, or inductor you may choose, the decision may become clearer to you once you have investigated the background and implications of each option. For example, an implant resistor may offer higher resistance than will a thin film resistor for a given size, but its precision may not be as good as the thin film resistor’s. The choice in this case may be determined by considering whether you need high resistance in a small size or if you need high precision in a larger size. Another sometimes difficult choice comes about in sizing transistors. The area of a transistor may be increased either by adding emitter fingers and placing all unit cells in parallel or by increasing the length of the emitter finger in a unit cell, using fewer unit cells to achieve a given transistor area. This is not an easy choice, and it may depend on various modeling considerations. For instance, many foundries only provide large-signal models for particular unit cell emitter lengths. In this case, the decision is an easy one: you stay with the emitter length supported by a foundry model. However, if the foundry’s models support many choices of emitter-finger length, the only way to make an informed decision is to experiment in your simulations with transistors of the same total size but with different emitter-finger lengths. This process becomes one of understanding how the transistor’s parasitic elements are affected by its unit cell’s aspect ratio. At low frequencies, it may not matter what aspect ratio you choose, but as the frequency increases, you may find that the shorter emitter fingers are more favorable.

14.7 Reticle Assembly

14.7

289

Reticle Assembly The first step in photo mask making is the assembly of a “reticle” which contains all RFIC and test cell layouts. Many foundries will take care of assembling your reticle, but some require the designer to perform this task. It is a straightforward procedure, but a number of basic considerations must be adhered to. To start the process, consider the completed reticle shown in Figure 14.1. This pattern will be step and repeated across the entire wafer during fabrication. In order to assemble all circuit and test cell designs together into a common reticle, some base rules must be observed: 1. Add (1/2) street borders around all design layouts. Be sure that the emitter fingers of all transistors are oriented in the same direction. The foundry device models assume a particular crystalogical direction for the device’s emitter fingers, and the model only works for this direction. Therefore, all transistors must, in the end, be oriented in the same direction relative to some fixed angular reference (often a “flat” on one side of the wafer). See Figure 14.2. 2. Assemble the reticle by joining all of the (1/2) streets for each circuit design and test cell. There can be absolutely no gaps between the (1/2) streets of any designs. When the circuits are brought together, they form a common street

Figure 14.1

The layout of a completed reticle.

290

Layout Design Strategies

Figure 14.2

An example of a simple feedback amplifier die layout surrounded by (1/2) streets.

between them of standard width simply by combining the (1/2) streets associated with each circuit, as shown in Figure 14.3. 3. All designs must share a common dimension and, perhaps, have only two or three options for the second dimension. If the common dimension is arranged in the horizontal direction, then all columns will have the same width, but there may be more than one row width. In my experience, it is far easier to place all designs within a (1/2) street border with common dimensions. This simplification will waste a little wafer area, but it will greatly simplify the reticle assembly process. 4. Arrange all circuits into a common array of rows and columns with streets running between each circuit design, forming the reticle, as shown in Figure 14.3. The foundry will give you a specification about the overall size of the reticle. In some cases, the overall reticle size is fixed; at other foundries, it is expressed as an upper-bound maximum. In either case, it is usually best to use the maximum reticle size. Of course, this will force the designer to make decisions about the mix of designs that populate the reticle. You may decide to put ten layouts of design A on a reticle but only five layouts of design B. This choice reflects your desires relative to how many die of a given design you wish to receive after wafer fabrication. In most cases, you only need to receive a very limited number of tests cells; however, circuit designs that you may wish to sample customers with may need to be available in higher quantity. 5. The foundry will require that in your reticle you either locate, or make space available within the reticle to locate a foundry layout pattern called a process control monitor (PCM). The easiest way to do this is simply to

14.7 Reticle Assembly

291

Figure 14.3 An array of prototype die layouts arranged in rows and columns separated by streets that are formed as the individual die layout (1/2) streets are merged together.

Figure 14.4 The foundry’s PCM pattern layout must be located at a position (or positions) within the array of die layouts that make up the reticle. The foundry specifies the PCM position (or positions).

remove one or more of your design layouts and to insert the PCM there. Some foundries will have specific locations for their PCMs, which you must

292

Layout Design Strategies

adhere to. Some may even require more than one PCM in your reticle. A reticle containing a PCM is shown in Figure 14.4. After wafer fabrication, assuming the wafer is acceptable to the foundry, you will receive a complete set of PCM data, sometimes with a map of how the data is distributed across the wafer. This is very handy data to have and should be examined carefully for signs of device performance gradients across the wafer. Fortunately, bipolar device technology is very uniform, and such gradients (which are often experienced with field-effect transistor technologies) are rare with bipolar processes.

CHAPTER 15

RFIC Economics 15.1

Levels of Integration The optimal level of integration for a given RFIC can often be a hotly debated topic. Many considerations must be researched in order to make a truly informed decision. Integrating a chip to very high levels has two important benefits and several potential disadvantages. The benefits are smallest possible size and lowest possible cost, which are truly huge benefits. The disadvantages are possible yield problems (it only takes one defect in a very large chip to render it useless), the inability to use different technologies in areas where their strengths lie, and the enormous task of assembling so many circuits on a common die. Another potential problem is made especially serious when a large integrated chip enters the test, verification, and troubleshooting phase. It is impractical to bring all critical test points out of the chip to enable complete testing of all circuits. Therefore, the designer who troubleshoots such a large circuit has to rely on a combination of simulations, theories, and hypotheses to make progress in identifying causes and solutions for problems. In general, the degree of difficulty in troubleshooting is a very steeply increasing function of the total die area. This is not to say that you should not attempt a large, highly integrated design because this is how true progress is made in the RFIC field, but you must be realistic and budget enough time for evaluations and redesign. It is not uncommon with a large, highly integrated design to go through as many as four or five design-fabrication cycles (spins). The cost of such a design exercise can be staggering, and the time to market can become a problem if the competition is making good progress. The alternative is to split the overall system design into several smaller pieces. Several advantages can be achieved by partitioning the system in this way. The first advantage is in keeping each die at a manageable size. The second is the ability to use multiple technologies to advantage (i.e., the LNA could be in PHEMT, the PA could be in GaAs HBT, and so forth). By partitioning the system, the best possible performance can be achieved simply by making use of the performance advantages of two or more different technologies. This is clearly a case of trading performance (highest with less integration) for low production cost (with higher integration). But perhaps the most important feature of lower integration with a partitioned system is the ability to test and troubleshoot more easily. Since the individual die have fewer circuit functions each, the test-and-evaluation phase of the project is significantly simplified. Divide and conquer is at work here. Another important outcome will be fewer spins to success because a more complete evaluation can be accomplished at each spin. This translates into shorter time to market.

293

294

RFIC Economics

To sum up, the partitioned RFIC system will have better performance, take less time (and less money) to develop, and get to market more quickly than the equivalent fully integrated chip system. However, the price paid for these advantages is higher production cost and larger area (because the customer will have to set aside more board area for this design). Another cost driver with the partitioned approach is the added cost of multiple packages. No longer is it a neat situation of one die in one package. The partitioned approach produces multiple die in multiple packages. This is called a chip set, and it is always more costly to use a chip set than a single-chip solution. Some manufacturers take the middle road by designing and prototyping a partitioned system. The resulting chip set is used to estimate market size and acceptability. Only when the market potential is deemed large enough to warrant the development cost of a fully integrated solution will a company take on its development. Of course, the danger of this approach is that if a competitor company has “leapfrogged” straight to a fully integrated solution they may be in a position to take away most of the business before the company which is taking the more cautious, two-phase approach can complete the development of a fully integrated chip and enter the market place with this solution.

15.2

Single-Ended versus Differential Topologies A growing trend among RFIC designers is to use more and more differential circuits within their designs. This trend is driven by a number of considerations. Probably the most important reason for this trend is the widespread use of Gilbert cell mixers, which are naturally differential at all three ports. Most wireless systems today make widespread use of Gilbert cell mixers both for receiving downconverters and transmitting modulators. Because of the heavy reliance on phase modulation in most, if not all, wireless applications, these mixers and modulators are usually arranged into quadrature-phase I/Q mixers and modulators designed for the detection and generation of phase-sensitive modulations. This trend requires that two Gilbert cell mixer be associated with each system function, multiplying by two the number of Gilbert cell mixers required by a typical system. This enlarged population of Gilbert cell mixers means that there are a lot of differential inputs and outputs within a typical system. Rather than facing the difficult task of converting all of these inputs and outputs to single-ended format (being on-chip does not make this task any easier), it is generally easier simply to design all on-chip components in differential form. This approach is not really all that difficult, and since transistors are essentially free in integrated circuits, there is little cost penalty to this approach. Of course, the designer has to be careful not to let the overall area become significantly inflated by the presence of all these differential circuits, but this is not generally a serious problem. One way to answer the single-ended-versus-differential question is to simply consider the size of the design and the overall count of Gilbert cell mixers. If the chip is very small and has no mixers (for example, a simple Darlington amplifier), it will be best to design it in single-ended form. However, if the design is large enough to contain several mixers, then it is best to use all differential circuits and make all inputs and outputs differential also. The customer is free to convert these inputs and

15.3 Process Technology Choices

295

outputs from differential to single-ended form by using off-chip commercial baluns placed right next to the chip on the system’s circuit board.

15.3

Process Technology Choices Not too many years ago, there were only two fabrication technologies available to the RF/microwave circuit designer. The first was standard silicon bipolar transistor technology, which was only good for frequencies up to about 1 GHz. The second was GaAs MESFET technology, which held the promise of operation up to 10 GHz. That situation has changed over the past few years. Today, there are as many as five major technologies (GaAs HBT, GaAs MESFET, GaAs PHEMT, RFCMOS, and SiGe) with at least four more technologies waiting in the wings for industry acceptance. As you might expect, no one technology offers the lowest cost and highest performance in all applications. This makes the job of choosing a technology that much more difficult. There is always the performance-versus-cost issue, but even that choice is further complicated by the question of whether we are talking about prototyping costs or production costs. Let us first look at performance considerations. On a purely performance basis, the best technology for an LNA is GaAs PHEMT. Also, GaAs PHEMT makes really excellent switches which are only exceeded in performance by PIN diode switches. In terms of power amplifiers, GaAs HBT makes really excellent, highly linear power amplifiers. Because of their low threshold voltages (Vt for RFCMOS and Vbe for SiGe), both RFCMOS and SiGe are excellent technologies for designing Gilbert cell mixers and modulators for applications requiring low dc voltages. In terms of passive components, like spiral inductors and MIM capacitors, the semi-insulating GaAs substrate used for GaAs HBT is unbeatable. All silicon-based technologies have a conductive substrate that potentially holds loss mechanisms that reduce performance. VCOs are best designed with a bipolar technology in order to keep the 1/f contributions to their phase noise to a minimum. All field-effect transistor technologies (MESFET, PHEMT, RFCMOS) have serious 1/f noise problems and are best avoided in favor of bipolar technologies in applications requiring extremely low-phase-noise VCOs. If it is imperative that only one technology be used for your designs, then you must learn to live with its weaknesses. A single-technology design will always have performance compromises. This is a given even before the design process begins. The main reason for pursuing a single-technology design is cost, either prototype cost, or more likely production cost. Cost is a very serious matter and cannot be taken lightly. However, the designer needs to recognize from the outset that using a single-technology design is an exercise in trading off performance for cost. If this is deemed to be a good trade-off in a business sense, based on market research, then taking this path makes good sense. But if there is any expectation that the final design must have maximum achievable performance and simultaneously lowest possible cost, then red lights should go on. The first law of good engineering practice states that you can’t get something for nothing. You can play the trade-offs to your own advantage, but you can never have it both ways. Engineering is the art and

296

RFIC Economics

science of crafting favorable trade-offs. It is very much like drawing up and consummating a good business deal with nature. You can never have it all, but with skill and cleverness, at the end of the day you can achieve those objectives that are most important by giving up those objectives that are less important.

15.4

Area versus Performance Trade-offs A very important trade-off in RFIC design is between chip area and performance. This seems like a very straightforward trade-off, but a lot of subtle factors affect the decision that needs to be made. If you implode the chip to an extreme degree to save area, all of the metal lines, transistors, resistors, capacitors, and inductors will be touching each other. Of course, at this point the chip is nonfunctional because of electrical short circuits. However, there is a broad middle ground in which the hard decisions need to be made. Let me say at the beginning that chip area and chip cost are essentially the same thing. This is because there is a fixed fabrication cost per wafer, which translates into a cost per die that is inversely proportional to its area (the number of die available on a given wafer equals the area of the wafer divided by the area per die). The bottom line is that from a cost point of view, there is heavy motivation to keep the die area to an absolute minimum. As I have already pointed out, if we “crunch” the chip’s area down to some absolute minimum, at some point in the crunch process the chip could become nonfunctional. So, the practical question to be answered is how much can the chip’s area be reduced before the impact on performance becomes unacceptable. This question assumes either that you have a perfect simulator that can give you an accurate assessment of performance for each area reduction or that you have unlimited time and resources to test hardware performance at each step in the area-reduction process. For most designers, neither possibility exists. Therefore, chip-area reductions become largely an exercise in risk management. Every proposed change in the design’s layout will have some impact on the design’s performance (usually performance will degrade if the change is associated with an area reduction, but not always). Each change is a special case unto itself. For instance, if he or she wishes to change the aspect ratio of a large capacitor to allow the occupation of some unused space, the designer must ask how the capacitor’s model is changed by the change in aspect ratio. At low frequencies, the answer, most likely, is not much, but at higher frequencies, the simple answer may no longer hold true. Modified current paths will always have parasitic elements associated with them that can play significant performance roles, especially at high frequencies. Another factor to consider is how much more strongly a device couples to its neighbors as they are packed closer and closer together. Cross talk between components can become a leading source of performance degradation as die area is reduced. This situation is equivalent to the noise problems experienced by residents of an apartment complex who are required to live closer and closer to their nearest neighbors. Component-to-component interaction and cross talk can be a major driver in determining the performance-versus-area trade-off. A second important area affecting performance as the chip’s area is reduced is the length of metal interconnecting lines. Initially, you would expect that a smaller chip would have shorter interconnecting lines. In many cases, this may be true, and

15.5 Electrical Yield

297

it is even possible that performance enhancements may result from this process initially. However, as the components get closer and closer together, it becomes increasingly difficult to route the metal lines in such a way that overlaps are avoided. When overlaps occur, there is always a coupling capacitance between the overlapping lines (assuming they are different metal layers), leading to complicated interactions and cross talk. Another difficulty is with metal lines that need to be a specific length. For instance, in a Gilbert cell mixer, in order to maintain peak performance, it is very important that the interconnecting metal on both sides of the mixer have identical lengths. However, this may no longer be possible if the area available for the mixer and its connections to surrounding components is significantly reduced. There will come a point where area reductions will make it very difficult to maintain the kind of metal-line-length symmetry that allows balanced component designs, like Gilbert cell mixers, to perform to their peak potential.

15.5

Electrical Yield In most cases, a given die’s electrical yield is determined by the severity of its specifications. A relatively easy set of specifications usually implies a high electrical yield, whereas a very difficult set of specifications may lead to a lowered electrical yield. This is simply a case of minor process variations’ having an effect when the specifications are inherently difficult to achieve, whereas when the specifications are relatively easy to achieve, minor process variations have very little impact on electrical yield. Bipolar processes are usually very stable from wafer to wafer. This is because the important parameters for determining electrical performance have already been built into the wafer during the process of epitaxial growth. In many cases, bipolar RFICs are tested only for dc conditions and not for RF performance due to the high degree of confidence in such a process’s repeatability. If the decision is made to perform RF electrical tests on each device, it is often best to delay the testing until the devices have been packaged in order to make use of automated test systems, such as computer-controlled network analyzers and chip handlers. The question is always, how much testing is enough? Perhaps only few key electrical parameters are necessary to perform a meaningful test. Perhaps one or two critical electrical specifications need to be 100 percent tested, but nothing else. Much good judgment must be exercised in making these decisions. If the die is a semicustom part targeted for only one customer, the manufacturing engineers at both companies must get together and agree on a set of tests that are both meaningful and cost-effective. The key in such cases is to identify those specifications that are truly critical and, for testing purposes, to disregard the rest. It is very important economically that once a part reaches production, its yield in manufacturing be quite high. It is poor practice to move a product into the production with a low yield in final electrical testing. Such a situation would mean that a lot of parts are thrown away, which is never a good thing. If you find yourself in a situation such as this, it becomes important to work with the designers in order to modify the design such that the electrical yield can be improved to at least 70 to 80 percent. In a large-scale manufacturing situation, it is worth investing considerable

298

RFIC Economics

engineering resources to improve the chip’s design to the point that electrical yield is acceptable. It is in no one’s best interest to continue running parts that will only be largely thrown away at the end of the line.

15.6

Prototype Costs When working with a foundry, it is very important to understand what costs you are facing in the near term and, ultimately, in larger-scale production. During the prototyping phase, foundries may charge their customers for a variety of services. The list of prototyping services varies from foundry to foundry, but the following is a partial list based on experience with a number of InGaP/GaAs HBT foundries: 1. Design rules: Foundries often charge $3,000 to $5,000 for a set of their latest design rules. 2. Training: The foundry may offer a course in how to design with their particular set of design rules and models. Such a course may last one day to one week at a cost of $10,000 to $30,000. 3. DRC (design rules check): Most foundries offer a DRC check of your design as part of the overall prototyping service. Even if you have your own ability to perform DRC, it is well worth making use of the foundry’s DRC service for the piece of mind of knowing that the foundry agrees that your design is manufacturable. 4. Mask making: It will cost $15,000 to $20,000 for a mask set of upwards of fifteen layers. This number can be greatly reduced for prototyping by using a so-called pizza mask, in which case you will share the cost of masking with several other organizations, whose parts will also be fabricated on the common wafer that you all share. The cost of a pizza mask and prototype fabrication is about $5,000 to $15,000 for a 5 × 5 mm slice of the material holding your prototypes.

15.7

Production Costs Production costs are mainly determined by the cost of fabricating a wafer and how many of your die it will yield. If you are forced to make a new production mask, this could mean an additional $20,000, or perhaps more. Other than that, it is purely a matter of determining how many of your die will be yielded by the wafer. As an example, we consider determining the cost of a 1,100 microns × 900 microns die. The major cost items involving RFICs are 1. 2. 3. 4. 5. 6.

Die size Wafer fabrication cost Cost per die = (die area/total wafer area) times the fabrication cost per wafer Yield by 80 percent for material lost in the saw streets Yield by 80 percent for electrical yield Added package cost (about $0.10 for a simple SOT-89 plastic package)

15.7 Production Costs

7. Added cost of electrical testing (about $0.20 for a simple die) Therefore the cumulative cost of manufacturing this die is: 1. 2. 3. 4. 5. 6.

Wafer fabrication cost per wafer is $3,000. Cost per die = $3,000 (1,100 × 900/7,853,981,635) = $0.37. Yield for streets = $0.47. Electrical yield = $0.59. Package cost (assume plastic) = $0.69. Electrical testing = $0.89.

299

Acronyms A ACPR ADC ADS AM AMPS BER BiCMOS BJT BPF BPSK BWO CAD CDMA CM CMOS DRC DSB DSP DSSS DTO EDA EVM FCC FET FM FOM GaAs GDSII Ge GFSK GPS GSM HBT HF HPF

attenuation adjacent channel power ratio analog digital converter Advanced Design System amplitude modulation Advanced Mobile Phone Service bit-error rate bipolar/complementary metal oxide semiconductor bipolar junction transistor band-pass filter binary phase-shift keying backward wave oscillator computer-assisted design code domain multiple access collector contact metal complementary metal oxide semiconductor design rule correction double side band digital signal processing direct sequence spread spectrum dielectrically tuned oscillator electronic design automation error vector magnitude Federal Communications Commission field effect transistor frequency modulation figure of merit gallium arsenide Graphic Data System II Stream Format germanium Gaussian frequency shift keying Global Positioning Services Global System for Mobile Communications heterojunction bipolar transistor hydrofluoric acid high-pass filter

301

302

Acronyms

I IC IEEE IF IIP3 InP IP IS-95 ISM LC LDMOS LMR LNA LO LPF LSB M1 M2 MAG MBE MCLIN MESFET MIM MLIN MMDS MMIC MOCVD MOS MOSCAP MRIND MSUB N NADC NF NPN NV OFDM OIP3 OIP5 OQPSK PA PAE PCB PCM PCMCIA PCS PDA

in phase integrated circuit Institute of Electrical and Electronics Engineers intermediate frequency input intermodulation intercept point indium phosphide intellectual property CDMA standard industrial scientific medical inductor capacitor lateral diffused metal oxide semiconductor land mobile radio low-noise amplifier local oscillator low-pass filter lower side band first metal second metal maximum available gain molecular beam epitaxy ADS schematic element metal-semiconductor field-effect transistor metal insulator metal ADS schematic element Multipoint Microwave Distribution System microwave monolithic integrated circuit metal oxide vapor deposition metal oxide semiconductor metal oxide semiconductor capacitor ADS schematic element ADS schematic element N–quadrature amplitude modulation) North American Digital Cellular noise figure n-type, p-type, n-type bipolar transistor nitride via orthogonal frequency division multiplexing third-order intermodulation intercept point fifth order intermodulation intercept point off set qudrature phase shift keying power amplifier power-added efficiency printed circuit board process control monitor standard plug-in module for lap top computers personal communication service personal digital assistant

303

PDK PHEMT PIN PV Q QAM QPSK RC RF RFCMOS

process design kit pseudomorphic high electron mobility transistor p-type, insulator, n-type diode polyimide via quadrature phase quadrature amplitude modulation quadrature phase-shift keying resistor times capacitance time constant radio frequency radio frequency complementary metal oxide semiconductor technology RFIC radio frequency integrated circuit RL resistor times inductor RMS root mean square S/N signal-to-noise Si silicon SiGe silicon germanium SMT surface mount technology SNR signal-to-noise ratio SP2T single pole two throw switch SPG Gummel Poon spice models SPV scratch protection via SSB single side band SV substrate via T/R transmit/receiver switch TCC temperature coefficient of capacitance TCR temperature coefficient of resistance TDMA time domain multiple access TFR thin film resistor TSMC Taiwan Semiconductor Manufacturing Co. TWT traveling-wave tube UHV/CVD ultrahigh vacuum chemical vapor deposition USB upper side band UWB ultrawideband VBIC Vertical Bipolar Industrial Committee bipolar transistor model VCO voltage-controlled oscillator VGA variable gain amplifier VSWR voltage standing wave ratio WLAN wireless local-area network WUSB wireless USB YIG yittrium iron garnet YTO YIG-tuned oscillator

About the Author Allen Sweet has been a consultant in the field of RF and microwave circuit design for nearly 30 years. His clients range worldwide, and include many of the leading corporations engaged the design of RF and Microwave devices, circuits and systems. His first book, on designing MIC and MMIC Amplifiers and Oscillators, was published by Artech House, Boston MA, in 1990. He holds a Ph.D. degree in Electrical Engineering (with minors in Physics and Applied Physics) from Cornell University, and has published widely in the field of RF/Microwave circuits (more than 30 published journal articles and conference papers). In 1977 he was a co-receiver of the IEEE MTT Microwave prize for his work on phase locked power amplifiers for FM/FDM telecommunications applications. In 1992 he served as the technical program chairman for a first ever conference (held in Santa Clara California) devoted to exploring newly emerging commercial applications of RF and Microwave technology. Since 2002 he has been an adjunct professor of Electrical Engineering at Santa Clara University in Santa Clara California; where he teaches graduate classes in Radio Frequency Integrated Circuit design, and undergraduate classes in electrical circuits. He is a member of the IEEE. His current research interests are low phase noise VCOs, mixers, and low noise and power amplifiers. His hobbies are amateur radio, reading, music, and travel.

305

Index 1/f noise. See Flicker noise

A Abrupt-junction varactor diodes, 243–48 capacitance and resistance relationships, 244 capacitance change, 245 doping profile, 244–45 frequency-tuning ratio, 246 at low reverse voltage, 244 See also Varactor diodes Active device sizing, 177–81 Active mixers, 200–217 defined, 200 fully balanced multiplying, 205–7 single-balanced multiplying, 200–205 topologies, 200 See also Mixers Adjacent channel power ratio (ACPR), 15 defined, 145 power amplifiers, 145–46 specifications, 145, 146 two-stage differential PCS power amplifier, 188, 189 Advanced Mobile Phone Service (AMPS), 14 Amplifier design, 105–13 cascode amplifiers, 111–13 differential amplifiers, 109–11 Fano’s limit, 106–7 gain compensation, 106 matching techniques, 105–6 stability, 107–9 See also Low-noise amplifiers (LNAs); Multistage amplifiers; Power amplifiers Amplitude modulation (AM) noise, 263 Analog digital converters (ADCs), 21 AppCAD, 174–75, 226 Applicas, 287 Applications, 10, 13–24 Bluetooth, 17–18

cellular/PCS handsets, 13–15 cellular/PCS infrastructure, 15–16 cognitive radio, 20–21 digital TV and set-top boxes, 20 physical layer standards, 22–24 spectrum allocation, 21–22 UWB, 18–19 WiMax, 19–20 WLANs, 16–17 AutoCAD, 70 Avalanche breakdown, 45 Avalanche multiplication, 78

B Back-to-back transformers, 97 Backward wave oscillators (BWOs), 1 Ballasting, 166, 167 Baluns, 102–4 Band-pass filters (BPFs), 93–95 construction methods, 93–94 lumped-element, 94–95 S-parameters, 96 two-section, 96 Base after gate (BAG), 76 Base-biasing network, 152, 154 Bias circuits power amplifiers, 150–54 for stabilizing bipolar amplifier at high frequencies, 151 for stabilizing bipolar amplifier at low frequencies, 151 BiCMOS, 5, 9 fabrication, 71 SiGe process, 83 Binary phase-shift keying (BPSK) modulation, 26–27 analog multiplying mixer, 27 constellation diagram, 26 idealized generator, 26 phase noise, 27 signal generation, 27

307

308

Bipolar process stability, 297 Bit-error rate (BER), 10, 25 BJT devices, 71 RF, 71 Si, 71, 72 Blocking capacitors, 152 Bluetooth, 17–18, 23 Boltzmann’s constant, 119 Bonding pads, 60–61 cross section, 61 input/output pattern, 61 layout, 60 mechanical strength, 60 in on-wafer testing, 61 Buffer amplifiers, 41, 219 Bypass capacitors, 152

C Cadence Spectra RF simulation tool, 80 Cadence tool set, 79–80, 81 CAD layout tools, 286–87 Graphic Data System II Stream Format (GDSII), 286 InGaP/GaAs HBT, 70 SiGe HBT, 86–87 suppliers, 287 Cascode amplifiers, 111–13 construction, 111–12 defined, 111 schematic diagram, 112 simulated gain and stability, 113 voltage gain, 112 Cellular/PCS, 13–16 handsets, 13–15 infrastructure, 15–16 Cellular/PCS downconverting RFIC, 221–29 block diagram, 222 differential LNA layout, 229 differential LNA schematic diagram, 223 Gilbert cell mixer, 224 Gilbert cell mixer layout, 229 layout, 228 LO phase shifter schematic diagram, 225 lumped-element low-pass filters, 223, 225 overall performance simulation, 227 time domain plot, 228 Cellular repeaters, 16 Choke inductors, 152 Class AB power amplifiers, 139–41 collector current, 140 current waveform, 140 dc power, 140–41

Index

defined, 134 efficiencies, 139 loadline resistance, 140–41 power-added efficiency, 140–41 RF power output, 140–41 See also Power amplifiers (PAs) Class A power amplifiers defined, 134 loadline, 138 See also Power amplifiers (PAs) CMOS devices, 9 fabrication backbone, 85 gate fabrication, 76 passive devices, 85 Code domain multiple access (CDMA), 14, 15, 22 envelope source parameters, 188, 190 handset power amplifiers, 192 modulation spectrum, 145 nonlinearity and, 133 simulated constellation diagram, 191, 192, 193 simulated spectrum, 191, 192, 193 Cognitive radio, 20–21 Colpitts oscillator circuit, 258–61 common-base, 253, 257 common-collector, 159, 253, 262 defined, 258 with Gummel Poon model, 257, 259 schematic diagram, 253, 257, 259 simulated impedance, 260, 262 See also Feedback circuit topologies; Voltage-controlled oscillators (VCOs) Costs production, 298–99 prototype, 298 technology, 295–96 Couple microstrip lines, 54, 55 Crossover capacitances, 61–62 Current-controlled current source (CCCS), 254

D Darlington amplifiers, 154–64, 269 advantages, 155 gain estimate, 155 with horizontally aligned emitter fingers, 162, 163 layout, 159 lumped-element, 157–58 noise figure, 160 parasitic-enhanced performance, 161

Index

parasitic inductance, 164 power output, 155 properties, 154–55 schematic diagram, 155, 156, 160 simulated power input versus power output, 158, 161 simulated S-parameter, 157, 160, 163, 164 stability performance, 164 third-order intermodulation intercept point, 158 with vertically aligned emitter fingers, 162 wideband gain block, 154–64 without layout parasitic elements, 163 See also Power amplifiers (PAs) Darlington LNA, 127–32 compression point, 131 defined, 127–28 differential broadband, 130–31 layout, 130 noise figure, 129 schematic diagram, 129 simulated S-parameter, 129 See also Low-noise amplifiers (LNAs) Dc offset, 38 Dc power efficiency, 25 Device models InGaP/GaAs HBT, 45–48 SiGe HBT, 79–81 Device-to-device isolation, 77 Dielectrically tuned oscillators (DTOs), 267 Differential amplifiers, 109–11 performance, 111 schematic diagram, 110 simulated gain and stability, 111 voltage gain, 111 Differential Darlington LNA, 130–31 Differential filters, 95–99 schematic diagram, 98 simulated S-parameters, 98, 99 Differential I/Q phase-shifting network, 104 Differential PCS power amplifier, 181–93 ACPR, 188, 189 ADS CDMA schematic diagram, 190 ADS GSM signal source, 189 ADS harmonic-balance controller, 188 base bias, 182 block diagram, 183 collector bias, 182 constellation diagram, 189, 190–91 envelope-simulation controller, 189 first stage calculation, 182 first stage schematic diagram, 183

309

layout, 193 output stage size calculation, 182 output transistor schematic diagram, 186 RF collector voltage, 185 second stage schematic diagram, 184 simulated CDMA spectrum, 191, 192, 193 simulated dynamic loadline, 187 simulated GSM spectrum, 189, 190 simulated OIP3, 187 simulated power input versus power output, 185 simulated S-parameters, 183, 184 simulated third-harmonic output, 185 simulated voltage and current waveforms, 186 Differential topologies, 41, 294–95 Differential VCO, 95, 272–78 electronic tuning and, 279–81 layout, 275 phase noise, 277, 278 power output simulation, 277 schematic diagram, 274 simulated S-parameters, 276 top-level schematic diagram, 274 varactor resonator schematic diagram, 275 See also Voltage-controlled oscillators (VCOs) Digital TV, 20 Diode mixers, 197–200 conversion loss, 197 double-balanced, 199 passive, 197–98 single-balanced, 198–99 single-diode, 198 See also Mixers Double-balanced mixers, 199 Double-conversion superheterodyne receiver, 36 Downconverting mixers block diagram, 197 cellular/PCS, 221–29 Gilbert cell, 216 single-balanced transistor, 204 See also Mixers; Upconverting mixers

E Eber-Moll equation, 110 Economics, 293–99 area versus performance trade-offs, 296–97 differential topologies, 294–95 electrical yield, 297–98 integration levels, 293–94

310

Economics (continued) process technology choices, 295–96 production costs, 298–99 prototype costs, 298 single-ended topologies, 294–95 technology costs, 295–96 Electrical yield, 297–98 Energy-conversion process, 248 Error vector magnitude (EVM), 30, 32 defined, 146 power amplifiers, 146–47 in UWB systems, 146 in WiFi systems, 146

F Fano’s limit, 106–7 Feedback application, 164 in LNAs, 123 parallel network, 127 resistors, 165 series, 165 Feedback circuit topologies, 252–61 Colpitts oscillator circuit, 258–61 negative-resistance oscillator circuits, 252–58 See also Voltage-controlled oscillators (VCOs) Feedback power amplifiers, 164–71 ballasting, 166 ballasting resistor layout, 167–68 layout, 68, 170 lumped-element circuit design, 169 lumped-element circuit schematic, 169 RF resistors, 165 schematic diagram, 165, 166 simulated OIP3 versus frequency, 171 simulated power input versus power output, 171 simulated S-parameters, 169, 170 See also Power amplifiers (PAs) Figure of merit (FOM), 278–79 Filtering, mixers, 197 Flicker noise, 118, 119–20 bipolar transistor susceptibility, 120 defined, 119 problem, 120 spectrum, 119 trapping states, 120 See also Noise Foundries applicas, 287

Index

comparison, 287–88 getting to know, 288 PCM pattern layout, 291 Frequency doublers, 231–33 differential, 232–33 diodes, 231 Gilbert cell, 236, 237 schematic diagram, 232, 234 simulated output power, 233 topology, 231 waveform diagram, 232 Frequency multipliers design, 231–39 diode-type, 235 doublers, 231–33 translators, 235–39 triplers, 233–35 Frequency-temperature stability, 261–62 Frequency-translating upconverting mixer, 31 Frequency translators, 235–39 Frequency triplers, 233–35 Gilbert cell, 236, 237–39 output voltage waveform, 235 schematic diagram, 234 simulated output power, 235 waveform diagram, 234 Front-end attenuation, LNAs, 117 Fully balanced active multiplying mixers. See Gilbert cell mixers

G GaAs HBTs, 5 temperature rise, 45 wafer cross section, 44 wafer fabrication, 44 See also Heterojunction bipolar transistors (HBTs) GaAs/InGaP interconnect lines, 82 GaAs MESFETs, 2, 3 GaAs PHEMT, 295 GaAs varactor diodes, 247 Gain compensation, 106 Gaussian frequency-shift keying (GFSK), 18 Gilbert cell mixers, 30, 41 circuit arrangement, 211 circuit diagram, 209–10 circuit schematic diagrams, 206 defined, 205 differential collector current, 209 differential output current, 210–11 differential pair of transistors, 209 disabled transistor and, 214

Index

downconverting, 216 as frequency multiplier, 235–39 intermodulation spurs, 215 as I/Q mixers, 217–19 as I/Q modulators, 219–21 isolations, 213 LO transistors, 207 nodes of operation, 211 noise figures, 216–17 performance parameters, 212–13 RF and LO match, 214 RFIC, 224 schematic diagram, 205 signal analysis, 208–9 simulated conversion gain, 212, 213 simulated input and output spectra, 215 simulated upconverting conversion gain, 215 top transistors, 208 upconverting, 216 See also Mixers Global Positioning Services (GPS), 19 Global System for Mobile Communications (GSM), 15, 22 Golden Gate harmonic-balance simulator, 80–81 Graphic Data System II Stream Format (GDSII), 286 Gummel Poon model, 8, 45 large-signal, 46 limitations, 45 simulated dc IV curves, 47 S-parameter simulation with, 47 Gummel Poon SPICE models (SPG), 79

H Heterojunction bipolar transistors (HBTs) advantages, 7–8 GaAs, 5, 44–45 GaAs/AlGaAs, 7 InGaP/GaAs, 7, 10, 43–70 InP, 8–9 SiGe, 10, 71–87 technologies, 8 Heterojunctions, 6–7 High-pass filters (HPFs), 93 phase shifter, 103 schematic diagram, 93 simulated S-parameters, 94, 95 single section, 93 two-section, 93, 95

311

I IC Editors layout tool, 70 Image filters, 34–35 InGaP/GaAs HBT, 7, 10, 43–70 bonding pads, 60–61 CAD layout tools, 70 crossover capacitances, 61–62 cross section, 45 device models, 45–48 fabrication layers, 49–50 fabrication technology, 43–70, 181 Gummel Poon model, 45 layout example, 65 layout parasitic elements, 65, 66 maximum electrical ratings, 67–70 microstrip lines, 53–55 passive structures, 48–67 process layer resistivity, 52 process layer thickness, 52 process minimum layer line spacing, 52 process minimum layer line widths, 52 spiral inductors, 62–64 transistor dummy cells, 64–65 transistor structures, 43–45 VBIC model, 45–46 See also Heterojunction bipolar transistors (HBTs) InP HBT, 8–9 Input-referred mean-squared noise voltage, 124 Interference, 33 I/Q demodulators, 29 I/Q mixers, 217–19 buffer amplifiers and, 219 circuits in differential form, 218 signal leakage, 218 See also Gilbert cell mixers I/Q modulators, 30–32, 219–21 architecture, 30 defined, 30, 221 frequency-translating upconverting mixer, 31 input voltage, 220 output, 32, 220 simulation, 221 specifications, 221 I/Q receivers, 25–30

J Johnson power limit, 78

312

Index

single-section, 91 two-section, 92

K Kirk effect, 73

L

M

Layout design strategies, 283–92 CAD systems, 286–87 foundry comparison, 287–88 minimum area, 283 on-chip versus off-chip component decisions, 283–84 parasitics, minimizing, 284–85 reticle assembly, 289–92 testability, 285–86 Linear efficiency, 144 Loadline impedance, 179 Loadline resistance class A amplifiers, 138 class AB amplifiers, 140–41 simulated, Smith chart, 148 unit cell, 175 LO leakage, 38, 39 Low-noise amplifiers (LNAs), 10, 32, 41 best technology for, 295 circuit topologies, 118–26 Darlington, 127–32 design, 115–32 effective, 126 feedback, 123 front-end attenuation and, 117 input circuit, 124 matching topology, 122 multistage, 173–75 noise figure calculation, 125 noise figure concepts, 115–16 noise temperature, 116–17 parallel feedback network, 127 project balance, 126 purpose, 32 in receiver sensitivity, 32–33 schematic diagrams, 123, 124, 125, 127 single-ended PCS, 126–27 single-stage, 123, 124, 125, 127 See also Amplifier design Low-pass filters (LPFs), 89–92 differential, 98–99 in lumped-element form, 90 phase shift, 90 phase shifter, 104 RFIC, 225 schematic diagram, 89, 91, 92 simulated S-parameter, 91, 92

M1-to-M2 vias, 57 Matching networks, 149–50 band-pass output, 150 high-pass output, 149 low-pass output, 149 multistage amplifiers, 176, 178 Matching techniques, 105–6 Maximum available gain (MAG), 105 Metal insulator metal (MIM) capacitors, 6, 57–58 cross section, 58 layout, 57, 58 simulator model, 59 Metal migration, 68, 69 Metal-semiconductor field-effect transistors (MESFETs) device gates, 4 GaAs, 2, 3 Microstrip lines, 53–55 ADS schematic symbol, 54 coupled, 54 cross section, 53 electrically critical dimensions, 53 formation, 53 layouts, 54 Microwave circuits, 1 Microwave monolithic integrated circuits (MMICs), 3–4 Mixers, 195–229 active, 200–217 basics, 195–97 cellular/PCS example, 221–29 design, 195–229 diode, 197–200 double-balanced, 199 downconverting, 33, 197 as frequency-conversion device, 195 fully balanced active multiplying, 205–17 Gilbert cell, 30, 41 I/Q, 217–19 as nonlinear devices, 195 output filtering, 197 passive, 197–98 power-series expression, 196 schematic symbol, 195 single-balanced, 198–99, 200–205 upconverting, 31, 197 Mixing frequency, 197

Index

Multistage amplifiers, 173–93 active device sizing, 177–81 cascade of interstage matching networks, 178 dc current requirements, 178 dc power requirements, 180 design procedure, 180–81 differential PCS PA, 181–93 gain allocation, 177 interstage matching network, 176 LNAs, 173–75 loadline impedance, 179 maximum power output, 176 power allocation, 177 power amplifiers, 175–76 power output tracking, 179 spreadsheets, 179, 180 unit cell requirements, 180

N N dB compression point, 141 Negative resistance, 248–51 power gain, 249 resistance magnitude, 250 start oscillation, 249 symbolic diagram, 249 Negative-resistance oscillator circuits, 252–58 common-base, 255, 256 with Gummel Poon model, 254–55 robustness, 258 schematic diagram, 252 simulated impedance, 256 Noise flicker, 118, 119–20 phase, 263–65 shot, 118, 119, 121 sources, 118 thermal, 118, 119, 120–21 white, 119 Noise figure (NF) calculation, 125 concepts, 115–16 conversion to noise temperature, 116–17 Darlington amplifier, 160 Darlington LNA, 129 defined, 115 Gilbert cell mixer, 216–17 minimum, 121 multistage contributions, 117–18 PCS LNA, 128 second-/third-stage contributions, 118 spectrum, 119

313

Noise matching, 109 Noise temperature, 116–17 conversion to/from noise figure, 116–17 defined, 118 Nonlinear performance metrics, power amplifiers, 141–45 Nonzero IF receivers, 32–37 North American Digital Cellular (NADC), 15 NPN HBT devices, 73, 75–76 N-quadrature amplitude modulation (N-QAM), 10, 32

O OIP3 requirements, 179 Orthogonal frequency division multiplexing (OFDM), 17 multiband approach, 19 subchannels, 18

P Parasitics, minimizing, 284–85 Passive circuit design, 89–104 band-pass filters, 93–95 differential filters, 95–99 high-pass filters, 93 low-pass filters, 89–92 phase shifters and baluns, 102–4 splitters/dividers, 99–102 technology and substrates, 99 Passive mixers, 197–98 Passive structures bonding pads, 60–61 crossover capacitances, 61–62 InGaP/GaAs HBT, 48–67 M1-to-M2 vias, 57 microstrip lines, 53–55 MIM capacitors, 57–58 SiGe HBT, 81–86 significant layout parasitic elements, 65, 66 spiral inductors, 62–64 substrate vias, 58–60 TFR resistors, 55–56 transistor dummy cells, 64–65 PCM pattern layout, 291 PCS LNA, 126–27 layout, 128 noise figure, 128 parallel feedback network, 127 schematic diagram, 127 simulated S-parameter, 128 topology, 126–27

314

PCS LNA (continued) See also Low-noise amplifiers (LNAs) Phase modulations, 25–26 BPSK, 26 information rate, 26 performance criteria, 25 Phase noise, 263–65 1/f, 279 differential VCO, 277, 278 ring oscillator, 273 spectrum, 263 thermal noise domination, 264 upconverted 1/F, 265 See also Noise Phase shifters, 102–4 differential LO, 225 HPF schematic, 103 LPF schematic, 104 Power amplifiers (PAs) adjacent channel power ratio (ACPR), 145–46 bias circuits, 150–54 circuit topologies, 147–48 class A, 134, 138 class AB, 134, 139–41 class B, 134 class C, 134 class D, E, and F, 135 classes, 134–35 conversion efficiency, 133 design, 133–71 differential PCS, 181–93 error vector magnitude (EVM), 146 feedback, 164–71 handset, 192 loadline concepts, 134–36 loadline resistance, 137, 139 matching, 136 matching circuit options, 149–50 maximum gain, 135 maximum power and efficiency, 136–39 multistage, 175–76 nonlinear performance metrics, 141–45 OIP3 calculation, 143–44 stability, 150 supply voltage, 138 two-tone intermodulation spectrum, 143 wideband gain block Darlington, 154–64 Power dividers, 99–102 impedances, 102 resistive, 99, 100 Power splitters, 99–102

Index

impedances, 102 Wilkinson, 99, 100, 101 Process technology choices, 295–96 Production costs, 298–99 Prototype costs, 298 Pseudomorphic films, 74 P+ substrate, 82

Q Quadrature phase-shifting networks, 266 Quadrature phase-shift keying (QPSK), 17, 19 constellation diagram, 28 defined, 27 modulator block diagram, 28 phase states, 27

R Radio frequency (RF) circuits, 1 Ratio frequency integrated circuits (RFICs), 4–5 applications, 10, 13–24 CAD systems and, 286–87 cellular handsets, 13–15 cellular infrastructures, 15–16 cellular/PCS downconverting, 221–29 circuit elements, 6 economics, 293–99 heterojunction bipolar technologies, 10 highly integrated, 6 inductor elements, 62–63 testability, 285–86 WiMax and, 20 See also RFIC architectures Receivers I/Q, 25–30 nonzero IF, 32–37 selectivity, 33 superheterodyne, 33, 33–34, 34, 36 WiFi, 38 zero IF, 37–41 Resistive power dividers, 99, 100 Reticle assembly, 289–92 RFCMOS, 5 RFIC architectures, 25–41 differential versus single-ended topologies, 41 I/Q modulators, 30–32 I/Q receivers, 25–30 nonzero IF receivers, 32–37 zero IF receivers, 37–41

Index

See also Ratio frequency integrated circuits (RFICs) Ring oscillators, 267–72 block diagram, 268 measured power output, 272, 273 measured S-parameters, 269, 270 mechanical cross section, 271 open-loop gain and phase, 269, 270 simulated phase and amplitude noise, 273 simulated power output, 272 wideband Darlington amplifier, 268 YIG-tuned filter, 268 See also Voltage-controlled oscillators (VCOs)

S Scaled linearity, 144 Scratch protection via (SPV), 60 Selectivity, 33 Series feedback, 165 Set-top boxes, 20 Shot noise, 118 collector, 121 mean square current intensity, 120–21 spectrum, 119 as white noise source, 119 See also Noise SiGe, 9 bipolar devices, 76 epitaxial base layers, 73 epitaxial concentration, 72 foundry processes, 79 maximum stable base thickness, 75 thin films, 73, 74 transistors, 72 VCOs, 9 SiGe BiCMOS process, 83–86 capacitor options with electrical parameters, 85 capacitor simulator model, 83 cross talk substrate coupling with, 87 metal layer parameters, 84 resistor options with electrical parameters, 85 resistor simulator model, 83 spiral inductor simulator model, 84 varactor diode options, 86 SiGe HBT, 10, 71–87 CAD layout, 86–87 design rules, 86 device evolution, 71 device models, 79–81

315

dual heterojunction, 72 extrinsic-base, 76 fabrication technology, 71–87, 181 GaAs/InGaP interconnect lines, 82 passive structures, 81–86 transistor structures, 71–78 See also Heterojunction bipolar transistors (HBTs) Signal-to-noise ratio (SNR), 14, 32 Significant layout parasitic elements, 65, 66 Single-balanced mixers, 198–99 active multiplying, 200–205 bias tree layout, 204 conversion gain, 205 conversion loss, 204 input power, 202 isolations, 204 layout, 203 output spectrum, 204 power conversion gain, 202 schematic diagram, 201 totem pole bias supply, 202 transistor layout, 203 waveform, 204 See also Mixers Single-ended topologies, 41, 294–95 Spectral efficiency, 25 Spectrum allocation, 21–22 Spiral inductors, 62–64, 102 electrical model for simulation, 64 layout, 64 resonator elements, 63 square spirals, 62–63 Splitters/dividers, 99–102 Stability in amplifier design, 107–9 bipolar process, 297 cascode amplifiers, 113 Darlington amplifier, 164 differential amplifiers, 111 factor, 108 frequency-temperature, 261–62 power amplifiers (PAs), 150 Substrate vias, 58–60 cross section, 60 defined, 58 layout, 59 Superheterodyne receiver, 33, 34 double-conversion, 36 downconversion process, 34 single-conversion, 34 Surface-mount technology (SMT) inductors, 69

316

T Technology costs, 295–96 Testability, 285–86 TFR resistors, 55–56 cross section, 55, 56 layout, 56 simulator model, 56 Thermal noise, 118 resistors, 120 spectrum, 119 thermal agitation, 120 as white noise source, 119 See also Noise Thin film resistors. See TFR resistors Third-generation (3G) cellular technology, 16 Time domain multiple access (TDMA), 14, 15, 22 Transistor dummy cells, 64–65 Transistor structures InGaP/GaAs HBT, 43–45 SiGe HBT, 71–78 Traveling-wave tubes (TWTs), 1, 2, 3

U Ultrahigh vacuum chemical vapor deposition (UHV/CVD), 72 Ultrawideband (UWB) transmission, 18–19 concept, 18–19 EVM metric, 146 physical layer standards, 23 standards, 19 as wireless USB standard, 18 Upconverting mixers block diagram, 197 Gilbert cell, 215, 216 See also Downconverting mixers; Mixers

V Varactor diodes, 242–48 abrupt-junction, 243–48 capacitance and resistance relationship, 244 capacitance change, 245, 248 doping profile, 244–45 electric field behavior, 243 frequency tuning curve, 246 GaAs, 247 at low reverse voltage, 244 noise sources, 263 space-charge density, 243 structure, 242 tuning, 280

Index

voltage controllable, 242 Varactor resonator, 275 Varactor-tuned VCOs, 21, 267 differential, 280, 281 negative-resistance, 278 power output, 281 schematic diagram, 280 VBIC model, 45–46 dc IV curve generation, 48 dc IV curve simulation, 49 large-signal, 48 S-parameter simulation, 49 Vertical Bipolar Industrial Committee (VBIC), 8 VGA saturation, 39–40, 41 Voltage-controlled oscillators (VCOs), 6, 241–81 biopolar technology design, 295 design, 10, 241–81 differential, 95, 272–78 electronic tuning and, 279–81 electronic tuning range, 265 feedback circuit topologies, 252–61 figure of merit (FOM), 278–79 frequency-temperature stability, 261–62 IC, 251 low-phase-noise, 9 negative-resistance, 278, 280 negative-resistance concepts, 248–51 phase noise, 263–65 quadrature phase, 30 quadrature phase-shifting networks, 266 resonator types, 252 RF circuits, 241 ring oscillators, 267–72 SiGe, 9 tuning port, 241 varactor diodes, 242–48 varactor-tuned, 21, 267, 280–81

W White noise, 119 Wideband gain block Darlington amplifier, 154–64 WiFi, 16–17 Bluetooth standards and, 18 equipment, 17 EVM metric, 146 OFDM modulation, 17 physical layer standards, 23–24 receivers, 38 Wilkinson power combiner/splitter, 99–102

Index

schematic diagram, 100 S-parameters, 101 WiMax, 19–20 Wireless local-area networks (WLANs), 16–17

Y YIG-tuned oscillators (YTOs), 21 in Ku band, 267 magnetic structure, 271 negative-resistance-type circuit, 267 output power simulation, 271

317

silicon bipolar transistors, 267 Yttrium iron garnet (YIG), 241–42, 262

Z Zero IF receivers, 37–41 block diagram, 37 defined, 37 disadvantages, 38 effectiveness, 40 See also Receivers ZigBee, 23