Frequency Synthesizers: From Concept to Product (Artech House Microwave Library)

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Frequency Synthesizers Concept to Product

For a complete listing of titles in the Artech House Microwave Library, turn to the back of this book.

Frequency Synthesizers Concept to Product

Alexander Chenakin

Library of Congress Cataloging-in-Publication Data A catalog record for this book is available from the U.S. Library of Congress. British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library. Cover design by Vicki Kane

ISBN 13: 978-1-59693-230-2

© 2011 ARTECH HOUSE, INC. 685 Canton Street Norwood, MA 02062

All rights reserved. Printed and bound in the United States of America. No part of this book may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage and retrieval system, without permission in writing from the publisher. All terms mentioned in this book that are known to be trademarks or service marks have been appropriately capitalized. Artech House cannot attest to the accuracy of this information. Use of a term in this book should not be regarded as affecting the validity of any trademark or service mark.

10 9 8 7 6 5 4 3 2 1

To my family

Contents xiii

Preface 1

Parameters and Architectures

1

1.1

Frequency Synthesizer Concept

1

1.2 1.2.1 1.2.2 1.2.3 1.2.4

Main Parameters Frequency and Timing Spectral Purity RF Output Power Other Parameters

3 3 5 12 14

1.3

Form Factors and Applications

14

1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 1.4.9

Control Interfaces Parallel Interface SPI I2C RS-232 USB GPIB VXI PXI LXI

16 16 17 20 20 20 21 21 22 23

vii

Frequency Synthesizers: Concept to Product

viii

1.4.10

AXIe

24

1.5 1.5.1 1.5.2 1.5.3

Main Architectures Direct Analog Synthesizers Direct Digital Synthesizers Indirect Synthesizers

24 25 31 35

References

38

2

Building Blocks

41

2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5

Oscillators Phase Noise in Microwave Oscillators Resonators Coupling Active Devices Noise Reduction Techniques

41 42 45 53 53 54

2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8

Frequency Multipliers Frequency Multiplication Single-Diode Multipliers Balanced Diode Multipliers Antiparallel Diode Multiplier Digital Logic Multipliers Step-Recovery-Diode Multipliers Varactor Multipliers Transistor Multipliers

58 58 59 60 62 62 63 64 64

2.3 2.3.1 2.3.2

Frequency Dividers Digital Dividers Analog Dividers

64 65 69

2.4 2.4.1 2.4.2 2.4.3 2.4.4

Frequency Mixers Frequency Mixing Harmonic Mixers Image-Reject Mixers IQ-Modulators

69 70 71 72 73

2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5

Phase Detectors Balanced Mixer Sampling Mixer Exclusive-OR Gate Flip-Flop Phase-Frequency Detector

74 74 75 75 76 76

Contents

ix

2.5.6

Integrated PLL Components References

79 82

3

Synthesizer Construction

87

3.1

Transmission Lines and Distributed Elements

87

3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6

Transmission Line Basics Transmission Line Types Microwave Materials Discontinuity Effects Coupling Distributed and Lumped Elements

87 89 92 95 95 96

3.2

Chip-and-Wire Approach

97

3.3

Printed Circuit Board

98

3.4 3.4.1 3.4.2 3.4.3 3.4.4

Packaging Electrical Interface Environmental Protection Shielding Mounting and Heat Sinking References

101 101 103 103 106 107

4

Design Process

109

4.1

Specifications

109

4.2

Block Diagram

110

4.3

Schematic

116

4.4

Board Layout

133

4.5

Assembly

134

4.6

Mechanical Design

135

4.7

Control Software

136

4.8

Troubleshooting

138

4.9

Testing

141


x

4.10

Documentation

145

References

146

5

Improving Performance

149

5.1

Performance Trade-Offs

149

5.2

Fractional-N

151

5.3

Using a DDS

155

5.4

Frequency Offset Schemes

158

5.5

Multiloop Architectures

163

5.6

Frequency Acquisition

164

5.7

Lock Monitoring

169

5.8

Fast-Switching Designs

170

5.9

VCO or YIG?

172

5.10

Reference Generation and Distribution

176

5.11

Filtering Harmonics

177

5.12

Frequency Extension

181

References

184

6

Advanced Functions

187

6.1

Frequency Stability and Synchronization

187

6.2 6.2.1 6.2.2 6.2.3

Frequency Control Blanking Frequency Sweep List Mode

191 191 192 194

6.3 6.3.1 6.3.2 6.3.3 6.3.4

Output Power Control Open-Loop Control Closed-Loop Control Power Equalizer Power Sweep

194 194 196 197 197

Contents

xi

6.3.5

Power Mute

198

6.4 6.4.1 6.4.2 6.4.3 6.4.4

Modulation Pulse Modulation Amplitude Modulation Frequency and Phase Modulation Complex Modulation References

198 198 200 201 204 206

About the Author

207

Index

209

Preface Frequency synthesizers have evolved over time, and this book offers an overview of well-established and recently developed techniques. It is primarily intended for engineers in their first years of practice and serves as a quick and effective guide to mastering professional skills. This book aims to bridge the gap between basic theoretical knowledge and the years of work required to build practical experience. It covers all design aspects including main architectures, key building blocks, and practical circuit implementations. This book is also likely to be helpful to professionals (engineers, researchers, consultants, and marketing and sales specialists), since it is meant to supplement technical articles, application notes, and design recipes in the field of frequency synthesis. This book is divided into six chapters that guide the reader from introductory material to advanced design topics. Chapter 1 provides a brief introduction to the field of frequency synthesis. It starts with general definitions and requirements followed by a review of main synthesizer architectures. Direct analog, direct digital, and indirect techniques are compared in terms of performance, circuit complexity, and cost impact. Chapter 2 continues with a review of key building blocks from the perspective of their practical use in microwave frequency synthesizers. The main focus is on how undesired signals (spurs and phase noise) are generated and then propagate through synthesizer components. Oscillators, frequency multipliers, dividers, mixers, phase detectors, and complex integrated circuits are discussed. The next logical step is to examine how the individual synthesizer components are physically connected together. Chapter 3 focuses on constructional and

xiii

xiv


packaging principles used for building microwave frequency synthesizers. It begins with a brief overview of transmission line theory, types of transmission lines, characteristic impedance, losses, discontinuity and coupling effects, microwave materials, and distributed and lumped elements. Chapter 3 continues with a review of the most popular assembling techniques including hybrid chip-and-wire and printed circuit board approaches. Packaging aspects, including grounding and shielding effects, are also discussed. Chapter 4 moves from general concepts to practical applications. A simple single-loop PLL example is used to demonstrate the most important aspects of the design process from the block diagram to production. The chapter begins by capturing and formulating design goals as formal specifications. A block diagram is created as a high-level pictorial model, which helps the reader to understand the overall design concept. It is transformed into a schematic that shows all individual components and their connections. Component selection and circuit optimization are discussed in detail. The design is laid out and implemented on a printed circuit board. It is discussed how to bring the assembled board to life through step-by-step troubleshooting of its individual blocks. Finally, the circuit is refined, tested, and properly documented. Additional small changes may be required until the design develops into a stable product that can be released to production. The simple single-loop PLL synthesizer scheme analyzed in Chapter 4 exhibits various limitations and trade-offs. Chapter 5 examines various design alternatives to achieve different performance objectives such as fast switching speed, low phase noise, and fine resolution. The design trade-offs are analyzed and complemented with a review of fractional-N, DDS, frequency offset, multiloop, and other schemes. Chapter 5 also covers such important design aspects as initial frequency acquisition, lock monitoring, oscillator selection, harmonic filtering, and frequency extension. The main function of any frequency synthesizer is to deliver a stable and clean signal. However, inside any synthesizer there are many circuits that can carry multiple functions and be reused to increase the functionality without a significant increase in cost. Chapter 6 concludes the book with notes on advanced design options that address frequency synchronization, sophisticated frequency and power control, and various modulation functions. Note that this book serves as a live guide to practical designs rather than acting as a comprehensive handbook. Although basic theoretical background is presented, mathematical treatment is kept at a minimum and left to numerous reference sources readily available. Several topics would require separate texts of their own. Further details can be found in the attached references listed in accordance with the individual chapter topics. Many pertinent sources have been cited; I apologize in advance to anyone who may have been slighted.

Preface

xv

The work presented in this book could not have happened without the help of many people. I express my sincere appreciation to colleagues from Phase Matrix, Inc. as well as other organizations that supported this endeavor. I especially thank Richard Bush, Pete Pragastis, Suresh Ojha, Heather Brown, Ronni Basu, Anthony Estrada, and Doug Padrick for their valuable suggestions that complemented the text. Finally, I would like to thank the Artech House team for their effort in publishing this book.

1 Parameters and Architectures The frequency synthesizer is a key component of virtually any radio-frequency (RF) and microwave test-and-measurement, communication, and monitoring system. It generates a stimulus signal and is used as a local-oscillator (LO) source in a variety of upconversion and downconversion schemes. Synthesizer designs utilize various techniques and are almost as diverse as the number of their applications [1–6]. This chapter provides a brief introduction to the field of frequency synthesis. It starts with general definitions and requirements followed by a review of the main synthesizer architectures. Direct analog, direct digital, and indirect techniques are compared in terms of performance, circuit complexity, and cost impact.

1.1 Frequency Synthesizer Concept A frequency synthesizer is an electronic device that translates one (or more) input base (reference) frequency to a number of output frequencies as illustrated in Figure 1.1. It can be treated as a “black box” containing individual components or building blocks such as voltage-controlled oscillators (VCOs), frequency dividers, multipliers, mixers, and phase detectors, which, when properly connected, perform this translation function. Its structure is defined by a system architecture that describes the organization and relationships among the individual components. Synthesizer architectures can be classified into a few main groups as indicated in Figure 1.2. The direct architectures are intended to create the output

1

2

Frequency Synthesizers: Concept to Product Δf

Frequency synthesizer fREF

Figure 1.1

fMIN

fMAX

Frequency synthesizer concept.

Frequency synthesizers

Indirect

Direct

Analog

Digital

Analog

Digital

Hybrid techniques

Figure 1.2

Frequency synthesizer classes.

signal directly from the available base frequency signals either by manipulating and combining them in the frequency domain (direct analog synthesis) or by constructing the output waveform in the time domain (direct digital synthesis). The indirect methods assume that the output signal is regenerated inside the synthesizer in such a manner that the output frequency relates (e.g., is phase-locked) to the input reference signal. Similarly, indirect synthesis can be accomplished with analog and digital techniques. Indirect synthesizers are also associated with integer and fractional-N phase-lock-loop (PLL) techniques, as will be further discussed in Chapter 5. A practical synthesizer, however, is usually a hybrid design that combines various techniques to achieve specific design goals based on the destination of the product. A good example is a multiloop synthesizer that is essentially a combination of direct analog (frequency mixing) and indirect PLL methods. By combining both technologies, it is possible to take advantage of the best aspects of each. These hybrid solutions, along with their design limitations and trade-offs, are discussed in more detail in Chapter 5.


3

1.2 Main Parameters An ideal synthesizer is intended to provide a pure sine-wave signal that, in the frequency domain, is represented as a pair of delta functions. Such an ideal signal would appear as a single tone (or, in other words, an indefinitely narrow line) on a spectrum analyzer screen. In reality this line is spread by signal fluctuation effects (referred to as phase noise or jitter); some other signal artifacts (spurs and harmonics) are also present. In the time domain, these artifacts manifest themselves as signal waveform distortion. The quality and usability of synthesized signal are determined by a few key parameters or specifications. The synthesizer’s parameters can be divided into a few groups depicting its frequency and timing (frequency coverage, resolution, accuracy, switching speed), spectral purity (harmonics, spurs, phase noise), and RF output power (output power, control range, step size, accuracy, flatness, impedance, return loss) characteristics, as well as how the synthesizer interfaces with the outside world (control interface, bias, power consumption, and size). 1.2.1

Frequency and Timing

Frequency coverage or range denotes the range of frequencies that can be generated by the synthesizer. It is specified in the units of hertz (megahertz and gigahertz) by indicating the minimum and maximum frequencies generated by the synthesizer. Frequency resolution or step size is the maximum frequency difference between two successive output frequencies indicated in Figure 1.1 as Δf = fn+1 − fn. The frequency coverage and resolution are fundamental synthesizer specifications set by a particular application. Some applications (e.g., test and measurement) require wide bandwidth and fine frequency resolution, while others need a relatively narrowband (10–20%) coverage with a rough step size or just a single fixed frequency. Frequency accuracy indicates the maximum deviation between the synthesizer’s set output frequency and its actual output. Frequency accuracy is normally determined by the reference signal, which can be internal or external to the synthesizer. Frequency synthesizers usually employ a crystal oscillator as an internal reference. The crystal oscillator’s temperature stability and aging are important characteristics that define the synthesizer’s frequency accuracy. Temperature stability denotes the maximum frequency drift over the operating temperature range and is usually expressed in ppm. The term ppm is an acronym for parts per million—a dimensionless coefficient equal to 10−6. For example, the temperature stability of 0.5 ppm for a 100-MHz crystal oscillator means that the oscillator frequency can drift up to 50 Hz (0.5 × 10−6 × 100 × 106 Hz) over the specified operating temperature range.

4


Aging is a change in frequency over time that occurs because of changes in the resonator material or a buildup of foreign material on the crystal. It is also specified in ppm over a certain period of time. Aging leads to a permanent frequency error; thus, it is good practice to use mechanical or electronic frequency adjustment means to compensate for internal reference aging. Switching or tuning speed determines how fast the synthesizer transitions from one desired frequency to another and is defined as time spent by the synthesizer between these two states (thus, the switching time is a more proper term). The definition seems straightforward for a hypothetical dual-frequency synthesizer (shown in Figure 1.3) where the frequency change is performed with an electronic switch. In this case, the switching time is simply a propagation delay inserted by the switch and its control circuit. However, a practical frequency acquisition scenario is usually a more complex process, as illustrated in Figure 1.4 for a PLL synthesizer. Let’s assume that at time t0 we send a command requesting the synthesizer to change its frequency from f1 to f2. Before starting the transition, the synthesizer needs to receive the command (which can be a digital data stream or a single trigger pulse), make all necessary calculations according to the synthesizer’s frequency tuning algorithm, and then program its individual devices (e.g., a programmable frequency divider in the PLL feedback path). Since this process takes a certain amount of time, the frequency transition itself starts at t1. Then the synthesizer’s PLL circuit steers the VCO to the desired frequency by changing the voltage on its tuning port. The process is not instantaneous and is similar to the process of charging a capacitor (that is a part of the PLL filter indeed). Moreover, the VCO can pass on the destination frequency; thus, the PLL has to return the VCO output back by correcting its tuning voltage. Depending on the dynamic characteristics of a particular loop filter, this process also takes time before the PLL brings the VCO output close enough to the desired frequency in order to meet the system requirements (point t2). The total switching time is calculated from the time when the synthesizer receives a command to the time it approaches the desired frequency with a specified accuracy (e.g., ±1 MHz, ±50 kHz, ±0.1 ppm, and so forth). It is also assumed that the synthesizer can jump from any one frequency

F1

F2

Figure 1.3

Switching time is set by a propagation delay inserted by the switch.


5 ΔF

f

f2

f1 t0

Figure 1.4

t1

t2

t

Frequency acquisition in a PLL synthesizer.

to any other frequency within its operating frequency range (unless otherwise specified). The switching speed is determined by a particular synthesizer scheme and is usually a trade-off between other synthesizer parameters, such as step size, spurs, or phase noise. 1.2.2

Spectral Purity

Harmonics appear in the synthesizer spectrum as integer multiples of the output frequency because of signal distortion in nonlinear components. For example, if the fundamental frequency is represented by f, the frequencies of the harmonics would be represented by 2f, 3f, and so forth. Harmonics are expressed in dBc (decibels relative to the carrier) and represent the power ratio of a harmonic to a carrier signal as shown in Figure 1.5. Harmonics usually do not cause serious problems since they are well separated from the main tone and can be easily filtered out. Moreover, they are often recreated in a nonlinear device (such as a mixer) connected to the synthesizer. The range of −15 to −30 dBc is acceptable

P, dBm ΔP, dBc

f

2f

3f

Figure 1.5 Harmonics appear in the synthesizer spectrum due to signal distortion in nonlinear components.

6


in many cases, although the level should be reduced to −50 dBc or even lower in some harmonic-sensitive applications such as test-and-measurement instruments. For a narrowband synthesizer, this is easily achieved by placing a lowpass filter at the output. A switched filter bank or a tunable filter is required for bandwidths reaching or exceeding an octave. Subharmonics are created at frequencies that are “subharmonically” related to the main signal such as f /2, f /3, and so forth. Propagating through nonlinear components, these signals exhibit their own harmonics. Thus, in a more general case, the subharmonics are considered as products appearing at N/K of the output frequency, where N and K are integers. A typical example that can demonstrate the creation of subharmonics is a frequency doubler, which is often used to extend the synthesizer output frequency range. As a nonlinear device, the doubler generates a number of harmonics of the incoming signal. It usually employs a balanced scheme that intends to suppress odd products as shown in Figure 1.6. Since the second harmonic now becomes the main signal, all the odd products, which are not completely suppressed, do not meet the harmonic relationship with respect to the desired output and are, therefore, treated as subharmonics. Another example is divider leakage, which can be found in PLL circuits as illustrated in Figure 1.7. In this example, the VCO signal at 2 GHz is divided down to 1 GHz by a frequency divider inserted into a PLL feedback path. The divider output is rich in odd harmonics due to the square-wave waveform of the signal produced by the divider. These products can leak back to the VCO output due to insufficient isolation of the feedback path and appear as subharmonics with respect to the VCO’s main signal. Similar to harmonics, subharmonics of a small order (e.g., 1/2 or 3/2) are well separated from the main output and, hence, can be easily filtered. However, high-order products can present a serious problem due to decreasing separation from the main tone. As a common rule, the subharmonics are normally treated as spurious (i.e., nonharmonically related) signals. Spurious signals or spurs are undesired artifacts created by the synthesizer at some discrete frequencies that are not harmonically related to the output signal

12 34

1

12 34

×2

Figure 1.6

A frequency doubler can generate subharmonic products.


2 4

7

1 2 34

VCO

÷N 1 2 34

Figure 1.7

Another subharmonic example.

ΔP, dBc

f

Figure 1.8

2f

3f

Spurious products are not harmonically related to the output signal.

(Figure 1.8). Spurs can come from different sources such as PLL reference spurs, mixer intermodulation products and LO leakage, some internal auxiliary signals, or even external signals coming through the bias or control interface. Although the spurs seem randomly positioned in the synthesizer spectrum, their location is mostly determined by a particular synthesizer architecture and frequency plan. In contrast to harmonics, the spurs are much more troublesome products that can limit the ability of receiving systems to resolve and process a desired signal. Spurs can sit very close to the main tone and in many cases cannot be filtered. Thus, the spurious level has to be minimized, typically to −60 dBc relative to the main signal, although many applications require bringing this level even lower. This presents a certain design challenge, especially if a small step size is required. A different concern is mechanically induced spurs usually referred to as “microphonics.” These spurs appear due to the sensitivity of certain synthesizer components to external mechanical perturbations and are treated by mechanical (e.g., damping) and electrical (e.g., wideband PLL) means. Phase noise is a measure of the synthesizer’s short-term frequency instability, which manifests itself as random frequency fluctuations around the desired

8


tone. As mentioned earlier, the output of an ideal synthesizer is a pure sine-wave signal with amplitude A0 and frequency ω0 = 2πf0 that is described by VOUT = A0 sin ω0t

(1.1)

However, in reality the output signal demonstrates amplitude and phase variations (Figure 1.9) because of noise fluctuations in the synthesizer’s components, which can be represented as follows: VOUT = ( A0 + a (t )) sin ( ω0t + ϕ (t ))

(1.2)

where a(t) and ϕ(t) are the amplitude and phase fluctuations, respectively. Amplitude noise is rarely as critical as phase noise. The amplitude variations can be easily reduced by balanced mixers, amplifiers in compression, diode limiters, or an automatic level control circuit. Hence, the phase effects generally dominate, reducing (1.2) to VOUT = A0 sin ( ω0t + ϕ (t ))

(1.3)

These phase fluctuation effects result in uncertainty on the signal zerocrossing, which in the time domain is referred as jitter. How do these fluctuations affect the synthesizer output spectrum? Let’s imagine that the phase fluctuations ϕ(t) are caused by an unwanted fixed-frequency signal ωm = 2πfm that modulates the synthesizer output frequency (for example, by approaching and modulating the VCO tuning port) and are expressed as ϕ (t ) = Am sin ωmt

(1.4)

In this case, the output signal can be described by VOUT = A0 sin ( ω0t + Am sin ωmt ) Amplitude variations

Phase variations

t

Figure 1.9

(1.5)

t

The synthesizer output signal exhibits both amplitude and phase variations.


9

With a well-known trigonometric identity sin(α + β) = sin α cos β + cos α sin β, the expression (1.5) is transformed into VOUT = A0 ⎡⎣sin ω0t cos ( Am sin ωmt ) + cos ω0t sin ( Am sin ωmt )⎤⎦

(1.6)

Assuming that the amplitude of the modulating signal Am is small (we can restrict a large unwanted signal at the most sensitive point in our design, right?), we can simplify corresponding terms of (1.6) to cos ( Am sin ωmt ) ≈ 1

(1.7)

sin ( Am sin ωmt ) ≈ Am sin ωmt

(1.8)

reducing the expression (1.6) to VOUT ≈ A0 ( sin ω0t + Am cos ω0t sin ωmt )

(1.9) 1

Using another elementary trigonometric formula, sin α cos β = [sin (α 2 + β) + sin (α − β)], the expression (1.9) is further modified to A ⎧ ⎫ VOUT ≈ A0 ⎨sin ω0t + m ⎡⎣sin ( ωmt + ω0t ) + sin ( ωmt − ω0t )⎤⎦ ⎬ 2 ⎩ ⎭

(1.10)

and finally

VOUT ≈ A0 sin ω0t +

A0 Am AA sin ( ω0 + ωm ) t − 0 m sin ( ω0 − ωm ) t 2 2

(1.11)

Note that (1.11) has three sinusoidal terms related to ω0, ω0 − ωm, and ω0 + ωm. Thus, in the frequency domain, the output signal is no longer a single spectral line but adds two spurious sidebands equally spaced by fm (below and above the main signal) as shown in Figure 1.10. This is a typical spectrum that represents spurious sidebands caused by a modulating signal of a fixed frequency fm. Obviously, if fm is not a fixed frequency but changes randomly, the sidebands also spread randomly over frequencies both above and below the nominal signal frequency. What spectrum should we observe in this case? To answer this question, let’s imagine that we can take a series of hypothetically instantaneous screenshots of such a fluctuating signal. Intuitively, we can say that in most cases we will

10

Frequency Synthesizers: Concept to Product PLL Spurs dBm 6 GHz 20 10 0 −10 −20 −30 −40 −50 −60 −70 −80

Start: 5.9750 GHz Res BW: 300 Hz

Vid BW: 1 kHz

Stop: 6.0250 GHz Sweep: 200.00s

Figure 1.10 The modulation on a VCO tuning port results in spurious sidebands below and above the main tone.

find the output somewhere close to the desired nominal frequency rather than far away from it. In other words, a “good” synthesizer design generates a signal that contains most of its energy around the nominal frequency as illustrated in Figure 1.11. How can we quantify this intuitive view of the spectral distribution? Obviously, we should do it by measuring the output power at many frequencies away from the nominal frequency and comparing it to the power at the nominal frequency. This leads us to a quantitative definition of the phase noise as the ratio of the noise power found in a 1-Hz bandwidth at a certain frequency offset Δf to the total power at the carrier frequency f0, which can be written as ⎛ Pf1 Hz ⎞ + Δf = 10 log ⎜ 0 ⎟ ⎝ Pf 0 ⎠

(1.12)

This ratio is normally taken in the logarithmic scale; hence, the phase noise is expressed in units of dBc/Hz (dBc per hertz) at various offsets from the carrier frequency and is usually specified by a table or as a graphic representation. Phase noise is one of the major parameters that ultimately limits the performance of RF and microwave systems. To illustrate this, let’s examine the ability of a microwave receiver to resolve a signal of small amplitude. The receiver is essentially a mixer that converts the signal down and processes it at a lower


11

P

1 Hz Δf

f0

Figure 1.11 signal.

f

Phase noise manifests itself as random frequency fluctuations around the output

intermediate frequency (IF). Naturally, the conversion is affected by the quality of the available LO source as illustrated in Figure 1.12. A receiver utilizing an LO source with excessive phase noise (source A) will not be able to detect the signal since it is masked under the phase noise. In order to receive the desired signal, either the transmitter has to provide higher output power, or a better LO source (source B) is required. Therefore, phase noise generated by the frequency synthesizer is a critical parameter that imposes the ultimate limit on the system’s ability to resolve signals of small amplitude. Phase noise minimization is a primary design concern—it demands a specific effort and usually results in a trade-off between other synthesizer parameters. dBm Source A Source B Signal 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100

Figure 1.12

Start: 9.9990 GHz Res BW: 10 kHz

Vid BW: 100 Hz


Excessive phase noise limits the ability to resolve a signal of small amplitude.

12

1.2.3


RF Output Power

Output power is a measure of the synthesizer output signal strength specified in units of watt or, more frequently, in dBm. The term dBm refers to the ratio in decibels of the measured power referenced to 1 milliwatt. The relationship between these two units is expressed by PdBm = 10 log Pmwatt

(1.13)

The RF output power can vary within a wide range depending on a particular application. A typical scenario assumes the frequency synthesizer as an LO source driving a frequency mixer in a variety of upconversion and downconversion schemes. This normally requires a 10- to 17-dBm output signal, although some applications need more power. A simple synthesizer usually delivers a fixed power level that cannot be changed. More complex designs provide an ability to control the output power in a specified range. In the latter case, the output power control range (i.e., the minimum and maximum values between which power can be set) and the power step size (i.e., the minimum change between two consecutive power settings) are specified as well. Note that output power can differ from its set value. This discrepancy is described by the output power accuracy that defines the absolute maximum variance between programmed and actual (i.e., measured) power values. Output power flatness denotes the difference between the maximum and minimum power values within the operating frequency range as shown in Figure 1.13. The output power usually tends to decrease at higher frequencies because of a “natural” gain roll-off of individual devices in the synthesizer output chain. Sophisticated synthesizer designs include compensation mechanisms using either hardware (e.g., gain equalizers) or software (e.g., power calibration) methods. The output power also varies with temperature change (Figure 1.14) and P

PMAX PMIN

f

Figure 1.13 Output power flatness denotes the difference between the maximum and minimum power values across the operating frequency range.


13

P T = 0°C C T = 25°C T = 55°C

f

Figure 1.14

Output power variations caused by temperature change.

is specified as a maximum power variation over operating temperature range. These two parameters are often combined together to present the total power variations at all operating conditions. Output impedance is an important characteristic since RF and microwave devices are supposed to be matched with other devices when connected. At microwave frequencies the source and load impedances are normally set to 50 ohms, although some equipment works in other environments (e.g., 75 or 600 ohms). When the source and load impedances are mismatched, some incident power is reflected back. As a result, not all of the available power from the source is delivered to the load. To describe this “loss,” the concept of return loss is introduced as RL = −20 log Γ

(1.14)

where Γ is the voltage reflection coefficient well known from transmission line theory. The return loss is measured in decibels and indicates how close the synthesizer output impedance is to 50 ohms (or another specified value). The best scenario assumes no reflection (i.e., Γ = 0), which corresponds to negligibly small return loss. On the other hand, a return loss of 0 dB corresponds to total reflection when |Γ| = 1 and all incident power is reflected. Alternatively, the output match can be described by the voltage standing wave ratio or VSWR, which relates to the voltage reflection coefficient as

VSWR =

1+ Γ 1− Γ

(1.15)

The VSWR of 2:1 (that roughly corresponds to a −10-dB return loss) is typically an acceptable level for many synthesizer designs. A better match is

14


required for some demanding applications and can be achieved by connecting an attenuator to the synthesizer output as depicted in Figure 1.15. This, however, results in reduced power level. 1.2.4

Other Parameters

Other specifications may include power supply (DC or AC voltage, current, power consumption), mechanical (size, weight, mounting dimensions), and environmental (temperature, humidity, altitude, vibration) characteristics as well as some special features such as dual output (or a number of outputs), various modulation options, and many other functions tailored to specific applications.

1.3 Form Factors and Applications Synthesizers come in a variety of forms ranging from tiny PLL chips and moderate-size modules to bench-top signal generators. Single-chip synthesizers are available in a die form or as surface-mount integrated circuits (ICs). They include key elements (such as RF and reference dividers, phase detector, and lock indicator) that are required to build a simple single-loop PLL synthesizer. More complex ICs include a built-in VCO, multiple PLLs, direct digital synthesizer (DDS), and other valuable components integrated on a single chip. Such ICs are installed on a printed circuit board (PCB) with additional circuitry (e.g., loop filter components) and are used in many applications, including various communication systems, wireless portable devices, FM radio, and TV receivers. They are also utilized as components in more complex, hybrid synthesizer designs. The next level of integration includes PCB-based modules that range from small, surface-mount, “oscillator-like” designs to more complex connectorized assemblies as exhibited in Figure 1.16. The level of complexity varies from simple single-loop PLLs to sophisticated multiloop and DDS-based designs. These are normally installed into larger systems that provide all necessary control functions as well as mechanical support and electrical shielding. Applications include various test-and-measurement, communication, and monitoring systems. Alternatively, such PCB assemblies can be packaged into metal housings and presented as complete, stand-alone synthesizer modules. These can be quite so-

Frequency synthesizer

Figure 1.15

An attenuator at the synthesizer output improves its return loss.


Figure 1.16

15

A PCB-based synthesizer module. (Courtesy of General Electronic Devices, Inc.)

phisticated designs (such as that shown in Figure 1.17) that include an internal microcontroller to control individual devices inside the synthesizer. Connectorized synthesizer modules (often called “bricks”) can be used to build larger bench-top and rack-mountable signal generators for test-andmeasurement applications. These are fairly complex, system-type instruments (Figure 1.18) complete with an AC power supply, display, and various communication interfaces. They come with high-end technical characteristics, precise calibration, and extended functionality including frequency and power sweep, various modulation modes, built-in modulation sources, and many other functions.

Figure 1.17 The QuickSyn synthesizer module features high performance and extended functionality. (Courtesy of Phase Matrix, Inc.)

16


Figure 1.18 A bench-top signal generator. (Copyright Agilent Technologies, Inc. 2007. Reproduced with permission.)

1.4 Control Interfaces The control interface is an electrical link that provides connection and data exchange between two (or more) devices such as a frequency synthesizer and host controller. There is a large variety of interfaces and data-exchange formats used in frequency synthesizers; the most popular ones are described next. 1.4.1

Parallel Interface

The parallel interface assumes transmitting and receiving control signals over multiple wires at one time. The number of wires heavily depends on the number of functions to be controlled. To illustrate this, let’s come back to the hypothetically simplest dual-frequency synthesizer example shown in Figure 1.3. Only a single control line is required to switch between two frequencies. If we need more output frequencies, more switches and more control lines must be added. Using a binary code, we can control as many as 2n frequencies, where n is the number of control lines (in addition to a ground connection). Alternatively, we can use a binary-coded decimal (BCD) control that is more convenient to set a frequency with decimal digits but requires a higher number of control lines. Besides setting the frequency, we may also need to control output power and other synthesizer functions that require even more control lines. Furthermore, the interface can also include some extra auxiliary signals such as a lock indicator, trigger, and so forth. Hence, the number of control wires grows with the design complexity. The main advantage of the parallel interface is high communication speed since all control signals are sent simultaneously. While data transmission in parallel is very fast, it usually requires a lot of control lines, bulky connectors on


17

both sides, and a complex, multiwire connecting cable. Nevertheless, the parallel interface can be a good choice in fast-switching designs such as direct analog synthesizers. 1.4.2

SPI

Serial peripheral interface (SPI) is a synchronous serial data link introduced by Motorola, Inc., that offers full duplex communication, relatively high throughput, and flexibility. The idea behind the SPI is to send controlling bits one by one rather than altogether via a single line. Another line is added to receive some information from the device under control. In order to synchronize the data streams, an auxiliary synchronization signal (such as clock pulses) is needed. Finally, we may want to control not one but several devices via the same wires. This is accomplished using an additional auxiliary line that allows the selection of a particular device. Thus, a multidevice, full-duplex interface can be physically constructed with four signal lines as shown in Figure 1.19. The controlling device is called master, and the device under control is called slave. The control lines are asserted to carry the following functions: SCLK

SCLK

MOSI MISO

MOSI MISO

SS

SS

Master

Slave 1

SCLK MOSI MISO SS Slave 2

SCLK MOSI MISO SS Slave N

Figure 1.19 The SPI interface offers full-duplex communication with multiple devices using four signal lines.

18


• Serial clock (SCLK) is used for synchronization of data streams. • Master output, slave input (MOSI) is used to stream data from the master device to the slave. • Master input, slave output (MISO) is used to stream data from the slave device to the master. • Slave select (SS) is used to select a particular slave device. The communication is initiated by the master that sets the SS signal low for a desired slave device (Figure 1.20). If only a single slave device is used in the system, the SS signal is not necessarily required and in many cases may be set to ground. With multiple slave devices, however, an independent SS signal is required from the master for each slave device; thus, only one slave may be chosen at a time. After selecting a slave, the master starts streaming the data through the MOSI line, simultaneously providing clock pulses on the SCLK line. The SCLK is aligned with MOSI in such a way that the slave device processes the data bit by bit with every clock pulse. Other slave devices that have not been chosen disregard the SCLK and MOSI signals. Besides, they must not drive the common MISO line. Most slave devices have an internal switch that disconnects or puts into a high-impedance state their MISO output when the device is not selected, thus allowing multiple devices to share the same line. To better understand the communication process, let’s consider the slave device input as a shift register, which is essentially a cascade of flip-flops, sharing the same clock as shown in Figure 1.21. A signal on the register’s data input line

SS

SCLK

MOSI

MISO

Figure 1.20

SPI communication timing diagram.

Parameters and Architectures DATA IN

CLOCK

D

19

Q

Q0

Q

Q1

Q

QN

CLK

D

CLK

D

CLK

Figure 1.21

A shift register allows converting a serial data stream into a parallel format.

is transferred to the first flip-flop output on the rising (or falling) edge of the clock signal. With the second clock pulse, this signal is further transferred to the output of the second flip-flop, and so forth. Thus, the series of data bits is shifted down and appears on the corresponding flip-flop outputs. In other words, the register converts an input data stream from serial to parallel format. Similarly, a parallel controlling word on the transmitter side can be converted to a serial format and delivered to the receiving device with a minimal number of physical connections between the devices. Although the concept seems straightforward, a number of SPI modifications exist because of the lack of a strict standard. Each device is described by its own specifications including maximum clock rate, timing characteristics, number of bits and their definitions, and polarity of control signals. Moreover, the MOSI and MISO signals are sometimes combined together into a common data line. The MISO signal is often omitted entirely, which allows programming the slave device but not reading information from it. This SPI modification is called “3-Wire” in contrast to the normal four-wire arrangement and is widely used in PLL synthesizer chips. Overall, the SPI interface is extensively used in both IC and module-level synthesizer designs to allow small packages and highly integrated functionality.

20

1.4.3


I2C

The I2C interface was introduced by Philips Semiconductors in the early 1980s. The name I2C translates into “Inter IC,” since the idea was to allow easy communication between components residing on the same circuit board. Currently I2C is not only used within a single board, but also used to connect separate devices using a cable. Each device connected to the bus is software addressable by a unique address. I2C is a multimaster bus, meaning that multiple masters can initiate data transfer over the shared bus. The main advantage of the I2C interface is its simplicity. Only two bidirectional lines (serial data and serial clock) are required for communication. Disadvantages include relatively low communication speeds and the lack of automatic bus configuration. 1.4.4

RS-232

RS-232 is another serial interface that is widely used in computer serial ports. The standard was introduced by the Electrical Industries Association and evolved from serving electromechanical teletypewriters to modern electronic devices and personal computers. While the standard recommends a 25-pin connector, a three-wire arrangement is often used when the full capabilities of RS-232 are not required. In the latter case, communication is established via the transmit data, receive data, and ground pins. RS-232 can be a good choice if the synthesizer needs to be controlled from a personal computer. Its main disadvantage is relatively low speed. As a result, it is being replaced by much faster USB and Ethernet connections. 1.4.5

USB

Universal serial bus (USB) is today’s most popular way of connecting various devices to a personal computer. Compared to RS-232, USB is faster, smaller, and simpler to use. The current USB version 2.0 provides up to 480 Mbit/second of data transfer and will be replaced with an even faster USB 3.0 rated to 5 Gbit/ second. USB also supports plug-and-play connectivity, meaning that devices are detected by the computer’s operating system and configured automatically as soon as they are attached. USB cables can be up to 30 meters long and can also be used to bias relatively low-power devices. These features make USB a very desirable option in the design of frequency synthesizer modules since it allows instant deployment or simply evaluation of a synthesizer using a personal computer as illustrated in Figure 1.22.


21

Figure 1.22 A USB interface allows instant deployment and evaluation of frequency synthesizer modules. (Courtesy of Phase Matrix, Inc.)

1.4.6

GPIB

General Purpose Interface Bus (GPIB) is a special interface for test-and-measurement applications. It was originally introduced by Hewlett Packard (now Agilent Technologies, Inc.) as an HPIB bus to control measurement instruments. In 1975, the interface was standardized by the Institute of Electrical and Electronics Engineers (IEEE) under the IEEE-488 standard. The GPIB bus has 24 lines: eight signal lines used for data transfer, three lines for handshake, five lines for bus management, and eight lines for ground returns. It allows the connection of multiple off-the-shelf instruments into a complex automated test system (ATE). 1.4.7

VXI

VXI stands for VME Extensions for Instrumentation and is an interface that was introduced in the mid-1980s as an open system platform for synthetic instrumentation. One of the principles behind synthetic instrumentation in general, and VXI in particular, is to offer a cost-efficient modular approach for building complex test-and-measurement equipment. It enables the emulation of various traditional bench-top instruments employed in automatic test systems using a reconfigurable combination of core hardware modules. A VXI instrument includes a chassis (also called mainframe) that contains several spaces (slots) where individual VXI modules can be placed. The mainframe also contains all necessary DC power supplies and provides communication between individual components and a host controller that is usually an external computer. A VXI module (such as a signal generator shown in Figure 1.23) fits into one or more slots in the chassis and connects through a VXI bus

22


Figure 1.23 A VXI signal generator covers the 0.01- to 20-GHz frequency range. (Courtesy of Phase Matrix, Inc.)

that delivers all necessary control and bias lines. The VXI specifications are governed by the VXI Bus Consortium, which was founded in 1987 by a group of interested companies to define mechanical, electrical, and software features of VXI instrumentation. 1.4.8

PXI

PXI stands for PCI Extensions for Instrumentation and is a further enhancement of the synthetic instrumentation concept (PCI stands for peripheral component interconnect). The PXI standard was introduced by National Instruments Corporation in 1997 and is currently governed by the PXI Systems Alliance (PXISA). The alliance includes more than 50 companies chartered to promote the standard, ensure interoperability, and maintain PXI specifications. Similar to VXI, a typical PXI instrument is built using a PXI chassis and a number of individual modules that fit into PXI slots (as shown in Figure 1.24). However, the size of the chassis and the modules is significantly smaller; a typical PXI module measures approximately 4 by 6 inches in dimensions. Moreover, the host computer can be built as a PXI component and plugged into the chassis.


23

Figure 1.24 A 3- to 9-GHz local oscillator module available in PXI form. (Courtesy of Phase Matrix, Inc.)

Therefore, a whole instrument or even an ATE system can be completed within a single PXI frame. Another distinct advantage is higher communication speed compared to the VXI environment. It should be noted that the PXI chassis backplane uses essentially the same PCI bus used in personal computers. Thus, the development and operation of PXI systems are not much different from that of standard Windows-based applications. A newer PXI Express standard (released in 2005) further increases the available PXI bandwidth by taking advantage of PCI Express technology. Users benefit from significantly increased bandwidth, ensured backward compatibility, and additional timing and synchronization features. 1.4.9

LXI

LXI stands for LAN Extensions for Instrumentation and is another interface for test-and-measurement applications (LAN stands for local area network). It was introduced in 2004 by Agilent Technologies, Inc., and is currently maintained by the LXI Consortium. The LXI concept offers integration advantages of modular instruments without the constraints of card-cage architectures. It is

24


based on a well-established Ethernet protocol that allows connecting individual instruments into a network. LXI can be used at any level of network complexity ranging from a single component and a controlling computer to complex multiinstrument systems operated remotely through the Internet. The LXI standard defines three classes of instruments. The base class C incorporates a Web browser via an Ethernet port as well as an interchangeable virtual instrument (IVI) driver. Class B brings synchronization capability via the IEEE 1588 precision time protocol and also supports peer-to-peer messaging. The IEEE 1588 protocol synchronizes clocks in multiple devices to ensure proper event time stamping and execution of synchronized events. Finally, Class A adds a fast hardware trigger bus, which offers lower-latency synchronization compared to the Class B. 1.4.10 AXIe

AXIe (Advanced TCA Extensions for Instrumentation and test) is a recent addition to the synthetic instrumentation interfaces that supports both PXI and LXI standards (TCA stands for Telecommunications Computing Architecture). It is governed by the AXIe Consortium that was formed in 2009 by Agilent Technologies, Inc., Aeroflex Corporation, and Test Evolution Corporation. AXIe addresses a wide range of ATE systems, rack-and-stack modular, bench-top, and module plug-ins. It offers higher performance per rack inch, greater scalability, more flexibility, and easy integration with various platforms.

1.5 Main Architectures The RF and microwave industry feels constant pressure to deliver higher performance, higher functionality, smaller size, lower power consumption, and lower-cost synthesizer designs. What parameters are the most important? Is there an “ideal” synthesizer design or architecture? Although all synthesizers exhibit significant differences as a result of specific applications, they share basic fundamental design objectives as depicted in Figure 1.25. The ideal synthesizer should be broadband with fine frequency resolution that allows addressing a larger number of potential applications. Aside from frequency coverage and resolution, phase noise and spurs are critical parameters that impose the ultimate limit in the system’s ability to resolve signals of small amplitude. Another key parameter of the synthesizer that impacts overall system performance is frequency switching speed. The time spent by the synthesizer transitioning between frequencies becomes increasingly valuable since it cannot be used for data processing. Modern synthesizers tend to be faster due to the ongoing increase of the data rates of RF and microwave systems. Another challenge is cost reduction. Although it is considered to be a universal, standard requirement, cost reduction drastically


25

Speed

Spurs

Noise Cost

Coverage

Figure 1.25

Step Size

Synthesizer design challenges.

narrows the designer’s choice since it determines the types of designs that can be utilized. These requirements—wide frequency coverage, small step size, fast switching speed, adequate spectral purity, and low cost—are the key drivers in the development of frequency synthesizers. Synthesizer characteristics depend heavily on a particular architecture. While reviewing traditional frequency synthesizer schemes, we specifically address the technology trend toward increasing the synthesizer tuning speed, improving the spectral purity as well as reducing its complexity and cost. The main architectures along with their characteristics and trade-offs are described next. 1.5.1

Direct Analog Synthesizers

The direct analog synthesizer is one of the most powerful techniques offering excellent switching speed and phase noise performance [3–7]. As the name suggests, the desired signal is created directly (i.e., without regeneration) by mixing base frequencies followed by switched filters as conceptually shown in Figure 1.26. The base frequencies can be obtained from low-frequency (e.g., crystal, SAW) or high-frequency (e.g., CRO, DRO, metal cavity, and sapphire resonator) oscillators by frequency multiplication, division, and/or mixing. The key advantage of the direct analog technique is extremely fast switching speed, ranging from microseconds to nanoseconds. Since direct analog synthesis assumes no closed loops, switching speed is only limited by propagation delays inserted by the switches and their control circuits as well as filter settling. Another distinct advantage is the ability to generate low phase noise due to usage of components with negligibly low residual noise compared to the base frequency sources. Hence, the direct analog synthesizer phase noise mainly depends on the noise of the available fixed-frequency sources and can potentially be very low. The main disadvantage of the indicated topology is limited frequency coverage and step size. In our example, only 18 output frequencies can be generated (even

26


F1 F2 F3

F4 F5 F6

Figure 1.26

Direct analog synthesizer concept.

by utilizing both mixer sidebands). Naturally, this is not enough for a practical design. The number of output frequencies can be increased by using a higher number of base frequencies and/or mixer stages as depicted in Figure 1.27. However, this rapidly increases the design complexity and overall component count. An effective solution is to use a direct digital synthesizer module (Figure 1.28) to increase the minimum step size requirements for the direct analog portion. The frequency resolution can also be improved by repeatedly mixing and dividing the base frequencies as conceptually shown in Figure 1.29. The synthesizer contains a chain of frequency mixer-divider cells that transform an input frequency fi to fi f f f = f 0 + 1 + 22 +  + i i i N N N N i =0

f OUT = ∑

(1.16)

where fi is a frequency driving the corresponding mixer and N is the division coefficient of the utilized frequency dividers. Using proper fixed frequencies and a sufficient number of individual cells, an arbitrarily small step size can be achieved. In general, the frequency division coefficients can also be arbitrary; however, N = 10 is the most commonly used scenario that leads to

f OUT = f 0 +

f1 f f + 2 +  + ii 10 100 10

(1.17)

Figure 1.27

A1

A2

A3

AX

Direct analog synthesizer with extended frequency coverage.

FN

F3

F2

F1

B1

B2

B3

BY

Parameters and Architectures 27

Figure 1.28

A1

A2

A3

AX

Using a DDS module for better frequency resolution.

DDS

B1

B2

B3

BY

28 Frequency Synthesizers: Concept to Product


29

÷N

fi

÷N

f1

f OUT

÷N

f0

Figure 1.29

Reducing step size by repeatedly mixing and dividing the base frequencies.

The frequencies fi are usually generated from a common reference F0 by utilizing its harmonics F0, 2F0, 3F0, …, 9F0 as shown in Figure 1.30 and can be presented by f i = Ai F0

(1.18)

where Ai is an integer between 1 and 9 that allows rewriting (1.17) to A ⎞ A A ⎛ f OUT = F0 ⎜ A0 + 1 + 2 +  + ii ⎟ ⎝ 10 100 10 ⎠

(1.19)

The decimal coefficients Ai in this formula simply show what harmonic is chosen. Furthermore, the individual mixer-divider cells can be bypassed as depicted in Figure 1.31, which mathematically corresponds to fi = 0 or Ai = 0. Therefore, the output frequency is conveniently represented in a decimal form by setting corresponding digits. Similarly, the synthesizer can be constructed using different frequency division coefficients to represent its output frequency in a binary or any other desired form, or a combination thereof. Moreover, there are numerous further modifications to this scheme that allow simplifying

30

Frequency Synthesizers: Concept to Product Harmonic Generator

F0 F0

X

2F0 3F0

9F0

Figure 1.30

All necessary frequencies are generated from a common reference.

Figure 1.31

An additional through path simplifies frequency setting.

the synthesizer design or improving its technical characteristics. Every design is unique since it is governed by specific requirements as well as available components and their cost. Thus, the designer’s experience and intuition are probably the most important factors in the synthesizer development equation. A serious problem associated with direct analog synthesis is the large amount of mixing products that have to be filtered. These include the undesired mixer sideband, LO leakage, and intermodulation products. Depending on a particular frequency plan, filtering close-in spurs can be a challenging task. Another serious issue is crosscoupling between individual filter channels and whole cascades. Switch isolation is one of the critical parameters that directly affect the synthesizer’s spurious characteristics. Special attention should also be paid to the synthesizer layout and isolation between its individual blocks. These are nontrivial considerations requiring certain design effort and careful frequency planning. Although a large variety of mixing and filtering organization schemes are possible, they tend to be hardware-intensive if a small frequency step and wide coverage are required. Therefore, while direct analog synthesis offers excellent tuning speed and phase-noise characteristics, its usage is limited to applications where fairly high cost can be tolerated. This includes radars, frequency hopping


31

and antijam communications, high-throughput ATE, medical imaging systems, and other applications that demand speed. 1.5.2

Direct Digital Synthesizers

In contrast to traditional analog concepts, direct digital synthesizers utilize digital signal processing (DSP) to construct an output signal waveform in the time domain piece by piece from a base (clock) signal [3–5, 8]. Although it may seem complex, the concept is fairly simple. To illustrate this, let’s take a shift register and inject a single, logic-high pulse into its input. With every clock cycle, this logic-high signal will travel through the register outputs from top to bottom. Let’s also connect resistors to these outputs to form voltage dividers as shown in Figure 1.32. The voltage at the divider output changes with every clock pulse in accordance with the chosen resistor values. We can adjust the values in such a manner that the voltage steps approximate a desired signal waveform, for example, a sine wave. The synthesized waveform looks “ugly,” meaning that it has a highly contaminated spectrum in the frequency domain. We can slightly improve it by adding a capacitor that smoothes the edges of the voltage steps; however, the signal is still far from perfect. What can be done to improve our simple digital synthesizer? First, we can increase the length of the shift register and use a higher clock frequency to approximate the sine wave in smaller steps. Second, we can use a specialized digital-to-analog converter (DAC) that generates a much more precise voltage than the simple resistor divider, thus, making the output signal closer to the desired waveform. In this case, we need to add some kind of a decoder between the shift register outputs and the DAC address bus to generate proper voltages. This can be easily accomplished with a memory chip. Furthermore, instead of a smoothing capacitor we can use a high-rejection lowpass filter (LPF) to clean up

DATA IN

D

Q0 Q1 Q3

CLOCK

CLK QN

Figure 1.32 A shift register creates voltage steps that approximate a desired signal waveform.

32


the spectrum of the synthesized signal. Another consideration is how to change the output frequency. Of course, it can be changed by simply varying the input clock frequency. However, this method defeats the whole purpose of frequency synthesis, that is, synthesizing many desired (not fixed) frequencies from an available single fixed-frequency reference. Note that we can change the output frequency by using a smaller (or larger) number of voltage steps within the fixed length defined by the register capacity. In other words, the output frequency can be changed by manipulating the number of register bits or their connections. Keeping all these ideas in mind, we can intuitively come to an improved block diagram depicted in Figure 1.33, which is not too different from what is used in real DDS designs. The direct digital synthesizer consists of four main blocks: a phase accumulator, digital look-up table, DAC, and LPF. The phase accumulator is essentially a more sophisticated version of the shift register used in our example. Instead of injecting a single pulse, it allows entering a digital word (code) called phase increment. At each clock pulse the phase accumulator adds (accumulates) the increment to the previously stored digital value that represents an instantaneous digital phase of the generated signal. This digital phase is continually updated until it reaches the capacity of the accumulator. For an N-bit accumulator and the smallest increment of one least significant bit, it will take 2N clock cycles to fill up the accumulator. Then the accumulator resets and the process starts over again. Hence, the lowest generated frequency is given by

f MIN =

f CLK 2N

(1.20)

that also equals the smallest frequency step. With a larger phase increment W, the phase accumulator obviously fills up faster and the DDS output frequency increases to

fCLK

Phase accumulator

Look-up table

f OUT

DAC

Tuning word Figure 1.33

A direct digital synthesizer block diagram.

LPF

Parameters and Architectures f DDS =

W f CLK 2N

33

(1.21)

Therefore, frequency tuning is accomplished by changing the phase increment word. This word defines the DDS output frequency and can be loaded into the accumulator through either a serial or parallel interface. The tuning process has essentially no settling time delays other than what is inserted by the digital interface. The frequency can be changed in very small steps determined by the length of the phase accumulator. For example, assuming that fCLK is 100 MHz and N = 32, we can calculate fMIN to approximately 0.023 Hz. The length of the phase accumulator can be further increased; thus, millihertz or even microhertz steps are easily achievable. The next step is to convert the digital phase value into a digital representation of the signal waveform. This is accomplished with a look-up table. It uses a read-only memory (ROM) to store a digital code that sets a proper address on the DAC’s bus and, consequently, its output voltage. In general, any desired waveform can be created; however, the sine wave is most commonly used. The waveform construction process completes with a lowpass filter required to remove some unwanted spurious components because of the imperfect approximation of the desired waveform. Practical realization of this concept brings further modifications. For example, the length of the phase accumulator, required to achieve the necessary resolution, can exceed practical limits for ROM and DAC devices. Due to the sine function’s symmetry, only one-fourth of the cycle needs to be stored, thus greatly reducing the required memory capacity. Furthermore, the DAC usually utilizes a smaller number of bits available from the phase accumulator. This may seem confusing. How can a 32-bit phase accumulator work with, let’s say, a 12bit DAC? Interestingly, the DAC may use only one (most significant) bit of the phase accumulator. In this case, it produces a signal of rectangular shape; however, the frequency is still set with the same 32-bit resolution. By adding DAC bits, the sine-wave function is better approximated, thus resulting in a cleaner output. This reduction in DAC resolution is called phase truncation and leads to increased spurious levels. The DDS output contains a number of spurious signals (Figure 1.34) as a result of truncation, amplitude quantization, and DAC nonlinearities. However, the most significant ones are aliased images of the output signal that appear on either side of the clock frequency and its multiples because of the sampling nature of digital signal synthesis. From this point of view, the DDS works as a frequency mixer producing spurs at f SPUR = ±n f CLK ± m f DDS

(1.22)

34

Frequency Synthesizers: Concept to Product DDS Spurs dBm 147 MHz 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100

Figure 1.34

Start: 10.0000 Hz

Stop: 200.0000 MHz

An output spectrum of a direct digital synthesizer.

where n and m are integers. Similar to mixer intermodulation products, these spurs require careful frequency planning since they can be very close to the output signal and, therefore, cannot be filtered. While spur location in the frequency domain can be easily determined, its amplitude is much less predictable. As a general rule, lower-order spurs are the strongest, although fairly high-order spurs can still be harmful and must be taken into account. Typical DDS spurious levels are −50 to −60 dBc for output signal ranges between a few tens to a few hundreds of megahertz. The DDS also provides reasonably low phase noise levels, even showing an improvement over the phase noise of the clock source itself. From the phase noise point of view, the DDS works as a fractional frequency divider with a very fine, variable, frequency division coefficient. Similar to dividers, the noise improvement is described by 20log(FCLK/FDDS ) function and is limited by the residual noise floor. The DDS is currently available as a tiny, yet highly integrated, surfacemount IC that includes the phase accumulator, look-up table, and DAC in a single chip. It needs only a few external components (LPF and bias circuitry) to build a powerful and versatile module. The most valuable DDS feature is its exceptionally fine frequency resolution and fast switching speed comparable to direct analog schemes. The main disadvantages are limited usable bandwidth and relatively poor spurious performance. While a DDS starts working from nearly DC, its highest frequency is limited within one half of the clock frequency according to the sampling theory. It is theoretically possible to use DDS aliased images above the one half of the clock limit; however, the spurious content is


35

further degraded. As a rule of thumb, the usable DDS bandwidth is limited to about 40% of the clock signal by practical LPF design considerations. Typical clock speeds for today’s commercial DDS ICs are in the range of a few hundred megahertz to a few gigahertz. The DDS technique is widely used to generate arbitrary waveforms at RF frequencies. However, it rarely works alone at microwave frequencies because of the mentioned bandwidth and spurious limitations. Rather DDS is used as a fine-frequency-resolution block in conjunction with direct analog and indirect architectures. Moreover, it is often accompanied by spur-reduction circuits that control spurious emission. These techniques will be further discussed in Chapter 5. Overall, direct digital synthesizers have a tremendous potential for future growth as a result of exceedingly rapid developments in solid-state devices. The extension of DDS usable bandwidth (together with its spurious content reduction) is the key improvement required by industry. 1.5.3

Indirect Synthesizers

Indirect frequency synthesizers use an additional high-frequency oscillator to generate an output signal that is in a certain relationship with the reference signal. Indirect synthesizers are commonly associated with phase-lock-loop techniques, which are extensively used in RF and microwave systems. A typical single-loop PLL synthesizer includes a tunable VCO that generates a signal in a desired frequency range. This signal is fed back to a phase detector through a frequency divider with a variable frequency division ratio N as depicted in Figure 1.35. The other input of the phase detector is a reference signal equal to a desirable step size. The phase detector compares the signals at both inputs and generates an error voltage, which, following filtering and optional amplification, slews the VCO until it acquires the lock frequency given by f OUT = N f PD

f REF

÷R

f PD

LPF

f OUT /N ÷N

Figure 1.35

A PLL synthesizer block diagram.

(1.23)

VCO

f OUT

36


where fPD is the comparison frequency at the phase detector inputs. The frequency tuning is achieved in discrete frequency steps equal to fPD by changing the division coefficient N. The available reference frequency can be divided down by another divider to reduce the step size. If the division coefficient of the reference divider is R, then the output frequency is set by

f OUT =

N f REF R

(1.24)

Although the phase-lock-loop block diagram appears fairly straightforward, its rigorous analysis is not so simple. The PLL is a nonlinear, closed-loop feedback system and is usually analyzed using the Laplace transform as extensively covered in [9–19]. Fortunately, there are a number of programs that can simulate and even synthesize a PLL circuit with desired characteristics. Hence, engineering effort reduces to formulating design goals that require a clear understanding of PLL limitations and trade-offs. A step-by-step review of the design sequence for a simple single-loop PLL example is given in Chapter 4. How does a PLL behave compared to direct analog and direct digital synthesizers? Since the output signal of the PLL synthesizer is generated at microwave frequencies, all spurs associated with the direct architectures are generally absent. The only source of the spurs in the PLL block diagram shown in Figure 1.35 is the reference signal itself. The reference signal and its harmonics modulate the VCO tuning port and create sidebands both above and below the main signal. The loop filter bandwidth has to be significantly lower than fPD (usually 10 times or more) to keep the reference spurs at a reasonable level. However, the loop bandwidth is inversely proportional to the settling time. Thus, achieving fine frequency resolution, low spurs, and fast switching is an arduous task as it means balancing mutually exclusive terms. Another important consideration and design trade-off is phase noise. The noise outside the PLL filter bandwidth is mainly determined by the VCO’s freerunning noise. The phase noise within the loop filter bandwidth is given by PLL = ΣPD + 20 log N

(1.25)

where ΣPD is the cumulative phase noise of the reference signal, reference and feedback dividers, phase detector, LPF, and loop amplifier recalculated to the phase detector input (Figure 1.36). In other words, the phase noise generated by PLL components is degraded by large division ratios required to provide a high-frequency output with a fine resolution. Moreover, programmable dividers are usually not available at high frequencies; thus, an additional, fixed-divisioncoefficient divider (called a prescaler) is required. In this case, the total division


37 VCO

REF

÷R

VCO

LPF

OUT

÷N

+ 20 log N ΣPD

Figure 1.36

PLL noise sources.

ratio will increase by the prescaler division coefficient resulting in further phase noise degradation. At high frequency offsets, the VCO’s free-running noise can be (and normally is) better than the multiplied PLL noise. The optimal phase noise profile is achieved by choosing the loop bandwidth at the cross point of the multiplied PLL noise and VCO free running noise curves as depicted in Figure 1.37. Clearly, by utilizing a low-noise VCO and narrower loop bandwidth, it is possible to mask some excessive PLL noise at high frequency offsets. However, VCO

OUT

PLL

20 log N ΣPD

Frequency offset

Figure 1.37

PLL synthesizer output phase noise.

38


this results in slower switching speed. Alternatively, a good PLL design can suppress VCO noise at higher frequency offsets and also provide faster tuning. Overall, the major advantages of the PLL schemes are reduced levels of spurious signals resulting from the lowpass filter action of the loop and much lower level of complexity compared to the direct analog architectures. In fact, all key PLL components can be integrated into a single chip that leads to low-cost, miniature designs. The main disadvantages are slower tuning, limited step size, and considerably higher phase noise. The PLL synthesizer’s characteristics can be improved by a number of techniques (such as fractional-N or frequency conversion within a feedback path), as will be further discussed in Chapter 5.

References [1] Stone, R. R., Jr., “Frequency Synthesizers,” Proc. 21st Annual Symposium on Frequency Control, April 1967, pp. 294–307. [2] Kroupa, V. F., Frequency Synthesis: Theory, Design and Applications, New York: John Wiley & Sons, 1973. [3] Manassewitsch, V., Frequency Synthesizers: Theory and Design, 3rd ed., New York: John Wiley & Sons, 2005. [4] Reinhardt, V., et al., “A Short Survey of Frequency Synthesizer Techniques,” Proc. 40th Annual Symposium on Frequency Control, May 1986, pp. 355–365. [5] Galani, Z., and R. A. Campbell, “An Overview of Frequency Synthesizers for Radars,” IEEE Transactions on Microwave Theory and Techniques, Vol. 39, No. 5, May 1991, pp. 782–790. [6] Chenakin, A., “Frequency Synthesis: Current Solutions and New Trends,” Microwave Journal, May 2007, pp. 256–266. [7] Karlquist, R. K., “A 3 to 30 MHz High-Resolution Synthesizer Consisting of a DDS, Divide-and-Mix Modules, and a M/N Synthesizer,” IEEE Int. Frequency Control Symposium Proc., June 1996, pp. 928–933. [8] Kroupa V. F., (ed.), Direct Digital Frequency Synthesizers, New York: IEEE Press, 1999. [9] Gardner, F. M., Phaselock Techniques, 3rd ed., New York: John Wiley & Sons, 2005. [10] Egan, W. F., Phase-Lock Basics, 2nd ed., New York: John Wiley & Sons, 2007. [11] Egan, W. F., Frequency Synthesis by Phase Lock, 2nd ed., New York: John Wiley & Sons, 1999. [12] Best, R. E., Phase-Locked Loops: Theory, Design, and Applications, New York: McGraw-Hill, 1984. [13] Rohde U. L., Digital PLL Frequency Synthesizers: Theory and Design, Upper Saddle River, NJ: Prentice-Hall, 1983. [14] Rohde, U. L., Microwave and Wireless Synthesizers: Theory and Design, New York: John Wiley & Sons, 1997.


39

[15] Klapper, J., and J. T. Frankle, Phase-Locked and Frequency-Feedback Systems, New York: Academic Press, 1972. [16] Crawford, J. A., Frequency Synthesizer Design Handbook, Norwood, MA: Artech House, 1994. [17] Crawford, J. A., Advanced Phase-Lock Techniques, Norwood, MA: Artech House, 2008. [18] Kroupa, V. F., Phase Lock Loops and Frequency Synthesis, New York: John Wiley & Sons, 2003. [19] Goldman, S. J., Phase-Locked Loop Engineering Handbook for Integrated Circuits, Norwood, MA: Artech House, 2007.

2 Building Blocks As discussed in Chapter 1, the frequency synthesizer can be thought of as a black box containing the necessary components to translate an input reference signal to a number of output frequencies. The synthesizer’s performance depends heavily on characteristics of individual components used in the design. This chapter continues with a review of key building blocks from the perspective of their practical use in microwave frequency synthesizers. The main focus is on how undesired signals (spurs, phase noise) are generated and then propagate through synthesizer components. Oscillators, frequency multipliers, dividers, mixers, phase detectors, and complex integrated circuits will be discussed.

2.1 Oscillators An oscillator is an electronic device that generates a repetitive electronic signal such as a sine wave. Oscillators are used extensively in many electronic instruments; hence, their parameters and design techniques are well covered in many sources, including [1–50]. Frequency coverage, tuning sensitivity, frequency stability, and output power are important characteristics for a synthesizer designer. However, oscillator phase noise is probably the most important figure of merit since it defines the ultimate performance of a frequency synthesizer. This section briefly summarizes the research and development effort in the area of low-noise signal generation. It discusses a general noise generation mechanism, the influence of individual elements on phase noise behavior as well as various noisereduction techniques.

41

42

2.1.1


Phase Noise in Microwave Oscillators

An oscillator can be looked at as either a feedback or negative resistance circuit. A typical feedback microwave oscillator, shown in Figure 2.1, consists of a passive frequency-determining resonant element and an active device required to compensate for the resonator loss in order to start oscillations. The oscillations are initiated due to small, noisy signal fluctuations occurring in the oscillator components. The active device’s small-signal gain has to be greater than the resonator loss to result in a rapid increase of the output signal. Naturally, some kind of limiting mechanism (such as gain compression) is required to stabilize the output power at a certain level. The gain compression usually occurs in the active device itself because of its natural nonlinear behavior. Thus, at steady state, the gain of the active device becomes equal to the overall loss in the resonator-feedback path that stabilizes the output signal amplitude. The oscillation frequency is determined by the resonator frequency selectivity and phase relationship in the oscillator-feedback path. Therefore, two essential requirements are necessary to realize an oscillator: • Noisy signal fluctuations in oscillator components are required to initiate oscillations. • A limiting, nonlinear mechanism is required to achieve steady-state oscillations. Unfortunately, these vital features of the microwave oscillator eventually result in output spectrum contamination either directly (due to the active device RF noise or resonant-frequency fluctuations) or indirectly (due to the upconversion of the active device’s low-frequency noise in its nonlinearities). In general, oscillator phase noise can be approximated by

Resonator Q

f0 , P G, F

Active device Figure 2.1

Feedback oscillator block diagram.

Building Blocks =∑ n

an a a a = a 0 + 1 + 22 +  + nn fn f f f

43

(2.1)

where f is the offset frequency from the carrier and an are coefficients that define the noise shape for a particular oscillator circuit. In practice, higher-order terms are ignored since they appear at very low frequency offsets (below 1 Hz) and the oscillator noise behavior is usually represented as

⎧⎪GFkT ≈ 10 log ⎨ ⎪⎩ 2P

⎡⎛ f 0 ⎞ 2 f c ⎛ f 0 ⎞ 2 1 ⎤ ⎫⎪ f × 3 +⎜ × 2 + c + 1⎥ ⎬ ⎢⎜ ⎟ ⎟ f f f ⎝ 2Q ⎠ ⎢⎣⎝ 2Q ⎠ ⎥⎦ ⎪⎭

(2.2)

where G = active device gain F = active device noise factor k = Boltzmann’s constant T = absolute temperature P = RF power applied to the resonator Q = resonator loaded Q-factor f0 = oscillation frequency fc = active device flicker-corner frequency f = offset frequency This expression is a well-known modification of Leeson’s equation [3–6] that depicts the oscillator phase noise behavior in the offset frequency domain. Although the formula defines four basic frequency offset regions, in microwave oscillators the 1/f term is further ignored because of the 1/f 2 noise domination. This leads to the “classical” microwave oscillator phase noise profile shown in Figure 2.2. For offset frequencies higher than the resonator half bandwidth f0/2Q, phase noise is mainly determined by the available RF power level and the active device thermal noise. This region shows a nearly flat response called noise floor. For frequencies between the half bandwidth and flicker-corner frequency fc, phase noise increases at a 20 dB per decade rate. In the last region, where the flicker noise dominates, the phase noise increases at 30 dB per decade. Thus, two important oscillator parameters, namely the resonator half bandwidth f0/2Q and flicker-corner frequency fc, define the shape of the phase noise curve while its magnitude is mainly determined by the GFkT/2P term.

44

Frequency Synthesizers: Concept to Product Phase noise fc , f 0 / 2Q 30 dB/decade

20 dB/decade Noise floor

fc

Figure 2.2

f 0 / 2Q

Frequency offset

Phase noise behavior of a microwave oscillator.

The graph in Figure 2.2 gives a simplified yet very helpful visualization of the phase noise behavior as well as some intuitive ideas on how to reduce its appearance in the oscillator output spectrum. The phase noise can be controlled by reducing the flicker-corner frequency fc and/or the resonator half bandwidth f0/2Q as shown. The flicker-corner frequency is mainly determined by a particular active device and its operating regime while the half bandwidth is set by the frequency resonator and its coupling scheme. Clearly, utilizing low-flicker-noise devices (such as silicon bipolar transistors) and applying a high-Q frequency resonator technology are effective and commonly used ways of cleaning up the oscillator output spectrum. Alternatively, the entire noise curve can be shifted down, as shown in Figure 2.3, by increasing the oscillator signal-to-thermal noise ratio. This can be achieved practically by maintaining a higher power level in front of the resonator and/or reducing the active device noise factor while setting the active device gain to its optimum value (determined by the resonator coupling as will be discussed later). Thus, extracting a higher power from the active device provides a considerable effect—the entire phase noise curve is shifted down, decibel for decibel. However, the output power increase should be implemented very carefully since severe phase noise degradation can occur because of the active device noise elevation at compression. It is preferable to operate the active device in a small-signal, “linear” regime in order to keep its noise characteristics unaffected. This may seem confusing since in order to get steady-state oscillations, a limiting mechanism is required (i.e., something has to be nonlinear). However, “something” does not necessarily mean the active device itself. The limiting mechanism can be effectively spread through oscillator components or even moved from the active device to a less critical (from the noise generation point of view) component. In a more general sense, the main idea here is to reduce the influence of oscillator

Building Blocks

45

Phase noise GFkT 2P

30 dB/decade

20 dB/decade Noise Floor

fc

Figure 2.3

f 0 /2Q

Frequency offset

Another method for phase noise reduction.

nonlinearities on the phase noise generation process that can be achieved with a variety of linearization and noise suppression techniques. In summary, the key principles in designing low-noise microwave oscillators are as follows: • Reducing the oscillator half bandwidth frequency by utilizing a high-Q resonator and optimum coupling scheme; • Reducing the flicker-corner frequency by choosing an appropriate active device and its operating regime; • Increasing the oscillator signal-to-thermal noise ratio by choosing an active device with a low noise figure and maintaining high signal level in front of the resonator; • Preventing the active device noise elevation by optimizing the oscillationlimiting mechanism as well as applying active device linearization and noise-reduction techniques. 2.1.2

Resonators

The frequency resonator element has considerable impact on oscillator phase noise and tuning characteristics. Modern microwave oscillators utilize various resonator technologies, based on electromagnetic, electro-acoustic, and electrooptical principles. 2.1.2.1 Electromagnetic Fixed-Frequency Resonators

An air-filled metal cavity is a typical example of a high-Q electromagnetic resonator, which confines the electromagnetic energy inside a shielded volume. The cavity is usually a cylinder made from a temperature-stable material such as Invar

46


while its internal walls are plated and thoroughly polished to minimize surface resistivity. Since dielectric dissipation and radiation losses are eliminated, the achievable Q is mainly limited by the loss in the metal walls and can be fairly high (10,000–70,000). The all-metal structure also permits increasing signal power levels to maximize the oscillator signal-to-thermal noise ratio. Excellent phase noise of −165 dBc/Hz at 10-kHz offset and the 10-GHz output has been achieved with a 33-dBm signal injected into a metal cavity and applying an advanced interferometer-based noise-suppression technique [7]. In spite of the high achievable Q-factors and excellent power handling capabilities, the impractically large size of cavity resonators restricts their integration with other surfacemount components commonly used in frequency synthesizer designs. Smaller sizes are realizable using dielectric resonators. A dielectric resonator is a cylindrically shaped piece of material (often called a “puck”) that resonates at certain frequencies determined by its geometry. The resonator can be conveniently mounted on an alumina substrate or printed circuit board and coupled to microstrip lines as illustrated in Figure 2.4. Hence, integration with other components is easily achieved. The practical frequency range for dielectric resonators is between 1 and 40 GHz, while their Q-factor typically reduces linearly with increasing frequency. A Q of 10,000 at 4 GHz is an average representative of commonly used materials [8–11]. The phase noise of −110 to −120 dBc/Hz at 100-kHz offset output is a typical number for X-band commercial dielectric resonator oscillators (DROs). Ceramic resonators offer a simple, low-cost solution for frequencies between a few hundred megahertz and a few gigahertz. The resonator is a silverplated length of temperature-stable ceramic, shorted on one end; achievable Qfactors are comparable to dielectric resonator pucks. Their low cost and easy implementation make them an excellent candidate for ceramic resonator oscillators (CROs), which are commercially available up to approximately 10 GHz

Transmission lines Dielectric resonator

Figure 2.4

Dielectric resonator oscillator.

Building Blocks

47

(such as shown in Figure 2.5). CROs exhibit low-noise characteristics (Figure 2.6), while their tuning is limited to a few percents. Much higher Q-factors are possible using sapphire resonators. The resonator is a cylinder made from a monocrystalline Al2O3 material known as sapphire. This material features extremely low dielectric loss at microwave frequencies. The typical Q-factor of a sapphire resonator used in the fundamental TE01δ mode is 40,000 to 50,000. The higher-order, so-called “whispering-gallery” modes are utilized to isolate the electromagnetic energy inside the resonator and, therefore, reduce the influence of the external elements. Q-factors greater than 200,000 at room temperature have been reported [12–16]. 2.1.2.2 Electromagnetic Tunable Resonators

The main disadvantage of the resonators described above is their limited tuning range, since any resonator detuning adversely affects its Q characteristics. Even frequency locking can be a certain challenge for high-Q resonators such as sapphire. Yttrium iron garnet (YIG) resonators are utilized when wideband tuning and high Q-factors are simultaneously required [17–23]. The YIG resonator consists of a small (8–20 mils in diameter) YIG sphere placed between the two poles of a cylindrically reentrant electromagnet and coupled with small wire loops as depicted in Figure 2.7. Frequency tuning is possible since the resonant frequency of the spherical YIG resonator in uniform magnetic field is a function of the magnetic field strength. The basic relationship between the resonant frequency f and magnetic field strength H is given by f = γH where

Figure 2.5 CRO module built on a 0.5 by 0.5 inch PCB and shielded with a metal can. (Courtesy of Z-Communications, Inc.)

48

Figure 2.6


CRO phase noise at 3.25 GHz. (Courtesy of Z-Communications, Inc.)

Electromagnet

Tuning coil YIG sphere

Figure 2.7

YIG resonator construction.

γ = 2.8 MHz/Oe is a physical constant called a gyromagnetic ratio. Thus, the resonant frequency is in direct proportion to the magnetic field, which can be controlled by changing the DC current injected into the electromagnet tuning coil. YIG resonators offer a relatively high Q (greater than 4,000 at 10 GHz),

Building Blocks

49

which linearly increases with frequency. A practical usable frequency range of pure YIG resonators lies between 2 and 50 GHz, similar to the frequency range of dielectric resonators. Lower operating frequencies (a few hundred megahertz) are obtainable by adding special dopes (such as gadolinium), which unfortunately degrades Q-characteristics. The highest boundary is mainly limited by magnet saturation and impractically high power consumption that is caused by the very high current required to generate the necessary magnetic field strength. The unique features of the YIG material have found application in YIGtuned oscillators (YTOs) featuring excellent phase noise performance. Active devices in the negative resistance configuration (Figure 2.8) are used to achieve wideband tuning. Using a silicon bipolar transistor and a composite feedback architecture (double coupling the YIG sphere in a series feedback for higher frequencies and in a parallel feedback for lower frequencies), a tuning range of 2 to 22 GHz has been achieved with a phase noise of better than −120 dBc/Hz at 100-kHz offset at 10 GHz [22]. YIG-tuned oscillators also offer very linear and repeatable tuning characteristics that simplify a synthesizer’s coarse tuning in multiloop PLL designs. The disadvantages are low tuning speed, high power consumption, large footprint, and relatively high cost. DC power consumption can be reduced by using a permanent magnet to boost magnetic field strength. However, permanent magnet bias leads to narrower tuning bandwidths. Besides this, the relatively slow tuning speed remains one of the major drawbacks that restricts the application of YIG-tuned oscillators in fast-switching synthesizer designs. Smaller size and lower-cost characteristics are possible with varactor-tuned oscillators (usually referred to as voltage-controlled oscillators or VCOs) based on either lumped LC or distributed microstrip resonators [24, 25]. Frequency tuning is achieved using varactor diodes, since their capacitance depends on the applied tuning voltage. Unfortunately, the Q-factors of these resonators are not high; typical values are between a few tens to a few hundreds, depending on the particular technology and tuning range. Thus, the free-running noise of the VCO is significantly higher in comparison with YIG-oscillator numbers. Nevertheless, the VCO is an attractive choice in designing a multiloop PLL synthesizer since its noise can be suppressed by utilizing a low-noise, fixed-frequency Active device YIG resonator

Figure 2.8

YIG-tuned oscillator utilizes a negative resistance concept.

50


reference oscillator as well as a very wide loop bandwidth. VCOs are available in different forms operating from low RF to millimeter waves (Figure 2.9). 2.1.2.3 Electro-Acoustic Resonators

A generic electro-acoustic device combines electrical-to-acoustic and backward acoustic-to-electrical signal transducers with a high-Q acoustic resonator as depicted in Figure 2.10. A “classical” representation is the crystal resonator that utilizes the piezoelectric effect in quartz material [26]. Quartz features exceptional stability and has been the industry’s workhorse for embeddable, precise time base for over half a century. It has also demonstrated exceptionally high Q-factors, ranging from 30,000 to more than 1 million and has been widely used in lownoise, time-stable oscillators from low RF to a few hundred megahertz. Temperature is a key parameter that affects the frequency stability and phase noise characteristics of a crystal oscillator. Various techniques are used to control temperature stability. A temperature-compensated crystal oscillator (TCXO) utilizes additional control circuitry to sense the temperature and generate a voltage that corrects oscillator output frequency drift. An oven-controlled crystal oscillator (OCXO), on the other hand, stabilizes the ambient temperature surrounding the crystal. The resonator as well as other oscillator components are confined in a thermally isolated package (called an oven) such as shown in Figure 2.11. The design also includes a temperature sensor and a thermal heater that form a feedback system to control the temperature inside the oven. When an OCXO is turned on, it goes through a warm-up period while the temperature inside the oven stabilizes and remains at a constant level. OCXOs deliver superior frequency stability and phase noise characteristics compared to other crystal oscillator types (as demonstrated in Figure 2.12) and are, therefore, extensively used in high-performance frequency synthesizer designs.

Figure 2.9

Voltage-controlled oscillator in TO-8 package. (Courtesy of Phase Matrix, Inc.)

Building Blocks

51

At higher frequencies surface acoustic wave (SAW) resonators are most commonly used. The SAW resonator structure is deposited onto a low-acousticloss substrate (such as lithium niobate) and exhibits high-Q characteristics at RF and microwave frequencies up to 2 GHz [27, 28]. The film bulk acoustic resonator (FBAR) is another representative of the electro-acoustic resonator family [29]. The resonator is a three-layer structure with the top and bottom electrodes of molybdenum sandwiching a middle layer of aluminum nitride. FBARs are used in the frequency range of a few hundred megahertz to approximately 5 GHz with a typical Q-factor of greater than 500 at 2 GHz. 2.1.2.4 Electro-Optical Resonators

Electro-optical principles are utilized in an optoelectronic oscillator (OEO), which is capable of generating a signal at microwave frequencies [30, 31]. The OEO generic architecture is essentially a transposed gain oscillator that utilizes laser light energy to enable an electro-optical signal conversion. The laser radiation propagates through a modulator and an optical energy storage element (that is a resonator) then is converted to electrical energy with a photodetector, as depicted in Figure 2.13. The electrical signal at the output of the photodetector is amplified, filtered, and fed back to the modulator to close the oscillator feed-

Electrical-to-acoustic signal transducer

Acoustic resonator

Acoustic-to-electrical signal transducer

Figure 2.10

Electro-acoustic resonator concept.

Figure 2.11

Oven-controlled crystal oscillator. (Courtesy of Bliley Technologies, Inc.)

52


Figure 2.12 An OCXO delivers superior phase noise characteristics. (Courtesy of Bliley Technologies, Inc.)

Laser

Electro-optical modulator

Optical resonator

Photo detector

RF output

Figure 2.13

Optoelectronic oscillator block diagram.

back loop. The optical resonator is constructed using a long fiber delay line; the Q-factor is proportional to the ratio of the delay time and line loss. Since fiber lines exhibit fairly low insertion loss (less than a decibel per kilometer), high-Q resonators can be constructed. Further improvements and miniaturization are possible with a microspherical optical resonator that utilizes multiple reflections inside a fused silica sphere [32].

Building Blocks 2.1.3

53

Coupling

Resonator coupling is another important consideration because any coupling mechanism reduces the residual (unloaded) resonator Q-factor to the actual (loaded) value used in phase noise calculations. However, it is a common design mistake to try to achieve high loaded Q values by using a very loosely coupled resonator. Resonator loss is a function of its unloaded and loaded Q-factors and is given by ⎛ ⎜ 1 Loss (dB) = 10 log ⎜ ⎜ 1 − QL ⎜⎝ Q U

⎞ ⎟ ⎟ ⎟ ⎟⎠

2

(2.3)

where QU and QL are the resonator unloaded and loaded Q-factors, respectively. Undercoupling results in increased overall resonator loss requiring an extra amount of gain to compensate it, which, in turn, results in thermal noise increase. Since these two factors work in opposite ways, intuitively, there should be a certain optimum determined by a specific oscillator topology. It can easily be shown [33, 34] that for the simple feedback oscillator discussed previously, the phase noise minimum is achieved when the resonator loaded Q-factor is set to one half of its unloaded value (i.e., QL = 0.5QU ). This corresponds to a 6-dB resonator loss. Other oscillator schemes may require different optimum coupling values depending on specific design goals and trade-offs. Moreover, the coupling structure does not necessarily have to be symmetrical, that is, the two resonator ports may have different coupling coefficients as required by a particular oscillator scheme [35, 36]. For example, a circulator-based oscillator, shown conceptually in Figure 2.14, utilizes a feedback signal reflected from one resonator port, while the second port is used to extract the output frequency. The output frequency can also be extracted from the amplifier output, thus eliminating the need for the second resonator port. No circulator is required in negative resistance designs, which utilize single-port resonators and are commonly used for wideband oscillators such as YIG-tuned oscillators. 2.1.4

Active Devices

Bipolar and field-effect transistors are the most common devices used in microwave oscillators. Transistor gain, maximum oscillation frequency, output power, and noise characteristics are the main parameters affecting oscillator design. These parameters are heavily dependent on a particular solid-state device technology; the most common ones are silicon (Si), gallium arsenide (GaAs), and silicon germanium (SiGe).

54


Output 2

Output 1

Figure 2.14 port.

A circulator-based oscillator utilizes a feedback signal reflected from a resonator

Silicon-bipolar-junction transistors have dominated the oscillator field up to approximately 20 GHz because of their excellent 1/f noise characteristics. GaAs FET and HEMT devices, on the other hand, have been demonstrated to oscillate at frequencies beyond 100 GHz as fundamental oscillators. Unfortunately, their flicker-corner frequency is also higher compared to the silicon bipolar transistors, which restricts their application in low-noise oscillator designs. In practice, it is more common to achieve millimeter-wave frequencies by using a lower frequency silicon bipolar transistor oscillator, followed by a frequency multiplier and bandpass filter. This arrangement usually results in better phase noise performance, compared to fundamental, GaAs-based oscillators. SiGe is another very promising technology that combines excellent noise characteristics with high oscillation frequencies. 2.1.5

Noise Reduction Techniques

Active device linearization is one of the techniques that help to prevent noise elevation [37–40]. The simplest solution is to avoid or, more precisely, reduce active device compression by implementing another less noisy limiting mechanism. Various techniques (or their combination) can be used, as shown in Figure 2.15. For example, a signal limiter can be placed either before or after the active device, keeping its output well below the compression level. The same function can be achieved with an automatic-level-control (ALC) feedback circuit that detects the active device output and adjusts the overall loop gain with an RF attenuator. The RF signal sampled from the amplifier output can be fed back to, and subtracted from, the RF input signal directly without DC detection as depicted in Figure 2.16. This is essentially a generic feedback concept, which can be implemented in a variety of forms ranging from transistor-level local feedback circuits to more complex system-level solutions. Active device characteristics can also be linearized using a feedforward amplifier approach [41]. The feedforward amplifier employs two cancellation

Building Blocks

Input limiter

Attenuator

55

Output limiter

ALC Figure 2.15

Implementation of limiting mechanism.

−

Figure 2.16

RF feedback concept.

circuits to generate an error signal and subtract it from the main amplifier output as shown in Figure 2.17. By properly balancing amplitude and phase characteristics, it is possible to remove undesired artifact products created by the main amplifier. This approach is widely used to suppress amplifier intermodulation distortion products; moreover, it can be effectively utilized for noise reduction as well. The level of suppression is mainly limited by amplitude and phase balance; typical values are in the 15- to 30-dB range and can be further improved by applying a more sophisticated balance adjustment. Another interesting method (shown conceptually in Figure 2.18) is based on the use of a transposed-gain amplifier [34, 42]. Low-flicker-noise silicon bipolar transistors can be utilized to generate output frequencies greater than their own maximum oscillation frequency. The auxiliary LO noise can be suppressed (to a certain degree, of course) by adjusting the phase delay between the mixer LO ports.

56


Main amplifier

Delay

−

Delay

− Auxiliary amplifier

Figure 2.17

Feedforward concept.

LO

Figure 2.18

Delay

Transposed gain oscillator.

Frequency locking is another powerful approach in constructing low-noise oscillators [43–46]. This approach utilizes a phase detector (usually a balanced mixer) to compare the two signals coming from a VCO directly and through a high-Q resonator used as an external frequency discriminator (Figure 2.19). These two signals are adjusted to be in quadrature to increase the phase detector sensitivity. The phase detector produces a voltage that steers the VCO to suppress its phase noise fluctuations. The noise suppression is limited by the discriminator sensitivity, which heavily depends on the resonator Q-factor. VCO phase noise can be drastically reduced by utilizing a high-Q external resonator, such as a metal cavity or sapphire. However, this circuit exhibits an

Building Blocks

57

VCO

Figure 2.19

Frequency-locked oscillator.

initial frequency-lock acquisition problem caused by the high-Q resonator characteristics. The problem can be elegantly solved by utilizing a common high-Q resonator, which is simultaneously used as both an oscillator resonant element and frequency discriminator (Figure 2.20). A phase noise of −140 dBc/Hz at a 100-kHz offset from a 10-GHz carrier has been achieved using a conventional dielectric resonator with a loaded Q of 1,500 and a FET-based transistor amplifier [46]. The discriminator sensitivity and consequently the phase noise performance can be further improved by putting an additional low-noise amplifier (LNA) in front of the phase detector. However, the incident power coming to the LNA should be kept very low to minimize its flicker noise contribution. This can be achieved by utilizing a near-critical coupling resonator configuration [47] or interferometric signal processing [48, 49]. A phase noise of −150 dBc/Hz at 1-kHz offset and 9-GHz output has been achieved using a whispering-gallerymode sapphire resonator and advanced interferometer-based noise suppression circuit [49]. A pound discriminator is another technique that reduces phase detector DC errors by modulating the VCO with an auxiliary RF generator [50].

ϕ

Figure 2.20

Frequency-locked oscillator with a built-in discriminator.

58


2.2 Frequency Multipliers A frequency multiplier is an electronic device that produces harmonics of the input signal. Frequency multiplication is achieved by introducing a component with nonlinear behavior (for example, a diode or transistor) that distorts a signal waveform and, therefore, generates harmonics [51–54]. Multipliers are used extensively in frequency synthesizers to multiply reference signals or to extend operating frequency range. 2.2.1

Frequency Multiplication

A frequency multiplier is characterized by the output harmonic content versus input frequency and power level. However, the main concern of a synthesizer designer is what happens to phase noise and spurs after passing through a multiplier. To answer this question, let’s examine a nonlinear component that produces an output signal described by VOUT = ∑ knV INn = k1V IN + k2V IN2 + k3V IN3 +  + knV INn n

(2.4)

In general, an infinite number of harmonics are generated. However, for simplicity, let’s consider a frequency doubler described by the k2V IN2 term only. In other words, such a hypothetical component squares the incoming signal. Let’s assume that the incoming signal is a phase-modulated sine wave expressed as V = A0 sin(ω0t + Am sin ωmt). Using the elementary identity sin2 α = (1 − cos 2α)/2 the output signal can be rewritten as

VOUT =

k2 A02 ⎡1 − cos ( 2 ω0t + 2 Am sin ωmt )⎤⎦ 2 ⎣

(2.5)

Ignoring the DC-related term (it can be simply removed with an AC blocking capacitor), we can state that the doubler output contains a signal at 2ω0 modulated at the same ωm rate. Hence, we should still expect two spurious sidebands, equally spaced from the doubled output, as illustrated in Figure 2.21. Note, that the amplitude of the modulating signal in (2.5) doubles, which corresponds to a 6-dB change in power (as the amplitude is given in terms of voltage). Since phase noise has essentially the same phase modulation nature, we should expect the same 6-dB degradation. Our model is very basic, yet quite helpful in understanding the multiplication process. Using more terms from (2.4) brings higher-order harmonics into consideration; however, the idea remains the same. A more rigorous analysis [53] leads to a general conclusion that a times-N multiplier introduces 20logN degradation for both PM spurs and phase noise.

Building Blocks

59

So far, we have considered a purely phase-modulated signal only. However, the input signal can present amplitude variations as well. As discussed earlier, amplitude modulation (AM) effects are often ignored since the AM is greatly attenuated if signal limiting takes place. In the latter case, however, AM-to-PM conversion can affect phase noise performance. The AM noise is first converted into PM noise and then enhanced by 20logN. Moreover, a solid-state device (a diode or transistor) used in a multiplier design also introduces its internal noise that can be upconverted on device nonlinearities and result in further phase noise increase. Thus, the designer’s primary concern is to avoid any extra phase noise degradation above the “natural” 20logN. From this point of view, passive, Schottky-diode-based solutions are generally preferred. 2.2.2

Single-Diode Multipliers

The easiest way to generate harmonics is to use diode nonlinearity to distort a sine-wave signal as shown in Figure 2.22. This circuit is called a half-wave rectifier because it cuts a half of the incoming sine wave. Its design is quite simple and assumes matching the diode impedance with both source and load. The output matching circuit is usually tuned for resonance to accentuate a desired harmonic. Typical conversion loss numbers for a single-diode doubler are in the order of 10 dB. The conversion loss varies as a function of the input power because of

6 dB f

Figure 2.21

2f

Frequency doubling results in 6-dB PM spur degradation.

Matching circuit

Matching circuit & ground return

Figure 2.22 A single-diode half-wave rectifier distorts the incoming sine wave and generates harmonics.

60


the change in diode impedance. The main disadvantages of this scheme are low efficiency and the lack of undesired product suppression. Obviously, the first, fundamental harmonic is the largest since the half-wave pulses still circulate at the same frequency. Although higher-order harmonics are present, the output power declines rapidly with the harmonic number. Therefore, amplification and extensive filtering are required. 2.2.3

Balanced Diode Multipliers

The performance of a single-diode frequency multiplier can be improved by using a balanced configuration. The idea is to suppress the fundamental and other undesired products by out-of-phase cancellation at the output load while combining a desired harmonic in-phase. This can be achieved by adding a signal transformer and another diode to the half-wave rectifier circuit as depicted in Figure. 2.23. The diodes are fed in antiphase; hence, each diode passes an opposite half of the incoming sine wave. Thus, current circulates through the load two times per cycle. The output waveform looks somewhat like a sine wave with twice the frequency of the signal applied to the input. Therefore, we should expect a strong second harmonic with no fundamental signal. Indeed, an ideal scheme outputs even harmonics only while all odd products are suppressed [51]. Although, this circuit works nicely as a doubler, it can also be used as a quadrupler or a higher even-order multiplier. Good odd-harmonic rejection requires that the diodes be balanced or, in other words, respond equally to the positive and negative portions of the input sine wave. A diode pair integrated on the same chip is preferable since the diode characteristics are well matched. In practice, however, no perfect balance can be achieved. Typical fundamental and thirdorder harmonic levels are in the range of −20 to −40 dBc with respect to the output signal as illustrated in Figure 2.24.

Figure 2.23

A balanced doubler is constructed by adding a transformer and another diode.

Building Blocks

Figure 2.24

61

Balanced doubler output spectrum.

Note that the diodes can be connected in antiphase by placing the transformer at the output as shown in Figure 2.25. The circuit behavior is nearly identical. Similar output waveforms can also be obtained with a double-balanced bridge multiplier (Figure 2.26) that requires no ground return, thus eliminating the transformer center point. This configuration is suitable for very broadband operation since it isolates the input and output ports making each easier to match. At microwave frequencies, baluns are used in the place of transformers. The word balun is an acronym for balanced-to-unbalanced converter that converts a single-ended signal to a balanced (differential) one. Baluns can be physically constructed from pieces of transmission lines, which can be conveniently formed on a printed circuit board. The design techniques are well described in [52]. Such balanced multipliers are readily available as low-cost, surface-mount components from Mini-Circuits, Hittite Microwave Corporation, and other manufacturers. Thus, the designer’s effort is reduced to selecting a part with the appropriate characteristics.

Figure 2.25

Another balanced multiplier configuration.

62

2.2.4


Antiparallel Diode Multiplier

The balanced solutions discussed above work nicely to generate even-order harmonics, but what if we need to create an odd-harmonic multiplier, let’s say, a tripler? A simple solution is to use an antiparallel diode pair as shown in Figure 2.27. This circuit can be thought of as a limiter that cuts sine wave edges from both sides, making it closer to a square wave. Fourier analysis reveals that such a signal contains only odd harmonics while even harmonics are suppressed. The level of suppression depends on how the diode characteristics are matched. Obviously, a diode pair integrated on the same chip is a preferable choice. Such a part is readily available in surface-mount packages; thus, a simple tripler can be easily built on a printed circuit board and integrated with other synthesizer components. 2.2.5

Digital Logic Multipliers

As discussed earlier, odd-order frequency multiplication can be accomplished simply by filtering the output of the circuits used to square the sine-wave signal. A good example is a digital logic gate shown in Figure 2.28. This circuit works nicely at low frequencies (depending on a particular logic device family) and provides an output turn-off feature by utilizing an auxiliary gate input. A typical spectrum for a 10-MHz input signal passed through a SN74LVC00A NANDgate is presented in Figure 2.29.

Figure 2.26

A double-balanced doubler utilizes a diode bridge.

Figure 2.27

Frequency tripler built with an antiparallel diode pair.

Building Blocks

Figure 2.28

63

A digital logic gate provides odd-order multiplication functions.

dBm 10 MHz IN 20 10 0 −10 −20 −30 −40 −50 −60 −70 −80

Figure 2.29

2.2.6

Start: 0 Hz Res BW: 10 kHz

Vid BW: 30 kHz

Stop: 100.0000 MHz Sweep: 1.00s

NAND-gate output spectrum for a 10-MHz input frequency.

Step-Recovery-Diode Multipliers

A step-recovery diode (SRD) has long been used to build high-order frequency multipliers. The SRD utilizes capacitive nonlinearity to generate a train of very short pulses that is rich in high-order harmonics. The circuit is called a comb generator and is often used in multiloop synthesizers to generate a high-frequency LO signal with a coarse step size. A fixed-frequency filter or switched filter bank can be placed at the SRD multiplier output to choose a desired harmonic as is often used in direct analog synthesizer designs. Note that although the circuit may seem simple, it can require a lot of effort to optimize and implement properly. Design details are given in [52].

64

2.2.7


Varactor Multipliers

A varactor diode multiplier also relies on capacitive nonlinearity. It provides relatively low conversion loss and excellent phase noise characteristics. However, the varactor multiplier is notoriously narrowband and, similar to the SRD, very sensitive to circuit parameter variations. Under certain conditions it can exhibit a negative resistance and become unstable. For these reasons, the varactor multiplier is rarely used in modern synthesizer designs. 2.2.8

Transistor Multipliers

Transistor multipliers use both bipolar and FET devices. A device is biased in such a manner that it conducts during a portion of the input sine-wave cycle. Similar to diode multipliers, the signal waveform is distorted and harmonics are created. The transistor DC bias is adjusted to accentuate a selected harmonic. A balanced design is also possible as depicted in Figure 2.30. This circuit utilizes two devices that are fed in antiphase and conduct current during a positive and a negative half-cycle, respectively. The circuit delivers two pulses per period of the incoming signal, therefore generating a strong second harmonic. All oddharmonic products should be generally suppressed. The level of suppression depends on the mismatch between individual transistor characteristics. The main advantage of a transistor multiplier is its high efficiency. Nonlinear behavior and signal amplification functions of a transistor are combined to achieve frequency multiplication with minimal conversion loss or even conversion gain. This minimizes the number of additional components (such as amplifiers) required to compensate for signal loss. The main disadvantage is higher noise, which can restrict its application in multiplying a low-noise reference signal.

2.3 Frequency Dividers A frequency divider is an electronic device that produces a signal at 1/N of the input frequency where N is an integer. It works in the exact opposite way that a multiplier does, that is, it brings phase noise and PM-spurious improvement at the same 20logN rate [53–55]. This reduction in noise is ultimately limited

Figure 2.30

Balanced transistor doubler.

Building Blocks

65

by the residual phase noise characteristics of a particular divider. Although both digital and analog implementations are possible, the digital dividers are more versatile and commonly used. They are easily programmable, allowing large and variable division coefficients. Different logic families have different phase noise characteristics as a function of the operating frequencies. The noise in digital dividers is mainly generated in the transition region where the signal crosses the logic threshold. In general, faster logic and larger voltage swings exhibit better phase noise performance; a comparative analysis is given in [56]. Analog dividers offer better phase noise characteristics. They also have the ability to work at very high frequencies and are used in some critical applications. 2.3.1

Digital Dividers

The simplest digital divider is built using a D-type flip-flop as depicted in Figure 2.31. The flip-flop changes its output state with every rising edge of the incoming pulses, thus, providing a divide-by-2 function. Such a divider with a fixed division coefficient is called a prescaler and is available up to a few tens of gigahertz. Ideally, the output of a digital divider has a square-wave waveform that, in the frequency domain, exhibits only odd harmonics. In reality, even products are still present as illustrated in Figure 2.32. Divider harmonics can also be utilized to obtain fraction frequency multiplication or division coefficients (e.g., 3/2, 3/4, 5/4, and so forth), which can be desirable in certain cases. These elementary dividers are cascaded to obtain higher division coefficients. An electronic switch can be added to select a desired division coefficient as depicted in Figure. 2.33. This concept is realized in the UXC20P divider manufactured by Centellax, which operates through 20 GHz providing divideby-2, -4, and -8 functions.

D f IN

Q

f OUT

CLK Q

f IN

f OUT

Figure 2.31

A D-type flip-flop provides a divide-by-2 function.

66

Frequency Synthesizers: Concept to Product dBm Divide-by-2 Fin = 4 GHz 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100

Figure 2.32

Start: 1.0000 GHz Res BW: 30 kHz


Divider output spectrum.

÷2

Figure 2.33

Vid BW: 100 kHz

÷2

÷2

Divider with a selectable division coefficient.

Other division coefficients are obtainable using a digital counter concept. A counter consists of a chain of flip-flops that are initially preset to a certain state by an external binary word as shown in Figure 2.34. The incoming pulses change the output state of the flip-flops, which is detected by an auxiliary state detector circuit. After counting a certain number of pulses, the circuit generates an output signal and also reloads the flip-flops to their initial state. The number of pulses to be counted during the full cycle depends on the initial, preloaded counter state. Thus, a variable, programmable divider can be realized. This is an important part of any PLL synthesizer since it controls the synthesizer’s output frequency by changing the division coefficient. Programmable dividers are usually implemented with CMOS technology and are readily available to a few hundred megahertz. Adding a high-frequency prescaler in front of the programmable divider extends the operating frequency range. Prescalers normally operate at much higher frequencies since they eliminate all delays involved in frequency presetting. This arrangement, however,

Building Blocks IN D1

CLK

67

Q

DATA PRE

CLK D2

Q

DATA State detector

PRE

CLK DN

OUT

Q

DATA PRE Reload

Figure 2.34

Programmable divider.

increases the synthesizer step size. For example, by adding a prescaler, the output frequency of a single-loop PLL synthesizer will be determined by f OUT = PNf PD

(2.6)

where fPD is the comparison frequency at the phase detector inputs, and P and N are division coefficients of a high-frequency prescaler and programmable divider, respectively. Since P is fixed, frequency tuning is now provided in discrete frequency steps equal to PfPD but not fPD. Decreasing comparison frequency can reduce the step size. However, this results in slower tuning and phase noise degradation. This limitation is overcome by using a dual-modulus prescaler concept depicted in Figure 2.35. A dual-modulus prescaler allows the setting of its division coefficient to have two different values: P or P + 1. It works in conjunction with two low-frequency, programmable dividers (marked as A-counter and B-counter), which are clocked from the same prescaler output. Initially, the prescaler divides by P + 1 until the A-counter counts A pulses and switches the prescaler division ratio to P. The number of input pulses required to reach this state equals

68

Frequency Synthesizers: Concept to Product Prescaler

B-Counter

÷(P+1)/P

÷B Reset

Modulus control

÷A A-Counter

Figure 2.35

Dual-modulus prescaler concept.

(P + 1)A. The B-counter counts B − A more pulses that corresponds to P(B − A) pulses at the prescaler input then generates an output signal. It subsequently reloads both counters to their initial settings and the process starts over. Thus, the overall number of input pulses counted during this full cycle is determined by N = (P + 1) A + P (B − A ) = PB + A

(2.7)

and the PLL tuning formula changes to f OUT = (PB + A ) f PD

(2.8)

Since both A and B are programmable integers, the output frequency can be tuned in steps equal to fPD. Therefore, the dual-modulus concept allows the extending of the operating frequency range without any loss in frequency resolution. However, several limitations are applied. First, A must be less than or equal to B. Otherwise, the B-counter would reset the system before the A-counter changed the prescaler division ratio, which would always be kept at P + 1. Moreover, A must cover the 0 to P − 1 range to ensure continuous integer spacing every time B is incremented. Therefore, we conclude that AMIN = 0, BMIN = AMAX = P − 1 and the minimum division coefficient is determined by N MIN = PBMIN + AMIN = P ( P − 1)

(2.9)

On the other hand, the P value should be kept sufficiently high to ensure proper operation of both counters when the input is at the highest operating frequency. This issue is addressed in multimodulus schemes that utilize a larger number of scaling factors.


69

Analog Dividers

An analog frequency divider is essentially an oscillator that generates a signal at a subharmonic of the input signal. For example, a varactor diode, used in a negative resistance mode, can accomplish this function [57]. Analog principles are also used in a regenerative frequency divider depicted in Figure 2.36. The regenerative divider forms a feedback system that can oscillate under certain conditions [57–60]. To start oscillation, a signal must be present in the feedback path (e.g., caused by thermal fluctuations) and the loop gain must be greater than unity. The input frequency f is mixed with a feedback signal in a mixer that produces two products at f /2 and 3f /2. A lowpass filter removes the upper sideband to deliver a feedback signal at the right frequency. Assuming that the oscillation conditions have been met, the circuit outputs the signal at f /2, thus working as a frequency halver. Higher division coefficients are attained by inserting a frequency multiplier into the feedback path as illustrated in Figure 2.37. Analog frequency dividers work at a higher operating frequency and also exhibit significantly lower residual phase noise compared to digital dividers. However, they are rarely used because of their narrowband behavior as well as sensitivity to circuit parameters and input signal level.

2.4 Frequency Mixers A frequency mixer is an electronic device that produces signals at the sum and difference of the two input frequencies and their harmonics. Mixers are utilized f

f/2

f/2

f/2

3f /2 f/2

Figure 2.36

Analog regenerative divider block diagram.

f

f /N

f /N

f (2N + 1)/N

f (N + 1)/N

Figure 2.37

×(N + 1)

f /N

Higher division coefficients are attained by adding a frequency multiplier.

70


in direct analog architectures as well as indirect schemes where frequency offsetting (mixing) is involved. Mixers are available in IC form and can also be built from discrete parts. Similar to frequency multipliers, passive (diode-based) solutions are preferable when phase noise is a concern. 2.4.1

Frequency Mixing

The concept of frequency mixing comes from the trigonometric identity sin α sin β = [cos(α − β) − cos(α + β)]/2 and can be mathematically represented by the multiplication of two sine-wave signals V1 = A1 sin ω1t and V2 = A2 sin ω2t as

VOUT =

A1 A2 ⎡cos ( ω1 − ω2 )t − cos ( ω1 + ω2 )t ⎤⎦ 2 ⎣

(2.10)

Frequency mixing occurs due to component nonlinearities and results in two spectral components at the sum and difference of the input frequencies. Since any nonlinear component creates harmonics, the sum and difference products are created at the multiples of the input frequencies as well. Besides this, direct port-to-port signal leakages also take place. Therefore, the mixer output contains the input signals, harmonics, and their multiplication products described by f OUT = ±nf 1 ± mf 2

(2.11)

where n and m are integers. Similar to frequency multipliers, a single Schottkybarrier diode can be used as a nonlinear component to perform frequency mixing. However, a balanced design is always preferable since it allows canceling of certain multiplication products. There is a large variety of mixer designs. The most popular schemes along with corresponding design techniques are presented in [52]. In contrast to frequency dividers and multipliers, an ideal mixer provides a frequency shift without disturbing signal phase-modulated spurious and phase noise characteristics. This can be easily shown by inserting a phase-modulated signal V = A0 sin(ω0t + Am sin ωmt) into (2.10) instead of the plain sine wave. To highlight the fundamental difference between these three devices, a propagation of a phase-modulated signal with a −60-dBc spurious level through a hypothetically ideal multiplier-mixer-divider chain is illustrated in Figure 2.38. As always, practical scenarios are usually more complicated since AM-to-PM conversion and other effects can take place.

Building Blocks −60 dBc

×2

−54 dBc

71 −54 dBc

÷2

−60 dBc

Figure 2.38 Propagation of a phase-modulated signal through a hypothetically ideal multiplier-mixer-divider chain.

2.4.2

Harmonic Mixers

Harmonic mixing is useful when an LO signal needs to be multiplied. In general, according to (2.11), any single-diode mixer can be used as a harmonic mixer. However, the efficiency of such a mixer would not be high since conversion loss increases rapidly with the harmonic number. A clever solution is to combine an SRD multiplier and mixer diodes in a common package as depicted in Figure 2.39. The use of an SRD multiplier provides a much better efficiency compared to a single-diode solution. This solution eliminates the need for a separate multiplier, leading to considerable reduction in synthesizer component count. However, this mixer is very sensitive to circuit parameters—making one work properly is not trivial. Another concern is a reduced signal-to-noise ratio caused by high multiplication factors, which can result in phase noise degradation in some cases. A fundamental mixer driven by a chain of frequency multipliers can still be a better solution. A second harmonic mixer is another useful circuit. It employs an antiparallel diode pair that is connected in series (or parallel) to the incoming RF signal as depicted in Figure 2.40. An LO signal switches a corresponding diode during a negative and a positive half-cycle, respectively. As a result, the diode pair conducts two times per cycle, as a single diode would be driven by a doubled signal. In other words, the second harmonic mixer requires an LO signal at half the frequency compared to a regular, fundamental mixer. A disadvantage is lower conversion loss and worse linearity compared to a fundamental solution.

Figure 2.39

A harmonic mixer IC combines an SRD multiplier with mixer diodes.

72


RF matching circuit

IF matching & ground return

LO matching circuit

Figure 2.40

2.4.3

Second harmonic mixer built with an antiparallel diode pair.

Image-Reject Mixers

In a regular mixer, two different (but spaced equally above and below the LO signal) input RF frequencies may result in the same IF output. An image-reject mixer eliminates this uncertainty by out-of-phase cancellation of an undesired signal sideband (called an image). A generic block diagram of the image-reject mixer is presented in Figure 2.41. It consists of two regular mixers fed with a 90° phase shift between their RF ports. As a result, the IF signals also have a 90° difference; hence, another 90° hybrid is used to combine the IF outputs in phase. Note that another RF sideband flips the phase shift; hence, the IFs are combined out-of phase and cancelled. This scheme can be used in reverse as a single-sideband (SSB) modulator that upconverts an IF signal and rejects an undesired sideband as illustrated in Figure 2.42. To examine this arrangement, let’s assume that the LO and IF signals at the first mixer are described by VLO = ALO sin ωLOt and VIF = AIF sin ωIF t, respectively. Then the second mixer is driven by VLO = ALO cos ωLO t and VIF = AIF cos ωIF t as a result of the 90° phase shift introduced by the LO and IF hybrids. The mixer output signals are determined by

RF

90° hybrid

90° hybrid

IF LO Figure 2.41

Image-reject mixer block diagram.

Building Blocks IF 1

IF

90° hybrid

90° hybrid

73 RF 1

LO 1

RF

LO 2

IF 2

RF 2

LO

Figure 2.42

SSB modulator upconverts an IF signal and rejects an undesired sideband.

V RF 1 = ALO sin ωLO t × AIF sin ωIF t =

V RF 2

ALO AIF 2 = ALO cos ωLO t × AIF cos ωIF t = ALO AIF 2

⎡⎣cos ( ωLO − ωIF )t − cos ( ωLO + ωIF ) t ⎤⎦

(2.12) ⎡⎣cos ( ωLO − ωIF ) t + cos ( ωLO + ωIF ) t ⎤⎦

After combining these two signals, the output will become VOUT = V RF 1 + V RF 2 = ALO AIF cos ( ωLO − ωIF )t

(2.13)

Thus, one (lower) sideband is generated and another one is cancelled. However, the unwanted sideband is never cancelled completely. The level of rejection depends heavily on the phase and amplitude balance. Equalizing the signal paths within 1 dB (amplitude) and 10° (phase) results in approximately a 20-dB sideband rejection, which is considered to be a reasonable number. 2.4.4

IQ-Modulators

Vector modulation (also called IQ-modulation) is widely used in modern digital communication systems. A typical IQ-modulator consists of two identical mixers driven with a 90° phase shift at their LO ports as shown in Figure 2.43. Two separate baseband data signals are applied directly to the IF ports, upconverted, and summed together with no phase shift between them. The resulting output is an IQ-modulated signal at the same carrier frequency as the LO. Similar to the previous case, the quality of the modulated signal depends on both amplitude and phase balance of the I and Q paths.

74

Frequency Synthesizers: Concept to Product I

LO

90° hybrid

RF

Q

Figure 2.43

IQ-modulator block diagram.

2.5 Phase Detectors A phase detector is an electronic device that compares two input signals and generates a voltage representing the phase difference between the signals. The phase detector is the main element of any PLL synthesizer. There are many types of phase detectors [54, 55]; the most popular ones are listed next. 2.5.1

Balanced Mixer

A balanced mixer can be used as a phase detector. As discussed earlier, a frequency mixer generates both the sum and difference frequencies described by (2.10). Assuming that the mixer is driven by two sine-wave signals V1 = A1 sin(ω1t + θ1) and V2 = A2 sin(ω2t + θ2), its output is described by

VOUT =

A1 A2 AA cos ⎡⎣( ω1 − ω2 )t + θ1 − θ 2 ⎤⎦ − 1 2 cos ⎡⎣( ω1 + ω2 ) t + θ1 + θ 2 ⎤⎦ (2.14) 2 2

By putting a lowpass filter at the mixer output, we can remove the sum product and (2.14) reduces to

VOUT =

A1 A2 cos ⎡⎣( ω1 − ω2 )t + θ1 − θ 2 ⎤⎦ 2

(2.15)

Note that when the mixer inputs have the same frequencies, its output provides a DC voltage that is proportional to the phase difference between the input signals. A balanced configuration should be used to minimize an unwanted DC voltage offset that could affect the detector output. Other undesired signals are

Building Blocks f REF

75

VCO

f OUT

f OUT = N f REF

Figure 2.44

A sampling mixer locks a VCO to an integer multiple of a reference signal.

present at twice the reference frequency (that is, the sum component) and the reference frequency itself (because of insufficient port-to-port isolation). The main advantages of such a phase detector are its low residual noise and ability to support a very high reference frequency. The disadvantages are relatively high undesired signals (e.g., reference harmonics as well as a DC offset caused by imperfect balance) and an initial frequency acquisition problem when the PLL is out of lock. An acquisition aid circuit is normally required to presteer a VCO to a frequency where it can be held by the phase detector. 2.5.2

Sampling Mixer

A harmonic (sampling) mixer, which we discussed earlier, can be used as a phase detector as well. It can lock a high-frequency VCO to an integer multiple of a reference (as shown in Figure 2.44), thus eliminating the need for a frequency multiplier or divider. Note, however, that the sampling detector is very sensitive to circuit parameters. It also exhibits elevated noise because of high multiplication factors. Moreover, broadband noise near multiples of the reference frequency is also converted down and appears at the sampler output. Thus, a fundamental balanced mixer driven by a separate multiplier is usually a better choice. The sampling mixer provides no frequency discrimination; thus, a frequency acquisition aid is required. 2.5.3

Exclusive-OR Gate

Digital logic is used extensively for constructing various phase detectors. The simplest solution is based on an exclusive-OR gate as depicted in Figure 2.45. This gate is driven by two square-wave pulse streams coming from the reference and feedback dividers. When the two signals are completely in-phase, the gate outputs zero voltage. When the signals differ by 180°, the gate’s output sets to high. A phase shift between 0° and 180° results in a train of pulses. By smoothing this output with a lowpass filter, we can get a voltage that is proportional to the phase difference between the two signals. The output spectrum of the exclusive-OR gate has no reference component; however, it does have the component at twice the reference frequency.

76


Figure 2.45

An exclusive-OR gate works as a phase detector.

This component has a maximum when the inputs have 90° phase shift, which is usually the operating state for the phase detector. From this point of view, the exclusive-OR gate works similarly compared to a balanced mixer. It has relatively strong spurious output content and has no frequency discrimination. Moreover, for proper operation, it has to be driven by symmetrical signals with a 50% duty cycle. Nevertheless, the exclusive-OR gate can be successfully used in some nondemanding applications (e.g., as a lock-detection circuit). 2.5.4

Flip-Flop

A flip-flop can be also used as a phase detector as illustrated in Figure 2.46. Similar to the exclusive-OR gate, it is driven by pulse streams that set and reset the output. Very short pulses should be used for proper operation. The average voltage at the flip-flop output represents the phase difference between the input signals. The main advantage is the circuit simplicity. No frequency discrimination is provided. 2.5.5

Phase-Frequency Detector

There is a large variety of phase detector schemes constructed with flip-flops. A phase-frequency detector (PFD) is a very popular solution since it provides a frequency-sensitive signal to aid frequency acquisition. The detector consists of a pair of D-type flip-flops as well as an AND-gate connected as shown in Figure 2.47. A time-delay element at the AND-gate output can also be added to remove the output uncertainty (referred to as a dead zone) when the signals are completely in-phase and there is no time separation between them. The PFD has two outputs marked as up and down. The logic high signal at the up-output

Building Blocks

Figure 2.46

77

Flip-flop phase detector.

Vcc D F1

Q

Up

Q

Down

CLK R Vcc D

F2

CLK R

Figure 2.47 A phase-frequency detector provides a frequency-sensitive signal when PLL is out of lock.

commands the VCO to increase its frequency. The logic high signal at the downoutput does the opposite. The lock is achieved when both outputs set to zero. Note that both flip-flops cannot be set to high simultaneously since they would be immediately reset by the AND-gate circuit. The PFD output information is contained in the polarity and widths of the up and down pulses that are combined and averaged with a loop filter shown in Figure 2.48. Alternatively, the outputs can be summed with a charge pump circuit, which is essentially a pair of switched current sources (Figure 2.49).

78

Frequency Synthesizers: Concept to Product Vcc D F1

Q

CLK R

− +

Vcc D F2

Q

CLK R

Figure 2.48

An operational amplifier combines PFD outputs.

V+ Vcc

Current source D

F1

Q

CLK R Vcc D

F2

Q

CLK

Current source

R V-

Figure 2.49

PFD outputs can be summed with a charge pump circuit.

The main advantage of the phase-frequency detector is its ability to sense the frequency, thus eliminating a need for initial frequency acquisition. This is probably the most popular and widely used phase detector. Disadvantages are associated with dead-zone effects and higher residual phase noise in comparison with analog schemes.


79

Integrated PLL Components

Phase detectors are available as surface-mount ICs and are often combined with other PLL components on the same chip. Analog Devices, Inc., National Semiconductor, Peregrine Semiconductor Corporation, Hittite Microwave Corporation, and other manufacturers provide fully integrated solutions that contain all necessary components required to build a whole synthesizer. A good example is the ADF4106 PLL IC manufactured by Analog Devices, Inc. The part consists of a digital phase-frequency detector with an integrated charge pump, programmable RF and reference dividers, lock detector, and other useful circuits as depicted in Figure 2.50. The reference divider is a 14-bit programmable counter that provides division ratios from 1 to 16,383. The counter divides the input reference signal down to produce a required phase detector comparison frequency (equal to a desired step size). The specified input frequency range is 20 to 300 MHz. It can be extended to lower frequencies by ensuring a sufficient slew rate of the incoming reference signal. This is accomplished practically by placing a sine-to-square wave converter in front of the IC. The RF divider is constructed using the dual-modulus technique discussed above. It includes a dual-modulus prescaler with a selectable modulus of 8/9, 16/17, 32/33, or 64/65. The prescaler works in conjunction with A- and Bcounters to allow a wide range of division ratios. The A-counter is a 6-bit counter that counts between 0 and 63. The B-counter is a 13-bit device that provides division ratios between 3 and 8,191. Keeping in mind that NMIN = P(P − 1) (as required to realize contiguous division ratios) and NMAX = PBMAX + AMAX, the available division ratios are calculated as indicated in Table 2.1. The RF divider input frequency range is specified between 0.5 and 6 GHz. Similar to the reference divider, the operating frequency range can be easily extended down with a sine-to-square wave converter. Higher operating frequencies are available with ADF4107 (7 GHz) and ADF4108 (8 GHz) ICs, which are pin-to-pin compatible devices. Note that the A- and B-counters are CMOS devices specified to work when the prescaler output is 325 MHz or less. The reference and RF divider outputs are routed to the phase detector that produces an output proportional to the phase and frequency difference between the inputs. The maximum allowable comparison frequency is 104 MHz. The phase detector is accompanied by a charge pump. The charge pump current is set by connecting an external resistor and can be further controlled (changed) by software means. Similarly, the phase detector polarity can be programmed if required. Furthermore, the detector also includes a programmable delay element that controls the width of the antibacklash pulse to minimize the dead-zone effects. The ADF4106 IC includes a lock detector that can work in either analog or digital lock detection mode as will be further discussed in Chapter 4. The

Figure 2.50

The ADF4106 PLL IC includes all essential components required to build a frequency synthesizer. (Courtesy of Analog Devices, Inc.)

80 Frequency Synthesizers: Concept to Product

Building Blocks

81

Table 2.1 RF Divider Division Ratios

P/P + 1

NMIN

NMAX

8/9

56

65,591

16/17

240

131,119

32/33

992

262,175

64/65

4,032

524,287

output multiplexer on the ADF4106 allows the user to access various internal points including the lock detector output, RF and reference divider outputs, bias voltage, and ground. A dedicated chip enable pin allows the disabling of all main blocks of the ADF4106 integrated circuit. A logic low signal on this pin powers down the device and puts the charge pump output into a three-state mode. Further details regarding functionality are available in the ADF4106 datasheet [61]. An evaluation board containing the IC and all other parts required to evaluate its functionality and technical characteristics is shown in Figure 2.51. ADF4106 parameters (such as RF and reference divider division coefficients) can be conveniently programmed through a built-in three-wire serial interface (clock, data, and chip select lines). The user can also program charge

Figure 2.51 An evaluation board allows evaluating functionality and technical characteristics of PLL ICs. (Courtesy of Analog Devices, Inc.)

82


pump current (to adjust PLL bandwidth), change phase detector polarity (this feature can be very helpful if frequency mixing is employed), monitor frequency lock, or access some internal signals. The IC allows building a simple single-loop PLL synthesizer (by adding an external VCO and loop filter components) or can be used in more complex schemes. A single-loop PLL design example, based on this part, will be reviewed in more detail in Chapter 4.

References [1] Bahl, I., and P. Bhartia, Microwave Solid State Circuit Design, 2nd ed., New York: John Wiley & Sons, 2003. [2] Rohde, U. L., A. K. Poddar, and G. Bock, The Design of Modern Microwave Oscillators for Wireless Applications: Theory and Optimization, New York: John Wiley & Sons, 2005. [3] Leeson, D. B., “A Simple Model of Feedback Oscillator Noise Spectrum,” IEEE Proc. Letters, Vol. 54, February 1966, pp. 329–330. [4] Parzen, B., “Clarification and a Generalized Restatement of Leeson’s Oscillator Noise Model,” IEEE Intl. Frequency Control Symposium Proc., June 1988, pp. 348–351. [5] Nallatamby, J., et al., “Extension of the Leeson Formula to Phase Noise Calculation in Transistor Oscillators with Complex Tanks,” IEEE Transactions on Microwave Theory and Techniques, Vol. 51, March 2003, pp. 690–696. [6] Rubiola, E., “The Leeson Effect: Phase Noise in Feedback Oscillators,” IEEE Int. Frequency Control Symposium Tutorial, June 2006. [7] Sen Gupta, A., et al., “High Spectral Purity Microwave Oscillator: Design Using Conventional Air-Dielectric Cavity,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 51, October 2004, pp. 1225–1231. [8] Kajfez, D., and P. Guillon, Dielectric Resonators, Norwood, MA: Artech House, 1986. [9] Khanna, A. P. S., “Review of Dielectric Resonator Oscillator Technology,” IEEE Intl. Frequency Control Symposium Proc., May 1987, pp. 478–486. [10] Loboda, M. J., T. E. Parker, and G. K. Montress, “Frequency Stability of L-Band, Two-Port Dielectric Resonator Oscillators,” IEEE Transactions on Microwave Theory and Techniques, Vol. 35, December 1987, pp. 1334–1339. [11] Khanna, A. P. S., “Microwave Oscillators: The State of the Technology,” Microwave Journal, April 2006, pp. 22–24. [12] McNeilage, C., et al., “A Review of Sapphire Whispering Gallery-Mode Oscillators Including Technical Progress and Future Potential of the Technology,” IEEE Intl. Frequency Control Symposium Proc., August 2004, pp. 210–218. [13] Tobar, M. E., et al., “High-Q Whispering Gallery Traveling Wave Resonators for Oscillator Frequency Stabilization,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 47, March 2000, pp. 421–426.

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[14] Tsarapkin, D. P., and N. A. Shtin, “Whispering Gallery Traveling Wave Interferometer for Low Phase Noise Applications,” IEEE Intl. Frequency Control Symposium Proc., August 2004, pp. 762–765. [15] Tobar, M. E., et al., “Compact, High-Q, Zero Temperature Coefficient, TE011 SapphireRutile Microwave Distributed Bragg Reflector Resonators,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 48, May 2001, pp. 821–829. [16] Dick, G. J., and J. Saunders, “Measurement and Analysis of a Microwave Oscillator Stabilized by a Sapphire Dielectric Ring Resonator for Ultra-Low Noise,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 37, September 1990, pp. 339–346. [17] Carter, Jr., P. S., “Magnetically-Tunable Microwave Filters Using Single-Crystal YttriumIron-Garnet Resonators,” IRE Transactions on Microwave Theory and Techniques, Vol. 9, May 1961, pp. 252–260. [18] Helszajn, J., YIG Resonators and Filters, New York: John Wiley & Sons, 1985. [19] Heyboer, T. L., and F. E. Emery, “YIG-Tuned GaAs FET Oscillators,” IEEE Intl. Microwave Symposium Dig., June 1976, pp. 48–50. [20] Trew, R. J., “Design Theory for Broad-Band YIG-Tuned FET Oscillators,” IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-27, January 1979, pp. 8–14. [21] Papp, J. C., “An 8-18 GHz YIG-Tuned FET Oscillator,” IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-28, July 1980, pp. 762–767. [22] Khanna, A. P. S., and J. Buenrostro, “2-22 GHz Low Phase Noise Silicon Bipolar YIG Tuned Oscillator Using Composite Feedback,” IEEE Int. Microwave Symposium Dig., June 1992, pp. 1297–1299. [23] Zensius, D. P., M. Draher, and N. K. Osbrink, “Device and Construction Refinements Yield First 33 to 50 GHz GaAs FET YTO,” Microwave Journal, June 1986, pp. 153–159. [24] Khanna, A. P. S., et al., “Low Jitter Silicon Bipolar Based VCOs for Applications in High Speed Optical Communication Systems,” IEEE Intl. Microwave Symposium Dig., May 2001, pp. 1567–1570. [25] Rohde, U. L., A. K. Poddar, and K. J. Schoepf, “Cost-Effective VCOs Replace PowerHungry YIGs,” Microwaves & RF, April 2006, pp. 80–87. [26] Kroupa, V. F., “The State of the Art of Flicker Frequency Noise in BAW and SAW Quartz Resonators,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 35, May 1988, pp. 406–420. [27] Driscoll, M. M., “Low-Noise Microwave Signal Generation Using Bulk- and SurfaceAcoustic-Wave Resonators,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 35, May 1988, pp. 426–434. [28] Montress, G. K., et al., “Extremely Low-Phase-Noise SAW Resonators and Oscillators: Design and Performance,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 35, November 1988, pp. 657–667. [29] Khanna, A. P. S., et al., “A Film Bulk Acoustic Resonator (FBAR) L band Low Noise Oscillator for Digital Communications,” Proc. of 32nd European Microwave Conference, October 2002.

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[30] Yao, S., and L. Maleki, “Characteristics and Performance of a Novel Photonic Oscillator,” IEEE Intl. Frequency Control Symposium Proc., May–June 1995, pp. 161–168. [31] Yao, X. S., and L. Maleki, “Optoelectronic Oscillator for Photonic Systems,” IEEE Journal of Quantum Electronics, Vol. 32, July 1996, pp. 1141–1149. [32] Ilchenko, V. S., “Optical Microsphere Resonators and Laser Frequency Stabilization,” Lasers and Electro-Optics Society Annual Meeting Proc., November 1997, pp. 94–95. [33] Parker, T. E., “Current Developments in SAW Oscillator Stability,” IEEE Intl. Frequency Control Symposium Proc., June 1977, pp. 359–364. [34] Everard, J. K. A., “A Review of Low Noise Oscillator. Theory and Design,” IEEE Intl. Frequency Control Symposium Proc., May 1997, pp. 909–918. [35] Galani, Z., et al., “Analysis and Design of a Single-Resonator GaAs FET Oscillator with Noise Degeneration,” IEEE Transactions on Microwave Theory and Techniques, Vol. 32, December 1984, pp. 1556–1565. [36] Tsarapkin, D. P., “Phase Noise in Microwave Bridge Oscillators,” IEEE Intl. Frequency Control Symposium Proc., August 2005, pp. 534–538. [37] Darwish, A. M., et al., “A New Phase Noise Reduction Technique for MMIC Oscillators,” IEEE Microwave and Millimeter-Wave Monolithic Circuits Symposium Dig., June 1992, pp. 171–174. [38] Kuleshov, V. N., and T. I. Boldyreva, “l/f AM and PM Noise in Bipolar Transistor Amplifiers: Sources, Ways of Influence, Techniques of Reduction,” IEEE Intl. Frequency Control Symposium Proc., May 1997, pp. 446–455. [39] Rohde, U. L., and A. K. Poddar, “Noise Minimization Techniques for RF and MW Signal Sources,” Microwave Journal, September 2007, pp. 136–162. [40] McNeilage, C., et al., “Review of Feedback and Feedforward Noise Reduction Techniques,” IEEE Int. Frequency Control Symposium Proc., May 1998, pp. 146–155. [41] Black, H. S., “Translating System,” U.S. Patent 1,686,792, October 1928. [42] Everard, J., Fundamentals of RF Circuit Design: with Low Noise Oscillators, New York: John Wiley & Sons, 2001. [43] Walls, F. L., C. M. Felton, and T. D. Martin, “High Spectral Purity X-Band Source,” IEEE Intl. Frequency Control Symposium Proc., May 1990, pp. 542–548. [44] Dick, G. J., “Microwave Oscillators for Superior Short Term Stability and Ultra-Low Phase Noise,” IEEE Intl. Frequency Control Symposium Proc., May 1992, pp. 349–355. [45] Tsarapkin, D. P., “Low Phase Noise Sapphire Disk Dielectric Resonator Oscillator with Combined Stabilization,” IEEE Intl. Frequency Control Symposium Proc., June 1994, pp. 451–458. [46] Bianchini, M. J., et al., “A Single-Resonator GaAs FET Oscillator with Noise Degeneration,” IEEE Int. Microwave Symposium Dig., May–June 1984, pp. 270–273. [47] Santiago, D. G., and G. J. Dick, “Microwave Frequency Discriminator with a Cooled Sapphire Resonator for Ultra-Low Phase Noise,” IEEE Intl. Frequency Control Symposium Proc., May 1992, pp. 176–182.

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[48] Ivanov, E. N., M. E. Tobar, and R. A. Woode, “Microwave Interferometry: Application to Precision Measurements and Noise Reduction Techniques,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 45, November 1998, pp. 1526–1536. [49] Ivanov, E. N., M. E. Tobar, and R. A. Woode, “Applications of Interferometric Signal Processing to Phase-Noise Reduction in Microwave Oscillators,” IEEE Transactions on Microwave Theory and Techniques, Vol. 46, October 1998, pp. 1537–1545. [50] Pound, R. V., “Electronic Frequency Stabilization of Microwave Oscillators,” Review of Scientific Instruments, Vol. 17, November 1946, pp. 490–505. [51] Faber, M. T., J. Chramiec, and M. E. Adamski, Microwave and Millimeter-Wave Diode Frequency Multipliers, Norwood, MA: Artech House, 1995. [52] Maas, S. A., The RF and Microwave Circuit Design Cookbook, Norwood, MA: Artech House, 1998. [53] Manassewitsch, V., Frequency Synthesizers: Theory and Design, 3rd ed., New York: John Wiley & Sons, 2005. [54] Egan, W. F., Frequency Synthesis by Phase Lock, 2nd ed., New York: John Wiley & Sons, 1999. [55] Gardner, F. M., Phaselock Techniques, 3rd ed., New York: John Wiley & Sons, 2005. [56] McClure, M. R., “Residual Phase Noise of Digital Frequency Dividers,” Microwave Journal, March 1992, pp. 124–130. [57] Driscoll, M. M., “Phase Noise Performance of Analog Frequency Dividers,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 37, July 1990, pp. 295–301. [58] Harrison, R. G., “Theory of Regenerative Frequency Dividers Using Double-Balanced Mixers,” IEEE Intl. Microwave Symposium Dig., June 1989, pp. 459–462. [59] Rubiola, E., M. Olivier, and J. Groslambert, “Phase Noise in the Regenerative Frequency Dividers,” IEEE Transactions on Instrumentation and Measurement, Vol. 41, June 1992, pp. 353–360. [60] Ferre-Pikal, E. S., and F. L. Walls, “Microwave Regenerative Frequency Dividers with Low Phase Noise,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 46, January 1999, pp. 216–219. [61] Analog Devices, Inc., “PLL Frequency Synthesizer, ADF4106,” Datasheet, www.analog. com.

3 Synthesizer Construction Chapter 2 discussed the individual components that are used in frequency synthesizers. The next logical step is to examine how these components are physically connected together. This chapter focuses on constructional and packaging principles used in building microwave frequency synthesizers. It begins with a brief overview of transmission line theory, types of transmission lines, characteristic impedance, losses, discontinuity and coupling effects, microwave materials, and distributed and lumped elements. It continues with a review of the most popular assembling techniques including hybrid “chip-and-wire” and printed circuit board approaches. Packaging aspects, including grounding and shielding effects, are also discussed.

3.1 Transmission Lines and Distributed Elements At low frequencies, a circuit can be built by simply connecting its individual elements with wires according to a schematic diagram. As frequency increases, however, various undesired effects occur. A key principle in designing RF and microwave circuits is the need to take into account physical dimensions not only for circuit components but also for their interconnections, which are treated as transmission lines. 3.1.1

Transmission Line Basics

A transmission line is a material medium that guides electrical energy from one point to another. The simplest transmission line is a wire (or two wires since a ground path is needed). In circuit theory, such a wire is a simple connection between circuit nodes. However, in reality, any wire has an inductance that is proportional to the wire’s length. Furthermore, there is always a capacitance be87

88


tween the signal wire and the ground. Inductance and capacitance effects can be significant at high frequencies. In general, they also take place at low frequencies and become quite noticeable for a very long wire. The terms “long” or “short” are relative since they depend on the frequency (or the wavelength) of the traveling electrical signal. A transmission line is considered to be electrically long when its physical length becomes comparable to the wavelength of the electrical signal it carries. At high frequencies, even a physically short wire acts as an LC-circuit rather than a simple electrical connection. Moreover, any transmission line introduces losses to the electrical energy that it is supposed to guide. The conductor, forming a transmission line, always has some resistance, which is never equal to zero. Obviously, a portion of the energy is dissipated in the form of heat when the current flows through such a conductor. The transmission line can also radiate some energy into surrounding space that results in transmission power loss. Furthermore, some energy is dissipated in the dielectric material between the signal line and the ground. These losses are modeled by adding a resistance in series with the inductor as well as a shunt conductance across the capacitor as illustrated in Figure 3.1. In reality, the picture is even more complicated as the indicated effects are not concentrated in one physical spot but rather distributed along the entire length of the transmission line. The transmission line is modeled by breaking it into an infinite number of electrically small elementary cells and then cascading them. The values of such elementary components (called distributed constants) are specified per unit length and depend on physical characteristics (e.g., dimensions, dielectric type) of a particular transmission line. Although the distributed constants can be extracted from the line dimensions, a more practical and widely used parameter is characteristic impedance determined by

Z0 =

R + j ωL G + j ωC

(3.1)

The characteristic impedance denotes the ratio of the complex voltage to the complex current of the traveling wave at any point on a matched terminated R

L

G

Figure 3.1

R

C

L

G

C

A transmission line is modeled by cascading an infinite number of elementary cells.


89

line. From this point of view, the characteristic impedance is somewhat comparable to the resistance in a “regular” DC circuit. The importance of this parameter is the fact that it governs what portion of the energy is delivered to the load and what portion is reflected back to the source. Obviously, a good connection assumes maximum energy transfer with minimal reflections. This is achieved when both source and load are matched, meaning that the load’s impedance is the complex conjugate of the source’s impedance. Note that any electronic device connects to another device through a transmission line that serves as a load for the input device and as a source for the output device, respectively. Thus, the transmission line should be matched with the devices that it connects. Many RF and microwave devices used in frequency synthesizer designs are specified for 50-ohm input and output impedances (although some devices work in other environments, such as 75 or 600 ohms). Hence, a 50-ohm transmission line is a key component of any high-frequency design since it serves as a connection element between individual devices. 3.1.2

Transmission Line Types

Transmission lines can be formed in many different ways—ranging from a twisted pair of wires and coaxial cable to exotic waveguide structures. However, planar transmission lines are the most practical media to interface with surfacemount and chip components used in synthesizer designs. The most popular planar structures are briefly described next. More details on particular transmission lines as well as their design techniques are given in [1–10]. 3.1.2.1 Microstrip Line

A microstrip transmission line is formed with a flat conductive strip on one side of a dielectric material called a substrate. The opposite side of the substrate is covered by metal that serves as a ground. The microstrip is the most popular transmission line and is widely used in both monolithic and hybrid circuits. It can be simply formed on a hard substrate or a soft board by photolithographic processes. If designed properly, the “printed” traces look and act very similar to the “natural” connection lines shown on a schematic diagram. The microstrip environment also allows the mounting of circuit components on the top side of the board, thus simplifying the assembly process. The basic geometry of the microstrip line is shown in Figure 3.2, where W denotes the width of the conductive strip, H is the substrate’s height, ε is the dielectric constant of the substrate, and T is the conductor’s thickness. There are a number of empirical equations for the microstrip line’s characteristic impedance, which is a function of the ratio of the substrate height to the conductor strip width. For example, a 15-mil strip printed on a 15-mil-thick alumina substrate (the dielectric constant of alumina is close to 10) produces approximately

90

Frequency Synthesizers: Concept to Product W

T H

Figure 3.2

ε

Microstrip transmission line.

a 50-ohm characteristic impedance. An alumina substrate of 10-mil thickness requires a 10-mil strip for the same impedance. The impedance also depends heavily on the dielectric constant of the substrate. A higher dielectric constant means higher line capacitance and lower characteristic impedance. For example, in order to realize 50-ohm impedance on an 8-mil soft board with the dielectric constant of 3.38 (RO4003C material manufactured by Rogers Corporation), the line width has to be increased to about 18 mils. The thickness of the metal strip also affects the characteristic impedance. Although the effect is not so pronounced, a greater metal thickness increases the capacitance of the line and therefore reduces its impedance. A metal enclosure in close proximity to the microstrip line has a similar effect (i.e., it lowers the line impedance). A disadvantage of the microstrip line is that it is an open structure and therefore tends to radiate. Hence, circuits that require high isolation (filters, switches, and so forth) have to be properly shielded. Another issue is the dispersion that becomes noticeable at high frequencies. The dispersion manifests itself through signals of different frequencies propagating at slightly different speeds. This may result in asymmetric frequency responses of some distributed structures such as bandpass filters. Microstrip lines also exhibit losses to the propagating signals. For substrates with high dielectric constants, resistive losses in the strip conductor and the ground plane usually dominate over dielectric and radiation losses. The losses in the strip conductor increase with increasing characteristic impedance because of the greater resistance of narrow strips. Surface roughness and skin effect contribute to the conductor losses as well. Skin effect manifests itself as electrical current irregularities inside a metal volume. The effect is characterized by skin depth, which denotes the distance where the electric field reduces to 1/e of its value at the conductor surface. In other words, skin depth indicates how deep the current penetrates into the conductor. The skin depth is inversely proportional to the square root of the operating frequency. At microwave frequencies, the electrical current is mostly concentrated near the conductor surface. There-


91

fore, proper metallization is vital to control conductive losses. The metallization thickness should be a few times higher than the skin depth to reduce this effect. 3.1.2.2 Stripline

A stripline uses a flat metal strip surrounded by a dielectric between two parallel ground planes as shown in Figure 3.3. It requires three metal layers, which is why it was originally called triplate. Similar to the microstrip, the characteristic impedance of the stripline is mainly determined by the width of the strip, the thickness of the substrate, and its dielectric constant. The structure is often built using a multilayer printed circuit board where the central conductor is sandwiched between two board pieces. The structure can also be made asymmetric if necessary. For example, the central conductor does not need to be equally spaced between the two ground planes. Furthermore, the dielectric materials may be different above and below the central conductor. The stripline exhibits lower radiation as compared to the microstrip line. It also offers excellent isolation since the central strip can be conveniently shielded by putting a few parallel rows of stitching via holes between the ground planes on both sides of the strip. The stripline is widely used to create broadband distributed circuits such as filters and directional couplers. However, in contrast with microstrip, the stripline is not easily integrated with other circuit components. It is mainly used in multilayer boards in conjunction with microstrip lines when it is necessary to route RF signals across each other. 3.1.2.3 Coplanar Waveguide

A coplanar waveguide consists of a conductive strip surrounded by a pair of ground planes as illustrated in Figure 3.4. Both conductor and ground planes are printed on the same surface of the dielectric substrate. The electric field is mainly concentrated not in the dielectric substrate but in the gap between the central strip and the ground planes. As a result, radiation effects are more pronounced compared to those of the microstrip. The structure is often accompanied by another ground plane formed on the opposite side of the substrate as shown in

Figure 3.3

Stripline structure.

92


Figure 3.4 A coplanar waveguide consists of a conductive strip surrounded by a pair of ground planes.

Figure 3.5. The top ground planes are usually connected to the bottom plane with stitching via holes. The coplanar waveguide allows for mounting circuit components on top of the substrate similar to the microstrip line environment. Moreover, mounting of shunt elements is even more convenient since the ground is within close proximity of the signal line. The ground path inductance is usually smaller compared to ground vias required in the microstrip environment. Therefore, the coplanar waveguide is preferable at higher frequencies over the microstrip line. The coplanar waveguide can easily interface with other transmission lines (such as microstrip or coaxial line) as well as with microwave probes. It is a good alternative to the microstrip and is widely used in both monolithic and hybrid circuits. 3.1.2.4 Slotline

A slotline is built as a narrow gap between conductive planes formed on one side of a dielectric substrate as depicted in Figure 3.6. Similar to the coplanar waveguide, it is a convenient medium for mounting shunt elements. Although, it is not as popular as the microstrip or the coplanar waveguide, the slotline is very useful in some applications. An example in Figure 3.7 shows a slotline junction that splits a signal into two branches with exactly a 180° phase shift caused by the inversion of the electric field. This circuit can be conveniently used in a variety of balanced devices such as mixers or frequency multipliers [11]. 3.1.3

Microwave Materials

The main parameters of planar transmission lines depend heavily on substrate material and its metallization. The most popular dielectric materials (divided

Figure 3.5

Coplanar waveguide with ground plane.


Figure 3.6

A slotline is built as a narrow gap between conductive planes.

Figure 3.7

A slotline splits a signal into two branches with a 180° phase shift.

93

into two main classes: hard substrates and soft boards), along with their physical properties, are listed in Table 3.1. Alumina is the most widely used hard substrate dielectric material, which provides a good balance between physical properties (e.g., reasonably low loss at Table 3.1 Hard Substrate and Soft Board Dielectric Materials Dielectric Constant

Loss Tangent, ×10−4

Alumina

9–10

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