Compound Semiconductor Devices: Structures and Processing

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Compound Semiconductor Devices Structures and Processing Edited by Kenneth A. Jackson

8WILEY-VCH

Related Reading: K. A. Jackson (Ed.)

Silicon Devices Structures and Processing ISBN 3-527-29595-X

K. A. Jackson (Ed.)

Processing of Semiconductors Volume 16 of Materials Science and Technology ISBN 3-527-26829-4

W. Schroter (Ed.)

Electronic Structure and Properties of Semiconductors ISBN 3-527-26817-0

Compound Semiconductor Devices Structures and Processing Edited by Kenneth A. Jackson

633 WILEY-VCH Weinheim . New York . Chichester

*

Brisbane Singapore . Toronto

Editor: Prof. K. A. Jackson The University of Arizona Arizona Materials Laboratory 4715 E. Fort Lowell Road Tucson, AZ 85712, USA

This book was carefully produced. Nevertheless, authors, editor and publisher do not warrant the information contained therein to be free of errors. Readers are advised to keep in mind that statements, data, illustrations, procedural details or other items may inadvertently be inaccurate.

Library of Congress Card No.: applied for British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library Die Deutsche Bibliothek - CIP-Einheitsaufnahme Compound semiconductor devices : structures and processing I ed. by Kenneth A. Jackson. Weinheim ; New York ; Chichester ; Brisbane ; Singapore ; Toronto : Wiley-VCH, 1998 ISBN 3-527-29596-8 0 WILEY-VCH Verlag GmbH, D-69469 Weinheim (Federal Republic of Germany), 1998

Printed on acid-free and chlorine-free (TCF) paper All rights reserved (including those of translation into other languages). No part of this book may be reproduced in any form - by photoprinting, microfilm, or any other means - nor transmitted or translated into a machine language without written permission from the publishers. Registered names, trademarks, etc. used in this book, even when not specifically marked as such, are not to be considered unprotected by law. Composition, Printing and Bookbinding: Konrad Triltsch, Druck- und Verlagsanstalt GmbH, D-97016 Wurzburg Indexing: Borkowski & Borkowski, Schauernheim Printed in the Federal Republic of Germany

Preface

This volume covers the basic processes involved in the manufacture of compound semiconductor devices, starting with materials preparation, purification and crystal growth, includes a description of various device structures, and concludes with a description of the processes involved in device fabrication. The chapters are drawn from the book “Semiconductor Processing” which is Volume 16 of the VCH series on Materials Science and Technology. It may be surprising to some how little the descriptions of the processing depends on the fundamental physics of semiconductors. The properties of the semiconductor determine what is to be done in the manufacturing process, but not how it is to be done. The processing depends critically on the properties of the wide variety of materials which are used, and the processing of semiconductor devices is a complex multi-stage sequence. There are many aspects of the processing of compound semiconductors which are common to silicon processing, but many of the devices are different, and the basic chemistry of the materials introduces significant differences in processing. In general the processing of compound semiconductors is more complex than silicon processing for a variety of reasons. It is more difficult to purify the starting materials and more difficult to grow single crystals. They are more susceptible to defect formation, and they are softer than silicon, and so must be handled more delicately. Care must be also taken to ensure that the processing preserves the stoichiometry, which is especially a problem when making electrical contacts. Compound semiconductors have some advantages over silicon, for example, the electron mobility is higher in GaAs than in silicon. This increased mobility is used to make GaAs amplifiers which operate at higher frequencies than is possible with silicon devices. But silicon processing technology is at a more advanced scale of integration than compound semiconductor technology, and so, if a semiconductor device can be made with silicon, it will be. In spite of the many predictions that GaAs will replace silicon for all applications, the more complex processing which GaAs requires make it unlikely that this will happen. As the wag says: GaAs is a material of the future, and always will be. And so silicon is used almost exclusively for logic and memory devices. But because of its intrinsic electronic structure, it cannot be used to make devices which emit light, such as light emitting diodes (LED’S)or semiconductor lasers. Semiconductor light source devices are the domain of compound semiconductors. The recent development of blue-emitting devices based on gallium nitride promise to extend the application of semiconductor light sources, and to lead to novel uses. This volume does not deal with the semiconductor circuit design, although this is clearly the essential first step in the production of a device. Nor does it deal with testing, which is a major aspect of semiconductor manufacture. Simple circuits are sample tested, but complex chips are subject to extensive electrical and performance testing. The test stations are expensive and the tests are time consuming, so that testing is a major cost factor in semiconductor production.

There are two important aspects to the fabrication of semiconductors which are beyond the scope of this volume. Photoresists are used for the patterning of the dopant distributions, as well as the patterning of the dielectrics and metallization. The sophisticated chemistry which is involved in the design of photoresists is beyond the scope of this volume. The packaging technology which used to protect the chips and to connect them to the outside world is also not discussed in detail. This volume deals with the basic manufacturing processes for compound semiconductor devices. The fabrication process starts with purification, followed by the growth of single crystals. These processes often have aspects in common for the different compound semiconductors, but in general they are unique for each material. After growth, the crystals are sliced into wafers which are then polished. These processes are discussed in first chapter by J. Brian Mullins. Compound semiconductor device structures including fieldeffect transistors, high electron mobility transistors, heterojunction bipolar transistors, and semiconductor lasers are described in the second chapter by William E. Stanchina and Juan F. Lam. In the concluding chapter, John M. Parsey, Jr. discusses compound semiconductor device processing, including doping, isolation methods, diffusion, etching, ohmic contacts and Schottky barriers, dielectrics, metallization, and die separation. The processing of a wafer typically involves hundreds of separate steps, but several hundred chips can be made from a single wafer. There is a continuing trend to use larger wafers and finer features on the wafers in order to get more chips from each wafer, and a continuing effort to improve performance and increase yields. I would like to thank the authors who have taken time from their very busy schedules to prepare their chapters. They are experts in processing technology because they are involved with it on a daily basis, and it has been difficult for them to find the time to write. But the result is a valuable and timely description of the state-of-the-art of compound semiconductor processing. Kenneth A. Jackson Tucson, A Z August, 1998

List of Contributors

Prof. Kenneth A. Jackson University of Arizona Arizona Materials Laboratory 4715 East Lowell Road Tucson, AZ 85712 U.S.A. Dr. Juan F. Lam Hughes Aircraft company Hughes Research Laboratories 3011 Malibu Canyon Road Malibu, CA 90265-4799 U.S.A. Dr. J. Brian Mullin EMC Malvern “The Hoo”. Brockhill Road West Malvern, Worcs. WR14 4DL U.K.

Dr. John M. Parsey, Jr. Advanced Materials Wireless Research and Development Laboratory Wireless Subscriber Systems Group Motorola, Inc. Tempe, AZ 85284 U.S.A. Dr. William E. Stanchina Hughes Aircraft Company Hughes Research Laboratories 3011 Malibu Canyon Road Malibu, CA 90265-4799 U.S.A.

Contents

1 Compound Semiconductor Processing J. B . Mullin

......................

1

2 Compound Semiconductor Device Structures W E . Stanchina. J. E Lam

..................

3 Compound Semiconductor Device Processing J . M . Parsey. Jr.

. . . . . . . . . . . . . . . . . . 61

Index

........................................

45

175

1 Compound Semiconductor Processing

.

J Brian Mullin Electronic Materials Consultancy. Malvern. Worcestershire. U.K.

List of Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Historical Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Purification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 1.3.1 General Purification Procedures .................................... 1.3.2 Zone Refining and Related Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.3 Problems with Specific Compounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.3.1 InSb and GaSb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.3.2 InAs and GaAs ................................................... 1.3.3.3 InP and G a P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.3.4 I1 - VI Compounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Technical Constraints to Melt Growth Techniques . . . . . . . . . . . . . . . . . . . . . . 1.4.1 Chemical Reactivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 Melting Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 Vapor Pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Crystal Growth ................................................... 1.5.1 Horizontal Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2 Vertical Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.3 Crystal Pulling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1S.4 Liquid Encapsulated Czochralski (LEC) Pulling ....................... 1.5.4.1 The Low Pressure LEC Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.4.2 The High Pressure LEC Technique .................................. Crystal Growth of Specific Compounds ............................... 1.6 1.6.1 InSb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.2 InAs and GaAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.3 InP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.4 11-VI Compounds: General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.4.1 Bulk Hg, -,Cd, Te ................................................ 1~j.4.2CdTe and Cd, -,Zn, Te . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.4.3 ZnSe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.4.4 ZnS and CdS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 Fundamental Aspects of Crystal Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7.2 Temperature Distribution, Crystal Shape and Diameter Control . . . . . . . . . 1.7.3 Solute Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 4 4 7 7 8 8 9 10 10 10 11 12 13 13 13 14 16 18 20 20 20 21 22 22 24 26 26 27 28 28 29 30 30 33

2

1.7.4 1.7.5 1.7.6 1.8 1.9


Constitutional Supercooling ........................................ Facet Effect. Anisotropic Segregation and Twinning .................... Dislocations and Grain Boundaries .................................. Wafering and Slice Preparation . . . . . . .: .............................. References .......................................................

34 36 39 40 41

List of Symbols and Abbreviations

List of Symbols and Abbreviations solute or dopant concentration (in the solid, in the liquid, at the interface) depth of volume of convecting gas diffusion coefficient temperature gradient Miller indices latent heat of fusion dopant distribution coefficient equilibrium dopant distribution coefficient thermal diffusivity gradient of liquidus gas pressure pressure of gas, pressure of dissociation vapor of components Rayleigh number temperature growth velocity

w

boundary layer “thickness”, parameter of BPS model angle kinematic viscosity crystal density thermal conductivity interfacial energies angular rotation rate

ACRT BPS CRA HG LEC LPE MBE MCT MOVPE PBN PPba PPm QA RF SI TGZM THM VGF VP

accelerated crucible rotation technique Burton, Prim and Slichter cast recrystallize anneal horizontal growth liquid encapsulated Czochralski (techniques) liquid phase epitaxy molecular beam epitaxy mercury cadmium telluride metal organic vapor phase epitaxy pyrolytic boron nitride atomic parts per billion parts per million quench anneal radio frequency semi-insulating temperature gradient zone melting traveling heater method vertical gradient freeze (technique) vertical pulling

4L,4s,4G

3

4


1.1 Introduction

1.2 Historical Background

This chapter reviews the general principles and practice governing the preparation and processing of compound semiconductors and their alloys, how they are purified, how they are prepared as single crystals and how they are converted into wafers suitable for epitaxial growth. The range of materials which can be classified as compound or alloy semiconductors is vast and covers the whole of the periodic table. It includes IV-IV, 11-IV, I-v, 11-v, 111-v, I-VI, 11-VI, 111-VI, IV-VI, v-VI, I-111-VI, I-IV-VI, I-VVI, 11-IV and 11-111-V compounds. However, because of the enormous cost of developing these materials as high-quality semiconductors most of these compounds are currently in a relatively primitive state of development when compared with Ge or Si. Indeed the only compounds which have been developed to a state of significant commercial application are to be found in the 111-V and 11-VI semiconductor groups of materials. It is with these classes of materials that this chapter will be mainly concerned. The efficient processing of semiconductors in a form suitable for device application requires a sound understanding of the practical technologies involved together with a knowledge of the scientific principles underlying these technologies. Both the technology and the science of the processing will be covered in this chapter. However, it is important to appreciate that the technology as opposed to the science of semiconductor processing is undergoing a constant evolution driven by ever more demanding specifications arising from of an ever increasing range of devices.

Probably the most important event which promoted significant scientific and technological research in the processing of semiconduction materials was the discovery of transistor action in germanium by Brattain and Bardeen (1948) which had been stimulated by the predictions of Shockley (1949). As a result serious international interest developed in the search for new semiconductors. 11-VI compounds had of course been known since before the beginning of the century, but the early work of Welker (1952, 1953) and his colleagues in Germany on 111-V compounds following the discovery of transistor action marked the beginning of the evolution of compound semiconductor processing. Our knowledge of semiconductor processing (Mullin, 1975a, b, 1989; Thomas et al., 1993), indeed of all aspects of semiconductors and the solid state, is rooted in research on Ge in the 1950s. Even early work in this period highlighted the two overriding requirements for semiconductors, the need for high purity and the need for single crystals. The first requirement resulted in the creation of new methods of purification and the evolution of a most significant concept, the concept of semiconductor purity. This specified the need for unprecedentedly low levels of impurities, typically less than 10 parts per billion atomic (ppba) of electrically active impurities. The second requirement resulted in the development of new technologies for producing completely single crystals free from defects including dislocations. At the forefront of this materials work aimed at fulfilling these demands of purity and crystalline perfection was the development of the science and technology of crys-

1.2 Historical Background

tal growth. In less than a decade the intense research and development effort resulted in the melt growth of Ge developing from an art to a science. In the case of the compound semiconductors, the less difficult materials, like InSb, followed the pattern of evolution of Ge, and single crystals containing less than 1013 carriers/cm3 (1 ppba is equivalent to 2.9 x l O I 3 atoms/cm3) were state of the art well within a decade. However, in the case of the more difficult materials like GaAs, InP and Gap, their evolution has taken over three decades and is still in a development phase. For the very difficult materials like ZnSe no melt growth technology has yet been devised that can achieve reproducibly and readily acceptable quality single-crystal material, although there are promising developments (Rudolph et al., 1994). For ZnSe, vapor growth techniques are pioneering the way to semiconductor quality (Cantell et al., 1992). The key to the development of Ge was the creation of new melt growth technologies. Very significant contributions to our knowledge resulted from the pioneering work of Pfann (1966) on zone melting and Teal (1958) on the vertical pulling of single crystals. Pfann (1966) initiated the concept of zone melting. This generic term covers a range of related horizontal crystallization technologies. The simplest technology is the single zone freeze in which a horizontal boat containing a molten charge is progressively frozen from one end. Other procedures were developed involving the translation of a liquid zone through a solid ingot. In particular it created two very powerful processing technologies, zone leveling and zone refining (see Sec. 1.3.2). Zone leveling was initially applied to Ge and resulted in a very successful crystallization technology for the production of

5

uniformly doped single-crystal material. This process involves the formation of a liquid zone in a solid ingot and its movement through the ingot in one direction and subsequently, for ideally uniform material, in the reverse direction. The liquid zone acquires a constant dopant concentration l / k times that in the solid, where k, the distribution coefficient, is given by k = C,/C, and C, and C, are the concentrations of dopant in the solid and liquid respectively. This process levels out the dopant concentration in the solid so that the dopant concentration of the solid being melted is the same as the concentration in the solid being crystallized. The horizontal technologies were not only used for zone leveling and for purification by zone refining but they were also developed for the growth of single crystals. This was achieved by arranging for a molten zone to melt-back into a single crystal seed positioned at one end of a polycrystalline ingot. The solid which crystallized on the seed as the zone was moved through the ingot took up the orientation of the seed and resulted in the formation of a single crystal. In addition to H G for the growth of single crystals, the use of VP of crystals from the melts was pioneered by Teal (1958). The technique has its origins in the Czochralski technique. Czochralski (1917) arranged to dip a thin rod which acted like a seed into a molten melt of metal and withdraw it from the melt. As the liquid was pulled away from the melt it crystallized, giving regions of single crystal metal. However, this technology is far removed from modern crystal pulling technology. The modern pulling technique (Teal, 1958) was developed during the initial phase of semiconductor research at Bell Labs in the 1950s and early 1960s. The most important innovation was the intro-

6


duction of rotation using a pull rod. A single-crystal seed was mounted in a chuck on the pull rod which could be raised and lowered at a set rate. In the pulling process the crystal nucleated on the seed and its diameter was controlled by adjusting the power to the melt. This concept had profound consequences for the semiconductor processing of single crystals. Theoretical work on crystal pulling has also had an important influence on the development of the technology. The work of Burton, Prim and Slichter (BPS) (Burton et a]., 1953) on solute distribution during crystal growth proved to be most significant. They modeled solute transport in the melt adjacent to the rotating crystallizing surface using concepts developed by von Karma, (1921) and Cochran (1934). BPS established the flow normal to the disc as a function of the crystal growth parameters enabling quantitative estimates to be made of the solute distribution from the interface into the melt. Use of the BPS model has stimulated much research and laid the foundations of a great deal of our understanding of the science of crystal growth from the melt. It has been used, for example, in the modeling of heavy doping during crystal pulling. This has resulted in a predictive theory of constitutional supercooling (Hurle, 1961; see Sec. 1.7.4). This knowledge is directly relevant to the crystallization of compound semiconductors from nonstoichiometric melts, where constitutional supercooling is a very common occurrence and can be a major problem seriously affecting crystal quality. The causes of nonuniform dopant or impurity incorporation are a major consideration in understanding the mechanisms of crystal growth. Of particular significance has been the discovery of the facet effect (Hulme and Mullin, 1959) and anisotropic

segregation (Mullin, 1962) of dopants during crystal growth. Also important are impurity striations, which are a common occurrence. Crystal rotation introduces periodic impurity incorporation due to the growth rate variations imposed by the rotating crystal. The incorporation of dopants will be developed in further detail in Sec. 1.7.5. The science of horizontal growth (HG) has lagged significantly behind that of vertical pulling (VP). In HG there is no effective working theory for convection in the molten zone and transient control of doping as opposed to uniform doping is not possible as it is in VP. The VP technique thus evolved as a favored tool for investigating the science of crystal growth from the melt. From an historical viewpoint it is instructive to follow the evolution and role of HG and VP techniques in relation to the science and technology of Ge and Si. The horizontal growth of Ge, a technology that pioneered purification by zone refining and the production of doped single crystals by zone melting, gradually emerged as the more cost effective crystal growth process and replaced the VP technique. Ultimately however, the semiconductor applications of Ge were taken over by Si, eliminating the need for Ge altogether with the exception of a few specialist applications such as the growth of very large crystals for detectors. These are fulfilled by pulling. It is interesting that the VP technique that was developed for Ge created the conditions for the single-crystal growth of Si. Silicon with its superior device properties has emerged as the dominant semiconductor and as such has had and continues to have a profound influence on every aspect of semiconductor processing. The VP technique has been refined and developed for Si and is still the dominant industrial tech-

1.3 Purification

nology for Si. But, also of major importance for Si is the float zone technique, in which a liquid zone out of contact with the container is moved through a vertical rod of Si. This zone refining action produces the very highest grade of single-crystal Si, a very important industrial requirement. Nevertheless, it is important to recognize that some of the unique properties of the compound semiconductors have also stimulated developments in semiconductor processing. Undoubtedly the very rapid expansion in our knowledge of semiconductor processing can be attributed to the relative ease of handling Ge and in particular to the ability to hold and crystallize molten Ge with negligible contamination from silica apparatus. The technology of Si is in many ways very different to that of Ge. It reacts with SiO, and cannot be crystallized in a silica boat. It also forms a tenacious oxide which requires special techniques to prevent its formation. Hence the importance of the pulling technique and the noncontacting float zone technique in its development. Technology never stands still. Zone refining has been developed (Hukin, 1989) for Si using a horizontal water-cooled Cu boat. A liquid zone is formed and levitated out of contact with the boat using R F fields. Two-meter, 125 cm2 section solar cell grade Si can be produced in this way. The 111-V and 11-VI compounds present different problems again to those of Si. The antimonides are similar in their attributes to Ge but the arsenides and the phosphides, selenides and tellurides suffer dissociative decomposition near their melting points, resulting in the loss of one of their component elements. As a result, closed-tube techniques needed to be developed in order to prevent vapor loss. This has stimulated new technologies such as

7

liquid encapsulation and more recently the vertical gradient freeze (VGF) technique to overcome this problem. The relatively slow development, over three decades, of these compounds is in no small way due to the difficulties associated with dealing with compounds which have a significant vapor pressure at the melting point. In addition the number of point defects at the melting point is high l O I 9 ~ m - This ~ . leads to extended defects and doping nonuniformities and a range of problems not found in Si and Ge. The continuing challenge of processing technology is to understand and control these problems.

-

1.3 Purification The cost of developing the knowledge and technology to be able to process raw materials into device quality semiconducting compounds is enormous and inevitably involves a very significant research and development effort involving both purification and crystal growth. As a consequence, there are only a few highly developed compound semiconductors. These include InSb, GaAs, InP, GaP and CdTe and its related alloys with HgTe. Most of the IIVI compounds are still not readily available in wafer form as high-quality singlecrystalline material. The basic aspects of the purification technologies required to produce high-purity semiconducting compounds will now be considered.

1.3.1 General Purification Procedures It is convenient to identify two stages in the purification of semiconductor compounds, firstly the purification of the elements themselves and secondly the purification of the compounds. From an historical perspective the role of the more con-

8


ventional chemical purification procedures has been more useful than zone refining in purifying the elements. This can be appreciated from the early reviews in Willardson and Goering’s book on 111-V compounds (1962). It is evident that work on zone refining of group I11 metals as well as phosphorus and arsenic was clearly not seen to be markedly effective. This coupled with the fact that zone refining represented an additional costly batch process meant that its use has always been problematical, especially for elements like In and Ga which are low melting point readily alloyable metals with a tendency, in the case of Ga, to supercool. Whilst zone refining has not been particularly useful for the common elements of groups I11 and V, in the case of groups I1 and VI zone refining has proved to be a very effective process for the production of ultra-pure Cd and Te. This development was made possible by military funding since these elements arse used in the preparation of HgCdTe for infrared detectors. Here very high purity elements, having less than 1 part in lo9 electrically active impurities are essential. It is evident that zone refining is most effective for strongly bonded materials which crystallize well and in which impurities have a low solubility. These criteria apply particularly to the compounds themselves. Thus many compounds can be zone refined but most compounds have their own peculiarities, demanding specialized processes. These will be considered for the more important compounds later. 1.3.2 Zone Refining and Related Techniques Zone refining, which involves the motion of a liquid zone or zones through an ingot, is the most important and effective

purification procedure for Ge. The impurities that are less soluble in the solid, or more soluble in the liquid ( k , c l ) , are moved in the direction of crystallization towards the finish (last to freeze) end of the ingot whereas the impurities that are more soluble in the solid ( k , > l), that is, less soluble in the liquid, are moved to the start end of the ingot. Provided the distribution coefficients k , are not close to 1 - a condition satisfied by Ge - this very simple process can after very few zone passes produce semiconductor purity in an ingot. A remarkable result. One can appreciate the effectiveness of zone refining from the graphs in Fig. 1-1, where the theoretical ultimate distributions for impurities having different distribution coefficients are given. Orders of magnitude improvement in purification are indicated. However, these dramatic results must only be taken as a guide since solid-state diffusion and vapor transport can reduce the effectiveness of impurity removal.

1.3.3 Problems with Specific Compounds Processing by conventional zone refining or chemical purification methods is often insufficient on its own as a means of achieving semiconductor purity in compounds. Inevitably there is some problem or problems, some difficult-to-remove residual impurity or some quirk of contamination that needs to be dealt with in an unconventional manner if the ultimate goal of semiconductor purity is to be achieved. The equilibrium distribution coefficient k , of a solute (dopant, impurity or excess component) is the ratio of the concentration of the solute in the solid, C,, to the concentration of the solute in the liquid, C , , if the phases are kept in contact for a sufficiently long period for them to come to equilibrium.

9

1.3 Purification

Initial concentratic _ _ _

~

~

/k=O.Ol

-24 * "V

O

P ~~

~

Length solidified

Figure 1-1. Theoretical ultimate distributions for dopants having different distribution coeficients ( k ) after multiple zone refining passes in an ingot where the zone length is 10% of the ingot length. It is assumed that there is no back reflection of dopant from the freezing of the last zone length. The results highlight the potential of lone refining (see Pfann, 1966).

In this section problems or aspects of purification will be considered which have proved to be important in the achievement of semiconductor purity of the more important compound semiconductors. It should be stressed that achieving semiconductor purity in compounds is a very demanding and generally costly process and one that is frequently underestimated. The processes of purification and the avoidance of contamination represent a continuous battle if the ultimate in semiconductor performance is to be achieved. In the case of many of the 11-VI compounds for example the presence of impurities could still be the principal problem preventing their effective development. 1.3.3.1 lnSb and GaSb Indium antimonide (Hulme and Mullin, 1962) has attracted much more research and development (R&D) over the years than GaSb. Major factors in this interest are of course the device applications of the material. InSb, for example, is an impor-

tant infrared detector material suitable for detectors working in the 3-5 pm region of the spectrum. The low melting point of InSb, 525"C, combined with the negligible vapor pressure of Sb over its melt make InSb an ideal candidate for conventional zone refining procedures. However, the straightforward process is of limited value because of troublesome impurities, particularly Zn and Te. Not only do they exhibit anisotropic segregation (Mullin, 1962), but in the case of Te the value of its effective distribution coefficient, kerf (see Sec. 1.7.5) can range from -0.5 for growth in an non[lll]direction to -4.0 for growth on a (111) facet. Thus Te would be distributed in polycrystalline material as though the effective k were some weighted mean of these values, that is, close to one. Zinc has a value of kerfranging from 2.3 to 3.0. But more troublesome is its volatility at the melting point of InSb. Vapor transport of Zn above the ingot can reduce the efficiency of zone refining. This problem has been overcome by using the volatility of Zn to advantage in a two-stage evaporation and zone-refining procedure (Hulme, 1959). Zone-refined Sb in excess of that required to form stoichiometric InSb is added to high-purity In in a boat in a modified zone-refining apparatus and melted under vacuum. Both Zn and Sb evaporate from the molten charge and condense on the cooled upper surface of the outer containing tube. The excess Sb traps in the very small quantity of the more volatile Zn. After a timed period when the excess Sb has evaporated the ingot is cooled and frozen. It is then zone refined under an atmosphere of H,, a condition where the Sb has negligible volatility. The purification process is highly reproducible, resulting in the production of very high

-

N

10


purity InSb with some 60% of the ingot having a carrier concentration less than 1 x loi4 cmP3. GaSb has not been developed in this way but it can be zone refined. The incentive to purify the material further, however, is limited by the belief that the residual carrier level, -2 x 10l6 p-type carriers per cm3, is determined by fundamental aspects of the band structure of the compound. 1.3.3.2 InAs and GaAs InAs and GaAs present additional handling problems because at their melting points the As dissociation pressures are respectively -0.3 and 1.0 atm. Nevertheless, considerable R&D effort has been carried out on GaAs using conventional hot wall technologies. However, a major problem encountered on zone refining GaAs has been the failure to achieve purities with carrier levels below 10l6 to loi7 n-type carriers per cm3. This has been shown by Hicks and Greene (1971) to be due to the reaction between Ga in the liquid Ga, As melts and the silica containing vessel, which introduces a fairly constant level of Si into the ingots at about one part per million:

-

+

4 Ga(L) SiO,(S) = 2 Ga,O(V)

(1-1)

+ Si(so1n)

The problem can be overcome by using BN or graphite boats. However, the zonerefining process has generally been superseded and simplified by in situ compounding of very high purity Ga and As which are now available as a result of improvements in chemical purification methods (see Sec. 1.6.2). 1.3.3.3 InP and GaP The very high vapor pressures generated by these compounds at their melting points, some 27 atm and 32 atm for InP

and GaP respectively, makes zone refining a difficult and potentially hazardous process. The compounds can nevertheless be prepared in horizontal systems by distilling the P, into the molten group I11 element contained in a silica or BN boat. By limiting the amount of group V distilled so that the group I11 element is in excess of stoichiometry the working vapor pressures are reduced. Crystallization under these conditions has an additional advantage; there is a very much greater purification effect for impurities from group I11 rich liquids than from stoichiometric melts. The disadvantage of course is that crystallization occurs under conditions of constitutional supercooling, which can result in trapping of the impurity-rich group I11 element in the solid. With the availability of purer starting elements, formation of the compounds from stoichiometric melts is now more usual. Nevertheless, further purification is generally required, and is now often achieved by pre-pulling charges using the liquid encapsulation technique. InP having carriers/cm3 can be produced in this way. A similar purification procedure for GaP can be used. The current commercial demands on GaP are somewhat less than on InP since it is either used as doped material or as a substrate on which active layers are grown. There is clearly scope for the development of further purification procedures for both these compounds. 1.3.3.4 11-VI Compounds The state of development of the 11-VI compounds is significantly behind that of the 111-V compounds even though they have a much longer history. Many of the 11-VI compounds, especially the higher energy gap oxides, sulfides and selenides, are not accessible by melt growth tech-

1.4 Technical Constraints to Melt Growth Techniques

niques and as a consequence there is a much greater emphasis in the use of vapor growth techniques to grow these difficult compounds. Our knowledge of the use of vapor growth as a purification technology is primitive. There is no equivalent to zone refining. Hence there is a more general tendency to rely on the use of elements that have been purified chemically or by zone refining. The elements Hg, Cd and Te, components of the exceptionally well developed infrared detector material Hg, -$d,Te, are now available as very high purity elements as a result of multiple zone refining technologies (Cd and Te) and distillation techniques (Hg). Hence compounds of these elements are prepared in situ by direct reaction. Most of the other elements Zn, Se and S although currently available in conventional high purity form are generally not as pure as the detector materials and do not form very pure semiconducting compounds. Zone refining of the IILVI compounds is not efficacious because of the volatility of both the group I 1 and group VI elements as well as the compounds themselves. Hence there has been little development of conventional zone-refining technology for the compounds. However, a related zone-refining technology called the traveling heater method (THM) or sometimes the traveling solvent method has attracted much interest and development for the 11-VI compounds. In the traveling heater method a molten zone is moved through the ingot as in zone refining, but in THM the zone comprises a solvent of Te or Se. Thus the compound dissolves at the leading edge of the zone and crystallizes out at the trailing edge. This has two advantages. Firstly, it reduces the temperature of crystallization significantly below the melting point of the

11

compound, thus markedly reducing the vapor pressure of the components of the compound, effectively eliminating evaporation. Secondly, it provides a group VI rich solution in which impurities are exceptionally soluble, a condition which results in the crystallization of a very pure compound. Because of the reduced growth temperature it is also possible to eliminate sub-grain boundaries. The technique, however, has not yet been developed to grow large completely single crystals. The process has been exploited particularly by Triboulet (1994) and the CRNS Bellevue group for the preparation and purification of Hg, -.Cd,Te, Hg, - .Zn,Te, CdTe, HgTe and ZnTe, as well as CdMnTe. It clearly has scope for the preparation and purification of ZnSe and various alloys of the compounds. The potential disadvantage of the technique is that the crystallization occurs under conditions of constitutional supercooling and solvent trapping can occur and give rise to group VI rich precipitates tokether with impurities. Nevertheless it would appear that by optimizing the temperature gradients and the gradient of constitutional supercooling (see Sec. 1.7.4) the worst effects of solvent trapping can be avoided.

1.4 Technical Constraints to Melt Growth Techniques The processing of compound semiconductors by melt growth techniques both for purification and crystal growth is generally much more difficult than the processing of Ge because of constraints imposed by the properties of the materials. Some of the significant properties which lead to constraints in the use of melt growth and related processing are listed in

12


Table 1-1. Material properties of main semiconductors. Compound

Melting point ("C)

Vapor pressure at M.Pt.(atm)

lnSb GaSb lnAs GaAs InP GaP HgSe HgTe CdSe CdTe

525 712 943 1238 1062 1465 799 670 1239 1092

4 x 10-8 1 x 10-6 0.33 1.o 27.5 32

ZnSe ZnTe Ge Si

1526 1300 960 1420

0.5 0.6

12.5 0.3 0.65

CRSS at M.Pt (MPa)

0.7 0.36

0.2

0.70 1.85

Table 1-1. Consideration of a wider range of properties, chemical reactivity, melting point, vapor pressure, critical resolved shear stress and ionicity are important in understanding the suitability, or more often, the unsuitability of a particular technology.

1.4.1 Chemical Reactivity Although not specifically listed in Table 1-1, chemical reactivity is an important constraint in all processing. The main problems arise from the reactivity of the molten semiconductor with the container or the gaseous environment. In this respect container materials have proved to be the dominant source of contamination for compound semiconductor melts. Vitreous silica is widely used as a crucible or boat material and is essentially stable against attack from the lower melting point materials like Ge (937"C), InSb (525°C) and GaSb (712°C). But, for higher melting point materials there is gen-

References

Muller and Jacob (1984) Muller and Jacob (1984) Van der Boomgaard and Schol(l957) Arthur (1967); Thomas et al. (1990) Bachmann and Buhler (1974); Thomas et al. (1990) Nygren et al. (1971) Mayer (1984) Harman (1 967); Strauss (1971) Bassam et al. (1994); Lorenz (1967) Isshiki (1992); Strauss (1971); Balasubramanian and Wilcox (1992) Isshiki (1992); Lorenz (1967) Isshiki (1992); Lorenz (1967) Thomas et al. (1990) Thomas et al. (1990)

erally contamination with silicon due to the reduction of the SiO, by the melt, in the case of GaAs (1238°C) it is typically above the part per million (ppm) level in the crystallized material. Pyrolytic boron nitride PBN can be used to overcome this problem and is well suited to the growth of 111-V compounds since it is a 111-V also and does not appear to give rise to electrically contaminating impurities. It is however expensive. Graphite is also used since it is stable in an inert atmosphere and does not appear to directly cause electrically active doping by contaminating melts. Graphite will react with silica at high temperature, but at lower temperatures ( ~ 9 0 0 ° C )it is a very useful material and is used as a slider boat material in liquid phase epitaxy (LPE) and as a boat material for 11-VI compounds. But, carbon can be electrically active as an acceptor in GaAs for example. It can be introduced on an As vacancy site via CO under Ga-rich growth conditions, hence the importance of removing 0, and H,O.

1.5 Crystal Growth

Another potential source of impurity contamination are the impurities such as S etc. in the graphite. These can generally be removed by vacuum heat treatment at very high temperatures ( > 1500"C). Graphite is a very useful material but since it varies in quality must be used with care. The gaseous environment is also a major cause for concern. Processing in vacuum is possible, but the volatility of the group V, I1 or VI components needs to be taken into account. This is discussed later. All the melts and compounds oxidize readily and it is vital to remove all sources of oxygen such as 0, and H,O from the source materials and the environmental gases. Pure H, or forming gas are very effective reducing agents and will remove oxides readily at temperature. Hydrogen does however react to form unpleasant poisionous 'hydrides and extreme precautions need to be taken to avoid leaks not only with pure H, but also with forming gas (N,/H, mixture). Pure inert gases such as N, ,A or He are safer and consequentally are more frequentally used.

1.4.2 Melting Point The melting point affects the choice of crucible material, and with it the extent of chemical reaction. Also, above about 1000 "C radiation fields tend to dominate thermal distribution, creating design problems and the need for radiation baffles. Also, above 1100-1200°C silica starts to soften, which generally means it needs to be supported by another material such as graphite.

1.4.3 Vapor Pressure Vapor pressure is probably the most crucial parameter affecting melt growth technologies. The long delay in the development of GaAs, InP and GaP is attributable

13

in part to the problems posed by the vapor pressure of the group V component generated on melting these compounds. Thus a melt of these materials will rapidly lose its group V component unless there is a pressure of the group V component above the melt at least equal to the equilibrium vapor pressure over the melt. Two types of technology have emerged to deal with this problem: hot wall technology and liquid encapsulation (see Sec. 1.5).

1.5 Crystal Growth The main techniques for growing crystals of compound semiconductors can conveniently be grouped into four categories: horizontal growth, vertical growth, crystal pulling and liquid encapsulated Czochralski (LEC) pulling. Although this classification differentiates the techniques by the physical disposition of the different growth processes it is very important to appreciate that each technology gives rise to different crystallization conditions which affect the quality and efficiency of production for different 111-V compounds. Factors such as the ease of seeding for crystal growth, crystal shape, twinning, the effect of growth in a constrained volume, temperature gradients, visibility and the economics of production and ease of automation are critical factors in the choice of a particular technology. The suitability of these techniques for particular compounds, which are listed in Table 1-2, have evolved with time and experience. They have all been refined for particular applications and are still undergoing both research and commercial development. Their application to the growth of particular compounds will be discussed in later sections.

14


Table 1-2. General applicability of growth techniques. Technique: Compound

Zone melting horizontal Bridgman

VGF vertical Bridgman ~

InSb GaSb InAs GaAs InP GaP HgSe HgTe CdSe CdTe ZnSe ZnTe HgS ZnS CdS

*** *** *** *** * * *

***

Conventional vertical pulling

~~

Liquid encapsulation pulling ~~

P P P c*** : L*** c* : L** c* : L**

** *** ** *** ** **

*** ***

*** *** *** ***

Vapor growth ~~~

P P P P P P

P P

*** *** *** *** *** *** ***

The more stars, currently the more appropriate the technique. P potentially applicable;C: conventional VGF; L: LEC VGE

a

1.5.1 Horizontal Growth

Horizontal growth (HG) is used here to cover all the horizontal crystallization techniques. They represent a subset of the zone-melting technologies described by Pfann (1966). A typical horizontal growth arrangement is shown schematically in Fig. 1-2 and discussed more fully in relationship to the growth of GaAs in Sec. 1.6.2. The growth of a single crystal can be carried out by controlled freezing of an ingot of molten semiconductor in a boat. The singularity of the ingot is achieved either by relying on self-seeding or through the use of a single-crystal seed which initially contacts the melt. The technique is often referred to as the horizontal Bridgman technique when the ingot is withdrawn from a furnace. The furnace can of course be moved relative to the ingot and this can be beneficial in that there may be less mechanical disturbance to the ingot and the crystallization process.

In the case of compound semiconductors the main problems generally concern the need to accurately control the thermal profiles, hence the movement of large furnaces tends to be undesirable and a combination of power control and the movement of small independent heaters is generally preferred in order to carry out the crystallization process. These benefits can also be achieved by using furnaces with independently controllable windings so arranged that the thermal profile can be moved. The attraction of HG stems from its relative simplicity and ease of automation. The method can be applied readily to compounds that can be processed in vitreous silica, that is, for compounds melting at temperatures less than about 1250"C having vapor pressures at the melting point not significantly in excess of one atmosphere. An advantage of the HG is that it can be used to prepare the compound from the elements as an ingot which can then be subsequently zone refined in the same ap-

---

15

1.5 Crystal Growth

G

F

~ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 l r

E

\

Figure 1-2. Schematic of a conventional horizontal growth apparatus used for the preparation and zoning of I l l - V compounds. The ingot in the boat B is contained in a sealed tube A. C is the boat used to hold the volatile component prior to its distillation into the group Ill element in A in order to form the compound. D is an anticonvection baffle and E the tube support for the thermocouples H and their support tube. F is a multiple section furnace. G is the traveling heater for the zone formation and movement.

paratus. Such an ingot can also be grown as a single crystal and even zone refined as a single crystal without taking it from the same apparatus. In situ compounding of the elements can also be used in vertical pressure pulling systems (Sec. 1.6.2), but the ability to zone refine in a horizontal system is a distinct advantage when superpure elements are not available. An important advantage of the H G technique is that its design readily lends itself to the establishment of low temperature gradients at the solid-liquid interface without creating a control problem. This contrasts with the situation in the pulling process where relatively high temperature gradients are needed to maintain control of the shape of the crystal. Low temperature gradients are extremely important in minimizing stress induced slip on crystallization and hence in minimizing dislocation formation. In the case of the H G growth of GaAs it is possible to grow low dislocation density material, typically

-

around lo2 dislocations/cm2, a factor of 100 less than currently found in routinely grown LEC vertically pulled crystals. This is very important for laser diodes based on GaAs, where even a single dislocation can readily bring about device failure. There are, however, disadvantages to the horizontal techniques. These can be of a scientific fundamental nature, such as constitutional supercooling or stress, or they can be preparation-related and involve, for example, growth orientation, contamination, or shape. One of the fundamental problems which is not widely recognised is constitutional supercooling, which can occur as a result of a nonstoichiometric melt due to inaccurate vapor pressure control. This can be especially troublesome with low temperature gradients as is analyzed later in Sec. 1.7.4. The most troublesome problems occur as a result of the contact of the melt and the grown crystal with the boat. The long

16


period of contact can be a source of impurities by reaction with the boat. Silicon as noted previously is a major problem with GaAs, but also the diffusion of impurities through the silica with the higher melting point compounds can also result in crystal contamination. Misnucleation from the walls of the container can give rise to twinning, grain boundaries and more often polycrystallinity. Also crystallization in a confined shape with materials like 111-V compounds which expand on freezing, especially if combined with localized sticking, will inevitably lead to stress, slip and dislocation formation. However, provided nonwetting surfaces are used for the containing boats and a nonconfining boat shape is used, this problem can be minimized. Most of the disadvantages are qualitative rather than absolute. They detract from the versatility and universality of the technique. In certain cases they may not be significant, such as in the case of the growth of low resistivity GaAs, for example, for especially for material which is subsequently sliced and diced for the fabrication of small discrete devices such as laser diodes. However, for integrated circuit applications where large area uniformity is crucially important HG is unattractive. Indeed the D-shape of HG ingots alone appears to have ruled them out for integrated circuit applications. Also the growth of very large cross section ingots as single crystals is fraught with difficulty. 1.5.2 Vertical Growth

Crystallization of ingots in a vertical container by the Stockbarger or vertical Bridgman techniques used to be associated with the growth of high-quality singlecrystal optical materials like CaF, . But, in the last few years the technology has been

refined and developed as a vertical gradient freeze technique for the growth of GaAs, InP and GaP (Gault et al., 1986; Clemens et al., 1986; Bourret, 1990). The relatively recent application of the VGF technique to the growth of GaAs occurred in response to the need to find a cost effective solution to the production of uniform GaAs wafers compatible with integrated circuit technology. Here there is a requirement for circular wafers having precise dimensions and very good electrical uniformity. “Conventional” wisdom would consider that crystallization in a vertical rigid container would give rise to unacceptable stress due to the expansion of the liquid GaAs on freezing. In the event this has not apparently been a problem. The growth process is fairly straightforward and is illustrated in Figs. 1-3a and b. In the study by Gault et al. (1986), which was a development of earlier studies (see review by Bourret, 1990), the VGF growth of large diamater Gap, InP and GaAs was reported. No B 2 0 3 encapsulant was used. The type of apparatus is illustrated in Fig. 1-3a. However, it appears that for the reproducible growth of GaAs it is necessary to use a B 2 0 3 encapsulant in a BN crucible (Bourret, 1990) such as that illustrated in Fig. 1-3b. The B 2 0 3 , which is now more generally used for InP, is not only a more effective encapsulant, making for a safer and simpler system, but the nonwetting characteristics of the GaAs melt with respect to the container wall reduce the twinning probability. The vertical gradient freeze technique involves the controlled freezing from the bottom up of a molten charge of material held in a tube-shaped vertical container. The freezing is best brought about not by the movement of the furnace relative to the tube, but by the use of a furnace comprising separate independently controlled

1.5 Crystal Growth

+A

17

--A

--

B

-C

--

C

-D

--D

-E

--

LE

--

E

--

F

--

G

.-

H

.-

L

-B

-F

-G II

I

-M -J

-K -L

-M

Figure 1-3. Schematic diagrams of crucibles used in the vertical gradient freeze technique, (a) “Conventional” VGF showing compound F, melt E and separate holder J containing group V component K at a controlled temperature in order to maintain sufficient pressure of V to avoid the dissociation of the compound. Plug B allows pressure equilibration between the crucible and the outer chamber. Loss of group V into the outer chamber is inevitable even when Pc > pd and is one of the drawbacks of the technique. A, furnace; C, BN crucible; D, main containing vessel; G, seed: H, crucible support; I, gap for group V transport; J, crucible for holding V; K, source of group V; L, base support; M, holder. (b) Liquid encapsulation VGF with Pc> pd; symbols have same meaning as above. B,O, encapsulant LE covers the melt and prevents the loss of the volatile component.

18


heating elements. Adjustment of the heating elements controls the position of the thermal profiles so that the movement of the liquid-solid interface can be raised smoothly to bring about the crystallization of an ingot. The technique provides two important growth conditions. It naturally lends itself to low temperature gradients, which in turn favor low dislocation densities. And, secondly, it provides an ingot of ideal shape of the required diameter. Provided the interface shape is flat or at least the growth surface is slightly convex the expansion problem on freezing does not appear to be serious and any stress can be annealed out. The main problems appear to be those involving design difficulties of the thermal furnaces, the choice of boat material, BN is generally used, and the choice of conditions which allow seeding and the growth of [loo] crystals without twinning. The ingots are usually encapsulated with B,O,. Whether the technique will supersede the LEC technique for the growth of GaAs is an open question. This can only be effectively assessed when commercially sensitive information on single-crystal growth yield comes available. 1.5.3 Crystal Pulling

The Teal and Little crystal pulling technique which was developed successfully for Ge was naturally tried for the 111-V compounds, but the problem of the volatility of the group V elements and their rapid loss from melts in the case of the arsenides and phosphides presented insuperable problems. The antimonides which have low dissociation pressures at their melting points can, however, be grown by any of the Ge-type semiconductor technologies. The crystal growth of the aluminum com-

pounds by either the horizontal or the vertical pulling techniques has never been developed because of the extreme reactivity of the A1 with traces of oxygen or water and with the silica boats. Any bulk material simply oxidizes in the atmosphere. The VP technique is illustrated in Fig. 1-4. The main factors affecting the design concern the type of heating, the crucible and the outer jacket. Heating can be by resistance heating or, for more versatility, induction-coupled RF power to a conducting crucible, generally graphite or a graphite support to a silica or PBN crucible. The outer jacket is usually silica and for strength reasons can only be used with internal gas pressures not in excess of about 2 atm. The growth of a single crystal involves lowering a seed mounted in a seed holder or chuck on the pull rod into a melt of the compound just above the melting point. After melting back a small amount of the seed, the seed-on process, the power to the melt is controlled so as to allow crystallization of the melt on the seed as it is gradually rotated and withdrawn from the melt. The shape of the crystal is controlled by the shape of the meniscus under the seed (Sec. 1.7.2). The whole process requires considerable operator skill and judgment. The growth can be automated by using a sensor to monitor the crystal diameter and provide feed back to the power control (Sec. 1.7.2). Constant diameter crystals are needed for producing standard sized wafers for device fabrication. This basic process can only be applied to the growth of compounds that have virtually no vapor pressure at the melting point. This is a very restrictive condition for the growth of compounds which generally dissociate near the melting point to some extent. In the case of the 111-V compounds and the 11-VI compounds the technology

1.5 Crystal Growth

rl

.i

n L J a

Figure 1-4. Vertical pulling apparatus for low pressure liquid encapsulation. The silica outer vessel N with viewing port J is held between end plates 0 and P. The induction heating coils couple into the graphite surround F mounted on Q. The seed A is fixed in the chuck on the pull rod K which rotates and moves through the bearing and seal L. The crystal C grows from the seed through a necking process at B and on withdrawal pulls out a layer of B,O, over its surface. Loss of the volatile group V component from the seed, crystal and melt is prevented if PG > 4.

19

is only really suitable for the growth of InSb and GaSb. As a consequence, considerable effort has been devoted to developing alternative technologies for the growth of compounds. Two types of technology aim to overcome the vapor pressure problem and loss of group V component. These are hot wall technology and liquid encapsulation technology, In hot wall technology the walls of the containing vessel surrounding the III-V compounds are kept sufficiently hot to prevent condensation of arsenic or phosphorus on the walls. This requires temperatures of 600 "C o r 700 "C, respectively, for the two elements. This condition is possible to apply in the case of horizontal crystal growth involving the use of a sealed silica tube but it creates serious technical problems in the case of a thermally complex vertical pulling apparatus since it requires the seals, pull rod and bearings, etc., to be heated and inert to the hot reactive component elements. Nevertheless, the problems of hot wall technology have been tackled by a variety of pulling methods with varying degrees of success. They are the syringe pulling and magnetic pulling methods, which have been reviewed by Gremmelmaier (1962) and Fischer (1970), and the pressure balancing technique, which has been proposed by Mullin and coworkers (1972). The principal problem is that of devising a pulling mechanism which prevents the volatile group V elements from being lost or from condensing of the on the walls of the system. Syringe pullers use a pull rod, generally ceramic, which is a close tolerance fit in a long bearing. Although such a seal is not perfect the loss of volatile elements can be minimized. The magnetic puller is a tour de force in which the whole ceramic pulling system contained in the pulling chamber is

-

-

20


kept above the condensation temperature of the volatile component. Translation and rotation are achieved by magnetic coupling to suitably sited and protected magnetic material on the pull rod. Neither syringe pullers nor magnetic pullers have achieved any significant following. They are expensive, technically difficult and not entirely satisfactory technologies. An alternative technology proposed and demonstrated by the author has been referred to as the pressure balancing technology (Mullin et al., 1972). This method overcomes loss of the volatile component up the pull rod by arranging for a liquid seal at the top of the bearing housing through’which the pull rod is pulled. The inside of the BN bearing has a screw thread so that rotation of the BN pull rod causes the B 2 0 3 liquid sealant to be “wound up” the shaft and kept in the upper reservoir. The inert gas pressure in the system is kept above the dissociation pressure and through the use of a u-tube gauge internal and external pressures can be kept the same. Of course the whole of the apparatus has to be kept above the condensation temperature of the volatile components. The pressure balancing technology works surprisingly well but was not developed and exploited because of the success of liquid encapsulation technology, which has transformed the whole of 111-V pulling technology for the arsenides and phosphides. 1S.4 Liquid Encapsulated Czochralski (LEC) Pulling Liquid encapsulation often referred to as the liquid encapsulation Czochralski (LEC) technique is illustrated in Fig. 1-4. The liquid encapsulation technique (Mullin et al., 1965, 1968; Mullin, 1989) avoids the need for hot walls and permits the use of

conventional pull rods. It is elegantly simple. It involves the use of an inert layer of transparent liquid, usually B 2 0 , , which floats on the surface of the melt, acts as a liquid seal and prevents the loss of the dissociating volatile component provided the pressure of external gas P , is greater than that of the dissociation vapor pressure P , of the volatile component. The encapsulant should possess additional properties. It should be immiscible with the melt and be unreactive towards it. But, most importantly, the encapsulant should wet the crystal and the crucible. Further, its viscosity and the temperature dependence of its viscosity should be such as to allow it to be drawn up with an encase the emerging crystal as a thin film of encapsulant. The latter property is desirable in order to prevent the decomposition of the hot crystal throughout the course of the crystal growing process after it has pulled clear from the layer of the encapsulant. Although many glass-like encapsulants have been tried only B , 0 3 and related mixtures fulfill sufficiently well these characteristics. 1.5.4.1 The Low Pressure LEC Technique For compounds that have dissociation pressures not in excess of about two atmospheres it is possible to apply the liquid encapsulation techniques using Ge-type crystal pulling chambers. For this low pressure liquid encapsulation technology it is possible to use an outer jacket of the growth chamber made of silica such as that illustrated in Fig. 1-4. Such a system would be suitable for the growth of InAs or GaAs (Sec. 1.6.2). 1.5.4.2 The High Pressure LEC Technique Silica growth chambers are not strong enough for compounds having high dissociation pressures ( > 2 atm) and steel or

1.6 Crystal Growth of Specific Compounds

metal pressure vessels are used. Pressure vessels have been designed for working upto 200 atm. The use of such steel pressure vessels has enabled the development of a unique technology which has been applied to the crystal pulling of InP and Gap, compounds which have dissociation pressures at their melting points of -27.5 atm and -32 atm respectively. The technology effectively simplifies the growth of these compounds so that the growth process is very similar to that of Ge except that an encapsulant is used and the pulling is carried out under a high pressure of inert gas in a steel pressure vessel. The process can be viewed directly via an optical window using a video camera. An example of a research system is shown in Fig. 1-5. The technical success of the LEC high pressure technology lies in the confinement of the chemically reactive elements such as arsenic and phosphorus to the region of the melt under the liquid encapsulant and out of contact with the chamber wall, the pull rod assembly, bearings seals, etc. Indeed the pressure chamber walls and the pull rod seals need only be capable of withstanding the inert gas pressure at relatively low temperatures, thus avoiding difficult design problems. Of course, the inert gas pressure must such that P, is greater than P, in order to avoid vapor loss. The overall effect of this technology has been to revolutionize the growth of these compounds, enabling them to be grown commercially.

1.6 Crystal Growth of Specific Compounds In discussing the crystal growth of specific compounds emphasis will be given to what is considered to be the most effective technique for general application. The main considerations under discussion will

21

Figure 1-5. 200 atm high pressure LEC crystal puller developed at RSRE showing water cooled steel pressure vessel and two optical ports for viewing, one fitted with a video camera. Below the steel pressure vessel is a large chamber containing the weighing cell for diameter control.

relate to the problem areas of diameter control, dislocations, grain boundaries, twinning and purity. A factor which can be important in the growth of compound semiconductors is the anisotropy introduced by the presence of two dissimilar atoms in the zinc blende lattice (Sec. 1.7.1). Thus the [ l l l ] direction where the surface terminates with group V atoms [some authors confusingly use the reverse designation: see discussion in Hulme and Mullin (1962)l differs in properties and behavior from the [TTT] which terminates in group I11 atoms. The designation [111]A or [111]B, where A and B represent the group I11 and group V atoms respectively, avoids ambiguity. The anistropy al-

22


so holds of course for all (hkl) versus (kH ) directions. This anistropy is important for all compounds but is particularly important in the case of the growth of the In compounds and is directly relevant to the problem of twinning. 1.6.1 InSb

Both the HG and the VP techniques are used for the preparation of single crystals of InSb. The former method is attractive for obtaining a controlled shape and the highest purity compound whereas the VP technique is more versatile and offers scope for growth in specific orientations. The compound can be formed by heating the elements together since molten In will dissolve Sb. Hence the horizontal technique is not required for preparing the compound. However, the technique does offer scope for the growth of single crystals which can be zone refined in order to obtain very high purity uniform crystals. It is particularly important with InSb to avoid growth in the [Ill] direction since (111) facet formation gives rise to the facet effect and can cause very nonuniform crystals. The HG technique also enables single crystal zone refining in growth directions, which minimizes facet formation on the growth surface at the solid-liquid interface, such as the [211]Sb or [311]Sb orientations. The technique has been used successfully for the growth of high purity p-type single crystals for detectors but requires considerable care in control of the growth conditions in order to avoid twin formation. Crystal pulling using a Ge-type puller is a more versatile technique and is probably now used more frequently but it does suffer from the same twinning problems as already discussed. The (11 l)Sb facet is more stable, requiring a greater supercool-

ing for nucleation and growth on its surface than the (TTT)In facet. As a result, twinning tends to be more probable on the (1 11)Sb facet when it is present at the edge of crystals, where it is subject to liquid motion, exposure to the gas environment and greater temperature fluctations than when it is at the center of a pulled crystal. Thus growth in the [I 111Sb direction is least likely to cause twinning even though there is a central (111)Sb facet whereas growth in the reverse [TTTIIn direction has the greatest likelihood of twinning since there is then the possibility of the formation of three (111)Sb-type edge facets. Although growth in the [I 111Sb direction offers the greatest opportunity to avoid twinning and the preparation of completely single crystals it is not to be recommended for undoped crystals or for doped crystals with dopants which exhibit a marked facet effect since the usual capricious size behavior of the central or principal (111)Sb fact can give rise to very nonuniform crystals. Growth in the [211]Sb or [311]Sb direction is usually recommended. Twinning and trapezoidal shape problems for the crystals may ensue, but by careful control of temperature gradient and temperature stability these effects can be minimized. 1.6.2 InAs and GaAs

The growth characteristics of both of these compounds are similar and both can be grown by the horizontal technique and by liquid encapsulation. However, the R&D carried out on GaAs vastly exceeds that on InAs. All the early work on these compounds involved their preparation in an HG apparatus (Sec. 1.5.1) in which As was distilled into the liquid group I11 element contained in a boat. The temperature of the liquid alloy was raised to the melting


point of the compound as the composition of the liquid approached stoichiometry. Finally the melt was progressively crystallized to form an ingot. A fairly high yield of self-seeded single crystal ingots could be obtained in this way. As an alternative a single-crystal seed at one end of the boat could be used to give controlled nucleation, but this is not a simple process and requires considerable development. Although crystals can be grown in low temperature gradients, resulting in low dislocation densities, scaling up the process to cut circular sections is not an efficient or very successful process. It is understandable then that the advantages of the VP technique using the liquid encapsulation technique has resulted in LEC becoming the industry standard for the growth of GaAs and InAs. The role of liquid encapsulation was considerably enhanced by two significant developments: in situ compounding and the production of semi-insulating (SI) GaAs without recourse to Cr doping. In situ compounding of the elements Ga and As was made possible by the introduction of steel pressure vessels. Liquid As at the melting point of GaAs 1238°C has pressure of -80 atm. Thus progressively raising the temperature of a crucible containing a charge of elemental Ga and As under a layer of B,O, in a pressure vessel containing inert gas at 100 atm to a little in excess of 1238O C is a convenient way of of forming a GaAs melt whilst avoiding significant loss of As. This in situ compounding has eliminated the need for compounding using a horizontal apparatus, a significant simplification. An additional important development was the use of BN crucibles. This had two effects, it avoided contamination by Si, which is endemic with the use of SiO, crucibles, thus giving a convenient very

-

23

rapid processing route to the formation of very high purity GaAs charges for LEC growth. Also, and somewhat inadvertently, it provided a route to the production of SI GaAs. Swiggard and coworkers (1979) reported that GaAs prepared in BN crucibles generally had very high resistivity and furthermore the electrical properties of the product were relatively stable to the type of heat treatments needed to anneal out ion implantation damage. This was a very important result in connection with the use of GaAs for integrated circuits since SI material provided an excellent insulator on which integrated circuits could be fabricated using ion implantation. A complete explanation of the reasons for the formation of SI GaAs and for its semi-insulating character is the subject of continuing scientific debate which is beyond the scope of this article. However, the materials science of the processing of SI GaAs is important. It is evident that the SI properties are fundamentally connected with the EL 2 center, which is a complex defect involving an As antisite, that is, As on a Ga site. EL 2 is a well characterized electron trap 0.75 eV below the conduction band. In detailed studies it has been shown that the acceptor carbon combines with the EL 2 donor to control the resistivity of the GaAs. From a processing point of view a critical preparation parameter was shown to be the melt stoichiometry (Holmes et al., 1982). Thus the As atom fraction in the melt needed to be greater than 0.475 in order for the resulting crystal to be semi-insulating. This result is qualitatively consistent with the concept of an As antisite being responsible for the SI properties. The LEC technique is now a well established industrial process for the production of 2 inch and 3 inch diameter GaAs either as doped n-type material for use as sub-

24


strates in the fabrication of devices such as light emitting diodes or as SI material for ion implantation and the fabrication of integrated circuits. However, in the last few years the VGF technique has assumed increasing importance as a means of preparing SI and doped GaAs crystals. As noted earlier the VGF technique involves the progressive crystallization of a molten charge in a vertical crucible by continuous adjustment or programming of the thermal profiles. It is a simple concept but its practical implementation is particularly demanding because of the lack of visibility and inability to follow exactly what is happening in the growth process and identify the onset of defect formation. This is a consequence of the use of nontransparent BN crucibles. Pressure vessels, often used for safety reasons, can also be a hindrance to visibility. Nevertheless, the quality of VGF crystals can be as good if not better than LEC crystals, indeed their dislocation densities are generally lower and more importantly uniformly distributed, a consequence, as with the horizontal technique, of the design resulting in low temperature gradients. The major unknown factors in both techniques are the average reproducible yields of single crystals that can be obtained. Yield is an overriding consideration in any growth process in the assessment of its commercial viability. One of the major factors which affects yield is twinning. The precise cause or causes of twinning in any growth run is difficult to identify, and whilst the general process is understood, what exactly brings about a twin misnucleation, be it an impurity, temperature fluctuation, foreign body or facet size, is rarely identifiable as a cause and effect relationship. As a result, trial and error development effort is normally expended in finding suitable twin-free growth conditions.

Twinning can be a serious problem in the VGF process not least because of the need to use [IOO] seeds in order to meet industrial demand for (100) wafers. Here there is the additional problem of seedingon blind. The lack of visibility is a big handicap in VGF. Thus unlike the situation in the LEC process it is not possible to identify, for example, the causes of poor crystal quality and or twinning except by inference after growth. With LEC, twins are generally visible and crystals can often be regrown to eliminate them. Nevertheless, VGF is now a commercial process for GaAs and one must assume that sufficiently twin-free conditions can be developed in the growth process. General crystal growth experience would suggest that B 2 0 3 quality, boat material, interface shape and thermal stability would need to be carefully controlled. Indium arsenide has similar processing problems to GaAs, although here the melting point is lower and the vapor pressure at the melting point is -0.3 atm. But there is very much less commercial interest in InAs and only the horizontal growth and LEC techniques appear to be used. Twinning is possibly an even more troublesome problem with InAs than with GaAs. The problem is multiple laminar twinning. Again its origin is uncertain, although it is possible to develop twin-free growth conditions. 1.6.3 InP

The application of the concept of liquid encapsulation to the growth of 111-V compounds was initially reported for the growth of InAs and GaAs by Mullin and his colleagues (1965). The use of B 2 0 3 is well known metallurgically and has a long history in protecting molten metals from oxidation and vapor loss. In the case of the IV-VI semiconductors Metz et al. (1962)


used B 2 0 3 in the crystal growth of volatile compounds of PbTe and PbSe. However, the most significant advance in the III-V compounds came with the application of liquid encapsulation to the concept of high pressure pulling in steel pressure vessels. Liquid encapsulation high pressure pulling was initially applied to the growth of InP and GaP (Mullin et al., 1968) and represented a breakthrough in the growth of these materials as high-quality single crystals. There is now considerable commercial interest in InP due in part to the InP-based structures used in the fabrication of very high quality lasers. It is becoming the laser material par excellence. The principal method of preparation of the raw material uses a pressurized horizontal technique involving distillation of P4 into a boat of molten In as discussed earlier. Crystal growth using the LEC technique is often carried out using a pre-pulled charge of InP. The LEC growth of InP has analogous problems to those of GaAs with respect to temperature gradients and the loss of the group V component. However, in addition, twinning of the crystals during growth is more of a problem. The effect of evaporation from the surface of the hot crystal after it has emerged from the B 2 0 3 is more troublesome than it is with GaAs even though the absolute temperatures are less. The loss of P, from the crystal as it merges from the B 2 0 3is connected, firstly, with the very high gas velocities near the crystal surface, and secondly with the temperature of the crystal surface, which is controlled by the temperature gradients. The high gas velocities are caused by Rayleigh convection driven by the high pressure, large temperature differences and relatively large dimensions of the Benard cells in the growth chamber. Convec-

25

tion that can occur in pressure pulling systems correlates with the magnitude of the Rayleigh number R , , which is given by (Chesswas et al., 1971)

ATgd3P2

(1-2) TKO vo where AT is the temperature difference of the depth of volume of convecting gas (the temperature difference between surfaces driving the Benard cell), and T is an average gas temperature, d is the depth of volume of convecting gas, KO is the thermal diffusivity, v o is the kinematic viscosity and P is the gas pressure. Note that R, depends on the square of the gas pressure, the cube of d and the temperature difference between surfaces driving the convective Benard cell. It is important therefore in the pulling systems to avoid large free volumes with large temperature differences between the hot and cold surfaces. The temperature gradient effects are basically similar to those encountered in the LEC pulling of GaAs. Attempts to reduce the temperature gradients in order to reduce the dislocation density cause a slower rate of fall off in surface temperature of the crystal surface above the layer of B 2 0 3 with consequent loss of the B,03 encapsulating film. The very high dissociation pressure of the InP also exacerbates the problem of P, loss. The loss of P, results in the deterioration of the surface quality of the InP involving the formation of In droplets which can move into the bulk InP under the applied temperature gradient by temperature gradient zone melting (TGZM) towards the solid-liquid interface. The need for low dislocation density is very important for device applications and there is an imperative need to reduce them well below the norm of lo4 to 105cm-2 generally found in undoped and lightly

R,

=

26


doped material to lo3 or nearer lo2 cm-2 for many device applications. Attempts to reduce the temperature gradients and the dislocation desities have been reported by Hirano et al. (1992). They used a system of double heat shields or baffles in order to reduce the temperature gradients. This was done in a way that minimized P4 loss presumably by minimizing gaseous convection. 1.6.4 11-VI Compounds: General

The status and development of 11-VI crystal growth is very different to that of the 111-V compounds. Most strikingly there is no successful pulling technology and it is only in the last few years that large-area CdTe and Cd,Zn - ,Te singlecrystal material has become available. The reasons for this are partly historical and partly materials property related. A significant R&D effort was deployed on the 11VI compounds in the 1950s and 1960s, but following the lack of any significant commercial device promise the major research companies stopped work on the 11-VI compounds. The enthusiasts continued, but the problems were formidable and progress was slow. In this phase of development, bulk vapor growth of the 11-VI compounds was the most successful crystal growth technology. However, in the early 1980s there was a resurgence of interest in the 11-VI compounds partly at least following the availability of the newer low temperature epitaxial technologies which were developed in the 1970s and 1980s for the 111-V compounds. The constraints to the melt growth of the 11-VI compounds are fundamentally similar to those of the 111-V compounds but practically very much more difficult to overcome. All the 11-VI compounds exert significant vapor pressures of their compo-

nents at the their melting points. ZnS and CdS have inaccessibly high melting points for melt growth. The more ionic nature of the compounds compared with the 111-V compounds gives rise to low critical resolved shear stresses and ease of deformation of the compounds. The high point defect concentrations of the compounds near the melting points conspire with the high diffusion rates in the 11-VI compounds, they are orders of magnitude greater than in the 111-V compounds, to allow polygonization of dislocations and the formation of grain boundaries and especially subgrain boundaries. The latter are virtually unknown in 111-V compounds. Liquid encapsulated pulling cannot be used to overcome the volatility of the compounds since B20, is partially miscible with 11-VI melts. Even if LEC could be used, the ease of deformation would probably limit the value of the technology. The emergence of 11-VI epitaxial device structures stimulated new developments in the crystal growth of the 11-VI compounds. One can readily identify requirements which were and still are responsible for creating the need for this work: bulk Hg,-,Cd,Te for 3-5pm and 8-14pm detectors, CdTe and Cd, -,Zn,Te substrates for epitaxial Hg, -,Cd,Te and ZnSe for blue light emitting diodes and lasers. 1.6.4.1 Bulk Hg, -,Cd,Te

Research on mercury cadmium telluride (MCT) has never waned since its discovery and it is still an active topic of materials R&D. Three main bulk techniques have been developed, the vertical Bridgman technique, the American quench anneal technique, an equivalent UK technology called the cast recrystallize anneal (CRA) technique and a traveling heater technology*


The vertical Bridgman technique involves sealing the pure elements in a thickwalled ( 3 mm) silica tube, a requirement needed to handle the Hg pressure, which can exceed 20 atm for melts used in the preparation of Hg,,,Cd,,,Te. After melting and mixing in a rocking furnace, the charge is frozen as an ingot and transferred to a VB apparatus where it is again completely melted and then slowly crystallized by withdrawal from the furnace. The resulting ingot has a composition gradient which varies from an x of 0.3 to less than 0.1 8 depending on the start composition. Much effort has been devoted on devising controlled mixing schemes to maximize the yield of x=0.2 and 0.3 detector material. These attempts have included work on the accelerated crucible rotation technique (ACRT), which involves increasing the rotation of the crucible in one direction from rest, slowing it down, and then repeating the operation. This can then be carried out in the opposite direction, but this is not essential. A great deal of study has been carried out by Capper and his colleagues (1994) at Mullard/Philips Research Laboratories (now GEC-Marconi) on this technology with very good results. The melt mixing conditions have attracted much study and whilst a great deal has been discovered the interactions between the complex transient Couette flow the spiral shearing and the Eckman flows across the solid-liquid interface are still not understood. The need to prepare very uniform MCT has resulted in the development of a unique technology, that of quench anneal (QA) or CRA. The method involves rapidly casting a melt of the appropriate MCT compositions in order to produce a macro uniform solid. On a micro scale, however, the material is extremely nonuniform a consequence of the dendritic growth as

-

-

27

well as the effects of constitutional supercooling. Advantage is then taken of the very high interdiffusion in these compounds and the material is recrystallized in a temperature gradient. This gives uniform MCT but also a high acceptor concentration, which equates to the high Hg vacancy concentration. This is eliminated by a final Hg anneal at low temperature. This is an astonishingly well developed technology, a consequence of support from a military infrared detector programme. The third bulk technology is the travelling heater method (Triboulet, 1994), which was described in connection with the purification and preparation of MCT in Sec. 1.3.3.4. This technique is also used for the growth of Zn, -,Cd,Te an alternative to MCT as a detector material. Material with very uniform x can be grown but the extent of material development is confidential and not available. Although bulk grown MCT is still used it is rapidly being superseded by liquid phase epitaxy (LPE) and by metal organic vapor phase epitaxy (MOVPE) and the less developed molecular beam epitaxy (MBE). These epitaxial technologies require highquality substrates which is the main reason for the extensive development of CdTe and Cd - ,Zn,Te.

1.6.4.2 CdTe and Cd - ,Zn,Te The most developed technology for these materials is the vertical Bridgman technique, where 2 inch and 3 inch diameter crystals, principally of Cd, -,Zn,Te, for use as substrates for MCTZ are under development. Again the technique involves the withdrawal of a molten charge of material from a furnace. The growth of both CdTe (Rudolph, 1995) and Cd, -,Zn,Te (Sen and Stannard, 1995) have recently been reviewed. The major

28


problems affecting the production of highquality single crystals are the avoidance of twins and both large and small angle boundaries. Tellurium precipitates cannot be avoided during growth but can be eliminated by a post-growth anneal in Cd vapor. The unequivocal correlation of the causes of the defects with the growth conditions is difficult to establish but it would appear that the main requirements for good growth are a flat to convex growth surface (relative to the solid) together with low axial and radial temperature gradients. The use of too low an axial temperature gradient can cause a condition of constitutional supercooling and hence a compromise value needs to be selected. Naturally a stoichiometric melt is needed which strictly requires a controlled separate Cd vapor source. However, since the effective distribution coefficient of Zn is 1.3 its segregation can also result in a condition of constitutional supercooling and hence it is important to grow ingots slowly to give time for rejected solute to diffuse into the melt and not build up as a solute boundary layer. The horizontal growth technique has also been developed over the last few years to grow high quality CdTe and Cd, -,Zn,Te. Crystals allowing the selection of single crystal sections greater than 2.5 inch in dimension have been grown from 4 kg ingots (Liao et al., 1992). Larger systems are under development. Seeds are mounted in a raised section at the top of the boat. Seeded growth propagates freely across the top of the surface of the liquid, resulting in the formation of large singlecrystal areas. There is very little detailed information available on the reasons for the good growth other than it is important to avoid propagation from the multiple grains which can be initiated by growth

nucleated on the bottom silica surface of the boat.

1.6.4.3 ZnSe The very high melting point of ZnSe, 1526 "C, makes the vertical Bridgman technique very difficult and most studies have been carried out using vertical gradient freeze technology. But neither of these melt growth techniques give really good quality crystals. Significantly, using a bulk seeded physical vapor transport technique better ZnSe crystals have been obtained by Cantwell et al. (1992). This method is now used by Eagle Picher as a production method. The technique uses 2 inch diameter seeds at either end of a quartz tube. A charge is situated half way between the seeds and is transported to the seeds using an appropriate temperature gradient. The growth of up to 2 inches of crystal has been reported. Very good quality ZnSe having etch pit densities of - 5 x lo4 cm-' has been grown. It is evident that growth at temperatures below the melting point are very important for ZnSe. Indeed bulk vapor growth could be the technology of the future for the 11-VI compounds.

1.6.4.4 ZnS and CdS The very high melting points of ZnS and CdS mean that melt growth is not possible. As a consequence considerable effort has been devoted to the development of vapor growth techniques for these compounds. A variety of physical vapor transport arrangements have been attempted. Probably the most successful has been the PiperPolich technique (Piper and Polich, 1961). This is illustrated in Fig. 1-6a. It uses a tube having a coned tip. The charge can first be transported by an appropriate temperature gradient away from the tip. Growth is achieved by physically moving

1.7 Fundamental Aspects of Crystal Growth

G

A

I

29

B 1

I

Figure 1-6. Schematic illustrations of vapor growth techniques. (a) Piper-Polich technique showing the growth crucible A supported by an outer jacket B mounted inside the furnace F. Movement of A relative to the heater (thermal profile) causes vapor transport of the charge G and its crystallization in the cone of the crucible. (b) Controlled vapor pressure method; growth crucible A has a long side tube D containing the elemental source E which controls the vapor pressure of the more volatile component; note seed crystal C and charge G and thermal profile.

the tube so that the tip sees a progressively lower temperature than the charge. A single crystal can be grown from the tip. An important factor in the growth of most 11-VI and other compounds is the necessity to maintain similar vapor pressures of both components during growth. This requirement can be fulfilled by using a separate source of the more volatile component. Its vapor pressure can then be independently controlled and adjusted to that of the other component. The concept is illustrated in Fig. 1-6b. A major problem with this and all the other earlier vapor growth technologies is that the crystal grows against the silica tube, often sticking to it. On cooling, differential contraction between the crystal and the tube causes strain and stress, resulting in the introduction of dislocations. Attempts have been made to develop freegrowing systems for CdTe and other 11-VI

compounds in which the crystal grows out of contact with the tube but it is not an easy technology and very carefully designed thermal systems are required.

1.7 Fundamental Aspects of Crystal Growth The purpose of this section is to provide a brief insight into the origin and mechanism of those dominant phenomena which are of practical importance in the processing of compound semiconductors and which can affect crystal quality and perfection. Only the significant aspects of structure, vapor pressure, temperature distribution, diameter control, facet effect, anisotropic segregation, twinning, solute distribution, constitutional supercooling, dislocations and grain boundaries will be considered.

30


1.7.1 Structure

Germanium and Si have a simple diamond cubic structure, which is centrosymmetric, and as a consequence there are no significant growth anisotropies. However, in the case of the compounds the different atoms have different electron affinities and as a result on finds a polarization of properties. In the case of the 111-V and 11-VI compounds the crystal is either zinc blende or wurtzite. This conveys a polar nature to the structure, and as result for the zinc blende, for example, growth in the [hkl] direction is different to growth in the [&rl direction. The crystal structure shown in Fig. 1-7 highlights this difference. The bond directions are (1 11) or (TTT) where the (TTT) direction terminates in a singly bonded group I11 atom and the opposite (1 11) terminates in a triply bonded group V atom. The { I l l } planes therefore have different polarities from the {TTT} planes and hence different stabilities. Thus each will require a different supercooling in order to initiate nucleation and growth. One of the most significant phenomena associated with structure is the development of (111) or {TTT} type facets on growth surfaces. These can give rise to the facet effect and correlate with twin formation (see Sec. 1.7.5).

1.7.2 Temperature Distribution, Crystal Shape and Diameter Control

One of the more difficult problems in growing crystals from the melt is the problem of arranging for the most suitable temperature distribution and temperature gradients in the growth chamber. Thermal modeling should ultimately provide a quantitative scientific background to the process but in practice it is still an operation requiring considerable skill and know-how.

Modeling horizontal growth is of course very much simpler than modeling vertical pulling. From the practical viewpoint it is important to appreciate that the relatively low temperature gradients normally used in the growth of compounds means that very small practical changes in the growth chamber, such as a small movement of a heat shield can often have a dramatic effect on crystal growth. It also is evident that many thermal models do not take full account of practical thermal arrangements. A major problem in HG and in VGF is the control of interface shape. It is generally recognised that the growth surface should be flat or slightly convex. Concave growth surfaces frequently result in crystal growth defects such as grain boundaries or trapped-in solute. Unfortunately, many heater designs involving a simple extra heater zone used to form a liquid zone are naturally prone to form concave growth surfaces. The use of modeling and the introduction of better thermal design concepts is beginning to overcome this problem. Vertical pulling apparatus, in contrast, is very difficult to model thermally, especially in the critical region of the solid-liquid interface. Unlike HG, where shape is controlled by the shape of the boat and is not an experimental problem, in VP shape or diameter control is a major problem, and one on which a vast amount of R&D effort is expended. The critical parameters controlling interface shape are the thermal heat balance at the solid-liquid interface and the surface tension forces operating between the solid, liquid and gaseous surfaces. The simplest approximation of the heat balance at the solid-liquid interface is given by

1.7 Fundamental Aspects of Crystal Growth

Figure 1-7. Zinc blende lattice showing (1 1 1 ) and

31

(TTT) bond directions and the nature of the lattice polarity.

32


where G is the temperature gradient, 0 is the thermal conductivity, Q, is the density of the crystal and H , is the latent heat of fusion. The temperature gradient G, ( I = S, L) refers to the gradient normal to the solid-liquid interface. In crystal pulling a net loss or gain of heat normal to the crystal axis at the solidliquid interface will cause the growth surface to become convex or concave. The crystal diameter, however, is determined by the shape of the meniscus above the melt. Figure 1-8 shows the steady-state position of the crystal being pulled from the melt and the shape of the meniscus. To a first approximation a meniscus which increases in diameter from the crystal causes the growing solid to increase in diameter. A meniscus which decreases in diameter or waists in from the crystal causes a growing crystal to decrease in diameter. However, this model is only an approximation since shape is also controlled by surface tension forces. Crystals appear to fall into two categories depending on whether their melts completely wet their solids or not. Melts of diamond cubic or zinc blende do not completely wet their own solids i.e.,

Figure 1-8. Diagrammatic illustration of the meniscus contact between a melt and its crystal at an angle 0, (0:for a crystal growing at constant diameter) to the vertical where the edge of the crystal is at an angle 0, and at a height h above the melt surface.

$SG 10 Gbs- ’) have pushed the semiconductor technology frontier towards devices that can accommodate faster and faster processing rates without deterioration of the quality and quantity of information. In view of the timeliness of this research and technology upsurge, this chapter provides a description of up-todate optoelectronic and electronic devices which may be of practical interest to researchers and engineers in the fields of optical communication, satellite communication, wireless communication, and information systems. Due to the limited scope of this review article, we will concentrate on some of the most recent developments in the field at the expense of other equally important contributions in optoelectronics and semiconductor technology. Compound semiconductors, while covering a very broad range of binary, ternary, and quaternary materials, will be limited in this discussion to the group 111-V semiconducting compounds. These refer more specifically, and for the most part, to GaAs and InP and those compounds that can be grown on these binary semiconductor substrates. Compound semiconductor device structures developed to date have generally been intended for application in very high speed electronic systems (taking advantage of the superior electronic transport properties of 111-V semiconductors over Si) and in optical or optoelectronic systems (taking advantage of the direct band gaps of these

semiconductors over a wavelength range of 0.6-3.5 pm). These devices have begun to dispel the common notion among their detractors that “they are the materials of the future and always will be”. Probably the most ubiquitous of these is the AlGaAs/GaAs red light emitting diode (LED), which is widely used in displays; however, the semiconductor laser, currently being utilized in long haul fiber optic communication links, pump sources for solid-state lasers, and digital audio discs, is a close second. The GaAs metal-semiconductor field-effect transistor (MESFET) is also gaining acceptance through commercially built integrated circuits that act as improved performance replacement parts for selected Si integrated circuits (ICs),and they have long held a highly regarded position in hybrid and monolithic microwave integrated circuit applications. As these and other 111-V devices build a history in terms of reliability and diminishing cost and new improved versions become available, 111-V compound semiconductors will inevitably grow in use.

2.2 Key Material Properties Group 111-V compound semiconductors have excellent transport and optical properties, and they include a wide range of crystallographicall y lat tice-ma tched and strained compounds which enable the development of improved and new device structures through “band gap engineering”. Many of these compounds are shown graphically in Fig. 2-1 in terms of their crystallographic lattice constant vs. the energy band gap. While only the binary compounds are labeled, ternary and quaternary compounds lie on the solid and dotted lines with compositions proportional to

49

2.2 Key Material Properties

Figure 2-1. Energy band gap vs. lattice constant for major 111-V compound semiconductors. Shaded vertical bands highlight groups of compound semiconductors with approximately the same lattice constant. 5.4

5.6

5.8 6.0 6.2 LATTICE CONSTANT (A)

6.6

6.4

their locations relative to the binary compounds terminating those line segments. The solid lines represent compounds with direct band gaps, while the dotted lines correspond to indirect band gap compositions. Shown in Table 2-1 is a selection of generally accepted physical constants for some of the more common direct band gap 111-V semiconductors. Not shown, but of equal

importance, are the bulk resistivities in excess of 1 x 10’ R-cm for semi-insulating GaAs and InP substrates. This property has been a key factor in the rise of high speed IIILV ICs, since it enables devices to be electrically isolated from one another in a simple fashion and since it allows the substrate to serve as a dielectric for stripline waveguides at microwave frequencies. While each material’s physical proper-

Table 2-1. Physical constants of group 111-V semiconductors. Properties Energy gap (25 ‘C) Conduction band energy (T-L)difference Electron effective mass

Units eV eV

GaAs 1.44

A1,,,Gao,,As 1.81

0.31

InP

Ga, ,,ln,,,,As

1.35

0.73

0.40

0.55

0.067

0.092

0.077

0.044

0.62

0.66

0.51

0.45

4.1

6.9

6

2.3

9.7

8.2

AIo,,,81no 5 2 A ~ InAs GaSb 1.45

0.35 1.35

0.075

0.023 0.042

0.72

(nir/mo)

Hole effective mass (mhhlmo) Conduction band density of states Valence band density of states Electron saturation velocity at 100 kV c m - ’ (25 ’C) Peak electron velocity Electron mobility (25 “C) Hole mobility (25 “C) Static dielectric constant Thermal conductivity

14 0.83

2.2 8500 450 Wcm-l K - ’

12.6 0.46

15

0.86

11.8 0.70

6.6

1.1

3

3000 100

0.32

4500 150 12.4

2.7 12000 450

6.6 1500 75

33000 4Ooo 400 650 14.6 15.7 0.26

0.35

50

2 Compound Semiconductor Device Structures

ties show distinctly advantageous features, 111-V devices can obtain enhanced performance by combining two or more of these semiconductor compounds in the same device. This has led to the technique of “band gap engineering” - the utilization of two or more semiconductor materials (having different energy band gaps) in the same structure to create new devices, enhance, or adjust the performance of existing device types. The interface between any two differing semiconductors is called a heterointerfuce (or heterojunction if the interface also includes a change in the doping type). These multilayers are then called heterostructures.

2.3 Group 111-V Materials Preparation Heterostructure devices are possible due to the development and refinement over the past 20 years of various epitaxial growth techniques, which include molecular beam epitaxy (MBE), metal-organic vapor phase epitaxy (MOVPE), and liquid phase epitaxy (LPE). Homojunction devices, too, are quite often grown by these epitaxial techniques with the most notable exception being the ion-implanted metal-semiconductor field-effecttransistor (MESFET). Epitaxial growth involves the deposition of semiconductor constituent atoms on a smooth, single crystal substrate under conditions such that the deposited material nucleates, coalesces, and grows into a smooth, single crystal layer lattice matched to the substrate. Semi-insulating substrates are commonly grown as bulk ingots by the liquid encapsulated Czochralski (LEC), horizontal Bridgman (HB), or gradient freeze techniques (AuCoin and Savage, 1985).The in-

gots are sawed, lapped, and polished to form 50mm, 75mm, IOOmm, or even 150 mm diameter wafers with a final thickness of 400-700 pm. Molecular beam epitaxy (MBE)(Arthur, 1968) is a growth technique in an ultra-high vacuum [Pbackground < lo-’’ Torr (1.33 x lo-* Nm-2)andPgr,,,, lozocm- have been created with carbon doping, although the use of the term “impurity” might be better replaced by “alloy component” at these levels. It should be noted that this is a doping tour-de-force since the electrical and physical properties of the GaAs degrade markedly for concentrations of carbon above - 5 x lo1’ cm-3 (George et al., 1991). The minimum concentrations are highly dependent on the growth apparatus as the background impurity concentrations and native defect structures in the epitaxial layers determine the minimum detectable change in the doping level. Recently, using gas-source epitaxial (GSMBE) methods, carbon concentrations above lo2’ cm-3 have been realized in GaAs (Abernathy et al., 1989), although the same caveats exist for high doping levels independent of the crystal growth method. Epitaxial growth processes provide significantly better control of the depth distribution of impurities than ion implantation, but have limited selected-area control capabilities. CBE/GSMBE methods are actively being explored for selected area growth (Tu, 1995). The issues which limit

83

the selected area growth are nucleation and growth phenomena and contamination in the patterned areas, as well as control of the growth rates on the various crystal planes exposed by the patterning. Recent advances in MOCVD have also shown some capability for controlled selective area growth (Linden, 1991). As was shown in Fig. 3-1, the device transfer characteristics are significantly better for epitaxy-based devices than for ion implanted structures. This is due to the tightly controlled charge distribution in a heterostructure device. Sidegating and backgating are also controlled in heterostructure devices, as the charge distribution is readily isolated by etching or ion implantation processes. This latter point is illustrated in Fig. 3-1 1. Principally, the improvements come from the significant differences in the charge distributions, the ability to isolate devices, the creation of atomic displacement damage, and the interaction of the substrate and the charge distribution during device operation [see DAvanzo (1982), Vuong et al. (1990)l. When doping compound semiconductors, many factors must be considered. The process of ion implantation is of relatively low cost compared to epitaxial layer growth. The cost saving is due to a high wafer throughput relative to all other methods of creating an active layer, which is a significant point for fabrication costs. Also, the uniformity and reproducibility are adequate for most applications, the trade-off coming in the ability to create the tightly-controlled charge distributions required for ultra-high performance devices. The performance of epitaxy-based devices is typically superior to that realized in ionimplanted devices for a given set of design rules and circuit configuration. With present processing costs and the recent introduction of high-volume production of epi-

84

3 Compound Semiconductor Device Processing 120

100

80

60

40

20

0

taxial materials, the actual cost differential between devices fabricated on epitaxial materials and those on ion-implanted materials is rapidly converging. Moreover, the performance advantage and yield improvements offered by epitaxial materials offset the higher costs of processing epitaxial materials in a number of applications. Furthermore, epitaxy-based heterostructures such as HBT, HEMT, VCSEL, and others cannot be fabricated by ion implantation or any other methods.

3.3 Isolation Methods Electrical isolation is required to prevent interaction between devices in an integrated circuit. The objective is to limit or eliminate interdevice current flows and electric field effects to levels below those which affect the device’s operation. Circuit parasitics may be reduced by proper application of isolation techniques so that higher performance may be realized. Ca-

Figure 3-11. Experimental results of sidegating effects in heterostructure FET devices. With optimized isolation at the device periphery, very large potential differences may be applied to adjacent devices with small interdevice spacings. The sidegating (dashed lines) relative to those devices that received an additional deep isolation implant (solid lines), within the same wafer. The y-axis is defined by (V,, = O)], the x-axis 100[Ids( VgS)/Ids is the voltage applied to a sidegate contact at the distances noted in the figure. Sidegating effects are mitigated to a great degree with the deep isolation implant. [Figure from Vuong et al. (1990).] 01990 IEEE.

pacitances, inductive coupling, and leakage currents can be mitigated. In addition, electrons and/or holes may be better confined within the transistor cell. The use of isolation leads to more reproducible electrical characteristics, better control of the charge distribution in active devices, and similar control over the electrical characteristics of passive components such as resistors, inductors, and capacitors. There are two principal approaches to isolating devices in a compount semiconductor integrated circuit: ion implantation and “mesa” etching. Each method has its own advantages and drawbacks. Mesa isolation was developed first. As substrate material quality and device fabrication processes have improved, ion implantation is becoming the method of choice for isolation. Implantation permits a desirable planar morphology and the creation of finer device geometries which are needed in order to fabricate high density circuits with high yields and reliability. However, effective isolation of very shallow, or highly

3.3 Isolation Methods

doped, layers often proves difficult in practice due to the Gaussian distribution of the ion implantation process. Implanting through photoresist or other capping layers can circumvent this problem by placing the peak of the ion distribution in the nearsurface region.

3.3.1 Mesa Etching Mesa isolation is an effective method for isolating discrete devices and active regions in integrated circuits. The technique involves defining regions surrounding the active devices with a photoresist layer or other masking materials, and subsequently etching away the exposed material to form isolated islands or ‘mesas’ in the surface (Fig. 3-12). The etching can be carried out using “wet” or “dry” chemistry methods. A key requirement of the mesa definition process is to produce a morphology that is compatible with any subsequent processing steps. Excessively deep trenches, reentrant edges, or sharply sloped side walls will impair the creation of fine features, and may give rise to poor or nonexistent coverage of subsequent metal layers or dielectrics. Smooth features and rounded or gentle transitions at step-edges are generally preferred. Some of the key features of mesa isolation are illustrated

85

in Fig. 3-13. If the trenches or mesas are incorrectly formed, as shown in Fig. 3-13 a, metallization layers and dielectrics will not deposit properly, leading to device failures (e.g., short or open circuits, leakage paths). Mesa-type structures such as those illustrated in Fig. 3-13b are desirable. The anisotropy of compound semiconductor materials becomes evident in the morphology created by the interaction of the etchant and the crystal structure, as shown in Fig. 3-14. Thus it is imperative to understand and control the etching process to produce the desired mesa or trench configuration. Etching characteristics, substrate crystallographic properties, and device implications were discussed, for example, by Lee (1982). The ability to force the etchant into very fine features, i.e., liquid surface tension or gas pressure/density effects, limits the minimum spacing between devices and features. Similarly, to remove the reaction products or to dilute the etchant and arrest the etching process is particularly difficult for high aspect ratio, or closely spaced, features. (Details of etching chemistries and processes are presented in Sec. 3.5.) As a result, devices must be separated to accommodate these process limitations at the expense of valuable semiconductor area. Thus the packing density and the integration level of the circuit are generally more

Figure 3-12. An illustration of an n-channel FET isolated by an etched mesa process. The areas between adjacent devices may be ion-implanted or covered with a passivation layer to further enhance the isolation.

86

3 Compound Semiconductor Device Processing

Semi-insulating Substrate

Figure 3-13. Cross section of an FET with mesa isolation. In (a) the mesa is undercut excessively. Dielectric coverage and integrity are compromised. In (b)the mesa edges are optimally formed and the dielectric coverage is uniform.

limited when mesa isolation is used as opposed to ion implantation processes. Redeposition of the host materials or masking materials may occur during the etching process, which may inhibit the formation of well-controlled mesa morphologies, creating curved or corrugated surfaces, nonuniform mesa definition, leakage paths, etc. These effects must be avoided to successfully isolate devices with mesa technology.

3.3.2 Ion Implantation Isolation With ion implantation, the object is to render the material semi-insulating or highly resistive by the formation of deep levels and recombination centers resulting from the ion bombardment. Use of this technique has the powerful advantage of maintaining surface planarity, which makes the definition of very fine features and multi-layer metallizations relatively straightforward. Thus better process integrity and greater complexity can be achieved with ion implantation as opposed to mesa etching methods.


87

t co1 I >

c11 I >

Direction

Direction

GaAs Substrate

t COI

i>

r

I

Direction

Direction GaAs Substrate

For successful isolation selection of the ion species, control of the ion flux, beam purity, and the ion energy are critical. The ion penetration depth is proportional to the ion energy, ion mass and host lattice atomic structure, molecular weights and composition. The concerns associated with ion implantation, as discussed in Sec. 3.2.1, are ion channeling, straggle, and tailing of the depth profile. However, for isolation processes it is usually desirable to extend the isolation as deeply into the substrate as possible, thus tailing may be a desirable feature in this case, as shown in Fig. 3-15. The efficacy of the isolation is a function of the chemistry between the host and the implanted ions as well as the formation of defects. Some of the important ion implantation ranging data are summarized in Table 3-3. The isolation effect is created by the displacement of host-lattice atoms, the creation of a myriad of defect complexes, and

Figure 3-14. Anisotropy of GaAs as revealed by chemical etchants. The limiting - crystal . -planes are of { 111) type, with arsenic or gallium planes exposed. This results from the nature of the zincblende crystal structure. (Figure courtesy of SEMI, Mt. View, CA, reprinted by permission.)

the reactions of the host species with the implanted ions (e.g., A 1 - 0 complexes in AlGaAs) (Donnelly, 1981; Short and Pearton, 1988). Commonly used ions are oxygen, boron, and protons ( H + )(Pearton et al., 1987; D’Avanzo, 1982). It is generally desirable to use heavier ions for the isolation implant, as greater atomic displacement occurs in the host. However, a significant compromise in the achievable depth arises for heavy ions at practical ion energies. Light ions, particularly protons, can be used for very deep isolation requirements if relatively high doses are required. The implanted ions may create a variety of atomic displacements in the crystal lattice. It is desirable to create defects which act as recombination centers to prevent the transport of charge between devices. As mentioned in Sec. 3.2.1, these defects consist of atomic displacements, vacancies, interstitials, a variety of defect complexes, and antistructure (resulting from atomic

88


Usable isolation effects in this region Figure 3-15. Ion implantation isolation schematic diagram. The peak of the ion range (R,) is the approximate position of maximum isolation. The displacement damage peak (maximum atomic displacement) will be somewhat shallower or deeper than R,, depending on the host and implanted species atomic numbers, the dose and the energy of the implantation. The approximate extent of the isolation is shown. Additional displacement occurs at the end-of-range, increasing the effective isolation depth.

Table 3-3. Ion-implantation ranging data for selected ion species in GaAs single crystal materiala,b , c . Energy (keV)

Element ~

20 50 100 150 200 300 380 a

H

B

C

0

Si

0.21810.099 0.48010.144 0.866/0.181 1.23310.205 1.601/0.275 2.42310.262 3.16110.292

0.04410.034 0.124/0.070 0.255/0.115 0.382/0.145 0.50410.1 I0 0.733/0.207 0.90510.229

0.039/0.030 0.101/0.060 0.20810.098 0.31310.125 0.415/0.147 0.606/0.182 0.75110.203

0.03010.022 0.07510.045 0.1 5410.076 0.233/0.100 0.3 1610.121 0.46210.1 52 0.567/0.172

0.01810.013 0.04210.025 0.085/0.044 0.129l0.061 0.1 14/0.074 0.263/0.100 0.333/0.117

Gibbons et al. (1975);

data are in micrometers; data are presented as depthlstandard deviation.

site exchanges). Each defect alters the electrical characteristics of the host material, and in the aggregate serve to create the insulating regions between devices. At very high doses the lattice may be disordered to the point of amorphization. This can occur at fluxes greater than lo1’ cm-2 for oxy-

gen or boron; protons require much larger doses (greater than lot6~ m - ~Excessive ). damage can create a conductive region instead of insulating characteristics. It should be noted that there are significant tradeoffs in the dose-energy relationships in the implantation process: simply in-

a9


creasing the dose or energy may actually enhance the interaction and leakage between devices, and also increase surface leakage due to excessive damage. The large density of states created permits hopping conduction and tunneling processes for charge transport. A light dose implant may not create sufficient recombination centers to be effective; a low energy may create insufficient displacement damage or too shallow an isolation region. Each ion species has a unique 'signature' in the isolation process. For example, Bf ions remove up to 200 electrons per ion when implanted into GaAs at 1 MeV (Davies et al., 1973). Oxygen ions, while less effective than B at removing electrons on a per-ion basis, have proven to be extremely effective at isolating GaAs and particularly AlAs or AlGaAs-containing structures (Favennec, 1976; Pearton et al., 1987; Short and Pearton, 1988; Ren et al., 1990). Oxygen produces a deep level in GaAs (Fig. 3-3, Sze, 1981, Chap. I), which captures electrons and may create a high resistivity characteristic. In the AlGaAs material A1 - 0 complexes are formed which are highly effective recombination centers (Pearton et al., 1987; Short and Pearton, 1988). Protons are the ion of choice for deep isolation schemes (D'Avanzo, 1982). Being of low mass, the proton may be injected deep into the lattice even at modest energies, e.g., beyond 2 pm at an energy of 250 keV (Gibbons et al., 1975). It is interesting to note that the damage profiles do not coincide with the ion profiles due to the large mass differences between the host and most implanted species. This discrepancy is greater as the mass difference between the ion and the host atoms increases. Owing to the approximately Gaussian nature of the ion and damage distributions in the lattice, multiple implant sequences are generally needed to

achieve a relatively smooth ion damage profile into the depth. This is illustrated in Fig. 3-1 6. When properly placed, multiple implants create a quasi - uniform, high resistivity volume in the implanted region. The drawback with the use of multiple implants is that the surface damage can be extensive, particularly at high doses or high energies, as well as extending process times and increasing macroscopic surface defect densities. The surface damage can lead to surface leakage paths or nonstoichiometric surface regions. For example, surface resistivity has been observed to fall by more than three orders of magnitude when very high energy isolation implants are carried out in GaAs (Liu et al., 1980). One very powerful advantage of ion implanted isolation is that selected areas with complex geometries can be readily formed by patterned masking. Use of the selected area ion implantation methods for active region and isolation region formation allows for optimizing layout compaction and device isolation in the integrated circuit. To withstand very high energy ion bombardment, very thick blocking layers must be deposited on the surface, which can limit fine feature definition. Suitable ion blocks are thick photoresist, or photoresist and combinations of dielectrics or thin metals. Photoresist layers of 2-4 pm in thickness are typically employed to block 0,B, or H implants at energies of 100keV to 400-800 keV. With lighter ions, such as protons, the displacement of lattice atoms is significantly less than that obtained with heavy ions. Therefore the recovery of lattice disorder may occur with lower driving forces. For example, the damage created by H + implantation in GaAs anneals out at temperatures above about 400 "C.Protons create only small lattice displacements, and hydrogen diffuses rapidly out of the host

-

90


Figure 3-16. Multiple implant isolation profile. In this case, ion implantation cycles are carried out at different energies. The deeper implants are performed at higher energies. End-of-range damage increases the isolation effectiveness and helps to smooth the net damage profile. With a large ion flux some amorphization or damage of the surface region may occur. A mild thermal anneal may be required to recover the crystal structure and stabilize the displacement damage profile without recovering the isolation effects.

leaving few electrically active defects (Pearton et al., 1990). The behavior puts significant constraints on processing temperatures and the viability of proton isolation for all but the lowest thermal budget processes. For most isolation processes a minimal thermal anneal is desirable, typically below 500 "C for relatively short times. This "gentle" anneal prevents complete relaxation of the lattice, but eliminates some of the marginally stable atomic displacements and potential leakage paths while maintaining the high resistivity of the isolated region. On the other hand, for ion implantation doping it is necessary to anneal at temperatures in the range of 75OoC-900"C to permit site selection by

-

the impurities (activation) and to remove electrically compensating displacement damage. This raises a conflict between the processes required to form the active layers and the need for isolation. For example, isolating underneath ohmic contact pads is not possible with present ion accelerator technologies. It should be noted that as the implantation process involves charged species interactions and significant energy is transferred to the lattice, the possibility of radiation damage and heating of the lattice during bombardment exists. The energy impinging on the wafer is of the order of hundreds of watts per square centimeter in a high-current implanter. If the wafer temperature rises above 150-2OO0C, the ef-

-


fectiveness of the isolation process may be compromised as lattice displacements can anneal out during the implantation cycle. To minimize the self-heating, it is prudent to implant at the lowest practical beam current and ion energy, or control the substrate temperature during implantation. Electron bombardment can be used for isolation, but the damage created is subject to annealing out at very low temperatures. The annealing of electron-induced damage has been observed to occur in two stages: 150-200 “C and 200- 300 “C (Aukerman and Graft, 1967; Vook, 1964). This makes electron irradiation unsuitable for isolation as temperatures in wafer fabrication typically exceed these levels. Neutron damage is another method for isolating regions in compound semiconductors. The typical array of defects and defect structures are produced by neutron irradiation. The damage induced by neutrons has been found to recover in two stages similar to electron-induced damage: at 200-300 “C (minor displacements), and then recovers fully at 600-700 “C (Lang, 1977). Thus the isolation created by neutron bombardment creates a stable isolation region only if processing temperatures are maintained below -500°C. Beam blocking materials are generally metals in order to obtain sufficient stopping power for the neutron flux. One additional variation of ion implanted isolation is the creation of an isolation “box” for devices. For example, in devices utilizing n-type implants, a p-type implantation can be placed beneath the tail of the donor distribution. This buried-p layer creates a p- n junction isolation condition. By carefully selecting the dose and energy, the p-type layer can be nearly fully depleted, leading to minimal capacitance, a sharp n-type charge profile, and mitigation of short channel effects (Finchem et al.,

91

1988; Matsunaga et al., 1989; Onodera and Kitahara, 1989; Sadler et al., 1989). Typically, the buried p-type implant is used only under the channel region. However, it may be connected to an external bias to enhance the back-plane isolation with a depleted p-n junction. An additional isolation implant or mesa processing may be used to create the “walls” of the box, thereby completely isolating each device, as illustrated in Fig. 3-17.

. 3.3.3 ‘Sidegating and Backgating

..

Sidegating and backgating are terms describing the interaction between devices in an integrated circuit laterally and from the back-plane region, respectively. These phenomena have plagued GaAs-based devices for many years (Vuong et al., 1990 D’Avanzo, 1982; Smith et al., 1988a; Lin et al., 1990), and arise from the electric fields induced in the material when the circuits are biased. The effects are realized as a modulation of the transistor channel current or the current flow in channel-resistors (Gray et al., 1990; DAvanzo, 1982). The problems associated with sidegating and backgating are greatly influenced by the circuit layout, and, in particular, the spacing and differential voltages between nearby devices and the condition of the back-plane (biased or grounded). Additional phenomena in sidegating and backgating effects are the charging and discharging of deep states. Electric fields, such as those created in p-n junctions, implanted isolation regions, ohmic contacts, depletion regions (e.g., Schottky barriers), etc., all lead to exposure of the various deep level states (traps), relative to the Fermi level, which lie in the semiconductor energy gap as shown in Fig. 3-18 (see also Milnes, 1973, and Sze, 1981, Chap. 1). As the electric fields are altered

92


Figure 3-17. A cross section schematic diagram of an FET isolated by ion implantation processing (or mesa etching). The device has a buried-p layer connected electrically to the low potential of the device. This addition serves to mitigate sidegating effects. The buried-p layer must be contacted through an additional p-type ion implantation adjacent to the n f contact implant (or diffusion). The gate is offset in the channel to reduce source resistance.

Semiconductor Surface Increasing reverse bias exposes additional deep states

-

Emitted Charges (Deep Levels Empty) Free charges may be recaptured by deep or shallow states

Fermi Level -L

E3

N-type Semiconductor

Valence Band Edge

-

Figure 3-18. Schematic representation of the near-surface band bending in an n-type semiconductor. Shallow donors are partially ionized. Deep levels are occupied within 2 k T of the Fermi level, and filled below the Fermi level crossover points. When the state is lifted above E , charges are emitted at rates proportional to their respective depths, the temperature, emission characteristics, and rate of band bending. The charges may be recaptured during relaxation processes and re-emitted, leading to an oscillatory condition.


first by biasing, then modulated during device operation, the deep traps charge and discharge as the bands bend. This leads to a secondary modulation of the charge transport in the devices, with response transients of sub-microseconds to minutes in duration. Several competing processes may arise from these deep levels in or near active device regions: 1) charge domains may be launched from a source (anode) contact under moderately high electric field conditions, and 2) DC and AC electric fields may modulate the deep state charge conditions (Milnes, 1973). In GaAs, for example, charge domains may be created and injected from ohmic contacts when electric fields exceed 500 V cm-’ to 1000 Vcm-’ between nearby devices (Ridley and Watkins, 1961; Ridley and Pratt, 1965; Kaminska et al., 1982). These charge domains travel through the semi-insulating substrate or buffer layer to the collecting contact (cathode). The motion of these charge packets induces a time-varying electric field under the gate and thereby upsets the channel charge distribution causing a modulation of the device operating conditions [see, for example, Fujisaki and Matsunaga (1988)l. In the case of field effects there are two main components. The DC contribution involves the equilibration of deep state capture and emission processes. This is typically a very slow process leading to long turn-on transients upon biasing, device latch-up, and an “improper” D C operating state. The details of this quasiequilibrium condition are affected by the operating temperature, and the temperature distribution in the device through the capture and emission rates and the concentrations of the deep states. The charge exchange processes can produce additional time constants in the temporal response as

93

the IC heats. Localized anomalies may arise as different regions of the IC dissipate varying amounts of heat during operation. The AC effects are essentially resonances of the deep state capture and emission rates with the operating frequency of the devices. For example, in GaAs there are at least 20 known deep levels of electron- and hole-like characteristics in the energy gap (Martin et al., 1977). Thus, for a given temperature, electric field strength (biasing condition and voltage swings), active layer configuration, and circuit layout, a number of traps may be exposed within a device as shown in Fig. 3-18. As the device changes state in response to an input, the trap exposure about the Fermi level is altered, and the emission or capture of charges by the trap@)may be stimulated. This leads to the “resonance” condition. The electrical manifestations of deep levels may be observed as long time constant effects, impaired transient responses, “ringing” in the device characteristics, or an apparent lack of device gain (Lin et al., 1990; Vuong et al., 1990; Smith et al., 1988 b). Similarly, the back-plane or substrate bias can modulate the channel charge distribution in FETs through the electric field created between the back-plane and the channel, thus upsetting the threshold and current-carrying capability in the devices. Again, as the electric fields are modulated, the channel charge distribution responds with multiple time constants determined by the trapping behavior of the exposed deep levels, particularly those at the buffer - substrate interface (epitaxial layers) or in the tail of the implant profile. These effects are not subtle: sidegating and backgating phenomena, either static or dynamic, can lead to collaps of the transfer characteristics, or pinch-off resistors and transistors, as illustrated in Fig. 3-19. In extreme cases, sidegating can impact

94

3 Compound Semiconductor Device Processing 10

‘1

-1.5

v,=2v

V c = 2.5 V SlDEGATE2pm

-1.0

-0.5

;// A

0

0.5

Vgs (VOLT)

Figure 3-19. The effect of the sidegating voltage on I,, vs. V,, in a depletion-mode HFET device. The sidegating potential is applied to a separate electrode separated 2pm from the source of the test device. Note the strong effects of negative bias effectively depleting the channel charge and causing closure of the channel. Forward biasing the sidegate electrode has a negligible effect.

devices separated across an entire 3” (76mm) wafer (Gray, 1989). The typical manifestations are devices operating well below expected performance levels, or the intermodulation effects as devices switch to different states and the electric fields are altered. These phenomena are well known and relatively well understood (DAvanzo, 1982; Vuong et al., 1990; Smith et al., 1988a; Ridley and Watkins, 1961; Ridley and Pratt, 1965; Milnes, 1973). A highly effective method for isolation in GaAs devices has been discovered: a “lowtemperature buffer” (LTB) grown by MBE (Smith, 1988a). This approach capitalizes on the extensive defect structure created by epitaxial crystal growth at low temperature under strongly nonequilibrium growth conditions. The material produced by this process is nearly completely inactive, both electrically and optically (Kaminska et al., 1989). Smith et al., 1988b, has found that the DC isolation and DC sidegatingimmunity are greatly improved negligible interactions are found for DC electric fields in

excess of 10 kV cm - However, unless other measures are taken to displace device active regions well away from the LTB, the high-frequency performance of circuits fabricated on these buffer layers is drastically affected. It has been found that integrated devices operating at -1 GHz, as fabricated with “standard” processing methods, are slowed to the kilohertz regime when constructed with the LTB structure without having sufficient isolation from the LTB (Lin et al., 1990). This effect was attributed to electron trap-related charge capture and emission with very long time constants. To circumvent these problems, a second relatively thick standard buffer layer must be grown on top of the LTB to minimize the effects on charge transport behavior in transistors (Smith et al., 1988a, b). Subsequently, the devices must be laterally isolated to prevent or mitigate the normal sidegating effects. The importance of controlling or eliminating interactions in compound semiconductor-based ICs continues to drive investigations into the trap-related, semiinsulating characteristics of GaAs and analogous effects in other 111-V semiconductors. At the present time, there are methods for mitigating the sidegating and backgating effects, but it appears unlikely given the nature of the compound semiconductor materials and their defect structures, and the desirability of the semi-insulating behavior, that these problems will be totally eliminated.

3.4 Diffusion Diffusion and impurity redistribution are of great importance and consequence in device fabrication processes. Diffusion has been the subject of extensive investiga-

3.4 Diffusion

tion (Tuck, 1988). The intentional diffusion of impurities is required in numerous fabrication steps. Often, however, the diffusion of impurities and the interactions amongst the various materials present on, and in, the wafer are highly undesirable. As examples, p-n junctions generally become less abrupt and the electrical and physical (chemical) junctions may shift when the impurity species diffuse. In heterostructure bipolar transistor (HBT) structures this type of “misalignment” strongly compromises the device electrical characteristics and device performance (Ali and Gupta, 1991). Rapid in-diffusion of gold in an ohmic contact region may cause device failure via punch-through (“spiking”) or lateral migration (Zeng and Chung, 1982). Silicon donor redistribution in HFET devices will alter the channel charge distribution, shift the device threshold voltage, the transconductance (gm), and affect the current carrying ability of the channel [see Daembkes (1991) and references therein]. The diffusion behavior may be characterized by a parameter known as the diffusion coefficient, and is controlled principally by the chemical potentials of the host and impurity atoms in the lattice, and the impurity concentration distribution@).Defects, such as vacancies, interstitials, impurities, and the relative physical sizes of the host lattice atoms and the impurity, the bond strengths and the dimensions of the lattice interstices all affect the atomic mobilities and the diffusivity of the impurity atoms. Diffusion processes are mathematically represented by several empirical relationships known as Fick’s laws. The first of these laws considers the flux of a diffusing species (in one dimension), J , through a plane in a direction x, at any time (t): J

=-D

g) f

(3-1)

95

where C is the concentration, dC/dx is the concentration gradient, and D is the diffusivity. Equation (3-1) describes the driving force behind diffusion: a concentration gradient, i.e., a chemical potential difference which, from thermodynamic arguments, must become negligible as the system reaches equilibrium. Equation (3-1) is illustrated schematically in Fig. 3-20. The relative ease with which a given species moves in the lattice is embodied in the magnitude of the diffusivity. Fick’s second law relates the change of the concentration profile with time [taking the derivative of Eq. (3-I)] dC d dC (3-2) z=&dx) Equation (3-2) describes 1) how rapidly the material will redistribute in the host lattice, and 2) the concentration profile as a function of time and distance. Using the grad operator, Eqs. (3-1) and (3-2) may be extended to accommodate the real three-dimensional behavior of the diffu-

1

.-6

it 0

Substitutional Impurity erfc behavior

F

Characterized by:

0

-I

t

Dirtance Into Semiconductor Surface

Figure 3-20. Schematic diagram of a “erfc” diffusion profile, represented by a single-value diffusion coefficient, D o , and a unique activation energy, E,; k and T have their usual meanings.

96


sion process in the crystal lattice. Implicit in these descriptions is the temperature sensitivity of the diffusion process, which is accounted for in the diffusivity. The diffusivity is defined as D = Do exp (- E,/kT)

(3-3)

where Do is the diffusion constant, E, is the activation energy for the diffusion process, k is the Boltzmann constant, and T is the temperature (K). In addition, the diffusivity of an impurity is sometimes dependent on the concentration, typically being enhanced at higher concentrations. Therefore to realize a high degree of stability against elevated temperature processing, it is desirable that an impurity species have a large activation energy and a small diffusion constant [see, for example, Tuck (1988) or Shewmon (1963)l. In compound semiconductors most impurities have segregation coefficient values of less than one which represent an additional driving force for the out-diffusion behavior. The crystal lattice is distorted by the presence of the impurity atoms due to size and/or the chemical incompatibility. The extra energy available tends to drive the impurity species from the lattice. The free surfaces, or those surfaces and interfaces under strain due to mismatched physical properties (e.g., heterostructures, dielectric layers, metals, etc.), will also provide added energy for diffusion, and may act as sinks for the diffusing species. Also, the solid solubility limit places an upper limit on stable concentrations of impurities in the lattice: concentration above this level will increase the driving force for redistribution, precipitation, site exchange processes, and electrical compensation. In GaAs it has been observed that the diffusivities of the groups IV and VI donor type species are generally small, whereas the

group I1 acceptor species tend to diffuse much more rapidly. Carbon, a group IV acceptor, is a notable exception, being extremely stable in most compound semiconductor lattices (Schubert, 1990; Schubert et al., 1990). Two additional concerns for the processing of compound materials at elevated temperatures are the increased vibration frequency of the lattice atoms and the dissociation of the compound semiconductor material. The motion of the atoms in a compound semiconductor lattice can create a variety of electrically active point defects (Hurle, 1977; Van Vechten, 1975), and diffusion may cause an undesirable redistribution of the impurity atoms. As a result, the electrical properties of the material may be altered in an uncontrollable manner. For the compound semiconductor materials GaAs and InP, the dissociation rate is significant for temperatures above 600 “C and 475 “C, respectively (Panish, 1974). This is due to the high partial pressure of the group V species over the host material, as illustrated in Fig. 3-21 [after Thurmond (1965)l. The key point in this figure is the region around the coherent decomposition pressure. By controlling partial pressures of the various species the decomposition may be suppressed. Without some mechanism for protecting the surface region during high temperature processing, either with a cap layer or an overpressure of the group V species, the surface rapidly decomposes creating a metal-rich surface, enhanced dissolution of the surface layers, and destruction of the semiconducting properties. It is critical to maintain a minimalistic approach to the thermal processing of most compound semiconductor materials. RTA (rapid thermal annealing) cycles or “low thermal budget” (i.e., lowest possible temperatures and minimal times) processing are needed to

-

-

3.4 Diffusion 1200 1100 I

I

1000

900

I

1

800

"C

10 1

10 10

$ -

10

Q

10

10 10

10 10

IO"/T, 1/K

Figure 3-21. The equilibrium vapor pressure (in atm.) of As, Ga, As,, and As, over GaAs as a function of lo4 T - The total arsenic pressure (referred to As,) is approximately 1 atm. lo" Nm-2) at the melting point, 1238 "C. [Reproduced from Thurmond (1965). Reprinted with permission.] 01965, Pergamon Press.

'.

maintain the impurity profile and materials integrity in the near-surface region. For successful device fabrication, knowledge of the stability of the donor and acceptor species in the lattice is critical. The diffusion coefficient values for these impurities are in the range of 10-3-10-6 cm2 s - ' at the temperatures used for epitaxial crystal growth, ion implantation annealing, and wafer processing, and thus most species move quite rapidly in the lattice (Tuck, 1988, Chaps. 4, 5; Shewmon, 1963). For example, one advantage of an epitaxial-grown MESFET device process sequence is the ability to minimize the thermal budget, leading to a limited redistribution of impurities. In contrast, in a similar

97

ion-implanted MESFET process, the thermal budget and maximum temperatures are extremely critical to the impurity distributions, the resulting charge distribution, and the device characteristics, particularly for the ultra-thin, ion-implanted structures required for high-speed or low-noise operation. On the other hand, high-temperature furnace or rapid thermal annealing of selfaligned MESFET and HFET devices is necessary and readily accomplished when refractory gate metals are used. The limited reactivity and stability of the refractory metals with most compound semiconductors permits the temperature to be raised above 800°C (for GaAs) sufficient to anneal the ion implantation damage, restore the lattice disorder, and activate the implanted species (Dautremont-Smith et al., 1990 Yamasaki et al., 1982; Shimura et al., 1992). At the same time, the impurities which provide charge to the channel may diffuse large distances (tens of nanometers), leading to uncontrolled device characteristics and poor performance, emphasizing the need for strict control and understanding of the time-temperature cycle impact. Si redistribution during annealing processes was investigated in GaAsIAlGaAs heterostructure (HFET) materials (Schubert et al., 1988, 1990). It was found that the diffusivity of silicon was roughly ten times higher in AlGaAs than GaAs at 800 "C. This places significant constraints on the device structures, particularly for HFET devices which may incorporate a "setback" (intentional spacing of the impurity species away from the channel region) to keep the ionized donors separated from the electrons that reside in the potential well (Sequeria et al., 1990; Bar et al., 1993; Danzilio et al., 1992). In a typical annealing cycle the Si atoms may diffuse more than 5 - 15 nm, thereby placing a signifi-

98


cant fraction of the Si atoms in the channel region. This phenomenon will be realized as a reduced electron mobility and somewhat impaired electrical performance. One of the anomalies in the diffusion behavior of most acceptor species in compound semiconductors is the double diffusion front (Tuck, 1988; Gosele and Moorhead, 1981). In this case the impurity appears to have at least two distinct values for the diffusivity. These phenomena have been explained in terms of interstitialcy and substitutionality of the diffusing species. Interstitials have significantly lower activation energies for motion in the lattice, and therefore larger diffusion coefficients since there is no requirement for atomic site-exchange to allow motion within the lattice (Gosele and Moorhead, 1981; Small et al., 1982). The interstitial atoms may therefore move very rapidly in the host material. The substitutional impurity, on the other hand, requires the presence of a vacancy or the exchange of adjacent lattice atoms to permit motion of the impurity. Such an exchange process requires the addition of significant amounts of energy, and the cooperative motion of several atoms. The activation energy for such a process is relatively large, the probability of site exchange is small, and the substitutional diffusion process is slow. The double diffusion behavior is illustrated in Fig. 3-22 for zinc in GaAs. It is clear that there are at least two mechanisms operating in this case, with significant differences in diffusivity values as well as the relative concentrations of interstitial and substitutional impurities. Several investigations have been carried out to understand the behavior of anomalous diffusers such as Mg, Zn, and Be (Small et al., 1982; Cunnel and Gooch, 1960; Gosele and Moorhead, 1981). At the present time, although the mechanisms for

50

100

150

200

250

300

Depth (pm)

Figure 3-22. Experimental diffusion profiles for zinc in GaAs at loo0 “C.A, B, C, and D represent the zinc concentration profiles after 10 min, 90 min, 3 h, and 9 h, respectively. Note the two unique regions for the concentration profiles in each case. [Reproduced from Tuck (1988). Reprinted by permission of Adam Hilger/ IOP, 01988.1 Note: Ordinate axis label corrected from the original publication.

explaining the double diffusion front behavior are well-accepted, the precise understanding of the processes by which the species simultaneously select both types of diffusion paths has yet to be elucidated. As device processing continues to improve, more stable species, such as carbon, are being utilized for acceptor doping. However, carbon is not a panacea as the effectiveness for doping in a number of ternary and quaternary compound semiconductors is very limited. As mentioned above, uncontrolled impurity redistribution can seriously affect device performance. These effects are often seen in one of the more promising device structures, i.e., the heterostructure bipolar transistor (HBT) (Ali and Gupta, 1991). Owing to “band gap engineering” (Capasso, 1987, 1990) and the properties of

99

3.4 Diffusion

device applications (Hafizi et al., 1990; Yin et al., 1990). It has been observed that the Be atoms redistribute so significantly in the lattice that this method of doping the p-base region is essentially impractical for use in controlled, reproducible HBT fabrication (Miller and Asbeck, 1985). Streit et al., (1992) claim to have solved the Be redistribution problem by controlling certain growth parameters in the MBE growth of HBT structures. Other p-type transition-metal species also behave in a manner similar to beryllium, but are not generally utilized for this reason. Accelerated device aging tests showed that Bedoped base HBTs can be relatively stable to self-diffusion failure mechanisms under low to medium power conditions, as shown in Fig. 3-23 (Yamada et al., 1994). They found failures (under accelerated aging conditions) occurring at 300 h, 230"C, and an apparent activation energy of 1.4 eV, which translated to projected operating lifetimes of -106-107 h at a junction temperature of 125 "C. Carbon, however, has been found to be very stable in compound semiconductor crystal lattices, and therefore appears to be

GaAs-based and InP-based ternary compounds, an HBT device in these materials is capable of switching in the hundreds of gigahertz, many times faster than the fastest silicon-based counterpart (Nubling et al., 1989; Nottenberg et al., 1989). Many of these HBT devices have been fabricated in MBE-grown epitaxial materials, using Be for the base dopant species (Kim et a]., 1988; Miller and Asbeck, 1985; Streit, 1992). Investigations into the performance of Bedoped base HBTs and the fundamental processes of diffusion of beryllium in GaAs have shown that this impurity diffuses extremely rapidly (Hafizi et al., 1990). This poses a difficult problem for the crystal grower and the process engineer, as significant impurity redistribution can occur during crystal growth, during even modest thermal processing, and subsequently during the device operation. The latter effect being induced by elevated junction operating temperatures and the extremely high electric fields in the devices (Ali and Gupta, 1991). As a result of the Be diffusion, the p-n junctions shift in an uncontrolled manner rendering the materials unsuitable for

-

CI

-30 -60

>

-2E

-90 -120

0

> Q

-150

t-T

-

215"C/biased 215"C/no bias (hot control) -CF- 25"C/no bias (control) --t

-240

0

100

I

I

I

I

200

300

400

500

Stress Time (Hour)

I

600

I

I

700

800

900

-

Figure 3-23. A plot of the change in output voltage of a HBT-based circuit as a function of stressing time at 215 "C. Parts which have not been subjected to current stress are shown as open circles and open squares. Parts which have been biased are shown as closed circles. At 215 "C, the output of the circuit degrades substantially up to 800 h. This indicates a change in the bases emitter junction, or a modification of the emitter contact resistane due to impurity diffusion. [Reproduced from Yamada et al. (1994). Reprinted with permission. 01994 IEEE.]

100


the practical alternative for p-type doping in many 111-V materials (Abernathy et al., 1989; Malik et al., 1989; Quinn, 19921993). Carbon may be introduced into the lattice by ion implantation or during crystal growth when carried out with techniques such as metal-organic chemical vapor deposition (MOCVD) or gas-based molecular beam epitaxy methods (chemical beam epitaxy - CBE or gas-source molecular beam epitaxy - GSMBE) (Abernathy et al., 1989; George et al., 1991). Several solid-phase carbon sources have been fabricated and used in standard MBE crystal growth (EPI/Chorus, 1994; Malik et al., 1989). Hole concentrations in HBT base layers exceeding 10’’ cm-3 have been realized without apparent problems with diffusion and redistribution. However, a significant lattice contraction occurs at these high carbon concentrations (above (3- 5 ) x IOl9 ~ m - George ~ , et al., 1991), with strong reductions in the hole mobility due to scattering events (Quinn, 1992- 1993). The formation of large numbers of line defects in base regions for these high carbon concentrations raises significant questions of long-term device reliability. Owing to the issues outlined in this section, there are only a limited number of solely diffusion-based processes remaining in compound semiconductor technology. For example, the JFET fabrication sequences are hybrid processes using diffusion of the p-type species to create the junction or highly doped p-contact region in an n-type material formed by epitaxy or ion implantation (Zuleeg et al., 1984, 1990; Wada et al., 1989). These diffusion processes are similar to those employed in silicon-based process sequences with the notable exception that they require very sensitive control of the process conditions. This is due to the large diffusivity of zinc or beryllium acceptor species, and the need to

prevent dissociation of the host material due to the high vapor pressure of the group V elements. The concern for rapid diffusivities arises also when considering reliability issues: significant redistribution of any impurities or defects in the active regions of the devices will degrade performance and lead to field failures (Hafizi et al., 1990; GaAs ZC,1992, 1993a). This has been observed in HBT devices, for example, where the performance characteristics decay rapidly as the device is operated under moderate to high stress conditions. This deterioration has been assigned to the redistribution of beryllium atoms in the base region of the device caused by thermal and electric fieldaided drift of beryllium ions (Miller and Asbeck, 1985; Hafizi et al., 1990).

-

3.5 Etching Techniques Material removal can be carried out by “wet” chemistry, or by “dry” (vapor or plasma/sputtering) techniques. Etching is used to delineate the features of active and passive devices and to form electrical contacts, gate recesses, and vias. The most critical issue is the ability to create an etched feature which has an optimal morphology compatible with the subsequent processing steps. The choice of wet or dry chemical etching methods depends upon the processing sequence, the required degree of etching control, the compatibility of the materials, and the availability of a suitable etchant for the target material which is benign to the masking or etch stop materials. Additional considerations are the control of undercutting of the mask layer (dimensional control), the creation of anisotropic features, and the permissible process latitude.

3.5 Etching Techniques

Etchants are used in a multitude of critical tasks in the fabrication of an integrated circuit. Various etchants and methods are used in the process sequence for defining features or general etching processes. Anisotropy and selectivity are critical and very useful features of etchants and the different etching processes. The crystallographic sensitivity of the etching chemistry can be utilized to form selectively sloped side walls for smooth metal coverage or to create a controlled undercut to prevent metal continuity where desired (see Sec. 10.9). At the same time, undercutting of photoresist layers by lateral dissolution of the semiconductor or metal can give rise to very undesirable expansion or contraction of etched features. Reaction products are important in all aspects of etching, in both wet or dry methods. Such by-products may impede contact between the etchant species and the surface atoms. They can lead to anisotropic effects resulting from build-up on the various exposed crystallographic planes, or block the etching process entirely. Bonding of the reaction products to the surface may alter the etching characteristics. In wet processes, continual solvation of the reaction products into the solution alters the pH and therefore the etching rates and the chemical activity of the etchant. In a similar manner, the poisoning of the plasma by reacted species may drastically alter the effectiveness of a dry-etching process. The understanding of all of these competing effects is a critical element in developing a viable, controlled, and reproducible etching process. For both dry and wet etching processes, the main limitation in typical processing sequences is the inability to readily etch gold, which is one of the principal metals in compound semiconductor device fabrication. However, ion milling or liftoff pro-

101

cesses produce excellent results in gold metallizations, even with very fine geometries. It should be noted that significant efforts have been directed to creating aluminum-based metallization schemes for interconnects (Vitesse, 1990, 1995), and the use of titanium or tungsten-based metals to overcome the limitations of the liftoff processes needed for gold metallizations (GaAs ZC, 1993b; Dautremont-Smith et al., 1990). Sputtering is also used for the etching of various layers during processing. In this case, the rate(s) of sputtering the desired material(s) relative to that of the masking material(s) is crucial to the success of the process (Melliar-Smith and Mogab, 1978; Chapman, 1980). The chemical anisotropy of the compound semiconductor materials plays an important role in the formation of etched structures. The shape of an etched feature may be strongly influenced by the polar nature of the 111-V or 11-VI zincblendetype or wurtzite-type lattices and anisotropic behavior of the etchant. For GaAs, anisotropic effects are further complicated by the existence of two standards for the substrate orientation. These two options are denoted “SEMI US” (wedge) and “SEMI ,/.I” (dovetail) (SEMI Standards, 1989). Both of these specifications adhere to the same electrical and physical characteristics as the SEMI standards, but they are rotated 90” about the (loo} with respect to each other, as shown in Fig. 3-24. As a result, the same chemical etchant may produce different (rotated 90”)etching features in the two wafer configurations. Thus it is critical to understand the interactions of an etchant with the surface layers to ensure the formation of a desired morphology.

102

3 Compound Semiconductor Device Processing As

As

KOH ETCH PIT

ON FRONT\ SURFACE OF WAFER

Figure 3-24. Crystallographic representations of the two standard configurations for gallium arsenide substrates. The etch pit configurations for each orientation are shown in (b) and (d) and on the central part of the crystal plane image. The etching response of the crystal with respect to the central axis is illustrated by the relative positions of the “V-groove” and “dovetail” etch figures. (a) V-groove option (known as the US standard); (c) dovetail option (known as the E/J standard). Note that the minor flats are 180” in opposition between the two orientations.

3.5.1 Wet Etching

To remove undesired material(s) from the surface region, solutions of appropriate chemicals (acids or bases and diluents) may be used. The etchant solution must be constantly in contact with the target material, and must typically be stirred or sprayed onto the wafer surface to ensure the constant replenishment of the etchant at the surface and to remove by-product materials (Shaw, 1981; Stirland and Straughan, 1976; Iida and Ito, 1971; Mukherjee and Woodard, 1985). The effects of stirring are typically observed as significant increases in etching rates relative to stagnant solutions, as shown in Fig. 3-25. Some means of arresting the etching process rapidly and

uniformly must be provided to neutralize the etchant and completely remove the reacted material@)in order to ensure reproducibility and control. Wet etching occurs by an oxidation process followed by solvation of the reacted species. The etching solution generally contains both the oxidizer and a solvent, and the oxidized species and reactants are preferably readily soluble materials. A complexing or buffering agent may be added to stabilize the etchant chemistry, and deionized water is commonly used as the diluent. A key issue in wet etching control is the boundary layer at the interface between the solution and the semiconductor surface. The schematic understanding of the boundary region is shown in Fig. 3-


103

Temperature ("C) 10

20

30

Solution

k =1

Figure 3-25. Etch-rate dependence on temperature and forced convection. The (8:l :l), etchant is H,SO,-H,O,-H,O with an addition of 50 wt.% citric acid. The ratio of H,O, (30%) to 50 wt.% citric acid is 1 : 1 by volume (k = 1 in the figure). It can be seen that the effects of stirring are dramatic, as is the importance of temperature and therefore temperature control of the etchant and the etching rate. [Reprinted from Howes and Morgan (1985). Reproduced with permission. 01985 John Wiley and Sons, Ltd. Figure caption modified by author (original data after lida and Ito (1975), and Otsubo et al. (1976).]

.\

- 1 W

0

Lz

I

30

3.2

34

36

1 0 ~( K -1' ) ~

26. The boundary layer controls the etching process through the exchange rates of the oxidation-dissolution cycle, i.e., the removal rate of the surface materials relative to the arrival rate of fresh reactants to the surface. For extremely critical etching processes such as gate etching, the oxidizer may be

Diffusion Boundary

I

Etchant Flow

1

Substrate Material

applied first, followed by a solvent solution so as to remove only a very thin surface layer rather than maintaining a constant etching process. Repetition of the process results in a step-wise approach to the final gate trough depth and shape. Table 3-4 presents a number of liquid etchants suitable for compound semiconductor materi-

Bulk Fluid

Convective Transport

Diffusion Limited Transport Reglon

I I

I I I

Dissolved Speclee Into Solvent Bulk I

I

Turbulent or Laminar Flow

Figure 3-26. Schematic representation of the region adjacent to a semiconductor interface during chemical etching. The diffusion boundary layer is the controlling region for the transport of species to, and o u t from, the interface. A similar diagram can be utilized for gas-phase chemistry, with varying meanfree-path lengths and very high convective velocities in the bulk gas phase.

104


Table 3-4. Common etchant compositions for compound semiconductors. Chemical formulation NH,OH:H,O,:H,O

H,SO,:H,O,:H,O

HCI: HNO, HF:HNO,:H,O, H,PO,:H,O,:H,O

Br-MeOH

Ratio

Reference

1:2:20 Shaw (1981) 3 : 1 :50 Gannon and Neuse (1 974) 5:l:l Adachi and Oe (1983) 1:8:40 Shaw (1981) 1 :3 Adachi and Oe (1983) 1:5:10 Adachi and Oe (1983) 5:1:20 Adachi and Oe (1 983) 1 :9:1 Mori and Watanabe (1978) 1 : 100 Adachi and Oe (1983)

als. Choice of a specific chemistry depends on the morphology and degree of control desired in the fabrication sequence. There the two basic limiting mechanisms in wet etching: diffusion-controlledand reaction-rate-limited processes. In the diffusion-controlled case, the transport of reactant to the interface and the transport of the reacted products away from the interface are moderated by the diffusion boundary layer. Material transport limits the etching rate as diffusion coefficients in liquids are typically in the range of 10-5cm2s-’. Therefore it may take a significant time for materials to reach the bulk liquid where convective flows (- cm s - ’ velocities) dominate. Additionally, there may also be an “incubation period” for etching initiation, i.e., the time required to come to a steadystate etching condition due to impeding surface layers or interfacial chemical imbalances. Typical wet etching rates are in the range of a few nanometers per minute to tens of micrometers per minute depending on the etchant agitation and dilution

factors. For example, in a gate etch process where control is crucial, the etch rate employed should be very slow. In contrast, for a backside via-etch a very high rate is needed to etch through (25 pm (- 1 mil) to 350 pm (- 14 mil) of substrate, while at the same time, a high degree of anisotropy is important to prevent lateral spreading and undercutting. Diffusion-limited etchants are relatively isotropic in general, as the surface reaction rate is orders of magnitude shorter than the residence time in the diffusion boundary layer. Agitation greatly affects the etch rates of diffusion-limited processes, as the diffusion boundary layer thickness is easily modulated by forced convective flow (see Fig. 3-26). Thus care must be exercised in wet etching processes to ensure stable, uniform and reproducible etching conditions. In the reaction-rate-limited case, the dissolution rate is determined by the rate of chemical interactions at the interface. Typically, reaction-rate-controlled etchants are anisotropic since the surface reactions are modulated by the availability of free electrons at the surface. Etching is therefore dependent on the surface atom density, the electrons configuration, the doping concentration, and any surface reconstruction. Convective flow generally has a minimal effect on reaction-rate-limited etchants, as the transport of etchant to the surface does not generally affect the reactions unless the solutions are highly dilute. Reaction-rate-controlled etchants may either preserve the morphology existing at the initiation of etching, or more often, develop anisotropic shapes as crystallographic effects influence the local etch rate. Reaction-rate-controlled etchants that exhibit strong anisotropy are very desirable for defining gates, mesas, vias, troughs, or other high-aspect-ratio fea-


tures, but are highly unsuitable for planarizing the surface or pre-crystal-growth surface preparation. In either case the formation of a remanent oxide layer can inhibit the interfacial reactions and material transport, thereby affecting the etch rate in both diffusion and reaction-rate-limited processes. Wet chemical etching is also generally very sensitive to temperature, as illustrated in Fig. 3-25, and may also be sensitive to above bandgap light exposure (electron hole pair generation). Etchant reactivity is nearly always enhanced by an increase in temperature, although depletion or exhaustion of the etchant solution accelerates at higher temperatures (Otsubo et al., 1976). Reaction-rate-limited processes are much more temperature-sensitive than diffusion-limited solutions. During the etching process, the reactions at the surface involve the breaking of many chemical bonds, and therefore energy is evolved. The temperature rise associated with the etching process can upset the local as well as the global etch rate, depending on the etching rate and the net free energy liberated in the reaction. Therefore it is optimal to provide relatively large volumes of etchant, and to provide temperature control to ensure stable etching conditions. The sensitivity to light is manifest through the creation of electron-hole pairs in the surface region, which may affect the charge exchange processes at the semiconductor etchant interface. The presence of near or above band-gap energy may increase etching rate or create anisotropic effects from surface charge density differences. Thus care must be taken to control illumination of the wafers, the light intensity, and the spectral content, to ensure reproducible etching processes. A difficulty with wet chemical etchants is maintaining the reproducibility of the

105

chemistry and reaction conditions. Several problems can arise in wet chemical etching processes: sensitivity to the etchant, temperature, the pH of the solution, chemical depletion, the presence of light, passivating layers, and the methods of application, e.g., immersion, agitation, spray and spin, etc. The etchant solutions deplete with usage (buffering may slow this process) and age (chemical breakdown during storage, heat, or exposure to air). The chemical potentials are altered (the pH changes) and diluent species (water and other contaminants) are formed during the reactions, thereby diluting the solution. Light of an appropriate wavelength can increase the etching rates may-fold by creating electron- hole pairs at the surface or assisting in the breaking of bonds. The presence of an increased charge density (dopant species) will nearly always increase the reaction rates at the surface. Wet etching solutions often produce gaseous by-products (e.g., H,, O,, Cl,, Br,, or other volatiles). The formation of bubbles and bubble streaks on the wafer may inhibit or acclerate the etch rate depending on the nature of the surface reactions. This bubbling phenomenon may lead to nonuniform etching across the wafer surface, and can damage the surface region morphology. For example, spiking at mask edges and openings can occur due to stagnation of the etchant material (Shin and Economou, 1991).Agitation or stirring can alleviate some of these problems. The use of spray etching methods avoids the difficulties of immersion-type etching baths, and can produce vastly superior results in terms of reproducibility and control of the etching process (Grim, 1989, 1990). Anodic etching is another method for removing the surface atoms in a controlled manner. Here the wafer is fitted with an electrical contact, immersed in an etchant

106


solution, and then biased to create a depletion region of the surface. The anodic oxidation reaction creates an interface charge which balances the impressed electric field. As etching proceeds, the surface potential is gradually equalized over the wafer surface, i.e., a relatively uniform surface oxide is created. Subsequently, this oxide may be removed by a suitable solvent and the process repeated until the desired amount of material is removed. In principle this method is well-controlled. In practice, significant problems arise with localized variation in the surface potentials, nonuniform current distribution, effects of localized charge (e.g., n- or p-type regions, semi-insulating regions, etc.), the impact of residues and surface contamination, and the presence of metals, which greatly complicate control of the etching uniformity. The high resistivity substrates of GaAs and InP used in IC fabrication also cause problems owing to the limited current flow permitted with reasonable bias voltages. Furthermore, the etching occurs in discrete steps which creates a “digital” thickness change with each step and protracts the etching cycle greatly. Some of the additional problems associated with wet etching are the undercutting of the surface layers or masks due to capillary effects and chemical anisotropy. Surface tension, viscosity, anisotropy, solubilities, and convective flows all conspire to reduce the control over the critical dimensions, the morphology, and the uniform arresting of the etching process. The capillary effects may be realized as “blow-out” or expansion of the feature peripheral dimensions, and contraction (undercutting) of interior features. These phenomena also affect the control of the etching end-point when rinsing the etchant from the surface. Crystal lattice and etchant anisotropies, as well as flow-related effects and surface

tension effects, can radically affect the shape of the etched feature. Some illustrations of different feature shapes are shown in Fig. 3-27. Once the desired chemistry is determined and understood, wafers may be routinely processed with wet etching methods. The etching of gates, vias, mesas, and channels are quite similar processes, the aim being to create a hole in, or a mesa on, the surface for the purpose of forming the gate trough, holes for interconnect vias, and isolation between devices, respectively. Wet etching may be used to subtractively define resistors on or in the surface layers, although dry techniques are generally preferred for this process (see Sec. 3.5.2). In addition, wet chemical processes are typically used for the preparation of the substrate surfaces prior to crystal growth or processing. For additional information, see Williams (1990, Chap. 5). 3.5.2 Dry Etching

Dry etching of compound semiconductor materials encompasses the generic methods of plasma-based surface decomposition: sputtering, plasma etching (PE), reactive ion etching (RIE), reactive ion beam etching (RIBE), and electron-cyclotron resonance etching (ECRE). All of these etching technique involve the creation of excited or reactive chemical species which selectively physically sputter, or react with, the target material(s) while minimally affecting the masking agent and those desirable materials that remain. Successful dry etching processes require careful selection of the reactive species, etching conditions, duration, control of the gas mixture, and the temperature. Dry etching is typically carried out in a reduced pressure environment. High-volume vacuum pumps (for maintaining a low


107

Figure 3-27. A schematic illustration of various etched shapes which can be created by wet or dry etching techniques. In a) a strongly “undercut” shape is shown. This morphology would be ideal for a metal liftoff process, but undesirable for metal or dielectric coverage. In b), the crystal anisotropy has dominated the etching process, producing an etch morphology that has been limited along the { 1 11 } crystal planes. Figure 3-27c illustrates a method by which very small features may be created: undercutting the masking material. Here a feature substantially smaller than the mask line is formed as material is removed from the exposed sides of the desired material. Depending on the etching conditions, anisotropy, and chemistry, vertical side walls, selectively curved side walls, or undercut features may be created, or highly selective etching may be carried out.

pressure), high-tension power supplies and field plates for developing a confined high electric field, controlled injection of the appropriate gases, an ion source (if needed), and monitoring of the process are required. Many configurations exist for these apparatus, but all systems contain the same basic components. A generalized system configuration is shown in Fig. 3-28. Dry methods are suitable for etching most of the materials present in a compound semiconductor integrated circuit process sequence. As with wet etching, gold is not etched by plasmas, although it can be sputter-etched.

Dry etching processes have excellent spatial resolution and the uniformity is typically very good, variation being of the order of a few percent across a 3” (76 mm) diameter wafer in a well-controlled process (O’Neill, 1991). Plasma etching processes have been used to define laser facets, gate troughs, and isolation mesas, as well as to form via structures. These methods have been used to define submicrometer gates (Sauerer et al., 1992), 40 pm diameter through-wafer vias (Chen et al., 1992), and achieve etch rates of 50 pm per hour (Kofol et al., 1992).

108


Figure 3-28. A schematic illustration of a generic plasma etching system. The plasma, containing a strongly reactive ion, is generated by RF excitation, with optional DC biasing. The reactive gas is injected into the plasma region and maintained in a dynamic vacuum condition. In this configuration, ions may directly bombard the water surface and induce damage in the semiconductor.A carrier or ballasting gas may be used to modulate the reactivity and etching rates. Rotation may be used to enhance the uniformity of the etching process. Heating may be used to accelerate or control the etching rate. Exhaust treatment may be required to handle toxic by-products.

There are several mechanisms that remove material during all types of plasma etching: physical sputtering, chemical etching, and reactive ion etching. Complicating the reactant removal and promoting continued surface reaction are problems associated with the formation of reaction by-products, surface and gas-phase polymerization, and other reaction inhibitors. These by-product materials act as contaminants in the plasma, as diluents in the gas stream, and block access of the surface to new reactant species or tie-up the reactant species in the gas phase through the formation of complex molecules or polymeric species. Chlorine-, fluorine-, or bromine-containing compounds are preferred for the etching gas. Such species as CCl, (Sato and Nakamura, 1982; Inamura, 1979), C1, (Donnelly and Flamm, 1981), HCl (Smolinsky et al., 1981), SiCl, (Sato and Nakamura, 1982), CF, (Schwartz et al., 1979; Harada et al., 1981), CCl,F, (Hosokawa et al., 1974; Smolinsky et al., 1981), and

BCl, (Tokunaga et al., 1981; Hess, 1981) are commonly used in plasma or reactive ion etching systems. The etching rates of various materials can be balanced or controlled with additions of ballasting gases, such as argon or helium, and the total system pressure may be modulated to alter the impingement and interaction rates at the surface. A process utilizing these types of chemical species is relatively hard on the apparatus, readily attacking the system components in the chamber, the gas control valves, feeds, injectors, pumping systems, pump fluids, and exhaust systems and waste treatment facilities. The selection of components is critical for mitigating contamination of the semiconductors. Exhaust scrubbing is often required to mitigate the polluting effects of the effluent gases. The excitation voltage and total RF and DC energy input to the plasma controls the ion creation rate and determines the ion energy distribution. There are frequency-dependent effects in the plasma, excita-


tion being carried out typically at either 300-455 kHz or 13.6 MHz (frequencies that do not interfere with communications bands) which alter the ionization efficiencies, ion densities, and energy distributions. The use of 13.6 MHz excitation results in minimal surface damage, while 300455 kHz excitation tends to severely exacerbate the damage. This can be understood from the point of momentum transfer to the ions: at the lower frequency, ions can travel a significant distance during a cycle, readily impinging onto the surface, causing atomic displacements. At the high frequencies, however, the ions have substantially less time to accelerate into the surface region, and thus have a lower probability of damaging the surface atoms. In addition, the electric field strength and the geometry of the plasma excitation plates have a strong influence on the etching process by affecting the flow of ions to the wafer surface. The system pressure may be controlled over a moderate range which also changes the plasma density, the reactive ion density and formation rate, and thus the etching rate and selectivity (feature shape). Since the plasma contains a significant amount of energetic species, the temperature of the substrates rises typically to -200°C to -300°C during the etching cycle. Heating or cooling of the substrate may be required to control of etching process. For the various materials exposed to the plasma during etching, the selectivity for removal is determined predominantly by the chemistry of the plasma, but also affected by the system operating pressure (impingement rates). For example, the etching of heterostructure materials (e.g., GaAs- AlGaAs materials) may be carried out selectively or nonselectively by plasma methods depending on the gas chemistry and relative etch rates. Typical dielectric

-

109

materials (oxides and nitrides) are readily etched by dry techniques, as are photoresists; the latter are removed particularly well in oxygen-containing plasma (“ashing” processes). Most metals, except gold, are also etched easily in plasma containing reactive species such as chlorine, fluorine or bromine (see Williams, 1990, Chap. 9). One major concern in plasma etching is ensuring that the protective coatings maintain their integrity during the etching cycle. A key to the successful implementation of plasma etching is controlling the damage induced by energetic ion bombardment of the exposed surfaces. This is especially true for devices using “shallow” p-n junctions or lightly-doped layers in the materials structures. Damage created by the injection or recoil of energetic ions can produce atomic displacements and create donors, acceptors, and deep levels, thereby altering the charge in the surface region. For example, to mitigate these effects there are parallel plate configurations with differing ratios between the upper and lower plate areas that control plasma confinement (density and impingement rate) and ion guiding effects, and “downstream” designs wherein the plasma region is confined “upstream” well away from the substrates (Pearton et al., 1991). This latter design approach attempts to minimize the direct ion bombardment of the surfaces. Here the reactive species formed in the plasma are swept through the chamber and across the wafers by a flowing carrier gas stream. A multitude of other competing variables exist in the plasma system and process: the gas-phase composition, chamber materials, biasing of the substrates, ion damage thresholds for the substrate materials, as well as sputtering of the chamber materials. All of these system variables contribute to variations in the etching rates. Etch rates and profiles are strongly influenced

110


by the pressure of the chamber, the gas chemistry, and even the slightest trace of contaminants in the etching chamber. Sputtering is the process of physically “blasting” atoms from the surface by atomic interactions. Typical sputtering systems have a source of energetic ions created by a DC or AC plasma in a diode configuration. The sputtering rates are controlled by the pressure, gas mixture, current, and voltage in the system. Argon ions are a preferred species as the gas is available relatively pure, is readily ionized, and the ion is massive. Charge separation in the plasma causes the argon ions to be attracted to the negatively charged (wafer) electrode. The ion impact sputters away the surface layers. Sputtering is carried out in relatively small volume chambers with a small spacing between the plates (- 10 cm). These systems are operated at total pressures of to -1 Torr (0.13133Nm-2). With a small chamber and close proximity of the plates, continuous redeposition may occur as it is difficult to extract the sputtered material rapidly from the center of the chamber. Contamination of the semiconductor material can occur by redeposition and decomposition of the chamber materials, and by implantation by ion bombardment at the surface. “Passivation” of the surface or redeposition may slow the etching process by interfering with the sputtering rates of the desired species and create nonuniform etching profiles over the wafer surface. Etch masking must be quite robust to withstand the continuous ion bombardment in sputtering or plasma processes. Thick photoresist (PR) layers or multiple PR/metal layers may be used to resist the ion flux. A balance of etching rates between the mask materials and the semiconductor is generally the best achievable compromise in practice. Metal layers etch substan-

tially more slowly than the semiconductor or photoresists. Thus relatively thin metal masking layers may be used to assist pattern definition, permitting very tine features to be carried. Etch feature side wall definition is generally poorer with sputtering processes relative to other approaches. The high wall angles desired for deep trenching (isolation) cannot be achieved easily by sputtering, due to the limited interaction of the ions with the surface at high incident angles and the high probability of redeposition within the trench. RIE/RIBE/PE processes operate at low pressures, in the range l o p 3Torr (0.13-0.0013 N m-2). RIE/RIBE chambers have relatively large electrode spacings, and lower energies (smaller potentials) are impressed, providing a cleaner environment for the etching process and somewhat reduced redeposition rates. The strongly enhanced etching comes from the reactivity of the ions rather than the energy imparted to the etchant species. Unlike plasma etching where the low-energy plasma consists of ions, radicals, and various molecular species, electrons, protons, etc., an ion source (RIE) or directed ion beam (RIBE) creates a selected set of ionized species to affect the etching. These systems exhibit somewhat slower etching rates than those of sputtering processes, predominantly due to the limitations of the ion sources. Plasma etching tends to be isotropic, whereas RIE and RIBE can be used to control the etched morphology and have very limited sputter damage and redeposition. The latter two points are very critical in device structures that incorporate field effects for charge modulation (FET-type devices and lightly-doped structures, for example). PE operates at higher pressures than RIE/RIBE, with relatively low power, and etches at moderately low rates. While


there is less surface damage created than with sputtering, PE still embodies a significant amount of damage and contamination from the plasma and chamber components. Operating at higher potentials generally leads to greater anisotropy in the etching, but greater damage to the surface due to implantation processes. RIE/RIBE carried out at higher voltages can produce near-vertical side walls due to impingement near 90”. In RIE/RIBE the etching is caused predominantly by the reactive species rather than all of the particles in the plasma, as in PE. The ion source in RIE/RIBE provides a reactive ionized species containing a group VII (chlorine, fluorine, or bromine) atom or molecule. For most 111-V materials, the chlorine and bromine compounds produce highly volatile reactants and are therefore preferred over the fluorine compounds (Burton et al., 1983; Ibbotson et al., 1983). Polymerization is a concern with any of these compounds. The objective is to provide selected, low-energy, reactive ions to the surface of the wafer whereupon they form volatile complexes with the surface atoms. This volatility limits redeposition as the complexes and compounds do not readily decompose or attach themselves to the surface of the wafer. A variety of halogenated compounds have been used as reactive ion sources: CF,, CCl,, BCl,, CBr,, or other chloro-fluoro carbons. CBr,CI,, CHCl,, and C,Cl, have been found to readily form polymeric compounds and by-products, and are generally unsuitable for RIE/RIBE. Construction materials (chamber walls, shields, electrodes, etc.) for RIE/RIBE systems are of critical importance as the reactive species may cause the system components to decompose and contaminate the wafers. RIBE is differentiated from RIE by the use of collimation to create a directed

111

beam of extracted ions from a high-density plasma source. This beam-like ion stream permits variation of the angle of incidence to the surface, thereby affecting the etching rates and morphology (Ide et al., 1992). Surface reactivity is not dependent on the incident angle to the first order, and therefore the side wall angle can be affected through the angle of incidence. The ability to control the interaction of the ions with the surface mitigates the problems of morphology control independent of the ion energy. RIE/RIBE are carried out in a parallel plate system, selecting the reacting ions by gas injection or ion extraction, under appropriate bias conditions. Etching occurs by chemical reaction and subsequent desorption of the reactants. The ability to create nearly vertical side walls at moderate bias voltages is a distinct advantage of RIBE. As with all plasma systems, RIE/ RIBE etch rates are influenced by pressure, gas mixture, ion density, and excitation power. Problems may occur with polymerization between certain etchant gases and the reactant species, which can inhibit the etching. RIE/RIBE are significantly better than sputtering techniques for most applications, having lower damage due to the lower ion energies and reduced contamination (with proper chamber construction). Electron-cyclotron resonance etching (ECRE) processes involve the selective excitation of an ionized species through a high frequency resonant coupling process (Pearton et al., 1991). Figure 3-29 schematically outlines an ECRE configuration. The excited ions are typically created well away (“upstream”) from the etching chamber to minimize direct ion bombardment damage to the wafer. Ions are extracted from the ECR source by the electric fields and the pressure gradient in the system: The etching processes occur in a manner

112


Optical or ion monltoring End Polnt Detection

I Figure 3-29. A schematic illustration of an ECR-plasma etching system. The ion plasma, containing a strongly reactive species, is generated by exciting electron-cyclotron resonance of the desired chemical species. The source is located “upstream” from the etching chamber to protect the wafer from direct ion bombardment. A carrier or ballasting gas flows through the ion source and the chamber, assisting in the transport of reactive ions to the wafer. Electronic extraction may be used to pull ions from the source. Rotation or heating may be used to enhance or control the uniformity and rate of the etching process. Exhaust treatment is generally required to handle toxic by-products in compound semiconductor processing.

similar to RIE/RIBE. ECRE has the advantages of “clean” etching as it is carried out in a high or ultra-high vacuum environment, gives very minimal surface damage (with low to moderate extraction/ accleration potentials), negligible redeposition, and reasonable etch rates (Pearton et al., 1991). Run-to-run reproducibility is somewhat difficult to control in plasma techniques as there is no convenient and accurate method for monitoring the etching rate. Control of the end point may be enhanced by the incorporation of etch-stop layers, monitoring of the reaction product generation rate, or the presence of specific reacted species (chemical indicators) in the plasma or exhaust gases. These techniques can provide adequate end point detection to determine the completion of the etching cycle. Presently, the best control parameter is tracking of the reactant species evolution by residual gas analysis, optical absorption, or similar methods to determine an

end point indication. Further development and refinement of gas-phase sensors will result in greatly improved control of plasma-type processes.

3.6 Ohmic Contacts Ohmic contacts provide low resistance current paths and interconnection between devices. The creation of the ohmic behavior is, and has been, a source of perpetual investigation and development activity in compound semiconductor materials (Braslau et al., 1967; Matino and Tokunuga, 1969; Schwartz, 1969; Edwards et al., 1972; Otsubo et al., 1977). The underlying difficulty in creating an “ohmic” contact is that Schottky barriers are formed when most metals are brought into initial contact with the semiconductor surface (Schottky barriers are considered in detail in Sec. 3.7). Therefore some means of eliminating this barrier must be developed. The details of

3.6 Ohmic Contacts

113

Vacuum Level Metal

Semiconductor EC

EF

EV

Metal

--

Semiconductor

EC E~

Is..‘&**Iys

EV f------)

W Depletion Width

the mechanisms behind the formation of ohmic contacts are not yet fully understood in spite of more than 50 years of work [see Sharma (1981)l. From a theoretical and physical standpoint an ohmic contact begins as a Schottky barrier, as shown in Fig. 3-30. The work function of the metal and semiconductor are initially offset as the Fermi energy is constant across the interface. This band offset creates a barrier to charge flow from the semiconductor to the metal, as attributed to the investigations of Schottky [see Chap. 5 in Sze (1981)], giving rise to a diode transfer characteristic. The Schottky barrier height is defined as the difference of the metal and semicon-

Figure 3-30. Initial formation of a Schottky barrier prior to annealing to create an ohmic contact. In a) 4,,, is the metal work function, x, is the electron affinity of the semiconductor, E, is the semiconductor energy gap, and E , and Ev are the conduction and valence band energies, respectively. E, is the Fermi energy and q V, is the difference between the Fermi level and x, relative to the vacuum level. b) As the metal is brought into contact with the semiconductor, charge is exchanged to maintain a constant Fermi energy. This creates a depletion region, W,in the semiconductor to balance the electrons in the metal. The semiconductor energy bands “bend” to reflect the charge distribution in the nearsurface region. The Schottky barrier height is &, and the junction buildin potential is Vbi at equilibrium (no applied bias).

ductor work functions

6 m -4 s =6 B

(3-4)

As long as the quantity +B is significantly greater than zero, a barrier to charge transport exists, and the flow of charge will not be linear with applied voltage (electric field strength). The formation of an “ohmic” contact to the semiconductor involves metallurgical reactions which create a transition from a Schottky barrier condition to a graded energy band structure with a negligible barrier height (Schwartz and Sarace, 1966; Schwartz, 1969; DiLorenzo et al., 1979). The initial formation of a depletion region (W) with the creation of a Schottky barrier

114


is illustrated in Fig. 3-31. The width of this depletion region is proportional to the square root of the doping concentration (in the abrupt junction approximation) governed by the relation (Sze, 1981, Sec. 5.2)

As the doping level is increased the depletion width shrinks, the interfacial electric field (Emax)becomes greater, and field emission, thermionic emission, and tunneling processes may readily occur. It is desirable to have: 1) a small & such that kT/q is “large”, or 2) a degenerately-doped semiconductor so that tunneling and/or field emission processes have a high probability. A model for this latter point was discussed in the light of the depletion width being substantially smaller than the depth of the degenerate layer. Thus tunneling and thermionic emission processes are facile, and the barrier to transport is negligible (Popovic, 1978). Conversely, as the doping density decreases, the depletion width increases and the metallurgical junction must be formed deeper into the semiconductor to affect an

ohmic behavior. Also, since there are fewer charges available in the semiconductor, the conductivity is reduced. All of these effects contribute to higher contact resistances for “lightly” doped materials, and make the formation of a high quality ohmic contact more dimcult. There is no consensus on a precise model and understanding for the ohmic contact formation (see Sharma, 1981, or Schwartz, 1969). Some investigators consider the interface to be a disordered alloy with “mobility gap” states (Peterson and Adler, 1976), while others interpret the interface as a transition from the metal through an amorphous region to the crystalline semiconductor material (Wey, 1976; Riben and Feucht, 1966). At present, resolution of these arguments remains unclear. Further investigations may some day shed light on the exact phenomena. For a more detailed theoretical development of ohmic contact electrical behavior see, for example, Chap. 5 in the book by Sze (1981). To eliminate the Schottky barrier and produce an ohmic behavior, a metal contact material must generally be alloyed into the semiconductor. The metal reacts with the semiconductor forming multiphase intermetallic compounds, lowering the barrier potential, and stretching the

Semiconductor

Depletion Width

Figure 3-31. The creation of a depletion region of width W in the surface region of an n-type semiconductor. ED is the donor energy level relative to the conduction band edge, &, E,, Ev, E,, and E , have their usual meanings. Vbi is the built-in potential. The depletion width is inversely proportional to the carrier density as in Eq. (10-5).

3.6 Ohmic Contacts

115

Figure 3-32. Creation of an “ohmic” contact to a semiconductor. In a) the barrier height, &, is very small, presenting a negligibility barrier to electron flow. dB,E,, ED,Ev, E,, and E , have their usual meanings. In b) the surface region of the semiconductor is doped to an n + degenerate condition (high electron density, Fermi level in the conduction band). The depletion width is dramatically narrowed. Thus tunneling processes may readily occur. Both of these processes may contribute to the ohmic behavior.

band-bending into the semiconductor, as illustrated in Fig. 3-32. Electron (or hole) flow is impeded less and less as the alloying process advances. If the condition

-

c$m - (bs = c$B 0 volts

(3-7)

is met for an n-type semiconductor material, then the contact is considered to be ohmic in nature. For small positive values of (bB(a small Schottky barrier height), significant tunneling and thermionic emission can occur permitting significant current

flow with a small forward bias. Thus only a very small resistive component is realized. Surface states and surface charge may also affect the barrier height and charge distribution in the semiconductor, and therefore the I- V behavior. This latter point is particularly important for devices which are lightly doped (“enhancement mode”) and therefore very sensitive to changes in near-surface depletion or the accumulation of charge. The contact resistance (R,) is derived from the thermionic I - V theory for an

116


ideal Schottky contact. The definition of R , is nkT R,=at V = O (3-8) 4 Is,,

A plot of logl vs. V should result in a straight line of slope q/(nkT) where n is the ideality factor from Schottky junction theory, k is the Boltzmann constant, q is the elementary charge, T is the temperature, and I,,, is the reverse bias saturation current. Typically, n is in the range 1.0-1.1 for a good ohmic contact; values very near 1 .O are most desirable. A critical feature of the ohmic contact is the linearity of the I - V relationship: any diode-like characteristics are undesirable. Contact metals must be deposited on clean surfaces to prevent erratic intermixing of the metal and semiconductor during alloying, particularly with reactive species such as aluminum or titanium. Typically, at least one of the components of the metallization is a donor (e.g., Si, Ge, Sn, Se, or Te in n-type, 111-V compounds) or an acceptor (e.g., Zn, Cd, Be, or Mg in p-type materials) species in the host semiconductor. This will greatly increase the ease of ohmic contact formation as the effective doping density can create a highly degenerate layer in the interfacial region of the metal and semiconductor. The alloying process causes intermixing of the metal, the doping species, and the semiconductor, as discussed above. However, many considerations arise in the process of alloying: chemical reactivity or inertness, diffusivity of the various species, the phase diagram for multi-component systems, surface tension, processing limitations (thermal and morphological) from previous steps, adhesion, defining geometry (masking),stability of the intermetallic phases, compatibility with the wire bonding metallurgy, etc. The phase diagram and the kinetics of the inter-

mixing process determine, to a large extent, the achievable barrier reduction and thus the conductivities of the interfacial metallic region. It is desired that the contact resistance be as low as possible, typically in the range of l o - ’ to R cm2 for n-type materials, and about ten times larger for p-type materials principally due to mobility differences. The range of interactions generate a large number of compromises in the development of a viable, manufacturable, and stable ohmic contact formation process. The fabrication of ohmic contacts begins with careful surface preparation, followed by deposition of metal@)and/or metal alloys. There are a multitude of methods and metallurgical systems suitable for the formation of ohmic contacts to 111-V compound (Sharma, 1981; Schwartz, 1969; Palmstrom and Morgan, 1985). Table 3-5 highlights a number of these metals systems; numerous other alloys have been evaluated. Predominantly, metallurgical systems based on Au-Ge, and more typically Au-Ge-Ni, are the most studied and in general use. For additional information see Sharma (1981), Howes and Morgans

Table 3-5. Ohmic metallizations. Metallization

In Sn Au-In Au-Sn Au-Ge Au-Ge-Ni Ag-In Al Ag-Zn In-Zn

Semiconductor type

Reference

n n n n n n

Wronski (1969) Schwartz and Sarace (1966) Paola (1970) Henshall (1977) Fukuta eta). (1976) Shih and Blum (1972), Kuan et al. (1983) Matino and Tokunaga (1969) Shih and Blum (1972) Ishihara et al. (1967) Matino and Tokunaga (1969)

n, P P P P

3.6 Ohmic Contacts

(1985, Chap. 6), Williams (1990, Chap. l l ) , and the associated references therein. Evaporation methods are particularly useful for multi-component metallizations. While heating of the substrate material must be carefully controlled through the deposition rate and intentional heating or cooling of the wafer, control of the thickness and deposition rate are very good. Compositions can be controlled either through multiple deposition steps, co-deposition, or the use of alloys as charge materials. Sputtering and plating-type processes can also be used to deposit the metal on the semiconductor, although plating is rarely implemented for top surface metallizations in practice. Sputtering methods generally have lower deposition rates, can generate substantial damage in the semiconductor, and thickness control is difficult. On the other hand, sputter damage to the interfacial region may lead to lower contact resistance through the creation of defect states and disorder at the surface. Plating processes rapidly build up layer thicknesses, but tend to be rather “dirty” from the chemical standpoint, and have problems in relation to control of the surface morphology and layer thicknesses. In some processes, such as backside ohmic metallization or bonding pad formation, where metal thickness control is relaxed but thick layers are desired, plating processes are the method of choice. Ohmic contact topology may be defined by standard photolithographic patterning methods after deposition. Liftoff patterning, photoresist or dielectric assisted, is the most common method for the removal of unwanted metal (see Sec. 3.1 1.2), provided the deposition process has not created a completely uniform layer of metal over the photoresist or dielectric surface topology. Aluminum and other non-gold bearing metallizations may be

117

patterned by dry etching methods such as RIE (as discussed in Sec. 3.5.2). Ion milling may be employed for patterning gold or gold-bearing alloys, or tungstenbased contact materials. The annealing of most metallizations used in IC fabrication is very critical. “Spiking” and other deviations from planarity can occur even with mild over-alloying (i.e., excessively high temperatures or extended alloy time), making subsequent processing more difficult (Gyulai et al., 1971; Zeng and Chung, 1982; Palmstrom et al., 1978; Miller, 1980). Spiking of the contact metal in the compound semiconductor systems is quite similar to that observed in the Al: Si system at edges of contact windows. Lateral spreading has a negative impact on electric field distributions and may cause short-circuiting in fine geometries [see Goronkin et al. (1989)l. Roughness or texturing in the contact region is apparent after alloying especially if “over-alloying” has occurred. Even 20 30°C over-temperatures (in the range of 400 “C for NiGeAu-based contacts to GaAs materials) or slightly extended cycle times can cause the metals to “punch through” active layers, as shown schematically in Fig. 3-33. Lateral spread of the contact materials may lead to uncontrolled electrical behavior in active and passive devices, such as low breakdown voltages or leaky characteristics. Roughness of the contact sites may also negatively impact subsequent alignment, photoresist, and other processing steps. A minimal thermal budget is typically used for alloying processes employing a furnace, “hot plate”, or rapid thermal annealing (RTA) system. The objective is to minimize the metallurgical interaction while maximizing the conductivity of the alloyed-contact region. For n-type materials, using gold-based metallurgy, the alloy~

-

118


Figure 3-33. Schematic representation of annealing effects on Ni-Au-Ge contacts to GaAs. In a) the metal regions have been deposited and defined by lithography. In b) the material has been annealed. The angular structure of the NiAs(Ge) crystal structure, represented by the shaded region, is characteristic of the metal-semiconductor interaction during annealing. This has been observed in several TEM investigations (Zeng and Chung, 1982; Parsey, 1990). Excessive annealing will produce punch-through of the metal below the n-layer, as shown.

ing process is carried out at relatively low temperatures ( I400 “C) and short times (of the order of 5-10 min), or in RTA systems with somewhat higher temperatures (- 500°C) but shorter durations (ca. 30 s) the contact metallurgy is controlled sufficiently to create a reproducible, low-resistance contact to the n-type materials [see Sec. V in Sharma (1981)l. Similarly, the Au-In and Au-Zn alloy families are commonly used for p-type contacts. Owing to the lower carrier mobility, and thus the higher resistivity of p-type materials, a higher doping level is required to achieve low contact resistance (doping levels are usually greater than l O I 9 cm-3) to achieve a highly degenerate region. It is possible to form “nonalloyed” ohmic contacts to GaAs and other compound semiconductors provided suffi-

-

ciently high doping concentrations exist in the surface layers. Typically, electron densities greater than (3-5 x loi9 cm-3 are necessary for a nonalloyed contact to n-type material (Chang et al., 1971). If the semiconductor bandgap energy is small or can be reduced, for example, by the addition of an alloy component, e.g., InGaAs, the formation of nonalloyed contacts is facile. The use of In,~,Ga,~,As as a low resistance contact to HBT devices has attracted significant interest (Poulton et al., 1994; Huang et al., 1993). Keys to creating this type of contact are: 1) the relatively small bandgap of In,,,Ga,~,As (approx. 0.8 eV); 2) the degeneracy of the semiconductor (high surface doping concentration); 3) the formation of an extremely thin depletion region (c10 nm) at the surface. Charge flows easily via tunneling and ther-

3.7 Schottky Barriers and Gates

malization processes, as well as requiring only minimal electric fields to drift the charges across the metallurgical junction. Detailed analyses of the ohmic contact and interfacial reactions have been made by numerous techniques, among them, X-ray diffraction (Ogawa, 1988), Auger electron spectroscopy (Robinson, 1975), transmission electron microscopy (Kuan et al., 1983), scanning electron microscopy (Robinson, 1975), and secondary ion mass spectroscopy (Palmstrom et al., 1978). The information obtained has led to a detailed understanding of the interactions and control of the alloy process (see Howes and Morgan, 1985, Chap. 6 ) . The reactions of gold-based ohmic alloys have been studied at length. A number of investigators have studied the interaction of gold and goldalloy materials with GaAs (Zeng and Chung, 1982; Vandenberg and Kingsborn, 1980) and InGaAsP (Vandenberg et al., 1982; Vandenberg and Temkin, 1984) and found that, as predicted from the phase diagrams, numerous intermetallic compounds form during the alloying process. For example, in the reaction of gold with GaAs, formation of the Au-Ga alloys occurs with the resulting loss of arsenic from the surface, and the creation of AuGa, and AuGa; p and y intermetallic phases are created, as shown in Fig. 3-34 [Massalski (1986), pp. 258-2611. Contact resistance in most ohmic contact systems has been found to increase if undesirable (high resistivity) phases form. For example, in the Ni-Au-Ge contact, if or-Au:Ge or Ni-Ge are created in significant amounts, or if excess gold diffuses into the semiconductor surface region, the contact resistance will be increased. In contrast, the contact resistance will be lower if Ni-As and the in-diffusion of germanium occurs and A u :Ga forms. Schmid-Fetzer (1988) has recently reviewed the phase rela-

119

tionships and predicted interactions of a large number of metals for potential contacts to GaAs. Contacting thin layers (of the order of a few tens of nanometers) is a dificult task due to the necessity to consume some of the surface material, to form the correct phase@),and the complication of uncontrolled in-diffusion processes due to surface defect formation. The varied and rapid diffusivity of the various component metals also complicates control of the alloying to very thin layers.

3.7 Schottky Barriers and Gates A Schottky barrier is the rectifying contact which forms when a metal is brought into contact with a semiconductor material. This structure is a charge dipole which creates a depletion region analogous top a p-n junction diode. Schottky barriers are the heart of most FET-type devices. The charge flow in the transistor is modulated by the bias applied to the Schottky barrier gate metal during device operation. The “barrier height”, in conjunction with the available charge density, determines the threshold of the switching action and the conduction state of the device at a given bias condition. In Fig. 3-35 the formation of a Schottky barrier is illustrated. The semiconductor material and the metal possess different work functions relative to the vacuum energy levels, 4,,, and 4s,respectively. As the metal is brought into contact with the semiconductor, charge is exchanged between the materials so as to balance the chemical potential of the electrons and holes, i.e., the Fermi energy level is constant across the interface. The metal contributes -1 electron per atom, and the semiconductor typically lop4to lop6elec-

120


Weight Percen t Gallium 1200

0 I

..

. . . . I . .

. ....

,

10

20

..

..-

30 1.

.

40

50

60

70

80

90 100

L

Au

Atomic Percen t Gallium

Ga

Figure 3-34. The Au-Ga phase diagram showing atomic percent (left figure) and weight percent (right figure) relationships. Numerous intermetallic phases can form in the temperature range 274°C to 491 “C, which can greatly affect the morphological and electrical behavior of annealed contacts [after Massalski (1990),p. 3701. Reprinted by permission of ASM International.

-

trons per atom. Charge exchange creates the dipole layer and charge equilibrium is established. As a result of the imbalance in the charge density, a depletion region, “W’, is formed in the semiconductor. From Fig. 3-35 the relationship

may be observed. The difference between the electron afinity of the semiconductor, x,, and the metal work function, &,,is the Schottky barrier height, +B. In principle each semiconductor-metal system should have a unique Schottky barrier height

based upon the configuration of Fig. 3-35. In’ reality, surface states, surface reconstruction, impurities, and defects may all act to “pin” the Fermi energy. Thus the barrier height values are confined to a relatively narrow range, as evident in Table 3-6. This phenomenon is the subject of intense investigation [see, for example, Spicer et al. (1980), Brillson et al. (1983), and Williams (1982)], and remains unresolved at present. The current flow in a Schottky diode is described by the relationship

I = I , {exp[q V/(kT)]- l }

(3-10)

121


Atomic P e r c e n t Gallium 0

10 20

30

50

40

60

70

80

90

Weight P e r c e n t Gallium

Au

100

Ga

Figure 3-34. (continued).

Table 3-6. Schottky barrier heights on selected com-

pound semiconductor materialsa,b. Metal

Semiconductor material GaAs

AlAs

InP ~

A1 Au Ag W Ti Ni Pt

0.80 0.90 0.88 0.80

0.83d 0.7ld 0.84

-

1.20 -

0.52' 0.52 0.54

-

-

-

-

-

-

1.0

GaP

ZnSe

1.07 1.30 1.20 1.12 1.27 1.45

0.76 1.36 1.21 1.40

~~~

Values in electronvolts at 300 K; from Sze (1981, p. 291); Sharma (1981); Waldrop (1984).

a

where q is the elementary charge, V is the applied voltage, k is the Boltzmann constant, and T is the absolute temperature. I, is the thermionic current

I,

= A*

T 2exp [ - 4 +B/(kT)]

(3-11)

where A* is the Richardson constant, +B is the Schottky barrier height, and the other symbols have their usual meaning. From Eq. (3-9) if & > x,, then 4B> 0 and the structure will be rectifying. Thus an ideal diode would have an infinitely large value of + B . In practice the largest possible value for the barrier height would suffice. For

122


Vacuum Level

Semiconductor

Empty Donor Stales

EC EF

w Depletionwidth

Figure 3-35. Schematic energy diagram of a Schottky barrier. 4, is the metal work function, x, is the electron affinity, Vbi is the built-in potential, E , is the energy gap, and E , and Ev are the conduction and valence band edges, respectively.$B is the Schottky barrier height. After a metal is placed on the semiconductorsurface, charge is exchanged to equilibratethe Fermi energy (EF). Since the semiconductorcontains far less charge than the metal, the donor states (ED)empty producing a depleted region of width W

further development of the Schottky barrier theory see Simmons and Taylor (1 983). Typically, & is in the range of 0.5 V to 1.4 V for most important compound semiconductor as shown in Table 3-6, clustering around -0.8 V for most metals on GaAs. The observed barrier height is related to the magnitude of the semiconductor band-gap, being about 0.5-0.6 of E,, lower for materials with a small E , , and higher for wide gap materials such as Gap. For materials with small band gaps, such as InAs (0.42 eV), this factor places stringent requirements on device operation, necessitating cryogenic temperatures to operate effectively. The value of the Schottky barrier height does not appear to depend strongly on the metal work function, although from the physical description of the barrier formation [Eq. (3-9)] is should be directly tied to &,. The “pinning” of the Schottky barrier height noted above has been attributed to the existence of surface states at the level of

to cm2. These states can arise from carbon, oxygen, surface defects, or other contaminants chemisorbed or physisorbed on the surface. Numerous interpretations have been put forth to explain these effects. Brillson et al. (1983) have considered that a finite amount of intermixing occurs during the metal deposition process rather than an idealized, atomically abrupt interface. An effective metal work function is defined which integrates the effects of defects, clusters of metal, or semiconductor species, etc. This leads to a “pinned” value for the Schottky barrier height. Spicer has postulated a “unified defect model”, depending on surface states from defects (e.g., vacancies) which gives rise to the pinning states. This behavior is discussed further by Williams (1982) and numerous theories exist for these pinning phenomenon. Many investigations of the Schottky barrier phenomenon have been carried out in an attempt to understand and control


the interfacial charge states and the metallurgy of the metal-semiconductor junction so as to provide a stable and reproducible barrier height (Spicer et al., 1980; Pan et al., 1983; Brillson et al., 1983; Waldrop et al., 1982; Williams, 1982). While the barrier heights obtained under nearideal conditions (e.g., in-vacuo cleaved surfaces) are relatively well-characterized, in practice, the variation induced by the processing chemistry and the materials properties requires significant efforts to provide a “reproducible” Schottky barrier height. However, the precise physical relationship of the energy gap, work function, and & is not fully understood, as remarked by many investigators [see review by Schmid-Fetzer (1 98 8)]. To form the Schottky-barrier gate structure, a metal (e.g., gold or aluminum) or metalloid (e.g., WSi, WN, TiWN, etc.) is deposited onto the semiconductor surface and then patterned by standard photolithographic processes. A key issue in the use of Schottky-barrier gates is the demands of the fabrication process sequence: the required thermal and patterning processes determine the permissible gate metallurgy. It is necessary to contend also with adhesion between the gate material and the semiconductor and the impact of subsequent processing steps on the chemical reactivity and stability of the metalsemiconductor system. Therefore the selection of suitable metals and metal alloys becomes relatively limited (see Table 3-6). These materials may be used in combination to improve properties such as the electrical resistivity, but the barrier height is determined by the metal or metal alloy in contact with the semiconductor surface. The primary metal deposition methods are sputtering and evaporation. As in any deposition process, the surface and the material to be deposited must be extremely

123

clean to prevent uncontrolled interfacial reactions or the creation of metal-insulator-semiconductor (MIS) structures. For most of the refractory metals, their melting points are sufficiently high that sputtering is the only viable method; electron beam evaporation for these materials is either impractical or the deposition process will raise the temperature of semiconductor surface too high to prevent chemical interactions. On the other hand, sputtering readily creates surface damage and thus creates surface states (see Sec. 3.6). As previously noted, the formation of a Schottky barrier is extremely sensitive to the interfacial density-of-states. The corresponding variability in the barrier height, locally or globally, will affect the transistor threshold voltage, operating conditions, and reproducibilities. Many of the metallurgical systems presented in Table 3-6, particularly in the case of refractory metals, may create significant stresses during deposition and fabrication, and also during device operation due to a mismatch in the lattice parameters, atomic configurations, and the existence of thermal expansion coefficient mismatch. These phenomena give rise to piezoelectric-type effects, and consequently, the transistor threshold voltage may shift. For example, the grain structure of a Schottky-barrier metallization, as deposited by various methods, is strongly dependent on the deposition rate and the deposition conditions (e.g., vacuum, plasma composition, target materials, etc.). Thus variations in 4Bmay be anticipated. The microscopic details of the grain structure may also affect the gate metal resistivity and the susceptibility to electromigration at high current densities. These issues must be carefully addressed to achieve a stable Schottky barrier process. If the device fabrication process is carried out at relatively low temperatures,

124


gate materials such as Ti-Pt-Au may be utilized (Wada et al., 1989; Brown et al., 1989).Gold suffers from relatively poor adhesion to most compound semiconductors and also rapidly diffuses in most compound materials, even at low temperatures (ca. 250-400"C), as does platinum. Thus there is a need to capitalize on the conductivity of gold, while maintaining process integrity. The Ti-Pt-Au system is commonly used for gate metals on GaAs. In this case, the titanium is used as an "adhesion promoter". The platinum layer serves as a diffusion barrier to prevent the gold from reacting with the titanium [see Massalski (1986), pp. 298-2991 and subsequent gold-spiking into the GaAs (Goronkin et al., 1989). The gold provides a very low resistance path to support a high density current flow. As these metals are relatively compatible from a thermal expansion standpoint there is little interlayer stress and little driving force for intermixing at temperatures below ca. 500"C, thereby producing a thermodynamically stable contact structure. For fabrication processes that employ nonalloyed or nonannealed contacts, aluminum, titanium, and tantalum have been found to be stable at temperatures up to 300 "C.These materials can be used in the gate structure provided temperatures in subsequent process steps do not exceed roughly 200-250°C and operating temperatures are limited to less than 125-200°C.

-

For devices which utilize an ion implantation and anneal step subsequent to the gate metal deposition (see Secs. 3.3 and 3.11), the gate material must be stable at temperatures at-least as high as the annealing temperature, typically in the range of 800 "C to 1000 "C. Self-aligned processes, such as the generalized approach shown in Fig. 3-36, require the use of ion implantation and annealing for defining the gate and channel regions. Several approaches exist for creating the self-aligned gate, among them, the self-aligned implantation for n + layer technology (SAINT) (Yamasaki et al., 1982) and the self-aligned refractory gate integrated circuit process (SARGIC) (Dautremont-Smith et al., 1990; Dick et al., 1989). Any variation on this type of technology relies on the existence of a stable Schottkybarrier gate metallurgy. Typically, for selfaligned structures the gate material is a refractory or noble metal such as tungsten (Sze, 1981, p. 290), platinum (Fontaine et al., 1983; Sinha and Poate, 1974), titanium (Matino), or an alloy or bi-layer such as W-Si (Dautremont-Smith et al., 1990), W-N (Kikaura et al., 1988), Ti-W-N (Sadler et al., 1989), W-A1 (Inokuchi et al., 1987), or other similar combinations. These types of Schottky barrier materials are stable at high temperatures and exhibit only very limited reactivity with the compound semiconductor surface. However, it has been observed that metals such as

1) Dielectric deposition, Open gate windows

Figure 3-36. Schematic flow of a "self-aligned"process wherein the gate metal layer is used to protect the FET channel from ion implantation and processing damage. Steps 1 and 2 define the channel and gate, step 3 is the self-aligning step. Step 4 provides the device isolation. Steps 5 to 8 define the ohmic contacts, first and second level interconnections, and passivation protection.

3.7 Schottky Barriers and Gates 2) Gate metal deposition, Photolithography, Etching or liftoff to define gate


125

126


6) Dielectric deposition, Via etch, Interconnect metal deposition, Patterning



tungsten must be treated extremely carefully as layers tend to lift from the semiconductor surface at temperatures above 400500°Cdue to thermal expansion mismatch (the ratio of thermal expansion coefficients is greater than 10: 1). Multi-layer metal-metalloid structures may be deposited to significantly reduce the electrical resistivity of the gate structure. For example, gold over W-Si, gold over Ta-Si, or tungsten over W-Si. Use of these layered structures is particularly important for device performance as silicide or refractory materials have a much higher resistivity than gold or gold-based alloys. Thus the current carrying capabilities are significantly lower. Electromigration and thermally-induced grain modification may also occur if the current densities are driven above lo5A cmP2(Irvin and Loya, 1978; Irvin, 1982; Oates and Barr, 1994). Localized heating can occur in a resistive gate structure, thereby upsetting the device operating characteristics and accelerating the degradation processes [see Irvin and Loya (1978), Irvin (1 982), and references therein]. The use of such “bi-layer” or T-gate structures substantially enhances the current carrying capability (Maeda et al., 1988)and increases the operating speed of a transistor by lowering the gate RC time constant. A low-resistance gate is crucial to the performance of devices with sub-

127

micrometer gate lengths, as the advantages of the small transit time through the gate region can be completely mitigated by the performance losses incurred from the RC effects of a high resistivity gate stripe. A gate structure known as the “T-gate” or “mushroom-gate’’ (Yuen et al., 1988; Beaubien, 1992) can be utilized to further reduce the resistance of the refractory or high-resistivity gate structure while maintaining a very small effective gate length. The T-gate configuration is formed by deliberately undercutting the Schottky barrier material beneath the top metallization layer, or by providing a photoresist or other sacrificial layer to shape the top metallization during deposition following the definition of the fine gate feature on the surface. This undercut structure is also useful for self-aligned ion implanted processes to prevent the implanted ions from encroaching on the channel region. In cross section the gate has a T-shape with the current being carried predominantly in the low-resistivity top metal layer, as shown schematically in Fig. 3-37. Here the large, low-resistance top metal extends over the higher resistance Schottky barrier material in a T-configuration. Figure 3-38 shows an SEM cross section of a T-gate structure. The physical gate length in this figure is -100nm, while the metal width of the cross is -0.5 pm. Electron-beam or deepUV lithography is required to achieve the

Figure 3-37. Cross-section schematic diagram of a “T-gate” structure. Numerous combinations of compatible materials may be used for this gate configuration.

128

3 Compound Semiconductor Device PI,ocessing

-

Figure 3-38. SEM micrograph of a T-gate structure. The physical gate length at the semiconductor surface is 100 nm.The width of the body is 0.5 pm. [Micrograph courtesy of Beaubien (1YY2).]

-

-

sub-0.25 pm dimensions, whereas g-line or i-line photolithography is suitable for dimensions larger than -0.4 pm. Many “tricks” of interference or multiple pass exposures, intentional misalignment, multilayer resists, shadowing, etc. can be used in either process to achieve very fine gate geometries. Trade-offs regarding the selection of a fine-line process must be determined vis-a-vis device and process complexity, yield, process cost, and reliability. Devices fabricated with these fine features show superior high frequency performance due to the small RC time constant and a short gate length. The key to realizing successful device performance lies in the uniformity and reproducibility of the gate formation process, coupled intimately with the materials properties (thickness x doping product, charge profile, charge density, heterostructure, etc.). Step and repeat lithographic systems can create minimum dimensions typically in

-

the range of 0.25-0.5 pm in production environments. G-line (dimensions 0.5 pm), I-line (dimensions -0.25 pm), deep UV ( 0.15 pm), image reversal processes, or X-ray flood exposure can be used to photolithographically define the fine features. Five-X or ten-X projection systems permit the writing of finer features than one-toone projectors or contact aligners. Electron beam methods are capable of achieving 0.1 pm line widths and can perform near this level in a low-to-modest volume production environment, the trade-off being that the systems are relatively slow, expensive, and limited to gate level exposures at the present time. As designers continue to push for higher frequency performance and device dimensions shrink, it should be recognized that processes must evolve that can work macroscopically at the near-atomic level: consider that a 0.1 pm gate stripe is only about 350 atoms wide, while substrates are at 100 mm diameters with 150 mm under development, and typical print fields in a step-and-repeat camera are 15-20 mm by 15- 20 mm. This area will be investigated intensely in the coming decade.

3.8 Annealing Annealing processes are required for activating ion implanted species, passivating surfaces and electrically active defects, and relieving stresses between layers of dissimilar materials. The underlying principle is to induce controlled atomic exchange within the wafer by thermal excitation. There are two basic approaches to this process: furnace annealing (FA) and rapid thermal annealing (RTA). The two configurations are illustrated schematically in Figs. 3-39 and 3-40, respectively, Furnace annealing tends to be less stressful to the wafer as the

TMil

129

Typical Maximum Temperatures -650-900°C

~

Temperature

Tlme(min.)

Arsine, Phosphine

3.8 Annealing

Typical Duration 10-30 min

Heating and cooling rates in the range -1 to 1 0 s of degrees per minute

-

................ ................ Wafers

Safely Systems

Furnace

Figure3-39. A schematic diagram of a furnace annealing system. In the upper section of the figure, the time-temperature sequence is illustrated. The key issues are a relatively slow temperature rise and fall, and a lengthy time at the peak temperature. The lower half of the figure shows wafers heating parallel to the gas stream to minimize stresses due to heat retention and radiative/conductive thermal exchanges. Safety systems are mandatory for handling efluent gases when processing most III-V or 11-VI compound semiconductor materials.

rate of change of temperature is relatively slow, while the time at high temperature is relatively long. In RTA the object is to provide a rapidly changing, high peak temperature condition (typically hundreds of degrees higher than that in FA) to effect atomic level rearrangement in a very short time span. The drawback of RTA is the stress induced by rapid heating: the short time tends to preclude uniform heating and the exposure period is generally insufficient for thermal equilibration. The primary difference between these approaches is the nature of diffusion and redistribution of the

(fi

behavior) due impurities and defects to the different time- temperature cycles. Annealing may be used for repairing the minor atomic displacements associated with ion implantation without causing the recovery of the gross displacement damage, as required for isolation processes; or, with a larger thermal budget, cause the ion implanted species to site select (activate) and occupy a substitutional position in the lattice while simultaneously recovering nearly all of the atomic displacement damage; and also, for strain-relieving multilayer materials structures with dissimilar

130


Typical Maximum Temperatures -700-1 OOO°C 5-60 sec typical

it H

E

f

Heating and cooling rates in the range -10 to loo’s of degrees per minute

RCKXll

Temp Tlme (aec)

I

Inlet Gas (Ar, H,

-

& , ASH,

etc.)

I

L--lormi&

I

Sukeptor

........ Heat lamps, DC or RF heating

‘

Wafer

I

Exhaust to Safety Systems

I--,

00 0000 00 Heat lamps, DC or RF heating

Figure 3-40. A schematic diagram of a rapid thermal annealing (RTA) system. In the upper section of the figure, the time-temperature sequence is illustrated. The key issues are a relatively rapid temperature rise and fall, and a relatively short time at the peak temperature. The lower half of the figure shows a wafer constrained between a graphite (or other material) susceptor. This configuration, typical of present commercial systems, can process one wafer at a time. The susceptor acts to supply heat uniformly to the wafer to prevent slip and stress, and to slow the actual rates of heating and cooling. Exhaust gases must be treated by combustion or scrubbing for safety.

physical properties, as are found in all integrated circuit fabrication sequences. Passivation may be realized through the “healing” of surface defects, the consolidation of deposited films, and the in-/out-diffusion of mobile species such as hydrogen (Pearton and Caruso, 1989). Annealing may be carried out using a variety of heat sources such as strip-heaters (Banerjee and Bakar, 1989, furnace-based processes (Woodall et al., 1981; Shigetomi and Matsumaro,

1983; Hiramoto et al., 1985), and RTA methods using lasers (Tsukada et al., 1983), rapid-cycling high intensity heat lamps (various types of IR generators) (Chan and Lin, 1986; Crist and Look, 1990), or arc sources (Tabatabaie-Alavi et al., 1983).The processes discussed here involve relatively high temperatures; low-temperature alloying and annealing processes are discussed relative to the formation of ohmic contacts in Sec. 3.6.

3.8 Annealing

On comparing FA and RTA methods, one finds the net thermal budget to be significantly different. For example, a furnace anneal cycle at 850 “C for 20 min is equivalent to a few seconds at 1000°Cin terms of atomic diffusivities. A typical RTA cycle may last only 5 or 10 s at 1000°C. It should be noted that the surface temperature achieved during RTA processes is not wellcharacterized as the heat sources (e.g., heat lamps) are operating many hundreds of degrees higher than the actual wafer temperature. It is the increased kinetic energy at the higher temperature that allows for more rapid atomic exchange and thus for very rapid recovery of lattice damage and impurity site selection. Since the time at elevated temperature is so short in the RTA process, typical dopant species diffuse distances of the order of a few nanometers rather than tens or hundreds nanometers in the case of FA. When a substrate is annealed after ion implantation, the donor and acceptor impurities generally become substitutional in the lattice and charge is provided to the semiconductor. The amount of charge depends on 1) the number of donor or acceptor species present; 2) site selection probabilities (interstitialcy, autocompensation effects, the ionization state in the lattice), and 3) the degree of lattice recovery (point defect concentrations). For example, n-type regions with electron densities as high as 5 x 1019cm-3 have been created using very high dose implants ( - 1015cm-’) and laser RTA techniques (Liu et al., 1980); p-type materials with hole densities up to 7 x 1019cm-3 have been formed using pulsed laser annealing (Kular et al., 1978). With furnace annealing processes, the peak charge densities achieved are somewhat lower than those obtained in RTA due to the quasi-equilibrium nature of the furnace anneal process. Typically, maximum

131

n-type and p-type carrier concentrations of 3-5 x 10” ~ m - ~and , 1-2 x 10’’ ~ m - ~ , respectively, are realized with furnace annealing processes. Much effort has been expended in understanding and controlling the annealing process in compound semiconductors, building on the experience developed in silicon wafer fabrication. Owing to the volatility of the group 11, V, and VI species, thermal annealing of the compound semiconductors poses significant challenges. The behavior of GaAs materials under various conditions of capping and/or arsenic overpressure have been studied at great length with widely varying results [see, for examples, Woodall et al. (1981), Banerjee and Bakar (1985), Tsukada etal. (1983), Crist and Look (1990), Asom et al. (1988), Look et al. (1986), Parsey et al. (1987)l. Site selection of impurities is affected by 1) the statistical nature of the atomic displacements, 2) the exchange processes that must take place to create a substitutional impurity, 3) the competing formation of point defects and defect complexes, etc. Since, in the compound semiconductors, there are two chemically and electrically distinct lattice sites, the charge state of an impurity can be either donor-like or acceptor-like, and in the case of interstitialcy the charge state may not be well-defined. Variations in activation have been attributed to inconsistencies in substrate properties (e.g., bulk and surface layer stoichiometry, impurities, out- and in-diffusion of both defects and impurities), the efficacy of “face-toface” vapor exchange processes, and the interaction of the capping layers with the semiconductor surface layers (e.g., stresses, interdiffusion, contamination, etc.). The annealing of compound semiconductor materials may be carried out with or without a protective cap, or a group 11, V, or VI “quasi-equilibrium’’ overpressure

132


atmosphere. In general, some method for maintaining the surface integrity is required to prevent decomposition of the surface regions due to the high vapor pressures of the group 11, V, and VI species, particularly with the phosphide-containing materials. The surface layers of compound semiconductors are subject to incongruent decomposition during heating due to the strongly mismatched vapor pressures of the respective components, as illustrated in Fig. 3-41 for GaAs, Gap, and InP (Panish, 1974). The vapor pressures of the group V species may be in the range of a few Pascal to many kilopascal at useable annealing temperatures. Surface losses must be minimized lest the surface become conducting (more metallic) in nature as the surface becomes rich in the less volatile species. This latter effect will occur in the temperature regime about and above the congruent evaporation point. For GaAs-based materials, this is in the range of 580-620°C (Panish, 1974).The group VI species tend to have lower vapor pressures than the group V elements, and thus somewhat more relaxed annealing conditions prevail for most I1- VI materials, although the same phenomena must be considered. However, in materials such as HgCdTe, the vapor pressure of mercury is extremely high (and toxic), and great care must be taken to prevent decomposition of the surface. In furnace annealing of GaAs, the rate of free-surface decomposition is of the order of 3 monolayers per second, depending on the heating rate, temperature, and presence of an atmosphere. In an equivalent RTA process, an uncapped surface decomposes at initial rates of tens of nanometers per second in GaAs; these rates are higher for phosphorus-containing compounds. The use of an overpressure of As, or P, vapor can reduce or prevent the decompo-

-

-

sition by balancing the surface dissociation rate, while a cap layer will completely suppress loss of the volatiles, although diffusion into the cap or wafer surface may become an issue. “Overpressures” may be generated by heating solid sources of the host material, from elemental or compound vapor species. Open tube or closed ampul methods have been used: practical considerations in the processing of large diameter wafers dictate the use of “open tube” methods, although significant safety measures must be in place for most compound semiconductors (Zuleeg et al., 1990). Furnace annealing of ion implanted GaAs is carried out typically for 20-30 min or more in the range of 700-900°C. Annealing processes carried out below about 700°C tend to be very protracted and are subject to large variation and irreproducibility (Henry, 1989- 1991). Lower temperatures in the range of 500-700°C are used for materials containing phosphorus, and yet lower temperatures for materials in the 11-VI family (ca. 200-350°C). To prevent or minimize decomposition of the surfaces, the wafers are typically capped with a nitride or oxide film (Nishi et al., 1982; Campbell et al., 1986; Mathur et al., 1985). In some processes, “face-to-face” configurations have been implemented (Woodall et al., 1981), and in others the overpressure methods are employed without capping (Henry, 1989- 1991). Complications arise in each approach: removal of the capping material is a moderately dificult process and may damage the surface layer@);the face-to-face approach subjects the wafer to yield-reducing damage from scratching and potential cross-contamination, and the overpressure method may have system and safety constraints due to the toxicity of the materials required in compound semiconductor processing.

3.8 Annealing 1O4K/T,(Ga-As,

‘ t

133

In-P)

6

7

8

9

10

11

12

13

I

I

I

1

1

I

I

I

Figure 3-41. A plot of the vapor pressures of arsenic and phosphorous over GaAs, Gap, and InP (solid). The pressure scale is in log(atmospheres), and the temperature scales are in lo4 T- (in Kelvin). The vapor pressures are represented as the dimeric form of arsenic and phosphorus. Reprinted from J. Crystal Growth, 27, Panish, M. B., “A Thermodynamic Evaluation of the Simple Solution Treatment of the Ga-P, In-P and Ga-As Systems”, 6 - 20 (1974) with kind permission of Elsevier Science - NL Sara Burgerhartstraat 25,1055 KV Amsterdam, The Netherlands.

134


Owing to the relative “softness” of the compound semiconductor materials (with respect to silicon), the maximum annealing temperatures and the heating and cooling rates are much more critical. For example, GaAs wafers may readily warp when furnace annealed in a vertical configuration at 850°C and withdrawn from the furnace at a rapid rate (effective dT/dt of -1001000 “C per minute). Such warpage renders the wafer unsuitable for any further processing, as modern step-and-repeat or contact photolithography systems cannot focus on a surface with more than a few micrometers of local focal plane variation, or the wafer may fracture when brought into clamp contact with the photomask. Annealing in a horizontal configuration has been accomplished, but consumes large areas in the furnaces, and is subject to the difficulties of maintaining a uniform and reproducible environment in a large volume. In addition, stresses generated by rapid heating or cooling may create slip in the substrate, which can lead to short or open circuits after processing and facile cleavage of the wafer in post-process steps such as wafer thinning, back-surface metallizing, or dicing operations. The very rapid thermal cycling impressed in an RTA process makes the understanding and control of these stress-induced phenomena particularly important for maintaining wafer integrity. RTA processes, although inducing higher peak temperatures in the host wafer than furnace annealing cycles, essentially affect the same atomic-level reconstructions. RTA process conditions are typically in the range of 850-1050°C for -10-60s (Banerjee and Baker, 1985; TabatabaieAlavi et al., 1983). They key issue in the RTA cycle is that the net thermal budget for the process is smaller than of the furnace-based processes. Thus, although the atomic-level excitation is greater due to the

high temperatures, the short time prevents a significant redistribution for most impurities, defects, and the host lattice atoms, and yet allows the damage and atomic displacements to recover. This latter point is the principal advantage of the RTA annealing procedure relative to the furnace-based processes. As previously noted, greater carrier concentrations can be obtained with RTA processes versus furnace annealing, an effect attributed to the nonequilibrium conditions created in RTA processes (Tiku and Duncan, 1985). Rapid thermal annealing has been investigated for several years with mixed results (Kular et al., 1978; Kasahara et al., 1979; Immorlica and Eisen, 1976; Fan et al., 1982; Arai et al., 1981; Ito et al., 1983). The successful implementation of RTA has been strongly dependent on the configuration of the annealing apparatus and the environment within the process chamber, as well as the details of the time-temperature cycle. RTA processes have been developed to anneal the wafers under atmospheres of As, ASH,, H,, N,, or Ar to mitigate surface decomposition effects. The difficulties in this approach lie in developing a uniform and reproducible thermal environment in a wafer with a patterned, and possibly metallized, surface in conjunction with the necessity of maintaining the surface integrity. The low thermal diffusivity of the compound semiconductor materials contributes significantly to the creation of localized temperature gradients in the wafer, which may be undesirable in terms of stress and electrical property uniformity. The thermal shock induced in the wafer from the extremely rapid rise of the wafer temperature and stresses generated from nonuniform heating due to the varied reflective and absorptive properties of the fabricated wafer, must be carefully considered and understood for RTA processes.

135

3.8 Annealing

Crystal slip may occur more readily with RTA processes than furnace annealing, due to the large thermal stresses (i.e., the thermal gradients between the front and rear surfaces, the finite thermal diffusivity of the semiconductor materials, and the metal thermal conductivity, etc. (Pearton and Caruso, 1989). Slip in the (110) crystal directions and dislocations can be generated in the peripheral region of the wafer, due to the large radial and axial thermal gradients enhanced by the radiative characteristics of the wafer edges. The mechanical failure and disruption of the crystal lattice leads to poor performance or failure of devices fabricated in these regions (Miyazawa et al., 1983; Ishii et al., 1984; Suchet et al., 1987).Stresses induced in the RTA process can lead to warping, delamination of dielectric layers, and damage to fine-featured components (e.g., separation of resistor films, cracking of metal traces, etc.), particularly at step edges. By careful design of the heating systems, the use of heat shields, susceptors, cover wafers, or heat spreaders, the RTA approach can be made to produce a viable wafer with minimal deleterious effects. Stresses generated in annealing arise from basically two phenomena: differential thermal expansion and physico-chemical interactions. The process of depositing a metal layer may expose the wafer surface to temperatures in excess of 1000°C in a metal evaporation system, or varying in the hundreds of degrees for sputteringbased depositions. While the bulk of the material may not achieve this high temperature during the process, the surface layers do realize this thermal insult. Upon cooling, stresses will build up from the large differences in the thermal expansion coefficients between the metal, the semiconductor, and the other layers, such as dielectric films. Typically, this difference in expan-

sion coefficients is of the order of 5 : 1 to 10 : 1 between the different materials. If care is not taken in the annealing cycle, this differential contraction/expansion can create sufficient stress to delaminate the structure, fracture fine features, or induce piezoelectric effects. An annealing process can also be used to relax stresses that arise from the process sequences and the incompatibilities of the multiple layers of dissimilar materials which comprise the fabrication of the device. Typically, a furnace anneal is utilized at relatively low temperatures (below -450-50OoC), with an appropriate neutral or protective atmosphere for times ranging from a few minutes to several hours. The object of this cycle is to permit some interatomic exchange and relaxation to create a transition region between the dissimilar materials. In the deposition of dielectric materials, the chemical compositions may be adjusted to reduce the stress generated in the anneal and thus lead to greater resistance to the effects of thermal cycling. However, even a low-stress film may create tension or compression in the range of lo9 to > 10" dyn cm-' (lo4 to > lo5 N), which is sufficient to alter the device electrical characteristics. This latter point is the result of the polar nature of compound semiconductor crystal lattices and resulting piezoelectric effects. The problem associated with such compositional variation is that the film properties are determined by the chemical make-up and may therefore be in conflict with the design requirements (e.g., the capacitance dielectric value or the isolation and standoff voltage capabilities). In the case of a dielectric-over-gate stripe, stresses in this critical area may shift the threshold voltage, which can lead to erratic circuit performance due to thermal cycling effects. The metallization/dielectric 'sandwich' structures, e.g., capacitors or induc-

-

136


tors, and multi-level metals, formed when passive components and interconnections are fabricated must also be stable to the thermal cycle. The respective materials properties and compatibility are very important if delamination or blistering resulting from excess stresses at the respective interface is to be avoided. Interface and deep-level states may be passivated in compound semiconductors by appropriate implantation processes (e.g., low energy protons), followed by a gentle, low-temperature annealing cycle (Pearton and Caruso, 1989). As hydrogen rapidly out-diffuses from compound semiconductors (Pearton et al., 1987), temperatures in the range of 300-400°C must be used for the annealing process. Also, with this high diffusivity the thermal excursion and thermal budget of any subsequent process steps are drastically limited if the effect of the hydrogen is to be maintained (see Sec. 3.3). Reproducibility‘is crucial to the performance of circuits that utilize an annealing cycle in the process sequence. The statistical nature of impurity site selection, and related compensation and defect formation processes, necessitates tight control of the annealing environment. If high temperature anneals are used, such as are necessary for ion implantation annealing, then considerations must be taken of the thermal history of the wafer from previous process steps, the impact on impurity and defect redistribution in subsequent processing, and the ability of the materials to withstand the additional thermal cycling. One of the conditions impressed on the fabrication sequence is that sequential steps must be carried out with continually lower thermal budgets to prevent uncontrolled reactions, undesirable phase formation, and additional in-diffusion and punch through of the junction and contact regions. There-

-

fore, careful planning and a detailed understanding of the material’s properties and the thermodynamics and kinetics of the processes are required.

3.9 Dielectrics and Interlayer Isolation It is necessary to provide electrical and mechanical isolation between the various layers of semiconductor and metals in a device. For example, the formation of capacitors requires a dielectric material to isolate the electrode plates. In the case of an inductor, the coil runners must be isolated from the substrate or any other metallizations. Schematic cross-sections of capacitors are illustrated in Fig. 3-42. Typically, the structure is formed as either an n + layer covered by a dielectric (Fig. 3-42a), or as one of the first level metals covered by a dielectric, followed by an upper level metal which defines the capacitor area (Fig. 3-42 b). In this application, the properties and perfection of the dielectric layer are critical to the reproducibility and yield of the capacitors. The complexity of modern circuit designs demands multiple metallization layers to interconnect the devices and the signal transmission lines, provide for power bus routing, and to permit adequate circuit compaction. Each of these metal layers must be isolated with a dielectric layer. The dielectric material must possess a suitable dielectric strength and dielectric constant, uniformity of thickness and physical properties, and be deposited with a high degree of layer integrity to minimize short circuits. The dielectric layers also play a critical role in controlling the density of surface states and pinning of the Fermi level at the semiconductor surface. These properties may

3.9 Dielectrics and lnterlayer Isolation

137

Figure 3-42. Schematic cross sections of capacitor structures. In a) a channel-based capacitor is illustrated. In b) the capacitor is formed from the first and second level metals, with the dielectric between them. The thickness and perfection of the dielectric layer is critical to the leakage and breakdown properties of the structure in both cases. The effective areal dimensions of the capacitor are determined by the lengths of the upper level metal pad.

affect the value and control of the device thresholds in MESFET, HFET (MODFET), and MISFET-type devices fabricated on GaAs, InP, and other compound semiconductor materials [see Daembkes (1991), and articles and references therein]. The dielectric material serves to reduce surface leakage by “tying up” dangling bonds and passivating the surfaces. A dielectric layer may also be used to protect the compound semiconductor from chemical attack and contamination during processing, and to provide mechanical protection of the surfaces. An encapsulating dielectric film may be used to prevent surface decomposition during annealing pro-

cedures. This is a crucial application in most IIILV and 11-VI compounds due to the volatility of the component species. To assist in the formation of air bridge metallizations, dielectric layers may be used to assist in the definition of the post-andbridge structures. Thus understanding of the dielectric material, the deposition process, and potential interactions at the interfaces are critical for achieving reproducible device characteristics. It is an unfortunate fact that the compound semiconductor materials do not have the strong native oxide available in silicon technology. For example, in GaAs the native oxides Ga,O, and As,O,

138


(y = 3 3 are very weak, being readily soluble in a variety of liquids. The suboxides (Ga,O and As,O) are quite volatile at common processing temperatures. These oxides, which form rapidly in air, are one source of interfacial states as the surface bond configuration and chemistry are strongly modified by the oxidation process. The native oxides also tend to be inhomogeneous in their properties due to strong local variation in the chemical composition and bonding (Watanabe et al., 1979).In part, this is due to the large difference in vapor pressure and reactivity of the constituent elements. Other oxide layers, for example those formed with glycolbased solutions, have been found to be electrically inferior to most deposited dielectric materials and have therefore received little attention (Hasegawa and Hartnagel, 1976). Dissolution of the group I11 and group V oxides may readily be carried out with HCl- or NH,OHbased chemistries. This is convenient for surface preparation, but emphasizes the limited utility of the native species for integrated circuit applications. Thus alternative deposited dielectric materials must be used. For most applications, the dielectrics SiO,N,, Si,N,, and SiO, are used. The dielectric constant of a dielectric material depends strongly on the chemical composition. The composition of these compounds is determined by the deposition chemistry and the apparatus configuration. Device performance criteria determine the optimum value of the dielectric constant. It should be emphasized that these materials are rarely, if ever, stoichiometric. Therefore care must be exercised in deposition to achieve a homogeneous, uniform, and lowstress film. The application of a dielectric layer embodies many compromises. Optimally, it is

desirable to have a low dielectric constant for high-speed operation. The tradeoff in the use of S O , , Si3N4,and SiO,N, is the value of the dielectric constant: nitride films are best for capacitors, but the oxide is optimum for runners due to the lower dielectric constant and a resulting lower capacitance. Mixed oxy-nitride materials have dielectric constants intermediate between SiO, and Si3N4, which permits a compromise in the circuit fabrication-performance relationship. For example, the dielectric constant for SiO, (x 2) is significantly less than that of Si,N, (x 3, y = 4), as shown in Table 10-7, along with other interesting dielectric materials. Therefore, when used for interconnect isolation, a lower capacitance may be realized with SiO,, a highly desirable feature for high-speed circuits. However, much thinner SiO, dielectric layers must be deposited to achieve a given capacitance value (relative to materials with larger dielectric constants) or, alternatively, large areas of the circuit must be committed to these devices with the resulting cost increase and yield reduction. In the case of very thin layers, the integrity of the film becomes a yield-limiting factor.

- -

Table 3-7. Values of dielectric constants for selected dielectrics. Material

Dielectric constant (relative)

GaAs SiO, Si,N, Polyimide Ta205 TiO, SrTiO

13.1 4-5 7.5 3.5 20-25 14-110 50- loo 9.5

A1203

-

Reference

Sze (1 98 1 , App. H) Williams (1990, p. 295) Sze (1981, App. I) CRC (1978) Williams (1990, p. 295) CRC (1978) Nishitsuji et al. (1993) CRC (1986)

3.9 Dielectrics and Interlayer Isolation

Most of these dielectric layers can be deposited with relatively low stresses, if the process is carried out under optimized conditions. Typical stress levels are in the range of 109-1011dyn cm (104-106 N). Values of lo9 dyn cm (lo4 N) are considered strain-free, while those above 10” dyn cm (lo5N) can create problems with yield and reliability (layer adhesion, thermal cycling effects). Another issue with stress is the piezo-electric (PE) effects arising from the polar nature of the compound semiconductor lattice. Interlayer stresses may generate significant anisotropic threshold shifts due to the PE effects; thus the gate orientation with respect to the substrate crystallographic orientation becomes important. In Si,N, films on GaAs, stress typically increases with increasing Si fraction. At the same time, the dielectric film resistivity varies with the silane concentration in the atmosphere, making the electrical isolation less effective, i.e., higher leakage currents may be observed. Hydro-

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139

gen incorporation also increases with lower deposition temperatures. An optimum balance of the properties in silicon nitride materials has been obtained with “near-stoichiometric” film compositions [see Williams (1990), Secs. 8.3.1, 13.3, and references therein]. A caveat to the use of dielectric materials is the mechanical incompatibility between most such materials and the compound semiconductors. The thermal expansion coefficients of dielectric materials are typically quite different from metals or the host semiconductor. Thus deposition of the dielectric layer can give rise to significant levels of stress. Thermal cycling caused by device operation can produce failures in metallization lines and contacts from cyclic fatigue, particularly at steps and edges. This effect is illustrated schematically in Fig. 3-43. Cyclical stresses can also give rise to shifts in device characteristics arising from the PE effects in the compound semiconductor. The PE effects and the fab-

Cracksand microfractures in metal lines

Figure 3-43. Detail of a metal line over a dielectric step. With continued thermal cycling, the differential expansion may induce fractures and microcracking in the metal lines. Similarly, dielectric over-layers may crack due to expansion of the metals beneath. Steps and edges are most susceptible owing to the concentration of stresses.

140


rication process-related phenomena, as they affect the device threshold and operation, must therefore be clearly understood to achieve proper and reliable circuit operation. The deposition of dielectric films may be carried out by a variety of techniques. Evaporation methods for dielectric material deposition are well understood but have limited applicability for compound semiconductor processing. This method suffers from exposure of the substrate to very high temperatures, dielectric composition control is very difficult, and variation in the composition occurs with time due to depletion of the various components from the source charge at varying rates. The control of stoichiometry and the materials properties are also complicated by the fact that elemental and molecular evaporation rates are very difficult to balance in a high vacuum (HV or UHV) deposition environment. Sputtering methods may be used for deposition but surface damage can be significant. Stoichiometry is generally variable throughout the film on the microscale, which may affect the physical properties as well as the etching characteristics. Aging of the sputtering target(s) may also cause a gradual shift in the dielectric properties. Lattice damage can occur from ions and surface atoms being driven into the surface region: resputtering of surface atoms also occurs during deposition. Hydrogenation of the surface region is also a problem, especially with the use of silane, hydrogen, and/or ammonia feed gases. The incorporation of hydrogen in various forms alters the dielectric properties in an uncontrolled manner and produces a time-varying effect in the film, due to out-diffusion of the hydrogen species during subsequent processing, or even during device operation (Pearton et al., 1987).

Standard CVD processes require relatively high deposition temperatures to drive the gas phase reactions. Typically, deposition takes place at temperatures greater than 500- 1000°C, which is incompatible with most metallizations used for ohmic contacts and interconnects. Temperatures in this range are also too high for most compound semiconductor materials: surface decomposition may occur during the deposition cycle, as the vapor pressures of the group V species, e.g., PASand Pp, for example, are significant at these processing temperatures [see Fig. 3-41, and Panish (1984), for example]. The deposition method of choice appears to be plasma-enhanced chemical vapor deposition (PECVD). This is due to the relatively low temperatures ( 175400°C) developed in these processes, and the enhanced controllability of the reactor systems. The plasma serves to create energetic reactive species, with the energy imparted by electrical excitation rather than direct thermalization. The plasma may be generated with DC or AC fields, in a variety of system configurations: each approach has its proponents (Gupta et al., 1983; Tsubaki et al., 1979). In PECVD processes the pressures are typically of the order of Torr (0.13 N m-2). The excitation in the plasma imparts energies in the range of a few hundred electronvolts or less. Thus there is only minimal surface damage due to electron or ion bombardment (Meiners, 1982). The chemically reactive species are generated at low temperatures by excitation in the plasma. Only a very small fraction of the available molecules are ionized by these interactions: most of the plasma is neutral and therefore relatively 'cool' and unreactive. The substrate may be heated, but it is necessary to raise the temperature to only 200- 300 "C for high quality depo-

-

-


sition. The self-heatingeffects during deposition can raise the substrates into this temperature range. The low temperature of this process allows direct monitoring of the gas-phase reactions, reaction species, and by-products by the characteristic emission or absorption energies (Havrilla et al., 1990). These type of measurements can be readily adapted to process control or endpoint detection. The PECVD method offers great flexibility: the dielectric density, composition, refractive index, and dielectric constant can be varied by controlling the deposition conditions. The PECVD processes can be used to create layers of AlN, Si,N,, SO,, Ta,O, , TiO,, and other materials, readily. AlN appears to be a promising new material for use in GaAs and related materials. It possesses a thermal expansion coefficient well matched to GaAs, but the depositionrelated damage is presently significant and the material is rather hard to remove without creating additional damage to the surface (Gamo et al., 1977). Growth rates in PECVD tend to decrease with increasing operating pressure or higher deposition temperatures, while the refractive index generally increases with a higher deposition temperature. Suitable gases for deposition and etching are reactive species: chlorines, fluorines, ammonia, silane, hydrogen, oxygen, and nitrogen-containing compounds. Noble gases such as argon may be used a diluents to moderate the deposition process. The major drawback to utilizing PECVD processing is that the process has many variables: gas pressure, chamber and substrate temperatures, flow rates, gas compositions, etching rates, the evolution of by-product materials, the electrode geometry, the excitation method (DC or R F and excitation frequency), the input power, the plasma energy density, the system configuration,

141

substrate rotation, etc. (Gupta et al., 1983). These variables present a formidable obstacle to process development, and complicate process control. For process consistency, contamination from pumps, leakage at vacuum seals (processes are not operated in UHV conditions), chamber materials, and residual species such as Si, 0,H, C, N, etc. must be considered. As a result, a stable, robust operating condition can be difficult to achieve and sustain. Another concern in the PECVD method is that deposition occurs over the entire chamber, complicating the control and stability of the process. Careful maintenance and consistent cleaning are required to maintain process integrity and consistency. By carefully designed experimental methods and the application of statistical process control monitoring, a robust and reproducible process may be obtained (Havrilla et al., 3 990). Barrel (or plate-type) PECVD reactor designs can be used for the deposition process (Fig. 3-44). In a barrel reactor the electrode plates in the chamber may be neutral or floating relative to the ground potential. Various susceptor and chamber configurations are possible. A low-energy ion flux is created between the plates above the wafers. Biasing the wafer plate can enhance or retard the deposition process, or alter the selectivity of the deposition. It is generally more difficult to control an etching process on a fine scale in this type of system, due to the low ion energy and small accelerating field strength. Local perturbations in the electric field on the wafer surface can readily deflect the incoming ions. This makes a barrel-type reactor best suited for relatively coarse processes, e.g., the ashing of photoresist, etching of large features, or deposition of thick, noncritical layers, due to problems associated with localized and nonuniform electric

142


n RF Coil

Reactive Gas Injection

-r

Exhaust

Figure 3-44. A schematic illustration of a RF-excited, barrel-type configuration for PECVD of dielectric films. The plasma above the wafer creates the active species for deposition. The energy of the excited species may be quite high and cause damage to the semiconductor surface. Susceptor rotation may be incorporated to improve uniformity. Heating and bias may be supplied to the wafers to assist deposition.

mJ RF Excitation

fields on the metallized and/or patterned wafers. Controlled gas flows, critical to achieving a uniform etching process, are also difficult to keep uniform in a barrel design due to nonuniform and nonsymmetric heating effects, convection, and generally asymmetric injection and pumping of the emuent species. Radial flow, rotating susceptor reactor designs have proven quite good for achieving uniform film deposition. A generalized configuration is shown in Fig. 3-45. New commercial systems, such as those developed by ElectroTech, or PlasmaTherm, are capable of 1YOcontrol of the thickness over a 3“ (76 mm) diameter GaAs wafer (ONeill, 1991). In this configuration the electrodes can be heated slightly, if desired, to raise the temperature of the wafers and enhance the surface reaction rate. Reactant gases and ion species are much better distributed in the radial reactors relative to the barreltype designs which leads to improved film characteristics and thickness uniformity. In a radial reactor the plasma is confined between the excitation plates, with a quenched region adjacent to the plate surfaces (space charge region). Ions are accel-

erated through the space charge region by the electric field and impinge on the wafer surface. Several investigators have introduced “downstream” (indirect) systems, wherein the plasma excitation and active species are generated “upstreamy’(with respect to the location of the substrates and the gas flow), well removed from the deposition region. The reactive materials are extracted from the source cell with the gas stream, and flow across the wafers. Deposition occurs on the wafer surface if the thermal conditions are appropriate. This configuration is shown in Fig. 3-46. It has been found that the use of such a downstream deposition process greatly reduces the plasma-induced ion damage in the surface regions (Meiners, 1982). Another approach to CVD deposition is photo-stimulated CVD. In this embodiment, a CVD chamber is fitted with windows to permit selected-wavelength light to impinge on the gases and/or the substrate. The added stimulation generates the desired species with reduced electrical energy input. The technique has advantages similar to PECVD: low deposition temper-


143

Figure 3-45. A schematic illustration of a high-performance, radial flow configuration for PECVD of dielectric films. The plasma is generated above the wafers, creating the active species for deposition. A radial flow is set up by the injection and exhaust configuration, improving the uniformity of the deposition. As in most plasmatype systems, the energy of the excited species may be quite high and cause damage to the semiconductor surface. Susceptor rotation may be incorporated to improve uniformity. Heating and bias may be supplied to the wafers to assist deposition.

Figure 3-46. A schematic illustration of an ECR-plasma CVD system. The plasma is generated by tuned electron-cyclotron resonance of the desired species in a cell well removed from the deposition region. A carrier gas flow or extraction potential transports the active species to the wafers. Minimal damage is imparted in the wafer in this configuration. Rotation of the wafers may be provided to improve the uniformity of the deposition. Heating or bias may be supplied to the wafers to assist deposition.

144


atures as well as a great selectivity for the excitation of specific molecular species by choice of the optical excitation energy (Peters, 1981). Photo-enhanced CVD induces less surface damage than the standard PECVD techniques, and by utilizing a downstream type configuration direct ion bombardment damage of the surface can be avoided. Electron-cyclotron resonance (ECR) is a relatively new method for creating a plasma while mitigating the damage induced by the ion and electron bombardment (Kondo and Nanishi, 1989;Takamori et al., 1987; Sugata et al., 1988). Here the plasma excitation is provided in the usual manner with the addition of a very high frequency R F excitation signal. Selective excitation is achieved by choosing the excitation frequency to resonate with the desired ion species cyclotron frequency. These selected ions absorb the energy and create the plasma for deposition. A relatively high excitation power is required in this approach, and therefore the downstream configuration is used for obvious reasons. Another class of dielectric materials are polyimides. These materials are polymeric organic films with relatively low dielectric constants: typical values are 3.5. Polyimides are very stable dielectrics: some compositions are capable of tolerating exposure to temperatures greater than 500 "C (Dupont, 1976). These materials are best suited as an encapsulant or capacitor dielectric, for inductor isolation, or for isolation of second (and higher) metal levels. These materials are also useable for the standoff of metal runners in air bridge configurations, although the large capacitances may present a problem at very high frequencies. Polyimides may be deposited with dispense/spin systems, as are used for pho-

-

toresist coating. The major drawbacks to the application of polyimides are: 1) the extended curing time required to drive off the solvents and crosslink the polymer chains (ca. 1 h or more at elevated temperatures), and 2) control of the thickness owing to the high viscosity of the liquid phase. Following the curing, the polyimide film can be patterned with standard photolithographic methods. However, only specific etchants and some plasmas will attack polyimide materials. They can be etched with oxygen plasmas (asher), or with strongly basic solutions. Appropriate solvents or alcohols may also be used for pattern development, but .care must be taken to minimize softening or other damage to the film. One great advantage of the polyimides is their dielectric strength typical values are lo6Vcm- I . This property, coupled with the high dielectric constant, makes these materials very attractive for use in high voltage circuits or for achieving very fine feature sizes. In PECVD and related deposition methods, film growth rates are in the range of 10-50 nm min-', and useful films are typically 50-1000 nm thick. The polyimide film thickness is controlled through the fluid viscosity and the spin speed and acceleration program in the deposition system. Thinner films can be deposited, but integrity generally suffers. All types of dielectric films can be evaluated with standard ellipsometric instruments to determined thickness and the dielectric constants. Other instruments, such as interferometers, are used to determine the compressive or tensile stress conditions in the deposited films. Pinholes or failures in the film integrity are a continual problem resulting from wafer surface contamination, the formation of large clusters or particulates in the plasma and on the chamber surfaces, or difficult surface topology. Mul-

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3.10 Resistors

tiple process cycles can be used to alleviate or minimize this problem. The impact of dielectric films and surface states on the channel saturation currents (Jsat),the device threshold voltage (I&), and reverse breakdown voltage ( Vbr) effects are poorly understood. Sputtering or PECVD typically produce ion damage depths less than 50- 100 nm, but can have a damage depth in GaAs up to twice the expected ion range under improper deposition conditions (Williams, 1990, Chap. 9). Significant surface depletion effects occur from this damage, and can result in erratic device behavior. The surface state effects are especially important for enhancement mode or low-current devices, where the charge is very close to the gate or present in a very low density, and thus the conducting channel is more sensitive to local perturbations in the surface electric field strength. Post-growth annealing may help stabilize the dielectric film properties by equilibrating the interface charge balance and the interfacial chemistry, and also relaxing built-in stresses (Weiss et al., 1977). All of these issues are crucial to the fabrication of high-performance, high-reliability integrated circuits in compound semiconductors, and are the subject of continuous investigation and development.

3.10 Resistors Biasing networks, feedback control, voltage and current dividers, load terminators, and balancing applications all require the use of resistors. During IC fabrication processes, resistors may be formed utilizing the conducting channels (active regions) in the surface of the wafer, or constructed as separate thin film layer structures. The channel-based resistor structures may be formed using the n-layer or the n/n+ layers

145

(ion implanted or epitaxially grown layers), as illustrated in Fig. 3-47a. This approach demands tight control of the sheet resistances in the layer(s) for a controlled resistance value. A thin film resistor is typically deposited above the first dielectric layer, as shown in Fig. 3-47 b, but may be placed in any convenient location within a multilayer metal scheme. A resistor requires a conductive resistor stripe and contacts. A channel-type structure will require some form of peripheral isolation. Thus the fabrication of resistors must be carefully considered when planning the process sequence. Either a trench, mesa, or ion implantation scheme must be used to define the body of the resistor and to isolate the contact region for channeltype resistors; deposited film resistors may be defined by photolithography and etching or liftoff processes. Greater latitude is permitted for the deposited film structures built on dielectric layers, as the resistor bodies can meander over the surface (with some restrictions) without consuming valuable active area. A larger range of resistivity values is accessible to the thin process relative to the channel-type structures. The processing associated with the resistor fabrication must not exceed the thermal constraints of the preceding processing sequences. The resistance value ( R ) achieved in a resistor is defined by the relationship (3-12) where e is the resistivity of the conducting medium, L is the length, and W is the width of the resistor body; t is the layer thickness, implant thickness ( 2 AR& or the total active epitaxial layer thickness, 2 R , is the sum of the contact resistances, and W, is the effective contact width. A resistor structure is shown in detail in

-

146


Substrate

b)

Figure 3-47. In a) a cross section of a channel-based resistor is illustrated. The effective length of the resistor is “I”. Ohmic contacts define the effective length. The width is determined by perimeter isolation [mesa or implant (shown)].A dielectric layer is used to protect the resistor body during subsequent processing steps. Figure 3-42 b illustrates a resistor structure made with a thin film resistor material. The layer is deposited on a dielectric as shown, and patterned by photolithographic methods. Metal contact pads are deposited and patterned on the ends of the resistor. Taps may be placed along the resistor body, if required. The effective length of this resistor is I, with the width determined by the lithography. Controlling the thickness or the chemical constituents in the film provides a high degree of control over the resistor properties.

Fig. 3-48. If multiple conducting layers are used in the resistor stripe, such as in an n + - n layer structure, Eq. (3-12) is modified to accommodate parallel conduction effects. For practical resistor structures, the contact resistance will be negligible (typically much less than one percent of the resistor value), and well within the resistor process variations. Resistors formed with the semiconductor conducting layers are relatively easy to implement. No additional mask levels are needed as the chan-

nel can be patterned with the process sequences of ohmic metallization and isolation. Typical resistivity values are in the range of -100-1000sZ/~,but this range may easily be extended with additional ion implantation and annealing steps. The implementation of channel-type resistors has several drawbacks: surface depletion (surfacestates) can affect the charge in the resistor stripe, surface potential offsets may arise with dielectric deposition, a

147

3.10 Resistors

Figure 3-48. Detail of a resistor structure showing the critical dimensions and features. The contact resistance is predominantly at the interface of the metal and the semiconductor. The bulk resistivity determines the dimensions of the resistor relative to the needs of the circuit design. W, is the effective contact width, W is the effective width of the resistor stripe, t is the effective thickness of the layer, and L is the effective length.

relatively large temperature coefficient of resistivity exists (band gap energy coef!icient, impurity ionization, mobility effects) saturation of the current-carrying capability can occur, heating or cooling effects alter the charge density and carrier mobility, and slow domain oscillations and high frequency (Gunn-type) oscillations can arise from charge injection into the substrate. All of these effects, described below, compromise the performance of such a resistor structure. Careful layout (with respect to power distribution busses, proximity to critical nodes, etc.) is necessary to minimize interactions with the resistors and other circuit components. The realities of IC fabrication manifest themselves in resistor structures in the following manner. Surface depletion can decrease the available charge in the resistor stripe, and generally leads to higher resistance values than expected. Owing to process-induced variations in the layer thicknesses, charge density, dimensional tolerances, surface states, and surface contamination effects, the resistance may actually increase or decrease in an uncontrolled manner. Layers of high sheet resistivity, with their correspondingly low-charge density, are more susceptible to these variations. The application of a dielectric film will tend to ameliorate the effects of surface states, but can aggravate control of the resistance owing to the generation of stress

and piezoelectric effects. The magnitude of these effects are subject to the dielectric film composition, surface preparation, and deposition conditions. Thermal effects must also be considered, as carrier mobilities decrease with heating (proportional to T -3/2). Thus the resistor value increases when significant power is dissipated in the circuit or the resistor. In addition, when temperatures are very high ( > 100°C), the effects of band-gap narrowing may also begin to influence the transport properties, again altering the resistivity. This behavior is of importance to the designers, as compensation networks may have to be built into the circuit to accommodate these changes in resistance. Since the resistor body is essentially the transistor conducting channel, it is subject to the same current saturation limits as the transistors. For most compound semiconductor materials, channel saturation occurs at electric field strengths of 10005000 V cm- (Sze, 1981d, pp. 44, 325). While these effects can be mitigated by careful design and control of the voltage drop across the resistor, it presents an additional restriction for the device designer and process engineer. Attempts to exceed the saturation values will lead to excessive heating and accelerated failure. Critical field effects may arise from both DC and AC operating conditions when the resistors are biased. Above the critical field

'

N

148


strength, charge may be injected into the regions surrounding the resistor (isolation regions or the semi-insulating substrate). Self-oscillations may then occur in the compound semiconductor material. These oscillations may be realized as “slow domains” (Ridley and Walkins, 1961; Ridley and Pratt, 1965; Kaminska et al., 1982), and Sec. 3.3.3) or high frequency, Gunntype oscillations (Sze, 1981, Chap. 11). In GaAs slow domains can be created when the electric field strength exceeds roughly 500- 1000 V cm- (Kaminska et al., 1989); Gunn oscillation are created at a field strength in excess of roughly 3000 V cm(see Sze, 1981d, Chap. 11). A major consideration in the use of channel resistors is the heat dissipation. The thermal conductivity ( x ) of GaAs is only -0.48 Wcm- K - ’ (EMIS, 1990, Sec. 1.8), and the thermal diffusivity is only -0.27 cm2 s (EMIS, 1990, Sec. 1.9).In InP these values are -0.56Wcm-’K-’ and -0.4 cm2s, respectively (EMIS, 1991, Sec. 1.8 and 1.9). Therefore care must be taken to avoid excessive local heating and thermal runaway conditions, particularly if a resistor body is adjacent to an active device. The last concern for channel-type resistors is the large distributed capacitance which arises from the depletion effects along the length of the resistor. The capacitance is of particular concern for “long” resistor stripes (high-resistance values), which can lead to intractable RC time constant problems and a significant reduction in device operating speeds. Inductive parasitics also arise with long meandering resistors, which again can limit high-frequency operation and create unexpected operating instabilities. Thin film resistors may be constructed on the semiconductor surface (with implant isolation beneath the resistor body

’

’

Table 3-8. Thin film resistor materialsa. Metal

Cr Ti NiCr TaN a

Resistivity range

wn)

Temperature coefficient (PPm K - ‘1

13 55-135 60 - 600 280

3000 2500 200 -180 to -300

From Williams (1990, p. 306).

and contact regions), or above the first or subsequent dielectric layer(s) by the deposition and patterning of thin layers of Cr, Ni-Cr (nichrome), TaN, or other materials (see Table 3-8). These resistor films have specific resistance values in the range of 10- 1000 n/n which provides a suitable range of resistor values. The deposition and patterning of these films on the semiconductor surface are subject to many of the effects that affect the channel-type structure described above. The formation of a thin film structure involves depositing a uniform layer of the resistor material, then photolithographically defining the appropriate pattern. Etching of the exposed material is carried out using plasmaetching techniques. Contact metals are then deposited on the resistor stripe as desired, patterned, and annealed to alloy the contact to the resistor body. Tapped resistor structures can be readily fabricated. These tapped resistor structures may be implemented in tuning high-frequency response or circuit gain characteristics, using laser ablation or current pulses to break the film at a desired location. By depositing the thin film layer on the dielectric, numerous advantages are gained relatively easy control of the resistance value, a trimming capability [laser trimming or focused ion beam (FIB) repair], reduction of the distributed capacitance,

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3.10 Resistors

149

Film resistors may be trimmed by laser ablation methods to “fine tune” the resistance value at the time of testing. More recently, with the advent of the FIB techniques, the resistor stripes may be repaired, or built-up, albeit this approach is presently limited to very costly circuitry. Fringing capacitance effects are minimized by the use of deposited film resistors, as the charge in the semiconductor is well removed from the resistor stripe. The dielectric constant of the dielectric layer may be optimized and a minimized capacitive coupling may be effected with a thin film structure. This can lead to significantly reduced RC time constants relative to channel-type resistors. In principle, the limit to current flow in a thin film resistor is the maximum current density supported by the material. This is constrained practically by electromigration phenomena, the heating-related effects, the materials’ temperature coefficients, and the maximum power dissipation of the resistor and substrate materials. As the dielectric materials are well behaved, there is little concern for charge injection, oscillations, and nonlinearity in the thin film structures deposited on dielectric layers when operated at high bias levels.

and design and layout flexibility at the expense of an additional masking level. Thin film deposition provides a large degree of process control, although the films are typically less than 100 nm thick. Evaporation and sputtering processes are the deposition methods used for resistor fabrication: plating processes are insufficiently well controlled. A caveat with these thin film structures is that continuity is strongly affected by pinholes and inhomogeneities in the film. High current densities in the thin film resistor can result in electromigration problems, localized heating, and catastrophic failure, particularly at the junction of the contact pad and the resistor body. These effects are similar to electromigration failures in drain/source or gate metallizations. This failure mechanism is illustrated schematically in Fig. 3-49 [see Magistrali et al. (1992)l. The adhesion of the resistor film to the semiconductor or dielectric material is a critical issue. This problem is typically surmounted by the deposition of a dielectric layer over the resistor to protect the thin film layer from damage, stresses, and confine the film. Control of the resistance value is influenced by the variations in film thickness, defined width, and film composition.

Region of Failure

Contact

-

Material Migration

Material Pile-up

Current Crowding

Figure 3-49. A schemdlic picture of film resistor failure The electromigration-induced transport of material (“electron wind”) causes a high resistivity region to form near one contact. Some material is transported to the opposite end of the resistor The loss of material creates a “hot spot” which ultimately fails catastrophically.

150


3.11 Metallization and Liftoff Processes A metallic conductor is required to provide the interconnection of devices, interlevel and back-plane connections (vias), and for electrical and thermal conduction paths to the external environment. The conductor material must have the following properties: a high electrical and thermal conducticity, be electrically and mechanically stable, be chemically inert yet patternable by fabrication-compatible chemistries, possess good adhesion characteristics, be corrosion resistant, ductile, and compatible with the processing sequences which follow the deposition and definition steps. The key issue for metallization and interconnect processes is minimizing the electrical resistivity in runners and vias to prevent excessive power dissipation and the concomitant loss of signal, as well as the operating speed limitations due to RC time constants and heating effects, while utilizing minimal geometries. Au, Al, Ti, Ta, W, Ge, various silicides, and numerous gold-based alloy materials are compatible with most compound semiconductor processes (Howes and Morgan, 1985, Chap. 6; Williams, 1990, Chap. 11). However, to prevent undesired chemical and metallurgical reactions, many of these materials must be used in a “multilayer” configuration, i.e., a barrier layer and high conductivity “bulk” metal(s). In addition, the interconnection metal must be stable to electromigration processes which arise at current densities above 10’- lo6 A cm- * (Davey and Christon, 1981; DiLorenzo and Khandelwal, 1982, p. 345; Williams, 1990, Chap. 20; Irvin, 1982). Furthermore, this stability must be maintained under highly stressful testing and operating conditions, e.g., accelerated aging, testing and

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operation at elevated temperatures, high bias, and high humidity. Only then can a material be called suitable for use in compound semiconductor devices. Unlike those in silicon-based products, such metallizations must be stable for tens of thousands of hours at substantially higher operating temperatures, ca. 150-200 “C. Metallization schemes are a major issue in IC interconnects. The typical “twolayer” processes prevent minimal dimension ICs from being fabricated due to the dominant problem of power routing. Thus lower performance, lower yields, and higher cost circuits are realized. Threelevel (Lee et al., 1989) and four-level (Vitesse, 1990, 1995; TriQuint) interconnect schemes provide for flexibility in signal and power routing, and allow for significant circuit compaction and optimization of the signal and power distribution. In multi-layer metallization schemes, the control signals are typically carried in the lower layers, while the power distribution and ground connections are handled in the upper layer(s). A commercial four-layer metallization process is illustrated schematically in cross section in Fig. 3-50. In this figure, the interconnection is made from an upper metal layer to a lower level metal directly. The multi-layer configuration shown in Fig. 3-51 is a “post-andrunner” structure. The interconnect layers would be created by sequential metallization, patterning, and some form of via-fill/ selected-area metallization. The interconnect runners are formed by aluminum or gold-based metal deposition processes, and photolithographic patterning techniques. The posts may be formed during the interconnect metal deposition or by, for example, selective-tungsten CVD processes (Wilson et al., 1993), as shown in Fig. 3-52. Each subsequent layer is generally printed with a slightly larger critical

3.1 1 Metallization and Liftoff Processes Mask levels

Process

Technolooy

4 layers of Aluminum Interconnect

Conventional state-okhwrt Silicon Interconnect

EF:ET

Proprietary to Vitesse

GoAs

Multiple 4 inch wafer vendors

151

I

41 ' } Gate Metal

~

MESFET Cross-section

Implant

Figure 3-50. A schematic cross section of a four-layer interconnect metal scheme. Aluminum is utilized for the

uppcr levcl metal laycrs in thcsc MESFET ICs. (Figure courtesy of C. Gardner, Vitesse Semiconductor Corporation, Camarillo, CA.)

Deposited SI,.N, S i w or SiO, Passivation I

as required

I

\

\ Deposited S i SiO&, or SiO, Passivation

Figure 3-51. Details of B "post-and-runner" multi-level metallization scheme. Two levels of metal are shown above the ohmic contact. The via plug may be formed by selected area chemical vapor deposition or by blanket deposition and etching. A substantial amount of planarization may occur in this type of structure as the dielectric layer tends to smooth out height variations and steps. This structure may be continued above the two layers by successive depositions and patterning.

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Figure3-52. An SEM cross section micrograph illustrating the details of a four-layer “post-and-runner” metallization process. The via plugs are selectedarea CVD tungsten, with a titanium adhesion layer and gold main metal on each tungsten plug. The magnification marker is 1 pm; the via diameters are approximately 1 pm, and the interconnect metal layer thickness is approximately 400- 500 nm. (Figure courtesy of Dr. M. Wilson, Cray Computer Co., Colorado Springs, CO.)

dimension as a result of circuit topology constraints. A substantial amount of planarization may be realized as a side benefit of the larger dimensions. However, as is evident in Fig. 3-52, this is not always required. In any case, the larger dimensions of the upper level metallizations have the distinct advantage of a higher current carrying capacity, ideal for low-loss power distribution busses. A four-level “post-andrunner” metal interconnect scheme is shown in a SEM micrograph (Fig. 3-53). This type of multi-layer process has proven to be reliable and manufacturable with high yields (Mickanin et al., 1989; Wilson, 1989). The circuit compaction permitted by multi-level metallization allows for significantly improved high-speed performance. This is achieved predominantly by optimizing the routing through various levels of interconnect and minimizing the distance between critical nodes in the circuit. At present, the use of fourth metal-level

power routing with relaxed design rules can approach 50% surface area utilization for both power and ground distribution lines (Vitesse). Since adding an additional metallization layer only requires relaxing the critical dimensions (due to surface topology), a via process, and a dielectric layer, there is no theoretical limit to the number of levels of metal. With present technologies, however, the topological considerations and yield limits mitigate against development above four or five metal levels.

3.1 1.1 Metallization In the manufacture of compound semiconductor devices, the interconnect metallizations are still predominantly gold and gold alloy based. Aluminum-based metallization processes are being introduced to fabrication sequences [see Vitesse (1990)], but the use of aluminum and aluminum alloys, while well understood in the silicon

Figure3-53. An SEM micrograph of a four-layer “post-and-runner’’ metallization process with interlayer dielectric removed. This figure illustrates the beauty and utility of the multi-layer metallization process. The fine geometry lines are gate fingers of nominally 1 pm in dimension. The increasingly larger metal lines are evident at higher levels. (Figure courtesy of Dr. W. Mickanin, TriQuint Semiconductor, Inc., Beaverton, OR.)

3.11 Metallization and Liftoff Processes

industry, is subject to the same constraints as are found in silicon processing: e.g., the formation of Au-A1 intermetallic compounds with undesirable high resistivity [e.g., “purple plague”, see Irvin and Loya (1978), and Irvin (1982)], and concerns for long term reliability from alloying materials such as copper. To minimize the metallurgical reactions and rapid in-diffusion of gold, barrier metals such as Pt, Pd, W, or Ti must be used between the contact layer (semiconductor or metal) and the gold interconnect layers. Numerous metallizations have been tried in the compound semiconductor field. The reader is referred to Sec. 3.6, and Howes and Morgan (1985, Chap. 6), for additional supporting discussions. As the processing of compound semiconductor devices matures, aluminum alloys are being used in an increasing number of applications. Aluminum and aluminum alloys have the distinct advantage of being patterned readily by reactive ion etching, ion milling, or lift-off methods, as well as relatively low cost. Gold can be effectively patterned by lift-off or ion milling processes. Submicrometer features may be patterned readily in any of the common metallization systems used in compound semiconductor IC fabrication. The aluminum layers are commonly alloyed with copper to stabilize the material against electromigration failure. In silicon devices, copper has not been found to affect device performance. For GaAs, copper is a deep acceptor with at least four deep levels in the lower half of the energy gap (see Fig. 3-3) (Kullendorf et al., 1983). This can give rise to slow transients and erratic device behavior under certain bias or operating conditions (strongly related to device design and structure). For GaAs digital applications, the Al-Cu system appears to be suitable. In the case of R F or

153

mixed signal applications, the process sequences and device structures and operating points are significantly different, and may result in compromised device performance. In InP materials, copper has at least three deep acceptor states, and, in fact, high concentrations of copper give rise to a semi-insulating characteristic and copper precipitation (Leon et al., 1992). Thus great care must be exercised when using Al-Cu metallizations. Gold-based interconnects, on the other hand, are problematic in the silicon case (carrier lifetimekiller centers), but are highly effective for compound semiconductor devices. Typically, gold-based gates and interconnections are utilized in processes that do not use ion implantation beyond the formation of the junction, isolation, and contact layers. This is due to the rapid diffusion and metallurgical reactions which occur at temperatures of 350- 500 “C in most compound semiconductors. A common interconnect metallization used in GaAs IC fabrication is the Au/Pt-Pd/Ti system (Niehaus et al., 1982). Here the titanium layer is used to enhance the adhesion. The palladium or platinum layer acts as a diffusion barrier against gold interdiffusion, and to mitigate the reaction of titanium and gold which occurs at -200°C. Since gold, platinum, and palladium have high conductivity, this “sandwich” structure produces very low resistivity interconnects. An interconnect for higher temperature applications is based on Ti-W/Au. The Ti-W layers are used to contact the semiconductor and provide a diffusion barrier to the gold, while the gold layer carries the majority of the current. This contact has been found to be stable to 500-6OO0C, although adhesion problems, differential thermal expansion (stress), and degradation mechanisms are not yet completely controlled. In addition, sputter

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deposition must be carefully controlled to prevent leakage currents due to surface damage (Kohn, 1979; Day et al., 1977). Interdiffusion is a problem with a number of desirable materials due to the reactivity of GaAs and InP with a wide range of metals. These reactions are well understood through the phase relationships for these systems. For example, aluminum on GaA interdiffusion has been observed at 250 “C and extended times (Mukherjee et al., 1979; Sealy and Surridge, 1975). It should be noted that for aluminum-based metallizations, 250°C is quite near the “2/3 melting point” criteria used in metallurgy for defining stability to interdiffusion, and thus such interactions are expected. For further understanding of potential intermetallic phase formations, see Massalski (1 986). As previously discussed, barrier metals or alloying elements can be used to improve the stability and minimize interdiffusion in the contact regions. High temperature interconnects and metallization are used when the wafer may be subjected to high processing temperatures as required for ion-implantation annealing. These materials were discussed in Sec. 10.6 in the context of gate formation. Such interconnect configurations are typically constructed from refractory metals such as Ti-W, W-Si, Ti-W-Si, W-N, Ta-N, and Ta-Si (some of these materials may also be used for thin film resistor stripes). It has been found that these materials withstand temperatures well in excess of 850 “C without significant interdiffusion [see Dautremont-Smith et al. (1990)l. There are significant limitations in the metal line widths, achievable by different patterning methods. The electron beam (e-beam) writing system has achieved dimensions below 100 nm in the laboratory, but this is a very daunting proposition for

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the fabrication line where control, low cost, and reproducibility are required. An example of a -0.1 pm e-beam-exposed, T-gate structure was shown in Fig. 3-38. Typically, gate dimensions as small as 0.5 pm are printed by step-and-repeat systems (Wilson et al., 1993), whereas “0.25 pm” technology is implemented with e-beam methods (Danzilio et al., 1992). Smaller gate features require multi-layer offset photoresist patterning, electron beam, or other short wavelength processes such as deep ultraviolet exposure. Owing to instrument throughput constraints, the e-beam is only used to write the finest gate features, not the general metallization patterns. The step-and-repeat systems can control line widths down to -0.4-0.5 pm using the G-line, and 0.3 pm using the I-line, from high intensity mercury vapor light sources. Figure 3-54 shows a 0.36 pm gate feature defined by G-line exposure and liftoff methods. Finer features can be produced

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Figure 3-54. A SEM micrograph showing a recessed gate opening. The magnification marker is 1 pm. The trench dimension is 0.356 pm at the bottom, printed by G-line photolithography. This dimension represents the limit to G-line lithography with single pass step-and-repeat exposure systems, and standard photoresists. (Micrograph courtesy of P. A. Grasso, S. E. Lengel, A. F. Williams, Lucent Technologies, Inc., Reading, PA.)


155

b)

Figure 3-55. A schematic view of a method for creating fine features with process-limited photolithography. a) A layer of photoresist is deposited and exposed at a controllable dimension. A second layer of photoresist is dcposited on the wafer and exposed with a specific offset to the original pattern. Clearing the exposed photoresist leaves a bilayer offset feature as shown in (b). Subsequent metal deposition, preferably at a substantial angle, produces a fine metal feature of dimension much less than the photolithography limit, if desired.

by careful control of the photoresist thickness, exposure conditions, multi-layer/ multi-exposure photoresist and metal thicknesses. Figure 3-55 schematically illustrates a method of offsetting multiple photoresist layers and implementing directional metal deposition to achieve finer metal line geometries. In the upper metallization levels there are fewer constraints in the metal line dimensions, but patterning and dimensional control may be complicated by the topology. Planarization by

dielectric deposition can partially relieve these problems. Ion milling or sputtering methods may be used for metal pattern definition. This process requires a high vacuum system and appropriate high current ion sources or plasma excitation systems. In the ion milling process, a high flux ion source is used to sputter the unwanted metal atoms from the exposed surface. In sputtering processes, an ion plasma is created above the wafer surface which removes metal

156


atoms by physical sputtering processes. Argon, or chlorine-containing compounds, are typically used for the source gases. Nitrogen gas may be added to ballast or control the ion milling rates. The patterning of fine features is limited by the spacing of adjacent metal runners due to shadowing of the ions by the topology of the metal and existing wafer surface, as well as the photoresist or other defining layer (e.g., a second metal, a dielectric layer, or a combination of photoresists and metals or dielectrics). Ion milling is relatively slow compared to liftoff processes, although it leaves a very smooth surface and is not subject to edge burring and adhesion-strength limitations. Sputtering is relatively rapid and can be used to etch fine features. One of the concerns in ion milling or sputtering is that in the process of etching, residual ion damage and redeposition of sputtered species may occur, which can lead to surface-state-induced electrical effects or leakage paths in devices. In most process tools, only a single wafer or a few wafers can be etched at a time, leading to a limited throughput in the apparatus. The topic of ion etching was discussed in Sec. 3.5 in a more general context. The criteria and utilization presented therein are applicable to metallization patterning.

3.1 1.2 Liftoff Processes Liftoff procedures are implemented when metallizations are incompatible with chemical etchants, or ion-based patterning is undesirable. The as-deposited metal layers are required to be ductile and adherent in order to permit the selective separation of the unwanted metal from the wafer surface. In addition, the control of step, edge, and side-wall coverage is critical for providing a “weak link” to permit separation of the

metal film, Metals that are deposited by evaporation or plating meet these criteria and are generally quite well suited for liftoff processes. These patterning methods are particularly effective for gold or gold-based materials, as deposited gold layers are nearly “dead soft”. Sputtered metal layers, and particularly refractory metals, are more difficult to liftoff successfully due to high adhesion to all surfaces, relatively good conformal coverage of steps and edges, and their tendency to be harder in the as-deposited state. Liftoff processes involve the creation of high aspect ratio trenches or undercut pattern features in the patterned photoresist or dielectric layer@),coupled with a “directional” type of metal deposition process. The metals are deposited over this patterned sacrificial film. Then the metal layer and sacrifical film is stripped off by mechanical, chemical, or chemo-mechanical means, so “lifting” the unwanted metal from the surface. To successfully carry out the liftoff process, complete, full thickness metal coverage at the edges of the photoresist or dielectric layers is highly undesirable. Electron beam or resistance-heated evaporation methods are best suited to the deposition of metal layers due to the highly directional nature of the evaporation process, resulting in “poor” edge or corner coverage, as illustrated by Figure 3-56. Other methods of metallization, such as sputtering or plating, tend to provide a more uniform surface coverage, and thus are less well suited to liftoff techniques, unless the sacrificial layer is shaped to create a thin parting line in the metal. The thickness of the dielectric or photoresist, and the edge definition, play a critical role in the perfection of the liftoff procedure by influencing the thickness of the metal coverage during deposition. The metal at step edges and corners is typically much thinner than


157

Metal Flux

b)

Figure 3-56. A schematic illustration of an optimal liftoff metal coverage. a) The key to a clean metal liftoff lies in the thin or nonexistent coverage of the side walls of the gate or metal trench feature. b) The thin lines of metal part readily from the main metal line when the photoresist of patterning material is removed from the wafer, leaving the desired metal line pattern.

the bulk regions of the metal film. Therefore the film is much weaker than the bulk and easily parted at these sites. The thinning or lack of coverage at the feature edges is also important for the prevention of burring and the elimination of interlayer short circuits. However, great care must be exercised in lifting off the metal, as many desired metal traces have steps and edges in their topology. Several methods of “lifting” the undesired metal are available. All of the methods rely on a solvent (water or organic chemicals) or an etchant to dissolve the sacrificial layer. Typical photoresists are

quite soluble in acetone or other organic solvents. Sacrificial dielectric films may be dissolved with H F or other suitable acids or bases. This latter approach has been used for large area liftoff of epitaxial films (Fan, 1990; Yablonovich et al., 1990) by utilizing sacrificial AlAs or AlGaAs layers. Subsequently, the unwanted metal and the sacrificial layer are floated or “scrubbed” off the surface of the semiconductor wafer with agitation, a high pressure fluid spray, or other mechanical means. As uncontrolled physical/mechanical scrubbing can be quite damaging to the remaining metal, most processes use deionized water or

158


other solvents at moderate pressures and flows to remove the metal and residual photoresist or dielectric materials. Metal recovery systems are used to reclaim precious metal wastes in these processes. The adhesion of the metal to the desired surfaces must be strong in the as-deposited state or the metal layer may be removed from undesired areas during the liftoff. At the same time, poor adhesion of the metal to the sacrificial dielectric or photoresist layer is highly desirable. In addition, relatively thin metal layers must be used to prevent tearing of the metal or lifting off of the desired layer. Edge lifting and undercutting may occur if the adhesion to the

desired contact region is insufficient. Burring can be a problem with liftoff processes owing to the ductility of the metals in the as-deposited state. The liftoff processes may tear the metal at the parting lines due to thickness variations, grain structure anomalies, adhesion variations, particles, etc., leaving small burrs along the edge of the metal line. This issue is illustrated in Fig. 3-57. The burrs can protrude through the next level of dielectric causing short circuits between the metal layers. Careful preparation and well-controlled deposition conditions are required to ensure clean removal of the unwanted metal. Figure 3-58 illustrates a “clean” edge defini-

Metal Flux

b)

Figure 3-57. An illustration of a burr formed on a metal feature due to improper trench edge definition or excessive metal layer thickness. In this case the burr may extend along the metal line or be an isolated fine point. This may cause interlayer shorting due to poor dielectric coverage in subsequent process steps.

3.12 Backside Processing and Die Separation

159

amount of yield reduction from open circuits, electrical contact resistance variations, burring, and short circuits. While these drawbacks can be quite serious, many materials cannot be successfully etched or ion milled, thus liftoff processes are the only viable alternative. It should be noted that commercial liftoff-based processes are quite robust, and presently operate with high yields.


Figure 3-58. Secondary electron micrographs of air bridge structures formed by liftoff methods. The marker is 10 pm in both images; the span dimension is approximately 25 pm. In a) a “sea” of approximately 125 air bridges over interconnect metal lines is presented. Note the moderate take-off angle of the bridge, leading to high strength and high reliability, and the elimination of electrical shorting. Bridge structures such as these readily withstand backside processing. (The micrographs are courtesy of P. A. Grasso, S. E. Lengle, A. F. Williams, Lucent Technologies, Inc., Reading, PA.)

tion on a multi-fingered air bridge structure created with liftoff methods. The air bridge was constructed by a sacrificial layer post-and-runner process. At the present time there is no solution for complete amelioration of the problems of edge lifting and minor tearing/burring of the metal layer. This results in a minor

Backside processing is carried out when the wafer must be thinned or if a back-surface metallization layer is needed. It is generally desirable to thin a compound semiconductor wafer to improve device performance from both the thermal and electrical standpoint. For example, thin wafers and the use of backsurface ground planes are critical to the R F performance of microwave ICs. The spacing of the top surface conductors to the ground plane (back surface) creates a controlled impedance condition for transmission lines, which is required for stable microwave performance. It may be necessary to link the top surface ground lines to the back surface ground plane, i.e., through-wafer vias are required. In addition, thinner substrates and through-wafer vias permit vastly improved heat extraction from the circuit. As the thermal conductivity of GaAs and InP is significantly less than that of silicon, this is a critical issue, as shown in Table 3-9. Thus by thinning the wafer, greater power may be dissipated per unit area for a given temperature rise, permitting compact, highpower devices without compromising performance. If no backside processing is required, the wafer would pass to die separation, as described in Sec. 3.12.2.

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Table 3-9. Thermal conductivity of selected semiconductorsa. Silicon

Gallium arsenide

Indium phosphide

0.48’

0.56d

1.5b

“Values in W c r n - ’ K - ’ at 300K; bSze (1981, App. H);‘ EMIS (1990, Sec. 1.8); EMIS (1991, Sec. 1.8).

One of the key issues in the backside process flow is attention to detail; the importance of this point cannot be over-emphasized. Since the front side process is now completed, it becomes an extremely expensive proposition to damage the active circuitry while thinning and metallizing the back surface. There is a great amount of handling in the backside process which subjects the wafer, in a relatively weak condition, to significant abuse. Breakage, contamination, and physical damage (e.g., scratches and chips) may occur at each of the mounting, grinding, pol-

ishing, cleaning, etching, metallization, and demounting steps, which encompass the backside process sequence (Fig. 3-59). In comparison to silicon fabrication, compound semiconductor materials are much “softer” (the hardness of GaAs is approximately one-tenth that of silicon), and have facile cleavage, which emphasizes the importance of careful handling to avoid chips and breakage. Finished die costs are highly dependent on the success of this final process step. Very little information on the complete backside processing sequence has been made available in the public domain, as it is considered highly proprietary. The process flow description herein is drawn from the authors’ experience and discussions with other experts, and represents a “hybrid” view of the backside issues.

3.12.1 Backside Processing The process involves a multitude of steps to complete the wafer process flow as shown in Fig. 3-59. The principal tasks to

9 Cleaning

Optional: Electrical Testing

Via Fill

Grind (oneor two-step)

9I

Through-wafer

b Plating-up

Cleaning

IPolish (chemical or mechanical)

I Cleaning -1

I Via Etching

Substrate

Figure 3-59. An example of process flow options for creating back surface metallizations, through-wafer vias, die separation, and the selection of viable devices.


be accomplished are: mounting, grinding, cleaning, polishing, and if required, masking, via etching and finally, metallization. Following these processes the wafers will be electrically tested and optically inspected, the useable die separated by various means, and the die passed to assembly and packaging. Mounting involves fixing the wafer topface-down onto a supporting substrate to facilitate the grinding or lapping processes and subsequent handling in a thinned condition. This mount must be physically strong, stiff, extremely flat, and not damaged by the thinning processes. Sapphire or quartz mounts, ground and polished to optical flatness, are suitable for this task. Other materials may be used if back-tofront alignment is not required. The wafers may be affixed to the mount by an IR-transparent adhesive (e.g., paraffin, beeswax, or other readily soluble, noncontaminating materials of low melting point). It is critical to ensure that the mount is free of particulates and that the wafer is parallel to the mount surface. The wafer must not be subjected to excessive stress or pressure during the mounting procedure, and great care must be take to prevent damage to the front side structures. This latter point is particularly important when air bridge technology is employed. Wafer thinning is a slow, labor-intensive process even with automated apparatus. The initial grinding or lapping of the back surface may remove up to -95% of the original thickness, with an accuracy of a few micrometers ( 0.1 mil). Typically the wafer is ground to a thickness slightly greater than the final target value, and then chemically polished or etched. This step removes grinding damage and achieves the final thickness and surface quality suitable for via etching and/or metallization. High precision grinding apparatus are required

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161

for this task, with well controlled stock removal rates to prevent damage to the wafer and to ensure accurate thickness control. Fine diamond grit (1- 10 pm nominal) grinding wheels can produce a good surface flatness at economical grinding rates without generating excessive damage to the substrate. Commercial vertical spindle/ horizontal pass grinding units can achieve very good control and reproducibility of the thickness and surface quality (Lapinsky, 1991). Following the grinding procedures, the wafer and mount are carefully cleaned to remove grinding residues. This step involves a detailed inspection of the wafer to identify any surface damage, fractures, or chipping of the edge. The wafer may then be chemo-mechanically polished to the final thickness, removing the gross damage from the grinding and preparing the surface for metallization or masking and via definition. The final polish chemistry is typically based on NaOCl or NH,OH etching solutions as they are anisotropic and produce a superior surface finish (Stirland and Straugham, 1976). For InP substrates, mixtures of bromine and methyl alcohol are typically employed (Chin and Barlow, 1988). Chemo-mechanical etching tends to slightly round the wafer profile as polishing occurs. Therefore care must be taken to maintain the flatness and parallelism of the wafer surface. In addition, the polishing systems must be well-characterized to achieve an accurate final thickness as the material removal rates vary strongly with pressure and solution pH. In a wellcontrolled process, variation can be maintained within 2.5 pm (0.1 mil) to 5 pm (0.2 mil) for a final thickness ranging from 100-250 pm (Lapinsky, 1991). Wafers for certain microwave or high power applications are thinned to as little as 25 pm (1 mil). At this thickness the wafer will

162


readily conform to corrugations in the NIT TO^^ mounting tape. The mounted wafer is now ready for backside metallization. As shown in Fig. 3-59, there are two paths: photoresist deposition and exposure of the via pattern to create the front-to-back contacts, or, if vias are not required, the mounted wafer is cleaned and passed to metallization. Typically, a 4 mil (100 pm) or thinner wafer will not be demounted as cleavage is quite facile in compound semiconductor materials; 250 pm (10 mil) thick wafers can be carefully handled without a carrier. Thorough cleaning is again critical to the success of the process, as adhesion of the photoresist and the initiation of etching are strongly influenced by the surface condition. The masking layer for backside processing must be significantly thicker that required for the front surface processing. Owing to the very extended etching times needed for opening vias through hundreds of micrometers of substrate, the masking layer must be much more robust, although the precision of the critical dimensions are more relaxed than for front side processes. Multi-layer masking techniques may be used to minimize via “blow-out” (expansion significantly beyond the patterned dimensions) and damage to the substrate (edge lifting, pinhole leakage, etc.). For example, additional layers of photoresist, or metals such as Ni or Cr, could be applied on top of the base photoresist layer. Exposing a through-wafer via pattern requires a “front-to-back” infrared aligner system. In this apparatus the front surface metallization pattern is imaged through the carrier and wafer using sub-bandgap infrared light. The alignment of the via mask pattern is referenced to the target contact pads on the front surface. Exposure is carried out as with normal photoresist techniques with the exception that very extended exposure

times may be required. In multi-layer processes several passes through this sequence are necessary. The through-wafer vias are etched in a manner described. Reactive ion etching is becoming the preferred method, as the morphology and aspect ratio of the via may be controlled through the etching conditions (pressure and gas compositions). With wet chemical methods, the vias tend to expand laterally as vertical etching proceeds even with highly anisotropic etchants. It is difficult to control the final ‘over-etching’ of the target areas and minimize the damage to the front surface if etchants leach around the metal contact pads. Also, the aspect ratio of the via and the side-wall structure is critical to the metallization process: severely undercut edges, re-entrant corners, or curved side walls (Fig. 3-60a), or vertical side walls and sharp corners (Fig. 3-60 b), will prevent or complicate successful metallization coverage, leading to unsatisfactory continuity, high resistivity, and poor reliability. Metallization steps are carried out after careful cleaning of the etched wafer. Residues are often left on the surface due to polymerization or overheating from the ion plasma during RIE, or residual byproducts from the chemical etching procedures. It is crucial that any foreign materials are removed as the metallization quality may be affected or inhibited entirely. There are several approaches to backside metallization: 1) deposit a thin layer of metal(s), form a plug in the via hole, and then deposit a thick, full surface metal layer over the entire wafer; 2) deposit a thin metal layer for contacting, and then use a “solder” flow process to fill the vias and provide the full surface metal coverage. Many variations of these general approaches exist.


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Back Surface of Wafer

Front Surface of Wafer

Metallization may be carried out in two or three steps: the first to provide an intimate conformal seed metal layer to ensure ohmic contact to the exposed (back surface) metal pads on the front surface (Fig. 3-61), then to “plug” or “fill” the vias, and the third step to completely contact the surface and the vias creating the ground plane. This may entail the addition of a

Figure 3-60. Illustrations of undesirable via morphologies. In Fig. 3-60a, the effects of undercutting or re-entrant corners are evident. Metal coverage and continuity are compromised by these conditions. Figure 3-60b highlights the additional problems of sharp corners and vertical side walls. Here the filling of the via may be compromised by the vertical wall, and the sharp corners enhance stress localization.

planarization metal deposition or the application of a thick back surface metallization. The first metallization may be an adhesion promoting layer (e.g., titanium), or a layer of gold or gold alloy. The plug process must fill a via to the level of 100250 pm and be relatively planar. When the final metal layer is formed it must be adherent, uniform in thickness, and planar.

164


Figure 3-61. Schematic illustration of a well-defined through-wafer via. The corners of the via are rounded to enhance continuity and minimize stresses. The seed plating is continuous and the filling metal shows only limited underfilling. A planarization metal layer is shown (optional). The final back surface metal layer provides the continuous back-plane conductor.

Front Surface of Wafer

Examples of the plug process are shown in Figs. 3-62 and 3-63. In Fig. 3-62 an SEM micrograph shows a view of a via hole. The morphology of the wall of the via is apparent. A series of via plugs with top surface contact pads is shown after etching away the substrate in Fig. 3-63. The surface morphology of the via perimeter is evident on the gold plugs. It is clear that

the shape of the via hole is critical for achieving continuity between the back plane and the front surface contacts. Plugs may be formed by selected area filling with gold, gold-based alloys, or other metal solders, or by plating processes with good filling characteristics. Solder-fill approaches can provide a via fill at relatively low cost. The plug metallization must be compatible

Figure 3-62. An SEM micrograph of a via hole after etching. The diameter of the via is approximately 100 pm. Note the gentle curvature of the top region of the via. (Figure courtesy of Dr. A. Colquhoun, Daimler-Benz Research Center, Ulm, Germany.)

Figure 3-63. An SEM micrograph of a series of through-wafer vias after removing the GaAs substrate. The top surface contact pads form a cap on the filled via metal. Via diameters are slightly larger than 100 pm. These vias are used to form a ground plane for 2 20 GHz device operation. (Figure courtesy of Dr. A. Colquhoun, Daimler-Benz Research Center, Ulm, Germany.)

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with plated or evaporated gold or gold alloys typically used for the ground plane formation. The back surface metal plate-up is many micrometers thick and uniform in coverage to ensure uniform electrical and thermal contact, low resistance, and to withstand the alloying and reaction that occurs during mounting of the finished die to the package. For this reason, plating methods (electro or electro-less) are optimal, although evaporated or sputtered metals may be used. The key issue during the metal deposition process is to keep the wafer temperature below the softening point of the adhesive material (the wafer is still mounted on a carrier). Plating may be carried out at temperatures below IOO”C, which is compatible with most adhesives, whereas evaporation may expose the wafer to very high surface temperatures, and sputtering methods can raise the temperature to well above 200°C. To circumvent the heating problem, evaporation or sputtering may be carried out in steps, although there is a penalty in throughput, the metal film qualities, and the cost associated with this type of process sequence. As in front surface metallizations, an adhesion promoter such as nickel or titanium may be used to improve the adherence of the back surface metal. When using electroplating processes it is difficult to produce a uniformly thick metal layer owing to the high resistivity of semi-insulating substrates (GaAs or InP). Current flow necessary to induce plating is inhibited in the substrate and therefore metal build-up generally occurs more rapidly in areas close to the contact(s). The use of thin adhesion-promoting layers can greatly reduce this problem by increasing the inplane conductivity. There is additional concern for interactions of gold with GaAs and InP with respect to long-term stability

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under severe operating conditions. Barrier metals such as platinum or palladium may be incorporated in the back surface metal layers to reduce the interaction of gold with the GaAs substrate. However, it has been shown that gold-based metallurgy is stable under high stress reliability testing (Irvin, 1982). Literature such as the book by Massalski (1986) should be consulted for further understanding of the relevant phase diagrams. At this point the wafer may be demounted from the supporting plate. The wafer is now quite fragile and easily damaged by mishandling. Several cleaning steps are required before the wafer may be passed to testing and evaluation. The adhesive materials and any undesired materials that were placed on the front surface as a protective coating must be removed. As before, no residues may be left on any surfaces as they will impede electrical contact to the back surface as well as the bonding pads on the front surface. The wafer may be transferred to a supporting carrier such as a NITTO tape handling system (Nitto). Here the wafer is gently pressed onto a polymer film which is supported by a tensioning ring carrier. The film and ring are capable of supporting the wafer mechanically during testing, die separation, and “pick and place”. As the polymeric film is plastic, separating the die is accommodated by expanding the film after the “streets and alleys” are cut or formed. 3.12.2 Die Separation

The wafer must now be electrically tested to identify the good die. After testing and marking (ink dot or X- Y die location map) the die must be separated for mounting in packages. Several methods exist for separating the die: scribe-and-cleave (diamond scribe or laser ablation using varied

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mechanical stresses to cleave the wafer along the scribe lines) and sawing (typically with diamond blades). The first approach is best suited to wafers with thin or no backside metallization, although if the metal layer is less than a few micrometers thick this tends not to be an insurmountable problem. The latter method is required for very thick backside metallizations because of the malleable nature of gold. With diamond or laser scribing, a groove is scored or ablated, respectively, in the “streets and alleys” between adjacent die. The groove acts to focus the mechanical stresses when the wafer is flexed on a suitable pad by a roller-type device or impacted by a cleaving bar. The use of a roller-type method is not well suited for devices using air bridge metallizations unless great care is exercised in the scribing and the mechanical handling: the air bridges are easily crushed. Also, detritus from the diamond scribe or laser ablation processes may be lodged around the air bridges leading to short circuits or other damage, unless the surface is encapsulated. A new apparatus for “scribe-and-cleave” processes has been introduced to compound semiconductor technology (Dynatex). This instrument uses an automated diamond scribe system coupled to a precision impact bar which rides below the backside of the wafer. Following the scribing process, the wafer is indexed in two dimensions while the impact bar is snapped up to the back surface at each scribe line. The sharp impact breaks or cleaves the wafer without excessive force, and has been found to be suitable for die separation when air bridge metallizations are used, although the cautions of contamination apply due to use of the diamond scribe. It is important to note that these processes perform best when photolithog-

raphy is carried out aligned to the preferred (110) cleavage directions in the compound semiconductors. Attempting to die separate along other crystal directions generally leads to failure and low yields. The second method of separation is diamond sawing (AT, Disco). In this approach, the wafer is placed on a precision indexing table and then moved beneath a rotating diamond wheel to cut a groove in the “streets” on the wafer surface. The blade width is typically 10 pm (0.0004 in) to 100 pm (0.004 in), creating a cut roughly 25% wider than the actual blade dimension. Diamond sawing is the ‘least clean’ method to separate the die. As noted above, the wafers should be encapsulated to protect the surfaces from damage and contamination. However, this may be in conflict with the testing and evaluation sequence. Use of the diamond blade, the coolant/lubricant fluid, and the generation of chips and other rubbish creates significant contamination of the wafer surface and necessitates careful cleaning procedures to remove the residual materials. After the “x” and “y” groove pattern is cut, the wafer may be mechanically stressed to cleave the substrate along the grooves, as noted above. The same constraints apply here to the use of the mechanical flexing approach for cleaving the wafer. In some cases the wafer may be sawn completely through the back surface metal. Great precision is demanded in the cutting process to avoid damage to the substrate carrier film layer. Vibration imparted into the wafer during sawing is of substantial detriment to GaAs and InP materials, as they are quite brittle. Edge damage, fractures, and undesired cleavage can readily occur during the sawing operation. One step remains before the die may be selected: physically separating the die. In the case of NITTOTMtape or similar mate-

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3.13 References

rials, this step is affected by stretching the polymer film. The spacing between the separated die is expanded to allow mechanical chip handling devices to remove the chip from the film, or to permit human handling, without damage to adjacent die. Exposure to chemicals or UV light may be used to reduce adhesion between the wafer and the carrier to facilitate the removal of the die from the film. “Pick-and-place’’ is a process of selecting the good die and locating them in a chip carrier or package cavity. This is done either manually or with automated systems. Vacuum pickups are employed to avoid the damage and yield losses associated with tweezers or mechanical clamping devices. In the case of expanded film carriers either method may be used. Solid wafer carriers (e.g., sapphire or quartz) do not lend themselves to effective die separation, and therefore require manual chip selection. In the latter case, further cleaning processes may be necessary to remove residues. The identity of the die and the location within the wafer are known from the testing sequence and may be maintained prior to assembly. Following completion of the pick-and-place operation, the die are subjected to additional visual inspection with the survivors passing to assembly and test.

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Index

accclcrated crucible rotation technique (ACRT) 27 acceptor concentrations 75 acceptor impurities 69 acceptor species diffusivity 100 acceptors - carbon, diffusion 96 - ohmic contacts 116 acids, etching I02 air bridge structure, liftoff processes 159 alloy semiconductors 4 aluminum I52 aluminum alloys I52 aluminum based interconnections 65 aluminum based metallization 101 arnorphization 77 amplifiers 73 anisotropic scgrcgation 29, 36 annealing 128 ff high-tcmpcraturc, doping proccsscs 72 ohmic contacts I I X argon containing compounds, source gas 156 arsine 80 ashing processes, etching 109 Au-Ga phase diagram 120 automated step-and-repeat lithography 65 ~

~

back-doping 77 bac kgat ing - doping processes 83 - isolation methods 91 f backside processing I59 ff band structure 69. I 13 bandgap 70 bandgap energy. ohmic contacts 1 18 bandgap engineering 50. 68 diffusion 9X barrel type PECVD reactor, dielectrics 141 barrier height 119 bases, etching 102 bcryllium diffusion 98 - doping processes 69 bilayer structures, Schottky barriers 127 binary systems, doping processes 68 blue-green semiconductor diode laser 59 BN bearing 20 ~

~

BN crucibles 23 Boltzmann constant 96. 121 boron, ion implantation range data 88 bode qualification process, doping 80 boundary regions, etching 102 bridge structures, liftoff processes 159 Bridgman technique 14,27 bromine chemistry, etching 108, 11 1 bubble formation, wet etching 105 bulk seeded physical vapor transport technique 28 bulk semiconductor, isolation methods 88 buried P-layers, doping processes 73, 77 Burton-Prim-Slichtcr (BPS) model 6 , 3 4 by-products, wet etching 105

C-HIGFETs 66 cadmium, doping processes 69 capacitor structures, dielectrics 137 carbon diffusion 96 doping processes 69, 72, 83 - ion implantation 88 carricr mobilities 69 cascade semiconductor laser 59 cast recrystallize anneal (CRA) 26 CdS 28 CdTe 7 f , 8 9 channel type resistors 146 channelling, doping processes 76 f charge domain travel, isolation methods 92 charge exchange process, isolation methods 92 charge transport, implantation methods 89 chemical polishing 41 chemical purification methods 8 chemical reactivity 12 chlorine chemistry 108, 1 I I , 156 chromium, doping processes 70 chromium doped GaAs 79 cleaning, backside processing 16 1 cleanroom facility classes 65 close tube diffusion process, doping 80 close tube techniqucs 7 Cochran analysis 34 complementary hcterostructure FET 66 compound semiconductor processing 1-13 conduction band, group 111-V semiconductors 49 ~

~

176

Index

conductivity 69 constitutional supercooling 6, 91,96 f - crystal growth 15 construction materials, etching techniques 1 I 1 contact resistance 115 contacts, melthoat, crystal growth 15 contaminations - dielectrics 141 - wafers Ill copper 153 Couette flow 27 critical condition, Hurle 34 critical resolved shear stress 12 crystal growth 13 ff - specific compounds 21 ff crystal pulling 18 crystal shape 30 crystal slip 135 current-voltage characteristics, MESFETs 53 cutting 41 Czochralski technique 5 damage, implantation methods 89 dead soft, liftoff processes 156 decomposition, wafers 1 1 I decomposition pressure, diffusion 96 deep level states, annealing 136 deep trenching, etching techniques 110 defects - annealing 131 doping processes 77, 8 I density, semiconductor materials 70 depletion regions - isolation methods 91 - ohmic contacts 114 - Schottky barriers 120 deposition methods, Schottky barriers 125 f detectors 65 device processing 61-1 73 device structures 45-60 diameter control 29 f diamond 30, 166 die separation 159 ff, I65 f dielectric constants, group Ill-V semiconductors 49 dielectric deposition, Schottky barriers I26 dielectrics 136 ff diffusion 94 ff - doping processes 70 diffusion controlled wet etching 104 diffusion methods, doping processes 80 f diffusivity 96 f diluents, etching 102 diodes 65 disilane, doping processes 80 dislocations 29, 39 f - doping processes 8 1 displacements, doping processes 77 distillation techniques 11 distribution coefficients 8 ~

donor concentrations 83 donors, ohmic contacts 116 dopant incorporation 6 f dopants 33 doping 68ff doping concentration, ohmic contacts double diffusion front 98 - doping processes 71, 82 dovetail 101 dry etching 106 f - isolation methods 85

114

Eckmanflow 27 ECR plasma CVD system 143 electrical isolation 84 electrical resistivity, metallization 150 electron beam writing system 154 electron bombardment 91 electron cyclotron resonance (ECR) 143 - etching 106, I 1 1 electron effective mass 49 electron mobility, semiconductor materials 70 electron wind, resistors 149 electronic properties 68 end-of-range damage, doping processes 76 energy band structure, ohmic contacts 113 energy gap, group 111-V semiconductors 49 enhancement mode, ohmic contacts 115 epitaxial growth 70 epitaxial methods 82 f etch masking 1 1 0 etching gas types 108 etching processes 100 ff evaporation - dielectric films 140 - ohmic contacts 117 - Schottky barriers 123 excess component distribution 8 exhaust scubbing 108 facet effect 29, 36 failure - hot spot 149 - compound semiconductor devices 65 Fermi energy - ohmic contacts 113 - Schottky barriers 120 Fermi level - dielectrics 136 - isolation methods 91 Fermi surface 69 Fick’s law 95 field effect transistors (FETs) 5 I f film resistor failure 149 finishing treatment 41 flammability, doping processes 8 1 fluorine, etching techniques 1 1 1 fluorine containing compounds 108

Index focused ion beam repair, resistors 148 four layer process, metallization 150 fracture, dielectrics I39 frequency dependent plasma effects, etching I 08 front-to-front IR aligner system 162 fundamental aspects. crystal growth 29 ff furnacc annealing 128 GaAs 7 f , 8 4 deep acceptor, carbon 153 doping processes 68 f, 79 furnace annealing I32 ion implantation range data 88 physical properties 70 thermal conductivity 160 GaAs substrate. crystallographic representations I02 GaP 7ff gas source MBE (GSMBE) 83 - diffusion 100 GaSb 9 gate lengths 65 gate metal deposition 125 gates 119 ff germanium 4 gold - compound semiconductor devices 65 metallization I52 gold alloys 65, 152 - liftoff processes 101, 156 - ohmic 119 - plug process 163 grain boundaries 29, 39 f graphite 12 grinding, backside processing 161 group ll-Vl compounds 10,26 f group 111-V semiconductors materials preparation 50 ff physical properties 49 growth rates, PECVD, dielectrics 141 growth techniques 14 -

-

-

-

~

-

historical background, compound semiconductor processing 4 hole concentrations, ion implantation 75 hole effective mass, group 111-V semiconductors 49 hole mobility 70 hopping conduction 89 horizontal Bridgman (HB) technique 50 horizontal crystallization techniques 5 , 50, 75 f host-lattice atoms displacement 87 hot spot, resistors 149 hot wall technology 19 Hurlc conditions 34 hydrogen, ion implantation range data 88 hydrogen incorporation, dielectrics I39 impurities 6, 70, 95,480 impurity isolation 90 impurity profile, double diffusion front 82 impurity redistribution - diffusion 94 doping processes 72 InAs 10.84 incubation period, etching initiation I04 InP 7 f - deep acceptor, copper 153 doping processes 68 f - LECgrowth 25 - physical properties 70 thermal conductivity I60 InSb 7 f - crystal pulling 22 interconnect metal deposition, Schottky barriers interconnections, metallization 150 interdiffision 154 interfaces, annealing 136 interlayer isolation 136 ff intermodulation effects, isolation methods 94 ion damage profile, implantation methods 89 ion implantation - doping processes 70 ff Schottky barriers 125 - isolation 86 f ion milling - etching 101 metallization 153 f ion penetration depth - doping processes 74 isolation methods 87 ionicity 12 iron, doping processes 70 isolation methods 84 ff - ion implantation, Schottky barriers 125 - thermal annealing 90 -

-

-

-

heat balance, solid-liquid interface 30 heat capacity, semiconductor materials 70 heat dissipation. resistors 148 heavy doping h hetero bipolar transistor HBT, diffusion 95 heterointerface SO heterostructure bipolar transistors (HBTs) 66 compound semiconductor devices 66 - diffusion 95. 98 heterostructure devices 83 heterostructure field effect transistor (HFET) 54, 66 heterostructures, group 111-V semiconductors SO HgTe 7 f high dose ion implantation 73 high electron mobility transistors 54 high pressure LEC technique 20 high temperature annealing 72 high volume manufacturing processes 8 1 -

177

-

-

junction field effect transistor (JFET) 66 Knudsen cell 50, 82

I26

178

Index

lasers 65 laser diodes 58 laser trimming, resistors 148 lateral migration, diffusion 95 lattice constants, semiconductor materials 70 lattice recovery, annealing 13 1 layers, doping processes 69 liftoff patterning, ohmic contacts I17 liftoff processes 150 ff, 156 f - gold 101 light emitting diode (LED) 48 lightly doped drain (LDD) 72 liquid encapsulated Czochralski (LEC) process 40 - group 111-V semiconductors 50 - low pressure 20 - pulling 13,20 f liquid phase epitaxy (LPE) 27 - doping processes 82 - group Ill-V semiconductors 50 low noise amplifiers, doping processes 73 low resistivity ohmic contacts, doping processes 73 low temperature buffer (LTB) 94 magnesium, diffusion 98 majority carriers 69 manganese, doping processes 69 manufacturing 65 masking, etch processing 110 masking layer, backside processing 162 masslcharge ratio, ion implantation 74 material properties 48 ff MBE see: molecular beam epitaxy melt growth, technical constraints I I ff melting points 9 ff - scmiconductor materials 70 meniscus contact, melticrystal 32 mercury cadmium telluride (MCT) 26 mesa etching, isolation methods 85 f metal-organic chemical vapor deposition (MOCVD) compound semiconductor devices 66 - diffusion 100 doping processes 82 metal-organic vapor phase epitaxy (MOVPE) 27 - doping processes 82 - group Ill-V semiconductors 50 metal-semiconductor field effect transistor (MESFET) 52,65 compound semiconductor devices 65 f doping processes 71 - group 111-V semiconductors 50 metallization 150 ff - ohmic 116 microcracks, dielectrics 139 migration, lateral 95 mitigation 108 - isolation methods 84 f mobilities, group Ill-V semiconductors 49 mobility gap, ohmic contacts 114 -

-

-

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molecular beam epitaxy (MBE) 27 compound semiconductor devices 66 - doping processes 82 - group 111-V semiconductors 50 mounting, backside processing 161 MOVPE see: metal-organic vapor phase epitaxy multilayer metal-metalloid structures 127 multilayer metallization 150 - isolation methods 86 mushroom structure, FETs 56 mushroom-gate, Schottky barriers I27 -

n-type compound semiconductors 68 neutron damage, isolation methods 91 nickel, doping processes 70 nitrogen gas, metallization 156 ohmic contacts I12 ff - doping processes 73 - fabrication 116 - isolation methods 91 ohmic metal deposition, Schottky barriers open tube, diffusion method 80 operating conditions, GaAs FET 54 operating tolerances 65 optical properties 68 overpressures, annealing 132 oxygen doped GaAs 79,88

I25

p-type semiconductors 68 palladium layer, metallization 153 passivation - annealing methods 130 - Schottky barriers 126 patterned masks, implantation methods 89 patterning, Schottky barriers 126 phosphide containing materials, annealing I32 phosphine, doping processes 80 photolithography - metallization 155 Schottky barriers 125 photoresist layers 110 - implantation methods 89 pick-and-place, die separation 167 piezoelectric effects, dielectrics 139, 147 pinning - Fermi levels 136 - Schottky barriers 122 Piper-Polich technique 28 planarization, metallization 155 plasma enhanced CVD, dielectrics 140 plasma etching 106 f plasma sputtering 100 plate type PECVD reactor, dielectrics 141 platinum layer, metallization 153 plug process, backside processing 163 point defect concentrations, annealing 13 I -

Index polishing 41 backside processing I6 1 polyimide, dielectrics 144 polymerization. etching 11 I post-and-runner structure, metallization 150 power dissipation, metallization I 50 pressure balancing 19 pressures, PECVD. dielectrics 140 process sequence. FET fabrication 67 protons, implantation methods 89 pulling 5, 80 purification, compound semiconductor processing 4 , 6 9 ff purity, ion implantation 74

semi-insulating characteristics, doping processes semiconductor laser diodes 58 ff shallow p n junctions, etching 109 sidegating - doping processes 83 isolation methods 91 sigma structure, FETs 56 silane, doping processes 80 silicon doping processes 69 ion implantation 88 physical properties 70 thermal conductivity 160 silicon production, doping processes 80 single zone freeze 5 singular planes 36 site selection doping processes 8 1 impurities activation 90 slice preparation 40 solar cells 65 solid-liquid interfaces, crystal growth 15 solute distribution 29, 33 source gas types, metallization 156 spiking diffusion 95 ohmic contacts 117 sputtering 106, 110 - dielectrics 140 etching 100 - metallization 155 ohmic contacts I17 - Schottky barriers 123 statistical process control (SPC) 65 stirring 34 etching techniques 102 straggle, doping processes 75 ff streets and alleys, die separation 166 stress, annealing 135 submicrometer gate lengths 65 substrate bias, isolation methods 92 sulfur, doping processes 69 supercooling 6, 77, 91, 96 f surface damage 4 1 - implantation methods 89 surface defects, annealing 130 surface depletion, resistors 147 syringe pulling I9

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quaternary systems, doping processes quench anneal 27

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~

~

~

~

68

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radial flow rotating susceptor reactor 142 rapid thermal annealing (RTA) I28 - diffusion 96 - doping processes 75 ohmic contacts I17 Rayleigh number 25 RC time constants, metallization 150 reaction products, etching 101 reaction-rate-limited wet etching I04 reactive ion etching (RIE) 106 - backside processing 162 reactors, dielectrics 141 recombination centers, implantation methods 89 refractory metals metallization 154 Schottky barriers 123 reproducibility compound semiconductor devices 65. I I2 wet etching 10.5 resistance, ohmic contacts 1 I9 resistors, compound semiconductor materials 145 ff Richardson constant 121 ~

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SAINT (self-aligned implantation for n+-layer technology) I24 SARGIC (self-aligned refractory gate integrated circuit process) I24 Schottky barriers I I9 ff isolation methods 91 ohmic contacts 112 self-aligned processes I24 Schottky diode 120 scibe-and-cleave, die separation 166 segregation 6, 36 segregation coefficients. diffusion 96 selective tungsten CVD process, metallization I50 self-aligned processes, Schottky barriers 124 SEMI I/J 101 SEMIUS I01 ~

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T-gate structures metallization 154 - Schottky barriers 127 T-structure, FETs 56 Teal-Little crystal pulling 18 tellurium - doping processes 69 impurities 9 - precipitates 28 temperature distribution 29 f ~

~

179 70

180

Index

temperature gradient, crystal growth 15 temperature gradient zone melting (TGZM) 25, 36 temperature range, wet etching 105 ternary systems, doping processes 68 thermal annealing, isolation processes 90 thermal budget - furnacehapid thermal annealing 13 1 - ohmic contacts 117 thermal conductivity - backside processing 160 - group 111-V semiconductors 49 - semiconductor materials 70 thermal effects, resistors 147 thermal expansion coefficients, semiconductor materials 70 thermal shock, annealing 134 thin film transistors (TFTs) 148 through-wafer via, backside processing 164 Ti-W layer, metallization 153 time-temperature cycles, annealing 129 tin, doping processes 69 topology, ohmic contacts I17 toxicity production 80 transistor action 4 transit time, heterojunction bipolar transistors 58 transition metals, doping processes 69 traveling heater method (THM) 1 I , 88 tunneling 89 twinning 16,29, 36 two layer process, metallization I50 undercutting, wet etching 106 unified defect model, Schottky barriers

122

V-groove option 102 vacuum processing 13 valence band, group Ill-V semiconductors 49 vapor crystal growth 14

vapor phase epitaxy (VPE) 82 vapor pressure 12,29, 80 vapor sputtering, etching I00 vertical crystal growth 13, 16 f vertical gradient freeze (VGS) 7 , 7 8 - InAsJGaAs 24 vertical growth freeze, wafering 40 vertical pulling 5 via etching, Schottky barriers I26 via plug process I5 1 vitreous silica, boat meterials I2 volatility 9 - group 11-IV compounds 26 wafer decompositiodcontamination, etching wafer thinning, backside processing 16 I wafer-to-wafer reproducibility 76 wafering 40 warpage, annealing 134 weak link, liftoff processes 156 wedge 101 weighing anomaly 33 wet etching 102 f - isolation methods 85 writing system, metallization I54 zinc - diffusion 71, 98 - doping processes 69 f - impurities 9 zinc blende lattice 3 1 ZnS 28 ZnSe 28 ZnxCd,,Te 27 zone leveling 5 zone melting 5 zone refining 5 f

II1

Compound Semiconductor Devices: Structures and Processing

Compound Semiconductor Devices: Structures and Processing

Silicon Devices: Structures and Processing

Nanoscaled Semiconductor-On-Insulator Structures and Devices

Semiconductor Physics And Devices

Rapid Thermal Processing for Future Semiconductor Devices

Semiconductor Physics And Devices

Semiconductor Physics And Devices

Rapid Thermal Processing for Future Semiconductor Devices

Physics of Semiconductor Devices

Semiconductor Nanostructures for Optoelectronic Devices: Processing, Characterization and Applications

Physics of Semiconductor Devices

Physics of Semiconductor Devices

Power semiconductor devices

Physics of Semiconductor Devices

Physics of Semiconductor Devices

Semiconductor optoelectronic devices

Physics of Semiconductor Devices

Physics of Semiconductor Devices

Physics of Semiconductor Devices

The Representation and Processing of Compound Nouns

Low Dimensional Semiconductor Structures

Low-dimensional semiconductor structures

Power Semiconductor Devices (General Engineering)

The Representation and Processing of Compound Nouns

Fundamentals of Power Semiconductor Devices

Physical limitations of semiconductor devices

Physical Limitations of Semiconductor Devices

Fundamentals of Power Semiconductor Devices

Fundamentals of power semiconductor devices

Advanced Theory of Semiconductor Devices

Compound Semiconductor Devices: Structures and Processing