Silicon Devices: Structures and Processing

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Silicon Devices Structures and Processing Edited by Kenneth A. Jackson

@ WILEY-VCH

Related Reading: K. A. Jackson (Ed.)

Compound Semiconductor Devices Structures and Processing ISBN 3-527-29596-8

K. A. Jackson (Ed.)

Processing of Semiconductors Volume 16 of Materials Science and Technology ISBN 3-527-26829-4

W Schroter (Ed.)

Electronic Structure and Properties of Semiconductors Volume 4 of Materials Science and Technology ISBN 3-527-26817-0

Silicon Devices Structures and Processing Edited by Kenneth A. Jackson

@ WILEY-VCH Weinheim . New York * Chichester . Brisbane . Singapore . Toronto

Editor: Prof. K. A . Jackson The University of Arizona Arizona Materials Laboratory 4715 E. Fort Lowell Road Tucson, A 2 85712, USA

This book was carefully produced. Nevertheless, authors, editor and publisher do not warrant the information contained therein to be free of errors. Readers are advised to keep in mind that statements, data, illustrations, procedural details or other items may inadvertently be inaccurate.

Library of Congress Card No.: applied for British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library Die Deutsche Bibliothek - CIP-Einheitsaufnahme Silicon devices : structures and processing / ed. by Kenneth A. Jackson. - Weinheim ; New York ; Chichester ; Brisbane ; Singapore ; Toronto : Wiley-VCH, 1998 ISBN 3-527-29595-X 0 WILEY-VCH Verlag GmbH, D-69469 Weinheim (Federal Republic of Germany), 1998

Printed on acid-free and chlorine-free (TCF) paper All rights reserved (including those of translation into other languages). No part of this book may be reproduced in any form - by photoprinting, microfilm, or any other means - nor transmitted or translated into a machine language without written permission from the publishers. Registered names, trademarks, etc. used in this book, even when not specifically marked as such, are not to be considered unprotected by law. Composition, Printing and Bookbinding: Konrad Triltsch. Druck- und Verlagsanstalt GmbH, D-97016 Wurzburg Indexing: Borkowski & Borkowski, Schauernheim Printed in the Federal Republic of Germany

Preface

This volume covers the basic processes involved in the manufacture of silicon devices, starting with purification and crystal growth, includes a description of various device structures, and concludes with a description of the processes involved in device fabrication. The chapters are drawn from the book “Semiconductor Processing” which is Volume 16 of the VCH series on Materials Science and Technology. It may be surprising to some how little the descriptions of the processing depends on the fundamental physics of semiconductors. The properties of the silicon determine what is to be done in the manufacturing process, but not how it is to be done. The processing depends critically on the properties of the wide variety of materials which are used, and the processing in a semiconductor fabrication facility, a “fab”, is a complex multi-stage sequence. The cost of a new fab, which is now at the incredible level of about one billion US dollars, is a measure complexity of the processing and of the sophistication of the equipment used. Semiconductor processing often makes use of materials at a limit of their capability. The silicon crystals used as starting material are as pure and as perfect as single crystals can be made, deposited layers are uniform and defect free, conductor cross-sections are limited by current densities, insulating layers must be uniform in thickness and free of pinholes. Ultra-purity is required not only of the silicon, but also of all the processing chemicals such as dopants, etchants, and cleaning materials, including the water. Even the air in a semiconductor fab is special: a whole technology exists to build clean rooms which are designed to limit the number and size of airborne particulates. All of the processing materials and processes have been and are continually scrutinized in minute detail to improve their efficiency and performance, and to reduce costs. This volume does not deal with the semiconductor design process, although design is clearly the essential first step in the production of a device. The design of new processors, memory chips and ASICs (Application Specific Integrated Circuits) is now implemented with extensive use of computer aided design. The electrical circuits are designed using computers and the designs are tested by computer simulation. The layout of the circuit components based on the circuit design is done by a computer which prepares the input for an electron beam writer which writes a mask set. The mask set is delivered to the fab where the masks are used successively to pattern the distribution of various dopants in the semiconductor, to pattern the dielectric layers and the conductor metallizations. Many circuit designers have never been in a fab, and the people who work in fabs need to know little about the design process. The other major aspect of semiconductor manufacture which is not dealt with in this volume is testing. Simple circuits are sample tested, but expensive chips such as microprocessors are subject to extensive electrical and performance testing. Testing all of the transistors on a chip which has ten million transistors and only a few hundred input/output pins requires a complex test procedure. The test stations are expensive and the tests are time consuming, so that testing is a major cost factor in semiconductor production.

This volume deals with the basic manufacturing processes for silicon. The fabrication process starts with the purification of the silicon followed by the growth of single crystals. The crystals are sliced into wafers which are then polished, so that silicon arrives at the fab as polished wafers. Each wafer diameter requires its own suite of processing equipment, and at the present time wafers up to twelve inches in diameter are being processed. Crystal growth and wafering processes for silicon are discussed by J. G. Wilkes in first chapter. Device structures including potential-effect devices, field-effect devices, quantum-effect devices, microwave devices and photodetectors are described in the second chapter by C.-Y Chang and S. M. Sze. In the concluding chapter, D.-L. Kwong discusses device processing, including gettering, device isolation, dielectrics, junction formation, metallization, and cluster tool technology. The processing of a wafer typically involves hundreds of separate steps, but several hundred chips can be made from a single wafer. There is a continuing trend to use larger wafers and finer features on the wafers in order to get more chips from each wafer. There are several important aspects of the fabrication of semiconductors which are beyond the scope of this volume. These include photolithography, which is used for the patterning of the dopants to make the devices, as well as the dielectrics and metallization. The feature size on wafers is now at the limit of optical resolution. The very sophisticated chemistry is needed to design the photosensitive materials which are used is beyond the scope of this volume. Similarly, the ion implantation process which is used for the selective introduction of dopants into the semiconductor is not discussed in detail, nor is the packaging technology used to protect the chips and to connect them to the outside world. Silicon processing technology is very advanced in scale of integration and so, if a semiconductor device can be made with silicon, it will be. Silicon is used almost exclusively for logic and memory devices, and although it is used for photodetectors and solar cells, it cannot be used to make devices which emit light, such as light emitting diodes (LED’S)or semiconductor lasers. Semiconductor light source devices are the domain of compound semiconductors, such as GaAs, which are discussed in a companion volume. Although there are many aspects of the processing which are common to both silicon and compound semiconductors, many of the devices are different, and the basic chemistry of the materials introduces significant differences in processing. I would like to thank the authors who have taken time from their very busy schedules to prepare their chapters. They are experts in processing technology because they are involved with it on a daily basis, and it has been difficult for many of them to find the time to write. But the result is a valuable and timely description of the state-of-the art for silicon processing. Kenneth A. Jackson Tucson, A Z August, 1998

List of Contributors

Prof. Chun-Yen Chang National Chaio Tung University National Nano Device Laboratory 1001-1Ta Hsueh Road Hsinchu, Taiwan 30050 R.O.C.

Prof. Simon M. Sze National Chiao Tung University Microelectronics and Information Systems Research Center 1001Ta Hsueh Road Hsinchu, Taiwan 30050 R.O.C.

Prof. Kenneth A. Jackson University of Arizona Arizona Materials Laboratory 4715 East Lowell Road Tucson, AZ 85712 U.S.A.

Prof. John G. Wilkes t Formerly with Mullard Ltd., Southampton U. K.

Dr. Dim-Lee Kwong The University of Texas at Austin Microelectronics Research Center Department of Electrical and Computer Engineering Austin, TX 78712 U.S.A.

Contents

1 Silicon Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J. G. Wilkes t

1

2 Silicon Device Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.-E: Chang. S . M . Sze

63

3 Silicon Device Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D..L . Kwong

113

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

195

1 Silicon Processing

.

John G Wilkes t Formerly with Philips Components Ltd., Southampton. U.K.

List of 1.1 1.2 1.3 1.3.1 1.3.2 1.3.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.6 1.6.1 1.6.2 1.7 1.7.1 1.7.2 1.7.3 1.8 1.8.1 1.8.2 1.9 1.10

Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metallurgical-Grade Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Semiconductor Grade Polycrystal Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Chlorosilane Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Silane Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Polycrystal Silicon Market ..................................... Single Crystal Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Float-Zoned Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Neutron Transmutation Doped Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Carbon and Nitrogen in Float-Zoned Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . Periodic Crystal Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Czochralski Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dislocation-Free Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Constitutional Supercooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Incorporation of Carbon and Oxygen . . . . . . . . . . . . . . . . . . . . . . . . . . . . Magnetic Czochralski Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Commercial Scaling of Czochralski Silicon . . . . . . . . . . . . . . . . . . . . . . . . Slice Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Damage in Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Polishing and Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxygen in Czochralski Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Behavior of Oxygen in Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Precipitation of Oxygen in Silicon ............................... Thermal Donors and Enhanced Diffusion ............................. Crystal Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extrinsic Gettering in Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intrinsic Gettering in Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 5 7 11 11 14 16 17 17 19 20 22 25 26 28 30 33 34 36 36 43 44 44 45 49 51 51 53 59 60

2


List of Symbols and Abbreviations Fourier series coefficient lattice constant (for Si, a, = 5.42 A) constant slice bow depth concentration crystal habit concentration in liquid concentration (of oxygen in oxide) in particle concentration in solid equilibrium solid solubility concentration initial concentration diameter diffusion coefficient activation energy for the formation of a particle of critical radius cut-off frequency mean value o f f , volume free energy change of a precipitate magnitudes of the forces generated at the edge during sawing fraction of melt solidified height enthalpy of reaction detector signal interstitial collector-base current Boltzmann constant effective distribution coefficient equilibrium distribution coefficient number of particles number of particles of critical radius fast neutron, thermal neutron number of oxygen atoms in axial bonds number of oxygen atoms in other bonds bound interstitial oxygen concentration Prandtl number radius radius of the total volume from which oxygen condenses into a precipitate critical radius radius of a final precipitate particle, small compared with R time absolute temperature melting point (Si: 1412 "C) half life of radioactive species thickness of a silicon slice

List of Symbols and Abbreviations

3

temperature difference velocity vacancy velocity of growth intrinsic X-ray signal half width measured X-ray signal half width rocking curve broadening

Y 6 E

0 QR

AC ACR ASTM BP CMOS CVD

cz

DC DCS DI DRAM EBE EG FZ HF HI-LO LPCVD MG-Si MOS

alpha particle absorption coefficient for polarized infrared light parallel to the stress axis absorption coefficient for polarized infrared light perpendicular to the stress axis gamma particle boundary layer thickness strain test sample angle Bragg angle, X-ray reflection Fourier coefficient (with dimensions of inverse length) constant kinematic viscosity surface free energy relaxation time relaxation time constants angular velocity alternating current advanced carbothermic reduction American Society for Testing Materials boiling point complementary, using both n- and p-type, metal-oxide-silicon device chemical vapor deposition Czochralski material direct current dichlorosilane deionized dynamic random access memory extended bulk epitaxy enhanced gettering float zoned (material) high frequency high temperature-low temperature (heat treatment) low pressure chemical vapor deposition metallurgical-grade silicon metal-oxide-silicon (device) (n-MOS, p-MOS refer to the dopant type structure employed)

4

NFZ NTD NTP PPba PPma PPt psi RF r Pm SANS SIMS SRAM TCS TD TIR UHF ULSI

uv

VLSI WCA


nitrogen-doped float zone (material) neutron transmutation doping normal temperature and pressure atomic parts per billion (lo9) atomic parts per million parts per trillion (10'') pounds per square inch radio frequency rotations per minute small angle neutron scattering secondary ion mass spectrometry static random access memory trichlorosilane thermal donor total integrated reading (of bow or warp) ultrahigh frequency ultra large scale integration ultraviolet very large scale integration water classified alumina

1.1 Introduction

1.1 Introduction Silicon today is a commodity, its price subject to all the forces of supply and demand in an intensely competitive market, and this has driven the development of high yield processes for the tight tolerance materials demanded. While discrete and power device manufacture calls for some float zoned, and neutron transmutation doped (NTD) silicon; the worldwide compass of integrated circuit manufacture consumes more than 75% of all the semiconductor silicon produced. The development of the product market distribution is shown in Fig. 1-1. Supply of this material is dominated by Czochralski crystal growth, the operational scale of which has increased from charges weighing a few hundred grams, around 1962, to the current units of 60 kilogram and more. The evolution of the semiconductor industry as we now know it began in the 1950s, when many of the then large electrical companies became involved in the chemistry and metallurgy of Germanium. Their starting point was GeO,, the dioxide, which had to be reduced to metal powder, melted, zone refined, and crystals grown, before the machining operations which led to discrete devices. Germanium being an expensive rare element, the ma60 New techn 0.

40n

/

Discrete anq p o r e r O

80

.

'

I

82

'

f

'

84

86

88

,

, 1990

Year

Figure 1-1. Development of the semiconductor product market.

5

chining itself generated valuable byproduct sludges which had to be recovered. The extreme purity necessary led into problems in chemical and physical analysis, materials of containment, and in general chemical engineering. In retrospect, very few of these electrical companies possessed either the resources or the experience needed for such work; so when, only shortly afterwards, silicon was introduced, almost all of them took the opportunity to withdraw from the chemical end of the business. Silicon is one of the most abundant elements, and so the sludges are of no economic importance. Henceforth their starting point became the ultrapure polycrystalline silicon from which they made their own single crystal. With time, the number of companies doing even this has steadily declined, until today few of the electronics manufacturers have any involvement in bulk material processing. Indeed most purchase polished slices, cleaned and packaged, furnace ready, for fabrication lines. A number of the device makers still carry out epitaxy and, to that extent alone, retain a residual materials activity. In modern very large scale integration (VLSI) circuits, lithographic feature sizes have been reduced to 1 pn or less, and use multilevel interconnects to enable the production of high complexity devices of steadily rising chip area. Consequently, as the number of chips per wafer decreases, so there has been an accompanying call for ever larger wafer diameter - to reduce perimeter wastage, and to improve fabrication line yield and throughput, as shown in Fig. 1-2 - hence the continuous need to scale up crystal size, this demanding extremely heavy investment. This scaling has not been at the expense of quality - in fact quite the reverse. As more has been learnt about the relation-

6


200 175 150

- 125 $100

E

.E 0

15

50 25

0

1960

1970

1980

1990

Year

Figure 1-2. The year of introduction of the largest silicon wafers in production. (Note: This trend continues. A very small number of companies, mainly Far East, are now looking at 250 mm diameter possibilitics.)

ship between materials properties and the device parameters, so the demand for better performance from the silicon has grown. If one compares a typical purchasing specification of even the mid 1970s, with that in force today for a similar application endproduct, the increase in the number of parameters specified, and the narrowing of virtually all tolerances, is marked. Contributory factors leading to this position include: Fine geometry lithography, needing slices of a flatness not even contemplated ten years ago; cassette, and now robotic, handling techniques, which call for close machining tolerances, and edge rounded slices, to prevent chipping and particles accumulating in ultraclean fabrication equipment. Research into the behavior of oxygen and carbon precipitation in bulk silicon under device furnacing conditions has led to the introduction of new specification parameters, new crystal processing methods, and to the concept of “crystal engineering”. Controlled oxide precipitation in slices is carried out, prior

to their use in fabrication lines, to provide sites for the intrinsic gettering of unwanted fast diffusing electrically deleterious impurities, away from the surface layer where the MOS devices are made. Residual mechanical damage sites after the crystal machining provide similar extrinsic gettering sites. For many applications in “crystal engineering” today, combinations of controlled mechanical and oxide precipitate gettering are used together to achieve optimum performance from the silicon, to match the particular device requirements in MOS, CMOS, and bipolar configurations. To achieve this matching it is necessary to examine the total thermal inventory of the multistage fabrication process, in order to select the most appropriate structure. While the early 1990s have seen a general slowdown in world economies, the surge in the personal computer market, linked to the major developments in microprocessor chips, has meant that device production revenues have continued to grow, by 1993, to $60-70 billion (lo9),and are projected to be in the range $150-200 billion by the year 2000. These microprocessor chips are of ever increasing size and complexity; for example the Intel Pentium with around 3 million transistors, running at a speed of 100 million instructions per second, is about 0.5 sq. in. (-3 cm’) in area. In memory chips the 16 Mbit DRAM is being followed by the 256 Mbit version, and since each DRAM cell needs one transistor, even with shrinking all dimensions the chip size is increasing. Charge coupled devices for displays also require large-area chips. Such ultra large scale integration (ULSI) applications today are leading the demand for Czochralski silicon wafers with diameters of 200 mm (S”), and inevitably still bigger will follow. For these diameters, the current pullers have to be scaled up

1.2 Metallurgical-Grade Silicon

further towards 100- 150 kg machines. The larger thermal masses will impose difficulties in the control and uniformity of the dopant, oxygen, and crystal defect concentrations. Finer dimension lithography needs ultra flat wafers, and particulate contamination levels of less than 10 particles greater than 0.1 pm per wafer are expected. Leakage control in large DRAMS requires metallic surface contamination to below lo9 atoms/cm. These are severe challenges at the final wafer cleaning and packaging stages. Overall, larger slices, made to extremely close tolerances by rigidly defined processing, from silicon that conforms to tightly specified criteria with respect to uniformity, dopants, impurities, point defect precipitates, clean surface characteristics, and metrology, are required of the materials vendors. Yet as the market competition is fierce, all of this is wanted at the minimum possible price - a constraint that reflects back through every step in silicon material manufacture. Thus right back in the raw material sector, over the past twenty years the supply of silicon has steadily become concentrated into fewer large specialist merchant vendors, and usually these operate as a division within some much bigger general chemical corporation. Many of the same companies are now involved in the present ruthless shakeout of the parallel gallium arsenide material market, as this sector, in the 1990s, is becoming commercially more significant. Thus the highly competitive commodity environment, which can never be ignored, is the constant background influence against which this chapter is set.

1.2 Metallurgical-Grade Silicon The source of the raw silicon used for semiconductor purposes is metallurgical-

7

grade silicon, manufactured by the carbothermic reduction of silica in an electric arc furnace. Silica, occurring naturally as quartzite, in vein quartz, and in sandstone, and as unconsolidated sands and gravels, is a common mineral with worldwide distribution. Silicon, after oxygen, is the second most abundant element, but does not occur naturally in its elemental form. Silica, either free as in quartz or in the many forms of silicate igneous rocks, constitutes about a quarter of the earth’s crust. However, the silicon metal producers demand an ore purity of better than 99% SiO,, and also place tight restrictions on the allowable concentrations of various impurities present - in particular arsenic, phosphorus, and sulfur - so that often only a small fraction of an ore deposit meets their purity specification. Geologically washed out gravel from river bed deposits, and similarly leached out quartz sands, are a source of very high purity silica. Vast new deposits, yielding quartzite ore of the highest purity available today, have been discovered in Arkansas, U.S.A., from which monocrystals weighing several tons apiece have been displayed in exhibitions worldwide. In the traditional electric arc furnace process, which has been used for most of this century, chunky quartzite is reacted with carbon, as the reductant, in the forms of coal, coke, or charcoal, which can be a source of at least an order of magnitude greater impurity levels than present in the silica. The overall reaction appears simple:

SiO,

+ 2C

+

Si + 2CO

(11

However, as discussed by Healy (1970),the actual reaction sequence in the different temperature zones of the furnace is far more complex than this, as set out in the schematic diagram of Fig. 1-3.

8


Figure 1-3. Schematic diagram of the submerged-electrode electric arc furnace for the production of metallurgical grade silicon.

Towards the bottom of the furnace, in the region of the arc between the electrodes where the temperature can exceed 2000 "C, silicon is produced by the reaction S i c + SiO,

+

Si + SiO + CO

(2)

Above this, at a somewhat lower temperature, around 1700- 1500 "C, the rising byproduct gases react to form the intermediate product silicon carbide by SiO + 2 C

--f

S i c + CO

(3)

Nearer to the top, where the temperature falls below 1500"C, as is expected thermodynamically, the reverse reaction predominates: SiO

+ CO

--f

SiO,

+C

(4)

The input materials are fed into the top of the furnace, while liquid silicon is periodically tapped from the bottom and cast into ingots. If this casting is carried out directionally, under the conditions referred to

as normal freezing, impurity redistribution can be used to effect some purification, following the well equation by Pfann (1952, 1958):

c, = kerf C,(1 - g p f f - 1 ) For the arc process to run properly, it is essential to maintain porosity throughout the charge to allow uniform SiO and C O gas flow, and to permit the escape of CO, some SiO, and H,O from the top. To assist this wood chips may be included in the feedstock, and the silica must be of a form which does not readily crumble during initial heating in the upper part of the furnace, which could lead to premature fusion and crusting over, with the risk of a dangerous pressure buildup within the charge. Clearly the carbothermic reduction of silica is not a trivial process. Crossman and Baker (1977) have given a very interesting comparison of the impurities present in typical quartzite and the carbon used, related to the spectrographic analysis of more than 2000 tons of the met-

1.2 Metallurgical-Grade Silicon

allurgical-grade silicon produced. Their data, collected into Table 1-1, indicated total impurity levels in the quartzite of around 750ppma; in the carbon 8000ppma, and in the resulting metallurgical-grade silicon (MG-Si) 4000-4500 ppma. Within this analysis the two predominant impurities are seen to be aluminum and iron, largely originating from the carbon, and taken together accounting for over 80% of that in the silicon product. Since these results referred to MG-Si to be used for the production of semiconductor grade polycrystal silicon, the importance of the purity of the carbon source is underlined. Recent developments have focused on improved and cleaner processes, better quality carbon, and efforts to develop quartz sands as an alternative low cost and high purity source. Maintaining charge porosity constitutes the most serious restriction in the operation of the submerged arc furnace, and much attention has been focused on how to meet, or circumvent this problem. In work aimed to reduce drastically the impurities in arc furnace silicon, Dosaj et al. (1978) working at Hemlock

Table 1-1. Impurities in silica, carbon, and metallurgical-grade silicon. Impurity

A1 B Cr Fe P Others Mn Ni Ti V

‘ Weighted;

Quartzite (PPW

Carbon” (PPma)

MG-silicon (PPma)

620

5500

14 5 15 10 10

40 14 1700 140 600

1570f580 44f 13 137f 75 2070 510 28+ 6 -

70+ 47f 163f loo*

20 28 34 47

avcrage value f standard deviation.

9

Semiconductor Corp. U.S.A. reported using a high purity silica source together with carbon black powder, pelletized with pure sucrose binder, to obtain MG-Si at 99.99% purity. Although the boron content of the material was relatively low, this particular element tends to be more persistent through the later stages of semiconductor silicon manufacture, and therefore recently there has been interest in exploiting the lower boron content of carbon obtained from petrocoke. The pelletization of upgraded quartz sands can provide very pure silica in a suitable form. This material then has to be agglomerated to lumps, either separately or mixed with carbon powder. This approach has been studied by several groups, including Elkem A/S, Norway, the largest European silicon metal producer, but until now it has only been taken to a development stage. The Siemens advanced carbothermic reduction (ACR) process has recently been described by Aulich et al. (1985), in which high purity pelletized quartz sand is reduced by carbon granules, prepared from carbon black briquettes, which had been leached with hot HC1 to a purity comparable to that of the silica. Since in an arc furnace about 10% of the carbon comes from the electrode, the effective carbon impurity level was somewhat higher. Nevertheless a substantial overall impurity reduction was achieved. A more radical approach to overcoming the porosity problem has been the application of DC plasma-arc techniques to the production of ferrosilicon alloys and silicon metal. The most important feature of the plasma-arc furnace here is that it can process ore fines directly, without prior briquetting or pelletization. The potential of this route is supported by the extremely efficient plasma purification of normal MG-Si, by factors of up to 100000, re-

10


ported by Armouroux et al. (1986). Developed up to the stage of full scale production of ferrochromium ore, in South Africa, the plasma-arc technology is now being assessed in other countries. The great evolution of heat from the oxidation of aluminum forms the basis of the Thermit process for the reduction of refractory oxides, such as Cr,O,, and MnO,. By the application of this technique to silicon, an entirely new manufacturing route has resulted from the extensive work by Dietl and Holm [see, e.g., Dietl et al. (1981) and Dietl and Holm (1986)l at Wacker Heliotronic, Germany, on the aluminothermic reduction of quartz sand in a liquid flux system (CaO-SiO,) at a temperature of 1600- 1700"C: 3Si0,

+ 4A1 + 3Si + 2A1,0,

(5)

The flux serves simultaneously as a solvent for the byproduct aluminum oxide, and as a liquid-liquid extraction medium. As the silicon is released it is immiscible in the flux and so separates. Since the silicon is of lower density, if floats as the upper layer and at intervals can be poured off into a mold, where controlled normal freezing further separates low segregation coefficient impurities. The silicon made by this novel semicontinuous process is of relatively high purity compared with normal MG-Si. It is characterized by low boron and carbon levels, and after subsequent grinding, acid leaching, and liquid-gas extraction, provides a material that is suitable for solar-cell applications. During the past decade, the most important economic trend in silicon metal production has been abandonment of the earlier small scale multi-unit plants, having limited productivity, for the use of very much larger electric arc furnaces, commonly dedicated to a particular product, which operate with lower unit costs. A

modern commercial submerged-electrode arc furnace built in a three phase, three electrode configuration, each of these t .25 m in diameter, and driven from a 24 M W power source, can produce 8000-10000 t/a metallurgical-grade Si at an energy consumption of 12-14 kWh/kg. The demand for metallurgical-grade silicon is dominated by the iron-steel and aluminum alloy industries, which require 98% purity metal. A somewhat higher quality, of 99% + purity, is required for conversion into chlorosilanes, the key intermediates in the synthesis of organo-silicon compounds for the silicone industry, leading to products such as oils, resins, lubricants, and water repellants. Although the semiconductor industry wants the highest purity it can obtain, the amount needed still represents only a very small fraction of the world's output. For example the global production of MG-Si in 1986 was just under 600000 t, from which the organo-silicones consumed about 20%. By contrast, in that same year the production of semiconductor-grade, ultrahigh purity, polysilicon reached about 6000 t - representing a consumption of less than 2% of total MG-Si output, and, significantly, only a fraction of the capability of a single-arc furnace. Western Europe accounts for over half the world capacity, led by Elkem, Norway, and Pechiney, France at 100000, and 75000 tons per annum, respectively. Thus, in summary, while the manufacturers of semiconductor silicon can have only limited influence over the quality of metallurgical silicon, there have been improvements in this product. While these have probably been driven more by the much larger organo-silicon purity needs, some of the companies in the MG-Si industry have established strong links in the semiconductor market, and their contributions are of greater significance when set

11

1.3 Semiconductor Grade Polycrystal Silicon

1.3.1 The Chlorosilane Route

against the global background of silicon metal production.

This process, developed at Siemens (Bischoff, 1954), rapidly superceded the earlier SiCl,/Zn method, which had been the principal silicon source until that time. There are three basic key steps in the process:

1.3 Semiconductor Grade Polycrystal Silicon As shown in Table 1-1, metallurgicalgrade silicon of 99%+ purity contains, in addition to carbon, the major impurities iron and aluminum at more than 1000 ppma, various transition and other metals - titanium, chromium, etc. - at around 100 ppma, and lesser impurities, including boron and phosphorus, at lower levels of lo’s ppma. Semiconductor polysilicon specifications require that all of these be reduced to parts per billion (ppba: 1 in lo9) levels. For the producers this extremely demanding task has to be achieved economically, to meet the very competitive market pricing pressures which dominate the industry. Early polysilicon plants were built with a capacity of around 100 t/a, but today, to meet price targets, the latest plants are built with capacities around 1000 tons, or more. Two main routes are available for the production of semiconductor-grade silicon from MG-Si; either via chlorosilanes (principally trichlorosilane, SiHCl,), or via silane (SiH,). The former has been predominant since the late 1950s, but is now being challenged.

MG-Si

grit

1 Pure anhydrous HCl

The fundamental, reversible, reaction is Si,,, + 3

w,,-.

fluidircd bed

C”D

SiHCl,,,,

+ H2fg)

(6)

The layout of a fluidized bed unit is shown in Fig. 1-4. However, again the actual reactions are more complex, and between this and the later stages of the process there is considerable recycling. The overall flow design of the plant, the efficient use of heat exchangers, and precise control of the recycling of intermediates are crucial factors in the operating costs.

H,,

T Vaporizer Heater

(a) Reaction between powdered MG-Si and hydrogen chloride gas in a fluidized bed reactor to form trichlorosilane (TCS). (b) Fractional distillation of the TCS to provide it in an ultrapure, ppba, form. (c) Reduction of the ultrapure TCS by hydrogen in a chemical vapor deposition (CVD) reaction to yield the desired product - semiconductor-grade polycrystalline silicon.

HCI

-!ICondenser

300-400°C

I

I

Heating

Cooling

Figure 1-4. Layout of a fluidized bcd rcactor. The high degree of recycling in a chlorosilane plant is similar to that in a silane plant see also Fig. 1-5. ~

Si H CI,,

Si Cl,

12


The reaction between powdered silicon and anhydrous hydrogen chloride gas in the fluidized bed, held at 300 to 400°C is highly exothermic, producing a mixed output which contains about 90% of the wanted SiHCI, [Boiling point (BP): 31.8"C], about 10% SiCl, (BP: 57.6"C), and also a little dichlorosilane, SiH,Cl, (BP: 8.5 "C); together with hydrogen, unreacted HCl, and some volatile impurity metal chlorides. For this conversion high purity anhydrous HC1 gas is essential, and a complex purification plant is needed to guarantee the < 1 ppma level specified for this stage. Phosphorus trichloride (BP: 76 "C), and boron trichloride, which is a gas at room temperature, are the two principal electrically active impurities carried over from the MG-Si; arsenic, as AsCl, (BP: 130°C) is also present to a lesser degree, together with small amounts other volatile metal chlorides, such as AlCl,; but the fluidized bed stage does reduce the incoming impurity levels quite substantially. At the next stage conventional high performance multiplate fractional distillation is employed to refine the TCS, separating it from other chlorosilanes and Si-H-C-C1 species present, and reducing the undesirable metals to ppba levels. The fractional distillation is backed up by the use of selective adsorption techniques to reach the very highest purity possible. This stage is pure chemical engineering, akin to that to be seen at any petrochemical refinery. Provided that they are kept completely dry, chlorosilanes, and also anhydrous hydrogen chloride, are chemically inactive in both liquid and gaseous form, and therefore can be moved and transported in conventional carbon-steel pipelines and tanks, but special valves and pumps are needed to maintain a totally leak-free environment. Thus the final ultrapure TCS is relatively easy to handle onwards to the next, silicon deposition, stage.

The quality of the semiconductor-grade TCS obtained at this stage is seen in Table 1-2, which shows the low levels of all impurities typically achieved. There has had to be much development of new analytical techniques in order to be able to quantify these impurities. Even using the highly sensitive method of ultraviolet spectroscopy, all metals are normally at a level below their respective detection limits. Special grades of even higher purity are available, for example, for epitaxial deposition. At this level often the only way to discriminate between two source materials is by their comparative performance under rigorously controlled conditions. When the data in Table 1-2 are compared with earlier published results, as for example those

Table 1-2. Impurities in semiconductor-grade trichlorosilane and polycrystalline silicon '. Impurity

SiHCI, SiH,CI, SiCI, Resistivity Carbon Oxygen Donors Acceptors Metals

Trichlorosilane

99.9% min 1000Qcm < 0.5 ppma' not quoted 755 barn, but, provided the boron concentration in the silicon is kept low, the effect is small. The most serious side reaction in the process is (18) Since the capture cross-section here is only 0.2 barn the amount of sulfur produced is minute in doping terms, but the long half life for the decay of 32Pcan impose restrictions on the handling of low resistivity NTD silicon. All the reactions so far have referred to thermal neutrons, that is, neutrons which have already been scattered by sufficient collisions within the pile that their energy has reached thermal equilibrium with the medium before intersecting the silicon. Such neutrons, at room temperature, have an average energy of only 0.025 eV and a velocity of 2200 m/s. However, fast neutrons in the pile, with energies in excess of 1 MeV, also reach the silicon. These give rise to much of the lattice damage generated during transmutation doping, and are also responsible for reactions of the type '%i(n,,a)

+

"Mg

(19)

producing a high energy a-particle. Even without reaction, the head-on collision of a 1 MeV neutron with a silicon atom will knock out about 200 silicon atoms from their lattice sites. Thus the slow-to-fast neutron ratio in the nuclear reactor is critical, and it is for this reason that heavy water reactors, with slow-to-fast ratios around 1000: 1 (a much higher ratio than available in light water and other reactors), have proved so successful for NTD processing. The subject of neutron irradiation damage has proved to be a matter of great complexity, beyond the scope of this chapter. Much lattice disarray is introduced, immediately after irradiation high resistivity values are found, and at this point most of the phosphorus formed is interstitial. Therefore the post-irradiation annealing process is crucial and has been studied in depth. The resistivity values, expected from the total reactor neutron flux, are fully realized after about 1 h at 600°C; however, defect studies indicate the need for a higher temperature, and poor minority carrier lifetime has been a problem (Meese, 1978). The producer's postanneal processes, which at the introduction of NTD products were at moderate temperature, sometimes relying on the high temperature semiconductor fabrication to complete the anneal, subsequently moved to higher temperatures and more complex time-temperature schedules. The exact details of vendor anneal schedules are generally sensitive proprietary information.

1.4.3 Carbon and Nitrogen in Float-Zoned Silicon For many years it was thought that any residual carbon in silicon was of little importance; it is an isoelectronic group 4 element, it occupies substitutional sites in the

1.4 Single Crystal Silicon

lattice, and silicon carbide is an insulator. The first indication of device linked effects came when Akiyama et al. (1973) reported a correlation between high carbon concentrations, reduced breakdown voltage, and increased reverse current leakage in rectifier diodes. Because this work used silicon with a very high carbon level (between 1 and 2 x lo1’ atoms/cm3) close to the solid solubility limit, and only appeared as a short communication, its significance was generally overlooked at the time. Carbon was not listed in most purchasing specifications. The common requirement of trichlorosilane for organosilicon and semiconductor use has already been noted in Sec. 1.2, and many of the world’s polysilicon plants are cosited with, or close to a silicones plant. Thus, when in mid 1975, accidentally and undetected, a quantity of high-carbon float zone silicon reached device lines, serious yield problems were met in rectifier, thyristor, and power transistor manufacture. Subsequent research showed that, while not affecting the breakdown voltage, lower levels of carbon still degrade the reverse leakage, as is shown in the plot of Fig. 1-8. Recognizing a severe problem, polysilicon producers made major plant overhauls to remove carbonaceous sources from pumps, valves, glands, etc., set new low carbon operating standards, and instituted strict test procedures - in single crystal the substitutional carbon has an infrared absorption at 16.6 pm (605 cm- I ) measured by differential (double-beam) spectrophotometry, ASTM Standard F123. Today carbon levels are rigorously controlled by all silane, TCS, and polysilicon producers, to ensure final silicon levels below around 2 x 1OI6 atoms/cm3. The role of nitrogen in silicon is quite different. Unlike other group 5 elements, such as P, or As, nitrogen does not behave

21 I

300 2

- 100

P (u

U

m

1

+ m 200 P

I

c

10

t

c (u

2

L

2 (u

D Y

m (u

1.0

100 2

cn

rn Y m ( u

VI aJ L

0.1

01

QJ w

i 1015

I

10l6

id7 C, I

o m

Carbon concentration (atorns/crn31

Figure 1-8. Rectifier diode failure as a function of carbon concentration: o breakdown voltage; x reverse leakage current. Note that, even when the breakdown voltage has been restored, leakage effects persist to much lower carbon levels. The dashed vertical line marks C,, , the carbon solid solubility saturation value.

as a donor impurity. An electronic center deep in the band gap has been reported by Tokumaru et al. (1982), but in general nitrogen does not appear to be electrically active in melt doped silicon. Another distinguishing feature is its low solid solubility: 3 x IOl5 atoms/cm3 at the melting point of silicon (Yatsurugi et al., 1973).This is much lower than for other light elements, ~ , such as carbon, N = 3.5 x lo1’ ~ m - or oxygen, 1.7 x lo1* atoms/cm3. In float zoned silicon the equilibrium solid solubility is often exceeded, the excess concentration being proportional to the zone velocity, where typically the values met may be up to 5 x lo1’ atoms/cm3 (Yatsurugi et al., 2973). The low electrical activity of nitrogen in silicon is useful because it has a major attribute, in that nitrogen doping at low concentrations, limited by its solid solubility, effectively inhibits dislocation generation and propagation, as first reported by Abe et al. (1981). Second-phase hardening is a well known metallurgical phenomenon,

22


amount of crystallographic slip caused by the controlled thermal stress. The results in Fig. 1-9 show clearly the advantages of NFZ doping. The material has been used successfully in both, bipolar and MOS, fabrication, but has not yet achieved major market penetration.

but usually occurs at higher concentrations. Low levels of nitrogen in silicon, in the 1015atoms/cm3 range, impart resistance to the thermally induced warp of wafers met during device fabrication. Slices of Czochralski silicon, grown from a silica crucible, with around 8 x l O I 7 atoms/cm3 oxygen content, are warp resistant, unless some of the oxygen is precipitated, when the material becomes less resistant, and here the oxygen levels are three orders greater. Normal float zoned silicon slices, with an oxygen content less then 1 x 10l6 atoms/cm3, and also low in carbon, distort readily under thermal stress, but with nitrogen doping outperform high oxygen Czochralski material. A simple demonstration to compare the normal FZ and CZ material is as follows. Standard, polished, (100) orientation single crystal slices, 76 mm diameter, 380 pm thick, mounted on a three support point silica jig span 63 mm, and loaded by a 50 g weight are heated at 1150 "C for 1 h, ramping the temperature up and down from 850°C in 30min measuring the change in warp, and, by Secco etching, the Slices a l l 380pm thick

140

1.4.4 Periodic Crystal Growth

Temperature oscillations during crystal growth have been recognized for a long time, and their effects described (Carruthers, 1967; Hurle, 1967; Chedzey and Hurle, 1966). At first sight this may appear an odd concept, but the underlying principle is simple and can easily be demonstrated (Hurle et al., 1974). A small channel containing gallium (a metal which, conveniently, is molten at temperatures above 30°C) with a number of thermocouples inserted equispaced along its length is well wrapped in thermal insulation to prevent heat loss. One end of the channel is clamped to a flowing water cooler, and so held at around 35-40°C. The other end is attached to a heater, whose temperature is

{loo! orientation

- LH

Load 5 0 9 Span 6 3 m m

___

120

-3 0 0

Change in TIR (warp) axis Extent o f slip RH axis

80

.-c & 60 c

m

5

I I I I

40 20

0

I

L Float zone N-doped

-

Float zone standard

Czochralski 0-doped

Figure 1-9. A comparison of warp and slip after loading slices (1 h at 11 50°C) (LH: left hand, RH: right hand). [Note that curvature in a silicon slice is hardly cvcr a simple saucer shape; it is more like a potato chip (potato crisp). Modern metrology equipment scans the whole surfacc to arrive at a single value, the total integrated reading (TIR), and also provides plots of the surfaces.]

1.4 Single Crystal Silicon

gradually increased. At first, simple heat flow along the channel creates a thermal gradient, recorded by the thermocouples. However, as this temperature gradient is increased, a point is reached when the thermocouple signals suddenly change into regular sinusoidal oscillation. The system behaves analogously to an electrical AC driven oscillator, whose frequency is determined by the inductance-capacitance product. Here the thermal diffusivity, kinematic viscosity, and channel dimensions, replace their electrical counterparts in an equivalent thermal -mechanical resonator. Thermal oscillations have been seen widely in many crystal growth systems, not only in semiconductors - Si, Ge, GaAs, InSb, etc. but also in LiNbO,, garnets, and most oxides and fluorides (Cockayne and Gates, 1967). Superposition of oscillations on the temperature near the solidliquid interface between a crystal and its melt causes large regular fluctuations in the growth conditions. The driving force, which determines the overall rate of growth, is provided by supercooling setting the melt temperature close to the interface a little below the melting point. Since most crystal growth rates are relatively slow, this value is normally smaller than the magnitude of the thermal oscillations, and so the growth becomes highly dynamic, and even, at the peak of each cycle, includes momentary meltback. This periodic nature of crystal growth controls the incorporation of dopants and impurities into the crystal, whose concentrations may vary markedly, the changes exactly replicating the periodicity. The regularity of these growth striations can be seen by etching, and by spreading resistance (microresistivity) measurements, made on a cut vertical section of a crystal, as shown in Fig. 1-10. Since the crystal growth interface across a diameter is always curved, cut

23

-

-

Figure 1-10. Periodic crystal growth (1). Spreading resistance plot (above), with points taken at 10pm intcrvals along the growth axis. Etched surfacc micrograph (below), showing the structure variations within a single striation.

slices intersect several striae, and subsequent delineation reveals a spiral radial impurity distribution pattern in the slice, as shown in the X-ray topograph of the carbon distribution in a float-zoned slice in Fig. 1-11. (Note: the X-ray topography technique is covered in Sec. 1.6.1.) If growth periodicity did not include a meltback within the cycle its effect on impurity distribution would be far less severe. This has been demonstrated by the float zone growth of small diameter rods, when the latent heat of solidification generated at the interface can escape more easily than at larger diameters, permitting higher growth rates. As the rate is increased, a

24


such crystals reveal an extremely wide scatter of values. Such material is immediately rejected. The effects of normal striated silicon in device manufacture are quite variable. In some cases it does not seem to matter, but in other cases striae can cause serious losses. Again because of the greater difficulties in zoner operation, float zone silicon tends to have more problems. For example, in the manufacture of UHF transistors, for applications at around 500 MHz, the cut-off frequency, f,, is a function of the collector base current, I,, , which is very susceptible to small, local, microresistivity variations. In a direct comparative trial, the percentage standard deviations about the mean of f,, J;, at the operating I,, current, has been measured using three materials sources (see Table 1-3). In the third material an epitaxial layer of the same type, and resistivity as the underlying substrate, deposited from the vapor phase, and so free of the melt-growth striae, provides an extended bulk material within which the transistors are fabricated. As the table shows neither CZ nor F Z can match extended bulk epitaxy, EBE, while the FZ material is the worst in this application. EBE material is used in large scale production of these devices, its additional cost far outweighed by the yield improvement. ~

Figure 1-11. Periodic crystal growth (2). X-ray topograph of the carbon distribution across a cut slice. C, = 4 x loi6atoms/cm3.

point is reached when the supercooling gradient overcomes the thermal oscillations, and at a growth rate above 3 mm/ min the striae dissappear. This research, while interesting, is not a production option. In the case of Czochralski growth, where, as will be discussed later, the melt is normally positioned in the heat field to keep thermal convection low, the axial pitch of striations is closely linked to the growth parameters. The etched vertical section shown in Fig. 1-10 was taken from an 80 mm diameter, (100) orientation, crystal pulled at 1.5 mm/min, with a rotation rate of 15 rpm hence the thickness of the silicon layer grown per revolution was 100 pm, which, as the measurements show, is also the striation pitch. On the other hand if the crystal is grown under high thermal convection, that is, forced convection, conditions, then the striae are closely spaced, discontinuous, and aperiodic (Carruthers et al., 1977). Spreading resistance measurements taken on the slices cut from

Table 1-3. The effect of resistivity striations on device mean value of performance. c:standard deviation, the cut-off frequency.

x:

Type of material Float zone Czochralski Epitaxially extended bulk

c(1)in % 24 10

3

1.5 Czochralski Silicon

Epitaxy therefore is one way to overcome the bulk striation problem. Another is the neutron transmutation doping method already described, and whose importance in the high voltage and power fields will now be more fully appreciated. Again the costs are obviously somewhat higher than for the conventionally doped materials, but the fabrication and device performance are far superior. Herzer (1977, 1980) and Herrmann and Herzer (1975) have examined the interaction of striations in NTD doping. Using material with a starting resistivity of 10 times the final value shows no background striations, at 5 times slight striations are seen, while an initial resistivity 2 times final, gave f 10% variations. A third, and the most widely used way to overcome striation effects, which introduces no added costs, is that employed in MOS integrated circuit fabrication. Taking n-MOS as the example, the substrate is p-type, boron doped at around 20-30 SZ cm resistivity. The MOS devices are made entirely by ion implantation, with n + source and drain channels, and an n- gate implant equivalent to a resistivity of somewhere around 1 - 5 i2 cm. These implant concentrations are at least 10 times higher than the substrate boron level, and striation effects are reduced to insignificance; that is, similar to the NTD situation. Today integrated circuit manufacture consumes more than 75% of the world's semiconductor silicon as Czochralski crystal, our next topic.

1.5 Czochralski Silicon The increasing size of crystals pulled by the Czochralski (1917) technique, and the technological developments associated with the growth of dislocation-free material, in which there is close control over not only

25

the dopants, but all impurities, represents one of the outstanding achievements in semiconductor processing. The silicon pullers used initially were quite simple (Teal and Buehler, 1952). The charge, consisting of small lumps of broken polysilicon, was melted together with a small precise amount of dopant, from a silicon alloy made with P, As, or Sb (n-type), or B (ptype), at just above the melting point, 1412 "C, in a pure silica crucible, retained in a graphite holder to prevent it sagging, held under an argon atmosphere; either resistance or R F induction heating was used. A thin, single crystal, seed rod mounted in a rotating shaft was lowered into contact with the melt surface, and a little melted off in order to establish a clean solid-liquid interface. Then, as the temperature was lowered, silicon started to solidify on the seed, which was withdrawn at a controlled rate to pull a crystal of the desired resistivity, ultimately almost emptying the crucible. This apparently simple description is deceptive, there were many hidden subtleties needing to be understood. It was soon realized that, to be able to pull a crystal at all, without spurious growth at the crucible wall, it was essential to have a centrosymmetric heat field - the introduction of crucible rotation followed, which also eliminated random convection in the melt. As charge sizes increased, R F heating was abandoned, and the tapering of graphite resistance heaters was used to shape the best vertical heat field profile. However, having established this in the melt -crystal interface region, it could only be maintained as melt was used by introducing a crucible lift mechanism. The furnace configuration which resulted, as shown in Fig. 1-12a, is that still in use in even the largest pullers.

26


1:’

Crystal rotation and lift

Seed

Solid conduction /

Surface radiation

Thermal baffles SiO evaporation Interface generation of latent heat

Crucible holder

Oxygen dissolution

Crucible

1,

Heater

Heater

‘I

ll

M

q€===== II

Vacuum pump I

-1

Crucible rotation and lift

la)

-t

Ib)

Figure 1-12. The Czochralski silicon crystal puller. (a) Principal components of the hot zone. (b) Heat flow (t) and oxygen transport (0)during crystal growth.

1.5.1 Dislocation-Free Silicon The first dislocation-free material (Dash, 1958, 1959, 1960), was made by slowly growing small finely tapered crystals, but Zeigler (1961) used a rapid pull rate after seeding, to establish a thin neck, in which the few dislocations present grew out to the side surfaces, onto which a large dislocation-free crystal could then be grown. This was possible since, once a crystal is free of dislocations, it is better able to withstand the thermal stresses met during crystal growth. Prior to the introduction of dislocation-free growth, the germanium and early silicon crystals contained lo5-lo6 cm-’ dislocations. As a result of the thermal gradients in the system, these formed up into arrays, and lineage, deteriorating towards the bottom of the crystal; twinning was a serious problem leading to yield losses (Wilkes, 1959). The ability to grow

dislocation-free crystals depends critically on control of the shape of the solid-liquid interface in the meniscus region. Why any crystal takes the shape it does is closely linked to this problem, and is examined first. The external shape of a crystal is related to two basic parameters, each a generic term covering several associated attributes: (a) Temperature, T, which includes all aspects of heat flow conduction, convection, etc. - and generation - from the main heater, or from latent heat at the interface. (b) Crystal habit, C,, which includes all aspects of morphology - nucleation, crystal growth along basal planes, dislocation formation, twinning, etc. ~

The totally facetted alum crystal from a near isothermal solution growth is crystal habit dominated, while the near shapeless


mass from a crude unbaffled melt system with high temperature gradients is temperature dominated. Normal Czochralski growth from a well designed system produces crystals whose macroscopic features show the balance that exists between the “temperature”, and “crystal habit”, contributions. In such a machine a very slowly rotated, (1 11) orientation silicon crystal can be pulled, at low or high growth rates, and will not exhibit any marked “flats” along its sides. There are high-temperature gradients across the melt surface in the vicinity of the growing crystal. On the other hand, under fast rotation conditions, while the interface shape becomes fluid flow dominated, the crystal grows out of a near isothermal surface; and such crystals, irrespective of growth rate, always exhibit extremely pronounced “flats”. Under normal growth using moderate rotation rates a crystal may exhibit narrow side facets near to its top which increase in width towards the bottom, when the near empty crucible behaves as a “black box”, near isothermal, cavity. For this reason the crucible and remaining charge is lifted faster than needed to keep the melt surface stationary, but lifting it out of this too isothermal region, so avoiding excessive facetting. The T $ C, balance applies everywhere, including at the solid- liquid growth interface, on which we now focus. While the main heater, and baffles, determines the overall thermal profile of the puller, it is actually quite ineffective in influencing the interface shape of the growing crystal, whose thermal conduction provides a good heat sink during growth. However, the latent heat of solidification (12.1 kcal mol-l or 50 J mol-I), released at the interface, is a significant heat source. As the pull rate increases the interface curvature changes from convex (into the melt),

27

to concave (back into the crystal). Silicon crystallizes in the diamond-cubic lattice, with the (111) planes being the most densely packed, while the bonding between adjacent ( I l l ) planes is relatively weak compared to other directions. Growth is fast along the (111) planes, so leading to the appearance of { 111) facets on crystals, but slow perpendicular, while cleavage, twinning, and dislocation generation and propagation all occur along this dominant basal plane (Ellis and Treuting, 1951; Townley, 1973). Since in the T =+C , interactive model, facets are only expected in near isothermal regions, their position and size can be predicted, as the interface shape changes from convex to concave during the growth of a (1 11) orientation silicon crystal, shown in Fig. 1-13, and matched by a series of actual interfaces of crystals snatched from the melt grown at increasing pull rates: from convex, to inversion, to ring facet, finally concave (Wilkes and Perkins, 1971-72). Dislocations form on the very small peripheral (111) facets at the edge of convex interfaces, and once formed continue downwards into the crystal as it grows further. This cannot happen where the (111) crystal is bounded by a ring facet, or, in the case of a (100) crystal, when the interface is concave. These are the conditions for the zero dislocation growth of silicon, and are established immediately after seed-on in a narrow neck, before proceeding on to enlarging the diameter to full size. As stated earlier, when a crystal is grown in the dislocation-free mode from its start, it is better able to resist the temperature gradient hoop stresses met later as the solid crystal cools, when it is withdrawn from the hot zone in the puller. To avoid thermal shock at the end of the pulling process, when the crystal is withdrawn from the residual melt, which can

28


Figure 1-13. The changes in interface shape of a (1 11) orientation silicon crystal as the growth rate is increased. As the growth rate increases latent heat of solidification at the interface plays the most significant role in

determining its shape (LHT, latent heat temperature profile; MHT, main heater temperature profile; hatching indicates the solid crystal). (1, A) Low speed, small central facet, convex. (2, B) Somewhat faster pull, larger central facet, still convcx. (3, C ) Even faster pull, latent heat generation now compensates for heat losses across the whole interface, which becomes a {I 1 1 ) mirror surface; the point of inversion. (4, D) Speed of growth greater than for inversion, producing a wide ring facet and a small relatively shallow central concavity. (4, E) Speed faster still. The central cavity is deeper and wider so there is a narrower ring. (5, F) The pull rate is now very fast and any MHT/LHT compensation is outside the pheriphery of the crystal. Very deep concavity, no ring facet.

lead to stress-generated dislocations running back up into the solid, so causing yield losses, the final part of the crystal is grown tapered in a cone to a point. Mastery of the zero dislocation growth mode, for both CZ and FZ techniques, at the end of the 1960s, preceded the later machine developments which have led to the crystals weighing more than > 60 kg, with diameters of up to 150 mm or more, in cur-

rent production many thousands of tons of dislocation-free silicon per year. ~

1.5.2 Constitutional Supercooling For epitaxial substrates, large amounts of very highly doped, n + and p + , zero dislocation crystal are needed, which involves the particular problem of constitutional supercooling, as described for metals by


29

Rutter and Chalmers (1953). At the crystal-melt, solid-liquid interface of a growing crystal impurity segregation occurs, its coefficient, different for each dopant, defined by concentration in solid keff = concentration in bulk liquid

I

-~ - cs

(1-2)

c,

For a rejected impurity keff is less than 1.0, but as a result of the rejection, a boundary layer builds up in the liquid at the interface, at a higher concentration than in the bulk, from which the crystal grows. Therefore the effective k e f ffor a finite growth rate is higher than the equilibrium value, k , , and rises with increasing growth rate. The thickness of the boundary layer, 6, within which fluid motion is laminar, relatively slow, and hence nonmixing, so that diffusion is the predominant transport mechanism, is determined by the crystal rotation stirring, and as the rotation rate increases the boundary layer gets thinner. This relationship is given by the Burton, Prim, and Schlichter (Burton et al., 1953) equation

keff =

k0

ko

+ (1 - k,) exp (

-

vg 6/D)

(1-3)

where ug is the growth velocity, and D the impurity diffusion coefficient in the liquid, cm s. This formula of the order of 5 x shows that k e f f varies continuously from k , , at very low growth rates, to 1.O, at very high rates. The higher impurity level in the boundary layer results in a silicon-dopant composition of lower freezing point, as seen in Fig. 1-14. The temperature gradient from the solid into the melt, necessary to allow growth at the chosen rate, is also shown in Fig. 1-14. At the higher rates needed to obtain the desired interface

Temperature gradient i n t o melt L al

a

+ m 01 L

n

5

+

Tr,

Position o f maximum supercooling due t o local composition Distance i n t o melt

Figure 1-14. Constitutional supercooling during k , = C,/C,, k,,, = CJC,, crystal growth. 6 2 1.6D"3 V ' ' ~ W ~ ' 'TcG: ~ , crystal growth temperature. As u, and 6 + 0, k,,, -+ k,; and as ug and 6 become large, k,,, + t .O.

shape for dislocation free growth, and when the dopant levels are also high, a region is formed in the liquid, ahead of the crystal, which is supercooled by virtue of its local constitution, and in which nucleation and random crystallization can happen. As the advancing interface approaches this point, the single crystal rapidly becomes polycrystalline. The greatest risk of this occurring is in the later stages of n', or pf crystal growth, when segregation by normal freezing, as defined by Eq. (1-I), further increases the already high initial dopant concentration. Studies of the onset of constitutional supercooling in these crystals (Wilkes and Perkins, 1971-72), using striation etching to reveal the details, has shown that the initial perturbations, and formation of cellular structure, in (1 11) orientation silicon, originate on the inner edge of the ring facet, as

30


Figure 1-15. The onset of constitutional supercooling at the inner edge of the ring facet during the growth of dislocation free, (1 11) orientation, n + Sb doped, silicon. Note: In the enlargements the arrow points outwards radially. At a later stage of growth, the whole interface breaks up into a hexagonal cellular structure, prior to the transition from single crystal to polycrystal.

shown in Fig. 1-15. Acheiving high production yield and reproducibility for this material demands precise control of the pulling parameters.

1.5.3 The Incorporation of Carbon and Oxygen Most of the components in the hot zone of a puller are made of some form of carbon - graphite heaters and crucible holder, and carbon felts in the baffle assembly but careful housekeeping can virtually eliminate these as a source of contamination. Maintaining the pullers leak-tight, using ultrapure argon as the purge gas, and employing rigorous purging schedules after ioading the charge, remove air or rnois~

ture, which could otherwise react with the carbon parts to form CO, to dissolve into molten silicon; and as we have seen, polysilicon itself is very low in carbon yet carbon can be a problem. During the first step of meltdown of the polysilicon into the pure silica-glass crucible the system is at its hottest, up to around 150O-155O0C, to achieve meltdown in a short time. Under these conditions reaction between the graphite crucible holder and the outer surface of the silica crucible releases carbon monoxide [see Reaction (1-l)]. This is the prime source of the carbon impurity. After the meltdown is complete and the temperature is lowered, to around 1420-1430°C for the start of pulling, the reaction only continues at a ~


much lower rate (Barraclough and Wilkes, 1986). In an atmospheric pressure puller, where the argon purge rate is commonly around 60 L/min, the initial carbon content in the crystal is around 2 x 10l6 atoms/cm3; but, if the start is deliberately delayed, this steadily rises as more carbon is slowly dissolved. Operating the puller at a reduced pressure, of about 20 torr ( z2600 Pa), with an argon input of 10 L/min at normal temperature and pressure, the effective gas displacement rate sweeping out the chamber is increased six-fold, and the silicon crystal produced contains far less carbon by at least an order of magnitude. Under carefully regulated conditions, a large proportion of the crystal can be grown with carbon below its infrared absorption detection limit of 5 x l o L 5atoms/cm3. In this case when meltdown is complete, and during crystal growth, further carbon transfer is insignificant. Today all large silicon Czochralski production pullers are operated at reduced pressure. While risk of carbon incorporation is essentially limited to the meltdown period, another reaction continues throughout the whole process - that between the silicon and the inner surface of the crucible, dissolving oxygen into the melt: Si + SiO,

-+

2SiO

which, at the same time, allows any other electrically active impurities present in the silica into the melt. Crucible quality is clearly important, and has steadily improved as natural sources of silica have widely been superceded by the use of fused synthetic SiO, made from semiconductor grade materials. As a result, the resistivity reached by pulling undoped silicon is now routinely greater than 200 Q cm, and with low compensation. This has permitted the producers to offer CZ crystal specifications

31

of up to around 50 R cm resistivity, n- or P-tYPe. Returning to the oxygen dissolution, as can be seen in Fig. 1-12b, this occurs primarily along the hotter inner wall of the crucible, and only to a lesser degree across its base; and, while thermal convection transports the SiO up to the free melt surface where it can evaporate, much oxygen becomes incorporated into the growing crystal. This is a highly dynamic equilibrium, altering continuously as silicon is withdrawn from the crucible, and the ratio of melt volume to crucible surface contact area changes. The oxygen concentration decreases down the length of the crystal typically from near loi8 atoms/cm3 at the top to around 5 x lo1' atoms/cm3 towards the base end; that is, from 20 to 10 ppma. In the Czochralski system, melt fluid dynamics clearly play a vital role in the growth, and in the incorporation of all impurities, into the crystal; the prime contributors being the thermal convection and the mechanical drive provided by the crystal and crucible rotations - usually in opposite sense. The convective drive is influenced by several factors. In fluid flow adjacent to a hot vertical wall, the velocity is a function of the temperature gradient, height up the wall, h, and Prandtl number, Pr (Schlichting, 1968):

(1-4) where the dimensionless Prandtl number, the ratio of the kinematic viscosity to the thermal diffusivity, is a measure of the relative ease of movement and heat transport in a fluid element. The value of Pr (Si, liq.) is 0.015, a lower value than that of mercury, 0.023. [In comparison Pr (H,O, room temperature) is 7, and Pr of glycerol is 300.1 Because liquid silicon has such a low Pr value, as heat flows through the wall into silicon it read-

32


ily convects. (A stability analysis for convection links this low Pr to the rotationally coupled thermal oscillations, described in Sec. 1.4.4 above.) Therefore thermal convection is less in a relatively wide flat melt, as is normal in CZ silicon, and decreases as the liquid diminishes. (Note: in the CZ growth of oxides, with Pr around 30, taller narrower crucibles are common.) Positioning the crucible lower in the heat field, with a greater power transfer into the upper part of the melt, also promotes a reduction in the convective drive. Again, the baffle configuration surrounding the heater crucible assembly reduces the temperature gradients in the system, and can be arranged to keep the crucible wall cooler, so reducing its dissolution rate (Moody, 1986). The functions of the mechanical rotation drives are quite different. Rotation of the crystal only couples it to the melt over the small area of its base, and this is withdrawn above the surrounding free surface by the height of the meniscus cell - about 4 mm. Thus, while crystal rotation directly affects the dopants incorporation, and their uniformity across the crystal, it has only minor influence on the bulk fluid motion. A realistic analogy is that of a skater on ice. On the other hand, the crucible rotation couples to the whole body of the melt, and, particularly in large systems, provides an important centripetal force, to modify the thermal convection. Heat flow, and the theory of rotating fluids, are mathematically complex, and generally involve significant approximations, even when using computer iteration procedures. However, because of its importance, there has been much work on silicon - CZ flow patterns (Robertson, 1966),nonmixing cells (Carruthers and Nassau, 1968), computational analysis of interface

shape and flow in a crucible (Kobayashi and Arizumi, 1970; Kobayashi, 1978; Kobayashi and Wilcox, 1982), digital flow simulation (Langlois and Shir, 1977; Langlois, 1984, 1985), and heat transfer in CZ systems (Dupret et al., 1986) - which taken overall indicate that the main mode of convection is natural, rather than forced. Under the conditions of a well designed thermal geometry, with more gentle convection, it is easy for the crucible rotation centripetal force to play a greater part in shaping a stable thermohydrodynamic melt. The simple model of melt convection in a very slowly rotating crucible is that of a single Benard cell - liquid rising near the wall, then flowing inwards radially, near to the melt surface, towards the growing crystal. As the crucible rotation rate is increased, the centripetal forces act in opposition to the convection, slowing the fluid motion, until at some higher rotation rate the melt behaves almost as a solid body. Such solid body rotation is seen in water dye tracer simulations of CZ systems, and a practical application is found in the control of the oxygen content of silicon crystals. Since the fluid convection transports not only dopants but also heat to the vicinity of the crystal, increasing the crucible rotation reduces this heat flow, and it is necessary to increase the crucible wall temperature to compensate and maintain constant diameter growth. Optical pyrometer measurements of the wall temperature have recorded rises of 30-40°C at high rotations. As a result the silica dissolution rate rises markedly, providing a higher oxygen flux to the crystal. This is seen for a series of crystals, grown at increasing crucible rotation rates, in Fig. 1-16, which also shows how accelerating the rotation as growth proceeds can produce silicon to specified limits in oxygen content (Barraclough, 1982; Murgai et al., 1982).


c 0

m

Fraction solidified (gl

Figure 1-16. The effect of crucible rotation rate on the incorporation of oxygen into Czochralski silicon.

This process works well for the production of medium to high oxygen content material but good yields at lower oxygen concentration are difficult to achieve. This problem is now addressed in the next section.

1.5.4 Magnetic Czochralski Silicon Electromagnetic stirring and other effects in molten metals have been recognized for many years, and, in the intense radio-frequency fields within the heater coil of a float zoner, magnetic levitation in part supports the molten silicon. Some large Czochralski pullers have used a three-legged graphite picket heater, driven from a three-phase AC mains supply at 50- 60 Hz, the heavy heater current inducing rotational forces in the melt, where flow rates as high as 20rpm have been observed. The latest puller designs have returned to using two-legged picket heaters and DC drive to avoid this effect. Today it is the application of static magnetic fields to dampen out the convection flows in Czochralski systems that is important.

33

The early work by Chedzey and Hurle (1 966) was initially directed towards the suppression of growth-striae in FZ, and then in CZ crystals (Hurle, 1967). Czochralski growth in a transverse magnetic field was reported by Witt et al. (1970), but it is the recent revival, initiated by Hoshi et al. (1980), who applied very large electromagnets to commercial silicon pullers, that has stimulated worldwide interest, and major developments. The Sony Co. results show that products with a wide range of oxygen content can be made by Czochralski growth in a strong magnetic field; the technique offers the control of resistivity up to 5000 Q cm, and also higher than normal growth rates. Both electromagnets and superconducting cryomagnets have been used to provide fields in the general range of 1000- 5000 G (0.1 -0.5 T). Hoshi et al. (1980) and Suzuki et at. (1981)first used a transverse magnetic field, with the lines of force parallel to the melt surface; axial fields have also been applied (Hoshikawa, 1982; Hoshikawa et al., 1984; Cartwright et at., 1985). As the strength of the magnetic field is increased, fluid motion perpendicular to the lines of force is progressively dampened out until, in a high field, it is suppressed altogether. Thus in an axial, vertical, field the radial fluid flow across the surface is reduced; whereas in a transverse, horizontal, field it is the axial (upwards at the crucible wall, and downwards beneath the crystal) and azimuthal motions (rotational shear around the crucible wall) which are reduced but then not the radial flow. Clearly, in either mode there is a strong effect on thermal convection. Hoshi and Suzuki showed that a horizontal field of 0.15 T was sufficient to suppress the convection in a melt contained in a 25 cm diameter crucible. Again, the balance between field strength and the crucible and

34


crystal rotations, both in their rates and relative senses, is apparent in the effects on impurity distribution. In a vertical field a wide range of oxygen concentrations is possible, but, because the radial flow is reduced, it is dificult to achieve acceptable radial uniformity, compared with the results possible in the absence of a field, whereas very good radial impurity distribution is possible using a transverse horizontal field. The two magnetic field modes are distinguished principally by the large differences in their temperature distributions, and gradients, which to a considerable degree determine the alternative product properties. Using the vertical-field conditions the increased radial temperature gradients are larger than if no field were present, whereas in the same puller under horizontal field conditions the temperature gradients are reduced, and can be much smaller than with no field. As we have previously seen, the oxygen dissolution rate is set by the wall temperature, and experience now suggests that horizontal-mode growth is more suitable for the production of controlled low-oxygen silicon. While both modes sharply reduce the growth striae, produced by thermal fluctuations in the melt close to the interface, which are a feature common to all zero field growth, again it is the lowtemperature gradient beneath the crystal, available under transverse fields of around 0.25-0.3 T which permits growth rates some 50% higher than with no field, yet maintaining the correct interface shape required for dislocation-free growth. While the balance of these trends, when set against the device maker’s needs, appears to be moving towards transverse-mode material, very recent research has explored the development of shaped, compound magnetic fields, with horizontal, vertical, and low-field components, designed into

different sectors of the melt, obtained from the interaction of two vertical coaxial magnets placed one above the other (Barraclough and Series, 1988). The makers of commercial production Czochralski pullers now offer machines with either magnetic mode and 60- 150 kg silicon capacity (e.g., from Hamco or Ferrofluidics). In summary, Czochralski silicon technology is indeed very complex. A large number of highly interactive, adjustable parameters are available in the thermal design of the core furnace, its heater and baffles, and in the aspect ratio of the melt; in the mechanical movements to position, lift and rotate the crucible and crystal; and now in the magnetic conditions, in mode choice, and field strength and position. It is, however, precisely this flexibility in design variables and growth control, not available to the same degree in float zoning, that gives the Czochralski technique its power to address the product requirements. 1.5.5 The Commercial Scaling of Czochralski Silicon

The constant competitive pressures in the market, and the demand for ever larger slice diameter, doubling about every seven years (seen in Fig. 1-2), together with increasingly stringent quality specifications, have placed emphasis not only on the technologies discussed so far, but also on process scaling. During crystal pulling from a crucible, unavoidable yield losses occur from the silicon used in the top and base cones, and in the residual silicon left in the crucible at the end. Further fixed losses are entailed in grinding the ingot from the growth diameter to exact cylindrical dimensions before slicing to parameter limits (e.g., resistivity, oxygen content). As the diameters have risen it has been essential to


scale up capacity in order to maintain the output-input ratio. The plots given in Fig. 1-17 show clearly why pullers used for the production of 150 mm diameter slices need to be in the 30- 60 kg range; and the introduction of 200mm slices pushes this further. Modern pullers with the features described above, > 60 kg capacity, with fully automatic, computerized growth control, with a 2 m (or more) pullstroke, and designed for 150- 200 mm diameter slice production, cost up to $ 1 M. each; a price which continues to increase as the new magnetic techniques have been introduced and even larger machines are built. However, automation leads to high product reproducibility, and, when worked continuously, these machines have a high silicon throughput. The economic gains of operating a block of such pullers, linked to the expertise needed, goes far to explain why the device houses have largely withdrawn from materials. The developments described have been essential to keep production costs down during the past inflationary, and competitive, decade; this is demonstrated in Fig. 1-6, where the single crystal plot is for standard base-line specification material. To place the whole operation into a framework, Table 1-4 gives an added value comparison for silicon material at key points in its manufacture, from metallurgical silicon to an epitaxial slice,

/ I /Id (u

-$I2 Jz U

a 4

0 10 20 30 40 50 60 70 80 90 Yield (%I Figure 1-17. Czochralski silicon growth. The influence of the crystal diameter on the initial charge weight and maximum yield possible.

taking as reference polycrystal silicon at a value of “100”. Today the ongoing increase in the size of ULSI chips described in the introduction is forcing further scaling-up to 200mm diameter wafers; some 250 mm material is already being made, and research towards 300mm is active. As the melt volume increases it becomes ever more difficult to control the fluid motion. As shown in Figs. 1 12 b, heat enters through the near vertical side wall of the crucible, and the principal heat losses are axial - downwards through the base, and upwards by conduction through the crystal and by radiation from the melt surface. However, even in a 30-40 kg melt the fluid motion is complex. Although the heat transfer mechanism still leads to the molten silicon rising around the crucible periphery and falling in the central region, the form is no longer a simple Benard cell. It is much more complex, -

Table 1-4. Addcd valuc comparison in silicon materials. Material stage Metallurgical grade Si Ultrapure polysilicon Monosilicon rod Polished Si slice Epitaxial slice“ a

Product price per kg 20 100 500 -900 2000 4000 5500- 14 000

(Ref.)

Epitaxy is the subject of Chap. 3 of this Volume.

35

36


with rotating eddies swirling in the mid-radial area superimposed upon the overall flow pattern. Crystal growth interfaces snatched from the melt reveal the greater thermal complexity, which causes the most problems during the initiation of growth, from seed on and through the phase until the crystal reaches a sufficient diameter that its rotation is able to stabilize the fluid flow geometry axially. As charge weights increase towards 100-1.50 kg these problems can only become more severe. Attaining high yields of close-tolerance material, both radially and along the crystal length, with respect to dopant and oxygen concentration will need fully computerized programmed control of all motions (translation and rotation), melt position in the heat field, and argon gas flow and pressure. During growth all these parameters may be varied continuously. For some years it has been recognized that the use of epitaxial material could offer advantages in MOS manufacture, in particular improved parasitic capacitance, leakage, and threshold voltage control, but the cost of an epitaxial slice has been a deterrant. Now, for large DRAM, SRAM, and some other applications, the use of pp’ and nn’ silicon is rising. However, the importance of gettering during fabrication means that the heavily doped substrate wafers needed for epitaxy also have precise oxygen-content requirements. This combination of very heavy doping and oxygen control in large diameter crystals poses further technological problems.

1.6 Slice Fabrication Stated simply, the polished slice fed into a device line must be flat, clean, and damage free; but often in the past, companies, after achieving good bulk crystal, have

failed to produce acceptable slice products. The steps used in wafer processing hide many pitfalls. In the slicing and grinding stages much damage is caused to the surface of the material, whether or not the shape be correct, and both have to be controlled. The subsequent etching and polishing stages have to remove the damage and produce the final surface in which devices are made. However, low level mechanical damage sites, at the back surface, have the useful property of acting as collection sinks for unwanted fast diffusing, electrically active, heavy metal contaminants, well away from the front polished surface and the devices. This is known as “extrinsic gettering”. On the other hand the precipitation of oxygen within the bulk of the slice, but away from the surface, provides internal, “intrinsic gettering” sites which perform a similar role. How these various features are handled is the subject of this section.

1.6.1 Mechanical Damage in Silicon The subsurface damage in silicon which results from the processes of diamond grinding, sawing, or lapping, can be assessed by various means. An early method was based on the fact that damaged silicon is etched faster than undamaged material, so that plotting etch rate versus depth gave some indication of the extent of damage associated with a particular process. Minority carrier surface recombination is very high in damaged material, but falls rapidly as the damage is removed by etching, providing another route to depth assessment (Buck and McKim, 1956). The decoration of dislocations and damage centers by copper, followed by infrared transmission microscopy, permitted the direct visualization of defects in silicon (Thomas, 1963), but the effects of decora-

37

1.6 Slice Fabrication

tion at 900°C and quenching were questionable. An unambiguous measurement technique uses the X-ray double crystal diffractometer to study strain and defects in crystals. First introduced by Bond and Andrus (1952), applied to silicon, it has become a major tool in the study of machining. The X-ray system is shown in Fig. 1-18 a, where the double crystal configuration results in monochromatic radiation reaching the sample crystal. The signal to the detector, I(@, changes as the sample is turned through a small angle about the Bragg reflection, producing the rocking curve of Fig. 1-18b. Provided that the reference crystal quality is good enough (Tanner, 1977), the angular width of the rocking curve is a measure of the defects and strain present in the test crystal. The width of the rocking curve at half peak height -the half width - can be calculated from first principles using structure factors, and the angular beam spreads (Deslattes and Paretzkin, 1968; Batterman and Hildebrandt, 1968), where useful intrinsic half-width values, W,, for silicon are:

(b) (422) reflection from (100) silicon: = 15.4”.

w,

Observed half-widths greater than these intrinsic values measure the strain in the lattice, which may be quantified using the expression

A%

-= - A W

cot0,

(1-5)

‘1 0

where AW = (W, - Wc),that is, the difference between the measured and intrinsic half widths. In addition to the rocking curve, this X-ray method leads to topography. If the sample is rotated into a position where the signal is at a half-height value, and then the detector is replaced by a photographic plate, contrast across the image originates from the variations in signal intensity caused by localized strains around defects in the surface of the sample. Carbon is a smaller atom than silicon and its substitution in the crystal leads to local strain, which, developed in the whole slice topograph (Fig. 1-1I), shows its radial distribution. In both rocking curve and topography applications, the X-ray penetration depth is limited to no more than about 30 pm,

(a) (115) reflection from (111) silicon: W, = 6.3”, X-ray source

I1

Rockino curve h d t h

/ 01

0 : L

r

'a 5

and therefore the method is usually coupled with etch removal of known depths, to build up a total picture of the damage. Applied to slicing, Fig. 1-19 shows the X-ray topograph of a step-etched sawn slice, and the associated step site density versus depth plot. In this case most of the sawing damage is confined within about 20pm depth beneath the surface. This is confirmed by the rocking curve plot shown in Fig. 1-20. Some low level of point damage sites persists beyond 20 pm, not readily

Initial, a s sawn, values 80 - 120s

I

0

5

I

I

I

I

10 15 20 25 Depth o f etch per side Iprn)

Figure 1-20. The depth of damage beneath a sawn surface measured by the etch/)(-ray rocking curve technique (A" = W, - WJ.

d

Figure 1-19. X-ray topography of a sawn and step-etched slice. Reflection: {220}, Mo KELradiation.

seen in the topograph, but detected by the signal integration inherent in this measurement. When both sides of a slice are examined it is usually found that the damage levels are different, and that the slice is bowed. It is important to distinguish between transient and permanent bow. The surface damage in a silicon slice can be pictured as an abrasion by surface cracking along the weaker bonded (111) planes, with the stress caused by the wedging open of microcracks by abraded debris. The annealing of an abrasion scratch at 1100"C for 30 min, examined by interference contrast microscopy in Fig. 1-21 a, reveals the (111) slip lines, while the topograph in Fig. 1-21 b shows the stress relief by plastic flow, creating an array of long dislocation loops on slip planes on either side of the scratch. Thus, in the presence of differential damage between two surfaces a slice bows - hollow on the least damaged side. If the bow, B, measured as the maximum depth of the hollowed side of the slice, diameter d, is taken to have a uniform radius of curvature, r = d2/(8B), then the relation between bow and strain (Tamura and Sunami, 1972), is given by c=--

16tSiB 3 d2


Figure 1-21. Surface damage in silicon. Annealing of an abrasion scratch in a { 11 I } orientation polished slice (1100°C for 30 min). (a) Interference contrast microscopy revealing slip relief along { 111) planes. (b)X-ray topograph showing the stress relief by plastic flow, creating a network of long dislocation loops on j l l l } slip planes on either side of the original scratch.

39

At temperatures below around 500 "C elastic deformation leads to brittle fracture as E > 5 x lo3, at a stress in the silicon > lo9N m-'. At higher temperatures, the elastic bending gives way to plastic deformation as the stress is applied, shown in the plot of Fig. 1-22. Since both silicon and germanium are hard brittle elements of the diamond cubic lattice structure, from the outset of the semiconductor industry diamond sawing has remained the prime route to slicing ingot material. Initially the sawblades were steel discs, slotted around the periphery, into which diamond grit particles were pressed. Such saw discs when rotated at high speed around 1500-2000 rpm, with water as a coolant, cut both germanium and silicon well. However, to cut thin slices accurately such blades have to be thicker than the wanted slices, and this is obviously very wasteful of the crystal material. As a result, these peripheral blades were rapidly superseded by internal diameter blades. Thin high tensile rolled steel sheet is punched out into large discs with a central hole around which a band of diamond of closely controlled particle size is electroplated. This blade is clamped into a mounting frame which is stretched over an outer ring in high tension, sufficient to enlarge the central diamond saw hole to-

1500

+ rn L W

a

Elastic d e f o r m a t i o n

01

I

lo7

I

1

1

1

1

I

I

I

I

I

1o8 Yield s t r e s s

(Nm-*)

OhP

d

Figure 1-22. Deformation and fracture of silicon resulting from mechanical stress. Note: For silicon Y/(1 - P ) = 1.8 x 10" (N rn-'). and so, approximately, thc stress/strain ratio is 2 x 10" ( Y :Young's modulus, P: Poisson's ratio). Hencc for cxample at a stress of lo8 N m-' the corresponding strain is 5 x

40


wards its elastic limit, so providing a thin but extremely rigid blade, capable of very precise slicing with minimum kerf loss of material. Very considerable effort has gone into the development of the internal diameter sawing machines and blades to meet the continuing scaling up of slice diameters. When an internal diameter diamond blade, stretched in tension over an outer ring and rotating at high speed, is driven forward into silicon to saw a slice, the tension is slightly relaxed and the blade vibrates (wobbles) slightly. The ingot on one side of the kerf slot is rigid, whereas the partially cut slice on the other side of the sawblade can relax a little. As the blade edge vibrates, the diamond on its sides impacts against the ingot and slice, causing differential damage, where, on the next cut, the newly exposed ingot surface becomes the other side of the next slice. Such slices may be cut perfectly uniform in thickness but bowed, until they are etched to remove the damage before polishing, when they relax to a very low bow value. On the other hand, if a blade is mounted and run incorrectly, so that it deflects during slicing, no amount of subsequent etching can correct the ensuing permanent bow. The forces which are generated at the blade edge during sawing can be followed by mounting the ingot on a dynamometer attached to an x --y - z - t chart recorder. The forces F,, Fy,and F,, measured simultaneously as the blade traverses the full diameter of the ingot, are related to the operating conditions. Typical results, looking at variable cutting rates, are shown in Fig. 1-23. Here F, is the direct loading force between the advancing ingot and blade, Fy is the tangential, dragging, force along the blade periphery, and F, is the smaller, but very important, vibrational force perpendicular to the blade. At a low feed rate the

saw is only in gentle contact with the silicon and free to vibrate; then, as the feed rate is increased towards its optimum, the blade is held more firmly and vibration decreases. . . and on the slices sawn so does the bow. Finally, as the feed rate is set too high, the pressure between the ingot and the blade begins to relax the blade tension, F, starts to rise again and the bow becomes severe. Taken further, beyond its stress limit, the blade ruptures. The role of the cutting fluid, “lubricant”, can also be studied. As an example: at such high rotation rates, around 2000 rpm, centripetal forces rapidly remove the cutting fluid from the blade edge, and the liquid film whose thickness should provide a cushion against F, is very thin. The long chain molecule polyethylene glycol both improves the streamline flow of high speed liquids and increases their viscosity, so maintaining a thicker film. Applied to silicon slicing under otherwise optimum feed conditions, the F, is halved, and the bow reduced even more. Today it is recognized that the slicing quality, which is hardly ever seen by device customers, is the key to performance, yield, and rework, in all the following polished slice manufacturing steps, and has a major impact on the overall production costs. Vendors internal sawn slice specifications always have tight tolerances on flatness, bow, and mean thickness distribution. Grinding is used at three stages in the progress of a slice into devices. Near the end of fabrication, prior to assembly, slices are back-ground substantially to reduce their thickness. In the process the slices move sideways under a spinning diamond loaded cup grinder, where the loading conditions are somewhat akin to sawing, in that material is removed parallel to the surface, and the perpendicular damaging forces into the slice are kept low. In fact,


41

-

5-

I

m

.c_

31 2

. I =

+ u

; 1 W

L c

m

O

3-

8-1 c W ._ - -2 L

c W

5u - 3

-;"-&I W

t 01

1

1

n I

1

1

Jo

vr

-5-

-3

3 4 5 Saw feed r a t e (cm min-') 2

(a)

-2

-1

0

1

2

3

Saw blade deflection (pml

(b)

Figure 1-23. Damage during silicon slicing. In (a) the force measurements and bow were recorded using distilled water as the cutting fluid ( 0 Fx, x F,,, + F,. o bow). The effect of replacing this by a 1YOsolution of polyethylene glycol (6000 mol wt.) is seen in a force F, (A) of 0.04 N, and a bow ( 0 ) of under 10 pm. Subsequently in (bf it is necessary t o etch the sawn slices to reveal the true distortion associated with blade deflection. + marks the zero bow, zero saw blade deflection intersection of the two axes.

the output surfaces, which will meet no further high temperature processing, have a semiglazed finish. Moving back into wafer manufacture, after sawing, the slices are edge-rounded to avoid the chipping which in automatic handlers leads to particle problems in clean lines. For this a spinning diamond loaded wheel is used, shaped to the desired edge profile, against which the silicon slice is itself slowly rotated. Before this, the first grinding stage the silicon meets is that of grinding the as-grown crystal into a cylindrical rod, prior to slicing. Again, the spinning diamond wheel traverses along the ingot, minimizing the forces into the silicon. Both of these stages introduce damage around the periphery, which has to be removed by etching. During later device processing the slice meets several high-temperature stages in which, if residual peripheral damage is still present, the heating and cooling gradients will lead to slip, and yield losses. This is

shown in Fig. 1-24. Here the transistor printout marking of rejects on-slice at Test1 , matches the slip, revealed by etching the back of a slice, which had been inadequately etched after grinding. After ingot

l a)

lbi

Figure 1-24. Device failures from slice fabrication. The Test-1 printout on-slice of UHF transistor rejects in (a) is linked directly to the process induced crystallographic defects revealed by selectively etching the reverse back face, seen in (b). Note the high incidence of failures initiated from the periphery, particularly near to the reference flat, contributed to by insuffcient ingot etching after grinding.

42


grinding, slicing, and edge-rounding, it is normal to etch off around 40 pm from the surface (80 pm thickness; 80 pm diameter), before going on to the polishing stage. For the back surface of the slice this etching defines the final finish, normally specified damage-free, unless some extrinsic gettering is required (see later). Its texture may be defined as “polished”, or “semi-matt” to customer choice. Various etches are used for this purpose. Lapping is a very different issue. While it is used after slicing to provide slices of the close thickness uniformity necessary to proceed on to etching and polishing, to remove any saw marks, and to improve the planarity and parallelism, fundamentally it is a retrograde process. The abrasive pressure is directed directly into the silicon surface. Under very low load, in hand lapping, the depth of damage generated is proportional to, but somewhat greater than the abrasive particle size (Buck and McKim, 1956).When the pressure is increased, as is necessary to achieve useful stock removal rates from commercial lapping machines, both the depth of damage, and the site density, rise steeply - under normal operating conditions to at least 3-4 times particle size. For example using a 20 pm, close particle size distribution, water classified alumina, WCA, at a load of 30g/cm2, the damage extends to a depth of around 90 pm - worse than in the original sawn slice. Where lapping is part of the slice machining, deep etching is needed subsequently to remove the subsurface structural damage it has caused. The issue of residual mechanical damage and flatness requirements in the large slices, of diameter 200 mm and above, required for the latest ULSI microprocessor and memory chip applications has focused attention on the lapping process and possible alternatives. The new standards of flat-

ness in the final polished wafers are now measured in nanometers (1 nm = m = 10A). This is needed because, in the fabrication of ULST circuits, the lithography uses submicrometer dimensions, with minimum feature sizes currently around 0.5 pm but decreasing and expected to be down to 0.15-0.2 pm before the century’s end. Associated with these dimensions, the thickness of gate oxides is now already down in the region of 200-100A, with close tolerances of k a few angstroms, and is also decreasing. Thus the underlying substrate surface has to be polished to commensurate values, with overall flatness within some tens of nanometers. Again, in processing these large diameter slices through the furnacing stages, thermal stress is a serious issue, pointing to the need for even greater attention to the effects of residual mechanical-damage-related defects (Wanatabe, 1991). This reference includes tables of current, and prognosed, specifications for ULSI wafers, and a useful glossary defining measurement terms, such as TTR. The back grinding of fabricated slices under a spinning diamond loaded cup grinder described above produces very flat surfaces, and as explained, since it removes material by a sideways motion there is very little damage driven into the wafer, compared to that generated by lapping. As an alternative to lapping, this process looks increasingly attractive, and new nanogrinders have been developed. These are built very rigidly to minimize vibration and maintain very low surface roughness and damage, while the feed mechanism can index in nanometer steps, starting off coarser but ending with very small increments. Sawn slices when nanoground on both sides exhibit a very high degree of parallelism and flatness. The subsurface


crystal structural damage is also shallow in depth, facilitating the subsequent etching and polishing stages. In order to assess the final surfaces of ULSI wafers, matching advances in the metrology apparatus now permit measurements at nanometer levels for production control, and these show that the nanoground material, with a near mirrorlike finish, can be flat overall across a 200 mm diameter to TIR values well under 100 nm. Comparing this to earlier previous standards, e.g. for 100 mm diameter wafers TIR values in the 1-3 pm range were common, the high standards now required can be appreciated. In reply to this challenge there have also been some advances in lapping techniques, with more attention being paid to abrasive quality in the particle shape and size distribution, operating process pressure and procedures, and in the construction of lapping machinery aimed to give flatter output. The economic cost differences between these contrasting processes have also to be taken into account in this highly competitive field. However, as tolerances continue to get tighter with respect to both metrology and damage levels, and as diameters further increase, nanogrinding is seen as a significant advance. Finally is should be noted that in research another new technique, atomic force microscopy, is being applied to the study of silicon surfaces at the nanometer level. Overall, mechanical damage in silicon is a serious issue, and closely linked to the material performance during device manufacture.

1.6.2 Polishing and Cleaning These will only be covered in outline since, although very important, much is concerned with practice and choice of materials, rather than underlying semicon-

43

ductor science. Silicon is a very hard, diamond type, element, but extremely chemically reactive, and is always covered by a native oxide, normally around 2 0 A in thickness. The materials used to polish it are all much softer, and the process employed is chemical-mechanical in nature, operating across the native oxide (Walsh and Hertzog, 1963), the Monsanto Syton patent. In principle therefore, while silicon is removed, there is little or no lattice damage generated. A three stage process is common. In the first stage an alkaline colloidal silica slurry is used with a fairly hard but porous bed pad. The silicon slices are mounted in groups on rigid very flat discs, generally by wax-mounting, but sometimes by a waxless process (against backing pads whose micropores act as vacuum suction points). These discs, which are driven in rotation themselves, are pressed into contact with the rotating bed pad, fed with the slurry, where fast stock removal occurs, around 1.O pm/min at SO- 60 “C. The temperature, monitored on the bed plate surface, is controlled to stay within close limits, initially by heating, but then later, as the process itself generates heat, by applying cooling to the bed and slice mounting plates. The pressure removes oxide from higher points on the slices, while the hot alkaline slurry dissolves the freshly formed, and chemically reactive, oxide- hydrated silicate film, generated by the reaction between the silicon and the high-pH slurry solution. About 20-25 pm may be removed at this stage, resulting in a surface having a highly polished appearance, free of all residual “orange peel” from the etched surface, haziness, and scratches. After being rinsed in deionized water, the mounted slices are transferred to a second similar polishing machine, which has a

44


softer bed pad, uses a gentler slurry of near neutral pH, and operates at lower pressure and around room temperature. After a somewhat shorter second polishing period, around 10 min, only a small extra amount of silicon is removed (1 -2 pm), but this delivers the final defect-free surface. In the third stage on the same machine, pressure is relieved so that the slices are almost free floating and the second stage slurry is replaced by a “haze supressant”, a complex organo-silicate, diluted in a glycol-water medium, which contributes to hydrophobicity, and clean liquid drainage from the slice surfaces, leaving no marks as they are removed at the end of the process. The fine tuning of the polishing process, to reach the very high standards demanded, involves considerably more variables and detail than given in this outline. This chemical-mechanical polishing combines both the mechanical process necessary to achieve flatness to micrometer tolerances, and a chemical process to ensure a final crystallographic perfection with undisrupted atomic structure free of all damage. The final cleaning and packaging are similar to polishing in their emphasis on the materials used and the practice. Again in outline, the first step after polishing is to remove any traces of polishing slurries, waxes, and organics by means of degreasants, and/or organic destruct routes, using, for example, hot nitric acid, followed by washing in deionized (DI) water. The emphasis in the final clean is on the removal of every trace of surface contaminants, metals, etc., and particles of whatever form. Kern and Puotinen (1970) first described the, subsequently widely used, RCA cleaning process. All the chemicals employed have to be of electronic grade, and membrane filtered to very low submicrometer particle counts, as is the DI water. Much

depends on the performance of soft-pad slice scrubbers, and single slice spinners, operating in a cassette-to-cassette mode, while robotics are finding increasing use, in Class 10, and lower, clean surroundings. In routes where hydrophobic slices are required, an HF dip is inserted, but where the, more normal, hydrophilic surface is wanted, the ammonia-peroxide treatment has become common, before the final DI water scrub-rinse-spin-dry schedule. Cassette packaging in multicomponent ultraclean boxes completes the wafer processing. The impact of ULSI requirements on these stages has been as demanding as elsewhere. At the polishing stage much attention has been paid to the machine bed construction to ensure that slices do not have their flatness degraded during the process. Then the process itself has been modified, essentially with the aim of reducing the temperatures and pressures used at all stages to achieve gentler processing. Pads and slurries have been improved; now instead of feeding slurry onto the machine in small quantities, flooding from a recirculating tank is used to ensure that adequate compound reaches the central area of large diameter slices. The comments on cleanliness given above are reinforced, and even more attention has been given to assay methods to test for impurities in chemicals to ultralow levels of detection in order to meet the very low surface metal ULSI targets of below lo9 atoms/cm2.

1.7 Oxygen in Czochralski Silicon 1.7.1 The Behavior of Oxygen in Silicon The dissolution, evaporation, and fluid flow, dynamic balance, controlling the incorporation of oxygen into silicon described in Secs. 1.5.3 and 1.5.4, above ig-

1.7 O x y g e n in Czochralski Silicon

nored its distribution coefficient. Under such growth conditions this is not easy to determine, and past estimates have varied widely, from ko = 0.5 to 1.4. Current views that it is less than 1.0 are supported by a recent study (Jackson, 1990),which arrived at 0.7. While carbon enters the lattice as a substitutional impurity occupying a silicon site, oxygen does not, but instead enters as a bound interstitial impurity, bonding between two adjacent silicon atoms, in a structure which permits more complex vibrational modes (Newman, 1973). The broad 9 pm infrared absorption band, seen at room temperature, arises from a number of vibrational modes of similar energies. The concentration of bound-interstitial oxygen in silicon is measured by the 9 pm

45

absorption (ASTM Standard F-121), and if any oxygen is precipitated within the crystal, by heating in the range 1050-600°C, the absorption decreases. Reheating at a high temperature, > 1100"C, disperses the precipitates and restores the absorption. However, if the temperature is held at around 450 "C, any unprecipitated interstitial oxygen present forms "thermal donors", which cause major resistivity changes in the crystal. This thermal behavior pattern was first established by Kaiser et al. (1956) and then expanded (Kaiser, 1957; Kaiser et al., 1958). Long Czochralski crystals, which are grown over a period of many hours, slowly withdrawing into a cooler chamber, experience a different thermal history between the seed and tail ends, depicted in Fig. 1-25. Heat losses:

Conduction along c r y s t a l and convective t r a n s f e r from surface t o gas

.,oooc

fi

-

Heterogeneous and homogeneous nucleation

Precipitate g r o w t h

Carbon via

900°C/ Oxide precipitation 1000oc

on nuclei-C, or condensing i n t e r s t i t i a l s

/ /

High temperature radiation

f a u l t defects high Si i n t e r s t i t i a l concentration

and convection Oxygen dissolution into melt a t wall

Figure 1-25. The variable thermal history of an as-grown Czochralski silicon crystal.

46


This has direct device effects; for example, a difference in leakage current yield losses of 16 k DRAM chips has been linked to the slice cutting location, reported by Steinbeck (1980 a, b). Other studies have shown device failures associated with crystal defects, either present at the start of the fabrication process or formed during it, and also linked to the oxygen status. From defect etching studies, many observers noted that where a high density of surface defect features (e.g., oxidation induced stacking faults, seen after the first furnace step) was found on one side of a slice, the opposite face had a very low density. In one direction, this was soon linked to residual damage remaining after slice polishing. Similar work demonstrated the relation between oxidation-induced stacking faults, the slice heat treatment temperature, and oxygen precipitation (Matsushita, 1982). Much device engineering research has explored the generation and supression of oxidation-induced stacking faults during fabrication (Stimmel, 1986), but to work bulk silicon it is necessary to understand the basic precipitation mechanism.

1.7.2 The Precipitation of Oxygen in Silicon The maximum amount of oxygen grown into a crystal at its top (seed) end, is such that, as it cools below about 12OO0C,the concentration exceeds the solid solubility limit (Carlberg, 1986), and precipitation of a second, silicon oxide, phase may be expected at any lower temperature. Solid state reactions proceed at far slower rates than in liquids or gases, so as the crystal cools, over many hours, the amount of the supersaturated oxygen which actually precipitates is so small as to be almost indetectable. It is only on heating slices cut

from the crystal, for many hours at elevated temperatures, that substantial precipitation occurs, growing from tiny initial nuclei. Research into bulk crystallization from liquids, to produce, for example, fertilizers and salts, has contributed much to nucleation concepts, and in particular the particle of critical radius r , . In a supersaturated liquid, or solid, at the outset tiny atomic clusters form and redisperse in a highly dynamic situation, but some merge and grow, until, reaching a certain critical radius, they become stable, and from then on will not redissolve. In such a process there is an initial induction period during which sufficient nuclei reach r,, then faster precipitation, which dies away as the equilibrium solubility is approached. Many systems exhibit this behavior, including the solid state precipitation of oxygen in silicon, where at 750 "C, the process has still not reached equilibrium after over 1000 h - solid state reactions are very slow. In this approach it should be expected that the nuclei formed by other impurities present will affect the initial nucleation induction step. Thus in the silicon case, the distribution of oxide precipitates across a slice after heat treatment closely maps the grown in carbon distribution shown in Fig. 1-11 (Wilkes, 1983), and also influences the actual precipitation kinetics (Kishino et al., 1979; Craven, 1981; Shimura et al., 1985; Barraclough and Wilkes, 1986). After nucleation, the main precipitation process reduces the bound interstitial oxygen concentration, developing different numbers and sizes of particles according to the temperature employed. A simple model can be used to predict the qualitative behavior correctly, and provides a basis for understanding the theoretical approach. Suppose two similar, adjacent, samples of the same impurity content, and with the

47

1.7 Oxygen in Czochralski Silicon

same high background nucleation site density, are annealed for a long time, but at different temperatures in the supersaturation range. (1) In the sample heated at the high temperature the supersaturation driving force for precipitation is low, whereas the diffusion rate of oxygen through the silicon is high. Once a few particles exceed the critical radius, rapid precipitation reduces the oxygen concentration, leading to the formation of a low density of large particles, making use of only a few of the available nucleation sites. (2) Conversely, in the sample heated at a low temperature, by the same reasoning, the supersaturation is high, but now the diffusion is low. The second phase must precipitate, but, since the oxygen only moves slowly and through a short range, a high density of small particles is predicted, making use of many of the available sites.

This is exactly what happens in practice, and if the substitional carbon signal is followed (linked to the nucleation), in the high temperature case it stays unchanged, but in the low temperature case disappears rapidly. There is an important further consequence: (3) Since the native oxide film on the surface of the silicon sample is effectively a particle of infinite radius, present at time zero, and needing no induction period, the supersaturation-diffusion model provides a simple and obvious explanation for the existance, close to the surface, of denuded zones, free of any precipitation. From the start of the heating process, oxygen close to the surface can diffuse out into the native oxide layer, so reducing its concentra-

tion and inhibiting precipitate formation in this region. The depth of this denuded zone is expected to be of a similar magnitude to the distance between particles in the bulk - deeper when formed at a higher temperature, but very shallow from a low temperature anneal. Again this is as observed in practice. In a quantitative approach, the mathematics of diffusion-limited precipitation (Ham, 1958) have been applied to the case of oxygen in silicon. The starting concentration of bound interstitial oxygen, C,, is assumed to be uniform. After a short induction period small precipitates are formed, whose density, N , remains constant throughout the remainder of the process. The particles are assumed to grow by diffusion with a spherical shape, and a common radius, ro ( t ) , small compared to the interparticle distance, and taken to be a constant corresponding to the final value r o , at t +a.The particle are a form of silica containing oxygen at a concentration C,, while that in the matrix close to the particle is C,, , the equilibrium solid solubility at the termperature chosen. The Wigner - Seitz approximation replaces the cubic cells around each particle, accounting for the total volume, by equivalent spheres of radius R , defined by (4/3)7t R 3 N = 1. The oxygen concentration profile as a function of position, and time, C (r, t ) can be represented by a Fourier series: C ( r , t )= c,, +

. exp

c 4 sin [An(r r

(- :.>

-

ro)]

n=O

(1-7)

satisfying the boundary conditions C = C,, at r = r o , and where z, is the relaxation time constant.

48


Fick's diffusion equation in spherical coordinates may be written

a2c(r,t ) +-2 ac (r, t ) ] -aC (r, t ) ar2

r

ar

at

(1-8)

while the requirement that there be no net o x y d flux across the outer sphere boundary is defined by

The oxygen distribution so described is essentially uniform, with a value slightly less than C,, throughout the diffusion volume, except in a small region of radius about 5 r,, around the particle, in what may be described as a random-walk-well model, as shown in Fig. 1-26. Further manipulation of the equations leads to two important expressions: 113

(1-14) Differentiating Eq. (1-7) with respect to r and t and substituting into Eq. (1-8) leads to the core expression given by Ham: tan [An(r-ro)] = A, r , r

=R

(1-10)

In this result A, has the dimensions of inverse length, and can take an infinite number of discrete positive values, which are the required solutions. Expanding this in a power series for small values of the argument gives 1

(1-11)

7, = __

A,zD

and 7, =

R3 3Dr,

(1-12)

~

If a particle does not nucleate, ro = 0; there is no oxygen diffusion, and the supersaturation is maintained indefinitely. Normally, after an initial transient, the first term of the Fourier series in Eq. (1-7) dominates when C(r,t) - C,, z A , A,

. exp

(-);

( - 3. 1

-

(1-13)

The constant A , 1, has the dimensions of concentration and a value somewhat less than C, - C,, .

and

If it is reasonably assumed that the oxide is close to SiO, in its composition, then a value can be assigned to C,. The values of C,, C,, , and the relaxation time constant, zo, are obtained from the infrared absorption measurements used to follow the precipitation process (Binns et al., 1983; Newman et al., 1983a; Wilkes, 1983). Hence, values for the particle density, N , and its radius, r, can be obtained at various annealing temperatures, based soZeZy on kinetic data. This can then be compared with direct measurements obtained from integrational etch pit counts, and scattering. By near infrared transmission the optical scattering from the large particles formed by high temperature anneals can be used to calculate N and r. Similarly, the very small particles, with radii less than 100 I$, can be measured by small angle neutron scattering (SANS) to validate the theoretical model (Livingston et al., 1984), as shown in Fig. 1-27. The analysis of SANS results also provides information about the shape of the particles, which has recently been allied to high resolution transmission electron microscopy, to reveal platelet precipitates, shown in Fig. 1-28 (Bergholtz et al., 1989).

49

1.7 Oxygen in Czochralski Silicon

Temperature 1100 1000 900

lo' 7.0

8.0

800

9.0

700

10.0

11.0

10L/T I K - ' )

Figure 1-26. The random-walk-well model of diffusion limited precipitation.

Only within a region of about 5 x the particle radius does a diffusing oxygen atom become trapped to a particular site and the number of particles formed is strictly defined.

Figure 1-27. Oxygen precipitation in silicon. The particle radii, and their corresponding number densities, based on the four methods shown, all assume spherical geometry. However, in the random walkwell theory the particle shape does not significantly affect the overall data given. The symbols are: o radius derived from kinetics, n radius from etch pit measurements, x radius from neutron scattering, + radius from optical scattering.

The total assembly of particle radii from these various techniques, plotted against reciprocal temperature in Fig. 1-27, shows a remarkable coherence of results, in spite of the different nature of the experimental methods and approximations involved, and the diffusion-limited precipitation theory underpins the qualitative model set out earlier.

1.7.3 Thermal Donors and Enhanced Diffusion The problems surrounding the understanding of thermal donors, their formation, and behavior, are aggravated by the lower temperatures involved, 350- 500 "C, in any kinetic study, and by the complexity

Figure 1-28. Direct lattice image of a platelike oxide precipitate in silicon. Finlike features extend above, and probably below, the main (100) habit plane. Sample annealed at 750°C for 431 h.

50


of their structure, where work suggests that four interstitial oxygen atoms are involved in a TD center (Newman and Claybourn, 1988). Following the oxygen precipitation kinetics at low temperatures requires a more sensitive method than infrared absorption; this is provided by the technique of the relaxation of stress induced dichroism (Corbett and Watkins, 1961), which has been applied to the silicon-oxygen system (Benton et al., 1983; Newman et al., 1983b). In this procedure, a small silicon rod sample, cut with a [ l l 11 axis, is heated at a temperature of 450- 500 "C, under a high pressure applied along the axis; subsequently the sample is cooled while still under stress. As a result of diffusion while stressed, the number of bound interstitial oxygen atoms, n , , linking matrix silicon sites in the [ l l l ] axial bonds becomes less than the number, n 2 , in each of the bonds in the [TIT], [Till, and [lTT], directions. If now linearly polarized 9 pm infrared light is used to measure the oxygen absorption coefficient, in directions parallel and perpendicular to the stressed [ l l l ] axis in the samples, the following relations apply:

from which (a, - c l , , ) = const . (nz- n,)

(1- 7)

When such a prepared test sample is then annealed at some chosen temperature but under no load, further diffusion allows the oxygen to return towards a random distribution, relaxing the induced stress dichroism, by a first order kinetic process, with a relaxation time constant L. Using a normalized dimensionless parameter (aI- all)/ai the constant tt is given by the slope d [log (a, - all)/a,]/dt, and is equal to t/8 where l/t is the fundamental fre-

quency of a single diffusion jump at the temperature concerned. The diffusion coefficient then follows from the simple relationship that D = a;/@ z), where a, = 5.42& the lattice constant of silicon. An early problem in the understanding of thermal donors arose from their speed of formation, requiring only a short heating time to reach an equilibrium resistivity. The role of lattice defects in this process is now recognized to be a major contributor. In their stress dichroism study, Benton et al. (1983) observed that, if the silicon was given a 900"C/2 h heat treatment followed by quick cooling to eliminate donors (but thereby freezing in excess silicon self-interstitials) before going into the stress dichroism procedure as described above, the value of the diffusion coefficient, D, was enhanced by nearly two orders of magnitude. Another way to alter the intrinsic defect balance in silicon is by irradiation. Newman et al. (1983 b) used 2 MeV electrons onto a stressed silicon sample target held on a water-cooled block at well below 60°C. After irradiation the 9 pm signal was lowered, while the generation of oxygenvacancy (0-V) A-centers was measured by their infrared absorption at 830 cm-'. On subsequent relaxation, the induced dichroism now decayed exponentially - with D several orders higher. Oxygen can also trap mobile silicon self-interstitials, to form an (0-1) center, with absorption at 935 cm-l. Tin is an efficient trap for vacancies in silicon; as-grown Sn-doped crystals have similar (0-1) center concentrations to undoped silicon, but substantially lower (0- V) A-center levels, and in this material the relaxation of stress dichroism is retarded by a factor of approximately 6. Involvement of both vacancies and interstitials in this diffusion was proposed by Gosele and Tan (1983). A simplistic view of a single jump could be that either oxygen

1.8 Crystal Engineering

traps a vacancy to form an A-center, which then intersects a self-interstitial, or, alternatively, an (0-1) center is formed, which then traps a vacancy. The reality is more complex than this. Enhanced diffusion is seen after metallic contamination by copper or iron. Carbon enters into a number of low temperature centers with oxygen and silicon, and as nucleation sites for self-interstitials (Davies, 1989). Free electron effects have been used to provide an explanation for dopant concentration-dependent thermal donor kinetics (Wada, 1984; Wada and Inoue, 1986); while in the precipitation of oxygen in heavily doped, n f and p’, silicon, Bains et al. (1990) have observed both enhanced (p’) and retarded (n’) precipitation, which they also link to the free electron model. Finally the thermal donor formation in p-type, 0.3 0 cm, material at 450°C is accompanied by the simultaneous loss of substitutional boron (Newman and Claybourn, 1988). Overall, while the diffusionlimited precipitation model provides a sound basis for understanding the behavior of oxygen in dislocation-free silicon, which is applied in the “crystal engineering” discussed next, there is still much to be learned about the detailed mechanism of enhanced diffusion and thermal donors.

1.8 Crystal Engineering In the preceding sections of this chapter, reference has been made at various points to the ability of defects to act as gettering sites, sinks, for fast diffusing impurities. Also the serious deleterious effects of such defects, where they intersect device structures, has been emphasized. In addition the very slow nature of solid-state oxygen precipitation, seen above, has to be overcome if any use is to be made of such bulk precip-

51

itates. The controlled application of external surface mechanical damage (extrinsic gettering), and internal bulk oxide particles (intrinsic gettering) is now addressed.

1.8.1 Extrinsic Gettering in Silicon Mechanical damage in a silicon surface has to be quantified in both density and depth, where as seen in Figs. 1-19 and 1-20, only a few damage sites extend to any great depth. Since etch rates are a function of the intensity of damage, they fall rapidly during the initial stages of etching, so it is very difficult to leave a well-controlled residual damage level on the back side and achieve the required slice thickness tolerances by trying to limit the etching. This also leaves more to be polished off the front surface. What is required is to create intentionally a high density of relatively shallow lattice disorder, whose associated stress relaxes into stacking faults and dislocation loops early on in the device thermal processing, to provide a high gettering capacity. The lattice distortion around the dislocations sets up strained regions, the actual gettering sites, which, in accommodating the diffusing impurities, relax further into stable lower energy atomic configurations. There are several controlled backside damage options available from polished slice suppliers, aimed to match the individual device processes: MOS, bipolar, etc. The damage is reinserted starting from well-etched slices. One method, widely used, employs a high adjustable- pressure water jet system, commonly used at around 1000 psi ( z 70 bar), which contains fine ground silica of well-defined particle size (about 1 pm). The grades of damage generated by the impingement of this jet on slices traversed beneath are achieved by varying the pressure, number of jets, and the traverse speed. Afterwards the front surface is polished in the normal way.

52


Typical site densities obtained by this treatment range between 5 x lo3 cmP2and 5 x lo7 cmP2.An example of a higher damage level slice, before and after treatment, is shown in Fig. 1-29, while the rocking curve broadening from this process is low to moderate: A W = 10’ to 30’. (Note other values: deep-etched slice 0” to 4/8“, sawn slice 80” to loo’, lapped slice A W > 120”.) Lighter damage is most suitable for MOS device processes when, during the first oxidation at around 1000- 1100“C, stacking fault gettering sites are formed on the treated back surface at a density of around lo5 cmP2, which has a negligible effect on the subsequent mechanical behavior, warp, etc. However, as device feature sizes continue to shrink, there is strong emphasis on reducing both the maximum temperatures, and the total thermal inventory, used in fabrication. At temperatures below 1000°C the stacking fault generation is more complex and influenced by the oxidation ambient (Claeys et al., 1981).Again, if the damage is too light, instead of forming getter sites on heating, a large proportion may be an-

Figure 1-29. Extrinsic gettering by silica-high pressure water jet trcatmcnt. Note the well-etched surface to remove uncontrolled damage prior to treatment, and the uniformity of mechanical damage sites generated (SEM photograph).

nealed out. This is seen when first stage polished surfaces, with some submicrometer damage, are compared by etching to reveal defects before and after an 1100 “C thermal cycle, when most of the damage sites disappear, and too low a stacking fault density results. The gettering performance, extrinsic or intrinsic, is monitored by etching the front polished surface, in which the device structures are fabricated, to reveal point defect sites: S-pits - shallow saucer etch pits, or haze, which are known to be related to the presence of heavy metal impurities, to low carrier lifetimes, and to emitter-collector leakage, which are all detrimental to yields. Again where the device process involves a number of high temperature stages, the extrinsic gettering performance gradually falls, and a higher initial damage level is necessary to counter this. For bipolar applications the same rules stand, but now the process employs higher temperatures, up to 1200”C, where shallow damage sites are more easily annealed out, and gettering performance falls more rapidly through the successive high-temperature stages. While damage depths around 1- 1.5 pm may be adequate in an MOS process, bipolar conditions can demand 2-4 pm, and even then the efficiency may be lower. Alternative approaches for inserting the mechanical back-surface damage, also widely used, are brush damage, or abrasive polishing, of the deep-etched slice, an example of which is seen in Fig. 1-30. By choice of materials and operating conditions (soft or hard brush, abrasive size, pressure, etc.) well-controlled products result, suitable for both MOS and bipolar applications. Finally, in a further development of extrinsic gettering, it has been recognized that fine grain polycrystalline silicon is an excellent, high temperature


53

resistant, gettering material. Using low pressure chemical vapor deposition (LPCVD) and a silane source, in a process closely similar to that employed during the fabrication of polysilicon interconnects, a thin, 1-2 pm, layer is deposited on the deep-etched slices, at a temperature of 600-650 "C, prior to the polishing stage, which becomes the extrinsic gettering backside of the slice. Known as enhanced gettering (EG) this additional step is obviously rather more expensive to manufacture than the other routes described for providing extrinsic gettering, but its performance, particularly in the multistage higher temperature applications, such as in bipolar circuits, is superior, maintaining very low S-pit densities, and high lifetimes, as shown in Fig. 1-31. Achieving the best results in this field involves very close liaison between the slice manufacturer and the consumer device engineer, in order to match the incoming material to the specific fabrication process.

Number of oxidation cycles

(b) Figure 1-30. Extrinsic gettering by abrasive (brush)

treatment: (a) and (b) show lower and higher damage, respectively. Note the well-etched underlying substrates.

Figure 1-31. Enhanced gettering by deposited polysilicon. Comparison between EG and mechanical backside damage (MBD) treatments. Material: Medium oxygen content, p-type, (100) orientation. Test: bipolar oxidation cycle - 1I O O T , steam, 2 h. Spits: x ; lifetime: 0 .

54


1.8.2 Intrinsic Gettering in Silicon The beneficial effects of oxygen precipitates in the bulk of a device structure, and also in the substrate of an epitaxial slice, were reported by Tan et al. (1977)and Yang et al. (1978). Now there are many papers on this topic, which, since it directly interfaces to device processing, has attracted much attention. The single stage heat treatments described in Sec. 1.7.2 are obviously far too slow to provide crystal-engineered slices tailored to meet device specifications. However, this is not the only constraint. Any useful process must make consistent intrinsically gettered slices using input silicon slices containing the varying amounts of oxygen typical of normal Czochralski growth. If insufficient of this oxygen is precipitated, there is a serious likelihood of further secondary precipitation in the vicinity of devices at some point during fabrication. Earlier work concentrated on two-step processes, with a first high temperature heat treatment, followed by a second at a lower temperature, the so-called HI - LO, treatment. Typical times and temperatures used are: 16 h a t 1150°C and 64 h a t 650°C (Yamamoto et al., 1980). While other variants of two-step treatments have been proposed, this HI -LO process shows the principles, using the models developed in Sec. 1.7.2 above. In the first step, the high temperature, 1150 "C, anneal is in a range where the supersaturation of bound interstitial oxygen is relatively low but diffusion high; any preexisting microprecipitates near the surface tend to dissolve. Oxygen readily diffuses to the surface oxide, so developing a concentration gradient near the surface, while deeper in the bulk, precipitates start to form.

In addition to conventional analysis methods, for example, by a SIMS profile on a cut section through the slice, the concentration gradient from the out-diffusion can also be measured by reheating the sample at 450"C, to generate thermal donors from the remaining interstitial oxygen, and then making a microresistivity scan on a beveled section, to calculate the gradient profile. The results from material with a bulk value [Oil around 8 x IOl7 cm-2 show the surface concentration falling to around 5 x 1017 after 6 h, with a precipitate denuded zone 20pm deep, while after 16 h the values are around 3-4x 1017 with a denuded zone up to 50 pm deep. While the interstitial oxygen content is lowered at step 1, in the following low temperature step 2 at 650°C the supersatura'tion is still high and precipitate growth continues at the sites formed at step 1 but there is little added fresh bulk nucleation. The desired intrinsic gettering structure, bulk precipitates and a surface denuded zone, is achieved - but there are problems. The amount of bound interstitial oxygen precipitated by this process, and whether or not a denuded zone is formed, are a direct function of the original oxygen content, as shown in Fig. 1-32. In addition, in this plot the wider scatter of results from material of lower initial oxygen content reflects the effects of other contributory factors. For example, in the influence of carbon on nucleation, where using material of normal high oxygen content but ultralow in carbon, < 3 x lo1' atoms/cm3, the precipitation is heavily retarded, and there is no denuded zone formation (Wilkes, 1983). The effects of not precipitating enough oxygen have been demonstrated by de Kock (1982),who found that, during an n+ phosphorus diffusion into an epitaxial layer, under the diffused region the denuded zone


-E

No denuded !

Denuded zone

A

I 0 %

I

+

I

'

I

I

I

I

I

7.0 10.0 8.0 9.0 Initial oxygen concentration [O,I(1017*)

cm3

Figure 1-32. Two-stage oxygen precipitation in silicon. Thermal cycles: 1 1 5 0 T , 16 h; 650"C, 64 h. Other two-stage processes exhibit similar behavior, with no denuded zone formation below an initial oxygen concentration of around 8 x lo" atoms/cm3.

width shrank, in one case from 50 to 25 pm, in another from 25 pm to zero. His interpretation of the denuded zone shrinkage under the diffused islands is that the rapid formation of critical nuclei and secondary precipitation is due to the local injection of a large excess of silicon self-interstitials. This links to the diffusion jump mechanism and enhanced diffusion described in Sec. 1.7.3. Such secondary precipitation is quite general, and may build up throughout a multistage process, rather than at one particular step. Again, during lower fabrication temperature CMOS device processing, using substrates of medium to high oxygen content, difficulties are often encountered because of thermal donor formation, which make voltage threshold adjustment steps necessary. Reducing the residual oxygen concentration eliminates this problem. Thus, while many intrinsic gettering studies have concentrated on the aspects of denuded zone depths, and the precipitate sizes and number densities, the residual bound interstitial oxygen concentration present afterwards is

55

a crucial performance parameter. Some two-step gettering processes rely on the first oxidation in the MOS fabrication line, at a temperature of 1000-1100"C, to provide some further precipitation, but as the oxides required get thinner, and oxidation times shorter, this is insufficient. A much better intrinsic gettering process, which overcomes these problems and permits matching, to optimize the material characteristics to individual device lines, is provided by a three-step system which separates control of the desired parameters. The concepts are illustrated in Fig. 1-33, which shows the purpose of each step. The highest oxygen concentrations, normally met at the top of Czochralski crystals, are around 1 x 1018atoms/cm3 which corresponds to a maximum solid solubility temperature of approximately 1200 "C, lower for the remainder of the crystal which contains less oxygen. In step 1 the slices are heated at a temperature chosen in the range 1100- 1200"C, above the solid solubility values for most slices, while even in the "worst cases" the supersaturation is very low. There is no precipitation and any pre-existent grown-in nuclei (Fig. 1-25) are dispersed, to ensure that all the material is in a uniform state. Out-diffusion reduces the oxygen content substantially as described above, the time, commonly in the range of 5-10 h, defining the chosen depth of the denuded zone to follow, Fig. 1-33 a. Next, in step 2, the slices are given a low temperature heat treatment, for example, at 750°C for times between 5 to 30 h. In accord with the theory a large number of small nuclei form and begin to grow slowly, except in the reduced oxygen content layer close to the surface, where very few are formed, any that are being of very small size, Fig. 1-33b. The assemblage so produced has a statistical particle size distribution, increasing slowly as longer times

56


1011 2

-.v)

W

u c

m L

a .e 0

d z

Particle size

Distance from surface X

I ‘;lICCCl

(a)

(C)

I

Temperature


(d)

(b)

I

I 1 !

Oxygen diffuses t o growing

Denuded; zone !e

Figure 1-33. Three stage oxygen precipitation in silicon. Crystal engineering: (a) stage 1: outdiffusion of oxygen to surface at 1100°C; (b) stage 2: nucleation at 750°C (c) particle size distributions at stage 2; (d) critical radius, r,, for particle growth as a function of temperature: (e) stage 3: particle growth at 1000°C.


(el

are chosen, while, as required by the Ham theory and depicted in Fig. 1-33c, their total numbers remain near constant. The concept of the stability of particles of greater than some critical radius, rc , has been introduced above. The value of this radius depends on a number of factors: (a) The surface free energy of the particle matrix interface, CT, and the volume free energy change of the precipitate, AF, (Burke, 1965), where y

20 AF,

=-

(1-18)

(b) The degree of supercooling, AT, the difference between the chosen anneal temperature, T, and that higher temperature at which the solute oxygen concentration, C,, is at saturation equilibrium, and the activation energy, E,, for the formation of a nucleus of the critical radius, are related by

N , = c, exp

(- &)

(1-19)

where N , is the concentration of precipitate particles.

57


(c) The volume free energy is related to the supercooling and the enthalpy of reaction, AH, by

AFv =

($)

AT

(1-20)

Finally the surface free energy for the precipitate-matrix interface is obtained from 3 E, (AFv)2‘ I 3 1671

.=[

]

(1-21)

Values for critical radii have been calculated for various temperatures and degrees of supersaturation (Freedland et al., 1977; Osaka et al., 1980).These are all very small, ranging from around 108, at a temperature of 1050”C, which corresponds to nuclei containing clusters of about 100 atoms, down to only 3-4 8, and clusters of 6-10 atoms at 650°C. While these numbers are very small, it should be remembered that the final precipitates grown at 650”C, while of platelet structure, have an “equivalent” spheroid radius of only around 30 8, (see Fig. 1-27).The form of the temperature dependence of the critical radius is shown in Fig. 1-33d. Further extension of this model to the rates of nucleation leads to predictions of induction times at the outset of single stage anneals, while stable nuclei are being formed, in accord with observations (Capper et al., 1977; Hu, 1981; Inoue et al., 1981). However, the important point to note is that the critical radius is temperature dependent, and at 7 5 0 T is much smaller than at 1000°C. Therefore, when in stage 3 the slices are heated for some hours at 1000°C most of the small particles generated at stage 2 redissolve, leaving only those at the upper end of the statistical distribution to continue to grow. A longer heating time at

stage 2 leaves more larger nuclei so this stage defines the number density of particles from the overall precipitation process. The final stage then determines how much of the oxygen initially present is to be precipitated, and so the particle size, see Fig. 1-33e (Wilkes, 1988). The matrix of Fig. 1-34, taken from the work of Huber and Reffle (1983), shows this three-stage process in operation. All the slices were given the same stage 1 out-diffusion of 10 h at 1100 “C then groups were nucleated at 750°C for increasing times, before the final precipitate growth at 1000°C again for 4 increasing times. The expected pattern is seen with all having about the same denuded zone depth, while the particle density increases with stage 2 time, down the figure, and the particle size with stage 3 time, from left to right across the figure, in a well-controlled manner. The ability of the three-stage process to handle a wide range of input oxygen concentrations is shown in Fig. 1-35 in comparison with two-stage results, where the high and consistent reduction in the initial oxygen level achieved ensures minimal further precipitation during subsequent device fabrication. In summary then, a three-stage intrinsic gettering process can overcome the earlier problems met in two-step methods. It accepts a wide input oxygen range, and the functions are separated, with stage 1 defining the denuded zone, stage 2 the particle density, and stage 3 the particle size and the total amount of supersaturated bound interstitial oxygen removed from solid solution. The three stages allow the parameters to be varied to meet individual customer requirements to match the material to the specific device fabrication process. Entering the ULSI era, it is becoming even clearer that close links between the silicon suppliers and the users are essential. -

58


Figure 1-34. A three-stage precipitation matrix. Note the clear separation of stage functions defining: (1) the denuded zone depth, (2) the number density, and (3) the precipitate size. Stage (1) was outdiausion at 1100°C for 10 h. The initial oxygen concentration was 8.15 x 10” atoms/ cm’. (By kind permission of Huber and Reffle, 1983.)

The crystal engineering of large diameter wafers has been noted previously in regard to the rising demands for the control of the oxygen level in p + and n + substrate materials, in addition to the attention already paid to this in normal p and n silicon. Full intrinsic gettering procedures as described

above are still not as widely adopted as might have been anticipated, although delivery of partially heat treated wafers in now common. On the other hand, forms of extrinsic gettering are quite widely used, and the market for enhanced gettered material appears to be growing steadily. After

1.9 Acknowledgements

59

Figure 1-35. The reduction in bound interstitial oxygen after two-stage (0)and three-stage annealing ( x). The markcd superiority of thc three-stage process is obvious. Initial oxygen concentration 1 1 0 ’ ~atoms/cm’)

many years of research and development fully crystal engineered wafers are now widely available incorporating both extrinsic and intrinsic gettering in combinations to achieve the highest possible performance. As in the other sectors examined in this chapter, in wafer manufacture the market pressures have been linked closely to the advances demanded in the technical attributes engineered into the material. Knowledge of the interaction between crystal microdefects and impurities, and device fabrication and performance has increased dramatically, and has impinged on the whole process, from crystal growth onwards, which has become more and more specialized, in the hands of the high capacity merchant producers. It is here, where the closest collaboration between the silicon material vendors and the device makers is most essential, that the combined economic and technical pressures from the Far East have been the most severe.

1.9 Acknowledgements The work described here represents over 30 years of continuing research and development. The author is indebted to his many colleagues in the Materials Departments at Philips/Mullard, Southampton for their years of valued, exciting, and enjoyable, support. Particularly I must record my thanks to Dave Perkins, Roland Kingsnorth, Dave Griffiths, and Ian Baldwin, and, for their encouragement, to Stan Bradshaw, and Dr. Max Smollett and Dr. Brian Avient. I also wish to recognize our long collaboration with the U.K. teams led by Prof. Ron Newman (Reading University), Dr. Keith Barraclough (RSRE, Malvern), and Prof. Ed Lightowlers (London University), in a wide range of joint projects. The contributions to my understanding of the silicon field from many friends in the major equipment and materials suppliers, and device houses around the world must be noted. In particular, Bob Lorenzini (Siltec), Remo Pellin and Gordon Martin (Monsanto), Ken Jackson (Bell Labs.), Ed Giess (LBM),and Don Jackson (Motorola),

60


have shared and discussed new developments over a long period. The close links with Dr. Erhard Sirtl and Dr. Dieter Huber (Wacker Chemitronic) have contributed directly to the preparation of this chapter. Figure 1-34 (first published by Wilkes, 1983) came from the work of Huber and Reffle, and was reproduced with their permission, while Horst Fleischmann has been-a prime source for my awareness of the market pressures and industry trends.

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Suzuki, T., Isawa, N., Okubo, Y., Hoshi, K. (1981), in: Semiconductor Silicon 1981, Huff, H. R., Kreigler, R. J., Takeishi, Y.(Eds.). Pcnnington, NJ: Electrochcm. SOC.,PV81-5, p. 90. Tamura, M., Sunami, H. (1972), Jpn. J. Appl. Phys. 11, 1097. Tan, T. Y, Gardner, E. E., Tice, W. K. (1977), Appl. Phys. Lett. 30, 175. Tanenbaum, M., Mills, A. D. (1961), J. Electrochem. SOC.108, 171. Tanner, B. K. (1977), X-Ray Diffraction Topography. Oxford: Pergamon, p. 50. Taylor, P. A. (1987), Solid State Technol. 30, No. 7, 53. Taylor, P. A. (1988), J. Cryst. Growth 89, 28. Teal, G. K., Buehler, E. (1952), Phys. Rev. 87, 190. Theurer, H. C. (1952), Patent USP 3060 123. Theurer, H. C. (1956), Trans. AIME 206, 1316. Thomas, D. J. D. (1963), Phys. Status Solidi 3, 2261. Tokumaru, Y., Ohushi, H., Masui, T., Abe, T. (1982), Jpn. J. Appl. Phys. 21, 443. Townley, D. 0. (1973), Solid State Technol. 16, 43. Wada, K. (1984), Phys. Rev. B 30, 5884. Wada, K., Inoue, N. (1986), in: Semiconductor Silicon 1986: Huff, H. R., Kolbesen, B. O., Abe, T. (Eds.). Pennington, NJ: Electrochem. SOC., PV86-4, p. 778. Walsh, R. J., Hertzog, A. H. (1963), Patent USP 3 170 273. Wanatabe, M. (1991), Solid State Technol. 34, 69, 133. Wilkes, J. G. (1959), Proc. IEE 106B. Supp. 17, 866. Wilkes, J. G. (1983), J. Cryst. Growth 65, 214. Wilkes, J. G. (1988), Trans.-Inst. Min. Metall. 97, C 72. Wilkes, J. G., Perkins, D. W. (1971 -72), DCVD Res. Rep. RP6-62. London: Ministry of Defence. Witt, A. F., Herman, C. J., Gatos, H. C. (1970), J. Mater. Sci. 5 , 822. Yamamoto. K., Kishino, S., Matsushi, Y. Iizuka, T. (1980), Appl. Plzys. Lett. 36, 195. Yang, K. H., Kappert, H. F., Schwuttke, G. H. (1978), Phys. Status Solidi A 50, 221. Yatsurugi, Y, Akiyama, T., Endo, Y., Nozaki, T. (1973), J. Electrochem. SOC.120, 985.

Yusa, A,, Yatsurguri, Y., Takaishi, T. (1975), J. Electrochem. SOC.122, 1700. Zeigler, G. (1961), Z. Naturforsch. 16a, 219.

General Reading Brice, J. C. (1973), The Growth of Crystalsfrom Liquids. Amsterdam: North-Holland. Einspruch, N. G., Huff, H. (1985), V L S IElectronics, Vol. 12: Silicon Materials. London: Academic. Gupta, D. C. (Ed.) (1983, 1984), Silicon Processing. Technical Publications 804 and 850. Philadelphia, PA: ASTM. Hurle, D. T. J. (1993), Crystal Pulling from the Melt. Heidelberg: Springer. Mikkelsen, J. C., Corbett, J. W., Pearton, S. J., Penneycook, s. J. (Eds.) (1986), Oxygen, Carbon, Hydrogen, and Nitrogen in Crystalline Silicon. Mater. Res. SOC.Symp. Proc., Vol. 59. Pittsburgh, PA: Materials Research Society. Ravi, K. V. (1981), Imperfections and Impurities in Semiconductor Silicon. New York: Wiley. Stavola, M., Pearton, S. J., Davies, G. (Eds.) (1988), Defects in Electronic Materials. Mater. Res. SOC. Symp. Proc., Vol. 104. Pittsburgh, PA: Materials Research Society. Sze, S. M. (Ed.) (1983), VLSI Technology. New York: McGraw-Hill. Wolf, S., Tauber, R. N. (1986), Silicon Processing for the V L S I Era, Vol. 1: Process Technology. Sunset Beach, CA: Lattice Press. Crystals: Growth, Properties, and Applications, Vols. 1-10. Vol. 5: Freyhard, H. C. (Ed.) (1981) for F Z Si. Vol. 7: Grabmaier, J. (Ed.) (1982) for CZ Si. Berlin: Springer. Semiconductor Silicon. This series of symposia organized by the Electrochemical Society reflects the whole development of silicon materials technology and provide a very important reference and reading resource: 1969 New York; 1973 Chicago; 1977 Philadelphia; 1981 Minneapolis; 1986 Boston; 1990 Montreal. The proceedings are published by the Electrochemical Society, Pennington, NJ.

2 Silicon Device Structures

.

Chun-Yen Chang and Simon M Sze National Chiao Tung University. Hsinchu. Taiwan. R.O.C.

List of Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Potential-Effect Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 2.2.1 n+-i-n+ Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Planar Doped Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 p-n Junction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4 Bipolar Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5 Heterojunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6 Heterojunction Bipolar Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.7 Thyristors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.8 Hot Electron Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Field-Effect Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Metal-Silicon Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 Homogeneous Field-Effect Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 MOS Structure and Charge-Coupled Devices . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4 MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4.1 Submicrometer MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4.2 Silicon-on-Insulator Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4.3 Thin-Film Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4.4 Nonvolatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.5 MODFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.6 Microvacuum Field Emitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quantum-Effect Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 2.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 Quantum Wells, Wires, and Dots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.3 Resonant-Tunneling Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.4 Multiple Quantum Well Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.5 Resonant-Tunneling Hot-Electron Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Microwave and Photonic Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 IMPATT Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 BARITT Diode ................................................... 2.5.3 Photodetectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4 Solar Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8

64 67 68 68 69 70 72 74 75 77 79 80 80 82 82 84 84 88 89 90 92 93 95 95 95 97 99 99 102 102 104 104 107 109 111 111

64


List of Symbols and Abbreviations cross-sectional area doping region thickness capacitance thickness; dimensionality diffusion constant energy electric field bandgap difference between emitter and base valence band offset Fermi energy frequency maximum frequency of oscillation cutoff frequency transconductance Planck constant (ti = h/(2x)] current gain current generation current recombination current current density Boltzmann constant wave vector length z-component of the angular momentum effective mass concentration doping concentration momentum charge charge surface density junction depth resistance subthreshold slope depleted silicon film thickness absolute temperature; transmission coefficient voltage breakdown voltage volume in k-space surface depletion width W,,W,, Wsub depletion layer width of source, drain, supporting silicon substrate Z total number of states c1

Y

sum of current gain lifetime width of resonant state

List of Symbols and Abbreviations

infinitesimal thickness permittivity dielectric permittivities in silicon, metal emission efficiency wavelength; penetration depth cutoff wavelength electron mobility valley degeneracy charge density lifetime barrier lowering metal work function change in electrostatic potential heterojunction barrier barrier height for electrons in the metal; Schottky barrier electron affinity BARITT BICFET BICMOS CCD CMOS CTE CVD CW DBQW DBRTD 2 DEG 2 DHG DOS EEPROM EPROM FAMOS FIPOS HBT HET HIPOX IBT IGBT IMPATT JFET LDD LRP LT MBE

barrier injection transit time bipolar inversion-channel field-effect transistor bipolar complementary metal-oxide semiconductor charge-coupled device complementary metal-oxide semiconductor charge-transfer efficiency chemical vapor deposition continuous wave double-barrier quantum well double-barrier resonant-tunneling diode two-dimensional electron gas two-dimensional hole gas density of states electrically erasable programmable read-only memory erasable programmable read-only memory floating gate avalanche injection metal-oxide semiconductor full isolation by porous oxidized silicon heterojunction bipolar transistor hot-electron transistor high-pressure oxidation induced base transistor insulated-gate bipolar thyristor impact ionization avalanche transit time junction field-effect transistor lightly doped drain limited reaction process low temperature molecular-beam epitaxy

65

66


MESFET MIOS MOCVD MODFET MOS MOSFET MQW NDR PBT PDB PECVD QW RTA SIMOX

so1

TFT UHV ULSI VLSI ZMR

metal-semiconductor field-effect transistor metal-insulator-oxide-semiconductor metal-organic chemical vapor deposition modulation-doped field-effect transistor metal-oxide semiconductor metal-oxide semiconductor field-effect transistor multiple quantum well negative differential resistance permeable-base transistor planar-doped barrier plasma-enhanced chemical vapor deposition quantum well rapid thermal annealing separation by implanted oxygen silicon-on-insulator thin-film transistor ultra-high vacuum ultra-large-scale integration very-large-scale integration zone melting recrystallization

67

2.1 Introduction

2.1 Introduction Silicon is the most important semiconductor for the electronics industry. At present, silicon-based devices constitute over 95% of all semiconductor devices sold worldwide. Silicon’s dominance is the result of its bandgap, its superb natural oxide, its outstanding mechanical properties, and its abundance in nature. Silicon’s bandgap of 1.12 eV at room temperature is large enough to give relatively low leakage current from thermally generated carriers. Silicon is unique in that it possesses the most outstanding natural dielectric, silicon dioxide (SiO,), which has high breakdown strength (- 10 MV/cm) and low interface trap density ( - lo9 traps/cm2). Silicon is an extremely hard, unyielding semiconductor with a Knoop hardness of 1150 kg/mm2 (twice that of stainless steel) and a yield strength of 7 x lo1’ dyn/cm2 (a factor of 1.8 larger than tungsten). Silicon in the form of silica and silicates makes up 28% of the Earth’s crust, and silicon is second only to oxygen in abundance. Figure 2-1 shows the world production of polished single-crystal Si wafers and 111-V compound semiconductor wafers. It is apparent that silicon has much higher production volume due to its pre-eminent position in very-large-scale integrated (VLSI) circuits as well as numerous discrete-device applications. We anticipate that this production trend will continue. By the year 2000, silicon wafer area will reach 10 square kilometers (or about 200 million wafers with a 250 mm diameter) while the 111-V compound wafer area will be about two orders of magnitude lower (Pearce, 1988; Meindl, 1984). Semiconductor devices can be broadly divided into three groups: potential-effect

10‘1,

10’0

I

1

’ /

-

h

N

6

v

109-

W LT

Q

108

-

107 1960

1980 YEAR

2000

Figure 2-1. World production of single-crystal silicon and 111-V compound semiconductors (after Pearce, 1988; Meindl, 1984).

devices, field-effect devices, and quantumeffect devices. Potential-effect devices, considered in Sect. 2.2, are current controlled, with the control electrode resistively coupled to the active device region, and the charge carriers separated energetically by an energy barrier. Potential-effect devices include the classic bipolar transistor and the heterojunction bipolar transistor. Fieldeffect devices, considered in Sect. 2.3, are voltage controlled, with the control electrode capacitively coupled to the active region of the device and the charge carriers separated by an insulator or a depletion layer. Field-effect devices include the MOSFET, MESFET, and MODFET. Quantum-effect devices, presented in Sect. 2.4, use resonant tunneling to provide controlled transport. In such devices, the operational distance is comparable to the de Broglie wavelength (A = h/p, where h is Planck’s constant and p is the momentum), which is about 200 A at room temperature.

68


Quantum-effect devices can increase the operational speed above that achievable by the conventional potential-effect or fieldeffect devices. In addition, many quantumeffect devices are functional devices, i.e., they can perform a given electronic function with a minimum number of electronic components. Silicon microwave and photonic diodes are covered in Sect. 2.5. The operation of most of these devices is based on the potential-effect principle. Microwave diodes are two-terminal devices that can generate, amplify, or detect signals at microwave frequencies (1 to 1000 GHz). The silicon microwave diodes to be considered are the IMPATT diode and the BARITT diode. Silicon photonic devices include the photodetector, which can detect optical signals through electronic processes, and the solar cell, which can convert optical radiation into electrical energy. We expect that silicon-based devices will remain the dominant devices for electronic applications in the foreseeable future. An outlook for advanced silicon-device structures is presented in Sect. 2.6.

2.2 Potential-Effect Devices 2.2.1 n+-i-n+ Diode In Fig. 2-2a, the n+-i-n+ diode is a majority-carrier device (electron conduction in n+-n-nf and hole conduction in p+-i-p+) in which a semicircular potential is formed between these two heavily doped electrodes. The formation of the barrier is due to the electron concentration n

in the i-layer, which constitutes a charge density e in the Poisson equation.

.

.,

U

V

I

I

'

L

I

-

a

v=o

I

APPLIED B l A S f P V )

(b) Figure 2-2. Illustration of the n-i-n diode under applied bias. (a) Schematic profiles of the electric field and the electrostatic potential energy. The energy diagram also shows the quasi-Fermi level EF(x)(dashed line). (b) Calculated current-voltage characteristics (Luryi, 1990).

The I - V characteristic is shown in Fig. 2-2b, which can be expressed at high voltage as

69

2.2 Potential-Effect Devices

wherej is the current density, L the i-layer thickness, E , the permeability, zcc! p the electron mobility. Equation (2-2) is identical to the classical Mott-Gurney law (Luryi, 1990) for space-charge-limited current, and at low voltage the I - V characteristic becomes

(2-3) which represents a linear law. n(0) is the carrier concentration at x = 0. The n+-i-n+ or p+-i-p+ diode is one of the building blocks for various kinds of novel electron devices.

A

2.2.2 Planar Doped Barrier The planar-doped-barrier (PDB) rectifying structure was first demonstrated in GaAs molecular-beam-epitaxy (MBE) grown samples (Malik et al., 1980). It represents an extension (the limiting case) of the camel-diode structure. We begin by reviewing the theory of rectification and charge injection in this important structure (Kazarinov and Luryi, 1982). A PDB [n-i-6 (p+)-i-n] structure, as shown in Fig. 2-3 a, has a nearly intrinsic (i) layer of thickness L sandwiched between two n-type layers of low resistivity. In the process of epitaxial growth, a p+-doped layer of (infinitesimal) thickness 6 4 L with a doping of NA is built into the i region. Acceptors in the p+ layer are completely ionized, that is, Completely depleted of holes. A negative charge sheet of surface density Q = q NA6 gives rise to a triangular potential barrier with shoulders L , and L , and a height 4 given approximately by

(2-4) This expression corresponds to a “capacitor” model in which the fixed charge Q

o+-,

0.5 1 1.5 2 APPLIED VOLTAGE ( V )

(b) Figure 2-3. (a) Schematic illustration of the planardoped triangular barrier. (b) Calculated I V characteristics for a Si PDB diode with the following parameters: L , = 250 A, L , = 2000 A, N,, = IOl9 ~ r n - ~ , Q/q = 2 x 10” (after Luryi, 1990). ~

induces charges only in an infinitesimally thin layer of the doped contacts at the boundaries of the i layers. In equilibrium, the barrier height is the same on both sides if the doping in both contact layers is identical. Under an applied bias K the height of the emitter (“uphill”) barrier will decrease by the amount V L J L(without loss of generality, we can assume that the emitter barrier corresponds to the shoulder L giving

70


rise to an exponentially increasing current I ePvLIILz (2-5) where = q/(k T ) . The band diagram of the planar-doped diode is shown in Fig. 2-3 a under equilibrium (V = 0) and nonequilibrium conditions [V(F) for forward bias and V(R) for reverse bias]. As can be seen from the figure, the barrier at the left is lowered (forward bias) by V, while the barrier at the right is increased by V2 in a reverse-bias sense, which is similar to the emitter-base and the base-collector harriers in an npn transistor, respectively. Figure 2-3 b shows I - V characteristics of a Si PDB with different lengths for L , and L,, ( L 2 / L ,= 8), and indicates that the device acts as a rectifier. The planar-doped barrier is another name for the “trinangular barrier”. It can also be built by grading the bandgap to make a triangular shape in the conduction or valence band, by using graded compositions of Si/Ge, Si/SiC (Jwo and Chang, 1986), and GaAs/AlGaAs (Allyn et al., 1980), etc. The planar-doped barrier is akin to a Schottky diode, with the advantage that the barrier height can be modified by the composition, doping or by controlling L and L,.

,

2.2.3 p-n Junction The most important characteristic of p-n junctions is their ability to rectify, that is, they allow current to flow easily in only one direction. When we apply a “forward bias” to the junction, the current increases rapidly as the voltage increases. However, when we apply a “reverse bias”, virtually no current flows initially. As the reverse bias is increased, the current remains very small until a critical voltage is reached, at

which point the current suddenly increases. This sudden increase in current is referred to as the junction breakdown. The applied forward voltage is usually less than 1 V, but the reverse critical voltage, or breakdown voltage, can vary from just a few volts to many thousands of volts depending on the doping concentration and other device parameters. The p-n junction is the basic building block of the bipolar transistor and thyristor, as well as of JFETs and MOSFETs. Given proper biasing conditions or exposure to light, the p-n junction also functions as either a microwave or photonic device. Figure2-4a shows the p-n junction cross section, the minority-carrier concentration, and the current across the depletion layer. The depletion layer is developed in the vicinity of the metallurgical junction when a bias V is applied (forward bias on the left side of Fig. 2-4a and reverse bias on the right side). The band diagram is shown in Fig. 2-4b. The quasi-Fermi levels E,, and E,., are split by an amount equal to I/: Therefore, the nonequilibrium minoritycarrier density at the depletion-layer edges are in accordance with the position of E,, in the p layer, and of E,, in the n layer. As shown, for example, under forward bias, np (0) = npo exp [q V / ( kT ) ] , while pn(0)= pnoexp [q V/(kTI],where npoI pno are the minority carrier concentrations at equilibrium (V = 0). The slopes of these carrier profiles represent the respective diffusion current by the equation

where i = n or p, i.e., C, = It, C, = p , D ithe diffusion constant, Lithe diffusion length = and zi the carrier lifetime. The

6,


FORWARD

71

REVERSE

Ln W Lp

M

m

JI

x‘

j

j

I

,

x

FP

EC

E Fn

Ev

Figure 2-4. (a) Injected minority carrier distribution and electron and hole diffusion currents of a pn junction under forward and reverse bias. (b) Band diagram and quasi-Fermi levels E,,, EFp.

total diffusion current becomes

while the generation current is

where A is the junction cross-sectional area. Another current comes from the recombination generation process in the depletion layer. Under forward bias the net rate is due to recombination, while under reverse bias it is due to generation (Sze, 1981, 1985). The recombination current is

where W is the depletion layer width. Figure 2-5 shows the I - V curves for a typical Si p-n junction under forward (a) and reverse (b) conditions, respectively. At low bias, the factor exp[q 1//(2k T ) ]is dominant while at high bias exp [q V / ( kT ) ]predominates. The increase of I, versus I/ is mainly due to an increase in the depletionlayer width W The breakdown voltage V, for a given background concentration can be ob-

72


-E

10-~

10 Y >

I

Y

10-6

ONE- SIDED ABRUPT JUNCTION

W E

n

-I

-a

w LL

z

za

; 10-8

Y

U

a

w (r m I-

10-10

U

T

: I-

10-12

0

0.2 0.4 0.6 0.8 1.0

(v) (a)

a W

VF

10-6

Z 1

I

0 I-

W

-I

a W

n

0.013 10'4

1 1017 1018 BACKGROUND DOPING NB ( ~ r n - ~ )

1015

10'6

Figure 2-6. Depletion-layer width ( Wm), maximum field at breakdown (&',,) and breakdown voltage (V,) for one-sided abrupt Si pn junctions (after Sze and Gibbons, 1966).

a CI

10-12 c 10-3

I

I

10-l

loo

plotted in Fig. 2-6 for a one-sided abrupt Si p-n junction at 300 K.

I

I

10'

lo2

2.2.4 Bipolar Transistor Figure 2-5. The current-voltage characteristics of a Si pn diode at various temperatures. (a) Forward bias. (b) Reverse bias.

tained from the maximum depletion-layer width W, and the maximum critical field &m, € , = q N , WJE,.The breakdown voltage VB is

(2-10) The breakdown voltage, the maximum ,, and the maximum depletion-layer field € width at breakdown W , versus NB are

The bipolar transistor is an active threeterminal device that combines an n-p junction and a p-n junction by means of a common middle p layer (base) which is very narrow. This is the npn bipolar transistor. Its complementary type is the pnp bipolar transistor. The band diagram of an npn bipolar transistor is shown in Fig. 2-7a. The solid lines are for the normal bias condition (i.e., emitter-base forward biased and the base-collector reverse biased) and the dotted lines for the equilibrium condition. Figure 2-7 b shows the minority carrier distribution profiles. Note that due


c

_

-

EMITTER

BASE

I'

COLLECTOR

73

tion current I, in the E-B junction and a generation current f G in the C-B junction as shown in Fig. 2-7 b. In Fig. 2-7c, the electron current In, is emitted from the E-B junction and diffuses through the base with partial leakage to the base due to electron-hole recombination ZnB.The remainder I , , is collected by the collector electrode. Hole-diffusion current I,, and I, is injected from the base to the emitter. This current makes no contribution to the collector current. Therefore, to achieve a high current gain, the hole-diffusion current should be minimized. I , and I , are the leakage currents due to diffusion and generation, respectively, under a C-B reverse bias condition. The inverse of current gain hf,' can be expressed (Yang, 1988) as h;

1 =

'B b + In' - InC+ I,

(2-1 1) IC In, In, In, Applying the p-n junction current theory,

5v

0.6 V

(C) Figure 2-7. An npn transistor in equilibrium and in nonequilibrium. (a) Band diagram and quasi-Fermi levels under bias compared to a no-bias condition. (b) Minority-carrier concentrations under normal active bias. (c) Carrier flows in the respective regions.

to a reverse bias applied to the collectorbase (C-B) junction, nP(xB)% 0 while np(0) = npo exp [q V E J k T ) ]due to forward bias in the emitter-base (E-B) junction. It is easy to apply the same principle, discussed in the previous section (2.2.3), to derive the current flows in the respective regions. In addition, there is a recombina-

,N

+

NA xB XdE DnB 'i

- e V ~ / ( 2Tk)

(2-12)

'0

Subscripts E, B, C refer to the emitter, base, and collector respectively. From Eq. (2-12), h,, increases with decreasing base doping concentration N A B . This, in turn, decreases the high-frequency performance due to a large base spreading resistance R B B . The maximum unity-power-gain frequency J,,, is (Sze, 1990) (2-13 ) where f is the cutoff frequency at unity current iain due to total delay and transit time from E to C. A heterojunction bipolar

74


transistor can meet the requirements of both high gain and high-frequency response by having wider bandgap material in the emitter. This will be discussed in the following two sections. A modern high-frequency, doped polycrystalline emitter, bipolar transistor is shown in Fig. 2-8. The device was fabricated in a double-polysilicon self-aligned bipolar process (Chen et al., 1989). A schematic cross section is shown in Fig. 2-8 a. A p- substrate with an n+/n-epitaxial layer was used. Then, the device fabrication follows the polysilicon refilled-trench isolation process. An epitaxial p-type layer was grown on top of n-collector and isolation-

oxide layer. After p'-polysilicon delineation, oxidation, and n+-polydeposition at the emitter window, a thermal furnace and rapid thermal annealing were used to provide a shallow emitter-base junction. A representative device profile is shown in Fig. 2-8 b. The estimated base widths range from 63 to 95 nm with an emitterbase junction depth of about 25 nm. Such devices exhibit gains ranging from around 100 to 200, depending on the base implant dose and the resulting base Gummel number. The cutoff frequency f , reaches 51 GHz at a current density of more than 1.0 mA/pm2 while maintaining an emittercollector breakdown of 3 V. The total transit time is less than 3.0 ps.

2.2.5 Heterojunction

n

0.0

0.1

0.2 0.3 DEPTH ( f i m )

0.4

0.5

(b)

Figure 2-8. The self-aligned poly-Si emitter npn bipolar transistor. (a) Schematic device cross section. (b) Representative secondary ion mass spectrometry (SIMS) profile of a device obtained from a monitor wafer (after Chen et al., 1989).

In the early 1980s, a new unorthodox player emerged on the heterostructure scene, Ge,Si, - on Si (Kasper and Bean, 1989).The lattice constant of germanium is about 4% larger than that of silicon. For a strained, but not relaxed, overgrowth layer that obeys a rule of equilibrium, the overgrowth thickness should not exceed a critical thickness L, as is shown in Fig. 2-9 with different germanium fractions x. The bandgap versus x is also shown and decreases with increasing x values. The epitaxial growth techniques involve the molecular beam epitaxy (People, 1985), UHV/CVD (Meyerson, 1986), limited reaction process (Gibbons et al., 1985), etc. The band alignment of Ge,Si,-, on Si substrates for different x values is shown in Fig. 2-10. The bandgap discontinuity in the conduction band is always smaller than that in the valence band, e.g., AEc = 0.020 eV while AEv = 0.15 eV for x = 0.2, as shown in Fig. 2-10a. For x = 0.5, AEc = 0.15eV and AEv=0.30eV on an unstrained (001) Geo.25Sio,75buffer layer

75


(not shown), as illustrated in Fig. 2-lob. Figure 2-1Oc shows the band alignment of the Ge,,,5Sio,5/Si heterostructure on a (001) Si substrate (People and Bean, 1986). The heterostructure is the building block for various kinds of novel GeSi/Si devices such as the heterojunction bipolar transistor, MODFET, and resonant-tunneling devices, which will be discussed in more detail in the following sections.

2.2.6 Heterojunction Bipolar Transistor The heterojunction bipolar transistor (HBT) offers numerous advantages over conventional homojunction bipolar transistors for high-frequency and high-speed applications. The advantage is due to the HBT's higher emitter injection efiiciency as a result of the bandgap of its emitter being larger than that of its base. Thus, higher base doping and lower emitter doping can be used to reduce the emitter-base delay time. The use of a graded base can further reduce the base transit time.

STRAl NED Eg (Geo.zSi0.e I = 1.OeV

CUBIC Eg (Si)=1.17eV

AEc Ec

0.150eV

__

t

I

STRAINED Eg (Geo.sSi0.5 ) = 089eV

STRAINED Eg ( S i 1 = 1.04eV

1 AEv = 0.30eV

- (bl

Ev

CUBIC

I

' STRAINED E g (Geo.sSi0.51= 0.78eV 4

E g ( S i ) = 1.17eV Ev

1

AEv

-__-

2

0.37eV

(C)

>

Figure 2-10. Band alignments for (a) Ge,,,Si,,,/Si heterostructures on (001) Si substrates, (b) Ge,,,Si,,,/Si heterostructures on an unstrained (001) Ge,,,,Si,,,5 buffcr layer, and (c)Ge,,,Si,,,/Si heterostructures on (001 )Si substrates (after People and Bean, 1986). 1.2

a,

v

a

1.1

Figure 2-1 1 a shows the band diagram of an HBT. Following the analysis of Eq. (2-12), the current gain, limited by emitter injection efficiency, is

1.0 >

2

0.9

w Z

w 0.8 h f e = NAE xEDnB

0.7

1-6.0

NAB x13 DpE

0 Si

0.2

0.4 0.6

Ge FRACTION , x

0.8

1.0

Ge

Figure 2-9. The critical thickness and bandgap energy versus Ge fraction of strained GeSi on a Si substrate (Bean, 1978).

exp

(2)

(2-14)

where AE, is the bandgap difference of the emitter and the base. Representative doping concentrations in state-of-the-art HBTs fabricated in the Si/GeSi system are shown in Fig. 2-11 b,

76


7SiGe

P

z

(550 "C) epitaxial silicon deposition process known as ultra-high vacuum chemical-vapor deposition (UHV/CVD). Demonstrated in this work are the excellent quality of Si/GeSi junctions formed using this method, the advantages of GeSi for bipolar device design, and the integration of this technology into a polyemitter bipolar process. Figure 2-12a shows the polyemitter bipolar structure with emitter dimensions of only 1.2 x 2.4 pm2, that was used in this work. An example of the final doping profile of a GeSi-base device is shown in Fig. 2-12b. In the GeSi-base transistors, the Ge content was graded from 0 to 14% across the base (roughly 6 to 13% across

- N * Pniv

,NITRIDE

w

0

0 N

+

SUBCOLLECTOR

P - SUBSTRATE

DEPTH (urn) (b) Figure 2-11. (a) Representative band diagram and (b) doping profile of an HBT.

which should be compared with those of Fig. 2-8 b for the homojunction transistor. In HBTs, doping levels of lozocmP3have been used in the base. As a result, base sheet resistance can be greatly decreased, even with ultra-narrow base regions, and transistor f,,, can be greatly increased, (Eq. (2-12)). In recent work (Meyerson et al., 1990),Si and graded-GeSi-base bipolar transistors were fabricated in a standard polyemitter bipolar process using the low-temperature

DEPTH ( n m l

(b) Figure 2-12. (a) Schematic cross section of the nonself-aligned bipolar structure with a base formed by UHV/CVD low-temperature epitaxy. (b) SIMS impurity profile of a 75 GHz (GeSi-base transistor (poly-Si emitter contact not shown) (after Meyerson et al., 1990).

77


the neutral base region), with the highest Ge percentage (largest bandgap reduction) occurring at the base-collector junction. The smaller bandgap in the base reduces the barrier for electron injection into that region, while the bandgap grading introduces a drift field (over 15 kV/cm) to aid the transport of electrons across the neutral base. The maximum cutoff frequency of the GeSi transistor increases from 75GHz at 298 K to 94 GHz at 85 K at a collector current of 28 mA. Equally significant, the peak cutoff frequency of the homojunction Si device increases from 52 to 57 GHz for a doubling of collector current, as illustrated in Fig. 2-13. The larger relative improvement for the graded-GeSi base transistor results from the quasi-field created by the bandgap grading in the base. This field is more effective at low temperatures, and it compensates the degradation in diffusivity of the base (Grabbe et al., 1990). A combination of the high density of ULSI and the high speed capability of GeSi-based HBT technology will have dramatic impact on future electronics system applications.

2.2.7 Thyristors The thyristor is a four-layer device that has an npnp or a pnpn structure. It can be treated as two transistors, one an npn and the other a pnp, connected in series. A schematic diagram of a thyristor is shown in Fig. 2-14a. Under forward conducting conditions, both pl -pl and n2-p2 are reverse biased while nl -p2 is forward biased. When the sum of current gains a,, a2 of the two transistors becomes unity, the device is turned on to a high-conduction state. The doping profile and the currentvoltage characteristics are shown in Fig. 2-14b and c, respectively (Yang, 1988). The

z t-

z

W

100

a a

3 V

I

-

-

-

-

-

50 -

Si

3

z

X

- C L - - 4 - 4 - 4 - 4 - 4 - 4 - - *

Q

=

-

1

I

I

300 A ~ 2 1 . 0 ~ 4 wrn* .6 200 - b = O V

20

-

I

I

I

I

I

L

I

I

I

80

-

C

-

I

60 -

l3

. 2 !

40 -

20 -

Figure 2-13. Collector current dependence of f , at 298 K and 85 K for Si and SiGe devices. In both cases, the peak fT and the associated collector current increase at lower temperature (after Grabbe et al., 1990).

basis current-voltage characteristic of a p-n-p-n diode exhibits five distinct regions: 0 + 1: The device is in the forward-blocking or off state and has a very high impedance. Forward breakover (or switching) occurs where dVdZ = 0; at point 1 we define a forwardbreakover voltage V,and a switching current I,.

78


dt

.,

K

(C)

Figure 2-14. (a) Planar three-terminal thyristor. (b) Doping profile. (c) i / V characteristics with I, (gate bias current) trigger.

2: The device is in a negative-resistance region, that is, the current increases as the voltage decreases sharply. 2 + 3: The device is in the forward-conducting or on state and has a low impedance. At point 2, where dV/dl = 0, we define the holding current I , and holding voltage V,. 0 -+ 4: The device is in the reverse-blocking state. 4 -+ 5: The device is in the reverse-breakdown region. Thus, a p-n-p-n diode operated in the forward region is a bistable device that can 1

-+

switch from a high-impedance, low-current off state to a low-impedance, high-current on state, or vice versa. The device can be operated in a threeterminal mode. The turn-on behavior can be modified by increasing the gate bias current I , turning on the device at a lower breakover voltage. Another type of thyristor, called the insulated-gate bipolar thyristor (IGBT), can handle power up to 1 MW and can be turned on and off quickly. Figure2-15 shows the structure of the IGBT. The IGBT is composed of an npnp thyristor and a MOSFET that acts as a gate to control the device’s on/off mode. When a positive bias is applied to th gate, the p base is inverted into the n channel along the Si0,-Si interface, which turns the device on immediately. The device can sustain a voltage of 2000 V and can be turned on in microseconds. Turning off is faster and happens within 0.2 ps. The devices were processed on 90 cm bulk silicon material with a thickness of 350 pm. The back side emitter was formed by a shallow backside boron implantation. No lifetime-killing steps were used. The result is a 2000 V IGBT on an area of 6.5 x 6.5 mm2 with an on-state voltage of 4.5 V at 15 A. To get the high blocking voltage, two factors have to G

I

E

-T I

n-

Figure 2-15. 2000 V insulated-gate bipolar thyristor (IGBT). The gate (G) inverts p- into n-channel and switches the device to a high conduction state (Laska and Miller, 1990).

79


be considered: a suitable junction termination using a poly-Si/Al field plate and a substrate with a width of 550 pm, which can sustain 2000 V. The device exhibited a turn-off time of 20011s. It can switch a shorted load up to 1800 V with a gate voltage of 20 V. The current is limited to 160 A (570 A/cm2) by the device itself (Laska and Miller, 1990).

I

L-

2.2.8 Hot Electron Transistor Basically, a hot electron transistor consists of an emitter that ejects electrons by a thermionic process, a base that controls the ejected current, and a collector that collects the current ejected ballistically from the base. In this section, two types of hot electron transistors are presented, namely the bipolar inversion-channel field effect transistor (BICFET) and the induced base transistor (IBT). Both of them can be built on a Si substrate with epitaxially grown SiGe/Si layers. The Ge,Si, -,/Si system is ideally suited for a silicon-based implementation of the p-channel BICFET because of the band lineup between unstrained silicon and commensurately strained Ge,Si, - x . Almost all of the band offset lies in the valence band, leading to a AEv = 0.37 eV for x = 0.5. Figures 2-16a and b show the charge distribution and the vertical cross section of the silicon-based BICFET band structure, respectively (Taft et al., 1989). The transistor is doped n-type, except for a very narrow region that is doped p-type. This p-type region is so narrow that there is insufficient band bending to produce a charge-neutral region of holes. However, the negative-acceptor charge sheet sets up a thermionic barrier that prevents electron flow even when a positive bias is applied to

0.0

0.5

1.0

1.5

2.0

APPLIED COLLECTOR VOLTAGE ( V 1 ( C )

Figure 2-1 6. Bipolar inversion-channel field effect transistor (BICFET). (a) Charge distribution. (b) Band diagram under bias. (c) I/V characteristics. The common-emitter characteristics are for a single-basecontact, 4 pmm BICFET (Taft et al., 1989).

the collector. The collector current is controlled by the hole quasi-Fermi level of the base region, or equivalently, the concentration of holes in the inversion channel, which can act directly to lower the barrier. The doping profile and the composition profile are also indicated in Fig. 2-16b. Before forming a two-dimensional hole gas (2DHG) in the narrow (50 A-100 A) GeSi layer, the nf-i-6p-i-n+ structure forms a triangular barrier shown in Fig.

80


2-16a. When a positive bias is applied to the collector with respect to the emitter, a 2 DHG is formed that reduces the effect of Ap (depleted negative delta charges). The reduced effect of Ap causes a barrier lowering A 4 which, in turn, increases the electron emission from the emitter. The amount of barrier lowering is

Si

(2-15 ) where Ap is the 2DHG concentration induced by VEB.The current

lOc A * T ~ ~ - ~ J o / ( ~ T ) ~ A $ / ~ T(2-16) ) The current-voltage characteristics are shown in Fig. 2-16c. The effect of VBE which induces A 4 is obvious. Because of the high conductance of the 2 DHG in the base, the device can operate at high speed and has high current handling capability. The implementation of an inducedbased transistor (IBT) ion a Ge/Si heterosystem is desirable (provided, of course, that one can achieve a high-quality interface of these lattice-mismatched materials). It makes sense to use the injection of hot holes because, unlike the conduction-band minima, the valence-band maxima are located at the same k = 0 point in both semiconductors. For a discussion of other exotic possibilities related to the IBT concept, see Luryi (1990) and Chang et al. (1986). The proposed induced-base transistor layer structure and band diagram is shown in Fig. 2-17. Layers 1-4 are GeSi, and layer 5 is undoped Si. In GeSi, the pf -i - 6n+-i2DHG forms a triangular barrier. At the GeSi-Si interface, there is a band discontinuity AE,. Holes are injected from emitter to base and traverse ballistically to the collector. The 2 DHG produces a barrier lowering, which enhances the hole emission.

6N i

E

C

A

-1

SiGe

I-Si

4

SI

2 (a)

.-

DEPLETED CHARGE SHEETS I'siZDHOLE GAS

'

G e l S i ALLOY I

I

3

5-

- 5 VLLECTOR

UNDOPED

AEv I

2h' (b)

Figure 2-17. Proposed induced-base transistor (IBT). (a) Charge distribution. (b) Band diagram (after Luryi, 1990).

2.3 Field-Effect Devices 2.3.1 Metal-Silicon Contact The first systematically studied semiconductor device was the metal-semiconductor contact (by Braun in 1874), which also happened to be the first practical semiconductor device (in the form of a point contact rectifier in 1904). In 1938, Schottky suggested that the rectifying behavior could arise from a potential barrier as a result of a stable space charge in the semiconductor. The model arising from his consideration is known as the Schottky barrier. Metal-semiconductor contacts For a collection of pioneering papers in metal-semiconductor contacts and other semiconductor devices see Sze (1991).

2.3 Field-Effect Devices

can also be nonrectifying; that is, the contact has a negligible resistance regardless of the polarity of the applied voltage. Such a contact is called an ohmic contact. All semiconductor devices as well as integrated circuits need ohmic contacts to make connections to other devices in an electronic system. The metal-silicon contact is the most extensively studied among all metal-semiconductor systems because of its importance in silicon-based devices and VLSI (very-large-scale integration) circuits. For high-barrier contacts operated at room temperature, the current transport is due mainly to thermoionic emission of majority carriers (e.g., electrons in an n-type Si) across the Schottky barrier. For lower temperatures or high doping concentrations ( > lo1* impurity atoms/cm3), field emission becomes dominant. For the classical metal-silicon contacts (e.g., Al), metals are deposited physically (e.g., by evaporation) or chemically (e.g., by chemical vapor deposition) onto a silicon surface. One potential problem is the possible contamination of the interface between the metal layer and the silicon surface. Recently, there has been a significant emphasis on the use of silicide-silicon contacts instead of the classical metal-silicon contacts. The new contacts are of interest because (1) many silicides have relatively low resistivities and, (2) silicide is formed underneath the original silicon surface and the silicide-silicon interface is generally free of oxides, impurities, or defects. Therefore, the silicide-silicon contacts are more reproducible and highly reliable. A new model for the silicide-silicon intimate contacts has been proposed based on microphysical investigations that show the existence of an interphase layer between the silicide and the silicon surface. This transition layer is responsible for the grad-

81

ual shift from silicon to metal silicide. The equilibrium band diagram of the silicide/ transition layer/silicon is shown in Fig. 2-1 8. The barrier height for the electrons in the metal, g5,,, is the Schottky barrier. From Fig. 7-18, we obtain

where +M is the metal work function, is the electron affinity, (A+)Mis the change in electrostatic potential at the metal surface, and fl is given by (2-18) where d is the transition-layer thickness (about 30 8, for a CrSi,/n-Si contact), 1 is the penetration depth in silicide (0.5 8, for CrSi,), and E, and E , are the dielectric permittivities in silicon and metal, respectively. The new model can explain the bias and temperature dependence of the current-voltage characteristics using a fielddependent barrier height as given by Eq. (2-17) (Sze, 1991).

x:O

\SILICIDE

x:d

\:RA;~ION

\

n-Si

Figure 2-18. Thermal equilibrium energy diagram for the silicide/transition layer/n-Si system (after Sze, 1991).

82


2.3.2 Homogeneous Field-Effect Transistors Homogeneous field-effect transistors include the JFET Cjunction FET), the MESFET (metal-semiconductor FET), and the PBT (permeable-basetransistor). They employ homogeneous semiconductor materials instead of heterojunctions to offer greater simplicity and ease of fabrication, because they do not depend critically on the precise control of layer thicknesses and sharp interfaces. The JFET consists of a conductive channel for current flow and two ohmic contacts. It uses the depletion region of a reverse-biased p-n junction as the gate electrode to modulate the crosssectional area of the conductive channel. The operation of a MESFET is identical to that of a JFET. The MESFET, however, has a metal-semiconductor rectifying contact instead of a p-n junction for the gate electrode. Silicon JFETs have been used extensively in many discrete and IC applications. Si MESFETs are more difficult to make than Si MOSFETs due to the great care needed to prevent native oxide formation at the metal-silicon interface. Furthermore, Si MESFETs are relatively unpopular, because they are outperformed by Si MOSFET and bipolar transistors. The Si permeable-base transistor (PBT) is a high-speed device that can be used in analog applications at microwave frequencies. In contrast to the planar homogeneous FETs such as JFET and MESFET, the PBT is a vertical device in which the current flow is normal to the Si waver surface rather than parallel to the surface. Because of lower effective electron velocity in Si, the frequency capabilities of the Si PBT are below that of its GaAs counterpart. However, the Si PBT provides a practical, high-performance microwave device that

EMITTER CONTACT

CONTACT

/

COLLECTOR CONTACT

si3 NL

Figure2-19. Cutaway diagram of a Si permeablebase transistor (after Rathman and Niblack, 1988).

has advanced fabrication technology and superior thermal conductivity. A schematic diagram of a Si PBT is shown in Fig. 2-19. Grooves are etched into an n-type Si layer, a metal (e.g., Pt) is deposited on top of the ridges and in the bottom of the grooves and then sintered to form silicide (e.g., PtSi) emitter and base contacts. Selective ion implantation is used to dope the active region and to obtain device isolation. Si PBTs with a grating periodicity of 0.32 pm have demonstrated a maximum frequency of oscillation (fmax) of 30GHz and a cutoff frequency (f,) of 22 GHz. Si PBT has very low llfnoise and excellent performance in low-noise oscillators (Rathman and Niblack, 1988). 2.3.3 MOS Structure and Charge-Coupled Devices The MOS diode is the heart of the most important device for very-large-scale integration - the MOSFET. It is also of paramount importance in semiconductor device physics. In recent years, MOS structures have been adopted for even wider applications. One example is the tactile imager for use in precision robotics applications where high packaging density and high resolution are required.


THIN SILICON SUPPORT BEAM

a3

DEEP BORON DIFFUSION

..... SILICUN-KIA1

1;1 A55

Figure 2-20. Fabrication of an MOS tactile imaging cell: (a) device cross section, (b) K O H etch, (c) deep boron diffusion, (d) shallow boron diffusion and dielectric deposition, (e) electrostatic bonding and final wafer etching (after Suzuki et al., 1990).

(el Figure 2-20 shows the MOS structure of the imaging cell. The force-sensitive capacitor is formed between the lower metallic plate on the glass substrate and a thick Si center plate that is supported by two thinner Si beams. When a force is applied to the top surface of the center plate, it deflects the thin beams to change the capacitive gap and hence the cell capacitance. The dielectric film over the center plate prevents electric shorts and provides buildin over-range protection when excessive force causes the plates to touch. The fabrication sequence of the tactile imager is shown in Figs. 2-20b-e. The process starts with a p-type (100) Si wafer. The wafer is oxidized and oxide mask patterns aligned to (110) are formed by HF etching. The Si islands are then created by

anisotropic etching in KOH, Fig. 2-20 b. Next, a thick oxide is thermally grown and patterned, followed by a deep boron diffusion, which defines the thickness of the center plate and the bonding islands, Fig. 2-2Oc. All oxide is removed and a third oxide is grown and patterned, followed by a shallow boron diffusion to define the supporting beams. Finally, a thin oxide and a thin nitride layer are deposited and patterned to form the protective dielectric, Fig. 2-20d. A glass substrate is metallized and patterned. The Si structure is fused to the glass substrate by electrostatic bonding. The device is placed in an EDP (ethylene diamine-pyrocatechol-water) etchant, which etches the lightly doped silicon wafer and stops at the boron p + layer, Fig. 2-20e.

84


This MOS structure is rugged and has a high damage threshold against excessive force. It operates over a wide temperature range and has a low temperature sensitivity ( 0.99996). The equivalent CCD with uniformly doped storage wells degrades rapidly above 240 MHz (Lattes et al., 1991).

2.3.4 MOSFET 2.3.4.1 Submicrometer MOSFET The metal-oxide semiconductor fieldeffect transistor (MOSFET) is the most important device for very-large-scale integrated circuits (> lo5 components/cm2) and ultra-large-scale integrated circuits (> 107 components/cm2). It is a four-terminal device as shown in Fig. 2-22a, consisting of a p-type Si substrate into which two n f regions, the source and drain, are formed. (This is called an n-channel device. One may consider a p-channel device by exchanging p for n.) The top metal contact is called the gate. Heavily-doped polysilicon or a combination of silicide and polysilicon can also be used as the gate electrode. Because the gate electrode is used as a mask to implant the source/drain regions, it self-aligns the source/drain with respect to the gate to minimize parasitic capacitance. The sidewall oxide spacer is used to bring the source/drain ohmic contacts as close as possible to the channel without shorting the source/drain to the gate electrode.

2.3 Field-Effect Devices GATE

P

SIDEWALL OXIDE /

p-Si

b SUBSTRATE (a1 SIDEWALL OXIDE

SHALLOW n

p- si

I

(b) Figure 2-22. (a) MOSFET with sidewall spacer. (b) MOSFET with sidewall spacer and lightly doped drain structure.

The basic device parameters are the channel length L , the oxide thickness d, the p-n junction depth rj, and the substrate doping N . To reduce the channel length to the submircometer ( < 1 pm) region, various approaches have been proposed. An empirical formula has been obtained to serve as a guide for MOSFET miniaturization:

+

Lmin= 0.4 [rj d (W, Wd)2]”3(pm) (2-19)

where Lminis the minimum channel length to maintain proper device behavior, W, and Wd are the depletion widths of source and drain, with rj, W,, W, in micrometers and d in angstroms. It is apparent that in order to reduce channel length, one must reduce rj, d, and the depletion widths (Sze, 1981). As the channel length moves into the submicrometer region, one key concern is

85

the hot-electron effect, i.e., the high-energy electrons near the drain can cause threshold-voltage shift and degradation of transconductance. To minimize the hot-electron effect, “drain engineering” has been proposed. One approach is the lightly doped drain (LDD) as shown in Fig. 2-22b. The drain consists of a shallow lightly doped n region followed by a deeper nf region. By proper design of the doping and the extension of the shallow n region, one can substantially reduce the peak field near the drain, thus reducing the generation of hot carriers there (Brews, 1990). To place millions of devices in an IC package, we must reduce power dissipation. Because of its low power dissipation, CMOS (complementary MOS) technology becomes the dominant technology in which both n-channel and p-channel devices are constructed simultaneously on the same substrate. Two examples of submicrometer CMOS devices are shown in Fig. 2-23. The device shown in Fig. 2-23 a has twin wells on a p- substrate. Each well is 2 pm deep and of retrograde type formed by high-energy ion implantation. The 2.2 pm deep trenches isolate the wells. The wells are 1 pm wide and are filled with chemicalvapor-deposited SiO, on top of a 2008, thick thermal oxidation layer of the trench surface. The active regions of each device are delineated with the LOCOS (local oxidation of silicon) process. The gate-oxide thickness is 35 8,. Surface-channel nMOS and buried-channel PMOS are employed so that a phosphorus-doped n + single-gate process can be used. The use of retrograde wells and trench isolation gives the devices a high latch-up immunity. The transconductance of the 0.22 pm gate-length n- and p-MOSFETs are 450 and 330 mS/mm, and unloaded ring-oscillator delays are 36 ps at 2 V (Okazaki et al., 1990).

86

2 Silicon Device Structures P DOPED POLY-Si

(a)

PMOS

nMOS

LOW-IMPURITY-CHANNEL

EPITAXIALLY GROWN FILM

I

S i0,

n

P,

\

/

J

HIGHLY DOPED WELL

(b) Figure 2-23. (a) Cross section of sub-0.25 pm CMOS device (after Okazaki et al., 1990).(b) 0.1 pm CMOS device using low-impurity-channel transistors (after Aoki et al., 1990).

Figure 2-23b shows a 0.1 pm CMOS using low-impurity channel transistors. The impurity concentrations in the low-impurity channels are 10'6-1017cmP3, which are about two orders of magnitude lower than those of the highly doped wells. The gate-oxide thickness is 50 8,. Ultra-shallow junctions are formed at 900 "C with rapid thermal annealing to give junctions of 500A for nMOS and 10008, for PMOS. By proper choice of the thickness of the low-impurity layer, we obtain low threshold voltage (due to low-impurity concentration in the channels) and high punchthrough voltage (due to the highly doped wells). The device shows a subthreshold swing of 40 mV at 77 K (Aoki et al., 1990). The performance of CMOS circuits is limited by the low transconductance of pMOSFET. This transconductance can be

improved by increasing the hole mobility. One novel approach is to place a buried Ge,Si, - x layer under the gate of a pMOSFET as shown in Fig. 2-24a where a 100 8, Ge,Si, -, layer is grown on a Si substrate, followed by the growth of a Si spacer layer of 30-90 A, both by chemical vapor deposition. Figure 2-24 b shows the band diagram at the flatband condition for a structure with a 75 A Si spacer and a 100 8, Ge,.,Si,,, well. The quantum well for holes is created because the bandgap discontinuity between Si and Ge,Si, -,occurs predominantly in the valence band. When a negative gate voltage is applied, an inversion layer is formed in the Ge,Si, --x well as shown in Fig. 2-24c. Numerical simulations have indicated that it is desirable to employ a minium Si spacer thickness and a maximum Ge fraction to maximize the number of holes confined in the Ge,Si, -, well. Since the hole mobility in Ge,Si, --x is higher than that in Si, this MOS-gated Ge,Si, -x.Si heterostructure is expected to have higher transconductance, improving CMOS performance (Garone et al., 1990). A novel combination of CMOS and bipolar technology has recently been considered. This BiCMOS approach can combine the advantages of both technologies the speed and power-handling capability of bipolar devices with the ease of fabrication and high density of MOS devices. Figure 2-25 shows the cross section of a nonoverlapping, super self-aligned BiCMOS structure. The active areas of the bipolar transistor and MOSFETs are virtually identical. The structure allows complete silicidation of active polysilicon electrodes, reducing the parasitic resistances of the source, drain, and extrinsic base. The gate and emitter regions are protected from exposure and damage from reactive ion etching. All shallow p-n junctions are con-


87

ALUMINUM GATE \

30 TO 90 A 5i BUFFER LAYER tooQQQ(

n - S i SUBSTRATE

EC EF Gex Sii-, W E L L Si BUFFER

I

BULK Si

GexSii-x W E L L SI BUFFER

BULK S i

(C)

Figure2-24. (a) Cross section of an MOS-gated Ge,Si, ~x device. (b) Thermal equilibrium band diagram of the device with a 75 8, Si buffer and a 100 A Ge, 4Sio.6well. (c) Band diagram of the device when the Ge,,Si,,, well is inverted (after Garone et al., 1990).

GATE

NMOS

DSi02 POLY

S/D

tacted by polysilicon electrodes that minimize silicide-induced leakage. An arsenic buried-collector layer minimizes collector resistance. Fully recessed oxide with a polysilicon buffer layer is used to achieve low defect-density isolation. CMOS with a channel length of 1.1 pm and a width of 10 pm exhibits ring oscillator delays of 128 pslstage. The corresponding n-p-n transistor has a cutoff frequency of 14 GHz and a ring oscillator delay of 87 ps/stage. This BiCMOS structure is suitable for gigabits per second, digital VLST applications. By scaling down the device dimensions, even higher speed operation is anticipated (Chiu et al., 1991). Another novel combination is the integration of Si devices with compound-semiconductor devices using heteroepitaxial technology. However, there are many difficulties in Si heteroepitaxy. These include lattice mismatch (the lattice of GaAs is 4% larger than that of Si), mismatch in thermal

GATE BASE EMITTER COLLECTOR

-

PMOS

ALUMINUM SlLlClDE

BIPOLAR

N C - REGtON P * - REGION

Figure 2-25. Cross-sectional view of a nonoverlapping, super self-aligned BiCMOS structure (after Chiu et al., 1991).

88


expansion coefficient (2.6 times larger for GaAs), and antiphase disorder due to single atomic layer steps on a Si surface. Various approaches have been investigated to grow compound semiconductors heteroepitaxially on a Si substrate, and the viability of GaAs-based millimeter-wave integrated circuits on Si substrates has been established. Figure 2-26 depicts a cross section of a Si wafer showing GaAs MESFETs integrated with Si CMOS devices. The Si devices are fabricated first because they require higher temperatures for their formation than do the GaAs devices (Shichijo et al., 1988). It is conceivable that a monolithic integration of digital and analog devices, Si and non-Si devices, and electronic and photonic devices can be built on a Si substrate using heteroepitaxial technology. This technology will create novel system architectures and enhance overall system performance.

2.3.4.2 Silicon-on-Insulator Devices When devices are scaled down to submicron dimensions, they are also pushed closer together to increase the packing density. But close packing of devices places severe demands on isolation between devices. One solution to the isolation requirement is to build the circuit on an insulating substrate. A silicon-on-insulator (SOI) MOSFET is shown in Fig. 2-27 where a MOSFET is built on a silicon dioxide layer, so substrate isolation does not require buried n + regions as shown previously in Fig. 2-25. There are additional advantages of SO1 devices. Since there are no parasitic p-n-p-n’s in SO1 devices, there is no latch-up in CMOS circuits. The volume of the p region under the gate is much smaller than that of the conventional device, there-

TiW/Au PLASMA LPCVD OXIDE NITRIDE

\ -

I

BORON ISOLATION POLYSILICON 1

SCHOTTKY GATE

p-Si, 3’ OFF

Figure 2-26. Cross section of a Si wafer showing a GaAs MESFET integrated with Si CMOS devices (after Shichijo et al., 1988).

fore, only a limited number of electronhole pairs will be generated under radiation by high-energy particles. The SO1 devices can thus stand a much higher dose of radiation than a conventional MOSFET. When the silicon film (p region) is fully depleted, the device behavior will depend on both the top and bottom Si-SiO, interfaces. this two-sided behavior lowers the fields inside the device and tends to reduce hot-electron effects and short-channel effects. Furthermore, the subthreshold slope S can be improved in a fully depleted device. The slope S is proportioned to (1 + C,/Cox),where C, is the capacitance between the silicon surface and ground and Coxis the gate-oxide capacitance, both per unit area. For a bulk or non-fully depleted MOSFET

c, = E,/W

(2-20)

f

f

GATE

f ts1-02wn

p-

SUBSTRATE

db’0.6)~m

Figure 2-27. A MOSFET built on an insulating substrate (after Brews, 1990).

a9


where E , is the permittivity of Si and Wis the surface depletion width. For a fully depleted device, the capacitance C , is a series combination of the capacitances of three layers:

c,= - + - + -

(

tsi E,

db

cox

Y1

-

SILICON

-

OXIDE

S lLlC0 N

(2-21)

ES

where tSi and d, are the depleted Si film thickness and the lower oxide-layer thickness, respectively (shown in Fig. 2-27), and is the depletion width in the supporting silicon substrate. If C, from Eq. (2-21)is less than C, from Eq. (2-20), the SOT device has a lower S than the bulk device for the same C,, (Brews, 1990). The major problem in SO1 technology is the relatively poor quality of the material, since it is difficult to produce a high-quality Si film on an insulating substrate. SO1 technologies include ZMR (zone-melting recrystallization of polysilicon by using a laser beam or a strip heater), FIPOS (full isolation by porous oxidized silicon), and SIMOX (separation by implanted oxygen, i.e., implantation of oxygen ions into Si followed by high-temperature annealing to form buried SiO,). These technologies are still evolving and their success depends on further improvements in the quality of Si film. A new SO1 method has been introduced to yield ultra-thin, defect-free silicon on silicon dioxide. This technique uses epitaxial overgrowth of Si and chemical-mechanical polishing. Figure 2-28 shows the fabrication sequence. A thermal oxide (0.3 pm) is grown and a polish-stop film is formed (Fig. 2-28a). Narrow lines are opened in the exposed oxide to act as a seed area for selective epitaxial silicon growth (Fig. 2-28 b). These lines are along (100) so that a defect-free film can be obtained by an epitaxial lateral overgrowth process, i.e., the growth initiates in the seed area and

I

SILICON

I

p e wOXIDE

1

SILICON

1

Figure 2-28. Fabrication sequence for producing Sion-insulator (SOI) structures using epitaxial lateral overgrowth and chemical-mechanical polishing (after Shahidi et al., 1990).

grows vertically and laterally over the oxide, as shown in Fig. 2-28 c. Chemical-mechanical polishing is used to thin the film. The polishing process is stopped when the polish pad reaches the polish-stop film. This process produces a SO1 film thickness that is determined by the polish-stop film thickness (Fig. 2-28 d). The quality of the SO1 film is equivalent to bulk silicon, and the basic device characteristics are comparable to those resulting from fabrication on bulk. However, because SO1 devices have better isolation and lower parasitic capacitance, ring oscillator measurements on the SO1 film have shown significant speed improvement over the bulk devices (e.g., 30ps versus 120ps for 0.5 pm channel length devices operated at 2 V) (Shahidi et al., 1990).

2.3.4.3 Thin-Film Transistors Thin-film transistors (TFTs) are MOSFETs fabricated by depositing amorphous or polycrystalline semiconductors on largearea glass or other insulating substrates. Because of their lower costs, TFTs are potentially very useful for active-matrix liq-

90


uid-crystal displays, printer heads, and image sensors. Figure 2-29a shows a cross section of a polysilicon TFT. The polysilicon films are deposited on an insulating substrate using standard low-pressure chemical vapor deposition techniques. Typically, they have a fine-grain structure of the order of 0.05 pm in diameter. To increase the grain size, lowtemperature seed selection is used by means of an ion-channeling technique. A Si ion implantation can make the deposited polysilicon film amorphous but a few (1 10) oriented grains survive the implant due to the ion channeling effect. When annealed at about 625 "C, the amorphized polysilicon film recrystallizes from the surviving grains via a solid-phase epitaxy process. Much larger grains, in excess of 1 pm, can be obtained. When the channel dimensions are reduced to the same size as the grain size, the TFT characteristics improve dramatically. A comparison of the mobilities for small and large grain sizes is shown in Fig. 2-29 b. Note the substantial increase in mobility for devices with large grains, especially with very small channel dimensions. Mobilities as high as 70 cm2 V - ' s-' and ON/OFF ratios larger than lo8 have been obtained in 2 pm devices (Yamauchi et al., 1991).

2.3.4.4 Nonvolatile Memory Nonvolatile memories are MOSFETs with modified gate electrodes to enable semipermanent charge storage inside the gate. At present, nonvolatile memories such as the EPROM (erasable programmable read-only memory) and the EEPROM (electrically erasable programmable read-only memory) constitute about 10% of all MOS IC scales. The first nonvolatile memory had a floating gate (not connected to external

Al-Si

n' POLY-Si

/

Al-Si

SPUTTERED 302

LPCVD POLY-Si

VD = 0.5V 150

SMALL GRAIN

LL LL W

n

_I

F

o-t0 o

-

-1r-70

CHANNEL DIMENSION W = L

2-5

(lm)

(b) Figure 2-29. (a) Cross section of a polysilicon thinfilm transistor. (b) Field-effect mobility in large and small grain polysilicon film as a function of channel dimensions (channel length = channel width) (after Yamauchi et al., 1991).

voltage) sandwiched between two insulating layers, Fig. 2-30a. When an appropriately high field is applied through the outer control gate, charge carriers transport through insulator 1 and charge the floating gate, giving rise to a threshold voltage shift. Such a device can function as a bistable, nonvolatile memory, because the charges are stored even after the charging field is removed due to a much lower probability of back-transport. If avalanche injection of electrons (near the drain) is used to charge the floating gate, we have a FAMOS (floating-gate

2.3 Field-Effect Devices INSULATOR 2

91

CONTROL GATE

(a) PA' V C l l c

' sio2

22

c avalanche injection MOS) nonvolatile memory (Fig. 2-30b). Since there is no outer gate electrode, the initial equilibrium condition can be restored by illuminating the device with ultraviolet light or exposing it to X-ray radiation. A MIOS (metal-insulator-oxide-semiconductor) memory device, shown in Fig. 2-30c, has a double-dielectric (AI-Si,N,Si0,-Si) structure. The charge carriers can tunnel through SiO, and are stored at the Si,N,-SiO, interface. Nonvolatile memories are now moving towards higher densities, faster access times, scaled-down cell sizes, lower power consumption, and lower voltage operation (e.g., 5 V for microcomputer systems). A triple-dielectric structure (Fig. 2-30d) has been proposed. Charge transport and storage can be modeled by using two-carrier (electrons and holes) injection simultaneously at both the Si-bulk and gate-electrode boundaries via Fowler-Nordheim or direct tunneling. In the case of low-voltage operations ( f 5 V), a projected 10 year lifespan and lo6 cycles are obtained for a device with dimensions of 20 8, for the tunnel oxide, 50 8, for the nitride, and 35 8, for the blocking oxide (Libsch and White, 1990).

Figure 2-30. Nonvolatile memory devices. (a) Floating gate. (b) FAMOS. (c) MIOS. (d) Triple-dielectric structure (after Libsch and White. 1990).

A novel nonvolatile memory cell has been made based on microelectromechanics. A schematic diagram of the memory cell is shown in Fig. 2-31. The memory cell has a micromachined, conductive membrane in the form of a bridge. The bridge is longitudinally stressed so that it can buckle upward or downward and is therefore mechanically bistable. The cell is fabricated using a modified MOS process. Silicon substrate is covered with a thin, insulating thermal oxide and a spacer layer of 1.5 pm polysilicon. The polysilicon is selectively masked and the unmasked areas are implanted heavily with boron; the implanted

L

,METAL

Figure 2-31. Schematic drawing of a microelectromechanical, nonvolatile memory cell based on a bistable bridge (B), a spacer (S), and the substrate (SUB) with lateral electrodes (L) fafter Holg, 1990).

92


areas are the etch-stop areas. The bridge material is a thermally grown SiO, layer covered by a 20 8, Cr layer, and the bridge is defined by photolithography and etching. The bridge is released by partly etching away the polysilicon spacer with EDP (ethylene diamine pyrocatechol solution). The etched channels are defined by the boron etch-stop mentioned above. The bistable bridge performs the memory function. The two logic levels are defined by the two stable states: the bridge bending upward or downward. The write function corresponds to the switching of the bridge between the two states. Switching to either state is done electrostatically by applying a voltage between the bridge and the substrate or the lateral electrodes. The read function is done by sensing the capacitance between bridge and substrate. Thus, the memory cell is nonvolatile and fully immune to an electromagnetic field, and the stored data can be retained permanently. Switching voltages around 30 V have been achieved; lower voltages are expected. Since the fabrication technology for the bridge is close to a standard MOS process, we expect that the microelectromechanical memory cells can be integrated monolithically with microelectronic read/ write circuits to form a full memory device (Holg, 1990).

We have used a Ge,Si, - x strained layer to fabricate the Si-based MODFET (modulation-doped FET) in which a two-dimensional electron gas is formed at the GeSi-Si heterojunction interface. The layers are grown at an epitaxy temperature of 600 "C on a (100) Si substrate using the Si MBE system. A schematic cross section of the layered structure is shown in Fig. 2-32a. A Geo,25Sio.,5buffer layer is deposited on a high resistivity (lo4Q cm) p-type Si substrate. The subsequent layers consist of an undoped Ge,Si,-, graded layer with x varying from 0.5 to 0 within the 1008, width, and, finally, an undoped Si top layer of 100 8,. Source and drain ohmic contacts

SOURCE

GATE

DRAIN

Ge0.25Si0.75 0.2 m

T

BUFFER LAYER

S i - SUBSTRATE

Sb DOPING SPIKE

2.3.5 MODFET Ev

In Sect. 2.2 we have considered the Ge,Si, -,/Si system. A Ge,Si, -, layer can be grown epitaxially on a Si substrate as a strained layer without interfacial misfit dislocations as long as the thickness of the Ge,Si, -,layer is less than the critical thickness (e.g., for x = 0.2, the critical thickness L , is 1600 A, and for x = 0.5, L , is 140 A).

p 0 0 . i +1ooA

+1ooA+2ooA

1 - 5 1 Ge,Sil-, GeaQias GRADED LAYER

+2000AI-SI

Gea2sSio.n BUFFER LAYER

(b) Figure 2-32. (a)Cross section of a GeSi/Si MODFET structure. (b) Band diagram of the n-channel MODFET at thermal equilibrium (after Daembkes et al., 1986).


are formed by thermal evaporation of AuSb. The gate is formed by electron-gun evaporation of a Pt/Ti/Au sandwich of 1000 A/IOOO A/1500 A thickness. The gate length and width are 1.6 and 160 pm, respectively, and the drain-to-source spacing is 5 pm. A schematic band diagram of the nchannel MODFET is shown in Fig. 2-32 b. A 2 DEG is formed in the undoped Si layer adjacent to the Geo,,Sio., layer. Because of the Ge,Si, -,graded layer we avoid the formation of a second quantum well near the surface. The device shows good FET characteristics with a transconductance of 70 mS/mm. The mobility is 1550 cm2 V - ' S - ' near the heterojunction interface. The cutoff frequency is 2.2 GHz. These values are all higher than those of a comparable Si MESFET, indicating the improved transport properties of electrons in the MODFET. Various device optimizations can be made so that the device can have substantially higher transconductance and higher cutoff frequencies. The Si n-channel MODFET can be combined with Si p-channel MODFET to form highperformance Si complementary-logic circuits (Daembkes et al., 1986). A MODFET consisting of p-Geo,,Sio,,/ Ge/Geo,,,Sio,,, with a strain-controlled Ge channel can be fabricated by MBE. A cross section of such a device is shown in Fig. 2-33. A 0.5 pm Geo,75Sio,,5buffer layer is grown on a (100) Ge substrate by MBE. A thin Ge film (200A) and a thin Ge,.,Si,,, film (150 A) are commensurably grown on the buffer layer. For the doping, Ge atoms are adsorbed on the Geo,,Sio,, surface. Finally, a Geo,,Sio~,film (150 A) is deposited. The strain at the heterointerface between p-Geo,,Sio., and Ge is controlled by the Ge,Si,-, buffer layer. By proper choice of x one can maximize the valence-band discontinuity at the heteroin-

si02

93

(5008) \

1- f

2D-HOLE GAS

Al

AuGo

\\\\\\\\\

----- Geo.sSio.s- - - -- GeXSii-, BUFFER LAYER

l50A 1508 2ooA

0.5 I r n

MISFIT SUBSTRATE

Figure 2-33. Cross section of a strain-controlled Gechannel MODFET (after Murakami, 1991).

terface and enable sufficient confinement of the two-dimensional hole gas. The x value is chosen to be 0.75 to give maximum hole mobility. The p-channel MODFET has a ultra-high hole mobility of 9000cm2 V - ' S - ' at 77 K (Murakami, 1991).

2.3.6 Microvacuum Field Emitter One of the major limitations of highspeed semiconductor devices is the carrier velocity saturation due to scattering effects. The carrier velocity in a vacuum, on the other hand, can be substantially higher and is only limited by relativistic effects. Therefore, a microvacuum devices become an important area of study. Figure 2-34a shows a microvacuum triode with molybdenum field-emission cathodes, and a close-spaced Si anode that is made by microfabrication technology. The anodes are fabricated from a (100) p + silicon wafer. A thermal oxide, 2 pm thick, is grown on the wafer. The oxide is then lithographically patterned with 1.25 mm wide lines on 2.5 mm centers parallel to the (1 11) plane. This pattern is transferred by anisotropic etching of Si using KOH to the depth required for emitter-to-anode spacing (up to 20 pm).After dicing, the silicon anode chip is positioned so that the SiO, straddles the emitting area. The anode is

94


-------_-- v,

0

= 120

_i 200

100

Va (VOLTS1

(b) Figure 2-34. (a) Microvacuum triode with closespaced Si anode. (b) Current-voltage characteristics of the microvacuum triode (after Holland et al., 1990).

supported by a layer of SiO, resting on the gate electrode. Electrical contact is made to the back of the Si anode chip, which is coated with TiW. BUILT-ON-ANO\DE

’’

/

I 1 ‘ c -

--

Figure 2-34b shows a set of currentvoltage characteristics for a triode that has an emitter-to-anode spacing of 8 pm. The measured transconductance is 1 pS for a cathode with 2500 emitters. The average tip current is 4 nA per emitter. The transit time is 4 x 1 0 - l ’ ~at 60 V. The advantage of the Si anode is that much lower anode voltage is required due to the small anodeto-emitter spacing. However, additional studies are needed to improve the transconductance and the emitter current (Holland et al., 1990). Figure 2-35 shows the cross section of a Si avalanche cold cathode. The device is fabricated on a (100) p-type Si epitaxial wafer ( 4 n c m ) grown on a p + substrate. The emission current is measured with a stainless steel anode at a distance of 1 mm from the cathode. Standard IC processing, including implantation of B, As, and P, is used to fabricate the cold cathode. The As peak is located at a depth of 120 A, and the junction depth is 300 A. When the device is reverse-biased to avalanche breakdown, the reverse current I increases linearly. The emission current I D also increases approximately linearly with increasing I,. The emission efficiency q is defined as I E / ( I D I,). For a single cathode with a 40 pm diameter, a reverse bias of 6.2 V, and an anode voltage of

+

..

p EPILAYER

p’ SUBSTRATE

=

METAL

~i02

nsi

Figure 2-35. Cross section of a Si avalanche cold cathode device (after Ea, 1990).

95

2.4 Quantum-Effect Devices

500 V, q is 2 x lo-’. The anode voltage can be lowered to 1 V and the emitter efficiency can be increased when the anode is replaced by cantilevered polysilicon beam to be constructed at a distance of 1-2 p from the emitting cathode as shown by the dashed line in Fig.2-35. Because of the small area (2x20pm2) of the proposed cantilevered polysilicon beam anode, the expected capacitance is a fraction of a picofarad, thus subpicosecond transit-time operation is posible (Ea, 1990).


well, quantum wire and even quantum dot. For example, a resonant tunneling device was fabricated (Takeda et al., 1990), and the multiple quantum-well structure revealed a n excellent infrared detection capability (Kesan et al., 1990). A resonant hotelectron transistor has also been fabricated (Rhee et al, 1989). All these devices will be presented in the following sections.

2.4.2 Quantum Wells, Wires, and Dots In the three-dimensional case, the energy E versus wave vectors k I,k i l can be expressed as

2.4.1 Introduction The quantization effect in field-effect transistors was first observed in a MOSFET in 1966 (Fowler et al., 1966). A twodimensional electron gas (2DEG) in nMOSFET and a two-dimensional hole gas (2DHG) in p-MOSFET are present in the triangular potential well right next to the SiO, -Si interface. Modern lithographic technology can fabricate a MOSFET with a channel length and width of 0.1 pm. For such a small channel, we can find only “one” interface state in the channel, if the interface state density is 10” states/cm2. Recently, single-electron trapping was observed. Employing the quantum wire as the channel of a MOSFET, e.g., a MOSFET with a channel length of 1 pm and a channel width of 10 nm, revealed many interesting physical insights (Pepper, 1990). In addition, using resonant tunneling phenomena, different kinds of structures can be made such as the effective-mass filter (Gennser et al., 1990), energy filter (Gennser et al., 1990), and the wave function filter (Rajakarunanayak, 1989), etc. Recent developments in GeSi technology can be employed to fabricate quantum

(2-22) where k I is the wavevector perpendicular to k l l and m , and m l l are the effective masses in the corresponding directions. However, in a quantum well a standing electron wavefunction is formed. This implies a quantized energy in this direction ( z in real space and k l l in reciprocal space). The wavevector k l Iis

In: k l l = - 1=1,2,3 ) . . . (2-23) Lz The E - k relation in a band (conduction or valence band) is given by hZk t hZ E ( k ,, 1) = -+ 122m, mllL2,

(2-24)

The low dimensionality can be further reduced to one dimension and to zero dimensions, in which the transverse wavevector k I is further quantized. Generally, the density of states (DOS) in d dimensions can be found. The number of states per unit volume in k-space is (2 x ) ~ , where d = dimensionality. The total number of states 2 in volume &(d) in k-space is (2-25)

96


In a multivalley semiconductor, using iJv for the valley degeneracy,

The energy-k relation is given by

for isotropic effective mass m. Therefore, the DOS per energy E to E+dEis

= 1.587 x

10"(~)(~)/(cm2meY)

for (100) Si e(E)=-=dE

-

dk dk states/( V d')energy) (2-26)

= 2.8 x 10'O/(cm2 meV) for GaAs In a one-dimensional system

For example, in a three-dimensional (3D) system, a free-electron-like gas has spin

dZ 8xk2 dk ( ~ I T dE h2k -=dk. m -=-

k

=

d Z- - 4 dk -27c

) ~

(2-29)

(2 m E)12 h 212 m 3 2 E12

Q3D(E)

=

7c2h3

(2-27)

In 3D, the DOS is proportional to the square root of energy. In a two-dimensional (2 D) system,

- -

-~ mll

h2kil nh2 The DOS is independent of energy.

(2-28)

In a zero-dimensional (OD) system, the DOS becomes a delta function located at each quantized state. The DOSs of 3D, 2D, 1D, and OD systems are shown in Fig. 2-36. Realizations of a 2 DEG or 2 DHG in a Si system have been shown previously. However, a quantum-wire-channel MOSFET, shown in Fig. 2-37a, has also been fabricated (Takeda et al., 1990). There are two gates, the first and the second, fabricated by electron-beam lithography. Their widths were both varied from 0.1 pm to 1.0 pm. The channel length from source to drain is approximately 2 pm. The second gate, which has a 10 nm gate oxide, creates the narrow conducting channel. In Fig. 2-37 b, the transconductance g,( = aI,,/a VFG) is found to show oscillatory behavior and negative differential resistance, which implies a resonant transport.

97

2.4 Quantum-Effect Devices FIRST GATE

B"'v I

I

..

\ ,';

-4 -VS 5 vVG

i

I 0.1 ps

i.

E

lu poDu 2

i = l

+.-I

0

3

(C 1

QUANTUM DOT

i =

1

3 4 5

(d

-

E,Ei

1

I

4.2 K I

I

2

1

,v,

I

(V 1

(b)

Figure 2-36. Density of states in (a) 3 D, (b) 2 D, (c) 1 I),and (d) 0 D systems.

Figure 2-37. Quantum wire channel MOSFET: (a) device structure; (b) transconductance oscillation in narrow Si inversion layers.

The quantum-dot structure can be fabricated by the following process steps. As shown in Fig. 2-38, thin layers of Si and GeSi are deposited on a Si substrate by MBE or a UHV/CVD process. After a mesa etching, an SiO, layer can be formed by a low-temperature oxidation step such as high-pressure oxidation (HIPOX) or plasma-enhanced chemical vapor deposition (PEVCD). Finally, a narrow metal gate strip is formed on the top oxide. If the dimensions L,, L,, L , are smaller than the

de Broglie wavelength (about 200 A at 300 K), a quantum dot is formed.

2.4.3 Resonant-Tunneling Diode The quantized states in a double-barrier quantum well (DBQW) are shown at the left in Fig. 2-39. The resonant phenomenon is analogous to the resonant transmission of light through a Fabry-Perot etalon. In DBQW, an electron wave behaves like a light wave.

98

2 Silicon Device Structures ,GATE

W

INVERSION LAYERS (QUANTUM WIRES 1

METAL

Figure 2-38. Structure of a quantum dot.

LY

Consider an electron at energy E incident on the one-dimensional DBQW structure. When E matches one of the energy levels Ei in the QW, the amplitude of the electron de Broglie waves in the QW increases due to multiple scattering, and the waves leaking in both directions cancel the reflected waves and enhance the transmitted ones. Near resonance one has (Luryi, 1990)

where Tl and T, are the transmission coefficients of the two barriers at the energy E = Ei and y = h/z is the lifetime width of the resonant state [quasi-classically,y z Ei

(Tl = T,)]. In the absence of scattering, a system of two identical barriers (TI = T2)is completely transparent to electrons entering at resonant energies and the transmission coefficients, plotted against the incident energy, have a number of sharp peaks, as shown at the right in Fig. 2-39b. A GeSi/Si double-barrier resonant-tunneling diode (DBRTD) was fabricated (Rhee et al., 1988). Figure 2-40a shows the energy barrier diagram in the valence band. Figure 2-40 b is the current-voltage characteristic ( I - V ) in which a resonant tunneling peak can be clearly observed around 300 meV at both 4.2 K and 77 K. The peak is due to the transmission through the light-hole ground state Elht (higher energy not shown).

B

0.8

Y

0.6

a

w

z w

0.4

.---

u

L

id

zY

c z w

i -- 1 uo 9 V

10-4

10oA

Si

GexSii-x

Figure 2-39. Double-barrie1 resonant-tunneling diode (DBRID): (a) quantized states in the well; (b) transmission coefficient vs. energy E (after Luryi, 1990).

Si

I 0-8

TRANSMISSION COEFFICIENT

5


index confinement region that permits effective waveguiding in the silicon overlayer. A silicon ridge was used as the waveguide. A multiple quantum well (MQW) layer was imbedded in a p-i-n structure as shown in Fig. 2-41 a. The 40 8, Si,,,Ge,,6/210 A Si, 28-period layer is equivalent to an average Ge composition of 10%. The response of the detector as a function of wavelength at 10 V reverse bias and at room temperature is shown in Fig. 2-41 b. A 50% internal quantum efficiency was obtained at 1.1 pm wavelength with an impulse response time of 100 ps (Kesan et al., 1990).

I

84-

c

99

2-

z w

2.4.5 Resonant-Tunneling Hot-Electron Transistor

a [L

3 0

u 0

8 -.

I

I

I

-800 -400 -200

I

I

200 400 DC VOLTAGE (mV)

0

800

(b) Figure 2-40. (a) Schematic band diagram of the double-barrier diode. For the structure used in this experiment, W, = W, = 50 A, W, = 40 A, and x = 0.4. (b) Observed current-voltage characteristics for the structure at three different temperatures (after Rhee et al., 1988).

The heavy-hole ground state Ehhl can only be seen by dI/dV or d2i/dV2 measurement because of the large tunneling effective mass. At higher bias a second peak occurred at 900 meV in the dl/dV measurement due to the first excited heavyhole state EhhZ(Rhee et al., 1988).

2.4.4 Multiple Quantum Well Detector The Si-Ge heterostructure makes the realization of a Si-based 1.3 pm long wavelength optoelectronic detector possible. Silicon-on-insulator (SOI) structures are used. The buried-oxide layer forms a low-

When a double-barrier resonant-tunneling diode (DBRTD) is imbedded in a structure, as in p + (Ge,,,Si,,,)-DBRTDP+ (Geo.5Sio.5) base-i (Ge,, 2Si,, &p (Ge,,,Si, ,6), a hot-electron transistor (HET) is formed. The HET exhibits negative differential resistance (NDR) in its current-voltage (I- V ) characteristics (Rhee et al., 1989). Because of its high-speed tunneling capability and negative differential resistance, integration of such a device into Si-based circuits could find applications in high-speed digital circuits, frequency multipliers, multistate logic circuits and tunable oscillator/ amplifiers. The HET samples were grown on highly doped p-type 400 “C) in order to minimize the damage to the surface layer. The growth characteristics and physical structure of the buried oxide and the single-crystal silicon produced by the SIMOX process has been studied extensively over the past several years, During the implantation, the oxygen concentration first forms a skewed Gaussian profile, but once the oxygen dose is sufficiently high the distribution becomes flat-topped, with a peak oxygen concentration corresponding to stoichiometric S O , . It has been found that al~rlTlalt

,

After Annealing

Figure 3-12. Scheme of SIMOX process.

3.3 Device Isolation

though the SIMOX buried oxide is in many ways similar to thermal oxides, it differs significantly in both conduction characteristics and radiation response. High temperature annealing ( > 1300“C) is performed following the implantation to eliminate crystallographic damage in the surface silicon layer, and to allow oxygen from the tails of the implanted distribution to diffuse to and be incorporated in the SiO, layer. After annealing, the dislocation and stacking fault density in the top silicon layer was quite high, i.e., approximately l o 4 to lo6 per cm’. Such high density of dislocations and stacking faults remaining in SIMOX wafers after annealing can cause emitter-collector shorts in bipolar devices, similar to the effects of these crystallographic defects on devices built in bulk material. As a result, SIMOX wafers cannot be used for ULSI bipolar applications. On the other hand, the effects of crystallographic defects in SIMOX material on CMOS devices can be minimized. The majority of applications of SIMOX SO1 technology are found in CMOS devices designed for operation in harsh environments. The typical SO1 materials needed for these applications have buried oxides with thicknesses in the range of 0.4 pm, and silicon layers with thicknesses of 0.3-0.5 pm. The SIMOX process is ideally suited to producing material with these layer thicknesses. Even with the device demonstrations, the major stumbling block for the use of SO1 technology in any large scale applications has been the credibility of supply of high quality SO1 at reasonable costs. A fundamental problem of buried oxide “pipes” are plagued SIMOX wafers. These buried oxide “pipes” are observed as conductive threads of silicon through the oxide. Measurements also showed that there are “partial pipes”, that is, areas which appear as thin oxide regions

133

in the SIMOX materials. The buried oxide pinhole problem has been correlated with particles on the wafers during the implantation step. The “pipes” are a result of the shadowing of specific areas from the oxygen implant by the particles. Eliminating these defects has not been a trivial task since particles can be generated in the clean-up before wafers are implanted as well as in the implanter itself. The wafer bonding process is illustrated in Fig. 3-13. In this process, two silicon wafers which have a very high degree of flatness are used. One, or both, of the wafers are oxidized. The surfaces are then mated, and the composite is annealed to form a single structure. One of the wafers is then used as a handle, and the other wafer is thinned from the back side until only a thin superficial silicon film is left. Several techniques for the thinning process have been used, including both physical and chemical techniques. In some methods, an etch stop is either implanted or diffused into the wafer to be thinned before the bonding process; initial thinning is accomplished by a mechanical process to produce a film in the range of several micrometers thickness. The final thinning is then accomplished by a chemical etch Two Flat Si Wafers Wafer 1 Wafer 2

1

I Oxidize, Bond, Anneal

Wafer 1

-

Oxide

Grind, Polish or Preferential Etch

r Wafer 2

Figure 3-13. Scheme of wafer bonding process.

134

3 Silicon Device Processing

back using a preferential etchant and an etch-stop layer. The structure of the superficial silicon films on bonded wafers are expected to be very similar to those of the bulk wafers used in the SO1 fabrication. This is generally found to be the case, at least for superficial silicon layers down to a thickness of a few micrometers. Typical crystal defect densities in bulk silicon are < 1o2/cm2. With the usual wafer grinding and polishing techniques used for silicon IC substrates, it is difficult to produce uniformities superior to & 0.5 pm. Although thinner superficial silicon layers can be produced with chemical etch stop techniques, this is at the expense of added process complexity and the possible introduction of defects due to the etch stop layer itself. Because it is relatively difficult to control the thickness of bonded wafers within very small ranges, these materials have been primarily applied to bipolar devices. In bipolar circuits, the superficial silicon layer must be essentially free of crystallographic defects, and is typically used to form a deep collector. This requires a thickness in the range of 2-4pm, with tolerances of f 0 . 5 pm. The wafer bonding approach is ideally suited for this application. Ultrathin bond and etch-back silicon on insulator (BESOI) in the thickness range of 75 to 100 nm offers the potential for performance enhancement in both CMOS and BiCMOS technology (Omura and Izumi, 1990; Shahidi et al., 1991). To be useful however, a very low total thickness variation (ttv) is desirable, typically below 10 nm. With the conventional grinding technology ttvs around 300 nm can be obtained, with ultra-precision grinders even better ttvs are possible (Abe et a]., 1992). Nevertheless, conventional grinding technology may be incapable of achieving the ultra-low ttvs which are required by these

new applications. Recently, several polishing techniques have been reported that utilize polish stops to achieve high ttvs with selected patterns. While these techniques are useful, they are expensive and do not yield a generic wafer. A unique plasma thinning technology has been demonstrated to be able to thin the superficial silicon on bonded wafers to thicknesses of 0.3 pm or less, with thickness tolerances of less than f 0.01 pm (Mumola et al., 1992). This may allow bonded wafers to be used for both CMOS and bipolar devices. Bonding of an oxidized wafer to another wafer was proposed by Lasky and coworkers (1985). They developed an ion implanted etch stop technology to thin the device wafers. Mazara (1991) and Hunt et al. (1991) extended this technique to include a double etch stop. A potential high throughput BESOI process that is capable of achieving both intrinsic high quality (both silicon and oxide) and versatility as well as high uniformity was developed by Iyer et al. (1993) using a well-defined and highly uniform etch stop system. The Si-Ge etch stop layers are deposited by low temperature UHVCVD epitaxial techniques (Iyer et al., 1989). After a low temperature joining and bonding process, the device wafer is thinned by moderate ttv grinding, followed by a damage removal step. The device wafer is then selectively etched in high selectivity silicon etch with the etching stopping well within the etch stop system. The etch stop layers are then separately removed in another selective etch. After taking into consideration the uniformity of the epitaxial processes, grinding and etching processes, a ttv that is typically well below 10 nm is routinely achieved with minimal edge loss. Electrical characterization of SO1 films showed superior carrier lifetimes and FET devices characteristics.

135

3.4 Gate Dielectrics

CMOS TECHNOLOGY TREND

The bonding interfaces must be free of bubbles. Bubbles are mainly caused by particles and adsorbed gases on silicon surfaces such as hydrocarbons. These particle-related bubbles can be eliminated by mating two wafers in an ultra-cleanroom (class 1 or better) or by using a micro-cleanroom set up (Mitani et al., 1991). Bubble generation caused by adsorbed gases can be prevented by degassing before wafer bonding (Mitani et al., 1991). Bonding strength is monotonically increased with increasing the annealing temperature due to atomic phase change at the bonding interface and the thermal flow of oxide at high temperature.

l

0

1000

-

-

Low defect density Good barrier properties against impurity diffusion High quality Si/SiO, interface with low interface state density and fixed charge

-

“Q v)

W

z Y

uI t-

W

E I

100

0 *

s W

3.4 Gate Dielectrics As device dimensions continue to shrink, a commensurate reduction in the gate oxide thickness is required, as shown in Fig. 3-14 (Taur et al., 1993), primarily to prevent the short-channel effects. For example, an excessive reduction in channel length without an adequate thickness scaling can result in threshold voltage instabilities due to charge sharing effect as well as excessive subthreshold and off-state currents due to drain-induced barrier lowering and punchthrough. Thus, in order to minimize the undesirable short channel effects while ensuring high performance of the device, gate oxide thickness scaling is a very efficient approach. In other words, by scaling the oxide thickness, the behavior of a MOSFET can be made more long-channel-like. Thin gate oxides ( < l o 0 A) in ULSI MOS applications should meet the following crucial requirements :

7

..

I

110

0.I

1.0 MOSFET CHANNEL LENGTH (pm) Figure 3-14. CMOS technology trend

-

-

Stability under hot carrier stress and irradiation Low thermal budget processing

Low defect density in the oxide ensures that the number of catastrophic oxide failures at low electric fields is minimum. One method to characterize oxide integrity is breakdown histograms. This well-established method categorizes failure modes as either mode A, B, or C (Sanchez et al., 1989). Mode C failures represent intrinsic oxide breakdown while mode A failures are related to surface foreign material such as unintentional contaminants, impurities and particles. Mode B failures on the other hand are largely related to silicon material crystallographic defects such as as-grown stacking faults and SiO, precipitates and process induced crystallographic defects. Other causes for Mode B failures are listed in Table 3-2.

136


Table 3-2. Causes for B-mode failures in oxide. 1 . Local electric field intensification a. Local oxide thinning b. Residual nitrogen at surface (Kooi effect)

2 . Charge trapping of oxide a. Electron trapping water related traps non-bridging oxygen defects dopant impurities b. Hole trapping oxygen vacancy

3. Crystal quality a. Metallic contamination b. Surface roughness c. Oxygen precipitates 4. Process-induced damage

a. Reactive ion-etching b. Photoresist ashing

Improved barrier properties are particularly important for p+-polysilicon gated p-MOSFETs. Low interface state density ensures a sharp switching characteristic in MOSFETs. High lateral electric fields in the channel in the downscaled MOSFETs lead to significant heating of channel carriers, resulting in hot carrier effects such as oxide charge trapping and interface state generation. The use of a gate dielectric which suffers minimum damage under hot carrier stress is a promising option in aggressively scaled MOSFETs. Processing techniques such as reactive ion etching (RIE) and some of the future tools such as X-ray lithography can expose gate oxides

to high energy plasma and radiation, which are known to reduce the quality of gate oxides. This imposes the requirement of the radiation “hardness” on thin gate oxides. Finally, low thermal budget is necessary in ULSI in order to minimize the redistribution of dopants by diffusion. The main thrust in the gate dielectric research in recent years has been addressed to the above mentioned issues. Numerous techniques have been suggested to solve one or more of these problems. These techniques can be broadly divided into four categories. The first approach involves variations of pre-oxidation cleaning procedures. The second approach involves process variations of the oxidation process. The third approach, which has received considerable attention over the past decade, is to chemically modify the properties of gate oxides. The final approach is deposition of oxides or formation of stacked layers as gate dielectrics. 3.4.1 Preoxidation Cleaning

The fundamental role of a silicon cleaning procedure is to remove from the surface (a) organics, (b) transition metal and alkali ions and (c) particulates. These contaminants, if not removed from the wafers prior to oxidation, can affect the quality of the gate oxide. Common wet cleans and their application are listed below:

0

HF/H,O

etching native SiO, layers

0

H2S04/H20,( 5 : l ) NH40H/H 2 0 2 / H 2 0(1 : 1 : 5 ) (SC-1)

removing heavy organics

HCl/H20,/H20 (1 : 1:5) (SC-2) Effects of NH,OH/H,O, ratio:

removing metallic species

0

0

0

removing light organic residue and particles

High: good for particle removal Low: less surface roughening

137


The RCA cleaning procedure, proposed by Kern and Puotinen (1970), is still used widely in its original form or with minor modifications. The cleaning procedure consists of two steps. The first step involves cleaning in a hot, high pH H,O, SC1 solution (H,O/H,O,/NH,OH = 5 : 1 : 1) in order to remove organic contaminants from the silicon surface by oxidation. The second step involves treatment of the silicon surface with a hot, low pH H,O, SC2 solution (H,O/H,O,/HCl= 5 : 1:1) to remove the metal contaminants via metal complex formation. An additional intermediate step of dilute H F dip is often used to remove the oxide grown during the first cleaning step. A detailed review of the chronological development of the cleaning processes has been published by Kern (1990). As the oxide thickness is scaled down to below 100 A, the requirements on the cleaning processes have become more stringent. Although RCA or modified RCA clean are adequate in effectively removing the surface contaminants, these cleaning treatments can also lead to surface microroughness due to the presence of alkaline NH,OH solution used. Ohmi et al. (1992) investigated this phenomenon in detail and reported that microroughness causes lowering of breakdown electric field and charge-to-breakdown in gate oxides grown on these surfaces. They suggested the use of a 5 : 1:0.25 H,O/H,O,/NH,OH solution, rather than the traditional 5 : 1 :1 mixture in order to prevent the surface microroughness. Optimization of the NH,OH/H,O,/H,O ratio in the SCIcleaning has been studied by Meuris et al. (1992). It was found that both metal contamination and particle densities were equal after the complete RCA cleaning for wafers processed using SC1 with different mixtures (NH,OH/H,O,/H,O =0.1- 1 : 1 :5).

From this, one would normally expect similar breakdown properties of subsequently grown gate oxides. However, large differences were found in yield. The 0.25:1:5 SC1 mixture results in much higher gate oxide integrity than the 1:1:5 mixture due to the Si-surface roughness caused by SC1 solutions. A qualitative model for the action of the SC1-cleaning helps to understand the observations (Meuris et al., 1992). When silicon is exposed to the SC1mixture, the peroxide will oxidize the silicon surface while the ammonia will disperse this chemical oxide; i.e. a chemical oxide layer will continually form and dissolve as a result of the compensating effect of the two chemical components. This process slowly etches the silicon. A high etching rate will increase the particle removal efficiency by undercutting the particles, but will cause a larger surface roughening during 10 min of cleaning. Consequently, it is important to find an optimum between particle removal efficiency and silicon surface roughening. An etching rate of 0.2 nm/ min was found to be the best. New cleaning solutions such as choline are also being used (Kao et al., 1989) with a reduction in defect density in oxides. The metallic contamination on Si wafers after various cleaning treatments is shown in Table 3-3 (Verhaverbeke et al., 1991). In general, a final cleaning step in H F results in lower metallic contamination compared with standard RCA cleaning. Surface metal Table 3-3. Typical metallic contamination after various final cleaning steps followed by DI water rinsing (10" at/cm2) (Verhaverbeke et al., 1992).

K

Ca

Cr

Fe

Ni

Cu

Zn

0.3 0.06 0.09 3.7

0.4 0.1 1.2 0.7

~

RCA HF HF/H,O, BHF

0.3 0.1 0.6 0.2

8.6 3.8 1.6 1.4

0.2 5.1 3.3 0.05 0.3 0.1 0.3 2.2 0.2 0.4 2.6 0.3

138


contamination resulting from SC-1 solutions include the following: -

Fe will form non-soluble iron hydroxide under SC-1 conditions; Iron hydroxide can be removed during SC-2 cleaning; Electrochemical plating of noble metals (e.g., Cu) from HF.

The hydrogenated surface resulting from H F etching allows electrochemical reactions with noble metals to occur. The reaction product is mostly a silicide, a chemical substance very difficult to remove in a subsequent set of chemical cleaning steps. Cu is present in an acid HF-solution with a higher half-cell potential than hydrogen and, therefore, can be deposited on the Sisurface from an HF-solution (Kern et al., 1991). This can be avoided by using highly purified chemicals or by adding small amounts of H 2 0 2 to the HF-solution (Ohmi et al., 1991). Contaminants in the chemicals used in wet etching and DI water distribution system have been major sources of metallic impurities which reduce the gate oxide integrity. In a recent work (Verhaverbeke et al., 1991), roles of various metallic contaminants on the gate oxide breakdown properties were studied. Ca was found to interact strongly with the Si substrate, resulting in interface roughness and deterioration of breakdown properties. Whereas Fe was observed to degrade the oxide integrity by forming defect spots during oxidation, A1 was shown to cause damage under the polysilicon gate/SiO, interface. Unlike Fe and A1 contamination, Ca contamination is largely unaffected by the gettering cycle. This is consistent with the fact that Ca is mainly located in the thermal oxide. From these results it can be concluded that for gate oxide integrity, Ca is the most important contaminant. The Ca

contamination can be avoided by using ultra-pure chemicals, ultra-pure distilled (DI) water, a carefully designed DI-water distribution system and by final cleaning with H F (Verhaverbeke et al., 1992). After the last cleaning step with HF, the metallic contamination on the Si-surface is lower on the average than after an RCA-cleaning for the typical metals found after a stateof-the-art cleaning. Owing to their low metallic contamination, HF-dipped surfaces are well-suited for the growth of highlyreliable thin gate oxides. However, hydrophobic surfaces are well-known to be susceptible to particle deposition, particularly during subsequent DI-water rinsing (Table 3-4). These particles can be reduced significantly after oxidation. Table3-4. Particles on a 5 inch wafer after HF-dip and rinse-dry (Verhaverbeke et al., 1992). N, Spin Spin manual dryer rinseblow dryer ~

HF-dip/no rinse HF-dip/overflow rinse HG-dip/quick dump rinse

7 400 3100

_

_

_

250 6900 500 6100 1200 7600

By adding minute amounts of isopropyl alcohol (IPA) to the HF-solution (Verhaverbeke et al., 1992), the deposition of particles on the Si surface can be prevented during HF-dipping and subsequent rinsing and results in highly reliable oxide layers. By adding 200 ppm or more IPA to the 0.5 YOH F solution, the particle deposition is dramatically reduced. The IPA does not chemically react with the Si surface; it is only physically adsorbed and desorbs readily at moderate temperatures. As the devices become smaller and smaller, there are several serious concerns for wet chemical cleaning. These include :

_

3.4 Gate Dielectrics -

-

-

Particulates generated after cleaning; Drying difficulties (watermarks) ; Large amount of hazardous waste chemicals produced; Inability to clean small contact holes with large aspect ratio; Incompatibility with certain existing processes ; Incompatibility with integrated processing.

For these reasons, dry cleaning processes have attracted significant attention (Moslehi et al., 1992; Ruzyllo et al., 1989) over the past several years. Advantages of dry cleaning include : -

~

-

-

A “cleaner” process; Gas reactive species have easier access to the wafer surface, capable of penetrating minute, high aspect ratio trenches ; Significant reduction in chemical waste disposal ; Can be incorporated in situ for integrated single wafer processing; Removal of metal and organics can be achieved by using UV-enhanced or plasma dry cleaning.

Ruzyllo et al. (1989) reported that the use of UV treatment on wafers in an 0, ambience to remove organic contaminants had no detrimental effect on mean time-tobreakdown ( t b d ) as well as t,, distribution. Kao et al. (1991) used a vapor phase HF/ HCl cleaning procedure and observed a ten-fold increase in t,, for the subsequently grown gate oxides compared to the oxides on RCA cleaned wafers. Kasi and Liehr (1 992) concluded that a pre-oxidation high temperature UV/O, treatment can effectively remove the hydrocarbon contamination. Fukuda et al. (1992) adopted a rapid thermal cleaning approach in which the wafers, initially subjected to H,SO,-H202 cleaning and 1 % HF dip were treated in

139

either H, or HCl/Ar ambience for various temperatures and durations. It was concluded that the HCl/Ar cleaning removes metallic impurities as well as the native oxide, whereas the H, cleaning is unable to remove the metallic impurities.

3.4.2 Process Dependence of Gate Oxide Quality The impact of gate oxide temperature on the quality of the gate oxides has been investigated by several researchers. For example, in an earlier work, Deal et al. (1967) reported that the fixed positive charge in the oxide decreased nearly linearly with increasing oxidation temperature. Hahn and Henzler (1984) studied the structural and electrical properties of the Si/SiO, interface as a function of oxidation temperature. They reported a strong correlation between the atomic steps at the interface, which were taken as a measure of roughness, and the electrical properties and concluded that high temperature oxidation results in a smoother interface with less interface states and less fixed charge. Fukuda et al. (1992) also indicated that high temperature (1200 “C) RTP oxidation results in a superior gate oxide with lower interface state density, longer t,d and tighter t,, distribution, as compared to low temperature (800 “C) furnace grown oxide. Walters and Reisman (1990) reported that the density of electron traps in the gate oxide decreased with an increase in oxidation temperature from 800°C to 1000°C. Joshi and Kwong (1992) reported that MOSFETs with gate oxides grown at high temperature show improved electron and hole mobility as well as suppressed degradation under radiation and hot-carrier stress, as shown in Fig. 3-15. The improved mobility was attributed to the formation of a smoother interface at elevated

140


560 m

. j

N

5

v

0 E,ff = 0.2 MVlcm . o Eeff = 0.8 MVlcm

550 -

9 z B 540

-

- 320

"*.,

,''

I'

-310

/

?

1;

J2 .2

M

Q-----&'

i L

+ -5s

/

,, /

/

- 330;

p--,P

/'

-

0

5

340

- 300

L 0

530

xO0

"

'

900

I

'

1000

"

'

1100

'

290

0 12Uu

TEMPERATURE ("C)

Figure 3-15. (a) Effective electron mobility (p,,) for two values of effective electric field (Eeff)in MOSFETs with gate oxides grown at different temperatures. (b) Increase in off-state leakage current (Aid,) and transconductance degradation as a function of gate oxide growth temperature.

temperatures, while the improved reliability was attributed to interfacial strain relaxation by viscous oxide flow at temperatures above 960°C (EerNisse, 1977). These studies suggest that high temperature oxidation is preferred in order to achieve good performance and reliability in gate oxides. Consequently, rapid thermal oxidation at high temperature appears to be a suitable approach for gate oxide growth in ULSI MOS devices. Apart from the higher growth rate, suppressed number of early breakdown as compared to dry oxides is an attractive feature of wet oxides (Irene, 1978). Wu et al. (1989) observed that wet oxides

-

show very sharp t,, distributions with 15 x larger t,, values as compared to dry oxides. Li and Chang (1988) used a two step approach to grow gate oxides, with a combination of dry-dry, wet-dry and wetwet processes. The wet-wet process resulted in the minimum defect density. A systematic decrease in the number of low field breakdowns was observed with an increase in wet oxygen partial pressure during oxidation. Recently, wet oxides have been implemented in a 0.8 pm technology and some attractive features have been reported (Wei et al., 1992). The comparison was made between 850°C wet oxide MOSFETs and 900°C dry oxide MOSFETs. The breakdown histograms were comparable in both the cases, unlike the significant improvement for wet oxides reported in earlier studies. A 10% increase in linear transconductance was observed in n-channel MOSFETs with wet gate oxides. However, in p-channel MOSFETs, where electron trapping during hot carrier stress is the dominant degradation mechanism (Koyanagi et al., 1984), wet oxide devices are somewhat worse than dry oxide devices. The use of high pressure oxidation was suggested for growing thick field oxides, e.g., in a LOCOS isolation (Baglee et al., 1984). The major advantage of high pressure oxidation is an enhanced growth rate as compared to atmospheric pressure oxidation. If atmospheric pressure oxidation is used to grow thick field oxide necessary to provide isolation between adjacent MOSFETs, high temperature/long duration processing is necessary. For example, a 3000 A field oxide can be grown by wet oxidation at 1000°C in about 2 h. Such a high thermal budget is not desirable in ULSI processing due to redistribution of dopants by diffusion. For example, channel width narrowing due to the encroach-


ment of channel stop implants into the active regions has been reported by Baglee et al. (1984). Due to the enhanced oxide growth rate, high pressure oxidation can be performed within a considerably smaller thermal budget either by lowering the oxidation temperature or by reducing the growth time. Since thermal budget reduction is crucial in ULSI processing, Tay et al. (1987) applied high pressure oxidation to grow gate oxides. At a pressure of 10 atm, an 120 8, thick gate oxide was grown at as low a temperature as 700°C. The pressure ramp-up was performed in N, ambience in order to avoid nonuniform oxide growth on wafers due to temperature instabilities. These oxides shows low interface state densities in the 1010 eV-' cm-, range. In a more recent work (Tay et al., 1990), the same research group demonstrated that high pressure oxidation at 700°C followed by nitrogen annealing at 900°C results in gate oxide films (80 A) with up to 15 MV/cm breakdown field and high quality Si/SiO, interface. In an earlier work, it has been indicated that high pressure oxides and conventional oxides grown at atmospheric pressure show similar radiation response (Gupta et al., 1980). Although the high pressure gate oxidation technique appears to be attractive due to its low thermal budget, a more detailed investigation is required to judge its applicability to ULSI MOS processing, especially regarding the MOSFET reliability. N

3.4.3 Chemically Modified Gate Oxides Over the past decade, a considerable amount of work has been reported on chemically modified gate oxides for MOS applications. The main goal of chemical modification is to introduce controlled quantities of impurities such as nitrogen or fluorine primarily at the Si/SiO, interface

141

to improve the interfacial properties that are critical to the performance and reliability of SiO, . The Si/SiO, interfacial region consists of a non-stoichiometric monolayer followed by a 10-40 8, thick strained SiO, (Grunthaner and Maserjian, 1978). The non-stoichiometric monolayer results from incomplete oxidation and the strained region is due to lattice mismatch between Si and SiO,, which causes a compressive strain in the interfacial SiO, . Relaxation of intrinsic strain at the Si/SiO, interface is an important technique to improve the reliability of MOS devices under electrical or radiation stresses. It is known that tensile strain exists in Si,N, in the Si,N,/Si system. This led to an approach which involves incorporation of a small amount of nitrogen in the interfacial region so as to oppose the compressive strain (Vasquez and Madhukar, 1985). Strain relaxation in such nitrided oxides is probably due to the formation of Si,N,O (Vasquez and Madhukar, 1986). Triangular planer bonding in Si,N,O allows a smoother transition from the tetrahedral bonding in silicon to amorphous SO,. In addition, since the Si-N bond strength is significantly higher than that of Si-H bonds, defect generation by hot carriers and ionizing radiation is suppressed. The other important advantage of introducing nitrogen into SiO, is the improved diffusion barrier properties to boron penetration, an extremely important requirement for p -polysilicon-gated surface-channel p-MOSFETs (Lo and Kwong, 1991). Incorporation of fluorine at the Si/ SiO, interface is another approach to modify the properties of MOS system. Fluorine has been suggested to satisfy some of the dangling bonds at the Si/SiO, interface (Wright and Saraswat, 1989). In a conventional process, the dangling bonds are satisfied by hydrogen during the sintering step. Since the bond strength of Si-F +

142


bonds (5.73 eV) is significantly higher than that of Si-H bonds (3.17 eV), defect generation by hot carriers and ionizing radiation is suppressed. Moreover, fluorine incorporation leads to strain relaxation at the interface (da Silva et al., 1987). Both these approaches to chemically modify thin oxides have been extensively studied. Annealing of gate oxides in NH, (Ito et al., 1982a; Lai et al., 1983) has been reported to achieve such desirable properties as good resistance against impurity diffusion (Ito et al., 1982a) and endurance against hot electron stress (Lai et al., 1983). Rapid thermal nitridation (RTN) is an attractive approach due to its low thermal budget requirement and good control over the resulting nitrogen profile (Moslehi and Saraswat, 1985). Reoxidation (Hori et al., 1989; Yang et al., 1988; Dunn and Scott, 1990; Joshi et al., 1992) or inert gas annealing (Wright et al., 1990) was proposed to reduce electron trap and fixed charge density in the nitrided oxides while still retaining the nitrogen-rich layer at the Si/SiO, interface. However, the electron traps induced by residual nitridation cannot be eliminated completely by reoxida-

tion or annealing, resulting in worse reliability in p-channel MOSFETs (Momose et al., 1991). The reoxidized nitrided oxides used in this case were prepared by rapid thermal processing after the conventional oxide growth. It turned out that reoxidized nitrided gate oxides are superior to pure oxides in numerous aspects. However, the presence of residual nitridation induced electron traps is a shortcoming in these dielectrics and, as a result, pMOSFET reliability is worse than that of the conventional gate oxide MOSFETs. The disadvantage can be avoided by using light NH,-nitridation, but such light nitridation may not be sufficient to prevent boron penetration into the channel region. This trade-off is depicted in Fig. 3-16 (Momose et al., 1991). Compared to NH,-based processes, the N,O-based processes have an important advantage in addition to the process simplicity, i.e., the elimination of any hydrogen-containing species during processing. Therefore, the hydrogen-related disadvantages can be avoided. Depending on process design, thermal budget limitation, and device applications, several processes have

Figure 3-16. Performance and reliability of RTN/ RTO SO, as a function of nitrogen concentration.


143

been developed to use the significant advantages offered by N,O process. These include Oxidation of Si in pure N,O (Lo et al., 1991); Nitridation of thermally grown SiO, in N,O (Ahn et al., 199221); Densification and Nitridation of CVD SiO, in N,O (Ahn et al., 1992b); Nitridation of N,O oxides in NH, for p+-poly-Si gated P-MOSFETs (Yoon et al., 1993).

Figure3-17. Comparison of the growth kinetics between N,O and 0, oxidation of Si.

The oxidation process is self-limiting compared with 0, oxidation, as shown in Fig. 3-17, allowing growth of ultrathin oxides with excellent thickness controllability. The process is simple, hydrogen-free and easy to integrate into modern ULSI processes. Because of nitrogen incorporation at the Si/SiO, interfizce during N,O oxidation, the resulting oxynitrides show lower hole trap density, reduced electron trap generation under high-field stressing, and reduced interface state and neutral trap generation under both hot-carrier stressing and X-ray irradiation in comparison to the control oxide. NH, nitridation of N,O-oxides does not reduce electrical and reliability properties of N,O-oxides, with the additional advantage of significantly improved resistance to boron penetration. Finally, study of hot-carrier related reliability in both n- and p-MOSFETs with N,O-based gate oxides under application specific stress conditions such as for SRAM-type pass transistors, CMOS logiccircuit transmission gates and CMOS analog devices shows that all the hot-carrier induced damages (i.e., interface states, electron/hole trapping, and neutral electron traps) are greatly suppressed in N,Obased gate oxides compared with control oxide devices (Yoon et al., 1993). These results suggest that N,O-based gate oxides

are promising for numerous MOS ULSI applications. Fluorine incorporation in the gate oxide has been performed by different techniques, such as immersion of Si wafers in HF prior to gate oxidation (Nishioka et al., 1988), F ion implantation (Lo and Kwong, 1991; Nishioka et a]., 1989) and NF, purge during or before gate oxidation (Lo et al., 1992). Different techniques produce different distributions of fluorine in the gate oxide, resulting in a wide variation of electrical properties. Since excessive fluorine incorporation in the oxide can lead to worse dielectric properties (Lo and Kwong, 1991; Nishioka et al., 1989), excellent control over the amount of incorporated fluorine is necessary which can be achieved by rapid thermal processing (RTP). Fluorination has been reported to increase fixed positive charge but suppress interface state density (Nishioka et al., 1989; Lo et a]., 1992). Wright and Saraswat (1989), on the other hand, reported a negative charge in the fluorinated oxides. The reduction in interface state density has been attributed to passivation of dangling bonds at the Si/SiO, interface by fluorine (Wright and Saraswat, 1989; Nishioka

~

-

-

z

C:

ion 0

0

~ ~ ~ " ~ ~ ~ ~

20

40

60

80

100 120 140 160

Oxidation Time (min)

144


et al., 1989; Lo et al., 1992), whereas the increase in positive charge is due to the formation of nonbridging oxygen defects by incorporation of fluorine in the oxide. Wright and Saraswat (1989) reported that the hot electron induced degradation in MOSFETs is considerably suppressed with an increase in the amount of fluorine incorporated in the gate dielectric. Lo et al. (1992), on the other hand, reported that both the amount and distribution of fluorine in the gate dielectric affect the hot carrier reliability of fluorinated oxides. Only a small process window was observed to result in improved hot carrier reliability as well as radiation hardness as compared to pure oxides. Moreover, the presence of fluorine at the Si/SiO, interface was found to be essential in order to realize a gate dielectric with superior reliability. The improvement in radiation and hot carrier immunity in fluorinated oxides has been mainly due to suppressed interface state generation. Interfacial fluorine incorporation has generally been accepted as a cause for the improvement (Ma and Dressendorfer, 1989). 3.4.4 CVD and Stacked Oxides

Deposition of gate oxide, rather than its growth from the substrate, is an attractive technique to suppress the density of defectrelated breakdowns in oxide films because the deposited oxides are less likely to be affected by the defects from the Si substrate. Another advantage of this technique is the feasibility of low temperature processing, which is an attractive feature from the viewpoint of stringent thermal budget requirements in ULSI MOS processing. Various CVD oxides such as TEOS, HTO, and LTO have been studied (Tseng et al., 1993). Ahn et al. (1992b) investigated hot-carrier reliability of MOSFETs with

z 65 LPCVD gate oxides (silane and oxygen reaction) annealed in presence of N, . The compressive stress in the films after post-deposition annealing was observed to be smaller than conventional thermal oxides, and was suggested to be the cause of improved current drive capability as well as hot-carrier reliability. In a recent report (Ahn and Kwong, 1992), N,O post-deposition is used instead of the conventional N, annealing in order to incorporate a small amount of nitrogen at the Si/SiO, interface. The resulting films show superior hot carrier reliability due to nitrogen at the Si/SiO, interface as well as low defect density due to the deposition of oxides, rather than growth from substrate. Roy et al. (1988) studied oxide films containing a stack of a “pad” oxide and a CVD oxide on top of it. The dramatic reduction in defect density observed in this stack layer was mainly attributed to misalignment of defects in individual components of the stack. Moreover, the stress at the Si/SiO, interface is close to zero due to the stress compensation between component layers. Kawamoto et al. (1987) demonstrated stacked layers with performance comparable to thermal oxide films. Tseng et al. (1991) used =I40 A stacked CVD oxides (40 8, thermal oxide and 100 8, LPCVD/TEOS) for 0.5 pm CMOS process and demonstrated several advantages. Firstly, the number of low field breakdowns was significantly smaller than for the conventional thermal oxides. In addition, due to the smaller levels of stress at the Si/SiO, interface, a large reduction in process induced damage was observed. An optimum ratio of bottom thermal oxide thickness to the top CVD oxide thickness was reported to achieve longer time-tobreakdown and lower defect density. The optimum ratio is a consequence of the compensation between the intrinsic defect

145

3.5 Shallow Junction Formation

3.5 Shallow Junction Formation

densities of the two layers and the mismatch mechanism. The use of oxide and Si,N, in a gate dielectric stack (ON (oxide/nitride) or O N 0 (oxide/nitride/oxide)) can yield two advantages. Firstly, as in the case of stacked CVD and thermal oxide, the misalignment of micropores in the individual components acts as an effective “seal” to prevent the early gate dielectric failures (Roy et al., 1988). Secondly, the use of Si,N, increases the effective dielectric constant of the film and serves as effective barrier against boron penetration. Iwai et al. (1990) studied the hot carrier irnmunity of MOSFETs with stacked ON gate dielectrics. It was observed that by reducing the top nitride thickness to about 30 A, the charge trapping in stacked layers can be significantly reduced and can be comparable to a conventional thermal oxide film. Dori et al. (1987) used ON dielectrics for a dual gate process and demonstrated that the top nitride layer is an effective barrier against boron penetration, which facilitates the fabrication of p +-polysilicon gated p-MOSFETs. In addition, these dielectrics showed a tighter E,, distribution than the conventional thermal oxides. Reduction in electron trapping by reducing the top nitride layer thickness was reported, as also stated by Iwai et al. (1987).

A significant requirement in high-performance semiconductor technologies is CMOS source/drain junction depth reduction to suppress MOS punchthrough leakage and to minimize device short channel effects such as drain-induced barrier lowering (DIBL) in CMOS devices. Device junctions with relatively high surface dopant concentrations, ultra-shallow depths, low contact and sheet resistances, and low junction leakage currents will be critical for advanced CMOS technologies. It has been projected that ultra-shallow junctions with junction depth

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