Nanoscaled Semiconductor-On-Insulator Structures and Devices

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Nanoscaled Semiconductor-on-Insulator Structures and Devices

NATO Science for Peace and Security Series This Series presents the results of scientific meetings supported under the NATO Programme: Science for Peace and Security (SPS). The NATO SPS Programme supports meetings in the following Key Priority areas: (1) Defence Against Terrorism; (2) Countering other Threats to Security and (3) NATO, Partner and Mediterranean Dialogue Country Priorities. The types of meeting supported are generally "Advanced Study Institutes" and "Advanced Research Workshops". The NATO SPS Series collects together the results of these meetings. The meetings are coorganized by scientists from NATO countries and scientists from NATO's "Partner" or "Mediterranean Dialogue" countries. The observations and recommendations made at the meetings, as well as the contents of the volumes in the Series, reflect those of participants and contributors only; they should not necessarily be regarded as reflecting NATO views or policy. Advanced Study Institutes (ASI) are high-level tutorial courses intended to convey the latest developments in a subject to an advanced-level audience Advanced Research Workshops (ARW) are expert meetings where an intense but informal exchange of views at the frontiers of a subject aims at identifying directions for future action Following a transformation of the programme in 2006 the Series has been re-named and re-organised. Recent volumes on topics not related to security, which result from meetings supported under the programme earlier, may be found in the NATO Science Series. The Series is published by IOS Press, Amsterdam, and Springer, Dordrecht, in conjunction with the NATO Public Diplomacy Division. Sub-Series A. B. C. D. E.

Chemistry and Biology Physics and Biophysics Environmental Security Information and Communication Security Human and Societal Dynamics

http://www.nato.int/science http://www.springer.com http://www.iospress.nl

Series B: Physics and Biophysics

Springer Springer Springer IOS Press IOS Press

Nanoscaled Semiconductor-onInsulator Structures and Devices Edited by

S. Hall University of Liverpool Liverpool, United Kingdom

A.N. Nazarov Lashkaryov Institute of Semiconductor Physics NAS of Ukraine, Kyiv, Ukraine

V.S. Lysenko Lashkaryov Institute of Semiconductor Physics NAS of Ukraine, Kyiv, Ukraine

Published in cooperation with NATO Public Diplomacy Division

Proceedings of the NATO Advanced Research Workshop on Nanoscaled Semiconductor-on-Insulator Structures and Devices Big Yalta, Ukraine 15–19 October 2006

A C.I.P. Catalogue record for this book is available from the Library of Congress.

ISBN 978-1-4020-6379- 4 (PB) ISBN 978-1-4020-6378-7 (HB) ISBN 978-1-4020-6380-0 (e-book)

Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands.

www.springer.com

Printed on acid-free paper

All Rights Reserved © 2007 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work.

INTRODUCTION This proceedings volume constitutes an archive of the contributions of the key-speakers who attended the NATO Advanced Research Workshop on “Nanoscaled Semiconductor-On-Insulator Structures and devices” held in the Tourist and Recreation Centre “Sudak” (Crimea, Ukraine) from 15 to 19 October 2006. The semiconductor industry has sustained a very rapid growth during the last three decades through impressive technological developments which have resulted in products with higher performance and lower cost per function. After many years of development it is now confidently predicted that semiconductor-on-insulator materials will enter and increasingly be used by manufacturing industry. The wider use of semiconductor (especially silicon) on insulator materials will not only enable the benefits of these materials to be demonstrated but, also, will drive down the cost of substrates which, in turn, will stimulate the development of other novel devices and applications. Thus the semiconductor-on-insulator materials of today are not only the basis for modern microelectronics but also for future nanoscale devices and ICs. In itself this trend will encourage the promotion of the skills and ideas generated by researchers in the Former Soviet Union and Eastern Europe. Indeed, one of the goals of this Workshop is to promote the development of SOI technologies worldwide. This volume contains mainly the review manuscrips composed on the basis of oral and poster papers presented during the four-day meeting, under the heading of: •

Nanoscaled SOI Material and Device Technologies;

•

Physics of Novel Nanoscaled SOI Devices;

•

Reliability and Characterization of Nanoscaled SOI devices;

•

Theory and Modeling of Nanoscaled Devices.

These high-quality papers were presented by researchers from Japan, USA, Western Europe and the Eastern European countries of the Former Soviet Union thereby fulfilling a key objective of the Workshop which was the development of world-wide contacts between researchers in the attendees countries.

v

vi

INTRODUCTION

The meeting thus successfully achieved its scientific and networking goals and the attendees wish to express their gratitude to the NATO Programme Security through Science and Network of Excellence Project of European Community “Silicon-Based Nanodevices”, whose financial support made the meeting possible; and National Academy of Sciences of Ukraine, Ministry of Science and Education of Ukraine and the Lashkaryov Institute of Semiconductor Physics, NASU who provided local support. We would like to thank the Agency of International Cooperation “Optima” whose Director Mariya Miletska helped us to organize this Workshop in a professional manner. Our sincere gratitude also goes to Dr. Ya. Vovk, A. Rusavsky, Dr. V. Kilchytska, V. Stepanov, V. Torbin, Dr. A. Stronskii, Dr. Yu. Gomenyuk, Dr. I. Osiyuk, Dr. T. Rudenko, Dr. I. Tyagulskii, V. Smirnaya, J. Cowan and A. Winker for their clerical and technical assistance. A final special thanks to Mr. Yurii Houk for his dedication in compiling this book and for many other practical contributions.

Steve Hall Liverpool, United Kingdom

Alexei Nazarov and Vladimir Lysenko Kyiv, Ukraine

INTRODUCTION

vii

viii

INTRODUCTION

INTRODUCTION

ix

CONTENTS

INTRODUCTION .............................................................................. v Nanoscaled SOI Material and Device Technologies Status and trends in SOI nanodevices................................................. 3 F. Balestra Non-planar devices for nanoscale CMOS ........................................ 19 M.C. Lemme, H.D.B. Gottlob, H. Kurz High-κ dielectric stacks for nanoscaled SOI devices ....................... 33 S. Hall, O. Buiu, I.Z. Mitrovic, Y. Lu, W.M. Davey Nanoscaled semiconductor heterostructures for CMOS transistors formed by ion implantation and hydrogen transfer......... 59 V. Popov, I. Tyschenko, A. Cherkov, M. Voelskow Fluorine –vacancy engineering: A viable solution for dopant diffusion suppression in SOI substrates............................................ 73 H.A.W. El Mubarek and P. Ashburn Suspended Silicon-On-Insulator nanowires for the fabrication of quadruple gate MOSFETs ............................................................ 89 V. Passi, B. Olbrechts, J.-P. Raskin, J. Bolten, T. Mollenhauer, T. Wahlbrink, M.C. Lemme, H. Kurz Physics of Novel Nanoscaled SemOI Devices Integration of silicon single-electron transistors operating at room temperature.............................................................................. 97 T. Hiramoto SiGe nanodots in electro-optical SOI devices ................................ 113 A.V. Dvurechenskii, A.I. Yakimov, N.P. Stepina, V.V. Kirienko, P.L. Novikov Nanowire quantum effects in trigate SOI MOSFETs..................... 129 J.-P. Colinge

xi

xii

CONTENTS

Semiconductor nanostructures and devices .................................... 143 J. Knoch and H. Lüth MuGFET CMOS process with midgap gate material .................... 159 W. Xiong, C.R. Cleavelin, T. Schulz, K. Schrüfer, P. Patruno and J.-P. Colinge Doping fluctuation effects in multiple-gate SOI MOSFETs .......... 165 C.A. Colinge, W. Xiong, C.R. Cleavelin and J.-P. Colinge SiGeC HBTs: impact of C on device performance ........................ 171 I.Z. Mitrovic, H.A.W. El Mubarek, O. Buiu, S. Hall, P. Ashburn, J. Zhang Reliability and Characterization of Nanoscaled SOI Devices Noise research of nanoscaled SOI devices ..................................... 181 N. Lukyanchikova Electrical characterization and special properties of FINFET structures......................................................................................... 199 T. Rudenko, V. Kilchytska, N. Collaert, A. Nazarov, M. Jurczak, and D. Flandre Substrate effect on the output conductance frequency response of SOI MOSFETs ........................................................................... 221 V. Kilchytska, D. Levacq, D. Lederer, G. Pailloncy, J.-P. Raskin and D. Flandre Investigation of compressive strain effects induced by STI and ESL .............................................................................. 239 S. Zaouia, S. Cristoloveanu and A.H. Perera Charge trapping phenomena in single electron NVM SOI devices fabricated by a self-aligned quantum dot technology........ 251 A. Nazarov, V. Lysenko, X. Tang, N. Reckinger, V. Bayot

CONTENTS

xiii

Theory and Modeling of Nanoscaled Devices Variability in nanoscale UTB SOI devices and its impact on circuits and systems ........................................................................ 259 A. Asenov, K. Samsudin Electron transport in Silicon-on-Insulator nanodevices ................. 303 F. Gámiz, A. Godoy, C. Sampedro All quantum simulation of ultrathin SOI MOSFETs...................... 323 A. Orlikovsky, V. Vyurkov, V. Lukichev, I. Semenikhin, A. Khomyakov Resonant tunneling devices on SOI basis....................................... 341 B. Majkusiak Mobility modeling in SOI FETs for different substrate orientations and strain conditions ................................................... 357 V. Sverdlov, E. Ungersboeck, H. Kosina Three-dimensional (3-D) analytical modeling of the threshold voltage, DIBL and subthreshold swing of cylindrical gate all around MOSFETs........................................................................... 363 H.A. El Hamid, B. Iñiguez, J. Roig AUTHORS INDEX ........................................................................ 369

Nanoscaled SOI Material and Device Technologies

STATUS AND TRENDS IN SOI NANODEVICES FRANCIS BALESTRA* Institut de Microélectronique, Electromagnétisme et Photonique IMEP (CNRS-INPG-UJF), INP Grenoble-Minatec, BP 257, 38016 Grenoble, France *

email: [email protected]

Abstract. A review of recently explored new materials and architectures for SOI nanodevices is given. Recent advances in the understanding of the sensitivity of electron and hole transport to the tensile or compressive uniaxial and biaxial strains in thin film SOI are presented. The electrical properties in multi-gate Si, SiGe, Ge and GaAs MOSFETs and Nanowires realized with various channel orientations are also addressed. The impact of gate misalignment or underlap, as well as the use of the back gate for charge storage in double-gate nanodevices and of capacitorless DRAM are also outlined.

Keywords: SOI nanodevices, Multi-gate MOSFETs, Nanowires, Strain, Channel orientation, Memories

1. Introduction SOI devices are the best candidates for the ultimate integration of integrated circuits on silicon. The flexibility of the SOI structure and the possibility to realize new device architectures allow to obtain optimum electrical properties for low power and high performance circuits. These transistors are also very interesting for high frequency and memory applications [1-3]. In this paper, an overview of recently explored new materials and device architectures is given. The advantages and drawbacks of a number of SOI nanodevices are also addressed.

3 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 3-18. © 2007 Springer.

4

STATUS AND TRENDS IN SOI NANODEVICES

2. Influence of strain and surface orientation on the electrical properties of thin layers on insulators Compressive and tensile biaxial and uniaxial stress silicon technologies are promising for enhancing CMOS performance in bulk and SOI MOSFETs. The combination of strained layers and ultra thin films SOI structures is one of the best candidate for decananometer MOSFETs. Figure 1 is a plot of the dependence of electron and hole mobilities as a function of the charge density [4]. The strained Si layer is fabricated with sacrificial thin relaxed SiGe and smart cut. In the sSOI devices, substantial enhancements of both electron (about 100%) and hole (about 50%) mobilities are obtained compared with the control SOI device at intermediate charge densities for long channel transistors. An enhancement of the electron mobility of about 15-20% has been obtained for short channels (70nm technology) SGOI MOSFETs (strained Si on SiGe on insulator) together with superior short channel control [5,6]. Fig. 2 shows the enhancement of the drain current for sub-0.1µm devices. 1000

200

NMOS 20 × 20

PMOS 20 × 20 150

SSOI

600

µeff (cm2/Vs)

µeff (cm2/Vs)

800

400

0 0

100 SOI 50

SOI

200

SSOI

3 6 9 Charge density (× 1012 cm-2)

12

0 0

3 6 9 Charge density (× 1012 cm-2)

Figure 1. Effective mobility comparison between SSOI and SOI MOSFETs

Drain current (mA)

1.0

VG (V)= Vth + 0, 0.25, 0.5, 0.75, 1

0.8

Strained-SOI

SOI

0.6 0.4 0.2 0.0 0

0.6 0.2 0.4 Drain voltage (V)

Figure 2. Id-Vd of 70nm MOSFETs (W=1um)

0.8

12


5

In Fig. 3, the electron mobilities are represented for various Ge content of the SiGe layer and different Si film thicknesses. The electron mobility enhancement is maximum for 30% of Ge due to the increase in alloy scattering and/or surface roughness and the hole mobility continuously increases with Ge up to 50% [6]. It is also worth noting that the enhancement of carrier mobility is reduced in thinner strained Si films due to interface states and fixed charges induced by the diffusion of Ge atoms to the interfaces. Figure 4(a,b) shows Idsat and Gmsat as a function of channel length for SGOI and SOI MOSFETs. An enhancement of Id is outlined down to sub50nm transistors for SGOI, but the difference diminishes at smaller channel length due in particular to larger self-heating (SH) in SiGe than in Si. This SH effect in SGOI degrades Gmsat, which is more sensitive to SH than Id. Therefore the transconductance appears degraded in SGOI as compared to SOI but after correction of the self-heating a similar increase is obtained for Id and Gm in the SGOI structure [7]. Electron mobility enhancement over universal mobility

2.0 1.8 1.6 TsSi (nm) = 25 15 10

1.4 1.2 1.0 0.8

Ge content = 10% 15%

20%

30%

40%

50%

0.2 0.7 0.2 0.7 0.2 0.7 0.2 0.7 0.2 0.7 0.2 0.7 Eeff (MV/cm)

Figure 3. Eeff dependence of electron mobility enhancement as a function of Ge content and film thickness 750 1200

SGOI

SOI gmsat (µS/µm)

ID, SAT (µA/µm)

700 650 SOI 600 550 500 20

1100 1000

SGOI

900

VGS - VT = 0.7 V 40

60 LGATE (nm)

80

800 20

100

(a)

40

60 LGATE (nm)

Figure 4. Comparison of Idsat and Gmsat at a constant gate overdrive

80

100

(b)

6


Mobility enhancement factor*

The HOI structure (strained Si/strained SiGe/ strained Si heterostructure on insulator) presents also substantial electron and hole mobility enhancements [8]. In particular, hole mobilities are very high for thin Si cap layer (enhancement of about 100%) compared with the universal SOI mobility and are also significantly larger that the best SSDOI mobility (Strained Si Directly On Insulator) due to the compressively strained buried SiGe channel (Fig. 5). Uniaxial strain engineering is also useful for mobility enhancement for Si film thickness in the sub-10nm range [9]. A similar enhancement of electron mobility in 3.5nm SOI devices under biaxial and uniaxial tensile strain has been obtained. The electron mobility is also enhanced in 2.3nm Si layer under uniaxial tensile strain (Fig. 6), and the hole mobility increases in 2.5nm film under uniaxial compressive strain. 2.2

PMOS, 46/24

tcap = 2 nm

2.0 5.4 nm 1.8 1.6 1.4

"best SSDOI"

7.1 nm * reference is "universal" SOI 1.2 0.5 1 0 1.5 Hole density (× 1013 cm-2)

2

Electron mobility (cm2/Vs)

Figure 5. Mobility enhancement in HOI compared with the best SSDOI curve relative to the “universal” SOI mobility

TSOI = 2.3 nm 200

2% 5% initial (W/O stress) 0.083% tensil 0.083% compressive

100 0.1

0.2 0.3 0.5 0.7 1 Effective field (mV/cm)

2

Figure 6. Electron mobility in 2.3-nm ultra-thin-body MOSFET under uniaxial strain


7

It has recently been shown that the use of a metal gate (TiN) can induce significant compressive stress along the channel direction. This stress is increased as the gate length decreases. This phenomenon progressively degrades electron mobility while hole transport is improved. Similar behaviors are obtained in single and double gate SOI devices, and the use of channel orientation is the most favorable in terms of electrical performance [10]. Pure Ge channel MOSFETs are also considered as one promising option for future high performance CMOS. A compressively strained Ge channel is expected to further enhance hole mobility due to the very small effective hole mass [11]. Figure 7(a) shows the linear current of s-Ge PMOS with Hf02 gate dielectrics along with the Si control device. A 2.5x performance enhancement is observed (similar enhancement for the transconductance). For s-Ge P-type devices with SiO2 gate oxide, a 3x drive current and transconductance is obtained (Fig. 7(b)). 10

TMs-Ge/HfO2

2.5X

L = 10 µm VDS = -50 mV Remote Plasma Oxide

8 IDS (µA/square)

IDS (µA/square)

8 6

10

L = 10 µm VDS = -50 mV

4 2

6

~3X

s-Ge

4 Si control 2

Si/HfO2 control 0 -3

-2.5

-2

-1.5 -1 VGS (V)

-1.5

0

0 -3 -2.5 -2 -1.5 -1 -1.5 VGS (V)

0.5

(a)

0

0.5

1

(b)

SR limited mobility

(cm2/Vs)

Figure 7. a) Drain current of PMOSFETs with HfO2 gate oxide on 60% Ge channel formed by local thermal mixing compared with Si PMOS control with HfO2; b) Drain current of PMOSFETs with remote plasma oxide on 100% Ge channel formed by selective UHVCVD compared with Si channel PMOS control with the same oxide @Hole density 5×1011 cm-2 104

@Hole density 5×1011 cm-2 104

Si

r6

dy T bo

e

103

y

d T bo

pow

6 er pow

Ge

103

Si Si

Ge

102

102 SILICON

2

Ge

3 4 Body thickness (nm)

GERMANIUM 5

2

3 4 Body thickness (nm)

5

Figure 8. Simulated Surface Roughness limited hole mobility for Si and Ge with various orientations

8

STATUS AND TRENDS IN SOI NANODEVICES 600

µ (cm2/Vs)

500 400 300 200 100 0 0

1.5

0.5 1 VG - Vth (V)

Figure 9. Electron mobility of FinFETs with and fin orientation. Tox=2nm, 4.5x1013 cm-2 channel implantation

The influence of surface roughness (SR) in ultra-thin films is very important. Figure 8 shows the SR limited hole mobility as a function of body thickness for Si (SOI) and Ge (GOI) channels. The variation of hole mobility is outlined for various surface orientations [12]. Figure 9 represents electron mobilities in FinFETs with various fin orientations. An improvement of electron mobility is observed for and an enhancement of hole mobility has also been shown for orientation [13]. 3. Comparison of the performance and physical mechanisms in multi-gate devices Multi-gate MOSFETs realized on thin films are the most promising devices for the ultimate integration of MOS structures due to the volume inversion in the conductive layer [14]. 0.7 LG

BR = ION/IBL

0.6 0.5 SOI DG 45 SOI DG 65 SOI DG 90 Bulk 65 Bulk 90 Bulk 130

0.4 0.3 0

50

100 150 DIBL (mV/V)

200

250

Figure 10. Ballisticity ratio at Vg=Vd=Vdd vs. DIBL. Filled symbols represent transistors with the nominal gate length for the high-performance MOSFET of each technology node


9

The on-current Ion of the MOSFET is limited to a maximum value IBL that is reached in the ballistic transport regime. Figure 10 reports the selfconsistent MC simulation of the ballistic ratio BR=Ion/IBL versus DIBL showing that one can increase the BR by scaling the gate length, thus increasing the longitudinal field at the source, but this comes at the cost of a larger DIBL. For a given DIBL, an increased ballisticity is obtained for low doping double gate SOI devices [15]. The transfer characteristics of several multiple-gate (1, 2, 3 and 4 Gates) MOSFETs, calculated using the 3D Schrödinger-Poisson equation and the Non-Equilibrium Green’s Function formalism for the ballistic transport or Monte Carlo simulations, have shown similar trends. The best performance (drain current, subthreshold swing) is outlined for the 4-gates (QG or GAA) structure [16,17] (Fig. 11). However, Fig. 12 demonstrates that the propagation delay in triple gate (TG) and quadruple gate (QG) MOSFETs are degraded due to a strong rise of the gate capacitance. A properly designed double-gate (DG) structure appears to be the best compromise at given Ioff [17]. 2500 2000

10 2 10 1

1500

TSi = 5 nm VGS = 0.7 V

SG

10 0

Drain current (A/m)

Drain current (A/m)

10 3

DG

1000

10-1 10-2 10-3

500

QG

TG

-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Gate voltage (V)

0

Figure 11. Id(Vgs) at Vds=0.7V in thin layers for different multi-gate architectures

Delay CGVDD/Ion (ps)

1.2 1.0

QG

Lch / TSi 15 nm / 10 nm 15 nm / 5 nm 25 nm / 10 nm

TG 0.8 DG 0.6 0.4 0.2 -3 10

QG

DG

10-2

QG

TG

TG SG SG DG

10-1 100 101 Current Ioff (A/m)

SG 102

103

Figure 12. Propagation delay versus Ioff for single-gate and multi-gate SOI devices

10


Figure 13 compares the calculated ballistic drive current for Si and Ge double-gate MOSFETs at the operation point of each generation as predicted by ITRS [18]. Si barely satisfies the ITRS requirement, whereas Ge offers much higher current drive. However, the simulated value of the real drain current of 2G SOI transistors is not able to satisfy the ITRS objectives, even for intrinsic devices without parasitic S/D resistances. 2G GOI MOSFETs are able to provide the needed current drive, but parasitic resistances drastically affect the drain current (not shown here). For a double gate device, the impact of a gate misalignment on the leakage current is important. This current is mainly due to GIDL. This off-current is enhanced with increasing the misalignment and it is higher for a shift of the bottom gate to the drain due to a larger Vgd compared to Vgs [19]. Drian current density (µA/µm)

5000 4000

GOI

3000 SOI 2000

ITRS'03

1000

10

20 Gate length (nm)

30

Figure 13. Ballistic drive current for different technology nodes for SOI and GOI devices

Off-state current (A/µm)

10- 5 10- 6 10- 7

simulations experience

FD

10- 8 10- 9 10-10 10-11 10-12 10-13 -20

0

20 40 Misalignment (nm)

Figure 14. Evolution of Ioff with misalignment (experimental and simulations results, Vd=1.2V). Single gate FD results are represented in dashed line


11

The impact of a gate misalignment is also significant for Ion in 2G MOSFETs [20]. A large back gate (BG) shift reduces the saturation current compared to the aligned case, whereas a slight BG shift towards the source increases Ion. This is due to a lower source access resistance. In terms of short channel effects, aligned transistors exhibit the best control while highly misaligned MOSFETs operate like single gate ones. Ioff is much more influenced by the misalignment than Ion due a degradation of the electrostatic control (Fig. 14). The oversized transistor shows attractive static performance (right hand side of Fig. 14) and a larger tolerance to misalignment but the dynamic performance is rapidly degraded as the overlap length increases. In decananometer MOSFETs, gate underlap is a promising solution in order to reduce the DIBL effect. Figure 15 presents the variations of the driving current, the subthreshold current and the gate direct tunneling current versus gate underlap [21]. The on-current is almost not affected by the gate underlap whereas the leakage currents are substantially reduced due to a decrease in DIBL and drain to gate tunneling current. A reduction of the effective gate capacitance Cg for larger underlap values at iso Ion has also been shown. This reduction of Cg leads to a decrease in the propagation delay and power. Multi-bridge-channel MOSFETs (MBCFET) present very high performance larger than those of GAA devices and exceeding the ITRS roadmap requirements (Fig. 16) [22].

10 - 2 Ion

log I (A/µm)

10 - 4 10 - 6 10 - 8 Isub 10-10 10-12

Igdt 0

2

4 6 8 10 Gate underlap (nm)

12

14

Figure 15. Ion, subthreshold (Isub) and gate direct tunneling (Igdt) currents as a function of gate underlap

12


BOX Figure 16. Schematic diagram of MBCFET on SOI 4

3

CNW CNT RNW FinFET

10 4

2

10 4 1 10-4

0

0.25

0.5 0.75 Gate voltage (V)

1

Electron density (107 cm-1)

Electron density (cm-1)

10 8

0

Figure 17. Electron density per unit length for various devices (FinFET, nanowires and carbon-nanotube FET). 65nm technology node data (EOT=0.9nm, tSi=5nm)

It is also interesting to compare FinFETs with cylindrical and rectangular nanowires and with gate-all-around carbon nanotubes – CNT-FET. It is shown that the CNT-FET exhibits superior performance (Fig. 17) due to electron charge confinement at the surface of the nanotube, whereas in the Sibased nanowires the charge confinement at the center of the wire is responsible for an additional depletion capacitance in series with the oxide capacitance, which reduces the overall effectiveness of the gate [23]. Finally, sub-10nm nanowires are compared for various channel materials and orientations using 3D quantum-mechanical simulations in pure ballistic regime [24]. Figure 18 shows the transfer current-voltage characteristics for a 9nm nanowire with a 4nm diameter, the gate workfunctions being adjusted to provide identical off-current. The Si and Ge nanowires provide similar on-current, whereas the GaAs nanowire suffers from a high source-to-drain tunneling in the subthreshold region leading to a smaller Ion/Ioff ratio.


13

Figure 18. Id(Vg) characteristics calculated for Si, Ge and GaAs gate-all-around nanowires oriented along the [100] direction, with 4nm wire diameter and 9nm gate length; 1nm gate oxide; Vds=0.4V

Figure 19. Id(Vd) characteristics calculated for n- and p-types Si nanowire FETs with four different channel orientations; 3nm wire diameter, 8nm gate length; 1nm gate oxide; Vds=0.4V

14


Figure 20. Id(Vd) characteristics calculated for Si and Ge nanowires FETs with [110] channel orientation; 3nm wire diameter, 8nm gate length; 1nm gate oxide; V ds=0.4V

In Fig. 19, the output Id-Vd characteristics are calculated using full-band simulations with a ballistic FET model for Si n- and p-type nanowire FETs with four different channel orientations, 8nm gate length and 3nm wire diameter [25]. Due to the behavior of the transport effective-mass and valley degeneracy, it is demonstrated that [110] is the best orientation for n- and p-channels that offers the highest Ion for the same off-current for this 3nm wire diameter. For this optimum channel orientation, Ge nanowires leads to an increase of Id between 30 and 40% for p- and n-type devices, respectively, compared to Si nanowires (Fig. 20). The variation of the intrinsic device delay with the wire diameter is shown in Fig. 21 for Si and Ge n- and p-type nanowires and various channel orientations [25]. P-channel nanowires displays a monotonically increasing speed with decreasing the wire diameter, while the performance of n-channel nanowires highly depends on wire orientation and material. 4. Advanced SOI DRAMs and NVMs It is becoming difficult for memories to be scaled down. Indeed, traditional embedded DRAM requires a complicated stack capacitor or a deep strench capacitor in order to obtain a sufficient storage capacitance in smaller cells. This leads to more process steps and thus less process compatibility with logic devices.


15

Figure 21. Intrinsic device delay as a function of wire diameter for n and p Si and Ge nanowires FETs with various channel orientations; 8nm gate length; 1nm gate oxide; Vds=0.4V

Capacitor-less 1T-DRAM or Floating body cells have shown promising results. The operation principle is based on excess holes which can be generated either by impact ionization or by Gate-Induced Leakage Current in partially-depleted SOI MOSFETs. The GIDL current is due to band-toband tunneling and occurs in accumulation leading to a low drain current writing and reduced power consumption together with a high speed operation. However, conventional PD SOI MOSFETs require high channel doping to suppress short-channel effects, which induces a degradation in retention characteristics. In order to overcome this problem, a DGFinDRAM has been proposed showing superior memory characteristics (Fig. 22) [26].

16


Drain current (µA/µm)

200 "0" state "1" state 150

VDS = 0.2 V VBG = 1.5 V

100

50

0 0.2

ID difference

0.4

0.6 0.8 Gate voltage (V)

1

Figure 22. Id(Vg) characteristics of the DG-FinDRAM

Conventional floating-gate flash memory has also scaling difficulties due to nonscaling of gate-insulator stack and inefficient hot carrier injection processes at sub-50nm gate dimensions. Back-floating gate flash memory overcomes these limitations by decoupling read and write operations and independent positioning and/or sizing of the storage element (back-floating gate) under the Si channel (Fig. 23). The charge in the back gate affects the field and the potential at the bottom interface and thus changes the threshold voltage of the device. The back-floating gate is charged by applying –10V to the source, the drain and the front gate simultaneously, and the charges are removed from the back floating gate (erasing) with the same method but with a bias of +10V [27]. Back-Floating Memory Gate Source

Read oxide Drain

Floating Substrate

Conventional Flash Gate Floating

Injection oxide Control oxide

Source

Drain Substrate

Figure 23. Cross-sections of back floating gate and conventional front-floating gate memories


17

5. Conclusion In this paper, a review of recent advances in the understanding of the sensitivity of electron and hole transport to the tensile or compressive uniaxial and biaxial strains in thin film SOI has been given,. The performance and physical mechanisms have also been presented in multigate MOSFETs and Nanowires realized with various channel materials and orientations. The impact of gate misalignment or underlap, as well as the use of the back gate for charge storage in double-gate nanodevices and of capacitorless DRAM have also been outlined. ACKNOWLEDGEMENTS

This work was partially supported by the European Network of Excellence SINANO (Silicon-based Nanodevices, FP6, IST-1-506844-NE).

References 1.

J.-P. Colinge, Silicon-On-Insulator technology: materials to VLSI (Kluwer Academic Publishers, 1991). 2. S. Cristoloveanu and S.S. Li, Electrical characterization of Silicon-On-Insulator materials and devices (Kluwer Academic Publishers, 1995). 3. F. Balestra, SOI devices (Wiley Encyclopedia of Electrical and Electronics Engineering, 1999). 4. J.J. Lee, J.S. Maa, D.J. Tweet et al, Mobility enhancement of SSOI devices fabricated with sacrificial thin relaxed SiGe, in: Proc. IEEE Intern. SOI Conf., (2004), p. 139. 5. M. Sadaka A.V.-Y. Thean, A. Barr et al, Fabrication and operation of sub-50nm strained-Si on Si1-xGex on insulator (SGOI) CMOSFETs, in: Proc. IEEE Intern. SOI Conf. (2004), p. 209. 6. T. Numata, T. Irisawa, T. Tezuka et al, Performance enhancement of partially- and fully-depleted strained-SOI MOSFETs and characterization of strained-Si devices parameters, in: Proc. IEDM (2004), p. 177. 7. J. Cai, K. Rim, A. Bryant et al, Performance comparison and channel length scaling of strained Si FETs on SiGe-on-Insulator (SGOI), in: Proc. IEDM (2004), p. 165. 8. I. Aberg, C.N. Chléirigh, O.O. Olubuyide et al, High electron and hole mobility enhancements in thin-body strained Si/strained SiGe/strained Si Heterostructures on Insulator, Proc. IEDM (2004), p. 173. 9. K. Uchida, R. Zednik, C.H. Lu et al, Experimental study of biaxial and uniaxial strain effects on carrier mobility in bulk and ultra-thin-body SOI MOSFETs, in: Proc. IEDM (2004), p. 229. 10. T. Guillaume, M. Mouis, S. Maîtrejean et al, Influence of the mechanical strain induced by a metal gate on electron and hole transport in single and double-gate SOI MOSFETs, in: Proc. IEEE Intern. SOI Conf. (2004), p. 42. 11. H. Shang, Selectively formed high mobility strained Ge PMOSFETs for high performance CMOS, in: Proc. IEDM (2004), p. 157.

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12. T. Low, Impact of surface roughness on silicon and germanium ultra-thin-body MOSFETs, in: Proc. IEDM (2004), p. 151. 13. E. Landgraf, W. Rösner, M. Staedele et al, Influence of crystal orientation and body doping on trigate transistor performance, in: Proc. ULIS (2005), p. 15. 14. F. Balestra, S. Cristoloveanu, M. Benachir et al, Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance, IEEE Electron Dev. Lett., EDL-8, 410 (1987). 15. S. Eminente, D. Esseni, P. Palestri et al, Enhanced ballisticity in nano-MOSFETs along the ITRS roadmap: a Monte Carlo study, in: Proc. IEDM (2004), p. 609. 16. M. Bescond, K. Nehari, J.L. Autran et al, 3D quantum modeling and simulation of multiple-gate nanowire MOSFETs, in: Proc. IEDM (2004), p. 617. 17. J. Saint-Martin, A. Bournel, P. Dollfus, Comparison of multiple-gate MOSFET architectures using Monte Carlo simulation, in: Proc. ULIS (2005), p. 61. 18. A. Khakifirooz, O.M. Nayfeh, D.A Antoniadis, Assessing the performance limits of ultra-thin double-gate MOSFETs: Silicon vs. Germanium, in: Proc. IEEE Intern. SOI Conf. (2004), p. 79. 19. C. Yin, P.C.H. Chan, Characterization and edge direct tunneling leakage of gate misaligned double gate MOSFETs, in: Proc. IEEE Intern. SOI Conf. (2004), p. 91. 20. J. Widiez, F. Daugé, M.Vinet et al, Experimental gate misalignment analysis on double gate SOI MOSFETs, in: Proc. IEEE Intern. SOI Conf. (2004), p. 185. 21. A. Bansal, B.C. Paul, K. Roy, Impact of gate underlap on gate capacitance and gate tunneling current in 16nm DGMOS devices, in: Proc. IEEE Intern. SOI Conf. (2004), p. 94. 22. E.-J. Yoon, S.Y. Lee, S.M. Kim et al, Sub-30nm multi-bridge-channel MOSFET (MBCFET) with metal gate electrode for ultra high performance application, in: Proc. IEDM (2004), p. 627. 23. A. Marchi, E. Gnani, S. Reggiani et al, Investigating the performance limits of siliconnanowire and carbon-nanotube FETs, in: Proc. ULIS (2005), p. 99. 24. M. Bescond et al, Ballistic transport in Si, Ge and GaAs nanowire MOSFETs, in: Proc. IEDM (2005). 25. J. Wang et al, Bandstructure and orientation effects in ballistic Si and Ge nanowire FETs, in: Proc. IEDM (2005). 26. T. Tanaka, E. Yoshida, T. Miyashita, Scalability study on a capacitorless 1T-DRAM: from single-gate PD-SOI to double-gate FinDRAM, in: Proc. IEDM (2004), p. 919. 27. U. Avci, A. Kumar, S. Tiwari, Back-floating gate non-volatile memory, in: Proc. IEEE Intern. SOI Conf. (2004), p. 133.

NON-PLANAR DEVICES FOR NANOSCALE CMOS M.C. LEMME*, H.D.B. GOTTLOB, H. KURZ Advanced Microelectronic Center Aachen (AMICA), AMO GmbH, 52074 Aachen, Germany * To whom correspondence should be addressed: Max Lemme, tel.: +49-241-8867-207, fax: +49-2418867-571, e-mail: [email protected]

Abstract. In this paper, various concepts of multi-gate transistors are discussed with regards to their technological feasibility and manufacturability. In addition, non-standard fabrication process modules for triplegate nanoscale MOSFETs and sub-10 nm nanowires are presented. Alternatives to costly extreme ultraviolet (EUV) lithography are proposed as well as a self-aligned nickel silicide module to reduce inherent parasitic access resistances.

Keywords: SOI, FinFET, Tri-Gate, triple gate, Nano-CMOS, Nanowire

1. Introduction Moore’s Law1, the famous scaling rule-of-thumb turned dogma has been the dominating driver for the enormous success of the semiconductor industry for the last four decades. It was quickly and continuously transformed into a precise set of guidelines2,3,4 and is now manifested in the International Technology Roadmap for Semiconductors (ITRS)5, the benchmark against which any new development is judged. Today, physical gate lengths have reached dimensions in the 50 nm range, with gate oxide thicknesses well below 3 nm. At these dimensions, further performance gains through geometric downscaling are no longer viable. Instead, Moore’s law requires a host of innovative transistor architectures and the introduction of novel materials to continue on the path sketched in 1965. Silicon on insulator (SOI) material yields a number of potential advantages for nanoscale MOSFETs compared to bulk silicon. The list includes reduced parasitic capacitances and leakage currents, increased packing density, inherent ultra-shallow junctions or latch-up suppression. There is a number of excellent books that describe the advantages of SOI material and devices in great detail6,7,8. 19 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 19-32. © 2007 Springer.

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Fully depleted SOI transistors are of particular interest, as they exhibit near ideal device behavior and strongly reduced short channel effects. The first fully depleted SOI transistors were published in the 1980’s and these single gate devices promised already superior characteristics compared to bulk silicon MOSFETs 9,10,11 . Multiple gate SOI transistors have an even greater potential for short channel control. They enable ideal gate swings of S = 60 mV/dec even with undoped channels. This potentially results in higher carrier mobilities and higher drive currents. In addition, band-toband tunneling in extremely short devices can be avoided using undoped channels12. Finally, undoped channels will become a necessity as highly doped 10 nm devices would suffer from statistical variations in the number of doping atoms. Each doping atom would literally determine the threshold voltage and off-current of a transistor13. Therefore, multi gate FETs with undoped channels, where the switching behavior is governed by electrostatics and threshold voltages are adjusted through the gate electrode work functions can be considered the ideal switches for end of the ITRS CMOS circuits. 2. Multi gate SOI transistors The first double gate SOI MOSFETs, named XMOS, were proposed in 198414, with an experimental demonstration in 199015. Since then, a range of double and multi gate device architectures has been investigated, with a schematic overview shown in Figure 1. In this section, the different multi gate FETs are briefly described. In planar double gate MOSFETs, a second gate electrode is placed underneath the regular gate. The effective gate width is twice the transistor width. A clear advantage of this concept from a circuit point of view is its similarity to conventional SOI MOSFETs. Overlay accuracy of the two gates, however, is the major drawback of planar double gate devices. At nanoscale gate lengths, even a misalignment of only a few nanometers would render these devices unfeasible. While self-aligned fabrication processes have been proposed to overcome this limitation16,17 , these schemes increase the complexity and therefore the cost and reliability of the fabrication process. This could be a major obstacle in commercializing these devices. FinFETs are a variation of double-gate MOSFETs and consist of thin silicon wires (or fins)18,19 , typically with a height to width ratio greater than one. The gate stacks are fabricated on the sidewalls of the fins and the top of the fins is covered in a thick dielectric to keep it electrically inactive. The effective gate width of each fin is twice its height, and therefore limited by the initial top silicon thickness. The total gate width and the total drive

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Figure 1. Schematic of multi gate SOI transistor concepts.

current can be controlled by using multiple parallel channels20,21. A possible disadvantage of FinFETs is their quantized drive current or device width quantization, as the total current is determined by the number of parallel fins22,23. Triangular gate MOSFETs, a variation of the FinFET concept, have been demonstrated experimentally24,25. However their manufacturability and CMOS process compatibility is not demonstrated on an industrial level. Triple gate or Tri gate transistors are related to FinFETs, but have an additional gate on top of the silicon wire26. The effective gate width of triple gate FETs is equal to the wire width plus two times the silicon thickness, as shown in the schematic in Fig. 2 (Weff = W + 2H). Triple gate FETs require only a moderate aspect ratio which translates into good manufacturability. The aspect ratio and the densities of wires can be carefully optimized to achieve higher circuit performance compared to planar devices27. Concerns about kinks in the subthreshold characteristics of triple gate devices due to a corner effect have been dismissed experimentally28,29 and through simulation30. Device width quantization on the other hand is of concern from a circuit point of view as in FinFETs.

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Figure 2. Schematic of a triple-gate SOI transistor with critical parameters.

Vertical multigate transistors have been considered for their potential to define the gate length by highly accurate thin film deposition methods such as molecular beam epitaxy 31,32,33, which can be controlled in the subnanometer range. In addition, three dimensional integration of vertical transistors has been proposed and demonstrated for memory applications34. For logic circuits, calculations show distinct performance gains by three dimensional integration35, but while experimental data is available from bonded multi-layer chips, the technological and design challenges for true 3D integration using vertical transistors seems overwhelming at this point in time. An extensive overview including a “family tree” of multi gate devices can be found in36 . 3. Future options for device fabrication Ultimately, the critical dimensions in non-planar, end of roadmap transistors will be in the range of 5 to 10 nm. Extreme UV (EUV) lithography with a wavelength of λ = 13.5 nm is an obvious option for such devices. The projected cost of EUV systems, however, may not permit their use for anything but very high volume memory and logic products. ASICs and other rather specific integrated circuits, which may well benefit from non-planar devices, could be denied this technology unless a low cost solution is found. Direct write electron beam lithography (EBL) and UVnanoimprint lithography (UV-NIL) are two contenders with a potential to deliver affordable processes for ultimately scaled MOSFETs.

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3.1. PROSPECTS OF ELECTRON BEAM LITHOGRAPHY

Electron beam lithography is a flexible method to fabricate structures and devices at the nanometer scale. It is widely applied to prototype and to evaluate nanoscale electron devices before conventional lithography methods are available. The application of e-beam lithography to production does, however, require the existence of high-throughput systems. Conventional Gaussian beam e-beam lithography systems use a highly serial technique to write patterns, but with limiting throughput. To overcome this obstacle several techniques to de-serialize the writing procedure have been proposed. Variable shaped-beam systems are already in wide use and offer the accuracy needed for the 32nm node37. Other solutions like cell-projection electron beam lithography38 or multi-beam approaches39 are still in a research and development phase. All these approaches have their special strengths and downsides. In order to utilize the full potential of electron beam lithography in the future, a careful choice of the adequate method will have to be made for each given application. Here, Gaussian beam e-beam lithography is used in an experimental CMOS process flow to demonstrate the benefits of triple gate control and to investigate the ultimate limit of scaling. Triple gate MOSFETs with different channel widths W and multiple parallel channels have been investigated. All devices have been fabricated on UNIBOND SOI material with various top silicon layer thicknesses tSi, buried oxide thicknesses of tBOX = 200 nm, gate oxide thicknesses of tox = 8 nm. The channels have been implanted and activated prior to structuring. A Leica EBPG-5000 e-beam system has been used to define the channel region40 with the negative tone e-beam resist hydrogen silsesquioxane (HSQ)41. The channels have been etched in a two-step process with an Oxford Plasmalab 100 inductively coupled plasma reactive ion etching system (ICP-RIE) using hydrogen bromide (HBr) based chemistry. The first step has been optimized for smooth vertical sidewalls, while the second step ensures a high selectivity of the silicon etch rate over BOX etch rate (50:1)42,43. Gate oxidation to tox = 8 nm has been followed by low pressure chemical vapor deposition (LPCVD) of tpoly = 100 nm undoped polysilicon. The gate electrode has again been defined by EBL (Leica EBPG 5000) with HSQ resist with modified parameters to account for the three dimensional topography. Etching of non-planar gate electrodes poses additional problems compared to planar technology. The selectivity of the polysilicon etch rate over gate oxide etch rate must be sufficient to allow for an adequate overetch to avoid the formation of parasitic spacers or the partial removal of the silicon source and drain leads (see schematic in Fig. 3).

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Figure 3. Schematic of undesired etching results in non-planar devices due to insufficient selectivity (after deposition (a), parasitic spacer (b) and removal of source/drain leads (c)).

The gate stack has therefore been patterned with a different HBr-based two-step process in the ICP-RIE system with an even higher etch selectivity. The source, drain and gate doping has been accomplished with a self aligned ion implantation and rapid thermal activation with temperature and duration depending on the respective n- and p-type dopants. A scanning electron microscope (SEM) image of a processed multi-channel triple gate MOSFET with L = 70 nm and W = 40 nm is shown in Fig. 4). Ultimate triple gate MOSFETs with dimensions below 10 nm are essentially gated silicon nanowires. It is an open question whether conventional, top-down fabrication methods can deliver such devices in an industrial scale, or whether bottom-up self-organized growth mechanisms can be maturated to the requireed degree. The limits of top down lithography have been explored by fabricating nanowires thin SOI material down to 7 nm. The process technology has been identical to the MOSFET fabrication descibed above, including the Leica EBPG 5000 e-beam system, HSQ resist and HBr-based reactive ion etching. An SEM image of a silicon nanowire with a width below 7 nm is shown in Fig. 5).

Source

BOX Gate

Drain Figure 4. SEM image of a multi-channel triple gate transistor (L = 70 nm, W = 40 nm).

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Figure 5. SEM image of a silicon nanowire fabricated with e-beam lithography.

3.2. FEASIBILITY OF UV NANOIMPRINT LITHOGRAPHY

UV-based nanoimprint is a low cost, high resolution nanolithography technique, which has recently been added to the ITRS roadmap as a contender for end of roadmap technology5. One of the crucial requirements for any such lithography is alignment accuracy of the different layers. To demonstrate the feasibility, functional triple gate MOSFETs have been fabricated, where both critical lithography steps for the top silicon wire and the gate electrode have been carried out by UV-NIL44. SOI wafers with a top silicon thickness of tSi = 40 nm and a buried oxide of tBOX = 400 nm have been implanted with a dose of 5e12 boron ions/cm² and annealed at 1000°C for 1h. UV-nanoimprint lithography has been used to define the transistor channels and alignment markers in layer 1. A 5 mm thick quartz mold with a diameter of 2.5 cm and a feature depth of 150 nm has been printed into the resist at a pressure of 300 mbar at reduced ambient pressure of 20 mbar45. The resist has then been cured in UV light and the mold has been detached. A CHF3-based reactive ion etching (RIE) process has been chosen to etch the residual resist layer, followed by an SF6/O2 process to form the silicon wires. The gate stack has been formed by thermal oxidation to tox = 8 nm and LPCVD of 100 nm undoped poly silicon. The poly silicon has been implanted with arsenic to 1e20 ions/cm². Lithography of the second layer has been carried out once more by UVnanoimprint with a 160 nm deep pattern of gate electrodes and level 2 alignment markers. Pre-alignment has been achieved with circular moiré markers to half of the interferometric grating pitch46. After coarse alignment, the maximum imprint pressure has been applied and a high precision interferometric technique with cross-gratings of 1 µm pitch in x- and ydirection has been used in contact for fine alignment. The alignment errors

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achieved after curing in UV-light are an order of magnitude lower than those achieved via optical markers. Again, the CHF3-based RIE process has been used to etch the residual resist layer, while the polysilicon gate electrodes have been etched with the highly selective HBr ICP-RIE process described elsewhere42,43. An implantation of arsenic followed by rapid thermal activation has resulted in a source and drain doping concentration of 2e20 ions/cm². Fig. 6 shows a scanning electron microscope image of a triple gate FET fabricated with two UV nanoimprint processes. The width of the silicon wire is W = 20 nm and the gate length is L = 200 nm. The misalignment of the gate electrode layer and the channel layer is below 20 nm. A detailed description of the fabrication process, the alignment routine and the UV-imprint process can be found elsewhere44,45. 3.3. SELF ALIGNED SILICIDATION

An inherent problem of nanoscale multi gate devices is their high parasitic access resistance. Simulations of such ultimately scaled devices have revealed that this leads to severely reduced on-currents and performance compared to theoretically achievable values47. Promising solutions to reduce the resistivity are raised source and drain areas manufactured by selective epitaxy48, by self aligned polysilicon49 or by self aligned silicidation50-52. Here, a self aligned nickel silicide process for source and drain leads of ultra thin body MOSFETs on SOI is investigated.

Figure 6. SEM image of a triple gate MOSFET fabricated with nanoimprint lithography.

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UTB MOSFETs have been fabricated using SOI-material with a 100 nm thick top-silicon film. After channel implantation to a concentration of 5e17 ions/cm³ and rapid thermal activation, the top-silicon layers have been thinned down to 80, 60, 30 and 15 nm using dry oxidation and subsequent HF wet etch. The channel has been etched with an HBr-based process in an Oxford Instruments RIE tool. An 8 nm thermal gate oxide has been grown and a 150 nm LPCVD polysilicon gate has been deposited. Similar to the triple gate FETs, a highly selective HBr etch process has been used to define the active gate areas42,43. Self-aligned arsenic source/drain implantations, tuned to correlate with the top-silicon-thicknesses, and rapid thermal annealing have been performed to achieve doping concentrations of 1e20 ions/cm3. A silicon nitride (Si3N4) spacer has then been formed by an LPCVD Si3N4-layer and subsequent highly anisotropic RIE etching with CHF3 and O2. A precise sputter process has been performed to deposit well controlled nickel films to match the respective top-silicon layers according to the reaction equation (1)51. 1 nm Ni + 1,84 nm Si –> 2,2 nm NiSi.

(1)

The NiSi has been formed by rapid thermal processing at 500°C and the unreacted nickel on buried oxide and the Si3N4 spacers have been removed by selective wet chemical etching. In Figure 7, an SEM image of a nickelsilicided MOSFET structure is shown. The source and drain of the transistor are fully silicided, while the thicker polysilicon gate is partially silicided, reducing the gate resistivity is as a beneficial side effect. If nickel silicide leads are to be used for ultimately scaled triple gate MOSFETs or FinFETs, they will have to withstand an extremely high current density. Current-voltage characteristics of NiSi nanowires have

Figure 7. SEM image of a nickel silicided MOSFET structure.

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2

current density J [A/cm ]

therefore been studied for various wire widths and lengths. As shown in Figure 8(a), NiSi nanowires exhibit ohmic behavior up to a certain current density, but are limited by destructive breakdown, indicated by the sharp current decrease. The SEM image in Figure 8(b) shows an example of a NiSi wire after destructive breakdown. Independent of device geometry, a typical maximum current density of J > 2·108 A/cm² has been reached, which corresponds well with results obtained from grown silicon nanowires53. In order to put the results for NiSi wires into perspective, we have compared them to on-current targets for future MOSFET generations defined in the ITRS. A rule of thumb for triple gate MOSFETs has been used to calculate current densities from on-currents: Triple gate transistors have been assumed to have equal values for with, height and length. The results are plotted in Figure 9 up to the 9 nm node, which translates into a current density of J = 1.2·108 A/cm² in 2020. Indicated by a black star, the maximum current density in NiSi exceeds ITRS requirements for final CMOS generations by a small margin. 8

5x10

8

8

4x10

8

3x10

FUSI NiSi Width: 36nm Heigth: 15nm Length: 90nm

2

Jmax = 3.8*10 [A/cm ]

8

2x10

8

1x10

0 0.0

0.2

0.4

0.6

voltage V [V]

0.8

1.0

Figure 8. Current density - voltage characteristic of a NiSi nanowire (a) and SEM image of an electrically destroyed NiSi nanowire. 8

2.0x10

this work: NiSi Jmax 8

2

J [ A/cm ]

1.5x10

8

1.0x10

7

ITRS HP devices

5.0x10

0.0 45

40

35

30

25

20

15

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ITRS Tech. Generation [nm]

Figure 9. Comparison of maximum current densities of future technology generations derived from the ITRS with results obtained in this work.

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4. Conclusion The ITRS defines technology requirements until fifteen years from now and down to the sub-10 nm range. While it is questionable for economic reasons, whether electron devices with such dimensions will ever be mass produced, enabling technologies should be investigated today. In this paper, some options for future non-planar device architectures have been discussed with regards to their manufacturability. As EUV lithography may be only available to very few large companies, other less costly options may be considered. Direct write electron beam and nanoimprint lithography are therefore proposed to fabricate triple gate MOSFETs. In addition, parasitic source and drain access resistance may limit the performance of end-ofroadmap CMOS circuits. Nickel silicidation has therefore been investigated as one option to overcome this limitation. While some technological options for the final scaling chapters of CMOS have been suggested, the decision for or against such technologies will certainly be taken out of the hands of engineers and physicists and made solely based on economical reasoning. ACKNOWLEDGEMENTS The authors would like to thank their colleagues J. Bolten, T. Echtermeyer, J.E. Efavi, T. Mollenhauer, M. Schmidt and T. Wahlbrink for fruitful discussions and device processing. Financial support by the German Federal Ministry of Education and Research (BMBF) within the research projects “HSOI”, “KrisMOS” and “MINALI” is gratefully acknowledged.

References 1. 2. 3. 4. 5. 6. 7. 8.

G.E. Moore, “Cramming more components onto integrated circuits”, Electronics, 38(8), April 1965. s:R. H. Dennard, F. H. Gaensslen, L. Kuhn, H. N. Yu, “Design of micron MOS switching devices,” Tech. Dig. IEDM, 1972. G. Baccarani, M.R. Wordeman, R.H. Dennard, “Generalized Scaling Theory and Its Application to a 1/4 Micrometer MOSFET Design”, IEEE Trans. on Electron Devices, 31(4): 452-462 1984. P. Packan, “Pushing the Limits”, Science, (285), 1999. International Technology Roadmap for Semiconductors, “Front End Processes”, 2005 edition. J.-P. Colinge, “Silicon-on-Insulator Technology: Materials to VLSI, 3rd Edition”, Kluwer Academic Publishers, Boston, Dordrecht, London, 2004. S. Cristoloveanu, S.S. Li, “Electrical Characterization of Silicon-On-Insulator Materials and Devices”, Kluwer Academic Publishers, Boston, Dordrecht, London, 1995. J.B. Kuo, S.-C. Lin, “Low-Voltage SOI CMOS VLSI Devices and Circuits”, John Wiley & Sons, New York, 2001.

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31. J.M. Hergenrother et al., “The Vertical Replacement-Gate (VRG) MOSFET: A 50-nm Vertical MOSFET with Lithography-Independent Gate Length”, IEDM Tech. Dig., 7578, 1999. 32. A.C. Lamb, L.S. Riley, S. Hall, V.D. Kunz, C.H.d. Groot, P. Ashburn, “A 50nm channel vertical MOSFET concept incorporating a retrograde channel and a dielectric pocket”, 31st European Solid-State Device Research Conference, ESSDERC 2001, 347-350, 2001. 33. J. Moers, S. Trellenkamp, L. Vescan, M. Marso, P. Kordoš, H. Lüth, “Vertical DoubleGate MOSFET based on epitaxial growth by LPCVD” 31st European Solid-State Device Research Conference, ESSDERC 2001, 191-194, 2001. 34. B. Goebel, J. Lutzen, D. Manger, P. Moll, K. Mummler, M. Popp, U. Scheler, T. Schlosser, H. Seidl, M. Sesterhenn, S. Slesazeck, S. Tegen, “Fully depleted surrounding gate transistor (SGT) for 70 nm DRAM and beyond”, IEDM Tech. Dig., 275-278, 2002. 35. A. W. Topol, D. C. La Tulipe, Jr., L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, M. Ieong, “Three-dimensional integrated circuits”, IBM J. Res. & Dev. 50(4/5): 491-506, 2006. 36. J.P. Colinge, “Multiple-Gate SOI MOSFETs”, Solid-State Electron, 48(6): 897-905, 2004. 37. I. Stolberg, P. Hahmann, J. Gramss, “Variable-Shaped-Beam Direct Writing In Semiconductor Manufacturing”, Semiconductor Manufacturing Magazine, April 2006. 38. Y. Sohda, H. Ohta, F. Murai, J. Yamamoto, H. Kawano, H. Satoh, H. Itoh, “Recent progress in cell-projection electron-beam lithography”, Microelectronic Eng., 67-68: 78-86, 2003. 39. T. H. P. Chang, M. Mankos, K. Y. Lee and L. P. Muray, “Multiple electron-beam lithography”, Microelectronic Eng., 57-58: 117-135, 2001. 40. B.E. Maile, W. Henschel, H. Kurz, B. Rienks, R. Polman, P. Kaars, “Sub-10nm Linewidth and Overlay Performance Achieved with a Fine-Tuned EBPF-5000 TFE Electron Beam Lithography System”, Jpn. J. Appl. Phys., 39: 6836-6842, 2000. 41. W. Henschel, Y.M. Georgiev, H. Kurz, “Study of a high contrast process for hydrogen Silsesquioxane as a negative tone electron beam resist”, J. Vac. Sci. Technol. B 21(5): 2018-2025, 2003. 42. M.C. Lemme, T. Mollenhauer, H. Gottlob, W. Henschel, J. Efavi, C. Welch, H. Kurz, “Highly selective HBr etch process for fabrication of Triple-Gate nano-scale SOIMOSFETs”, Microelectronic Eng., 73-74, 346-350, 2004. 43. T. Wahlbrink, T. Mollenhauer, Y.M. Georgiev, W. Henschel, J.K. Efavi, H.D.B. Gottlob, M.C. Lemme, H. Kurz, J. Niehusmann, P. Haring Bolivar, “Highly selective etch process for silicon-on insulator nano-devices”, Microelectronic Eng., 78-79: 212217, 2005. 44. A. Fuchs, M. Bender, U. Plachetka, L. Kock, T. Wahlbrink, H.D.B. Gottlob, J.K. Efavi, M. Moeller, M. Schmidt, T. Mollenhauer, C. Moormann, M.C. Lemme, H. Kurz, “Nano-wire FinFETs via UV-based Nanoimprint Lithography”, J. Vac. Sci. Technol. B 24(6): 2964-2967, 2006. 45. A. Fuchs, M. Bender, U. Plachetka, U. Hermanns, H. Kurz, “Ultraviolet-based nanoimprint at reduced environmental pressure”, J. Vac. Sci. Technol. B 23(6): 29252928, 2005. 46. K. Patorski, M. Kujawinska, “Handbook of the Moiré Fringe Technique”, Elsevier, Amsterdam, 1993. 47. S. Hasan, J. Wang, M. Lundstrom, “Device design and manufacturing issues for 10 nmscale MOSFETs: a computational study”, Solid-State Electron, 48(6): 867-875, 2004. 48. R. Chau, J. Kavalieros, B. Doyle, A. Muthy, N. Paulsen, D. Lionberger, D. Barlage, R. Arghavani, B. Roberds, M. Doczy, “A 50nm Depleted-Substrate CMOS Transistor (DST)”, IEDM Tech. Dig., 621-624, 2001.

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49. Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor, C. Hu, “Ultrathin-Body SOI MOSFET for Deep-Sub-Tenth Micron Era”, IEEE Electron Dev. Let., 21(5), 2000. 50. F. Deng, R.A. Johnson, P.M. Asbeck, S.S. Lau, W.B. Dubbelday, T. Hsiao, J. Woo, “Salicidation process using NiSi and its device applications”, J. Appl. Phys., 81(12), 1997. 51. B. Froment et al., “Nickel vs. Cobalt Silicide integration for sub-50 nm CMOS”, 33rd European Solid-State Device Research Conference, ESSDERC 2003, 215-218, 2003. 52. M. Schmidt, T. Mollenhauer, H.D.B. Gottlob, T. Wahlbrink, J.K. Efavi, L. Ottaviano, S. Christoloveanu, M.C. Lemme and H. Kurz, “Nickel-Silicide Process for Ultra-ThinBody SOI-MOSFETs”, Microelectronic Eng., 82(3-4): 497-502, 2005. 53. Y. Wu, J. Xiang, C. Yang, W. Lu, C.M. Lieber, “Single crystal metallic nanowires and metal/semiconductor nanowire heterostructures”, Nature, 430(July): 61-65, 2004.

HIGH-κ DIELECTRIC STACKS FOR NANOSCALED SOI DEVICES S. HALL*, O. BUIU, I.Z. MITROVIC, Y. LU, W.M. DAVEY Department of Electrical Engineering & Electronics, Brownlow Hill, University of Liverpool, L69 3GJ UK *To whom the correspondence should be addressed: [email protected]

Abstract. The combination of ultra-thin body (UTB), undoped silicon-oninsulator films to control short channel effects and high permittivity (κ) gate dielectric with metal gate to control gate leakage current, can provide a highly scaleable technology to address challenges towards the end of the road map. This paper sets out the basic issues and physics associated with both hi- κ/metal gate and UTB from a device perspective, and establishes the advantages associated with merging the two approaches. A review of the state-of the art devices is undertaken also which serves to emphasize the great potential and progress of this technology.

Keywords: high-κ dielectric stacks, nanodevices, SOI

1. Introduction The silicon microelectronics revolution has been largely driven by continuing miniaturisation of the devices and associated interconnections as directed by Moore’s Law. The law predicts an exponential relationship between, for instance, the number of components on a chip with time. A number of related parameters such as delay and power consumption also follow the general trend. The industry has encapsulated these trends together with indications of solutions to potential roadblocks in the ITRS roadmap1. The roadmap document constitutes a reference manual which informs research directions for the community engaged in Si related research. The scaling of devices for the immediate future seems to be feasible with relatively conventional approaches together with the ‘technology booster’ of local strain to compensate for degradation in the charge carrier mobility which is incurred as a result of the channel engineering required to avoid excessive short channel effects (SCE). In particular, a 33 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 33-58. © 2007 Springer.

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HI-κ AND UTB-SOI

nitrided silicon dioxide gate oxide of the order 1.5 nm can control adequately the electrostatic integrity of the MOSFET channel at least in the short term although there is a case for heavily nitrided silicon dioxide to further generations2. Looking then to subsequent generations, the gate oxide must become vanishingly thin; in fact, the ITRS roadmap predicts equivalent oxide thicknesses of 1 nm in 2007, reducing to 0.35 nm for the 22 nm node1. Notwithstanding other issues, at least three mono-layers of SiO2 are required so that ‘bulk’ like properties can be achieved giving a lower limit for the native oxide in any event, of about 0.7 nm3. Of course, such oxide thickness reduction comes at a price because the quantum mechanical current leakage through the gate becomes prohibitively high and so therefore is the stand-by power dissipation in chips which even now can contain a billion individual transistors. Moreover, the gate leakage must be reduced without compromising the current drive (ION) of the transistor therefore materials with higher dielectric constant (κ) are sought to allow a thicker oxide for the same gate capacitance, so mitigating the leakage problem. It is likely that hi-κ will enter the mainstream technology at the 45 nm technology node although there is a possibility also for a heavily nitrided SiO2 layer. Any replacement for silicon dioxide as a gate material must satisfy stringent requirements which can be summarised4 as relating to: a) thermodynamic stability in contact with Si; b) a high enough κ to warrant the cost of R&D – including a propensity to be scaled; c) band offsets for electrons and holes >1 eV which translates to band gap energies (Eg) > 5 eV taking into account the inverse relationship between Eg and κ; d) stability through a high temperature CMOS manufacturing process and finally, acceptable reliability and wear-out attributes to achieve industry standard product lifetimes, typically ten years. With these constraints in mind, the periodic table reveals, perhaps not surprisingly, relatively few contenders. In the short to medium term, taking account of ITRS performance requirements, the metallic oxide hafnium oxide (HfO2 or hafnia) is the main contender and its silicates and aluminates can reduce the tendency for crystallisation occurring at temperatures beyond about 450oC, at the expense of a slight reduction in the κ values. Looking at the requirements for the 22 nm node, contenders such as Pr, La look to be promising, while Gd, Ce and Sm oxides are also worthy of consideration in many respects. Alongside the challenges of the gate leakage, is the need to maintain the electrostatic integrity of the device; that is to say, the electric field imposed by the gate electrode must win in the competition with the drain field encroachment, to minimise undesirable short channel effects. Solutions require either double gate architectures such as the FINFET or fully depleted (FD), ultra-thin body (UTB) silicon-on-insulator (SOI) devices5,6. It has been

HI-κ AND UTB-SOI

35

proposed that the excellent electrostatic integrity brought with the FINFET architecture brings the potential for scaling to the 22 nm node whilst maintaining nitrided SiO2 for the gate oxide7. The FINFET however faces major challenges not least due to the challenges around the large parasitic source and drain series resistance. The UTB-SOI device with hi-κ gate oxide and metal gate then provides a potential solution for the 22 nm node and it is worth noting that a study is made in these proceedings whereby a comparison between bulk and UTB-SOI is made8. The paper is organised as follows. Section 2 describes briefly the dielectric physics underlying the increase of the permittivity, κ. The section also includes a brief summary of the metrology challenges for characterising these gate materials and a description of the enhanced charge trapping evident in the films. Section 3 includes a review of the hafnium oxide system which is the most widely studied material for this application. Hafnia has the disadvantage of relatively poor thermal stability in the context of a CMOS process. Introduction of either aluminium or silicon to form aluminates and silicates respectively allow higher thermal stability and a review of important results are presented in the section also. Section 4 includes consideration of some basic issues associated with the combination of hi-k gate dielectric and metal with UTB-SOI and also contains a review of state-of-the art results for this technology. The paper is concluded in section 5. 2. Physics and metrology of hi-κ dielectrics 2.1. DIELECTRIC PHYSICS

Figure 1, reproduced from Ref. 9, presents a useful description of the frequency dependence of the dielectric function over a wide range of frequencies. In general, the ‘zero frequency’ value of the dielectric constant can be seen to have two components: a ‘high – frequency’ one, where the contribution of electronic polarization dominates and one related to the ionic contribution10. In the CMOS frequency window, we can see that electronic and ionic processes contribute to κ and we consider that the permittivity is given by the relation:

ε ox = ε ∞ + ε latt

(1)

where εox is equivalent to κ. The electronic component, which arises from simple polarisation of the atoms, is the main component for SiO2 and the simple relationship n ~ ε ∞ links the refractive index, readily measurable

36

HI-κ AND UTB-SOI

Figure 1. The frequency spectrum of permittivity: εr’ is the real part and determines the gate capacitance, εr’’ is the imaginary part and reflects the losses in the dielectric layer9.

in ellipsometry, to the permittivity, giving ε ox ~ ε ∞ . The essence of increasing κ then is to choose materials that can contribute a large lattice component. Table 1 shows some values of these parameters for different crystalline forms of hafnia. We can see that εox can vary from less than 10 to about 25 depending on the crystalline form. Without going into details of the crystallography, we can simply make the point that the permittivity can vary over a wide range depending on the form of the material and hence the method used to prepare it. Furthermore, amorphous forms are preferred for processing in any event. The variability of κ with the structure of various metallic oxides is pointed out from another perspective in Ref. 11, by consideration of the Clausius-Mossotti (C-M) theory which links the κ to the polarizability α, and the volume of the unit cell, Vm as described in Eq. 2: TABLE 1. Differing structural forms of hafnia can result in wide variations of permittivity indicating the dependence on deposition process and subsequent manufacturing conditions Crystalline phase

ε∞

εlatt

εox (k)

c-HfO2 t-HfO2: parallel t-HfO2:perpendicular m-HfO2: yy m-HfO2: xx m-HfO2: zz m-HfO2:xz

5.37 5.13 5.39

20.80 14.87 27.42 10.75 11.70 7.53 1.82

26.17 20.00 32.81

⎛ 2 α ⎞ ⎜⎜1 + 4π ⎟ 3 V M ⎟⎠ ⎝ . εr = 1 α 1 − 4π 3 VM

(2)

37

HI-κ AND UTB-SOI

In essence, larger atoms yield more polarization and hence higher κ values. The C-M equation reveals that κ raises steeply as the ratio α/Vm increases demonstrating the strong connection with the structure and nature of the material. The form of Eq. 2 is simplified so to illustrate the basic point and assumes homogeneity of the material but can readily be extended to encompass greater complexity of the dielectric layer morphology and related polarization phenomena9. A similar approach can be applied to the case of mixed oxides, i.e. MxOy+M’pOq, resulting in so called “additivity rule” where the polarizability of the mixed oxide MAxM’BpOay+Bq can be expressed as follows:

(

)

(

' α m M Ax M Bp O Ax + By = Aα m (M x O y ) + Bα m M 'p O q

)

(2a)

Using Eq. (2a) a similar expression for ε r of mixed oxides can be written, with Vm now being the volume of the complex molecule12. It is obvious that in such a case the dielectric constant of the mixed oxide has precise high and low limits, given by the dielectric constants of the oxides being mixed. However, there are situations when abnormal variations in the dielectric constant can result from molecular volume modifications induced during the alloying process especially when low and high coordination metal oxides are concerned (such as Hf and Zr oxides versus SiO2). 2.2. PARASITIC CHARGE AND RELATED METROLOGY CHALLENGES

A key advantage of the SiO2 system is the excellent electrical properties in terms of parasitic electron and hole traps. As-grown and appropriately annealed thermal oxide contains very low trap concentrations with relatively small capture cross-sections, which translate to time constants for oxide charging under normal operation. As well as being virtuous for integrated circuit engineering, the excellent and relatively stable intrinsic properties has made far easier the characterisation and study of the properties of these traps. Investigation of trapping in SiO2 has been a major activity for nearly 50 years. For the hafnia system, and some other high-κ dielectrics, electron trapping is extremely severe and a need arose for specialized measurement configurations to characterise the extremely fast trapping kinetics. Figure 2 shows a typical set-up of an analogue based technique whereby the drain current is monitored across a small drain load resistance and fed to an oscilloscope13 although the technique has been refined further14.

38

HI-κ AND UTB-SOI

Figure 2. Typical set-up to measure transfer characteristics of hi-k gate stack MOSFETs.

A study by Zhang15 illustrates effectively the trapping time constants and it can be seen that data capture of the order of 10’s of microsecond are required to capture the full extent of the trapping. Translating the timedependence of the voltage shifts with first order trapping theory reveals for as-grown electron traps, two effective capture cross-sections of the order of 10-15 cm2 with concentrations of the order of 1012 cm-2; these being very large values relative to SiO2. Considering an associated ‘capture radius’ of σ / π gives trap ‘sizes’ of the order of 2 nm which are only about a factor of two less than typical film thicknesses. Furthermore, the concentrations of defects imply average trap separations of a similar order. It’s worth noting also that breakdown in SiO2 occurs when defect levels rise to concentrations of this order with commensurate similarity in trap spacing. The propensity for percolation paths in such hi-k films is therefore high and the films are also likely to be more prone to parasitic stress-induced leakage currents. It is important to point out that such closely spaced traps makes the use of the first order trapping theory somewhat controversial. However, the values at least convey the rapid nature of the trapping and are useful for providing a representation of the time constants associated with the phenomenon. Other trapping studies show also that the films are rich in fixed positive charge with similar concentrations. It is possible also to create positive charge by stressing, with similar concentrations to the as-grown ones16. The measurements are usually carried out on MOSTs but there is a great advantage to employing MOS capacitors due to the simplicity of the structure. Capacitor based measurements can be employed for rapid screening of new materials. We have developed a novel measurement system based on pulsing MOS capacitors17 and is depicted in Fig. 3.

HI-κ AND UTB-SOI

39

Figure 3. The MOSC is pulsed from accumulation to deep depletion and as electrons are detrapped from the film, a positive charge centroid is developed which causes an undershoot in the capacitance transient.

Using this technique, which involves a deep-depleting voltage step, we can detect the presence of positive charge which would not readily be apparent from transistor based measurements which involve an inverted surface with a ready supply of minority carriers. Fast pulse techniques allow the C-V plot to be constructed to obviate the effects of electron trapping which compromises the standard, dc sweep technique18. 3. A review of hafnium oxide and its aluminates and silicates 3.1. HAFNIUM OXIDE

The hafnia system is the most widely studied and offers many of the necessary attributes in terms of both manufacture and electrical properties to satisfy the industry. It is likely to be adopted for low-stand-by power (LSTP) technology at the 45 nm node, by a number of companies. Hafnia is detailed in the various excellent reviews of hi-k dielectrics2,4,19,20 and in particular, generic challenges are described in Ref. 21. Surface preparation involving growth of a chemical oxide (SiOx) is paramount although this does add to the equivalent oxide thickness (EOT) and presents a scaling limitation. Problems of Fermi-level pinning between a poly gate electrode and the high-k film makes metal gate mandatory for this system to yield sub 1 nm EOT. Channel mobility is reduced significantly by the high levels of oxide charge and associated coulombic scattering: the remote charge scattering (RCS) effect. The large traps give rise to electron trap charging/discharging instabilities but these may be mitigated at very high digital switching speeds. Reliability issues are prevalent and in particular, as mentioned in section 2.2, SILC arising from the large traps in these thin films both as-grown and generated by voltage stress. The other key

HI-κ AND UTB-SOI

40

reliability issues such as negative bias instability and time-to-breakdown represent ongoing challenges. There is considerable evidence both experimental and theoretical, that the physical origin of the transient charge trapping behaviour in HfO2 may be attributed to oxygen vacancies since their energy levels appear above the silicon conduction band22. Using density functional theory methods, Gavartin et al.23 pointed out that negatively charged oxygen vacancies in HfO2 should be responsible for the trap discharging behaviours. This result is consistent with the electrical results observed by Ribes et al.24 who concluded that the threshold voltage, Vt instability is due to an equilibrium balance of electron tunneling from channel to traps and detrapping by Poole–Frenkel conduction towards the electrode although the basic model, shown in Fig. 4, was first proposed in Ref. 25 and further in Ref. 13. A trap level about 0.7 eV from the conduction band edge of the hafnia film was deduced in Ref. 25 whereas in the work of Ribes24 a trap energy of 0.35 eV was extracted. Both can be considered to link to negatively charged oxygen vacancies. Tse26 and Xiong27 respectively proposed strategies for the passivation of oxygen vacancies in HfO2, namely incorporation of fluorine and nitrogen. Their ab initio calculation showed that these two elements should be effective passivants for oxygen vacancies in hafnia. Another question associated with defects in HfO2 is their spatial distribution. Heh et al.28 applied the charge pumping technique to extract the spatial distribution of traps in SiO2/HfO2 gate stacks. They found that electron traps accessible by CP measurements are located within or near the interfacial SiO2 layer rather than in the bulk of the high k film. It is believed that hydrogen is also responsible for the anomalous positive charge creation in HfO2. Work by C. Zhao et al.16 demonstrated HfO2/SiO2 MOS transistors As-grown e-traps e Ec Ef Ev

EFm

Et=0.5∼0.8eV

e Et

Gate

HfO2

SiO2 Si

(a) e trapping at Vg>0

(b) e detrapping at Vg18%), whereas for Si and Ge lattices, this value is near to 4%. To increase the upper Si lattice parameter we use Sb implantation and solid state epitaxial regrowth of the upper Si layer prior to bonding. We suggest that this increase in Si lattice constant would serve to accommodate stress for the InSb film growth at the Si/SiO2 interface. All other treatments were the same as for the case of In and Sb ion implantation into BOX.

Figure 5. XTEM bright (a) and dark (b,c) field images of SOI with InSb atoms in buried oxide (BOX) after annealing at 800oC (a,b) and 900oC (c). Bright strip on image (b) is due to an InSb film incoherent with the upper Si lattice.

NANOSCALED SEMICONDUCTOR HETEROSTRUCTURES

67

RBC Yield, counts

2000 Random Aligned

1500 1000 500 o

InSb S-10 - 500 C 0

200

400

600

Channels

(a)

RBC Yield, counts

2000 Random Aligned

1500 1000 500 o

InSb S-10 - 500 C 0

200

400 Channels

600

(b)

Figure 6. RBS/channeling spectra of SOI with InSb in BOX and at upper Si/SiO2 interface after annealing at 500oC (a) and 800oC (b).

The RBS/channeling results are presented on Figure 6. Evidence of strong InSb accumulation at the upper Si/SiO2 interface is seen as a peak at channel number 750 on Figure 6b. In this case we observed a larger region (~30%) of InSb atoms coherent with the upper Si lattice; 5-7 monolayers of InSb film at the Si/SiO2 interface. The high resolution image of Figure 7a confirms this estimation. The InSb film looks like a dark strip of coherent atoms at the interface. Dark spots in the BOX are due to incoherent InSb nanoclusters near the interface. The HREM image in Figure 7b shows a transition from a flat to rough InSb film and a growth of strain in the Si crystal after higher temperature treatment at 900oC. Lose of pseudomorphism is also observed in thicker parts of the InSb film with the highest contrast.

68


(a)

(b)

Figure 7. HREM image of SOI with InSb atoms at upper Si/SiO2 interface and in buried oxide SiO2 (BOX) after annealing at 800oC (a) and 900oC (b) for tensile strained upper Si layer.

Higher temperature treatments at 1000 and 1100oC completely destroy pseudomorphic InSb films and lead to semi-coherent InSb islands placed exactly at the top Si/SiO2 interface, as shown in Figure 8. The BOX and bottom Si/SiO2 interface are free from InSb nanoparticles, as shown on the XTEM and HREM images in Figure 8a. Semi-coherent InSb islands appear at both sides of the top Si/SiO2 interface and have (111) planes inclined from (111) planes of the upper Si layer with inter-plane spacing equal to 0.365 nm, which corresponds to the value for pure InSb. These InSb islands have elliptical form with dimensions 20-30 nm along the Si/SiO2 interface and 10-20 nm across, with moiré fringes on the Si side (Figure 8b). Incorporation of tensile strain into the top Si layer produces quite different InSb atom distributions including a thin pseudomorphic film in SOI structure as can be seen in Figures 5, 7 and 8. Semi-coherent InSb islands at the top Si/SiO2 interface, with different orientations with respect to top Si layer are also evident. This approach may be useful in the case of huge lattice mismatch for HOI formation by an IME process.

(a)

(b)

Figure 8. Bright XTEM (a) and HREM (b) images of SOI with InSb nanocrystals at top Si/SiO2 interface after annealing at 1100oC during 1 h. Dark strip on image (b) is due to InSb lattice moiré fringes with Si.


69

3. Discussion 3.1. THERMODYNAMICS AND KINETICS OF THE IME PROCESS

3.1.1. Thermodynamic and kinetic driving forces A monotonic increase in Ge film thickness for increasing growth time or temperature is not consistent with the disappearance of the InSb film for similar conditions. This disparity may be connected with the more thermodynamically stable configuration of Ge films at an Si/SiO2 interface compared to InSb. Consider thermodynamic quantities connected with new layer formation. It is known that for epitaxial growth of a new film in vapour or in liquid, that a stable layer requires that the following relationship between interfacial energies should take place (Frank – Van der Merwe growth): γBC > γAB + γAC ,

(1)

where γBC is an initial interface energy between B and C materials, and A is a new material with interfacial energies γAB and γAC between them. We suggest that the same relation is true for the case of endotaxy or oriented solid state regrowth without elastic stresses. According to the published data (see work9 and references therein), γBC (or interfacial Si/SiO2 energy) is equal to 1.44 J⋅m-2, γAB = 1.10 J⋅m-2 for the silicon-germanium interface, γAC ~ 0.8 J⋅m-2 for the germanium-silicon dioxide interface. These values do not satisfy the condition of Eq.1 suggesting that the driving force for Ge film formation is kinetic rather than thermodynamic. The observed dissolution of the Ge layer at longer annealing times supports this suggestion. Unfortunately, the interfacial energy data for InSb in the Si and SiO2 system is not complete in the literature so we cannot draw a conclusion about the mechanism, but it is clear that the preference for InSb nanocrystal growth within the BOX rather than at the Si/SiO2 interface may be due to the large lattice mismatch for pseudomorphic growth. 3.1.2. Phase transition during IME process We have mentioned before in Section 2.1.3, that Ge atom diffusivity in silica may be high due to the presence of hydrogen. Thus diffusion of Ge atoms in silicon may be a limiting factor for germanium segregation in silicon where the solubility is much higher. Accumulation of Ge atoms should take place at the Si/SiO2 interface causing melting of the SiGe alloy if the Ge content exceeds the equilibrium value for melting at a given annealing temperature. In the case of the Ge film melting, γAB , γAC should

70


fall to γAB =0.26 Jm-2 and γAC ~ 0.8 J⋅m-2 9, with the result that equation 1 is satisfied when the Ge film grows in liquid form. However this explanation is still not fully justified because we observed Ge film growth even at temperatures ≤900oC, which is much lower than the pure Ge melting temperature. We conclude that interface vacancies and implanted hydrogen mediated lowering of the interfacial energy may be responsible for the IME process. 3.2. ROLE OF STRESS IN THIN FILM GROWTH AND MOBILITY ENHANCEMENT

3.2.1. Lattice mismatch and metamorphic growth Pseudomorphic growth of a strained heterolayer of n monolayer (ML) thickness is thermodynamically favorable when the contribution of the elastic energy σ(n) to the total energy remains lower than that of the previous interfacial layer: γBC > γAB + γAC + σ(n),

(2)

If inequality 2 is not satisfied, metamorphic growth of an InSb film other than (100) silicon orientation is still possible. Such growth can be realised using patterned implantation or as a result of tensile stress in the top Si film. Even light tensile stress (a few percent) obtained by Sb implantation and solid state re-growth has allowed us to grow very thin (5-7 ML) InSb films at the moderate temperature of 800oC. Such tensile deformation can be introduced using a silicon nitride capping layer or silicide growth on a thin top Si layer. Metamorphic InSb nano-islands with other orientations than that of the Si can form during a high temperature treatment, by melting and recrystallization at the Si/SiO2 interface. 3.2.2. Mobility enhancement The trapping of negative charge by the Ge nanocrystals within the SiO2 layer was suggested as a possible reason for the observed effect of strong carrier accumulation6. Another explanation for this phenomenon is filling of the Ge QW layer by holes from the p- doped Si cap layer. The last explanation is more probable because in the case of n- doped silicon, carrier depletion was observed at the same fields even when the electrons were the majority carriers. This means that previously unexplained6 positive charge accumulation in dioxide with Ge nanocrystals, may be connected with Ge QW layer formation at the interface after high temperature annealing. Such a layer exhibits higher mobility for holes and may serve as a high mobility channel in the next generation of PMOS FETs. The InSb QW layer may be


71

a promising candidate for increasing electron mobility for NMOS FETs using the dual channel structure proposed by Fitzgerald10. 4. Conclusion We proposed a simple CMOS compatible approach named Interface Mediated Endotaxy (IME) for heterostructure-on-insulator (HOI) formation. IME is based on ion-implantation of semiconductor elements and subsequent endotaxial synthesis of an interfacial heterolayer combined with a proximal silicon layer, transferred and placed above the synthesized heterolayer at the bonding Si/SiO2 interface. Such an approach allows the use of the cost-effective CMOS planar technology for high mobility dual channel or quantum well FETs based on SiGe HOI structures. We speculate that an upper Si film on a few nanometer thin A3B5 layer allows the use of semiconductor heterostructures for CMOS volume production. The dual channel device design proposed by E. Fitzgerald can be employed also in dual gate HOI FETs and will allow better tuned characteristics than the dual channel devices on bulk silicon with buffer layer. Results presented here allow us to conclude that the proposed IME method can be an attractive alternative for integration of germanium or other semiconductors into new generations of CMOS technological nodes. ACKNOWLEDGMENTS

The authors thank Olga Naumova and Daniel Nikolaev for their help in electrical measurements; Gregory Pokhil and Vladimir Fridman for RBS measurements.

References 1. 2. 3. 4. 5. 6.

C. W. Leitz, M. T. Currie, M. L. Lee, Z.-Y. Cheng, D. A. Antoniadis, E. A. Fitzgerald, J. Appl. Phys. 92, 3745 (2002). S. Takagi, T. Mizuno, T. Tezuka et al., N. Sugiyama, S. Nakaharai, T. Numata, J. Koga, K. Uchida, Solid-State Electronics, 49, 6844 (2005). Z. Cheng, J. Jung, M. L. Lee, A. J. Pitera, J. L. Hoyt, D. A. Antoniadis and E. A. Fitzgerald, Semicond. Sci. Technol., 19, L48 (2004). M. L. Lee, E. A. Fitzgerald, M. T. Bulsara, M. T. Currie, and A. Lochtefeld, J. Appl. Phys. 97, 011101 (2005). L. Rebohle, I. E. Tyschenko, J. von Borany, B. Schmidt, R. Grötzschel, A. Markwitz, R. A. Yankov, H. Fröb, W. Skorupa, Mater. Res. Soc. Symp. Proc. 486, 175 (1998). I. E. Tyschenko, A. A. Franzusov, O. V. Naumova, B. I. Fomin, D. V. Nikolaev, V. P. Popov, Solid State Phenomena, 108-109, 77 (2005).

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J. W. Fleming, S. R. Kurkjian, U.-C. Paek, Journ. Amer. Ceram. Soc., 68, C-246 (1985). 8. H. A. Bracht, H. H. Silvestri, E. E. Haller, Advanced diffusion studies with isotopically controlled materials (November 14, 2004); http://repositories.cdlib.org/lbnl/LBNL-56924. 9. Q. Xu, I. D. Sharp, C. W. Yuan, D. O. Yi, C. Y. Liao, A. M. Glaeser, A. M. Minor, J. W. Beeman, M. C. Ridgway, P. Kluth, J. W. Ager III, D. C. Chrzan, E. E. Haller, Phys. Rev. Lett. 97, 155701 (2006). 10. E. Fitzgerald. Dual layer Semiconductor Devices, (US Patent 6,974,735, December 13, 2005).

FLUORINE–VACANCY ENGINEERING: A VIABLE SOLUTION FOR DOPANT DIFFUSION SUPPRESSION IN SOI SUBSTRATES HUDA ABDEL WAHAB EL MUBAREK* AND PETER ASHBURN Nanoscale Systems Integration Group, School of Electronics and Computer Science University of Southampton, Highfield, Southampton, SO17 1BJ, United Kingdom * To whom correspondence should be addressed: H.A.W. El Mubarek, e-mail: [email protected], tel: +44 2380593777, fax: +44 2380593029

Abstract. This paper reviews progress in vacancy engineering using a silicon implant into SOI substrates and considers the prospects for vacancy engineering using fluorine implantation. Vacancy engineering using a silicon implant comprises a high energy silicon implant into an SOI substrate, to separate the excess vacancies in the SOI layer and the excess interstitials below the buried oxide. Results on vacancy-engineering show that a properly optimized high energy silicon implant is able to suppress boron transient enhanced diffusion. Results are also presented on the behaviour of fluorine in bulk silicon and it is shown that a high energy fluorine implant not only completely suppresses boron transient enhanced diffusion but also significantly reduces boron thermal diffusion. The suppression of boron thermal diffusion is due to the formation of vacancyfluorine clusters that form at approximately half the range of the fluorine implant. Finally, fluorine implantation is applied to SOI wafers, with the aim of separating the vacancy-fluorine clusters in the active layer from interstitial dislocation loops below the buried oxide layer. These results show a high energy fluorine implant into SOI substrates is also effective in suppressing boron diffusion.

Keywords: Vacancy engineering, Fluorine, SOI

1. Introduction Silicon-on-Insulator (SOI) substrates are rapidly replacing bulk silicon substrates and opening a wide range of novel applications. According to 73 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 73-87. © 2007 Springer.

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Soitec, SOI will enable a $12 billion share of the worldwide IC market in 2006 [1]. SOI substrates have been driven deep into petroleum wells in SOI-MEMS pressure sensors and flown high into the sky in commercial aircraft circuitry and even taken to Jupiter and Mars in radiation hard data acquisition systems by Honeywell [1]. SOI substrates are now in all the new major electronic games. Microsoft has signed a contract with Chartered Semiconductor to migrate the IBM and Microsoft designed SOI microprocessor used in the Xbox 360 to the 65nm process node in the first quarter of 2007 [2]. Strained SOI is rapidly evolving. Soitec have recently released news of the commercial availability of their global strained SOI substrates in both 200mm and 300mm wafer sizes [3]. These are being used in the recently reported Freescale’s 45nm node CMOS technology for low power portable gaming electronics applications [3]. The SOI substrates rapid overtake of the semiconductor market is creating an urgent demand for ultra shallow junction solutions for the next generation SOI CMOS devices. Applying a Si or Ge preamorphisation implant prior to the dopant atom implant followed by solid phase epitaxial regrowth (SPER) and dopant activation of the layer, has long been used as a solution to eliminate channelling of light atoms such as boron and to improve dopant activation. However, preamorphisation and SPER are not suitable for the current and future ultra thin SOI substrates, because of the limitation introduced by the minimum thickness of a silicon seed layer to allow regrowth of the SOI layer [4]. This paper reviews progress in techniques used to suppress dopant diffusion in semiconductors such as vacancy engineering and fluorine co-implantation. Recent results on the prospects for vacancy engineering using fluorine are also presented.

Figure 1. A schematic of the defects distribution in an SOI substrate after a vacancy engineering implant.


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2. Vacancy engineering using Si implantation Vacancy engineering is an alternative solution to the problem of dopant diffusion suppression, which is directly applicable to SOI substrates. The basic concept is by applying a high energy silicon implant into an SOI substrate prior to the dopant implant a vacancy rich layer is created in the SOI layer, which is separated from the deeper interstitial rich layer via the buried oxide as illustrated in figure 1. The first group to experimentally study the decoupling of the vacancy and interstitial rich regions of an implant using a buried oxide layer in an SOI substrate were Roth et. al. [5]. They used a 2MeV silicon implant in an SOI substrate, which positioned most of the excess interstitials below the buried oxide layer and reported a reduction in boron transient enhanced diffusion. However, it was not possible to clearly identify the role of the excess vacancies as the boron itself was implanted and introduced excess interstitials. Later on Venezia et. al. [6] repeated Roth’s experiment using epitaxially grown boron marker layers. This proved conclusively that excess vacancies were responsible for the reduction in boron TED. Figure 2 shows the simulated vacancy and interstitial distributions caused by a 1MeV silicon implant before (a) and after (b) a 600s anneal at 790°C, after Venezia et. al. [6]. This shows clearly the excess vacancies region in the SOI layer and the excess interstitials region below the buried oxide.

Figure 2. (a) Simulation of the vacancy and interstitial distribution created after a 1 MeV, 1016cm-2 Si+ implant. (b) Simulation of the vacancy and interstitial distribution created after a 1 MeV, 1016cm-2 Si+ implant followed by a 600s anneal at 790°C. After Venezia et. al. [6].

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The diffusion of the epitaxially grown six boron marker layers in the top SOI layer was used to study the effects of the Si implants on B diffusion. A low energy 40keV Si+ implant was used to introduce excess interstitials into the top SOI layer and hence induce boron transient enhanced diffusion similar to a B+ implant. As seen from figure 3 (a) there is enhanced diffusion in the first three boron marker layers which had a 40keV Si+ implant. Hence, the excess interstitials introduced by the 40KeV Si+ implant have caused boron transient enhanced diffusion. In comparison in figure 3 (b) when the material has been exposed to a 1MeV Si+ implant prior to the 40keV Si+ implant no excess boron diffusion is observed. Hence, the excess vacancies introduced by the 1MeV Si+ implant have completely eliminated the excess interstitials introduced by the low energy Si+ implant.

Figure 3. (a) boron SIMS profiles of marker layers implanted with 40keV, 5×1013cm-2 Si+ followed by a 600s anneal at 790°C. (b) boron SIMS profiles of marker layers implanted with 1 MeV, 1016cm-2 Si+ followed by a 600s anneal at 790°C with and without a 40keV, 5×1013cm-2 Si+ implant prior to the anneal After Venezia et. al. [6].


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Recently, Nejim et. al. [7] reported a study of vacancy engineering using a 1 MeV Si+ implant to suppress boron transient enhanced diffusion. Various B+ implant energies were studied both in bulk and SOI substrates. It was shown that complete TED elimination occurred at 10keV B+. As seen in figure 4, the combination of the 1 MeV Si+ implant and the 5keV B+ implant in the SOI substrate results in less diffusion compared with the bulk silicon. More recently, Smith et. al. [4] reported an optimised vacancy engineering Si+ implant condition of 300keV which is more suitable for

Figure 4. High resolution SIMS boron profiles of a 5keV B+ implant; after implant (S0), after implant and anneal in a bulk Si substrate (S1) and co-implanted with 1MeV 1×1016cm-2 Si+ implant in an SOI substrate after anneal (S14). After Nejim et. al. [7].

(a)

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Figure 5. (a) B SIMS profiles after implant and after a 300keV Si+ implant and anneal at 700C. (b) Boron sheet resistance after implant and anneal, for B+ only, B+ and 300keV Si+ and B+ and 1MeV Si+ implanted samples. After Smith et. al. [4].

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industrial applications compared with the high energy Si+ implant. Boron activation with minimal diffusion was obtained annealing at 700°C as seen in figure 5(a). Sheet resistance measurements were reported, as shown in figure 5(b), the boron sample which had a 300keV Si+ implant has the lowest sheet resistance followed by the boron sample which had a 1MeV Si+ implant and the B+ only implanted sample. 3. Fluorine co-implantation Fluorine co-implantation is an alternative technique for boron diffusion suppression which is gaining a lot of interest. There have been several reports in the literature of fluorine co implantation suppressing boron transient enhanced diffusion [8-11]. Fluorine implantation has been applied to MOS transistors to reduce boron diffusion in critical areas of the source and drain [12] [13]. It was reported that fluorine implantation resulted in reduced junction capacitance, an improved Ion - Ioff trade-off [13] and improved threshold voltage roll-off characteristics [13]. Recently, we have reported silicon bipolar transistors with a record cut off frequency fT of 110GHz, which were fabricated using a high energy fluorine implant to suppress boron diffusion in the base [14]. 3.1. ELIMINATION OF BORON TED BY F+ IMPLANTATION

In this section we review our previous work on the elimination of boron transient enhanced diffusion and the suppression of boron thermal diffusion in silicon using F+ implantation as reported in [11]. As grown Annealed (P+& F+ implanted)

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Figure 7. Comparison of fluorine profiles before and after anneal for 30s at 1000°C in nitrogen for (a) the P+ & 2.3×1015cm-2 F+ implanted sample and (b) the 2.3×1015cm-2 F+ implanted sample . The corresponding annealed boron profiles are added for reference.

Figure 6(a) shows the effect of a 185keV, 2.3×1015cm-2 F+ implant on boron transient enhanced diffusion in samples implanted with P+. It is clear that there is dramatically less boron diffusion in the sample implanted with both P+ & F+. Comparing the boron profiles at a concentration of 1×1017cm-3, we observe that the diffusion of boron into the substrate in the P+ & F+ implanted sample (14nm) is 42nm less than that in the P+ implanted sample (56nm). Figure 6 (b) shows the effect of a 185keV, 2.3×1015cm-2 F+ implant on boron thermal diffusion in samples not given a P+ implant. It can be seen that there is considerably less diffusion in the sample implanted with F+ than in the unimplanted sample. Comparing the boron profiles at a concentration of 1x1017cm-3 we find that the diffusion of boron into the substrate for the F+ implanted sample (11nm) is 20nm less than that in the unimplanted sample (31nm). This indicates that the F+ implant has not only eliminated boron transient enhanced diffusion but has also dramatically reduced the boron thermal diffusion by 65%. Figure 7 compares the fluorine profiles of the (a) P+ & F+ implanted sample and of the (b) F+ implanted sample discussed in figure 6, before and after anneal at 1000ºC for 30s in nitrogen. The corresponding boron profiles are shown for reference. The annealed fluorine profiles of the P+ & F+ implanted sample and the F+ implanted sample are very similar. Both are considerably different than the as-implanted profile and show two broad peaks. The deeper broad peak lies within a depth range of 0.29µm to 0.73µm with a peak concentration of 8.31x1019cm-3 at a depth of 0.42µm for the (a) P+ & F+ implanted sample and with a peak concentration of 9.11x1019cm-3 at a depth of 0.43µm for the (b) F+ implanted sample. For the

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Figure 8. Cross sectional transmission electron microscopy micrographs of 2.3×1015cm-2 F+ implanted and annealed Si MBE layers (a) P+ & F+ implanted sample and (b) F+ implanted sample.

(a) P+ & F+ implanted sample; this peak almost coincides with the asimplanted peak concentration of 8.32x1019cm-3 at a depth of 0.42µm. The shallower peak lies between 0.055µm and 0.232µm, coinciding with the boron profile, and shows several small peaks. The integrated dose of the asimplanted fluorine SIMS profile is 2.3×1015cm-2 and the integrated fluorine doses after anneal are 1.5×1015cm-2 and 1.6×1015cm-2 indicating that 35% and 30% of the implanted fluorine has been lost during annealing for the P+ & F+ implanted sample and the F+ implanted sample respectively. The majority of the fluorine lost comes from the surface side of the fluorine peak, but there is also some loss of fluorine from the substrate side. Figure 8 shows cross sectional transmission electron microscopy micrographs of the P+ &F+ implanted sample (a) and the F+ implanted sample (b) after an anneal at 1000°C for 30s in nitrogen, samples discussed in figures 7(a) and (b) respectively. In both figures 8(a) and (b) the region from the surface to a depth of 0.29µm is smooth with no visible defects and a band of dislocation loops is seen from a depth of 0.29µm to a depth of 0.73µm, centred around the implantation range of 0.42µm. 3.2. EFFECT OF F+ IMPLANTATOTION DOSE ON BORON DIFFUSION

In this section we review our previous work on the effect of F+ implantation dose on boron thermal diffusion in silicon as reported in [15].



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Figure 9 shows a comparison of boron SIMS profiles in F+ implanted and unimplanted samples after an anneal at 1000°C for 30s in nitrogen. The as-grown boron profile is also included for reference. Results are shown for fluorine implantation doses of 5×1014cm-2 (figure 9 (a)), 9×1014cm-2 (figure 9 (b)) and 1.4×1015cm-2 (figure 9 (c)). For the lowest fluorine dose of 5×1014cm-2 the fluorine implanted boron profile width (100nm) at a concentration of 1x1017cm-3 is 8nm wider than that of the unimplanted profile (92nm), perhaps indicating a slight enhancement in boron diffusion. The width of the boron profile of the 9×1014cm-2 fluorine implanted sample (92nm) is exactly the same as that of the unimplanted sample, indicating that the fluorine implant had no effect on the boron thermal diffusion. The width of the boron profile of the 1.4×1015cm-2 fluorine implanted sample (78nm) is 14nm less than that of the unimplanted sample (92nm) indicating that the fluorine has suppressed the boron thermal diffusion. The boron diffusion length into the substrate at a concentration of 1x1017cm-3 of the 1.4×1015cm-2 fluorine implanted sample (10nm) is 9nm less than that of the unimplanted sample (19nm) indicating a 47% reduction in thermal diffusion. The reduction in thermal diffusion in the 2.3×1015cm-2 fluorine implanted sample is 65%, as seen from figure 6 earlier. These results show that a critical fluorine dose between 9×1014cm-2 and 1.4×1015cm-2 is needed before fluorine shows a reduction effect on the thermal diffusion of boron in silicon at 1000°C and that the reduction in thermal diffusion increases as the fluorine dose increases. Figure 10 compares the fluorine SIMS profiles before and after an anneal at 1000°C for fluorine implantation doses of 5×1014cm-2 (figure 10 (a)), 9×1014cm-2 (figure 10 (b)), 1.4×1015cm-2 (figure 10 (c)) and 2.3×1015cm-2 (figure 10 (d)). The corresponding boron profiles are added for reference. For all the implanted doses the as-implanted fluorine profile is approximately gaussian with an implantation range of 0.41µm. For the lowest fluorine implantation dose of 5×1014cm-2, negligible fluorine is present (SIMS background level) in the vicinity of the boron profile after anneal. The majority of the fluorine is located in a broad double peak at a depth corresponding approximately with the range of the fluorine implant (0.41µm). This deep fluorine peak extends from a depth of about 0.3µm to 0.64µm. For a fluorine implantation dose of 9×1014cm-2, negligible fluorine is again visible in the vicinity of the boron profile, but a small shoulder can be seen on the surface side of the deep fluorine peak between about 0.22 and 0.28µm. This shoulder was not present for the lower fluorine dose of 5×1014cm-2 in figure 10 (a). For the highest fluorine dose of 1.4×1015cm-2, an additional shallow, fluorine peak can be clearly seen in the vicinity of the boron marker layer, extending from about 0.07µm to 0.22µm.

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The shape of this shallow fluorine peak is complex and comprises two small ripples at depths of 0.16 and 0.18µm. A substantial shoulder can also be seen at a similar depth as the shoulder seen in figure 10 (b) (≈0.220.28µm). The results in figure 6 show that the high energy F+ implant has not only completely eliminated boron transient enhanced diffusion, but has also given a substantial reduction in the thermal diffusion of boron. The results in figure 9 clearly show that no reduction of boron thermal diffusion is seen at F+ doses of 5×1014 and 9×1014cm-2, whereas significant reduction is seen at a F+ dose of 1.4×1015cm-2. Furthermore, the results in figure 10 show that a shallow fluorine peak is present in the vicinity of the boron marker layer for a F+ dose of 1.4×1015cm-2, but is not present for lower doses. Thus there is a correlation between the appearance of the shallow fluorine peak in the vicinity of the boron marker layer and the reduction of boron thermal diffusion. This reduction of boron thermal diffusion occurs above a critical F+ dose between 9×1014 and 1.4×1015cm-2. The shallow fluorine peak in figure 10 (c) lies at a depth of about 0.070.22µm, which corresponds to 0.17-0.53Rp, where Rp is the range of the fluorine implant. Simulations of vacancy and interstitial profiles after implantation [16] have predicted a vacancy-rich region extending from the surface to a depth approaching the implantation range, Rp, and a deeper interstitial-rich region peaking at a depth just beyond Rp. This indicates that the shallow fluorine peak lies in the vacancy-rich region of the damage profile. The presence of the shallow fluorine peaks in figures 7 and 10 (c) after anneal therefore suggests that fluorine has been trapped at defects created by the fluorine implant. The TEM micrograph in figure 8 shows no evidence of extended defects down to a depth of 0.29µm, and hence the trapping of fluorine at the shallow fluorine peak must be due to defects that are too small to resolve by TEM. There is considerable evidence in the literature for the formation of vacancy-fluorine clusters [17, 18] that are too small to resolve by TEM. Our results are consistent with this work, and hence we propose that the shallow fluorine peak is due to the trapping of fluorine at vacancy-fluorine clusters. The strong correlation between the suppression of boron thermal diffusion and the appearance of the shallow fluorine peak in the vicinity of the boron marker layer at a fluorine implantation dose of 1.4×1015cm-2 provides clear evidence that this peak is responsible for the suppression of boron thermal diffusion. The presence of vacancy-fluorine clusters in the vicinity of the boron marker layer would be expected to give an undersaturation of the local interstitial concentration, since any interstitials in the vicinity would be able to recombine and annihilate with vacancies at or near the vacancy-fluorine clusters. Since boron diffusion in silicon is mediated


85

by interstitials, an under-saturation of the interstitial concentration would give rise to a suppression of the boron thermal diffusion. A comparison of the SIMS profiles in figures 7(a) and (b) with the TEM micrographs in figures 8(a) and (b) respectively, shows that the deep fluorine peak correlates with the band of dislocation loops. The deep fluorine peak extends from about 0.28µm to 0.70µm, which compares with the band of defects in figure 8 extending from about 0.29µm to 0.73µm. Given the location of the deep fluorine peak in the interstitial-rich region of the fluorine damage profile, we suggest that the deep fluorine peak is due to fluorine trapping at interstitial type dislocation loops. Interstitials trapped at these dislocation loops will not backflow to the boron marker layer as in the case of the P+ implant only and hence boron transient enhanced diffusion is suppressed. However, the presence of these dislocation loops in the depletion regions of a transistor could result in leakage which is detrimental for the device performance. Hence, we propose the combination of the two concepts vacancy engineering and fluorine co-implantation in SOI substrates. The aim is to separate the vacancy-fluorine clusters needed to suppress the boron diffusion from the potentially detrimental fluorine induced dislocation loops using the buried oxide layer of the SOI wafers as a barrier between the two regions. This will result in a vacancy-fluorine clusters rich SOI layer maximising dopant diffusion reduction for future ultra shallow junction device applications. 1.0E+20

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4. Fluorine-vacancy engineering in SOI substrates Figure 11 shows boron SIMS profiles of 5keV, 1×1014cm-2 B+ implanted into SOI samples and annealed at 1000°C for 10s in nitrogen. Results are shown for an unimplanted (no F+ implant) sample and a sample implanted with 185keV F+. The boron profiles show that the 185keV F+ implant gives a significant suppression of the boron diffusion. The junction depths measured at a doping concentration of 1×1017cm-3 are 96nm for the F+ implanted sample, compared with 133nm for the unimplanted sample. This indicates that fluorine vacancy engineering is effective in SOI substrates in suppressing boron diffusion.

5. Conclusions A review has been presented of recent progress in vacancy engineering using silicon implantation into SOI wafers and fluorine implantation into both bulk and SOI wafers. The use of a 1MeV silicon implant creates excess vacancies close to the surface, which eliminate excess interstitials created by dopant and other silicon implants. High energy silicon implants into SOI wafers have the additional advantage of the separation of interstitial and vacancy defects by the buried oxide layer. Consequently excess boron diffusion in boron marker layers is eliminated. Results on high energy fluorine implantation into bulk silicon have been shown to completely suppress boron transient enhanced diffusion and also significantly reduce boron thermal diffusion. The boron thermal diffusion suppression has been explained by the creation of vacancyfluorine clusters in the vacancy-rich region of the fluorine damage profile. Fluorine implants into SOI substrates have the additional advantage that the buried oxide layer separates the vacancy-fluorine clusters from deeper lying interstitial dislocation loops. Hence, this technique is very effective in suppressing boron diffusion in SOI substrates. ACKNOWLEDGEMENTS

The authors acknowledge the European Union (SINANO Project) for partially funding this project. Dr. H. A. W. El Mubarek (Royal Academy of Engineering and EPSRC Research Fellow) wishes to thank the Royal Academy of Engineering and the Engineering and Physical Sciences Research Council (EPSRC) for funding her research.


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5. 6.

7. 8. 9. 10.

11. 12. 13.

14.

15.

16.

17. 18.

Advanced Substrate News, No. 5, (2006); http://www.advancedsubstratenews.com Chartered Semiconductor to migrate Xbox 360 CPU to 65nm in 1Q07, (April 21, 2006); http://www.fabtech.org/content/view/1443/74/ Soitec to offer global strain SOI wafers for 45nm node integration (July 18, 2006); http://www.fabtech.org/content/view/1670/74/ A. J. Smith, B. Colombeau, N. Bennett, R. Gwilliam, N. Cowern and B. Sealy, Low Temperature B Activation in SOI using Optimised Vacancy Engineering Implants, in: Mater. Res. Soc. Symp. Proc. (2005), 864, pp. E7.1.1-E7.1.5. E. Roth, O. Holland, V. Venezia and B. Nielsen, J. Elec. Mat. 26 (11) 1349 (1997). V. Venezia, T. Haynes, A. Agarwal, L. Pelaz, H.-J Gossmann, D. Jacobson and D. Eaglesham, Mechanism for the reduction of interstitial supersaturations in MeVimplanted silicon, App. Phys. Lett., 74 (9), 1299-1301 (1999). A. Nejim and B. Sealy, Retarding transient enhanced diffusion of boron in silicon with high energy silicon co-implants, Semicond. Sci. Technol. 18, pp. 839-844 (2003). K. Ohyu, T. Itoga and N. Natsuaki, Advantages of fluorine introduction in boron implanted shallow p+/n junction formation, Jap. J. App. Phys., 29, 457-462, (1990). D.F. Downey, J.W. Chow, E. Ishida, K.S. Jones, Effect of fluorine on the diffusion of boron in ion implanted silicon, App. Phys. Lett.; 73 (9), 1263-1265, (1998). T.S. Shano, R. Kim, T. Hirose, Y. Furuta, H. Tsuji, M. Furuhashi and K. Taniguchi, Realization of ultra-shallow junction: suppressed boron diffusion and activation by optimised fluorine co-implantation, Technical Digest of the International Electron Devices Meeting IEDM (2001), pp. 37.4.1-37.4.4. H.A.W. El Mubarek and P. Ashburn, Reduction of boron thermal diffusion in silicon by high energy fluorine implantation, Appl. Phys. Lett., 83(17), 4134-4136 (2003). K. Liu, J. Wu, J. Chen, A. Jain, Fluorine assisted super-halo for sub-50nm transistors, IEEE Elec. Dev. Lett.; 24, 180-182 (2003). H. Fukutome, Y. Momiyama, H. Nakao, T. Aoyama, H. Arimoto, Fluorine implantation impact in extension region on the electrical performance of sub-50nm PMOSFETS, Technical Digest of the International Electron Devices Meeting (2003), pp. 20.2.120.2.4. M. N. Kham, H. A. W. El Mubarek, J. M. Bonar, P. Ashburn, P. Ward, L. Fiore, R. Petralia, C. Alemanni and A. Missina, 110-GHz f T Silicon Bipolar Transistors Implemented using Fluorine Implantation for Boron Diffusion Suppression, IEEE Trans. Elec. Dev., 53(3), 545-552 (2006). H. A. W. El Mubarek, M. Karunaratne, J. M. Bonar, G. D. Dilliway, Y. Wang R. Price, J. Zhang, P. L. F. Hemment, A. F. Willoughby, P. Ward, P. Ashburn, Effect of fluorine implantation dose on boron thermal diffusion in silicon, J. Appl. Phys., 96(8), 41144121 (2004). A. Peeva, R. Kögler, W. Skorupa, J. S. Christensen, and A. Yu. Kuznetsov, Spatial distribution of cavities in silicon formed by ion implantation generated excess vacancies, J. Appl. Phys., 95(9), 4738-4741 (2004). X. D. Pi, C. P. Burrows and P. G. Coleman, Fluorine in silicon: diffusion, trapping and precipitation, Phys. Rev. Lett., 90(15), 155901-1 – 155901-4 (2003). R. R. Robinson, M. E. Law, Fluorine diffusion: models and experiments, Technical Digest International Electron Devices Meeting (2002), pp. 883-886.

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SUSPENDED SILICON-ON-INSULATOR NANOWIRES FOR THE FABRICATION OF QUADRUPLE GATE MOSFETS VIKRAM PASSI1*, BENOIT OLBRECHTS1, JEAN-PIERRE RASKIN1, JENS BOLTEN2, THOMAS MOLLENHAUER2, THORSTEN WAHLBRINK2, MAX C. LEMME 2, HEINRICH KURZ 2 1 Université catholique de Louvain, Microwave Laboratory, Maxwell building, Place du Levant, 3, B–1348 Louvain-la-Neuve, Belgium 2 Advanced Microelectronic Center Aachen, AMO GmbH, Otto-Blumenthal strasse 25, 52074 Aachen, Germany * Vikram Passi, Microwave Laboratory, Université catholique de Louvain, Maxwell building, Place du Levant, 3, B–1348, Louvain-la-Neuve, Belgium. E-mail: [email protected]

Abstract. Scaling of MOSFET physical dimensions is approaching the nanoscale regime, which causes increase of short-channel effects such that the electrical performance of classical MOSFET structure is becoming seriously degraded. The limits of silicon scaling have been the major challenge for technologists for the past years. With the 90 nm generation in production and despite many roadblocks, the latest International Roadmap for Semiconductors 2005 expects that CMOS can be scaled down to 16 nm, by introducing new transistor architectures and materials. In this paper, we propose fabrication of a non-classical device architecture namely the “Quadruple-Gate MOSFET” which is based on definition of narrow, suspended silicon fins defined by electron-beam lithography into the topsilicon film of a Silicon-on-Insulator (SOI) wafer.

Keywords: Electron-beam lithography, Quadruple-Gate, Silicon-on-Insulator

1. Introduction After over thirty years of downscaling for increased packing density and speed of operation, CMOS technology has survived the hardships and continues to lead technology in today’s era of Very Large Scaling Integration (VLSI). The limits of silicon scaling are the major challenge that 89 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 89-94. © 2007 Springer.

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technologists are facing today. The International Roadmap for Semiconductors (ITRS) predicts that MOS transistors in the year 2020 will have printed gate lengths of 9 nm1. Traditionally, the control of short-channel effects in bulk devices has been achieved with the use of thin gate dielectrics, reduced junction depths and channel engineering. All these parameters are approaching their physical limits, which will render further scaling of device dimensions difficult. The need arises therefore for new device architectures such as multiple-gate MOS (Double-Gate, FinFET, Pi-Gate and Gate-AllAround/Quadruple-Gate) and materials (high-k dielectrics and metal gates) along with the transition from bulk-silicon to SOI MOSFET. By such means it is hoped that Moore’s law can be continued. In this paper, we propose a fabrication method for a Quadruple-Gate MOSFET based on suspended silicon fins defined by electron beam (E-beam) lithography into the top-silicon film of an SOI wafer. Critical steps in the fabrication process are discussed. 2. Device fabrication A three-dimensional structure of suspended SOI nanowires which are the starting material for the fabrication of Quadruple-gate device is shown in Fig. 1a. Figure 1b shows the desired cross section of the suspended nanowires surrounded by silicon dioxide and a polysilicon gate. The complete process steps for the fabrication of quadruple-gate MOSFET are illustrated in Fig. 2 (a - l).

Figure 1. (a) 3-D structure of suspended SOI nanowires; starting structure for the fabrication of Quadruple-Gate device, (b) Cross section of silicon fins surrounded by the gate oxide and material gate


91

The starting SOI wafer is composed of a top-silicon layer of 145 nm, buried-oxide (BOX) of 400 nm and a silicon-bulk substrate of 800µm (Fig. 2a). The first step begins with the thinning of the top-silicon layer from 145 nm down to 50 nm using a pre-heated bath (75°C) containing a mixture of ammonium-hydroxide (20 ml), hydrogen-peroxide (160 ml), and water (1280 ml). After six thinning and cleaning steps the desired topsilicon thickness of 50 nm was achieved all over the wafer (Fig. 2b), as confirmed by ellipsometer measurement. After standard cleaning, the thinned wafer is spin-coated with hydrogen-silsesquioxane (HSQ) (Fig. 2c), a negative tone E-beam resist, and E-beam lithography is performed. After exposure and development of HSQ the structure looks like as presented in Fig. 2d. After the development of the unexposed resist, the top-silicon and buried-oxide are etched using HSQ as a mask (Fig. 2e and 2f ). The topsilicon layer is etched using HBr chemistry in a two-step process followed by partial buried-oxide (100 nm) etching using C4F82,3. Ellipsometry measurements were performed to confirm the thickness of the remaining buried-oxide which was measured to be TBOX = 298 nm.

Figure 2. Process flow for fabrication of Quadruple-Gate device

92


The remaining BOX layer underneath the silicon fins is removed by a HF-5% dip for 30s. Silicon fins over the remaining BOX are completely suspended (Fig. 2g). Gate-oxidation and polysilicon deposition are then done followed by implantation of source/drain, deposition of passivation layer, definition of contacts and finally the metallization of contacts which are common CMOS process steps (Fig. 2h – 2k). Figure 2l shows the final device fabricated after the above mentioned steps. 3. Critical fabrication steps The critical steps in the fabrication process are: •

Silicon fins definition

•

Release of nanowires (fins)

•

Conformal deposition of polysilicon (future metal gates) around fins

•

Alignment of gates

3.1. SILICON FIN DEFINITION AND ETCHING

Tests were made on small samples to determine the dose of exposure (pads dose = 2700 µC/cm², fins dose = 2100µC/cm²), and definition of silicon fins with the desired widths and spacing between them. Silicon fins of 50 nm width and a spacing of 300 nm and 500 nm were defined. Figures 3a and 3b show silicon fins of 50 nm width (Wfin) and spacing (Sfin) of 300 nm and 500 nm, respectively. 3.2. RELEASE OF SILICON FINS

After the removal of the oxide between the fins using RIE etching, the remaining oxide under the fins has to be removed using wet etching. This

Figure 3. Nanowires with desired fin width and spacing


93

was done by placing the samples in HF-5% for 30s. The fins were completely suspended over the remaining buried-oxide. There is an overetch (the lighter area in Fig. 4a) of almost half the fin width, which is not significant in long channel devices, but for deep submicron devices, this etch can result in poor device performance. This problem can be avoided by the use of implantation and highly selective etching of implanted oxide4. Figures 4a and 4b show the damaged silicon fins due to Nitrogen blow drying, and undamaged fins, dried using a critical point drying machine, respectively. 3.3. CONFORMAL DEPOSITION OF POLYSILICON AROUND FINS

Filling of buried cavities by polysilicon for building planar double gate devices was already demonstrated in5, as shown in Fig. 5a. In Fig. 5b, we can see the polysilicon deposited over the oxidized silicon fins.

Figure 4. Suspended nanowires over remaining BOX

Figure 5. Conformal deposition of polysilicon around oxidized fins

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3.4. ALIGNMENT OF GATES

Misalignment occurs when multiple lithographic steps are performed to define the gate. This can be avoided with the use of implantation to tune the oxide etch rate. The use of vapour HF (VHF) to selectively etch implanted oxide combined with damascene gate definition could avoid misalignment problems that occur from lithography4. 4. Conclusion In the race to follow Moore’s law, a novel fabrication process for a multiple gate device is proposed. The device is a quadruple gate MOSFET and critical steps of fabrication are discussed. Pictures showing the process steps performed so far are presented. Critical point drying was used to carefully release the silicon fins without damage. An improvement in the process by avoiding etching under the source and drain pads is proposed. The use of multiple gate architectures along with high-k dielectric and/or metal gates can extend the lifetime of silicon CMOS in the coming years. ACKNOWLEDGEMENTS

The authors would like to acknowledge the European Network of Excellence SINANO for funding and the cleanroom staff at UCL for their support. References 1. 2.

3.

4. 5.

International Roadmap for Semiconductors. M. C. Lemme, T. Mollenhauer, W. Henschel, T. Wahlbrink, M. Baus, O. Winkler, B. Spangenberg, H. Kurz, “Subthreshold Behavior of Triple-Gate MOSFETs on SOI Material”, Solid State Electronics, 48(4), 529-534 (2004). M. C. Lemme, T. Mollenhauer, H. Gottlob, J. Efavi, C. Welch, H. Kurz, “Highly Selective HBr Etch Process for Fabrication of Triple-Gate Nano-Scale SOI MOSFETs”, Proceedings of Microelectronics Engineering, 72-73, 346-350 (2004). R. Charavel, J.-P. Raskin, “Etch Rate Modification of SiO2 by Ion Damage”, Electrochemical and Solid State Letters, 9, G245-248 (2006). T. M. Chung, B. Olbrechts, J.-P. Raskin, D. Flandre, Planar Double-Gate SOI MOS Devices: Fabrication by Wafer Bonding over Pre-Patterned Cavities and Electrical Characterization, in Proceedings of EUROSOI (2006), pp. 111-112.

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Physics of Novel Nanoscaled SemOI Devices

INTEGRATION OF SILICON SINGLE-ELECTRON TRANSISTORS OPERATING AT ROOM TEMPERATURE TOSHIRO HIRAMOTO* Institute of Industrial Science, University of Tokyo, Japan Collaborative Institute for Nano Quantum Information Electronics, University of Tokyo, Japan * To whom correspondence should be addressed. Toshiro Hiramoto, Institute of Industrial Science and Collaborative Institute for Nano Quantum Information Electronics, University of Tokyo, 4-6-1, Meguro-ku, Tokyo 153-8505, Japan; Email: [email protected]

Abstract. Recent research and development of silicon single-electron transistors are reviewed. The fabrication process of extremely small silicon dot in the channel of MOS transistors has been advanced, and the dot size is now as small as 2 nm. Consequently, the single-electron transistors operate at room temperature and the peak-to-valley current ratio of the Coulomb blockade oscillations reaches as high as 480 at room temperature. The attempts to integrate the single-electron transistors and to develop new circuit applications are also described.

Keywords: Coulomb blockade, quantum effect, quantum dot, single electron, resonant tunneling, CMOS, MOSFET, nano device

1. Introduction The metal-oxide-semiconductor field-effect transistors (MOSFET) that compose very large scale integrated circuits (VLSI) have been miniaturized to achieve higher integration, higher performance, lower power consumption, and lower cost for more than 35 years. The size of the state-of-the-art MOSFETs in mass production has reached less than 35 nm, and the MOSFETs will be further scaled down for even more performance of VLSI. Therefore, silicon MOSFETs are now in the nanometer regime. Although the VLSI technology has been generally called “microelectronics”, it should be called “nanoelectronics”. However, it is generally recognized that simple scaling of MOSFETs does not work in the nanometer regime. To enhance the performance of 97 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 97-112. © 2007 Springer.

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VLSI, new transistor structures and new materials for nanoscale MOSFETs have been widely studied and developed. These are the grand challenges in the development of silicon nanodevices. On the other hand, when the transistor size is in the nanometer regime, a lot of new physical phenomena, such as quantum effects and single-electron charging effects, are emerging. Some of these phenomena will have a unique feature in current-voltage characteristics that conventional MOSFETs do not have, and they appear even at room temperature when the transistor size is extremely small. When these physical phenomena are incorporated in VLSI, they offer the great potential to add new functionalities to future VLSI. One of the most promising new devices based on new nanoscale physics is the single-electron transistor (SET)1-2. A SET has an extremely small quantum dot in the channel. The number of electrons in the dot is precisely controlled by the Coulomb blockade, and a SET shows unique oscillatory I-V characteristics that are expected to have new functionalities. SETs have been studied using various materials, including metals,3-4 GaAs,5 carbon nanotube (CNT)6, and silicon7-8. Among them, silicon SETs are most attractive for future VLSI applications, because nearly all state-ofthe-art VLSI processes can be utilized to fabricate silicon SETs and silicon SETs may be easily integrated into conventional CMOS circuits.9 In this chapter, recent developments of silicon SETs are reviewed. Firstly, silicon nanodevices are classified in three categories and the position of SETs in these categories is discussed. Then, the development of the characteristics of silicon SETs is described. Special emphasis will be placed on the room temperature operation and the integration of SETs. 2. Position of SET in nanodevice categories 2.1. THREE CATEGORIES OF NANODEVICES

There are numerous types of nanodevices that have been actively studied. Figure 1 shows examples of nanodevices and their classifications. The horizontal axis is the approximate time when each nanodevice will be practically realized. Note that this figure illustrates the nanodevices in future VLSI for information processing applications; memory devices and interconnect technologies are not included.

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99

Figure 1. Examples of nanodevices and their classifications. The horizontal axis shows approximate time when each nanodevices is practically realized.

2.1.1. CMOS extension In the near future, complementary MOS (CMOS) transistors will be certainly dominant in VLSI. New transistor structures, such as fully depleted (FD) silicon-on-insulator (SOI) MOSFETs and three-dimensional structures, and new materials, such as high-k/metal gate technology and Ge channel, are the promising technologies. Suppression of characteristic variations and obtaining high yield are also important technical issues. These CMOS devices are fabricated by so-called “top-down” process (see (a) CMOS in Figure 1). Next, some devices fabricated by so-called “bottom-up process” such as self-assembly technology will emerge. CNT FETs10 and silicon nanowire FETs11 are included (see (b) bottom-up FET in Figure 1). In the author’s opinion, these devices are “CMOS-based”, because if these devices are realized, the circuit scheme that will be utilized may be that of conventional CMOS. These devices, that may be smaller than the lithography limit, will extend the life of the CMOS platform technology. A small step between (a) and (b) in Figure 1 shows a technological paradigm shift in the fabrication process from top-down fabrication to bottom-up fabrication. These two types of nanodevices, (a) CMOS and (b) bottom-up FET, are classified into the “CMOS Extension” category.

100 INTEGRATION OF SILICON SINGLE-ELECTRON TRANSISTORS

2.1.2. Beyond CMOS In time, new devices that are not CMOS-based, such as a resonant tunnel device (RTD) and a SET, will appear. They utilize “charges” as the state variables, but the circuit scheme and device operation principles are not CMOS ((c) charge-based devices in Figure 1). After these devices, even newer devices that utilize the state variables other than charges will emerge, such as the spin transistor12 ((d) non-charge devices in Figure 1). These two types, (c) and (d), are classified into “Beyond CMOS”. There is a huge technological gap between CMOS Extension and Beyond CMOS. There is also a huge gap between (c) charge-based devices and (d) non-charge devices. 2.1.3. New functions added to CMOS There is one more category in nanodevices. This is “New Functions added to CMOS”, where non-CMOS devices, such as MEMS, sensors, and bio devices, are integrated into a CMOS chip and new functionalities that cannot be attained by CMOS is added to the CMOS technology. The technology is mainly CMOS-based, but the non-CMOS technologies are merged into CMOS. This combination has huge potential to enhance the overall performance of CMOS-based systems, and this kind of technological approach is very different from the “Beyond CMOS” approach. 2.2. POSITION OF SET

A SET is a charge-based device, but is not CMOS-based. Therefore, a SET is classified in Beyond CMOS and also in (c) charge-based device, as shown in Figure 1. Many proposals of single-electron circuits, which are exclusively composed of SETs, have been made so far13. However, as pointed out in the previous subsection, there is a large technological gap between CMOS Extension and Beyond CMOS, and the single-electron circuits will not be realized in the near future as long as a SET is utilized as a beyond-CMOS device. To make the SET a more practical device, we should take the “New Functions Added to CMOS” approach. A SET has very unique I-V characteristics that are not achieved in conventional CMOS. When SETs are integrated in a CMOS chip, new functionality can be added to the CMOS technology. An example of the “New Functions Added to CMOS” approach of a SET is described in Section 5.

INTEGRATION OF SILICON SINGLE-ELECTRON TRANSISTORS 101

3. Structure and fabrication of silicon SETs 3.1. OPERATION PRINCIPLE OF SET

Figure 2 shows schematics of a SET. The structure of a SET is very similar to that of a FET. A SET has source, drain, and gate electrodes. The only difference between a SET and a FET is the existence of a quantum dot between source and drain in a SET as shown in Figure 2(a). The quantum dot is connected to source and drain via tunnel barriers. The potential of the dot is controlled by the gate voltage. Electrons flow from source to drain via a quantum dot, by tunneling. The equivalent circuit of a SET is shown in Figure 2(b). When one electron is injected from the source to the dot, the potential of the dot is raised by the electron charge. When the potential increase of the dot is larger than the thermal energy, the second electron cannot tunnel to the dot because of the potential barrier and the current does not flow. This is the Coulomb blockade. When the dot potential is raised by the gate, the second electron can tunnel to the dot and the current flows, but when the potential is raised by the gate further, then the third electron is forbidden to tunnel and the current stops again. Consequently, the current oscillates periodically as a function of the gate voltage as shown in Figure 2(c). This is referred to as the Coulomb blockade oscillations. The potential increase of the dot by one electron is called the charging energy and is given by e2/Ctotal, where e is the electron charge and Ctotal is the total capacitance of the dot. In order for the Coulomb blockade to appear at room temperature, the charging energy should be larger than the Gate Cg

Source

e

Drain

Cd

Cs

Cs Dot Cd

Id

Cg

Vg

(a)

Dot = /

Csub Vds

Vsub Vg (c)

(b)

Figure 2. (a) A schematic of the structure of a SET. (b) An equivalent circuit of a SET. (c) A schematic of I-V characteristics of a SET.


thermal energy at room temperature (26 meV). A simple calculation shows that the dot size should be smaller than roughly 10 nm to observe the Coulomb blockade oscillations at room temperature. Note that the Coulomb blockade is a classical phenomenon. When the dot size is very small and the quantum effect appears, the characteristics of the Coulomb blockade oscillations will be changed. 3.2. FABRICATION OF THE SILICON SET

Figure 3(a) shows a schematic structure of SETs we have fabricated.14 The transistors are fabricated on a silicon-on-insulator (SOI) substrate and are in the form of a point-contact MOSFET15, where a part of the channel is extremely narrow. The silicon quantum dot is self-formed in the very narrow channel, and therefore, the transistor acts as a SET16. Some of the single-electron transistors are in the form of an ultra-narrow wire MOSFET, as shown in Fig. 1(b), where multiple quantum dots are formed in the channel. The most small quantum dot dominates the electrical characteristics and most of the transistors operate as SETs.17 Moreover, some of the transistors are p-type MOSFETs, and therefore, these transistors act as single-hole transistors (SHT). The point-contact silicon channel and extremely narrow silicon nanowire channels were fabricated by electron-beam (EB) lithography and reactive ion etching on SOI substrates. The silicon channels were further narrowed by SC1 (NH4OH/H2O2/H2O2) wet etching. Thin thermal oxide was grown and chemical vapor deposition (CVD) oxide was deposited for the gate oxide. The total gate oxide thickness is approximately 20 nm. The rest of the fabriccation process was completed by single-layer polycrystalline-silicon gate electrode deposition, gate etching, BF2+ ion implantation into the gate and source/drain regions, dopant activation annealing, passivation oxide deposition, and the formation of contact holes and an Al electrode.

Figure 3. Structures of silicon SETs. (a) A SET in the form of a point contact MOSFET. (b) A SET in the form of ultra-narrow wire MOSFETs.


4. Room temperature operation of SETs/SHTs 4.1. EVOLUTION OF COULOMB BLOCKADE OSCILLATIONS

Figure 4 shows the current-gate voltage characteristics of a SET15 at a very early stage of the SET research in our group (in 1997). The Coulomb blockade oscillations are clearly observed at low temperatures below 77 K. When the temperature increases, the oscillations become broad and finally the oscillations are almost smeared out at room temperature. The values of capacitances in Figure 2(b) can be derived from the contour plot of the current as functions of drain voltage and gate voltage (not shown). Dot diameter and charging energy are estimated using these values to be approximately 6 nm and 90 meV, respectively. It is found that the dot size of 6 nm is not small enough to observe the large Coulomb blockade oscillations at room temperature. The size of the quantum dot should be further reduced by the improvement of the fabrication technology. The oscillations in Figure 4 are not periodic. According to the classical Coulomb blockade theory, periodic oscillations are expected. It has been found that the aperiodic oscillations are due to the dot size being too small, where the quantum level spacing in the dot is comparable to the charging 2.0 Dot size = 6 nm Ec = 90 meV

300 K

Id (nA)

1.5

240 K 1.0

160 K Vds = 1.0 mV Vsub = 0 V

0.5

77 K 21 K 15 K

0 0

1

2

3

4 5 Vg (V)

6

7

8

Figure 4. Measured current-gate voltage characteristics of a SET fabricated in 1997. The clear Coulomb blockade oscillations at low temperatures are almost smeared out at room temperature.


Id [pA]

150

100

150K 240K 300K

50

PVCR ~ 2 Ec ~ 250 meV Dot size ~ 4 nm

0

1

2

3

4

5

V [V] g

Figure 5. Measured current-gate voltage characteristics of a SET fabricated in 2000. The clear Coulomb blockade oscillations are observed at room temperatures. The PVCR at room temperature is 2.

energy.15 This fact indicates that a quantum dot in a SET that shows large Coulomb blockade oscillations at room temperature also shows the quantum effects. The examples of the quantum effects will be described later. Figure 5 shows the current-gate voltage characteristics of a SET18 fabricated in 2000. Larger oscillations are clearly observed at room temperature. The ideality of the oscillations is generally characterized by the peak-to-valley current ratio (PVCR). The PVCR of the oscillations in Figure 5 at room temperature is approximately 2, which is not enough for the practical applications. The estimate quantum dot diameter and the charging energy is 4 nm and 250 meV, respectively. The dot size of 4 nm is still too small to observe the large Coulomb blockade oscillations at room temperature. Great efforts have been made to further reduce the quantum dot size. One technique to make the dot size small is the removal of the buried oxide (BOX) layer of the SOI substrate just under the silicon nanowire channel by HF before SC1 etching.19 As a result, the wet etching of the nanowire channel by SC1 proceeds from both the top and the bottom, and the channel thickness and width are effectively reduced. Moreover, we fabricated SHTs,


instead of SETs, because we found that larger oscillations can be obtained in a hole system than in an electron system.20 Figure 6 shows the current-gate voltage characteristics at room temperature of a SHT19 fabricated in 2003. PVCR reaches as high as 40. The estimated dot size is as small as 2 nm. From the smooth curve shape of the oscillations, it is estimated that the number of the dominant dots in the channel is unity. In the multiple-dot system in which the curve has some shoulders or multiple peaks, we observed a PVCR of 1280.21 4.2. MECHANISM OF DOT FORMATION

In our SETs and SHT, the quantum dots are self-formed in the ultra-narrow channel. It is considered that the silicon narrow channel is not separated but the silicon channel is continuous. Figure 7 shows a schematic of the band structure of the ultra-narrow channel.20 The two tunnel barriers may be formed by expansion of the band gap due to the quantum confinement effect, and the quantum dot may be formed by the band gap shrinkage due to the compressive strain during thermal oxidation.22 The local channel width fluctuations may also be responsible for the dot formation.16,20 The exact origin of the dot formation mechanisms is not clear at present.

Drain Voltage : -1 mV PVCR ~ 40 Dot size ~ 2nm

10-10 10-11

0.3 0.2

10-12 0.1

10-13 10-14

|Drain Current (nA)|

10-9

0.4 | Drain Current (nA) |

| Drain Current (A) |

10-8

0 0

-1

-2 -3 -4 -5 Gate Voltage (V)

-6

Figure 6. Measured current-gate voltage characteristics of a SHT fabricated in 2003 at room temperature. The PVCR is 40. Note that left vertical axis is in the logarithmic scale and the right vertical axis is in the linear scale. The two curves are identical data.


Tunneling barriers

Bottom of econduction band

Top of valence band

Dot

h+

Tunneling barriers Figure 7. A schematic of the band structure of a quantum dot in the narrow channel. The band gap expands by the quantum confinement and the gap shrinks due to the compressive strain by the thermal oxidation.

4.3. LARGEST COULOMB BLOCKADE OSCILLATIONS AND NDC

Figure 8 shows the current-gate voltage characteristics at room temperature of a SHT23 fabricated in 2005. The PVCR of the Coulomb blockade oscillations is as high as 395. Since the dot is extremely small, the quantum level spacing in the dot is not negligible and some quantum effects appear even at room temperature, as mentioned above. One of the examples is the negative differential conductance (NDC). Figure 9 shows the current-drain voltage characteristics of the SHT.23 Note that the horizontal axis is not the gate voltage but the drain voltage. When the drain voltage increases at the gate voltage of -0.4V, the current increases but starts to decrease soon. This decrease in the current is NDC. The observed NDC is attributable to resonant tunneling through one quantum level in the extremely small quantum dot.19 The PVCR of NDC is as large as 106 at room temperature. It is clearly shown in Figure 9 that the amplitude of NDC is controlled by the gate voltage. More recently, we have intensively investigated the charge polarity dependence and nanowire direction dependence of the Coulomb blockade oscillations and NDC.24 It has been found that the [100]-directed SHT is the best to obtain a large PVCR. Actually, the fabricated SHT in the [100] direction shows PVCR of 480 in the Coulomb blockade oscillations and


PVCR of 300 in NDC,24 both of which are the highest ever reported at room temperature.

20

PVCR 395 -11

10

| IDS | (A)

| IDS | (pA)

15

Room Temp. VDS = -1mV

-12

10

10

5

10

-13

0 0.0

-14

-0.4

10 -1.2

-0.8

VGS (V)

Figure 8. Measured current-gate voltage characteristics of a SHT fabricated in 2005 at room temperature. The PVCR is 395.

VGS

Room Temp.

IDS (nA)

1.5 PVCR = 106

-0.2 V -0.4 V -0.6 V -0.8 V

1.0 0.5 0.0 0.0

0.2

0.4

0.6

VDS (V) Figure 9. Measured current-drain voltage characteristics of the SHT. The PVCR of NDC is 106.


5. Integration and circuit application of SETs 5.1. DIGITAL CIRCUIT APPLICATION

Great efforts have also been made to integrate room-temperature operating SETs and SHTs. A directional current switch has been formed by two integrated SHTs that show the Coulomb blockade oscillations at room temperature21 (not shown). This was the first integration of the roomtemperature operating SETs/SHTs, and the operation of directional current switch has been successfully demonstrated. Although some digital applications of SETs/SHTs have also been successfully demonstrated at room temperature14, it is known that digital circuits that are composed of SETs/SHTs have problems such as small gain, small drive current, and high bit error rates. Although the problem of the small gain has been partly solved recently25, the highest gain of a SET/SHT obtained at room temperature is 5.2,23 which is too small for practical digital applications. 5.2. ANALOG CIRCUIT APPLICATION

One of the best applications of SETs/SHTs is an analog circuit application. An example is the analog pattern matching application. The bell-shaped current-gate voltage characteristics can be utilized for analog pattern matching circuits.26 The Coulomb blockade oscillations have certainly the bell-shaped current-gate voltage characteristics, so we have applied them to the analog pattern matching.27 Figure 10 shows the operation principle of analog pattern matching.27 A device that exhibits the bell-shaped current-gate voltage characteristics is utilized. The gate voltage of the oscillation peak, a1 corresponds to a stored datum and is changed by programming. When input voltage, x1 is provided to the gate, input x1 and stored a1 are compared. When x1 and a1 are close, the output current is high because of the bell-shaped characteristics. On the other hand, if x1 and a1 are far away, the output current is very small. Therefore, the output current shows the similarity between input x1 and stored a1. SHTs are utilized as devices that have the bell-shaped current-gate voltage characteristics. Moreover, each SHT has silicon nanocrystals embedded in the gate oxide. When the pulse voltage is applied to the gate, charges are injected to the nanocrystals and the device acts as a non-volatile memory.28 Therefore, the peak position of the Coulomb blockade oscillations can be controlled by programming,28 and stored datum a1 can be easily changed.


Active range 0% 100%

Id

Data are stored by the peak shift

Vg

a1 x1

Figure 10. A schematic to show the principle of analog pattern matching. The output current represents the similarity between stored data a1 and the input x1.

Three SHTs that operate at room temperature are successfully integrated,27 as shown in Figure 11. The three SHTs correspond to three elements of a vector. For simplicity, the three elements are fitted to the three basic elements of colors (RGB) in this example, and color “orange” is stored by programming. The characteristics in Figure 11 are the curves after the programming. Then, various other colors are input. The results are shown in Figure 12. The largest output current is clearly obtained when the input is “orange”, indicating that “orange” is successfully read out.27 -20 0 % Active 100 % Range

Drain Current (pA)

Room Temp.

-15

Drain Voltage : -1 mV

-0.4V -0.6V -0.8V

B-SHT

-10

G-SHT R-SHT with a series MOS

-5

0 0.5

0

-0.5

-1

-1.5

Gate Voltage (V) Figure 11. Measured current-gate voltage characteristics of three integated SHTs operating at room temperature.


Figure 12. Measured output current at room temperature. The output is the sum of drain current in three SHTs. When the input is orange, the highest output current is obtained.

In this application, the matching is performed by the SHTs and other calculations are done by conventional CMOS circuits. Therefore, this new circuit scheme that utilizes SETs/SHTs and adds new function to CMOS is the “New Functions Added to CMOS” approach in Figure 1. Please note that the output of this analog pattern matching circuit is not deterministic.26 The output current represents the “similarity” between the stored data and the input data. Therefore, some errors are allowed in the circuits. The SETs/SHTs are suitable for this kind of applications. 6. Conclusion Recent developments of room temperature operating silicon SETs and SHTs are reviewed. The PVCR of the Coulomb blockade oscillations is as high as 480 and the PVCR of NDC is as high as 300 at room temperature. It is shown that “New Functions Added to CMOS” approach is very effective, and the analog pattern matching application is successfully demonstrated using integrated SHTs. SETs/SHTs are promising devices for future VLSI and add new functions to conventional CMOS circuit systems.

INTEGRATION OF SILICON SINGLE-ELECTRON TRANSISTORS 111 ACKNOWLEDGMENTS

The author would like to thank Prof. H. Ishikuro, Dr. M. Saitoh, Mr. K. Miyaji, and Mr. M. Kobayashi for performing experiments. This work was partly supported by Grant-in-Aid for COE (Center of Excellence) Research, the IT program, and Special Coordination Funds for Promoting Science and Technology from the Ministry of Education, Culture, Sports, Science and Technology, Japan.

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SiGe NANODOTS IN ELECTRO-OPTICAL SOI DEVICES A.V. DVURECHENSKII*, A.I. YAKIMOV, N.P. STEPINA, V.V. KIRIENKO, P.L. NOVIKOV Institute of Semiconductor Physics, Siberian Branch of Russian Academy of Science, Novosibirsk ∗ Anatoly V. Dvurechenskii. Institute of Semiconductor Physics, Siberian Branch of Russian Academy of Science, Lavrentiev Prospect13, 630090 Novosibirsk, Russia.

Abstract. The electronic and optical phenomena, as well as possible device-oriented application in Ge/Si and Ge/SiO2 nanodots that have been synthesized by molecular-beam growth are the scope of this article. We focus on the fundamental aspects and device applications of the small size dots whose electronic states resemble those of an atom even at room temperature.

Keywords: quantum dots, germanium, silicon, field effect transistor, infrared photo detector, memory device.

1. Introduction A new branch of semiconductor physics that studies the behavior of electrons confined in precisely tailored potential emerged during the last 20 years. This field has developed from the progress in technology that now allows for the routine fabrication of nanometer-scale solid state structures that contain small numbers of conduction electrons (3 mm and Ub >3 V. p+ Si bottom contact

Sio2

Al contacts n+Si top contact Ge dots Si

Figure 6. Schematic layout of waveguide near-infrared photodetector on a silicon-oninsulator substrate.

Figure 7. Quantum efficiency of a 4 mm waveguide photodetector as a function of reverse bias.

SiGe NANODOTS IN ELECTRO-OPTICAL SOI DEVICES

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To the best of our knowledge, the first observation of mid-infrared photoconductivity in Ge QDs has been reported in 199915. The QDIP under investigation was a p+–p–n+ silicon diode embedded with a single layer of pyramidal Ge SAQDs. The average size of the dot base length is 15 nm, the height is 1.5 nm. As the heterostructure was growth at low temperature (Ge layer was grown at 300 C and covered with Si at 500 C), the segregation and inter-diffusion effects are negligible and the Ge islands contain no silicon atoms. The large areal density of Ge QDs (3×1011 cm-3) was responsible for the high absorption coefficient. 4. Ge nanodots on SiO2 for non-volatile memory devices A nanocrystal in a dielectric matrix has attracted much attention as a promising candidate for a charging node in a single-electron memory device (SEMD). An advantage of the nano-floating gate memory over the continuous floating gate is its improved endurance due to the prevention of lateral charge movement. Faster writing/erasing time, lower operating voltage and longer retention time have been demonstrated in a memory device based on Si islands embedded in SiO219. Recently it was shown that a Ge-based SEMD has superior properties over Si-based SEMD in terms of the writing /erasing time and the operating voltage. Since then, different methods were used for fabrication of Ge nanodots in a dielectric matrix, such as ion beam synthesis20, oxidation and reduction of Ge/Si islands21, rapid thermal annealing of co-sputtered22 and chemical-vapor-deposition layers, and pulsed-laser deposition23. However practically all of these techniques create the random distribution of nanodots inside the dielectric, that yields the ensemble-averaged information only. To suppress the tunneling distance fluctuation and allow carrying out the detail analysis of tunneling-out mechanism it is necessary to form in-plane distribution of nanodots. Moreover, when used nanodots for charge storage devices, the general requirements that can be placed upon the control are the size of nanodots, theirs density and homogeneity in growth plane, that is the problem for most of above-mentioned growth methods. In other work24 pulsed low-energy (100-200 eV) ion-beam-induced nucleation was found to stimulate Ge nanocrystal formation on relatively thick films of SiO2 (about 100 nm) prepared by thermal oxidation of Si. It was shown that the ion-beam action causes an increase in nanocrystal density and size homogeneity. The idea of using the ion-beam action is that each ion impact into the SiO2 surface (a) produces a vacancy depression with surface steps being nucleation sites for nanocrystal growth; (b) generates adatoms assisting in nuclei growth; c) stimulates surface adatom diffusion. Ion energy should be low enough to avoid introduction of defects

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into the SiO2 film, but high enough in comparison to the thermal energy of deposited atoms. The regime of pulsed ion-beam irradiation allows synchronous nucleation of new phases, favorable for highly homogeneous nanocrystal size distributions. The pulsed low-energy (200 eV) ion-beam-induced nucleation during Ge deposition on SiO2 was used to study the formation of Ge nanocrystals arrays on thin films of dielectric which are usually tunnel layers in memory devices. A 4.5 nm thick SiO2 film tunnel insulator was grown by thermal oxidation on (111) p-type silicon substrates at 850o C. After dioxide formation, the wafers were washed, dried and inserted into the ultrahighvacuum (UHV) chamber. About a 1 nm-thick SiO2 layer was removed from the top surface in-situ using a Si flux at 820o C, before Ge deposition. Molecular beam deposition (MBD) of Ge was carried out in an UHV chamber of a molecular beam epitaxy set-up equipped with a boron nitride crucible effusion cell. The system of ionization and acceleration of Ge+ ions provided a degree of ionization of the Ge molecular beam from 0.1% to 0.5%. A pulse accelerating voltage supply unit generated ion-current pulses with duration of 0.5-1 s and ion energy of 200 eV. The angle of incidence of the molecular and ion beams on the substrate was 54o out of the surface normal. The analytical assembly of the chamber included a reflection high energy (20 keV) electron diffraction (RHEED) unit. The substrate temperature of Ge deposition was varied from 250 to 400o C. In all experiments, the nominal Ge layer thickness was targetted as 20 monolayers (ML). The rate of Ge deposition was varied between 0.08 - 0.19 ML/s. Two different regimes of ion stimulation were studied. In the first case (regime 1) three ML of Ge were deposited without ion-beam action. Pulsed ionbeam actions were applied in series at the effective Ge layer thickness of 3 ML, 4 ML and 5 ML. In the second case, ion implantation was commenced simultaneously with Ge deposition in series, at the effective thickness of 1ML, 2 ML and 3ML (regime 2). Ge nanocrystal density and size distribution were studied with high resolution electron microscopy (HREM), both plan-view and cross-sectional geometries. To prevent Ge oxidation, some samples were capped by a thin Si layer (~5 nm) in the same UHV chamber. The chemical composition of the uncapped samples and tunnel insulator thickness variation were studied with the Electron Spectroscopy for Chemical Analysis (ESCA) technique by transferring samples via ambient atmosphere to the ESCA spectrometer. An Al source with K line 1486.6 eV was used for exciting X-ray photoelectron spectra with an energy resolution of 0.7 eV and probing depth from 1 to 4 nm, independent of photoelectron energy.


123

Figure 8. The HREM image (plane view) of Ge nanocrystals on SiO2.

Figure 9. Cross-section HREM image of Ge nanocrystals on SiO2.

To determine the influence of the ion beam on the thickness of the tunneling insulator during Ge deposition, the intensity of the Si 2p line was analyzed. The thickness of the tunneling insulator was evaluated from the intensity ratio of the oxide component Si 2p (103.0 eV) to substrate component Si 2p (98.7 eV). A significant decrease of tunneling insulator thickness (from 4.2 to 2.4 nm) was observed, when ions irradiate an uncapped SiO2 surface (regime 2). When ion action takes place on the surface capped by Ge (the regime 1) the tunneling insulator thickness was unaffected. In both cases there are no any changes in stoichiometry of SiO2 layers. As a measure of the germanium content, the line intensity of Ge 2p x-ray photoelectron yielded the probing depth; about 0.89 nm in our

124


experiment. This reflects the inelastic mean free path of photoelectrons. The Ge 2p states are clearly resolved with a spin-orbit splitting of 31.1 eV. Both Ge 2p1/2 and Ge 2p3/2 lines show pronounced superposition of two components with an energy shift of 2.3 eV. These two components have peak positions of binding energies at 1217.7 eV and at 1220.0 eV and are related to the germanium in pure and partially oxidized states, correspondingly. The origin of the GeOx fraction relates to the unintentional oxidation during the transfer of samples to the ESCA spectrometer in the ambient atmosphere. The HREM image of Fig. 8 shows homogeneous Ge nanocrystals of 7 nm average size on the SiO2 surface. An additional cross-section study depicted in Fig. 9, shows the spherical shape of the Ge nanocrystals. The density of nanocrystals increases with top value up to 1012 cm-2 as the substrate temperature goes down (Fig. 10). Strong Ge desorption was observed during deposition as the substrate temperature was increased. The pulsed ion beam nucleation in regime 1 was found to gives rise to suppression of Ge desorption. This effect is clearly demonstrated with ESCA measurements of Ge peak intensity and HREM studies of nanocrystal size distribution, as seen in Fig. 11. At a substrate temperature of 300o C, the pulsed ion beam action in regime 1 results in an increase in the total amount of Ge deposited on SiO2 by a factor 1.7, as compared with conventional MBD. However, even in this case the effect of desorption still dominates. From 20 effective Ge MLs intended for deposition, just 2 MLs remain on the SiO2 surface.

Figure 10. Density of Ge nanocrystals on SiO2 versus the substrate temperature.


125

Figure 11. Ge nanocrystal’s size distributions: 1 – Ge deposition with pulsed ion-beam action (regime 1); 2 – no ion-beam action during Ge deposition.

The growth procedure was optimized with respect to a uniform dot-size distribution around 6 nm and a dot density about 1012 cm-2. The main parameters determining these regimes are the deposition temperature and Ge flux. To clarify the mechanism of Ge nanocrystal formation and the role of ion irradiation, we have carried out Monte Carlo (MC) simulations of the reaction kinetics. The kinetics of nanocrystsl formation was calculated using the “lattice gas” model25, which includes Ge atoms deposition on SiO2 surface, their surface diffusion, desorption, precipitation, and ion-beam action. The sites occupied by Ge atoms and SiO2 were restricted to a facecentered cubic (FCC) lattice, which is well suited to describe precipitation in isotropic amorphous matrices such as SiO2. The lattice includes 128×128×32 sites with cylindrical boundary conditions in the lateral plane. The number and type of nearest neighbours to a Ge atom determine its interaction energy with other Ge atoms and the SiO2 matrix. The energy per one Ge-Ge bond in the FCC lattice was taken to beequal to 0.2 eV, which corresponds to an activation surface diffusion energy of 0.8 eV at a free Ge surface as obtained from molecular dynamics calculation26. For Ge in the SiO2 environment, the interaction energy per one neighbour site occupied by SiO2 was chosen to be as high as 0.076 eV, which provides the reproduction of the experimental dependence of residual surface compared to the amount of Ge deposited.

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The simulated nanocrystals were found to have isotropic shape. This result was not expected in advance, since the growth proceeds under nonequilibrium conditions. An irradiation effect was described by the concept of collisional mixing, that is, the displacement of atoms. In the simulation process each Ge atom has a probability P, to be displaced by a distance R, during one MC step. Ion-beam action results in the smaller nanocrystal size and the higher density due to precipitation and nucleation of new nanocrystals by atoms knocked out from initial ones to the SiO2 surface. 5. Conclusions We have shown that pulsed low-energy ion beam nucleation during Ge deposition on SiO2 films allows us to suppress Ge desorption, increase the density of Ge nanocrystals and decrease the average nanocrystal size and size dispersion. The pre-deposition of Ge before the pulsed ion beam action was found to allow excellent control of the thickness of the thin SiO2 film which forms the tunnel insulator in memory device. The C-V curves of the structures with control insulator over Ge nanocrystals show hysteresis with memory windows up to 7 V, indicating the charge storage effect in Ge nanocrystals. ACKNOWLEDGMENTS

This work was supported by the Russian Foundation for Basic Research (Grant No.06-02-08077).

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NANOWIRE QUANTUM EFFECTS IN TRIGATE SOI MOSFETS JEAN-PIERRE COLINGE* Dept. of Electrical and Computer Engineering, Univ. of California, Davis, CA 95616, USA *

To whom the correspondence should be addressed.

Abstract. This paper describes low-dimensional nanowire quantum effects that occur in small trigate SOI MOSFETs. 2D numerical simulation is used to calculate the electron concentration profile as a function of gate voltage in devices with different cross sections. The smaller the section, the higher the threshold voltage. A dynamic increase of threshold voltage with electron concentration is observed. Inter-subband scattering causes oscillations of the transconductance when measured as a function of the gate voltage. These oscillations are visible at low temperature (< 30K) in samples with a 45 × 82nm cross section and at room temperature in devices with a 11nm × 48nm cross section.

Keywords: Silicon-on-Insulator, SOI MOSFET, multiple-gate MOSFET

1. Introduction The Multi-Gate SOI MOSFET (or MuGFET) structure is being considered as a replacement to the single-gate MOSFET as it prolongs the life of silicon CMOS beyond the limits of classical scaling. MuGFETs can be realized with gate length well below 10 nm without suffering from the short-channel effects that plague single-gate MOSFETs. The MuGFET category includes devices such as the FinFET, a two-gate device, the trigate FET, and the gate-all-around device. Due to the presence of several channels operating in parallel at the top and the sidewalls of the device, multi-gate SOI MOSFETs can have a current drive that is significantly larger than that of planar MOSFETs1,2,3,4. Empirically, and to a first-order approximation, it is found that, in order to avoid short-channel effects, the width and height of a trigate MOSFET must be smaller than the effective gate length1. As a result, the width and height of these devices are predicted to reach values smaller than 20 nm in the near future5,6. The influence of film thickness reduction on the threshold voltage of single and double-gate SOI MOSFETs has been reported in the literature. It is found that, due to 129 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 129-142. © 2007 Springer.

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QUANTUM EFFECTS IN TRIGATE SOI MOSFETS

quantum confinement of carriers in the thin silicon layer, the minimum energy for electrons in the conduction band increases when the thickness of the silicon film is reduced. As a result, the threshold voltage increases as the film thickness is reduced. This effect was first predicted by Y. Omura et al. in 1993, and has been simulated and observed experimentally by several groups since7,8,9. It is included in modern thin-film SOI and double-gate MOSFET simulators10,11. It is also predicted that when the silicon film is sufficiently thin and/or narrow, energy subbands form, and inter-subband scattering effects should affect carrier mobility. Such effects have been reported in double-gate devices where transconductance oscillations have been observed when the gate voltage is increased12,13. In this paper, we report several effects occurring in trigate SOI MOSFETs that can directly be attributed to the formation of energy subbands and to inter-subband scattering. Firstly, the formation of subbands and the increase of the minimum subband energy when the section of the device is decreased yields an increase of the threshold voltage. Furthermore, the minimum energy for the electrons in the conduction energy subbands increases with the electron concentration, which dynamically increases the threshold voltage as the inversion charge builds up14. This effect reduces the current drive of the device and is not predicted by classical simulators. Secondly, increasing the gate voltage increases the number of subbands that are populated with electrons. As a result, inter-subband scattering increases with gate voltage and drain current oscillations are observed as gate voltage is increased15,16. 2. Device fabrication The first set of devices has a final fin width, Wsi, and height, tsi, of 45 nm and 82 nm, respectively. The gate oxide thickness is 2 nm. A polysilicon layer was then deposited and doped n-type by phosphorus ion implantation to form the gate. Arsenic was implanted to form source and drain regions and titanium silicide was formed on source and drain regions to reduce parasitic resistance. Figure 1 shows a close up TEM cross-section of one fin from such a Trigate SOI MOSFET. A second set of devices has silicon fins with a width of 11nm. A 1.7-nm gate oxide was grown by wet oxidation. A 6 nm-thick TiSiN gate layer was then deposited by LPCVD on the gate oxide, and capped with a 100nm polysilicon layer. The work function of the TiSiN gate is 4.65eV, which makes it a “midgap” gate material. Gate electrodes were patterned using lithography and etched. A combination of dry and wet chemistry was used to etch the poly capping layer and metal gate. Significant over etch was used to ensure all poly and metal are clear in


131

Figure 1. TEM cross section of a device with a fin width and height of 45 nm and 82 nm (left) and a device with a fin width and height of 11 nm and 58 nm (right).

the undercut region under the fin. As a result the devices are more of the Pigate type than straight Trigate devices. Figure 1 shows a close up TEM cross-section of one fin from such a Trigate SOI MOSFET. The fin width, Wsi, is 11 nm and the fin height, tsi, is 58 nm. 3. Device modelling The devices were modeled using a self-consistent Poisson-Schrödinger 2D simulator implemented in Comsol MultiphysicsTM. The electron concentration is obtained by adding the electron concentrations of subbands with energies ranging from EC to EC+10kT. The electron concentration is thus given by:

n ( x, y ) = ∑ ⎡ Ψ ( x, y ) × Ψ * ( x, y ) × ∫ ⎢ EC j ⎣

EC +10 kT

ρ j ( E ) f FD ( E )dE ⎤ (cm-3) ⎥⎦

(1)

where ρj(E) is the density of states in the j-th subband and fFD(E) is the Fermi-Dirac distribution function. The density of states used in the simulations corresponds to that of a one-dimensional structure: 17

ρ j (E) =

1 πAsi

2m ds* =2

1 E − Ej

(cm-3 J-1)

(2)

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QUANTUM EFFECTS IN TRIGATE SOI MOSFETS Gate electrode

A

B

Gate oxide

tsi

Silicon

y x

Wsi

Buried oxide

Back gate electrode

Figure 2. A: Cross section of the simulated device; B: Typical simulation mesh.

where Asi = Wsi×tsi is the cross-sectional area of the silicon fin. Figure 2 shows the schematic cross-section of the simulated device and a typical simulation mesh. Self-consistency of the calculation is obtained by using the following algorithm: The Poisson equation is first solved with n(x,y)=0 as the initial condition. The resulting potential distribution is fed into the Schrödinger equation to calculate the 2D wavefunctions and their energy levels. Using this information the electron concentration n(x,y) is calculated using Equation (1). The electron concentration is then introduced in the Poisson equation and a Newton-Raphson iteration process is used until convergence of the electron concentration is obtained. The criterion for convergence is a variation of electron concentration less than 0.1% between two iterations. The electron concentration profile for different values of the gate voltage (VG = 0, 0.7 and 1.5 V) is shown in Figures 3 and 4. The results are shown when using either a Poisson solver only (left columns) or a Poisson + Schrödinger solver (right columns). In Figure 3, the width and height of the silicon fin is 20 nm, while Wsi and tsi are equal to 5 nm in Figure 4. In the device with the larger cross section (Figure 3), the electron profiles obtained by the Poisson solver are very similar to those yielded by the Poisson + Schrödinger solver. This is because the section is too large for confinement effects to be of significant importance. It is worth noticing, however, that the electron concentration is lower in the Poisson + Schrödinger solutions than in the Poisson only simulations because of a bandgap widening effect predicted by the Poisson + Schrödinger simulations.

QUANTUM EFFECTS IN TRIGATE SOI MOSFETS Electron concentration (cm-3)

Poisson only

Electron concentration (cm-3)

A2

x1014 Electron concentration (cm-3)

Poisson only


VG = 0.7V

B1

Poisson + Schrödinger VG = 0.7V

B2 20

x10


Poisson only


VG = 1.5V

C1

Poisson + Schrödinger VG = 0V

VG = 0V

A1

133


C2

Figure 3. Poisson only (A1, B1, C1) and Poisson + Schrödinger (A2, B2, C2) simulation of the electron concentration profile in a trigate device with Wsi=tsi= 20 nm, ΦMS=0V, VG2=0V, 17 -3 tox=2nm and Na=5x10 cm at T=300K. A1 and A2: VG= 0V; B1 and B2: VG= 0.7V; A1 and A2: VG= 1.5V.

In the device with the smaller cross section (Figure 4), the electron profiles obtained by the Poisson solver and the Poisson + Schrödinger solver are very different. In this case, the section of the device is small enough to show confinement effects. Once again, the electron concentration is lower in the Poisson + Schrödinger solutions than in the Poisson only simulations because of the widening of the bandgap predicted by the Poisson + Schrödinger simulations.

134

QUANTUM EFFECTS IN TRIGATE SOI MOSFETS Electron concentration (cm-3)

Poisson only


VG = 0V

VG = 0V

A1

A2


Poisson only


VG = 0.7V

B1


B2 20

x10


Poisson only


VG = 1.5V

C1

Poisson + Schrödinger


C2

Figure 4. Poisson only (A1, B1, C1) and Poisson + Schrödinger (A2, B2, C2) simulation of the electron concentration profile in a trigate device with Wsi=tsi= 5 nm, ΦMS=0V, VG2=0V, 17 -3 tox=2nm, and Na=5x10 cm at T=300K. A1 and A2: VG= 0V; B1 and B2: VG= 0.7V; A1 and A2: VG= 1.5V.

Figure 5 shows the variation of the minimum energy in the first electron subband as a function of device dimensions and as a function of the average electron concentration. Clearly the energy of the lowest subband increases with the electron concentration, i.e., when the concentration of electrons increases the local electron charge increases and the repulsive forces between these electrons increases. More energy is thus required to further increase the electron concentration and, as a result, the energy of the subbands increases.


135

Energy above Ec (eV)

0.25

0.2

W = tsi = 2 nm 20 nm

0.15

3 nm 4 nm

0.1

5 nm

0.05

10 nm 0 13 10

10

14

10

15

10

16

10

17

10

18

10

19

Average electron concentration (cm-3) Figure 5. Minimum energy of first subband vs. average electron concentration in devices with different cross sections. NA =5x1017 cm-3. The small circles represent the average electron concentration at threshold.

3.1. THRESHOLD VOLTAGE AND SUBTHRESHOLD SLOPE

The current, calculated as a function of gate voltage, is shown in Figure 6. The acceptor doping concentration is 5x1017 cm-3 and the gate oxide thickness is 2 nm in all devices. The graph compares devices simulated by classical means (Poisson’s equation (P)) and using the self-consistent Poisson-Schrödinger solver (P+S). The increase of threshold voltage brought about by the reduction of device dimensions can be appreciated by comparing the P and P+S curves. The increase of threshold voltage is negligible in the largest devices but becomes quite significant in the devices with the smallest cross sections. The threshold voltage is not the only parameter influenced by the increase of subband energy levels with gate voltage and electron concentration; the subthreshold slope and the current drive are affected as well. The subthreshold slope is close to 60 mV/decade at T = 300K in the devices with the largest cross sections. The PoissonSchrödinger solver predicts an increase of subthreshold slope in small devices due to the dynamic increase of subband energy levels (and thus threshold voltage) when the electron concentration is increased. The current drive is affected as well. Because of the rapid increase of the subband energy levels (and thus the threshold voltage) with increased electron concentration above threshold, the drain current predicted by the P+S

136


simulator is lower than the drain current calculated using a classical Poisson solver. The drive current is approximately 15% smaller in the P+S calculations for a gate voltage overdrive (VG – VTH) of 300 mV in all devices. The study of the evolution of threshold voltage with device dimensions is more complicated than that of the subthreshold slope. Since devices with different cross sections have different average electron concentrations and different shapes of electron distributions at “threshold”, the classical definition, based on ΦS=2ΦF cannot be used. Furthermore the presence of volume inversion complicates the definition of threshold voltage. Here we will define the threshold voltage as the gate voltage for

d 2ID which reaches a maximum18. The threshold calculated using dVG2 Poisson’s equation only (P) increases as the device section decreases. This effect is due to the need for a higher electron concentration to build up a charge that varies linearly with gate voltage in smaller device, (Figure 6) and to the reduction of volume-inversion subthreshold current in devices with a reduced cross section. A similar effect is observed in thin, doublegate devices19. An additional increase in threshold voltage increase is observed when quantum effects are taken in consideration (P+S) because of the increase of the energy levels at reduced dimensions. 10

10

-6

W = tsi = 20 nm

-7

Drain current (A)

10 nm 10

10

10

10

10

-8

-9

5 nm 3 nm

-10

2 nm .. Schrodinger P Poisson P+S

-11

-12

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

Gate voltage (V) Figure 6. Drain current vs. gate voltage in trigate MOSFETs with different cross sections. Devices are simulated using either Poisson’s equation only (P) or the Poisson+Schrödinger solver (P+S). VDS = 50 mV, tox = 2 nm, NA = 5x1017 cm-3.


137

4. Mobility Effects The density of states (DoS) of the devices shown in Figure 1 is shown in Figure 7. The energy levels are relative to the 3D conduction band minimum when the device is biased under flatband conditions, EC0. The energy values are negative because of the downward band bending due to the application of a positive gate bias (VG=VTH) during the simulation. In the sample with Wsi = 45 nm and tsi = 82 nm, the typical energy difference between subbands (or at least between the two first ones) is on the order of 150 µeV. On the other hand, in the sample with Wsi = 11 nm and tsi = 58 nm, the energy separation is much larger, typically of the order 2 meV. When the gate voltage is increased above threshold the number of populated subbands increases. Intersubband scattering increases with each new subband that becomes populated, which results in mobility reduction and, therefore, oscillations of drain current when gate voltage is increased as shown in Figure 8. Current oscillations can be observed as long as the drain voltage is not significantly larger than the energy separation between subbands, ∆E, divided by the electron charge, q. When the drain voltage is very small (ideally zero) electrons flow from source to drain in parallel “channels” corresponding to the different subbands. When the drain voltage is increased, the number of “channels” decreases near the drain, which smears out the oscillations. However, damped oscillations are still visible when qVDS is a few times larger than ∆E. In Figure 8 the subband energy separation is equal to 0.15 mV when Wsi=45nm and tsi=82nm and oscillations are observed at VDS=0.2mV (Figure 8). -0.75

-0.558

Wsi = 45 nm tsi = 82 nm

Energy above ECo (eV)

-0.5582

Energy above Eco (eV)

Wsi = 11 nm tsi = 58 nm

-0.755

-0.5584 -0.5586 -0.5588 -0.559

-0.76

1 meV

-0.765

-0.5592 -0.5594 -0.5596

150 µeV

5 meV

-0.77

-0.5598 -0.56 0

1

2

3

4

Density of states (cm-3 eV-1)

5 x 10

20

-0.775

0

2

4

6

Density of states (cm-3 eV-1)

8

10 x 10

20

Figure 7. Density of states at VG=VTH calculated for a Trigate SOI MOSFETs with dimensions corresponding to the cross sections shown in Figure 1. Left: Device with Wsi=45nm and tsi=82nm; Right: Device with Wsi=11nm and tsi=58nm.

138

QUANTUM EFFECTS IN TRIGATE SOI MOSFETS -7

x 10

Current (A)

3.5

T=4.4K, VDS=0.2mV

3 2.5 2

T=8K, VDS=0.2mV T=5K, VDS=50mV (x 0.004)

1.5 1

T=150K, VDS=0.2mV

0.5 0 0

Effective mobility (cm 2 V-1 s -1 )

4

T=28K, VDS=0.2mV 0.1

0.2

1200

800

T=8K

600 T=28K

400 T=150K 200 0 0.05

0.3

Gate Voltage (V)

T=4.4K

1000

0.1

0.15

0.2

Gate Voltage (V)

0.25

0.3

Figure 8. Drain current vs. gate voltage for different temperature and drain voltage values in the device with Wsi=45nm and tsi=82nm (Left). The amplitude of the curve for VDS=50mV is multiplied by a factor 200µV/50mV=0.004 to fit in the same graph as the curves measured at VDS=200µV. Right: effective mobility calculated from g = µ C Weff V . m

eff

ox

L

DS

Figure 9 shows the conductance, defined as the drain current divided by the drain voltage, measured as a function of gate voltage in a device with Wsi=11nm and tsi=58nm. The measurement was carried out at room temperature. Oscillations can clearly be seen when the drain voltage is 100 µV. The magnitude of the oscillations decreases when the drain voltage is increased, but they are still visible at VDS=1mV. When the drain voltage is 5 mV however, the oscillations are no longer present. This result supports that the average subband energy separation is indeed the 2 meV, predicted by the simulation result shown in Figure 7.

Drain conductance (S)

20

x 10

-4

VDS = 100 µV

15

200 µV 400 µV 10

500 µV 1 mV

5

5 mV 0

-5

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Gate voltage (V)

Figure 9. Drain conductance, ID/VD, vs. gate voltage measured for different drain voltage values, in a device with Wsi=11nm and tsi=58nm.


139

The oscillations measured in an individual device are reproducible from measurement to measurement and are independent of the integration time (short, medium or long). The oscillations, however, differ from device to device. This is not surprising since each device is made of 20 fins in parallel and since any variation in device width or height will affect the position of the energy levels. It can be noted that the conductance drops when drain voltage is increased. When the drain voltage is equal to zero the electron concentration in the different subbands is constant along the channel. When the drain voltage is increased, the population in the higher subbands decreases near the drain. This forces some electrons to jump from higher to lower subbands, which increases intersubband scattering and reduces the mobility. 5. One- vs. Two-dimensional behaviour The calculations presented in this paper are all based on the assumption that a one-dimensional Density of States (DOS) can be used. If a device is significantly taller than it is wide (e.g. in a FinFET), one may wonder if this assumption is still valid, or if a two-dimensional DoS should be used. Onedimensional DoS is characterized by a series of spikes described by Equation (2). Each spike corresponds to an electron energy level. Figure 10 shows the electron concentration profile and the DoS in devices with a width of 5 nm and thicknesses of 5, 25 and 100 nm. The simulations were carried out for a gate voltage equal to the threshold voltage. Threshold was determined by measuring the gate voltage at which d 2 I D dVG2 reaches a maximum18. The electron concentration is approximately equal to 5×1017 cm-3 in all cases. In the device with the smallest cross section (5nm × 5nm), the electron distribution is clearly one-dimensional. The density of states is clearly composed of a succession of individual peaks. When the silicon thickness is increased to 25 nm, the energy separation between the different peaks decreases and “group of peaks” start to form in the DoS. When the fin height is increased to 100nm (the width is still 5nm) the electron distribution takes a definite two-dimensional shape as shown in Figure 10. The 1D peaks of the DoS clearly regroup in bundles that give the overall DoS distribution a definite 2D appearance, i.e. a staircase-like function. In this case, the device could be simulated using a simpler 2D DoS, but the results obtained from Equation (2) are still valid, and the 1D DoS distribution naturally converges to a 2D-like distribution. Figure 10 shows that the 1D or 2D nature of a sample can simply be deduced from looking at the shape of the DoS.

140


Figure 10. Electron concentration profile at VG=VTH in trigate MOSFETs with a width, Wsi, of 5 nm and a thickness, tsi, of 5, 25, and 100 nm. The corresponding DoS (Density of States) is shown.


141

6. Conclusion This paper describes low-dimensional nanowire quantum effects that occur in small trigate SOI MOSFETs. 2D numerical simulation is used to calculate the electron concentration profile as a function of gate voltage in devices with different cross sections. The smaller the section, the higher the threshold voltage. A dynamic increase of threshold voltage with electron concentration is observed. Inter-subband scattering causes oscillations of the transconductance when measured as a function of the gate voltage. These oscillations are visible at low temperature (< 30K) in samples with a 45 × 82nm cross section and at room temperature in devices with a 11nm × 48nm cross section.

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3. 4. 5.

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SEMICONDUCTOR NANOSTRUCTURES AND DEVICES JOACHIM KNOCH* AND HANS LÜTH* Institute of Bio- and Nanosystems, IBN-1, Forschungszentrum Jülich, D-52425 Jülich, Germany * To whom the correspondence should be addressed: : Joachim Knoch, IBM Research GmbH, Zurich Research Laboratory, Säumerstrasse 4, 8803 Rüschlikon, Switzerland, [email protected]; Hans Lüth, Institute of Bio- and Nanosystems, IBN-1, Forschungszentrum Jülich, 52425 Jülich, Germany, [email protected].

Abstract. In this paper we present semiconductor nanostructures and devices for future nanoelectronics applications. New device architectures for advanced CMOS as well as novel concepts for a beyond CMOS scenario are presented and discussed. We study SOI Schottky-barrier MOSFETs and show methods for improving the device performance using dopant segregation during silicidation as well as ultrathin body SOI and ultrathin gate oxides. Furthermore, electronic transport in GaN and InN nanowire structures is discussed. In addition, novel device concepts are also introduced and the electronic transport in such structures is studied. In particular, nanoscale resonant tunneling diodes with improved peak-to valley ratio and a band-to-band tunneling transistor based on a nanowire/ nanotube that allows for subthreshold swing smaller than 60mV/dec are presented.

Keywords: Nanowire; band-to-band tunneling; tunneling FET; SB-MOSFET; RTD

1. Introduction The continued down-scaling of bulk-silicon MOSFETs will become increasingly difficult and eventually come to an end in the near future. A loss of gate control over the channel, high gate leakage currents and increasing parasitic resistances of the source and drain electrodes, for instance, will strongly deteriorate the device performance. A continuation of CMOS technology thus makes the introduction of new device architecttures and new materials necessary. Beyond todays CMOS technology, novel concepts have to be introduced that either rely on different switching mechanisms in CMOS circuitry or even on completely new logic functionality. 143 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 143-158. © 2007 Springer.

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SEMICONDUCTOR NANOSTRUCTURES AND DEVICES

In the present paper we elaborate on both aspects, that is, new architectures as well as novel concepts. Examples of some solutions to the aforementioned issues are presented and discussed. 2. New device architectures Scaling MOSFETs to the smallest dimensions makes necessary the introduction of new materials not only to facilitate suppression of short channel effects but also for the source/drain electrodes. In the following we discuss Schottky-barrier (SB)-MOSFETs with metallic source and drain electrodes and show ways to significantly improve their performance. In addition, GaN and InN nanowires and their electronic transport properties are discussed as examples for more general one-dimensional semiconductor devices structures. 2.1. SOI SCHOTTKY-BARRIER MOSFETS

Schottky-barrier (SB) MOSFETs offer solutions associated with a number of issues related to source/drain engineering (Dubois and Larrieu, 2004; Fritze et al., 2004) such as very low extrinsic parasitic resistances, ideally abrupt contact-channel interfaces and ultra-shallow junction depths. However, Schottky contacts to date exhibit significant barrier heights much larger than kBT at the interface between the metal and the silicon and it is found that negative SBs are needed for a SB- MOSFET to exhibit a similar performance as a conventional MOSFET (Guo and Lundstrom, 2002). As a result, over a rather large gate voltage range, the drain current is determined by tunneling of carriers through the Schottky-barriers leading to poor subthreshold behavior and lower on-currents compared to conventional type devices (Knoch and Appenzeller, 2002). Therefore, improving the tunneling probability through the SB is mandatory if SB-MOSFETs are to become a viable alternative to conventional MOSFETs. In the following sections we will show two approaches to improve the carrier injection using dopant segregation during silicidation and ultrathin body (UTB) SOI and gate oxides. 2.1.1. Dopant segregation during silicidation Ohmic metal-semiconductor contacts are usually realized by heavily doping the semiconductor which leads to a thin SB through which carriers can easily tunnel. However in the fully-depleted SOI devices considered here,


145

10

As concentration (cm -3 )

Drain

with dopant segregation without doping with channel doping

Source

potential (eV)

doping the channel leads to a shift of the threshold voltage Vth but does not increase the tunneling probability through the SB. Therefore, non uniform doping profiles have to be generated with a highly doped layer only at the contact channel interface as depicted in Fig. 1 (a). As a result, strong band bending occurs yielding an increased tunneling probability through the SB without shifting Vth. Such a doping profile can be realized by dopant segregation during silicidation. Here, dopants redistribute during the silicidation process and are piled up at the silicide-silicon interface (Kinoshita et al., 2004; Zhang et al., 2006). We have confirmed this pile-up with a detailed SIMS study of the dependence of the arsenic segregation in bulk-silicon samples on initial implantation energy, silicide thickness and process flow. Figure 1 (b) displays a typical SIMS spectrum showing that indeed arsenic dopant concentrations ≥ 1020 cm-3 can be realized with an initial implantation dose of 5×1014 cm-2 and larger. In order to study the impact of dopant segregation on the Schottky barriers, SB-MOSFETs have been fabricated as schematically shown in Fig. 2. After thinning the SOI to a thickness of ≈25 nm, a gate oxide was grown and poly-silicon deposited. Subsequently, the source and drain areas were implanted with arsenic at a dose of 5×1014 cm-2 and an energy of 5keV. Then, without activation, spacers were formed and samples were coated with nickel. The last steps include a full silicidation of the contacts at 450°C for 20s and the removal of superficial nickel. The silicidation conditions are such that the silicide encroached underneath the spacer towards the beginning of the gated area as can be seen in the right panel of Fig. 2, whereby the dopants in the spacer regions are piled up at the silicidesilicon interface.

10

Ef Ec

10

Ef

(a) L (a.u.)

10

15

1.10 As/cm 2 14 5.10 As/cm 2

21

20

19

NiSi-

18

(b) interface 0

40

80

120

160

200

depth (nm)

Figure 1. (a) Schematic illustration of the conduction band profile in a SB-MOSFET without channel doping (gray), with channel doping (black) and with dopant segregation (dashed). (b) As concentration SIMS profile of a silicide-silicon junction.

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Figure 2. Fabrication process of SB-MOSFETs with dopant segregation. The right panel shows a cross-sectional TEM image of a real device.

Figure 3. Transfer (a) and output (b) characteristics of a SB-MOSFET with dopant segregation.

Figure 3 shows transfer characteristics of a SB-MOSFET with dopant segregation. The device with segregation exhibits a rather n-type behavior with one order of magnitude larger on-currents compared to control samples without dopant segregation (not shown here). The most prominent feature of the characteristics however is, that the subthreshold swing S for electron injection is 70mV/dec which is close to the thermal limit and indicates that the off-state of the device incorporating dopant segregation is determined by thermal emission rather than tunneling. This is also supported by the output characteristics of Fig. 3 (b), which show a linear current increase for small bias. This means that the device with dopant segregation behaves like


147

an SB-MOSFET with very low SB heights. The reason for this behavior is displayed in Fig. 4 which shows schematically the conduction band profile at the source channel interface for four different gate voltages (1-4V); the two dashed lines belong to the device off-state whereas the other two are for gate voltages in the on-state. For a sufficiently high doping level in the segregation layer, the band bending at the contact-channel interface is strong enough to render the tunneling probability so high that the device off-state is determined by the bulk potential in the channel rather than the SB; that is, the situation is similar to a conventional MOSFET. In a fullydepleted SOI device, a change of gate voltage leads to a commensurate change of the bulk potential barrier and as a result S ≈ 60 mV/dec is obtained. For each gate voltage an effective SB ΦeffSB for thermal emission can be associated with the resulting conduction band profile. In order to find out the dependence of ΦeffSB on Vgs we performed temperaturedependent measurements of the I-V characteristics and extracted ΦeffSB for several Vgs (Zhang et al., 2005). The result of this analysis is shown in Fig. 4(a). In the device off-state ΦeffSB indeed changes on a one-to-one basis with changing gate voltage, i.e. the effective SB in this case is the bulk potential as has been discussed above. For larger Vgs, that is in the device on-state, ΦeffSB can be manipulated by the gate only slightly leading to a certain on-state current. Looking again at Fig. 4(a) one can extract a new, reduced SB due to dopant segregation from the point where the curve deviates from the one-to-one behavior (Appenzeller et al., 2004). In the present case this barrier is ~0.1 eV much lower than the original barrier of 0.64 eV, meaning that by using dopant segregation, the SB can be lowered very effectively. source

(a)

0.3 0.2

(b)

0.4

∆Φ

eff SB

tunneling

ΦSB

reduced

0.1 0.0

ΦSB

0.6

E (eV)

effective SBH (eV)

Vds = 0.1V

channel

∆ΦSB

0.2

-0.4

-0.2 -0.4

0.0

0.4

0.8

Vgs (V)

1.2

1.6

∆Φ

2

∆Φ

eff SB

0.0

eff

thermal emission

1 eff SB

s E f

3 segregation layer

4

x (a.u.)

Figure 4. (a) extracted ΦeffSB vs. Vgs in a segregation device. (b) shows a schematics of the source Schottky diode for four different Vgs (1-4).

148


2.1.2. Impact of the gate oxide and SOI thickness In a recent publication we investigated the impact of the SOI and gate oxide thicknesses (dsoi and dox, respectively) on the electrical behavior of SBMOSFETs (Knoch and Appenzeller, 2002). It was found that both ultrathin dsoi and dox are beneficial for the injection of carriers through the SB. In order to show this performance improvement experimentally, we fabricated a number of devices with different SOI and gate oxide thicknesses. Figure 5 shows typical results where (a) displays devices with a constant dox and varying dsoi whereas (b) shows transistors with varying gate oxide thickness and constant initial SOI thickness. In both cases, the on-state current and the off-state in terms of the subthreshold, are improved consistent with our simulation study (Knoch and Appenzeller, 2002). To quantify the impact of a varying dox and dsoi on the carrier injection through the SB we chose the subthreshold swing as a relevant figure of merit since the value of S is insensitive to parasitic source/drain resistances and also - in case of SB heights larger than several kBT, is insensitive to variations of the actual SB height. It is important, however, to keep in mind that a steeper S implies increased carrier injection and hence an improved on-state of the devices. The S-values of various devices where extracted and are plotted in Fig. 5(c) (for details on the device fabrication and the extraction procedure of S, see Zhang et al., 2006). It can be seen that indeed S depends increasingly on dsoi as dox becomes larger. The straight lines indicate an analytical calculation of S where we employed the surface potential model of Young (Young, 1989) (see eqn. (2)) and replaced the actual potential

1

-Id (mA/mm)

10

-1.0

Vgs (V)

0.0

1.0

(a)

(c)

900

-2

10

dox = 3.5nm

-5

10

-Id (mA/mm)

1

10

d ox=3.5nm d ox=15nm 500 d ox=24nm

(b)

Vds = -1V

300

-2

10

S (mV/dec)

700

Vds = -1V

-5

10

dsoi = 50nm

-1.0

0.0

Vgs (V)

100 1.0 5

15

25

35

45

55

dsoi (nm)

Figure 5. Transfer characteristics of SB-MOSFETs with dsoi = 10, 15, 22nm (a) and dox = 3.5, 10, 24nm. (c) Extracted S-values as a function of dsoi of all fabricated devices.


149

distribution of the Schottky barrier with a lower effective SB for thermal emission only. As a result (Knoch et al., 2006) ⎛ ⎞ ε si S ≈ k BT / q ln(10) ⎜⎜ 1/ 2 + d soi d ox / d ⎟⎟ ε ox ⎝ ⎠

(1)

where, d is a tunneling distance/thickness of the SB beyond which tunneling can be neglected; all other symbols have their usual meaning. Since d only very weakly depends on dox and dsoi it is considered as constant; d = 3.7 nm in the present case. The obvious agreement between experimental data and calculation shows that indeed S and hence the injection of carriers through the Schottky barrier strongly depends on dsoi and dox. Using UTB SOI and ultrathin gate oxides allows realization of an effectively thinner SB thereby increasing the tunneling probability which in turn improves the on- and offstate of SB MOSFETs. We can consider an upper limit for acceptable S values, then from Fig. 5(c) it becomes apparent that this can be achieved by making dox ultrathin relaxing the requirement for the SOI body thickness and vice versa. A special class of SB-MOSFETs with ultimately thin body are carbon nanotube FETs. Due to their inherent small diameter in the few nanometer range, excellent carrier injection even for larger gate oxide thicknesses is obtained. For instance, in CNFETs S-values of 100mV/dec were found in the case of a device with a gate oxide as thick as 10nm (Lin et al., 2005). CNFETs with metallic source/drain contacts behave as Schottky-barrier FETs and thus exhibit a strong dependence of S on dox as was recently shown experimentally (Appenzeller et al., 2002). In such ultrathin body FETs the carrier injection is high and hence it can be expected that the effective SB height will be rather small. We therefore took temperature dependent measurements using the same procedure as described above and extracted ΦeffSB using thermal emission theory (Appenzeller et al., 2004). It turns out that the effective Schottky-barrier in such an ultimate UTB SB-MOSFET can be influenced by the gate even well into the on-state; that is, the barrier is significantly lowered even in the device on-state. It is therefore interesting to combine dopant segregation with UTB SOI and gate oxides. In order to investigate such a combined approach we have performed quantum simulations of SOI SB-MOSFETs (Knoch and Appenzeller, 2002) using the surface potential model mentioned above. In this model, the two-dimensional potential distribution in MOSFET devices is well described by a 1D, modified Poisson equation (Young, 1989) given by

150


d 2Φ f dx

2

−

Φ f − Φ g + Φ bi

λ

2

e ( ρ ( x) + N seg )

=

(2)

ε 0ε si

where Φf, Φg and Φbi are the surface potential, the gate potential and the builtin potential, respectively; λ = ε si ε ox d ox d si is the relevant length scale over which potential variations are screened. The effect of dopant segregation is accounted for by a step-function like doping profile of spatial extension lseg and doping concentration Nseg right at the contact-channel interfaces. The charge ρ(x) in and current through the channel is calculated self consistently employing the non-equilibrium Green’s function formalism (NEGF) (Datta, 1995). For simplicity, ballistic transport is assumed in order to give an upper estimate of the possible device performance. Although simple, the model reproduces the main experimental observations (for more details see Ref. (Knoch et al., 2005) and references therein). We have simulated transfer characteristics of SB-MOSFETs with DS (Nseg = 2×1020 cm-3, lseg = 2 nm) and a fixed SB of 0.64eV for two different body and oxide thicknesses, namely (1) dox = 1 nm, dsi = 5 nm and (2) dox = 5 nm, dsi = 25 nm. A channel length of L = 60 nm in case of (1) and L = 160 nm in the case of (2) was found to be sufficient to ensure long-channel behaviour. Figure 6(a) shows ΦeffSB as extracted from the simulations as a function of gate voltage. The one-to-one change of ΦeffSB with Vgs for small gate voltages, that is in the device off-state, shows that the effective SB is not determined by the actual SB but rather by the bulk potential in the channel as in a conventional MOSFET. Hence an almost ideal off-state can be expected as indeed observed in the simulations of Fig. 6(b). However, for larger gate voltages in the on-state, it is obvious for the case of device (1) that the effective SB can be further reduced in contrast to the transistor (2). This is due to the improved gate control over the potential distribution of the SB in the case of (1) which as a result leads to much larger 0.6

Id (mA/mm)

eff

d soi =25nm, dox =5nm

100

0.4

ΦSB (eV)

d soi =5nm, dox =1nm

102

S=70mV/dec

10-2

0.2

10-4 0.0

(a) 0.0

0.2

0.4

0.6

Vgs (V) ΦeffSB

0.8

1.0

10-6 0.0

(b) 0.2

0.4

0.6

0.8

1.0

Vgs (V)

Figure 6. (a) vs. Vgs extracted from the simulations and transfer characteristics (b) for a device of type (1) with thin dsoi,ox (black curve) and (2) with thick dsoi,ox (gray curve).


151

on-currents as can be seen in Fig. 6(b). Therefore, combining dopant segregation with UTB SOI and ultrathin gate oxides is a promising approach to make the intrinsic SB-MOSFET performance comparable to that of conventional devices. 2.2. NANOWIRE DEVICES

Semiconductor nanowires are an attractive material for future ultimately scaled devices as their geometrical shape is ideally suited for surround-gate FETs. However, as nanowire diameter decreases, the surface plays an increasingly important role. Due to Fermi level pinning at semiconductor surfaces, a depletion layer builds up with an extension of the same order as the wire diameter for thin nanowires. Hence completely depleted wires can be obtained. Thus the influence of the diameter on the electronic transport through GaN and InN MBE-grown nanowires has been investigated (Calarco et al., 2005; Meijers et al., 2006).

I (A)

10-4 10

-6

10

-8

10

(a)

d=190 nm

(b)

(c)

d > dcrit

d < dcrit EC EF

F

EF

-10

EV

d=70 nm

10-12 -2

-1

0

1

2

bias voltage (V)

Figure 7. (a) I-V characteristics of GaN nanowires with different diameters. The insets show schematically the Fermi level pinning in the wires with respect to the band edges Ec,v. (b) SEM image of self-assembled GaN wires. (c) shows an SEM image of a nanowire contacted with metallic electrodes.

Figure 7(b) shows an SEM image of self-assembled GaN nanowires grown in MBE under nitrogen-rich conditions (Meijers et al., 2006). After growth, the nanowires are dispersed on an oxidized silicon wafer and contacted with metal electrodes using e-beam lithography and a lift-off process, as displayed in Fig. 7(c). Current-voltage characteristics of GaN nanowires exhibiting different diameters were measured. As can be seen in Fig. 7(a), in the case of GaN wires the thinner nanowire exhibits a drastically lower current compared to the nanowire with larger diameter. The reason for this has already been mentioned above and is displayed in the inset of Fig. 7(a). The Fermi level pinning within the band gap leads to a completely depleted wire in the case of a thin GaN wire, thus setting a lower limit for diameter reduction. Recently, InN nanowires exhibiting very

152


promising properties were investigated (Stoica et al., 2006). Due to surface accumulation, the current through an InN nanowire is insensitive to diameter variation (Calarco and Marso, 2006). This property together with a band gap of approximately 0.75eV makes InN nanowires an attractive material for future electronics applications. 3. Novel concepts Beyond the scaling of today’s CMOS technology, novel device concepts have to be introduced either leading to a completely new logic or making use of CMOS logic but employ alternative switching mechanisms. In the following we will discuss two examples namely a band-to-band tunneling FET and nanoscale resonant tunneling devices. 3.1. TUNNELING FIELD-EFFECT TRANSISTORS

The power consumption of highly integrated circuits becomes more and more the central issue calling for high-performance, low power transistor devices. In this respect the limitation of conventional-type FETs to a subthreshold swing of 60mV/dec is a major obstacle to further reduce the supply voltage while maintaining constant device on/off-current ratio. The reason for this is that all conventional devices rely on the modulation of carrier transport injected from a thermally broadened Fermi function. Tunneling FETs (t-FETs) on the other hand have recently attracted a great deal of interest due to their potential of providing S < 60 mV/dec (Appenzeller et al., 2005; Knoch and Appenzeller, 2005). In fact, employing a dual-gate device architecture, a t-FET based on carbon nanotubes was demonstrated for the first time to exhibit an S = 40 mV/dec (Appenzeller et al., 2004). A t-FET consists of an n-doped source(drain), an intrinsic channel and a p-doped drain(source). In such a device, the carrier injection into the channel is mediated by band-to-band tunneling (BTBT) through the potential barrier at the source-channel junction. Hence, in order to obtain a large on-state current it is necessary that the BTBT barrier is as thin as possible. However, from the analysis in section 2.1.2 we know that an ultrathin channel layer together with a thin gate dielectric leads to a screening of potential variations on the length scale, λ. The BTBT barrier is such a potential variation and hence can be made thin if the device architecture is chosen so as minimise λ. It has been shown that a cylindrical surround-gate transistor layout based on a nanowire/tube yields the best electrostatic control over the channel and hence the smallest possible λ


153

(Auth and Plummer, 1997). Therefore we will consider only nanowire t-FETs as follows. The switching mechanism of a t-FET is illustrated in Fig. 8 which shows the conduction and valence bands in the device off-state (a), around threshold (b) and in the on-state (c). The respective current spectra are shown as well (gray lines). In the off-state the band gap of source, channel and drain effectively block current transport leading to a low off-state leakage. However, once the valence band in the channel is lifted above the conduction band in the source, a conducting channel via BTBT is opened up. Looking at the current spectra in the device on-state it becomes apparent that a significant current contribution stems exclusively from the energetic window between the valence band edge in the channel and the conduction band edge in the source contact, that is, the band gap in the source and channel represent a bandpass filter cutting off the high and low energy tails of the Fermi function which can be considered as an effective cooling of f(E). This bandpass filter behaviour is the reason why t-FETs can exhibit an S < 60 mV/dec at room temperature. We have simulated a nanowire t-FET using the NEGF on a finite difference grid. For the electrostatics we use the modified Poisson equation (2) given above (for more details on the calculations see Ref. (Knoch and Appenzeller, 2006)) and rather aggressively scaled geometrical parameters are chosen in the present case as shown in Fig. 9(b). Figure 9(a) displays a gray-scale plot of the local density of states which shows a large DOS in the BTBT barrier yielding in turn a large tunneling probability. Figure 9(b) shows the transfer characteristic of the simulated t-FET with S = 15 mV/dec over several decades of current. For comparison, S = 60 mV/dec is shown as well. It is apparent that in a t-FET a superior off-state can be realized compared to conventional FET devices. On the other hand the BTBT barrier also leads to lower on-state currents than achievable in conventional transistors. However, from the intrinsic device point of view, the on-state Vgs = -0.2V channel

Vgs = -0.45V

Vgs = -0.5V

drain

1.2

1.2

0.8

0.8

0.8

0.4

0.4

0.4

0.0

-0.4

Ec

0.0

-0.4

Ev

-0.8 -1.2

E (eV)

1.2

E (eV)

E (eV)

source

-0.4

-0.8

(a)

current

-1.2

0.0

-0.8

(b)

current

-1.2

(c)

current

Figure 8. Conduction and valence bands in a t-FET’s off-state (a), around threshold (b) and on-state (c). The gray lines show the respective current spectra.

154


Figure 9. (a) Local DOS in a t-FET and (b) transfer characteristic for the simulated t-FET.

current is not the best metric to qualify a device. A better measure is the device delay time τ = CgVdd/Id where Cg is the total gate capacitance and Vdd the supply voltage. In a one-dimensional system the so-called quantum capacitance limit can be reached, i.e. Cox >> Cq with Cq being the quantum capacitance (Luryi, 1988) and as a result, Cg ≈ Cq. Using the WKB approximation for the BTBT probability it can be shown that to first order Cq as well as Id are proportional to the BTBT probability (Knoch et al., 2007); that is, Cg is decreased directly with Id for decreasing tunneling probability (if for example, dox is increased). As a result, the tunneling probability to first order does not affect τ. Note that this is a specific feature of one-dimensional t-FETs and together with the small geometry makes nanowires ideally suited for the realization of such devices since a superior off-state can be combined with an excellent on-state performance. 3.2. NANOSCALE RESONANT TUNNELING DEVICES

Resonant tunneling devices have recently attracted an increasing interest as quantum devices which operate at room temperature. The interest stems from the fact that due to the particular electric characteristics, RTDs allow for more complex logic circuits with fewer electronic parts. As a general feature, RTDs exhibit a current peak and a region of negative differential resistance (NDR). This behavior results from a peaked transmission coefficient of the double barrier structure in conjunction with the injection electron distribution from the emitter. The ratio between the peak current and the valley current in the NDR region, the peak-to-valley ratio (PVR), serves as a figure of merit of the RTD. The impact of the geometrical size of RTDs on their electronic transport was investigated by fabricating nanocolumn RTDs with varying diameters in the range of 1µm down to 50nm using a top-down approach. For the present experiments, vertical


155

Figure 10. PVR vs. column diameter of nanoscale RTDs. The data points represent average results measured on 5-6 equally prepared devices. (b) displays the I-V-characteristic of an RTD with 50nm column diameter; the inset shows an SEM of the same column.

GaAs nanocolumns with two embedded AlAs barriers were processed by e-beam lithography from an MBE-grown layer stack. The heterostructure exhibits a symmetrical layer sequence with an undoped part around the quantum well which in turn is cladded with highly n-doped regions (for details see Ref. (Wensorra et al., 2005)). The heterostructure is capped by a thin layer of low-temperature grown GaAs enabling excellent non-alloyed ohmic contacts using a Ti/Au metallization. Nanocolumns were patterned out of this heterostructure/metal stack using e-beam lithography followed by ion beam and reactive ion etching. The inset of Fig. 10(b) shows a fabricated nanocolumn with a diameter of 50nm. DC measurements at room temperature have been carried out on the processed nanodevices and the PVR has been extracted from the measurements. Figure 10(a) displays the extracted PVRs as a function of column diameter. Reducing the diameter first leads to a decrease of the PVR due to a relative increase of surface scattering. However, below ∼80nm the PVR strongly increases again. This unusual behavior can be explained by looking at the conduction band profile in the nanocolumn. As it turns out, the large depletion length in the undoped region of the column leads to the formation of a potential barrier when the column diameter is of the same order as shown in Fig. 11(b). Due to the highly doped regions cladding the intrinsic part, a saddle point is formed in the undoped region that acts as a quantum point contact. Under bias the saddle point is formed in front of the double barrier and hence the quantum point contact (saddle point) leads to a pre-selection of allowed kz-values as shown schematically in Fig. 11(a). It is this filter behaviour that leads to the increasing PVR with decreasing column diameter (Wensorra et al., 2005). As a result, employing particular doping profiles in combination with nanoscale dimensions

SEMICONDUCTOR NANOSTRUCTURES AND DEVICES source

drain E1

Ef

E0

0.5

0.0

Ec saddle point

(a)

(b)

energy (eV)

156

-0.5

-1.0

Figure 11. (a) Schematics of the pre-selection mechanism of kz-values by differently spaced subbands. (b) Conduction band profile Ec in nanscaled RTDs.

enables the creation of a potential landscape that is beneficial for the performance of RTDs and allows for improved PVR in such nanosized resonant tunneling devices. More generally, similar doping profiles with saddle points might improve the performance of all kinds of quasi 1Dnanodevices by quantum collimation of propagating electrons. 4. Conclusion In the present paper we elaborated on semiconductor nanostructures and devices for future nanoelectronics applications. SB-MOSFETs as well as nanowire structures were presented as possible solutions to issues related to advanced CMOS devices. Two ways of increasing the carrier injection in SB-MOSFETs were shown that allow for high performance devices. In addition, GaN and InN nanowire structures were presented and discussed as possible future channel material. Moreover, we also studied novel device architectures, in particular a BTB tunneling FET that allows for an off-state superior to any conventional FET and a resonant tunneling diode. Here the use of nanoscale dimensions together with a particular doping profile enabled an improved PVR in such RTD devices.

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Appenzeller, J., Radosavljevic, M., Knoch, J., and Avouris, Ph., 2004, Tunneling versus thermionic emission in one-dimensional semiconductors. Phys. Rev. Lett., 92:048301-1 – 4. Appenzeller, J., Lin, Y. M., Knoch, J., Chen, Z., and Avouris, Ph., 2005, Comparing carbon nanotube field-effect transistors - The ideal choice: A novel tunneling device design. IEEE Trans. Electron Dev., 52:2568 – 2576. Auth, Ch. P. and Plummer, J. D., 1997, Scaling theory for cylindrical, fully depleted, surrounding-gate MOSFET’s. IEEE Electron Dev. Lett., 18:74 – 76. Calarco, R., Marso, M., Richter, Th., Aykanat, A. I., Mejers, R., Hart, v.d., A., Stoica, T. and Lüth, H., 2005, Size-dependent Photoconductivity in MBE-grown GaN-nanowires. Nano Lett., 5:981 – 984. Calarco, R. and Marso, M., GaN and InN nanowires grown by MBE: a comparison, 2005, cond-mat/0611674. Datta, S., 1995, Electronic Transport in Mesoscopic Systems, Cambridge University Press. Dubois, E. and Larrieu, G., 2004, Schottky-barriersource/drain MOSFETs on ultrathin SOI body with tungsten metallic midgap gate, IEEE Electron Dev. Lett., 25:801 – 803. Fritze, M., Chen, C. L., Calawa, S., and Yost, D., 2004, High-speed Schottky-barrier pMOSFETs with fT = 280GHz, IEEE Electron Dev. Lett., 25:220 – 222. Guo, J., and Lundstrom, M. S., 2002, A computational study of thin-body, double-gate Schottky barrier MOSFETs, IEEE Trans. Electron Dev., 49:1897 – 1902. Kinoshita, A., Tsuchiya, Y., Yagishita, A., Uchida, K. and Koga, J., 2004, Solution for highperformance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique, in: 2004 Symp. VLSI Technol., 168 – 169. Knoch, J., Lengeler, B., and Appenzeller, J., 2002, Quantum simulations of an ultrashort channel single-gated n-MOSFET on SOI. IEEE Trans. Electron Dev., 49:1212 – 1218. Knoch, J. and Appenzeller, J., 2002, Impact of the channel thickness on the performance of Schottky barrier metal-oxide-semiconductor field-effect transistors. Appl. Phys. Lett., 81:3082 – 3084. Knoch, J., Zhang, M., Zhao, Q. T., Lenk, St., Appenzeller, J., and Mantl, S., 2005, Effective Schottky-barrier lowering in silicon-on-insulator Schottky-barrier metal-oxidesemiconductor field-effect transistors using dopant segregation, Appl. Phys. Lett., 87:263505-1 – 3. Knoch, J., and Appenzeller, J., 2005, A novel concept for field-effect transistors - the tunneling carbon nanotube FET, in: Device Research Conf., Conference Digest, 153 – 156. Knoch, J., Zhang, M., Mantl, S., and Appenzeller, J., On the performance of single-gated ultrathin body SOI Schottky-barrier MOSFETs. IEEE Trans. Electron Dev., 53:1669 – 1674, 2006. Knoch, J., and Appenzeller, J., 2006, Carbon nanotube FETs – the importance of being small, in: Hardware Technology Drivers for Ambient Intelligence, Kluwer Academic Publisher. Knoch, J., Mantl, S., and Appenzeller, J., 2007 (in press), Impact of the dimensionality on the performance of tunneling FETs: Bulk- versus one-dimensional devices. Solid-State Electron. Knoch, J., Zhang, M., Appenzeller, J., and Mantl, S., 2007 (in press), Physics of ultrathinbody silicon-on-insulator Schottky-barrier field-effect transistors. Appl. Phys. A. Lin, Y. M., Appenzeller, J., Knoch, J., and Avouris, Ph., 2005, High performance carbon nanotube field-effect transistors with tunable polarities. IEEE Trans. Nanotechnol., 4:1536 – 1544. Luryi, S., 1988, Quantum capacitance devices. Appl. Phys. Lett., 52:501 – 503.

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Meijers, R., Richter, T., Calarco, R., Stoica, T., Bochem, H.-P., Marso, M. and Lüth, H., 2006, GaN-nanowhiskers: MBE-growth conditions and optical properties. J. Crystal Growth, 289:381 – 386. Stoica, T., Meijers, R., Calarco, R., Richter, T., Sutter, E., and Lüth, H., 2006, Photoluminescence and intrinsic properties of MBE-grown InN nanowires. Nano Lett., 6:1541 – 1547. Wensorra, J., Indlekofer, K. M., Lepsa, M., Förster, A. and Lüth, H., 2005, Resonant tunneling in nanocolumns improved by quantum collimation. Nano Lett., 5:2470 – 2475. Young, K. K., 1989, Short-channel effect in fully depleted SOI MOSFET's. IEEE Trans. Electron Dev., 36:399 – 402. Zhang, M., Knoch, J., Zhao, Q. T., Fox, A., Lenk, St. and Mantl, S., 2005, Low temperature measurements of Schottky-barrier SOI-MOSFETs with dopant segregation. Electronics Lett., 41:1085 – 1086. Zhang, M., Knoch, J., Zhao, Q. T., Lenk, St., Breuer, U., and Mantl, S., 2006, Impact of dopant segregation on fully depleted Schottky-barrier SOI-MOSFETs. Solid-State Electron., 50:594 – 600. Zhang, M., Knoch, J., Mantl, S. and Appenzeller, J., 2007 (in press), Improved carrier injection in SOI Schottky-barrier MOSFETs. IEEE Electron Dev. Lett.

MuGFET CMOS PROCESS WITH MIDGAP GATE MATERIAL W. XIONG1*, C. R. CLEAVELIN1, T. SCHULZ2, K. SCHRÜFER2, P. PATRUNO3 AND J.P. COLINGE4 1 SiTD, Texas Instruments Incorporated, Dallas, TX 75265, USA 2 Infineon Technologies, Am Campeon 1-12, 85579 Neubiberg, Germany 3 SOITEC S.A., Parc Technologique des Fontaines – 38190 Bernin, France 4 Dept. of Electrical and Computer Engineering, Univ. of California, Davis, CA 95616, USA *

To whom correspondence should be addressed. [email protected]

Abstract. An increase in threshold voltage is observed in ultra-thin body MuGFET (multi-gate FET) devices. The threshold increase is due to of lack of carriers at the classical threshold definition. A sufficient amount of carrier build-up requires additional gate voltage (0.12V in our experiment).

Keywords: Silicon-on-Insulator, SOI MOSFET, multiple-gate MOSFETs

1. Introduction Advanced transistor structures, such as the Multi-Gate FET (MuGFET), offer improved control of short-channel effects compared to the planar bulk-Si MOSFET. Hence they may be adopted in CMOS technology nodes toward the end of the roadmap. To control the Short Channel Effect (SCE), fins need to be thin, typically less than 2/3 of the gate length1. For the 32nm node, fin width is expected to be 1, m >> 1,

U ij ( x ) ~

1 n2 + m2

.

(10)

Therefore, the transformation of the incident mode i into upper modes j is negligible. The necessary number of modes involved into consideration could be determined immediately during simulation. The equation is to be solved on a uniform mesh with nodes in x=xk, k=-1, 0, 1..N, N+1, N+2 and step ∆x. The finite difference approximation of Eq. (8) is

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ALL QUANTUM SIMULATION OF ULTRATHIN SOI MOSFETS

ci (xk −1 ) = −ci (xk +1) + 2ci (xk ) + ⎛ ⎞ +2mx ⋅ ∆x 2 ⎜ ∑ U i , j ( xk )c j ( xk ) − [ E − ε i ] ci ( xk ) ⎟ . ⎝ j ⎠

(11)

The same in vector presentation looks like

c( xk −1 ) = −c( xk +1 ) + 2c( xk ) +

+2mx ⋅ ∆x 2 ( U( xk )c( xk ) − [ E − ε ] c( xk ) ) =

= −c( xk +1 ) + A( xk )c( xk ) ,

(12)

where c=(ci) and ε=(εi) are vectors, U=(Uij) and A=(Aij) are matrices. Then we rewrite equation (12) as

⎛ c( xk −1 ) ⎞ ⎛ A ( xk ) − I ⎞⎛ c( xk ) ⎞ ⎛ c ( xk ) ⎞ = T( xk ) ⎜ ⎟ ⎟, ⎜ c( x ) ⎟ = ⎜ I ⎟⎜ 0 ⎠⎝ c( xk +1 ) ⎠ k ⎝ ⎝ c( xk +1 ) ⎠ ⎠ ⎝

(13)

where I is a unity matrix. The solution is

⎛ c( x−1 ) ⎞ N +1 ⎛ c( xN +1 ) ⎞ ⎛ c( x N +1 ) ⎞ ⎜ c( x ) ⎟ = ∏ T( xk ) ⎜ c( x ) ⎟ = Ttot ⎜ c( x ) ⎟ . k =0 0 ⎠ ⎝ ⎝ N +2 ⎠ ⎝ N +2 ⎠

(14)

The Eqn. 14 relates the coefficients c at the left boundary with that at the right-hand one via the total transfer-matrix Ttot being a product of individual transfer-matrices for particular nodes xk. To pose boundary conditions one should express the coefficients, c in terms of amplitudes of waves going to the right and the left in the extreme nodes placed fairly deeply in the contacts

ci ( x−1 ) = ciL+ + ciL− , i 2 m x ( E − ε i ) ∆x + = iL

ci ( x0 ) = c e

(15a) − iL

+c e

−

i 2 m x ( E − ε i ) ∆x =

ci ( x N ) = ciR+ + ciR− , i

ci ( xN +1 ) = ciR+ e = + ciR− e

2 mx ( E − eVD −ε i )∆x

−

,

(15b) (15c)

+

i 2 mx ( E − eVD −ε i )∆x =

,

(15d)

where VD is the drain voltage. There is an assumption that the potential φ does not vary between nodes which is valid sufficiently deep in the contacts. For the left (source) contact, φ=0, meanwhile for the right (drain)


333

contact φ=VD. For evanescent modes which correspond to negative energy of longitudinal motion, the sign of the square root in Eqn. (15b) and (15c) is chosen according to the rules

i E − εi = − | E − εi | ,

(16a)

−i E − ε i = + | E − ε i | ,

(16b)

i E − eVD − ε i = − | E − eVD − ε i | ,

(16c)

−i E − eVD − ε i = + | E − eVD − ε i | .

(16d)

To calculate the transmission coefficients Tij one should pose the boundary conditions in source (left) and drain (right) contacts, that is, ascribe

c +jL = 0 for all j ≠ i and ciL+ = 1 ,

(17a)

c −jR = 0 for all j including j = i .

(17b)

Actually, this condition implies unity amplitude of an incident wave from one contact and zero amplitude of incident waves from another. After substituting boundary conditions (17) in Eqn. (15), then in Eqn. (14) one obtains a system of linear equations. The solution produces the requisite transmission coefficients

Tij =| c −jR |2 .

(18)

These coefficients are further employed for calculation of the current using the Buttiker-Landauer formulism. Moreover, the direct employment of Eqn. (14) in intermediate nodes xk inside the channel, allows the reconstruction of the wave function amplitude c(xk) everywhere in the channel and thus the electron density can be determined. The latter could be further used for iteration with the Poisson equation. 5. One-dimensional classical ballistic simulation Classical ballistic simulation can be regarded as an approximate step towards quantum simulation. When a bias is absent (VD=0) the electron density is calculated according to

334

ALL QUANTUM SIMULATION OF ULTRATHIN SOI MOSFETS ∞

ρ tot ( x ) = −4e∑ i =0

∞

dk

∫ 2π = f ( E ) + eN

D

( x) ,

(19)

0

where the factor of 4, arises from two possible spin states and two possible directions of motion; ND(x) is the doping profile. The summation is really extended over a finite number of modes i. The equilibrium Fermi-Dirac distribution function is

f (E) =

1 . E − εF 1 + exp kT

(20)

The Fermi energy is calculated in the usual way via the neutrality condition ρ=0 which is realized fairly deep in the contacts. The total energy is composed of the transversal quantization energy (mode energy) εi, potential energy eφ(x), and longitudinal kinetic energy depending on a wave number k(x):

E = εi +

= 2k ( x )2 − eϕ ( x ) . 2m x

(21)

The computed density of free carriers is substituted into the Poisson equation to allow calculation of the potential, φ(x). The iteration procedure stops when the required accuracy is achieved. Surprisingly, the self-consistent solution of the Poisson equation with the equilibrium distribution function is sufficient to simulate a steady current regime for one-dimensional motion. As a matter of fact, it is simply an extension of the Landauer approach to classical ballistic longitudinal motion. The particles (waves) are divided into those moving from the left contact and those moving from the right one. The corresponding densities produced are calculated in accordance with the relations ∞

ρ `L ( x ) = 2 ∑ i =0 ∞

ρ `R ( x ) = 2 ∑ i =0

∞

dk ( x ) f ( E )(2 − Ti ( E )) , 2π = 0

∫

(22)

∞

dk ( x ) f ( E )(2 − Ti ( E )) , 2π = 0

∫

ρ tot ( x ) = ρ L ( x ) + ρ R ( x ) + eN D ( x ) .

(23) (24)


335

The transmission coefficient T(E) equals 0 if the particle is reflected from the barrier, otherwise it equals 1. If the particle is reflected, the density is doubled. If at the potential barrier top, the condition –eφm < E - εi is satisfied, that particle is reflected back from the barrier and T=0. If the condition is not satisfied, the particle passes through the barrier and T=1. The expression for charge density according to formulae (22)-(24) undergoes iteration with Poisson equation solution. Afterwards, the current is calculated via the Buttiker-Landauer relation (1). 6. Stages of simulation The program operates as follows. 1. Classical ballistic simulation via self-consistent solution of the Poisson equation with Fermi-Dirac distribution function to obtain a selfconsistent potential. 2. Solution of the Schroedinger equation with the foregoing self-consistent potential to obtain the transmission coefficients and new (quantum) electron density inside the channel. 3. Solution of Poisson equation corrected by new electron density inside the channel to obtain a self-consistent potential. Iterations with stage 2 until the required accuracy is attained. 4. Calculation of current according to Buttiker-Landauer formula. 7. Results of simulation Up to date we have carried out only preliminary, all-quantum calculations. Geometrical parameters of the structure are: gate length 10nm, spacer length 5nm, silicon body thickness 2nm, channel width 5nm, effective gate oxide thickness 1.5nm. The source/drain doping is 1020cm-3. The simulation region involves a 5nm contact length, which turned out to be sufficient to make a rigorous description of the self-consistent potential barrier. The potential flattens by the boundaries and this is taken as an indication that a sufficient portion of the contact is included in the simulation area. The calculated quantum transmission coefficients for different valleys and in the absence of random impurities in the channel, are demonstrated in Fig. 6a and 6b. A sharp transition from T=0 to T≈1 appears when the longitudinal energy surmounts the barrier height. Evidently, this resembles very much, classical behaviour.

336

ALL QUANTUM SIMULATION OF ULTRATHIN SOI MOSFETS 1,2

Transmission

1 0,8 0,6 0,4 0,2 0 0

0,1

0,2

0,3

0,4

0,5

Energy, eV

(a)

Transmission

1,2 1 0,8 0,6 0,4 0,2 0 0

0,1

0,2

0,3

0,4

0,5

Energy, eV

(b) Figure 6. (a) Transmission coefficient vs. longitudinal energy of an electron in [100] and [010] valleys. No impurities in the channel. (b) Transmission coefficient vs. longitudinal energy of an electron in [001] valleys. No impurities in a channel.

The calculated quantum transmission coefficients for 4 and 10 random impurities in the channel are depicted in Fig. 7-8, respectively. It can be readily seen that the interference peaks are much more pronounced for an electron in [100] and [010] valleys than in [001] valley. This is a result of the much smaller mass and thus much larger wave length. It should be noted that electrons of [100] valleys make the largest contribution to the current as they have the lowest energy of transversal quantization due to a large mass mt=0.98m0 along the z-axis. Only electrons with energy inside a short range about several kT around the barrier top contribute to current. At room temperature kT=0.026eV. The above curves show that most of the electrons coming from contacts really possess a transmission coefficient close to zero. Indeed, they could be considered as classical. This supports our proposal for accelerating the all-quantum simulation program.


337

Transmission

1,2 1 0,8 0,6 0,4 0,2 0 0

0,1

0,2

0,3

0,4

0,5

Energy, eV

(a)

Transmission

1,2 1 0,8 0,6 0,4 0,2 0 0

0,1

0,2

0,3

0,4

0,5

Energy, eV

(b) Figure 7. (a)Transmission coefficient vs. longitudinal energy of an electron in [100] and [010] valleys. 4 random impurities in a channel. (b) Transmission coefficient vs. longitudinal energy of an electron in [001] valleys. 4 random impurities in a channel.

The present calculations are merely demonstrations of program effectiveness. Indeed, the doping in the channel is too high, of the order of 1019cm-3. In the near future we intend to account for more realistic distributions of impurities in the channel. 8. Pitfalls of Buttiker-Landauer formalism In spite of the clarity of the Buttiker-Landauer formula (1), actually, it contains hidden quite limiting assumptions. First of all, we assume that contact reservoirs supply only pure states into the channel and they sustain their coherence during transmission through the channel. There are several reasons to make this assumption questionnable: 1. mixed states are injected from contacts instead of pure ones; 2. entangled states are injected from contacts; 3. electron-electron scattering inside the channel is considerable.

338


Transmission

1,2 1 0,8 0,6 0,4 0,2 0 0

0,1

0,2

0,3

0,4

0,5

Energy, eV

(a)

Transmission

1,2 1 0,8 0,6 0,4 0,2 0 0

0,1

0,2

0,3

0,4

0,5

Energy, eV

(b) Figure 8. (a) Transmission coefficient vs. longitudinal energy of an electron in [100] and [010] valleys. 10 random impurities in a channel. (b) Transmission coefficient vs. longitudinal energy of an electron in [001] valleys. 10 random impurities in a channel.

We can consider the likely effect on the current if we take those circumstances into account. The mixed state means that a single electron occupies simultaneously, several eigen-states in the channel. Interference between these states will cause the current to vary in space and time. However, after an averaging over time and keeping in mind the random nature of the phases of states in the mixture, one comes again to the initial formula of Eqn.1 for the current. The same considerations occur when we deal with entangled states whereby the overall state of several electrons is not separable into a product of individual states. The formulism of Eqn.1 survives again. As for the electron-electron scattering, it is commonly omitted in classical Monte Carlo simulation. This is substantiated by the fact that this kind of scattering, at least, does not influence significantly the mobility due to the momentum conservation law. Such is not the case if we regard interference in quantum simulation. Interference requires coherence in the channel and electron-electron scattering breaks such coherence. The decoherence time has a reciprocal relationship with the


339

electron-electron scattering rate which is for the typical bulk density n ~ 1018cm-3 equal to ~1013s-1. It leads to the decoherence length about 10nm for the thermal velocity 107cm/s. These estimations readily show that electron-electron scattering could substantially smooth down the sharpness of interference peculiarities on the I-V curve, obtained in a single-particle model. 9. Conclusion A procedure for all-quantum 3D simulation of a nanometer scale silicon-oninsulator MOSFETs is proposed. The procedure is based on the BüttikerLandauer approach and realized via a self-consistent solution of the Schrödinger and Poisson equations. Stabilization of the numerical solution of the Schrödinger equation is achieved by a wave-guide mode approach. Most of the particles (waves) moving from a contact are reflected by the self-consistent barrier and returned to the contact. Therefore, they are in equilibrium with the contact reservoir. Those particles could be easily put into consideration via Fermi-Dirac statistics and Poisson’s equation to estimate the self-consistent electric field. Herewith, no dynamic equations need to be solved. The numerical solution of dynamic equations (Schrödinger equation in this case) is only required for particles which surmount the barrier and contribute to the current. As a result, this method constitutes a fast and efficient simulation algorithm. ACHNOWLEDGEMENTS

The authors extend much gratitude to K.A.Valiev for fruitful discussions. The research was supported by NIX Computer Company ([email protected]), grant #F793/8-05, and Russian Basic Research Foundation, grants #06-0789151-а and #06-01-00097-а.

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ALL QUANTUM SIMULATION OF ULTRATHIN SOI MOSFETS Ernst T., Munteanu D. et al. 1999. Ultimately thin SOI MOSFETs: Special characteristics and mechanism. in: Proc. IEEE Int. SOI Conf., Rohnert Park (California, USA), oct. 1999. Popov V. P., Antonova I. V., Stas V. F. et al. 2000. Properties of extremely thin silicon layer in silicon-on-insulator structure. J. Mater. Sci. Eng. B73: 82-86. Uchida K. and Takagi S. 2003. Carrier scattering induced by thickness fluctuation of silicon-on-insulator film in ultrathin-body metal-oxide-semiconductor field-effect transistors. Appl. Phys. Lett. 82: 2916-2918. Ananiev S. D., V’yurkov V. V., and Lukichev V. F. 2006. Surface scattering in SOI field-effect transistor. in: Proc. SPIE, 6260:0O-1-8. Shifren L., Ringhofer C., and Ferry D. K. 2003. A Wigner function-based quantum ensemble Monte Carlo study of a resonant tunneling diode. IEEE Trans. El. Devices 50: 769. Bordone P., Pascoli M., Brunetti R., Bertoni A., and Jacoboni C. 1998. Quantum transport of electrons in open nanostructures with the Wigner-function formalism. Phys. Rev. B. 59: 3060. Mamaluy D., Sabathil M., and Vogl P. 2003. Efficient method for calculation of ballistic quantum transport. J. Appl. Phys. 93: 4628. Lake R., Klimeck G., Bowen R. C., and Javanovic D. 1997. Single and multiband modeling of quantum electron transport through layered semiconductor devices. J. Appl. Phys. 81: 7845. Hake A. and Khondker A. N. 2000. Quantum transport in mesoscopic devices: Current conduction in quantum wire structures. J. Appl. Phys. 87: 2553. Fischetti M. V. 1998. Master-equation approach to the study of electronic transport in small semiconductor devices. Phys. Rev. B 59: 4901. Venugopal R., Paulsson M., Goasguen S., Datta S., and Lundstrom M. S. 2003. A simple quantum mechanical treatment of scattering in nanoscale transistors. J. Appl. Phys. 93: 5613. Jimenez D., Saenz J.J., Iniquez B. et al. 2003. Unified compact model for the ballistic quantum wire and quantum well metal-oxide-semiconductor field effect transistor. J. Appl. Phys. 94: 1061. Landauer R. 1985. Transport as a Consequence of the Incident Carrier flux, in Localization, Interaction, and Transport Phenomena, G.Bergmann and Y. Buynseraede, Eds., Springer-Verlag, Heidelberg, P. 38. Buttiker M. 1988. Symmetry of electrical conduction. IBM J. Res. Dev. 32: 317. Gilbert M. J. and Ferry D. K. 2004. Efficient quantum three-dimensional modeling of fully depleted ballistic silicon-on-insulator metal-oxide-semiconductor field-effecttransistors. J. Appl. Phys. 95: 7954-7960. Venugopal R., Goasguen S., Datta S., and Lundstrom M.S. 2004. Quantum mechanical analysis of channel access geometry and series resistance in nanoscale transistors. J. Appl. Phys. 95: 292. Kane E. O. 1969. Tunneling Phenomena in Solids, edited by E. Burstein and S. Lundqvist (Plenum, New York) p. 1. Schulman J. N. and Chang Y. C. 1983. Reduced Hamiltonian method for solving the tight-binding model of interfaces. Phys. Rev. B. 27: 2346.

RESONANT TUNNELING DEVICES ON SOI BASIS BOGDAN MAJKUSIAK* Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw, Poland *

To whom the correspondence should be adressed: [email protected]

Abstract. The paper reviews achievements and perspectives of building silicon-base resonant tunneling devices in respect to the material and architecture issues, with especial emphasis on the SOI technology.

Keywords: nanoelectronics; silicon-on-insulator; resonant tunneling.

1. Introduction Resonant tunneling (RT) means tunneling through a quantum system containing at least two potential barriers and a quantum well between them. The probability of tunneling exhibits sharp peaks for energies corresponding to eigen-states of the inner quantum well, reaching unity if the barriers are symmetrical. In the case of a superlattice of identical barriers separated by identical quantum wells, the resonant levels create the resonant transport energy minibands. Current-voltage dependence of the resonant tunneling diode (RTD) can exhibit multiple current peaks followed by ranges of the negative differential resistance (NDR). The NDR ranges begin at peak voltages (Vp), when subsequent resonant energy levels in the quantum well drop below the bottom of the conduction band in the emitter, becoming unable to transfer carriers from the emitter to the collector electrode. The peak current density (Jp) and the peak-to-valley current ratio (PVCR) are the main figures-ofmerit of a RTD. If the potential of the quantum well is controlled directly by a galvanic contact or affected by the electric field of an additional gate electrode, the double barrier system can be exploited as the resonant tunneling transistor (RTT). Since the first theoretical prediction1 and especially the first roomtemperature observation of the NDR effect2 in the double barrier quantum

341 S. Hall et al. (eds.), Nanoscaled Semiconductor-on-Insulator Structures and Devices, 341-356. © 2007 Springer.

342

RESONANT TUNNELING DEVICES ON SOI BASIS

system, resonant tunneling structures have become well known and widely investigated but mainly in III/V semiconductors. Attempts to build silicon nanoelectronics have resulted in a search for the resonant tunneling effect in silicon-based structures. Currently, the silicon-based resonant tunneling devices are considered to be the most promising candidates to replace MOSFETs in the beyond-CMOS era3. One of the obvious reasons for the search for new alternative silicon devices arises because scaling of the channel length in conventional field-effect transistors cannot proceed infinitely due to the ballistic transport and direct source-to-drain tunneling4. On the other hand, such conditions are desirable for tunneling as an alternative to the drift-diffusion transport principle. Because of their inherent high speed and multi-stability, the resonant tunneling devices are attractive for very high frequency, low power and multi-valued logic circuits and can be incorporated in more compound quantum functional devices and circuits. The one-transistor static memory cell5 is a good example of the increased functionality offered by the resonant tunneling device. It consists of two tunnel diodes connected in series and a transfer field effect transistor. Potential of the connection point stays in one of two stable states and switching between them is forced by the potential of the bit line, transferred by the channel of the turned-on transistor controlled from the word line. Although most concepts of the silicon resonant tunneling devices can be realized in the conventional bulk MOS technology, the ultra-thin, double gate silicon-on-insulator technology (DG SOI), owing to its manufacture possibilities, is well-suited to play the role of a technological platform for silicon nanoelectronics. Its most important feature is that the silicon thickness, which can define the length of the RTD quantum well, is controlled not by lithography but by the growth and thinning processes, which offer greater control and sensitivity than lithography resolution. Also, very good uniformity of the layer thickness can be achieved. Additionally, the thick buried oxide gives an excellent isolation of the realized structure. However, at the current state of knowledge and experience, the main task in relation to the resonant tunneling effect, is its feasibility for incorporation into the silicon technology and to silicon-on-insulator technology in particular. 2. Structural and physical requirements In order to evaluate the feasibility for silicon based resonant tunneling devices, it is appropriate to consider structural and physical requirements which must be fulfilled by a double barrier system to result in a distinct NDR effect and to be applicable in the silicon CMOS process.


343

Taking into consideration the manufacture requirements to transfer resonant tunneling devices to the main-stream technology, the fabrication process of the double barrier structure must be compatible with the silicon CMOS process and the structure must have two independently biased gate electrodes. The first requirement corresponds mainly to materials issues since the silicon based double barrier structure can exploit some exotic insulators. The second condition is not trivial given that the majority of current DG SOI technologies have the gates shorted together. The most important design parameter of a RTD structure is the base length. It determines the phase shift of the wave function in its transit through the base, which must be a multiple of 2π for the eigen-energies of the quantum well and the resonant tunneling levels. If the base length is too long and resonant levels lie too densely, a drop of the resonant tunneling current through one resonant level is covered by a practically unchanged current flowing through higher resonant levels and the NDR effect may be invisible. The base length must be shorter or at least comparable to the carrier mean free path for scattering. In the opposite case, when carriers lose quantum coherence in scattering events, the double barrier system represents two tunnel junctions separated by a classical diffusive transport region and no interference effect of the wave functions should be expected. The base thickness of the RTD must be uniform since the non-uniformity results in the resonant current ‘washout’ and reduction of the peak-to-valley current ratio. The conduction band discontinuity at the base/barrier interface cannot be too small if multiple tunneling probability peaks, and in consequence multiple resonant current peaks are required. Barrier height and the effective mass of carriers in the barrier affect also resonant energies since they determine the wave function shift at inner reflections from the barriers. Barrier thickness does not affect position of the resonant energies but influences sharpness of the resonant peak of the tunneling probability and hence the magitude of the tunnel current. 3. Silicon based double barrier material systems In general, taking into consideration the energy band diagram of a double barrier system, two kinds of RT structures can be distinguished: a) intraband or b) interband. The intraband resonant tunneling (Fig. 1a) takes place when electrons or holes tunnel between energy bands of the same kind in all three conductive regions of the quantum system. In the interband resonant tunneling, electrons tunnel between the conduction and valence bands at least in one

344


Figure 1. Resonant tunneling structures based on: a) electron intraband RT, b) interband RT, c) junction interband RT.

barrier region. The barrier can be created as an additional layer of material of the appropriate band offset, as shown in Figs. 1a and 1b, or can be electrostatically induced or formed as a junction transition region, as shown in Fig. 1c for the junction interband tunneling. The choice of the barrier material system is a key issue for developing the silicon-based RTDs due not only to requirements of physical parameters but also the need for compatibility with the conventional CMOS technology. The Si/SiO2 system would be the most natural and desirable but also other materials have been investigated. Different attempts have been undertaken to realize resonant tunneling structures under the requirement that the system is at least grown or deposited on a silicon substrate. In general, three approaches can be distinguished: 1) the material of the barrier layer is different than SiO2, 2) the RTD is based on the Si/SiGe heterostructure, 3) the RTD is based on the Si/SiO2 heterostructure. Given that the III/V semiconductors are established as a powerful technology for fabrication of resonant tunneling devices, it could be that a good route is to deposit them onto a silicon substrate. Such an approach has been successfully applied6 to fabricate an RT diode with AlAs barriers and In(Ga)As quantum well with electrodes grown on a silicon substrate, covered before by the InP quasi-substrate and the low temperature InAlAs buffer layer. A clear NDR effect with PVCR of 2 at room temperature was observed. One of the earliest attempts to observe the resonant tunneling effect in a structure grown on a silicon substrate was presented in7, where silicon nitride played the role of barrier layer and an amorphous silicon layer as a quantum well. No NDR effect was observed at 77 K, but current bumps at voltages corresponding to calculated resonant energies, confirmed a contribution due to resonant tunneling. Successful observation of the NDR effect at room temperature was reported for a transistor structure with a triple barrier resonant tunneling system8, where calcium fluoride was used as a barrier layer. This material has a fluorite lattice structure well-matched to the silicon lattice. The band offset at the Si/CaF2 interface is equal to 2.9 eV, nearly the same as for the Si/SiO2 system. The metallic CoSi2 layer was deposited as the quantum well region. High PVCR with a clear effect of the third electrode was observed.


345

The successful use of CaF2 as a barrier layer has encouraged other attempts to fabricate resonant tunneling structures with this material. In9, amorphous silicon was deposited as a quantum well layer. The NDR effect with PVCR of 3.1 at room temperature was observed but only with the use of the pulsing measurement technique, probably due to large scattering and trapping in the amorphous silicon. The most successful result using CaF2 as a barrier layer was reported in10. The 0.9 nm thick crystalline CaF2 layer was grown on a silicon substrate and the crystalline 3.7nm–thick CdF2 was deposited as the quantum well layer. The observed record PVCR of the order 105 at room temperature, confirmed CaF2/CdF2 as a very promising material system for fabrication of resonant tunneling devices on silicon substrates. Aluminum oxide has been also investigated as a barrier layer in the RT diode on a silicon substrate11. The obtained PVCR was equal to 26 at room temperature. Another idea to fabricate silicon based resonant tunneling devices relies on the use of Si/SiGe heterostructures. Many papers on different layer combinations have been published. In general, two main concepts are exploited: intraband resonant tunneling and interband resonant tunneling. Depending on the technology and stress/relaxation engineering, resonant tunneling of holes12,13 and electrons14,15,16,17,18 with high PVCRs has been reported. In19, a triple-barrier electron intraband resonant tunneling diode with PVCR of 7.6 at room temperature was described. The first interband resonant tunneling diode was presented by Rommel20. In general, the idea of operation of such a diode and the origin of the NDR effect is the same as in the well-known Esaki diode. It relies on tunneling of electrons from the conduction band of a highly doped n-type side of the junction to the valence band of highly doped p-type side of the junction. The delta-doping layers on both sides of the junction help to fulfill the energy band overlapping required for such a tunneling. However, a very important change is introduced if an additional SiGe layer is placed between the delta-doped planes. Due to the upward shift of the valence band edge, intermediate resonant states for tunneling are created that filter energy levels that aid transfer electrons and the tunneling probability is enhanced due to the resonant tunneling regime. Structures of this type (e.g., 21,22,23 ) have been realized with different sequences and parameters of the sandwich layers, resulting in high PVCR factors and in a very wide range of the peak current. Also, examples of successful monolithic integration with Si CMOS process to fabricate quantum functional and multi-valued logic circuits have been reported (e.g.,24,25,26) confirming that this technology can be considered to be mature for commercial applications.

346


However for the silicon technology, silicon dioxide is the most natural and well recognized insulator material, thus it would be most desirable to fabricate the resonant tunneling devices basing on the Si/SiO2 material system. Compared to Si/SiGe, the Si/SiO2 system offers much higher conduction band discontinuity. The silicon dioxide is also an excellent insulator. The fundamental limit for the SiO2 thickness to confine electrons in the Si quantum well is evaluated to about 0.5nm27 as a result of the probability washout. The practical problem results from the fact that the ultrathin crystalline silicon layer must be grown on a SiO2 layer, which is amorphous. The first attempts to observe resonant effects in a Si/SiO2 multilayer structure obtained by recrystallization of the deposited amorphous silicon has been done my Tsybeskov28. Although no NDR effect was observed, the step-like characteristics at temperature 4.2 K were interpreted as a result of hole tunneling. A similar approach to realize nanocrystalline silicon superlattices was applied to fabricate RT based memory devices29. Another idea to fabricate the Si/SiO2 based resonant tunneling structures is to produce silicon micro- or nano-crystallites embedded in SiO2 (e.g.,30,31,32,33). Different processing techniques have been used and resonant tunneling has been proposed as an explanation for current jumps observed on current-voltage characteristics. In general, it must be remembered that due to the dependence on crystallite dimensions, the current-voltage characteristic can be affected by resonant tunneling and also by Coulomb blockade. Resonant tunneling has been also observed through boron B+ states in a δ layer34 and Na+ ions embedded in the SiO2 layer35. An interesting way of fabricating an assembly of silicon nanodots between conducting electrodes patterned from the silicon-on-insulator layer was proposed in36. Owing to a good contrast between the hydrophobic surface of silicon and hydrophilic surface of silicon dioxide, the dispersion solution containing silicon nanodots has a tendency to settle between the source and drain nano-electrodes made of silicon-on-insulator layer. The dispersion solution was deposited with the use of a capillary but other deposition techniques could be developed. If the growth of a crystalline silicon layer on SiO2 presents so many problems, it seems natural to use the silicon-on-insulator layer as a quantum plane of the resonant tunneling diode. In37,38,39,40 resonant tunneling diodes were fabricated on the bonded SOI substrate with a buried oxide of thickness in the range of a few nanometers. The silicon layer was thinned to the same thickness range and thermally oxidized to obtain the second ultrathin SiO2 layer. The n+ substrate served as the emitter while the aluminum electrode was used as a collector. The measured current-voltage characteristics exhibited the peak-to-valley current ratio of 1.8 at temperature 15 K, which was the first observation of the NDR effect in the


347

SiO2/crystalline silicon/SiO2 resonant tunneling system. Although such SOI devices using the silicon substrate as an active electrode cannot be integrated in a circuit, the obtained result is very promising for the development of SOI based resonant tunneling devices. 4. Device architectures Two architecture configurations of resonant tunneling devices, shown schematically in Fig. 2, can be defined due to the dependence on the direction of tunneling in reference to the crystal substrate surface: vertical and lateral. The vertical configuration is natural for RT structures utilizing the base region obtained in the semiconductor growth or deposition processes, with a very good control of thickness. The area of the active tunneling region is defined by the lateral dimensions of the gate electrode and can be large, which is desirable. A galvanic contact to the base region can potentially lead to the RTT structure, but due to the extremely thin semiconductor layer

Figure 2. Configurations of the resonant tunneling structures: a) vertical (potentially with a galvanic contact to the base), b) lateral (potentially with a double gate control).

348


and resultant large base resistance, the RT current control by the base potential or current can be difficult. As an example, the vertical RTD configuration can be easily achieved with the use of the PAGODA separate double gate SOI architecture 41. The lateral RT structure can be realized provided the lithography resolution allows the fabrication of semiconductor quantum wells in the sub-10nm range, where ballistic transport dominates the source-to-drain current, defining the ultimate limit for the classically operating field-effecttransistor. If such patterning control of the lateral dimensions is achieved, ordinary planar FETs but also FinFETs can be exploited to build the RTT structure42,43. Figure 3 shows a single gate SOI adaptation of this concept, where the source/drain regions play the role of emitter/collector electrodes and are separated from the semiconductor body region by ultrathin barrier layers. In this architecture, the gate electrode(s) can effectively control the potential of the ultrathin base, influencing the position of the resonant levels and the output current. Theoretically, resonant tunneling in SiO2/Si based structures in the lateral architecture may be also obtained with the use of Schottky barriers at the source and drain junctions. Another possibility for the RTT utilizing the MOSFET structure is that the potential barriers are induced in the base region by a vertical electrostatic effect, if the sourcedrain channel is not completely overlapped by the gate electrode. Lateral structures with negative differential conductance (NDC) or transconductance (NDT) effects have been obtained utilizing the interband tunneling between the source/drain regions and the gate-induced body region at the surface in the field-induced interband tunneling-effect transistor (FIBTET)44. In this SOI compatible device45,46 (Fig. 4 shows the npn version) with the lateral energy band diagram schematically shown in Fig. 4b, the NDC effect results from Esaki tunneling in the emitter junction

Figure 3. Concept of the lateral SOI RTT in the planar single gate SOI technology.


349

Figure 4. The schematic structure (a) and the energy band diagram (b) of the field-induced interband tunneling-effect transistor.

surface region, but if the surface base length is shorter than 10 nm, the resonant tunneling regime can additionally affect the PVCR. 5. Theoretical simulation Theoretical simulation of resonant tunneling has had a long history but the first papers on the SiO2/Si/SiO2 structures47,48 and influence of the main design parameters has been considered quite recently49. Key issues for theoretical modeling of RTDs are the description of the scattering effect and definition of the condition determining the steady state for the floating base regime of operation. In general, the electrostatic problem requires selfconsistent solution of the set of equations consisting of Poison’s equation, two Schrödinger’s equations for electrons with the longitudinal ml = 0.916m0 and the transverse mt = 0.190 m0 effective mass and at least two Schrödinger’s equations for holes with heavy mhh = 0.537m0 and light mlh = 0.153m0 effective mass. The tunneling probability can be calculated basing on the scattering matrix based model50: Prt =

k C / m xC t E t B tC k E / m xE (1 − rE ' rB )(1 − rB ' rC ) − rE ' t B t B ' rC

2

(1)

where t, t’, r, and r’ are elements of the scattering matrices for the regions in Fig. 5, binding the forward (a) and back (b) going components of the wave functions in the emitter, base, and collector regions. The elements of the scattering matrices are calculated with the use of the transfer matrix method for a given distribution of the electrostatic potential in the structure.

350


Figure 5. Scattering matrices defined for the emitter, base, and collector regions.

If scattering is taken into account, the transition coefficients of the base matrix tB and tB’ are multiplied by (1–Psc)1/2, where Psc is the probability of scattering during one sequential transition of the electron wave function through the base: ⎛ tT ⎞ ⎟ Psc = 1 − exp⎜⎜ − ⎟ τ r ⎠ ⎝

(2)

where tT is the semi-classical transit time through the base and τr is the scattering time constant obtained50 from perturbation theory and the Fermi golden rule for energy levels in the semiconductor well. Then, the scattering probability is calculated as: (3)

PS = 1 − Prt − Rrt

where Rrt is the probability of reflection of an electron hitting the double barrier system from the emitter side: R rt = rE + t E t E '

rB + rC (t B t B '−rB rB ') (1 − rE ' rB )(1 − rB ' rC ) − rE ' t B t B ' rC

2

(4)

Figure 6 shows energy distributions of the tunneling probability without scattering (Prt0) and with scattering included (PrtS) as well as the probability of scattering PS calculated for the (n+)polySi/SiO2/ (i)Si/SiO2/(n+)polySi system with the 1nm/3nm/1nm thickness sequence and at the collectoremitter voltage VCE = 0.5V. Since the electron effective mass in silicon has two values, two ladders of the resonant levels are present. Scattering strongly reduces the resonant tunneling probability peaks, but it has also a resonant character, exhibiting probability peaks for the resonant energy levels.


351

PROBABILITY

1 10

-2

10

-4

10

-6

10

-8

10

-10

10

-12

-0.2

PS Prt0

mt PrtS

ECE

0

0.2

ml VCE = 0.5V

0.4 0.6 E - EFE [eV]

0.8

1

Figure 6. Energy distributions of the resonant tunneling probability Prt (with and without scattering) and scattering probability PS calculated50 for the polySi/SiO2/Si/SiO2/polySi structure (1nm/3nm/1nm) at VCE = 0.5 V.

The resonant tunneling current density Jrt and the scattering currents supplying noncoherent electrons to the base from the emitter SE and the collector SC can be calculated basing on the Tsu-Esaki formula1: J rt = q ∫ Prt (E x )[ N E (E x ) − N C (E x )]dE x ,

(5)

S E ,C = q ∫ PS (E x )N E ,C (E x ) dE x ,

(6)

where NE and NC are the “supply” functions in the emitter and the collector region, respectively, e.g: NE =

4πm E h

3

⎡ ⎛ E − Ex k B T ln ⎢1 + exp⎜⎜ FE ⎝ k BT ⎣⎢

⎞⎤ ⎟⎟⎥ ⎠⎦⎥

(7)

Figure 7 shows the energy distributions of the resonant tunneling current with and without scattering included and of the scattering currents. In turn, Figure 8 shows the voltage dependence of the total current density calculated for the considered structure with and without scattering.


352

2

ELECTRON CURRENT [A/cm eV]

10

5

10

1

10

-3

10

Jrt

-7

10

-11

10

-15

VCE = 0.5V

Jrt0

SE

JrtS

SeC ECE

-0.2

0

0.2

0.4

0.6

0.8

1

E - EFE [eV] Figure 7. Energy distributions of the resonant tunneling current without (Jrt0) and with (JrtS) scattering included and of scattering currents supplying electrons from the emitter SE and the collector SC. 3

without IeRT 0 scattering IC with scattering

2

ELECTRON CURRENT [A/cm ]

3x10

2x10

10

T = 300 K

3

3

0 0

0.5 1 VOLTAGE VCE [V]

1.5

Figure 8. Voltage dependence of the tunneling current without and with scattering included for the polySi/SiO2/Si/SiO2/polySi structure (1nm/3nm/1nm).


353

6. Conclusions The Si/SiGe intraband and interband RT structures are mature for applications both in SOI and bulk Si technology, offering high peak-tovalley current ratios and peak current density in a wide range. Resonant tunneling in the Si/SiO2 based double barrier system has been also observed but much effort must be devoted to develop deposition of ultrathin (

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