Wireless Communications Design Handbook Terres- Trial Mobile Interference

WIRELESS COMMUNICATIONS DESIGN HANDBOOK Aspects of Noise, Interference, and Environmental Concerns VOLUME 3" INTERFERE...

Author: Reinaldo Perez

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WIRELESS COMMUNICATIONS DESIGN HANDBOOK Aspects of Noise, Interference, and Environmental Concerns

VOLUME 3" INTERFERENCE INTO CIRCUITS

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WIRELESS COMMUNICATIONS DESIGN HANDBOOK Aspects of Noise, Interference, and Environmental Concerns

VOLUME 3: INTERFERENCE INTO CIRCUITS

REINALDO PEREZ

Spacecraft Design Jet Propulsion Laboratory California Institute of Technology

ACADEMIC PRESS San Diego London Boston New York Sydney Tokyo Toronto

This book is printed on acid-free paper. @

Copyright 9 1998 by Academic Press All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher.

ACADEMIC PRESS 525 B Street, Suite 1900, San Diego, CA 92101-4495, USA http ://www.apnet.com

Academic Press 24-28 Oval Road, London NW1 7DX, UK http ://www.hbuk.co.uk/ap/

Library of Congress Cataloging-in-Publication Data Perez, Reinaldo. Wireless communications design handbook : aspects of noise, interference, and environmental concerns / Reinaldo Perez. p. cm. Contents: v. 1. Space interference m v . 2. Terrestrial and mobile interference m v . 3. Interference into circuits. ISBN 0-12-550721-6 (volume 1); 0-12-550723-2 (volume 2); 0-12-550722-4 (volume 3) 1. Electromagnetic interference. 2. Wireless communication systems--Equipment and supplies. I. Title. TK7867.2.P47 1998 98-16901 621.382' 24-dc21 CIP Printed in the United States of America 98 99 00 01 02 IP 9 8 7 6 5 4 3 2 1

Contents

Acknowledgments Preface Introduction

Chapter 1 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12

Chapter 2 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11

ix xi xv

Noise Interactions in High-Speed Digital Circuits Introduction Microstrip Configuration Crosstalk in the Time Domain Power Distribution Decoupling Capacitance Effects Power Dissipation in TTL and CMOS Devices Thermal Control in Equipment and PCB Design Lossy Transmission Lines and Propagation Delays VLSI Failures and Electromigration Interference Concerns with Connectors Ground Loops and Radiated Interference Solving Interference Problems in Connectors The Issue of Vias

1 3 11 14 17 21 22 32 35 40 43 47 50

Noise and Interference Issues in Analog Circuits

52

Basic Noise Calculation in Op-Amps Op-Amp Fundamental Specifications Input Offset Voltage The Noise Gain of Op-Amps Slew Rate and Power Bandwidth of Op-Amps Gain Bandwidth Produced Internal Noise in Op-Amps Noise Issues in High-Speed ADC Applications Proper Power-Supply Decoupling Bypass Capacitors and Resonances Use of Two or More Bypass Capacitors Designing Power Bus Rails in Power/Ground Planes for Noise Control

52 55 61 63 63 65 65 69 72 76 81 83

vi

Contents 2.12 2.13 2.14 2.15

Chapter 3

3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.23 3.24 3.25 3.26 3.27

Chapter 4

4.1 4.2 4.3 4.4

The Effect of Trace Resistance ASIC Signal Integrity Issues (Ground Bounce) Crosstalk through PC Card Pins Parasitic Extraction and Verification Tools for ASICs

87 94 98 100

Noise Issues in High-Performance Mixed-Signal ICs and Other Communications Components

103

Analog-to-Digital Converter Noise Driving Inputs in ADCs Filtering the Switching-Mode Power Supply Capacitor Choices for Noise Filtering The Use of Ferrite Cores in Switching-Mode Power Supplies Shielding Cables of Op-Amp Inputs to Avoid Interference Coupling RFI Rectification in Analog Circuits Op-Amps Driving Capacitive Loads Load Capacitance from Cabling Intermodulation Distortion Phase-Locked Loops Voltage-Controlled Oscillators VCO Phase Noise Phase Detectors Basic Topology of a Phase-Locked Loop Phase Noise in DC Amplifiers Phase Noise in High-Frequency Amplifiers Phase Noise in Phase Detectors Phase Noise in Digital Frequency Dividers Phase Noise in Frequency Multipliers Phase Noise in Oscillators Phase Noise in Reference Frequency Generators More about VCO Design and Noise Modeling RF Interference at the Transistor Level RFI Effects on Digital Integrated Circuits RFI Effects in Operational Amplifiers RFI-Induced Failures in Crystal Oscillators

103 108 117 118 124 131 135 140 143 145 148 151 156 159 160 169 169 169 170 170 170 171 171 173 184 189 190

Computational Methods in the Analysis of Noise Interference

General Introduction The Method of Moments in Computational Electromagnetics High-Frequency Methods in Computational Electromagnetics The Finite-Difference Time Domain in Computational Electromagnetics 4.5 The Finite Element Method in Computational Electromagnetics 4.6 The Transmission-Line Method in Computational Electromagnetics 4.7 Computational Methods at Work: Getting Numbers from Your Models

194 194 200 237 265 279 291 307

Contents Chapter 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19

Antennas for Wireless Personal Communications

Radiation from Current Sources Thin-Wire Antennas The Linear Dipole Simplest Current Distribution in Wire Dipoles Sinusoidal Current Distribution in Wire Dipoles The Generalized Thin-Wire Loop Antenna The Simplest Small Loop The Square Loop Antenna Microstrip Antennas Array Theory Planar Arrays Mutual Coupling among Array Elements Reflector Antennas Offset Parabolic Reflectors Helical Antennas Designing a Quadrifilar Helix Antenna Numerical Methods in Loop Antenna Design Using MOM for Designing Cylindrical Arrays for PCS Simulation of Portable UHF Antennas in the Presence of Dielectric Structures 5.20 Other Wire-Type Antennas for Portable Communications 5.21 Modeling a Monopole Mounted on a Moving Car Index

vii 354 354 356 358 360 361 361 366 367 369 375 380 381 383 386 390 396 402 407 412 416 416 422


Acknowledgments I would like to acknowledge the cooperation and support of Dr. Zvi Ruder, Editor of Physical Sciences for Academic Press. Dr. Ruder originally conceived the idea of having a series of three volumes to properly address the subject of noise and interference concerns in wireless communications systems. Considerable appreciation is extended to Madeline Reilly-Perez who spent many hours typing, organizing, and reviewing this book.

ix


Preface

Before the dawn of the digital age, about 25 years ago, when analog electronics was still in a commanding lead, the only interference problems of concern involved transmitters and receivers, in which spurious sidebands from a given transmitter coupled to a sensitive receiver whose bandwidth was wide enough to receive the unintentional radiation. As the digital age took off in the 1970s, the interference problems started to shift more and more to the electronic components level and PCB; analog and digital circuits were now coexisting with each other, and noise coupling between them started to appear. Furthermore, as the clock frequencies of digital circuits started to increase in the 1980s and 1990s, the interference problems between analog and digital circuits and among digital circuits themselves became even more pronounced: the multiple harmonics unintentionally generated by the clocked circuits now extended all the way to the gigahertz range, exposing the susceptibility of many circuits to these high frequencies. It was then, really out of necessity, that digital designers started to pay more attention to the "analog effects" of their digital design, and analog designers started thinking about ways to protect their highly susceptible components from digital interference and noise while improving performance. Designing electronic components and circuits that are highly immune to interference problems became a necessary goal. In many cases noise and interference control in personal communications services has to be dealt with eventually at the most fundamental level of electronics components. We can spend considerable resources at the system and subsystem level to remedy an interference problem that has surfaced in a given wireless communications scenario, and still come out empty-handed, meaning that the problem is still present. We have concentrated only on the periphery of the problem, and perhaps even tried to eliminate some of the symptoms, but the interference problem is still there. Why? Because it needs to be addressed and solved at the electronic component level. In this volume we provide the electronic designer (both digital and analog) with an introduction to the fundamentals of noise control in electronic design. This is indeed a vast field of research at many places, and there is still new xi

xii

Preface

territory to be discovered as we try to understand the physics of interference phenomena--a subject that is often difficult to address because it is embedded in electromagnetic theory. We have decided in this book to combine simple steps with more complicated steps in the identification and solution of interference problems, and to provide a fundamental knowledge of the physics of such interference cases, which the engineer can later use to optimize the design. This volume looks at noise issues in digital circuits, analog circuits, mixedsignal analog and digital circuits, and computational methods commonly used in the analysis of interference problems. It also provides a good introduction to the design of the most commonly used types of antennas in wireless communications. In the analysis of interference issues concerning digital logic, the basic factors that contribute to such interference are outlined: crosstalk in the time domain, power distribution models in TTL and CMOS devices, thermal control and the effects of thermal analysis in assessing the reliability of sensitive components, lossy transmission lines and the role of such transmission lines in the propagation delay of signals, electromigration mechanisms, and ground loops and interference consequences. We also look at noise problems arising from interfaces such as connectors and cables. ASIC and FPGA signal integrity issues (e.g., ground bounce) and methods for parasitic extraction and verification are briefly discussed. In the analysis of interference issues concerning analog circuits, the emphasis is on circuits involving operational amplifiers (op-amps). For example, we cover basic noise calculations in op-amps, input offset voltage when that offset is caused by a noise source, noise gains in op-amps, and slew rate and power bandwidth of op-amps. Internal noises in op-amps are discussed, but also in conjunction with high-speed analog-to-digital converter applications. Considerable space is given to the subject of proper bypass capacitance for analog circuits, especially analog-to-digital converters. Power bus rail design and the design of power/ ground planes are also covered. In the analysis of interference issues concerning mixed-signal ICs, a great number of subjects are discussed. For example, a more detailed look is given to analog-to-digital converters, switching mode power supplies, and the need for filtering and shielding. Radio frequency interference and the effects of intermodulation distortion are briefly covered. We also cover phase noise in most of the commonly used components of communications, such as VCO, phase detectors, PLL, DC/HF amplifiers, oscillators, frequency dividers, generators, and multipliers. An important section addresses the direct effects of radio frequency interference in transistors and digital ICs. We thus provide analytical approaches to the study, analysis, and correction of many interference problems in electronic components. However, this volume

Preface

xiii

also dedicates considerable effort to introducing computational electromagnetic methods for the analysis of interference problems that can be modeled from Maxwell equations. Several numerical techniques are discussed in detail to provide readers with good foundations in these methods. The theoretical aspects of these methodologies are put into practice in a discussion of the modeling of a wireless communications antenna. The last part of this volume discusses in detail most of the antennas commonly used in wireless communications services, from simple wire antennas to parabolic reflectors. The material learned concerning computational methods is applied in this area for the design of cylindrical arrays in PCS, portable UHF antennas, quadrafilar helix antennas, and diverse kinds of monopoles. The student should see this volume as a good introduction to issues of noise in analog and digital electronic systems, and to some methods of improving design techniques that will increase the immunity of wireless communications systems to interference problems. We wish to acknowledge the valued contribution of Madeline Reilly-Perez in the typing and editing of this manuscript.


Introduction

The information age, which began its major drive at the beginning of the 1980s with the birth of desktop computing, continues to manifest itself in many ways and presently dominates all aspects of modem technological advances. Personal wireless communication services can be considered a "subset technology" of the information age, but they have also gained importance and visibility over the past 10 years, especially since the beginning of the 1990s. It is predicted that future technological advancements in the information age will be unprecedented, and a similar optimistic view is held for wireless personal communications. Over the past few years (since 1994), billions of dollars have been invested all over the world by well-known, technology-driven companies to create the necessary infrastructure for the advancement of wireless technology. As the thrust into wireless personal communications continues with more advanced and compact technologies, the risks increase of "corrupting" the information provided by such communication services because of various interference scenarios. Although transmission of information through computer networks (LAN, WAN) or through wires (cable, phone, telecommunications) can be affected by interference, many steps could be taken to minimize such problems, since the methods of transmitting the information can be technologically managed. However, in wireless communications, the medium for transmission (free space) is uncontrolled and unpredictable. Interference and other noise problems are not only more prevalent, but much more difficult to solve. Therefore, in parallel with the need to advance wireless communication technology, there is also a great need to decrease, as much as possible, all interference modes that could corrupt the information provided. In this handbook series of three volumes, we cover introductory and advanced concepts in interference analysis and mitigation for wireless personal communications. The objective of this series is to provide fundamental knowledge to system and circuit designers about a variety of interference issues which could pose potentially detrimental and often catastrophic threats to wireless designs. The material presented in these three volumes contains a mixture of basic interference fundamentals, but also extends to more advanced XV

xvi

Introduction

topics. Our goal is to be as comprehensive as possible. Therefore, many various topics are covered. A systematic approach to studying and understanding the material presented should provide the reader with excellent technical capabilities for the design, development, and manufacture of wireless communication hardware that is highly immune to interference problems and capable of providing optimal performance. The present and future technologies for wireless personal communications are being demonstrated in three essential physical arenas: more efficient satellites, more versatile fixed ground and mobile hardware, and better and more compact electronics. There is a need to understand, analyze, and provide corrective measures for the kinds of interference and noise problems encountered in each of these three technology areas. In this handbook series we provide comprehensive knowledge about each of three technological subjects. The three-volume series,

Wireless Communications Design Handbook: Aspects of Noise, Interference, and Environmental Concerns, includes Volume I, Space Interference; Volume II, Terrestrial and Mobile Interference; and Volume III, Interference into Circuits. We now provide in this introduction a more detailed description of the topics to be addressed in this handbook.

Volume 1 In the next few years, starting in late 1997, and probably extending well into the next century, hundreds of smaller, cheaper (faster design cycle), and more sophisticated satellites will be put into orbit. Minimizing interference and noise problems within such satellites is a high priority. In Volume 1 we address satellite system and subsystems-level design issues which are useful to those engineers and managers of aerospace companies around the world who are in the business of designing and building satellites for wireless personal communications. This material could also be useful to manufacturers of other wireless assemblies who want to understand the basic design issues for satellites within which their hardware must interface. The first volume starts with a generalized description of launch vehicles and the reshaping of the space business in general in this post-Cold War era. A description is provided of several satellite systems being built presently for worldwide access to personal communication services. Iridium, Globalstar, Teledesic, and Odessey systems are described in some detail, as well as the concepts of LEO, MEO, and GEO orbits used by such satellite systems.

Introduction

xvii

Attention is then focused briefly on the subject of astrodynamics and satellite orbital mechanics, with the sole objective of providing readers with some background on the importance of satellite attitude control and the need to have a noise-free environment for such subsystems. Volume 1 shifts to the study of each spacecraft subsystem and the analysis of interference concerns, as well as noise mitigation issues for each of the satellite subsystems. The satellite subsystems addressed in detail include attitude and control, command and data handling, power (including batteries and solar arrays), and communications. For each of these subsystems, major hardware assemblies are discussed in detail with respect to their basic functionalities, major electrical components, typical interference problems, interference analysis and possible solutions, and worst-case circuit analysis to mitigate design and noise concerns. Considerable attention is paid to communications subsystems: noise and interference issues are discussed for most assemblies such as transponders, amplifiers, and antennas. Noise issues are addressed for several multiple access techniques used in satellites, such as TDMA and CDMA. As for antennas, some fundamentals of antenna theory are first addressed with the objective of extending this work to antenna interference coupling. The interactions of such antennas with natural radio noise are also covered. The next subject is mutual interference phenomena affecting space-borne receivers. This also includes solar effects of VHF communications between synchronous satellite relays and earth ground stations. Finally, satellite antenna systems are discussed in some detail. The final section of Volume 1 is dedicated to the effects of the space environment on satellite communications. The subject is divided into three parts. First, the space environment, which all satellites must survive, is discussed, along with its effects on uplink and downlink transmissions. Second, charging phenomena in spacecraft are discussed, as well as how charging could affect the noise immunity of many spacecraft electronics. Finally, discharging events are investigated, with the noise and interference they induce, which could affect not only spacecraft electronics, but also direct transmission of satellite data.

Volume 2 In the second volume of this handboook series, attention is focused on systemlevel noise and interference problems in ground fixed and mobile systems, as well as personal communication devices (e.g., pagers, cellular phones, two-way radios). The work starts by looking at base station RF communications systems and mutual antenna interference. Within this realm we address interference be-

xviii

Introduction

tween satellite and earth station links, as well as interference between broadcasting terrestrial stations and satellite earth stations. In this approach we follow the previous work with a brief introduction to interference canceling techniques at the system level. Volume 2 devotes considerable space to base-station antenna performance. We address, in reasonably good technical detail, the most suitable antennas for base-station design and how to analyze possible mutual interference coupling problems. The book also gives an overview of passive repeater technology for personal communication services and the use of smart antennas in such systems. A section of Volume 2 is dedicated entirely to pagers and cellular phones and interference mitigation methods. The fundamentals of pagers and cellular phone designs are studied, and the use of diversity in antenna design to minimize interference problems is reviewed. A major section of this volume starts with the coverage of propagation models for simulating interference. In this respect we cover Rayleigh fading as it relates to multipath interference. Path loss, co-channel, and adjacent channel interference follows. This last material is covered in good detail, since these techniques are prevalent in the propagation models used today. The last sections of Volume 2 deal in depth with the subject of path loss, material that needs better coverage than found in previous books. The following subjects are reviewed in detail: ionospheric effects, including ionospheric scintillation and absorption; tropospheric clear-air effects (including refraction, fading, and ducting); absorption, scattering, and cross-polarization caused by precipitation; and an overall look at propagation effects on interference.

Volume 3 In Volume 3, we focus our attention inward to address interference and noise problems within the electronics of most wireless communications devices. This is an important approach, because if we can mitigate interference problems at some of the fundamental levels of design, we could probably take great steps toward diminishing even more complex noise problems at the subsystem and system levels. There are many subjects that could be covered in Volume 3. However, the material that has been selected for instruction is at a fundamental level and useful for wireless electronic designers committed to implementing good noise control techniques. The material covered in Volume 3 can be divided into two major subjects: noise and interference concerns in digital electronics, including mitigation responses; and noise and interference in analog electronics,

Introduction

xix

as well as mitigation responses. In this volume we also address computational electromagnetic methods that could be used in the analysis of interference problems. In the domain of digital electronics we devote considerable attention to power bus routing and proper grounding of components in printed circuit boards (PCBs). A good deal of effort is spent in the proper design of power buses and grounding configurations in PCBs including proper layout of printed circuit board traces, power/ground planes, and line impedence matches. Grounding analysis is also extended to the electronic box level and subsystem level, with the material explained in detail. At the IC level we concentrate in the proper design of ASIC and FPGA to safeguard signal integrity and avoid noise problems such as ground bounce and impedance reflections. Within the area of electronic design automation (EDA), parasitics and verification algorithms for ASIC design are also discussed. A great deal of effort is put into the study of mitigation techniques for interference from electromagnetic field coupling and near-field coupling, also known as crosstalk, including crosstalk among PCB card pins of connectors. The work continues with specific analysis of the interactions in high-speed digital circuits concerning signal integrity and crosstalk in the time domain. Proper design of digital grounds and the usage of proper bypass capacitance layout are also addressed. Other general topics such as power dissipation and thermal control in digital IC are also discussed. Electromagnetic interference (EMI) problems arising in connectors and vias are reviewed extensively, including novel studies of electromigration in VLSI. In the analog domain, Volume 3 also addresses many subjects. This section starts with the basics of noise calculations for operational amplifiers. Included here is a review of fundamentals of circuit design using operational amplifiers, including internal noise sources for analysis. As an extension concerning noise issues in operational amplifiers, the material in this volume focuses on the very important subject of analog-to-digital converters (ADCs). In this area considerable effort is dedicated to proper power supply decoupling using bypass capacitance. Other noise issues in high-performance ADC are also addressed, including the proper design of switching power supplies for ADC, and the shielding of cable and connectors. Finally, at the IC level, work is included for studying RFI rectification in analog circuits and the effects of operational amplifiers driving several types of capacitive loads. We end this volume with the study of system-level interference issues, such as intermodulation distortion in general transmitters and modulators, and the subject of cross modulation. This is followed by the concept of phase-locked loops (PLL) design, development, and operation. Because of the importance of

xx

Introduction

PLL in communications electronics, considerable space is devoted to the study of noise concerns within each of the components of PLL. Finally, Volume 3 ends with an attempt to explore interference at the level of transistors and other components.

Errata

Wireless Communications Design Handbook: Volume 3

Reinaldo Perez

Page 175, Figure 3.69; page 178, Figure 3.72; page 180, Figure 3.74; page 181, Figure 3.75; page 191, Figure 3.83: J. Tron, J. J. Whalen, C. E. Larson, and J. M. Roe, "Computer-aided analysis of RFI effects in operational amplifiers," IEEE Trans. in EMC, Voi. 21, No. 4, 9 1979 IEEE. Page 126, Figure 3.25, and page 127, Figure 3.26: Reprinted with permission from Electronic Design, September 5, 1995. Copyright 1995, Penton Publishing Co.


Chapter 1

1.0

Noise Interactions in High-Speed Digital Circuits

Introduction

Several years ago, when TTL logic was still the predominant player in digital design, the analog effects of chip-to-chip interactions were a minor consideration. In today's IC design, the high-speed logic families make the printed circuit board look like transmission lines. Digital designers must become familiar with a series of high-speed effects in PCBs, such as transmission lines stubs, interlayer vias, voltage reflections caused by mismatches, conductor geometry, and printed-board dielectric effects. Designing high-speed logic requires a working strategy to correlate the speed of the system architecture and the interconnect integration level. To minimize interconnect performance, the following goals should be achieved: 1. Minimize ringing (mismatch reflection) when high-speed signals propagate through impedance discontinuities (such as comers, stub junctions, pins, vias, unmatched loads). 2. Diminish crosstalk between nearby signal lines. This can be achieved by separating the lines and minimizing signal-to-ground distances. 3. Reduce interconnect delays between chips by using the closest path between ICs. 4. Use high interconnect DC resistance and high dielectric loss effect at gigahertz frequencies in order to minimize edge degradations. 5. Minimize power and ground noise by decreasing the impedance of power distribution systems. Use plenty of decoupling capacitors and many power and ground planes. 6. Minimize voltage transition by using proper termination impedance. Improper impedance terminations could result in voltage transitions that are insufficient to develop a logic level transition. 7. Minimize the capacitance loading on signal lines to obtain the largest characteristic impedance and smallest propagation delay.

2

1. Noise Interactions in High-Speed Digital Circuits

As system complexity increases there is a need for automated CAE tools that would optimize the design using some of these findings, as shown in Figure 1.1. The developed EDA tools should be coupled with design guidelines and methodologies to handle the thousands of interconnections in a PCB. Desirable capabilities for such an integrated EDA tool include the ability to perform parasitic effect analysis and prediction, modeling, and simulation of physical geometries. One of the most important parameters in the design of PCBs, which has a direct effect on the electrical performance of the interconnection, is the relative dielectric constant e r. The term e r is used in the design of the interconnecting media, in the calculation of impedance, capacitance, and time propagation. In a transmission line the propagation time is proportional to the square root of e r, and impedance will vary inversely as the square root of er. A useful term often

IC Design Flow Physical Flow

Function Simulation t

Modeling Flow VHDL/Verilog

"'-.. Specified Analog Models

Synthesis /

II,"

T

Timing Analysis VHDL/Verilog

Gate Level Simulation

~r Analog Behavioral Models

Place-and-Route

Parasitic Extraction

Physical Timing Simulation

SPiCE-like Tools

Figure 1.1 IC design flow which accounts for analog effects.

SPICE Models

1.1. Microstrip Configuration

3

given is the effective relative permittivity (e~) which is the permittivity experienced by a signal as it is transmitted along a conductive path. Let us consider some typical electrical configurations of PCBs in which e r plays an important role.

1.1 Microstrip Configuration The microstrip configuration is shown in Figure 1.2a. An empirical relationship is available that gives the effective relative expression e; = 0.475e r + 0.67

for

2

- 0.5tr(m) = 0"5[trd(SeC)c(m/sec)]

(1.5)

4


Figure 1.2 Typical configuration of a microstrip line.


5

where tr (m) is the rise time in question, trd (sec) is the device rise time, c is the speed of light and e~ is the effective relative permittivity. For conductor length L (m) greater than 0.5tr, the reflection from a mismatched load impedance will be received back at the source after the pulse has reached its maximum value. In high-speed digital design it is not uncommon for the clock cycle time to be smaller than the propagation time td from one device to another. For a system to perform properly, the propagation time td must be well controlled. When the signal line is considered to be capacitive, then the propagation time is calculated using the assumption that the loads and the line connecting these lines are purely capacitive. The propagation delay time of a signal transmitted through a conductor is given by to -

.

(1.6)

C

The characteristic impedance Z o of a line is also important in printed circuit boards. The amount of current that a circuit driven will need to supply along a path depends on the characteristic impedance value. The value of Z 0 is also important in the design of integrated circuits, since it can affect the location of receiver IC along a circuit in a PCB. The characteristic impedance for an ideal microstrip transmission line as shown in Figure 1.2 is given by 60 Zo = ~ In

in ohms,

(1.7)

or it can also be expressed as Zo = 87 l n [ ~ ]

/(er

+ 1.41) 0.5

in ohms,

(1.8)

where er is the relative permittivity of the material between the wire and the reference ground plane. Notice that in the preceding equations we have to transform the rectangular cross-section of a microstrip line of width W and thickness t into a round wire using the expression d = 0.670W [0.8 + t / W].

(1.9)

Combining these equations gives us the impedance Z o and intrinsic line capacitance C o for microstrip circuitry, Z o = 87 In

[ 5"98h]/(er+l.41)~ ( 0 . 8 W + t)

C o = 0.67(e r + 1.41) / ln(5.98h / (0.8W + t)),

(ohms),

(110)

(pF/inch),

(1.11)

6


for W/h < 1.0 where h is the dielectric thickness, W is the conductor width, and t is the conductor thickness. For coated microstrip transmission lines (Figure 1.3), the preceding two equations can be used if a modified effective relative permittivity is used as given by /3~ =

/3r [1 +

e(-l55*h'/h)].

(1.12)

For striplines the characteristic impedance Z o and intrinsic line capacitance C O for a fiat conductor geometry are given by Z o = 60 l n [ 1 . 9 ( ~ ) / ( 0 . 8 W

+ t)]/X/~er

C o = [1.41Xer] / ln(3.81h / (0.8W + t)

(ohms),

(pF/inch) for W / h

(1.13) < 2.

Finally, for the dual stripline the characteristic impedance Z o and intrinsic line capacitance Co are given by

(0.8W + t)

4(h + t + c)

C O = 2.82 9 ~ ln[2(h - t) / (0.268W + 0.335t)]

' (pF/inch),

where h c t W h'

= = = = =

distance from signal layer to reference plane distance between signal layers signal conductor thickness signal conductor width. distance from reference plane to top of dielectric

Figure 1.3

Embedded or coated microstrip line.

(1.14)


7

Dual striplines have the advantage that such conductors on one layer are generally routed orthogonally to those on the other layer, keeping crosstalk to a minimum. 1.1.1

MINIMUM LOAD SEPARATION

This is defined as the minimum distance at which reflection from load in a transmission line begins to affect other adjacent loads. Let us consider Figure 1.4, which addresses the capacitive effect in loads and transmission lines. Each of the loads and all the associated capacitances will reflect a portion of the incident pulse back to the source. We look for a minimum separation distance between the loads (Lmin) such that the reflected pulses will not add up constructively to diminish the contribution from the original signal pulse. The minimum distance is given by tmin

(1.15)

- - 0 . 8 5 tr ,

td

where tr - 10% to 90% of the edge transmission rate (nsec) t d = unloaded line propagation delay (nsec/inch). For example, for a 54SXX IC with an edge transition time of 3.0 nsec and an FR-4 line propagation of t d = 0.148 nsec/inch, Lmin = 17.2 inches, which means

,,.._ Incident

Lmin _1_

m

CT L

Reflected CTL = transmission line capacitance CL = load capacitance

_1_

~ Figure 1.4

CTL

Capacitive effects in loads and transmission lines.

8


that if the separation between the loads is greater than this, the reflected signals will overlap and diminish the amplitude of the incoming signal. Most often, however, we find distributed loads as shown in Figure 1.5. In such cases the transmission line is such that the separation between loads is less than the minimum separation distance Lmin. The effective capacitance per unit length experiences an overall increase, and so does transmission line capacitance:

CT = riCE (1.16)

CTotal-- dLCT L

1 Z0 --

CTotal (1 + CT / CTotal)

] "

Here, CT is the total load capacitance, CTota1 is total line capacitance, Z 0 is the unloaded line impedance, and L T is the total line inductance.

Z; -- Z 0 / ~/(1 -k- C T/fTotal)

(1.17)

is the loaded line impedance. The loaded propagation delay time (tdL) per unit length is given by tdL - td [ 1 + CT / CTotal]0"5.

(1.18)

Even when reflections are not additive, glitches will still form as a result of the reflected pulse, as shown in Figure 1.6. The reflective pulse amplitude is given by

VR - CLZoVo/ 2tt,

-

~'

CTL

CTL = transmissionlinecapacitance CL = loadcapacitance

_L

, ~ cTL

CTL Figure 1.5

Capacitive effects in transmission lines and distributed loads.

(1.19)


Zo

I ' ~ CTL CTL = transmission line capacitance CL = Load capacitance

Figure 1.6 Reflections in capacitive loaded lines.

where t t is the edge transition time. If the load has a resistance R E of significant value, an additional delay must be added to that of Equation (1.19) to give tT = tdL + RLZoCL /(R E + Zo).

(1.20)

One important aspect of time delays is in radial loads. Radial loading occurs if multiple lines diverge from a common point on a line. The divergence point can be located anywhere along the transmission line. Radial lines offset the propagation in a transmission line by developing an impedance Znet, given by Zne t =

Z~

(1.21)

n

where Z o is the characteristic impedance of each radial line (we are assuming each radial line has the same characteristic impedance) and n is the number of radial lines. Let us consider Figure 1.7. The number of radial loads (three as shown in Figure 1.7) divided by the main line length (n/dm) will provide maximum loading density, and this magnitude defines the maximum number of loads per unit length that will maintain Z o above the minimum predefined magnitude. Usually, d m is the distance between the driver and the most distant load. -

] Co

1/ _1 CT"

For example, in Figure 1.7, d m = 22 inches (main line length) C o = 4.0 pF/inch (line capacitance per unit length = CTL) CL = 10.0 pF 10 inches; dnet2 t d = 0.15 nsec/inch

dnetl

--

Z o = 50 ohms.

'-

8 inches;

dnet3

--

6 inches

(1.22)

10


NET1

[ DRIVER

dNetl

I dm

r".'-

dNet3 .,~-~ -

I

NET3 I I

~

- Fb L ~ I

dNe~. - -

I t I --I~

I NET2

Figure 1.7

Effect of radial lines on propagation through a transmission line.

Using Equation (1.16): Cx(main) = nC L = (5)(10.0 nF) = 50 pF Cx(netl) = nC L = (2)(10.0 nF) = 20 pF Cx(net2) = nCL = (2)(10.0 nF) = 20 pF Cx(net3) = nCL = (1)(10.0 nF) = 10 pF. Using Equation (1.16): Ctotal(main) = dLCTL = dmC0 = (22 inches)(4.0 pF/inch) = 88 pF Ctota](netl) = dLCTL = dmCo = (10 inches)(4.0 pF/inch) = 40 pF Ctotal(net2) = dLCTL = dmCo = (8 inches)(4.0 pF/inch)

= 32 pF

Ctotal(net3) = dLCTL = dmCo = (6 inches)(4.0 pF/inch)

= 24 pE

Using Equation (1.17): Z~ = (main) = Z 0 / %/1 + C T / CTota 1 -- 50 / V/1 + 50 pF / 88 pF = 41.2 ohms Z~ = (main) = Z 0 / %/1 + C T / CTota 1 = 50 / V / 1 + 20 pF / 40 pF = 42 ohms Z D = (main) = Z o / %/1 + Ca- / CTota 1 = 5 0 / V / 1 + 20 pF 132 pF = 39.2 ohms Z~ = (main) = Z o / V ' I + CT / CTotal = 5 0 / g / 1'"'nL l 0 pF / 24 pF = 42 ohms.

I I

]

1.2. Crosstalk in the Time Domain

11

The parallel impedance between Z~(main) and Z~(netl) is given by Zol (parallel) =

(41.2)(42.0) (41.2) + (42.0)

= 20.8 ohms,

and for the other nets we have Zo2(parallel ) =

(41.2)(39.2) = 20.1 41.2 + 39.2

Zo3(parallel ) =

(41.2)(42.0) = 20.7. 41.2 + 42.0

Using Equation (1.18): toE(main) = td[1 + CT / CTotal] 0"5 = 0.15 nsec/inch[1 + 50 / 80] 0.5 = 0.18 nsec/inch tdL(net 1) = td[1 + CT / CTotal] 0"5 = 0.15 nsec/inch[1 + 20 / 40] 0.5 = 0.18 nsec/inch tdL(net2) - to[1 + C T [ CTotal] 0"5 = 0.15 nsec/inch[1 + 20 / 32] 0.5 = 0.19 nsec/inch tdL(net3) = td[1 + C T [ CTotal] 0"5 = 0.15 nsec/inch[1 + 10 / 24] 0.5 = 0.17 nsec/inch. The total propagation delays are given by td(main total) = (22 inches)(tdL(main)) = (22 inches)(0.18 nsec/inch) 3.96 nsec td(netl total) = (10 inches)(toL(net 1)) = (10 inches)(0.18 nsec/inch) 1.8 nsec td(net2 total) = (8 inches)(tdL(net2)) = (8 inches)(0.19 nsec/inch) 1.52 nsec td(net3 total) = (6 inches)(toL(net3)) = (6 inches)(0.17 nsec/inch) 1.02 nsec m

1.2

Crosstalk in the Time Domain

The subject of crosstalk for transmission lines in the time domain is next. We now address a more simplified approach concerning crosstalk in the time domain for simple microstrip lines in the PCB. The noise caused by crosstalk is created by the adjacent signals from active lines to passive lines. The crosstalk happens

12


when the lines are close enough so as to have mutual capacitance Cm and mutual inductance L m as shown in Figure 1.8. For a microstrip line length that is greater than 2t d, the forward and backward crosstalk coefficients Kf and K b are given by (K L - K c) C o Zo (KL + K c) / 4t d,

(1.23)

Kf -- 0.5C o Z o

Kb

=

where K L = 0.55 exp { - ( A 2 9% + B 2 9w/4,)} Kc = 0.55exp { - ( A 1 . % A1 =

+B 1.%)}

1 + 0.251n[ e r +1 1 2

A 2 = 1 + 0.25 ln[/x r + 1)/2] B 1 = 0.1 ( 8 r nt- 1) ~ B2

--

d -

0 . 1 (/.z r +

1) 0.5

line spacing.

For an embedded microstrip transmission line, the crosstalk equations are the same as those given for microstrip lines in Equation (1.23) except that e r is substituted for e'r given by the equation g"r -- g'r [1 +" e ( - 1.55h'/h)].

(1.24)

For the stripline environment, the forward crosstalk is zero (K L = Kc); however, the backward crosstalk is twice the equivalent microstrip crosstalk in which the impedances are the same and the capacitances are twice as large. Two other formulas of importance are the crosstalk for inductive and capacitive coupling (see Figure 1.8): Crosstalk =

RLCm

and

Crosstalk = Lm

tr

(1.25)

Rst r "

The terms C m and L m can be calculated analytically within uncertainty by using 2

m-0002,4 [, +

]

126,

and 2

0 7Linches, Cm =

ln[1 + 2

pF

1.2. Crosstalk in the Time Domain

13

(a)

l

[;>-

+

DRIVERS (b) Rs Ivvx,

\

vs Lm

?

/

ZO Rout ~-

Cm

70

I

L Figure 1.8

~RL

(a) Physical representation of two circuits in a crosstalk scenario, separated by a distance d. (b) Mutual capacitance and inductance in PCB microstrip lines.

where h is the height above ground plane, s is the separation between wires, and L is the length of wires in inches, er(ef0 is the effective dielectric constant and r is the wire radius. We can use equation 1.9 to convert flat conductions into round wires for usage of equations (1.25) and (1.26) or through measurements, which would give equations such as (Area of coupled noise impulse)R s Lm =

AV

(1.27)

14


and (Area of coupled noise impulse) C m

-

RLAV

.

(1.28)

Some of these parameters can be observed in Figure 1.9.

1.3

Power Distribution

Power distribution is an important factor that is usually of great importance in the design of PCBs. In high-speed digital design the grounding of the PCB provides not only a DC return but also a radio-frequency return plane for all of the IC. There are a series of rules that should be considered: 1. There should be an even and low RF impedance in the DC power distribution. Minimize ground loops in the RF grounding system in order to minimize radiated emissions. 2. Decouple ICs in a PCB using bypass capacitors ranging from 0.1 to 10.0/zF. The capacitor leads should be as short as possible in order to minimize inductive effects. The bypass capacitors should be as close to the IC as possible. 3. Use planes rather than return traces for power and ground in PCBs. 4. Power and ground planes should be kept close to each other to reduce radiated emissions. The best layout to reduce radiated EMI is shown in Figure 1.10. The power distribution planes used in multilayer PCB do have some impedance. An example of a circuit model for a multilayer power distribution is shown in Figure 1.11. The power supply is shown by its source and ground impedances. The distribution impedances are also shown for the backplane with its inductances, resistance, and capacitance coupling between planes. From the AC impedance point of view, the power distribution is described in Figure 1.12. The first impedance Z t is the transient impedance, which is modeled between the Vcc and the decoupling capacitor (Cby). The second impedance in the figure is the bulk capacitance impedance (Zb), which changes the IC decoupling capacitance. The final AC impedance in power distribution planes is the one given by the plane bulk decoupling capacitance. To this impedance (Zt, Zb, Zbulk)

1.3. Power Distribution

15

Vo of driver

Voltage ......

Av

Vcrosstalk

: VIA ii

time (nSec)

.

.

.

.

.

~

m

pied Noise VCrosstalk

i

time (pSec) Figure 1.9

Crosstalk measurements.

we must also add the DC resistance of copper planes (ground and Vcc), given by 679 Zplan e (DC) = Tp (/z - ohms)square'

(1.29)

16


Gnd 5V

~~~~~~~~~lfl~~~~b I[__----F____F----~__I~I__--IF____F----~__

Gnd _ _ l _ . 5V

Figure 1.10

I I

Rs "VVk,

PCB layout for reducing radiated EMI.

Rb 'VVk,

&

I I

Vs

I

I

I !

"VVk, Rg

I

Power Supply

Lb

I

RpCB

I Cb

Lby

Rby

I I

Backplane

LpCB

~

~c

I

I

z!o

I Rg(PCB) I

Lg(PCB)

PCB

Figure 1.11 DC power distribution in a PCB card.

Cbulk(PCB)

Vcc IC

Zt

Figure 1.12

I~

~ ' ,

'k/k/k,

It

Cby

Zb

Cbulk Zbulk(PCB)

Power distribution with the AC impedance effect.

/

1.4. Decoupling Capacitance Effects

17

where Tp is the thickness of the plane (0.025 mm/0.001 inch), as well as the impedance between parallel planes, given by Zplanes-- 377

h W + X/~e~'

(1.30)

where h is the spacing between planes, W is the conductor width, and t is the plane thickness. The plane inductance Lplan e is given by h W

Lplan e "- 0.383 "

(nil/inch),

(1.31)

and the plane capacitance Cplan e is given by S Cplane --" er /30 ~

pE

(1.32)

where s is the surface area in inch 2, h is the plane separation distance, and W is the plane width (inch).

1.4 Decoupling Capacitance Effects The ICs need to have sufficient current to operate, including high peak-current requirements during switching. The PCB power system must provide this current requirement without the need to lower the supply voltage. To alleviate this problem, capacitors placed near the devices are connected between the power and ground planes. These capacitors provide the charge current needed by the IC and not the power planes. When their current is discharged, these capacitors will recharge quickly from the energy provided by the bulk capacitors and PCB bulk capacitors. A typical use of bypass capacitors (Cby) is shown in Figure 1.13.

vcc

GND

Figure 1.13 Proper use of bypass capacitance in PCB.

18


The capacitance Cm is the mutual capacitance between planes which are very close to each other. This capacitance is of very low impedance at high frequencies, allowing RF current to cross easily between planes. For lower frequencies, the bypass capacitance helps to short together the power and ground planes. At high frequencies, however, the bypass capacitor, associated planes, leads, and device models can have associated parasitics, as shown in Figure 1.14. Bypass or decoupling capacitors provide the current needed to the devices until the power supply can respond. In high-frequency switching, bypass capacitors of several capacitance ranges must be used. Bypass capacitors with short leads provide faster current because of the diminished lead inductance. Therefore, in high-speed design, it is highly recommended that leadless surface mount capacitors be used. The best performance is obtained when the capacitors are within the component package. As shown in Figure 1.14, the bypass capacitor's equivalent circuit is composed of Rsh, the insulation resistance (100 Mohm), which means it has a minimum effect in the operation of the bypass capacitor; R c, the series resistance; Cc, the bulk capacitance of the capacitor; and Lc, comprising both the lead and plate inductance. The plate inductance is usually small when compared to the lead inductance. The real impedance of the capacitor is given by Zby---- VRc2 Jr (X L --Xc) 2 Cby Model at High Frequencies

Lp

.rYy,~ _

_

Ground Leads Model at High

Frequencies

Capacitive Load Model at High Frequencies

I Vcc

:c, I _

.

~:Rg I,

(1.33)

+V Power Leads Model at High Frequencies

I/ I

=.-.

-

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

i

I

I

I

I I

I I ~

I

I

I

I

I

I

I

I

I

I ~

t -

4.0

3.8

I

-

3.6

i

i

I

I

I I

I

I

I

i

i 5

i 10

1

2

Figure 1.20

I

20

50

100

150

MHz

Dielectric constant vs frequency of various PCB traces.

7.5 7.0

_

m

n

6.5 O

tl) 09 t-

cc.m

6.0

,r

5.5

5.0

i 2.8 3.0

I

I

I

I

3.2

3.4

3.6

3.8

4.0

!

I

I

I

4.2

4.4

4.6

4.8

Relative Dielectric Constant ~R

Figure 1.21

Signal velocity vs dielectric constant in a PCB.

I 5.0 5.2

30


copper in a trace may result in voltage drops and heating that could degrade circuit performance. In Figure 1.22 we see the illustration of the trace resistance of copper as a function of trace width and thickness. Finally, Figure 1.23 shows the conductor heating as a function of width, thickness, and current flow. One of the most common methods to decrease the thermal resistance and increase the power dissipation is to use thermal vias. Thermal vias are largediameter holes punched into the substrate, aligned vertically. The resultant via pattern is like a solid metallic plug, and the vias are filled with a high-thermalconduction material. With the use of thermal vias, the heat that is generated from the IC is transported through the interface between the die and substrate to the thermal vias. The vias will then transfer the heat to other heat conductors such as heatsinks. The heat removal capabilities are dictated by the size and number

!

2.5~

2.0 o o t~

E tO v

o

tO t-

t~

o rr

I

I

I

I I

I

I

I

I

I

I

I

I

I

I

I

0 . 5 0 Z Copper

/

I

r~

i "-,%# I

i/

~

,

,

i

i

,

,

_

I

I'~

I

I

I

I

I

I

I

I

I

I

I

'

'

I-1.5 -

I

I

['~

-

I

I

I

1.0 _

,

,

,

''-L

I

I

I

I

I ~

,'

,

,

F

I

0.5 k

I

"~

I/ 20ZCopper~

jr

i

I

I

t

t,'----z__. T--

, 4

6

8

10

12

14

16

Trace Width (mils) Figure 1.22

I

Trace resistance vs trace width and thickness.

18

20

1.6. Thermal Control in Equipment and PCB Design i

0.24 -~,

0.20 --

=o ~"

0.16

I

0

0.04

l

I

I

I

l/

I/

I

I 30001/ I/' I I rise/ / 4000[ I /I /I rise I

i

V

/

'

'

I

I

' lJ ~/i/I

I

0

g

I

i 5oc.I 1o0~ I rise/I rije I/ ] I / I I /I

-I 0.08

I

-

I

I

i

4

8

0.0

/ ; I I /'1

I

i

i

I

I

I

#,.

Jf

I

I

I

I

i

i

I

I

I

I

I

I

I

I

!

i

I

i

I

I

I

12

16

20

24

28

f

l

31

I

i

32

Current (Amps) Figure 1.23 Temperature rise vs copper for 2OZ copper.

of vias. Thermal vias should be located close to the hot spots of a PCB only because they occupy routing space and make the routing of PCB traces more difficult. A representation of thermal vias is shown in Figure 1.24. The total heat Q transferred by radiation is given by Q = keflA(T

where k

= = p = A = Th, Tc = ~3

the Boltzmann's constant emissivity the view of the shape factor radiating surface area hot and cold temperature in K.

4 -

T4),

(~.55)

32

1. Noise Interactions in High-Speed Digital Circuits Die

i ()

i

~

()

I-!

f

'"'"~,

ic

i ()~

()

!-I

!-1

Solder

I 1 ~\

Substrate

Thermal Vias

Figure 1.24 Thermal vias illustration.

1.7

Lossy Transmission Lines and Propagation Delays

As we go into more dense packaging and more packed ICs, many of the internal interconnections have significant resistance and therefore must be considered as lossy transmission lines. We now outline some of the basic parameters of lossy transmission lines and develop formulas for signal delays. For the microstrip given in Figure 1.25, the DC resistances are given by Equation (1.56), which is the low-frequency loss factor:

OZR

P 2 Wt Z o,

--

(1.56)

W

~

' .

_

/

,I

h

-f

~

It

, -

-

Sr

_

-

:

Figure 1.25 Parameters of a microstrip configuration.

1.7. Lossy Transmission Lines and Propagation Delays

33

where W and h are the conductor width and thickness, p is the material resistivity, and Zo is the conductor characteristic impedance. At higher frequencies another factor plays a role in transmission lines: the skin effect, in which the current at higher frequencies is concentrated on the surface area of the conductor. The skin depth is given by /

6= ~ p 7r/~f'

(1.57)

where f is the frequency and/z and p are the permeability and resistivity coefficients of the material. When conductor thickness is about 2~ or more, increasing the conductor thickness does not reduce the effective resistance of the interconnec-

tion. The dielectric attenuation constant is defined as 7rV~er f tan ~d ffd=

C0

(1.58) '

where tan 6d is defined as the loss tangent given by the expression tan 8d = ~

(1.59)

0)8 r

where o"a is the conductivity of the dielectric material and o) is the angular frequency (w - 2 ~ f ) . Choosing the dielectric constant correctly minimizes the dielectric losses. As for the propagation and interconnect delay, consider the model in Figure 1.26. I

I

I

I

Zout

I

I

I I

Linl f,y.yy~

I

Z.ps

Lgs

Lin2

Cgs/2

Cin2/2 Cin2/2

I

Cou t

qnll2

I

l T T :l I

Cps/2

Cinl/2

I

I

DRIVER

I

Packaging Interconnect

I PCBMicrostrip

I Transmission Line

:T T i I Packaging

I Interconnect

I

I RECEIVER

Figure 1.26 Electrical modeling of a driver/receiver with transmission line.

34


A first approximation to the propagation delay is given by td = 0.7[Zout(Cin 1 + Cout + Cus + C L + Cin2) l § ~ZusCus § Zus(Cin 2 + CL) ],

(1.60)

where Zout and Zus are the equivalent resistance of the driver and the characteristic impedance of the microstrip line, respectively (both in ohms). The term Cus is the total line capacitance. Cin 2 and Cin 1 are the equivalent total packaging interconnect capacitances. C L is the load capacitance of the receiver IC. The effect of the line inductances (i.e., Linl, Lin2, and Lus) is to increase the time delay by 10-30%, as the terms Zout and Zus in Equation (1.60) are substituted by the terms (Zout + 2Lin) and (Zus + Lus), respectively. The capacitance terms in the preceding equation are given by W/b

Cus = 2ere~ 1 - t / h '

(1.61)

where t is the thickness of the microstrip line, b is the thickness of the dielectric material (2h), and W is the width of the microstrip. For a stripline as shown in Figure 1.27, the foregoing expression becomes W/b

Cus = 2ere~ 1 - t / b " Often, fringing capacitance must also be considered, as shown in Figure 1.27. The fringing capacitance for the stripline is given by Cf ~

1 - t/b

II h

In 1 +

1 - t/b

-

/of

~

-

1 - t/b

1 In

(1 - t / b ) 2

- 1

cfHO

Figure 1.27 Parameters in a stripline configuration.

.(1.62)

1.8. VLSI Failures and Electromigration

35

The characteristic impedance of a stripline is given by 1207re Zus(Stripline) = X/~erCt'

(1.63)

where Ct 4= 2Cus + 4Cf. For the microstrip line, the characteristic impedance is given by the following expressions. For Well/h -< 1" Zus = eX/~reff60ln[8h , Weff

Weft] 4h J'

+

where

+0.04[1 T - 1, 2 '{[1+ 12 ] 2,[h,1 + In 1 Weff = W + 1. for--W>-

1/2

/3r'eff --

h

Weff= W + 125ht[1 + l n ( 4 t W ) ] 9

27r

(1.64)

forW< 1 h 27r"

For Weff/h > 1" 120~" / ~//er,eff ZUS -'--

Weff+h 1.393+ 0.667 ln[~-~eff + 1.444] -

8r, eff :

8r+ 1 + 2

8 r --

2

1/2

(1.65)

1[1 + 12 ~eff ]

The delay of the transmission line tL in Figure 1.26 depends on the characteristic impedance of the line and is given by tL = 85X/0-475er + 0.67

(psec/inch),

(1.66)

and for a buried microstrip the delay of the transmission line is given by tL = 85X/~er

1.8

(psec/inch).

(1.67)

VLSI Failures and Electromigration

The issue of electromigration refers to the mass transport in metals under highcurrent and high-temperature conditions. It is a key problem in VLSI circuits

36


because it can cause open circuits and short-circuit failures in the VLSI interconnections. This is even more important with today's technologies, where VLSI circuits are fabricated on small chip areas to save space and reduce propagation delays. In FET devices, as the device decreases in size, the propagation delay decreases and the power dissipation remains constant, but the current density increases. In bipolar devices, similar behavior is observed. The problems caused by electromigration can be divided into two categories: topology-related problems and material-related problems. 1.8.1

TOPOLOGY-RELATED PROBLEMS

These problems result when the interconnection dimensions decrease to the micron range. Interconnection lines can then fail at different unrelated sites. Furthermore, as the device contact size decreases, the contacts become comparable to interconnection lines and are subject to the same current density as the conductor lines. 1.8.2

MATERIAL-RELATED PROBLEMS

These problems are basically caused by high current densities. Three problems are associated with electromigration from the materials point of view. The first is Joule heating. As the current inside the IC increases, the heat distribution becomes a serious concern. The temperature rise caused by very thin metal wires generates a great deal of heat that must then be removed through the substrate. The cooling rate provided by heat sinks and thermal vias must be greater than the heating rate due to the current density. Any imperfection within the substrate may diminish the efficiency of the heat dissipation process and speed up a thermal runaway process that could destroy the line. The second materials-related problem is current crowding. Because of structural inhomogeneities, there is an uneven distribution of current along metallization conductors. This also causes the atoms in certain metallization lines to migrate at different speeds, resulting in the formation of voids that will eventually fail to open. Finally, there is reaction of materials. Because of mass accumulation and storage and depletion, the mass transport generated is enough to cause stresses and lead to extrusion in the passive layers. This can also change the electrical properties of junction contacts. 1.8.3

ELECTROMIGRATION M E C H A N I S M S

Metallization is the process by which semiconductor substrates are joined together through a metal line. The ions in the metal are held together by the metal line.

1.8. VLSI Failures and Electromigration

37

The binding force of these metal ions is stronger than any possible opposing electrostatic force. As the temperature increases, some of the ions escape from the potential well that binds them in the metal lattice. When these ions reach the potential well, they become energized and move around. These ions, for example, can move to vacancies within the metallization line in a process called selfdiffusion. In the absence of an electric field, the self-diffusion process is random. Therefore, a random rearrangement of atoms occurs with no net gain in mass transport. When a current is applied, there are two external forces applied in the metallization: the frictional force and the electrostatic force. The frictional force is due to the momentum changes within the metallization structure; it is proportional to the current density. The electrostatic force is caused by interactions between the electric fields created by the electrons and the positively charged metallic ions. The electric field caused by the electrons will attract the positively charged metallic ions against the electron flow. In Figure 1.28 the frictional force and electrostatic force are given by Ff and F e, respectively. The frictional flow acts in the direction of current flow J. The electrostatic force acts against the current flow and in the same direction as the electric field. Because F t- > > F e, the net force will always be in the direction of current flow. The induced flux created by the net frictional force is given by

0 = ~ fkT ) (Zeffe)eXp

'

where

(1.68) Zef

=

Z(\2pndm p ,,m 1)

and Z = electron-to-atom ratio Pd = defect resistivity

J E

Fe

,._

Ff

Figure 1.28 Illustration of electromigration.

38


p

= resistivity of metal

nd n m E

= = = =

T K D

= absolute temperature = Boltzmann's constant = self-diffusion coefficient

f

= correction factor on the lattice structure.

density of defects density of metal free electron mass activation energy

Because of ~pf the original random process changes to a well-directed process in which metallic ions move opposite to the electron flow of the current, whereas the vacancies move in the opposite direction. The metallic ions condense to form whiskers, and the vacancies condense to form voids. This process results in a change in the density of the metal ions with respect to time. The density change is given by

dn d--7 = - V(V 9~p),

(1.69)

where V is the volume and

dO

dO

V " O = gx

dO dz 9

This formation of voids causes the metallization lines to foil. As the current is diverted to other lines, current density and heating increase, causing the local temperature at certain locations within the IC to increase and therefore more lines to fail. Finally, as whiskers form, mass-related stresses could occur that can cause additional lines to fail. These failure scenarios and processes will continue until the circuits fail. The mean time between failures is given by

A,

ex

(1.70)

where J is the current density, A is a constant depending on geometry, k is Boltzmann's constant, n is a constant ranging from 1 to 7, and T is the temperature in kelvins. Two factors are responsible for inducing electromigration. The first is current density. As current density increases, momentum exchange between the electron carriers and metallic ions causes large frictional forces and flux to occur along

1.8. VLSI Failures and Electromigration Table 1.3

MTBF (hours) at a Temperature of 160~

Density (mA/cm z)

Current

0.1 0.2 0.4 0.6 0.8 1.0 2.0 4.0 6.0 8.0

39

and 10 -7 cm z Cross-section

Small Crystalline

Large Crystalline

15,500 4,000 960 450 250 155 40 10 ~

120,000 30,000 7,800 3,300 1,900 1,250 300 75 33 18

Glassed Large Crystallite

65,000 29,000 15,000 11,000 2,700 700 370

the metallization lines, which could eventually make the lines to fail. As can be observed in Table 1.3, the MTBF decreases as the current density increases. The second factor is thermal effects. Electromigration develops from a high temperature to a low temperature. The thermal gradients can induce thermal forces that can cause mass transport in metallization lines. According to Table 1.4, the MTBF increases with line temperature.

Dependence of the MTBF on Temperature for Three Kinds of AL Film Conductor Having Cross-sectional Area of 10-7 c m 2 and Current Density of 1 mA/cm 2 Table 1.4

MTBF (hours) Current Density (mA/cmZ)

Small Crystalline

Large Crystalline

40 80 120 160 20O 220 240 260

23,000 3,000 580 155 52 32 21 14

m m 12,500 1,250 180 80 37 18

Glassed Large Crystallite m n 11,000 800 255 90 34

40


1.9

Interference Concerns with Connectors

A major source of radiated EMI is connectors, or rather, connector pins. Current flow tends to couple among connector pins and between connector pins and the ground plane, and return paths are such that large ground loops are created, causing even more radiated EMI, but also more noise coupling among pins within a connector. The most important factors affecting the performance of connector pins are (1) mutual inductance between connector pins, (2) mutual inductance between connector pins and groun d , (3) series inductance of pins, and (4) parasitic capacitance between connector pins or between pins and ground. Let us consider the connector in Figure 1.29. Notice that currents I 1, I 2, and I, (from drivers 1, 2, and n) return through the ground connector pin, creating current loops of different sizes and loop areas. First, because of current flow between conductors, there is a mutual coupling between each of the conductors' drivers and the return conductor. This mutual coupling results from the mutual inductance of current loops. Let us consider the mutual interaction between loop 1 and loop 2. The contribution to the total magnetic flux in loop 2 comes from the current flowing out of driver 1 and

CARD1

I'

Driver 1 - - - ~

,vv~,__l~~ I1 Driver2 _ _12___~ 4

Driv~er

CONNECTOR d

I

~1

P~

__

I

CARD2

I

~V~, - LTI Loop 1 t_ - - - ~ ' - I ~ - - -I I

~ - "

L

"~176

V

I ~7

I I

Loop 3 .

13

~

--===m

I

_--.~

i

I

Figure 1.29 Typical connector with driver and receiver loads.

I

1.9. Interference Concerns with Connectors

41

flowing through loop 1, and from the returning current flowing through the ground pin. The mutual inductance formula has two terms: (1.71) Here, c is the distance between driver 1 and the ground pin; a is the distance between driver 1 and driver 2; b is the distance between driver 2 and the ground pin; r is the radius of the ground pin; and d is the separation between cards. Also, the total magnetic flux in loop 3 gives rise to mutual inductance by L123 = 5 . 0 8 d ( C ) + 5 . 0 8 h l n ( f ) + 5 . 0 8 h l n ( r - ~ 4 ) + 5 . 0 8 h l n ( j ) ,

(1.72)

where b is the distance between driver 2 and the ground pin, f is the distance between driver 2 and driver 3, g is the distance between driver 3 and the ground pin, and j is the distance between driver 1 and driver 3. Because we are assuming that the source impedance Zo is always present in a driver circuit (electrical length of wire is sufficiently large), the noise coupled due to crosstalk splits half in either direction, and therefore the crosstalk is given by 1

dI

EMI crosstalk = ~L12 dt 1

dI

(1.73)

EMI crosstalk = ~L12 3 dt" From this crosstalk equation, several factors can be deduced that could result in a dimensional crosstalk. First, slowing the rise time of the drivers would result in a diminished dl/dt. The driving rise time can be reduced by using a capacitor on the source side of the connector as shown in Figure 1.30. Notice that in the figure we are assuming that the receivers can be modeled as capacitive loads; such loads of capacitive nature could make surge currents appear as switching occurs. Another way to diminish crosstalk behavior is to decrease the mutual inductance. For example, rearranging the layout of pins in Figure 1.31 could diminish the mutual inductance. If the ground pin and corresponding wire are moved away from driver 1 and driver 2, increasing the distances b and c, the mutual inductance L12 will increase. Therefore, decreasing the distance between the driver pins and the ground pin will likewise diminish the mutual inductance.

42


CONNECTOR CARD1 Driver 1

~1

~..

I

d

~1

,,--

CARD2

I

IV-

-LC L

Driver 2 CL

Driver

CL

Figure 1.30 Employing capacitances to reduce rise time.

CARD1

Driver 1

CARD2

i

~V,,T---a_

~_~_ I --"

Driver 2

c L

+~ ~lg/4 Ig/4 \

12

I

~-41~ - - - - I ---L I C L 1o/4 ~ "

-- ~ -

"i- ~-

9VVi ~ " ~

I

Ig/~l Driver 3

\ -.,-.i

_.__..~

_

,~7 CL

_l

I

~

---,.., Ig/4 CONNECTOR

Figure 1.31 Adding/rearranging ground pins to reduce interference.

1.10. Ground Loops and Radiated Interference

43

Finally, adding more ground pins/wires would also decrease the overall inductance. The ground pin/wire is responsible for coupling drivers 1, 2, and 3 and their respective wires. Therefore, providing more ground wiring will force the ground current to distribute itself among the different wiring as shown in Figure 1.31. Notice that in Figure 1.31 there are four ground pin returns and three driver signals, such that every driver signal is "flanked" on either side by grounded pin returns. If we consider driver 2, for example, the total ground return current of 12 can be split in four different ways. Ideally, the figure shows each return pin carrying equal (88Ig) current, but in reality the closest pins would carry the greatest return current. Nevertheless, the point is made that the mutual inductance between drivers will decrease, therefore considerably reducing the crosstalk among pin connectors. Furthermore, since the loop area transversed by the ground currents is much smaller, the effects of radiated EMI will also decrease considerably. Imposing even more ground returns between driver signals should decrease the crosstalk by a factor of 1(1 + n2), where n is the number of ground pins between driver signals, as shown in Figure 1.32.

1.10

Ground Loops and Radiated Interference

It was previously stated that ground loops can contribute significantly to the radiated EMI. This is important because such radiated noise can couple into other

CAR01 Driver 1

l

CONNECTOR

I

CAR02 -LC L

Zo 2

.9 m

I

J

n-1 ~7 Driver

n~

~7

Figure 1.32 Employing multiple ground returns to reduce interference.

44


sensitive circuits of analog or digital nature. Let us consider, for example, the scenario depicted in Figure 1.33. In this figure, two connectors (connector 1 and connector 2) are used to implement two driver/receiver card configurations. In connector 1, the return current from driver 1 has the option of returning through its closest ground pin; some of it, especially at high frequencies, could return through a much more distant grounded pin closest to driver n. The loop area 1(0) (driver 1 and ground pin 0) formed by the return current of driver 1 through its closest ground pin is much smaller than the loop area 1(n) (driver 1 and ground pin n) caused by some of the return current using pin n of connector 1 as its return. Other scenarios for

CARD1

CONNECTOR

I

CARD2

I

""me

Ig1

Loop~ea 1101

Driver 1

_

//~ /

/

. . . .

Loop A r e a l ( n )

d3

~

Driver n

"'-': *

d r

Ig2

dl

. d4

/ 'vvvT---J-c L

/--"

*" ,~- Cc4

CARD 3

Cc2-~

C0nnector 2

_

7- Ccl ~

CARD 4

Zo

I Ig4

// /.

,~

CL

I

Loop Area , - ' 9 1 - --- -

Figure 1.33 Illustration of ground loops among card connectors.

1.10. Ground Loops and Radiated Interference

45

the return current to use other ground pins within connector 1 are also possible. Because loop area 1(n) > > loop area 1 (0), the radiated emission from connector 1 could increase greatly, especially at high frequencies, where a significant portion of the return current could choose pin n as a return path. The electric field magnitude from a loop current is directly proportional not only to the current itself, but also to the loop area traversed by that current. In the figure we also observe another scenario very common at high frequencies: capacitive coupling between the ground pin n in connector 1 and the connector metal casing (Cc3, Cc4). Further coupling would capacitively couple both connectors 1 and 2. Some of the ground current from connector 1 would flow into connector 2 and its grounding pins through capacitive coupling. The total loop area now becomes the sum of loop areas, loop area 1(n) + loop area 2(n), with the potential of creating an even bigger radiated emissions problem. The amount of radiated emissions created by loop areas of signal/return currents is given by E(V / m) = 263 • 10-16 F2(Hz)A(m2)I(amp s) R(m)

(1.74)

where F(Hz) is the frequency of interest, A(m 2) is the loop area formed by the driver signal and return curent, I(amps) is the current magnitude, and R(m) is the distance in meters at which the electric field is to be computed. Assuming, for example, the scenario of Figure 1.33, the total radiated electric field could be approximately calculated for a worst-case scenario as I E total (V/m)] = I Elr

+ ]El(n) I -']- ] E2(n)1,

(1.75)

where El(o~, EI(,O, and E2o0 are the electric fields produced by ground loop areas through pin 0, pin n of connector 1, and pin n of connector 2: El(o)(V/m) ~ 263 • 10 -16fe(Hz)(l~176area 1(0))Igl(amps) R(m)

(1.76)

l(n))Ig2(amps) El(n)(V/m ) ~-- 263 • 10 -16fe(Hz)(10~ area R(m)

(1.77)

Ez(n)(V/m ) ~-- 263 • 10 -16fz(Hz)(10~ area 2(n))Ig4(amps) R(m)

.

(1.78)

In calculating Igl, lg2, Ig3, and/84, we know that

I1 : Igl Jr- Ig2-- Igl "1- /g3 -']- Ig4,

(1.79)

46


and the maximum I 1 can be calculated approximately by using the expression 5V I 1 - Zo(ohms).

(1.80)

The current in Igl is given by

Igl

= ( 5.0V )Lgl(O ) \Zo~-O--~ms) Lgl(n )'

(1.81)

where Lgl(O) and Lgl(n) are the inductance of the ground loop through pin (0) in connector 1 (loop area 1(0)) and Lglr is the inductance of the ground loop through pin n in connector 1 (loop area l(n)), respectively. Also, in the same manner, =

=(

+

5.0v

r

The terms Lgl~,0 and Lg00o are obtained from the pin inductance given by

where d is the separation in inch of signal to ground. The term d will be either dl or d2 as indicated in Figure 1.33 for Lgo(n) and Lgl(n) calculations, respectively. L is the length of the pin in inches and r is the pin radius. In the same manner, once we have calculated Ig2 we can calculate Ig3 and Ig4 as follows: [Lg3] =

1.84)

Ig4-- Ig2 L~g3j, where Lg3, Lg4 can be calculated from Equation (1.84) using d3, d4 illustrated in Figure 1.33. One of the most trivial conclusions of the preceding analysis is that adding more ground pins to the connector will bring the grounds closer to each signal and will lower the inductance of the overall return path. Other things that can be done are to move the I/O connectors as close to each other as possible, never to route ground returns from the same source on separate connectors, and to provide slower rise time for drivers. The issue of parasitic capacitance not only affects the return path of ground current, but its cumulative effects from many connectors can distort transmitted

1.11. Solving Interference Problems in Connectors

47

signals. Therefore, conductors with minimum parasitic capacitance are highly desirable. Parasitic capacitance effects on connectors are shown in Figure 1.34. As the signal is transmitted, the lump parasitic capacitance of the ground at each bus tap will provide some parasitic distortion. This lump capacitance, represented in Figure 1.34, can come as a result of (1) pin-to-pin capacitance from the connector on the printed circuit board, (2) trace capacitance from the connector to the local drivers and receivers, or (3) input capacitance of the local receiver plus the output capacitance of the drivers. The trace capacitance is given by C(pF/inch)

= t__d_0 Z0,

(1.85)

where to is the trace propagation in psec/inch and Z0 is the trace impedance in ohms. One example of proper layout of signal and ground pins in a connector is shown in Figure 1.35.

1.11

Solving Interference Problems in Connectors

There are basically three ways in which a signal line can be made much less noisy, especially for connectors near a chassis, from which the lines would leave. 1.11.1

FILTERING

Filtering removes the high-frequency content of signals. By removing the high frequencies, we can decrease dramatically the capacitive coupling among connectors. Furthermore, at lower frequencies the current will tend to follow closer return paths, using the closest connector pins rather than pins that are farther away. Therefore, the radiation efficiency of current loops increases greatly at higher frequencies. Most typical filters involved small impedances in series with each driver. The series impedance would then feed into a shunt capacitance to ground, which must be a quiet ground that connects directly to the chassis. 1.11.2

SHIELDING

An example of shielding the connector lines is shown in Figure 1.36. In a shield a continual metal surface is provided around the inner conductors. The returning signal currents distribute evenly around the outgoing signal wires. The current loop between signal and ground paths is very small, and a perfectly conducting and symmetric shield will not radiate.

48


CARD 1

Connector

-LCL

Zo

C

Cp Connector

CARD 2

Cp

3_

I CARD 3

Transmission Bus Cp= parasitic capacitance between connector and bus tap.

"1:

Connector

3_ Zo Cp -LC L

$ Figure 1.34

Parasitic capacitance effects on connectors.

1.11. Solving Interference Problems in Connectors

49

Ground Plane

Signal Lines Figure 1.35 Proper layout of signal and ground pins (dark) in a connector.

Connector

CARD

Shielded Cable Zo

zo

Zo

Figure 1.36 Example of shielding a connector line.

When using a shield, make sure that the pigtail connection is as small as possible, since pigtails, also known as drain wires, work poorly at high frequencies. Furthermore, noisy wires should be used on separate shields; otherwise they would be sharing the same common return path of the shield. Best of all is to use specially designed connectors that are metal in their outer structure and incorporate grounding schemes that are internal to the connector.

50

1. Noise Interactions in High-Speed Digital Circuits Connector

Connector

CARD 1 Driver

Zo

CARD 2 ferrite beads

I1

,1 cc

,lcc 'T

CL ..1_

I

1

A

Figure 1.37 Common-mode and differential-mode currents flow among cards.

1.11.3

C O M M O N M O D E CHOKE

This is a series of ferrite beads that are used mostly on I/O cabling to eliminate, as much as possible, the common-mode current, which is the component of current most responsible for conducted and radiated emissions. This current should be distinguished from different-mode current, which is the return current of driver circuits. This distinction is shown in Figure 1.37. 11 and 12 are differential-mode currents and are therefore of equal magnitude. I c is a common-mode current which follows a different return path. In the figure, the abnormal return path is facilitated by the parasitic capacitance Cc between conducting wires. The use of ferrite beads with their high inductance will reduce the magnitude of I c, especially at high frequencies. Ferrite beads' effectiveness in reducing common-mode current is frequency dependent. Therefore, care must be exercised in choosing the correct bead material to eliminate the right frequencies, which are embedded in I c.

1.12

The Issue of Vias

The vias in a PCB layout have both parasitic capacitance and parasitic inductance, shown in Figure 1.38. These capacitances and inductances are usually small, but their cumulative effects can add significantly in an adverse manner. The value of such parasitic capacitance and inductance can be estimated to be [1 ] 1.41srtd 1

Cpv= d z - d ,

1]

(1.86)

References

51

pad Z.

Lpv

VIA

v, Cpv = parasitic via /

~

inductance and capacitance

Figure 1.38 Parasitic effects in vias.

where D h Lpv t d2 d1 Cpv

= = = = = =

diameter of via, inches length of via, inches parasitic inductance of via, inches thickness of PCB diameter of clearance hole in ground plane, inches diameter of pad surrounding via, inches parasitic capacitance of via, inches.

Reference 1. Howard W. Johnson and Martin Graham, High Speed Digital Design, Prentice Hall 1993.

Chapter 2

2.0

Noise and Interference Issues in Analog Circuits

Basic Noise Calculation in Op-Amps

The noise in operational amplifiers (op-amps) is related to the passive and active components within the circuit. It is also the kind of noise that could induce errors that could not be detected by DC error analysis. Noise can be random and repetitive, either of voltage or current form, and can be at any frequency. Noise can be qualitatively classified as either white noise or color noise. Examples of white noise are Johnson (or thermal) noise and shot noise, which can exist up to a frequency of 100 GHz. Color noise has an amplitude that changes over frequency, such as flicker noise 1/f or popcorn noise. An example of a noise density spectrum is shown in Figure 2.1.

100

N

"1t-

10

r

>

o~,~

01

10

I 100

I lk

I

I

I

10k

100k

1M

I 10M

Frequency (MHz) Figure 2.1 Example of noise density spectrum. 52

I 100M

2.0. Basic Noise Calculation in Op-Amps

53

The noise spectral density is the rms value of the noise voltage Vn or a noise current I n which is expressed as a voltage or current per X/-H~z. The power spectral density is defined as the derivative of noise power over frequency range" P(Watts/Hz) - dPn

(2.1)

df The power spectral density for the voltage and current are defined as Vn(rms)

(volts/X/-H-zz) (2.2)

l~(rms) In=x@

2.0.1

(amps/X/-~z).

THERMAL NOISE

Thermal noise in all electronic devices results from the random motion of free electrons in a conductor as a result of thermal agitation. Therefore, the thermal noise power is directly proportional to temperature and frequency,

Pn = KTB(Hz)

(J/sec),

(2.3)

where K = 1.38 • 10 -23 J/K is Boltzmann's constant, T is the absolute temperature (K), and B(Hz) is the bandwidth of the system. In conductors and semiconductors the thermal noise is always present. For example, an ohmic resistor can experience a thermal noise voltage given by Vn(rms ) = X/4KTRB(Hz),

(2.4)

or in terms of spectral noise density, Vn

-- 4KTR

x/-fiSz

(2.5)

(nV/X/~z).

R

"O

Vn(~ Vn=(4KTRB(Hz)) 1/2 0

Figure 2.2

m m

In = (4KTB(Hz)) 1/2 / R

0

Thermal noise representation of a resistor.

54

2. Noise and Interference Issues in Analog Circuits

Noise figures in op-amps not only reflect the noise contributions of the IC itself, but also describe the IC with its feedback network, source, and load resistance. With the use of noise figures, a gain block can be completely characterized and total system noise calculations can be obtained by summing all the noise figures of each stage. The noise figure for an op-amp is the logarithm of the ratio of the signal-tonoise ratio of the input of the amplifier to the signal-to-noise ratio at the output: Noise figure =

(S/N)in 10 log (S/N)ou t"

NF =

(2.6)

To calculate the noise figure for an op-amp gain stage, the equation is

NF=

(InRs)2) 4KTRs

10log (1 + V 2 +

(2.7)

It can be shown that the noise figure includes the voltage and current noise from the amplifier. The noise current I n flows through the source impedance R s. An important factor is the bandwidth. In order to calculate the total noise, the total output noise spectral density, which is given in nV/X/-H~z, is multiplied by the square root of the bandwidth. The calculation of op-amp noise in a sizenoninverting configuration is shown in Figure 2.3. In order to obtain the total output noise, each term is multiplied by its gain and taken to the output as a voltage. Finally, all the terms are squared and added together, taking the square root of the sum of the squares. The individual terms are

Rs___)__)X/4KTRs(1 +R_~gg)

'nl 'nl s(1 (1 In2 -')"-) In2Rf Rf Rg --->--->X/4KTRg R--gg Rf ---)---)X/4KTRf

Vout= [(4KTRs + (ln2Rs)2+ V2) (1 +-~gg)2 +

.f)] + 4KTRI ( 1 +-~g

(2.9)

(In~ Rf) 2 (2.10)

.

2.1. Op-Amp Fundamental Specifications

55

Vn

vol

as Rf

(~(4KTR s ) 1/2 In2 I

C+)----

Rg

(4KTRf)1/2 2

Figure 2.3 Intrinsic op-amp noise for an inverting amplifier.

2.1

O p - A m p Fundamental Specifications

A block diagram of a basic op-amp is shown in Figure 2.4. The input stage is basically a differential input. Op-amps with a differential input as well as a differential output have very good common mode rejection ratios. The op-amp contains a high-gain stage with a single-pole frequency response. The output is a single-ended output stage. A(s) in the figure, known as the open-loop voltage gain, is the gain with respect to the differential input voltage V = (V+ - V_). A(s) is a dimensionless quantity and is expressed in decibels in some cases, but usually as a plain number (100,000 is typical). Because of their tremendous gain, op-amps are not useful in the open-loop mode, since a small input voltage can quickly make an op-amp saturate, producing an output gout = gcc" The most useful configuration, of course, is the closed-loop configuration, when a negative feedback from Vout is fed back to the inverting input ( - ) using a feedback network as shown in Figure 2.5.

56

2. Noise and Interference Issues in Analog Circuits

v+ O

High Gain Single-Pole Frequency Response

Differential Input

v- O~__.__

Vout

Output Stage

--> C s

analog g r o ~

.o,o

S/H

Figure 3.9 RC filtering for noise elimination in S/H amplifier.

buffer's offset and the input signal. The buffer provides the major portion of the current needed to charge the sampling capacitor, and this reduces the current demand from the source outside the IC. The sampler then enters into the finecharge sampling phase. The fine charge bypasses the buffer and will then connect

3.2. Driving Inputs in ADCs

111

the external source directly to the sample capacitor. The sampling capacitor is then charged to a voltage equal to the input voltage. The basic charge equations are AQ I = At

and

Q = CsV.

(3.1)

The instantaneous current is I and is equivalent to the charge Q per unit time. The input current to the buffered sampler of Figure 3.10 is defined as I

CsVos t

=

or

I = Vosf C s,

(3.2)

where f - 1/t is the sampling frequency and Cs is the sampling capacitor. The input current in the buffered sampler is a constant as long as the Vo~ of the buffer, the sampling frequency, and the sampling capacitor remain constant. It was previously stated that a filter be used at the ADC input to eliminate possible noise and pass only the desired signal bandwidth. This is shown in Figure 3.11. The RC filters are usually recommended by manufacturers. The R 1 value should be chosen to isolate the driving amplifier from the transient capacitive load of the sampler. The C1 value (C1 > > Cs) is selected to provide a very low source impedance to the sample transient, while also providing a reservoir of charge. The RC time constant is chosen to be short enough to allow the sampler to settle to full accuracy in the allotted sample time. At the PCB level, proper power supply decoupling must be used for every PCB in the system. An example of decoupling the power lines is shown in

fine

I

$2

I

vos

coarse !

$1

__J

I

i

III III

S3

I

Figure 3.10 Properly buffered sampler.

I

,

Vout v

112

3. Noise Issues in High-Performance Mixed-Signal ICs

s2 J _

VDD

Fine I

cb

,,.

Coarse

s,_.L." _[_R1

c~

...L. Successive Approximation Registers

Dout

;5 c VDD

Figure 3.11 Properlychosen RC filter in ADC to eliminate input noise.

Figure 3.12. The power supply input is first decoupled to the large-area lowimpedance ground plane with a good-quality tantalum electrolytic capacitor. The capacitor bypasses the low-frequency noise to the ground plane. A ferrite bead reduces high-frequency noise to the rest of the circuit. Low-inductance ceramic capacitors should be used for each power pin on each IC. To minimize inductance, surface-mounted chip capacitors should be used. Multilayer PCBs with one plane just for ground are required when multiple bypass capacitors are used for bypassing the power path in ICs. When connecting to the backplane, several pins of each connector should be used for connection to ground. In this way a low-inpedance ground plane is maintained between the various PCBs in a multicard system. Furthermore, it is highly recommended to establish separate analog and digital ground planes on each PCB as shown in Figure 3.13. The separation between analog and digital ground planes is stretched all the way to the backplane using a motherboard ground plane. The ground planes are joined together at the system through a single point ground. Schottky diodes are inserted in order to prevent DC voltages from developing between the two ground systems. Analog components such as operational amplifiers, comparators, and analogto-digital converters are decoupled to the analog ground plane. All ADCs, DACs, and mixed-signal ICs should be treated as analog circuits with their ground connected to the analog ground plane. This scenario can be observed in Figure 3.14, which shows the internal block diagram of an ADC, with its parasitic capacitances, wire-bond inductance, and parasitic inductance associated with connecting the pads on the IC to the package pins.

3.2. Driving Inputs in ADCs

0

+V

113

c0,1; L

~~7 Cb2

low frequency noise current

IC

Cbl l

Cbn Backplane Ground Plane

4,

PCB Ground Plane

IC

Figure 3.12 Decoupling of power bus lines in ICs.

As can be observed in the figure, there is considerable wire-bond inductance (Lp) associated with connecting the pads on the chip to the package pin charging currents in digital circuits to produce voltage at point (2), which will couple into point (1) of the analog circuits through the capacitance Cp. Furthermore, there is also some small parasitic capacitance between every pin of the chip. As was previously stated, the analog and digital ground should be connected at a point outside the analog ground plane using minimum load length. This is necessary because any extra impedance in the digital ground connection can cause more digital noise to be developed at point (2), which will cause more coupled digital noise into the analog circuit. As shown in the figure, it is advisable to place a buffer latch adjacent to the ADC to isolate the converter's digital lines from the

114


PCB1 An~log log ]Digital Grc ~nd ] Ground I ,.., Pla ,,, ~le t"lane

PCBn

PCB(n-1) I

II I

Analog Ground

P~._~

"//////////~

Dil ~ital

~ Aroalu:g I G' Grr)und PI~ne

Digital Ground Plane

~/////////////////~ ~ f / / / / / / / / ' J / / / / / / ~ , . .

~/////'//,~ ~////_~//'//////~

Backplane

/

Back0,ane

T

T1

Power Supply Single Point Ground

Figure 3.13 Separation of digital and analog grounds in mixed-signal ICs. noise which can be present in the data bus. The buffer latch and other digital circuits should be grounded and also decoupled to the digital ground. The noise that could exist between the analog and digital ground planes can reduce the noise margin at the ADC digital interface. The clock circuit should also be grounded and decoupled to the analog ground plane, since phase noise on the clock signal produces degradation in the system SNR. If possible (though this is not always likely), separate power supplies for analog and digital circuits should be made available. The analog power supply should be dedicated to the ADC. All DAC power pins should be decoupled to the analog ground plane, and all logic circuit power pins should be decoupled to the digital ground plane. A quiet digital power supply could also be used for an analog circuit. Clocks with low phase noise should be the main characteristic of crystal oscillators, since sampling clock jitters can modulate the input signal and raise the noise and distortion floor. The clock generator should be isolated from noisy digital circuits and grounded as well as decoupled to the analog ground plane.

3.2. Driving Inputs in ADCs Cb

() 5V

5V (

Cb

,, +

,

_1_

O

L

~. Lp ~"

~

+~~

!

~

Circuits

Cp

,...

VlI///ilII///II/~'/A

Digital GRN

Buffer Latch

Digital

Circuit~ 2~-

] VDD / Voltage Reference

"lock

I I

~

VDD

Lp

C

Analog

115

~

,~ Data Bus

DigitalGround Plane

Z

Analog Ground Plane

Analog Ground v

F////////J/////~/////////////////A Analog Ground

Figure 3.14 Proper grounding of a mixed-signal circuit.

Jitter in an ADC is simply the RMS value of the sample-to-sample variation at the point in time at which the input signal is sampled. The RMS time jitter produces a responding RMS voltage error, which is proportional to the slew rate of the input signal. The consequence of broadband jitter is to degrade the overall SNR of the ADC. Jitter for an ADC is usually attributed to the sample and hold circuits. The ADC sampling clock unfortunately is a phase and amplitude modulated by external noise sources; the sources can be wideband random noise, oscillator phase noise, power line noise, or digital noise due to poor layout, bad bypassing techniques, and bad grounding methodologies. Phase jitter on the sampling clock causes the same effect as jitter on the input sine wave. The consequences of even small amounts of jitter can be observed in Figure 3.15, where the SNR is plotted as a function of full-scale input sine-wave frequency for various amounts of RMS timing jitter using the formula SNR=201og where tj is the jitter time.

['] 2~ftj

'

(3.3)

116


SNR

(dB)

0.1

1.0

MHz

10

100

Figure 3.15 Example of jitter in ADC and its consequences.

A reading of the figure shows, for example, that in order to obtain an SNR of 90 dB on a 10-Mhz, full-scale input sine wave, the RMS jitter can be no more than 1 psec RMS. The total RMS jitter consists mostly of two frequency factors: narrowband and broadband. The clock will most likely have narrowband phase noise. The narrowband phase noise centered about the sampling frequency produces similar phase noise around the fundamental sinusoid frequency in an FET of the digitized sinusoid. On the other hand, the high-speed logic circuits in the sampling clock path will introduce broadband noise on the pulse edges which by itself can cause broadband jitter due to sample variations in the time at which the internal logic threshold was crossed. Clocks must have low phase noise. The crystal oscillator for these clocks should be constructed around discrete bipolar and FET devices. In other applications, additional filtering is usually needed for certain ADCs. In Figure 3.16, the bandpass filter after the crystal oscillator serves to remove any frequency noise around the sampling frequency. The low-pass filter removes any harmonics of the sampling clock frequency which may not have been attenuated enough by the bandpass filter. The output drives a low-jitter wideband comparator which converts the sine wave into a digital signal. The clock circuits should be isolated from the noise generated by digital portions of the system. It is important that the digital outputs of the ADC not be allowed to couple into the sampling clock signal. Possible coupling will cause

3.3. Filtering the Switching-Mode Power Supply

117

Low Jitter Comparator

Crystal Oscillator

Bandpass Filter

Low Pass

Filter

C

I

I I

fs

fs

Figure 3.16 Bandpass/low-passfiltering needed for driving a low-jitter comparator.

an increase in the harmonic distortion due to transients coupling into the sampling clock. Finally, the sampling clock itself, which is a digital signal, should be isolated from both the analog and digital portions of the ADC.

3.3

Filtering the Switching-Mode Power Supply

Switching-mode power supplies are small and highly efficient power sources, with high reliability, that are capable of operating with a wide range of input voltages. However, switching-mode power supplies produce noise over a wide band of frequencies. The noise is both conductive and radiated in nature, producing undesirable electric and magnetic fields. When such power supplies are used to drive logic circuits, more noise is usually generated on the power-supply bus. The noise consists basically of voltage spikes in the range of 10 to 300 kHz. These voltage spikes contain frequency components that would extend into the hundreds of megahertz. Filtering switching-mode power supplies must be tackled primarily by the power supply itself, but additional external filtering as shown in Figure 3.17 should also be added. Split-core inductors on large ferrite beads should be used as inductors. Both C1 and C 2 must have low parasitic inductance and must be located as close to the power supply as possible to minimize current loops and high-frequency magnetic fields. The filter design is very important, since the power provided to analog devices must be as clean as possible. Factors that are important are (1) characterization

118


L1

Switching Mode Power Supply

l ol

02=

ii ,ll o3

9

il L2

Figure 3.17 Filtering noise out of switching-mode power supplies.

of output noise, (2) identification of the frequency range of interference produced by the power supply, and (3) evaluation of the component used in external filtering. An example of switching noise in the output of a switching mode power supply can be observed in Figure 3.18, where the fast voltage spikes can produce significant harmonics well into the megahertz range. Because most analog ICs show degraded power-supply rejection at frequencies only above a few kilohertz, some filtering is highly desirable. An example of a block diagram for a switching-mode supply is shown in Figure 3.19. The input voltage is first filtered to remove any input noise that might be present on the power bus. The input voltage is then converted to 30 kHz on a higher square wave, which drives a transformer. The signal is then rectified and filtered at the transformer output. Pulse width regulation to control the duty cycle of the transformer drive is used in a feedback loop. It is important to realize that noise is being generated at several stages in the switching-mode power supply. The first producer of noise occurs at the inverter stage, where fast pulse edges generate harmonics which can extend for several megahertz. Secondly, the parasitic capacitance between the primary and secondary windings of the transformer will provide a secondary path through which highfrequency noise can corrupt the DC output voltage. Finally, high-frequency noise is also generated by both rectifier stages. We now look at some defaults concerning the capacitors and inductors used in filtering the noise from switching-mode power supplies.

3.4

Capacitor Choices for Noise Filtering

Capacitors are very useful filter components in switching-mode power supplies. There are many different types of capacitors, and their use in power supplies

3.4. Capacitor Choices for Noise Filtering

119

80 mV 40 mV Switching Noise (mV) 5V

I_/

-40 mV

-80 mV Time (laSec)

80 mV

40 mV Switching Noise (mY)

I

I I

30 ~tS

I

I I

5V

-40 mV

-80 mV

Time (lasec)

Figure 3.18 Example of switching noise at the output of a switching-mode power supply.

must be well understood. There are basically three classes of capacitors useful in filter design in the 10- to 100-kHz frequency range. They can be classified depending on their dielectric types: electrolytic, film, and ceramic. Table 3.1 shows a classification of several capacitors.

120


Vin

Input Filter

Inverter

rransfo~ "ner

"

Figure 3.19

Table 3.1

I

Pulse Width Modulator

Block diagram of a switching-mode power supply.

General Classification of Commonly Used Capacitors

Aluminum

Electrolytic (General Purpose)

Electrolytic (Switching)

Electrolytic

Size

100 txF

120 txF

100 txF

1 ~zF

0.1 IxF

Vrate d

2

25

20

400

50

ESR

0.6 ohms at 100 kHz

0.18 ohms at 100 kHz

0.12 ohms at 1 MHz

0.11 ohms at 1 MHz

0.12 ohms at 1 MHz

f(MHz)

100 kHz

500 kHz

10 MHz

10 MHz

1 GHz

Aluminum Tantalum

Polyester

Ceramic

Ceramic capacitors are usually the choice for a frequency above several megahertz. These capacitors are compact in size, low-loss, and are available up to several microfarads and with voltage ratings of up to 200 V. Multilayer ceramic chip capacitors are very popular for bypassing and filtering at 10 MHz or more. These capacitors have very low inductance, which is optimum for RF bypassing. In smaller sizes, ceramic chip capacitors have an operating frequency range of up to 1 GHz. All capacitors have some finite equivalent series resistance (ESR). Sometime these dielectric losses can help in the reduction of resonance peaks in filters and provide some degree of damping. For example, in tantalum and switching-type

3.4. Capacitor Choices for Noise Filtering

121

electronics, a broad series resonance region can be observed in an impedance vs frequency plot when Z falls to a minimum level, which is the capacitor's at that particular frequency. In most electrolytic capacitors, ESR degrades at low temperature by a factor ranging from 3 to 7 times. Figure 3.20 shows the highfrequency impedance characteristics of a number of electrolytic types. All capacitors have parasitic elements that limit their performance. The electrical network representing a capacitor and its parasitic elements is shown in Figure 3.21. The voltage across the capacitor is proportional to its net impedance, as shown in Figure 3.21, and to temperature. Capacitors also have parasitic inductance, which determines the frequency where the net impedance of the capacitor changes from a capacitive to inductive characteristic. In the frequency range from 10 kHz to 100 MHz, the parasitic resistance and inductance can be minimized with chip ceramic-type capacitors. The electrolytic capacitors are of a great variety of types. They include the general-purpose aluminum electrolytic capacitors, which are polarized and cannot support any voltage in the reversed bias direction. Also included in the electrolytic family are the tantalum-type capacitors with an upper limit voltage of 100 V and upper capacitance of 500 ~F. A subset of aluminum electrolytic capacitors is the switching type, which can handle high pulse transients in frequencies of up to

100

10

zohms, I

film 10 ~tF, 20 V

1.0 -

tantalum 101.tF, 20 V 0.1

ceramic 10~tF, 20 V

10

In 10

I

1

I

1O0

1K

1OK

I 100K

1 1M

Frequency (Hz)

Figure 3.20

High-impedance profile of electrolytic capacitors.

10M

122


100

_~apacitive

10 IZl in ohms 1.0

lOOm

70m

_

Resistive

I 10

I 1K

I I I I I I 1OK lOOK 1M IOM lOOM 1G Frequency (Hz)

Rp, Rs, Lp are the parasitic resitance and inductance of the capacitor

I

I

lOG

!

[100 • signal bandwidth], 1 where the signal bandwidth is given by BW = 5,TrRfC2. These equations for filter design and signal bandwidth for op-amps are good scenarios as long as C~ and

138


C2 ,

,,

II

Filter F

.

.

.

.

I R/2 i 'VVX,

VinO

, I

i

I ,,

]_'

C1

R/2

I ~/XA, I

Vout

C

R1

C2 II

R1

4;

I

I- . . . . R Vi n o L , % A / ~ , I I - 9- - -

I

.

Vout

I I

C1 .

O

.

.

0

filter Figure 3.35

Implemeting filtering to eliminate RFI rectification in op-amps.

3.7. RFI Rectification in Analog Circuits

139

C 2 have low inductances and the resistors have low parasitic reactance and are mostly metal-film resistors. Noise can also couple into an amplifier's input stage through its output as shown in Figure 3.36, especially in low-power circuits where operational amplifier output resistance and external resistances are large. The output resistance of operational amplifiers increases with frequency and exhibits an inductive behavior. As the output impedance increases with frequency, the high-frequency noise at the output is not attenuated and may couple to the amplifier's input, bypassing backwards through the feedback network. To prevent noise from coupling into the inputs via the feedback network, an input resistor Rin is connected between the sum node and the inverting terminal of the operational amplifier, forming a low-pass filter with the amplifier's input capacitance as shown in Figure 3.37.

C2 II

Vin

E-field

R1 -I-"

Vn

Vout in -field

Figure 3.36 Noise coupling into amplifier's input.

140


Ii

Vin 9

R1

C2

Rin

,~/x/x,

Vout

+ Figure 3.37 Preventing high-frequency output noise coupling into input.

3.8 Op-Amps Driving Capacitive Loads Transmission lines connecting op-amps provide parasitic capacitances which tend to load the op-amp. To these parasitic capacitances, we must add load capacitances, which are predominant in many wide-bandwidth situations. Capacitive loading effects should always be considered in wideband applications. PCB capacitance can increase substantially for long signal runs over ground planes in high dielectrics. For example, it is not unusual for long runs of signal to have capacitance to ground of over 100 pF (e.g., G-10 dielectric at 0.03 inches above ground has a capacitance of 22 pF/foot). Capacitive loading of op-amps can cause the settling time to be greater than desired. One of the methods to overcome capacitive loading is to use overcompensation of the amplifier. This reduces the amplifier bandwidth so that additional load capacitance does not affect the phase margin. In general, any amplifier using external compensation can be overcompensated to reduce bandwidth, which restores more stability against capacitive loads by lowering the amplifier's unity gain frequency. Capacitive loading of an op-amp reduces phase margin and may cause instability. Another approach to reduce the instability problems is by forcing a high-gain noise, where use is made of resistive or RC pads at the amplifier input, as shown in Figure 3.38. In this technique, an extra resistor R d is added, as shown in the figure, to work against Rf to force the noise gain of the stage to a level higher than the signal gain (assume unity). If we assume that C 2 in Figure 3.37 is such that it produces a

3.8. Op-Amps Driving Capacitive Loads

Vin 0

141

Vout

,'~

O

Rd=Rf / 10 Figure 3.38

RL

~CL

Improving the stability of capacitively loaded op-amps.

parasitic pole near the amplifier's natural crossover, this loading combination could lead to oscillation due to the excessive phase lag. However, connecting Ro to a higher amplifier noise gain produces a new 1/,8 open-loop rolloff intersection nearly a decade lower in frequency. This is set low enough that the extra phase lag from CL is no longer a problem and amplifier stability is restored. A disadvantage of this method is that the DC offset and input noise of the amplifier will increase. An optional series capacitance Cd can be added to R d, and the noise is only confined to a region ~RdC d. Another approach for capacitive load compensation is shown in Figure 3.39. It is a simple isolation technique, with the use of an out-of-loop resistor R t t o isolate the capacitive load. This method can be applied to any amplifier, with the small disadvantage that there is a reduction in the amplifier bandwidth a s R t and C L work to reduce the bandwidth. In high-speed amplifiers and applications where the lowest setting time is critical, even small values in the load capacitance can be unfavorable for the frequency response, as in the case of driving analog-to-digital converter inputs. High-speed ADC inputs are usually capacitive in nature. The amplifier must be capable of driving the capacitance, but it must also keep the bandwidth and settling-time characteristics. In applications requiring the drive of high impedances, as in ADCs, we do not have the convenient back termination resistor to dampen the effects of capacitive loading. At high frequencies, an amplifier output impedance is rising with frequency and acts like an inductance, which in combination with CL causes oscillation. In general a small damping resistor R t

142

3. Noise Issues in High.Performance Mixed-Signal ICs

Rin Rt

1

Vin 0 Rb

CL-]-

RL

-Vcc

Figure 3.39 Isolation technique in capacitively loaded compensation.

which is placed in series with CL will help restore response. The recommended value of R t will optimize response, but CL will also degrade the maximum bandwidth and settling performance. In the limit RtCL, the time constant will dominate the response. In any given application, the value for R t should be taken as a starting point in an optimization process. The example shown in Figure 3.40 provides feedback correction for the DC and low-frequency gain error associated with R t. Active compensation can only be used with voltage-feedback amplifiers.

Rf

Cf

I1

Rin

V~n

Rt O

Rk

Vout

j_o ~

Figure 3.40 Feedback correction for the DC and low-frequency gain error.

3.9. Load Capacitance from Cabling

143

In this current, there is the DC feedback from the output side of the isolation resistor R t correcting for errors. The AC feedback is returned via Cf which b y p a s s e s R t [ef at high frequencies. With an approximate value of Cf the stage can be adjusted for a well-damped transient response. We still would have a bandwidth reduction and slew-rate reduction. However, the DC errors can be very low. There will always be a need to tone Cf and CL even if this is done well initially; any change to CL will alter the response away from the flat response.

3.9

Load Capacitance from Cabling

Transmission lines are widely used in wideband operational amplifiers such as the one shown in Figure 3.41. In the figure, an operational amplifier driver uses at its output a matched resistive impedance (R t = 93 ohms) to the transmission line connecting the driver and receiver. In the figure the line is a 93-ohm coax line. However, twisted pairs or stripline configurations (e.g., in a PCB) could have also been used. The differential receiver terminates the line also with a resistive impedance of 93 ohms. The receiver stage recovers a noise-free 1-V signal which is referenced to system ground. In this configuration there is only resistive loading to drive the amplifiers at the source, which provides amplifier stability and minimizes distortion, line reflection, and other time-domain aberrations. There is a 6-dB loss associated with the line source and load terminations, but this can be easily made up by a 2• driver stage gain. The most effective way to drive a long line is to use a transmission line, which has been standard for video signal for many years. A transmission line which is correctly terminated with pure resistances does not look capacitive, but instead a controlled capacitance and inductance exist, providing a

Single-EndedDriver Vin,, I~Rt-93ohms. ( ) ~

Receiver

Differential

93ohmsCoax

Vout

Rt GroundA

I

\

'

L.

.

.

.

.

I

Figure 3.41 Properly matching transmission lines to op-amps.

144


characteristic impedance of Z o = 1/N/-~. Correctly terminated transmission lines have impedances equal to their characteristic impedance. Unterminated transmission lines (on either the driver or the receiver side) behave approximately as lumped capacitances at frequencies fc <

NOISE IN PHASE-LOCKED

LOOPS

Because phase-locked loops operate on the phase of signals, they are susceptible to phase noise and jitter. We examine two important cases of noise in PLL: when the signal contains noise, and when the VCO introduces noise. f ( t ) = A sin(wct + ~in (t))

(3.57a)

g(t) = B sin(wct + (J~out).

(3.57b)

166

3. Noise Issues in High-Performance Mixed-Signal ICs (o in = o) fr +

Ao~

Phase Detector

LPF

VCO

T

o) out

feedback 1/M

Figure 3.63

Phase-locked loop in locked configuration.

As previously outlined, the transfer function (Figure 3.64) is given by 2 (.O n

H(s)

s 2 + 2 P WnS 4- (O2"n

(3.58)

If ~bin(t) is varied slowly such that the denominator of the transfer function is still close to w 2n, H(s) remains close to unity, showing that the output phase follows the input phase, which is the natural PLL definition as a tracking system. If ~bin(t) varies at an increasingly higher rate, the transfer function equation shows that the output excess phase ~bout(t) drops, eventually approaching zero and providing g(t) = B sin w c t. In fast variations of the input excess phase, the PLL fails to track the input. The input phase noise spectrum of a PLL is dependent on the characteristic low-pass transfer function when it appears at the output.

O,n

LPF

VCO out

Figure 3.64

Linear model for transfer function calculation.

3.15. Basic Topology of a Phase-Locked Loop

3.15.3

167

P H A S E N O I S E I N VCOs

The phase noise in the VCO can be modeled as an additive term ~bnvco, as shown in Figure 3.65. We are assuming ~bin and ~bnvco are uncorrelated. We set ~bin(t) = 0, which means the excess phase noise of the input is zero: q~out(S)

~bnvco(S)

_

-

2 (.O n

(3.59)

2"

s 2 + 2 p WnS + Wn

This transfer function has the same poles as before, but it contains two zeros at Wzl = 0 and Wz2 = - w f, characteristics of a high-pass filter. The zero at the origin means that for slow variations in ~bnvco, ~bout is small. The rationale is that in lock, the phase variations in the VCO are converted to voltage by the phase detector and applied to the control input of the VCO to accumulate phase in the opposite directions. Because the VCO voltage phase conversion has nearly infinite gain, for slowly varying Vc, the negative feedback suppresses variations in the output phase. Let us now assume that we experience a rate increase in ~bnvco. Then, the magnitude of Kvc 0 / s and the loop gain decrease, allowing the virtual ground to experience significant variations. As the rate of ~bin approaches wf, the loop gain is reduced by the low-pass filter. As s ~ co, q~out ~ Q~nVCO, which is to be expected because the feedback loop is essentially open for very fast changes in ~bnvco. If we apply a small step to the power supply and find the time required for the input-output phase difference to settle within a certain error band, since such a step affects mainly the VCO output, we can use Equation (3.59) to predict the circuit's behavior. For a phase step of height, the output assumes the form q~out(t) = 05l

p

cos X//1 -- p2 Wnt + V'I - p2 sin N/1 - p2 Wnt] e-POint.

nvco1 1t)

out

O,n

LPF

Figure 3.65

VCO

Adding phase noise to the VCO linear model.

168


This means that the output initially jumps to r and subsequently decays to zero with a time constant (pWn)-1. It is therefore desirable to maximize pw n for fast recovery of the PLL. We can conclude that to minimize the VCO phase noise contribution, the loop bandwidth must be maximized. Unfortunately, this may conflict with the case where the PLL input contains noise. In cases where the input has negligible noise, the loop bandwidth should be maximized to reduce both the VCO phase noise and the lock time. Other noise sources can be considered as shown in Figure 3.66. In the figure, a frequency synthesizer and a divider provide the input to the PLL. The noise sources in the figure are the phase detector noise t~pd,n, frequency divider noise ~boq,n, low-pass filter noise ~bf,n, voltage-controlled oscillator noise ~VCO,n, and feedback loop divider noise ~bdi,n. An IF filter is also used in the feedback loop to limit even more possible noise that could have been generated by the VCO.

3.15.4

LOW-PASS FILTER NOISE

If the low-pass filter is a passive one (i.e., a simple RC lag or lag/lead network), there are two major sources of noise: First, basically some types of capacitors and carbon resistors can generate a substantial amount of 1/f noise. As a result, the low-noise design would require the individual selection of low-noise capaci-

$ dq,n

~._rn fr Synthesizer

f,]Divider =fr/ Qbyt

$ pd,n

~~

$ f,n

(~~~,,~~

LPF ,~

~rn/Q

di,n Figure 3.66

~ vco,n Dividerby N Other additive noises in PLL.

~I

IFFilter ]

3.18. Phase Noise in Phase Detection

169

tors and resistors. The second source may be the decoupling resistors Rdc, separating the varactor circuit from the loop filter and the phase detector. The respective noise power density is given by

Sf = 4KTRdc = 1.66 • 10 - 2 0 Rdc

3.16

( g 2 [ Hz).

(3.60)

Phase Noise in DC Amplifiers

As shown in Table 3.2, in several cases we may need to introduce either an active lag/lead filter or a DC amplifier. The design of a low-noise amplifier is somewhat complicated. Typical equivalent input noise voltage is only several nV/X/-H-~z, with the comer low frequency between 10 and 100 Hz. Similar performance is also achieved with some modem IC operational amplifiers.

3.17

Phase Noise in High-Frequency Amplifiers

It has been found that the power spectral density of the flicker noise close to the carrier is approximately given by 10-11.2 S ( f ) -- ~ -~ S(fJwhite

f

(3.61)

for the range of 5 to 100 MHz, quite independent of the transistor type and even of the multiplication factor. Experiments proved that the intrinsic direct phase modulation of the RF carrier by transistor was responsible for the phenomenon. The improvement has been achieved by applying local RF negative feedback using a small unbypassed resistor in the emitter, typically from 10 to 100 ohms. Low amplifier currents and high voltages help to keep the 1/f noise current low.

3.18

Phase Noise in Phase Detection

The best phase detectors are double balanced mixers with Schottky barrier diodes in the ring configuration. A further improvement may be achieved by placing two diodes in each arm. Measurements performed reveal that 10-14+1 Spd(f ) ~

nt- 10 -17

f

(3.62)

170


On the other hand, it has also been found that noise properties of popular digital phase frequency detectors in the range from 0.1 to 1 MHz can be modeled as 1010.6+--0.3

S(f) =

3.19

.

f

(3.63)

Phase Noise in Digital Frequency Dividers

Since the frequency or phase modulation index decreases proportionally to the division factor N, the ideal noise figure is Fdivide r -- --20 log N.

However, additional noise is generated in the divider itself. The output phase noise is given by Sdi(f ) :

3.20

Sdi,in(f) 10 -14 N2 + f + 10 -16"5.

(3.64)

Phase Noise in Frequency Multipliers

The noise for properly designed transistor frequency multiplier is given by 10 -14 Smu(f ) ~" ~ - 1 -

10 -16"5.

(3.65)

f In diode frequency multipliers the flicker noise level is higher, given by 10-12.9/f.

3.21

Phase Noise in Oscillators

In accordance with several models, any oscillator can be simplified into a loop containing a resonator and an amplifier limiter. As a result, its output spectral density is given by Svco,n(W) = Sa,n(W)[1 + (090/2QL~O)2], where the amplifier limiter noise is given by Sa,n(f)

= a_ 1/f +

ao,

(3.66)

3.23. More about VCO Design and Noise

171

and the magnitude of the flicker noise constant a_ 1 has been found experimentally in the range from 5 to 100 MHz to be a-1 = F-1 • 10 -112

(rad2).

The white noise constant is the ratio of the noise power ~bnoise(t) 2 to the oscillator power Po reduced to 1-Hz bandwidth and multiplied by a noise factor Fo: a o = FoKT/P

o ~

4.0 •

lO-21Fo/Po

(rad2/Hz).

A power law relation can also be established: Svco,n(f) = f2

[]h-l7+ 7J5h~ hl- + ~ +- -~o

h2 9

(3.67)

Here, h 1 = a 1/4Q 2 _ / 2 lfo, -

-

L ,

hl=a

h o = a o / 4Q L, 2 / 2 h2 -'- ao fo,

where QL is the oscillator quality factor andfo is the oscillator resonance frequency. Finally, the general oscillator noise equation is 1 10 -11"6

Svco,n(f) = f 2 f-3

3.22

1 10 -15"6 1 10 -11 10215 ] Q2L- -~- f2 - - ~Q 2 -~ f f2 t- fo "

(3.68)

Phase Noise in Reference Frequency Generators

The reference generator in low-noise PLL systems (frequency synthesizers) is a spectrally pure crystal oscillator. A low close-to-carrier noise requires the use of resonators with the highest possible Q. For an average crystal oscillator, the following noise equation is applicable:

Sosc n(f) 1 37.25f~ 72 39.4f2 1 10 -12"15 10 -14"9 fo2 -f~10+ 10+~ ~ + f2 9

3.23

(3.69)

More about VCO Design and Noise

In the VHF region, the fabrication of VCOs using hybrid elements is still very common. Unfortunately, this approach can result in stray capacitances and parasitics which could cause problems in circuit development. The control of the output

172


frequency range is not an easy task in such VCO designs. For example, the equivalent series self-inductance in ceramic multilayer capacitors introduces a series resonant frequency which affects the tuning bandwidth. As the self-resonant frequency is exceeded, the reactance of the ceramic capacitors changes polarity, resulting in increased oscillation. In the circuit of Figure 3.67, a Colpits oscillator with the emitter in series with a capacitor connected to ground is shown. The reactive elements consist of capacitances C1, C2, and Ct along with inductance L 1. Ct can be realized with two varactors placed back-to-back for better AC performance. The series combination of L 1 and the varactors behaves like an inductor. The varactors are used to reduce the inductance from L 1 in order to vary the oscillation frequency. C1 is a forward-biased base-to-emitter junction capacitance that is approximately equal to C 1 -- Cje o "k- gm'/'f,

where Cjeo is the base-to-emitter capacitance in the zero-biased depletion region, grn = Ic/Vt, Ic is the collector current, Vt is the threshold voltage, and zf is the base transmit time. Notice that in Figure 3.67 C 2 has a series of parasitic inductance. This related self-resonance frequency is generally an inverse function of the capacitance. The oscillating frequency is roughly equal to fosc = 1 / [277"L1C1C 2 / ( C 1 + C 2 ) ~

(3.70)

V 2

V Figure 3.67

Colpits oscillator.

3.24. Modeling RF Interference at the Transistor Level

173

whereas the negative resistance is Rneg = gm /

w2C1C2,

(3.71)

where w is the operating frequency. A series inductor L 2 from a nonideal ground introduces an additional critical frequency given by fcr -- 1 /

[2~(L2C2)~

(3.72)

The circuit could not sustain oscillation above fcr as a result of the change in polarity of the effective reactance in the emitter branch. Therefore, the series resonance frequency acts as the upper bound of the tuning range: f~ = 1 / 2 77"(L2C2)0"5.

3.24

(3.73)

M o d e l i n g R F I n t e r f e r e n c e at the Transistor Level

In electronic circuits, the RF energy is first picked up by cables and associated wiring and then conducted directly into the circuits. In essence, the RF signal is envelope detected by the nonlinear characteristics of the semiconductor junctions. The interference problem can be modeled as the low-frequency components that are produced when high-frequency RF-induced currents flow through a nonlinear device. The low-frequency components which are dependent on the modulation of the RF signal are often within the passband of the low-frequency circuits and are processed as if they were the required signals. With the understanding of this rectification process, the interference effects in semiconductors can be simulated and circuit susceptibility in different environments can be assessed. Using a time domain approach in which RF waveforms are corrupted is very time-consuming and is more suitable to SPICE models. The approach discussed here is to develop models of semiconductors in which the low-frequency components resulting from rectification of an RF signal are included [2]. The parameters of the rectification components in the models depend on the characteristics of the semiconductor device itself and also on the external circuit of the device. Of primary importance are the device capacitances and the frequency, power level, and equivalent impedance of the interfering RF source models. These are discussed, dealing with PN junction transistors which include rectification effects. Parametric studies involving ideal diodes are described in which the expected range of each of the rectification parameters is estimated, as well as their dependence on capacitance, frequency, RF power, and equivalent

174


RF impedance. Reference [2] describes the use of these models in analyzing interference in integrated circuits with a SPICE-like analysis program.

3.24.1

RECTIFICATION IN PN JUNCTIONS

Rectification is the mechanism by which out-of-band RF and microwave signals are converted to in-band signals. This process is very much an envelope detector. In such cases the unwanted signals are detected by electronic devices intended to process other signals. The detected response varies with the envelope of the RF signal, which will depend on the characteristic of the RF source. These lowfrequency signals may be very similar to those normally present in a circuit. Once the RF signal is rectified and mixes with the data from the desired signal, it is difficult, probably impossible, to remove the interference effect even with additional processing. The only way to avoid this problem is through adequate shielding, preventing the interference signal from entering the rectification process. Rectification is the result of the nonlinearities inherent in semiconductor devices. Most semiconductor devices are built of PN junctions which have nonlinear current voltage characteristics. Figure 3.68 shows how this nonlinear behav-

/

Normal Diode

Characteristic

Characteristics

_.

current waveform I I ~

Voltage Waveform

Figure 3.68 Illustration of rectification in an PN junction. The AC component of voltage causes an offset in the DC component of current flow.


175

ior is used to rectify an AC signal. In the figure, a continuous sinusoidal voltage is applied to the junction with a DC bias voltage. The current flows in series of nonsymmetrical pulses. The average value of the current pulses is higher than the DC value of current that would flow if only the bias voltage were present, so it appears as if the signal has caused a DC offset current to flow. As the bias voltage level is changed, the offset current also changes; thus, a locus of average current vs DC bias voltage can be obtained and plotted as shown in Figure 3.68. This can be interpreted as an RF-induced diode l-Vcharacteristic. This is probably what a low-frequency circuit sees of the diode. At a given bias voltage, the DC current flow is given by RF-induced characteristics if RF is present. In general, a biased diode or transistor junction will experience an increase in average current when exposed to RE The circuit in Figure 3.69 models the diode characteristics under RF conditions [3].

(~ Id Ix

Rx D1 ~

Id2

Idl

D2

~ld Figure 3.69

Circuit model of a diode including rectification effects.

176


The model of Figure 3.69 is composed of two diodes, a current source, and a resistor. The diode D1 models the diode with no RF energy on it and follows the standard diode equation

,o

(exp q 1)

(3.74)

where ID1

-'-

Va Ias q K T n

= = = = = =

current through diode D1 voltage across D1 diode reverse saturation current electron charge Boltzmann's constant junction temperature in kelvins emission coefficient.

The elements D2, I x, and R x model the offsets in the device characteristics due to RE The current source I x depends on the RF power level, frequency, and RF source impedance. For large RF signals, I x is proportional to the square root of the RF power PRF by the relation I x = K VPRF,

(3.75)

where K is a constant with power, but is dependent on the frequency and source impedance of the interfering signal. The value of the resistor R x is also dependent on the frequency and source impedance of the RF signal, but it is independent of the power level of the RF energy. In general, R x increases with frequency or increased source impedance. Figure 3.70 shows a piecewise linear approximation of RF-induced diode characteristics.

3.24.2

I N T E R F E R E N C E OF R F E N E R G Y I N T R A N S I S T O R S

Diode transistors go through a change in DC characteristics when exposed to RF. A low-frequency circuit unable to respond directly to the RF energy will exhibit changes in transistor bias points caused by RF-induced changes in transistor characteristics. The change is due to current and voltage offsets resulting from rectification of RF signals in the transistor junctions. In Figure 3.71 we see an oscillation of the DC characteristics for a 2N2369A transistor. When the transistor is stimulated by 90 mW of RF power at 220 MHz [3] on the collector lead, the characteristic curve appears to shift to the fight by


id/

Ix

--

177

cNh ramaa~teDi~

I

.

.

.

.

.

.

.

.

.

A

current waveform

Figure 3.70

I

I

i~

I

Vd

Voltage Waveform

Piecewise linear approximation of RF-induced diode characteristics.

4.5 V. Different responses occur for different transistors at different injection points. Figure 3.72 shows the change in DC characteristics of a 2N2222A transistor stimulated on its collector with 90 m W of RF power at 220 MHz. In general, for an N P N transistor with RF conducted on its collector, the collector current will increase at voltages near saturation. The 2N2222A transistor shows this

~_/._ lc(ma)

(a)

j[~ Ic(ma)

28 21

21

(b)

F

I

14

I 0

2

Figure 3.71

4

6

8

10

VCE (volts)

12

I

0

2

/I/I

4

I

I

I

i,~

6 8 10 12 VCE (volts)

Characteristic curves for a 2N2369A transistor (a) without an interfering signal and (b) with a 90-mW 220-MHz signal entering the collector.

178


~ lc(ma)

~ lc(ma )

(a)

28 !-

21

21

14

14

(b)

7

0

2

4

6

8

10

12

0

2

VCE (volts) Figure 3.72

4

6

8

10

12

VCE (volts)

Characteristic curves for a 2N2222A transistor (a) without an interference signal and (b) with a 90-mW 220-MHz signal entering the collector.

effect as a rounding of the characteristics at voltages near zero. These effects can also be observed at higher frequencies, but the magnitude of the effects decreases. When an NPN transistor receives RF energy on its base or emitter leads, these effects are usually accompanied by a fl decrease, and it is more pronounced at low RF power levels. Furthermore, it has been observed that the base-emitter voltage decreases as the RF power increases. If the transistor is biased in the forward region, the normal base emitter voltage is usually around 0.7 V for a Si NPN transistor. RF power on the order of 1 mW can reduce this to zero. In general, significant base-emitter decreases can occur at very low power levels, which is a great degradation in sensitive analog circuits that respond to small bias voltages. Significant voltage offsets in feedback amplifiers have been observed at power levels as low as 1 /zW [3]. The Ebers-Moll representation of a transistor model is now modified to account for RF effects. Figure 3.73 shows the standard Ebers-Moll model for an NPN transistor. The diode characteristics which represent the base-emitter and base collector junctions are given by

If:Iof(expCqV 1)e x fqVbe~ ) ,

IR = /OR ~e p ~ - ~ - j - 1

(3.77)


C

?; c

Ifo~f

B C)

3~ IR

Ib V

If

IR o~R

Figure 3.73

179

The standard Ebers-Moll model for an NPN transistor.

where /Of and /OR are the diode forward and reverse saturation currents. The transistor forward and reverse betas, flf and fir, are related to the values of af and a r by

fir-

af

(3.78)

ar

(3.79)

1 _ ar"

In order to account for the rectification in the transistor junction, the rectification model for diodes previously illustrated in Figure 3.69 was substituted for each diode in the standard Ebers-Moll NPN transistor model of Figure 3.73.

180


Figure 3.74 shows the modified Ebers-Moll model after the substitutions. Using this approach the rectification in each junction is treated separately. The current sources Ixe and Ixc are dependent on the RF level power, frequency, and RF source impedance. For large signal, they are proportional to the square root of the RF power level,

Ixe-- Ke'V/PRF lxc =

(3.80)

KcX/PRF,

(3.81)

C

Ic

B 0

IR o~R

Figure 3.74

Ib

.c ']:;

~

'xe

Re

3

E

~ Ie

IR

V

The Ebers-Moll model for an NPN transistor modified to include interference effects.


181

where Ke and Kc are constants with power but depend on the frequency and source impedance of the interfering RF signal. In general, K e and K c decrease with increasing RF frequency. The values of R e and R c are constants with RF power at a given RF source impedance and frequency, and, of course, they increase with increasing source impedance and frequency.

3.24.3

WORST-CASE CALCULATIONS

It is often required just to get the worst-case response of a circuit under certain environmental conditions. This scenario calls for a worst-case analysis for which the Ebers-Moll transistor is well suited. The procedure calls for varying the values of components I• Re, I• and R e until a combination is found that produces the worst output response. The analysis done in [3] produces the model shown in Figure 3.75, where r includes the lossy elements within the diode itself,

Id r I

+

I

Rx C._~_

Ix

II

II Figure 3.75

D1

T

D2

I I

Model of a diode or transistor junction.

182


such as bulk resistance, and those external to the diode itself, such as losses associated with cables and printed wiring. C is a shunt parallel capacitance across an ideal diode D1. The worst-case parameters are given by Kmax

R2)2 (1 +472)1/2] 1/2 4/}x? + (1 + ~ x ~ l - + 4r2) 1/2

8~-~[/~x(1 + R2)-

/}x

kx(min ) = Js9,~

~(1-

[1 + (1 27 + 4~2) 1/2]

= [1 + (1

(3.82)

+ 4~2) 1/2] 2?

Ix(max )

= KmaxV/-PRF,

where

Rx = ~oCRx ~" = ooCr. 3.24.4 CALCULATING MAGNITUDE OF OFFSET VOLTAGE AT EMITTER-BASE JUNCTIONS Measurements and calculations have shown that rectification in a bipolar transistor operating in linear mode occurs principally at the emitter base junction. Furthermore, as long as the RF voltage at the junction is not significantly greater than 26 mV, the rectified offset voltage A V follows a square law relationship and is proportional to the absorbed power [4]. The offset voltage is given by

1/2

AVpa 2KTq[RsaeogC.n.P2el]

(V/W),

(3.83)

where C.,r/Ae is the base emitter junction capacitance per unit area, R s is the base sheet resistivity, Pe is the emitter perimeter, and Pa is the absorbed power in the emitter base junction. The preceding equation is correct for the limiting case where there is severe crowding of the AC signal near the edges of the transistor emitter and the device may be viewed as a distributed circuit. At low frequencies or where the emitter width 2L is so small that sufficient crowding does not occur, the equation takes the limiting case

where VT =

KT/q

= 0.026 V.

AV

4A e

Pa

VTWC~P2,

(3.84)

3.24. Modeling RF Interference at the Transistor Level 3.24.5

183

RFI RECTIFICATION IN JFETs

For a given DC bias and a given frequency, the JFET exhibits an increase in the drain current as the absorbed RF power increases. For low levels of RF power, the drain current is proportional to the power absorbed in the device. Empirically, this phenomenon can best be explained through the use of a standard hybrid r smallsignal FET model with the addition of an RF-induced noise current source in the drain, as shown in Figure 3.76. This source generates an offset current AId. The rectification effect can be modeled in terms of the nonlinearity of the gate voltage drain current characteristics in order to calculate Ia, the average value of the drain current. An analysis done in this respect shows that V 2 dg m

I d ~ Id(Vo) +---s ~ 4 dVg'

(3.85)

where gm is the device transconductance and at bias point Vo, Vo is the quiescent gate source voltage, Vg is the gate voltage, and Vp is the amplitude of RF noise source Vp sin wt. The preceding equation shows that for low levels of absorbed RF power where Vp is small, the rectified offset current appearing in the drain is proportional to the square of the RF voltage at the gate source junction, which is proportional to the absorbed microwave power. In terms of absorbed power P~, the induced RF voltage at the junction is given by AI d _ 1 dg m Pa 2w 2 C 2g R i dVg

(3.86)

D

GO gmV9

$ Figure 3.76

The standard hybrid "rr small-signal FET model with an induced RF noise current.

184


where Cg is the gate-to-source capacitance, and device input impedance. Finally, from the above last two equations,

Ri

is the real part of the FET

my__ V__~dgm

(3.87)

4 gmdVg" The term gm is given by the expression

O0[1

1/2

I,

(3.88)

where G o is the conductance of the metallurgical channel, discounting the presence of depletion regions; 453 is the PN junction built-in voltage (about 0.6 V); Vp is the pinch-off voltage = N d d2/(8eeo + ~ ) ; Vg is the gate voltage; d is the channel thickness; and N d is the doping concentration in the channel. By taking the derivative of this last expression, we finally obtain

A V = 2co 2C2 Ri

1/2

2 ( q ~ - Vp)(q~B- Vg)

1/2

1-

"

(3.89)

~ - Vg

Operation of this FET device near the pinch-off voltage drives the denominator of this expression toward zero and increases the nonlinearity. Therefore, the amount of equivalent offset voltage increases. This situation becomes more serious with the higher capacitive reactance of the gate junction as its reversed bias is increased.

3.25

RFI Effects in Digital Integrated Circuits

In the previous section, the modified Ebers-Moll model for a bipolar transistor was developed for predicting RFI effects in bipolar integrated circuits. We now show that the modified Ebers-Moll model can be used with SPICE to provide useful information about RFI in bipolar integrated circuits [3]. The basic situation of interest is illustrated in Figure 3.77. Electromagnetic energy incident on the outer enclosure of an electronic system is coupled through the apertures in the skin to the interior of the electronics. The electromagnetic field inside the enclosure will couple and induce RF voltages on the system cables. The RF voltages are conducted to the semiconductor devices such as the

3.25. RFI Effects in Digital Integrated Circuits

185

FI

I

Cable

I I I I I I

L

I

Susceptible Electronics

@

r

I

V

I I I I

_1

APERTURE I

I

\

Incident Electromagnetic Energy Figure 3.77 Incident RF energy on susceptible electronics.

IC electronics. This scenario is shown in Figure 3.78. The RF voltage induced on a system cable is modeled by the Thevenin equivalent voltage s o u r c e Vgen with impedance Rgen. The bipolar IC is a NAND gate. The case that is being modeled is the one in which the NAND gate input voltages are high and the NAND gate output voltage is low in the absence of RF energy. The RF signal is injected into the output terminal. The electronic circuit analysis program SPICE is used for analyzing ICs and has been used in the past to predict normal IC operation. Most ICs can operate in an ideal environment in which no RFI signal is present. However, in most cases there is no ideal environment, and the IC must operate in the presence of strong RFI. Standard SPICE models can be used for all IC components not affected by RFI. The transistors into which RF is injected are modeled using the modified Ebers-Moll model previously described. The modified Ebers-Moll model is implemented by using the external model function available in most SPICE programs. Similar procedures can be applied to other cases where an RF signal is injected into the terminals of a small-scale bipolar IC. Results show that NAND gate operation can be affected significantly by RF injected into several of its terminals. However, the most susceptible case is that of Figure 3.78, in which an RF signal is injected into the output terminal when the

186


GATE

I Thevenin I

NAND

I

Vin

vnl

V Vn:

Rgen Vgen]

Figure 3.78 Modeling noise sources in a gate.

normal output voltage is low (Vout < 0.4 V), which is when both inputs to the NAND gate are high (Vin > 2 V). When both NAND gate input terminals are high, the RF injected noise into the output terminal can cause the output voltage to change from its normal low value (Vout < 0.4 V) to an RF-induced higher value (Vout > 0.8 V). This is the situation that can be simulated using SPICE. Shown in Figure 3.79 is a circuit schematic of an NAND gate (7400). The 7400 NAND gate includes four resistors (R1-R4), four transistors (T1-T4), and three diodes (D1-D3). The dual emitter transistor T1 can be modeled by a single emitter transistor, and the diodes D1 and D2 can be modeled by a single diode Din. The RF interference can be accounted for by assuming that all the incident RF power is absorbed in the output transistor T4. One result is that the standard component models available in SPICE can be used for all NAND gate components except the transistor T4. The transistor T4 is modeled using the modified Ebers-Moll model shown in Figure 3.79. The modified Ebers-Moll model is shown in Figure 3.80. To implement the current-dependent current sources Ife and/re in the modified Ebers-Moll model, current-sensing resistors Re,sens e and Rc,sens e are placed in the emitter and collector circuit as shown in Figure 3.80. The current sources Ife(CeFIF) and IRC(CeRIR) are made to depend upon the voltage drops V12-V13 and V12-V11 across the resistors Re,sens e and Rc,sense, respectively. The result is that Ife = AF(V12-V13) and Ifr - AR(V12-V11), where the values of AF(aF) and AR(aR) are the forward

3.25. RFI Effects in Digital Integrated Circuits

187

NAND --

--

--I

I I

R1

I

> R2

R3 I I

I

T1

,

I I

'

I

,(

V

a u gE

& A~

=m

,

U

PIE:^ 3 ; s.29 "j

a

s

asaost:;;;

- e$+s3 - 2 53 -

a

-

asm m 8 .5!mG+

- .s

338'94

1, 5 2 ! j .g: 5;; L I E =Y OG gOkz2c4gZmgc-$33 5 5 2

0

5

ELY g.3 %

l C ) U o + o g o m m

3

-g , E

e

.5 m a =

2s g

8

.-a$

$..EEL%

3

g>

a

'G

a

V)

0 %

KJ

4-

g

& 2 5

8

u 0 0 c

C, p.gc

* *

a

-.--

u

8 0

-c

r n r n

3

d 0 .-*

d j z0 .sc Y $ 3 m

a E 3 . s J =.-

V)

0

. ? 2 g Z m" M - ' E $ g s8.2 2.,,i P.5"U 5 s : a p?

4> s

- 0 4 +OgF ,=

2o 's 2 g -g Z - 2 & ~ 2 .8a6> 8 * U J = m m a b 9 3 . 3.;; 3 & 3 L Z - o Z S 25 g z s 2 $22.m*% 2 a . 2 9 . Z 5 3 P E5 26

12

8

+: ag a~ $$z@ 9" 2 o g o 25

,

=

g o L L =5 CA )ta

g b 2 & 4g . s a 5 :a 3g

8e .%g sg

4. Computational Methods in the Analysis of Noise Interference

P

4

s

e g C 9 2

b

6

2

9

#

e2

e C9

z2

4.2. The Method of Moments in Computational Electromagnetics

I

I

---

EMProblem

ExactSolution

I ApproximateSolution~

I

4,,

I MaxwelrsEquations "l

Integral Representation

Trans. Line Method

203

Differential I Representation l

Finite Elemen Method

IiF~~teeDiff" Domain

I I Representati 'n'e~'a' on

~-EMqaat,e/isn

,,

]

i Geometrical G'[;~i~setrical ] [Theory

i Diffraction

:oO"

iffraction

Physical 1 Theory Diffraction

Figure 4.3 Overview of techniques available in computational electromagnetics.

electromagnetic interference. The reader is advised to consult these and other related references for a more in-depth study of the method of moments.

4.2.2

MATHEMATICAL THEORY OF THE METHOD OF MOMENTS

In the realm of functional analysis, the solution of functional equations is addressed by interpreting such solutions in terms of projections onto subspaces of functional spaces, as shown in Figure 4.4. The general concept of solving functional equations by projection onto subspaces has had different names through the years" method of moments, method of weighted residuals, and method of projections.

Fapprox-- (gl(x),F(x,y))

gl(x) + (g2(x),F(x,y)) g2(x)

Fapprox = Flgl(x ) --- Fege(y)

204


F

f l 2 ( x ~

'

\

.

.

.

/'-

\ \

-~_..

\

\ \

-

Figure 4.4

.

~

/

_4k/ F approx

-

Approximate solutions by projection methods using functions.

where

Fl= (gl(x),F(x,y)) =

f g,(x) . F(x,y) dx og

F 2 = (g2(x),F(x,y)) = f g2(x).F(x,y)dx. oz

Consider the functional equation LF = g,

(4.1)

where L is a linear operator, g is a known function, and F is an unknown function which we need to determine. We can represent F by a set of functions {F 1, F 2, F 3 , . . . } in the domain of L in a linear combination that will take the form N

F = ~ j=l

otjFj,

(4.2)


205

where c~j are scalars to be determined. Fj are called expansion functions or basis functions. Notice that j has a limit of N; hence, for computational purposes Fj must be finite, which means that we get an approximate solution when we substitute Equation (4.2) into Equation (4.1) to get N

e~jLFj -~ g.

(4.3)

j=l

The objective now is to solve Equation (4.3). Notice that we have N unknowns. This equation can be solved if we transform Equation (4.3) into a system of N linearly independent simultaneous equations with N unknowns. Thus, we multiply both sides of Equation (4.3) by a set of N weighting functions {W 1, W 2, W 3, . . } in the range of L, and then take the inner product of (4.3) with each W i. Because of the linearity of the inner product, this transformation yields N Z ~j <Wi, j=l

where i = 1, 2, 3 . . . . . as

LFj) =

<Wi, g),

(4.4)

N. The inner product of two functions g and w is defined

(w,g) = f w ( x )

9g(x) dx,

o~

which has the following properties: 1. (w,g) = (g,w)*--conjugate symmetric 2. (alw + a2w, g ) = a 1 (w,g) +

a 2

(w,g)--linearity

3. (w,w) > 0 if wl0 and (w,w) = 0 if w = 0 - - p o s i t i v e definite This set of equations can be written in linear form as [C]~ = g,

(4.5)

where [C] is the matrix [C] - [<Wi,

LFj>]

(4.6)

and ~ and g are column vectors

= [ a j] g = [<W/, g>].

(4.7a) (4.7b)

206


If [C] is a nonsingular matrix, its inverse exists, and ct can be expressed by [O~j] --" [C] -1 [(We, g)].

(4.8)

The solution for F is given by Equation (4.2) once the coefficients ctj are found from Equation (4.8); hence, we can now obtain N

F = ~

[C] -1 [(Wi, g)] Fj.

(4.9)

j=l

The term method of moments derives from the original terminology that fx nf(x) dx is the Nth moment of f(x). When x n is replaced by a function W,, we have an expression similar to the inner product. We have continued calling the integral a moment off(x). The method of weighted residuals derives from the following interpretation. If Equation (4.3) represents an approximate equality, then the difference between the exact and approximate LFs is r/

g-

~ otjLFj= R,

(4.10)

j=l

where R is called the residual. The inner products (Wi, R) are called the weighted residuals. Equation (4.10) is obtained by setting all weighted residuals equal to zero. The method of projections can be visualized as follows. The weighting function Fj generate a subspace from which we can approximate F. The weighting function W i generates a subspace into which we project LF. The method of moments then sets the residual equal to the null vector in the weighting subspace. The inner products with each Wi in Equation (4.4) are proportional to the Fj components of (4.3). We can then say that each component of the residual is zero in the weighting subspace, or that the residual is orthogonal to every Wi. When the domains of W i and Fj are the same, we can choose Wi = Fj, and this special case is known as Galerkin's method. When L is self-adjoint, the matrix [C] is a symmetric matrix. Symmetric matrices have several theoretical advantages. However, for computational purposes the evaluation of the elements in [C] may be difficult when a Galerkin method is used. If the domains of Wi and Fj are different, then the weighting functions must be different than the basis functions. This is known as the Petrov-Galerkin method. The simplest way to simplify the computation of the integrals used in the inner products of Equations (4.6) and (4.9) is the use of point matching (or the collocation method). This technique consists of satisfying Equations (4.6) and (4.9) at discrete points in the region of interest. For the method of moments, this


207

is equivalent to choosing the weighting functions to be Dirac delta functions. The integrations outlined by Equations (4.6) and (4.9) are now trivial. This is the main advantage of the point-matching method. The solution, however, is sensitive to the points at which the equations are matched, which is the major disadvantage of this method. Only when care is taken in choosing the points of match are answers with good accuracy obtained. Another choice for solution is that of minimizing the length or norm of the residual given in Equation (4.10). This procedure is called the least-squares method. It can be observed from Equation (4.10) that minimizing R is similar to finding the shortest distance from g to the subspace generated by LFj. By the projection concept, the least norm is obtained by taking Wi = LFj in the MOM.

4.2.3

THE METHOD OF MOMENTS IN ELECTROMAGNETICS

The method of moments has found important applications in the area of computational electromagnetics. Rather than pursuing a generalized approach to this subject [10], we will address the application of the method of moments to the solution of three main types of problems: (1) those where the topology can be represented by thin-wire geometries, (2) those where the topology can be represented by surfaces (including hybrids of thin wires/surfaces), and (3) those where the topology include apertures (including hybrid thin wires/surfaces/apertures). It turns out that problems of these types of topologies are the most common in electromagnetic interference (e.g., EMI resulting from wire/cable emissions, fieldto-wire coupling, penetrations due to holes/seams/joints, or reflections from surfaces). 4.2.3.1

Modeling Electromagnetic Problems Using Wire Geometries

Early in its development the method of moments was first used for treating scattering problems (in the frequency domain) of arbitrarily bent, perfectly conducting, and interconnected thin wires and rods. For radiation (antenna) types of problems, the method of moments can be used to calculate the current distribution on the wires, the near- and far-field patterns, and input impedances corresponding to feed points. In electromagnetic interference, for example, the method of moments can be used to calculate the near and far fields produced by wires and cables, which are notorious conductors of common-mode currents [ 11 ], and often the major sources of radiated EMI. For scattering problems the method of moments can calculate current distributions on scattering surfaces, scattered fields, and radar cross-sections. In electromagnetic interference, for example, the

208


method of moments can be used for modeling field-to-wire coupling problems, especially when wire size L _ h in which lumped-parameter network representations of coupling scenarios are not accurate. In all these problems mutual coupling and retardation effects are taken completely into account; hence, there is no need to make unrealistic assumptions regarding current distributions along wires and rods. The method of moments can consider two-dimensional and three-dimensional conducting structures that can be represented by wires having different shapes and radii. The effects of ground, whether perfectly conducting or imperfectly conducting, can be included. Both lumped and distributed loading can be taken into account, and the wires can be excited at any arbitrary point along their length. We will consider in this section thin-wire problems. The term "thin-wire" implies that L / a > > 1 and a < A, where L is the length of the wire and a is the radius. For thin-wire problems, Equation (4.1) is an integro-differential equation with current distribution along the wires. Thin-wire problems are modeled using the electric field integral equation, or EFIE (to be derived). However, the method of moments can also be used for modeling volume geometries, and the magnetic field integral equation, or MFIE, is the best suited for these types of problems. The MFIE will not be treated in this chapter, but can be reviewed in reference [12]. The problem of finding the current distribution on wire antennas or scatterers is addressed by first stating the boundary condition at the surface of each perfectly conducting wire to be (4.11)

fi X E T = 0,

where n is a unit vector normal to the surface of the conductor, and E x is the total electric field consisting of both incident and scattered fields, as shown in Figure 4.5 for a general scatterer. Hence, E T can be expressed as E T = E s + E i.

(4.12)

The scattered field E s is defined as the field produced by all currents and charges present on the conductor. The boundary value problem represented in Figure 4.5 can be characterized by E s = -jwA A = ~

-

Vcb

f J(r') e j~R s

(4.13a) (4.13b)


209

(b)

i

(a)

t

2a

I I I

Figure 4.5

h~

Boundary value problem for (a) general scatterer and (b) thin wire.

=

1 f e-jkR 4ere P R ds

(4.13c)

s

1 p = - _ V s 9J(r'),

jw

(4.13d)

where the time-dependent term e j~ is suppressed. The term R is given by R = Ir - r' I, where r and r' are defined in Figure 4.5a and k = 2~r/,~. Because of the condition expressed by Equation (4.11), Equation (4.12) can be expressed as

n x E s = -n

x E i,

(4.14)

which holds true at the surface of each conductor. In Equation (4.13), A is the magnetic field vector potential, 9 is the scalar electric vector potential, p is the charge density, J ( r ' ) is the current distribution on the conductor, R is the distance from the current source point to the point at which the field is to be evaluated, and S is the surface of the conductor. For thin wires, we assume the following: 1. Current flows only in the axial direction for each wire. This means that circumferentially directed current radiates very little. 2. Current and charge densities are approximated by a filamentary current I and charge p along the wire axis.

210


3. With the help of Figure 4.5b, Equation (4.14) is satisfied along a path L parallel to the wire axis. This path (L') is displaced a distance equal to one wire radius a from L'. Furthermore, Equation (4.14) is only applicable to the axial component of E i along L. Points along L' are denoted by the length variable f' while those points along L are denoted by f. Using the previously stated assumptions (1) through (3), Equation (4.13a) reduces to -jkR

ES

_ -jwlZ47r f l(f')e-JknR dr'

47telV f p(f,)e R dr'

L'

(4.15)

L'

where R is now the distance between a source point at f' (e' would be the unit vector) on the wire axis L' and a field point at f along L (e would be the unit vector). Using Equations (4.13) through (4.15), we can write ~.Ei

j,o f e~.r

=-~

,) e -jc~

1

Of O e -jkR 0-~-7[I(~')] R d~'.

R d~' jw4creO~

L'

(4.16)

L'

This is the desired integro-differential equation known as the electric field integral equation (EFIE) for current distribution along thin wires. By comparison of this equation with Equation (4.1), the known function g is shown to be I t . E i. The current 1(2') is the unknown function to be determined, i.e., N

l(f') = ~

(4.17)

ajFj(/?'),

j=l

and the linear operator is given by

L(l(e'))

= jw/z - ~ f t" t'I(t')G(t,t ,) de' L'

1 of o jw4we Of ~

(4.18a)

,1

[I(/?')]G(~,f d/?',

L'

where

G(f ,s =

e -jkR

is known as the free-space Green function for a radiating source in an unbounded region.


211

A frequently used modified form of Equation (4.18a) is obtained by integrating the second term by parts. We can then obtain

e" E = Jwlz ~ f e" ~' I(f')a(f,f') df'

L'

1

o f

jw4we Of

o

[l(f')] ~

(4.18b) G(f,f

,)

dr'.

L'

Then, under certain conditions, we can rewrite the preceding equation as

418c) L'

which is known as Pocklington's integral equation. If a wire terminates, the additional boundary condition I = 0 at the open ends must also be satisfied. For scattering problems which involve an incident field E i impressed on a perfectly conducting and completely specified wire configuration the term/?. E i can be easily evaluated. For radiation problems, the excitation can be specified as either discrete or distributed. For a discrete excitation a voltage V/is given over an infinitesimal gap (delta gap) as V/8(/? - fi). For several of such excitations, g = Z V i ~ ) ( ~ - ~i)" i=1

(4.19)

For distributed excitations in radiation problems, the known function g is similar to the one used for scattering, except that E i exist only over several partitions of the wire junctions. In Equation (4.17) the basis functions Fj are chosen to be linearly independent and cej are the complex coefficients to be determined. By using the same procedure leading to Equation (4.4), inner products with weighting functions W i are implemented. The resulting set of equations can be written in matrix form as

[Zij] [lj]

= [Vi],

(4.20)

where (W1,L(F1)) (W2,L(F1))

9. . 9. .

(W1,L(FN))

(4.21)

[zi~] = 9

(WN,L(F1))

~

9. .

(WN, L(FN))

212


where i, j = 1, 2, 3 . . . . . N and m

if2 O~3 j

(4.22)

"--

~N

For the scattering problem,

(W1,E i- e) (W2,E i" ~)

[~.]

(4.23)

=

(WN,E i" e) For radiating problems the typical element of [Vi] is obtained by replacing the term E i. ~ in Equation (4.23) by Equation (4.19). The desired solution for the current is obtained by [/j] = [Zij]-I[v/],

(4.24)

which allows calculation of the unknown coefficients c9 in Equation (4.17). Choosing Basis and Weighting Functions The basis functions Fj in Equation (4.17) for the current should be linearly independent, should lie within the domain of L, and should be capable of approximating the current distribution along the wires. Collectively, they should also satisfy Kirchoff's current law at a wire junction. Fj functions can be classified into two groups: entire and subsectional. Subsectional functions exist only over a small portion of a wire structure and are the ones commonly used in MOM codes. Most MOM computer codes are based on one of four commonly used sets of subsectional current basis functions: (1) pulse functions which result in a staircase approximation of wire currents; (2) triangle functions; (3) sinusoidal functions (the latter two being piecewise linear approximations of wire currents); and (4) a set of three-term (constant, sine, and cosine) basis functions which offer several analytical advantages. Pulse, triangular, and sinusoidal basis functions are de-


213

scribed in Figure 4.6 as they are distributed over several wire segments (1 through 6). Notice that if we apply Equation (4.17) to Figure 4.6 we would only have the contribution of six segments (N = 6); hence, Equation (4.16) would only have six terms with six unknown current coefficients (al-a6). The three-term basis function will not be addressed in this section, but extensive discussions of

F1

0

F2

F3

F4

2

3

4

1

F5

F6

5

6

7

Pulse Functions F1

u

F2

B

0

F3

g

1

F4

g

F5

g

2 3 4 Triangular Functions

I1F1

w

w

0

1

12F2

2

F6

g

u

5

13F3

g

w

3

4

Piecewise Sinusoidal Figure 4.6

6

Different types of basis/weighting functions used in MOM codes.

214


it can be found in reference [ 13] for the Numerical Electromagnetic Code (NEC), which is a very popular MOM code.

Pulse Functions As shown in Figure 4.6, the current is expanded in a series of pulses; each pulse is nonzero only over a single segment length of one wire. Each pulse function is characterized by a complex number representing the current amplitude over a given segment. The boundary condition I = 0 at open ends of wires is fulfilled by using half-segments to which zero current is assigned at each open end of each wire. The weighting functions comprise a set of N weighted impulse functions. Each of these is defined at the midpoint of the segment to which the corresponding expansion function is assigned. For example, if ~3 denotes the location of point 3 along the wire (and the midpoint of F3), then the weighting function W 3 is defined to be W 3 = @ ~ - f3)Af,

(4.25)

where Af is the length of the segment. The excitation matrix [V] is calculated as in Equation (4.23), with each element V1 through VN representing the complex excitation in volts that is applied to the corresponding segment length by means of either an incident field (scattering problem) or a local source (radiation problem). In the radiation problem, the term e. E i in Equation (4.23) is replaced by Vi/DAf,, where V/is the locally generated voltage applied over a small gap A/? centered at point i. In typical radiation problems, many of the elements of [Vi] will be zero. Elements of [Zij] are calculated using Equation (4.21) with the typical element Zij representing the voltage induced on the ith segment due to a unit current pulse along the jth segment. The matrix [Z/j] is known as the generalized impedance matrix. This matrix includes all self and mutual interaction terms of the wire structure. The matrix [Z/j] is of order N and is nonsingular so we can evaluate the current using Equation (4.24). For radiation problems, once the voltage and current matrices [/fl, IV/] are known it is very simple to calculate the input admittance (Yin) at the pth feed point. That is,

yip _ Ip.

(4.26)

In order to take wire losses and loading into account, it is only necessary to add a load impedance [Ze] to the generalized impedance matrix [Z/ft. The matrix [Ze] is a square N • N matrix with nonzero elements on the diagonal. Thus, if a


215

segment j is loaded with some Zej in ohms, then the jth term on the diagonal of [Ze] is Zeg. Using a totally generalized impedance matrix ZT such that [ZT] = [gij ] nt- [gf],

(4.27)

the current can be found to be [6 ] -- [ZT] -1 [Vi].

(4.28)

From the current distribution on the various wires, several quantities can be easily computed, including near fields, far fields, radiation hazards, EMI coupling, scattering, and quantities related to good design [14-16]. Electric field calculations can be made using Equation (4.15) for each wire segment. The total field is the vector sum of contributions from all segments in the wire. Pulse functions are used for point-matching techniques. The boundary condition of the tangential component of the total electric field at the surfaces of wires is applied only at discrete points along the length of the wires. The popular NEC code uses pulse functions as weighting functions. Triangular Functions When triangular functions are used, the result consists of a piecewise linear approximation of the current in the wires. Often the weighting functions used are also triangular, giving rise to the Galerkin method. The matrix elements are calculated using Equations (4.21) through (4.23). The elements of [lj] can be calculated from Equation (4.24). For radiation problems and discrete excitation, the elements of [Vi] are obtained by replacing the term E i. f in Equation (4.23) by Equation (4.19) as before. The fields are calculated using Equation (4.15) as before. Loading follows the same approach described by Equations (4.25) through (4.28). For more information concerning triangular functions, especially those used by the WIRE code [17], the reader is advised to consult references [ 18-20].

Sinusoidal Functions

The piecewise sinusoidal functions were first introduced

by Richmond [21]:

ij(e) = e

sin k(e - ~j-1) sin k(e,j - s

/?j-1 .

/

\

--.

/

\

\j

/

--\

\

\

Radiating source over ground plane to be modeled using FEM.

[ ]1[ ]

The coefficients a, b, and c are determined from Equation (4.165) as a =

1 l

xi xj

Yi yj

fIJi

1

Xm

Ym

f~m

d~j

.

(4.166)

Substituting Equation (4.166) into Equation (4.163), we obtain

[ ~e =

XmY' lxy

|(Yj--Ym) k(Xm - X)

(Ym -- Yi) (Xi - Xm)

(Yi - Yj) % -- Xi)

f~lj f~m

(4.167)

or

f ~ e - - Z cen(x,y)~ben n=i,j,m or

dPe = OZi(x,y)q~ei + cej(x,y)q~ej + O~m(X,y)q~em,

(4.168)

284


where 1

ai(x,y ) = ~

[(xjy m -- XmYj) + ( y j -- Ym)X + (X m --

xj)y]

1

cej(x,y) -- ~ - [ ( X m Yi - XiYm) -1- (Ym -- Yi) x + (Xi - Xm)Y] 1 Olm(X,Y) = ~

[(xiYj -- xjYi) + (Yi -

y j ) x -I- (Xj -- x i ) Y ] ,

(4.169a)

(4.169b)

(4.169c)

and A is the area of the element e, that is,

A

1 1 1

xi xj Xm

Yi 3) Ym

-- ( x i y j -

x j Y i ) + (XmY i -

XiYm) + ( x j y m -- XmYj)

or 1

A = ~[(xjy m - X m Y j + X m Y i -- x i Y m + x i Y j -- xjY i) ] .

(4.170)

The value of A is positive if the nodes are numbered counterclockwise (starting from any node) as shown in Figure 4.44. From Equation (4.168), the potential at any point (x,y) can be calculated, provided that the potential at the vertices is known. This is different from finite-difference analysis, where the potential is known at the grid points only. The terms aj, a i, and a m are called element shape functions, and they are linear interpolation functions. The functional corresponding to Laplace's equation (4.162) is given by

Fe - ~1 f ~lEI2ds - ~1 f elVCPe(X,y) 12 dxdy De

De

(4.171)

--2 f \Ox: + \--~y] dxdy. De

The functional is the energy per unit length associated with the element e. By doing the algebra in Equation (4.171) using Equation (4.168), we can express F e in matrix form as F e -- 2E[f~kelt I f e] [(I)e] ,

(4.172)

4.5. The Finite-Element Method in Computational Electromagnetics

285

where the superscript denotes the transpose of the matrix

=

[

~ei] eJ/ (~emJ

and the matrix C e is given by

Cii Cji Cmi

C

Cij Cjj Cmj

Cim ] Cjm . Cram

The matrix Ce is usually called the element coefficient matrix. The matrix elements of the coefficient matrix may be regarded as the coupling between nodes i, j, and m. The values of such elements are

Cim = -~A[(Yj- Y m ) ( Y i -

yj) + (X m -- Xj)(Xj -- Xi) ]

(4.173a)

Cj m

Yj) + ( X i -

Xm)(Xj -- Xi)]

(4.173b)

xj) 2]

(4.173c)

Xm)2]

(4.173d)

xi)2].

(4.173e)

1 = -~[(Ym -- Y i ) ( Y i -

Cii = ~A[(yj -- ym) 2 -]- (x m --

1

Cij - -~[(Ym -- Yi) 2 + (Xi -

1

Cm m = _4__~[(yi _ yj)2 + (xj -

Also, Cji = Cij; Cmi = Cim; Cmj = Cjm. Laplace's equation is satisfied when the total energy in the solution region is minimum. Thus, we require that the partial derivatives of F~ with respect to each nodal value of the potential be zero, that is, =

OFf

=

=

o.

286


It can be shown using Equations (4.172) and (4.173a-e) that

OFe_o= O~)i

e

~

{[(yj -- ym) 2 + (Xj -- Xm) 2] (~i -- [(Yi - Ym)(Yj -- Ym)

-I- (X i -- Xm)(Xj -- Xm)]~ j -- [(Yi - Yj)(Ym - Yj) + (Xi - Xj)(Xm -- Xj)]q~m} (4.174) and the same procedure can be used to find OFe/O4) m. If the equations for the three derivatives are assembled in matrix form, the total system of linear equations minimizing the functional F e can be expressed as

[~liii 4e, Oji Omi

~llij ~jj Omj

OmmjOiml[q~ei] ~jml~eJl-'-O, ~emJ

(4.175)

where ~9ii = A [ ( y j - ym) 2 nt- (xj - Xm) 2] J/ij = A [ ( y i - Ym)(Yj - Ym) + (Xi - Xm)(Xj -- Xm)]

Oim = A [ ( y i - Yj)(Ym - Yi) + (xi - xj)(Xm - xj)] and any other combination can be obtained by permuting i, j, and k. The final system obtained can be written as [0] [4~e] = [bl,

(4.176)

where [b] is the result of replacing the known node potentials with their Dirichlet values. Equation (4.176) can now be solved for rkei, q~ej, and Ckem, and then Equations (4.168), (4.169), and (4.170) can be used to obtain the solution. Sometimes we are interested in modeling radiation phenomena and provide field levels at any position. We can use the finite-element method to emulate the radiation in a homogeneous domain. Figure 4.45 depicts a sketch of a radiating source over a perfectly conducting ground plane. The modeling space in Figure 4.45, limited by an absorbing boundary surface S a and the surface of interest S, is discretized with triangular finite elements. The equation modeling electromagnetic propagation in the homogeneous domain DH is the Helmholtz wave equation V2(I ) nt- k2(I) -- g,

(4.177)

where q~ is the field quantity (E or H). For waveguide problems, $ = H z for TE mode or E z for TM mode. The term g is the source function, and k = w(/xe)1/2 is the wave number of the medium. Notice that for k = g = 0, Laplace's equation


287

is obtained. For k = 0, Poisson's equation is obtained. For g = 0, the homogeneous, scalar Helmholtz equation is obtained. We know that an operator equation of the form LcI) = g

(4.178)

can be solved by extremizing the functional F h (h for Helmholtz): (4.179a)

Fh(CP) = (L, c P ) - 2((I),g).

Hence, the solution of Equation (4.177) is equivalent to satisfying the boundary conditions and minimizing the functional Fh (~) = 1

f [IV~I2 -

2dPg]ds.

k2(i)2 +

(4.179b)

S

We can express the potential (Peh and source geh in terms of shape functions an over a triangular element e:

dPeh(X'Y) = Z %(x'y)q~n n=i,j,m

geh (x, y)

(4.180a)

= ~ Ce,(x,y)gen,

(4.180b)

n = i,j,m where ~eh and geh stand for the potentials to be used for solving the Helmholtz equation. The terms ~bo, and gen are, respectively, the values of 9 and g at nodal points (i, j, or k) of element e. Substituting Equation (4.180) into Equation (4.179b), we have

Fh (dPe)= ~_[dPe]t[Ce] [Cite] -

k2 -~- [dPe]t[Te] [Cite] +

[d~e]t[Te] [Ge],

(4.181)

where [q~e] =

[C e] =

[ q~ei

q~ej

~em]t; [Ge] = [gei

ICiiCijCiml Cji Cjj Cjm Cmi

Cmj

[A/12 ; [T~] =

[_A/6

gej gem] t

fori, j, m4=](4.182) for i = j = m

Cmm

The matrix elements of [C e] are given by Equation (4.173). Minimizing the functional Fh(Fe) means taking all the partial derivatives of Fh(ePe) with respect to ~bi, ~bj, 4)m and setting them equal to zero in order to solve for the three

288


potentials ~ei, ej, em" Equation (4.181), derived from a single element, can be applied for all N triangular elements in the solution region. Thus, N

F(O) = ~., Fh(Oe).

(4.183)

e----1

4.5.2

THREE-DIMENSIONAL

FINITE-ELEMENT

METHODS

The solution of finite-element analysis of Helmholtz's equations in three dimensions can be accomplished using tetrahedral elements of the form shown in Figure 4.46. Assuming a four-node tetrahedral element, the function (I) e is represented within the element by (4.184)

dPe = a-k- bx-k- cy + d z.

The same applies to the function g. Since Equation (4.184) must be satisfied at the four nodes of the tetrahedral elements, ~ e -" a + bx,, + cy,, + dz,,,

4

3 Four-Node Tetrahedron Figure 4.46 Four-nodetetrahedron for 3D FEM.

(4.185)


289

where n = i,j, m,k. We have four simultaneous equations from which the coefficients a, b, c, and d can be determined. The determinant of the system of equations is given by

A

___

1 1

Xi

Yi

xj

3)

zj

1

Xm

Ym

Zm

1

x~

y~,

zk

Zi

= 6V,

(4.186)

where V is the volume of the tetrahedron. By finding a, b, c, and d, we can write an equation of the same form as Equation (4.180) in three dimensions q~(x,y,z) =

~

cen (x,y,z) q~e,,,

(4.187)

n=i,k,j,m

where

1

a/= g-~

~=~

1

1 1

x xj

y yj

z zj

1 1

Xm

Ym

Zm

x~

y~

zl,

1

Xi

Yi

Zi

1

x

y

z

1

Xm

Ym

Zm

1

x~

y~

z~

X i Yi 1xjyjzj

Zi

1 1

z zk

1 1

1

x x~

y y~

1

Xi

Yi

Zi

1

xj

yj

zj

1

Xm

Ym

Zm

1

x

y

z

(4.188a)

(4.188b)

(4.188c)

(4.188d)

We can now express Equation (4.187) in the form f~Je = Ogi ( x , Y , Z ) ~ e i "-1- Olj ( x , y ~ Z ) ~ e j + a m (x,y~z)~)em + Olk ( x , y ~ Z ) ~ e k .

(4.189)

290


A similar equation exists for

ge:

ge (x,y~z) -- Odi (x,y~Z)gen + Odj (x,y~Z)gen Jr- O[m (x,y~Z)gen + Odk (x,y~Z)gen.

(4.190) By inserting Equations (4.189) and (4.190) into Equation (4.179b), we obtain an equation for of the same form as Equation (4.181), except that all the matrices are augmented by one column (the k column in matrices ~e and Ge) and by one column and one row (the k column and row in matrix Minimizing the functional Fh(~e) means taking all the partial derivatives of with respect to ~bi, ~bj, ~bm, and ~bk and setting them equal to zero in order to solve for the four potentials ~ei, ej, em, ek" Using Equation (4.183), we can solve F(~) for all N tetrahedral elements involved in the solution region. The finite elements discussed thus far have been linear in nature. This means that the shape functions used (e.g., Equations (4.163) and (4.164)) are of order 1. A higher-order function is one in which the shape function or interpolation polynomial is of order 2 or more. The accuracy of a finite-element solution can be improved by using a finer lattice or higher-order elements. In general, fewer higher-order functions are needed to achieve the same degree of accuracy when compared to first-order elements. The higher-order elements are useful when it is expected that the total field variable will change rapidly. To learn more about the use of secondorder and higher-order elements in finite-element methods, especially as they apply to three-dimensional problems, the reader should refer to [76]. Another technique used in three-dimensional finite-element methods is that developed by MacNeal [77] using a time-integrated electric scalar potential. This technique is the one used in a popular code known as MSC/EMAS. It can be shown that electrical and magnetic energy variation can be expressed as variations (represented here as D) in terms of A (the magnetic field vector potential) and Y (the time integral of the electric scalar potential f). This variation can be expressed as

Fh(dPe)

Ce). Fh(Cbe)

et al.

AF=fd~'fdt((A(VO)+AO--A)'e( ) O v~176 t ~A v

- (A(V0) + AA)

to

9o- V

0 +~A

(

-A(V•215

0

(4.191)

9 V . A ) - A ~ 0(P) + AA. (J)

(0)

9 j

) + ds s dt(AA-(H • fi) - A0fi S

- fj d s A O ( f i - D ) S

to

to

4.6. The Transmission-Line Method in Computational Electromagnetics

291

The first volume term in this expression is due to stored electric energy in materials of permittivity e, the second volume integral is due to power loss in materials of conductivity tr, and the third volume integral is due to stored magnetic energy in material of reluctivity v = 1//z. The fourth term guarantees uniqueness in the solution by penalizing the square of the divergence of A with the factor a times reluctivity. The fifth and sixth terms represent charge density (p) excitation on ~ and current density (J) excitation on A. The final three surface integrals allow energy of H, J, or D fields to be input through the boundary of the finiteelement model. Setting Equation (4.191) to zero yields the matrix equation [M][/;/] + [B][/~] + [K][u] = [J]

(4.192)

and the electrostatic initial condition [M][ti] = [Qi]

(4.193)

where [u] is a column vector which contains the unknown magnetic vector potential and time-integrated electric scalar potential of all the nodes. From a knowledge of A and 9 t (i.e., the solution to Equation (4.192)), we can obtain the electric and magnetic fields and other parameters related to such fields: [u] = [Ax Ay a z ~]x.

(4.194)

The matrix [J] contains current excitations, which may be static, time-dependent, or frequency-dependent. The excitation vector [Qi] corresponds to the initial charge distribution. The matrices [M], [B], and [K] are proportional to permittivity, conductivity, and reluctivity, respectively. In the frequency domain, Equation (4.192) becomes {--O) 2 [m] +

4.6

jw[B] + [K]}[u] = [J].

(4.195)

The Transmission-Line Method in Computational Electromagnetics

Circuits are mathematical abstractions of physically real fields. The representation of fields using circuit elements is feasible when A > > ~, where ~ is the dimensions of the circuit involved. The transmission-line method (TLM) is a numerical technique for solving electromagnetic field problems using equivalent circuits. TLM is based on the correlation between Maxwell equation and the equations corresponding to voltages and currents on a mesh of continuous two-wire transmission lines. When compared to the lumped network model, the transmission-

292


line method is more general and provides better accuracy at high frequencies where the transmission and reflection properties of geometrical discontinuities cannot be regarded as lumped [78]. The material discussed in this section is based on the work in this field by P. B. Johns [79], S. Akhtarzad [80,81 ], Wolfgang J. R. Hoefer [83], and P. B. Johns [84]. Other references are cited as we proceed. The TLM is a discretization technique. However, it differs from FDTD and finite-element methods in that it is a physical discretization, whereas FDTD and finite-element methods are mathematical discretization approaches. In TLM, the discretization of a field involves the replacement of a continuous system by a network of lumped elements. The TLM involves dividing the solution region into a rectangular mesh of transmission lines. Junctions are formed where the two lines cross, forming impedance discontinuities. The TLM involves two basic steps: (1) replacing the electromagnetic problem by an equivalent network representation, hence establishing an equivalency between field elements and network quantities; and (2) solving the equivalent network by interactive methods. In order to show how Maxwell equations may be represented by the transmission-line equations, the differential length of a lossless transmission line between two nodes of the mesh is represented by lumped inductors and capacitors as shown in Figure 4.47 for two-dimensional wave propagation problems. At the node locations, pairs of transmission lines form impedance discontinuities. The

ix(x + A~ 12)

A e/2

Iz(z- A e 12)

Iz(Z + A ~/2) v

Ae/2

A~/2

~

- -

2AZC

Ix(X- A ~/2)

i A~/2

Figure 4.47 Network representation of a 2D TLM shunt node.

9"- I


293

complete transmission-line matrix is made up of large numbers of transmissionline building blocks. It is assumed that internodal distance is Af. Consider Figure 4.47 and apply Kirchoff's current law at node O to obtain Ix(x-

Af/2) - / ~ ( x + All2) + I z ( z -

At/2) - Iz(z + At/2) = 2cAt O.,.v,, 3t

(4.196)

Dividing Equation (4.196) by Af and taking the limit Af---)0, we obtain

Ol~

Ol~

Oz

Ox

-

OVy

2c

at

.

(4.197)

If we now apply Kirchoff's voltage law around the loop in the x - y plane, we obtain Vv(x-

-

All2) - L gk---= O l x ( X - All2) _ L A__=gOlx(x + All2) 2 at 2 at - Vv(x + A t / 2 ) = O.

(4.198)

By dividing Equation (4.198) by Af and taking the limit A/?---~0, we obtain 0Vy Ox

= - L LO_,.

(4.199)

at

Doing the same for the y - z plane, we have 0 Vy Oz

= - L L&~,.

(4.200)

at

Equations (4.197), (4.199), and (4.200) can be combined to give the wave equation 02 Vy -f 02 Vv OX 2

__

O2gy

2LC ~

OZ 2

(4.201)

Ot 2 "

Equation (4.201) is analogous to the Helmholtz wave equation in two-dimensional space. This can be seen by considering Maxwell equations OH V x E = -/x~ Ot

0E

V x H = ~.

at

(4.202a)

(4.202b)

294


By expressing Equations (4.202) in rectangular coordinates and considering the TE mode with respect to the z-axis, we obtain OHx Oz

OHz OEy - e Ox Ot

OEy _

onz

-/.t~

Ox

Ot

OEy OHx = #~. Oz Ot

(4.203a)

(4.203b)

(4.203c)

Equation (4.203) can be combined to give the wave equation OZEY t OZEY _ fl,~3 02Ey . OX2 OZ2 at 2

(4.204)

By comparing Equations (4.199) through (4.201) with Equations (4.203) and (4.204), we get the following equivalences between the parameters:

I4~ -

-Iz

Hz=-I~

(4.205)

t.t~ L e = 2C.

The manner in which a wave propagates in a TLM mesh for a two-dimensional problem is dictated by the transcendental equation

sin ( ;

sin

(4.206)

where Af is the size of the mesh cell, A is the wavelength of the frequency of interest, and r is the ratio of the velocity Vn of the waves on the network to the free space wave velocity c, that is, r-

Vn_

c

w _ 2r

/~nC

(4.207)

aBn'

where fin is the imaginary part of the propagation constant in the network. If we select different values of A~/A, the frequency values of Vn/c (or r) can be obtained numerically by using Equation (4.206). From Equation (4.206) it can be deduced that TLM can only represent Maxwell equations over the range of frequencies from zero to their first network cutoff frequency, occurring at toAr = ~/2 or


0.7

295

B

Normalized Propagation Velocity 0.6 (Vn/c)

0.5

0.05

0.1

0.15

0.2

0.25

Normalized Frequency (A I/X ) Figure 4.48

As

Dispersion of the velocity of the waves in a 2D TLM network.

1

= ~. Over this range, the velocity of the waves behaves according to the

characteristics given by Figure 4.48 [83].

4.6.1

T H E S C A T T E R I N G P R O C E S S FOR 2D P R O B L E M S

If V ki n and V ~:n are the voltage impulses incident upon and reflected from terminal n of a node at time t = kAY~c, we can derive the relationship between these two quantities. Consider the case of four pulses being incident on four branches of a node. If, at time t = kAs voltage impulses Vilk, Vi2k, V~k, and V~,~ are incident on lines 1 through 4, respectively, at any junction node as shown in Figure 4.49, the combined voltages reflected along lines 1 through 4 at time t = (k + 1)As are given by V1] r

I;i] V~

-1

:2

k+l

1

1

1

Vi i

'1

1 1

,1

1

1

- 1, 1

V~ " V~4 k

--1

(4.208)

296


JL JO~L'

JL

~F

(b) First Iteration

(a) Excitation

-a~ow

-.~r

(c) Second Iteration

Figure 4.49 Scattering in a 2D TLM network excited by a pulse.

Furthermore, an impulse emerging from a node at position (x,y) in the mesh (i.e., a reflected pulse) automatically becomes an incident impulse at the neighboring node; hence,

v~k+ l~ (z,x + A~) = vr3~+ ~ (z,x) V i2(k+l) (Z Jr" A~, x ) - -

V r4(k+ 1) (Z,X) V~(k+ l) (Z,X -- m~,) -" Vrl(k+ l) (Z,X)

V 4(k+ i 1) (z -

(4.209)

A~, x) -- V r2(k+ 1) (Z,X)

The application of Equations (4.208) and (4.209) allows us to calculate the magnitudes, position, and directions of all impulses at time (k + 1)Af/c for each node in the network, provided that their corresponding values at time kAr are known. The impulse response can be found by initially fixing the magnitude, position, and direction of travel of impulse voltages at time t = 0 and then calculating the state of the network at successive times.

297


~

X

,Z"

/

J

/

/

Y

Figure 4.50

Transmission line matrix with boundaries.

Figure 4.49 shows the propagation of pulses in which the first two interactions following an initial excitation are shown for a two-dimensional TLM. The scattering process is the basis algorithm of the TLM [79].

4.6.2

BOUNDARY CONDITIONS FOR 2D PROBLEMS

To ensure synchronism, boundaries are usually placed halfway between two nodes. This can be obtained by making the mesh size A~e an integer fraction of the structure's dimensions. Any resistive load at boundary (see Figure 4.50) may be simulated by introducing a reflection coefficient F,

vi4(k+ 1) (Xl,Yl)

-" gr2k (Xl + 1,y) =

F[V~4k (xl, Yl)],

(4.210)

where F = (R s - 1)/(Rs + 1) and R~ is the surface resistance of the boundary normalized by the line characteristic impedance. For a perfect conductor R s = 0; F = - 1 , representing a short circuit; and v i4(k+ 1~ (xl, Yl) = V4k r (Xl, Yl)"

4.6.3

(4.211)

CALCULATION OF FIELDS

For the TE mode represented by Equations (4.203) and (4.204), we can calculate the terms Ey, H x, and H z. From Equation (4.205), Ey at any point can be calculated

298


from the node voltage at the point. H z at any point can be calculated from the net current entering the node in the x direction. H x at any point can be calculated from the net current in the negative z direction. For any point (x 1, yl) on the grid of Figure 4.50, we have for each kth transient time Eyk (Xl , Yl)

=

1

~

[V~k (Xl , Yl)

+

Vi2k (Xl, Yl) + V3k i (Xl, Yl) q- V4k i (Xl, Yl)]

- Hxk (Xl, Yl) = V~k (Xl, el) -- V~k (x~, Yl) = Vi3k (Xl' Yl) -- V ilk (X,1 Yl)

(4.212)

Hzk (Xl ' Yl)

A series of discrete delta functions of magnitude Ev, Hx, and H z corresponding to time intervals of Af~/c are obtained by the interactions of Equations (4.208) and (4.209). Any point in the mesh can serve as an output or observation point. Equation (4.212) provides output-impulse functions for the point representing the response of the system to an impulse excitation. If we want to calculate the frequency response due to a sinusoidal excitation, all we need to do is to take the Fourier transform of the time-domain impulse response. Because the impulse response is a series of delta functions, the Fourier transform becomes a summation. The real and imaginary parts are given by [83] (for Ey(x l, Yl) in this case) as

Re[Ey(zXe/a)] = ~

Eyk(x~, Yl)COS

k--1 N

Im[E~(Af/a)] = ~ "

(4.213)

2~'kAf

A

Eyk(Xl, yl)sin

k= 1

(27rkAf) A

(4.214) "

The same expressions can be written for calculating H~, H:. Ev(As ) is the frequency response, Ey(Xl, Yl) is the value of the impulse response at time t = kAs and N is the total number of intervals for which the calculation is made. 4.6.4

T L M FOR I N H O M O G E N E O U S M E D I A

In order to account for an inhomogeneous medium (i.e., e is not constant), there is a need to add more capacitance at nodes in order to represent an increase in permittivity [82]. This is accomplished by introducing an additional line as shown in Figure 4.51a. The line is of length Af/2 and open-circuited at the end and has a variable characteristic admittance Y' relative to the unity characteristic admittance assumed for the main transmission line. At low frequencies, the effect of this additional line is to add to each node a lumped shunt capacitance CY' A/?/2, where C is the shunt capacitance per unit length of the main lines that


13

299

13

2

,-on

2

O4

L,C

L,C

CY'

I,, '~

CY'

Q CG'

1

1

(a)

(b)

Figure 4.51 A two-dimensional node: (a) node with permittivity stub, (b) permittivity and loss stub.

have unity characteristic admittance. At each node the total shunt capacitance becomes C ' = 2CAt -~ C ' 2Y A f ' - 2 C A t ( 1

+-~)

(4.215)

For a lossy medium, we also add a power-absorbing single resistor, and this is implemented by a matched line of characteristic admittance G' normalized to the characteristic impedance of the main lines as illustrated in Figure 4.5 lb. The equivalent network now becomes that of Figure 4.52. Applying Kirchoff's current law to node O in the x-z plane and taking the limits as Af--->0, we get

Oz

Ox

ZoAf + 2C 1 +

~'Ot

(4.216)

Expanding Maxwell equations, V x E= V•

OH -/.z,~ at

(4.217a)

0E

Ot

(4.217b)

300


Ix(X + A e/2)

iz~- a e/2) Ix(x ,~ -

~i ~ ~ / , ~ V ( z G O / Zo

c'l

/2) i

+At/2) 2A ZC

'

I

i~ z Figure 4.52

Two-dimensional shunt node for inhomogeneous lossy media.

for O/Oy = 0, we obtain

OHx + OHz OZ

OEy

Ox = o'Ey + 808

,

(4.218)

which is the TEmo modes with components H z, Hx, and Ey When we compare Equations (4.216) and (4.218), the equivalence between TLM and Maxwell equations can be expressed as

ey-Vy 14~ -

-lz

I4z =- I~ 80 = 2C 4+y' 8F

---

o" =

G

(4.219)

or

(y' = 4(8 r - 1))

or

(G ' =

!

ZoAe

o'AfZ o)

where Z o = (L/C) 1/2. The losses in the network can be varied by changing the value of G'.

4.6. The Transmission-Line Method in Computational Electromagnetics 4.6.4.1

301

The Scattering Process for 2D Problems

If Vnk(Z,X) is the unit impulse voltage reflected from the node at (z, x) into the nth coordinate direction (n = 1, 2, 3 . . . . . 5) at the time kAf/c, then at node (z, x),

V~(z,x)]

I

V2(z,x)l ~(z,x)/= v4(z,x) I

v~(z,~)J,,+

2 1 -f

1 1

1 1

1 1

1 1

Y' Y'

1 1

1 1

1 1

1 1

Y' Y'

1

1

1

1

Y'

V3(z,x -- A ~ ) - i V 4 ( z - A~,x) -[I]

Vl(z, A e + x )

,

(4.220)

V2(Z qt_ A~, x)

Vs(z,x+Af)

k

where [/] is a unit matrix and Y = 4 + Y' + G'. The coordinate directions 1, 2, 3, and 4 correspond to - x , - z , +x, and +z, respectively, and 5 refers to the permittivity line. Notice that the voltage V6 (see Figure 4.51 b) which is scattered into the loss line is dropped across G' and not returned to the matrix. If y = ce + jfl is the propagation constant of the medium and Yn = an + Jfln is the network propagation constant, it can be shown that

Yn =

2(1 + -~--) y

(for low frequencies)

(4.221)

and the network velocity Vn of waves on the matrix is obtained from 2 V 2 __ n

4.6.4.2

c

(4.222)

Boundary Conditions for 2D Problems

In order to account for a lossy boundary we define the reflection coefficients [80] as F=

Zs - Z~

z~+Zo'

(4.223)

where Z 0 = (/x0/8o) 1/2 and Z S is the surface impedance of the lossy boundary given by

Zs =

~r

IX/~-' (1 + j),

(4.224)

w h e r e / x and o-are the permeability and conductivity of the boundary. As can be seen, F is a complex quantity; hence, the impulse functions are altered at the

302


conducting boundary during reflection, which cannot be accounted for in the TLM [80]. To get around this difficulty, it is assumed that the imaginary part of F is negligible and Z s < < Zo to give. /

F ~ - - 1 + _/2e-~ x/

.

(4.225)

o-

Notice that/-" is slightly less than - 1 . 4.6.5

THREE-DIMENSIONAL TLM PROBLEMS

In order to represent three-dimensional problems, TLM uses a hybrid mesh consisting of three shunt and three series nodes to describe the six field components. Shunt nodes were described previously for two-dimensional problems. The voltages at the three shunt nodes represent the three components of the electric field (E). The currents of the series nodes represent the three components of the magnetic field (H). In the x - z plane, the voltage-current equations for the shunt node are

aL

aI~_ 2caVy

Oz

Ox

Ot

(4.226a)

OVy _ Ox

- L &~f

(4.226b)

OVy=

L.OI~

(4.226c)

Ox

Oz

Ot

and for the series node in the x - z plane, the equations are OVx Oz

O V z _ 2LOly Ox at

air = _cOVz Ox

(4.227)

Ox

Oly = _cOVx Oz

Ot

The equivalent Maxwell equations for O/Oy = 0 give

aH~

aHz

aEy

Oz

Ox

Ot

aEy _ Ox

/.t

aH~ Ot

a E y = /~

0z

Ot

(4.228a)

(4.228b)

(4.228c)


303

and

oE~

OEz

Oz

Ox OHy Ox

oI-Iy

= /x

=

-e

=

-e

OHy Oz

(4.228d)

Ot OE~ Ot

(4.228e)

OEz Ot

.

(4.228f)

Similar equations for nodes in the x - y and y - z planes will yield voltage-current equations and the analogous Maxwell equations. Figure 4.53 shows a threedimensional node representing a cubical volume of space Af/2 so that similar nodes are spaced A/? from each other. If the voltage between lines represent the E field and the current in the line represents the H field, we can then write the following Maxwell equations:

OH~

aHz

Oz

Ox

Onz

Ony _

=

-

Oy

Oz

e

e

aH~ ~

(4.229a)

Ot

OE~

(4.229b)

Ot

Hx

E

Ex

Ez

Figure 4.53 A general three-dimensional node.

~

X "9 z

304


oily Ox

oH~ Oy

OEz

OEy

Oy

Oz

OEy

OEx -

Ox

aEx Oz

=

Oy

aEz Ox

e

-~

oEy

(4.229c)

at

OHx

(4.229d)

Ot

Onz

-/z ~ Ot -~

(4.229e)

Oily.

(4.2290

Ot

A series connected node which is lossless is shown in Figure 4.54. The network representation is shown in Figure 4.55. The input impedance of the short-circuited line of Figure 4.55 is given by

93

tan

II

3q

Z i = jZ 0

(4.230)

~- jwLZ o

Y

y

AI/2 A W

w

2 A W

w

Figure 4.54

Lossless series node with permeability stub.

Z


Vz+At dVz/dz

v

I ~/2

~

T cA~/2

305

LAe/2

I,x~-

,,

cA~/~

l

I A ~ / 2 ( 1 7-o)

~/2 I

Vy+AI dVy/dz

z v

y

Figure 4.55 Network representation of series node.

This represents an impedance with inductance

L' = L~-f Zo .

(4.231)

The total inductance on the side in which the short-circuited line is inserted is given by L - ~ ( 1 + Zo).

(4.232)

Applying Kirchhoff's voltage law around the series node of Figure 4.55 and dividing by Af, we obtain

Oy

Oz

--~

(4.233)

for the node oriented in the y-z plane. For the x-y plane orientation, we have

OVy Ox

( z0~

OV~ _ 2L 1 + Oy 4 ] Ot '

(4.234)

306


and for the x - z plane orientation,

( ZoOy

OVx Oz

O V z _ 2L 1 + Ox 4 / Ot"

(4.235)

By comparing Equation (4.235) with Maxwell equations, we obtain

~-Vx Ez-Vz

(4.236)

/z=2L _ (4 + Zo) /Zr= 4

A voltage impulse incident on a series node is scattered in a fashion dictated by Vl(Z,X)q

I

-1

r

V2(z, x) V3(z,x)

=

2

V4(z,x )

Vs(z,x) ~+

1 1 -1 1 -1

-1

-z0

1

-1

-1 -1 1

1

V3(z , X -

-1 1 1

-1

1 1 + [/] -1

Zo Z o - Z o - z 0

A~)

i

V4(z - Ar x) VI(Z , A~ -~- x)

,

V2(z + Af, x)

Vs(z, x + Af) (4.237)

where Z = 4 + Z 0 and [/] is the unit matrix. The velocity characteristic for the three-dimensional case in Equation (4.237) is the same as for the shunt node. In the upper half of the node in Figure 4.53 there is a shunt node in the x - z plane (representing Equation (4.229a)) connected to a series node in the y - z plane (representing Equation (4.229d)) and a series node in the x - y plane (representing Equation (4.229e)). In the lower half of the node, a series node in the x - z plane (representing (4.229f)) is connected to a shunt node in the y - z plane (representing (4.229b)) and a shunt node in the x - y plane (representing Equation (4.229c)). A three-dimensional TLM mesh is obtained by stacking similar nodes in the x, y, and z directions. It can be shown that for a general node the following equivalences apply [80]: E x = common voltage at shunt node E x Ey = common voltage at shunt node Ey E z = common voltage at shunt node E z Hx = common current at series node H x Hy = common current at series node Hy H z = common current at series node H z

e o = C (capacitance per unit length of line) 8r =

2(1 + Y'/4)

4.7. ComputationalMethods at Work: Getting Numbers from Your Models

307

#0 = L (inductance per unit length of line) /z r = 2(1 + Zo/4) o-= G'/(A~(L/C)),

where Y', Z 0, and G' have been previously defined. By interconnecting many of these three-dimensional nodes, we obtain a TLM mesh representing an inhomogeneous medium. The TLM for three-dimensional problems consists of applying Equation (4.237) to obtain an impulse response. Any field component can be excited by specifying initial impulses at the appropriate nodes. The wave characteristics (propagation constant, wave velocity) of the threedimensional mesh are similar to those of the two-dimensional mesh.

4.6.5.1

Boundary Conditions

The tangential components of E must vanish in the plane of an electric wall, whereas the tangential components of H must be zero in the plane of a magnetic wall. Boundary conditions are simulated by short-circuiting shunt nodes or opencircuiting series nodes (magnetic wall). The continuity of the tangential components of E and H fields across a dielectric/dielectric boundary is automatically satisfied in the TLM mesh. Finally, wall losses are included by introducing imperfect reflections coefficients as in Equation (4.223).

4.7

C o m p u t a t i o n a l M e t h o d s at Work: G e t t i n g N u m b e r s f r o m Your M o d e l s

We conclude this chapter with some worked examples of the use of computational electromagnetics in the analysis of certain types of EMC problems. Five examples are studied. The first three examples use the method of moments and the fourth uses the FDTD method. The fifth example is an overview of several techniques being applied to a single problem. The material presented is of a tutorial and practical nature. It is intended to provide some insight into how to use computational electromagnetics to solve simple EMC problems. 4.7.1

M E T H O D OF M O M E N T S USING T H I N - W I R E M O D E L I N G

Because of its widespread use in the analysis of EMI problems, a more detailed study of the method of moments is addressed for the case of modeling structures using thin wires. Thin-wire modeling is useful in EMC because it blends easily the modeling of cables, wires, microstrips (e.g., in PCB), and antennas, all of which often serve as major sources of EMI problems in many types of electronic equipment.

308


It is possible to rewrite Equation (4.18b) in a more compact form E ie = 47Tjwe •

1_, L

Oe2

+ kZG(e,#, ') l ( e ' ) d r ' .

(4.238)

where k 2 = wz/ze. In this equation I(~') is the current distribution on the perfectly conducting structure. This induced current distribution will result from either of two sources: a voltage source, if the metallic structure behaves as a radiator (antenna-type problem), or a field source, if the metallic structure behaves as a scatterer (radar cross-section type of problem). Consider the simple case of a radiating wire as shown in Figure 4.56. This model could represent a radiating I/O cable from a computing device, whose common-mode current is the major contributor to radiated emissions. The radiating structure is divided into four segments. The excitation source creates a current distribution in the wire structure, represented in this case by three sinusoids as shown in the figure. The complex coefficients I 1, 12, and 13 of the current expression I(/?') must satisfy the following conditions: f l = I(e0) , h h 12 = I(eo) + ~ = I(eo) - ~ = 13. The current distribution I(~') can now be represented as

,o)

,

Ii(~' ) = I1 i2(t )

' =

sin k d

i2 sin k(h - ( t ' - ~o)) sin k d '

12

+ / 2 sin k(f' - fo) sin k d '

fo < f ' -< ~ + fo

h -+ 2

~o < ~ " - > 1) is the predominant field of interest. For the case of kR > > 1, the dominant term in Equation (5.35) is the first one within the parentheses. For the far-field approximation, Equation (5.35) becomes H r = H4,=

ER =

k2beI~ 4R

H~ = -

Eo=O

sin 0

(5.38)

keb2Ioe-J kR

E4' = 77

5.8

4R

sin 0.

The Square Loop Antenna

Square loop (or polygonal) antennas are typical in pagers, as shown in Figure 5.7.

368

5. Antennas for Wireless Personal Communications

1st Downconverter L~~176 AntennaI

'

Filter

~7

1

1

!

LNA

_t_ r--] osc

FSK Mod. ASIC

I I Filter

J

I Filter ..... "i

I

,

I LNA

',

I I

I

2nd Downconverter

J

Figure 5.7 Small loop antenna as part of a pager device.

Pagers can operate at UHF or VHF frequencies. The 930-MHz pager is most typical in the United States, but 150 MHz and 450 MHz can also be used. Receivers for the UHF frequency band are commonly implemented with a doubleconversion superheterodyne design. Signals from the receiving antenna are boosted through a low-noise amplifier and then filtered to remove unwanted harmonics generated by the nonlinear behavior of the low-noise amplifier. The filtered signal is then translated to the pager's first intermediate frequency (IF) using a frequency downconverter. The first IF is translated to the lower frequency, a second IF, via a second-stage frequency downconverter or discrete mixer/oscillator combination prior to signal processing. The double-downconverter version provides good image rejection between the RF port and the local oscillator and IF ports. The square loop is the simplest loop configuration after the circular loop. The far-field pattern of the small square loop can be obtained by assuming that each of its sides is a small linear dipole of constant current I o and length L as shown in Figure 5.8. The worst-case field is generally given by

E4, = r/

47rR

sin #

sin

.

(5.39)

5.9. Microstrip Antennas

Z

/

/

/ r3

/

/

369

/

/

/

/ r2 /

/

/ /

Io /

/

/

rl

Y

10 X Figure 5.8

A square loop antenna.

For the case of L < < M50, the preceding equation reduces to (kL) 2 I 0 e - J ~R

E,r = r/

4~R

sin 0.

(5.40)

In these equations we have made the approximation that in the far field, the length L is the largest length of the square loop even if each of the four sides is of different length.

5.9

Microstrip Antennas

Microstrip antennas have become fashionable in some wireless communications systems, such as in the use of arrays with parabolic reflectors or even in the use of a patch antenna in the back of a cellular phone, as shown in Figure 5.9. There are several reasons why microstrip antennas are so popular: 1. Easily conformable to nonplanar surfaces 2. Low-profile antennas

370


Microstrip Patch Antenna

Figure 5.9

Cellular phone with a patch antenna.

3. Inexpensive to manufacture using printed circuit board techniques 4. Flexible so as to produce a wide variety of patterns with different polarizations 5. Mechanically robust. A typical patch antenna is shown in Figure 5.10. Most often, microstrip antennas are made by etching the patch from a printed circuit board with conductor on both sides. The top metallic flat region, which is called the patch antenna, sits on a dielectric substrate. A feed system supplies the RF power, and a ground plane is at the bottom of the patch antenna, sustaining the substrate. Typical sizes of a microstrip patch range from M2 to M3, and the dielectric thickness for such antennas is usually in the range of 0.003A to 0.05A. The relative constant/3 r is in the 2.5 to 3.2 range. The main disadvantage of the microstrip antennas lies in their quality factor Q. Microstrip antennas have high Q (Q > 100 is common), which means that they have small bandwidths. The bandwidths can be increased by increasing the thickness of the dielectric, but as this is done, surface waves (instead of transverse waves) use more and more of the delivered power, which could be considered as a power loss. Furthermore, as the size of the microstrip increases, it can allow resonant frequencies of two or more resonant modes to exist, leading to instabilities. When a current is injected into a microstrip antenna, a charge distribution becomes present at the microstrip surface and ground plane. For thin microstrips, most of the current resides at the bottom of the microstrip and on the top surface


371

Patch Antenna

Substrate

Feed

Ground Plane

Figure 5.10 A typical circular microstrip antenna.

of the ground plane. Therefore, the component of the magnetic field which is tangential to the patch edge is small. The input impedance of the microstrip antenna has both reactive and resistive components. Its resistive components account for the power radiated by the antennas. The presence of complex poles means that the imaginary parts of these poles account for the power loss by radiation and by dielectric and conduction losses. The real part and antenna poles are dependent on the shapes of their modal distributions. If the dielectric within the cavity has a dielectric loss tangent given by 8~, then at a frequency f near a resonance it has a quality factor of

1 O-- ~

1 WRe 2Wlm

(5.41)

where WRe and Wim are the real and imaginary part of the poles. This means that to properly choose the dielectric loss tangent 8~, we must use the reciprocal of the antenna quality factor. The magnetic and electric surface currents in the presence of the grounded dielectric slab are shown in Figure 5.11.

372


Jt microstrip

Js

~

,,~n

d plane

Figure 5.11 Modeling the source current in a microstrip antenna.

The magnetic surface current density M is related to the electric field in the surface between the patch microstrip and the ground plane by M = - n x E - ( - 2 n x E)

if ground plane removed,

(5.42)

where n is the unit vector pointing outward. The electric surface current density Js is given by Js = n • H,

(5.43)

and the current Jt is the tangential surface current on the top surface of the microstrip. In reality both currents Js and Jt are small compared to M, which is the dominant current. The radiated fields can be obtained by treating the antenna as an aperture. Let us first consider the rectangular microstrip shown in Figure 5.12. The rectangular patch is one of the two most popular microstrip antenna types in wireless design (the other being the circular patch).


373

Substrate

Figure 5.12

Rectangular microstrip patch antenna parameters.

Let us assume that Eaperture =axEo is a constant (we are neglecting Equation (5.42), we can say that M = - 2 n • E t = - 2 a X X ayE 0 -- - 2 a z E o.

Ey). From (5.44)

The far fields components of the electric field are given by Er=EO=O

bhkE~

~=-~

~=~

sin 0

sin(-~-sin 0 cos ~ b ) [ s i n ( ~ ........

cos O)

L~sin0cos~ [(~cos0)

. (5.45)

For small values of h (h < < ,~), the preceding equations reduce to

si.( cos 0) E4, = - j - ~R

sin 0

cos 0

(5.46)

374


Notice that in both of these equations, Vs = h E o, where Vs is the voltage across the feed point. The resonance modes (or resonant frequencies) can be obtained by solving the Helmholz equation

[77.2 .+_ K m2n ] E m n -

(5.47)

O,

yielding

_

1

~(~_~)2

Kmn = (fR)mn -- 2r

m =0,

(~_~)2 +

1,2,3 ....

n =0,

(5.48)

,

1,2,3 ....

The radiated power is given by

27r 7r/2 PRad-- L f f }E4~NR2 sin e d8

(5.49)

d4~.

r/~ o o The typical radiation pattern of a rectangular microstrip antenna is shown in Figure 5.13.

-X~

~h

-Z 'V\

f" l Figure 5.13

J

E~

I Substrate Feed

Typical radiation pattern of a rectangular microstrip antenna.

5.10. Array Theory

375

5.10 Array Theory Arrays of radiating elements provide high directivity, narrow beams, low side lobes, steerable beams, particular pattern characteristics, and more efficient use of radiated power. In wireless communications, array antennas are used mainly in satellite communications systems. Array antennas together with reflector antennas are the most widely used types of antennas in satellite telecommunications. The design of an array involves mainly the following factors: 1. The selection of elements and array geometry. For example, rectangular and circular patches are the most frequently used array elements; circular and square geometries are also the most frequently used array geometries. 2. The determination of the element excitations required for a given performance. 3. Detailed knowledge of element input impedance and mutual impedance between any two elements in the array. As with other types of antennas, we are only interested in far-field theory for wireless communications. Consider the generalized array in Figure 5.14.

Array Elements /

Rn '

k

Y

Figure 5.14 Array of identical elements.

P (Observation Point)

376


For any element in the array of Figure 5.14, A(r) =

tz "rre-JZ'R R f j(R,)e-J,R'

cos ~ dv',

(5.50)

V

where

J(R')

= dielectric current distribution of the array element

R

= observation point vector

R'

= source element position vector

V

= volume of source element

cos ~ = R' 9R', k = 2'n/A, is the free space number, and jkR' cos ~ = j k - R'. The far fields are given by E(R) =

-jwA +

H(R) ~ - 1 R X E, 17

1

7-:---VV- A -~ j w (~0 + ~)~)). A where q7 =

%/tz/e,.

(5.51)

For an array of N elements, the far field can be expressed as

E(R) ~_ --i t~jO.)-jkR r..~

F(O,~),

4 7rR

(5.52)

where N F ( 0 , ~b) =

E

Fn (Oq~) = ( ~ + $ $ )

n= 1

f

Jn(ern)e -jkk'(R'-Rn) dV n. r

nth element

Here, Rn = reference point in the nth element R',, = nth element Fn(0,~b) is known as the nth element pattern function. If all the elements are the same,

F,,( O, ck) = I,,Fo( O,4,),

(5.53)

where I,, is the complex excitation of the nth element. Fo(0,~b) is the pattern function of any single element.

5.10. Array Theory

377

Equation (5.53) becomes E(R)

=

--Jt~ 4"n'R

N F~ O'~) ~ Ine-J~R'R""

(5.54)

n=l

If the array is linear as shown in Figure 5.15, with array elements separated by a distance d, then for the nth element R n = fiz nd, and for an array of N elements, N

Inejknclcos 0.

F(0, ~b) = F(0) = ~ n=l

The far-field equation becomes N

E(R) = --Jt~ 4erR

Fo( O)~ Ine-jknd cos o. n=l

1

/

R4 f

R3'I

f

I

f f f

d

f

R2]

I

f

i

f

Figure 5.15

Linear array of dipole antennas.

(5.55)

378


If all the excitations I,, are equal and if the reference point is the physical center of the array, then

sin( Nkdc~

N

F( O) = In ~

e j#'nd cos

o=

n=l

iN

(5.56) sin( kd c~ 2 0)

and again the far field for a linear array of N elements with the same excitation for each array element is given by E(R) =

-J~ 4~R

sin[(Nkdcos 0) / 2] F~ O)IN sin[(kd cos 0) / 2] "

(5.57)

A normalized pattern of the array factor as a function of kd cos 0 is shown in Figure 5.16 for several values of N. The term sin[(Nkd cos O)/2]/sin[(kdcos 0)/2] is known as the array factor. The beam maximum appears at 0 = 7r/2. Therefore, the array is called a broadside array. When 0 = 0, the main beam will be along the array axis, and the array is called end-fire. Some important formulas, such as directivity D, half-power beamwidth, beamwidth between first nulls, null angular position, side-lobe maximum position, and far broadside and end-fire uniform arrays are given in Table 5.1. Table 5.1

1.0

0.5

0.0

"

0.04

0.08

0.12

0.16

0.20

0.24

0.28 0.32

v

0.36

0.40

0.48

kd cos O

Figure 5.16

Normalized pattern for an array of N linear elements.

Table 5.1 Formulas for Several Linear Arrays

Directivity

-

-

Uniform Broadside (Nd >> A)

2N (&A)

4N ( d A )

Half-power beamwidth (%-&A

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