The Circuits and Filters Handbook

© 2003 by CRC Press LLC

© 2003 by CRC Press LLC

© 2003 by CRC Press LLC

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Library of Congress Cataloging-in-Publication Data The circuits and filters handbook / editor-in-chief, Wai Kai Chen.— 2nd ed. p. cm. — (The electrical engineering handbook series)

Includes bibliographical references and index.

ISBN 0-8493-0912-3 (alk. paper)

1. Electronic circuits. 2. Electric filters. I. Chen, Wai-Kai, 1936- II. Series. TK7867 .C4977 2002 621.3815—dc21

2002031311

This book contains information obtained from authentic and highly regarded sources. Reprinted material is quoted with permission, and sources are indicated. A wide variety of references are listed. Reasonable efforts have been made to publish reliable data and information, but the authors and the publisher cannot assume responsibility for the validity of all materials or for the consequences of their use. Neither this book nor any part may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, microfilming, and recording, or by any information storage or retrieval system, without prior permission in writing from the publisher. All rights reserved. Authorization to photocopy items for internal or personal use, or the personal or internal use of specific clients, may be granted by CRC Press LLC, provided that $1.50 per page photocopied is paid directly to Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923 USA The fee code for users of the Transactional Reporting Service is ISBN 0-8493-0912-3/03/$0.00+$1.50. The fee is subject to change without notice. For organizations that have been granted a photocopy license by the CCC, a separate system of payment has been arranged. The consent of CRC Press LLC does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific permission must be obtained in writing from CRC Press LLC for such copying. Direct all inquiries to CRC Press LLC, 2000 N.W. Corporate Blvd., Boca Raton, Florida 33431. Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used only for identification and explanation, without intent to infringe.

Visit the CRC Press Web site at www.crcpress.com © 2003 by CRC Press LLC

No claim to original U.S. Government works

International Standard Book Number 0-8493-0912-3

Library of Congress Card Number 2002031311

Printed in the United States of America 1 2 3 4 5 6 7 8 9 0

Printed on acid-free paper

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Preface

We are most gratified to find that the first edition of The Circuits and Filters Handbook (1995) was well received and is widely used. Thus, we feel that our original goal of providing in-depth professional level coverage of circuits and filters was, indeed, worthwhile. Eight years is a short time in terms of development of science or technology; but as this Handbook shows, momentous changes have occurred during this period, necessitating not only the updating of many chapters of the Handbook, but more startling, the addition and expansion of many topics. Significant examples are entries for design automation, circuit simulation, hardware/software co-design, and VLSI circuits to name a few of the more prominent additions.

Purpose The purpose of The Circuits and Filters Handbook is to provide in a single volume a comprehensive reference work covering the broad spectrum of electrical circuits and filters. It is written and developed for the practicing electrical engineers in industry, government, and academia. The goal is to provide the most up-to-date information in classical fields of circuit theory, circuit components and their models, feedback circuits, nonlinear circuits, distributed circuits, active and passive filters, general circuit analysis techniques, digital filters, and analog integrated circuits, while covering the emerging fields of digital and analog VLSI circuits, computer-aided design and optimization techniques, and design automation. In addition, the necessary background in mathematics is reviewed in the first section. The Handbook is not an all-encompassing digest of everything taught within an electrical engineering curriculum on circuits and filters. Rather, it is the engineer's first choice in looking for a solution. Therefore, full references to other sources of contributions are provided. The ideal reader is a B.S. level engineer with a need for a one-source reference to keep abreast of new techniques and procedures as well as review standard practices.

Background The Handbook stresses fundamental theory behind professional applications. In order to do so, it is reinforced with frequent examples. Extensive development of theory and details of proofs have been omitted. The reader is assumed to have a certain degree of sophistication and experience. However, brief reviews of theories, principles, and mathematics of some subject areas are given. These reviews have been done concisely with perception. The Handbook is not a textbook replacement, but rather a reinforcement and reminder of material learned as a student. Therefore, important advancement and traditional as well as innovative practices are included. Since the majority of professional electrical engineers graduated before powerful personal computers were widely available, many computational and design methods may be new to them. Therefore, computers and software use is thoroughly covered. The handbook uses not only traditional references to cite sources for the contributions, it also contains relevant sources of information and tools that will assist the engineer in performing his/her job. This includes sources of software, databases, standards, seminars, conferences, etc. © 2003 by CRC Press LLC

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Organization Over the years, the fundamentals of electrical circuits and filters have evolved to include a wide range of topics and a broad range of practice. To encompass such a wide range of knowledge, the Handbook focuses on the key concepts, models, and equations that enable the electrical engineer to analyze, design, and predict the behavior of large-scale circuits, devices, filters, and systems. While design formulas and tables are listed, emphasis is placed on the key concepts and theories underlying the applications. The information is organized into 13 major sections, which encompass the field of electrical circuits and filters. Each section is divided into chapters. In all there are 93 chapters, each of which was written by leading experts in the field to enlighten and refresh knowledge of the mature engineer, and to educate the novice. The first section summarizes the applicable mathematics and symbols underlying other applications. Each section contains introductory material, leading to the appropriate applications. To help the reader, each article includes two important and useful categories: defining terms and references. Defining terms are key definitions and the first occurrence of each term defined is indicated in boldface in the text. The references provide a list of useful books and articles for following reading. Finally, further information contained in some articles provides general and useful sources of additional information on the topic.

Locating Your Topic Numerous avenues of access to information contained in the Handbook are provided. A complete table of contents is presented at the front of the book. In addition, an individual table of contents precedes each of the 13 sections. Finally, each chapter begins with its own table of contents. The reader is urged to look over these tables of contents to become familiar with the structure, organization, and content of the book. For example, see Section II: Circuit Elements, Devices and Their Models, then Chapter 10: Passive Circuit Elements, and then Chapter 10.1: Resistor. This tree-like structure enables the reader to move up the tree to locate information on the topic of interest. An index has been compiled to provide multiple means of accessing information. It includes authors and subjects. The index can also be used to locate definitions. The page on which the definition appears for each key defining term is given in this index. The Circuits and Filters Handbook is designed to provide answers to most inquiries and direct the inquirer to further sources and references. We trust that it will meet your needs.

Acknowledgments The compilation of this book would not have been possible without the dedication and efforts of the Editorial Board of Advisors, the section editors, the publishers, and most of all the contributing authors. I particularly wish to acknowledge Richard C. Dorf, Handbook Series Editor, for his leadership, and my wife, Shiao-Ling, for her patience and support. Wai-Kai Chen Editor-in-Chief

© 2003 by CRC Press LLC

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Editor-in-Chief

Wai-Kai Chen, Professor and Head Emeritus of the Depart­ ment of Electrical Engineering and Computer Science at the University of Illinois at Chicago, is now serving as Academic Vice President at International Technological University. He received his B.S. and M.S. degrees in electrical engineering at Ohio University, where he was later recognized as a Distin­ guished Professor. He earned his Ph.D. in electrical engineering at the University of Illinois at Urbana/Champaign. Professor Chen has extensive experience in education and industry and is very active professionally in the fields of circuits and systems. He has served as visiting professor at Purdue Uni­ versity, University of Hawaii at Manoa, and Chuo University in Tokyo, Japan. He was Editor of the IEEE Transactions on Circuits and Systems, Series I and II, President of the IEEE Circuits and Systems Society, and is the Founding Editor and Editor-inChief of the Journal of Circuits, Systems and Computers. He received the Lester R. Ford Award from the Mathematical Asso­ ciation of America, the Alexander von Humboldt Award from Germany, the JSPS Fellowship Award from Japan Society for the Promotion of Science, the Ohio University Alumni Medal of Merit for Distinguished Achievement in Engineering Education, the Senior University Scholar Award and the 2000 Faculty Research Award from the University of Illinois at Chicago, and the Distinguished Alumnus Award from the University of Illinois at Urbana/Champaign. He is the recipient of the Golden Jubilee Medal, the Education Award, the Meritorious Service Award from IEEE Circuits and Systems Society, and the Third Millennium Medal from the IEEE. He has also received more than a dozen honorary professorship awards from major institutions in China. A fellow of the Institute of Electrical and Electronics Engineers and the American Association for the Advancement of Science, Professor Chen is widely known in the profession for his Applied Graph Theory (North-Holland), Theory and Design of Broadband Matching Networks (Pergamon Press), Active Network and Feedback Amplifier Theory (McGraw-Hill), Linear Networks and Systems (Brooks/Cole), Passive and Active Filters: Theory and Implements (John Wiley), Theory of Nets: Flows in Networks (Wiley-Interscience), and The VLSI Handbook (CRC Press).

© 2003 by CRC Press LLC

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Advisory Board

Leon O. Chua University of California Berkeley, California

John Choma, Jr. University of Southern California Los Angeles, California

Lawrence P. Huelsman University of Arizona Tucson, Arizona

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Contributors

Rahim Akbari-Dilmaghani

Martin A. Brooke

Moon-Jung Chung

University College of London London, England

Georgia Institute of Technology Atlanta, Georgia

Michigan State University East Lansing, Michigan

Philip E. Allen

Gordon E. Carlson

David J. Comer

Georgia Institute of Technology Atlanta, Georgia

University of Missouri Rolla, Missouri

Rashid Ansari

A. Enis Cetin

University of Illinois at Chicago Chicago, Illinois

Bilkent University Bilkent, Ankara, Turkey

Andreas Antoniou

Josephine C. Chang

University of Victoria Victoria, British Columbia, Canada

Peter Aronhime University of Louisville Louisville, Kentucky

James H. Aylor University of Virginia Charlottesville, Virginia

Peter Bendix LSI Logic Santa Clara, California

Jay Bhasker eSilicon Corporation Allentown, Pennsylvania

Benjamin J. Blalock The University of Tennessee Knoxville, Tennessee

Bruce W. Bomar The University of Tennessee Tullahoma, Tennessee

Taiwan Semiconductor Manufacturing Co. Taiwan

Robert C. Chang National Chung Hsing University Taiwan

K.S. Chao Texas Tech University Lubbock, Texas

Guanrong Chen

Brigham Young University Provo, Utah

Donald T. Comer Brigham Young University Provo, Utah

A. G. Constantinides Imperial College London, England

Don Cottrell Si2, Inc. Austin, Texas

Artice M. Davis San Jose State University San Jose, California

Bram De Muer

City University of Hong Kong Kowloon, Hong Kong

Katholieke Universiteit Leuven Leuven-Heverlee, Belgium

Ray R. Chen

Daniël De Zutter

San Jose State University San Jose, California

Gent University Gent, Belgium

Wai-Kai Chen

James F. Delansky

University of Illinois Chicago, Illinois

The Pennsylvania State University University Park, Pennsylvania

John Choma, Jr.

Manuel Delgado-Restituto

University of Southern California Los Angeles, California

Universidad de Sevilla Sevilla, Spain

Marc Borremans

Leon O. Chua

John R. (Jack) Deller, Jr.

Katholieke Universiteit Leuven Leuven-Heverlee, Belgium

University of California Berkeley, California

Michigan State University East Lansing, Michigan

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Allen M. Dewey (Deceased) Duke University Durham, North Carolina

Abhijit Dharchoudhury Intel Corporation Austin, Texas

Igor Djokovic California Institute of Technology Pasadena, California

Ramesh Harjani

Sung-Mo Kang

University of Minnesota Minneapolis, Minnesota

University of California Santa Cruz, California

Martin Hasler

Michael Peter Kennedy

Swiss Federal Institute of Technology Lausanne, Switzerland

University College Dublin, Ireland

Marwan M. Hassoun

I-Hung Khoo

Iowa State University Ames, Iowa

University of California Irvine, California

Maria del Mar Hershenson

Heechul Kim

Nanyang Technological University Singapore

Stanford University Stanford, California

Hankuk University of Foreign Studies Yongin, Kyung Ki-Do, North Korea

Joseph B. Evans

Shu-Chuan Huang

Robert H. Klenke

ITTC Lawrence, Kansas

The Ohio State University Columbus, Ohio

Virginia Commonwealth University Richmond, Virginia

Igor Filanovsky

Yih-Fang Huang

Jelena Kovaˇcevic´

University of Notre Dame Notre Dame, Indiana

Bell Labs, Lucent Technologies New Vernon, New Jersey

Larry P. Huelsman

Stuart S. Lawson

University of Arizona Tucson, Arizona

University of Warwick Coventry, England

J. L. Huertas

Thomas H. Lee

Universidad de Sevilla Sevilla, Spain

Stanford University Stanford, California

Virginia Polytechnic Institute and State University Blacksburg, Virginia

Chung-Chih Hung

John Lidgey

Tatung Institute of Technology Taipei, Taiwan

Oxford Brookes University London, England

F. Gail Gray

Thomas Koryu Ishii

Yong-Ching Lim

Marquette University Milwaukee, Wisconsin

National University of Singapore Singapore

Mohammed Ismail

Pen-Min Lin

The Ohio State University Columbus, Ohio

Purdue University West Lafayette, Indiana

Meng Hwa Er

University of Alberta Edmonton, Alberta, Canada

Norbert J. Fliege University of Mannheim Mannheim, Germany

Sergio B. Franco San Francisco State University San Francisco, California

Yosef Gavriel

Virginia Polytechnic Institute and State University Blacksburg, Virginia

Edwin W. Greeneich Arizona State University Tempe, Arizona

Johan Janssens

Erik Lindberg

TRLabs, University of Alberta Edmonton, Alberta, Canada

Katholieke Universiteit Leuven Leuven-Heverlee, Belgium

Technical University of Denmark Lyngby, Denmark

David G. Haigh

W. Kenneth Jenkins

Stephen I. Long

University College of London London, England

The Pennsylvania State University University Park, Pennsylvania

University of California Santa Barbara, California

Wayne D. Grover

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Flavio Lorenzelli

Alice C. Parker

Trond Saether

University of Milan/Crema Crema, Italy

University of Southern California City of Commerce, California

Luc Martens

Alison Payne

Norwegian University of Science and Technology Trondheim, Norway

Gent University Gent, Belgium

Imperial College of Science London, England

Wolfgang Mathis

Tomasz W. Postupolski

University of Hannover Hannover, Germany

Wasfy B. Mikhael University of Central Florida Orlando, Florida

Stephen W. Milam RF Micro-Devices Carrollton, Texas

Sunderarajan S. Mohen Stanford University Stanford, California

Hirad Samavati

Roland Priemer

Edgar Sánchez-Sinencio

University of Illinois Chicago, Illinois

P. K. Rajan Tennessee Tech University Cookeville, Tennessee

Jaime Ramirez-Angulo New Mexico State University Las Cruces, New Mexico

Hari C. Reddy

Queen's University Kingston, Ontario, Canada

California State University Long Beach, California

Robert W. Newcomb

Bill Redman-White

University of Maryland College Park, Maryland

University of Southampton Southamptom, England

Nhat M. Nguyen

Csaba Rekeczky

Truong Q. Nguyen

University of Notre Dame Notre Dame, Indiana

Institute of Electronic Materials Technology Warsaw, Poland

David G. Nairn

Rambus IMC.

Los Altos, California

Michael K. Sain

Hungarian Academy of Sciences Budapest, Hungary

Benedykt S. Rodanski

Stanford University Stanford, California

Texas A&M University College Station, Texas

Sachin S. Sapatnekar University of Minnesota Minneapolis, Minnesota

Tapio Saramäki Tampere University of Technology Tampere, Finland

Rolf Schaumann Portland State University Portland, Oregon

Cheryl B. Schrader The University of Texas San Antonio, Texas

Naveed Sherwani Intel Corporation Hillsboro, Oregon

University of California San Diego, California

University of Technology, Sydney Broadway, New South Wales, Australia

Bing J. Sheu

Kenneth V. Noren

Angel Rodríguez-Vázquez

José Silva-Martinez

University of Idaho Moscow, Idaho

Josef A. Nossek Technical University of Munich Munich, Germany

Stanislav Nowak University of Mining and Metallurgy Crakow, Poland

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Nassda Corporation Santa Clara, California

Universidad de Sevilla Sevilla, Spain

Texas A&M University College Station, Texas

J. Gregory Rollins

Marwan A. Simaan

Antrim Design Systems Scotts Valley, California

University of Pittsburgh Pittsburgh, Pennsylvania

Tamás Roska

L. Montgomery Smith

Hungarian Academy of Science Budapest, Hungary

The University of Tennessee Tullahoma, Tennessee

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Bang-Sup Song

Chris Toumazou

Chorng-Kuang Wang

University of California San Diego, California

Imperial College of Science London, England

National Taiwan University Taipei, Taiwan

F. William Stephenson

J. Trujillo

Bogdan M. Wilamowski

Virginia Polytechnic Institute and State University Blacksburg, Virginia

University of Southern California Los Angeles, California

University of Idaho Boise, Idaho

John P. Uyemura

Wayne Wolf

Georgia Institute of Technology Atlanta, Georgia

Princeton University Princeton, New Jersey

P. P. Vaidyanathan

Xiaojian Xu

California Institute of Technology Pasadena, California

Imperial College London, England

Texas A&M University College Station, Texas

L. Vandenberghe

Andrew T. Yang

James A. Svoboda

University of California Los Angeles, California

University of Washington Seattle, Washington

Clarkson University Potsdam, New York

J. Vandewalle

Kung Yao

Vladimir Székely

Katholieke Universiteit Leuven Leuven Heverlee, Belgium

University of California Los Angeles, California

F. Vidal

Min-Shueh Yuan

Universidad de Malaga Malaga, Spain

National Taiwan University Taipei, Taiwan

Sirindhorn International Institute of Technology Pathumthani, Thailand

Jiri Vlach

C. Patrick Yue

University of Waterloo Waterloo, Ontario, Canada

Stanford University Stanford, California

Krishnaiyan Thulasiraman

Suhrid A. Wadekar

Akos Zarandy

University of Oklahoma Norman, Oklahoma

IBM Corp. Riverside, California

Hungarian Academy of Science Budapest, Hungary

Michael Steyaert Katholieke Universiteit Leuven Leuven-Heverlee, Belgium

Maciej A. Styblinski (Deceased)

Budapest University of Technology and Economics Budapest, Hungary

Sawasd Tantaratana

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Table of Contents

SECTION I

Mathematics

Section Editor: Y.F. Huang

1

Linear Operators and Matrices

2

Bilinear Operators and Matrices

3

The Laplace Transformation

4

Fourier Series, Fourier Transforms and the Discrete Fourier Transform W. Kenneth Jenkins

5

z-Transform

6

Wavelet Transforms

7

Graph Theory

8

Signal Flow Graphs

9

Theory of Two-Dimensional Hurwitz Polynomials

SECTION II

Cheryl B. Schrader and Michael K. Sain Michael K. Sain and Cheryl B. Schrader

John R. Deller, Jr.

Jelena Kovacevic P.P. Vaidyanathan and Igor Djokovic

Krishnaiyan Thulasiraman Krishnaiyan Thulasiraman

Circuit Elements, Devices and Their Models

Section Editor: John Choma, Jr.

10

Passive Circuit Elements 10.1 10.2 10.3 10.4 10.5

Stanislav Nowak

Resistor Stanislav Nowak Capacitor Stanislav Nowak Inductor Tomasz W. Postupolski Transformer Gordon E. Carlson Semiconductor Diode Bogdan M. Wilamowski

© 2003 by CRC Press LLC

Hari C. Reddy

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11

RF Passive IC Components Tomas H. Lee, Maria del Mar Hershenson, Sunderarajan S. Mohen, Hirad Samavati, and C. Patrick Yue

12

Circuit Elements, Modeling and Equation Formulation

13

Controlled Circuit Elements

14

Bipolar Transistors (BJT) Circuits

15

Operational Amplifiers

16

High-Frequency Amplifiers

Josef A. Nossek

13.1 Controlled Sources Edwin W. Greenneich 13.2 Signal Converters James F. Delansky

David J. Comer and Donald T. Comer

15.1 The Ideal Operational Amplifier David G. Nairn 15.2 The Non-Ideal Operational Amplifier David G. Nairn 15.3 Frequency- and Time-Domain Considerations Sergio Franco

SECTION III

Chris Toumazou and Alison Payne

Linear Circuit Analysis

Section Editor: Larry P. Huelsman.

17

Fundamental Circuit Concepts

18

Network Laws and Theorems

19

Terminal and Port Representation

20

Signal Flow Graphs in Filter Analysis and Synthesis

21

Analysis in the Frequency Domain

22

Tableau and Modified Nodal Formulations

John Chroma, Jr

18.1 Kirchhoff's Voltage and Current Laws Ray R. Chen and Artice M. Davis 18.2 Network Theorems Marwan A. Simaan

James A. Svoboda

21.1 Network Functions Jiri Vlach 21.2 Advanced Network Analysis Concepts John Chroma, Jr.

© 2003 by CRC Press LLC

Jiri Vlach

Pen-Min Lin

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23

Frequency Domain Methods

24

Symbolic Analysis

25

Analysis in the Time Domain

26

State-Variable Techniques

SECTION IV

Peter Aronhime

Benedykt S. Rodanski and Marwan Hassoun Robert W. Newcomb

K.S. Chao

Feedback Circuits

Section Editor: Wai-Kai Chen

27

Feedback Amplifier Theory

28

Feedback Amplifier Configurations

29

General Feedback Theory

30

The Network Functions and Feedback

31

Measurement of Return Difference

Wai-Kai Chen

32

Multiple-Loop Feedback Amplifiers

Wai-Kai Chen

SECTION V

John Choma, Jr. John Choma, Jr.

Wai-Kai Chen Wai-Kai Chen

Nonlinear Circuits

Section Editor: Leon O. Chua

33

Qualitative Analysis

34

Synthesis and Design of Nonlinear Circuits Manual Delgado-Restituto, and J.L. Huertas

35

Representation, Approximation, and Identification

36

Transformation and Equivalence

© 2003 by CRC Press LLC

Martin Hasler

Angel Rodriguez-Vazquez,

Wolfgang Mathis

Guanrong Chen

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37

Piecewise-Linear Circuits and Piecewise-Linear Analysis and L. Vandenberghe

38

Simulation

39

Cellular Neural Networks Rekeczky

40

Bifurcation and Chaos

SECTION VI

Joo Vandewalle

Erik Lindberg Tamas Roska, Akos Zarandy, and Csaba

Michael Peter Kennedy

Distributed Circuits

Section Editor: Thomas Koryu Ishii

41

Transmission Lines

42

Multiconductor Tranmission Lines

43

Time and Frequency Domain Responses Martens

44

Distributed RC Networks

45

Synthesis of Distributed Circuits

SECTION VII

Thomas Koryu Ishii Daniel De Zutter and Luc Martens Daniel De Zutter and Luc

Vladimir Szekely Thomas Koryu Ishii

Computer-Aided Design and Optimization

Section Editor: Sung-Mo Kang

46

Modeling of Circuit Performances Dharchoudhury

47

Symbolic Analysis Methods

48

Numerical Analysis Methods

© 2003 by CRC Press LLC

Sung-Mo Kang and Abhijit

Benedydt S. Rodanski and Marwan Hassoun Andrew T. Yang

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49

Design by Optimization

50

Statistical Design Optimization Styblinski

51

Physical Design Automation

52

Design Automation Technology

53

Computer-Aided Analysis

54

Analog Circuits Simulation

Sachin S. Sapatnekar Maciej A. Styblinski and Bogumila

Naveed A. Sherwani Allen M. Dewey

53.1 Circuit Simulation Using SPICE and SUPREM J. Gregory Rollins 53.2 Parameter Extraction for Analog Circuit Simulation Peter Bendix

SECTION VIII

J. Gregory Rollins

Analog Intergrated Circuits

Section Editor: John Choma, Jr.

55

Monolithic Device Models

56

Analog Circuit Cells

57

High Performance Analog Circuits

55.1 55.2 55.3 55.4 55.5

Bipolar Junction Transistor Bogdan M. Wilamowski MOSFET Technology Devices John Choma, Jr. JFET Technology Transistors Stephen I. Long Passive Components Nhat M. Nguyen Chip Parasitics in Analog Integrated Circuits Martin A. Brooke

56.1 Bipolar Biasing Circuits Kenneth V. Noren 56.2 Canonical Cells of Bipolar Technology John Choma, Jr. 56.3 Canonical Cells of MOSFET Technology Mohammed Ismail, Shu-Chuan Huang, Chung-Chih Hung, and Trond Saether 56.4 MOSFET Biasing Circuits David G. Haigh, Bill Redman-White, and Rahim Akbari-Dilmaghani

57.1 Broadband Bipolar Networks Chris Toumazou, Alison Payne, and John Lidgey 57.2 Bipolar Noise Bogdan M. Wilamowski

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58

RF Communication Circuits Borremans and Bram De Muer

59

PLL Circuits

SECTION IX

Michael Steyaert, Johan Janssens, Marc

Chorng-Kuang Wang and Min-Shueh Yuan

The VLSI Circuits

Section Editor: John Choma, Jr.

60

Digital Circuits

61

Digital Systems

62

60.1 MOS Logic Circuits John P. Uyemura 60.2 Transmission Gates Robert C. Chang and Bing J. Sheu

61.1 61.2 61.3 61.4 61.5

Programmable Logic Devices Festus Gail Gray Clocking Schemes Wayne D. Grover MOS Storage Circuits Bing J. Sheu and Josephine C. Chang Microprocessor-Based Design Roland Priemer Systolic Arrays Kung Yao and Flavio Lorenzelli

Data Convertors 62.1 Digital-to-Analog Converters Bang-Sup Song 62.2 Analog-to-Digital Converters Ramesh Harjani

SECTION X

Design Automation

Section Editor: Allen M. Dewey

63

Internet Based Micro-Electronic Design Automation (IMEDA) Framework Moon-Jung Chung and Heechul Kim

64

System-Level Design Wadekar

65

Synthesis at the Register Transfer Level and the Behavioral Level Jay Bhasker

66

Embedded Computing Systems and Hardware/Software Co-Design Wayne Wolf

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Alice C. Parker, Yosef Tirat-Gefen, and Suhrid A.

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67

Design Automation Technology Roadmap

68

Performance Modeling and Analysis in VHDL Robert H. Klenke

SECTION XI

Don Cottrell James H. Aylor and

Passive Filters

Section Editors: Larry P. Huelsman and Wai-Kai Chen.

69

General Characteristics of Filters

70

Approximation

71

Frequency Transformations

72

Sensitivity and Selectivity

73

Passive Immittances and Positive-Real Functions

74

Passive Cascade Synthesis

75

Synthesis of LCM and RC One-Port Networks

76

Two-Port Synthesis by Ladder Development

77

Design of Resistively Terminated Networks

78

Design of Broadband Matching Networks

SECTION XII

Andreas Antoniou

Artice M. Davis Jaime Ramirez-Angulo Igor Filanovsky Wai-Kai Chen

Wai-Kai Chen Wai-Kai Chen Wai-Kai Chen Wai-Kai Chen Wai-Kai Chen

Active Filters

Section Editor: Larry P. Huelsman

79

Low-Gain Active Filters Stephen W. Milam

80

Single-Amplifier Multiple-Feedback Filters

© 2003 by CRC Press LLC

Philip E. Allen, Benjamin J. Blalock, and

F. William Stephenson

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81

Multiple-Amplifier Biquads

82

The Current Generalized Immittance Converter (CGIC) Biquads Wasfy B. Mikhael

83

Higher-Order Filters

84

Continuous-Time Integrated Filters

85

Switched Capacitor Filters

SECTION XIII

Norbert Fliege

Rolf Schaumann Rolf Schaumann

Jose Silva-Martinez and Edgar Sanchez-Sinencio

Digital Filters

Section Editor: Yong-Ching Lim.

86

FIR Filters

87

IIR Filters

88

Finite Wordlength Effects

89

Aliasing-Free Reconstruction Filter Bank

90

VLSI Implementation of Digital Filters

91

Two-Dimensional FIR Filters

Rashid Ansari and A. Enis Cetin

92

Two-Dimensional IIR Filters

A. G. Constantinides and Xiaojian Xu

93

Symmetry and 2-D Filter Design P. K. Rajan

86.1 Properties of FIR Filters Meng Hwa Er 86.2 Window Techniques Meng Hwa Er 86.3 Design of FIR Filters by Optimization Andreas Antoniou, L. Montgomery Smith, Bruce W. Bonar, Yong-Ching Lim, and Tapio Saramaki

87.1 87.2 87.3 87.4

Properties of IIR Filters Sawasd Tantaratana Design of IIR Filters Sawasd Tantaratana Wave Digital Filters Stuart S. Lawson Lattice Filters Yong-Ching Lim

© 2003 by CRC Press LLC

Bruce W. Bonar Truong Q. Nguyen Joseph B. Evans

Hari C. Reddy, I-Hung Khoo, and

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I Mathematics Y. F. Huang University of Notre Dame 1 Linear Operators and Matrices Cheryl B. Schrader, Michael K. Sain Introduction • Vector Spaces over Fields • Linear Operators and Matrix Representations • Matrix Operations • Determinant, Inverse, and Rank • Basis Transformations • Characteristics: Eigenvalues, Eigenvectors, and Singular Values • On Linear Systems

2 Bilinear Operators and Matrices Michael K. Sain, Cheryl B. Schrader Introduction • Algebras • Bilinear Operators • Tensor Product • Basis Tensors • Multiple Products • Determinants • Skew Symmetric Products • Solving Linear Equations • Symmetric Products • Summary

3 The Laplace Transform John R. Deller, Jr. Introduction • Motivational Example • Formal Developments • Laplace Transform Analysis of Linear Systems • Conclusions and Further Reading • Appendix A: The Dirac Delta (Impulse) Function • Appendix B: Relationships among the Laplace, Fourier, and z-Transforms

4 Fourier Series, Fourier Transforms, and the Discrete Fourier Transform W. Kenneth Jenkins Introduction • Fourier Series Representation of Continuous-Time Periodic Signals • The Classical Fourier Transform for Continuous-Time Signals • The Discrete-Time Fourier Transform • The Discrete Fourier Transform • The Family Tree of Fourier Transforms • The Walsh–Hadamard Transform • Selected Applications of Fourier Methods • Summary

5 z-Transform Jelena Kovaˇc evi´c Introduction • Definition of the z-Transform • Inverse z-Transform • Properties of the z-Transform • Role of the z-Transform in Linear Time-Invariant Systems • Variations on the z-Transform • Concluding Remarks

6 Wavelet Transforms P. P. Vaidyanathan, Igor Djokovic Introduction • Signal Representation Using Basis Functions • The Short-Time Fourier Transform • Digital Filter Banks and Subband Coders • Deeper Study of Wavelets, Filter Banks, and Short-Time Fourier Transforms • The Space of L1 and L2 Signals • Riesz Basis, Biorthogonality, and Other Fine Points • Frames in Hilbert Spaces • Short-Time Fourier Transform: Invertibility, Orthonormality, and Localization • Wavelets and Multiresolution • Orthonormal Wavelet Basis from Paraunitary Filter Banks • Compactly Supported Orthonormal Wavelets • Wavelet Regularity • Concluding Remarks

7 Graph Theory Krishnaiyan Thulasiraman Introduction • Basic Concepts • Cuts, Circuits, and Orthogonality • Incidence, Circuit, and Cut Matrices of a Graph • Orthogonality Relation and Ranks of Circuit and Cut Matrices • Spanning Tree Enumeration • Graphs and Electrical Networks • Tellegen’s Theorem and Network Sensitivity Computation • Arc Coloring Theorem and the No-Gain Property

8 Signal Flow Graphs Krishnaiyan Thulasiraman Introduction • Adjacency Matrix of a Directed Graph • Coates’ Gain Formula • Mason’s Gain Formula

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9 Theory of Two-Dimensional Hurwitz Polynomials Hari C. Reddy Introduction • Preliminaries and Notations • Value of Two-Variable Polynomial at Infinity • Various Analog Hurwitz Polynomials • Testsets for Analog Hurwitz Polynomials • TwoVariable Very Strict Hurwitz Polynomials • Application of Two-Dimensional Hurwitz Polynomials for Two-Variable Passive Networks and Stability • Conclusions

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1 Linear Operators and Matrices

Cheryl B. Schrader The University of Texas

Michael K. Sain University of Notre Dame

1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8

Introduction Vector Spaces over Fields Linear Operators and Matrix Representations Matrix Operations Determinant, Inverse, and Rank Basis Transformations Characteristics: Eigenvalues, Eigenvectors, and Singular Values On Linear Systems

1.1 Introduction It is only after the engineer masters linear concepts — linear models, and circuit and filter theory — that the possibility of tackling nonlinear ideas becomes achievable. Students frequently encounter linear methodologies, and bits and pieces of mathematics that aid in problem solution are stored away. Unfor­ tunately, in memorizing the process of finding the inverse of a matrix or of solving a system of equations, the essence of the problem or associated knowledge may be lost. For example, most engineers are fairly comfortable with the concept of a vector space, but have difficulty in generalizing these ideas to the module level. Therefore, it is the intention of this section to provide a unified view of key concepts in the theory of linear circuits and filters, to emphasize interrelated concepts, to provide a mathematical reference to the handbook itself, and to illustrate methodologies through the use of many and varied examples. This chapter begins with a basic examination of vector spaces over fields. In relating vector spaces the key ideas of linear operators and matrix representations come to the fore. Standard matrix operations are examined as are the pivotal notions of determinant, inverse, and rank. Next, transformations are shown to determine similar representations, and matrix characteristics such as singular values and eigenvalues are defined. Finally, solutions to algebraic equations are presented in the context of matrices and are related to this introductory chapter on mathematics as a whole. Standard algebraic notation is introduced first. To denote an element s in a set S, use s ∈ S. Consider two sets S and T. The set of all ordered pairs (s, t) where s ∈ S and t ∈ T is defined as the Cartesian product set S × T. A function f from S into T, denoted by f : S → T, is a subset U of ordered pairs (s, t) ∈ S × T such that for every s ∈ S one and only one t ∈ T exists such that (s, t) ∈ U. The function evaluated at the element s gives t as a solution (f (s) = t), and each s ∈ S as a first element in U appears exactly once. A binary operation is a function acting on a Cartesian product set S × T. When T = S, one speaks of a binary operation on S.

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1.2 Vector Spaces over Fields A field F is a nonempty set F and two binary operations, sum ( + ) and product, such that the following properties are satisfied for all a, b, c, ∈ F : 1. 2. 3. 4.

Associativity: Commutativity: Distributivity: Identities:

5. Inverses:

(a + b) + c = a + (b + c); (ab)c = a(bc) a + b = b + a; ab = ba a(b + c) = (ab) + (ac) (Additive) 0 ∈ F exists such that a + 0 = a

(Multiplicative) 1 ∈ F exists such that a1 = a

(Additive) For every a ∈ F, b ∈ F exists such that a + b = 0 (Multiplicative) For every nonzero a ∈ F, b ∈ F exists such that ab = 1

Examples • • • •

Field of Field of Field of Field of

real numbers R complex numbers C rational functions with real coefficients R(s) binary numbers

The set of integers Z with the standard notions of addition and multiplication does not form a field because a multiplicative inverse in Z exists only for ± 1. The integers form a commutative ring. Likewise, polynomials in the indeterminate s with coefficients from F form a commutative ring F[s]. If field property 2 also is not available, then one speaks simply of a ring. An additive group is a nonempty set G and one binary operation + satisfying field properties 1, 4, and 5 for addition; i.e., associativity and the existence of additive identity and inverse. Moreover, if the binary operation + is commutative (field property 2), then the additive group is said to be abelian. Common notation regarding inverses is that the additive inverse for a ∈ F is b = –a ∈ F. In the multiplicative case b = a –1 ∈ F. An F-vector space V is a nonempty set V and a field F together with binary operations + : V × V → V and ∗ : F × V → V subject to the following axioms for all elements v, w ∈ V and a, b ∈ F: 1. 2. 3. 4. 5.

V and + form and additive abelian group a ∗ (v + w) = (a ∗ v) + (a ∗ w) (a + b) ∗ v = (a ∗ v) + (b ∗ v) (ab) ∗ v = a ∗ (b ∗ v) 1∗v=v

Examples • The set of all n-tuples (v1, v2, …, vn) for n > 0 and vi ∈ F • The set of polynomials of degree less than n with real coefficients (F = R) Elements of V are referred to as vectors, whereas elements of F are scalars. Note that the terminology vector space V over the field F is used often. A module differes from a vector space in only one aspect; the underlying field in a vector space is replaced by a ring. Thus, a module is a direct generalization of a vector space. When considering vector spaces of n-tuples, + is vector addition defined by element using the scalar addition associated with F. Multiplication (∗), which is termed scalar multiplication, also is defined by element using multiplication in F. The additive identity in this case is the zero vector (n-tuple of zeros) or null vector, and F n denotes the set of n-tuples with elements in F, a vector space over F. A nonempty – subset V ⊂ V is called a subspace of V if for each v, w ∈V˜ and every a ∈ F, v + w ∈V˜ and a ∗ v ∈V˜ . When the context makes things clear, it is customary to suppress the ∗, and write av in place of a ∗ v. A set of vectors {v1, v2, …, vm} belonging to an F-vector space V is said to span the vector space if any element v ∈ V can be represented by a linear combination of the vectors vi . That is, scalars a1, a2, …, am ∈ F are such that © 2003 by CRC Press LLC

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v = a1v1 + a2v 2 +L+ amv m

(1.1)

A set of vectors {v1, v2, …, vp} belonging to an F-vector space V is said to be linearly dependent over F if scalars a1, a2, …, ap ∈ F, not all zero, exist such that a1v1 + a2v 2 + L + a pv p = 0

(1.2)

If the only solution for (1.2) is that all ai = 0 ∈ F, then the set of vectors is said to be linearly independent. Examples • (1, 0) and (0,1) are linearly independent. • (1, 0, 0), (0, 1, 0), and (1, 1, 0) are linearly dependent over R. To see this, simply choose a1 = a2 = 1 and a3 = –1. • s2 + 2s and 2s + 4 are linearly independent over R, but are linearly dependent over R (s) by choosing a1 = – 2 and a2 = s. A set of vectors {v1, v2, …, vn} belonging to an F-vector space V is said to form a basis for V if it both spans V and is linearly independent over F. The number of vectors in a basis is called the dimension of the vector space, and is denoted dim(V). If this number is not finite, then the vector space is said to be infinite dimensional. Examples • In an n-dimensional vector space, any n linearly independent vectors form a basis. • The natural (standard) basis 1 0 0 0 0           0 0 1 0 0           0 0 0 0 1 e1 =   , e 2 =   , e3 =   ,L, en − 1 =   , en =   M  M  M  M  M            0 1 0 0 0           0 0 0 1 0           both spans F n and is linearly independent over F. Consider any basis {v1, v2, …, vn} in an n-dimensional vector space. Every v ∈V can be represented uniquely by scalars a1, a2, …, an ∈ F as v = a1v1 + a2v 2 + L + anv n

= [v1 v 2

 a1    a 2  L vn]   M   a   n

= [v1 v 2 L v n ] a © 2003 by CRC Press LLC

(1.3)

(1.4)

(1.5)

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Here, a ∈ F n is a coordinate representation of v ∈V with respect to the chosen basis. The reader will be able to discern that each choice of basis will result in another representation of the vector under consid­ eration. Of course, in the applications some representations are more popular and useful than others.

1.3 Linear Operators and Matrix Representations First, recall the definition of a function f : S → T. Alternate terminology for a function is mapping, operator, or transformation. The set S is called the domain of f, denoted D( f ). The range of f, R( f ), is the set of all t ∈T such that (s,t) ∈U (f(s) = t) for some s ∈ D( f ) . Examples Use S = {1, 2, 3, 4} and T = {5, 6, 7, 8}. • • •

U˜ = {(1, 5), (2, 5), (3, 7), (4, 8)} is a function. The domain is {1, 2, 3, 4} and the range is {5, 7, 8}. Uˆ = {(1, 5), (1, 6), (2, 5), (3, 7), (4, 8)} is not a function. U = {(1, 5), (2, 6), (3, 7), (4, 8)} is a function. The domain is {1, 2, 3, 4} and the range is {5, 6, 7, 8}.

If R( f ) = T, then f is said to be surjective (onto). Loosely speaking, all elements in T are used up. If f : S → T has the property that f (s1) = f (s2) implies s1 = s2, then f is said to be injective (one-to-one). This means that any element in R( f ) comes from a unique element in D( f ) under the action of f. If a function is both injective and surjective, then it is said to be bijective (one-to-one and onto). Examples • U˜ is not onto because 6 ∈ T is not in R( f ). Also U˜ is not one-to-one because f (1) = 5 = f (2), but 1≠ 2. • U is bijective. Now consider an operator L : V → W, where V and W are vector spaces over the same field F. L is said to be a linear operator if the following two properties are satisfied for all v, w ∈ V and for all a ∈F: L(av ) = aL(v )

(1.6)

L( v + w ) = L(v ) + L(w )

(1.7)

Equation (1.6) is the property of homogeneity and (1.7) is the property of additivity. Together they imply the principle of superposition, which may be written as L(a1v1 + a2v 2 ) = a1L(v1 ) + a2 L(v 2 )

(1.8)

for all v1, v2 ∈ V and a1, a2 ∈ F. If (1.8) is not satisfied, then L is called a nonlinear operator. Examples • Consider V = C and F = C. Let L : V → V be the operator that takes the complex conjugate: L(v) = v for v , v ∈V . Certainly L(v1 + v 2 ) = v1 + v 2 = v1 + v 2 = L(v1 ) + L(v 2 ) However, L(a1v1 ) = a1v1 = a1v1 = a1L(v1 ) ≠ a1L(v1 ) Then L is a nonlinear operator because homogeneity fails. © 2003 by CRC Press LLC

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• For F-vector spaces V and W, let V be F n and W be F n-1. Examine L : V → W, the operator that truncates the last element of the n-tuple in V ; that is, L((v1 , v 2 , K, v n −1 , v n )) = (v1 , v 2 , K, v n −1) Such an operator is linear. The null space (kernel) of a linear operator L:V → W is the set

{

}

ker L = v ∈ V suchthat L(v ) = 0

(1.9)

Equation (1.9) defines a vector space. In fact, ker L is a subspace of V. The mapping L is injective if and only if ker L = 0; that is, the only solution in the right member of (1.9) is the trivial solution. In this case, L is also called monic. The image of a linear operator L:V → W is the set

{

}

im L = w ∈ W suchthat L(v ) = w for some v ∈V

(1.10)

Clearly, im L is a subspace of W, and L is surjective if and only if im L is all of W. In this case, L is also called epic. A method of relating specific properties of linear mappings is the exact sequence. Consider a sequence of linear mappings L˜

L

…V → W → U → …

(1.11)

This sequence is said to be exact at W if im L = ker L˜ . A sequence is called exact if it is exact at each vector space in the sequence. Examine the following special cases: L

0 → V → W

(1.12)

~ L

W → U → 0

(1.13)

Sequence (1.12) is exact if and only if L is monic, whereas (1.13) is exact if and only if L˜ is epic. Further, let L : V → W be a linear mapping between finite-dimensional vector spaces. The rank of L, ρ(L), is the dimension of the image of L. In such a case ρ( L) + dim ( ker L) = dim V

(1.14)

Linear operators commonly are represented by matrices. It is quite natural to interchange these two ideas, because a matrix with respect to the standard bases is indistinguishable from the linear operator it represents. However, insight may be gained by examining these ideas separately. For V and W n- and m-dimensional vector spaces over F, respectively, consider a linear operator L : V → W. Moreover, let {v1, v2, …, vn} and {w1, w2, …, wm} be respective bases for V and W. Then L : V → W can be represented uniquely by the matrix M ∈ F m×n where m11   m21 M=  M  m  m1 © 2003 by CRC Press LLC

m12

L

m22

L

M

O

mm2

L

m1n   m2n   M   mmn 

(1.15)

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The ith column of M is the representation of L(vi) with respect to {w1, w2, …, wm}. Element mij ∈ F of (1.15) occurs in row i and column j. Matrices have a number of properties. A matrix is said to be square if m = n. The main diagonal of a square matrix consists of the elements mii. If mij = 0 for all i > j (i < j) a square matrix is said to be upper (lower) triangular. A square matrix with mij = 0 for all i ≠ j is diagonal. Additionally, if all mii = 1, a diagonal M is an identity matrix. A row vector (column vector) is a special case in which m = 1 (n = 1). Also, m = n = 1 results essentially in a scalar. Matrices arise naturally as a means to represent sets of simultaneous linear equations. For example, in the case of Kirchhoff equations, a later section on graph theory shows how incidence, circuit, and cut matrices arise. Or consider a π network having node voltages vi, i = 1, 2 and current sources ii, i = 1, 2 connected across the resistors Ri, i = 1, 2 in the two legs of the π. The bridge resistor is R3. Thus, the unknown node voltages can be expressed in terms of the known source currents in the manner

(R1 + R3 ) v

1

−

1 v =i R3 2 1

(1.16)

(R2 + R3 ) v

−

1 v =i R3 1 2

(1.17)

R1R3

R2 R3

2

If the voltages, vi , and the currents, ii , are placed into a voltage vector v ∈ R2 and current vector i ∈ R2, respectively, then (1.16) and (1.17) may be rewritten in matrix form as  ( R1 + R3 )  i1   R1R3  = i2    − 1  R3 

   v1     (R2 + R3 )  v 2  R2 R3  −

1 R3

(1.18)

A conductance matrix G may then be defined so that i = Gv, a concise representation of the original pair of circuit equations.

1.4 Matrix Operations Vector addition in F n was defined previously as element-wise scalar addition. Similarly, two matrices M and N, both in F m×n, can be added (subtracted) to form the resultant matrix P ∈F m×n by mij ± nij = pij

i = 1, 2, ..., m

j = 1, 2, ..., n

(1.19)

Matrix addition, thus, is defined using addition in the field over which the matrix lies. Accordingly, the matrix, each of whose entries is 0 ∈ F, is an additive identity for the family. One can set up additive inverses along similar lines, which, of course, turn out to be the matrices each of whose elements is the negative of that of the original matrix. Recall how scalar multiplication was defined in the example of the vector space of n-tuples. Scalar multiplication can also be defined between a field element a ∈ F and a matrix M ∈ F m×n in such a way that the product aM is calculated element-wise: aM = P ⇔ amij = pij

© 2003 by CRC Press LLC

i = 1, 2,..., m j = 1, 2,..., n

(1.20)

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Examples 4 M=  2

3  1

3 − 3 6  =  1 + 6  3

0 

7

(F = R):  4 + 2 • M +N =P=   2 + 1

4 − 2 3 + 3 2  =  • M − N = P˜ =   2 − 1 1 − 6  1 (−0.5)4 • aM = Pˆ =   −0.5 2 ) (

(−0.5)3

2 N=  1

−3  6 

a = − 0.5

6 

−5

−2  = 

(−0.5)1 −1

−1.5  −0.5

To multiply two matrices M and N to form the product MN requires that the number of columns of M equal the number of rows of N. In this case the matrices are said to be conformable. Although vector multiplication cannot be defined here because of this constraint, Chapter 2 examines this operation in detail using the tensor product. The focus here is on matrix multiplication. The resulting matrix will have its number of rows equal to the number of rows in M and its number of columns equal to the number of columns of N. Thus, for M ∈ F m×n and N ∈ F n×p, MN = P ∈ F m×p. Elements in the resulting matrix P may be determined by n

Pij =

∑m n

(1.21)

ik kj

k =1

Matrix multiplication involves one row and one column at a time. To compute the pij term in P, choose the ith row of M and the jth column of N. Multiply each element in the row vector by the corresponding element in the column vector and sum the result. Notice that in general, matrix multiplication is not commutative, and the matrices in the reverse order may not even be conformable. Matrix multiplication is, however, associative and distributive with respect to matrix addition. Under certain conditions, the field F of scalars, the set of matrices over F, and these three operations combine to form an algebra. Chapter 2 examines algebras in greater detail. Examples

(F = R):

4 M=   2

3  1

1 N=   2

3 4

5  6

10 24 38 • MN = P = 

  4 10 16

To find p11, take the first row of M, [4 3], and the first column of N, 1 , and evaluate (1.21): 2 4(1) + 3(2) = 10. Continue for all i and j. • NM does not exist because that product is not comformable. • Any matrix M ∈ F m×n multiplied by an identity matrix I ∈ F n×n such that MI ∈ F m×n results in the original matrix M. Similarly, IM = M for I an m × m identity matrix over F. It is common to interpret I as an identity matrix of appropriate size, without explicitly denoting the number of its rows and columns.

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The transpose M T ∈ F n×m of a matrix M ∈ F m×n is found by interchanging the rows and columns. The first column of M becomes the first row of M T, the second column of M becomes the second row of M T, and so on. The notations Mt and M′ are used also. If M = M T the matrix is called symmetric. Note that two matrices M, N ∈ F m×n are equal if and only if all respective elements are equal: mij = nij for all i, j. The Hermitian transpose M ∗ ∈ C n× m of M ∈ C m×n is also termed the complex conjugate transpose. To compute M ∗, form M T and take the complex conjugate of every element in M T. The following properties also hold for matrix transposition for all M, N ∈ F m×n, P ∈ F n ×p, and a ∈ F: (M T)T = M, (M + N)T = M T + N T, (aM)T = aM T, and (MP)T = P TM T. Examples j M= 4

(F = C ):  j • M T =  1 − j

4  

2 + j3



 −j • M * =  1 + j

4  

2 − j3



1− j   2 + j3

1.5 Determinant, Inverse, and Rank Consider square matrices of the form [m11] ∈ F 1 × 1. For these matrices, define the determinant as m11 and establish the notation det([m11]) for this construction. This definition can be used to establish the meaning of det(M), often denoted |M|, for M ∈ F 2 × 2. Consider m11 M= m21

m12   m22 

(1.22)

The minor of mij is defined to be the determinant of the submatrix which results from the removal of row i and column j. Thus, the minors of m11, m12, m21, and m22 are m22, m21, m12, and m11, respectively. To calculate the determinant of this M, (1) choose any row i (or column j), (2) multiply each element mik (or mkj) in that row (or column) by its minor and by (–1)i+k (or (–1)k+j), and (3) add these results. Note that the product of the minor with the sign (–1)i+k (or (–1)k+j) is called the cofactor of the element in question. If row 1 is chosen, the determinant of M is found to be m11 (+m22) + m12 (– m21), a wellknown result. The determinant of 2 × 2 matrices is relatively easy to remember: multiply the two elements along the main diagonal and subtract the product of the other two elements. Note that it makes no difference which row or column is chosen in step 1. A similar procedure is followed for larger matrices. Consider

Expanding about column 1 produces

© 2003 by CRC Press LLC

m11

m12

m13

det( M ) = m21

m22

m23

m31

m32

m33

(1.23)

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det( M ) = m11

m22

m23

m32

m33

− m21

m12

m13

m32

m33

+ m31

m12

m13

m22

m23

= m11 (m22m33 − m23m32 ) − m21 (m12m33 − m13m32 ) + m31 (m12m23 − m13m22 ) = m11m22m33 + m12m23m31 + m13m21m32 − m13m22m31 − m11m23m32 − m12m21m33

(1.24)

(1.25)

(1.26)

An identical result may be achieved by repeating the first two columns next to the original matrix: m11

m12

m13

m11

m12

m21

m22

m23

m21

m22

m31

m32

m33

m31

m32

(1.27)

Then, form the first three products of (1.26) by starting at the upper left corner of (1.27) with m11, forming a diagonal to the right, and then repeating with m12 and m13. The last three products are subtracted in (1.26) and are formed by starting in the upper right corner of (1.27) with m12 and taking a diagonal to the left, repeating for m11 and m13. Note the similarity to the 2 × 2 case. Unfortunately, such simple schemes fail above the 3 × 3 case. Determinants of n × n matrices for n > 3 are computed in a similar vein. As in the earlier cases the determinant of an n × n matrix may be expressed in terms of the determinants of (n – 1) × (n –1) submatrices; this is termed Laplace’s expansion. To expand along row i or column j in M ∈ F n ×n, write det( M ) =

n

∑

n

˜ ik = mikm

k =1

∑ m m˜ kj

(1.28)

kj

k =1

˜ ik (m ˜ ) are cofactors formed by deleting the ith (kth) row where the mik (mkj) are elements of M. The m kj and the kth (jth) column of M, forming the determinant of the (n – 1) × (n – 1) resulting submatrix, and multiplying by (–1)i+k ((–1)k+j). Notice that minors and their corresponding cofactors are related by ±1. Examples 0  M = 3  2

(F = R):

1

2  5  6

4 3

• Expanding about row 1 produces det( M ) = 0

4

5

3

6

−1

3

5

2

6

+2

3

4

2

3

= − (18 − 10) + 2(9 − 8) = − 6

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• Expanding about column 2 yields det( M ) = −1

3

5

2

6

+4

0

2

2

6

−3

0

2

3

5

= − (18 − 10) + 4(0 − 4) − 3(0 − 6) = − 6 • Repeating the first two columns to form (1.27) gives 0

1

2

0

1

3

4

5

3

4

2

3

6

2

3

Taking the appropriate products, 0 ⋅ 4 ⋅6 + 1⋅5 ⋅ 2 + 2 ⋅3 ⋅3 − 1⋅3 ⋅6 − 0 ⋅5 ⋅3 − 2 ⋅ 4 ⋅ 2 results in –6 as the determinant of M. • Any square matrix with a zero row and/or zero column will have zero determinant. Likewise, any square matrix with two or more identical rows and/or two or more identical columns will have determinant equal to zero. Determinants satisfy many interesting relationships. For any n × n matrix, the determinant may be expressed in terms of determinants of (n – 1) × (n –1) matrices or first-order minors. In turn, determinants of (n – 1) × (n –1) matrices may be expressed in terms of determinants of (n – 2) × (n – 2) matrices or second-order minors, etc. Also, the determinant of the product of two square matrices is equal to the product of the determinants: det( MN ) = det ( M ) det(N )

(1.29)

For any M ∈ F n × n such that |M| ≠ 0, a unique inverse M –1 ∈ F n× n satisfies MM −1 = M −1M = I

(1.30)

For (1.29) one may observe the special case in which N = M –1, then (det(M))–1 = det(M –1). The inverse M –1 may be expressed using determinants and cofactors in the following manner. Form the matrix of cofactors ˜ 11 m  ˜ m ˜ =  21 M  M  m  ˜ n1

˜ 12 m

L

˜ 22 m

L

M

O

˜ n2 m

L

˜ 1n  m  ˜ 2n  m  M   ˜ nn  m

(1.31)

The transpose of (1.31) is referred to as the adjoint matrix or adj(M). Then, M −1 =

© 2003 by CRC Press LLC

˜ T adj( M ) M = M M

(1.32)

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Examples • Choose M of the previous set of examples. The cofactor matrix is 9  0  − 3

−8 −4 6

1   2  − 3

Because |M| = –6, M –1 is − 32   34  − 1  6

0 2 3

− 13

  −1  1 2 1 2

Note that (1.32) is satisfied. 1 −1 − 12   32 3 −1 adj( M ) =  

  M =  −4 −2 3 2  1 

In the 2 × 2 case, this method reduces to interchanging the elements on the main diagonal, changing the sign on the remaining elements, and dividing by the determinant. • Consider the matrix equation in (1.18). Because det(G) ≠ 0, whenever the resistances are nonzero, with R1 and R2 having the same sign, the node voltages may be determined in terms of the current sources by multiplying on the left of both members of the equation using G–1. Then G–1 i = v. 2 • M =  4

The rank of a matrix M, ρ(M), is the number of linearly independent columns of M over F, or using other terminology, the dimension of the image of M. For M ∈ F m×n the number of linearly independent rows and columns is the same, and is less than or equal to the minimum of m and n. If ρ(M) = n, M is of full column rank; similarly, if ρ(M) = m, M is of full row rank. A square matrix with all rows (and all columns) linearly independent is said to be nonsingular. In this case, det(M) ≠ 0. The rank of M also may be found from the size of the largest square submatrix with a nonzero determinant. A full-rank matrix has a full-size minor with a nonzero determinant.Consider the matrix equation in (1.18). Because det(G) ≠ 0, whenever the resistances are nonzero, with R1 and R2 having the same sign, the node voltages may be determined in terms of the current sources by multiplying on the left of both members of the equation using G –1. Then G –1i = v. The null space (kernel) of a matrix M ∈ F m×n is the set

{

}

ker M = v ∈F n such that Mv = 0

(1.33)

Over F, ker M is a vector space with dimension defined as the nullity of M, v(M). The fundamental theorem of linear equations relates the rank and nullity of a matrix M ∈ F m×n by ρ( M ) + v ( M ) = n If ρ(M) < n, then M has a nontrivial null space. Examples 0 • M =  0 © 2003 by CRC Press LLC

1 

 0

(1.34)

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The rank M is 1 because only one linearly independent column of M is found. To examine the null space of M, solve Mv = 0. Any element in ker M is of the form f 1 for f1 ∈ F. Therefore, v(M) = 1. 0

1 4 5 2    • M = 2 5 7 1    3 6 9 0    The rank of M is 2 and the nullity is 2.

1.6 Basis Transformations This section describes a change of basis as a linear operator. Because the choice of basis affects the matrix of a linear operator, it would be most useful if such a basis change could be understood within the context of matrix operations. Thus, the new matrix could be determined from the old matrix by matrix operations. This is indeed possible. This question is examined in two phases. In the first phase the linear operator maps from a vector space to itself. Then a basis change will be called a similarity transformation. In the second phase, the linear operator maps from one vector space to another, which is not necessarily the same as the first. Then a basis change will be called an equivalence transformation. Of course, the first situation is a special case of the second, but it is customary to make the distinction and to recognize the different terminologies. Philosophically, a fascinating special situation exists in which the second vector space, which receives the result of the operation, is an identical copy of the first vector space, from which the operation proceeds. However, in order to avoid confusion, this section does not delve into such issues. For the first phase of the discussion, consider a linear operator that maps a vector space into itself, such as L : V → V, where V is n-dimensional. Once a basis is chosen in V, L will have a unique matrix representation. Choose {v1 , v 2 , ..., v n } and {v1 , v 2 , ..., v n } as two such bases. A matrix M ∈ F n ×n may be determined using the first basis, whereas another matrix M ∈F n × n will result in the latter choice. Accord­ ing to the discussion following (1.15), the ith column of M is the representation of L(vi) with respect to {v1 , v 2 ,..., v n }, and the ith column of M is the representation of L(v i ) with respect to {v1 , v 2 , ..., v n }. As in (1.4), any basis element vi has a unique representation in terms of the basis {v1 , v 2 , ..., v n }. Define a matrix P ∈ F n ×n using the ith column as this representation. Likewise, Q ∈ F nxn may have as its ith column the unique representation of v i with respect to {v1 , v 2 ,..., v n } . Either represents a basis change which is a linear operator. By construction, both P and Q are nonsingular. Such matrices and linear operators are some­ times called basis transformations. Notice that P = Q –1. If two matrices M and M represent the same linear operator L, they must somehow carry essentially the same information. Indeed, a relationship between M and M may be established. Consider av , aw , av , aw ∈F n such that Mav = aw and Mav = aw . Here, av denotes the representation of v with respect to the basis vi , av denotes the representation of v with respect to the basis v i and so forth. In order to involve P and Q in these equations it is possible to make use of a sketch: M

av P

Q

aw P

Q a−w

a−v M

In this sketch, a vector at a given corner can be multiplied by a matrix on an arrow leaving the corner and set equal to the vector that appears at the corner at which that arrow arrives. Thus, for example, aw = Mav may be deduced from the top edge of the sketch. It is interesting to perform “chases” around such sketches. By way of illustration, consider the lower right corner. Progress around the sketch counterclockwise so as © 2003 by CRC Press LLC

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to reach the lower left corner and set the result equal to that obtained by progressing clockwise to the lower left corner. In equations this is carried out as follows: aw = Paw = PMav = PMQav = Mav

(1.35)

Inasmuch as av ∈F n is arbitrary it follows that M = PMP −1

(1.36)

Sketches that have this type of property, namely the same result when the sketch is traversed from a starting corner to an finishing corner by two paths, are said to be commutative. It is perhaps more traditional to show the vector space F n instead of the vectors at the corners. Thus, the sketch would be called a commutative diagram of vector spaces and linear operators. M and M are said to be similar because a nonsingular matrix P ∈F n×n is such that (1.36) is true. The matrix P is then called a similarity transformation. Note that all matrix representations associated with the same linear operator, from a vector space to itself, are similar. Certain choices of bases lead to special forms for the matrices of the operator, as are apparent in the following examples. Examples • Choose L:R2 → R2 as the linear operator that rotates a vector by 90˚. Pick {v1, v2} as the natural basis {[1 0]T, [0 1]T} and {v 1 , v 2 } as {[1 1]T, [1 0]T}. Then,

[

0 v2   1 

[

−1 v2    0

[

 1 v2     −2

[

 1 v2   −1

−1  0

 1 M=  −2

L(v1 ) = v1 L(v 2 ) = v1 L(v1 ) = v1 L(v 2 ) = v 1

] ] ]

]

so that 0 M=  1

1  −1

To find the similarity transformation P, determine the representations of the basis vectors vi in terms of the basis {v1 , v 2 }. Then 0 P=  1

1  −1

1 P=  1

1  0

so that PMP –1 = M. • Suppose that M ∈ F n× n is a representation of L : V → V. Assume a v ∈ F n exists such that the vectors {v, Mv, …, M n – 1v} are linearly independent. Thus, these n vectors can be chosen as an alternate basis. (Section 1.7 discusses the characteristic equation of a matrix M.) Using the Cayley–Hamilton theorem, which states that every matrix satisfies its own characteristics equation, it is always possible to write M n v as a linear combination of these alternate basis vectors © 2003 by CRC Press LLC

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−α nv − α n−1Mv − L − α1M n−1v for αi ∈ F. The matrix representation of L with respect to the alternate basis given by this set of linearly independent vectors is 0  1  0 M=   M  0  0

0

L

0

0

L

0

1

L

0

M

O

M

0

L

0

0

L

1

− αn   − αn − 1   − αn − 2    M   − α2   − α 2 

which is the transpose of what is known as the companion form. For the second phase of the discussion, select a pair of bases, one for the vector space V and one for the vector space W, and construct the resulting matrix representation M of L:V → W. Another choice of bases exists for V and W, with the property that the resulting matrix M representing L is of the form I  0

0  0

(1.37)

where I is ρ(M) × ρ(M). Such a matrix is said to be in normal form. It is possible to transform M into M with the assistance of three types of transformations which are called elementary: (1) interchange any two rows or any two columns, (2) scale any row or column by a nonzero element in F, and (3) add any F-multiple of any row (column) to any other row (column). It is apparent that each of the three transformations involving rows may be accomplished by multiplying M on the left by a nonsingular matrix. Column operations require a corresponding multiplication on the right. The secret to under­ standing elementary transformations is to recognize that each of them will carry one basis into another. Not as easy to see, but equally true, is that any transformation that carries one basis into another basis must be a product of such elementary transformations. The elementary column transformations are interpreted as changing the basis in the vector space from which the operator takes vectors, whereas the elementary row transformations correspond to changing the basis in the vector space into which the operator places its result. It stands to reason that a simultaneous adjustment of both sets of basis vectors could lead to some quite special forms for the matrices of an operator. Of course, a great deal of linear algebra and its applications is concerned with just such constructions and forms. Space does not permit a complete treatment here. If a matrix M has been transformed into normal form, certain types of key information become available. For example, one knows the rank of M because ρ(M) is the number of rows and columns of the identity in (1.37). Perhaps more importantly, the normal form is easily factored in a fundamental way, and so such a construction is a natural means to construct two factors of minimal rank for a given matrix. The reader is cautioned, however, to be aware that computational linear algebra is quite a different subject than theoretical linear algebra. One common saying is that “if an algorithm is straightforward, then it is not numerically desirable”. This may be an exaggeration, but it is well to recognize the implications of finite precision on the computer. Space limitations prevent addressing numerical issues. Many other thoughts can be expressed in terms of elementary basis transformations. By way of illustration, elementary basis transformations offer an alternative in finding the inverse of a matrix. For a nonsingular matrix M ∈ F n ×n, append to M an n × n identity I to form the n × 2n matrix

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17

Linear Operators and Matrices

ˆ = [M M

]

(1.38)

Perform elementary row transformations on (1.38) to transform M into normal form. Then M –1 will appear in the last n columns of the transformed matrix. Examples 2 M=  4

(F = R) :

1  3

• Transform M into normal form. The process can be carried out in many ways. For instance, begin by scaling row 1 by 12 ,  12 L1 M =  0

  3 

1 1 =  3 4

0 2  1 4

1 2

Clear the first element in row 2 by

L2 L1

0 1   1 4

1 =   −4

  1

 1 =  3 0 1 2

1 2

Finally, perform a column operation to produce M :  1   1 0

1 L2 L1MR1 =   0

1 2

− 12  1 =  1  0

0  1

The rank of M is 2. ˆ and transform M into normal form by the following • Recall M –1 from previous examples. Form M row operations: 1 ˆ =  2 L1 M 0

1 ˆ =  L2 L1M −4 ˆ = 1 L3 L2 L1M   0

0 2  1 4 0 1  1 4 − 12  1  1  0

1

1

3

0

0 1 =  1 4

1 2

1 2

3

0

1 2

1 2

1

−2

0 = 1

1  0

0 1 =  1 0

1 2

1 2

3

0

0  1

1 2

1 2

1

−2 0

3 2

1

−2

0  1 − 12   1 

1.7 Characteristics: Eigenvalues, Eigenvector s, and Singular Values A matrix has certain characteristics associated with it. Of these, characteristic values or eigenvalues may be determined through the use of matrix pencils. In general a matrix pencil may be formed from two matrices M and N ∈ F m ×n and an indeterminate λ in the manner

[ λN − M ] ∈F[λ]

m×n

© 2003 by CRC Press LLC

(1.39)

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In determining eigenvalues of a square matrix M ∈ F n ×n one assumes the special case in which N = I ∈F n×n. Assume that M is a square matrix over the complex numbers. Then, λ ∈C is called an eigenvalue of M if some nonzero vector v ∈ C n exists such that Mv = λv

(1.40)

Any such v ≠ 0 satisfying (1.40) is said to be an eigenvector of M associated with λ. It is easy to see that (1.40) can be rewritten as

(λI − M )v = 0

(1.41)

Because (1.41) is a set of n linear homogeneous equations, a nontrivial solution (v ≠ 0) exists if and only if ∆(λ ) = det(λI − M ) = 0

(1.42)

In other words, (λI – M) is singular. Therefore, λ is an eigenvalue of M if and only if it is a solution of (1.42). The polynomial ∆(λ) is the characteristic polynomial and ∆(λ) = 0 is the characteristic equation. Moreover, every n × n matrix has n eigenvalues that may be real, complex or both, where complex eigenvalues occur in complex-conjugate pairs. If two or more eigenvalues are equal they are said to be repeated (not distinct). It is interesting to observe that although eigenvalues are unique, eigenvectors are not. Indeed, an eigenvector can be multiplied by any nonzero element of C and still maintain its essential features. Sometimes this lack of uniqueness is resolved by selecting unit length for the eigenvectors with the aid of a suitable norm. Recall that matrices representing the same operator are similar. One may question if these matrices indeed contain the same characteristic information. To answer this question, examine

(

)

(

det(λI − M ) = det λPP −1 − PMP −1 = det P(λI − M )P −1

( )

)

= det( P ) det(λI − M ) det P −1 = det(λI − M )

(1.43) (1.44)

From (1.44) one may deduce that similar matrices have the same eigenvalues because their characteristic polynomials are equal. For every square matrix M with distinct eigenvalues, a similar matrix M is diagonal. In particular, the eigenvalues of M, and hence M , appear along the main diagonal. Let λ1, λ2, …, λn be the eigenvalues (all distinct) of M and let v1, v2, …, vn be corresponding eigenvectors. Then, the vectors {v1, v2, …, vn} are linearly independent over C. Choose P –1 = Q = [v1 v2 … vn] as the modal matrix. Because Mvi = λivi , M = PMP –1 as before. For matrices with repeated eigenvalues, a similar approach may be followed wherein M is block diagonal, which means that matrices occur along the diagonal with zeros everywhere else. Each matrix along the diagonal is associated with an eigenvalue and takes a specific form depending upon the characteristics of the matrix itself. The modal matrix consists of generalized eigenvectors, of which the aforementioned eigenvector is a special case; thus the modal matrix is nonsingular. The matrix M is the Jordan canonical form. Space limitations preclude a detailed analysis of such topics here; the reader is directed to Chen (1984) for further development. Examples

(F = C ):

© 2003 by CRC Press LLC

1 4   M= 2 3

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• The characteristic polynomial is ∆(λ) = (λ – 1) (λ – 3) – 8 = (λ – 5) (λ + 1). The eigenvalues are λ1 = 5, λ2 = –1. To find the associated eigenvectors recall that for each λi , (λi I – M) is singular, and write (1.41) 4

(λ1I − M )v1 = 

−2

− 4  v11 

0   =  2 v12  0

−2 − 4 v 21  0  =  −2 − 4 v 22  0

(λ 2I − M )v 2 = 

Then, v11 = v12 and v21 = –2v22 so that v1 = [1 1]T and v2 = [–2 1]T are eigenvectors associated with λ1 and λ2, respectively. • Because the eigenvalues of M are distinct, M may be diagonalized. For verification, choose P –1 = [v1 v2]. Then M = PMP −1 =

=

1  1 2 1 4  1 − 2     3 −1 1 2 3 1 1      1 15 0  5  = 3 0 − 3 0   

?1 = −1  0

0 

0 



? 2 

In general a matrix M ∈ F m× n or rank r can be written in terms of its singular-value decomposition (SVD), M = U ∑ V *

(1.45)

For any M, unitary matrices U and V of dimension m × m and n × n, respectively, form the decomposition; that is UU* = U*U = I and VV* = V*V = I. The matrix ∑ ∈ F m × n of the form ∑ r  0

0



(1.46)

0 

for ∑r , ∈ F r × r, a diagonal matrix represented by σ1  0  M  0 

0 L 0 



σ2 L 0 

   0 L σ r 

M O M

(1.47)

The elements σi, called singular values, are related by σ1 ≥ σ2 ≥ L ≥ σr > 0, and the columns of U (V) are referred to as left (right) singular vectors. Although the unitary matrices U and V are not unique for a given M, the singular values are unique. Singular-value decomposition is useful in the numerical calculation of rank. After performing a SVD, the size of the matrix ∑r may be decided. Additionally, the generalized inverse of a matrix M may be found by

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∑ r−1

M† = V 

0 

0

U* 0 

(1.48)

It can be verified easily that MM† M = M and M † MM † = M †. In the special case in which M is square and nonsingular, M † = M −1 = V ∑ −1 U *

(1.49)

1.8 On Linear Systems Consider a set of n simultaneous algebraic equations, in m unknowns, written in the customary matrix form w = Mv where w1  m11 m12    w 2  m21 m22  =  M  M M    w  m  n   n1 mn 2

L m1m  v1 

 



L m2m  v 2  O L

   mnm 

M

  M    v   m

(1.50)

In the context of the foregoing discussion, (1.50) represents the action of a linear operator. If the left member is a given vector, in the usual manner, then a first basic issue concerns whether the vector represented by the left member is in the image of the operator or not. If it is in the image, the equation has at least one solution; otherwise the equation has no solution. A second basic issue concerns the kernel of the operator. If the kernel contains only the zero vector, then the equation has at most one solution; otherwise more than one solution can occur, provided that at least one solution exists. When one thinks of a set of simultaneous equations as a “system” of equations, the intuitive transition to the idea of a linear system is quite natural. In this case the vector in the left member becomes the input to the system, and the solution to (1.50), when it exists and is unique, is the output of the system. Other than being a description in terms of inputs and outputs, as above, linear systems may also be described in terms of sets of other types of equations, such as differential equations or difference equations. When that is the situation, the familiar notion of initial condition becomes an instance of the idea of state, and one must examine the intertwining of states and inputs to give outputs. Then, the idea of (1.50), when each input yields a unique output, is said to define a system function. If the differential (difference) equations are linear and have constant coefficients, the possibility exists of describing the system in terms of transforms, for example, in the s-domain or z-domain. This leads to fascinating new interpretations of the ideas of the foregoing sections, this time, for example, over fields of rational functions. Colloquially, such functions are best known as transfer functions. Associated with systems described in the time domain, s-domain, or z-domain some characteristics of the system also aid in analysis techniques. Among the most basic of these are the entities termed poles and zeros, which have been linked to the various concepts of system stability. Both poles and zeros may be associated with matrices of transfer functions, and with the original differential or difference equations themselves. A complete and in-depth treatment of the myriad meanings of poles and zeros is a challenging undertaking, particularly in matrix cases. For a recent survey of the ideas, see Schrader and Sain (1989). However, a great many of the definitions involve such concepts as rank, pencils, eigenvalues, eigenvectors, special matrix forms, vector spaces, and modules — the very ideas sketches out in the sections preceding. One very commonly known idea for representing solutions to (1.50) is Cramer’s rule. When m = n, and when M has an inverse, the use of Cramer’s rule expresses each unknown variable individually by using a ratio of determinants. Choose the ith unknown vi . Define the determinant Mi as the determinant of a matrix formed by replacing column i in M with w. Then, © 2003 by CRC Press LLC

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vi =

M i det ( M )

(1.51)

It turns out that this very interesting idea makes fundamental use of the notion of multiplying vectors, which is not part of the axiomatic framework of the vector space. The reader may want to reflect further on this observation, with respect to the foregoing treatment of determinants. When the framework of vector spaces is expanded to include vector multiplication, as in the case of determinants, one gets to the technical subject of algebras. The next chapter returns to this concept. The concepts presented previously allow for more detailed considerations in the solution of circuit and filter problems, using various approaches outlined in the remainder of this text. The following chapter provides for the multiplication of vectors by means of the foundational idea of bilinear operators and matrices. The next chapters on transforms — Fourier, z, and Laplace — provide the tools for analysis by allowing a set of differential or difference equations describing a circuit to be written as a system of linear algebraic equations. Moreover, each transform itself can be viewed as a linear operator, and thus becomes a prime example of the ideas of this chapter. The remaining chapters focus on graph-theoretical approaches to the solution of systems of algebraic equations. From this vantage point, then, one can see the entire Section I in the context of linear operators, their addition and multiplication. A brief treatment cannot deal with all the interesting questions and answers associated with linear operators and matrices. For a more detailed treatment of these standard concepts, see any basic algebra text, for example, Greub (1967).

References C.-T. Chen, Linear System Theory and Design, New York: GBS College Publishing, 1984. W. H. Greub, Linear Algebra, New York: Springer-Verlag, 1967. C. B. Schrader and M. K. Sain, “Research on system zeros: a survey,” Int. J. Control, Vol. 50, No. 4, pp. 1407–1433, Oct. 1989.

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2 Bilinear Operators and Matrices

Michael K. Sain University of Notre Dame

Cheryl B. Schrader The University of Texas

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11

Introduction Algebras Bilinear Operators Tensor Product Basis Tensors Multiple Products Determinants Skew Symmetric Products Solving Linear Equations Symmetric Products Summary

2.1 Introduction The key player in Chapter 1 was the F-vector space V, together with its associated notion of bases, when they exist, and linear operators taking one vector to another. The idea of basis is, of course, quite central to the applications because it permits a vector v in V to be represented by a list of scalars from F. Such lists of scalars are the quantities with which one computes. No doubt the idea of an F-vector space V is the most common and widely encountered notion in applied linear algebra. It is typically visualized, on the one hand, by long lists of axioms, most of which seem quite reasonable, but none of which is particularly exciting, and on the other hand by images of classical addition of force vectors, velocity vectors, and so forth. The notion seems to do no harm, and helps one to keep his or her assumptions straight. As such it is accepted by most engineers as a plausible background for their work, even if the ideas of matrix algebra are more immediately useful. Perhaps some of the least appreciated but most crucial of the vector space axioms are the four governing the scalar multiplication of vectors. These link the abelian group of vectors to the field of scalars. Along with the familiar distributive covenants, these four agreements intertwine the vectors with the scalars in much the same way that the marriage vows bring about the union of man and woman. This section brings forth a new addition to the marriage. As useful as it is, the notion of an F-vector space V fails to provide for one of the most important ideas in the applications — the concept of multiplication of vectors. In a vector space one can add vectors and multiply vectors by scalars, but one cannot multiply vectors by vectors. Yet there are numerous situations in which one faces exactly these operations. Consider, for instance, the cross and dot products from field theory. Even in the case of matrices, the ubiquitous and crucial matrix multiplication is available, when it is defined. The key to the missing element in the discussion lies in the terminology for matrix operations, which will be familiar to the reader as the matrix algebra. What must occur in order for vector-to-vector multiplication to be available is for the vector space to be extended into an algebra.

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Unfortunately, the word “algebra” carries a rather imprecise meaning from the most elementary and early exposures from which it came to signify the collection of operations done in arithmetic, at the time when the operations are generalized to include symbols or literals such as a, b, and c or x, y, and z. Such a notion generally corresponds closely with the idea of a field, F, as defined in Chapter 1, and is not much off the target for an environment of scalars. It may, however, come as a bit of a surprise to the reader that algebra is a technical term, in the same spirit as fields, vector spaces, rings, etc. Therefore, if one is to have available a notion of multiplication of vectors, then it is appropriate to introduce the precise notion of an algebra, which captures the desired idea in an axiomatic sense.

2.2 Algebras Chapter 1 mentioned that the integers I and the polynomials F[s] in s with coefficients in a field F were instances of a ring. In this section it is necessary to carry the concept of ring beyond the example stage. Of course, a long list of axioms could be provided, but it may be more direct just to cite the changes necessary to the field axioms already provided in section 1.2. To be precise, the axioms of a commutative ring differ from the axioms of a field only by the removal of the multiplicative inverse. Intuitively, this means that one cannot always divide, even if the element in question is nonzero. Many important commutative rings are found in the applications; however, this chapter is centered on rings, wherein one more axiom is removed — the commutativity of multiplication. The ring of n × n matrices with elements from a field is a classic and familiar example of such a definition. It may be remarked that in some references a distinction is made between rings and rings with identity, the latter having a multiplicative identity and the former not being so equipped. This treatment has no need for such a distinction, and hereafter the term “ring” is understood to mean ring with identity, or, as described above, a field with the specified two axioms removed. It is probably true that the field is the most comfortable of axiomatic systems for most persons because it corresponds to the earliest and most persistent of calculation notions. However, it is also true that the ring has an intuitive and immediate understanding as well, which can be expressed in terms of the wellknown phrase “playing with one arm behind one’s back”. Indeed, each time an axiom is removed, it is similar to removing one of the options in a game. This adds to the challenge of a game, and leads to all sorts of new strategies. Such is the case for algebras, as is clear from the next definition. What follows is not the most general of possible definitions, but probably that which is most common. An algebra A is an F-vector space A which is equipped with a multiplication a1a2 of vectors a1 and a2 in such a manner that it is also a ring. First, addition in the ring is simply addition of vectors in the vector space. Second, a special relationship exists between multiplication of vectors and scalar multipli­ cation in the vector space. If a1 and a2 are vectors in A, and if f is a scalar in F, then the following identity holds: f (a1a2 ) = ( fa1 )a2 = a1 ( fa2 )

(2.1)

Note that the order of a1 and a2 does not change in the above equalities. This must be true because no axiom of commutativity exits for multiplication. The urge to define a symbol for vector multiplication is resisted here so as to keep things as simple as possible. In the same way the notation for scalar multiplication, as introduced in Chapter 1, is suppressed here in the interest of simplicity. Thus, the scalar multiplication can be associated either with the vector product, which lies in A, or with one or other of the vector factors. This is exactly the familiar situation with the matrix algebra. Hidden in the definition of the algebra A above is the precise detail arising from the statement that A is a ring. Associated with that detail is the nature of the vector multiplication represented above with the juxtaposition a1a2. Because all readers are familiar with several notions of vector multiplication, the question arises as to just what constitutes such a multiplication. It turns out that a precise notion for multiplication can be found in the idea of a bilinear operator. Thus, an alternative description of

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Section 2.3 is that of vector spaces equipped with vector multiplication. Moreover, one is tempted to inquire whether a vector multiplication exists that is so general in nature that all the other vector multiplications can be derived from it. In fact, this is the case, and the following section sets the stage for introducing such a multiplication.

2.3 Bilinear Operators Suppose that there are three F- vector spaces: U, V, and W. Recall that U × V is the Cartesian product of U with V, and denotes the set of all ordered pairs, the first from U and the second from V. Now, consider a mapping b from U × V into W. For brevity of notation, this can be written b: U × V → W. The mapping b is a bilinear operator if it satisfies the pair of conditions b ( f1u1 + f 2u 2 , v ) = f1b (u1, v ) + f 2b (u 2 , v )

(2.2)

b (u, f1v1 + f 2v 2 ) = f1b (u, v1 ) + f 2b (u, v 2 )

(2.3)

for all f1 and f2 in F, for all u, u1, and u2 in U, and for all v, v1, and v2 in V. The basic idea of the bilinear operator is apparent from this definition. It is an operator with two arguments, having the property that if either of the two arguments is fixed, the operator becomes linear in the remaining argument. A moment’s reflection will show that the intuitive operation of multiplication is of this type. One of the important features of a bilinear operator is that its image need not be a subspace of W. This is in marked contrast with the image of a linear operator, whose image is always a subspace. This property leads to great interest in the manipulations associated with vector products. At the same time, it brings about a great deal of nontriviality. The best way to illustrate the point is with an example. Example. Suppose the U, V, and W have bases {u1, u2}, {v1, v2}, and {w1, w2, w3, w4}, respectively. Then, vectors u in U and v in V can be represented in the manner u = f1u1 + f 2u2

(2.4)

v = g1v1 + g 2v 2

(2.5)

where fi and gi are elements of F for i = 1, 2. Define a bilinear map by the action b (u, v ) = 2 f1g 1w 1 + 3 f1g 2w 2 + 3 f 2 g 1w 3 + 2 f 2 g 2w 4

(2.6)

h1w1 + h2w 2 + h3w 3 + h4w 4

(2.7)

It is clear that every vector

in the image of b has the property that 9h1h4 = 4h2h3. If the {hi, i = 1, 2, 3, 4} are given so as to satisfy the latter condition, consider the task of showing that this vector in W is a vector in the image of b. Suppose that h1 = 0. Then either h2 or h3, is zero, or both are zero. If h2 is zero, one may choose f1 = 0, f2 = 1, g1 = h3/3, and g2 = h4/2. If h3 = 0, one may choose g1 = 0, g2 = 1, f1 = h2/3, and f2 = h4/2. An analogous set of constructions is available when h4 = 0. For the remainder of the argument, it is assumed that neither h1 nor h2 is zero. Accordingly, none of the coordinates {hi, i = 1, 2, 3, 4} is zero. Without loss, assume that f1 = 1. Then, g1 is given by h1/2, g2 is found from h2/3, and f2 is constructed from h3/3g1, which is then 2h3/3h1. It is easy to check that these choices produce the correct first three coordinates; the last coordinate is 4h3h2/9h1, which by virtue of the property 9h1h4 = 4h2h3 is equal to h4 as desired. Thus, a vector in W is in the image of b if and only if the relation 9h1h4 = 4h2h3 is satisfied. Next, it is © 2003 by CRC Press LLC

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shown that the vectors in this class are not closed under addition. For this purpose, simply select a pair of vectors represented by (1, 1, 9, 4) and (4, 9, 1, 1). The sum, (5, 10, 10, 5), does not satisfy the condition. It is perhaps not so surprising that the image of b in this example is not a subspace of W. After all, the operator b is nonlinear, when both of its arguments are considered. What may be surprising is that a natural and classical way can be used to circumvent this difficulty, at least to a remarkable degree. The mechanism that is introduced in order to address such a question is the tensor. The reader should bear in mind that many technical personnel have prior notions and insights on this subject emanating from areas such as the theory of mechanics and related bodies of knowledge. For these persons, the authors wish to emphasize that the following treatment is algebraic in character and may exhibit, at least initially, a flavor different from that to which they may be accustomed. This difference is quite typical of the distinctive points of view that often can be found between the mathematical areas of algebra and analysis. Such differences are fortunate insofar as they promote progress in understanding.

2.4 Tensor Product The notions of tensors and tensor product, as presented in this treatment, have the intuitive meaning of a very general sort of bilinear operator, in fact, the most general such operator. Once again, F-vector spaces U, V, and W are assumed. Suppose that b: U × U → W is a bilinear operator. Then the pair (b, W) is said to be a tensor product of U and V if two conditions are met. The first condition is that W is the smallest F-vector space that contains the image of b. Using alternative terminology this could be expressed as W being the vector space generated by the image of b. The term generated in this expression refers to the formation of all possible linear combinations of elements in the image of b. The second condition relates b to an arbitrary bilinear operator b˘: U × V → X in which X is another F-vector space. To be precise, the second condition states that for every such b˘, a linear operator B˘ : W → X exists with the property that ( ( b (u, v ) = B b (u, v )

(

)

(2.8)

for all pairs (u, v) in U × V. Intuitively, this means that the arbitrary bilinear operator b˘ can be factored in terms of the given bilinear operator b, which does not depend upon b˘, and a linear operator B˘ which does depend upon b˘. The idea of the tensor product is truly remarkable. Moreover, for any bilinear operator b˘, the induced linear operator B˘ is unique. The latter result is easy to see. Suppose that there are two such induced linear operators, e.g., B˘ 1 and B˘ 2. It follows immediately that (

(

(B − B )(b(u, v)) = 0 1

2

(2.9)

for all pairs (u, v). However, the first condition of the tensor product assures that the image of b contains a set of generators for W, and thus that (B˘ 1 – B˘ 2) must in fact be the zero operator. Therefore, once the tensor product of U and V is put into place, bilinear operations are in a one-to-one correspondence with linear operations. This is the essence of the tensor idea, and a very significant way to parameterize product operations in terms of matrices. In a certain sense, then, the idea of Chapter 2 is to relate the fundamen­ tally nonlinear product operation to the linear ideas of Chapter 1. That this is possible is, of course, classical; nonetheless, it remains a relatively novel idea for numerous workers in the applications. Intu­ itively, what happens here is that the idea of product is abstracted in the bilinear operator b, with all the remaining details placed in the realm of the induced linear operator B˘ . When a pair (b, W) satisfies the two conditions above, and is therefore a tensor product for U and V, it is customary to replace the symbol b with the more traditional symbol ⊗. However, in keeping the notion that ⊗ represents a product and not just a general mapping it is common to write u ⊗ v in place

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of the more correct, but also more cumbersome, ⊗(u, v). Along the same lines, the space W is generally denoted U ⊗ V. Thus, a tensor product is a pair (U ⊗ V, ⊗). The former is called the tensor product of U with V, and ⊗ is loosely termed the tensor product. Clearly, ⊗ is the most general sort of product possible in the present situation because all other products can be expressed in terms of it by means of linear operators B˘ . Once again, the colloquial use of the word “product” is to be identified with the more precise algebraic notion of bilinear operation. In this way the tensor product becomes a sort of “grand­ father” for all vector products. Tensor products can be constructed for arbitrary vector spaces. They are not, however, unique. For instance, if U ⊗ V has finite dimension, then W obviously can be replaced by any other F-vector space of the same dimension, and ⊗ can be adjusted by a vector space isomorphism. Here, the term isomor­ phism denotes an invertible linear operator between the two spaces in question. It can also be said that the two tensor product spaces U ⊗ V and W are isomorphic to each other. Whatever the terminology chosen, the basic idea that the two spaces are essentially the same within the axiomatic framework in use.

2.5 Basis Tensors Attention is now focused on the case in which U and V are finite-dimensional vector spaces over the field F. Suppose that {u1, u2, …, um} is a basis for U and {v1, v2, …, vn} is a basis for V. Consider the vectors u1 ⊗ v1 u1 ⊗ v 2 ,..., u1 ⊗ v n

u2 ⊗ v1 ,..., um ⊗ v n

(2.10)

which can be represented in the manner {ui ⊗ vj, i = 1, 2, …, m; j = 1, 2, …, n}. These vectors form a basis for the vector space U ⊗ V. To understand the motivation for this, note that vectors in U and V, respectively, can be written uniquely in the forms m

u=

∑fu

(2.11)

i i

i=1 n

v=

∑g v

(2.12)

j j

j=1

Recall that ⊗, which is an alternate notation for b, is a bilinear operator. It follows then that u⊗v =

m

n

i=1

j=1

∑∑ f g u ⊗ v i

j i

j

(2.13)

which establishes that the proposed basis vectors certainly span the image of ⊗, and thus that they span the tensor product space U ⊗ V. It also can be shown that the proposed set of basis vectors is linearly independent. However, in the interest of brevity for this summary exposition, the details are omitted. From this point onward, inasmuch as the symbol ⊗ has replaced b, it will be convenient to use b in place of b˘ and B in place of B˘ . It is hoped that this leads to negligible confusion. Thus, in the sequel b refers simply to a bilinear operator and B to its induced linear counterpart. Example. Consider the bilinear form b: R2 × R3 → R with action defined by b ( f1, f 2 , g 1, g 2 , g 3 ) = 2 f 2 g 3 Observe that this can be put into the more transparent form

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(2.14)

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[f

1

 g1  0 0 0    g 2  f2  0 0 2   g   3

]

(2.15)

which, in turn, can be written in the compact notation uTMv. Clearly, U has dimension two, and V has dimension three. Thus, U ⊗ V has a basis with six elements. The operator b maps into R, which has a basis with one element. All bases are chosen to be standard. Thus, an ith basis vector contains the multiplicative field element 1 in its ith row, and the additive field element 0 in its other rows. Therefore, the matrix of B has one row and six columns. To compute the entries, it is necessary to agree upon the order of the basis elements in R2 ⊗ R3. It is customary to choose the natural ordering as introduced previously: u1 ⊗ v1 u1 ⊗ v 2 u1 ⊗ v 3 u2 ⊗ v1 u2 ⊗ v 2 u2 ⊗ v 3

(2.16)

The coordinate h1 associated with the basis vector [1] in R, considered to be a vector space, is given by h 1 = b (1, 0, 1, 0, 0) = 0

(2.17)

when u and v are given by the respective first basis vectors in R2 and R3, respectively: 1 u=  0

(2.18)

1   v = 0   0

(2.19)

Similarly, for other five pairings in order, one obtains h1 = b (1, 0, 0, 1, 0) = 0

(2.20)

h1 = b (1, 0, 0, 0, 1) = 0

(2.21)

h1 = b (0, 1, 1, 0, 0) = 0

(2.22)

h1 = b (0, 1, 0, 1, 0) = 0

(2.23)

h1 = b (0, 1, 0, 0, 1) = 2

(2.24)

in order. In view of these calculations, together with the definitions of matrices in Chapter 1, it follows that the matrix description of B: R2 ⊗ R3 → R is given by

[B] = [0

0 0 0 0 2]

(2.25)

Observe that all the numerical information concerning B has been arrayed in [B]. It becomes increasingly clear then that such numerical entries define all possible bilinear forms of this type.

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Example. In order to generalize the preceding example, one has only to be more general in describing the matrix of M. Suppose that m11 m12 m13   m21 m22 m23 

[M ] = 

(2.26)

so that the bilinear operator b has action g1  m11 m12 m13     g 2  f2  m2 m22 m23    g   3

[

]

b( f1 , f 2 , g1 , g 2 , g 3 ) = f1

(2.27)

Thus, it is easy to determine that

[B] = [m11

m12

m13

m21

m22

m23

]

(2.28)

The two examples preceding help in visualizing the linear operator B by means of its matrix. They do not, however, contribute to the understanding of the nature of the tensor product of two vectors. For that purpose, it is appropriate to carry the examples a bit further. Example. The foregoing example presents the representations  f1     f 2 

(2.29)

g1    g 2    g   3

(2.30)

for u and

for v. From the development of the ideas of the tensor product, it was established that b(u, v) = B(u ⊗ v). The construction of u ⊗ v proceeds according to definition in the manner  u⊗v =  =

2

∑ i=1

  fiui  ⊗   

2

3

i=1

j=1



3

∑ g v 

(2.31)

j j

j=1

∑∑ f g u v i

(2.32)

j i j

From this and the basis ordering chosen above, it is clear that the representation of u ⊗ v is given by

[u ⊗ v ] = [ f g

1 1

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f1 g 2

f1 g 3

f 2 g1

f2 g 2

f2g 3

]

T

(2.33)

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The total picture for the tensor representation of b(u, v), then, is

 f1  b ( f1 , f 2 , g1 , g 2 , g 3 ) =    f 2 

T

[

= m11

[

= m11

 g1  m11 m12 m13      g 2  m21 m22 m23    g   2

m12

m12

m13

m13

m21

m21

m22

m22

(2.34)

m23

m23

  g1    f1       ⊗  g 2    f 2      g    3

(2.35)

 f1 g1     f1 g 2     f1 g 3    f g   2 1 f g   2 2    f2 g 3 

(2.36)

]

]

The reader should have no difficulty extending the notions of these examples to cases in which the dimensions of U and V differ from those used here. The extension to an X with dimension larger than 1 is similar in nature, and can be carried out row by row. Example. Another sort of example, which is likely to be familiar to most readers, is the formation of the ordinary matrix product m(P, Q) = PQ for compatible matrices P and Q over the field F. Clearly, the matrix product m is a bilinear operator. Thus, a linear operator M exits that has the property m( P, Q) = M ( P ⊗ Q)

(2.37)

The matrix P ⊗ Q is known in the applications as the Kronecker product. If the basis vectors are chosen in the usual way, then its computation has the classical form. Thus, the Kronecker product of two matrices is seen to be the most general of all such products. Indeed, any other product, including the usual matrix product, can be found from the Kronecker product by multiplication with a matrix.

2.6 Multiple Products It may happen that more than two vectors are multiplied together. Thus, certain famous and well-known field formulas include both crosses and dots. While the notion of multiple product is part and parcel of the concept of ring, so that no further adjustments need to be made there, one must undertake the question of how these multiple products are reflected back into the tensor concept. The purpose of this section, therefore, is to sketch the major ideas concerning such questions. A basic and natural step is the introduction of a generalization of bilinear operators. For obvious reasons, not the least of which is the finite number of characters in the alphabet, it is now necessary to modify notation so as to avoid the proliferation of symbols. With regard to the foregoing discussion, the modification, which is straightforward, is to regard a bilinear operator in the manner b: U1 × U2 → V in place of the previous U × V → W. Generalizing, consider p F-vector spaces Ui , i = 1, 2, …, p. Let m: U1 × U2 × L × Up → V be an operator that satisfies the condition © 2003 by CRC Press LLC

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(( m u1, u 2 ,..., ui − 1, fi ui + fi ui , ui + 1,..., u p = fi m u1, u 2 ,..., ui − 1, ui , ui + 1,..., u p

(

)

(

) ,..., u )

( ( + fi m u1, u 2 , ..., ui−1, ui , ui+1

(

(2.38)

p

for i = 1, 2, …, p, for all fi and f˘i in F, and for all ui and u˘ i in Ui. Thus, m is said to be a p-linear operator. Observe in this definition that when p – 1 of the arguments of m are fixed, m becomes a linear operator in the remaining argument. Clearly, the bilinear operator is a special case of this definition, when p = 2. Moreover, the definition captures the intuitive concept of multiplication in a precise algebraic sense. Next, the notion of tensor product is extended in a corresponding way. To do this, suppose that m and V satisfy two conditions. The first condition is that V is the smallest F-vector space that contains the image of m. Equivalently, V is the F-vector space generated by the image of m. Recall that the image of m is not equal to V, even in the bilinear case p = 2. The second condition is that ( ( m u1 , u2 , ..., u p = M m u1 , u2 , ..., u p

(

((

)

))

(2.39)

˘ : V → W is a linear operator, W is an F-vector space and m˘ : U1 × U2 × L × Up → W is an where M arbitrary p-linear operator. If m satisfies these two conditions, the action of m is more traditionally written in the manner

(

)

m u1, u 2 , ..., u p = u1 ⊗ u 2 ⊗ ... ⊗ u p

(2.40)

and the space V is given the notation V = U1 ⊗U 2 ⊗ L ⊗Up

(2.41)

Once again, existence of the tensor product pair (m, V) is not a problem, and the same sort of uniqueness holds, that is, up to isomorphism. It is now possible to give a major example of the multiple product idea. The general import of this example far exceeds the interest attached to more elementary illustrations. Therefore, it is accorded its own section. The reason for this will shortly become obvious.

2.7 Determinants The body of knowledge associated with the theory of determinants tends to occupy a separate and special part of the memory which one reserves for mathematical knowledge. This theory is encountered some­ what indirectly during matrix inversion, and thus is felt to be related to the matrix algebra. However, this association can be somewhat misleading. Multiplication in the matrix algebra is really a multiplication of linear operators, but determinants are more naturally seen in terms of multiplication of vectors. The purpose of this section is to make this idea apparent, and to suggest that a natural way to correlate this body of knowledge is with the concept of an algebra constructed upon a given F-vector space. As such, it becomes a special case of the ideas previously introduced. Fitting determinants into the larger picture is then much less of a challenge than is usually the case, which can save precious human memory. Consider at the outset a square array of field elements from F, denoted customarily by  d11 d12 L d1 p     d21 d22 L d2 p   D=  M M O M    d  L d d  p1 p2 pp  © 2003 by CRC Press LLC

(2.42)

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The determinant of D will be denoted by det(D). It is assumed that all readers are comfortable with at least one of the algorithms for computing det(D). The key idea about det(D) is that it is a p-linear operator on its columns or upon its rows. In fact, two of the three classical properties of determinants are tantamount precisely to this statement. The third property, which concerns interchanging columns or rows, is also of great interest here (see below). Without loss of generality, suppose that det(D) is regarded as p-linear function of its columns. If the columns, in order, are denoted by d1, d2, …, dp , then it is possible to set up a p-linear operator

(

)

m d1, d2 , ..., dp = det (D )

(2.43)

Accordingly, tensor theory indicates that this operator can be expressed in the manner

(

)

(

m d1, d2 , ..., dp = M d1 ⊗ d2 ⊗ L ⊗ dp

)

(2.44)

It is interesting to inquire about the nature of the matrix [M]. In order to calculate [M], it is necessary to select bases Ui, i = 1, 2, …, p. In this case it is possible to identify Ui for each i with a fixed space U of dimension p. Let {u1, u2, …, up} be a basis for U and represent this basis by the standard basis vectors {e1, e2, …, ep} in F p. Moreover, select a basis for F and represent it by the multiplicative unit 1 in F. Then the elements of [M] are found by calculating

(

det ei1

ei2

L eip

)

(2.45)

for all sequences i1i2 … ip in the increasing numerical order introduced earlier. Thus if p = 3, this set of sequences is 111, 112, 113, 121, 122, 123, 131, 132, 133, 211, 212, 213, 221, 222, 223, 231, 232, 233, 311, 312, 313, 321, 322, 323, 331, 332, 333. Example. For the case p = 3 described previously, it is desired to calculate [M]. The first few calculations are given by

© 2003 by CRC Press LLC

det (e1 e1 e1 ) = 0

(2.46)

det (e1 e1 e 2 ) = 0

(2.47)

det (e1 e1 e3 ) = 0

(2.48)

det (e1 e 2 e1 ) = 0

(2.49)

det (e1 e 2 e 2 ) = 0

(2.50)

det (e1 e 2 e3 ) = +1

(2.51)

det (e1 e3 e1 ) = 0

(2.52)

det (e1 e3 e 2 ) = −1

(2.53)

det (e1 e3 e3 ) = 0

(2.54)

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Bilinear Operators and Matrices

det (e 2 e1 e1 ) = 0

(2.55)

det (e 2 e1 e 2 ) = 0

(2.56)

det (e 2 e1 e3 ) = − 1

(2.57)

M Rather than provide the entire list in this form, it is easier to give the elements in the right members of the equations. Employing determinant theory, it follows that those sequences with repeated subscripts correspond to 0. Moreover, interchanging two columns changes the sign of the determinant, the third property mentioned previously. Thus, the desired results are 0, 0, 0, 0, 0, + 1, 0, − 1, 0, 0, 0, − 1, 0, 0, 0, + 1, 0, 0, 0, + 1, 0, − 1, 0, 0, 0, 0, 0

(2.58)

Then [M] is a row matrix having these numerical entries. It is 1 × 27. Example. The preceding example indicates that the formation of the determinant in tensor notation results in the appearance of numerous multiplications by zero. This is inefficient. Moreover, if all the zero entries in [M] are dropped, the result is a product of the form d11d22d33    d11d32d23    d21d12d33   [ +1 − 1 − 1 + 1 + 1 − 1]  d21d32d13    d d d   31 12 23    d31d22d13 

(2.59)

easily seen to be the standard formula for classical calculation of the determinant. In view of this result, one immediately wonders what to do about all the dropped zeros. The following section shows how to do away with all the zeros. In the process, however, more things happen than might have been anticipated; as a result, an entirely new concept appears.

2.8 Skew Symmetric Products The determinant is an instance of skew symmetry in products. Consider a p-linear operator m: U1 × U2 × L × Up → V with the property that each interchange of two arguments changes the sign of the result produced by m. Thus, for example,

(

)

(

m u1 , K, ui −1 , ui , K, u j −1 , u j , K, u p = − m u1 , K, ui −1 , u j , K, u j −1 , ui , K, u p

)

(2.60)

If a list of k interchanges is performed, the sign is changed k times. Such an operator is described as skew symmetric. Provided that only skew symmetric multiplications are of interest, the tensor construction can be streamlined. Let (mskewsym, V) be a pair consisting of a skew symmetric p-linear operator and an F-vector space V. This pair is said to constitute a skew symmetric tensor product for the F-vector spaces U1, U2, … Up, if two conditions hold. The reader can probably guess what these two conditions are. Condition one is that V is the F-vector space generated by the image of mskewsym. Condition two is the property that © 2003 by CRC Press LLC

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˘ skewsym: for every skew symmetric p-linear operator m˘ skewsym: U1 × U2 × L × Up → W, a linear operator M V → W exists having the feature ( ( mskewsym u1 , u2 , K, u p = M skewsym mskewsym u1 , u2 , K, u p

(

(

)

(

))

(2.61)

If these two conditions hold for the pair (mskewsym, V), then the custom is to write

(

)

mskewsym u1 , u2 , K, u p = u1 ∧ u2 ∧ L ∧ u p

(2.62)

V = U1 ∧ U 2 ∧ L ∧ Up

(2.63)

for the action of mskewsym and

for the product of the vector spaces involved. Once again, this skew symmetric tensor product exists, and is unique in the usual way. Now suppose that Ui = U, i = 1, 2, …, p and that {u1, u2, …, up} is a basis for U. It is straightforward to show that ui1  ui2  L  uip vanishes whenever two of its arguments are equal. Without loss, assume that uij = uik = u. If uij and uik are switched, the sign of the product must change. However, after the switch, the argument list is identical to the previous list. Because the only number whose value is unchanged after negation is zero, the conclusion follows. Accordingly, the basis U1  U2  L  Up is the family

{u

∧ ui2 ∧ L ∧ ui p

i1

}

(2.64)

where each i1 i2 L ip consists of p distinct nonzero natural numbers, and where the ordinary convention is to arrange the {ik}so as to increase from left to right. A moment’s reflection shows that only one such basis element can exist, which is u1  u2  L  up. Thus, if p = 4, the basis element in question is u1  u2  u3  u4. If we return to the example of the determinant, and regard it as a skew symmetric p-linear operator, then the representation

(

)

(

mskewsym d1 , d2 , K, dp = M skewsym d1 ∧ d2 ∧ K ∧ dp

)

(2.65)

is obtained. Next observe that each of the p columns of the array D can be written as a unique linear combination of the basis vectors {u1, u2, …, up} in the manner p

dj =

∑d u

ij i

(2.66)

i=1

for j = 1, 2, …, p. Then it follows that d1  d2  L  dp is given by p

p

p

∑∑ ∑ d L

i1 =1 i2 =1

d Ldi p pui1 ∧ ui2 ∧ L ∧ ui p

i11 i2 2

(2.67)

i p =1

which is a consequence of the fact that  is a p-linear operator. The only nonzero terms in this p-fold summation are those for which the indices {ik, k = 1, 2, …, p} are distinct. The reader will correctly surmise that these terms are the building blocks of det(D). Indeed, d1 ∧ d2 ∧ L ∧ dp = det( D)u1 ∧ u2 ∧ L ∧ u p © 2003 by CRC Press LLC

(2.68)

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35

Bilinear Operators and Matrices

and, if U is Rp with the {ui} chosen as standard basis elements, then d1 ∧ d2 ∧ L ∧ d p = det( D)

(2.69)

because u1  u2  L  up becomes 1 in F. Moreover, it is seen from this example how the usual formula for det(D) is altered if the columns of D are representations with respect to a basis other than the standard basis. In turn, this shows how the determinant changes when the basis of a space is changed. The main idea is that it changes by a constant that is constructed from the determinant whose columns are the corre­ sponding vectors of the alternate basis. Finally, because of this new basis is given by an invertible linear transformation from the old basis, it follows that the determinant of the transformation is the relating factor. It can now be observed that the change from a tensor product based upon ⊗ to a tensor product based upon  has indeed eliminated the zero multiplications associated with skew symmetry. However, and this could possibly be a surprise, it has reduced everything to one term, which is the coordinate relative to the singleton basis element in a tensor product space of dimension one. This may be considered almost a tautology, except for the fact that it produces a natural generalization of the determinant to arrays in which the number of rows is not equal to the number of columns. Without loss, assume that the number of columns is less than the number of rows. Example. Consider, then, an array of field elements from F, with less columns than rows, denoted by  d11 d12 L d1 p     d21 d22 L d2 p   D=  M M O M     d  q1 dq2 L dqp 

(2.70)

where p < q. The apparatus introduced in this section still permits the formation of a skew symmetric p-linear operation in the manner d1  d2  L  dp. This is a natural generalization in the sense that the ordinary determinant is recovered when p = q. Moreover, the procedure of calculation is along the same lines as before, with the representations q

dj =

∑d u

(2.71)

ij i

i=1

for j = 1, 2, …, p. Note that the upper limit on the summation has changed from p to q. The reader will observe, then, that d1  d2  L  dp can be found once again by the familiar step q

q

q

∑∑ ∑ d L

i1 =1 i2 =1

d Ldi p pui1 ∧ ui2 ∧ L ∧ ui p

i11 i2 2

(2.72)

i p =1

which is a consequence once again of the fact that  is a p-linear operator. In this case, however, there is more than one way to form nonzero products in the family

{u

i1

∧ ui2 ∧ L ∧ ui p

}

(2.73)

in which i1i2 … ip contains p distinct numbers, and where the traditional convention is to arrange the {ik} so that the numbers in each list are increasing, while the numbers which these sequences represent are also increasing. This verbiage is best illustrated quickly. © 2003 by CRC Press LLC

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Example. Suppose that p = 3 and q = 4. Thus, the sequences i1i2i3 of interest are 123, 124, 134, 234. It can be observed that each of these sequences describes a 3 × 3 subarray of D in which the indices are associated with rows. In a sense these subarrays lead to all the interesting 3 × 3 minors of D, inasmuch as all the others are either zero or negatives of these four. Some of these designated four minors could also be zero, but that would be an accident of the particular problem instead of a general feature. Example. This example investigates in greater detail the idea of q > p. Suppose that p = 2 and q = 3. Further, let the given array be d11 d12    D =  d21 d22     d  31 d32 

(2.74)

Choose the standard basis {e1, e2, e3} for U = F 3. Then d1 = d11e1 + d21e 2 + d31e3

(2.75)

d2 = d12e1 + d22e 2 + d32e3

(2.76)

from which one computes that d1 ∧ d2 = (d11e1 + d21e 2 + d31e3 ) ∧ (d12e1 + d22e 2 + d32e3 ) = (d11d22 − d21d12 ) e1 ∧ e 2 + (d11d32 − d31d12 ) e1 ∧ e 3 + (d21d32 − d31d22 ) e 2 ∧ e3

(2.77)

(2.78)

that evidently can be rewritten in the form d11 d12  d1 ∧ d2 = det   e1 ∧ e 2  d21 d22  d11 d12  + det   e1 ∧ e3  d31 d32 

(2.79)

d21 d22  + det   e 2 ∧ e3  d31 d32  making clear the idea that the 2 × 2 minors of D become the coordinates of the expansion in terms of the basis {e1  e2, e1  e3, e2  e3} for R3  R3.

2.9 Solving Linear Equations An important application of the previous section is to relate the skew symmetric tensor algebra to one’s intuitive idea of matrix inversion. Consider the linear equation

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d11 d12 L d1 p  x1  c1       d d22 L d2 p  x 2  c 2  21    =    M M O M   M   M         x  c  d p1 d p 2 L d pp   p   p 

(2.80)

With the aid of the usual notation for columns of D, rewrite this equation in the manner p

∑x d = c i i

(2.81)

i =1

where c is a vector whose ith element is ci . To solve for xk , multiply both members of this equation by the quantity d1 ∧ d2 ∧ L ∧ dk −1 ∧ dk +1 ∧ L ∧ d p

(2.82)

which will be denoted by dk–. This multiplication can be done either on the left or the right, and the vector product which is used is . Multiplying on the left provides the result x kdk − ∧ dk = dk− ∧ c

(2.83)

Now if det(D) is not zero, then this equation solves for x k = (dk − ∧ c ) (dk − ∧ dk )

(2.84)

and this is essentially Cramer’s rule. Using this rule conventionally one performs enough interchanges so as to move c to the kth column of the array. If these interchanges are performed in an analogous way with regard to dk in the denominator, the traditional form of the rule results. This approach to the result shows that the solution proceeds by selecting multiplication by a factor which annihilates all but one of the terms in the equation, where each term is concerned with one column of D. This is simply a new way of viewing an already known result. However, the treatment of Section 2.8 suggests the possibility of extending the construction to the case in which are found more unknowns than equations. The latter procedure follows via a minor adjustment of the foregoing discussion, and thus it seems instructive to illustrate the steps by means of an example. Example. Consider the problem corresponding to q = 3 and p = 2 and given by three equations in two unknowns as follows: 1 2  7   x1    3 4   = 8   x 2    5 6  9

(2.85)

Begin by rewriting the equation in the form 1  2  7       x1 3 + x 2 4 = 8       5 6  9 © 2003 by CRC Press LLC

(2.86)

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To solve for x2, multiply from the left with [1 3 5]T. This gives 1  2  1  7         x 2 3 ∧ 4 = 3 ∧ 8         5 6  5 9

(2.87)

− 2  − 13      x 2 − 4 = − 26     − 6  − 13 

(2.88)

which then implies

which implies that x2 = 13/2. Next, consider a left multiplication by [2 4 6]T. Therefore, 2  1  2  7         x1 4 ∧ 3 = 4 ∧ 8         6  5 6  9

(2.89)

2  − 12      x1 4 = − 24     2  − 12 

(2.90)

which then implies

which implies that x1 = –6. It is easy to check that these values of x1 and x2 are the unique solution of the equation under study. The reader is cautioned that the construction of the preceding example produces necessary conditions on the solution. If any of these conditions cannot be satisfied, no solution can be found. On the other hand, if solutions to the necessary conditions are found, we must check that these solutions satisfy the original equation. Space limitations prevent any further discussion of this quite fascinating point.

2.10 Symmetric Products The treatment presented in Section 2.8 has a corresponding version for this section. Consider a p-linear operator m: U1 × U2 × L × Up → V with the property that each interchange of two arguments leaves the result produced by m unchanged. Symbolically, this is expressed by

(

) (

m u1 , K , ui −1 , ui , K , u j − 1 , u j , K , u p = m u1 , K , ui −1 , u j , K , u j −1 , ui , K , u p

)

(2.91)

Such an operator is said to be symmetric. If only symmetric multiplications are of interest, the tensor construction can once again be trimmed to fit. Let (msym, V) be a pair consisting of a symmetric p-linear operator and an F-vector space V. This pair is said to constitute symmetric tensor product for the F-vector spaces U1, U2, …, Up if two conditions hold. First, V is the F-vector space generated by the image of msym; and, second, for every symmetric ˘ sym: V → W such that p-linear operator m˘ sym: U1 × U2 × L × Up → W, linear operator M

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( ( msym u1 , u2 , K, u p = M sym msym u1 , u2 , K, u p

(

( (

)

))

(2.92)

In such a case, one writes

(

)

(2.93)

V = U1 ∨ U 2 ∨ L ∨ U p

(2.94)

msym u1 , u2 , K, u p = u1 ∨ u2 ∨ L ∨ u p to describe the action of msym and

for the symmetric tensor product of the vector spaces involved. As before, this symmetric tensor product exists and is essentially unique. Next, let Ui = U, i = 1, 2, …, p, and {u1, u2, …, up} be a basis for U. Because the interchange of two arguments does not change the symmetric p-linear operator, the basis elements are characterized by the family

{u ∨ u i1

i2

∨ L ∨ ui p

}

(2.95)

where each i1i2Lip consists of all combinations of p nonzero natural numbers, written in increasing order, and where the ordinary convention is to arrange the basis vectors so that the numbers i1i2Lip increase. Unlike the skew symmetric situation, quite a few such basis vectors can, in general, exist. For instance, the first basis element is u1  u1  L  u1, with p factors and the last one is up  up  L  up, again with p factors. Example. Suppose that p = 3 and that the dimension of U is 4. The sequences i1i2i3 of interest in the representation of symmetric p-linear products are 111, 112, 113, 114, 122, 123, 124, 133, 134, 144, 222, 223, 224, 233, 234, 244, 333, 334, 344, 444. Section 2.7 showed a related example which produced 27 basis elements for the tensor product space built upon ⊗. In this case, it would be 64. The same situation in Section 2.8 produced four basis elements for a tensor product space constructed with . Twenty basis elements are found for the tensor product space produced with . Notice that 20 + 4 ≠ 64. This means that the most general space based on ⊗ is not just a direct sum of those based on  and . Example. For an illustration of the symmetric product idea, choose U = R2 and form a symmetric bilinear form in the arrangement of a quadratric form uTMu: msym ( f1 , f 2 )

 f1  =    f 2 

T

m11 m12   f1     m21 m22   f 2 

(2.96)

A word about the matrix M is in order. Because of the relationship M=

1 2

(M + M ) + 12 (M − M ) T

T

(2.97)

it is easy to see that M may be assumed to be symmetric without loss of generality, as the remaining term in this representation of msym (f1, f2) leads to a zero contribution in the result. Thus, one is concerned with a natural candidate for the symmetric tensor mechanism. The tensor construction begins by considering

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 f1   f1   ∨   f 2   f 2 

(2.98)

Choose a standard basis {e1, e2} for R2. Then the expression introduced previously becomes 2

2

i=1

j=1

∑∑ f f e ∨ e i j i

(2.99)

j

which becomes f12e1 ∨ e1 + 2 f1 f 2e1 ∨ e 2 + f 22e 2 ∨ e 2

(2.100)

The result may be represented with the matrix

[f

2 1

2 f1 f 2 f 22

]

T

(2.101)

Because p = 2, the basis vectors of interest are seen to be {e1  e1, e1  e2, e2  e2}. Inserted into the expression for msym , these produce the results m11, m12 = m21, m22, respectively. Thus,

[M ] = [m

m12

11

sym

m22

]

(2.102)

 f12 

 

2 f f  1 2    2   f2 

(2.103)

Finally, the symmetric tensor expression for msym is

[

msym ( f1 , f 2 ) = m11

m12

m22

]

Example. If M, as in the previous example, is real and symmetric, then it is known to satisfy the equation ME = EΛ

(2.104)

where E is a matrix of eigenvectors of M, satisfying ETE = I, and Λ is a diagonal matrix of eigenvalues {λi}, which are real. Then M = EΛE T

(2.105)

and the quadratic form uTMu becomes

[ ] [ ] T

uT Mu = E Tu Λ E Tu

(2.106)

p

=

∑ λ [E u ] T

i

i

(2.107)

i=1

When one considers u to be an arbitrary vector in R p, this quadratic form is non-negative for all u if and only if the {λi} are non-negative and is positive for all nonzero u if and only if the {λi} are positive. M is then non-negative definite and positive definite, respectively. © 2003 by CRC Press LLC

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Bilinear Operators and Matrices

Example. With reference to the preceding example, it is sometimes of interest to choose U = C p, where the reader is reminded that C denotes the complex numbers. In this case a similar discussion can be carried out, with M as a complex matrix. The quadratic form must be set up a bit differently, with the structure u*Mu, in which superscript * denotes a combined transposition and conjugation. Also, without loss one can assume that M* = M. A common instance of this sort of situation occurs when M is a function M(s) of the Laplace variable s, which is under consideration on the axis s = jω.

2.11 Summary The basic idea of this chapter is to examine the axiomatic framework for equipping an F-vector space V with a vector multiplication, and thus develop it into an algebra. Despite the fact that vector multiplication is manifestly a nonlinear operation, a very useful matrix theory can be developed for such multiplications. The treatment is based upon notions of algebraic tensor products from which all other multiplications can be derived. The authors demonstrate that the determinant is nothing but a product of vectors, with a special skew symmetric character attached to it. Specializations of the tensor product to such cases, and to the analogous case of symmetric products, were discussed. As a final remark, it should be mentioned that tensor products develop into a complete algebra of their own. Although space does not permit treatment here, note that the key idea is the definition

(v ⊗ L ⊗ v ) ⊗ (v 1

p

p+1

)

⊗ L ⊗ v q = v1 ⊗ L ⊗ v q

Reference W. H. Greub, Multilinear Algebra, New York: Springer-Verlag, 1967.

© 2003 by CRC Press LLC

(2.108)

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3 The Laplace Transform 3.1 3.2

Introduction Motivational Example Series RLC Circuit • Homogeneous Solution and the Natural Response • Nonhomogeneous Solution and the Forced Response • Total Solution • Scrutinizing the Solution • Generalizing the Phasor Concept: Onward to the Laplace Transform

3.3

Formal Developments Definitions of the Unilateral and Bilateral Laplace Transforms • Existence of the Laplace Transform • Example of Laplace Transform Computations and Table of Unilateral Laplace Transforms • Poles and Zeros — Part I: Properties of the Laplace Transform • Inverse Laplace Transform

3.4

Laplace Transform Analysis of Linear Systems Solution of the System Differential Equation • The System Function • Poles and Zeros — Part II: Stability Analysis of Systems • Laplace-Domain Phasor Circuits

John R. Deller, Jr.

3.5 3.6 3.7

Michigan State University

Conclusions and Further Reading Appendix A: The Dirac Delta (Impulse) Function Appendix B: Relationships among the Laplace, Fourier, and z-Transforms

3.1 Introduction The Laplace Transform (LT) is the cornerstone of classical circuits, systems, and control theory. Developed as a means of rendering cumbersome differential equation solution simple algebraic problems, the engineer has transcended this original motivation and has developed an extensive toolbag of analysis and design methods based on the “s-plane.” After a motivating differential equation (circuit) problem is presented, this chapter introduces the formal principles of the LT, including its properties and methods for forward and inverse computation. The transform is then applied to the analysis of circuits and systems, exploring such topics as the system function and stability analysis. Two appendices conclude the chapter, one of which relates the LT to other signal transforms to be covered in this volume.

3.2 Motivational Example Series RLC Circuit Let us motivate our study of the LT with a simple circuit example. Consider the series RLC circuit shown in Fig. 3.1, in which we leave the component values unspecified for the moment. With the input and output to the circuit taken to be the voltages x and y, respectively, the input–output dynamics of this circuit are found to be governed by a linear, constant-coefficient differential equation

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The Circuits and Filters Handbook, Second Edition

+

R

+

L C

x (t)

y (t)

−

−

FIGURE 3.1 Series RLC circuit example.

x (t ) = LC

d2y dy + RC + y (t ) 2 dt dt

(3.1)

This equation arises from a circuit example, but is typical of many second-order systems arising in mechanical, fluid, acoustic, biomedical, chemical, and other engineering models. We can, therefore, view the circuit as a “system,” and the theory explored here as having broad applicability in modeling and analysis of systems. Suppose we are asked to find the complete solution for the output voltage y, given input x (t ) = M x e σ xt cos (ω x t + θ x ) u(t )

(3.2)

in which u denotes the unit step function, u(t ) = {0, t < 0 def

1 2, t = 0

1, t > 0}

(3.3)

For convenience and without loss of generality we assume that Mx > 0. The initial conditions [at time t(0–)] on the circuit are given to be1 i(0–) = i0 and y(0–) = y0 where y0 and i0 are known quantities.

Homogeneous Solution and the Natural Response ~ The homogeneous or complementary solution of the differential equation, say y, represents the natural, or unforced, response of the system. The natural response occurs because of the inequity between the initial conditions and the conditions imposed upon the system by the input at the instant it is applied. The system must adjust to these new conditions and will do so in accordance with its own physical properties (e.g., circuit values). For stable systems (see “Poles and Zeros — Part II”), the natural response will consist of transients, signals which decay exponentially with time. The unforced response will always be present unless the system is stable, and either the input was applied at time t = –∞ (transient will have diminished in the infinite time interval prior to time zero) or the initial conditions on the system exactly nullify the “shock” of the input so that a transient adjustment is not necessary. The form of the natural response (homogeneous solution) is not dependent on the input (except for its use in determining changes around time t = 0), but rather on the inherent properties of the system. The homogeneous solution is found by initially seeking the input-free response which may be written as

(

)

0 = LC2 + RC +1 y (t ) with  =

def

di dt i

(3.4)

1The notations 0+ and 0– indicate limits at t = 0 from the right and left, respectively. That y(0+) = y(0–), for example, indicates continuity of y(t) at t = 0.

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45

The Laplace Transform

The characteristic equation is therefore

(

)

0 = LCp 2 + RCp +1

(3.5)

Solving for the roots, we find p1 , p2 =

−RC ± R 2C 2 − 4LC 1 R R2 =− ± − 2 2LC 2L 4L LC

(3.6)

In general, p1 and p2 can be real and unequal (overdamped case), equal and real (critically damped case), or complex conjugates (underdamped case). Except in the critically damped case (in which R2C2 = 4LC so that two indentical real roots are found), the homogeneous solution takes the form. y˜ (t ) = Ae p1t + Be p2t

(3.7)

With A and B to be specified at the end of the solution. For the sake of discussion, assume the underdamped case in which the natural response will be oscillatory, corresponding to a complex-conjugate pair of roots of (3.5). In this case we have R2 C 2 < 4LC def and p2 = p*1. Let us define ph = p1, so the two roots are ph and = ph*. The meaning of the subscript “h” will become clear later. Some manipulation of (3.7) will simplify our future work. We have p t y˜ (t ) = Ae pht + Be h *

(3.8)

We observe that A and B must be complex conjugates if y~ is to be a real signal. Thus, we write y˜ (t ) = Ae pht + A * e pht

(3.9)

After some manipulation using Euler’s relation, e jα = cos (α) + j sin (α), we have y˜ (t ) = 2Aree σht cos(ω ht ) − 2Aime σht sin(ω ht ) = 2 A e σht cos(ω ht + θ A )

(3.10)

where A = Are + jAim = A e jθA and ph = σh + jωh . The numbers Are and Aim, or, equivalently, |A| and θA, are to be determined later.2 Note that the number ph is often called the complex frequency associated with the damped3 sinusoid. The complex frequency is simply a convenient mathematical way to hold the damping and frequency information in one quantity. Later in the chapter we see that ph is also a “pole” of the system being analyzed.

Nonhomogeneous Solution and the Forced Response ≈

The nonhomogeneous, or particular solution, say y, represents the system’s forced, or driven, response. For certain prevalent types of inputs, the forced response represents an attempt to “track” the forcing function in some sense. If the natural response in a particular problem is transient and the forced response is not, then a “long time” (theoretically, t → ∞) after the input is applied, only this “tracking” response 2

In fact, because Are and Aim are unknowns, we could replace 2Are, 2Aim, and 2|A| with some simpler notations if desired. 3We use the term “damping” to refer to the real part of any complex frequency, “σ”, with the understanding that two other cases are actually possible: If σ= 0 the signal is undamped, and if σ> 0, the signal is exponentially increasing. © 2003 by CRC Press LLC

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The Circuits and Filters Handbook, Second Edition

will remain. In the present circuit example the forced response is uniquely present as t → ∞ if σh < 0 (natural response exponentially decays) and σx ≥ 0 (forcing function persists in driving the circuit for all time). Further, in the special case in which the forcing function is a periodic or constant signal [an undamped sinusoid, undamped complex exponential, or a constant (in each case σx = 0)], this “tracking” response, in the absence of any transients, is called the steady-state response of the system. Note that the forced response will be present for all t > 0, but may become uniquely evident only after the transient natural response dies out. Also, note that the forced response might never become evident if it is itself a transient (σx < 0), even though in this case the forced response will still represent an attempt to track the input. ≈ For mathematical convenience in finding y, we let x be replaced by σ jω t +0 x (t ) = M x e x ( x x ) u(t )

[

] [

(3.11)

]

= M x e σ xt cos(ω x t + θ x ) + jM x e σ xt sin(ω x t + θ x ) u(t ) ≈

Because of the linearity of the system, the real and imaginary parts of the solution y will correspond to the real and imaginary parts of the complex x. Because we want the response to the real part (the cosine), we simply take the real part of the solution at the end.4 It is extremely useful to rewrite (3.11) as x (t ) = M x e jθx e (

σ x + jω x )t

u(t ) = M x e jθx e pxt u(t )

(3.12)

We shall call the complex number X = M x e jθx a generalized phasor for the sinusoid, noting that the quantity is a conventional phasor (see, e.g., [5]) when σx = 0 (i.e., when x represents an undamped def sinusoid). The complex frequency associated with the signal x is px = σx + jωx . Any signal that can be written as a sum of exponentials will be an eigensignal of a linear, time-variant (LTI) system such as the present circuit. The forced response of a system to an eigensignal is a scaled, time-shifted version of the eigensignal. This means that an eigensignal generally has its amplitude and phase altered by the system, but never its frequency! Many signals used in engineering analysis are eigensignals. This is the case with the present input x. Because x is an eigensignal, the nonhomogeneous solution will be of the form y (t ) = H ( px ) M x e σ xt e ≈

(

{

}) = M e jθy e Pxt y

j ω xt + θ x +arg H ( px )

(3.13)

where H (px) represents the amplitude scaling imposed upon a signal of complex frequency px , and arg {H (px)} is the phase shift. For the moment, do not be concerned about the seemingly excessive notation H (px) and arg{H (px)}. The number H(px) = H(px) e j arg{H(px )}, called the eigenvalue of the system for complex frequency px, is a package containing the scaling and phase change induced upon a def sinusoid or exponential input of complex frequency px. In (3.13) we have implicitly defined My = H (px) Mx and θy = θx + arg{H(px)}, noting that Y = M ye

jθ y

= H ( px ) M x e jθx = H ( px ) X

(3.14)

is the generalized phasor for the forced response y≈. Let us now put expressions (3.12) and (3.13) into the differential equation (3.1) [ignoring the u(t) because we are seeking a solution for t > 0]

4

Alternatively, we could also find the response x*(t), and average the two responses at each t.

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The Laplace Transform

M x e jθx e pxt = px2 LCM ye

+ px RCM ye

j θ y p xt

+ px RCM y e

jθ y

jθ y pxt

e

e

+ M ye

jθ y pxt

e

(3.15)

Dividing through by e px t (note this critical step), M x e jθx = px2 LCM y e

jθ y

+ Mye

jθ y

(3.16)

Isolating My e jθy on the left side of (3.16), we have

My e

jθ y

=

M x e jθx

(3.17)

LCpx2 + RCpx + 1

Because all quantities on the right are known, we can now solve for My and θy . For example (so that we can compare this result with future work), suppose we have system parameters L = 2H, C = 1 F, R = 1 Ω, y 0 = 12 V, i0 = 0 A

(3.18)

and signal parameters M x = 3 V,

σ x = − 0.1 s,

ω x = 1 rd s, θ x = π 4 rd

(3.19)

Then we find My e jθy = 2.076e –j (0.519 π). Whatever the specific numbers, let us now assume that My and θy are known. We have y (t ) = M ye y e ( ≈

jθ

σ x + jω x )t

(3.20)

Taking the real part,

(

y (t ) = M ye σ xt cos ω x t + θ y ≈

)

(3.21)

This nonhomogeneous solution is valid t > 0

Total Solution Combining the previous results, we obtain the complete solution for t > 0.

(

y (t ) = y˜ (t ) + y (t ) = 2 Ae σht cos(ω ht + θ A ) + M ye σ x t cos ω x t + θ y ≈

)

(3.22)

We must apply the initial conditions to find the unknown numbers A and θA. By a physical considerations we know y(0+) = y(0–) = y0 and i(0+) = i(0–) = i0, so

( )

y (0) = y 0 = 2 A cos(θ A ) + M y cos θ y

(3.23)

and i(0) = i0 = C

[

]

dy = 2 AC σ h cos(θ A ) − ω h sin(θ A ) dt t =0

[

]

+ M yC σ h cos(θ A ) − ω h sin(θ A ) © 2003 by CRC Press LLC

(3.24)

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These two equations can be solved for A and θA. For example, for the numbers given in (3.18) and (3.19), using (3.6) we find that ph = –1/4 + j 7/4 and A = 0.416 e j(0.230 π). Whatever the specific numbers, let us assume that A and θA are known. Then, putting all the known numbers back into (3.23) gives a complete solution for t > 0.

Scrutinizing the Solution The first term in the final solution, (3.22), comprises the unforced response and corresponds to the homogeneous solution of the differential equation in conjunction with the information provided by the initial conditions. Notice that this response involves only parameters dependent upon the circuit com­ ponents, e.g., σh and ωh, and information provided by the initial conditions, A = Ae jθA. The latter term in (3.22) is the forced response. We reemphasize that this part of the response, which corresponds to the nonhomogeneous solution to the differential equation, is of the same form as the forcing function x and that the system has only scaled and time-shifted (as reflected in the phase angle) the input. It is important to understand that the natural or unforced response is not altogether unrelated to the forcing function. The adjustment that the circuit must make (using its own natural modes) depends on the discrepancy at time zero between the actual initial conditions on the circuit components and the conditions the input would “like” to impose on the components as the forcing begins. Accordingly, we can identify two parts of the natural solution, one due to the initial energy storage, the other to the “shock” of the input at time zero. We can see this in the example above by reconsidering (3.23) and (3.24) and rewriting them as

( )

y 0 = 2Are + M y cos θ y

(3.25)

and

[

[

]

( )

( )]

i0 = 2 Are σ h − Aimω h + M y σ x cos θ y − ω x sin θ y C

(3.26)

Solving

Are =

Aim =

( )

y 0 M y cos θ y − 2 2 σ h y 0 − (i0 C ) 2ω h

+

(3.27)

( )

( )

M y cos θ y (σ x − σ h ) − M y sin θ y ω x 2ω h

(3.28)

We see that each of the real and imaginary parts of the complex number A can be decomposed into a part depending on initial circuit conditions, y0 and i0, and a part depending on the system’s interaction with the input at the initial instant. Accordingly, we may write A = Aic + Ainput

(3.29)

where Aic = Are, ic + jAim, ic and Ainput = Are, input + jAim, input. In polar form Aic = Aice jθAic and Ainput = Ainpute jθAinput . Therefore, the homogeneous solution can be decomposed into parts

(

y˜ (t ) = y˜ ic (t ) + y˜ input (t ) = 2 Aic e σht cos ω ht + θ Aic

(

+ 2 Ainput e σht cos ω ht + θ Ainput © 2003 by CRC Press LLC

)

)

(3.30)

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The Laplace Transform

Hence, we observe that a natural response may occur even if the initial conditions on the circuit are zero. The combined natural and forced response in this case, y≈(t) + y~input (t), is called the zero-state response to indicate the state of zero energy storage in the system at time t = 0. On the other hand, the response to initial energy only, y~ic, is called the zero-input response for the obvious reason.

Generalizing the Phasor Concept: Onward to the Laplace Transform To begin to understand the meaning of the LT, we reflect on the process of solving the circuit problem above. Although we could examine this solution deeply to understand the LT connections to both the natural and forced responses, it is sufficient for current purposes to examine only the forced solution. Because the input to the system is an eigensignal previously, we could assume that the form of y≈ would be identical to that of x, with modifications only to the magnitude and phase. In noting that both x and y≈ would be of the form Me jθ, it seems reasonable that the somewhat tedious nonhomogeneous solution would eventually reduce to an algebraic solution to find My and θy from Mx and θx. All information – – needed and sought is found in the phasor quantities X and Y in conjunction with the system informa­ tion. The critical step which converted the differential equation solution to an algebraic one comes in (3.16) in which the superfluous term e pxt is divided out of the equation. Also observe that the ratio H(px) = My e j θy/Mx e j θx depends only on system parameters and the complex frequency of the input, px = σx + jωx . In fact, this ratio, when considered a function, e.g., H, of a general complex frequency, say, s = σ + jω, is called the system function for the circuit. In the present example, we see that H (s ) =

1 LCs 2 + RCs + 1

(3.31)

The complex number H(s), s = σ + jω, contains the scaling and delay (phase) information induced by the system on a signal with damping σ and frequency ω. Let us now consider a slightly more general class of driving signals. Suppose we had begun the analysis above with a more complicated input of the form5 N

x (t ) = ∑ M ie σit cos(ω it + θi )

(3.32)

i=1

which, for convenience, would have been replaced by N

N

i=1

i=1

x (t ) = ∑ M ie jθi e ( σi + jωi )t = ∑ M ie jθi e pit

(3.33)

in the nonhomogeneous solution. It follows immediately from linearity that the solution could be obtained by entering each of the components in the input individually, and then combining the N solutions at the output. In each case we would clearly need to rid the analysis of the superfluous term of the form e pi t by division. This information is equivalent to the form e σi t cos(ω it) which is known to automatically carry through to the output. Now, recalling that Mi e jθi is the generalized phasor for the ith component in (3.33), let us rewrite this expression as N

x(t ) = ∑ X ( pi )e pit

(3.34)

i=1

5We omit the unit step u which appears in the input above because we are concerned only with the forced response for t > 0.

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The Circuits and Filters Handbook, Second Edition —

def

where X(pi) = Mi e jθi. Expression (3.34) is similar to a Fourier series (see Chapter 4), except that here (unless all σi = 0) the signal is only “pseudo-periodic” in that all of its sinusoidal components may be — decaying or expanding in amplitude. The generalized phasors X(pi) are similar to Fourier series coeffi­ cients and contain all the information (amplitude and phase) necessary to obtain steady-state solutions. These phasors comprise frequency domain information as they contain packets of amplitude and phase information for particular complex frequencies. With the concepts gleaned from this example, we are now prepared to introduce LT in earnest.

3.3 Formal Developments Definitions of the Unilateral and Bilateral Laplace Transforms Most signals used in engineering analysis and design of circuits and filters can be modeled as a sort of limiting case of (3.34). Such a representation includes not just several complex frequency exponentials as in (3.34), but an uncountably infinite number of such exponentials, one for every possible value of frequency ω. Each of these exponentials is weighted by a “generalized phasor” of infinitesimal magnitude. – The exponential at complex frequency s = σ + jω, for example, is weighted by phasor X(σ + jω)dω/2π, where the differential dω assures the infinitesimal magnitude and the scale factor of 2π is included by convention. The uncountably infinite number of terms is “summed” by integration as follows x (t ) =

∫

∞ −∞

X (σ + jω )

dω ( σ + jω )t e 2π

(3.35)

The number σ in this representation is arbitrary as long as the integral exists. In fact, if the integral converges for any σ, then the integral exists for an uncountable infinite number of σ. – The complex function X(σ + jω) in (3.35) is the Laplace transform (LT) for the signal x(t). Based on the foregoing discussion, we can interpret the LT as a complex-frequency-dependent, uncountable infinite set of “phasor densities” containing all the magnitude and phase information necessary to find forced solutions for LTI systems. We use the word “density” here to indicate that the LT at complex frequency σ + jω must be multiplied by the differential dω/2π to become properly analogous to a phasor. The LT, therefore has, for example, units volts per Hertz. However, we find that the LT is much more than just a phasor-like representation, providing a rich set of analysis tools with which to design and analyze systems, including unforced responses, transients, and stability. As in the preceding simpler examples, the solution of differential equations will be made easier by ridding the signals of superfluous complex exponentials of form e(σ + jω), that is, by working directly with LTs. Before doing so we change variables, to put (3.35) into a more conventional form. Let s denote the def general complex frequency s = σ + jω. Then x (t ) =

1 j2π

∫

σ + j∞ σ − j∞

X (s )e st ds

(3.36)

where we have dropped the bar over the LT, X. This integral, which we have interpreted as an “expansion” of the signal x in terms of an uncountably infinite set of infinitesimal generalized phasors and complex exponentials, offers a means for obtaining the signal x from the LT, X. Accordingly, (3.36) is known as the inverse Laplace transform (inverse LT). The inverse LT operation is often denoted

{ }

x (t ) =  −1 X (s )

(3.37)

How one would evaluate such an integral and for what values of s it would exist are issues we shall address later.

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In order to rid the the signal x of the superfluous factors est, we can simply compute the LT. Without any rigorous attempt to derive the transform from (3.36), it is believable that X (s ) =

∫

∞ −∞

x (t ) dt = e st

∞

∫

−∞

x (t )e −st dt

(3.38)

This is the bilateral, or two-sided, Laplace transform (BLT). The descriptor “bilateral” or “two-sided” is a referece to the fact that the signal may be nonzero in both positive and negative time. In contrast, the unilateral, or one-sided, Laplace transform (ULT) is defined as X (s ) =

∫

∞

0−

x (t ) dt = e st

∫

∞

0−

x (t )e −st dt

(3.39)

When a signal is zero all for t < 0, the ULT and BLT are identical. The same inverse LT, (3.36), is applied in either case, with the understanding that the resulting time signal is zero by assumption in the ULT case. While the BLT can be used to treat a more general class of signals, we find that ULT has the advantage of allowing us to find the component of the natural response due to nonzero initial conditions. In other words, ULT is used to analyze signals that “start” somewhere, a time we conventionally call6 t = 0. These transformations are reminiscent of the process of dividing through by the complex exponential which was first encountered in the forced solution in the motivating circuit problem [see (3.16)].

Existence of the Laplace Transform The variable s = σ + jω is a complex variable over which the LT is calculated. The complex plane with σ along the abscissa and jω on the ordinate, is called the s-plane. We find some powerful tools centered on the s-plane below. Note that the s-plane is not the LT, nor can the LT be “plotted” in the s-plane. The LT is a complex function of the complex variable s, and a plot of the LT would require another two dimensions “over” the s-plane. For this reason, we need to place some constraints on either s or X(s) or both to create a plot. For example, we could use the LT to plot X(jω) as a function of ω, by evaluating the magnitude of X(s) along the jω axis in the s-plane.7 An illustration of these points is found in Fig.3.2. We now address the question: For what values of s (i.e., “where” in the s-plane) does the LT exist? Consider first a two-sided (in time) signal, x. x is assumed piecewise continuous in every finite interval of the real line. We assert that the BLT X ordinarily exists in the s-plane in a strip of the form σ + < Re{s} = σ < σ −

(3.40)

as illustrated in Fig. 3.3. In special cases the BLT may converge in the half-plane σ+ < σ, or the half-plane σ < σ–, or even in the entire s-plane. The boundary values σ+ and σ– are associated with the positive-time and negative-time portions of the signal, respectively. The minimum possible value of σ+, and maximum possible value of σ–, are called the abscissas of absolute convergence. We henceforth use the notations σ+ and σ– to explicitly mean these extreme values. The vertical strip between but exclusive of, these abscissas is called the region of convergence (ROC) for the LT. In the special cases the ROC extends indefinitely from a single abscissa to the right (σ+ < σ) or left (σ < σ–) or covers the entire s-plane.

6

Note that if we apply the ULT to a signal x(t) that “starts” in negative time, the result will be identical to that for the signal x(t) u(t). 7This particular plot is equivalent to the magnitude spectrum of the signal that could be obtained using Fourier techniques discussed in Chapter 4.

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6 H(s) 5 4 3 2 1 0 −2

1.8 − 1.5

−1

− 0.5

1.2 0.6

0

0.5

Damping, σ

0

1

1.5

(a) 2

Frequency, ω

2

H( jω)

1.5

1

0.5

0 −2

− 1.5

−1

− 0.5 0 0.5 Frequency, ω (rad/sec)

(b)

1

1.5

2

FIGURE 3.2 The LT is called “H” instead of “X” in this figure for a reason to be discovered later. (a) A plot of H(s) vs. s for the LT H(s) = (0.5)/(s2 + 0.5s + 0.5). Only the upper-half s-plane is shown (ω ≥ 0). Note that the peak occurs near the value ph = –1/4 + j 7 /4, as a root of the denominator of H(s), which we shall later call a pole of the LT. The LT is theoretically infinite at s = ph . (b) Evaluation of H(s) along the jω axis (corresponding to σ = 0) with the magnitude plotted as function of ω.

To verify that (3.40) is a correct description of the ROC consider the positive-time part of x first. We maintain that X(s) will exist on any s such that Re{s} = σ > σ+, if and only if (iff) a positive M exists such x is bounded by Me σ+t on t ≥ 0, x (t ) < Me σ +t

t ≥0

Under this condition (letting X+ denote the LT of non-negative-time part of x),

© 2003 by CRC Press LLC

(3.41)

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The Laplace Transform

jω

s plane

ROC σ+

σ−

σ

FIGURE 3.3 Except in special cases, the region of con­ vergence for the BLT will be a vertical strip is the s-plane. This strip need not contain the jω axis as is the case in this illustration.

∞

X + (s ) =

∫ x(t )e

≤

∫ x(t )e

≤

∫ x(t ) e

−st

0

∞

−st

0

∞

dt

dt

−σt

dt
σ+  =  σ − σ+  otherwise ∞, If there is no finite, positive M such that (3.30) holds, then the signal grows faster than e –σ+t and the LT integral (area under x(t)e –σ+t e jωt) will not converge for at least some value of s in the neighborhood of the vertical line s = σ+. In this case, σ+ is not a proper abscissa. By similar means, we can argue that the negative-time part of x must be bounded as x (t ) < Me σ −t

t σ + iff a positive M exists such that (3.41) is met. This follows immediately from the fact that © 2003 by CRC Press LLC

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the ULT of x(t) is equivalent to the BLT of x(t)u(t). The “negative-time” part of x(t) yields X–(s) = 0 which converges everywhere in the s-plane. The ULT may also converge everywhere in the s-plane in special cases.

Example of Laplace Transform Computations and Table of Unilateral Laplace Transforms A listing of commonly used ULTs with ROCs is given in Table 3.1. Each entry in the table can be verified by direct computation of the appropriate LT integral, or in many cases, properties of the LT can be exploited to make the computation easier. These properties are developed in the section “Properties of the Laplace Transform.” It is rare to find a table of BLTs in engineering material because most of our work is done with the ULT. However, BLTs can often be found by summing the results of two ULTs in the following way. Suppose x is written as x (t ) = x + (t ) + x − (t )

(3.45)

where x+ and x– are the causal and anticasual parts of the signal, respectively. To obtain X+, we can use a ULT table. To obtain X–, note the following easily demonstrated property of the BLT: If {y(t)} = Y(s) with ROC {s : Re{s} > a}, then {y(–t)} = Y(–s) with ROC {s : Re{s} > – a}. Therefore, we can find {x–(–t)} in a ULT table, and replace the argument s by –s to obtain X–(s). The X(s) = X+(s) + X–(s). TABLE 3.1

Table of Unilateral Laplace Transform Pairs

Signal, x(t)

ULT, X(s)

ROC

d(t)

1

Entire s-plane

d δ dt k

sk

Entire s-plane

u(t)

1 s

k

t n−1 u(t ) e pxt u(t )

{s : σ > 0}

(n − 1)!

{s : σ > 0}

sn 1

{s : σ > σ }

(s − p )

x

x

t ne pxt u(t )

n!

(s − p ) s cos(θ ) − ω

{s : σ > σ }

n+1

x

x

cos(ω xt + θ x ) u(t ) e σ xt cos(ω xt + θ x ) u(t )

x

x 2 x

s +ω 2

sin(θ x )

(s − σ ) cos(θ ) − ω (s − σ ) + ω x

x

x

2

x

M xt n−1e σ xt cos(ω xt + θ x ) u(t )

E

(s − p ) x

n

+

sin(θ x )

n

{s : σ > σ } x

2 x

E *

 s − p*  x 

{s : σ > 0}

;

M x real and positive, E =

Mx (n − 1)!e jθx 2

{s : σ > σ } x

Note: In each entry, s is the general complex number σ + jω, and, where relevant, px is the specific complex number σx + jωx.

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This strategy is illustrated in Example 1. The ROC of the sum will ordinarily be the intersection of the individual LTs X+ and X–, but the total ROC may be larger than this if a pole-zero concellation occurs (see the next section). Let us consider some examples which illustrate the direct forward computation of the LT and the process discussed in the preceding paragraph. Example 1. Find the BLT and ULT for the signal x (t ) = Ae at u(−t ) + Be bt u(t )

A, B < ∞

(3.46)

Note that A, B, a, and b may be complex. Solution. In the bilateral case, we have X (s ) =

∫

0−

−∞

Ae at e −st + Ae (a −s )t a−s

=

 A , − = s−a ∞, 

∫

−∞

0−

+ −∞

0−

Be bt e −st dt

Be (b−s )t b−s

∞

0−

 Re{s} < Re{a}   otherwise 

(3.47)

 B   s − b , Re{s} > Re{b} +  ∞, otherwise   The ROC for this LT is {s : Re{b} < Re{s} < Re{a}}. The LT does not exist for any s for which Re{s} ≥ Re{a} or Re{s} ≤ Re{b}. Note also that when Re{b} ≥ Re{a}, then no ROC can be found, meaning that the BLT does not exist anywhere for the signal. The ULT follows immediately from the previous work. We have

X (s ) =

∫

∞ bt

Be e 0−

−st

 B ,  dt =  s − b  ∞,

Re{s} > Re{b}

(3.48)

otherwise

The ROC in this case is {s : Re{s} > Re{b}}. We need not be concerned about the negative-time part of the signal (and the associated ROC) because the LT effectively zeros the signal on t < 0. Note. The result of this example is worth committing to memory because it will reappear frequently. Note that if we had found the ULT, (3.48), for the casual part of x in a table [call it X+(s)], then we could employ the trick suggested above to find the LT for the anticausal part. Let x– denote the negative­ time part: x–(t) = Aeatu(–t). We know that the LT of x–(–t) = Ae–atu(t) (a casual signal) is X − (−s ) =

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A , s+a

{

}

with ROC s : Re{s} > − a

(3.49)

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Therefore, X − (s ) =

−A , s−a

{

}

with ROC s : Re{s} < a

(3.50)

The overall BLT result is then X(s) = X+(s) + X–(s) with ROC equal to the intersection of the individual results. This is consistent with the BLT found by direct integration. ▫ The preceding simple example suggests that the BLT can treat a broader class of signals at the expense of greater required care in locating its ROC. A further and related complication of the BLT is the nonuniqueness of the transform with respect to the time signals. Consider the following example. Example 2. Find the BLT for the following signals: x1 (t ) = e bt u(t ) and x 2 (t ) = − e bt u(−t )

(3.51)

Solution. From our work in Example 1, we find immediately that X1 (s ) =

1 , Re{s} > Re{b} and s−b

(3.52)

1 X 2 (s ) = , Re{s} < Re{b} s−b Neither X1 not X2 can be unambiguously associated with a time signal without knowledge of its ROC.

▫

Another drawback of the BLT is its inability to handle initial conditions in problems like the one that motivated our discussion. For this, reason, and also because signals tend to be casual (occuring only in positive time) in engineering problems, the ULT is more widely used and we shall focus on it exclusively after treating one more important topic in the following section. Before moving to the next section, let us tackle a few more example computations. Example 3. Find the ULT of the impulse function, δ(t) (see Section 3.6, Appendix A). Solution. ∆(s ) =

∞

∫ δ(t )e

−st

0−

dt = 1 for all s

(3.53)

The LT converges everywhere in the s-plane. We note that the lower limit 0– is important here to yield the answer 1 (which will provide consistency of the theory) instead of 1/2. ▫ Example 4. Find the ULT of the unit step function, u(t) [see (3.3)]. Solution. U (s ) =

∫

∞ 0−

1e

−st

−e −st dt = s

∞

= 0−

1 s

for Re{s} > 0

The ROC for this transform consists of the entire right-half s-plane exclusive of the jω axis.

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(3.54) ▫

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Example 5. Find the ULT of the damped (σx < 0), undamped (σx = 0), or expanding (σx > 0) sinusoid, x(t ) = M x e σxt cos(ω x t + θ x )u(t ). Solution. Using Euler’s relation, write x as x (t ) =

[

]

M x σ xt j (ω xt +θx ) M − j ω t +θ e e + e ( x x) = x 2 2

e jθx e pxt + e − jθx e p*x t   

(3.55)

def

with px = σ x + jω x . Taking the LT, X (s ) = =

Mx 2

∫

∞

0−

∫

∞

 −st  jθx pxt − jθ x p* xt e e + e e  e dt

0−

M x jθx pxt −st e e e dt + 2

∫

∞

0−

(3.56)

M x − jθx p*x t −st e e e dt 2

Now using (3.48) on each of the integrals X (s ) =

(M x 2) e jθ ( s − px )

x

+

(M x 2) e − jθ

x

(3.57)

(s − p ) * x

with the ROC associated with each of the terms being Re{s} > Re{px} = σx. Putting the fractions over a common denominator yields X (s ) =

=

(

)

jθ − jθ M x  s − px* e x + (s − px ) e x    2  s − px ) s − px*  (  

(

)

(

jθ − jθ − jθ * jθ M x  se x + se x − px e x − px e x  2 2  s 2 − 2Re{ px }s + px 

) 

(3.58)

 

 (s − σ ) cos (θ ) − ω sin(θ )  x x x x  = Mx  2 2   s − + σ ω ( ) x x   The ROC of X is {s : Re{s} > σx}. Note. The chain of denominators in (3.58) is worth noting because these relations occur frequently in LT work.

(s − px ) (s − px* ) = s 2 − 2 Re{px }s + px

2

= s 2 − 2σ x s + px = (s − σ x ) + ω x2 2

2

(3.59) ▫

Poles and Zeros — Part I “Pole-zero” analysis is among the most important uses of the LT in circuit and system design and analysis. We need to take a brief look at some elementary theory of functions of complex variables in order to carefully describe the meaning of a pole or zero. When we study methods of inverting the LT in a future section, this side trip will prove to be especially useful.

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Let us begin with a general function, F, of a complex variable s. We stress that F(s) may or may not be a LT. F is said to be analytic at s = a if it is differentiable at a and in a neighborhood of a. For example, F(s) = s – 1 is analytic everywhere (or entire), but G(s) = s is nowhere analytic because its derivative exists only at s = 0. On the other hand, a point p is an isolated singular point of F if the derivative F does not exist at p, but F is analytic in a neighborhood of p. The function F(s) = e–s/(s – 1) has a singular point at s = 1. There is a circular analytic domain around any singular point, p, of F, say {s:s – p < p}, in which the function F can be represented by a Laurent series [3], ∞

∞

F (s ) = ∑ qi , p (s − p) + ∑ i

i=1

i=0

ri , p

(s − p)i

(3.60)

The second sum in (3.60) is called the principle part of the function F at p. When the principle part of F at p contains terms up to order n, the isolated singular point p is called an nth-order pole of F. Evidently from (3.60), F tends to infinity at a pole and the order of infinity is n. For future reference, we note that def the complex number rp = r1, p is called the residue of F at s = p. A zero of F is more simply defined as a value of s, say z, at which F is analytic and for which F(z) = 0. If all the derivatives up to the (m – 1)st are also zero at z, but mth is nonzero, then z is called an mth­ order zero of F. It can be shown that the zeroes of an analytic function F are isolated, except in trivial case F(s) = 0 for all s [3]. Most LTs encountered in signal and system problems are quotients of polynomials in s, say X (s ) =

N (s ) D(s )

(3.61)

because of the signals employed in engineering work, and because (as we shall see later) rational LTs are naturally associated with LTI systems. N and D connote “numerator” and “denominator.” In this case both N and D are analytic everywhere in the s-plane, and the poles and zeroes of X are easily found by factoring the polynomials N and D, to express X in the form  nN X (s ) = C  ∏(s − z i )  i=1

nD



i=1



∏(s − pi )

(3.62)

where nN is the number of simple factors in N(s) (order of N in s), nD the number of simple factors in D(s) (order of D in s), and C is a constant. X is called a proper rational LT if nD > nN . After canceling all factors common to the numerator and denominator, if m terms (s – z) are left in the numerator, then X has an mth order zero at s = z. Similarly, if n terms (s – p) are left in the denominator, then X has an nth order pole at s = p. Although the LT does not exist outside the ROC, all of the poles will occur at values of s outside the ROC. None, some, or all of the zeros may also occur outside the ROC. This does not mean that the LT is valid outside the ROC, but that its poles and zeroes may occur there. A pole is ordinarily indicated in the s-plane by the symbol ×; whereas a zero is marked with a small circle . Example 6. Find the poles and zeros of the LT X (s ) =

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3s 2 + 9s + 9

(s + 2) (s 2 + 2s + 2)

(3.63)

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59

The Laplace Transform

jω

s plane

2

× −2

×

1

−1

0

×

−1

1

2

σ

−2

FIGURE 3.4 Pole-zero diagram for Example 6.

Solution. Factoring the top and bottom polynomials to put X in form (3.62) we have X (s ) = 3

(s + (3 − j 3 ) 2)(s + (3 + j 3 ) 2) (s + 2) (s + 1 + j) (s + 1 − j)

(3.64)

There are first-order zeros at s = (−3 + j 3) 2 and s = (−3 − j 3 ) 2 , and first order-poles at s = – 2, s = –1 + j , and s = –1 – j. The pole-zero diagram appears in Fig. 3.4. Two points are worth noting. First, complex poles and zeros will always occur in conjugate pairs, as they have here, if the LT corresponds to a real signal. Second, the denominator of (3.64) also can be expressed as (s + 2)[(s + 1)2 + 1] [recall (3.59)]. Comparing this form with the LT obtained in Example 5 suggests that the latter form might prove useful. ▫ The purpose of introducing poles and zeros at this point in our discussion is to note the relationship of these singularities to the ROC. The preceding examples illustrate the following facts: 1. For a “right-sided” (non-negative-time only) signal, x, the ROC of LT X (either ULT or BLT) is {s : Re{s} > Re{p+} = σ+}, where p+ is the pole of X with maximum real part, namely, σ+. If X has no poles, then the ROC is the entire s-plane. 2. For a “left-sided” (negative-time only) signal, x, the ROC of BLT X is {s: Re{s} < Re{p–} = σ–}, where p– is the pole of X with minimum real part, namely, σ–. If X has no poles, then the ROC is the entire s-plane. 3. For a “two-sided” signal x, the ROC of the BLT X is {s : Re{p+} = σ+ < Re{s} < Re{p–} = σ–} where p+ is the pole of maximum real part associated with the right-sided part of x, and p– is the pole of minimum real part associated with the left-sided part of x. If the right-sided signal has no pole, then the ROC extends indefinitely to the right in the s-plane. If the left-sided signal has no pole, then the ROC extends indefinitely to the left in the s-plane. Therefore, if neither part of the signal has a pole, then the ROC is the entire s-plane. Let us revisit three of the previous examples to verify these claims. In Example 1, we found the ROC for the BLT to be {s : Re{b} < Re{s} < Re{a}}. The only pole associated with the left-sided sequence is at s = a. The only pole associated with the right-sided signal occurs at s = b. Following rule 3 in the list above yields exactly the ROC determined by analytical means. The poles of X as well as the ROC are shown in Fig. 3.5(a).

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jω

jω

jω

ROC

ROC

×

ROC

jωx

× a σ

b ×

×

σ

σx

σ −jωx

×

(a)

(b)

(c)

FIGURE 3.5 Pole-zero plots ROCs for the LTs of (a) Example 1, (b) Example 4, and (c) Example 5.

In Example 4, we found the ROC to be the entire right-half s-plane, exclusive of the jω axis. The single pole of U(s) = 1/s occurs at s = 0. Figure 3.5(b) is consistent with rule 1. The ULT of Example 5 has poles at s = σx ± jωx and a zero at s = σx + ωx tan(θx). Rule 1 therefore specifies that the ROC should be {s : Re{s} > Re{σx ± jωx} = σx}, which is consistent with the solution to Example 5. The pole-zero plot and ROC are illustrated in Fig. 3.5(c).

Properties of the Laplace Transform8 This section considers some properties of the LT which are useful in computing forward and inverse LTs, and in other manipulations occurring in signal and system design and analysis. A list of properties appears in Table 3.2. In most cases, the verification of these properties follows in a straightforward manner from the definition of the transform. Consider the following examples. For convenience, we define the notation x (t ) ↔ X (s )

(3.65)

to mean that x and X are an LT pair, X(s) = {x(t)}. Example 7. Verify the modulation property of the LT which states that if x(t) ↔ X(s), then e s0t x(t) ↔ X(s – s0). Solution. By definition,

{

} ∫

 e s 0 t x (t ) = =

0

∫

∞ −

∞

0−

e s0t x (t ) e −st dt (3.66) x (t )e

dt = X (s − s0 )

− ( s −s0 )

▫ 8

Henceforth, this study restricts attention to the ULT and uses the acronym “LT” only.

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TABLE 3.2

Operational Properties of the Unilateral Laplace Transform

Description of Operation

Formal Operation

Corresponding LT

Linearity

αx (t ) + βy (t )

αX ( s ) + βY ( s )

Time delay (t0 > 0)

x (t − t 0 ) u(t − t 0 )

e −st 0 X ( s )

Exponential modulation in Time (or complex frequency (“s”) shift)

e s0t x (t )

X ( s − s0 )

Multiplication by t k, k = 1, 2, …

t k x (t )

(−1)

Time differentiation

dk x dt k

s k X (s) −

k

dk X ds k k −1

∑s x dix dt i

x (i ) (0 − ) def =

∫

Time integration

t

−∞

i ( k −1−i )

(0 − )

i=0

X (s)

x (λ ) d (λ )

−1 x ( ) (0 − ) s

+

s

t =0−

t

( ) ∫ x(λ)d(λ)

x ( −1) 0 − =

def

Convolution

∫

∞

∫

∞

0

Correlation

0

x (λ ) y(t − λ )dλ

X (s)Y (s)

x (t ) y (t + τ)dt

X ( s )Y ( − s )

∫

σ+ j ∞

−∞

x (t ) y (t )

1 j2π

Initial signal value (if time limit exists)

limt →0+ x (t )

lim s→∞ sX ( s )

Final signal value (if time limit exists)

limt →∞ x (t )

lim s→0 sX ( s )

Time scaling

x (αt ), α > 0

1  s X  α  α 

Periodicity (period T)

∑ x(t − iT )

Product (s-domain convolution)

X (s)

∞

X (λ )Y ( s − λ )dλ



(1 − e ) −sT

i =0

x (t ) = 0,

σ− j ∞

t =0−

[ ]

t ∉ 0, T

Note: Throughout, X and Y are LTs of signals x and y, respectively; x and y are casual signals.

Example 8. Verify the periodicity property and find the LT for a square wave of period T = 2 and duty cycle 1/2. Solution. Using the linearity and time-delay properties of the LT  ∞   x (t − iT ) =  i=0 

∑

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∞

∑ X(s)e i=0

−siT

∞

∑e

= X (s )

i=0

−siT

=

X (s )

(1 − e ) −sT

(3.67)

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z(t)

0

1

2

3

4

5

t

FIGURE 3.6 Square wave of Example 8.

Let us call the square wave z(t) and its LT Z(s). Now one period of z can be written as x(t) = u(t) – u(t – 1), 0 ≤ t < 2 (see Fig. 3.6). Using the delay property, therefore, X(s) = (1/s) – (e–s/s). Using (3.67) with T = 2, we have Z (s ) =

(1 s) − (e −s s) (1 − e −s ) =

(1 − e )

(

−2s

s 1 − e −2s

(3.68)

)

▫

Example 9. Verify the time-differentiation property of the LT which states that if x(t ) ↔ X (s), then dx / dt ↔ sX (s) − x(0 − ). Solution. By definition, {dx/dt} =

∞

∫ (dx dt )e

−st

dt. Integrating by parts yields

0−

dx    = x (t )e −st  dt 

∞ 0

−

+s

∫

∞

0−

( )

x (t )e −st dt = sX (s ) − x 0 −

(3.69) ▫ +

Example 10. Verify the initial value theorem of the LT which states that if x(0 ) = limt↓0 x(t ) < ∞ , then lim s→∞ sX (s) = x(0+ ). Solution. In case a discontinuity exists in x at t = 0, define the signal y (t ) = x (t ) − cδ(t )

(3.70)

where c is the amplitude shift at the discontinuity, c = x(0+) – x(0–). Then y will be continuous at t = 0 (see Fig. 3.7). Further, dx dy = + cδ(t ) dt dt

(3.71)

so that using the time-differentiation property and the fact that {cδ(t)} = c, we have

( ) ∫

sX (s ) − x 0 − =

∞

0−

dy −st e dt + c dt

(3.72)

Because c = x(0+) – x(0–), sX (s ) =

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∫

∞

0−

( )

dy −st e dt + x 0 + dt

(3.73)

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The Laplace Transform

x(t) c y(t) t

FIGURE 3.7 The signals x and y used in Example 10.

Assuming that the LT of the signal y has a ROC (y is of exponential order), the integral in (3.73) vanishes ▫ as s → ∞. Finally, therefore, we obtain that lims→∞ sX (s) = x(0+). Example 11. Verify the convolution property of the LT which states that if x and h are casual signals with x(t) ↔ X(s), and h(t) ↔ H(s), then x (t ) ∗ h(t ) =

∫

∞

−∞

x (ξ)h (t − ξ)dξ ↔ X (s )H (s )

(3.74)

Solution. Because x(t) = 0 for t < 0, we can write

∫

∞

−∞

x(ξ)h (t − ξ) dξ =

∫

∞

0−

x (ξ) h (t − ξ) dξ

(3.75)

Now   

 x (ξ)h(t − ξ)dξ  = −∞ 

∫

∞

∞

∫∫

∞

0−

0−

∞

∞

0−

0−

=

∫∫

=

∫

0

∞ −

x (ξ)h(t − ξ)e −st dξdt x (ξ)h(β)e −sβe −sξdβd ξ

x (ξ)e −sξdξ

∫

0

∞ −

(3.76)

x (β)e −sβdβ

= X (s )H (s ) The causality of h is used in line (3.76) in setting the lower limit of integration over β to 0–.

▫

The operational properties are used to simplify forward and inverse transform computations and other manipulations involving transforms. To briefly illustrate, three examples follow. Example 12. Using operational properties, rederive the LT for x(t) = Mx cos(ωxt + θx )u(t), which was first considered in Example 5. Solution. Write x as x (t ) =

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M x jθx ( σ x + jω x )t M σ − jω t e e u(t ) + x e − jθx e ( x x ) u(t ) 2 2

(3.77)

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The linearity property allows us to ignore the factors Mxe ± jθx in the process of taking the transform, and returning them afterward. Recalling the previous result, (3.48), we can write immediately

{

}

1 , s − (σ x + jω x )

Re{s} > σ x

(3.78)

{

}

1 , s − (σ x − jω x )

Re{s} > σ x

(3.79)

σ + jω t  e ( x x ) u(t ) =

σ − jω t  e ( x x ) u(t ) =

so M x j θx 1 e 2 s − (σ x + jω x )

X (s ) =

(3.80)

M 1 + x e − j θx 2 s − (σ x − jω x )

Re{s} > σ x

Placing the fractions over a common denominator yields the same result as that found using direct integration in Example 5. Example 13. Find the time signals corresponding to the following LTs: X (s ) = e −πs

for all s

Y (s ) = log(7)

e −32s , s

Z (s ) =

e 2s 3 , + s+5 s−5

Re{s} > 0

(3.81)

Re{s} > 5

Solution. Recognize that X(s) = e–πs∆(s), where ∆(s) = 1 is the LT for the impulse function δ(t). Using the time-shift property, therefore, we have x(t) = δ(t – π). Recognize that Y(s) = log(7)e–32s U(s) where U(s) = 1/s is the LT for the step function u(t). Using linearity and the time-shift properties, therefore, y(t) = log(7) u(t – 32). In finding z, linearity allows us to treat the two terms separately. Further, from (3.48), we know that –1{1/(s – 5)} = e–5tu(t) and –1{1/(s – 5)} = e5tu(t). Therefore, x(t) = e–5(t+ 2)u(t + 2) + 3e5t u(t). Note that the first term has a ROC {s: Re{s} > –5}, while the second has ROC {s : Re{s} < 5}. The overall ROC is therefore consistent with these two components. ▫

Inverse Laplace Transform In principle, finding a time function corresponding to a given LT requires that we compute the integral in (3.36): x (t ) =

1 j2π

∫

σ + j∞

σ − j∞

X (s ) e st ds

(3.82)

Recall that σ is constant and taken to be in the ROC of X. Direct computation of this line integral requires a knowledge of the theory of complex variables. However, several convenient computational procedures are available that circumvent the need for a detailed understanding of the complex calculus. These measures are the focus of this section. The reader interested in more detailed information on complex variable theory is referred to [3]. “Engineering” treatments of this subject are also found in [10]. © 2003 by CRC Press LLC

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We first study the most challenging of the inversion methods, and the one that most directly solves the inversion integral above. The reader interested in quick working knowledge of LT inversion might wish to proceed immediately to the section on partial fraction expansion. Residue Theory It is important to be able to compute residues of a function of a complex variable. Recall the Laurent series expansion of a complex function, say, F, which was introduced in “Poles and Zeros — Part I,” equation (3.60). Also, recall that the coefficient r1,p is called the residue of F at p, and that we defined def the simplified notation rp = r1,p to indicate the residue because the subscript “1” is not useful outside the Laurent series. In the analytic neighborhood of singular point s = p (an nth-order pole) we define the function ϕ p (s ) = (s − p) F (s ) = r1, p (s − p) n

n−1

∞

+ r2, p (s − p)

n−2

+ L + rn, p +

∑ q ( s − p)

n+i

i, p

(3.83)

i=0

in which it is important to note that rn, p ≠ 0. Because F is not analytic at s = p, ϕp is not defined, and is def therefore not analytic, at s = p. We can, however, make ϕp analytic at p by simply defining ϕp(p) = rn,p . In this ϕp is said to have a removable singular point (at p). Note that (3.83) can be interpreted as the Taylor series expansion of ϕp about the point s = p. Therefore, the residue is apparently given by ϕ (pn−1) ( p)

def

rp = r1, p =

(3.84)

(n − 1)!

where ϕ(pi ) indicates the ith derivative of ϕp . When n = 1 (first-order pole), which is frequently the case in practice, this expression reduces to rp = ϕ p ( p) = lim(s − p) F (s )

(3.85)

s→ p

The significance of the residues appears in the following key result (e.g., see [3]): Theorem 1 (Residue Theorem): Let C be a simple closed contour within and on which a function F is analytic except for a finite number of singularity points, p1, p2, …, pk interior to C. If the respective residues at the singularities are rp1, rp2 , …, rpk , then

∫ F (s)ds = j2π (r

+ rp2 + L + rpk

p1

C

)

(3.86)

where the contour C is traversed in the counterclockwise direction. The relevance of this theorem in our work is as follows: In principle, according to (3.82), we want to integrate the complex function F (s) = X (s)e st on some vertical line in the ROC, for example, c − j∞ to c + j∞ , where c > σ+. Instead, suppose we integrate over the contour shown in Fig. 3.8. By the residue theorem, we have

∫ X (e)e ds = j2π (r st

p1

C

+ rp 2 + L + rpk

)

(3.87)

where rp1, rp2, …rpk are the k residues of the function X(s)e st. The integral can be decomposed as

∫ X (s)e ds = ∫ st

C

© 2003 by CRC Press LLC

C1

X (s ) e st ds +

∫

C2

X (s ) e st ds

(3.88)

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jω c + jp ROC C2

C1 σ=c

σ+

σ

c − jp

FIGURE 3.8 Contour in the s-plane for evaluating the inverse LT.

where, as ρ → ∞ , C1 approaches the line over which we wish to integrate according to (3.82). It can be shown1 that the integral over C2 contributes nothing to the answer for t > 0, provided that X approaches zero uniformly2 on C2. Therefore, lim

∫ X (s ) e

ρ→∞ C

st

ds = lim

∫

ρ→∞ C 1

X (s ) e st ds

1 = lim ω→∞ j2π

∫

c + jω

c − jω

(3.89) X (s ) e ds st

From (3.87), we have 1 j2π

∫

σ + j∞

σ − j∞

X (s ) e st ds = rp1 + rp 2 + L + rp k ,

t >0

(3.90)

Thus, recalling that the left side is the original inversion integral, we have x (t ) =

k

∑r , pi

t >0

(3.91)

i=1

where the rpi are the residues of X(s)est at its k singular points. Note that the residue method returns a time function only over the positive time range. We might expect a result beginning at t = 0 or t = 0– because we have defined the forward LT as an integral beginning at t = 0–. The reason for this lower limit is so that an impulse function at the time origin will be transformed “properly.” Another important place at which the initial condition “x(0–)” appears is in the LT of a differentiated time function (see Table 3.2 and Example 9). Again, the condition is included to properly handle the fact that if x has a discontinuity at t = 0, its derivative should include an impulse and the LT of the derivative should include a corresponding constant. The residue cannot properly invert LTs of impulse functions (constants over the s-plane) because such LTs do not converge uniformly to zero over the semicircular part of the contour C2. Such constants in the LT must be inverted in a more ad hoc way. If no apparent impulses occur and the residue method has provided x for t > 0, it is, in fact, possible, to assign an arbitrary finite value to x(0). This is because one point in the time signal will not 1

A rigorous mathematical discussion appears in [3], while a particularly clear “engineering” discussion appears in Appendix B of [6]. 2At the same rate regardless of the angle considered along C . 2 © 2003 by CRC Press LLC

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affect the LT, so the proper correspondence between x and X remains.11 If it is necessary to assign a value def to x(0), the most natural procedure is to let x(0) = x(0+). Then when we write the final answer as x(t) = [time signal determined by residues] u(t), the signal takes an implied value x(0+ ) 2 at t = 0. The preceding discussion emphasizes that, in general, successful application of the residue method depends on the uniform convergence of the LT to zero on the contour segment C2. In principle each LT to be inverted must be checked against this criterion. However, this seemingly foreboding process is usually not necessary in linear signal and system analysis. The reason is that a practical LT ordinarily will take the form of a ratio of polynomials in s like (3.61). The check for proper convergence is a simple matter of assuring that the order of the denominator in s exceeds that of the numerator. When this not the case, a simply remedy exists which we illustrate in Example 15. Another frequent problem is the occurrence of a LT of form X (s ) =

N (s )e st0 , D(s )

t0 < 0

(3.92)

where N and D are polynomials. The trick here is to recognize the factor e st0 as corresponding to a time shift which can be taken care of at the end of the problem, once the rational part of the transform is inverted. Finally, we remark that similar results apply to the bilateral LT. When the signal is two-sided in time, the casual part is obtained using the procedure above, but including only residues of poles known to be associated with the non-negative-time part of the signal. The noncausal part of the signal is found by summing residues belonging to “noncausal” poles. Note that the association of poles with the casual and noncausal parts of the signal follows from a specification of the ROC. Poles belonging to the causal signal are to the left of the ROC, while noncausal poles are to the right. Let us now illustrate the procedure with two examples. Example 14. In Example 5, we showed that  (s − σ ) cos(θ ) − ω sin(θ )  x x x x   M x e σ xt cos(ω x t + θ x ) u(t ) = M x  2 2   − + s σ ω ( ) x x  

{

}

(3.93)

with ROC {s : Re{s} > σx}. Verify that this is correct by finding the inverse LT using residues. Call the signal x and LT X. Solution. We can ignore the scalar Mx until the end due to linearity. Two poles are in the transform: px = σ x + jω x and px* = σ x − jω x (k = 2 in the discussion above). These can be obtained by expanding the denominator and using the quadratic equation, but it is useful to remember the relationship between a quadratic polynomial written in this form and the conjugate roots [recall (3.59)]. The residue for the pole at px is given by ϕ px ( px ) = X (s )e st (s − px )

11

s = px

=

[(s − σ ) cos(θ ) − ω sin(θ )] e x

x

(s − p )

x

st

x

* x

s = px

=

[( p

=

[( jω ) cos(θ ) − ω sin(θ )] e (

x

]

− σ x ) cos(θ x ) − ω x sin(θ x ) e pxt

(

x

x

px − px* x

)

(2jω x )

x

σ x + jω x )t

In fact, any two signals that differ only on a set of measure zero (e.g., see [7]) will have the same LT.

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(3.94)

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Similarly, we have for the pole at px* , ϕ p* (px* ) = [(− jω x ) cos(θ x ) − ω x sin(θ x )]e (σx − jω x )t (−2 jω x ). For t > 0, x therefore, x (t ) = ϕ px ( px ) + ϕ p* px* x Mx

( )

=

[

(

)

(

e σ xt jω x cos(θ x ) e jω xt + e − jω xt − ω x t sin(θ x ) e jω xt − e − jω xt 2jω x

[

]

)]

= e σ xt cos(θ x ) cos(ω x t ) − sin(θ x ) sin(ω x t ) = e σ xt cos(ω x t + θ x )

(3.95)

(3.96) ▫

and the transform is verified.

The following example illustrates the technique for handling polynomial quotients in which the order of the denominator does not exceed the numerator (X is not a proper rational LT). Example 15. Find the causal time signal corresponding to LT X (s ) =

N (s ) Gs 2 = , D(s ) (s − p)2

G, p are real

(3.97)

Solution. To use the residue method, we must reduce the order of the numerator to at most unity. By dividing polynomial D and N using long division, we can express X as X (s ) = G +

2Gps − Gp 2

( s − p)

2

= X1 (s ) + X 2 (s )

def

(3.98)

First note that we can use linearity and invert the two terms separately. The first is simple because (see Table 3.1, –1{X1(s)} = –1{G} = Gδ(t). In the second term we find a pole of order n = 2 at s = p. To use (3.84) to compute the residue, we require ϕ p (s) = X 2 (s)e st (s − p)2 = 2Gps − Gp 2 e st . Then, for t > 0, the residue is

[

rp =

1 dϕ p 1! ds

s= p

[

]

]

= G 2pe pt + 2p 2te pt − p 2te pt = Gpe pt [2 + pt ]

(3.99)

Because rp is the only residue, we have x(t ) = Gδ(t ) + Gpe pt [2 + pt ] u(t ). Remark. If the order of the numerator exceeds the denominator by k > 0, the long division will result in a polynomial of the form Aks k + Ak – 1s k – 1 + L + A0. Consequently, the time domain signal will contain derivatives of the impulse function. In particular, if k = 1, and a “doublet” will be present in the time signal. (See Table 3.1 and Appendix A for more information.) ▫ We can usually find several ways to solve inverse LT problems, residues often being among the most challenging. In this example, for instance, we could use (3.98) to write X (s ) = G +

2Gps

( s − p)

2

−

Gp 2

( s − p) 2

= G + X 3 (s ) − X 4 (s )

(3.100)

then use Table 3.1 to find –1{G} = Gδ(t) and –1{X4} = x4(t) [or use residues to find x4(t)]. Noting that X3(s) = 2 psX4(s), we could then use the s-differentiation property (Table 3.2) to find x3 from x4. This alternative solution illustrates a general method that ordinarily is used regardless of the fundamental © 2003 by CRC Press LLC

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The Laplace Transform

inversion technique. Linearity allows us to divide the problem into a sum of smaller, easier problems to invert, and then combine solutions at the end. The method presented next is probably the most popular, and clearly follows this paradigm. Partial Fraction Expansion The partial fraction expansion (PFE) method can be used to invert only rational LTs, with the exception that factors of the form est0 can be handled as discussed near (3.92). As noted previously, this is not practically restricting for most engineering analyses. Partial fraction expansion is closely related to the residue method, a relationship evident via our examples. As in the case of residues, a rational LT to be inverted must be proper, having a numerator polynomial whose order is strictly less than that of the denominator. If this is not the case, long division should be employed in the same manner as in the residue method (see Example 15). Consider the LT X(s) = N(s)/D(s). Suppose X has k poles, p1, p2, …, pk and D is factored as D(s ) = (s − p1 ) 1 (s − p2 ) 2 L (s − pk ) k n

n

n

(3.101)

k where ni is the order of the ith pole. (Note that Σ i=1 ni = nD.) Now if x is a real signal, the complex poles will appear in the conjugate pairs. It will sometimes be convenient to combine the corresponding factors into a quadratic following (3.59),

(s − p) (s − p *) = s 2 + βs + γ = s 2 − Re{p}s + p 2 = s 2 − 2σ ps + p 2

(3.102)

for each conjugate pair. Assuming that the poles are ordered in (3.101) so that the first k′ are real and the last 2k″ are complex (k = k′ + 2k″), D can be written

(

D(s ) = (s − p1 ) re,1 (s − p2 ) re,2 L (s − pk′ ) re,k ′ s 2 + β1s + γ 1 n

(

× s 2 + β 2s + γ 2

n

)

nc,2

n

(

L s 2 + βk′′ s + γ k′′

)

nc,1

)

(3.103)

nc ,k ′′

Terms of the form (s – p) are called simple linear factors, while those of form (s2 + βs + γ) are simple quadratic factors. When a factor is raised to a power greater than one, we say that there are repeated linear (or quadratic) factors. We emphasize that linear factors need not always be combined into quadratics when they represent complex poles. In other words, in the term (s – pi)ni, the pole pi may be complex. Whether quadratics are used depends on the approach taken to solution. The idea behind PFE is to decompose the larger problem into the sum of smaller ones. We expand the LT as X (s ) =

N (s ) N (s ) = D(s ) factor1factor2 L factork′ factork′ +1 L factork′+k′′

N (s ) N (s ) N (s ) N (s ) = 1 + 2 + L + k′ + k′+1 factor1 factor2 factork′ factork′ +1 +

N k′+k′′ (s ) factork′+k′′

(3.104)

(3.105)

Now, because of linearity, we can invert each of the partial functions in the sum individually, then add the results. Each of these “small” problems is easy and ordinarily can be looked up in a table or solved by memory.

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We now consider a series of cases and examples. Case 1: Simple Linear Factors. Let X(s) = N(s)/D(s). Assume that the order of N is strictly less than the order of D. Without loss of generality (for the case under consideration), assume that the first factor in D is a simpler linear factor so that D can be written D(s) = (s – p1)Dother (s) where Dother is the product of all remaining factors. Then the PFE will take the form X (s ) =

N (s ) N (s )

= = D(s ) (s − p1 ) Dother (s )

(3.106)

N1 (s ) + other PFs corresponding to factors in Dother (s ) s ( − p1 )

[

]

Now note that

(s − p1 )X (s) = DN (s()s) = other

[

]

(3.107)

N1 (s ) + (s − p1 ) other PFs corresponding to factors in Dother (s ) Letting s = p1 reveals that N1 ( p1 ) = A1 =

N ( p1 )

Dother ( p1 )

[

]

= (s − p1 ) X (s )

(3.108) s = p1

Note that the number A1 is the residue of the pole at s = p1. In terms of our residue notation ϕ p1 (s ) = (s − p1 ) X (s ) =

N (s ) Dother (s )

and rp1 = A1 = ϕ p1 ( p1 )

(3.109)

Carefully note that we are computing residues of poles of X(s), not X(s)est, in this case. Example 16. Given LT X (s ) =

s 2 + 3s (s + 1) (s + 2) (s + 4)

(3.110)

with ROC {s: Re{s} > – 1}, find the corresponding time signal x. Solution. Check that the order of the denominator exceeds that of the numerator. Because it does, we can proceed by writing X (s ) =

A1 A2 A3 + + (s + 1) (s + 2) (s + 4)

(3.111)

s 2 + 3s (s + 2)(s + 4)

(3.112)

Using the previous method, we find that A1 =

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=− s=−1

2 3

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In a similar manner, we find that A2 = 1 and A3 = 2/3. Therefore, X (s ) = −

2/3

1

+

+

2/3

(3.113)

(s +1) (s + 2) (s + 4)

Now, using linearity and Table 3.1 [or recalling (3.48)], we can immediately write 2  2  x (t ) = − e −t + e −2t + e −4t u(t ) 3  3 

(3.114)

Case 2: Simple Quadratic Factors. When D(s) contains a simple quadratic factor, the LT can be expanded as X (s ) =

N (s ) N (s ) = 2 D(s ) s − βs + γ Dother (s )

(

)

Bs + C = 2 + other PFs corresponding to factors in Dother (s ) s − βs + γ

) [

(

]

(3.115)

The usefulness of this form is illustrated next. Example 17. Find the time signal x corresponding to LT X (s ) =

(s + 4)

(s + 2) (s 2 + 6s + 34)

, ROC{s:Re{s} > −3}

(3.116)

Solution. The order of D exceeds the order of N, so we may proceed. The roots of the quadratic term are p, p* = (−6 ± 36 − 136) / 2 = −3 ± j5 , so we leave it as a quadratic. (If the roots were real, we would use the simple linear factor approach.) Expand the LT into PFs X (s ) =

A Bs + C + 2 (s + 2) s + 6s + 34

(

(3.117)

)

Using the method for simple linear factors, we find that A = 1/13. Now multiply both sides of (3.117) by D(s) = (s + 2) (s 2 + 6s + 34) to obtain

(s + 4) = 131 (s 2 + 6s + 34) + (Bs + C )(s + 2)

(3.118)

Equating like powers of s on the two sides of the equation yields B = –1/13 and C = –1/13, so X (s ) =

[

]

(−1 13)s + (9 13) 1 13 + (s + 2) s 2 + 6s + 34

(

)

(3.119)

The first fraction has become familiar by now and corresponds to time function (1/13)e–2t u(t). Let us focus on the second fraction. Note that [recall (3.59)] s 2 + 6s + 34 = (s − p)(s − p *) = (s + 3 − j5)(s + 3 + j5) = (s + 3) + 52 2

The second fraction, therefore, can be written as © 2003 by CRC Press LLC

(3.120)

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−

 12 1  (s + 3)   − 2 2 2 2 13  (s + 3) + 5 (s + 3) + 5   

(12 5)5  1  (s + 3) =−  − 2 2 13  (s + 3) + 5 (s + 3)2 + 52   

(3.121)

The terms in brackets correspond to a cosine and sine, respectively, according to Table 3.1. Therefore, 1  1 12 −3t X (t ) =  e −2t − e −3t cos(5t ) + e sin(5t )u(t ) 13 5(13) 13 

(3.122) ▫

Simple quadratic factors need not be handled by the above procedure, but can be treated as simple linear factors, as illustrated by example. Example 18. Repeat the previous problem using simple linear factors. Solution. Expand X into simple linear PFs X (s ) =

A E E* + + , p = −3 + j5 (s + 2) (s − p) (s − p *)

(3.123)

Note that the PFE coefficients corresponding to complex-conjugate pole pairs will themselves be complex conjugates. In order to derive a useful general relationship, we ignore the specific numbers for the moment. Using the familiar inverse transform, we can write

[

]

x (t ) = Ae −2t + Ee pt + E * e p*t u(t )



(3.124)

Letting E = Ee jθE and p = σp + jωp , we have Ee pt + E * e p*t = E e jθE e (

) + E e − jθE e (σ p − jω p )t = 2E e σ pt cos ω t + θ ( p E)

σ p + jω p t

(3.125)

This form should be noted for use with complex-conjugate pairs. Using the method for finding simple linear factor coefficients, we find that A = 1/13. Also E = X ( s ) ( s − p)

s= p

=

(s + 4) | = ( p + 4) s= p (s + 2)(s − p *) ( p + 2)( j 2 Im{p})

(1 + j5) = 0.1e − j 0.626π = (−1 + j5)( j10)

(3.126)

Therefore, the answer can be written: 1  x (t ) =  e −2t + 0.2e −3t cos(5t − 0.626π)u(t ) 13 

(3.127)

This solution is shown to be consistent with that of the previous example using the trigonometric identity cos (α + β) = cos(α) cos(β) – sin(α) sin(β). ▫

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Case 3: Repeated Linear Factors. When D(s) contains a repeated linear factor, for example, (s – p)n the LT must be expanded as X (s ) =

N (s ) N (s ) An An−1 A1 = = + +L+ D(s ) (s − p)n Dother (s ) (s − p)n (s − p)n−1 s ( − p)

[

(3.128)

]

+ other PFs corresponding to factors in Dother (s ) The PFE coefficients of the n fractions are found as follows: Define ϕ p ( s ) = ( s − p) X ( s ) n

(3.129)

Then An−i =

1 di ϕ i! ds i p

|

(3.130)

s= p

The similarity of these computations to residues is apparent, but only A1 can be interpreted as the residue of pole p. We illustrate this method by example. Example 19. Find the time signal x corresponding to LT X(s) = (s + 4)/(s + 1)3. Solution. The order of D exceeds the order of N, so we may proceed. X has a third-order pole at s = –1, so we expand X as X (s ) =

(s + 4) = A3 + A2 + A1 (s + 1)3 (s + 1)3 (s + 1)2 (s +1)

(3.131)

Let ϕ–1(s) = (s + 1)3 X(s) = (s + 4). Then A3 = ϕ −1 (−1) = 3, A2 =

dϕ −1 ds

|

s=−1

= 1, and A1 =

1 d 2ϕ −1 2 ds 2

|

s=−1

=0

(3.132)

So X (s ) =

3

(s +1)

3

+

1

(s +1)2

(3.133)

Using Table 3.1 we have 3  x (t ) =  t 2e −t + te −t  u(t ) 2 

(3.134) ▫

Case 4: Repeated Quadratic Factors. When D(s) contains a repeated quadratic factor, e.g., (s 2 + βs + γ)n, the LT may be either inverted by separating the quadratic into repeated linear factors [one nth-order factor for each of the complex roots; see (3.155)], then treated using the method of Case 3, or it can be expanded as

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X (s ) =

N (s ) N (s ) = n D(s ) s 2 + βs + γ Dother (s )

(

)

(B s + Cn−i ) + other PFs corresponding to factors in D (s) = ∑ n−i [ ] other n 2 n−1

i=0

(s

+ βs + γ

(3.135)

)

The PFE coefficients of the n factions are found algebraically as we illustrate by example. Example 20. Find the time signal x corresponding to X (s) = 4s 2 / (s 2 +1)2 (s + 1)[10]. Solution. Recognize the factor (s2+1)2 as an n = 2 order quadratic factor with β = 0 and γ = 1. We know from our previous work that β = −2 Re{p}, where p and p* are the poles associated with the quadratic factor, in this case ± j. In turn, the real part of p provides the damping term in front of the sinusoid represented by the quadratic factor. In this case, therefore, we should expect one of the terms in the time signal to be a pure sinusoid. Write X as X (s ) =

(B2s + C2 ) + (B1s + C1 ) +

(s +1) 2

(

2

)

s 2 +1

A

(s +1)

(3.136)

Using the familiar technique for simple linear factors, we find that A = 1. Now multiplying both sides of (3.136) by (s 2 +1)2 (s + 1) , we obtain 4s 2 = (B2s + C 2 )(s + 1) + (B1s + C1)(s 2 +1)(s + 1) + (s 2 +1)2. Equating like powers of s, we obtain B2 = –1, C2 = 1, B1 = 2, and C1= – 2. Hence, X (s ) =

(2s − 2) + (s − 1) 1 + (s + 1) s 2 + 1 2 s 2 + 1

) (

(

)

(3.137)

We can now use Tables 3.1 and 3.2 to invert the three fractions. Note that the third term will yield an undamped sinusoid as predicted. Also note that the middle term is related to the third by differentiation. This fact can be used in obtaining the inverse. ▫

3.4 Laplace Transform Analysis of Linear Systems Let us return to the example circuit problem, which originally motivated our discussion, and discover ways in which the LT can be used in system analysis. Three fundamental means are available for using the LT in such problems. The most basic is the use of LT theory to solve the differential equation governing the circuit dynamics. The differential equation solution methods are quite general and apply to linear, constant coefficient differential equations arising in any context. The second method involves the use of the “system function,” an LT-based representation of an LTI system, which embodies all the relevant information about the system dynamics. Finally, we preview “LT equivalent circuits,” an LT method that is primarily used for circuit analysis, and is treated more completely in Chapter 19.

Solution of the System Differential Equation Consider a system is governed by a linear, constant coefficient differential equation of the form nD

∑ l=0

© 2003 by CRC Press LLC

al

dl y (t ) = dt l

nN

∑b

l

l=0

dl x (t ) dt l

(3.138)

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75

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with appropriate initial conditions given. (The numbers nN and nD should be considered fixed integers for now, but are later seen to be consistent with similar notation used in the discussion of rational LTs.) Using the linearity and time-differentiation properties of the LT, we can transform both sides of the equation to obtain nD



l−1



l=0



i=0



∑ al s l Y (s ) − ∑ y (i) (0 − )s l−i−1  (3.139)

l−1   = ∑ bl s l X (s ) − ∑ x (i ) 0 − s l−i −1  l=0 i=0   nN

( )

where y(i) and x(i) are the ith derivatives of y and x. Rearranging, we have

Y (s ) =

X (s )

∑

nN l=0

bls l −

∑ b∑ nN

l=0

l

l−1

i =0

( )

x (i ) 0 − s l−i −1 +

∑

nD l =0

∑

nD l=0

al

∑

l−1

i =0

( )

y (i ) 0 − s l−i −1

al s l

(3.140)

Given the input signal x and all necessary initial conditions on x and y, all quantities on the right side of (3.140) are known and can be combined to yield Y. Our knowledge of LT inversion will then, in principle, allow us to deduce y. This process often turns an unwieldy differential equation solution into simpler algebraic operations. The price paid for this simplification, however, is that the process of inverting Y to obtain y is sometimes challenging. Recall that in the motivating example, a similar conversion of the (nonhomogeneous) differential equation solution to algebraic operations occurred [recall (3.16) and surrounding discussion], as the superfluous term e pxt was divided out of the equation. Except for the lack of attention paid to initial conditions, what remains in (3.16) is tantamount to a LT equation of form (3.139), as shown below. The homogeneous solution and related initial conditions were not included in the earlier discussion to avoid obfuscating the main issue. The reader was encouraged to think of the LT as a process of “dividing” the “e st ” term out of the signals before starting the solution. We can now clearly see this fundamental connection between the differential equation and LT solutions. Example 21. Return to the motivating example in Section 3.2 and solve the problem using LT analysis. Solution. Recall the differential equation governing the circuit, (3.1), x(t) = LC(d 2 y/dt 2) + RC(dy/dt) + y(t). The initial conditions are y(0 –) = y0 and i(0 –) = i0. Recall also that for convenience we seek the solution for x(t ) = M x e jθx e (σx + jω x )t u(t ) = M x e jθx e pxt u(t ), recognizing that the “correct” solution will be the real part of that obtained. Taking the LT of each side of the differential equation, we have

[

( )]

( )

[

]

X (s ) = LC s 2Y (s ) − sy 0 − − y (1) 0 − + RC sY (s ) − y(0 − ) + Y (s )

(3.141)

or Y (s ) =

(LCs

X (s ) 2

)

+ RCs + 1

+

(sLC − RC ) y(0− ) + LCy(1) (0− )

(LCs

2

)

+ RCs + 1

(3.142)

Dividing both numerator and denominator of each fraction by LC, and inserting the LT X(s) = Mx e jθx/(s – px) and the initial conditions [recall that Cy (1)(t ) = i(t ) ⇒ Cy (1) (0 − ) = i0], we have Y (s ) =

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[

]

s − ( R L) y 0 + i0 C M x e jθx LC + 2 s 2 + ( R L)s + 1 (s − px ) s + (R L)s + 1

[

]

[

]

(3.143)

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Using PFE, this can be written

Y (s ) =

[

M x e jθx LC px2 + ( R L) px + 1

]+

( s − px )

M x e jθx LC ( ph − px )

(s − ph )

*

 M e jθx LC  x  p −p  s − ( R L) y 0 + i0 C  ( h x)  + + * s − ph (s − ph ) s − ph*

(

)

[

] (

(3.144)

)

where ph and ph* are the system poles. We have expanded the first fraction in (3.143) using simpler linear factors involving the poles px , ph , and ph* . The latter two poles correspond to the system [roots of (s2 + (r/L)s + 1)]], and the resulting terms in (3.144) are part of the natural response. The first pole, px , is attributable to the forcing function, and the resulting term in (3.144) will yield the forced response in the time domain. Finally, the last term in (3.144), which arises from the last term in (3.143), is also part of the natural response. The separation of the natural response into these three LT terms harkens back to the time-domain discussion about the distinct contributions of the input and initial conditions to the natural response. The last term is clearly related to initial conditions and the circuit’s natural means of dissipating that energy. The former, terms, which will also yield a damped sinusoid of identical complex frequency to that of the third term, are clearly “caused” by the input. Remark. The reader may wonder why the first fractions in (3.144) and (3.17), both of which represent the forced response, are not identical. After all, we have been encouraged to view the LT as a kind of generalized phasor representation. Recall, however, that the LT at a particular s must be thought of as a “phasor density.” If an eigensignal of the system represents one complex frequency, e.g., s = px , the LT is infinitely dense at that point in the s-plane, corresponding to the existence of a pole there. If the signal – does have a conventional phasor representation such as Y = Mye jθy, then this phasor will be related to the LT as Y = Y (s )

ds = lim Y (s ) (s − px ) 2π s = px s→ px

(3.145)

which we recognize as the residue of the LT Y at the pole px. The reader can easily verify this assertion using (3.143). This discussion is closely related to the interconnection between the Fourier series coeffi­ cients (which are similar to conventional sinusoidal phasors) and the Fourier transform. These signal representations are discussed in Chapter 4.

The System Function Definition 1. In our motivating example an input sinusoid with generalized phasor Mx e jθx produced an output sinusoid with generalized phasor My e jθy. We discovered that the ratio of phasors was dependent only upon system parameters and the complex frequency, px. We noted that when considered as a function of the general complex frequency, s, this ratio is called the system function. That is, the system function is a complex function, H, of complex frequency, s, such that if a damped sinusoid of complex frequency – s = px and with generalized phasor X = Mxe jθx is used as input to the system, the forced response will be a sinusoid of complex frequency px and with generalized phasor M ye

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jθy

= H ( px )M x e jθx

(3.146)

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77

The Laplace Transform

jω jω − p1 jω − z1

p1 × jω − p2 (a)

z1

σ

p2 ×

jω

FIGURE 3.9 Pole-zero plot for an example system func­ tion, H(s) = C(s – z1)/(s – p1)(s – p2). (a) To obtain the magnitude response H(sω) at frequency ω, the product of lengths from all zeroes to s = jω is divided by the product of lengths from all poles to s = jω. The result must be multiplies by the gain term C. (b) To obtain the phase response {H(jωx)} at frequency ω, the sum of angles from all poles to s = jω is subtracted from the sum of angles from all zeroes to s = jω. An additional π radians is added if C < 0.

p1 ×

α1 β1

(b) p2 ×

α2

z1

σ

α1 (ω) = arg ( jω − p1) α2 (ω) = arg ( jω − p2) β1 (ω) = arg ( jω − z1)

Preview of Magnitude and Phase Responses It is often important to know how a system will respond to a pure sinusoid of radian frequency, e.g., ωx. In particular, we would like to know the amplitude and phase changes imposed on the sinusoid by the system. In terms of the definition just given, we see that this information is contained in the sytem function evaluated at frequency px = jωx . In particular, H (jωx ) represents the magnitude factor and arg {H (jωx)} the phase change at this frequency. When plotted as functions of general frequency ω, the real functions H (jω) and arg {H (jωx )} are called the magnitude (or sometimes frequency) response, and phase response of the system, respectively. The complex function H(jω) will be seen to be the Fourier transform of the impulse response (see Appendix B and Chapter 4) and is sometimes called the transfer function for the system. Returning to Fig. 3.2(b), the reader will discover that we have plotted the magnitude response for the series RLC circuit of Section 3.2 with numerical values given in (3.18). The magnitude and phase responses of the system can be obtained graphically from the pole-zero nN nD (s – zi)/∏ i=1 (s – pi ). Therefore, diagram. Writing H(s) similarly to (3.62), H(s) = C∏ i=1 H ( jω ) = C

{

∏ ni=1N jω − z i D ∏ ni=1 jω − pi

and (3.147)

nN

nD

} ∑ arg{( jω − z )} − ∑ arg{( jω − p )}

arg H ( jω ) =

i

i=1

i

i=1

where we have assumed C > 0 (if not, add π radians to arg {H (jωx )}). By varying ω the desired plots are obtained as illustrated in Fig. 3.9. Definition 2. More generally, the system function, H(s), for an LTI system can be defined as the ratio of the LT, for example, Y(s), of the output, resulting from any input with LT, for example, X(s), when

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the system is initially at rest (zero initial conditions). In other words, H is the ratio of the LT of the zerostate response to the LT of the input, H (s ) =

def

Y (s ) X (s )

when all initial conditions are zero

(3.148)

While the latter definition is more general, the two definitions are consistent when the input is an eigensignal, as we show by example. Example 22. Show that the two definitions of the system function described previously are consistent for the RLC circuit of Section 3.2. Solution. Replacing the specific frequency px by a general complex frequency s in the initial example using phasor analysis, we found that [recall (3.31)] H(s) = 1/(LCs2 + RCs + 1). On the other hand, using more formal LT analysis on the same problem, we derived (3.142). Forming the ratio Y(s)/X(s) where both initial conditions are set to zero, yields an identical result. ▫ Finally, another very useful definition of the system is as follows. Definition 3. The output of LTI system to an impulse excitation, x(t) = δ(t) (see Section 3.6, Appendix A), when all initial conditions are zero, is called the impulse response of the system. The impulse response is usually denoted h(t). The system function can be defined as the LT of the impulse response H(s) = {h(t)}. The consistency of this definition with the first two is easy to demonstrate. Let H denote the system function for the system, regardless of how it might be related to h(t). From Definition 2, we have H(s) = Y(s)/X(s) for any valid LTs X and Y. Let x(t) = δ(t), in which X(s) = 1. By definition, y(t) = h(t), so {h(t)} = {y(t)} = H(s)X(s) = H(s). This interpretation of H enables us to find the impulse response of the system, a task which is not always easy in the time domain because of the pitfalls of working with impulse functions. Example 23. Find the impulse response, h, for the circuit of Section 3.2. Solution. Using various means we showed that the system function is H(s) = 1/(LCs2 + RCs + 1). Let us find h by computing h(t) =  –1{H(s)}. Using the quadratic equation, we find the roots of the denominator (poles of the system) to be [c.f., (3.6)]

p1 , p2 =

−RC ± R 2C 2 − 4LC R =− ± 2LC 2L

R2 1 − 4L2 LC

(3.149)

Assume that these poles are complex conjugates and call them ph , ph* , where ph = −

R 1 R 2 def +j − 2 = σ h + jω h 2L LC 4L

(3.150)

Comparing to our initial work on finding the homogeneous solution of the differential equation, we see that these system poles are the roots of the characteristic equation. The reason for using subscript “h” in our early work should now be clear. In terms of (3.150) we can rewrite H as H (s ) =

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1 LC

(s − σ h )

2

+ ω h2

(3.151)

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79

The Laplace Transform

[recall (3.59)]. Now using Table 3.1: {e σht cos(ωht + θh)} = [(s – σh) cos(θh) – ωh sin(θh)]/[(s – σh)2 + ωh2]. Letting θh = π/2 and using linearity, we have 1 π 1  e σht cos ω ht +  u(t ) = e σht sin(ω ht ) u(t )  2 LCω h LCω h

h(t ) = −

We could also note that ph = 1 ⁄ LC and write the initial scale factor as ph2/ωh.

(3.152) ▫

We see clearly that the impulse response is closely related to the natural responses of a system, which in turn are tied to the homogeneous solution of the differential equation. These transient responses depend only on properties of the system, and not on properties of the input signal (beyond the initial instant of excitation). The form of the homogeneous differential equation solution is specified by the number and values of the roots of the characteristic equation. These roots are, thus, the poles of the system function H. The system function offers an extremely valuable tool for the design and analysis of systems. We now turn to this important topic.

Poles and Zeros — Part II: Stability Analysis of Systems We return to the issue of poles and zeroes, this time with attention restricted to rational LTs. In particular, we focus on the poles and zeroes of a system function and their effects on the performance of the system. Natural Modes The individual time responses corresponding to the poles of H are often called natural modes of the system. These modes are indicators of the physical properties of the system (e.g., circuit values), which in turn determine the natural way in which the system will dissipate, store, amplify, or respond to energy of various frequencies. Consider two general cases. Suppose H has a real pole of order n at s = p, so that it can be written H (s ) =

n

∑ i=1

Ai

( s − p)

i

+ [other terms]

(3.153)

We know from previous work, therefore, that (see Table 3.1) h has corresponding modal components, h(t ) =

n

∑ i A− 1 ! t i=1

i

(

)

e u(t ) + [other terms]

i−1 pt

(3.154)

When |p| < 0, the modal components due to pole p will decay exponentially with time (modulated by the terms t i – 1). When |p| > 0, these modal components will increase exponentially with time (modulated by the terms t i – 1). When p = 0, the term will either remain bounded if n = 1, or terms will increase with power n as t increases. These cases are illustrated in Fig. 3.10(a). Next, let H have a complex pole pair of order n at s = p, p*, so that it can be written H (s ) =

n





∑  (s − p) + (s − p *)  + [other terms] E i*

Ei

i

i

(3.155)

i=1

Using Table 3.1 we see that h has a corresponding modal component, h(t ) =

n

∑ (i − 1)! t i=1

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2 Ei

i−1 σ pt

e

(

)

cos ω pt + θ Ei u(t ) + [other terms]

(3.156)

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80

The Circuits and Filters Handbook, Second Edition

� ��� �

���

= −�� � = �

���������� � ���

���

= −�� � = �

�

��� ��� ��� ��� ��� ��� � �

���

�

���

�

���

�

���

�

���

�

���

�

����� � �����

���

�

��� �

= − ��� + �� � = �

��� �

���������� � ���

���

= − ��� + �� � = �

���

� �

�

�

�

�

�

�

�

�

�

��

−��� −��� −��� −��� ����� � ����� ���

FIGURE 3.10 Modal components in the impulse response corresponding to (a) a real pole of orders n = 1 and n = 2 at s = p, and (b) a complex pole pair of orders n = 1 and n = 2 and s = p, p*.

where p = σp + jωp, and θEi = arg{Ei}. In this case, when |p| < 0, the sinusoidal components will decay exponentially with time (modulated by the terms t i – 1); when |p| > 0, these terms will increases expo­ nentially with time (modulated by the terms t i – 1); and when p = 0, the terms due to p will either represent a constant or increasing sinusoid, depending on the value of n. These cases are illustrated in Fig. 3.10(b).

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81

The Laplace Transform

BIBO Stability We digress momentarily to discuss the concept of stability. To avoid some unnecessary complications, we restrict the discussion to causal systems, and, as usual, to the unilateral LT. There are various ways to define stability, but the most frequent and useful definition for a LTI system is that of BIBO stability. A system is said to be bounded-input–bounded-output (BIBO) stable iff every bounded input produces a bounded output. Formally, any bounded input, for example, x such that |x(t)| ≤Bx < ∞ for all t, must result in an output, y, for which By < ∞ exists so that |y(t)| ≤By for all t. A necessary and sufficient condition for BIBO stability of a LTI system is that its impulse response be absolutely integrable,

∫

∞

0

h(t ) dt < ∞

(3.157)

This is easy to show. First, assume |x(t)| 0 h(λ ) < 0

(3.160)

h(λ ) = 0

For this input, the output at time t is y (t ) =

∫

0

∞

h(λ ) dλ

(3.161)

which is not bounded according to assumption. Therefore, we encounter a contradiction showing that the condition (3.157) is also necessary for BIBO stability. Stability and Natural Modes Now we tie the stability analysis to the discussion of modal components above. We assert that a causal LTI system with proper rational system function H will be BIBO stable iff all of its poles are in the left-half s-plane. That this is true is easily seen. If any pole is in the right-half s-plane, we know that h will contain at least one mode that will increase without bound. Therefore, (3.157) cannot hold and the system is not BIBO stable. Conversely, if all poles are in the left-half s-plane, (3.157) will hold. The case in which one or more simple poles fall exactly on the s = jω axis (and none in the right-half s-plane) is called marginal BIBO stability. In this case (3.157) does not hold, so the system is not strictly BIBO stable. However, the system does theoretically produce bounded outputs for some inputs. Finally, note that we

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show by example below Example 24(a) that an improper rational system function cannot represent a BIBO stable system. Based on our earlier discussion of LT ROCs, an equivalent way to state the BIBO stability condition is as follows: A causal, LTI system is BIBO stable iff the ROC of its system function H includes the s = jω axis in the s-plane. We recall that the failure to include the jω axis would imply at least one pole of H in the right-half s-plane. Let us conclude this discussion by considering some examples. Example 24. Comment on the BIBO stability of the following systems: (a) H (s ) = (b) H (s ) = (c) H (s ) =

N (s ) (1 2) s 3 = (1 2) s 3 = 2 D(s ) s + 2s + 1 (s +1)2

(s − 3)

s + 5s + 4 2

(s

(s − 3) 2

)(

)

+ 5s + 4 s 2 − 2s − 3 6

(d) H (s ) =

[(s + 3) + 25](s + 8)

(e) H (s ) =

s s2 + 4

2

Solution. (a) H is not a proper rational fraction because the order of N(s) > order of D(s). We illustrate that such a system is not BIBO stable. Dividing D into N, we can write 32 1 H (s ) = s − 1 + 2 2 s s + 2s + 1

(

(3.162)

)

Suppose we enter x(t) = u(t) as a (bounded) input. Then Y (s ) = H (s ) X (s ) =

H (s ) 1 1 32 = − + 2 2 s s s + 2s + 1 s

(

(3.163)

)

Therefore,  32 1 y (t ) = δ(t ) − u(t ) + terms resulting from 2 2 s s + 2s + 1  

(

)

   

(3.164)

The output is unbounded in response to a bounded input and the system is therefore not BIBO stable. A similar result will occur whenever H is not proper. (b) H has poles at s = – 1, – 4, and zero at s = 3. The system is BIBO stable. Note that the right-half plane zero has no adverse effect on stability. (c) H(s) = N(s)/D(s) has a second-order pole at s = – 1, and a simple pole at s = – 4. Both N and D have roots s = 3, thus, neither a pole nor zero is found there (they cancel). The system is therefore BIBO stable.

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83

The Laplace Transform

Remark. The response to nonzero initial conditions of a system which has one or more “cancelled poles” in the right-half s-plane will increase without bound, and therefore could be considered “unstable” in some sense, even though it is BIBO stable. The reader is invited to show that the present system will respond in this undesirable manner to nonzero initial conditions. A system is said to be asymptotically stable if it is BIBO stable and its response to initial conditions approaches zero as t → ∞. We see that asymptotic stability implies BIBO stability but the converse is not true. (d) Recalling (3.59) we find H has poles s = –3 ± j5 and s = –8. No finite zeros are included. The system is BIBO stable and will have both an oscillatory mode and a damped exponential mode. (e) H has poles at s = ± j2 which are on the jω axis. The system is marginally BIBO stable. ▫ Example 25. Return to the series RLC circuit of Section 3.2 and discuss the system’s stability as R varies for a fixed L and C. Assume that R < 2 L ⁄ C . Solution. In light of (3.149), the upper bound on R means that the poles of the system will always be complex conjugates, e.g., ph, ph* [h is oscillatory]. From (3.150) we see that the poles of the system can be written in polar form as ph , ph* = σ h2 + ω h2 e

± j tan−1 ( ω h σh )

=

1 ± j tan−1 (ωh e LC

σh )

(3.165)

For fixed L and C, the poles remain on a circle of radius 1/ LC in the s-plane. Having established this fact, recall the Cartesian form of ph given in (3.149) and note that as R → 0, ph → j 1 ⁄ LC . On other hand, as R → 2 L ⁄ C, ph → – 1 ⁄ LC (see Fig. 3.11). Therefore, the poles remain in the left-half s-plane over the specified range for R, except when R = 0, in which case the poles are exactly on the jω-axis at s = ± j(1/ LC ). Therefore, the system is BIBO stable, except when R = 0, in which case it is marginally stable. Only if R were to take negative values would the circuit go unstable. This is not realistic unless active circuit elements are present which effectively present negative resistance. The reader is encouraged to explore what happens as R continues to increase beyond the given upper bound. jω

s plane

×

R increases

When R = 2 pole at ph = −

L , double C 1 LC

1 LC

When R = 0, poles at ph,ph* = ± j 1 LC

×

σ

×

× R increases

FIGURE 3.11 Locus of the poles as R varies in Example 25.

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Laplace-Domain Phasor Circuits After completing a sufficient number of circuit problems involving differential equations like Example 21, certain patterns would become apparent in a Laplace-transformed differential equation like (3.141). These patterns occur precisely because of the invariant relationships between currents and voltages across lumped parameter components. For example, because the current and voltage through an inductor are related as vL(t) = L(diL/dt), whenever this relationship is encountered and transformed in a circuit problem, it becomes VL(s) = sLIL(s) – LiL(0–). This relationship may be written without recourse to the time domain by treating VL(s) and IL(s) as a “DC voltage” and a “DC current,” by replacing the inductor with a “resistor” with value sL, by adding a voltage source in series with value LiL(0–) having proper polarity, a small DC circuit problem. In general, we can make “Laplace” substitutions for each component in a circuit, then use “DC” analysis to write the Laplace-transformed differential equation directly. The appropriate substitutions and vari­ ations for both mesh and nodal analysis are discussed in detail in Chapter 38, along with more advanced frequency-domain uses of such LT replacements. After studying that material, the reader may wish to provide closure to the present discussion by solving the following problem. Example 26. Derive the Laplace-transformed differential equation, (3.141), using Laplace circuit equivalents.

3.5 Conclusions and Further Reading The Laplace transform (LT) is a powerful tool in the analysis and design of linear, time-invariant circuits and systems. In this exposition we have developed the LT by appealing to the manner in which it turns differential equation solutions into simple algebraic problems. We have focused not only on the technique for exploiting this advantage, but also the reasons that this happens. Along the way we have discovered some useful properties of the LT, as well as the meaning of poles and zeros. We also discussed numerous techniques for recovering the time signal from the LT, noting that this sometime difficult task is the price paid for alleviating the difficulties of time-domain solution. In the latter part of the chapter we turned our attention to the analysis of systems, in particular the meaning and derivation of the system function. This study led to the understanding of the relationship between the system function and impulse response, and between the pole locations of the system function and stability of the system. Most of our work has focused on the unilateral LT (ULT), although the bilateral LT (BLT) was carefully discussed at the outset. The advantage of the ULT is that it provides a way to incorporate initial condition information, a very important property in many design and analysis problems, particularly because the initial conditions play an important role in the transient response of the system. On the other hand, the BLT can handle a much broader class of signals, a feature that is often advantageous in theoretical and formal developments. The region of convergence (ROC) of the LT in the s-plane becomes much more important for the BLT as the LT itself is not unique without it. Accordingly, we spent a significant amount of effort studying the ROC. The LT is closely related to the Fourier and z-transforms, which are the subjects of subsequent chapters. Section 3.7, Appendix B previews these ideas. Finally, we note that several LT topics have not been treated here. These topics, such as the analysis of feedback systems and state-space models, deal principally with control theory and applications and are therefore outside of the scope of this book. Many fine books on signals and systems are available to which the reader can turn to explore these subjects. Some of these texts are referenced below. Many excellent books on circuit analysis and filter design, too numerous to cite here, are also available.

3.6 Appendix A: The Dirac Delta (Impulse) Function The Dirac delta, or impulse, function, δ(t), is defined as the function with the following properties: If signal x is continuous at t0 (“where the impulse is located in time”), then, © 2003 by CRC Press LLC

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The Laplace Transform

0,

t 0 ∉[a, b]

x  (t 0 ),

t 0 ∈(a, b)

∫ x(t )δ(t − t ) dt =  b

0

a

(3.166)

Two special cases are noted: 1. Note that (3.166) does not cover the case in which the impulse is located exactly at one of the limits of integration. In such cases whether x is continuous at t0, The integral takes the value 1-2 x(t0+) if t0 is the lower limit, t0 = a. The integral takes the value 1-2 x(t0–) if t0 is the upper limit, t0 = b. 2. The only case not explicitly covered is one in which x is discontinuous at t0 and t0 is not a limit of integration. In this case the integral takes the value 1-2 [x(t0–) + x(t0+)] if t0 ∈ (a, b), and 0 otherwise. Note that this answer is also valid if x is continuous at t0, but it is unnecessarily complicated. Note what happens in the special case in which x(t) = 1, a = – ∞, b = t, and t0 = 0. From the definition, we can write

∫

0, t < 0  δ(λ ) dλ = 1, t > 0 −∞  1  2 , t = 0 t

(3.167)

We see that t

∫ δ(λ) dλ = u(t )

(3.168)

du = δ(t ) dt

(3.169)

−∞

Therefore, except at t = 0,

What emerges here is a very strange function. We see from (3.168) that δ must be zero everywhere except at t = 0 because, apparently we accumulate area at only that point. The area under that one point is unity because the integral takes a jump from 0 to 1 as t crosses zero. Because δ has zero width and unity total area, it must have infinite amplitude (at that one point!). To indicate the delta function, therefore, we draw “arrows” as shown in Fig. 3.12. It is sometimes mathematically useful to indicate a delta function with area other than unity. In this case we simply label the arrow with a number called the “weight” of the impulse. Note that it makes no sense to draw taller and shorter arrows for different weights, although this is sometimes done in textbooks, because the weight does not indicate the “height” of the function (∞!), but instead, its area! Finally, note that computing integrals with delta functions in them is very easy because one need only follow the rules of the definition. For example,

∫

∞

e π( λ − 4)δ(λ − 6) dλ = e 2π

(3.170)

∫ 3u(t ) δ(t ) dt = 3 u(02 ) = 3 2

(3.171)

−18

and 2

+

0

Remark. The kth derivative of the impulse (usually k ≤ 2) occasionally appears in LT work. The notation δ (k ) (t ) = def

d kδ dt k

(3.172)

is often used to denote this signal. The signal δ(1)(t) is called a doublet and is plotted as shown in Fig. 3.13. © 2003 by CRC Press LLC

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7

0

3

8

t

FIGURE 3.12 The impulse functions δ(t), δ(t – 3), and 7δ(t – 8).

δ (1) (t)

0−

0+

t

FIGURE 3.13 The doublet.

3.7 Appendix B: Relationships among the Laplace, Fourier, and z-Transforms The transforms previewed here are most frequently defined and discussed for two-sided signals. There­ fore, it is most natural to base this discussion on the BLT, as defined in (3.38). The Fourier transform (FT), XF , of a signal x is defined by the integral X F (ω ) =

∞

∫ x(t ) e −∞

jωt

dt

(3.173)

Upon comparison with (3.38), it is apparent that the FT evaluated at radian frequency ω is equivalent to the BLT of x evaluated at s = jω in the s-plane. The FT can, therefore, be obtained over all ω by evaluating the BLT, e.g., XL along the jω axis: © 2003 by CRC Press LLC

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87

The Laplace Transform

X F (ω ) = X L (s )

(3.174)

s = jω

Evidently, the FT will only exist for a signal x if its BLT has a ROC that includes the jω axis. One very important class of signals whose BLT ROCs include the entire left-half s-plane, but not the jω axis, is the periodic signals. For this purpose, the Fourier series (FS) can be used to expand the signal on a set of discrete, harmonically related, basis functions (either complex exponentials or sinusoids). The complex version is x (t ) =

∞

∑ c e

l=−∞

l

jlω 0t

(3.175)

where ω0 = 2π/T0 is the fundamental radian frequency, with T0 the period of the waveform. The complex numbers cl, l = …, –1, 0, 1, 2, … are the FS coefficients computed as c l =

1 T0

∫ x(t )e

− jlω 0t

dt

(3.176)

T0

where the integral is taken over any period of the waveform. Comparing (3.176) and (3.173), we see that the FS coefficients are equivalent to (scaled) samples of the FT of one period of x, where the samples are taken at frequencies lω0. If we have a periodic waveform, therefore, we can always represent it by samples of the FT of one period. Similarly, if we have “short” signal and want to represent it using only frequency samples, we can let it be periodic and represent it using the FS coefficients. In this case we simply need to recall that the signal is not truly periodic and work with only one period. Conversely, the FT may be represented using only samples of the time waveform by artificially letting the FT become periodic, then letting the time samples play the role of the FS coefficients. In this case, we in effect, let the BLT become periodic along the jω axis. This “backward FS” is what is know as the discrete-time Fourier transform (DTFT). The DTFT is discussed in Chapter 4 along with the discrete Fourier transform, a Fourier-type transform which is discrete and periodic in both time and frequency. For the latter, the connections to the BLT are too obtuse to describe in brief terms here. Finally, if we let the BLT become periodic in ω with some fixed period along each σ line, the BLT can also be represented by discrete-time samples. This is similar to writing a “FS” which changes for each σ. This discrete-time Laplace transform (DTLT) could, in principle, be used in the design and analysis of discrete-time systems in much the same way the BLT is used in continuous-time work. For historical reasons and for mathematical convenience, however, the z-transform (ZT) is almost universally used. The ZT is obtained from the DTLT using the mapping e sT → z, where T is the sample period on the time signal. As a consequence of this mapping, “strips” in the s-plane map into annuli in the z-plane. Therefore, the ROC of a ZT takes the form of an annulus and the unit circle in the z-plane plays the role of the jω axis in the s-plane. These ideas will become clearer and more precise through the study of successive chapters. The reader is also encouraged to see [2] for an elementary approach to discrete FTs.

References [1] G. E. Carlson, Signal and Linear System Analysis, Boston: Houghton-Mifflin, 1992. [2] J. R. Deller, “Tom, Dick and Mary discover the DFT,” IEEE Signal Processing Mag., vol. 11, pp. 36–50, Apr. 1994. [3] R. V. Churchill, J. W. Brown, and R. F. Verhey, Complex Variables and Applications, 3rd ed., New York: McGraw-Hill, 1976. [4] G. Doetsch, Guide to the Applications of Laplace Transforms, New York: Van Nostrand, 1961. © 2003 by CRC Press LLC

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[5] W. H. Hayt and J. E. Kemmerly, Engineering Circuit Analysis, New York: McGraw-Hill, 1971. [6] R. C. Houts, Signal Analysis in Linear Systems, Philadelphia: Saunders, 1989. [7] A. N. Kolmogorov and S. V. Fomin, Introductory Real Analysis, New York: Dover, 1975. Translated and edited by R. A. Silverman. [8] P. Kraniauskas, Transforms in Signals and Systems, Reading, MA: Addision-Wesley, 1992. [9] W. LePage, Complex Variables and the Laplace Transform for Engineers, New York: McGraw-Hill, 1961. [10] C. D. MacGillem and G. R. Copper, Continuous and Discrete Signal and System Analysis, 3rd ed., Philadelphia: Saunders, 1991.

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4 Fourier Series, Fourier Transforms, and the DFT 4.1 4.2

Introduction Fourier Series Representation of CT Periodic Signals The Exponential Fourier Series • The Trigonometric Fourier Series • Convergence of the Fourier Series

4.3

The Classical Fourier Transform for CT Signals Properties of the CT Fourier Transform • Fourier Spectrum of the CT Sampling Model • Fourier Transform of Periodic CT Signals • The Generalized Complex Fourier Transform

4.4

The Discrete-Time Fourier Transform Properties of the Discrete-Time Fourier Transform • The Relationship between the CT and DT Spectra

4.5

The Discrete Fourier Transform Properties of the Discrete Fourier Transform • Fourier Block Processing in Real-Time Filtering Applications • Fast Fourier Transform Algorithms

4.6 4.7 4.8

The FFT in Spectral Analysis • FIR Digital Filter Design • Transform Domain Adaptive Filtering

W. Kenneth Jenkins The Pennsylvania State University

The Family Tree of Fourier Transforms Walsh–Hadamard Transform Selected Applications of Fourier Methods

4.9

Summary

4.1 Introduction Fourier methods are commonly used for signal analysis and system design in modern telecommunica­ tions, radar, and image processing systems. Classical Fourier methods such as the Fourier series and the Fourier integral are used for continuous-time (CT) signals and systems, i.e., systems in which a charac­ teristic signal, s(t), is defined at all values of t on the continuum –∞ < t < ∞. A more recently developed set of Fourier methods, including the discrete-time Fourier transform and the discrete Fourier transform, are extensions of basic Fourier concepts that apply to discrete-time (DT) signals. A characteristic DT signal, s[n], is defined only for values of n where n is an integer in the range –∞ < n < ∞. The following discussion presents basic concepts and outlines important properties for both the CT and DT classes of Fourier methods, with a particular emphasis on the relationships between these two classes. The class of DT Fourier methods is particularly useful as a basis for digital signal processing (DSP) because it extends the theory of classical Fourier analysis to DT signals and leads to many effective algorithms that can be directly implemented on general computers or special purpose DSP devices.

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s a(t)

s(-2T)

s(-T)

-2T

-T

s(0)

0

s(T)

s(2T)

T

2T

FIGURE 4.1 Continuous-time (CT) model of a sampled CT signal.

The relationship between the continuous-time domain and the discrete-time domain is characterized by the operations of sampling and reconstruction. If sa(t) denotes a signal s(t) that has been uniformly sampled every T seconds, then the mathematical representation of sa(t) is given by sa (t ) =

∞

∑ s(t )δ(t − nT ),

(4.1)

n = −∞

where δ(t) is a CT impulse function defined to be zero for all t ≠ 0, undefined at t = 0, and has unit area when integrated from t = –∞ to t = +∞. Since the only places where the product s(t)δ(t – nT) is not identically equal to zero are at the sampling instances, s(t) in Eq. (4.1) can be replaced with s(nT) without changing the overall meaning of the expression. Hence, an alternate expression for sa(t) that is often useful in Fourier analysis is given by sa (t ) =

∞

∑ s(nT )δ(t − nT ).

(4.2)

n = −∞

The CT sampling model sa(t) consists of a sequence of CT impulse functions uniformly spaced at intervals of T seconds and weighted by the values of the signal s(t) at the sampling instants, as depicted in Fig. 4.1. Note that sa(t) is not defined at the sampling instants because the CT impulse function itself is not defined at t = 0. However, the values of s(t) at the sampling instants are imbedded as “area under the curve” of sa(t), and as such represent a useful mathematical model of the sampling process. In the discrete-time domain, the sampling model is simply the sequence defined by taking the values of s(t) at the sampling instants, i.e., s[n] = s(t )

t −nT

.

(4.3)

In contrast to sa(t), which is not defined at the sampling instants, s[n] is well defined at the sampling instants, as illustrated in Fig. 4.2. From this discussion it is now clear that sa(t) and s[n] are different but s [n ] s(0) s(-T)

-2

-1

s(2T)

0

s(-2T)

FIGURE 4.2 Discrete-time (DT) model of a sampled CT signal. © 2003 by CRC Press LLC

1

s(T)

2

n

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Fourier Series, Fourier Transforms, and the DFT

equivalent models of the sampling process in the CT domain and the DT domain, respectively. They are both useful for signal analysis in their corresponding domains. It will be shown later that their equivalence is established by the fact that they have equal spectra in the Fourier domain, and that the underlying CT signal from which sa(t) and s[n] are derived can be recovered from either sampling representation, provided a sufficiently large sampling rate is used in the sampling operation.

4.2 Fourier Series Representation of CT Periodic Signals It is convenient to begin the discussion with the classical Fourier series representation of a periodic time domain signal, and then derive the Fourier integral from this representation by finding the limit of the Fourier coefficient representation as the period goes to infinity. The conditions under which a periodic signal s(t) can be expanded in a Fourier series are known as the Dirichet conditions. They require that in each period s(t) has a finite number of discontinuities, a finite number of maxima and minima, and that s(t) satisfies the following absolute convergence criterion [1]: T 2

∫

s(t ) dt < ∞

(4.4)

−T 2

It is assumed in the following discussion that these basic conditions are satisfied by all functions that will be represented by a Fourier series.

The Exponential Fourier Series If a CT signal s(t) is periodic with a period T, then the classical complex Fourier series representation of s(t) is given by s(t ) =

∞

∑a e

jnω 0t

(4.5a)

n

n = −∞

where ω0 = 2π/T, and where the an are the complex Fourier coefficients given by T 2

an = (1 T )

∫ s(t )e

− jnω 0t

dt .

(4.5b)

−T 2

It is well known that for every value of t where s(t) is continuous, the right-hand side of Eq. (4.5a) converges to s(t). At values of t where s(t) has a finite jump discontinuity, the right-hand side of Eq. (4.5a) converges to the average of s(t –) and s(t +), where s(t –) ≡ limε → 0 s(t – ε) and s(t+) ≡ limε → 0 s(t + ε). For example, the Fourier series expansion of the sawtooth waveform illustrated in Fig. 4.3 is charac­ terized by T = 2π, ω0 = 1, a0 = 0, and an = a–n = Acos(nπ)/(jnπ) for n = 1, 2, …. The coefficients of the exponential Fourier series represented by Eq. (4.5b) can be interpreted as the spectral representation of s(t), since the an-th coefficient represents the contribution of the (nω0)-th frequency to the total signal s(t). Because the an are complex valued, the Fourier domain representation has both a magnitude and phase spectrum. For example, the magnitude of the an is plotted in Fig. 4.4 for the sawtooth waveform of Fig. 4.3. The fact that the an constitute a discrete set is consistent with the fact that a periodic signal has a “line spectrum,” i.e., the spectrum contains only integer multiples of the fundamental frequency ω0. Therefore, the equation pair given by Eqs. (4.5a) and (4.5b) can be interpreted as a transform pair that is similar to the CT Fourier transform for periodic signals. This leads to the observation that the classical Fourier series can be interpreted as a special transform that provides a one-to-one invertible mapping between the discrete-spectral domain and the continuous-time domain. The next section © 2003 by CRC Press LLC

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���� � � ��

�π

��π

�π

�π�

FIGURE 4.3 Periodic CT signal used in Fourier series example.

� � � �

��π� ��� π� ��

��

��

��

�

�

�

�

�

�

FIGURE 4.4 Magnitude of the Fourier coefficients for example of Fig. 4.3.

demonstrates how the periodicity constraint can be removed to produce the more general classical CT Fourier transform that applies equally well to periodic and aperiodic time domain waveforms.

The Trigonometric Fourier Series Although Fourier series expansions exist for complex periodic signals, and Fourier theory can be gener­ alized to the case of complex signals, the theory and results are more easily expressed for real-valued signals. In the following discussion it will be assumed that the signal s(t) is real-valued for the sake of simplifying the discussion. However, all results are valid for complex signals, although the details of the theory will become somewhat more complicated. For real-valued signals s(t), it is possible to manipulate the complex exponential form of the Fourier series into a trigonometric form that contains sin(ω0t) and cos(ω0t) terms with corresponding real-valued coefficients [1]. The trigonometric form of the Fourier series for a real-valued signal s(t) is given by s(t ) =

∞

∑ n=0

bn cos(nω 0t ) +

∞

∑ c sin(nω t ), n

0

(4.6a)

n =1

where ω0 = 2π/T. The bn and cn are real-valued Fourier coefficients determined by T 2

b0 = (1 T )

∫ s(t ) dt

−T 2 T 2

bn = (2 T )

∫ s(t ) cos(nω t )dt, 0

n = 1, 2, …

−T 2 T 2

c n = (2 T )

∫ s(t ) sin(nω t )dt , 0

−T 2

© 2003 by CRC Press LLC

n = 1, 2, …,

(4.6b)

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93

Fourier Series, Fourier Transforms, and the DFT

����

�� π

�

π ��

π�

�

��π

FIGURE 4.5 Periodic CT signal used in Fourier series example 2.

�� �� ��� π� ��

��

��

�

�

�

�

�

FIGURE 4.6 Fourier coefficients for example of Fig. 4.5.

An arbitrary real-valued signal s(t) can be expressed as a sum of even and odd components, s(t) = seven(t) + sodd(t), where seven(t) = seven(–t) and sodd(t) = –sodd(–t), and where seven(t) = [s(t) + s(–t)]/2 and sodd(t) = [s(t) – s(–t)]/2 . For the trigonometric Fourier series, it can be shown that seven(t) is represented by the (even) cosine terms in the infinite series, sodd(t) is represented by the (odd) sine terms., and b0 is the DC level of the signal. Therefore, if it can be determined by inspection that a signal has a DC level, or if it is even or odd, then the correct form of the trigonometric series can be chosen to simplify the analysis. For example, it is easily seen that the signal shown in Fig. 4.5 is an even signal with a zero DC level. Therefore, it can be represented accurately by the cosine series with bn = 2Asin(πn/2)/(πn/2), n = 1, 2, … as illustrated in Fig. 4.6. In contrast, note that the sawtooth waveform used in the previous example is an odd signal with zero DC level, so that it can be completely specified by the sine terms of the trigonometric series. This result can be demonstrated by pairing each positive frequency component from the exponential series with its conjugate partner, i.e., cn = sin(nω0t) = ane jnω0t + a–ne–jnω0t, whereby it is found that cn = 2Acos(nπ)/(nπ) for this example. In general, it is found that an = (bn – jcn)/2 for n = 1, 2, …, a0 = b0, and a–n = an*. The trigonometric Fourier series is common in the signal processing literature because it replaces complex coefficients with real ones and often results in a simpler and more intuitive interpretation of the results.

Convergence of the Fourier Series The Fourier series representation of a periodic signal is an approximation that exhibits mean squared convergence to the true signal. If s(t) is a periodic signal of period T, and s′(t) denotes the Fourier series approximation of s(t), then s(t) and s′(t) are equal in the mean square sense if T 2

MSE =

∫

2

s(t ) − s(t )′ dt = 0.

(4.7)

−T 2

Even with Eq. (4.7) satisfied, mean square error (MSE) convergence does not mean that s(t) = s′(t) at every value of t. In particular, it is known that at values of t where s(t) is discontinuous, the Fourier series converges to the average of the limiting values to the left and right of the discontinuity. For example if t0 is a point of discontinuity, then s′(t0) = [s(t0–) + s(t0+)]/2, where s(t0–) and s(t0+) were defined previously (note that at points of continuity, this condition is also satisfied by the very definition of continuity). © 2003 by CRC Press LLC

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Because the Dirichet conditions require that s(t) have at most a finite number of points of discontinuity in one period, the set St such that s(t) ≠ s′(t) within one period contains a finite number of points, and St is a set of measure zero in the formal mathematical sense. Therefore, s(t) and its Fourier series expansion s′(t) are equal almost everywhere, and s(t) can be considered identical to s′(t) for the analysis of most practical engineering problems. Convergence almost everywhere is satisfied only in the limit, as an infinite number of terms are included in the Fourier series expansion. If the infinite series expansion of the Fourier series is truncated to a finite number of terms, as it must always be in practical applications, then the approximation will exhibit an oscillatory behavior around the discontinuity, known as the Gibbs phenomenon [1]. Let sN′(t) denote a truncated Fourier series approximation of s(t), where only the terms in Eq. (4.5a) from n = –N to n = N are included if the complex Fourier series representation is used, or where only the terms in Eq. (4.6a) from n = 0 to n = N are included if the trigonometric form of the Fourier series is used. It is well known that in the vicinity of a discontinuity at t0 the Gibbs phenomenon causes sN′(t) to be a poor approximation to s(t). The peak magnitude of the Gibbs oscillation is 13% of the size of the jump discontinuity s(t0–) – s(t0+) regardless of the number of terms used in the approximation. As N increases, the region that contains the oscillation becomes more concentrated in the neighborhood of the discontinuity, until, in the limit as N approaches infinity, the Gibbs oscillation is squeezed into a single point of mismatch at t0. If s′(t) is replaced by sN′(t) in Eq. (4.7), it is important to understand the behavior of the error mseN as a function of N, where T 2

MSE N =

∫

s(t ) − s N ′ (t ) dt . 2

(4.8)

−T 2

An important property of the Fourier series is that the exponential basis functions e jnω0t (or sin(nω0t) and cos(nω0t) for the trigonometric form) for n = 0, ± 1, ± 2, … (or n = 0, 1, 2, … for the trigonometric form) constitute an orthonormal set, i.e., tnk = 1 for n = k, and tnk = 0 for n ≠ k, where T 2

t nk = (1 T )

∫ (e )(e )dt . − jnω 0t

jkω 0t

(4.9)

−T 2

As terms are added to the Fourier series expansion, the orthogonality of the basis functions guarantees that the error decreases in the mean square sense, i.e., that MSEN monotonically decreases as N is increased. Therefore, a practitioner can proceed with the confidence that when applying Fourier series analysis more terms are always better than fewer in terms of the accuracy of the signal representations.

4.3 The Classical Fourier Transform for CT Signals The periodicity constraint imposed on the Fourier series representation can be removed by taking the limits of Eqs. (4.5a) and (4.5b) as the period T is increased to infinity. Some mathematical preliminaries are required so that the results will be well defined after the limit is taken. It is convenient to remove the (1/T) factor in front of the integral by multiplying Eq. (4.5b) through by T, and then replacing Tan by an′ in both (4.5a) and (4.5b). Because ω0 = 2π/T, as T increases to infinity, ω0 becomes infinitesimally small, a condition that is denoted by replacing ω0 by ∆ω. The factor (1/T) in Eq. (4.5a) becomes (∆ω/ 2π). With these algebraic manipulations and changes in notation, Eqs. (4.5a) and (4.5b) take on the following form prior to taking the limit: s(t ) = (1 2π)

∞

∑ a′ e

n = −∞

© 2003 by CRC Press LLC

n

jn∆ωt

∆ω

(4.10a)

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Fourier Series, Fourier Transforms, and the DFT

T 2

a′n =

∫ s(t )e

− jn∆ωt

dt

(4.10b)

−T 2

The final step in obtaining the CT Fourier transform is to take the limit of both Eqs. (4.10a) and (4.10b) as T → ∞. In the limit, the infinite summation in Eq. (4.10a) becomes an integral, ∆ω becomes dω, n∆ω becomes ω, and an′ becomes the continuous-frequency Fourier transform of s(t), denoted by S(jω). The result is summarized by the following transform pair, which is known throughout most of the engineering literature as the classical CT Fourier transform: ∞

∫

s(t ) = (1 2π) S( jω )e jωt dω

(4.11a)

−∞

S( jΩ) =

∞

∫ s(t )e

− jΩt

dt

(4.11b)

−∞

Often, Eq. (4.11a) is called the Fourier integral and Eq. (4.11b) is simply called the Fourier transform. The relationship S(j Ω) = � {s(t)} denotes the Fourier transformation of s(t), where � { . } is a symbolic notation for the Fourier transform operator, and where Ω becomes the continuous frequency variable after the periodicity constraint is removed. A transform pair s(t) ↔ S(j Ω) represents a one-to-one invertible mapping as long as s(t) satisfies conditions which guarantee that the Fourier integral converges. (More mathematical details of the CT Fourier transform are presented in Chapter 6, “Wavelet Transforms.” From Eq. (4.11a) it is easily seen that � {δ(t – t0)} = e –jωt0, and from Eq. (4.11b) that � –1{2πδ(ω – ω0)} = e jω0t, so that δ(t – t0) ↔ e –jωt0 and e jω0t ↔ 2πδ(ω – ω0) are valid Fourier transform pairs. Using these relationships, it is easy to establish the Fourier transforms of cos(ω0t) and sin(ω0t), as well as many other useful waveforms that are encountered in common signal analysis problems. A number of such transforms are shown in Table 4.1. The CT Fourier transform is useful in the analysis and design of CT systems, i.e., systems that process CT signals. Fourier analysis is particularly applicable to the design of CT filters which are characterized by Fourier magnitude and phase spectra, i.e., by H(jω) and arg H(jω), where H(jω) is commonly called the frequency response of the filter. For example, an “ideal” transmission channel is one that passes a signal without distorting it. The signal may be scaled by a real constant A and delayed by a fixed time increment t0, implying that the impulse response of an ideal channel is Aδ(t – t0), and its corresponding frequency response is Ae –jωt0. Hence, the frequency response of an ideal channel is specified by constant amplitude for all frequencies, and a phase characteristic that is a linear function given by ωt0.

Properties of the CT Fourier Transform The CT Fourier transform has many properties that make it useful for the analysis and design of linear CT systems. Some of the more useful properties are stated below. A more complete list of the CT Fourier transform properties is given in Table 4.2. Proofs of these properties can be found in References [2] and [3]. In the following discussion �{·} denotes the Fourier transform operation, � –1{·} denotes the inverse Fourier transform operation, and ∗ denotes the convolution operation defined as f1 (t ) ∗ f 2 (t ) =

∞

∫ f (t − τ) f (τ)dτ. 1

2

−∞

1. Linearity (superposition): �{af1(t) + bf2(t)} = a�{f1(t)} + b�{f2(t)}

(a and b, complex constants)

2. Time-Shifting: �{f(t – t0)} = e –jωt0�{f(t)} © 2003 by CRC Press LLC

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TABLE 4.1

Some Basic CT Fourier Transform Pairs

Signal +∞

∑

Fourier Series Coefficients (if periodic)

Fourier Transform +∞

ak e jkω0t

2π

k = −∞

∑ a δ(ω k

k = −∞

k

− ω 0 )

ak

ejω0t

2πδ(ω – ω0)

cos ω0t

π δ(ω − ω 0 ) + δ(ω + ω 0 )

[ [

] ]

π δ(ω − ω 0 ) − δ(ω + ω 0 ) j 2πδ(ω)

sin ω0t x(t) = 1

a1 = 1 ak = 0, otherwise a1 = a–1 = 1/2 ak = 0, otherwise a1 = –a–1 = 1/2j ak = 0, otherwise a0 = 1, ak = 0, k ≠ 0 (has this Fourier series representation for any choice of T0 > 0)

Periodic square wave 1, t < T1  x (t ) =  T0 0, T1 < t ≤ 2 and x(t + T0) = x(t)

+∞

∑

2sinkω 0T1 δ(ω k ω 0 ) k

∑ δ(t − nT )

2π T

+∞

1, t < T1 x (t ) =  0, t > T1

 ωT  2sin ωT1 2T1 sinc  1  =  π  ω

W  Wt  sinWt sinc  =  π  π πt

1, ω < W X (ω ) =  0, ω > W 1 1 + πδ(ω ) jω e –jωt0 1 a + jω 1

k = −∞

+∞

n= −∞

δ(t) u(t) δ(t – t0) e u(t ),Re{a} > 0 −at

te −at u(t ),Re{a} > 0 t

n−1

∑k = −∞δ ω −

(a + jω)

e −at u(t ),

(n −1)! Re{a} > 0

2

1

(a + jω)

n

2πk   T 

ω 0T1  kω T  sinkω 0T1 sinc  0 1  =  π  π kπ

ak =

1 T

for all k

—

— — — — — —

—

Source: A.V. Oppenheim et al., Signals and Systems, Englewood Cliffs, NJ: Prentice Hall, 1983.

3. 4. 5. 6.

Frequency-Shifting: e jω 0tf(t) = � –1{F(j(ω-ω0))} Time-Domain Convolution: �{ f1(t) ∗ f2(t)} = � f1(t)}�{f2(t)} Frequency-Domain Convolution: �{f1(t)f2(t)} = (1/2π)�{f1(t)} ∗ �{f2(t)} Time-Differentiation: –jωF(jω) = �{d(f(t))/dt}

t 7. Time-Integration: � ∫ f ( τ)dτ  = (1/jω)F(jω) + πF(0)δ(ω)



−∞



These properties are particularly useful in CT system analysis and design, especially when the system characteristics are easily specified in the frequency domain, as in linear filtering. Note that properties 1, 6, and 7 are useful for solving differential or integral equations. Property 4 (time-domain convolution) provides the basis for many signal processing algorithms, since many systems can be specified directly by their impulse or frequency response. Property 3 (frequency-shifting) is particularly useful in analyzing © 2003 by CRC Press LLC

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TABLE 4.2

Properties of the CT Fourier Transform If � f (t ) = F ( jω ), then

Name f ( jω ) =

Definition

f (t ) = Superposition

∫

∞

f (t )e − j ω t dt

−∞

1 2π

[

∫

∞

−∞

F ( jω )e j ω t dω

]

� af1 (t ) + bf 2 (t ) = aF1 ( jω ) + bF2 ( jω )

Simplification if: (a) f(t) is even (b) f(t) is odd

F ( jω ) = 2

∫

F ( jω ) = 2 j

∞

0

∫

f (t ) cosωt dt

∞

0

f (t ) sin ωt dt

� f ( −t ) = F ∗ ( jω )

Negative t Scaling:

1  jω  F  a  a 

(a) time

� f (at ) =

(b) magnitude

�af (t ) = aF ( jω )

Differentiation

 dn  n �  n f (t ) = ( jω ) F ( j ω )  dt 

Integration

 �  

Time shifting

� f (t − a) = F ( jω ) e − j ωt

Modulation

� f (t )e jω0t = F j(ω − ω 0 )

∫

t

−∞

 1 f ( x ) dx  = F ( jω ) + πF (0) δ (ω )  jω

[

]

� f (t ) cosω 0t =

1 2

� f (t ) sin ω 0t =

1 2

[

{F [ j (ω − ω )] + F [ j (ω + ω )]} j{F [ j (ω − ω )] − F [ j (ω + ω )]} 0

0

0

∞

] ∫ f (τ) f (t − τ)dτ

Time convolution

� −1 F1 ( jω ) F2 ( jω ) =

Frequency convolution

� f1 (t ) f 2 (t ) =

[

0

]

1 2π

∫

−∞

∞

−∞

1

2

[

]

F1 ( jλ ) F2 j(ω − λ ) dλ

Source: M.E. VanValkenburg, Network Analysis, 3rd ed., Englewood Cliffs, NJ: Prentice Hall, 1974.

communication systems where different modulation formats are commonly used to shift spectral energy to frequency bands that are appropriate for the application.

Fourier Spectrum of the CT Sampling Model The CT sampling model sa(t), given in Eq. (4.1), is in its own right a CT signal, therefore, it is appropriate to apply the CT Fourier transform to obtain an expression for the spectrum of the sampled signal. ∞  ∞  � sa (t ) = �  s(t )δ(t − nT ) = s(nT )e − j ωTn n = −∞  n = −∞

{ }

© 2003 by CRC Press LLC

∑

∑



(4.12)

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2π c

-2

-2

{s(t)}

2 πc

2πc

-1

2 πc

0

-1

ö

�

1

1

0

2sc

2

2

n

FIGURE 4.7 Spectrum of the Fourier series representation of s(t).

Because the expression on the right-hand side of Eq. (4.12) is a function of e jωT it is customary to denote the transform as F(e jωT) = �{sa(t)}. Later in the chapter, this result will be compared with the result of operating on the DT sampling model, namely s[n], with the discrete-time Fourier transform to illustrate that the two sampling models have the same spectrum.

Fourier Transform of Periodic CT Signals It was demonstrated earlier that a periodic CT signal can be expressed in terms of its Fourier series. The CT Fourier transform can then be applied to the Fourier series representation of s(t) to produce a mathematical expression for the “line spectrum” characteristic of a periodic signals.

{ }

� s(t )

∞  ∞  jnω 0t  = � ane anδ(ω − nω 0 )  = 2π n = −∞  n = −∞

∑

∑

(4.13)

The spectrum is shown pictorially in Fig. 4.7. Note the similarity between the spectral representation of Fig. 4.7 and the plot of the Fourier coefficients in Fig. 4.4, which was heuristically interpreted as a “line spectrum.” Figures 4.4 and 4.7 are different, but equivalent, representations of the Fourier spectrum. Note that Fig. 4.4 is a DT representation of the spectrum, while Fig. 4.7 is a CT model of the same spectrum.

The Generalized Complex Fourier Transform The CT Fourier transform characterized by Eqs. (4.11a) and (4.11b) can be generalized by considering the variable jω to be the special case of u = σ +jω with σ = 0, writing Eq. (4.11) in terms of u, and interpreting u as a complex frequency variable. The resulting complex Fourier transform pair is given by Eqs. (4.14a) and (4.14b). σ + j∞

s(t ) = (1 2πj )

∫ S(u)e

jut

du

(4.14a)

σ − j∞

S(u) =

∞

∫ s(t )e

− jut

dt

(4.14b)

−∞

The set of all values of u for which the integral of Eq. (4.14b) converges is called the region of convergence, denoted ROC. The transform S(u) is defined only for values of u within the ROC, therefore, the path of integration in Eq. (4.14a) must be defined by σ so the entire path lies within the ROC. In some literature this transform pair is called the bilateral Laplace transform because it is the same result obtained by including both the negative and positive portions of the time axis in the classical Laplace transform integral. [Note that in Eq. (4.14) the complex frequency variable was denoted by u, instead of by the more common s, in order to avoid confusion with earlier uses of s(·) as signal notation.] The complex © 2003 by CRC Press LLC

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Fourier transform (bilateral Laplace transform) is not used often in solving practical problems, but its significance lies in the fact that it is the most general form that represents the point where Fourier and Laplace transform concepts become the same. Identifying this connection reinforces the notion that Fourier and Laplace transform concepts are similar because they are derived by placing different con­ straints on the same general form. (For more reading on the Laplace transform, see Chapter 3.)

4.4 The Discrete-Time Fourier Transform The discrete-time Fourier transform (DTFT) can be obtained by using the DT sampling model and considering the relationship obtained in Eq. (4.12) to be the definition of the DTFT. Letting T = 1 so that the sampling period is removed from the equations and the frequency variable is replaced with a normalized frequency ω′ = ωT, the DTFT pair is defined in Eq. (4.15). Note that in order to simplify notation it is not customary to distinguish between ω and ω’, but instead to rely on the context of the discussion to determine whether ω refers to the normalized (T = 1) or the unnormalized (T ≠ 1) frequency variable. ∞

( ) ∑ s[n]e

S e jω′ =

− jω′n

(4.15a)

n = −∞ π

∫( )

s[n] = (1 2π) S e jω′ e jnω′ dω′.

(4.15b)

−π

The spectrum S(e jω′) is periodic in ω′ with period 2π. The fundamental period in the range –π < ω′ ≤ π, sometimes referred to as the baseband, is the useful frequency range of the DT system because frequency components in this range can be represented unambiguously in sampled form (without aliasing error). In much of the signal processing literature, the explicit primed notation is omitted from the frequency variable. However, the explicit primed notation will be used throughout this section because there is a potential for confusion when so many related Fourier concepts are discussed within the same framework. By comparing Eq. (4.12) and Eq. (4.15a), and noting that ω′ = ωT, it is seen that

{ }

{ }

� sa (t ) = DTFT s[n]

(4.16)

where s[n] = s(t)t = nT . This demonstrates that the spectrum of sa(t) as calculated by the CT Fourier transform is identical to the spectrum of s[n] as calculated by the DTFT. Therefore, although sa(t) and s[n] are quite different sampling models, they are equivalent in the sense that they have the same Fourier domain representation. A list of common DTFT pairs is presented in Table 4.3. Just as the CT Fourier transform is useful in CT signal system analysis and design, the DTFT is equally useful in the same capacity for DT systems. It is indeed fortuitous that Fourier transform theory can be extended in this way to apply to DT systems. In the same way that the CT Fourier transform was found to be a special case of the complex Fourier transform (or bilateral Laplace transform), the DTFT is a special case of the bilateral z-transform with z = e jω′t. The more general bilateral z-transform is given by: S( z ) =

∞

∑ s[n]z

−n

(4.17a)

n = −∞

∫

s[n] = (1 2πj ) S( z ) z n−1 dz , C

© 2003 by CRC Press LLC

(4.17b)

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TABLE 4.3

Some Basic DT Fourier Transform Pairs

Sequence

Fourier Transform

1.

δ[n]

1

2.

δ[n – n0]

e − jωn0

3.

1 (–∞ < n < ∞)

∞

∑ 2πδ(ω + 2πk)

k = −∞

4.

anu[n] (a < 1)

1 1 − ae − jω

5.

u[n]

1 πδ(ω + 2πk ) + 1 − e − jω k = −∞

6.

(n + 1)anu[n] (a < 1)

7.

r n sinω p (n +1)

∞

8.

∑

sin ω p

(

(1 − ae ) − jω

)

u[n] r 2ωc , then the DT spectrum is a copy of S(jω) (scaled by 1/T) in the baseband. The limiting case of ωs = 2ωc is called the Nyquist sampling frequency. Whenever a CT signal is sampled at or above the Nyquist rate, no aliasing distortion occurs (i.e., the baseband spectrum does not overlap with the higher order replicas) and the CT signal can be

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|S(e

jω '

)|

Baseband Spectrum T

0

ω'c

ˆ

ˆ

- ω'c

-2 s

2s

ω'

FIGURE 4.8 Illustration of the relationship between the CT and DT spectra.

exactly recovered from its samples by extracting the baseband spectrum of S(e jω′) with an ideal low-pass filter that recovers the original CT spectrum by removing all spectral replicas outside the baseband and scaling the baseband by a factor of T.

4.5 The Discrete Fourier Transform To obtain the discrete Fourier transform (DFT) the continuous-frequency domain of the DTFT is sampled at N points uniformly spaced around the unit circle in the z-plane, i.e., at the points ωk = (2πk/N), k = 0, 1, …, N – 1. The result is the DFT transform pair defined by Eqs. (4.20a) and (4.20b). The signal s[n] is either a finite length sequence of length N, or it is a periodic sequence with period N. S[k ] =

N-1

∑ s[n]e

− j 2πkn N

k = 0, 1, …, N ­ 1

(4.20a)

n=0

N-1

∑ S[k]e

s[n] = (1 N )

j 2πkn N

n = 0, 1, …, N ­ 1

(4.20b)

n=0

Regardless of whether s[n] is a finite length or periodic sequence, the DFT treats the N samples of s[n] as though they characterize one period of a periodic sequence. This is an important feature of the DFT, and one that must be handled properly in signal processing to prevent the introduction of artifacts. Important properties of the DFT are summarized in Table 4.5. The notation ([k])N denotes k modulo N, and RN[n] is a rectangular window such that RN[n] = 1 for n = 0, …, N-1, and RN[n] = 0 for n < 0 and n ≥ N. The transform relationship given by Eqs. (4.20a) and (4.20b) is also valid when s[n] and S[k] are periodic sequences, each of period N. In this case, n and k are permitted to range over the complete set of real integers, and S[k] is referred to as the discrete Fourier series (DFS). The DFS is developed by some authors as a distinct transform pair in its own right [6]. Whether or not the DFT and the DFS are considered identical or distinct is not very important in this discussion. The important point to be emphasized here is that the DFT treats s[n] as though it were a single period of a periodic sequence, and all signal processing done with the DFT will inherit the consequences of this assumed periodicity.

Properties of the Discrete Fourier Transform Most of the properties listed in Table 4.5 for the DFT are similar to those of the Z-transform and the DTFT, although there are some important differences. For example, Property 5 (time-shifting property), holds for circular shifts of the finite length sequence s[n], which is consistent with the notion that the DFT treats s[n] as one period of a periodic sequence. Also, the multiplication of two DFTs results in the circular convolution of the corresponding DT sequences, as specified by Property 7. This later property is quite different from the linear convolution property of the DTFT. Circular convolution is the result of the assumed periodicity discussed in the previous paragraph. Circular convolution is simply a linear

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TABLE 4.5

Properties of the DFT

Finite-Length Sequence (Length N)

N-Point DFT (Length N)

1. x[n]

X [k ]

2. x1[n], x 2 [n]

X1[k ], X 2 [k

3. ax1[n] + bx 2 [n]

aX1[k ] + bX 2 [k ]

4. X [n]

Nx ( −k )

[(

)

5. x (n − m)

N

]

)

WNkm X [

]

[(

6. WN−ln x[n]

∑ x (m)x [((n − m)) ] 1

2

]

N

)

X (k − l )

N −1

7.

[(

N

]

X1[k ] X 2 [k ]

N

m=0

N −1

8. x1[n] x 2 [n]

1 N

∑ X (l) X [((k − l)) ]

9. x ∗ [n]

X∗

[((−k)) ]

10. x ∗

1

X ∗ [k ]

{ }

X ep[k ] =

1 2

X op[k ] =

1 2

11. Re x[n]

{ }

12. j Im x[n] 13. x ep[n] =

1 2

14. x op[n] =

1 2

{ [ ] [(( )) ]} { [ ] [(( )) ]} x n + x∗

−n

x n − x∗

−n

N

N

[((−n)) ] N

2

l =0

{ [(( )) ] [(( )) ]} { [(( )) ] [(( )) ]} X k

X k

N

N

+ X∗

−k

− X∗

−k

N

N

{ }

N

Re X [k ]

N

j Im X [

{ ]}

Properties 15–17 apply only when x[n] is real.

15. Symmetry properties

16. x ep[n] =

1 2

17. x op[n] =

1 2

{ [ ] [(( )) ]} { [ ] [(( )) ]} x n +x

−n

x n −x

−n

[((−k)) ] {X[k]} = Re{X[((−k)) ]} {X[k]} = −lm{X[((−k)) ]} X [k ] = X [(( −k )) ] {X[k]} = −  {X[((−k)) ]}

    Re  lm      

X [k ] = X ∗

N

N

N

N

N

{ }

N

Re X [k ]

N

j Im X[k ]

{ }

Source: A.V. Oppenheim and R.W. Schafer, Discrete-Time Signal Processing, Engle­ wood Cliffs, NJ: Prentice Hall, 1989.

convolution of the periodic extensions of the finite sequences being convolved, where each of the finite sequences of length N defines the structure of one period of the periodic extensions. For example, suppose it is desired to implement a digital filter with finite impulse response (FIR) h[n]. The output in response to s[n] is

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y[n] =

N-1

∑ h[k]s[n − k],

(4.21)

k=0

which is obtained by transforming h[n] and s[n] into H[k] and S[k] using the DFT, multiplying the transforms point-wise to obtain Y[k] = H[k]S[k], and then using the inverse DFT to obtain y[n] = DFT–1{Y[k]}. If s[n] is a finite sequence of length M, then the results of the circular convolution imple­ mented by the DFT will correspond to the desired linear convolution if and only if the block length of the DFT, NDFT, is chosen sufficiently large so that NDFT > N + M and both h[n] and s[n] are padded with zeros to form blocks of length NDFT .

Fourier Block Processing in Real-Time Filtering Applications In some practical applications, either the value of M is too large for the memory available, or s[n] may not actually be finite in length, but rather a continual stream of data samples that must be processed by a filter at real-time rates. Two well-known algorithms are available that partition s[n] into smaller blocks and process the individual blocks with a smaller-length DFT: (1) overlap-save partitioning and (2) overlap-add partitioning. Each of these algorithms is summarized next. Overlap-Save Processing In this algorithm, NDFT is chosen to be some convenient value with NDFT > N. The signal s[n], is partitioned into blocks which are of length NDFT and which overlap by N – 1 data points. Hence, the kth block is sk[n] = s[n + k(NDFT – N + 1)], n = 0, …, NDFT – 1. The filter is an augmented filter with NDFT – N zeros to produce h[n], hpad [n] =   0,

n = 0, …, N -1   n = N , …, N DFT 

(4.22)

The DFT is then used to obtain Ypad[n] = DFT{hpad[n]} · DFT{sk[n]}, and ypad[n] = IDFT{Ypad[n]}. From the ypad[n] array, the values that correctly correspond to the linear convolution are saved; values that are erroneous due to wrap-around error caused by the circular convolution of the DFT are discarded. The kth block of the filtered output is obtained by  y pad [n], y k [n] =   0,

n = N -1, …, N DFT -1   n = N , …, N DFT -1 

(4.23)

For the overlap-save algorithm, each time a block is processed there are NDFT – N +1 points saved and N – 1 points discarded. Each block moves forward by NDFT – N +1 data points and overlaps the previous block by N – 1 points. Overlap-Add Processing This algorithm is similar to the previous one except that the kth input block is defined to be s[n + kL], sk [n] =   0,

n = 0, …, L −1   n = L, …, N DFT -1

(4.24)

where L = NDFT – N + 1. The filter function hpad[n] is augmented with zeros, as before, to create hpad[n], and the DFT processing is executed as before. In each block ypad[n] that is obtained at the output, the first N – 1 points are erroneous, the last N – 1 points are erroneous, and the middle NDFT – 2(N – 1) points correctly correspond to the linear convolution. However, if the last N – 1 points from block k are © 2003 by CRC Press LLC

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overlapped with the first N – 1 points from block k + 1 and added pairwise, correct results corresponding to linear convolution are obtained from these positions as well. Hence, after this addition the number of correct points produced per block is NDFT – N + 1, which is the same as that for the overlap-save algorithm. The overlap-add algorithm requires approximately the same amount of computation as the overlap-save algorithm, although the addition of the overlapping portions of blocks is extra. This feature, together with the extra delay of waiting for the next block to be finished before the previous one is complete, has resulted in more popularity for the overlap-save algorithm in practical applications. Block filtering algorithms make it possible to efficiently filter continual data streams in real time because the the FFT algorithm can be used to implement the DFT, thereby minimizing the total com­ putation time and permitting reasonably high overall data rates. However, block filtering generates data in bursts, i.e., there is a delay during which no filtered data appears, and then suddenly an entire block is generated. In real-time systems, buffering must be used. The block algorithms are particularly effective for filtering very long sequences of data that are pre-recorded on magnetic tape or disk.

Fast Fourier Transform Algorithms The DFT is typically implemented in practice with one of the common forms of the fast Fourier transform (FFT) algorithm. The FFT is not a Fourier transform in its own right, but rather it is simply a compu­ tationally efficient algorithm that reduces the complexity of the computing DFT from Order {N2} to Order {Nlog2N}. When N is large, the computational savings provided by the FFT algorithm is so great that the FFT makes real-time DFT analysis practical in many situations that would be entirely impractical without it. There are numerous FFT algorithms, including decimation-in-time (D-I-T) algorithms, decimation-in-frequency (D-I-F) algorithms, bit-reversed algorithms, normally-ordered algorithms, mixed-radix algorithms (for block lengths that are not powers-of-2), prime factor algorithms, and Winograd algorithms [7]. The D-I-T and the D-I-F radix-2 FFT algorithms are the most widely used in practice. Detailed discussions of various FFT algorithms can be found in References [3], [6], [7], and [10]. The FFT is easily understood by examining the simple example of N = 8. There are numerous ways to develop the FFT algorithm, all of which deal with a nested decomposition of the summation operator of Eq. (4.20a). The development presented here is called an algebraic development of the FFT because it follows straightforward algebraic manipulation. First, each of the summation indices (k, n) in Eq. (4.20a) is expressed as explicit binary integers, k = k24 + k12 + k0 and n = n24 + n12 + n0, where ki and ni are bits that take on the values of either 0 or 1. If these expressions are substituted into Eq. (4.20a), all terms in the exponent that contain the factor N = 8 can be deleted because e–j2πl = 1 for any integer l. Upon deleting such terms and re-grouping the remaining terms, the product nk can be expressed in either of two ways: nk = ( 4k0 )n2 + ( 4k1 + 2k0 )n1 + ( 4k2 + 2k1 + k0 )n0

(4.25a)

nk = ( 4k0 )k2 + ( 4n1 + 2n0 )k1 + ( 4n2 + 2n1 + n0 )k0

(4.25b)

Substituting Eq. (4.25a) into Eq. (4.20a) leads to the D-I-T FFT, whereas substituting Eq. (4.25b) leads to the D-I-F FFT. Only the D-I-T FFT is discussed further here. The D-I-F and various related forms are treated in detail in [4, 6]. The D-I-T FFT decomposes into log2N stages of computation, plus a stage of bit reversal,

[

]

x1 k0 , n1 , n0 =

[

]

x 2 k0 , k1 , n0 =

© 2003 by CRC Press LLC

1

∑ s[n ,n ,n ]W 2

1

0

4k0n2 8

(stage 1)

(4.26a)

(stage 1)

(4.26b)

n2 = 0 1

∑ x[k ,n ,n ]W ( 0

n1 = 0

1

0

8

4k1 +2k0 )n2

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Fourier Series, Fourier Transforms, and the DFT

[

]

1

x 3 k0 , k1 , k2 =

[

]

∑ x[k ,k ,n ]W ( 0

1

0

8

4k2 +2k1 +k0 )n0

(stage 1)

(4.26c)

(bit reversal)

(4.26d)

n0 = 0

[

S k2 , k1 , k0 = x 3 k0 , k1 , k2

]

In each of these summation, one of the ni is summed out of the expression, while at the same time a new ki is introduced. The notation is chosen to reflect this. For example, in stage 3, n0 is summed out, k2 is introduced as a new variable, and n0 is replaced by k2 in the result. The last operation, called bit reversal, is necessary to correctly locate the frequency samples X[k] in the memory. It is easy to show that if the samples are paired correctly, an in-place computation can be done by a sequence of butterfly operations. The term in-place means that each time a butterfly is to be computed, a pair of data samples is read from memory, and the new data pair produced by the butterfly calculation is written back into the memory locations where the original pair was stored, thereby overwriting the original data. An inplace algorithm is designed so that each data pair is needed for only one butterfly, and so the new results can be stored immediately on top of the old in order to minimize memory requirements. For example, in stage 3 the k = 6 and k = 7 samples should be paired, yielding a “butterfly” computation that requires one complex multiply, one complex add, and one subtract. x 3 (1, 1, 0) = x 2 (1, 1, 0) + W83 x 2 (1, 1, 1)

(4.27a)

x 3 (1, 1, 1) = x 2 (1, 1, 0) − W83 x 2 (1, 1, 1)

(4.27b)

Samples x2(6) and x2(7) are read from the memory, the butterfly is executed on the pair, and x3(6) and x3(7) are written back to the memory, overwriting the original values of x2(6) and x2(7). In general, there are N/2 butterflies per stage and log2N stages, so the total number of butterflies is [N/2]log2N. Because there is, at most, one complex multiplication per butterfly, the total number of multiplications is bounded by (N/2)log2N (some of the multiplies involve factors of unity and should not be counted). Figure 4.9 shows the signal flow graph of the D-I-T FFT for N = 8. This algorithm is referred to as an in-place FFT with normally ordered input samples and bit-reversed outputs. Minor variations that include bit-reversed inputs and normally ordered outputs, and non-in-place algorithms with normally ordered inputs and outputs are possible. Also, when N is not a power of 2, a mixed-radix algorithm can be used to reduce computation. The mixed-radix FFT is most efficient when N is highly composite, i.e., N = p1rip2r2 … pLrL, where the pri are small prime numbers and the ri are positive integers. It can be shown that the order of complexity of the mixed radix FFT is Order{N(r1(p1 – 1) + r2(p2 – 1) + … + rL(pL – 1)}. Because of the lack of uniformity of structure among stages, this algorithm has not received much attention for hardware implementation. However, the mixed-radix FFT is often used in software appli­ cations, especially for processing data recorded in laboratory experiments where it is not convenient to restrict the block lengths to be powers of 2. Many advanced FFT algorithms, such as higher-radix forms, the mixed-radix form, prime-factor algorithm, and the Winograd algorithm are described in Reference [9]. Algorithms specialized for real-valued data reduce the computational cost by a factor of two. A radix­ 2 D-I-T FFT program, written in C language, is listed in Table 4.6.

4.6 The Family Tree of Fourier Transforms It is now possible to illustrate the functional relationships among the various forms of CT and DT Fourier transforms that have been discussed in the previous sections. The family tree of CT Fourier transforms is shown in Fig. 4.10, where it is illustrated that the most general, and consequently the most powerful, Fourier transform is the classical complex Fourier transform (or equivalently, the bilateral Laplace transform). Note that the complex Fourier transform is identical to the bilateral Laplace transform, and

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X(0)

x(0) WN0

x(1)

−1

X(4)

0

WN

x(2)

WN0

x(3)

x(4)

x(5)

x(6)

x(7)

X(2)

−1 WN2 −1

−1

WN0

X(1)

−1 WN1

WN0

−1

−1 WN0

WN2 −1

WN0

X(6)

X(3)

−1 WN2

−1

X(5)

WN3 −1

−1

X(7)

FIGURE 4.9 Decimation-in-time FFT algorithm with normally ordered inputs and bit-reversed outputs.

it is at this level that the classical Laplace transform techniques and Fourier transform techniques become identical. Each special member of the CT Fourier family is obtained by impressing certain constraints on the general form, thereby producing special transforms that are simpler and more useful in practical problems where the constraints are met. The analogous family of DT Fourier techniques is presented in Fig. 4.11, where it is seen that the bilateral z-transform is analogous to the complex Fourier transform, the unilateral z-transform is anal­ ogous to the classical (one-sided) Laplace transform, the discrete-time Fourier transform is analogous to the classical Fourier (CT) transform, and the discrete Fourier transform is analogous to the classical (CT) Fourier series.

4.7 Walsh–Hadamard Transform The Walsh–Hadamard Transform (WHT) is a computationally attractive orthogonal transform that can be implemented in practical applications without multiplication, and with a computational complexity for addition that is on the same order of complexity as that of an FFT implementation. The tmk -th element of the WHT matrix TWHT is given by t mk =

1 N

p −1

∏ (−1) ( )

bl m bp−1−l ( k )

with m and k = 0, …, N -1

l=0

where bl(m) is the lth order bit in the binary representation of m, and N = 2p. Note that the WHT is defined only when N is a power of 2. The columns of TWHT form a set of orthogonal basis vectors whose elements are all 1s or –1s, so that the calculation of the matrix-vector product TWHT X can be accomplished with only additions and subtractions. It is well known that TWHT of dimension (N × N), for N a powerof-two integer, can be computed recursively according to

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Fourier Series, Fourier Transforms, and the DFT

TABLE 4.6

An In-Place D-I-T FFT Program in C Language

************************************************************************/

* fft: in-place radix-2 DIT DFT of a complex input */

* */

* input: */

* n: length of FFT: must be a power of two */

* m: n = 2**m */

* input/output: */

* x: float array of length n with real part of data */

* y: float array of length n with imag part of data */

************************************************************************/

fft(n,m,x,y)

int n.m.;

float x[].y[]:

{

int i,j,k,n1,n2;

float c,s,e,a,t1,t2;

j = 0; /* BIT-REVERSE */

n2 = n/2;

for (i=1; 1 < n - 1; i++) /* bit-reverse counter */

{

n1 = n2;

while (j >= n1)

{

j = j - n1;

n1 = n1/2;

}

j = j + n1;

if (i < j) /* swap data */

{

t1 = x[i]; x[i] = x[j]; x[j] = t1;

t1 = y[i]; y[i] = y[j]; y[j] = t1;

}

}

n1 = 0, n2 = 1; /* FFT */

for (i=0; i < m; i++) /* stage loop */

{

n1 = n2; n2 = n2 + n2;

e = -6.283185307179586/n2; —

a = 0.0;

for (j=0; j < n1; j++) /* flight loop */

{

c = cos(a); s = sin(a);

a = a + e;

for (k=j; k < n; k=k+n2) /* butterfly loop */

{

t1 = c*x[k+n1] - s*y[k+n1];

t2 = s*x[k+n1] + c*y[k+n1];

x[k+n1] = x[k] - t1;

y[k+n1] = y[k] - t2;

x[k] = x[k] + t1;

y[k] = y[k] + t2;

}

}

}

return;

}

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FIGURE 4.10 Relationships among CT Fourier concepts.

Tk 2 Tk =  Tk 2 

Tk 2  1  for K = 4, …, N, and T2 =  −Tk 2  1

1 . −1

This relationship provides a convenient way of quickly constructing the Walsh–Hadamard matrix for any power-of-two integer. Due to structural similarities between the DFT and the FFT matrices, the WHT transform can be implemented as a sliding window operator using a modified FFT algorithm operating on blocks of input data. The core of any FFT program is a butterfly calculation that is characterized by a pair of coupled equations that have the following form: jθ m k s X i+1 (l,m) = X i (l,m) + e ( l, , , ) X i (k, s ) jθ m k s X i+1 (l,m) = X i (l,m) − e ( l, , , ) X i (k, s )

If the exponential factor in the butterfly calculation is replaced by a “1”, so the “modified butterfly” calculation becomes X i+1 (l,m) = X i (l,m) + X i (k, s ) X i+1 (l,m) = X i (l,m) − X i (k, s ) the modified FFT program will in fact perform a WHT on the input vector. This property not only provides a quick and convenient way to implement the WHT, but it also clearly establishes that, in addition

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Fourier Series, Fourier Transforms, and the DFT

��������� �����������

����� ��

������ ���

������������� ������� ���������� ������

���������� �����������

������ �� ������ �

�������� ������� ��������� �����

������ �������� ���� �������� ����� ���� ������� �� ��� �����

FIGURE 4.11 Relationships among discrete-time Fourier concepts.

to the WHT requiring no multiplication, the number of additions required has an order of complexity of N · log2N, i.e., the same as that of the FFT. The Walsh–Hadamard transform is used in many signal processing applications that require signals to be decomposed in real time into a set of orthogonal components. A typical application in which the WHT has been used in this manner is in CDMA wireless communication systems. A CDMA system requires spreading of each user’s signal spectrum using a PN sequence. An IS-95A system uses two PN codes, referred to as the short PN code and the long PN code. In addition to the PN spreading codes, a set of length-64 mutually orthogonal codes, called the Walsh codes, are used for ensuring orthogonality between the signals for different users received from the same base station. The same Walsh codes are used for modulation in the reverse channel of an IS-95A system. The length N = 64 Walsh codes can be thought of as the orthogonal column vectors from a (64 × 64) Walsh–Hadamard matrix. The process of demodulation in the receiver can be interpreted as performing a WHT on the complex input signal containing all the modulated user’s signals so they can be separated for accurate detection.

4.8 Selected Applications of Fourier Methods The FFT in Spectral Analysis An FFT program is often used to perform spectral analysis on signals that are sampled and recorded as part of laboratory experiments, or in certain types of data acquisition systems. There are several issues to be addressed when spectral analysis is performed on (sampled) analog waveforms that are observed over a finite interval of time.

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TABLE 4.7

Common Window Functions

Name

Function

Peak Side-Lobe Amplitude (dB)

Main-Lobe Width

Minimum Stop-Band Attenuation (dB)

Rectangular

ω(n) = 1, 0 ≤ n ≤ N −1

–13

4π/N

–21

Bartlett

2n N , 0 ≤ n ≤ ( N − 1) 2 ω(n) =  2 − 2n N , ( N − 1) 2 ≤ n ≤ N − 1

–25

8π/N

–25

Hanning

ω(n) = (1 2) 1 − cos (2πn N ) ,

–31

8π/N

–44

Hamming

ω(n) = 0.54 − 0.46 cos(2πn N ),

–43

8π/N

–53

Blackman

ω(n) = 0.42 − 0.5cos(2πn N )

–57

12π/N

–74

[

]

0 ≤ n ≤ N −1

0 ≤ n ≤ N −1 + 0.08 cos(4πn N ), 0 ≤ n ≤ N − 1

Windowing The FFT treats the block of data as though it were one period of a periodic sequence. If the underlying waveform is not periodic, then harmonic distortion may occur because the periodic waveform created by the FFT may have sharp discontinuities at the boundaries of the blocks. This effect is minimized by removing the mean of the data (it can always be reinserted) and by windowing the data so the ends of the block are smoothly tapered to zero. A good rule of thumb is to taper 10% of the data on each end of the block using either a cosine taper or one of the other common windows shown in Table 4.7. An alternate interpretation of this phenomenon is that the finite length observation has already windowed the true waveform with a rectangular window that has large spectral sidelobes (see Table 4.7). Hence, applying an additional window results in a more desirable window that minimizes frequency-domain distortion. Zero-Padding An improved spectral analysis is achieved if the block length of the FFT is increased. This can be done by: (1) taking more samples within the observation interval, (2) increasing the length of the observation interval, or (3) augmenting the original data set with zeros. First, it must be understood that the finite observation interval results in a fundamental limit on the spectral resolution, even before the signals are sampled. The CT rectangular window has a (sin x)/x spectrum, which is convolved with the true spectrum of the analog signal. Therefore, the frequency resolution is limited by the width of the mainlobe in the (sin x)/x spectrum, which is inversely proportional to the length of the observation interval. Sampling causes a certain degree of aliasing, although this effect can be minimized by sampling at a high enough rate. Therefore, lengthening the observation interval increases the fundamental resolution limit, while taking more samples within the observation interval minimizes aliasing distortion and provides a better definition (more sample points) on the underlying spectrum. Padding the data with zeros and computing a longer FFT does give more frequency domain points (improved spectral resolution), but it does not improve the fundamental limit, nor does it alter the effects of aliasing error. The resolution limits are established by the observation interval and the sampling rate. No amount of zero padding can improve these basic limits. However, zero padding is a useful tool for providing more spectral definition, i.e., it enables one to get a better look at the (distorted) spectrum that results once the observation and sampling effects have occurred.

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UNDERLYING SPECTRUM

ω

ωk − 1 ωk ωk + 1 (A) FFT of a windowed sinusoid with frequency ωk = 2πk /N.

UNDERLYING SPECTRUM

ωk − 1 ωk

ωk + 1/2

ω

ωk + 1

(B) Leakage for a nonharmonic sinusoidal component.

FIGURE 4.12 Illustration of leakage and the picket-fence effect.

Leakage and the Picket-Fence Effect An FFT with block length N can accurately resolve only frequencies ωk = (2π/N)k, k = 0, …, N – 1 that are integer multiples of the fundamental ω1 = (2π/N). An analog waveform that is sampled and subjected to spectral analysis may have frequency components between the harmonics. For example, a component at frequency ω k+1/2 = (2π/N)(k+1/2) will appear scattered throughout the spectrum. The effect is illus­ trated in Fig. 4.12 for a sinusoid that is observed through a rectangular window and then sampled at N points. The “picket-fence effect” means that not all frequencies can be seen by the FFT. Harmonic components are seen accurately, but other components “slip through the picket fence” while their energy is “leaked” into the harmonics. These effects produce artifacts in the spectral domain that must be carefully monitored to assure that an accurate spectrum is obtained from FFT processing.

FIR Digital Filter Design A common method for designing finite impulse response (FIR) digital filters is by use of windowing and FFT analysis. In general, window designs can be carried out with the aid of a hand calculator and a table of well-known window functions. Let h[n] be the impulse response that corresponds to some desired frequency response, H(e jω). If H(e jω) has sharp discontinuities, such as the lowpass example shown in Fig. 4.13, then h[n] will represent an infinite impulse response (IIR) function. The objective is to time­ H(e jw ) TRUNCATED FILTER

0

ωb

ω

FIGURE 4.13 Gibbs effect in a lowpass filter caused by truncating the impulse response.

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H^(e jw )

0

π

ω0

ω

(2π − ω0)

2π

FIGURE 4.14 Design of a simple bandpass FIR filter by windowing.

limit h[n] in such a way as to not distort H(e jω) any more than necessary. If h[n] is simply truncated, a ripple (Gibbs phenomenon) occurs around the discontinuities in the spectrum, resulting in a distorted filter, as illustrated in Fig. 4.13. Suppose that w[n] is a window function that time-limits h[n] to create an FIR approximation, h′[n]; i.e., h′[n] = w[n]h[n]. Then if W(e jω) is the DTFT of w[n], h′[n] will have a Fourier transform given by H′(e jω) = W(e jω)∗H(e jω), where ∗ denotes convolution. From this, it can be seen that the ripples in H′(e jω) result from the sidelobes of W(e jω). Ideally, W(e jω) should be similar to an impulse so that H′(e jω) is approximately equal to H(e jω). Special Case. Let h[n] = cos nω0, for all n. Then h[n] = w[n]cos nω0, and

( )

(

)

(

)

j ω +ω j ω −ω H ′ e jω = (1 2)W e ( 0 ) + (1 2)W e ( 0 ) .

(4.28)

as illustrated in Fig. 4.14. For this simple class, the center frequency of the passband is controlled by ω0, and both the shape of the passband and the sidelobe structure are strictly determined by the choice of the window. While this simple class of FIRs does not allow for very flexible designs, it is a simple technique for determining quite useful lowpass, bandpass, and highpass FIRs. General Case. Specify an ideal frequency response, H(e jω), and choose samples at selected values of ω. Use a long inverse FFT of length N′ to find h′[n], an approximation to h[n], where if N is the desired length of the final filter, then N′  N. Then use a carefully selected window to truncate h′[n] to obtain h[n] by letting h[n] = w[n]h′[n]. Finally, use an FFT of length N′ to find H′(e jω). If H′(e jω) is a satisfactory approximation to H(e jω), the design is finished. If not, choose a new H(e jω), or a new w[n] and repeat. Throughout the design procedure it is important to choose N′ = kN, with k an integer that is typically in the range [4, …, 10]. Since this design technique is a trial-and-error procedure, the quality of the result depends to some degree on the skill and experience of the designer. Table 4.7 lists several wellknown window functions that are often useful for this type of FIR filter design procedure.

Transform Domain Adaptive Filtering A transform domain adaptive filter (TDAF) is a generalization of the well-known LMS adaptive filter in which the input signal is passed through a linear transformation in order to decompose it into a set of orthogonal components and to optimize the adaptive step size for each component, thereby maximizing the learning rate of the adaptive filter [11]. The LMS algorithm is an approximation to the steepest descent optimization strategy. For a length N FIR filter with the input expressed as a column vector x(n) = [x(n), x(n – 1), …, x(n-N + 1)]T, the filter output y(n) is expressed as y (n) = w T (n)x (n) , where w(n) = [w0(n), w1(n), …, wN-1(n)]T is the time varying vector of filter coefficients (tap weights), and the superscript “T” denotes vector transpose. The output error is formed as the difference between the filter output and a training signal d(n), i.e., e(n) = d(n) – y(n). Strategies for obtaining an appropriate © 2003 by CRC Press LLC

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d(n) vary from one application to another. In many cases the availability of a suitable training signal determines whether an adaptive filtering solution will be successful in a particular application. The ideal cost function is defined by the mean squared error (MSE) criterion, E{e(n)2}. The LMS algorithm is derived by approximating the ideal cost function by the instantaneous squared error, resulting in JLMS(n) = e(n)2. While the LMS seems to make a rather crude approximation at the very beginning, the approxi­ mation results in an unbiased estimator. In many applications the LMS algorithm is quite robust and is able to converge rapidly to a small neighborhood of the Wiener solution. When a steepest descent optimization strategy is combined with a gradient approximation formed using the LMS cost function JLMS(n) = e(n)2, the conventional LMS adaptive algorithm results: w (n + 1) = w (n) + µe(n) x (n) , e(n) = d(n) − y (n) ,

(4.29)

y (n) = x (n) w (n) T

The convergence behavior of the LMS algorithm, as applied to a direct form FIR filter structure, is controlled by the autocorrelation matrix Rx of the input process, where

[

]

R X ≡ E x ∗ (n)x T (n) .

(4.30)

The autocorrelation matrix Rx is usually positive definite, which is one of the conditions necessary to guarantee convergence to the Wiener solution. Another necessary condition for convergence is 0 < µ < 1/λmax, where λmax is the largest eigenvalue of Rx. It is well established that the convergence of this algorithm is directly related to the eigenvalue spread of Rx . The eigenvalue spread is measured by the condition number of Rx , defined as κ = λmax/λmin, where λmin is the minimum eigenvalue of Rx . Ideal conditioning occurs when κ =1 (white noise); as this ratio increases, slower convergence results. The eigenvalue spread (condition number) depends on the spectral distribution of the input signal, and is related to the maximum and minimum values of the input power spectrum. From this line of reasoning it becomes clear that white noise is the ideal input signal for rapidly training an LMS adaptive filter. The adaptive process is slower and requires more computation for input signals that are colored. The TDAF structure is shown in Fig. 4.15. The input x(n) and the desired signal d(n) are assumed to be zero mean and jointly stationary. The input to the filter is a vector of N current and past input samples, defined in the previous section and denoted as x(n). This vector is processed by a unitary transform, such as the DFT. Once the filter order N is fixed, the transform is simply an N × N matrix T, which is in general complex, with orthonormal rows. The transformed outputs form a vector v(n) which is given by

[

]

z(n) = v 0 (n), v1 (n), …, v N −1 (n)

x(n) . . . x(n-1) . . . x(n-N+1)

z0

NxN Linear Transform

z1

T

= Tx(n) .

W0 d(n) W1

Σ zN-1

y(n) -

WN-1 e(n)

FIGURE 4.15 The transform domain adaptive filter structure.

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With an adaptive tap vector defined as w(n) = [w0(n), w1(n), …, wN-1(n)]T, the filter output is given by y (n) = w T (n) v (n) = WT (n)Tx(n) .

(4.31)

The instantaneous output error is then formed and used to update the adaptive filter taps using a modified form of the LMS algorithm [11]: W(n +1) = W(n) + µe(n)Λ−2 v ∗ (n)

[

Λ2 ≡ diag σ12 , σ 22 , …, σ N2

]

(4.32)

2 σ i2 = E  v i (n)  . 

 

where σ i2 = E  v i (n)  .   The power estimates σi2 can be developed online by computing an exponentially weighted average of past samples according to 2

σ i2 (n) = ασ i2 (n − 1) + v i (n) , 2

0 < α < 1.

(4.33)

If σi2 becomes too small due to an insufficient amount of energy in the ith channel, the update mechanism becomes ill-conditioned due to a very large effective step size. In some cases, the process will become unstable and register overflow will cause the adaptation to catastrophically fail. So the algorithm given by (4.32) should have the update mechanism disabled for the ith orthogonal channel if σi2 falls below a critical threshold. The motivation for using the TDAF adaptive system instead of a simpler LMS based system is to achieve rapid convergence of the filter coefficients when the input signal is not white, while maintaining a reasonably low computational complexity requirement. The optimal decorrelating transform is com­ posed of the orthonormal eigenvectors of the input autocorrelation matrix, and is known in the literature as the Karhunen-Loe’ve transform (KLT). The KLT is signal dependent and usually cannot be easily computed in real time. Throughout the literature the discrete Fourier transform (DFT), the discrete cosine transform (DCT), and the Walsh–Hadamard transform (WHT) have received considerable atten­ tion as possible candidates for use in the TDAF. Figure 4.16 shows learning characteristics for computer generated TDAF examples using six different orthogonal transforms to decorrelate the input signal. The examples presented are for system identification experiments, where the desired signal was derived by passing the input through an 8-tap FIR filter, which serves as the model system to be identified. Computer generated white pseudo-noise, uncorrelated with the input signal, was added to the output of the model system, creating a –100-dB noise floor. The filter inputs were generated by filtering white pseudo-noise with a 32-tap linear phase FIR noise-coloring filter to produce an input autocorrelation eigenvalue ratio of 681. Experiments were then performed using the DFT, the DCT, the WHT, discrete Hartley transform (DHT), and a specially designed computationally efficient “power-of-2” (PO2) transform, as listed in Fig. 4.16. The eigenvalue ratios that result from transform processing with each of these transforms is shown in Fig. 4.16 All of the transforms used in this experiment are able to reduce the input condition number and greatly improve convergence rates, although some transforms are seen to be more effective than others for the coloring chosen for these examples.

4.9 Summary Many different Fourier transform concepts have been presented for both continuous-time and discretetime signals and systems. Emphasis was placed on illustrating how these various forms of the Fourier transform relate to one another, and how they are all derived from more general complex transforms, © 2003 by CRC Press LLC

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PO2 DFT DCT WHT DHT I

SQUARED ERROR, DB

0

−50

−100

−150 0

2500

Transform

5000 ITERATION

7500

10000

Effective input correlation matrix eigenvalue ratio

Identity (I)

681

Discrete Fourier Transform (DFT)

210

Discrete Cosine Transform (DCT)

200

Walsh Hadamard Transform (WHT)

216

Discrete Hartley Transform (DHT)

218

Power-of-2 Transform (PO2)

128

FIGURE 4.16 Comparison of (smoothed) learning curves for five different transforms operating on a colored noise input signal with condition number 681.

the complex Fourier (or bilateral Laplace) transform for continuous-time, and the bilateral z-transform for discrete time. It was demonstrated that many of these transforms have similar properties, which are inherited from their parent forms, and that there is a parallel hierarchy among Fourier transform concepts in the “continuous-time world” and the “discrete-time world.” Both continuous-time and discrete-time sampling models were introduced as a means of representing sampled signals in these two different “worlds,” and it was demonstrated that the models are equivalent by virtue of having the same Fourier spectra when transformed into the Fourier domain with the appropriate Fourier transform. It was demonstrated how Fourier analysis properly characterizes the relationship between the spectra of a continuous-time signal and its discrete-time counterpart obtained by sampling. The classical reconstruc­ tion formula was obtained as an outgrowth of this analysis. Finally, the discrete Fourier transform, the backbone for much of modern digital signal processing, was obtained from more classical forms of the Fourier transform by simultaneously discretizing the time and frequency domains. The DFT, together with the remarkable computational efficiency provided by the FFT algorithm, has contributed to the resounding success that engineers and scientists have had in applying digital signal processing to many practical scientific problems.

References [1] M. E. VanValkenburg, Network Analysis, 3rd ed., Englewood Cliffs, NJ: Prentice Hall, 1974. [2] A. V. Oppenheim, A. S. Willsky, and I. T. Young, Signals and Systems, Englewood Cliffs, NJ: Prentice Hall, 1983. [3] R. N. Bracewell, The Fourier Transform, 2nd ed., New York: McGraw-Hill, 1986.

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[4] A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing Englewood Cliffs, NJ: Prentice Hall, 1989. [5] W. K. Jenkins and M. D. Desai, “The discrete-frequency Fourier transform,” IEEE Trans. Circuits Syst., vol. CAS-33, no. 7, pp. 732–734, July 1986. [6] A. V. Oppenheim and R. W. Schafer, Digital Signal Processing, Englewood Cliffs, NJ: Prentice Hall, 1975. [7] R. E. Blahut, Fast Algorithms for Digital Signal Processing, Reading, MA: Addison-Wesley, 1985. [8] J. R. Deller, Jr., “Tom, Dick, and Mary discover the DFT,” IEEE Signal Processing Mag., vol. 11, no. 2, pp. 36–3550, April 1994. [9] C. S. Burrus and T. W. Parks, DFT/FFT and Convolution Algorithms, New York: John Wiley & Sons, 1985. [10] E. O. Brigham, The Fast Fourier Transform, Englewood Cliffs, NJ: Prentice Hall, 1974. [11] W. K. Jenkins et al., Advanced Concepts in Adaptive Signal Processing, Boston MA: Kluwer Academic Publishers, 1996.

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5 z-Transform

5.1 5.2 5.3

Introduction Definition of the z-Transform Inverse z-Transform Contour Integration • Partial Fraction Expansion • Other Methods for Obtaining the Inverse z-Transform

5.4

Properties of the z-Transform Region of Convergence • Properties of the Transform • Convolution in z-Domain

5.5 5.6

Role of the z-Transform in Linear Time-Invariant Systems Variations on the z-Transform Multidimensional z-Transform • Modified z-Transform • Chirp z-Transform Algorithm

Jelena Kovacevi ˇ c´ Bell Labs, Lucent Technologies

5.7

Concluding Remarks Acknowledgment

5.1 Introduction When analyzing linear systems, one of the problems we often encounter is that of solving linear, constantcoefficient differential equations. A tool used for solving such equations is the Laplace transform. At the same time, to aid the analysis of linear systems, we extensively use Fourier-domain methods. With the advent of digital computers, it has become increasingly necessary to deal with discrete-time signals, or, sequences. These signals can be either obtained by sampling a continuous-time signal, or they could be inherently discrete. To analyze linear discrete-time systems, one needs a discrete-time counterpart of the Laplace transform (LT). Such a counterpart is found in the z transform, which similarly to the LT, can be used to solve linear constant-coefficient difference equations. In other words, instead of solving these equations directly, we transform them into a set of algebraic equations first, and then solve in this transformed domain. On the other hand, the z-transform can be seen as a generalization of the discretetime Fourier transform (FT) +∞

( ) ∑ x[n]e

− jωn

X e jω =

(5.1)

n = −∞

This expression does not always converge, and thus, it is useful to have a representation which will exist for these nonconvergent instances. Furthermore, the use of the z-transform offers considerable notational simplifications. It also allows us to use the extensive body of work on complex variables to aid in analyzing discrete-time systems. The z-transform, as pointed out by Jury in his classical text [3], is not new. It can be traced back to the early 18th century and the times of DeMoivre, who introduced the notion of the generating function, extensively used in probability theory

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Γ( z ) =

+∞

∑ p[n]z

n

(5.2)

n = −∞

where p[n] is the probability that the discrete random variable n will take a value n [8]. By comparing (5.2) and (5.3) below, we can see that the generating function Γ(1/z) is the z-transform of the sequence p[n] = p{n = n}. After these initial efforts, and due to the fast development of digital computers, a renewed interest in the z-transform occurred in the early 1950s, and z-transform has been used for analyzing discrete-time systems ever since. This section is intended as a brief introduction to the theory and application of the z-transform. For a rigorous mathematical treatment of the transform itself, the reader is referred to the book by one of the pioneers in the development of analysis of sampled data systems, Jury [3], and the references therein. For a more succinct account of the z-transform, its properties and use in discrete-time systems, consult, for example, [7]. A few other texts which contain parts on the z-transform include [1, 2, 5, 6, 10].

5.2 Definition of the z-Transform Suppose we are given a discrete-time sequence x[n], either inherently discrete time, or obtained by sampling a continuous-time signal xc(t), so that x[n] = xc(nT), n ∈ Z, where T is the sampling period. Then the two-sided z-transform of x[n] is defined as X (z ) =

+∞

∑ x[n]z

–n

(5.3)

n = –∞

Here, z is a complex variable, and depending on its magnitude and the sequence x[n], the above sum may or may not converge. The region in the z-plane where the sum does converge is called the region of convergence (ROC), and is discussed in more detail later. Observe that in (5.3), n ranges from –∞ to +∞. That is why the z-transform defined in this way is called two-sided. One could define a one-sided z-transform, where n would range from 0 to +∞. Obviously, the two definitions are equivalent only if the signal itself is one-sided, that is, if x[n] = 0, for n < 0. The advantage of using the one-sided z-transform is that it is useful in solving linear constantcoefficient difference equations with nonzero initial conditions and in the study of sampled-data feedback systems, discussed later. However, from now on, we deal mostly with the two-sided z-transform (see also Chapter 3 where the one-sided LT is used). A power series given in (5.3) is a Laurent series, and thus for it to converge uniformly, it has to be absolutely summable, that is, the following must hold: n = +∞

∑ x[n]

z

–n

1. As a consequence, if the ROC includes the unit circle, then the discrete-time FT of a given sequence will exist, otherwise it will not. The unit circle captures the periodicity of the discrete-time FT. If we start evaluating the z-transform on the unit circle at the point (Re z, Im z) = (1, 0) corresponding to ω = 0, going through (Re z, Im z) = (0, j), (Re z, Im z) = (–1, 0) which corresponds to ω = π, and (Re z, Im z) = (0, –j), back to (Re z, Im z) = (1, 0) corresponding to ω = 2π, we have evaluated one period of the FT and have returned to the same point. Thus, we are effectively warping the linear frequency axis into the unit circle (see Fig. 5.2). We also mentioned that the z-transform is the discrete-time counterpart of the LT. Consider the function x cs (t ) =

+∞

∑ x (nT )δ(t – nT )

(5.7)

c

n= – ∞

or, the sampled version of the original continuous time function xc (t). Here, T is the sampling period, and δ (t) is the Dirac function. Taking the LT of xcs(t), we obtain X cs (s ) =

+∞

∑ x (nT )e

–nTs

(5.8)

c

n= – ∞

If we now replace e sT by z, we obtain the z-transform. Now, observe that Xcs (s) in (5.8) is periodic, because 2π   X cs  s + j  =  T

+∞

∑ x (nT )e c

–nT ( s+ j(2π) T )

(5.9)

+∞

=

,

n= – ∞

∑ x (nT )e c

–nTs – j 2πn

e

= X cs (s )

n= – ∞

This means that Xcs(s) is periodic along constant lines σ = σconst (parallel to the jω-axis). This further means that any line parallel to the jω-axis maps into a circle in the z-plane. It is easy to see that the jω­ axis itself would map into the unit circle, while the left (or right) half-planes would map into the inside (or outside) of the unit circle, respectively.

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Finally, let us say a few words about a very important class of signals, those whose z-transform is a rational function of z. They arise from systems that can be represented by linear constant-coefficient difference equations and are the signals with which we deal mostly in practice. If we represent such signals by X (z ) =

N (z ) D( z )

(5.10)

then the zeroes of the numerator N(z) are called zeroes of X(z), while the zeroes of the denominator D(z) are called poles of X(z) (more precisely, a pole zp will be a point at which limz→zp X(z) does not exist). How the poles can determine the region of convergence is the subject of a discussion later in the chapter.

5.3 Inverse z-Transform We have seen that specifying the ROC when taking the z-transform of a sequence is an integral part of the process. For example, consider the following sequences: x[n] = u[n] and y[n] = –u[–n–1], where u[n] is the unit-step function. Taking their z-transforms, we obtain X (z ) =

Y (z ) =

1 , 1 – z –1

1 , 1 – z –1

(5.11)

z >1

z 1. (c) Sequence y[n] = –u[–n – 1] and (d) its ROC z < 1.

The integral in parentheses on the right side of (5.14) can be evaluated using Cauchy’s integral formula, which states that if the contour of integration C contains the origin, and integration is performed counterclockwise, then 1 2πj

k = −1,

1,  z kdz =  C 0,

∫

(5.15)

otherwise

Substituting (5.15) in (5.14), we see that the integral is nonzero only for n = k, and thus (5.14) can be rewritten as 1 2πj

∫ X ( z )z C

dz = x[k ]

k−1

(5.16)

Equation (5.16) is the inversion formula for the z-transform. To evaluate it for general functions can be quite difficult. However, in cases in which X(z) is a rational function of z, we can make use of Cauchy’s formula. It tells us that 1 2πj

( )

F z , F (z )  p dz =  C z − zp  0,

∫

z p inside C,

(5.17)

otherwise

where C is a simple closed path and F ′(z), the derivative of F(z), exists on and inside C. If we have a pole of multiplicity r enclosed in the contour C, and F(z) and its (r + 1) derivatives exist in and on C, then

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1 2πj

F (z )

∫ (z − z ) C

r

p

 1 d r −1 F (z ) ,  dz =  (r − 1)! dz r −1 z=z p  0, 

z p inside C,

(5.18)

otherwise

Equations (5.17) and (5.18) are called residues. Use (5.17) and (5.18), and if we express X ( z )z k−1 =

F (z )

(5.19)

(z − z )

r

p

where F(z) has no poles at z = zp , then Cauchy’s residue theorem says that x[k ] =

1 2πj

∫ X ( z )z

∑R

dz =

k−1

(5.20)

i

C

i

where Ri are residues of X(z)z k–1 at the poles inside the contour C. The poles outside the contour do not contribute to the sum. If no poles are inside the contour of integration for a certain k, then x[k] is zero for that k. Do not ignore the fact that the contour of integration C must lie within the ROC. In some instances, it may be quite cumbersome to evaluate (5.20), for example, when we have a multiple-order pole at z = 0, whose order depends on k. In that case we can rewrite (5.20) as x[k ] =

∑ R′ i

i

where R′i is the residue of X(1/z)z –k–1 at the poles inside the contour C′, and C′ is a circle of radius 1/s if C is a circle of radius s. For more details, see [7].

Partial Fraction Expansion Another method of obtaining the inverse z-transform is by using partial fraction expansion. Note, however, that the partial fraction expansion method can be applied only to rational functions. Thus, suppose that X(z) can be represented as in (5.10). We can then rewrite it as

∏ (1 − n z ) ∏ (1 − d z ) N

N X (z ) = 0 ⋅ D0

−1

i

i =1 D

(5.21)

−1

i

i=1

where ni are nontrivial zeroes of N(z) and di are zeroes of D(z). The partial fraction expansion of X(z) can be written as X (z ) =

N −D

∑ i=0

Ds

Ai z −i +

∑( i=1

Dm

pi

) ∑∑ (1 − d z )

Bi + 1 − di z −1

i=1 m=1

Cmi

−1

m

(5.22)

i

Here, if N ≥ D, Ai can be obtained by long division of the numerator by the denominator; otherwise, that first sum in (5.22) disappears. In the second sum Ds denotes the number of single poles di of X(z), and the coefficients Bi can be obtained as

(

)

Bi = 1 − di z −1 X ( z ) z = di

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(5.23)

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The third sum (double sum) represents the part with multiple poles. Dm is the number of multiple poles di, and pi are their respective multiplicities. The coefficients Cmi can be obtained as Cmi =

d pi

1

( p − m)!(−d ) i

i

pi

−m

dz

−m

pi − m

( )

(1 − d z ) pi X z −1  i  

z = di −1

(5.24)

Once we have the expression (5.22), we can recognize each term as the z-transform of a known sequence. For example, Bi/(1 – di z–1) will be the z-transform of either Bidinu[n], or –Bi dinu[–n–1], depending on whether z > di, or z < di.

Other Methods for Obtaining the Inverse z-Transform Although the two methods presented previously will work in most cases, sometimes it can be more convenient to use simpler techniques. One of these is the inspection method [7]. It consists of learning to recognize some often-used z-transform pairs. For example, if we are given 3/(1 – z –1) with the ROC z < 1, from (5.21) we can recognize it as the z-transform of – 3u[–n – 1]. In this process the tables of z-transform pairs are an invaluable tool. An extensive list of z-transform pairs can be found in [3]. Another technique can be used if we are given a z-transform in the form of a power series expansion: X ( z ) = … + x[−1]z + x[0] + x[1]z −1 + … Then, we can identify each term with the appropriate power of z. For example, the coefficient with z –k will be x[k].

5.4 Properties of the z-Transform Although we can always obtain a z-transform of a sequence by directly applying its definition as given in (5.3), it is useful to have a list of properties at hand to help calculate a particular z-transform or inverse z-transform more easily. We divide these properties into two categories: properties of the ROC, and properties of the z-transform itself. In what follows Rx will denote the ROC of the signal x[n], while Rx – and Rx + will denote its lower/upper bounds, respectively [as given in (5.5)].

Region of Convergence The ROC is an integral part of the z-transform of a sequence. Thus, this section goes into more detail on some of the points touched upon earlier. These properties and the order in which they are presented follow those in [7]; therefore, for more details, see [7]. First, we said that the ROC is an annular region in the z-plane, i.e., 0 ≤ R– < z < R+ ≤ ∞. This follows from the fact that if the z-transform converges for z = z1, it will converge for all z such that z = z1, that is, for all z on the circle z = z1. Then, if we put z = 1 in (5.3), we obtain (5.6), or the discrete-time FT. Therefore, it is obvious that the FT of x[n] converges iff the z-transform of x[n] converges for z = 1, that is, iff the ROC of the z-transform contains the unit circle. Another useful property is that the ROC cannot contain any poles. This stems from the fact that if it did, the z-transform at the pole would be infinite and would not converge. Consider now what happens if the sequence is of finite duration — it is zero except in a finite interval – ∞ < N1 ≤ n ≤ N2 < + ∞. If all the values are finite, then the sequence is clearly absolutely summable and the z-transform will converge everywhere, except possibly at points z = 0 or z = ∞. Using the same type of arguments one can conclude that if the sequence is right-sided (it is zero for n < N1 < + ∞), then

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the ROC will be the annular region outside of the finite pole of X(z) of the largest magnitude. Similarly, if the sequence is left-sided (it is zero for n > N2 > – ∞), then the ROC will be the annular region inside the finite pole of X(z) of the smallest magnitude. As a result, if a sequence is neither left- nor right-sided, the ROC will be an annular region bounded on the interior and the exterior by a pole.

Properties of the Transform The sequences x[n], y[n], … will have associated z-transforms X(z), Y(z), …, with ROCs Rx , Ry , …, in which each ROC will have its associated lower and upper bounds, as given in (5.5). Linearity ax[n] + by[n] ↔ aX ( z ) + bY ( z )

ROC ⊃ Rx ∩ Ry

(5.25)

To prove this, apply the definition given in (5.5). Note that the resulting ROC is at least as large as the intersection of the two starting ROCs. For example, if both X(z) and Y(z) are rational functions of z, and by adding aX(z) to bY(z) we introduce a zero that cancels one of the poles, the resulting ROC is larger than the intersection. If, on the other hand, no pole/zero cancellation exists, the resulting ROC is exactly the intersection. Shift in Time x[n − i ] ↔ z −i X ( z )

ROC = Rx

(5.26)

The proof is straightforward and follows by the change of variables k = n – i in (5.5). Note that the resulting ROC could gain or lose a few poles at z = 0 or z = ∞. Time Reversal  1 x[−n] ↔ X    z

1 1 0, especially in circuit analysis. Next, consider a band-limited signal x(t) with FT X(ω) as demonstrated in Fig. 6.2. If we sample the signal at the Nyquist rate 2β rad/s (i.e., sampling period T = π/β), then multiple copies of the FT are generated [2], and we can recover x(t) from the samples by use of an ideal low-pass filter F(ω) (Fig. 6.3). The impulse response of the filter is the sinc function f (t) = sin βt/βt so that the reconstruction formula is x (t ) =

∞

∑

n=−∞

x (nT ) f (t − nT ) =

∞

∑ x(nT )

n=−∞

sin β(t − nT ) , β(t − nT )

T=π β

(6.3)

Comparing to (6.2) we see that the transform domain coefficients αn can be regarded as the samples x(nT), whereas the functions gn(t) are the shifted sinc functions. If a signal is time-limited or band-limited, we can express it as a countable linear combination of a set of fundamental functions (called basis functions, in fact an orthonormal basis; see below). If the signal is more arbitrary, i.e., not limited in time or bandwidth, can we still obtain such a countable linear 2 combination? Suppose we restrict x(t) to be a finite energy signal (i.e., x(t ) dt < ∞; also called L2 signals, see below). Then this is possible. In fact, we can find an unusual kind of basis called the wavelet basis, fundamentally different from the Fourier basis. Representation of x(t) using this basis has, in some applications, some advantages over the Fourier representation or the short-time (windowed) Fourier

∫

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representation. Wavelet bases also exist for many other classes of signals, but this discussion is limited to the L2 class of signals. The most common kind of wavelet representation takes the form x (t ) =

∞

∞

∑∑ c

kn

2k 2 ψ (2k t − n) 14 4244 3

(6.4)

ψ kn (t )

k=−∞ n=−∞

The functions ψ kn (t ) are typically (but not necessarily) linearly independent and form a basis for finite energy signals. The basis is very special in the sense that all the functions ψ kn (t ) are derived from a single function ψ(t) called the wavelet, by two operations: dilation (t → 2k t) and time shift (t → t − 2−k n). The advantage of such a basis is that it allows us to capture the details of a signal at various scales, while providing time-localization information for these “scales”. Examples in future sections clarify this idea. Why Worry about Signal Representations? A common feature of all the previous discussions is that we have taken a signal x(t) and found an equivalent representation in terms of the transform domain quantity {αn} in (6.2), or {ckn} in (6.4). If our only aim is to compute αn from x(t) and then recompute x(t) from αn , that would be a futile exercise. The motivation in practice is that the transform domain quantities are better suited in some sense. For example, in audio coding, decomposition of a signal into frequency components is motivated by the fact that the human ear perceives higher frequencies with less frequency resolution. We can use this infor­ mation. We can also code the high-frequency components with relatively less precision, thereby enabling data compression. In this way, we can take into account perceptual information during compression. Also, we can account for the fact that the error allowed by the human ear (due to quantization of frequency components) depends on the frequency masking property of the ear, and perform optimum-bit allocation for a given bit rate. Other applications of signal representations using wavelets include numerical analysis, solution of differential equations, and many others [5, 15, 16]. The main point, in any case, is that we typically perform certain manipulations with the transform domain coefficients αn [or ckn in (6.4)] before we recombine them to form an approximation of x(t). Therefore, we really only have xˆ (t ) =

∑ αˆ g (t ) n n

(6.5)

n

where {αˆ n} approximates {αn}. This discussion gives rise to many questions: how best to choose the basis functions gn(t) for a given application? How to choose the compressed signal {αˆ n} so that for a given data rate the reconstruction error is minimized? What, indeed, is the best way to define the reconstruction error? These questions are deep and complicated and will take us too far afield. Our goal is to point out the basic advantages (sometimes) offered by the wavelet transform over other kinds of transforms (e.g., the FT).

Ideal Bandpass Wavelet Consider a bandpass signal x(t) with FT as shown in Fig. 6.4. Such signals arise in communication applications. The bandedges of the signal are ω1 and ω2 (and –ω1 and –ω2 on the negative side, which is natural if x(t) is real). Viewed as a low-pass signal, the total bandwidth (counting negative frequencies also) is 2ω2, but viewed as a bandpass signal, the total bandwidth is only 2β where β = ω2 – ω1. Does it mean that we can sample it at the rate 2β rad/s (which is the Nyquist rate for the low-pass case)? In the low-pass case, sampling at Nyquist rate was enough to ensure that the copies of the spectrum created by the sampling did not overlap (Fig. 6.3). In the bandpass case, we have two sets of such copies; one created by the positive half of the frequency ω1 ≤ ω ≤ ω2 and the other by the negative half –ω2 ≤ ω ≤ –ω1. This makes the problem somewhat more complicated. It can be shown that, for sampling at © 2003 by CRC Press LLC

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X(ω)

−ω2

−ω1

β

ω1

0

ω2

ω

FIGURE 6.4 Fourier transform of a bandpass signal. β

F(ω) π/β −ω2

−ω1

ω1

0

ω

ω2

FIGURE 6.5 Bandpass filter to be used in the reconstruction of the bandpass signal from its samples. A bandpass subband X(ω)

lowpass subband

− ω3 − ω2

− ω1

0

ω1

ω

ω2 ω3

FIGURE 6.6 Splitting a signal into frequency subbands.

the rate 2β, no overlap of images exists iff one of the edges, ω1 or ω2, is a multiple of 2β. This is called the bandpass sampling theorem. The reconstruction of x(t) from the samples proceeds exactly as in the low-pass case, except that the reconstruction filter F(ω) is now a bandpass filter (Fig. 6.5), occupying precisely the signal bandwidth. The first part of the expression (6.3), therefore, is still valid, i.e., x(t) = Σn x(nT) f (t – nT), where T = π/β again, but the sinc function is replaced with the bandpass impulse response f (t). Given a signal x(t), imagine now that we have split its frequency axis into subbands in some manner (Fig. 6.6). Letting yk (t) denote the kth subband signal, we can write x(t) = Σk yk(t). This can be visualized as passing x(t) through a bank of filters {Hk (ω)} [Fig. 6.7(a)], with responses as in Fig. 6.7(b). Note that each subband region is symmetric with respect to zero frequency, and therefore supports positive as well as negative frequencies. If the subband region ωk ≤ ω < ωk+1 satisfies the bandpass sampling condition, then the bandpass signal yk(t) can be expressed as a linear combination of its samples as before. Thus, x(t) = Σk yk(t) = Σ k Σn yk (nTk ) fk (t – nTk ), where Tk = π/βk. Here, fk (t) is the impulse response of the reconstruction filter (or synthesis filter) Fk (ω) shown in Fig. 6.7(c). Fig. 6.7 (a) also illustrates this reconstruction schematic. Figure 6.8 shows the set of synthesis filters {Fk (ω)} for two examples of frequency splitting arrangement, namely uniform splitting and nonuniform (octave) splitting. We will see later that the uniform splitting arrangement gives an example of the STFT representation (Sections 6.3 and 6.9). In this section we are interested in octave splitting. The bandedges of the filters here are ωk = 2kπ (k = …–1, 0, 1, 2,…). The bandedges are such that yk (t) is a signal satisfying the bandpass sampling theorem. It has βk = 2k π, according to the notation of Fig. 6.7. It can be sampled at period Tk = π/βk = 2–k without aliasing, and we can reconstruct it from samples as y k (t ) =

∞

∑ y (2 n) f (t − 2 n) −k

k

n=−∞

© 2003 by CRC Press LLC

−k

k

(6.6)

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analysis filters

synthesis filters Hk−1(ω)

x(t) Hk(ω)

yk−1(t)

yk(t)

sampler

Fk−1(ω)

sampler

Fk(ω) (a)

Hk+1(ω)

yk+1(t)

sampler

Fk+1(ω)

Subband decomposition

Reconstruction

βk

Hk(ω) kth analysis filter −ωk+1

1 −ωk

ωk

0

ωk+1

−ωk

(b)

βk

Fk(ω) π/βk

kth synthesis filter −ωk+1

ω

(c) ωk

0

ω

ωk+1

FIGURE 6.7 (a) Splitting a signal into subband signals, sampling, and then recombining; (b) response of the kth analysis filter; and (c) response of kth synthesis filter.

1 (a)

F3 F2 F1 F0 F0 F1 F2 F3 −π

0

π

F−1

2

F0

F1

1 −π

0

ω

2π 3π

π

(b) 2π

4π

8π

ω

FIGURE 6.8 Two possible schemes to decompose a signal into frequency bands: (a) uniform splitting, and (b) octave-band splitting. The responses shown are those of synthesis filters.

As k increases, the bandwidths of the filters increase so the sample spacing Tk = 2–k becomes finer. Because x(t) = Σk yk (t) we see that x(t) can be expressed as x (t ) =

∞

∞

∑∑ y (2 k

−k

n) fk (t − 2−k n)

(6.7)

k=−∞ n=−∞

Our definition of the filters shows that the frequency responses are scaled versions of each other, i.e., Fk(ω) = 2–k ψ(2–k ω), with ψ(ω) as in Fig. 6.9. The impulse responses are therefore related as fk(t) = ψ(2k t), and we can rewrite (6.7) as © 2003 by CRC Press LLC

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Ψ(ω) 1 −2π −π

ω

π 2π

0

FIGURE 6.9 The fundamental bandpass function that generates a bandpass wavelet.

C−1,n H−1(ω)

0

sampler

2

t F−1(ω)

C0n x(t)

H0(ω)

sampler

0 1 2

H1(ω)

sampler

0 1

t F0(ω)

C1,n

x(t)

t F1(ω)

Analysis bank

Synthesis bank (a) H−1 and F−1 √2

H0 and F0 H1 and F1

1 −π

0

π 2π (b)

4π

H2 and F2 8π

ω

FIGURE 6.10 The octave-band splitting scheme. (a) The analysis bank, samplers, and synthesis bank; and (b) the filter responses.

x (t ) =

∞

∞

∑∑ y (2 n)ψ(2 −k

k

−k

)

t −n

k=−∞ n=−∞

(6.8)

We will write this as x(t) = Σk Σn Ckn ψkn (t) by defining ckn = 2–k/2 yk (2–k n) and

(

)

( (

))

ψ kn (t ) = 2k 2 ψ 2k t − n = 2k/2 ψ 2k t − 2−k n

(6.9)

Then the functions ykn(t) will have the same energy ∫ψkn (t)2 dt for all k, n. From the analysis/synthesis filter bank point of view (Fig. 6.7) this is equivalent to making Hk (ω) = Fk (ω) and rescaling, as shown in Fig. 6.10. With filters so rescaled, the wavelet coefficients ckn are just samples of the outputs of the analysis filters Hk (ω). The function ψ(2kt) is a dilated version of ψ(t) (squeezed version if k > 0 and stretched version if k < 0). The dilation factor 2k is a power of 2, so this is said to be a dyadic dilation. The function ψ(2k (t – 2–k n)) is a shifted version of the dilated version. Thus, we have expressed x(t) as a linear combination of shifted versions of (dyadic) dilated versions of a single function ψ(t). The shifts 2–k n, are in integer multiples of 2–k, where k governs the dilation. For completeness, note that the impulse response ψ(t) corresponding to the function in Fig. 6.9 is given by © 2003 by CRC Press LLC

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ψ(t)

1

t

t=2

FIGURE 6.11 The ideal bandpass wavelet.

ψ (t ) =

sin(πt 2) cos(3πt 2) πt 2

(ideal bandpass wavelet)

(6.10)

This is plotted in Fig. 6.11. In (6.8) we obtained a wavelet representation for x(t) [compare to (6.4)]. The function ψ(t) is called the ideal bandpass wavelet, also known as the Littlewood–Paley wavelet. We now introduce some terminology for convenience and then return to more detailed definitions and discussions of the WT.

L2 Spaces, Basis Functions, and Orthonormal Bases Most of our discussions are restricted to the class of L2 functions or square integrable functions, i.e., functions x(t) for which ∫ x(t)2 dt exists and has a finite value. The norm, or L2 norm, of such functions, denoted x(t)2, is defined as x(t)2 = (∫ x(t)2 dt)1/2. The notation L2[a,b] stands for L2 functions that are zero outside the interval a ≤ t ≤ b. The set L2(R) is the class of L2 functions supported on the real line –∞ < t < ∞. We often abbreviate L2(R) as L2. The class of L2 functions forms a (normed) linear vector space, i.e., any finite linear combination of functions in L2 is still in L2. In fact, it forms a special linear space such that a countable basis exists. That is, a sequence of linearly independent functions {gn (t)} exists in L2 such that any L2 function x(t) can be expressed as x(t) = Σn αn gn (t), for a unique set of {αn}. We say that gn (t) are the basis functions. L2 spaces have orthonormal bases. For such a basis, the basis functions satisfy g k (t ), g m (t ) = δ(k − m)

(6.11)

∆ where the notation 〈 f (t), g(t)〉 = ∫ f (t)g ∗ (t)dt denotes the inner∞ product between f (t) and g(t). For an orthonormal basis, the coefficients αn in the expansion x(t) = ∑ α g (t ) can thus be computed using n =−∞ n n the exceptionally simple relation

α n = x (t ), g n (t

(6.12)

Two examples of orthonormal basis were shown previously. The first is the FS expansion of a time-limited signal (0 ≤ t ≤ 1). Here, the basis functions {e j2πnt} are clearly orthonormal, with integrals going from 0 to 1. The second example is the expansion (6.3) of a band-limited signal; it can be shown that the shifted versions f (t – nT) of the sinc functions form an orthonormal basis for band-limited signals (integrals going from –∞ to ∞). © 2003 by CRC Press LLC

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Orthogonal Projections Suppose we consider a subset {gnk (t)} of the orthonormal basis {gn (t)}. Let  denote the subspace generated by {gnk (t)} (an accurate statement would be that  is the “closure of the span of {gnk (t)}”; see Section 6.7). Consider the linear combination y(t) = ∑k α nk g nk (t ), where the αnk are evaluated as above, i.e., αnk = 〈x(t), gnk (t)〉 for some signal x(t). Then, y(t) ∈ , and it can be shown that among all functions in , y(t) is the unique signal closest to x(t) (i.e, x(t ) − y(t ) 2 is the smallest). We say that y(t) is the orthogonal projection of x(t) onto the subspace , and write

[ ]

y (t ) = P x (t )

(6.13)

Wavelet Transforms If a signal x(t) is in L2, then its FT X(ω) exists in the L2 sense (see Section 6.6). We will see in Section 6.6 that the discussion which resulted in (6.8) is applicable for any signal x(t) in L2. Equation (6.8) means that the signal can be expressed as a linear combination of the form

x (t ) =

∞

∞

∑∑ c

kn

(

)

2k 2 ψ 2k t − n 14 4244 3

(6.14)

ψ kn (t )

k=−∞ n=−∞

where ψ(t) is the impulse response (Fig. 6.11) of the bandpass function Ψ(ω) in Fig. 6.9.2 Because the frequency responses for two different values of k do not overlap, the functions ψkn(t) and ψmi(t) are orthogonal for k ≠ m (use Parseval’s relation). For a given k, the functions ψkn(t) are shifted versions of the impulse responses of the bandpass filter Fk(ω). From the ideal nature of this bandpass filter, we can show that ψkn(t) and ψkm(t) are also orthonormal for n ≠ m. Thus, the set of functions {ψkn(t)}, with k and n ranging over all integers, forms an orthonormal basis for the class of L2 functions, i.e., any L2 function can be expressed as in (6.14) and furthermore,

ψ kn (t ), ψ mi (t ) = δ (k − m)δ(n − i )

(6.15)

Because of this orthonormality, the coefficients ckn are computed very easily as

c kn = x (t ), ψ kn (t ) =

∞

∫ x(t )2

k 2

−∞

ψ * (2k t − n)dt

(6.16)

Defining

η(t ) = ψ * (−t )

(6.17)

this takes the form

c kn = x (t ), η *kn(−t ) =

∞

∫ x(t )2 η(n − 2 t )dt k 2

−∞

k

(6.18)

resembling a convolution. Wavelet Transform Definitions A set of basis functions ψkn(t) derived from a single function ψ(t) by dilations and shifts of the form

(

)

ψ kn (t ) = 2k 2 ψ 2k t − n 2

(6.19)

The above equality and the convergence of the summation should be interpreted in the L2 sense; see Section 6.6.

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is said to be a wavelet basis, and ψ(t) is called the wavelet function. The coefficients ckn are the wavelet transform coefficients. The formula (6.16) that performs the transformation from x(t) to ckn is the wavelet transform of the signal x(t). Equation (6.14) is the wavelet representation or the inverse wavelet transform. While this is only a special case of more general wavelet decompositions outlined at the end of this section, it is perhaps the most popular and useful. Note that the kth dilated version ψ(2k t) has the shifted versions ψ(2k t – n) = ψ(2k (t – 2–k n)), so the amount of shift is in integer multiples of 2–k. Thus, the stretched versions are shifted by larger amounts and squeezed versions by smaller amounts. Even though we developed these ideas based on an example, the above definitions still hold generally for any orthonormal wavelet basis. For the ideal bandpass wavelet, the function ψ(t) is real and symmetric [see (6.10)] so that η(t) = ψ(t). For more general orthonormal wavelets, we have the relation η(t) = ψ ∗ (–t). We say that η(t) is the analyzing wavelet [because of (6.18)] and ψ(t) the synthesis wavelet [because of (6.14)]. For the nonorthonormal case we still have the transform and inverse transform equations as above, but the relation between ψ(t) and η(t) is not as simple as η(t) = ψ ∗ (–t). Before exploring the properties and usefulness of wavelets let us turn to a distinctly different example. This shows that unlike the Fourier basis functions {e j2πnt}, the wavelet basis functions can be designed by the user. This makes them more flexible, interesting, and useful.

Haar Wavelet Basis An orthonormal basis for L2 functions was found by Haar [5] as early as 1910, which satisfies the definition of a wavelet basis given above. That is, the basis functions ψkn(t) are derived from a single function ψ(t) using dilations and shifts as in (6.19). To explain this system, first, consider a signal x(t) ∈ L2[0,1]. The Haar basis is built from two functions called φ (t) and ψ(t), as described in Fig. 6.12. The basis function φ (t) is a constant in [0,1]. The basis function ψ(t) is constant on each half interval, and its integral is zero. After this, the remaining basis functions are obtained from ψ(t) by dilations and shifts as indicated. It is clear from the figure that any two of these functions are mutually orthogonal. We have an orthonormal set, and it can be shown that this set of functions is an orthonormal basis for L2[0,1]. However, this is not exactly a wavelet basis yet because of the presence of φ(t).3 If we eliminate the requirement that x(t) be supported or defined only on [0,1] and consider L2(R) functions then we can still obtain an orthonormal basis of the above form by including the shifted versions {ψ(2k t – n)} for all integer values of n, as well as the shifted versions {φ(t – n)}. An alternative to the use of {φ(t – n)} would be to use stretched (i.e., ψ(2k t), k < 0) as well as squeezed (i.e., ψ(2k t), k > 0) versions of ψ (t). The set of functions can thus be written as in (6.19), which has the form of a wavelet basis. It can be shown that this forms an orthonormal basis for L2(R) . The FT of the Haar wavelet ψ (t) is given by Ψ(ω ) = je − jω

2

sin 2 (ω 4) ω 4

(Haar wavelet)

(6.20)

The Haar wavelet has limited duration in time, whereas the ideal bandpass wavelet (6.10), being bandlimited, has infinite duration in time.

Basic Properties of Wavelet Transforms Based on the definitions and examples provided so far, we can already draw some very interesting conclusions about wavelet transforms, and obtain a preliminary comparison to the FT.

3We see in Section 6.10 that the function φ (t) arises naturally in the context of the fundamental idea of multiresolution.

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φ(t)

2ψ(4t)

1

2 t

0

ψ20(t)

1

ψ(t)

2ψ(4t−1)

1

2

ψ00(t) 0.5

1

t

ψ21(t)

t

0.5

0

0.25

√2 ψ(2t) ψ10(t)

t

0.25

2ψ(4t−2)

√2

2 t

0.5

ψ22(t)

t

0.75 0.5

√2 ψ(2t−1) ψ11(t)

2ψ(4t−3)

√2

2 1

t

ψ23(t)

0.5

1.0

t

0.75

FIGURE 6.12 Examples of basis functions in the Haar basis for L2[0, 1].

1. Concept of scale. The functions ψkn(t) are useful to represent increasingly finer “variations” in the signal x(t) at various levels. For large k, the function ψkn(t) looks like a “high frequency signal”. This is especially clear from the plots of the Haar basis functions. (For the bandpass wavelets, see below.) Because these basis functions are not sinusoids, we do not use the term “frequency” but rather the term “scale”. We say that the component ψkn(t) represents a finer scale for larger k. Accordingly k (sometimes 1/k) is called the scale variable. Thus, the function x(t) has been represented as a linear combination of component functions that represent variations at different “scales”. For instance, consider the Haar basis. If the signal expansion (6.14) has a relatively large value of c4,2 this means that the component at scale k = 4 has large energy in the interval [2/24, 3/24] (Fig. 6.14). 2. Localized basis. The preceding comment shows that if a signal has energy at a particular scale concentrated in a slot in the time domain, then the corresponding ckn has large value, i.e., ψkn(t) contributes more to x(t). The wavelet basis, therefore, provides localization information in time domain as well as in the scale domain. For example, if the signal is zero everywhere except in the interval [2/24, 3/24] then the subset of the Haar basis functions which do not have their support in this interval are simply absent in this expansion. Note that the Haar wavelet has compact support, that is, the function ψ(t) is zero everywhere outside a closed bounded interval ([0,1] here). While the above discussions are motivated by the Haar basis,

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many of them are typically true, with some obvious modifications, for more general wavelets. Consider, for example, the ideal bandpass wavelet (Fig. 6.11) obtained from the bandpass filter Ψ(ω) in Fig. 6.9. In this case the basis functions do not have compact support, but are still locally concentrated around t = 0. Moreover, the basis functions for large k represent “fine” information, or the frequency component around the center frequency of the filter Fk(ω) (Fig. 6.10). The Haar wavelet and the ideal bandpass wavelet are two extreme examples (one is time limited and the other band-limited). Many intermediate examples can be constructed.

Filter Bank Interpretation and Time-Frequency Representation We know that the wavelet coefficients ckn for the ideal bandpass wavelet can be viewed as the sampled version of the output of a bandpass filter [Fig. 6.10(a)]. The same is true for any kind of WT. For this recall, the expression (6.18) for the wavelet coefficients. This can be interpreted as the set of sampled output sequences of a bank of filters Hk (ω), with impulse response hk(t) = 2k/2 ho(2kt), where ho(t) = η(t). Thus the wavelet transform can be interpreted as a nonuniform continuous time analysis filter bank, followed by samplers. The Haar basis and ideal bandpass wavelet basis are two examples of the choice of these bandpass filters. The wavelet coefficients ckn for a given scale k are therefore obtained by sampling the output yk(t) of the bandpass filter Hk (ω), as indicated in Fig. 6.13(a). The first subscript k (the scale variable) represents the filter number. As k increases by 1, the center frequency ωk increases by a factor of 2. The wavelet coefficients ckn at scale k are merely the samples yk (2–k n). As k increases, the filter bandwidth increases, and thus the samples are spaced by a proportionately finer amount 2–k. The quantity ckn = yk(2–k n) measures the “amount” of the “frequency component” around the center frequency ωk of the analysis filter Hk(ω), localized in time around 2–k n. In wavelet transformation, the transform domain is represented by the two integer variables k and n. This means that the transform domain is two dimensional (the time-frequency domain), and is discretized.

C−1,n

y−1(t) sampler Ts = 2

h−1(t) = 1 η(t/2) √2

(a) x(t)

C0,n

y0(t) sampler Ts = 1

h0(t) = η(t) y1(t) h1(t) = √2 η(2t)

f−1(t) = 1 Ψ(t/2) √2 f0(t) = Ψ(t)

x(t)

C1,n sampler Ts = 0.5

f1(t) = √2 Ψ(2t)

wavelet coefficients Analysis bank η(t) = analyzing wavelet

Synthesis bank

Ψ(t) = synthesizing wavelet

F−1 (ω) F0 (ω) = Ψ(ω)

√2 1

(b) 0

π

2π

4π

F1 (ω)

F2 (ω) ω

FIGURE 6.13 (a) Representing the dyadic WT as an analysis bank followed by samplers, and the inverse transform as a synthesis bank. For the orthonormal case, ψ(t) = η∗(–t), and fk(t) = hk∗ (–t). (b) Filter responses for the example in which ψ(t) is the ideal bandpass wavelet.

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We say that ckn is a time-frequency representation, of x(t). Section 6.3 explains that this is an improve­ ment over another time-frequency representation, the short-time Fourier transform (STFT), introduced many years ago in the signal processing literature. Synthesis Filter Bank and Reconstruction The inner sum in (6.14) can be interpreted as follows: For each k, convert the sequence ckn into an impulse train4 Σn ckn δa(t – 2–k n) and pass it through a bandpass filter Fk (ω) = 2–k /2 Ψ(2–k ω) with impulse response fk(t) = 2k/2 Ψ(2k t). The outer sum merely adds the outputs of all these filters. Figure 6.13(a) shows this interpretation. Therefore, the reconstruction of the signal x(t) from the wavelet coefficients ckn is equivalent to the implementation of a nonuniform continuous time synthesis filter bank, with ∆ ψ(t). synthesis filters fk (t) = 2k/2 f0 (2k t) generated by dilations of a single filter f0(t) = As mentioned earlier, the analyzing wavelet η(t) and the synthesis wavelet ψ (t) are related by η(t) = Ψ ∗ (–t) in the orthonormal case. Thus, the analysis and synthesis filters are related as hk (t) = fk∗ (–t); i.e., Hk (ω) = Fk∗ (ω). For the special case of the ideal bandpass wavelet (6.10), ψ(t) is real and symmetric so that fk (t) = fk∗ (–t); i.e., hk (t) = fk (t). Figure 6.13 summarizes the relations described in the preceding paragraphs. Design of Wavelet Functions Because all the filters in the analysis and synthesis banks are derived from the wavelet function ψ(t), the quality of the frequency responses depends directly on Ψ(ω). In the time domain the Haar basis has poor smoothness (it is not even continuous), but it is well localized (compactly supported). Its FT ψ(ω), given in (6.20), decays only as 1/ω for large ω. The ideal bandpass wavelet, on the other hand, is poorly localized in time, but has very smooth behavior. In fact, because it is band-limited, ψ(t) is infinitely differentiable, but it decays only as 1/t for large t. Thus, the Haar wavelet and the ideal bandpass wavelet represent two opposite extremes of the possible choices. We could carefully design the wavelet ψ(t) such that it is reasonably well localized in time domain, while at the same time sufficiently smooth or “regular”. The term regularity is often used to quantify the degree of smoothness. For example, the number of times we can differentiate the wavelet ψ(t) and the degree of continuity (so-called Hölder index) of the last derivative are taken as measures of regularity. We return to this in Sections 6.11 to 6.13, where we also present systematic procedures for design of the function ψ(t). This can be designed in such a way that {2k/2 ψ(2k t – n)}forms an orthonormal basis with prescribed decay and regularity properties. It is also possible to design ψ(t) such that we obtain other kinds of structures rather than an orthonormal basis, e.g., a Riesz basis or a frame (see Sections 6.7 and 6.8).

Wavelet Basis and Fourier Basis Returning to the Fourier basis gk (t) = {e j2πkt} for functions supported on [0,1], we see that gk(t) = g1(kt), so that all the functions are dilated versions (dilations being integers rather than powers of integers) of g1(t). However, these do not have the localization property of wavelets. To understand this, note that e j2πkt has unit magnitude everywhere, and sines and cosines are nonzero almost everywhere. Thus, if we have a function x(t) that is identically zero in a certain time slot (e.g., Fig. 6.14), then in order for the infinite series Σn αn e j2πnt to represent x(t), extreme cancellation of terms must occur in that time slot. In contrast, if a compactly supported wavelet basis is used, it provides localization information as well as information about “frequency contents” in the form of “scales”. The “transform domain” in traditional FT is repre­ sented by a single continuous variable ω. In the wavelet transform, where the transform coefficients are ckn , the transform domain is represented by two integers k and n. It is also clear that WT provides a great deal of flexibility because we can choose ψ(t). With FTs, on the other hand, the basis functions (sines and cosines) are pretty much fixed (see, however, Section 6.3 on STFT). δa(t) is the Dirac delta function [2]. It is used here only as a schematic. The true meaning is that the output of fk(t) is n cknfk(t – 2–k n). 4

Σ

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Ψ4.2(t) 3

16

t 2

16

x(t)

3

16

t 0

2

1 16

FIGURE 6.14 Example of an L2[0,1] signal x(t) for which the Haar component ψ4,2(t) dominates.

More General Form of Wavelet Transformation The most general form of wavelet transform is given by X (a, b)

1 a

 t − b ∫ x(t )ψ a  dt ∞

−∞

(6.21)

where a and b are real. This is called the continuous wavelet transform (CWT) because a and b are continuous variables. The transform domain is a two-dimensional domain (a, b). The restricted version of this, in which a and b take a discrete set of values a = c –k and b = c –k n (where k and n vary over the set of all integers), is called the discrete wavelet transform (DWT). The further special case, in which c = 2, i.e., a = 2–k and b = 2–k n, is the WT discussed so for [see (6.16)] and is called the dyadic DWT. Expansions of the form (6.14) are also called wavelet series expansions by analogy with the FS expansion (a summation rather than an integral). For fixed a, (6.21) is a convolution. Thus, if we apply the input signal x(t) to a filter with impulse response ψ(–t/a)/ a , its output, evaluated at time b, will be X(a, b). The filter has frequency response a Ψ(–aω). If we imagine that ψ(ω) has a good bandpass response with center frequency ω0, then the above filter is bandpass with center frequency –a –1 ω0; i.e., the wavelet transform X(a, b), which is the output of the filter at time b, represents the “frequency content” of x(t) around the frequency –a –1ω0 “around” time b. Ignoring the minus sign [because ψ(t) and x(t) are typically real anyway], we see that the variable a –1 is analogous to frequency. In wavelet literature, the quantity |a| is usually referred to as the “scale” rather than “inverse frequency”. For reasons that cannot be explained with our limited exposure thus far, the wavelet function ψ(t) is restricted to be such that ∫ ψ(t)dt = 0. For the moment, notice that is equivalent to Ψ(0) = 0, which is consistent with the bandpass property of ψ(t). In Section 6.10, where we generate wavelets systematically using multiresolution analysis, we see that this condition follows naturally from theoretical considerations.

6.3 The Short-Time Fourier Transform In many applications, we must accommodate the notion of frequency that evolves or changes with time. For example, audio signals are often regarded as signals with a time-varying spectrum, e.g., a sequence of short-lived pitch frequencies. This idea cannot be expressed with the traditional FT because X(ω) for each ω depends on x(t) for all t. The STFT was introduced as early as 1946 by Gabor [5] to provide such a time-frequency picture of the signal. Here, the signal x(t) is multiplied with a window v(t – τ) centered or localized around time τ (Fig. 6.15) and the FT of x(t) v(t-τ) computed as

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x(t) t

Shifted version

v(t−τ)

t

τ

FIGURE 6.15 A signal x(t) and the sliding window v(t – τ).

X (ω, τ) =

∞

∫ x(t )v(t − τ)e

− jωt

−∞

dt

(6.22)

This is then repeated for shifted locations of the window, i.e., for various values of τ. That is, we compute not just one FT, but infinitely many. The result is a function of both time τ and frequency ω. If this must be practical we must make two changes: compute the STFT only for discrete values of ω, and use only a discrete a number of window positions τ. In the traditional STFT both ω and τ are discretized on uniform grids: ω = kω s τ = nTs

(6.23)

The STFT is thus defined as XSTFT (kω s ,nTs ) =

∞

∫ x(t )v(t − nT )e −∞

s

− jkω st

dt,

(6.24)

which we abbreviate as XSTFT (k, n) when there is no confusion. Thus the time domain is mapped into the time-frequency domain. The quantity XSTFT(kωs, nTs) represents the FT of x(t) “around time nTs” and “around frequency kωs”. This, in essence, is similar to the WT: in both cases the transform domain is a two-dimensional discrete domain. We compare wavelets and STFT on several grounds, giving a filter bank view and comparing timefrequency resolution and localization properties. Section 6.9 provides a comparison on deeper grounds: for example, when can we reconstruct a signal x(t) from the STFT coefficients XSTFT (k, n)? Can we construct an orthonormal basis for L2 signals based on the STFT? The advantage of WTs over the STFT will be clear after these discussions.

Filter Bank Interpretation The STFT evaluated for some frequency ωk can be rewritten as X STFT (ω k, τ) = e − jωk τ

∞

∫ x(t )v(t − τ)e −∞

− jω k (t − τ )

dt

(6.25)

This integral looks like a convolution of x(t) with the filter impulse response hk (t ) = v (−t )e jωkt ∆

(6.26)

If v(– t) has a FT looking like a low-pass filter then hk(t) looks like a bandpass filter with center frequency ωk (Fig. 6.16). Thus, XSTFT (ωk , τ) is the output of this bandpass filter at time τ, downshifted in frequency by ωk. The result is a low-pass signal yk (t) whose output is sampled uniformly at time τ = nTs . For every © 2003 by CRC Press LLC

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FT of v(−t)

Hk(ω)

ω

ωk

0 X(ω)

X(ω)Hk(ω) ω

ωk

0

Downshifted X(ω)Hk(ω) ω

0

FIGURE 6.16 STFT viewed as a bandpass filter followed by a downshifter.

y−1(t) H−1(ω) e jωst x(t)

sampler Ts

t

sampler Ts

t

sampler Ts

t

y0(t)

H0(ω) 1

y1(t)

H1(ω) e−jωst

STFT coefficients

H0(ω) H (ω) 1

H−1(ω)

−ωs

0

ωs 2ωs

ω

FIGURE 6.17 The STFT viewed as an analysis bank of uniformly shifted filters.

frequency ωk so analyzed, one such filter channel exists. With the frequencies uniformly located at ωk = kωs, we get the analysis filter bank followed by downshifters and samplers as shown in Fig. 6.17. The STFT coefficients XSTFT (kωs, nTs), therefore, can be regarded as the uniformly spaced samples of the outputs of a bank of bandpass filters Hk(ω), all derived from one filter h0(t) by modulation: hk(t) = e jkωst ho(t); i.e., Hk(ω) = H0(ω – kωs). (The filters are one sided in frequency so they have complex coefficients in the time domain, but ignore these details for now.) The output of Hk(ω) represents a portion of the FT X(ω) around the frequency kωs. The downshifted version yk(t) is therefore a low-pass signal. In other words, it is a slowly varying signal, whose evolution as a function of t represents the evolution of FT X(ω) around frequency kωs. By sampling this slowly varying signal, we can therefore compress the transform domain information. If the window is narrow in the time domain, then Hk(ω) has large bandwidth. That is, a good time resolution and poor frequency resolution are obtained. If the window is wide, the opposite is true. Thus, © 2003 by CRC Press LLC

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if we try to capture the local information in time by making a narrow window, we get a fuzzy picture in frequency. Conversely, in the limit, as the filter becomes extremely localized in frequency, the window is very broad and STFT approaches the ordinary FT. That is, the time-frequency information collapses to the all-frequency information of ordinary FT. We see that time-frequency representation is inherently a compromise between time and frequency resolutions (or localizations). This is related to the uncertainty principle: as windows get narrow in time they have to get broad in frequency, and vice versa. Optimal Time-Frequency Resolution: The Gabor Window What is the best frequency resolution one can obtain for a given time resolution? For a given duration of the window v(t) how small can the duration of V(ω) be? If we define duration according to common sense, we are already in trouble because if v(t) has finite duration then V(ω) has infinite duration. A more useful definition of duration is called the root mean square (RMS) duration. The RMS time duration Dt and the RMS frequency duration Df for the window v(t) are defined such that

∫ t v(t ) dt = ∫ v(t ) dt 2

2

Dt2

2

∫ ω V (ω) dω = ∫ V (ω) dω 2

2

D 2f

2

(6.27)

Intuitively, Dt cannot be arbitrarily small for a specified Df. The uncertainty principle says that Dt Df ≥ 0.5. Equality holds iff v(t) has the shape of a Gaussian, i.e., v(t) = Ae –αt 2, α > 0. Thus, best joint timefrequency resolution is obtained by using the Gaussian window. This is also intuitively acceptable for the reason that the Gaussian is its own FT (except for scaling of variables and so forth). Gabor used the Gaussian window as early as 1946. Because it is of infinite duration, a truncated approximation is used in practice. The STFT based on the Gaussian is called the Gabor transform. A limitation of the Gabor transform is that it does not give rise to an orthonormal signal representation; in fact, it cannot even provide a “stable basis”. (Sections 6.7 and 6.9 explain the meaning of this.)

Wavelet Transform vs. Short-Time Fourier Transform The STFT works with a fixed window v(t). If a high frequency signal is being analyzed, many cycles are captured by the window, and a good estimate of the FT is obtained. If a signal varies very slowly with respect to the window, however, then the window is not long enough to capture it fully. From a filter bank viewpoint, notice that all the filters have identical bandwidths (Fig. 6.17). This means that the frequency resolution is uniform at all frequencies, i.e., the “percentage resolution” or accuracy is poor for low frequencies and becomes increasingly better at high frequencies. The STFT, therefore, does not provide uniform percentage accuracy for all frequencies; the computational resources are somehow poorly distributed. Compare this with the WT, which is represented by a nonuniform filter bank [Fig. 6.8(b)]. Here, the frequency resolution gets poorer as the frequency increases, but the fractional resolution (i.e., the filter bandwidth ∆ωk divided by the center frequency ωk) is constant for all k (the percentage accuracy is uniformly distributed in frequency). In the time domain this is roughly analogous to having a large library of windows; narrow windows are used to analyze high-frequency components and very broad windows are used to analyze low-frequency components. In electrical engineering language the filter bank representing WT is a constant Q filter bank, or an octave band filter bank. Consider, for example, the Haar wavelet basis. Here, the narrow basis functions ψ2,n (t) of Fig. 6.12 are useful to represent the highly varying components of the input, and are correspondingly narrower (have shorter support than the functions ψ1, n (t)). A second difference between the STFT and the WTs is the sampling rates at the outputs of the bandpass filters. These are identical for the STFT filters (since all filters have the same bandwidth). For the wavelet filters, these are proportional to the filter bandwidths, hence nonuniform [Fig. 6.10(a)]. This is roughly

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analogous to the situation that the narrower windows move in smaller steps compared to the wider windows. Compare again with Fig. 6.12 where ψ2,n (t) are moved in smaller steps as compared to ψ1,n (t) in the process of constructing the complete set of basis functions. The nonuniform (constant Q) filter stacking [Fig. 6.8(b)] provided by wavelet filters is also naturally suited for analyzing audio signals and sometimes even as components in the modeling of the human hearing system. Time-Frequency Tiling The fact that the STFT performs uniform sampling of time and frequency whereas the WT performs nonuniform sampling is represented by the diagram shown in Fig. 6.18. Here, the vertical lines represent time locations at which the analysis filter bank output is sampled, and the horizontal lines represent the center frequencies of the bandpass filters. The time frequency tiling for the STFT is a simple rectangular grid, whereas for the WT it has a more complicated appearance.

6ωs

5ωs

4ωs (a) 3ωs

2ωs ωs

−3Ts

−2Ts

−Ts

0

Ts

2Ts

3Ts

8ωs

(b) 4ωs

2ωs ωs −2Ts

−Ts

−Ts/2

0

Ts/2

Ts

FIGURE 6.18 Time-frequency tiling schemes for (a) the STFT and (b) the WT.

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2Ts

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x(t)

t −0.4

0.2

0.4

FIGURE 6.19 The signal to be analyzed by STFT and WT.

100 90

90

80

80

70

70

60

60

50

50

40

40

ω/π

ω/π

(a)

100 STFT 0.1

30

30

20

20

10

10

0 −2

−1.5

−1

−0.5

0 time

0.5

1

1.5

0 −2

2

100 90

90

80

80

70

70

60

60

50

50

40

40

30

30

20

20

10 0 −2

(b)

−1.5

−1

−0.5

0 time

0.5

1

1.5

2

100 STFT 0.3

a−1

ω/π

(c)

STFT 1.0

Wavelet Transform

(d)

10 −1.5

−1

−0.5

0 time

0.5

1

1.5

2

0 −2

−1.5

−1

−0.5

0 b

0.5

1

1.5

2

FIGURE 6.20 (a) to (c) STFT plots with window widths of 0.1, 1.0, and 0.3, respectively, and (d) WT plot.

Example 1. Consider the signal x(t) = cos(10πt) + 0.5 cos(5πt) + 0.5 cos(5πt) + 1.2δa(t – 0.07) + 1.2δa(t + 0.07). It has impulses at t = ±0.07 in the time domain. Two impulses (or “lines”) are found in the frequency domain, at ω1 = 5π and ω2 = 10 π. The function is illustrated in Fig. 6.19 with impulses replaced by narrow pulses. The aim is to try to compute the STFT or WT such that the impulses in time as well as those in frequency are resolved. Figure 6.20(a) to (c) shows the STFT plot for three widths of the window v(t) and Fig. 6.20(d) shows the wavelet plot. The details of the window v(t) and the wavelet ψ(t) used for this example are described next, but first let us concentrate on the features of these plots.

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Ψ(ω)

ω 0

π

FIGURE 6.21 FT magnitude for the Morlet wavelet.

The STFT plots are time-frequency plots, whereas the wavelet plots are (a –1, b) plots, where a and b defined by (6.21). As explained in Section 6.2, the quantity a –1 is analogous to “frequency” in the STFT, and b is analogous to “time” in the STFT. The brightness of the plots in Fig. 6.20 is proportional to the magnitude of the STFT or WT, so the transform is close to zero in the dark regions. We see that for a narrow window with width equal to 0.1, the STFT resolves the two impulses in time reasonably well, but the impulses in frequency are not resolved. For a wide window with width equal to 1.0, the STFT resolves the “lines” in frequency very well, but not the time domain impulses. For an intermediate window width equal to 0.3, the resolution is poor in both time and frequency. The wavelet transform plot [Fig. 6.20(d)], on the other hand, simultaneously resolves both time and frequency very well. We can clearly see the locations of the two impulses in time, as well as the two lines in frequency. The STFT for this example was computed using the Hamming window [2] defined as v(t) = c[0.54 + 0.46 cos (πt/D)] for – D ≤ t ≤ D and zero outside. The “widths” indicated in the figure correspond to D = 0.1, 1.0, and 0.3 (although the two-sided width is twice this). The wavelet transform was computed by using an example of the Morlet wavelet [5]. Specifically, ψ (t ) = e −t

2

16

(e

jπt

−α

)

First, let us understand what this wavelet function is doing. The quantity e –t2/16 is the Gaussian (except for a constant scalar factor) with Fourier transform 4 π , e –4ω2 which is again Gaussian, concentrated near ω = 0. Thus, e –t2/16 e jπt has a FT concentrated around ω = π. Ignoring the second term α in the expression for ψ(t), we see that the wavelet is a narrowband bandpass filter concentrated around π (Fig. 6.21).5 If we set a = 1 in (6.21), then X(1, b) represents the frequency contents around π. Thus, the frequencies ω1 = 5π and ω2 = 10π in the given signal x(t) show up around points a –1 = 5 and a –1 = 10 in the WT plot, as seen from Fig. 6.20(d). In the STFT plots, we have shown the frequency axis as ω/π so that the frequencies ω1 and ω2 show up at 5 and 10, making it easy to compare the STFT plots with the wavelet plot. ▫ Mathematical Issues to Be Addressed While the filter bank viewpoint places wavelets and STFT on unified ground, several mathematical issues remain unaddressed. It is this deeper study that brings forth further subtle differences, giving wavelets a definite advantage over the STFT. Suppose we begin from a signal x(t) ∈ L2 and compute the STFT coefficients X(kωs, nTs ). How should we choose the sampling periods Ts and ωs of the time and frequency grids so that we can reconstruct x(t) from the STFT coefficients? (Remember that we are not talking about band-limited signals, and no sampling theorem is at work.) If the filters Hk(ω)are ideal one-sided bandpass filters with bandwidth ωs , the downshifted low-pass outputs yk(t) (Fig. 6.16) can be sampled separately at the Nyquist rate ωs or higher. This then tells us that Ts ≤ 2π/ωs , that is, The quantity α in the expression of ψ(t) ensures that ∫ψ(t)dt = 0 (Section 6.2). Because α is very small, it does not significantly affect the plots in Fig. 6.20. 5

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ω sTs ≤ 2π

(6.28)

However, the use of ideal filters implies an impractical window v(n). If we use a practical window (e.g., one of finite duration), how should we choose Ts in relation to ωs so that we can reconstruct x(t) from the STFT coefficients X(kωs , nTs )? Is this a stable reconstruction? That is, if we make a small error in some STFT coefficient does it affect the reconstructed signal in an unbounded manner? Finally, does the STFT provide an orthonormal basis for L2? These questions are deep and interesting, and require more careful treatment. We return to these in Section 6.9.

6.4 Digital Filter Banks and Subband Coders Figure 6.22(a) shows a two-channel filter bank with input sequence x(n) (a discrete-time signal). Ga(z) and Ha(z) are two digital filters, typically low-pass and high-pass. x(n) is split into two subband signals, x0(n) and x1(n), which are then downsampled or decimated (see the following paragraphs for definitions). The total subband data rate, counting both subbands, is equal to the number of samples per unit time in the original signal x(n). Digital filter banks provide a time-frequency representation for discrete time signals, similar to the STFT and WT for continuous time signals. The most common engineering appli­ cation of the digital filter bank is in subband coding, which is used in audio, image, and video compression. Neither subband coding nor such a time frequency representation is the main point of our discussion here. We are motivated by the fact that a deep mathematical connection exists between this digital filter bank and the continuous time WT. This fundamental relation, discovered by Daubechies [6], is fully elaborated in Section 6.10 to 6.13. This relation is what makes the WT so easy to design and attractive to implement in practice. Several detailed references on the topic of multirate systems and digital filter banks are available [7], and a detailed treatment can be found in Chapter 89 of this handbook, so we will be brief. The Multirate Signal Processing Building Blocks: The building blocks in the digital filter bank of Fig. 6.22(a) are digital filters, decimators, and expanders. The M-fold decimator or downsampler (denoted ↓M) is defined by the input-output relation y(n) = x(Mn). The corresponding z-domain relation

x(n) Ga(z) (a) Ha(z)

x0(n)

x1(n)

↓2

↓2

Subband signals

y0(n)

↑2

Gs(z)

↑2

Hs(z)

expanders

synthesis filters

y1(n)

Analysis filters Decimators

xˆ (n) Reconstructed signal

Ha(e jω )

Ga(e jω ) (b)

0

π/2

ω

π

X(e jω ) Typical input spectrum (c)

0

π

ω

FIGURE 6.22 (a) The two-channel digital filter bank, (b) typical filter responses, and (c) typical input spectrum.

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is Y(z) = (1/M) Σ k=0 X(z1/M e –j2πk/M). This relation is sometimes abbreviated by the notation Y(z) = X(z)↓M or Y(e jω) = X(e jω)↓M . The M-fold expander or upsampler (denoted ↑M) is defined by M–1

(

)

 x n M ,

y (n) = 

 0,

n = multiple of M, otherwise



(6.29)

The transform domain relation for the expander is Y(z) = X(zM), i.e., Y(e jω) = X(e jMω).

Reconstruction from Subbands In many applications, it is desirable to reconstruct x(n) from the decimated subband signals yk(n) (possibly after quantization). For this, we pass yk(n) through expanders and combine them with the synthesis filters Gs(z) and Hs(z). The system is said to have the perfect reconstruction (PR) property if xˆ(n) = cx(n – n0) for some c ≠ 0 and some integer n0. The PR property is not satisfied for several reasons. First, subband quantization and bit allocation are present, which are the keys to data compression using subband techniques. However, because our interest here lies in the connection between filter banks and wavelets, we will not be concerned with subband quantization. Second, because the filters Ga(z) and Ha(z) are not ideal, aliasing occurs due to decimation. Using the above equations for the decimator and expander building blocks, we can obtain the following expression for the reconstructed signal: Xˆ (z) = T(z)X(z) + A(z)X(–z), where T(z) = 0.5[Ga(z)Gs(z) + Ha(z)Hs(z)] and A(z) = 0.5[Ga(–z)Gs(z) + Ha(–z)Hs(z)]. The second term having X(–z) is the aliasing term due to decimation. It can be eliminated if the filters satisfy Ga (−z )Gs ( z ) + H a (−z )H s ( z ) = 0

(alias cancellation)

(6.30)

We can then obtain perfect reconstruction [Xˆ (z) = 0.5X(z)] by setting Ga ( z )Gs ( z ) + H a ( z )H s ( z ) = 1

(6.31)

A number of authors have developed techniques to satisfy the PR conditions. In this chapter we are interested in a particular technique to satisfy (6.30) and (6.31), the conjugate quadrature filter (CQF) method, which was independently reported by Smith and Barnwell in 1984 [18] and by Mintzer in 1985 [19]. Vaidyanathan [20] showed that these constructions are examples of a general class of M channel filter banks satisfying a property called orthonormality or paraunitariness. More references can be found in [7]. The two-channel CQF solution was later rediscovered in the totally different contexts of multiresolution analysis [11] and compactly supported orthonormal wavelet construction [6]. These are discussed in subsequent sections. Conjugate Quadrature Filter (CQF) Solution Suppose the low-pass filter Ga(z) is chosen such that it satisfies the condition G˜ a ( z )Ga ( z ) + G˜ a (−z )Ga (−z ) = 1

for all z

(6.32)

If we now choose the high-pass filter Ha(z) and the two synthesis filters as H a ( z ) = z −1G˜ a (−z )

Gs ( z ) = G˜ a ( z )

˜ (z ) Hs (z ) = H a

(6.33)

then (6.30) and (6.31) are satisfied, and xˆ (n) = 0.5x(n). In the time domain the above equations become ha (n) = −(−1)n g a∗ (−n + 1)

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g s (n) = g a∗ (−n)

hs (n) = ha∗ (−n)

(6.34)

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↓2

x(n) (a)

z−1

E(z2)

z−1

z

↑2

↓2

x(n)

xˆ (n) R(z2)

↓2

(b)

↑2

↑2 E(z)

z

R(z)

↓2

xˆ (n)

↑2 Polyphase matrices

↓2

x(n) (c)

↑2

z−1

xˆ (n) z

↓2

↑2

FIGURE 6.23 (a) The polyphase form of the filter bank, (b) further simplification, and (c) equivalent structure when R(z) = E–1(z).

The synthesis filters are time-reversed conjugates of the analysis filters. If we design a filter Ga(z) satisfying the single condition (6.32) and determine the remaining three filters as described previously, then the system has the PR property. A filter Ga(z) satisfying (6.32) is said to be power symmetric. Readers familiar with half-band filters will notice that the condition (6.32) says simply that G˜ a(z)Ga(z) is half-band. To design a perfect reconstruction CQF system, we first design a low-pass half-band filter G(z) with G(e jω) ≥ 0, and then extract a spectral factor Ga(z). That is, find Ga(z) such that G(z) = G˜ a(z)Ga(z). The other filters can be found from (6.33).

Polyphase Representation The polyphase representation of a filter bank provides a convenient platform for studying theoretical questions and also helps in the design and implementation of PR filter banks. According to this repre­ sentation the filter bank of Fig. 6.22(a) can always be redrawn as in Fig. 6.23(a), which in turn can be redrawn as Fig. 6.23(b) using standard multirate identities. Here, E(z) and R(z) are the “polyphase matrices”, determined uniquely by the analysis and synthesis filters, respectively. If we impose the condition R(z)E(z) = I, that is R( z ) = E −1 ( z )

(6.35)

ˆ the system reduces to Fig. 6.23(c), which is a perfect reconstruction system with x(n) = x(n). Equation (6.35) will be called the PR condition. Notice that insertion of arbitrary scale factors and delays to obtain R(z) = cz –K E –1(z) does not affect the PR property.

Paraunitary Perfect Reconstruction System A transfer matrix6 H(z) is said to be paraunitary if H(e jω) is unitary; that is, H†(e jω)H(e jω) = I (more generally H†(e jω)H(e jω) = cI, c > 0, for all ω. In all practical designs, the filters are rational transfer ˜ ˜ ) was functions so that the paraunitary condition implies H(z)H(z) = I for all z, where the notation H(z 6Transfer matrices are essentially transfer functions of multi-input multi-output systems. A review is found in Chapter 13 of [7].

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˜ ) reduces to transpose conjugation H†(e jω) on the unit circle. A explained in Section 6.1. Note that H(z filter bank in which E(z) is paraunitary and R(z) = E˜(z)enjoys the PR property xˆ(n) = cx(n), c ≠ 0. We often say that the analysis filter pair {Ga(z), Ha(z)} is paraunitary instead of saying that the corresponding polyphase matrix is paraunitary. The paraunitary property has played a fundamental role in electrical network theory [1, 21], and has a rich history (see references in Chapters 6 and 14 of [7]). Essentially, the scattering matrices of lossless (LC) multiports are paraunitary, i.e., unitary on the imaginary axis of the s-plane. Properties of Paraunitary Filter Banks Define the matrices Ga(z) and Ha(z) as follows: Ga ( z ) Ga (z ) =  H ( z )  a

Ga (−z )   H a (−z )

 Gs ( z ) Gs (z ) =  G (−z )  s

Hs (z )   H s (−z )

(6.36)

Notice that these two matrices are fully determined by the analysis filters and synthesis filters, respectively. ˜ )R(z) = 0.5I and R(z ˜ )R(z) = 0.5I, it can If E(z) and R(z) are paraunitary with E˜(z)E(z) = 0.5I and R(z be shown that ˜ ( z )G ( z ) = I G a a

˜ ( z )G ( z ) = I G s s

(6.37)

In other words, the matrices Ga(z) and Gs(z) defined previously are paraunitary as well. ˜ (z) = I is also Half-Band Property and Power Symmetry Property. The paraunitary property Ga(z)G a equivalent to Ga(z)Ga(z) = I, which implies G˜ a ( z )Ga ( z ) + G˜ a (−z )Ga (−z ) = 1

(6.38)

In other words, Ga(z) is a power symmetric filter. A transfer function G(z) satisfying G(z) + G(–z) = 1 is called a half-band filter. The impulse response of such G(z) satisfies g(2n) = 0 for all n ≠ 0 and g(0) = 0.5. We see that the power symmetry property of Ga(z) says that G˜ a (z)G1(z) is a half-band filter. In terms of frequency response the power symmetry property of Ga(z) is equivalent to

( )

Ga e jω

2

(

+ Ga −e jω

)

2

=1

(6.39)

Imagine that Ga(z) is a real-coefficient low-pass filter so that Ga(e jω)2 has symmetry with respect to zero frequency. Then Ga(–e jω)2 is as demonstrated in Fig. 6.24, and the power symmetry property means that the two plots in the Figure add up to unity. In this figure ωp and ωs are the bandedges, and δ1 and δ2 are the peak passband ripples of Ga(e jω) (for definitions of filter specifications see [2] or [7]). Notice in particular that power symmetry of Ga(z) implies that a symmetry relation exists between the passband and stopband specifications of Ga(e jω). This is given by ωs = π – ωp, δ 22 = 1 – (1 – 2δ1)2. 1

Ga(e jω )

Ga(–e jω ) 2

2

2

(1–2δ1)

δ22

0.5π 0

ωp

ωs

π

ω

FIGURE 6.24 The magnitude responses Ga(e jω)2 and Ga(–e jω)2 for a real-coefficient power symmetric filter Ga(z). © 2003 by CRC Press LLC

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˜ (z)G (z) = I implies a relation between G (z) and Relation between Analysis Filters. The property G a a a ˜ (–z), where θ is arbitrary and N is an arbitrary odd integer. Let N = –1 Ha(z), namely Ha(z) = e jθ z N G a and θ = 0 for future simplicity. Then H a ( z ) = z −1G˜ a (−z )

(6.40)

In particular, we have Ha(e jω) = Ga(–e jω). Combining with the power symmetry property (6.39), we see that the two analysis filters are power complementary:

( )

Ga e jω

2

( )

+ H a e jω

2

=1

(6.41)

for all ω. With Ga(z)=∑nga(n)z –n and Ha(z) = ∑nha(n)z –n we can rewrite (6.40) as ha (n) = −(−1) g a (−n + 1) n

*

(6.42) ~

Relation between Analysis and Synthesis Filters. If we use the condition R(z) = E(z) in the definitions ˜ (z), from which we conclude that the synthesis filters are given of Gs(z) and Ga (z) we obtain Gs(z) = G a ˜ ˜ by Gs(z) = Ga(z) and Hs(z) = Ha(z). We can also rewrite these in the time domain; summarizing all this, we have ˜ (z ) Gs ( z ) = G˜ a ( z ), H s ( z ) = H a

g s (n) = g a* (−n), hs (n) = ha* (−n)

(6.43)

The synthesis filter cofficients are time-reversed conjugates of the analysis filters. Their frequency responses are conjugates of the analysis filter responses. In particular, Gs(e jω)= Ga(e jω) and Hs(e jω) = Ha(e jω). In view of the preceding relations, the synthesis filters have all the properties of the analysis filters. For example, Gs(e jω) is power symmetric, and the pair {Gs(e jω), Hs(e jω)} is power complementary. ˜ (–z), instead of (6.40). Finally, Hs(z) = z G s Relation to Conjugate Quadrature Filter Design. The preceding discussions indicate that in a paraun­ itary filter bank the filter Ga(z) is power symmetric, and the remaining filters are derived from Ga(z) as in (6.40) and (6.43). This is precisely the CQF solution for PR, stated at the beginning of this section. Summary of Filter Relations in a Paraunitary Filter Bank If the filter bank of Fig. 6.22(a) is paraunitary, then the polyphase matrices E(z) and R(z) (Fig. 6.23) ˜ (z)R(z) = 0.5I. Equivalently, the filter matrices G (z) and G (z) and satisfy satisfy E˜ (z)E(z) = 0.5I and R a s ˜ ˜ Ga(z)Ga(z) = I and Gs(z)Gs(z) = I. A number of properties follow from these: 1. All four filters, Ga(z), Ha(z), Gs(z), and Hs(z), are power symmetric. This property is defined, for example, by the relation (6.38). This means that the filters are spectral factors of half-band filters; for example, G˜ s(z)Gs(z) is half-band. 2. The two analysis filters are related as in (6.40), so the magnitude responses are related as |Ha(e jω)| = |Ga(–e jω)|. The synthesis filters are time-reversed conjugates of the analysis filters as shown by (6.43). In particular, Gs(e jω) = Ga∗ (e jω) and Hs(e jω) = Ha∗ (e jω). 3. The analysis filters form a power complementary pair, i.e., (6.41) holds. The same is true for the synthesis filters. 4. Any two-channel paraunitary system satisfies the CQF equations (6.32, 33) (except for delays, constant scale factors, etc.). Conversely, any CQF design is a paraunitary filter bank. 5. The design procedure for two-channel paraunitary (i.e., CQF) filter banks is as follows: design a zero-phase, low-pass, half-band filter G(z) with G(e jω) ≥ 0 and then extract a spectral factor Ga(z). That is, find Ga(z) such that G(z) = G˜ a(z)Ga(z). Then choose the remaining three filters as in (6.33), or equivalently, as in (6.34).

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Parametrization of Paraunitary Filter Banks Factorization theorems exist for matrices, which allow the expression of paraunitary matrices as a cascade L of elementary paraunitary blocks. For example, let H(z) = Σ n=0 h(n)z –n be a 2 × 2 real causal FIR transfer matrix (thus, h(n) are 2 × 2 matrices with real elements). This is paraunitary iff it can be expressed as H(z) = RN Λ(z)RN –1… R1(z)ΛzR0H0 where  cosθm Rm =  − sin θm

1 ( z ) =  0

sinθm   cos θm 

0  z −1 

α H0 =  0

0   ± α 

(6.44)

where α and θm are real. For a proof see [7]. The unitary matrix Rm is called a rotation operator or the Givens rotation. The factorization gives rise to a cascaded lattice structure that guarantees the paraunitary property structurally. This is useful in the design as well as the implementation of filter banks, as explained in [7]. Thus, if the polyphase matrix is computed using the cascaded structure, Ga(z) is guaranteed to be power symmetric, and the relation Ha(z) = z –1 G˜ a(–z) between the analysis filters automatically holds. Further results on factorizations are described in Chapter 89.

Maximally Flat Solutions ~

∆ The half-band filter G(z) = Ga(z)Ga(z) can be designed in many ways. One can choose to have equiripple designs or maximally flat designs [2]. An early technique for designing FIR maximally flat filters was proposed by Herrmann in 1971 [7]. This method gives closed form expressions for the filter coefficients and can be adapted easily for the special case of half-band filters. Moreover, the design automatically guarantees the condition G(e jω) ≥ 0, which in particular implies zero phase. The family of maximally flat half-band filters designed by Herrmann is demonstrated in Fig. 6.25. The transfer function has the form

 1 + z −1  G( z ) = z K    2 

 K + n −1  1 − z −1  2n n −z  ( )  n  2   n=0

2K K −1

∑

(6.45)

The filter has order 4K – 2. On the unit circle we find 2K zeroes, and all of these zeroes are concentrated at the point z = –1 (i.e., at ω = π). The remaining 2K – 2 zeroes are located in the z-plane such that G(z) has the half-band property described earlier (i.e., G(z) + G(– z) = 1). Section 6.13 explains that if the CQF bank is designed by starting from Herrmann’s maximally flat half-band filter, then it can be used to design continuous time wavelets with arbitrary regularity (i.e., smoothness) properties.

G(e jω ) 1

K

2K zeros

0

π

FIGURE 6.25 Maximally flat half-band filter respones with 2K zeroes at π.

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ω

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↓2

Ga(z)

Ga(z)

↓2

Ha(z)

↓2 (a)

Ga(z)

↓2

Ha(z)

↓2

↓2

Ha(z)

x(n)

↑2

Gs(z)

↑2

Hs(z)

↑2

Gs(z)

↑2

Hs(z)

↑2

Gs(z)

↑2

Hs(z)

(b)

xˆ (n)

FIGURE 6.26 Tree-structured filter banks: (a) analysis bank and (b) synthesis bank.

Tree-Structured Filter Banks The idea of splitting a signal x(n) into two subbands can be extended by splitting a subband signal further, as demonstrated in Fig. 6.26(a). In this example the low-pass subband is split repeatedly. This is called a tree-structured filter bank. Each node of the tree is a two-channel analysis filter bank. The synthesis bank corresponding to Fig. 6.26(a) is illustrated in Fig. 6.26(b). We combine the signals in pairs in the same manner that we split them. It can be demonstrated that if {Ga(z), Ha(z), Gs(z), Hs(z)} ˆ = x(n) when connected in the form Fig. 6.22(a)], then the tree-structured is a PR system [i.e., satisfies x(n) ˆ analysis/synthesis system of Fig. 6.26 has PR x(n) = x(n). The tree-structured system can be redrawn in the form shown in Fig. 6.27. For example, if we have a tree structure similar to Fig. 6.26 with three levels, we have M = 4, n0 = 2, n1 = 4, n2 = 8, and n3 = 8. If we assume that the responses of the analysis filters Ga(e jω) and Ha(e jω) are as in Fig. 6.28(a), the responses of the analysis filters Hk (e jω) are as shown in Fig. 6.28(b). Note that this resembles the wavelet transform

x(n)

H0(z)

↓n0

H1(z)

↓n1

HM−1(z)

↓nM−1

y0(n)

y1(n)

↑n0

F0(z)

↑n1

F1(z)

↑nM−1

FM−1(z)

yM−1(n)

FIGURE 6.27 A general nonuniform digital filter bank.

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xˆ (n)

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Ga

Ha

(a) ω

π/2

0

H3 H2

π

H1

H0 (b) ω

0

π/4

π/2

π

FIGURE 6.28 An example of responses: (a) Ga(z) and Ha(z), and (b) tree-structured analysis bank.

[Fig. 6.8(b)]. The outputs of different filters are subsampled at different rates exactly as for wavelets. Thus, the tree-structured filter bank bears a close relationship to the WT. Sections 6.10 to 6.13 present the precise mathematical connection between the two, and the relation to multiresolution analysis.

Filter Banks and Basis Functions ˆ Assuming PR [x(n) = x(n)], we can express x(n) as x (n) =

M −1

∞

∑ ∑ y (m)1f (4n2− n4m3) k

k = 0 m = −∞

k

k

(6.46)

ηkm ( n )

where yk(n) are the decimated subband signals, and fk(n) are the impulse response of Fk(z). Thus, the system is analogous to the filter bank systems which represented the continuous time STFT and WT in Sections 6.2 and 6.3. The collection of subband signals yk(m) can be regarded as a time-frequency representation for the sequence x(n). As before, k denotes the frequency index and m the time index in the transform domain. If we have a PR filter bank, we can recover x(n) from this time-frequency representation using (6.46). The doubly indexed family of discrete time sequences {ηkm(n)} can be regarded as “basis functions” for the representation of x(n). To make things mathematically accurate, let x(n) ∈ l2 (i.e., Σn| x(n)|2 is finite). If the two-channel filter bank {Ga(z), Ha(z), Gs(z), Hs(z)}, which makes up the tree structure of Fig. 6.26 is paraunitary, it can be shown that ηkm(n) is an orthonormal basis for l 2. Orthonormality means ∞

∑η

k1m1

(n)η*k2m2 (n) = δ(k1 − k2 )δ(m1 − m2 )

(6.47)

n=−∞

Notice that the basis functions (sequences) are not derived from a single function. Instead, they are derived from a finite number of filters {fk(n)} by time shifts of a specific form. The wavelet basis {2k/2 ψ (2kt – n)}, on the other hand, is derived from a single wavelet function ψ(t). We say that {ηkm(n)} is a filter bank type of basis for the space of l 2 sequences.

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6.5 Deeper Study of Wavelets, Filter Banks, and Short-Time Fourier Transforms We already know what the WT is and how it compares with the STFT, at least qualitatively. We are also familiar with time-frequency representations and digital filter banks. It is now time to fill in several important details, and generally be more quantitative. For example, we would like to mention some major technical limitations of the STFT which are not obvious from its definition, and explain that wavelets do not have this limitation. For example, if the STFT is used to obtain an othonormal basis for L2 signals, the time-frequency RMS durations of the window v(t) should satisfy Dt Df = ∞. That is, either the time or the frequency resolution is very poor (Theorem 6.5). Also, if we have an STFT system in which the time-frequency sampling product ωsTs is small enough to admit redundancy (i.e., the vectors are not linearly independent as they would be in an orthonormal basis), the previous difficulty can be eliminated (Section 6.9). The Gabor transform, while admittedly a tempting candidate because of the optimal time-frequency resolution property (Dt Df minimized), has a disadvantage. For example, if we want to recover the signal x(t) from the STFT coefficients, the reconstruction is unstable in the so-called critically sampled case (Section 6.9). That is, a small error in the STFT coefficients can lead to a large error in reconstruction. The WT does not suffer from the above limitations of the STFT. Sections 6.11 to 6.13 show how to construct orthonormal wavelet bases with good time and frequency resolutions. We also show that we can start from a paraunitary digital filter bank and construct orthonormal wavelet bases for L2(R) very systematically (Theorem 6.13). Moreover, this can be done in such a way that many desired properties (e.g., compact support, orthonormality, good time frequency resolution, smoothness, and so forth) can be incorporated during the construction (Section 6.13). Such a construction is placed in evidence by the theory of multires­ olution, which gives a unified platform for wavelet construction and filter banks (Theorems 6.6. and 6.7). At this point, the reader may want to preview the above-mentioned theorems in order to get a flavor of things to come. However, to explain these results quantitatively, it is very convenient to review a number of mathematical tools. The need for advanced tools arises because of the intricacies associated with basis functions for infinite dimensional spaces, i.e., spaces in which the set of basis functions is an infinite set. (For finite dimensional spaces an understanding of elementary matrix theory would have been sufficient.) For example, a representation of the form x(t) = Σ cn fn(t) in an infinite dimensional space could be unstable in the sense that a small error in the transform domain {cn} could be amplified in an unbounded manner during reconstruction. A special type of basis called the Riesz basis does not have this problem (orthonormal bases are special cases of these). Also, the so-called frames (Section 6.8) share many good properties of the Riesz bases but may have redundant vectors (i.e., not a linearly independent set of vectors). For example, the concept of frames arises in the comparison of wavelets and the STFT. General STFT frames have an advantage over STFT bases. Frames also come into consideration when the connection between wavelets and paraunitary digital filter banks is explained in Section 6.11. When describing the connection between wavelets and nonunitary filter banks, one again encounters Riesz bases and the idea of biorthogonality. Because it is difficult to find all the mathematical background material in one place, we review a carefully selected set of topics in the next few sections. These are very useful for a deeper understanding of wavelets and STFT. The material in Section 6.6 is fairly standard (Lebesgue integrals, Lp spaces, L1 and L2 FTs). The material in Sections 6.7 and 6.8 (Riesz bases and frames) are less commonly known among engineers, but play a significant role in wavelet theory. The reader may want to go through these review sections (admittedly dense), once during first reading and then use them as a reference. Following this review, we return to our discussions of wavelets, STFT, and filter banks.

6.6 The Space of L1 and L2 Signals We developed the wavelet representation in Section 6.2 based on the framework of a bank of bandpass filters. To make everything mathematically meaningful it becomes necessary to carefully specify the types

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of signals, types of FTs, etc. For example, the concept of ideal bandpass filtering is appealing to engineers, but a difficulty arises. An ideal bandpass filter H(ω) is not stable, that is, ∫ h(t)dt does not exist [2]. In other words h(t) does not belong to the space L1 (see below). Why should this matter if we are discussing theory? The frequency domain developments based on Fig. 6.2, which finally give rise to the time domain expression (6.8), implicitly rely on the convolution theorem (convolution in time implies multiplication in frequency). However, the convolution theorem is typically proved only for L1 signals and bounded L2 signals; it is not valid for arbitrary signals. Therefore, care must be exercised when using these familiar engineering notions in a mathematical discussion.

Lebesgue Integrals In most engineering discussions, we think of the integrals as Riemann integrals, but in order to handle several convergence questions in the development of Fourier series, convolution theorems, and wavelet transforms, it is necessary to use Lebesgue integration. Lebesgue integration theory has many beautiful results which are not true for the Riemann integral under comparable assumptions about signals. This includes theorems that allow us to interchange limits, integrals and infinite sums freely. All integrals in this chapter are Lebesgue integrals. A review of Lebesgue integration is beyond the scope of this chapter, although many excellent references, for example, [22], are available. A few elemen­ tary comparisons between Riemann and Lebesgue integrals are given next. 1. If x(t) is Riemann integrable on a bounded interval [a, b] then it is also Lebesgue integrable on [a, b]. The converse is not true, however. For example, if we define x(t) = –1 for a rationals and x(t) = 1 for all irrationals in [0,1] then x(t) is not Riemann integrable in [0,1], but it is Lebesgue 1 integrable, and ∫0 x(t)dt = 1. 2. A similar statement is not true for the unbounded interval (–∞,∞). For the unbounded interval (–∞,∞) the Riemann integral is defined only as a limit called the improper integral.7 Consider the sinc function defined as: s(t) = sin t/t for t ≠ 0, and s(0) = 1. This has an improper Riemann integral = π, but is not Lebesgue integrable. 3. If x(t) is Lebesgue integrable, so is x(t). The same is not true for Riemann integrals, as demon­ strated by the sinc function s(t) of the preceding paragraph. 4. If x(t) is Lebesgue integrable, so is x(t) as long as it is measurable.8 This, however, is not true for Riemann integrals. If we define x(t) = –1 for all rationals and 1 for all irrationals in [0,1], it is not Riemann integrable in [0,1] although x(t) is. 5. If x(t) is (measurable and) bounded by nonnegative Lebesgue integrable function g(t) [i.e., x(t) ≤ g(t)], then x(t) is Lebesgue integrable. Sets of Measures Zero A subset  of real numbers is said to have measure zero if, given ε > 0, we can find a countable union ∪i Ii of open intervals Ii [intervals of the form (ai, bi), i.e., ai < x < bi] such that  ⊂ ∪i Ii and the total length of the intervals < ε. For example, the set of all integers (in fact, any countable set of real numbers, e.g., rationals) has measure zero. Uncountable sets of real numbers exist that have measure zero, a famous example being the Cantor set [22]. When something is said to be true “almost everywhere” (abbreviated a.e.) or “for almost all t,” it means that the statement holds everywhere, except possibly on a set of measure zero. For example, if x(t) = y(t) Essentially, we consider ∫–a x(t)dt and let a and b go to ∞ separately. This limit, the improper Riemann integral, a should not be confused with Cauchy principal value, which is the limit of ∫–a x(t)dt as a → ∞. The function x(t) = t has Cauchy principal value = 0, but the improper Riemann integral does not exist. 8The notion of measurable function is very subtle. Any continuous function is measurable, and any Lebesgue integrable function is measurable. In fact, examples of nonmeasureable functions are so rare and so hard to construct that practically no danger exists that we will run into one. We take measurability for granted and never mention it. 7

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everywhere except for integer values of t, then x(t) = y(t) a.e. An important fact in Lebesgue integration theory is that if two Lebesgue integrable functions are equal a.e., than their integrals are equal. In particular, if x(t) = 0 a.e., the Lebesgue integral ∫x(t)dt exists and is equal to zero. Convergence Theorems What makes the Lebsegue integral so convenient is the existence of some powerful theorems which allow us to interchange limits with integrals and summations under very mild conditions. These theorems have been at the center of many beautiful results in Fourier and wavelet transform theory. Let {gk(t)}, 1 ≤ k ≤ ∞ be a sequence of Lebesgue integrable functions. In general, this sequence may not have a limit, and even if it did, the limit may not be integrable. Under some further mild postulates, we can talk about limits and their integrals. In what follows we often say “g(t) is a pointwise limit a.e. of the sequence {gk(t)}”, or “gk(t) converges to g(t) a.e.” This means that for any chosen value of t (except possibly in a set of measure zero), we have gk(t) → g(t) as k → ∞. Monotone Convergence Theorem: Suppose {gk(t)} is nondecreasing a.e. (i.e., for almost all values of t, gk(t) is nondecreasing in k) and ∫gk(t)dt is a bounded sequence. Then {gk(t)} converges a.e. to a Lebesgue integrable function g(t) and limk ∫gk (t)dt = ∫ limk gk (t)dt, i.e., limk ∫gk (t)dt = ∫g(t)dt. That is, we can interchange the limit with the integral. Dominated Convergence Theorem: Suppose {gk(t)} is dominated by a non-negative Lebesgue integrable function f(t), i.e., gk(t) ≤ f (t) a.e. and {gk(t)} converges to a limit g(t) a.e. Then the limit g(t) is Lebesgue integrable and limk ∫ gk(t)dt = ∫ limk gk(t)dt, i.e., limk ∫ gk(t)dt = ∫ g(t)dt. That is, we can interchange the limit with the integral. Levi’s Theorem: Suppose ∫Σ k=1 gk (t)dt is a bounded sequence in m. Then ∫Σ k=1 gk (t)dt = Σ k =1 ∫ gk (t)dt. ∞ This means, in particular, that Σ k=1 gk(t) converges a.e. to a Lebesgue integrable function. This theorem permits us to interchange infinite sums with the integrals. ∞

m

∞

Fatou’s Lemma: Let (a) gk(t) ≥ 0 a.e., (b) gk(t) → g(t) a.e., and (c) ∫ gk(t) dt ≤ A for some 0 < A < ∞. Then the limit g(t) is Lebesgue integrable and ∫ g(t) ≤ A. (Stronger versions of this result exist [23], but we shall not require them here.)

Lp Signals Let p be an integer such that 1 ≤ p < ∞. A signal x(t) is said to be an Lp signal if it is measurable, and if ∫ x(t)p dt exists. We define the Lp norm of x(t) as x(t)p = [∫ x(t)p dt]1/p. For fixed p, the set of Lp signals forms a vector space. It is a normed linear vector space, with norm defined previously. The term “linear” means that if x(t) and y(t) are in Lp, then αx(t) + βy(t) is also in Lp for any complex α and β. Because any two signals x(t) and y(t) that are equal a.e. cannot be distinguished (i.e., x(t) – y(t)p = 0), each element in L p is in reality “a set of functions that are equal a.e.” Each such set becomes an “equivalence 2 class” in mathematical language. For p = 2 the quantity x(t) p is equal to the energy of x(t), as defined in signal processing texts. Thus, an L2 signal is a finite-energy (or square-integrable) signal. For p = ∞ the above definitions do not make sense, and we simply define L∞ to be the space of essentially bounded signals. A signals x(t) is said to be essentially bounded if there exists a number B < ∞ such that x(t) ≤ B a.e. We often omit the term “essential” for simplicity; it arises because of the a.e. in the inequality. The norm x(t) ∞ is taken as essential supremum of x(t) over all t. That is, x(t) ∞ is the smallest number such that x(t) ≤ x(t) ∞ a.e. L1, L2, and L∞ functions are particularly interesting for engineers. Note that neither L1 nor L2 contains the other. However, bounded L1 functions are in L2, and L2 functions on bounded intervals are in L1. That is L1 ∩ L∞ ⊂ L2 and L2 [a, b] ⊂ L1 [a, b]

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(6.48)

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Thus, L2 is already bigger than bounded L1 functions. Moreover, x (t ) ∈ L1 ∩ L∞ ⇒ x (t ) ∈ Lp for all p > 1 p–1

This follows because x(t)p ≤ x(t) x(t) ∞ . Thus, x(t)p is (measurable and) bounded by a Lebesgue integrable function (because x(t) is integrable), and is therefore integrable. Orthonormal Signals in L2 The inner product 〈x(t), y(t)〉 = ∫ x(t)y ∗(t)dt always exists for any x(t) and y(t) in L2. Thus, the product of two L2 functions is an L1 function. If 〈x(t), y(t)〉 = 0 we say that x(t) and y(t) are orthogonal. Clearly, 2 x(t) 2 = 〈x(t), x(t)〉. Consider a sequence {gn(t)} of signals such that any pair of these are orthogonal, and gn(t)2 = 1 for all n. This is said to be an orthonormal sequence. The following two results are fundamental. Theorem 6.1: Let {gn (t)}, 1 ≤ n ≤ ∞ be an orthonormal sequence in L2. Define cn = 〈x(t), gn(t)〉 for some x(t) ∈ L2. Then the sum Σn cn2 converges, and Σn cn2 ≤ x(t)2. Theorem 6.2 (Riesz-Fischer Theorem): Let {gn(t)}, 1 ≤ n ≤ ∞ be an orthonormal sequence in L2 and let {cn} be a sequence of complex numbers such that Σn cn2 converges. Then there exists x(t) ∈ L2 such that cn = 〈x(t), gn(t)〉, and x(t) = Σn cngn(t) (with equality interpreted in the L2 sense; see below). The space L2 is more convenient to work with than L1. For example, inner product and the concept of orthonormality are undefined in L1. Moreover (see following section), the FT in L2 has more timefrequency symmetry than in L1. In Section 6.7 we will define unconditional bases, which have the property that any rearrangement continues to be a basis. It turns out that any orthonormal basis in L2 is unconditional, whereas the L1 space does not even have an unconditional basis. Equality and Convergence in Lp Sense Let x(t) and y(t) be LP functions (p < ∞). Then x(t) – y(t)p = 0 iff x(t) = y(t) a.e. For example, if x(t) and y(t) differ only for every rational t we still have x(t) – y(t)p = 0. Whenever x(t) – y(t)p = 0, we say that x(t) = y(t) in Lp sense. Now consider a statement of the form x (t ) =

∞

∑ c g (t ) n n

(6.49)

n =1

for p < ∞, where gn(t) and x(t) are in L p. This means that the sum converges to x(t) in the L p sense; that N is, x(t) – Σn=1 cn gn(t)p goes to zero as N → ∞. If we modify the limit x(t) by adding some number to N x(t) for all rational t, the result is still a limit of Σn=1 cn gn(t) in the L p sense. L p limits are unique only p the a.e. sense. We omit the phrase “in the L sense” whenever it is clear from the context. lp Spaces Let p be an integer with 1 ≤ p ≤ ∞. The collection of all sequences x(n) such that Σnx(n)p converges to a finite value is denoted l p. This is a linear space with norm x(n)p defined so that x(n)p = (Σnx(n)p)1/p. Unlike L p spaces, l p spaces satisfy the following inclusion rule: l1 ⊂ l 2 ⊂ l 3 Kl ∞

(6.50)

The spaces l1 and l2 are especially interesting in circuits and signal processing. If h(n) ∈ l1, Σnh(n) < ∞. This is precisely the condition for the BIBO (bounded-input–bounded-output) stability of a linear time invariant system with impulse response h(n) [2].

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Continuity of Inner Products If {xn(t)} is a sequence in L2 and has an L2 limit x(t), then for any y(t) ∈ L2, lim x n (t ), y (t ) = lim x n (t ), y (t ) = x (t ), y (t )

n→∞

n→∞

(6.51)

with the second limit interpreted in the L2 sense. Thus, limits can be interchanged with inner product signs. Similarly, infinite summation signs can be interchanged with the inner product sign, that is, ∞ ∞ Σn=1 〈αnx n (t), y(t)〉 = 〈 Σn=1 αnx n (t), y(t)〉, provided the second summation is regarded as an L2 limit. These follow from the fundamental property that inner products are continuous [23]. Next, suppose {xn(t)} is a sequence of functions Lp for some integer p ≥ 1, and suppose xn(t) → x(t) in the L p sense. Then  xn(t) p → x(t) p as well. We can rephrase this as lim x n (t ) = lim x n (t ) = x (t ) p

n→∞

n→∞

p

p

(6.52)

Thus, the limit sign can be interchanged with the norm sign, where the limit in the second expression is in the L p sense. This follows because x n (t ) − x (t ) p

p

≤ x n (t ) − x (t ) → 0 as n → ∞ p

Fourier Transforms The Fourier transform is defined for L1 and L2 signals in different ways. The properties of these two types of FT are significantly different. In the signal processing literature, in which we ultimately seek engineering solutions (such as filter approximation with rational transfer functions), this distinction often is not necessary. However, when we try to establish that a certain set of signals is a basis for a certain class, we must be careful, especially if we use tools such as the FT, convolution theorem, etc. (as we implicitly did in Section 6.2). Detailed references for this section include [15, 22, and 23]. L1 Fourier Transform Given a signal x(t) ∈ L1, its FT X (ω) (the L1 FT) is defined in a manner that is familiar to engineers: X (ω ) =

∞

∫ x(t )e −∞

− jωt

dt

(6.53)

The existence of this integral is assured by the fact that x(t) is in L1.9 In fact, the preceding integral exists iff x(t) ∈ L1. The L1 FT has the following properties: 1. X(ω) is a continuous function of ω. 2. X(ω) → 0 as ω → ∞. This is called the Riemann–Lebesgue lemma. 3. X(ω) is bounded, and x(ω) ≤ x(t)1. In engineering applications, we often draw the ideal low-pass filter response (F(ω) in Fig. 6.3) and consider it to be the FT of the impulse response f (t), but this frequency response is discontinuous and already violates property 1. This is because f (t) is not in L1 and F(ω) is not the L1-FT of f (t). That f (t) is not in L1 is consistent with the fact that the ideal filter is not BIBO stable (i.e., a bounded input may not produce bounded output because ∫ f (t)dt is not finite).

9Because x(t) is Lebesgue integrable (hence, measurable), the product x(t)e –jωt is measurable, and it is bounded by the integrable function x(t). Thus, x(t)e –jωt is integrable.

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Inverse Fourier Transform. The FT X(ω) of an L1 signal generally is not in L1. For example, if x(t) is the rectangular pulse, then X(ω) is the sinc function which is not absolutely integrable. Thus, the familiar inverse transform formula x (t ) =

1 2π

∫

∞ −∞

X (ω )e jωt dω

(6.54)

does not make sense in general. However, because X(ω) is continuous and bounded, it is integrable on c any bounded interval, so ∫–c X(ω)e jωtdω/2π exists for any finite c. This quantity may even have a limit as c → ∞, even if the Lebesgue integral or improper Rieman integral, does not exist. Such a limit (the Cauchy principal value) does represent the original function x(t) under some conditions. Two such cases are outlined next. Case 1. Thus, suppose x(t) ∈ L1 and suppose that is of bounded variation in an interval [a, b]; that is, it can be expressed as the difference of two nondecreasing functions [22]. Then, we can show that the above Cauchy principal value exists, and x (t + ) + x (t − ) 1 = lim c→∞ 2π 2

c

∫ X (ω)e −c

jωt

dω

(6.55)

for every t ∈ (a, b). The notations x(t –) and x(t +) are the left-hand limit and the right-hand limit respectively, of x(·) at t; for functions of bounded variation, these limits can be shown to exist. If x(·) is continuous at t, then x(t –) = x(t +) = x(t), and above reduces to the familiar inversion formula. ∆ ∞ Case 2. Suppose now that x(t) ∈ L1 and X(ω) ∈ L1 as well. Then, the integral y(t) = ∫–∞ X(ω)e jωtdω/2π exists as a Lebesgue integral, and y(t) = x(t) a.e. [23]. In particular, if x(·) is continuous at t, x(t) = ∞ ∫–∞ X(ω)e jωtdω/2π. If x(t) and X(ω) are both in L1 they are both in L2 as well. This is shown as follows: because x(t) ∈L1 implies that X (ω) is bounded. We see that X(ω) ∈ L1 ∩ L∞. So X(ω) ∈ Lp for all integer p (See previous section). In particular, X(ω) ∈ L2, so x(t) ∈ L2 as well (by Parseval’s relation; see below). The L2 Fourier Transform The L1 Fourier transform lacks the convenient property of time-frequency symmetry. For example, even though x(t) is in L1 , X(ω) may not in L1. Also, even though x(t) may not be continuous, X(ω) is necessarily continuous. The space L2 is much easier to work with. Not only can we talk about inner products and orthonormal bases, perfect symmetry also exists between time and frequency domains. We must define L2-FT differently because the usual definition (6.53) is meaningful only for L1 signals. Suppose x(t) ∈ L2 and we truncate it to the interval [–n, n]. This truncated version is in L1 because of (6.48), and its L1 FT exists: X n (ω ) =

n

∫ x(t )e

− jωt

−n

dt



(6.56)

It can be shown that Xn(ω) is in L2 and that the sequence {Xn(ω)} has a limit in L2. That is, there exists an L2 function X(ω) such that lim X n (ω ) − X (ω ) = 0

n→∞

2

(6.57)

This limit X(ω) is defined to be the L2 FT of x(t). Some of the properties are listed next: 1. X(ω) is in L2, and we can compute x(t) from X(ω) in an entirely analogous manner, namely the n L2 limit of ∫ –n X(ω)e jωtdω/2π. 2. If x(t) is in L1 and L2, then the above computation gives the same answer as the L1-FT (6.53) a.e. For example, consider the rectangular pulse x(t) = 1 in [–1, 1] and zero otherwise. This is in L1 © 2003 by CRC Press LLC

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The Circuits and Filters Handbook, Second Edition

and L2 , and the FT using either definition is X(ω) = 2sinω/ω. This answer is in L2, but not in L1. The inverse L2-FT of X(ω) is the original x(t). ∞ If x(ω) ∈ L2 and x(ω) ∈ L1 then the Lebesgue integral ∫ –∞ X(ω)e jωtdω/2π exists, and equals x(t) a.e. Parseval’s relation holds, i.e., 2π x(t)2 = X(ω)2. Thus, the FT is a linear transformation from L2 to L2, which preserves norms except the scale factor 2π. (Note that this would not make sense if x(t) were only in L1.) In particular, it is a bounded transformation because the norm X(ω)2 in the transform domain is bounded by the norm x(t)2 in the original domain. Unlike the L1-FT, the L2-FT X(ω) need not be continuous. For example, the impulse response of an ideal low-pass filter (sinc function) is in L2 and its FT is not continuous. Let {fn(t)} be a sequence in L2 and let x(t) = Σn cn fn(t) be a convergent summation (in the L2 sense). With upper case letters denoting the L2-FTs, x(w) = Σn cn Fn(ω). This result is obvious for finite summations because of the linearity of the FT. For infinite summations, this follows from the property that the L2-FT is a continuous mapping from L2 to L2. (This in turn follows from the result that it is a bounded linear transformation). The continuity allows us to move the FT operation inside the infinite summation.

Thus, complete symmetry exists between the time and frequency domains. The L2-FT is a one-to-one mapping from L2 onto L2. Moreover, because 2π x(t)2 = X(ω)2, it is a norm preserving mapping — one says that the L2 -FT is an isometry from L2 to L2. l1 Fourier Transform If a sequence x(n) ∈ l 1 its discrete-time FT X(e jω) = Σn x(n)e –jωn exists, and is the l1-FT of x(n). It can be demonstrated that X(e jω) is a continuous function of ω and that X(e jω) is bounded.

Convolutions Suppose h(t) ∈L1 and h(t) ∈L p for some p in 1 ≤ p ≤ ∞. The familiar convolution integral defined by (x ∗ h)(t) = ∫x(τ)h(t – τ)dτ exists for almost all t [23]. If we define a function y(t) to be x ∗ h where it exists and to be zero elsewhere, the result is, in fact, an Lp function. We simply say that the convolution of an L1, function with an Lp function gives an Lp function. By recalling that an LTI system is stable (i.e., BIBO stable), iff its impulse response is in L1, we have the following examples: 1. If an L1 signal is input to a stable LTI system, the output is in L1. Because the convolution of two L1 signals is in L1, the cascade of two stable LTI systems is stable, a readily accepted fact in engineering. 2. If an L2 signal (finite energy input) is input to a stable LTI system, the output is in L2. 3. If an L∞ signal is input to a stable LTI system, the output is in L∞ (i.e., bounded inputs produce bounded outputs). If x(t) and h(t) are both in L1, their convolution y(t) is in L1, and all three signals have L1-FT. The convolution theorem [23] says that theses three are related as Y(ω) = H(ω) X(ω). When signals are not necessarily in L1 we cannot in general write this, even if convolution might itself be well defined. Convolution Theorems for L2 Signals For all our discussions in the preceding sections, the signals were restricted to be in L2, but not necessarily in L1. In fact, even the filters are often only in L2. For example, ideal bandpass filters (Fig. 6.8) are unstable, and therefore only in L2. For arbitary L2 signals x(t) and h(t), the convolution theorem does not hold. We therefore need to better understand L2 convolution. Assume that x(t) and h(t) are both in L2. Their convolution y(t) = ∫x(τ)h(t – τ)dτ exists for all t, as the integral is only an inner product in L2. Using Schwartz inequality [23], we also have y(t) ≤ x(t)2 h(t)2, that is, y(t) ∈ L∞. Suppose the filter h(t) has the further property that the frequency response H(ω) is bounded, i.e., H(ω) ≤ B a.e., for some B < ∞. Then we can show that y(t) ∈ L2, and that the convolution theorem holds (Y(ω) = H(ω)X(ω)). To prove this, note that © 2003 by CRC Press LLC

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y (t ) = x (τ)h(t − τ)dτ =

∫

1 2π

∫ X (ω)H (ω)e

jωt

dω

(6.58)

from Parseval’s relation which holds for L2 signals [23]. If H(ω) ≤ B, then X(ω)H(ω)2 ≤ B2X(ω)2. Therefore, X(ω)H(ω)2 is bounded by the integrable function X(ω)2, and is therefore integrable. Thus, X(ω)H(ω) ∈ L2, and the preceding equation establishes that y(t) ∈ L2. The equation also shows that y(t) and H(ω)X(ω) form an L2 -FT pair, so Y(ω) = H(ω)X(ω). Bounded L2 Filters Filters for which h(t) ∈ L2 and H(ω) bounded are called bounded L2 filters. The preceding discussion shows that bounded L2 filters admit the convolution theorem, although arbitrary L2 filters do not. Another advantage of bounded L2 filters is that a cascade of two bounded L2 filters, h1(t) and h2(t), is a bounded L2 filter, just as a cascade of two stable filters would be stable. To see this, note that the cascaded impulse response is the convolution h(t) = (h1 ∗ h2)(t). By the preceding discussion, h(t) ∈ L2, and moreover, H(ω) = H1(ω)H2(ω). Clearly, H(ω) is still bounded. Bounded L2 filters are therefore very convenient to work with. Fortunately, all filters in the discussion of wavelets and filter banks are bounded L2 filters, even though they may not be BIBO stable (as are the ideal bandpass filters in Fig. 6.8). We summarize the preceding discussions as follows. Theorem 6.3 (Convolution of L2 functions): We say that h(t) is a bounded L2 filter if h(t) ∈ L2 and H(ω) ≤ B < ∞ a.e. 1. Let x(t) ∈ L2 and let h(t) be a bounded L2 filter. Then y(t) = (x ∗ h)(t) exists for all t and y(t) ∈ L2. Moreover, Y(ω) = H(ω)X(ω). 2. If h1(t) and h2(t) are bounded L2 filters, then their cascade h(t) = (h1 ∗ h2)(t) is a bounded L2 filter and H(ω) = H1(ω)H2(ω).

6.7 Riesz Basis, Biorthogonality, and Other Fine Points In a finite dimensional space, such as the space of all N-component Euclidean vectors, the ideas of basis and orthonormal basis are easy to appreciate. When we extend these ideas to infinite dimensional spaces (i.e., where the basis {gn(t)} has infinite number of functions), a number of complications and subtleties arise. Our aim is to point these out. References for this section include [5, 15, and 24]. Readers familiar Hilbert spaces will note that the L2 space is a Hilbert space; all our developments here are valid for any Hilbert space . Elements in  (vectors) are typically denoted x, y, etc. When we deal with Hilbert space L2, the vectors are functions and are denoted as x(t), y(t), etc. for clarity. Similarly, for the special case of Euclidean vectors we use boldface, e.g., x, y, etc. The reader not familiar with Hilbert spaces can assume that all discussions are in L2 and that x is merely a simplification of the notation x(t).

Finite Dimensional Vector Spaces We first look at the finite dimensional case and then proceed to the infinite dimensional case. Consider an N x N matrix F = [f1 f2 … fN]. We assume that this is nonsingular, that is, the columns fn are linearly independent. These column vectors form a basis for the N-dimensional Euclidean space N of complex N-component vectors. This space is an example of a finite dimensional Hilbert space, with inner product defined as 〈x,y〉 = y†x = Σ Nn =1 xn xn*. The norm x induced by this inner product is defined as x 〈 x, x〉 . Thus, x2 = x†x = Σ Nn=1 xn 2. Any vector x ∈N can be expressed as x = Σ Nn=1 cn fn for some uniquely determined set of scalars cn . We can abbreviate this as x = Fc, where c = [c1 c2…cN]T. The matrix F can be regarded as a linear transformation from N to N. The nonsingularity of F means that for every x ∈ N we can find a unique c such that x = Fc.

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Boundedness of F and Its Inverse In practice, we have further requirement that if the norm c is “small” then x should also be “small”, and vice versa. This requirement implies, for example, that if a small error occurs in the transmission or estimate of the vector c, the corresponding error in x is also small. From the relation x = Fc we obtain 2

x = x † x = c †F†Fc

(6.59)

Letting λM and λm denote the maximum and minimum eigenvalues of F † F, it then follows that x2 ≥ λm c2 and that x2 ≤ λM c2. That is, 2

2

λm c ≤ x ≤ λ M c

2

(6.60)

with 0 < λm ≤ λM < ∞, where 0 < λm follows from the nonsingularity of F. Thus, the transformation F, which converts c into x, has an amplification factor bounded by λM in the sense that x2 ≤ λM c2. Similarly, the inverse transformation G = F – 1, which converts x into c, has amplification bounded by 1/λm . Because λM is finite, we say that F is a bounded linear transformation, and because λm ≠ 0, we see that the inverse transformation is also bounded. Using x = Σn cn fn and c2 = Σncn2 we can rewrite the preceding inequality as A

∑c

2 n

n

≤

∑c f

2

n n

≤B

n

∑c

2 n

(6.61)

n

where A = λm > 0 and B = λM < ∞, and all summations are for 1 ≤ n ≤ N. Readers familiar with the idea of a Riesz basis in infinite dimensional Hilbert spaces will notice that the above is in the form that agrees with that definition. We will return to this issue later. Biorthogonality With F –1 denoted as G, let g n† denote the rows of G: g1†    g †  2 G =   , F = f1 f2 … fN M     † g N 

[

]

(6.62)

The property GF = I implies g †k fn = δ(k − n): fn , g k = δ(k − n)

(6.63)

for 1 ≤ k, n ≤ N. Equivalently, 〈gk fn〉 = δ(k – n). Two sets of vectors, {fn} and {gk}, satisfying (6.63) are said to be biorthogonal. Because c = F–1 x = Gx we can write the elements of c as cn = gn† x = 〈x, gn 〉. Then x = Σncnfn = Σn〈x,gn〉fn . Next, G† is a nonsingular matrix, therefore, we can use its columns gn, instead of the columns of F, to obtain a similar development, and express the arbitrary vector x ∈N as x = Σn〈x, fn 〉gn . Summarizing, we have x=

∑ x, g n

n

fn =

∑ x, f

n

gn

(6.64)

n

where the summations are for 1 ≤ n ≤ N. By using the expressions cn = 〈x, gn 〉 and x = Σn cnfn , we can rearrange the inequality (6.61) into B–1 x2 ≤ Σn 〈x, gn〉2 ≤ A–1x2. With the columns gn of G†, instead of the columns of F, used as the basis for N, we obtain similarly © 2003 by CRC Press LLC

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2

Ax ≤

∑ x, f

2 n

≤Bx

2

(6.65)

n

where 1 ≤ n ≤ N, and A = λm, B = λM again. Readers familiar with the idea of a frame in an infinite dimensional Hilbert space will recognize that the above inequality defines a frame {fn}. Orthonormality The basis fn is said to be orthonormal if 〈fk , fn〉 = δ(k – n), i.e., fn†fk = δ(k – n). Equivalently, F is unitary, i.e., F † F = I. In this case the rows of the inverse matrix G are the quantities fn†. But F † F = I, and we have λm = λM = 1 or A = B = 1. With this, (6.60) becomes c = x, or Σncn2 = Σn cn fn2. This shows that equation (6.61) is a generalization of the orthonormal situation. Similarly, biorthogonality (6.63) is a generalization of orthonormality. Basis in Infinite Dimensional Spaces When the simple idea of a basis in a finite dimensional space (e.g., the Euclidean space N) is extended to infinite dimensions, several new issues arise which make the problem nontrivial. Consider the sequence of functions {fn }, 1 ≤ n ≤ ∞ in a Hilbert space . Because of the infinite range of n, linear combinations of the form Σ∞n=1 cn fn must now be considered. The problem that immediately arises is one of conver­ gence. For arbitrary sequences cn this sum does not converge, so the statement “all linear combinations” must be replaced with something else.10 Closure of Span First define the set of all finite linear of the form ΣNn=1 cn fn, where N varies over all integers ≥1. This is called the span of { fn}. Now suppose x ∈  is a vector not necessarily in the span of { fn}, but can be approximated as closely as we wish by vectors in the span. In other words, given an ε > 0 we can find N and the sequence of constants cnN such that N

x−

∑c

f 0, there exists n0 such that N

x−

∑c f

n n

0 in (6.61). For our basis {fn}, we can indeed show that no A > 0 satisfies (6.61). To see this let cn = 0 for all n, except that ck = 1. Then, Σn cn fn = fk = ek /k and has norm 1/k. So (6.61) reads A ≤ ▫ 1/k2 ≤ B for all k ≥ 1. This is not possible with A > 0. If {en}, 1 ≤ n ≤ ∞ is an orthonormal basis in an infinite dimensional Hilbert space , then any vector ∞ x ∈  can be expressed uniquely as x = Σ n=1 cnen where 12As we make ε increasingly smaller, we may need to change N and all coefficients c . Therefore, this does not kN imply fm = n ≠m cn fn for fixed {cn}.

Σ

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∞

2

x =

∑c

2 n

n =1

This property automatically ensures the stability of the transformations from x to {cn} and vice versa. The Riesz basis is defined such that this property is made more general.1 Definition of a Riesz Basis. A sequence { fn}, 1 ≤ n ≤ ∞ in a Hilbert space  is a Riesz basis if it is complete and constants A and B exist such that 0 < A ≤ B < ∞ and ∞

A

∑ n =1

2

cn ≤

∞

∑ n =1

2

c n fn ≤ B

∞

∑c

2 n

(6.69)

n =1

for all choice of cn satisfying Σncn2 < ∞. In a finite dimensional Hilbert space, A and B come from the extreme eigenvalues of a nonsingular matrix F†F, so automatically A > 0 and B < ∞. In other words, any basis in a finite dimensional space is a Riesz basis. As Example 2 shows, this may not be the case in infinite dimensions. Unconditional Basis It can be shown that the Riesz basis is an unconditional basis, that is, any reordering of { fn} is also a basis (and the new cn are the correspondingly reordered versions). This is a nontrivial statement; an arbitrary (Schauder) basis is not necessarily unconditional. In fact, the space of L1 functions (which is a Banach space, not a Hilbert space) does not have an unconditional basis. Role of the Constants A and B 1. Strongest linear independence. The condition A > 0 means, in particular, that Σn cn fn ≠ 0 unless cn is zero for all n. This is just ω-independence. Actually the condition A > 0 means that the vectors { fn} are independent in the strongest sense (type 3), that is, { fn} is minimal. To see this, assume this is not the case by supposing some vector fm is in the closure of the span of the others. Then, given arbitrary ε > 0 we can find N and cnN satisfying (6.66) with x = fm . Defining cn = –cnN for n ≠ m and cm = 1, (6.69) implies A(1 + Σ n≠mcnN2) ≤ ε2. Because ε is arbitrary, this is not possible for A > 0. 2. Distance between vectors. The condition A > 0 also implies that no two vectors in { fn} can become “arbitrarily close”. To see this, choose ck = –cm = 1 for some k, m and cn = 0 for all other n. Then (6.69) gives 2A ≤ fk – fm2 ≤ 2B. Thus, the distance between any two vectors is at least 2A, at most 2B. 3. Bounded basis. A Riesz basis is a bounded basis in the sense that  fn  cannot get arbitrarily large. In fact, by choosing cn = 0 for all but one value of n, we can see that 0 < A ≤ fn2 ≤ B < ∞. That is, the norms of the vectors in the basis cannot become arbitrarily small or large. Note that the basis in Example 2 violates this, because  fn  = 1/n. Therefore, Example 2 is only a Schauder basis and not a Riesz basis. 4. Stability of basis. The condition A > 0 yields Σncn2 ≤ A–1x2, where x = Σn cn fn. This means that the transformation from the vector x to the sequence {cn} is bounded, so a small error in x is not amplified in an unbounded manner. Similarly, the inequality x2 ≤ B Σn cn2 shows that role of B is to ensure that the inverse transformation from cn to x is bounded. Summarizing, the trans­ formation from x to {cn} is numerically stable (i.e., small errors not severely amplified) because A > 0, and the reconstruction of x from {cn} is numerically stable because B < ∞.

1For readers familiar with bounded linear transformations in Hilbert spaces, we state that a basis is a Riesz basis iff it is related on an orthonormal basis via a bounded linear transformation with bounded inverse.

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5. Orthonormality. For a Riesz basis with A = B = 1 the condition (6.69) reduces to Σn cn2 =  Σn cn fn2. It can be shown that such a Riesz is as simply an orthonormal basis. The properties listed above show that the Riesz basis is as good as orthonormal basis in most applications. Any Riesz basis can be obtained from an orthonormal basis by means of a bounded linear transformation with a bounded linear inverse. Example 3, Mishaps with a System That Is Not a Riesz Basis. Let us modify Example 2 to fn = (en/n) + e1, n ≥ 1, where {en} is an orthonormal basis. As n → ∞ the vectors fn move arbitrarily closer together (although  fn  approaches unity from above). Formally, fn – fm = (en/n) – (em/m), so  fn – fm  2 = (1/n2) + (1/m2), which goes to zero as n, m → ∞. Thus there does not exist A > 0 satisfying (6.69) (because of comment 2 above). This, then, is not a Riesz basis; in fact, this is not even a Schauder basis (see below). This example also has B = ∞. To see this let cn = 1/n, then Σn cn2 converges, but Σ Nn=1 cn fn2 does not converge as N → ∞ (as we can verify), so (6.69) is not satisfied for finite B. Such mishaps cannot occur with a Riesz basis. In this example, { fn} is not minimal (which is type 3 independence). Note that  f1 – fn  gets arbitrarily small as n increases to infinity, therefore, f1is in the closure of the span of { fn}, n ≠ 1. However, { fn} is ω-independent; no sequence {cn} exists such that  ΣNn=1 cn fn  → 0 as N → ∞. In any case, the fact that { fn} is not minimal (i.e., not independent in the strongest sense) shows that it is not even a Schauder basis.

Biorthogonal Systems, Riesz Bases, and Inner Products When discussing finite dimensional Hilbert spaces, we found that given a basis fn (columns of a nons­ ingular matrix) we can express any vector x as a linear combination x = Σn 〈x, gn 〉fn , where gn is such that the biorthogonality property 〈fm , gn 〉 = δ(m – n) holds. A similar result is true for infinite dimensional Hilbert spaces. Theorem 6.4, Biorthogonality and Riesz Basis: Let {fn} be a basis in a Hilbert space . Then, there exists a unique sequence {gn} biorthogonal to {fn}, that is, fm , g n = δ(m − n)

(biorthogonality)

(6.70)

Moreover, the unique expansion of any x ∈  in terms of the basis {fn} is given by ∞

x=

∑ x, g

n

fn

(6.71)

n =1

It is also true that the biorthogonal sequence {gn}is a basis and that x = Σ∞n=1 〈x, fn 〉gn . Moreover, if {fn} is a Riesz basis, then Σ n〈x, gn 〉2 and Σ n 〈x, fn 〉2 are finite, and we have 2

Ax ≤

∞

∑ x, f

2 n

≤B x

2

(6.72)

n =1

where A and B are the same constants as in the definition (6.69) of a Riesz basis.

▫

This beautiful result resembles the finite dimensional version, where fn corresponds to the column of a matrix and gn corresponds to the rows (conjugated) of the inverse matrix. In this sense we can regard the biorthogonal pair of sequences {fn}, {gn} as inverses of each other. Both are bases for . A proof of the above result can be obtained by combining the ideas on pp. 28 to 32 of [24]. The theorem implies, in particular, that if {fn}is a Riesz basis, then any vector in the space can be written in the form Σ∞n=1 cn fn , where cn ∈l 2.

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Summary of Riesz Basis The Riesz basis {fn} in a Hilbert space is a complete set of vectors, linearly independent in the strongest sense (i.e., type 3 or minimal). It is a bounded basis with bounded inverse. Any two vectors are separated by at least 2A, that is,  fn – fm 2 ≥ 2A. The norm of each basis vector is bounded as  fn ≤ B. In the expression x = ∑n c n fn the computation of x from cn as well as the computation of cn from x are numer­ ically stable because B < ∞ and A > 0, respectively. A Riesz basis with A = B = 1 is an orthonormal basis. In fact, any Riesz basis can be obtained from an orthonormal basis via a bounded linear transformation with a bounded inverse. Given any basis {fn} in a Hilbert space, a unique biorthogonal sequence {gn} exists such that we can express any x ∈  as x = Σ n∞=1 〈x, gn 〉 fn as well as x = Σ ∞n=1 〈x, fn 〉gn ; if this basis is also a Riesz basis, then Σ n 〈x, fn 〉2 and Σ n 〈x, gn 〉2 are finite. If {fn} is a Riesz basis, then any vector x ∈ can be written in the form x = Σ∞n=1 cn fn, where cn ∈ l 2.

6.8 Frames in Hilbert Spaces A frame in a Hilbert space  is a sequence of vectors {fn} with certain special properties. While a frame is not necessarily a basis, it shares some properties of a basis. For example, we can express any vector x ∈ as a linear combination of the frame elements, i.e., x = Σn cn fn . However, frames generally have redundancy — the frame vectors are not necessarily linearly independent, even in the weakest sense defined in Section 6.7. The Riesz basis (hence, any orthonormal basis) is a special case of frames. The concept of a frame is useful when discussing the relation between wavelets, STFTs, and filter banks. Frames were introduced by Duffin and Schaeffer [25], and used in the context of wavelets and STFT by Daubechies [5]. Excellent tutorials can be found in [12] and [24].

Definition of a Frame A sequence of vectors {fn} in a (possibly infinite dimensional) Hilbert space x ∈ is a frame if there exist constants A and B with 0 < A ≤ B < ∞ such that for any x ∈ we have 2

Ax ≤

∞

∑ x, f

2 n

≤Bx

2

(6.73)

n=1

The constants A and B are called frame bounds. In Section 6.7, we saw that a Riesz basis, which by definition satisfies (6.69) and also satisfies (6.72), which is precisely the frame definition. A Riesz basis is, therefore, also a frame, but it is a special case of a frame, where the set of vectors is minimal. Any frame is complete. That is, if a vector x ∈ is orthogonal to all elements in { fn}, then x = 0, otherwise A > 0 is violated. Thus, any x ∈ is in the closure of the span of the frame. In fact, we will see that more is true; for example, we can express x = Σ cn fn, although {cn} may not be unique. The frame elements are not necessarily linearly independent, as demonstrated by examples below. A frame, then, is not necessarily a basis. Compare (6.73) with the Riesz basis definition (6.69), where the left inequality forced the vectors fn to be linearly independent (in fact, minimal). The left inequality for a frame only ensures completeness, not linear independence.

Representing Arbitrary Vectors in Terms of Frame Elements We will see that, given a frame { fn} we can associate with it another sequence {gn} called the dual frame, ∞ ∞ such that any element x ∈ can be represented as x = Σ n=1 〈x, gn 〉fn . We also can write x = Σ n =1 〈x, fn 〉gn . This representation in terms of { fn} and {gn} resembles the biorthogonal system discussed in Section 6.7, but some differences are pointed out later.

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x

Linear transform

x, gn = cn

Stable, because A > 0 ∞

x = ∑ cnfn n=1

cn =

Linear transform

x, gn

x

Stable because B < ∞

FIGURE 6.29 Representation of x using frame elements {fn }. The transformation from x to {cn} and vice versa are stable.

Stability of Computations To obtain the representation x = Σ n=1 〈x, fn 〉gn we compute (at least conceptually) the coefficients 〈x, fn 〉 for all n. This computation is a linear transformation from  to the space of sequences. The inverse ∞ transform computes x from this sequence by using the formula x = Σ n=1 〈x, fn 〉gn . The condition B < ∞ in the frame definition ensures that the transformation from x to 〈x, fn 〉 is bounded. Similarly, the condition A > 0 ensures that the inverse transformation, from 〈x, fn 〉 to x is bounded. The conditions A > 0 and B < ∞, therefore, ensure stability; small errors in one domain are not arbitrarily amplified in the other domain. A similar advantage was pointed out earlier for the Riesz basis — for arbitrary bases in infinite dimensional spaces such an advantage cannot be claimed (Example 4). ∞ ∞ If we wish to use the dual representation x = Σ n=1 〈x, gn 〉fn instead of x = Σ n=1 〈x, fn 〉gn , we must compute 〈x, gn 〉, etc.; the roles of A and B are taken up by 1/B and 1/A, respectively, and similar discussions hold. This is summarized in Fig. 6.29. ∞

Exact Frames, Tight Frames, Riesz Bases, and Orthonormal Bases The resemblance between a Riesz basis and a frame is striking. Compare (6.69) with (6.73). One might wonder what the precise relation is. Thus far, we know that a Riesz basis is a frame. To go deeper, we need a definition: a frame { fn} which ceases to be a frame if any element fk is deleted is said to be an exact frame. Such a frame has no redundancy. A frame with A = B is said to be a tight frame. The defining property reduces to x2 = A–1 Σn〈x, fn〉2, resembling Parseval’s theorem for an orthonormal basis. A frame is normalized if  fn = 1 for all n. The following facts concerning exact frames and tight frames are fundamental: 1. A tight frame with A = B = 1 and  fn  = 1 for all n (i.e., a normalized tight frame with frame bound = 1) is an orthonormal basis [5]. 2. {fn} is an exact frame iff it is a Riesz basis [24]. Moreover, if a frame is not exact then it cannot be a basis [12]. Thus, if a frame is a basis, it is certainly a Riesz basis. 3. Because an orthonormal basis is a Riesz basis, a normalized tight frame with frame bound equal to 1 is automatically an exact frame. Some examples follow that serve to clarify the preceding concepts and definitions. In these examples, the sequence {en}, n ≥ 1 is an orthonormal basis for . Thus, {en} is a tight frame with A = B = 1, and en = 1. Example 4. Let fn = en/n as in Example 2. Then { fn} is still a (Schauder) basis for , but it is not a frame. In fact, this satisfies (6.73) only with A = 0; i.e., the inverse transformation (reconstruction) from 〈x, fn 〉 to x is not bounded. To see why A = 0, note that if we let x = ek for some k > 0 then x = 1, whereas Σn 〈x, fn 〉2 = 1/k2. The first inequality in the frame definition becomes A ≤ 1/k2, which cannot be satisfied for all k unless A = 0. In this example a finite B works because 〈x, fn 〉 = 〈x, en 〉/n for each n. Therefore, ▫ Σn 〈x, fn 〉2 ≤ Σn 〈x, en 〉2 = x2.

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Example 5. Suppose we modify the above example as follows: define fn = (en/n) + e1. We know that this is no longer a basis (Example 3). We now have B = ∞ in the frame definition, so this is not a frame. To verify this, let x = e1 so x = 1. Then 〈x, fn 〉 = 1 for all n > 1, so Σ n 〈x, fn 〉2 does not converge to a finite value. ▫ Example 6. Consider the sequence of vectors {e1, e1, e2, e2, …}. This is a tight frame with frame bounds A = B = 2. Note that, even though the vectors are normalized and the frame is tight, this is not an orthonormal basis. This has a redundancy of two in the sense that each vector is repeated twice. This frame is not even a basis, therefore, it is not a Riesz basis. ▫ Example 7. Consider the sequence of vectors {e1,(e2/ 2), (e2/ 2), (e3/ 3), (e3/ 3), (e3/ 3), …}. Again, redundancy occurs, so it is not a basis. It is a tight frame with A = B = 1, but not an exact frame, and clearly not a basis. It has redundancy (repeated vectors). ▫ Frame Bounds and Redundancy For a tight frame with unit norm vectors fn , the frame bound measures the redundancy. In Example 6 the redundancy is two (every vector repeated twice), and indeed A = B = 2. In Example 7, where we still have redundancy, the frame bound A = B = 1 does not indicate it. The frame bound of a tight frame measures redundancy only if the vectors fn have unit norm as in Example 6.

Frame Operator, Dual Frame, and Biorthogonality The frame operator  associated with a frame { fn} in a Hilbert space  is a linear operator defined as ∞

x =

∑ x, f

n

fn

(6.74)

n=1

The summation can be shown to be convergent by using the definition of the frame. The frame operator  takes a vector x ∈ and produces another vector in . The norm of  x is bounded as follows: A x ≤ x ≤ B x

(6.75)

The frame operator is a bounded linear operator (because B < ∞; hence, it is a continuous operator [12]. Its inverse is also a bounded linear operator because A > 0). From (6.74) we obtain 〈x, x〉 = Σn〈x, fn 〉2 by interchanging the inner product with the infinite summation. This is permitted by the continuity of the operator  and the continuity of inner products (see Section 6.6). Because {fn} is complete, the right-hand side is positive for x ≠ 0. Thus, 〈 x, x〉 > 0 unless x = 0, that is,  is a positive definite operator. The realness of 〈 x, x〉 also means that  is selfadjoint, or 〈x, y〉 = 〈x, y〉 for any x, y ∈. The importance of the frame operator arises from the fact that if we define gn = 1fn, any x ∈ can be expressed as ∞

x=

∑ n =1

∞

x , g n fn =

∑ x, f

n

gn

(6.76)

n =1

The sequence {gn} is itself a frame in  called the dual frame. It has frame bounds B –1 and A–1. Among all representations of the form x = Σn cn fn , the representation x = Σn〈x, gn 〉fn possesses the special property that the energy of the coefficients is minimized, i.e., Σ n〈x, gn 〉2 ≤ Σncn 2 with equality iff cn = 〈x, gn 〉 for all n [12]. As argued earlier, the computation of 〈x, fn 〉 from x and the inverse computation of x from 〈x, fn〉 are numerically stable operations because B < ∞ and A > 0, respectively.

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For the special case of a tight frame (A = B), the frame operator is particularly simple. We have x = Ax, and so gn =  –1 fn = fn/A. Any vector x ∈ can be expressed as x=

1 A

∞

∑ x, f

n

fn

(tight frames)

(6.77)

n=1

Notice also that (6.73) gives ∞

∑ x, f

2 n

=Ax

2

(tight frames)

(6.78)

n=1

For a tight frame with A = 1, these equations resemble the representation of x using an orthonormal basis, even though such a tight frame is not necessarily a basis because of possible redundancy (Example 7). Exact Frames and Biorthogonality For the special case of an exact frame (i.e., a Riesz basis) the sequence {fn} is minimal, and it is biorthogonal to the dual frame sequence {gn}. This is consistent with our observation at the end of Section 6.7. Summary of Frames A sequence of vectors {fn} in a Hilbert space  is a frame if there exist constants A > 0 and B < ∞ such that (6.73) holds for every vector x ∈. Frames are complete (because A > 0), but not necessarily linearly independent. The constants A and B are called the frame bounds. A frame is tight if A = B. A tight frame with A = B = 1 and with normalized vectors ( fn  = 1) is an orthonormal basis. For a tight frame with  fn  = 1, the frame bound A measures redundancy. Any vector x ∈ can be expressed in either of the two ways shown in (6.76). Here, gn =  –1 fn, where  is the frame operator defined in (6.74). The frame operator is a bounded linear operator and is self-adjoint (in fact, positive). The sequence {gn} is the dual frame and has frame bounds B –1 and A–1. For a tight frame the frame representation reduces to (6.77). A frame is exact if deletion of any vector fm destroys the frame property. A sequence {fn} is an exact frame iff it is a Riesz basis. An exact frame {fn} is biorthogonal to the dual frame {gn}. Figure 6.30 is a Venn diagram, which shows the classification of frames and bases and the relationship between these.

6.9 Short-Time Fourier Transform: Invertibility, Orthonormality, and Localization In Section 6.8, we saw that a vector x in an infinite dimensional Hilbert space (e.g., a function x(t) in ∞ L2) can be expanded in terms of a sequence of vectors {fn} called a frame, that is x = Σ t=1〈x, gn 〉fn . One of the most important features of frames is that the construction of the expansion coefficients 〈x, gn 〉 from x as well as the reconstruction of x from these coefficients are numerically stable operations because A > 0 and B < ∞ (see Section 6.8). Riesz and orthonormal bases, which are special cases of a frame (Fig. 6.30), also share this numerical stability. In Section 6.3, we attempted to represent an L2 function in terms of the short time Fourier transform (STFT). The STFT coefficients are constructed using the integral (6.24). Denote for simplicity

(

)

g kn (t ) = v ∗ t − nTs e jk ωst

(6.79)

The computation of the STFT coefficients can be written as X STFT (kω s , nTs ) = x (t ), g kn (t )

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(6.80)

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Wavelet Transforms

Frames Tight frames (A = B)

Exact frames ≡ Riesz bases Orthonormal bases ≡ Normalized tight frames with A = 1

Bases

FIGURE 6.30 A Venn diagram showing the relation between frames and bases in a Hilbert space.

This is a linear transformation which converts x(t) into a two-dimensional sequence because k and n are integers. Our hope is to be able to reconstruct x(t) using an inverse linear transformation (inverse STFT) of the form x (t ) =

∞

∞

∑∑ X

STFT

(kω s ,nTs ) fkn (t )

(6.81)

k=−∞ n=−∞

We know that this can be done in a numerically stable manner if {gkn(t)} is a frame in L2 and {fkn(t)} is the dual frame. The fundamental questions, then, are under what conditions does {gkn(t)} constitute a frame? Under what further conditions does this become a Riesz basis, better still, an orthonormal basis? With such conditions, what are the time-frequency localization properties of the resulting STFT? The answers depend on the window v(t) and the sample spacings ωs and Ts. We first construct a very simple example which shows the existence of orthonormal STFT bases, and indicate a fundamental disadvantage in the example. We then state the answers to the above general questions without proof. Details can be found in [5, 12, and 16]. Example 8, Orthonormal Short-Time Fourier Transform Basis. Suppose v(t) is the rectangular window shown in Fig. 6.31, applied to an L2 function x(t). The product x(t)v(t) therefore has finite duration. If v(t)

v(t−1) x(t)

0

FIGURE 6.31 The rectangular window in STFT. © 2003 by CRC Press LLC

1

t

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we sample its FT at the rate ωs = 2π we can recover x(t)v(t) from these samples (this is like a Fourier series of the finite duration waveform x(t)v(t)). Shifting the window by successive integers (i.e., Ts = 1), we can in this way recover successive pieces of x(t) from the STFT, with sample spacing ωs = 2π in the frequency domain. Thus, the choice Ts = 1 and ωs = 2π (so, ωsTs = 2π) leads to an STFT XSTFT(kωs , nTs), from which we can reconstruct x(t) for all t. The quantity gkn(t) becomes g kn (t ) = v (t − n)e jkω st = v (t − n)e j 2πkt

(6.82)

Because the successive shifts of the window do not overlap, the functions gkn(t) are orthonormal for different values of n. The functions are also orthonormal for different values of k. Summarizing, the rectangular window of Fig. 6.31, with the time-frequency sampling durations Ts = 1 and ωs = 2π, produces ▫ an orthonormal STFT basis for L2 functions. This example is reminiscent of the Nyquist sampling theorem in the sense that we can reconstruct x(t) from (time-frequency) samples, but the differences is that x(t) is an and L2 signal, not necessarily bandlimited. Note that Ts and ωs cannot be arbitrarily interchanged (even if ωsTs = 2π is preserved). Thus, if we had chosen Ts = 2 and ωs = π (preserving the product ωsTs) we would not have obtained a basis because two successive positions of the window would be spaced too far apart and we would miss 50% of the signal x(t).

Time-Frequency Sampling Density for Frames and Orthonormal Bases Let us assume that v(t) is normalized to have unit energy, i.e., ∫v(t)2 dt = 1 so that  gkn(t) = 1 for all k, n. If we impose the condition that gkn(t) be a frame, then it can be shown that the frame bounds satisfy the condition A≤

2π ≤B ω sTs

(6.83)

regardless of how v(t) is chosen. As an orthonormal basis is a tight frame with A = B = 1, an STFT orthonormal basis must therefore have ωs Ts = 2π. It can further be shown that if ωSTS > 2π, {gkn(t)} cannot be a frame. For ωsTs < 2π, we can find frames (but not orthonormal basis) by appropriate choice of window v(t). The critical time-frequency sampling density is (ωsTs)−1 = (2π)−1. If the density is smaller we cannot have frames, and if it is larger we cannot have orthonormal basis, only frames. Orthonormal Short-Time Fourier Transform Bases have Poor Time-Frequency Localization If we wish to have an orthonormal STFT basis, the time-frequency density is constrained so that ωsTs = 2π. Under this condition suppose we choose v(t) appropriately to design such a basis. The time-frequency localization properties of this system can be judged by computing the mean square durations Dt2 and Df2 defined in (6.27) It has been shown by Balian and Low [5, 16] that one of these is necessarily infinite no matter how v(t) is designed. Thus, an orthonormal STFT basis always satisfies Dt Df = ∞. That is, either the time localization or the frequency resolution is very poor. This is summarized in the following theorem. Theorem 6.5: Let the window v(t) be such that {gkn(t)} in (6.79) is an orthonormal basis for L2 (which means, in particular, that ωsTs = 2π). Define the RMS durations Dt and Df for the window v(t) as usual (6.27). Then, either Dt = ∞ or Df = ∞. Return now to Example 8, where we constructed an orthonormal STFT basis using the rectangular window of Fig. 6.31. Here, Ts = 1 and ωs = 2π so that ωsTs = 2π. The window v(t) has finite mean square

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ωs ωsTs > 2π; no frames possible

ωsTs < 2π. Good tight

frames possible

ωsTs = 2π; necessary condition for orthonormality. Orthonormality implies DtDf = ∞, so poor time-frequency localization.

Ts

FIGURE 6.32 Behavior of STFT representation for various regions of time-frequency sampling product ωs Ts. The curve ωs Ts = 2π is critical; see text.

duration Dt2. Its FT V (ω) has magnitude V(ω) = sin(ω/2)/(ω/2) so that ∫ω2V(ω)2 dω is not finite. This demonstrates the result of Theorem 6.5. One can try to replace the window v(t) with something for which Dt Df is finite, but this cannot be done without violating orthonormality. Instability of the Gabor Transform Gabor constructed the STFT using the Gaussian window v(t) = ce –t2/2. In this case the sequence of functions {gkn(t)} can be shown to be complete in L2 (in the sense defined in Section 6.7) as long as ωsTs ≤ 2π. However, if ωsTs = 2π the system is not a frame because it can be shown that A = 0 in (6.73). Thus, the reconstruction of x(t) from XSTFT (kωs , nTs) is unstable if ωs Ts = 2π (see Section 6.8), even though {gkn(t)} is complete. Although the Gabor transform has the ideal time frequency localization (minimum Dt Df ), it cannot provide a stable basis; hence, it is certainly not an orthonormal basis, whenever ωs Ts = 2π. Because orthonormal STFT basis is not possible if ωs Ts ≠ 2π, this shows that an orthonormal basis can never be achieved with the Gabor transform (Gaussian windowed STFT), no matter how we choose ωs and Ts. The Gabor example also demonstrates the fact that even if we successfully construct a complete set of functions (not necessarily a basis) to represent x (t), it may not be useful because of the instability of reconstruction. If we construct Riesz bases (e.g., orthonormal bases) or more generally frames, this disadvantage disappears. For example, with the Gabor transform if we let ωs Ts < 2π then all is well. We obtain a frame (so A > 0 and B < ∞ in (6.73)); we have stable reconstruction and good time frequency localization, but not orthonormality. Figure 6.32 summarizes these results pertaining to the time-fre­ quency product ωsTs in the STFT. A major advantage of the WT over the STFT is that it is free from the above difficulties. For example, we can obtain an orthonormal basis for L2 with excellent time-frequency localization (finite, controllable Dt Df ). We will also see how to constrain such a wavelet ψ (t) to have the additional property of regularity or smoothness. Regularity is a property which is measured by the continuity and differentiability of ψ(t). More precisely, it is quantified by the Hölder index (defined in Section 6.13). In the next few sections where we construct wavelets based on paraunitary filter banks, we will see how to achieve all this systematically.

6.10 Wavelets and Multiresolution Section 6.11 to 6.13 show how to construct compactly supported wavelets systematically to obtain orthonormal bases for L2. The construction is such that excellent time-frequency localization is possible. Moreover, the smoothness or regularity of the wavelets can be controlled. The construction is based on the two-channel paraunitary filter bank described in Section 6.4. In that section, we denoted the synthesis filters as Gs(z) and Hs(z), with impulse response gs(n) and hs(n), respectively.

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All constructions are based on obtaining the wavelet ψ(t) and an auxiliary function φ (t), called the scaling function, from the impulse response sequences gs (n) and hs (n). We do this by using time domain recursions of the form φ(t ) = 2

∞

∑

g s (n)φ(2t − n)

ψ (t ) = 2

∞

∑ h (n)φ(2t − n)

(6.84)

s

n=−∞

n=−∞

called dilation equations. Equivalently, in the frequency domain

(

)

(

Φ(ω ) = Gs e jω 2 Φ(ω 2)

)

Ψ(ω ) = H s e jω 2 Φ(ω 2)

(6.85)

If {Gs(z), Hs(z)} is a paraunitary pair with further mild conditions (e.g., that the low-pass filter Gs(e jω) has a zero at π and no zeroes in [0, π/3]) the preceding recursions can be solved to obtain ψ (t), which gives rise to an orthonormal wavelet basis {2k/2 ψ(2kt – n)} for L2. By constraining Gs (e jω) to have a sufficient number of zeroes at π we can further control the Hölder index (or regularity) of ψ (t) (see Section 6.13). Our immediate aim is to explain the occurrence of the function φ(t), and the curious recursions (6.84) called the dilation equations or two-scale equations. These have origin in the beautiful theory of multiresolution for L2 spaces [4, 11]. Because multiresolution theory lays the foundation for the construction of the most practical wavelets to date, we give a brief description of it here.

The Idea of Multiresolution Return to Fig. 6.13(a), where we interpreted the wavelet transformation as a bank of continuous time analysis filters followed by samples, and the inverse transformation as a bank of synthesis filters. Assume for simplicity the filters are ideal bandpass. Figure 6.13(b) is a sketch of the frequency responses. The bandpass filters Fk (ω) = 2− k/2 ψ(ω / 2k ) become increasingly narrow as k decreases (i.e., as k becomes more and more negative). Instead of letting k be negative, suppose we keep only k ≥ 0 and include a low-pass filter Φ(ω) to cover the low frequency region. Then, we get the picture of Fig. 6.33. This is analogous to Fig. 6.12, where we used the pulse function φ (t) instead of using negative k in ψ(2k t − n). Imagine for a moment that Φ (ω) is an ideal low-pass filter with cutoff ± π. Then we can represent ∞ any L2 function F(ω) with support restricted to ±π in the form F(ω) = Σ n=–∞ anΦ(ω)e –jωn. This is simply the FS expansion of F (ω) in [−π, π], and it follows that Σ n an2 < ∞ (Theorem 6.1). In the time domain, this means f (t ) =

∞

∑ a φ(t − n)

(6.86)

n

n=−∞

Fk(ω) = 2−k/2 Ψ(2−kω)

Ψ(ω) = F0(ω) F1(ω)

F2(ω)

1 −8π

−4π

−2π

0

π

2π

4π

8π

ω

1 Φ(ω) −π

0

π

ω

FIGURE 6.33 The low-pass function Φ(ω), bandpass function Ψ(ω), and stretched bandpass filters Fk(ω). © 2003 by CRC Press LLC

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Wavelet Transforms

V3 V2 V1 V0 W0 0 π

2π

W1

W2 4π

ω

8π

FIGURE 6.34 Toward multiresolution analysis. The spaces {Vk } and {Wk } spanned by various filter responses.

Let us denote by V0 the closure of the span of {φ (t − n)}. Thus, V0 is the class of L2 signals that are bandlimited to [−π, π]. Because φ(t) is the sinc function, the shifted functions {φ(t − n)} form an orthonormal basis for V0. . The bandpass Consider now the subspace W0 ⊂ L2 of bandpass functions band-limited to π < |ω| ≤ 2π sampling theorem (Section 6.2) allows us to reconstruct such a bandpass signal g (t) from its samples g (n) by using the ideal filter Ψ(ω). Denoting the impulse response of Ψ(ω) by ψ(t) we see that {ψ(t – n)} spans W0. It can be verified that {ψ (t − n)} is an orthonormal basis for W0. Moreover, as Ψ(ω) and Φ(ω) do not overlap, it follows from Parseval’s theorem that W0 is orthogonal to V0. Next, consider the space of all signals of the form f (t ) + g (t ), where f (t ) ∈V0 and g (t ) ∈W0. This space is called the direct sum (in this case, orthogonal sum) of V0 and W0, and is denoted as V1 = V0 ⊕ W0. It is the space of all L2 signals band-limited to [−2π, 2π]. We can continue in this manner and define the spaces Vk and Wk for all k. Then, Vk is the space of all L2 signals band-limited to [−2k π, 2k π], and Wk is the space of L2 functions band-limited to 2k π < ω ≤ 2k+1 π. The general recursive relation is Vk+1 = Vk ⊕ Wk. Figure 6.34 demonstrates this for the case in which the filters are ideal bandpass. Only the positive half of the frequency axis is shown for simplicity. It is clear that we could imagine V0 itself to be composed of subspaces V–1 and W–1. Thus, V0 = V–1 ⊕ W–1, V–1 = V–2 ⊕ W–2, and so forth. In this way, we have defined a sequence of spaces {Vk} and {Wk} for all integers k such that the following conditions are true: Vk+1 = Vk ⊕Wk

Wk ⊥Wm ,

k ≠ m

(6.87)

where ⊥ means “orthogonal”, i.e., the functions in Wk are orthogonal to those in Wm. It is clear that Vk ⊂ Vk+1. We will see later that even if the ideal filters Φ(ω) and Ψ(ω) are replaced with nonideal approximations, we can sometimes define sequences of subspaces Vk and Wk satisfying the above conditions. The impor­ tance of this observation is that whenever Ψ (ω) and Φ (ω) are such that we can construct such a subspace structure, the impulse response ψ(t) of the filter Ψ(ω) can be used to generate an orthonormal wavelet basis. Although this might appear to be too complicated and convoluted, we will see that the construction of the function φ(t) is quite simple and elegant, and simplifies the construction of orthonormal wavelet bases. A realization of these ideas based on paraunitary filter banks is presented in Section 6.11. It is now time to be more precise with definitions as well as statements of the results.

Definition of Multiresolution Analysis Consider a sequence of closed subspaces {Vk} in L2, satisfying the following six properties: 1. Ladder property. ⋅⋅⋅ V–2 ⊂ V–1 ⊂ V0 ⊂ V1 ⊂ V2 ⋅⋅⋅. ∞ 2. I Vk = {0}. k=–∞ ∞ 3. Closure of U Vk is equal to L2. k=–∞ 4. Scaling property. x (t) ∈ Vk iff x(2t) ∈ Vk+1. Because this implies “x(t) ∈ V0 iff x(2k t) ∈ Vk”, all

the spaces Vk are scaled versions of the space V0. For k > 0, Vk is a finer space than V0.

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5. Translation invariance. If x(t) ∈ V0, then x(t – n) ∈ V0; that is, the space V0 is invariant to

translations by integers. By the previous property, this means that Vk is invariant to transla­ tions by 2–k n. 6. Special orthonormal basis. A function φ (t) ∈ V0 exists such that the integer shifted versions {φ (t – n)} form an orthonormal basis for V0. Employing property 4, this means that {2k/2φ (2k t – n)} is an orthonormal basis for Vk. The function φ (t) is called the scaling function of multiresolution analysis. ▫ Comments on the Definition

Notice that the scaling function φ (t) determines V0, hence all Vk. We say that φ (t) generates the entire multiresolution analysis {Vk}. The sequence {Vk} is said to be a ladder of subspaces because of the inclusion property Vk ⊂ Vk+1. The technical terms closed and closure, which originate from metric space theory, have simple meanings in our context because L2 is a Hilbert space. Thus, the subspace Vk is “closed” if the following is true: whenever a sequence of functions {fn (t)} ∈ Vk converges to a limit f (t) ∈ L2 (i.e.,  f (t) – fn (t) → 0 as n → ∞), the limit f (t) is in Vk itself. In general, an infinite union of closed sets is not closed, which is why we need to take “closure” in the third property on page 187. The third property simply means that any element x (t) L2 can be ∞ approximated arbitrary closely (in the L2 norm sense) by an element in U k=−∞ Vk . General Meaning of Wk In the general setting of the previous definition, the subspace Wk is defined as the orthogonal complement of Vk with respect to Vk+1. Thus, the relation Vk+1 = Vk ⊕ Wk, which was valid in the ideal bandpass case (Fig. 6.34), continues to hold. Haar Multiresolution

A simple example of multiresolution in which Φ(ω) is not ideal low-pass is the Haar multiresolution, generated by the function φ(t) in Fig. 6.35(a). Here, V0 is the space of all functions that are piecewise constants on intervals of the form [n, n + 1]. We will see later that the function ψ(t) associated with this example is as in Fig. 6.35(b) — the space W0 is spanned by {ψ (t – n)}. The space Vk contains functions that are constants in [2–k n, 2–k (n+1)]. Figure 6.35(c) and (d) show examples of functions belonging to V0 and V1. For this example, the six properties in the definition of multires­ olution are particularly clear (except perhaps property 3, which also can be proved). 1

φ(t), the scaling function

(a) 0 1 (b)

1 0

t

1

Ψ(t) t

A function in V0 (c) t

(d)

A function in V1 t

FIGURE 6.35 The Harr multiresolution example. (a) The scaling function φ(t) that generates multiresolution, (b) the function ψ(t) that generates W0, (c) example of a member of V0, and (d) example of a member of V1. © 2003 by CRC Press LLC

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Wavelet Transforms

The multiresolution analysis generated by the ideal bandpass filters (Fig. 6.33 and 6.34) is another simple example, in which φ (t) is the sinc function. We see that the two elementary orthonormal wavelet examples (Haar wavelet and the ideal bandpass wavelet) also generate a corresponding multiresolution analysis. The connection between wavelets and multiresolution is deeper than this, and is elaborated in the following section. Derivation of the Dilation Equation Because { 2φ(2t − n)} is an orthonormal basis for V1 (see property 6), and because φ(t) ∈V0 ⊂ V1, φ(t) can be expressed as a linear combination of the functions { 2φ(2t − n)}: φ(t ) = 2

∞

∑ g (n)φ(2t − n) s

(dilation equation)

(6.88)

n=−∞

Thus, the dilation equation arises naturally out of the multiresolution condition. For example, the Haar scaling function φ(t) satisfies the dilation equation φ(t ) = φ(2t ) + φ(2t −1)

(6.89)

The notation gs (n) and the factor 2 in the dilation equation might appear arbitrary now, but are convenient for future use. Orthonormality of {φ(t – n)} implies that φ(t) = 1, and that { 2φ(2t − n)} are orthonormal. Therefore, Σn gs (n)2 = 0.5 from (6.88). Example 9, Nonorthonormal Multiresolution. Consider the triangular function shown in Fig. 6.36(a). This has φ(t)= 1 and satisfies the dilation equation φ(t ) = φ(2t ) + 0.5φ(2t − 1) + 0.5φ(2t +1)

(6.90)

as demonstrated in Fig. 6.36(b). With Vk denoting the closure of the span of {2k/2 φ(2kt – n)} it can be shown that the spaces {Vk} satisfy all the conditions in the multiresolution definition, except one. Namely, {φ (t – n)} does not form an orthonormal basis [for example, compare φ (t) and φ (t – 1)]. We will see later (Example 10) that it does form a Riesz basis and that it can be converted into an orthonormal basis by orthonormalization. This example is a special case of a family of scaling functions called spline functions [15]. ▫ We will see below that starting from an orthonormal multiresolution system [in particular from the function φ(t)] one can generate an orthonormal wavelet basis for L2. The wavelet bases generated φ(t)

√3/2

t

−1

φ(2t+1)

(a)

1 φ(2t)

−1 −0.5

√3/2

φ(2t−1)

(b) t

0

0.5

1

FIGURE 6.36 Example of a scaling function φ(t) generating nonorthogonal multiresolution. (a) The scaling func­ tion, and (b) demonstrating the dilation equation. © 2003 by CRC Press LLC

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from splines φ(t) after orthonormalization are called spline wavelets [15]. These are also called the Battle–Lemarié family of wavelets. The link between multiresolution analysis and wavelets is explained quantitatively in the following section, “Relation between Multiresolution and Wavelets.” Multiresolution Approximation of L2 Functions ∞

Given a multiresolution analysis, we know that I k=−∞ Vk = {0} and that the closure of From this it can be shown that the Wk make up the entire L2 space, that is L2 =

∞

U k=−∞ Vk = L2 .

∞

⊕W

(6.91a)

k

k=−∞

We can approximate an arbitrary L2 function x(t) to a certain degree of accuracy by projecting it onto Vk for appropriate k. Thus, let xk(t) be this orthogonal projection (see Section 6.2). Suppose we increase k to k + 1. Because Vk+1 = Vk ⊕ Wk and Wk is orthogonal to Vk, we see that the new approximation xk+1(t) (projection onto the finer space Vk+1) is given by xk+1(t) = xk(t) + yk(t), where yk(t) is in Wk . Thus, when we go from scale k to scale k+1 we go to a larger space Vk+1 ⊃ Vk , which permits a

finer approximation. This is nicely demonstrated in the two extreme examples mentioned previ­ ously. For the example with ideal filters (Figs. 6.33, 6.34), the process of passing from scale k to k+1 is like admitting higher frequency components, which are orthogonal to the existing low-pass components. For the Haar example (Fig. 6.35) where ψ(t) and φ(t) are square pulses, when we pass from k to k+1 we permit finer pulses (i.e., highly localized finer variations in the time domain). For this example, Figs. 6.35(c) and (d) demonstrate the projections xk(t) and xk+1(t) at two successive resolutions. The projections are piecewise-constant approximations of an L2 signal x (t). By repeated application of Vk+1 = Vk ⊕ Wk, we can express V0 as −1

V0 =

⊕W

(6.91b)

k

k=−∞

which, together with (6.91a), yields L2 = V0 ⊕W0 ⊕W1 ⊕W2 ⊕L

(6.91c)

This has a nice interpretation based on Fig. 6.34. The L2 signal x(t) has been decomposed into orthogonal components belonging to V0 (low-pass component), W0 (bandpass component), W1 (bandpass with higher bandwidth and center frequency), etc. We can find an infinite number of multiresolution examples by choosing φ(t) appropriately. It is more important now to obtain systematic techniques for constructing such examples. The quality of the example is governed by the quality of ψ(t) and φ(t) — the time localization and frequency resolution they can provide, the smoothness (regularity) of these functions, and the ease with which we can implement these approximations.

Relation between Multiresolution and Wavelets Suppose φ(t ) ∈L2 generates an orthonormal multiresolution {Vk}, as defined in the previous section. We know φ(t ) ∈V0 and that {φ(t – n)} is an orthonormal basis for V0 . Moreover, φ(t ) satisfies the dilation equation (6.88), and the sequence {g s (n)} ∈l 2 defines the filter Gs(e jω). Now consider the finer space V1 = V0  W0, where W0 is orthonormal to V0 . If f (t ) ∈W0 then f (t) ∈V1, so it is a linear combination of 2 φ(2t – n) (property 6; see definitions). Using this and the fact that W0 is orthogonal to V0 , we can show that F(ω) [the L2-FT of f (t )] has a special form. This is given by

(

)

( )

F (ω ) = e jω 2Gs* −e jω 2 Φ(ω 2)H e jω

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where H (e jω ) is 2π-periodic. The special case of this with H (e jω ) = 1 is denoted Ψ(ω); that is,

(

Ψ(ω ) = e jω 2Gs* −e jω

2

)Φ(ω 2)

(6.92)

[dilation equation for ψ (t )]

(6.93)

The above definition of Ψ(ω) is equivalent to ψ (t ) = 2

∞

∑ (−1)

g s∗ (−n − 1)φ(2t − n)

n+1

n=−∞

The function ψ(t) satisfying this equation has some useful properties. First, it is in L2. This follows from 2 Theorem 6.2 (Riesz–Fisher Theorem), because ∑n g s (n) is finite. It can be shown that ψ(t − n) ∈W0 and that {ψ(t − n)} is an orthonormal basis for W0. This implies that {2k/2 ψ(2k t − n)} is an orthonormal basis for Wk because f (t ) ∈W0 iff f (2kt) ∈Wk , which is a property induced by the scaling property (property 4 in the definition of multiresolution). In view of (6.91) we conclude that the sequence {2k/2 ψ(2k t − n)}, with k and n varying over all integers, forms a basis for L2 . Summarizing we have the following result: Theorem 6.6 (Multiresolution and Wavelets): Let φ (t ) ∈L2 generate an orthonormal multiresolution, i.e., a ladder of spaces {Vk} satisfying the six properties in the definition of multiresolution; {φ(t – n)} is an orthonormal basis for V0. Then, φ(t) satisfies the dilation equation (6.88) for some gs (n) with Σn gs(n)2 = 0.5. Define the function ψ(t) according to the dilation equation (6.93). Then, ψ(t) ∈W0 ⊂ L2, and {ψ(t – n)} is an orthonormal basis for W0. Therefore, {2k/2 ψ(2k t – n)} is an orthonormal basis for Wk , just as {2k/2 φ(2k t – n)} is an orthonormal basis for Vk (for fixed k). Morever, with k and n varying over all integers, ▫ the doubly indexed sequence {2k/2 ψ(2k t – n)} is an orthonormal wavelet basis for L2. Thus to construct a wavelet basis for L2 we have only to construct an orthonormal basis {φ (t − n)} for V0. Everything else follows from that. All proofs can be found in [5, 11, and 15].

Relation between Multiresolution Analysis and Paraunitary Filter Banks Denoting hs (n) = (−1)

n+1

g s∗ (−1 − n),

( )

( )

i.e., H s e jω = e jωGs∗ −e

jω

we see that φ(t) and ψ(t) satisfy the two dilation equations in (6.84). By construction, ψ(t) ∈W0 and φ(t) ∈V0. The fact that W0 and V0 are mutually orthogonal subspaces can be used to show that Hs(e jω) and Gx(e jω) satisfy Gs∗ (e jω )H s (e jω ) + Gs∗ (−e jω )H s (−e jω ) = 0

(6.94)

Also, orthonormality of {φ (t − n)} leads to the power complementary property Gs (e jω ) + Gs (−e jω ) = 1 2

2

(6.95) 2

In other words, Gs (e jω ) is a power symmetric filter. That is, the filter Gs (e jω ) is a half-band filter. Using Hs(e jω) = e jω G s∗ (–e jω), we also have

( )

H s e jω

© 2003 by CRC Press LLC

2

(

+ H s −e jω

)

2

=1

(6.96)

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A compact way to express the above three equations is by defining the matrix

( )

Gs e

jω

( ) ( )

Gs e jω =  jω Gs −e 

( ) ( )

H s e jω    jω H s −e  

The three properties (6.94) to (6.96) are equivalent to G †s (e jω )G s (e jω ) = I; i.e., the matrix G s (e jω ) is unitary for all ω. This matrix was defined in Section 6.4 in the context of paraunitary digital filter banks. Thus, the filters Gs(e jω) and Hs(e jω) constructed from a multiresolution setup constitute a paraunitary (CQF) synthesis bank. Thus, orthonormal multiresolution automatically gives rise to paraunitary filter banks. Starting from a multiresolution analysis we obtained two functions φ(t) and ψ(t). These functions generate orthonormal bases {φ(t − n)} and {ψ(t − n)} for the orthogonal subspaces V0 and W0. The functions φ(t) and ψ(t) gen­ erated in this way satisfy the dilation equation (6.84). Defining the filters Gs (z) and H s (z) from the coefficients gs(n) and hs(n) in an obvious way, we find that these filters form a paraunitary pair. This raises the following fundamental question: If we start from a paraunitary pair {Gs (z), H s (z)} and define the functions φ(t) and ψ(t) by (successfully) solving the dilation equations, do we obtain an orthonormal basis {φ(t − n)} for multiresolution, and a wavelet basis {2k/2 ψ(2k t − n)} for the space of L2 functions? The answer, fortunately, is in the affirmative, subject to some minor requirements which can be trivially satisfied in practice. Generating Wavelet and Multiresolution Coefficients from Paraunitary Filter Banks Recall that the subspaces V0 and W0 have the orthonormal bases {φ(t – n)} and {ψ(t – n)}, respectively. By the scaling property, the subspace Vk has the orthonormal basis {φkn (t)}, and similarly the subspace Wk has the orthonormal basis {ψkn(t)}, where, as usual, φkn(t) = 2k/2 φ(2k t – n) and ψkn(t) = 2k/2 ψ(2k t – n). The orthogonal projections of a signal x(t) ∈L2 onto Vk and Wk are given, respectively, by ∞

[ ] ∑ x(t ), φ (t ) φ (t )

Pk x (t ) =

kn

kn

and

n=−∞

(6.97)

∞

[ ] ∑ x(t ), ψ (t ) ψ (t )

Qk x (t ) =

kn

kn

n=−∞

(see Section 6.2). Denote the scale-k projection coefficients as dk(n) = 〈x(t), φkn(t)〉 and ck(n) = 〈x(t), ψkn(t)〉 for simplicity. (The notation ckn was used in earlier sections, but ck(n) is convenient for the present discussion.) We say that dk(n) are the multiresolution coefficients at scale k and ck(n) are the wavelet coefficients at scale k. Assume that the projection coefficients dk(n) are known for some scale, e.g., k = 0. We will show that dk(n) and ck(n) for the coarser scales, i.e., k = –1, –2, . . . can be generated by using a paraunitary analysis filter bank {Ga (e jω)), H a (e jω )}, corresponding to the synthesis bank {Gs (e jω ), H s (e jω )} (Section 6.4). We know φ(t ) and ψ(t ) satisfy the dialtion equations (6.84). By substituting the dilation equations into the right-hand sides of φkn (t ) = 2k/2 φ(2k t − n) and ψ kn (t ) = 2k/2 ψ(2k t − n), we obtain φkn (t ) = 2

∞

∑ g (m − 2n)φ s

k+1,m

(t )

m=−∞

ψ kn (t ) = 2

© 2003 by CRC Press LLC

(6.98)

∞

∑ h (m − 2n)φ s

m=−∞

and

k+1,m

(t )

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Wavelet Transforms

dk+1(n) Multiresolution coeff. at level k+1

√2ga(n)

↓2

√2ha(n)

↓2

dk(n) Multiresolution coeff. at level k ck(n)

Wavelet coeff. at level k

FIGURE 6.37 Generating the wavelet and multiresolution coefficients at level k from level k + 1.

A computation of the inner products dk (n) = x(t ), φkn (t ) and c k (n) = x(t ), ψ kn (t ) yields ∞

∑

dk (n) =

2 g a (2n − m)dk+1 (m)

m=−∞

c k (n) =

∞

∑

(6.99) 2ha (2n − m)dk +1 (m)

m=−∞

where ga (n) = gs∗ (–n) and ha (n) = hs∗ (–n) are the analysis filters in the paraunitary filter bank. The beauty of these equations is that they look like discrete-time convolutions. Thus, if dk+1(n) is convolved with the impulse response 2g a (n) and the output decimated by 2, the result is the sequence dk (n). A similar statement follows for c k (n). The above computation can therefore be interpreted in filter bank form as in Fig. 6.37. Because of the PR property of the two-channel system (Fig. 6.22), it follows that we can reconstruct the projection coefficients dk+1(n) from the projection coefficients dk(n) and ck(n). Fast Wavelet Transform Repeated application of this idea results in Fig. 6.38, which is a tree-structured paraunitary filter bank (Section 6.4) with analysis filters 2g a (n) and 2ha (n) at each stage. Thus, given the projection coeffi­ cients d0 (n) for V0 , we can compute the projection coefficients dk (n) and c k (n) for the coarser spaces V−1 , W−1 , V−2 , W−2 ,KThis scheme is sometimes referred to as the fast wavelet transform (FWT). Figure 6.39 shows a schematic of the computation. In this figure each node (heavy dot) represents a decimated paraunitary analysis bank { 2ga(n), 2ha(n)}. The subspacess Wm and Vm are indicated in the Figure rather than the projection coefficients. Computation of the Initial Projection Coefficient. Everything depends on the computation of d0 (n). Note that d0 (n) = x(t ), φ(t − n) , which can be written as the integral d0 (n) = ∫ x(t )φ *(t − n)dt. An elaborate computation of this integral is avoided in practice. If the scale k = 0 is fine enough — if x(t)

√2ga(n)

d0(n)

↓2

d−1(n)

√2ga(n)

↓2

d−2(n)

Multiresolution coeffs.

√2ha(n)

√2ha(n)

√2ha(n)

↓2

↓2

↓2

c−1(n) Scale 0

Scale −1

c−2(n) Scale −2

c−3(n)

Wavelet coeffs.

Scale −3

FIGURE 6.38 Tree-structured analysis bank generating wavelet coefficients ck(n) and multiresolution coefficients dk(n) recursively. © 2003 by CRC Press LLC

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V−1

V−2

V−3

V0

W−1

W−2

W−3

FIGURE 6.39 A schematic of the tree-structured filter bank, which generates the coefficients of the projections onto Vk and Wk .

does not change much within the duration where φ(t) is significant — we can approximate this integral with the sample value x(n); i.e., d0 (n) ≈ x(n). Improved approximations of d0(n) have been suggested by other authors, but are not reviewed here.

Continuous Time Filter Banks and Multiresolution The preceding discussions show the deep connection between orthonormal multiresolution analysis and discrete time paraunitary filter banks. As shown by (6.91c), any L2 signal x(t) can be written as a sum of its projections onto the mutually orthogonal spaces V0 , W0 , W1, etc.: x (t ) =

∑

d0 (n)φ(t − n) +

n

∞

∑∑ c (n)2 ψ(2 t − n) k/2

k

k

k=0

n

This decomposition itself can be given a simple filter bank interpretation, with continuous time filters and samplers. For this, first note that the V0 component ∑n d0 (n)φ(t − n) can be regarded as the output of a filter with impulse response φ(t), with the input chosen as the impulse train ∑n d0 (n)δ a ( t − n). Similarly, the Wk component ∑n c k (n)2k/2 ψ(2k t − n) is the output of a filter with impulse response fk (t ) = 2k/2 ψ(2k t), in response to the input ∑n c k (n)δ a (t − 2−k n). This interpretation is shown by the synthesis bank of Fig. 6.40(a). The projection coefficients d0(n) and ck(n) can also be interpreted nicely. For example, we have d0 (n) = x(t ), φ(t − n) by orthonormality. This inner product can be explicitly written out as

∫

d0 (n) = x (t )φ * (t − n)dt The integral can be interpreted as a convolution of x(t) with φ*(–t). Consider the output of the filter with impulse response φ*(-t), with the input chosen as x(t). This output, sampled at time n, gives d0(n). Similarly, ck(n) can be interpreted as the output of the filter hk (t ) = 2k/2 ψ *(−2k t), sampled at the time 2–kn. The analysis bank of Fig. 6.40(a) illustrates this interpretation. Thus, the projection coefficients

d0(n) and ck(n) are the sampled versions of the outputs of an analysis filter bank.

Notice that all the filters in the filter bank are determined by the scaling function φ(t) and the wavelet function ψ(t). Every synthesis filter fk(t) is the time-reversed conjugate of the corresponding analysis filter hk(t), that is, fk (t ) = h *k (−t) (a consequence of orthonormality). In terms of frequency responses this means Fk (ω) = H k* (ω). For completeness of the picture, Fig. 6.40(b) shows typical frequency response magnitudes of these filters.

Further Manifestations of Orthonormality The orthonomality of the basis functions {φ(t – n)} and {ψ(t – n)} have further consequences, summarized below. A knowledge of these will be useful when we generate the scaling function φ(t) and the wavelet function ψ(t) systematically in Section 6.11 from paraunitary filter banks.

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d0(n) x(t)

sampler Ts = 1

φ∗(−t)

c0(n)

sampler Ts = 1

ψ∗(−t)

x(t)

Signal in W0 ψ(t)

c1(n)

sampler Ts = 0.5

√2ψ∗(−2t)

Signal in V0 φ(t)

Signal in W1 √2ψ(2t)

Analysis bank (multiresolution analysis)

Synthesis bank (a)

for φ(t) and φ∗(−t) for ψ(t) and ψ∗(−t) Frequency response magnitude

for √2 ψ(2t) and √2 ψ∗(−2t) V0

W0

W1

W2

ω

V0 V1 = V0 ⊕ W0 V2 = V1 ⊕ W1 (b)

FIGURE 6.40

(a) The multiresolution analysis and resynthesis in filter bank form, and (b) typical frequency responses.

1

0

R(τ)

1

τ

2

FIGURE 6.41 Example of an autocorrelation of the scaling function φ(t).

Nyquist Property and Orthonormality With φ(t ) ∈L2 , the autocorrelation function R(t) = ∫ φ(t)φ ∗ (t – τ) dt exists for all τ because this is simply an inner product of two elements in L2. Clearly, R(0) = φ(t)2 = 1. Further, the orthonormality property 〈φ(t), φ(t – n)〉 = δ(n) can be rewritten as R(n) = δ(n). Thus, R(τ) has periodic zero crossings at nonzero integer values of τ (Fig. 6.41). This is precisely the Nyquist property familiar to communication engineers. The autocorrelation of the scaling function φ(t) is a Nyquist function. The same holds for the wavelet function ψ(t). Next, using Parseval’s identity for L2-FTs, we obtain 〈φ(t), φ(t – n)〉 = ∫ Φ(ω)Φ ∗ (ω)e jωndω/2π = δ(n). If we decompose the integral into a sum of integrals over intervals of length 2π and use the 2π-periodicity of e jωn, we obtain, after some simplification: ∞

∑ Φ(ω + 2πk)

k=−∞

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2

=1

a.e.

(6.100)

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This is the Nyquist condition, now expressed in the frequency domain. The term a.e., almost everywhere, arises from the fact that we have drawn a conclusion about an integrand from the value of the integral. Thus, {φ(t – n)} is orthonormal iff the preceding equation holds. A similar result follows for Ψ(ω), so orthonormality of {ψ(t – n)} is equivalent to ∞

∑ Ψ(ω + 2πk)

2

=1

(6.101)

a.e.

k=−∞

Case in Which Equalities Hold Pointwise If we assume that all FTs are continuous, then equalities in the Fourier domain actually hold pointwise. This is the most common situation; in all examples here, the following are true: the filters Gs (e jω )and H s (e jω ) are rational (FIR or IIR), so the frequency responses are continuous functions of ω, and φ(t) and ψ(t) are not only in L2, but also in L1; i.e., φ(t ), ψ(t ) ∈ L1 ∩ L2 . Thus, Φ(ω) and Ψ(ω) are continuous functions (Section 6.6). With the dilation equation Φ(ω) = Gs (e jω/2 )Φ(ω / 2) holding pointwise, we have Φ(0) = Gs (e j0 )Φ(0). In all our applications Φ(0) ≠ 0 (it is a low-pass filter), so Gs (e j0 ) = 1. The power symmetry property

( )

Gs e jω

2

(

+ Gs −e jω

)

2

=1

then implies Gs (e jπ ) = 0. Because the high-pass synthesis filter is H s (e jω ) = e jω Gs * (−e jω ) we conclude H s (e j0 ) = 0 and H s (e jπ ) = −1. Thus,

( )

Gs e j0 = 1

( )

( )

Gs e jπ = 0

( )

H s e j0 = 0

H s e jπ = −1

(6.102)

In particular, the low-pass impulse response gs(n) satisfies ∑n g s (n) = 1. Because we already have Σn gs(n)2 = 0.5 (Theorem 6.6), we have both of the following: ∞

∑

g s (n) = 1 and

n=−∞

∞

∑ g (n)

2

s

= 0.5

(6.103)

n=−∞

From the dilation equation Φ(ω) = Gs(e jω/2)Φ(ω/2), we obtain Φ(2πk) = Gs (e jπk )Φ(πk). By using the fact that Gs (e jπ ) = 0, and after elementary manipulations, we can show that Φ(2πk ) = 0

k≠0

(6.104)

In other words, Φ(ω) is itself a Nyquist function of ω. If (6.100) is assumed to hold pointwise, the above implies that Φ(0) = 1. Without loss of generality we will let Φ(0) = 1, i.e., ∫φ(t)dt = 1. The dilation equation for the wavelet function Ψ(ω) in (6.85) shows that Ψ(0) = 0 [because Hs(e j0) = 0 by (6.102)]. That is, ∫ ψ(t )dt = 0. Summarizing, the scaling and wavelet functions satisfy ∞

∫ φ(t )dt = 1

∫

−∞ ∞

−∞

∫ φ(t ) dt = ∫ −∞

2

∞

∞

−∞

ψ (t )dt = 0

ψ (t ) dt = 1

and (6.105)

2

where property 3 follows from orthonormality. These integrals make sense because of the assumption φ(t ) ∈ L1 ∩ L2 . Another result that follows from Φ(2πk) = δ(k) is that © 2003 by CRC Press LLC

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∞

∑ φ(t − n) = 1

a.e.

(6.106)

n=−∞

Thus, the basis functions of the subspace V0 add up to unity. Return to the Haar basis and notice how beautifully everything fits together.

Generating Wavelet and Multiresolution Basis by Design of (t) Most of the well-known wavelet basis families of recent times were generated by first finding a scaling function φ(t ) such that it is a valid generator of multiresolution, and then generating ψ(t ) from φ(t ). The first step, therefore, is to identify the conditions under which a function φ(t ) will be a valid scaling function (i.e., it will generate a multiresolution). Once this is done and we successfully identify the coefficients g s (n) in the dilation equation for φ(t ), we can identify the wavelet function ψ(t ) using the second dilation equation in (6.84). From Theorem 6.6, we know that if ψ(t ) is computed in this way, then {2k/2 ψ(2k t – n)} is an orthonormal wavelet basis for L2. The following results can be deduced from the many detailed results presented in [5]. Theorem 6.7 (Orthonormal Multiresolution): Let φ(t ) satisfy the following conditions: φ(t) ∈ L1 I L2, ∫φ(t) dt ≠ 0 (i.e., Φ(0) ≠ 0), φ(t) = 2Σn gs (n)φ(2t – n) for some {gs (n)}, and {φ(t – n)} is an orthonormal sequence. Then the following are true: 1. φ(t ) generates a multiresolution. That is, if we define the space Vk to be the closure of the span of {2k/2 φ(2k t – n)}, then the set of spaces {Vk} satisfies the six conditions in the definition of multiresolution. 2. Define ψ(t) = 2 Σn (–1)n +1gs∗ (–n–1)φ(2t – n). Then, ψ(t ) generates an orthonormal wavelet basis for L2 ; that is, {2k/2 ψ(2k t − n)} , with k and n varying over all integers, is an orthonormal basis for L2. In fact, for fixed k, the functions {2k/2 ψ(2k t − n)} from an orthonormal basis for the subspace Wk (defined following the definition of multiresolution analysis). ▫ Comments. In many examples, φ(t ) ∈L2, and it is compactly supported. Then it is naturally in L1 as well, so the assumption φ(t ) ∈L2 I L1 is not too restrictive. Because L1 I L2 is dense in L2, the previous construc­ tion still gives a wavelet basis for L2. Notice also that the orthonormality of {φ(t − n)} implies orthonor­ mality of { 2φ(2t – n)}. The recursion φ(t ) = 2 ∑n g s (n)φ(2t − n), therefore, is a Fourier series for φ(t ) in L2. Thus the condition Σn gs(n)2 = 0.5 is automatically implied. This is not explicitly stated as part of the conditions in the theorem. Orthonormalization We know that orthonormality of {φ(t − n)} is equivalent to ∞

∑ Φ(ω + 2πk)

2

= 1

(6.107)

k=−∞

Suppose now that this is not satisfied, but the weaker condition ∞

a≤

∑ Φ(ω + 2πk)

2

≤ b

(6.108)

k=−∞

holds for some a > 0 and b < ∞. Then, it can be shown that, we can at least obtain a Riesz basis (Section 6.7) of the form {φ(t − n)} for V0. We can also normalize it to obtain an orthonormal sequence {φˆ (t − n)} from which an orthonormal wavelet basis can be generated in the usual way. The following theorem summarizes the main results. © 2003 by CRC Press LLC

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Theorem 6.8: Let φ(t ) ∈L1 I L2 , ∫ φ(t ) dt ≠ 0 (i.e., Φ(0) ≠ 0), and φ(t ) = 2 ∑n g s (n)φ(2t − n) with Σngs(n)2 < ∞. Instead of the orthonormality condition (6.107), let (6.108) hold for some a > 0 and b < ∞. Then the following are true: a Riesz basis for the closure V0 of its span. 1. {φ(t − n)} is 2. φ(t ) generates a multiresolution. That is, if we define the space Vk to be the closure of the span of { 2k/2 φ(2k t − n)}, the set of spaces {Vk} satisfies the six conditions in the definition of multiresolution. ▫ If we define a new function φˆ (t ) in terms of its FT as ˆ (ω ) = Φ

Φ(ω )  ∑ Φ(ω + 2πk ) 2   k 

0.5

,

(6.109)

then φˆ (t) generates an orthonormal multiresolution, and satisfies a dilation equation similar to (6.84). Using this we can define a corresponding wavelet function ψˆ (t) in the usual way. That is, if φˆ (t) = ˆ (t) = 2Σ h (n) φˆ (2t – n), where h (n) = (–1)n+1 g ∗(–n – 1). This wavelet ψ(t) ˆ 2Σn gs (n) φˆ (2t – n), choose ψ n s s s generates an orthonormal wavelet basis for L2. Note that the basis is not necessarily compactly supported if we start with compactly supported φ(t ). An example is given in Fig. 6.46(b) later. Example 10, Battle–Lemarié Orthonormal Wavelets from Splines. In Example 9, we considered a triangular φ(t ) (Fig. 6.36), which generates a nonorthonormal multiresolution. In this example, we have Φ(ω ) =

3  sin(ω 2)  2  (ω 2) 

2

(6.110)

and it can be shown that ∞

∑ Φ(ω + 2πk)

k=−∞

2

=

2 + cosω 2

(6.111)

The inequality (6.108) is satisfied with a = 1/2 and b = 3/2. Thus, we have a Riesz basis {φ(t − n)} for V0 . ˆ (ω) as above and then generate the From this scaling function, we can obtain the normalized function Φ wavelet function ψˆ (t ) as explained earlier. This gives an orthonormal wavelet basis for L2. φˆ (t) does not, however, have compact support [unlike φ(t)]. Thus, the wavelet function ψˆ (t ) generating the orthonormal wavelet basis is not compactly supported either. ▫

6.11 Orthonormal Wavelet Basis from Paraunitary Filter Banks The wisdom gained from the multiresolution viewpoint (Section 6.10) tells us a close connection exists between wavelet bases and two-channel digital filter banks. In fact, we obtained the equations of a paraunitary filter bank just by imposing the orthonormality condition on the multiresolution basis functions {φ(t − n)}. This section presents the complete story. Suppose we start from a two-channel digital filter bank with the paraunitary property. Can we derive an orthonormal wavelet basis from this? To be more specific, return to the dilation equations (6.84) or equivalently (6.85). Here, g s (n) and hs (n) are the impulse response coefficients of the two synthesis filters Gs (e jω ) and H s (e jω ) in the digital filter bank. Given these two filters, can we “solve” for φ(t ) and ψ(t )? If so, does this ψ(t ) generate an orthonormal basis for L2 space? This section answers some of these questions. Unlike any other section, we also indicate a sketch of the proof for each major result, in view of the importance of these in modern signal processing theory.

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Recall first that under some mild conditions (Sections 6.10) we can prove that the filters must satisfy (6.102) and (6.103), if we need to generate wavelet and multiresolution bases successfully. We impose these at the outset. By repeated application of the dilation equation, we obtain Φ(ω) = Gs(e jω/2) G s (e jω/4 )Φ(ω/4). Futher indefinite repetition yields an infinite product. Using the condition Φ(0) = 1, which we justified earlier, we obtain the infinite products Φ(ω ) =

∞

∏

Gs (e jω

k=1

2k

∞

) = Gs (e jω 2)∏Gs (e jω 2 )

Ψ(ω ) = H s (e jω

k

(6.112a)

k=2

∞

2

)∏Gs (e jω 2 ) k

(6.112b)

k=2

The first issue to be addressed is the convergence of the infinite products above. For this we need to review some preliminaries on infinite products [22, 23]. Ideal Bandpass Wavelet Rederived from the Digital Filter Bank. Before we address the mathematical details, let us consider a simple example. Suppose the pair of filters Gs(e jω) and Hs(e jω) are ideal brickwall low-pass and high-pass filters in the Fig. 6.28(a). Then we can verify, by making simple sketches of a few terms in (6.112), that the above infinite products yield the functions Φ(ω) and Ψ(ω) shown in Fig. 6.33. That is, the ideal bandpass wavelet is indeed related to the ideal paraunitary filter bank by means of the above infinite product.

Convergence of Infinite Products To define convergence of a product of the form ∏k =1 ak , consider the sequence {pn} of partial products n pn = ∏k=1 ak. If this converges to a (complex) number A with 0 < A < ∞, we say that the infinite product converges to A. Convergence to zero should be defined more carefully to avoid degenerate situations (e.g., if a1 = 0, then pn = 0 for all n regardless of the remaining terms ak, k > 1). We use definition in [22]. The infinite product is said to converge to zero iff ak = 0 for a finite nonzero number of values of k, and if the product with these ak deleted converges to a nonzero value. ∞

Useful Facts about Infinite Products ∞

1. Whenever ∏k =1 ak converges, it can be shown ak → 1 as k → ∞. For this reason it is convenient to write ak = 1 + bk ∞ ∞ 2. We say that ∏ k =1 (1 + bk) converges absolutely if ∏ k =1 (1 + bk) converges. Absolute convergence ∞ of ∏ k =1 (1 + bk) implies its convergence. ∞ ∞ 3. It can be shown that the product ∏ k =1 (1 + bk) converges iff the sum Σ k =1 bk  converges. That ∞ ∞ is, ∏ k =1 (1 + bk) converges absolutely iff Σ k =1 bk converges absolutely. Example 11. The product ∏ k =1 (1 + k –2) converges because Σ k =1 1/k 2 converges. Similarly, ∏ k =1 (1 – k –2) ∞ converges because it converges absolutely, by the preceding example. The product ∏ k =1 (1 + k –1) does ∞ ∞ not converge because Σ k =1 1/k diverges. Products such as ∏ k =1 (1/k 2) do not converge because the terms do not approach unity as k → ∞. ▫ ∞

∞

∞

Uniform Convergence A sequence {pn(z)} of functions of the complex variable z converges uniformly to a function p(z ) on a set  in the complex plane if the convergence rate is the same everywhere in . More precisely, if we are given ε > 0, we can find N such that pn (z) − p(z) < ε for every z ∈, as long as n ≥ N . The crucial thing is that N depends only on ε and not on z, as long as z ∈. A similar definition applies for functions of real variables. © 2003 by CRC Press LLC

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We say that an infinite product of functions ∏k =1 ak (z) converges at a point z if the sequence of partial n products pn (z) = ∏k=1 ak (z) converges as described previously. If this convergence of pn(z) is uniform in a set , we say that infinite product converges uniformly on . Uniform convergence has similar advan­ tages, as in the case of infinite summations. For example, if each of the functions ak(ω) is continuous on ∞ the real interval [ω1, ω2], then uniform convergence of the infinite product A(ω) = ∏k =1 ak (ω) on [ω1 , ω 2 ] implies that the limit A(ω) is continuous on [ω1 , ω 2 ]. We saw above that convergence of infinite products can be related to that of infinite summations. The following theorem [23] makes the connection between uniform convergence of summations and uniform convergence of products. Theorem 6.9: Let bk(z), k ≥ 1 be a sequence of bounded functions of the complex variable z, such that Σ k =1 bk(z) ∞ converges uniformly on a compact set2  in the complex z plane. Then, the infinite product ∏ k =1 (1 + bk(z)) ▫ converges uniformly on . This product is zero for some z0 iff 1 + bk (z 0 ) = 0 for some k. ∞

Uniform convergence and analyticity. We know that if a sequence of continuous functions converges uniformly to a function, then the limit is also continuous. A similar result is true for analytic functions. If a sequence {fn(s)} of analytic functions converges uniformly to a function f (s), then f (s) is analytic as well. For a more precise statement of this result see Theorem 10.28 in [23].

Infinite Product Defining the Scaling Function Return now to the infinite product (6.112a). As justified in Section 6.10, assume Gs(e jω) to be continuous, Gs(e j0) = 1, and Φ(0) ≠ 0. Note that Gs(e j0) = 1 is necessary for the infinite product to converge (because convergence of ∏k ak implies that ak → 1; apply this for ω = 0 ). The following convergence result is fun­ damental. ∞

Theorem 6.10, Convergence of the Infinite Product: Let Gs (e jω ) = ∑n = −∞ g s (n)e − jωn . Assume that Gs(e j0) = 1, and ∑n ng s (n) < ∞. Then, 1. The infinite product (6.112a) converges pointwise for all ω. In fact, it converges absolutely for all ω, and uniformly on compact sets (i.e., closed bounded sets, such as sets of the form [ω1,ω2]). 2. The quantity Gs(e jω) as well as the limit Φ(ω) of the infinite product (6.112a) are continuous functions of ω. 3. Gs(e jω) is in L2. Because the condition Σnngs(n) < ∞ implies Σngs(n) < ∞, the filter Gs(e jω) is restricted to be stable, but the above result holds whether gs(n) is FIR or IIR. Sketch of Proof. Theorem 6.9 allows us to reduce the convergence of the product to the convergence of an infinite sum. For this we must write Gs(e jω) in the form 1– F(e jω) and consider the summation ∞ Σk =1 F(e jω/2k). Because , Gs(e j0) = 1 = Σn gs(n), we can write Gs(e jω) = 1 – (1 – Gs(e jω)) = 1 – Σn gs(n)(1 – e –jωn). However,  Σn gs(n)(1 – e –jωn) ≤ 2 Σn gs(n) sin (ωn/2) ≤ ω Σn ngs (n)(use sin x/x ≤ 1). Σ n ngs(n) is assumed to converge, thus we have  Σn gs(n)(1 – e –jωn) ≤ cω. Using this and the fact that Σ k∞=1 2 –k converges, we can complete the proof of part 1 (by applying Theorem 6.9). Σn ngs (n) < ∞ implies in particular that g s (n) ∈l1 , therefore, its l1 − FT Gs (e jω ) is continuous (see Section 6.6). The continuity Gs(e jω), together with uniform convergence of the infinite product, implies that the pointwise limit Φ(ω) is also continuous. Finally, because l1 ⊂ l 2 (Section 6.6), we have g s (n) ∈l 2 , that is, Gs (e jω ) ∈L2[0, 2π] as well. ▫

2For us, a compact set means any closed bounded set in the complex plane or on the real line. Examples are all points on and inside a circle in the complex plane, and the closed interval [a, b] on the real line.

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Orthonormal Wavelet Basis from Paraunitary Filter Bank ∞

We now consider the behavior of the infinite product ∏ k =1 Gs(e jω/2k), when Gs(e jω) comes from a paraunitary filter bank. The paraunitary property implies that Gs(e jω) is power symmetric. If we impose some further mild conditions on Gs(e jω) , the scaling function φ(t) generates an orthonormal multires­ olution basis {φ(t – n)}. We can then obtain an orthonormal wavelet basis {ψkn(t)} (Theorems 6.6 and 6.7). The main results are given in Theorems 6.11 to 6.15. First, we define the truncated partial products Pn(ω). Because Gs(e jω) has period 2π, the term Gs(e jω/2k) n has period 2k+1π. For this reason the partial product ∏ k=1 Gs(e jω/2k) has period 2n+1π, and we can regard the region [–2nπ, 2nπ] to be the fundamental period. Let us truncate the partial product to this region, and define

∏

  Pn (ω ) =  0,

n k=1

Gs (e jω

2k

),

for − 2n π ≤ ω ≤ 2n π,

(6.113)

otherwise

This quantity will be useful later. We will see that this is in L2(R), and we can discuss pn(t), its inverse L2-FT . Theorem 6.11: Let Gs(e jω) be as in Theorem 6.10. In addition let it be power symmetric; in other words, Gs(e jω)2 + Gs(–e jω)2 = 1. Notice in particular that this implies Gs(e jπ) = 0, because Gs(e j0) = 1]. Then the following are true: 1. ∫ 0 Gs(e jω)2 dω/2π = 0.5. ∞ 2. The truncated partial product Pn(ω) is in L2, and ∫ –∞ Pn(ω)2 dω/2π = 1 for all n. Further, the inverse L2-FT, denoted as pn(t), gives to an orthonormal sequence {pn(t – k)}, i.e., 〈pn(t – k), pn(t – i)〉 = δ(k – i) for any n ≥ 1. 3. The limit Φ(ω) of the infinite product (6.112a) is in L2; hence, it has an inverse L2-FT, φ(t) ∈L2. Moreover, φ(t)2 ≤ 1. ▫ 2π

Sketch of Proof. Part 1 follows by integrating both sides of Gs(e jω)2 + Gs(–e jω)2 = 1. The integral in part n n+1 n 2n+1π 2 is ∫0 ∏ k=1 Gs(e jω/2k)2 dω/2π, which we can split into two terms such 2as ∫02 π + ∫22nπ2 π . Using the 2π periodicity and the power symmetric property of Gs(e jω), we obtain∫Pn  dω =∫Pn–1  dω. Repeated 2 ∞ application of this, together with part 1, yields ∫–∞ Pn (ω) dω/2π = 1. The proof of orthonormality of ∞ 2 {pn(t – k)} follows essentially similarly by working with the modified integral ∫–∞ Pn (ω) e jω(k–i) dω/2π, and using the half-band property of Gs(e jω)2. The third part is the most subtle, and uses Fatou’s lemma for Lebesgue integrals (Section 6.6). For this, define gn (ω) = Pn(ω)2. Then, {gn (ω)} is a sequence of nonnegative integrable functions such that gn (ω) → Φ(ω)2 pointwise for each ω. Because ∫ gn(ω)dω = 2π (from part 2), Fatou’s lemma assures us ▫ that Φ(ω)2 is integrable with integral ≤ 2π. This proves part 3. It is most interesting that the truncated partial products Pn(ω) give rise to orthonormal sequences {pn (t − k)}. This orthonormality is induced by the paraunitary property, more precisely the power symmetry property of Gs (e jω). This is consistent with the fact that the filter bank type of basis introduced in Section 6.4 is an orthonormal basis for l2 whenever the filter bank is paraunitary. As the scaling function Φ(ω) is the pointwise limit of {Pn (ω)} as n → ∞, this leads to the hope that {φ (t −k)} is also an orthonormal sequence, so that we can generate a multiresolution and then a wavelet basis as in Theorems 6.6 and 6.7. This, however, is not always true. The crux of the reason is that Φ(ω) is only the pointwise limit of {Pn (ω)}, and not necessarily the L2 limit. The distinction is subtle (see below). The pointwise limit property means that for any fixed ω, the function Pn(ω) approaches Φ(ω). The L2 limit property means that ∫ Pn(ω) – Φ(ω)2 dω → 0. Neither of these limit properties implies the other; neither is stronger than the other. It can be shown that it is the L2 limit that propagates the orthonormality property, and this is what we want.

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Theorem 6.12: Let {pn (t – k)} be an orthonormal sequence for each n. That is, 〈pn (t – k), pn (t – i) = ▫ δ(k – i). Suppose pn (t) → φ (t) in the L2 sense. Then {φ(t – k)} is an orthonormal sequence. Proof. If we take limits as n → ∞, we can write lim pn (t − k ), pn (t − i ) = lim pn (t − k ), lim pn (t − i )

n→∞

n→∞

(6.114)

n→∞

This movement of the “limit” sign past the inner product sign is allowed (by continuity of inner products, Section 6.6), provided the limits in the second expression are L2 limits. By the conditions of the theorem, the left side of the above equation is δ(k – i), whereas the right side is 〈φ(t – k),φ (t – i)〉. So the result follows. ▫ L2 Convergence vs. Pointwise Convergence The fact that L2 limits are not necessarily pointwise limits is obvious from the fact that differences at a countable set of points do not affect integrals. The fact that pointwise limits are not necessarily L2 limits is demonstrated by the sequence of L2 functions {fn(t)}, with fn(t) as in Fig. 6.42. Note that fn(t) → 0 pointwise for each t, that is, the pointwise limit is f (t) ≡ 0. Hence,  fn(t) – f (t) =  fn(t) = 1 for all n, so  fn(t) – f (t) does not go to zero as n → ∞ and thus, f (t) is not the L2 limit of fn(t). Notice in this example that 1 = limn → ∞ ∫  fn(t)2 dt ≠ ∫ limn → ∞  fn(t)2 dt = 0. This is consistent with the fact that the Lebesgue dominated convergence theorem cannot be applied here — no integrable function dominates  fn(t)2 for all n. In this example, the sequence {fn(t)} does not converge in the L2 sense. In fact,  fn(t) – fm(t)2 = 2 for n ≠ m. Thus, {fn} is not a Cauchy sequence [22] in L2. Some facts pertaining to pointwise and L2 convergences: It can be shown that if fn(t) → f (t) in L2 sense and fn(t) → g(t) ∈ L2 pointwise as well, then f (t) = g(t) a.e. In particular,  f (t) – g(t) = 0 and  f (t) =  g(t). It also can be shown that if fn(t) → f (t) in L2 sense, then  fn(t) → f (t). Finally, if fn(t) → f (t) ∈L2 pointwise a.e., and  fn(t) → f (t) then fn(t) → f (t) in L2 sense as well [23]. Theorem 6.13, Orthonormal Wavelet Basis: Let the filter Gs(e jω) = Σ n=–∞ gs(n)e –jωn satisfy the following properties: ∞

1. Gs(e j0) = 1 2. Σnngs(n) < ∞ 3. Gs(e jω)2 + Gs(–e jω)2 = 1 (power symmetry) 4. Gs(e jω) ≠ 0 for ω ∈[–0.5π, 0.5π] Then the infinite product (6.112a) converges to a limit Φ(ω) ∈L2, and its inverse FT φ(t) is such that {φ(t – n)} is an orthonormal sequence. Defining the wavelet function ψ(t) as usual, i.e., as in (6.93), the sequence {2k/2 ψ(2k t – n)} (with k and n varying over all integers) forms an orthonormal wavelet basis for L2. ▫ Sketch of Proof. We will show that the sequence {Pn(ω)} of partial products converges to Φ(ω) in the L2 sense, i.e., ∫Pn(ω) – Φ(ω)2 dω → 0, so that pn(t) → φ(t) in L2 sense. The desired result then follows in view of Theorems 6.11 and 6.12. The key tool in the proof is the dominated convergence theorem for

0

1

fn(t)

n

n+1

FIGURE 6.42 A sequence {fn(t)} with a pointwise limit is not a limit in the L2 sense.

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t

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Lebesgue integrals (Section 6.6). First, the condition G(e jω) ≠ 0 in [–0.5π, 0.5π] implies that Φ(ω) ≠ 0 in [–π, π]. Because Φ(ω)2 is continuous (Theorem 6.10) it has a minimum value c2 > 0 in [–π, π]. Now the truncated partial product Pn(ω) can always be written as Pn(ω) = Φ(ω)/Φ(ω/2n) in its region of support. Because Φ(ω/2n)2 ≥ c2 in [–2nπ, 2nπ], we have Pn(ω)2 ≤ Φ(ω)2/c2 for all ω. Define Qn(ω) = Pn(ω) – Φ(ω)2. Then using Pn(ω)2 ≤ Φ(ω)2/c2 we can show that Qn(ω) ≤ αΦ(ω)2 for some constant α. Because the right-hand side is integrable, and because Qn(ω) → 0 pointwise (Theorem 6.10) we can use the dominated convergence theorem (Section 6.6) to conclude that limn ∫Qn(ω)dω = ∫ limnQn(ω) dω = 0. This completes the proof. ▫ Computing the Scaling and Wavelet Functions Given the coefficients gs(n) of the filter G(e jω), how do we compute the scaling function Φ(t) and the ∞ wavelet function ψ(t)? Because we can compute ψ(t) using ψ(t) = 2 Σ n=–∞ (–1)n+1 g∗s (–n – 1)φ(2t – n), the key issue is the computation of φ(t). In the preceding theorems φ(t) was defined only as an inverse L2 –FT of the infinite product Φ(ω) given in (6.112a). Because an L2 function is determined only in the a.e. sense, this way of defining φ(t) itself does not fully determine φ(t). Recall, however, that the infinite product for Φ(ω) was only a consequence of the more fundamental equation, the dilation equation φ(t) = ∞ 2 Σ n=–∞ gs(n)φ(2t – n). In practice φ(t) is computed using this equation, which is often a finite sum (see Section 6.12). The procedure is recursive; we assume an initial solution for the function φ(t), substitute it into the right-hand side of the dilation equation, thereby recomputing φ(t), and then repeat the process. Details of this and discussions on convergence of this procedure can be found in [5, 15, and 26]. Lawton’s Eigenfunction Condition for Orthonormality [5] Equation (6.100) is equivalent to the orthonormality of {φ(t – n)}. Let S(e jω) denote the left-hand side of (6.100), which evidently has period 2π in ω. Using the frequency domain version of the dilation equation (6.85), it can be shown that the scaling function φ(t) generated from GS(e jω) is such that

( ) ( ) 2

Gs e jω S e jω

( )

= 0.5S e jω ↓2

(6.115)

where the notation ↓2 indicates decimation (Section 6.4). Thus, the function S(e jω) can be regarded as an eigenfunction (with eigenvalue = 0.5) of the operator , which performs filtering by GS(e jω)2 followed by decimation. Now consider the case in which the digital filter bank is paraunitary, so that GS(e jω) is power symmetric [i.e., satisfies (6.95)]. The power symmetric condition can be rewritten in the form GS(e jω)2↓2 = 0.5. Thus, in the power symmetric case the identify function is an eigenfunction of the operatior . If the only eigenfunction of the operatior  is the identity function, it then follows that S(e jω) = 1; i.e., (6.100) holds and {φ(t – n)} is orthonormal. The FIR Case. Section 6.12 shows that restricting Gs(z) to be FIR ensures that φ(t) has finite duration. For the FIR case, Lawton and Cohen independently showed that the previous eigenfunction condition also works in the other direction. That is, if {φ(t – n)} has to be orthonormal, then the trignometric polynomial S(e jω) satisfying (6.115) must be unique up to a scale factor.3 Details can be found in [5]. Examples and Counter-Examples We already indicated after the introduction of (6.112) that the example of the ideal bandpass wavelet can be generated formally by starting from the ideal brickwall paraunitary filter bank. We now discuss some other examples.

3A finite sum of the form Σ Nn=2 N 1 pne jωn is said to be a trignometric polynomial. If Gs(e jω ) is FIR, it can be demonstrated that the left-hand side of (6.100) is not only periodic in ω, but is in fact a trignometric polynomial.

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Gs(e jω)

Hs(e jω) Gs(z) = (1 + z −1)/2

(a)

Hs(z) = (1 − z −1)/2

π

0

ω

φ(t) 1 (b)

scaling function 0

1

t

1

ψ(t) Haar wavelet

(c) 1 0

t

FIGURE 6.43 Haar basis generated from a paraunitary filter bank. (a) The synthesis filters in the paraunitary filter bank, (b) the scaling function, and (c) the wavelet function generated using dilation equations.

Example 12, Haar Basis from Filter Banks. A filter bank of the form Fig. 6.22(a) with filters Ga ( z ) =

1 + z −1 1 + z −1 1 − z −1 z −1 −1 Ha (z ) = Gs ( z ) = H s (z) = 2 2 2 2

is paraunitary. The magnitude responses of the synthesis filters, Gs(e jω) = cos(ω/2) and Hs(e jω) = sin(ω/2), are shown in Fig. 6.43(a). Gs(z) satisfies all the conditions of Theorem 6.13. In this case we ∞ can evaluate the infinite products for Φ(ω) and ψ(ω) explicitly by using the identity ∏ m=1 cos(2–m ω) = sin ω/ω. The resulting φ(t) and ψ(t) are as shown in Fig. 6.43(b) and (c). These are precisely the functions that generate the Haar orthonormal basis. ▫ Example 13, Paraunitary Filter Bank that Does Not Give Orthonormal Wavelets. Consider the filter bank with analysis filters Ga(z) = (1 + z–3)/2, Ha(z) = –(1 – z–3)/2, and synthesis filters Gs(z) = (1 + z–3)/2, Hs(z) = (1 – z–3)/2. Because this is obtained from the preceding example by the substitution z → z3, it remains paraunitary and satisfies the PR property. Gs(z) satisfies all the properties of Theorem 6.13, except the fourth condition. With φ(t) and ψ(t) obtained from Gs(e jω) using the usual dilation equations, the functions {φ(t – n)} are not orthonormal. In addition, the wavelet functions {2k/2 ψ(2k t – n)} do not form an orthonormal basis. These statements can be verified from the sketches of the functions φ(t) and ψ(t) shown in Fig. 6.44. Clearly, φ(t) and φ(t – 1) are not orthogonal, and ψ(t) and ψ(t – 2) are not orthogonal. In this example, Pn(ω) = 1 for all n, whereas Φ(ω) = 1/ 3. The limit of Pn(ω) does not agree with Φ(ω), and our conclusion is that Φ(ω) is not the L2 limit of Pn(ω). The L2 limit of Pn(ω) does not exist in this example. ▫ Thus, a paraunitary filter bank may not generate an orthonormal wavelet basis if the fourth condition in Theorem 6.13 is violated. However, this is hardly of concern in practice, because any reasonable low-pass © 2003 by CRC Press LLC

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Gs(e jω) 1 (a)

π/3

0

2π/3

π

ω

φ(t) (b)

1/ 3

scaling function

0

1/ 3

t

3

ψ(t)

(c)

wavelet function 3 0

t

ψ(t−2) (d)

1/ 3

0

t 3

FIGURE 6.44 A paraunitary filter bank generating nonorthonormal {φ(t – n)}. (a) The synthesis filter response, (b) the scaling function, (c) the wavelet function, and (d) a shifted version.

filter designed for a two-channel filter bank will be free from zeroes in the region [–0.5π, 0.5π]. In fact, a stronger result was proved by Cohen, who derived necessary and sufficient conditions for an FIR paraunitary filter bank to generate an orthonormal wavelet basis. One outcome of Cohen’s analysis is that the fourth condition in Theorem 6.13 can be replaced by the even milder condition that Gs(e jω) not be zero in [–π/3, π/3]. In this sense, the condition for obtaining an orthonormal wavelet basis is trivially satisfied in practice. The case in which the fourth condition fails is primarily of theoretical interest; an attractive result in this context is Lawton’s tight frame theorem.

Wavelet Tight Frames Although the wavelet functions {2k/2 ψ(2k t – n)} generated from a paraunitary filter bank may not form an orthonormal basis when the fourth condition of Theorem 6.13 is violated, the functions always form a tight frame for L2. Thus, any L2 function can be expressed as an infinite linear combination of the functions {2k/2 ψ(2k t – n)}. More precisely, we have the following result due to Lawton [5]. © 2003 by CRC Press LLC

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Theorem 6.14, Tight Frames from Paraunitary Filter Banks: Let Gs(e jω) = Σ n=0 gs(n)e –jωn be a filter satisfying the following properties: N

1. Gs(e j0) = 1 2. Gs(e jω)2 + Gs(–e jω)2 = 1 (power symmetry) Then, φ (t) ∈ L2. Defining the wavelet function (t) as in (6.93), the sequence {2k/2 ψ(2k t – n)} (with k and n varying over all integers) forms a tight frame for L2, with frame bound unity (i.e., A = B = 1; see Section 6.8). Thus, the functions ψkn(t) in Example 13 constitute a tight frame for L2. From Section 6.8, we know that this tight frame property means that any x(t) ∈ L2 can be expressed as x (t ) =

∞

∞

∑∑ x(t ), ψ

kn

(t ) ψ kn (t )

(6.116)

k=−∞ n=−∞

where ψkn(t) = 2k/2 ψ(2k t – n). This expression is pretty much like an expansion into an orthonormal basis. We can find the wavelet coefficients ckn = 〈x(t), ψkn(t)〉 exactly as in the orthonormal case. We also know that frames offer stability of reconstruction. Thus, in every respect this resembles an orthonormal basis, the only difference being that the functions are not linearly independent (redundancy exists in the wavelet tight frame {ψkn(t)}).

6.12 Compactly Supported Orthonormal Wavelets Section 6.11 showed how to construct an orthonormal wavelet basis for L2 space by starting from a paraunitary filter bank. Essentially, we defined two infinite products Φ(ω) and Ψ(ω) starting from the digital low-pass filter Gs(e jω). Under some mild conditions on Gs(e jω), the products converge (Theorem 6.10). Under the further condition that Gs(e jω) be power symmetric and nonzero in [-0.5, 0.5], we saw that {φ(t – k)} forms an orthonormal set, and the corresponding {2k/2 ψ(2k t – n)} forms an orthonormal wavelet basis for L2 (Therorem 6.13). If we further constrain Gs(e jω) to be FIR, that is, Gs(z) = ΣNn=0 gs(n)z –n, then the scaling function φ(t) and the wavelet function ψ(t) have finite duration [6, 5]. Theorem 6.15: Let Gs(z) Σ n=0 gs(n)z –n, with Gs(ej0) = 1 and Hs(e jω) = e jω Gs*(–e jω). Define the infinite products as in (6.112a) and (b), and assume that the limits Φ(ω) and Ψ(ω) are L2 functions, for example, by imposing power symmetry condition on Gs(z) as in Theorem 6.11. Then φ(t) and ψ(t) (the inverse L2­ FTs) are compactly supported, with support in [0, N]. The time decay of the wavelet ψ(t) is therefore excellent. In particular, all the basis functions {2k/2 ψ(2k t – n)} are compactly supported. By further restricting the low-pass filter Gs(z) to have a sufficient number of zeroes at ω = π, we also ensure (Section 6.13) that the FT Ψ(ω) has excellent decay (equivalently ψ(t) is regular or smooth in the sense to be quantified in Section 6.13). The rest of this section is devoted to the technical details of the above result. The reader not interested in these details can move to Section 6.13 without loss of continuity. The theorem might seem “obvious” at first sight, and indeed a simple engineering argument based on Dirac delta functions can be given (p. 521 of [7]). However, the correct mathematical justification relies on a number of deep results in function theory. One of these is the celebrated Paley–Wiener theorem for band-limited functions. N

Paley–Wiener Theorem. A beautiful result in the theory of signals is that if an L2 function f (t) is bandlimited, that is, F(ω) = 0, ω ≥ σ, then f (t) is the “real-axis restriction of an entire function”. We say that a function f (s) of the complex variable s is entire if it is analytic for all s. Examples are polynomials in s, exponentials such as es, and simple combinations of these. The function f (t) obtained from f (s) for real values of s(s = t) is the real-axis restriction of f (s). Thus, if f (t) is a band-limited signal then an entire function f (s) exists such that its real-axis restriction is f (t). In particular, therefore, a band-limited function f (t) is continuous and infinitely differentiable

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with respect to the time variable t. The entire function f (s) associated with band-limited function has the further property  f (s) ≤ ce σs for some c > 0. We express this by saying that f (s) is exponentially bounded or of the exponential type. What is even more interesting is that the converse of this result is true: if f (s) is an entire function of the exponential type, and the real-axis restriction f (t) is in L2, then f (t) is bandlimited. By interchanging the time and frequency variables, we can obtain similar conclusions for timelimited signals; this is what we need in the discussion of the time-limited (compactly supported) wavelets. Theorem 6.16 (Paley–Wiener): Let W(s) be an entire function such that for all s, we have W(s) ≤ c exp (As) for some c, A > 0, and the real-axis restriction W(ω) is in L2 . Then, there exists a function w(t) in L2 A such that W(s) = ∫–A w(t)e –jts dt. ▫ A proof can be found in [23]. Thus, w(t) can be regarded as a compactly supported function support in [-A,A]. Recall (6.48) that L2[–A,A] ⊂ L1[–A,A] so w (t) is in L1[–A,A] and L2[–A,A]. Therefore, W(ω) is the L1 –FT of w(t), and agrees with the L2-FT a.e. Our aim is to show that the infinite product for Φ(ω) satisfies the conditions of the Paley–Wiener theorem, and therefore that φ(t) is compactly supported. A modified version of the previous result is more convenient for this. The modification allows the support to be more general, namely [–A1,A2], and permits us to work with the imaginary part of s instead of the absolute value. Theorem 6.17 (Paley–Wiener, Modified): Let W(s) be an entire function such that

( (

) )

c exp A Im s , 1 1 W (s ) ≤  c 2 exp A2 Im s , 

Im s ≥ 0 (6.117) Im s ≤ 0

for some c1, c2, A1, A2 > 0, and such that the real-axis restriction W(ω) is in L2. Then a function w(t) exists A in L2 such that W(s) = ∫–A21 w(t)e –jts dt. We can regard W(ω) as the FT of the function w(t) supported in [–A2, A1]. This result can be made more general; the condition (6.117) can be replaced with one in which the right-hand sides have the form Pi(s) exp(AiIm s), where Pi(s) are polynomials. We are now ready to sketch the proof that φ(t ) and Ψ(t ) have the compact support [0, N]. 1. Using the fact that Gs(z) is FIR and that Gs(e j0) = 1, show that the product ∏ k=1 Gs(e js/2k) converges uniformly on any compact set of the complex s-plane. (For real s, namely s = ω, this holds even for the IIR case as long as ∑n ng s (n) converges. This was shown in Theorem 6.10.) 2. Uniformity of convergence of the product guarantees that is limit Φ(s) is an entire function of the complex variable s (Theorem 10.28 [23]). 3. The FIR nature of Gs(z) allows us to establish the exponential bound (6.117) for Φ(s) with A2 = 0 and A1 = N. This shows that φ(t ) is compactly supported in [0, N]. Because Ψ(t ) is obtained from the dilation equation (6.93), the same result follows for Ψ(t ) as well. ∞

6.13 Wavelet Regularity From the preceding section, we know that if we construct the power symmetric FIR filter Gs(z) properly, we can get an orthonormal multiresolution basis {φ(t – n)}, and an orthonormal wavelet basis {2k/2 ψ(2k t – n)} for L2. Both of these bases are compactly supported. These are solutions to the two-scale dilation equations N

∑ g (n)φ(2t − n)

φ(t ) = 2

s

n=0

© 2003 by CRC Press LLC

(6.118)

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N

∑ h (n)φ(2t − n)

ψ (t ) = 2

s

(6.119)

n=0

where hs(n) = (–1)n+1g s∗ (–n – 1). In the frequency domain we have the explicit infinite product expressions (6.112) connecting the filters Gs(z) and Hs(z) to the L2 − FTs Φ(ω) and Ψ(ω). Figure 6.45(a) shows two cases of a ninth-order FIR filter Gs(e jω) used to generate the compactly supported wavelet. The resulting wavelets are shown in Figs. 6.45(b) and (c). In both cases all conditions of Theorem 6.13 are satisfied so we obtain orthonormal wavelet bases for L2. The filter Gs(e jω) has more zeroes at π for case 2 than for case 1. The corresponding wavelet looks much smoother or “regular”; this is an example of a Daubechies wavelet. By designing Gs(z) to have a sufficient number of zeroes at π, we can make the wavelet “as regular as we please”. A quantitative discussion of the connection between the number of zeroes at π and the smoothness of ψ(t) is given in the following discussions. Quantitatively, the idea is that if Gs(e jω) has a large number of zeroes at π, the function Φ(ω) given by the infinite product (6.112a) decays “fast”, as ω → ∞. This fast asymptotic decay in the frequency domain implies that the time function φ(t) is “smooth”. Because ψ(t) is derived from φ(t) using a finite sum (6.119), the smoothness of φ(t) is transmitted to ψ(t). We will the make ideas more quantitative in the next few sections. Why Regularity? The point made above was that if we design an FIR paraunitary filter bank with the additional constraint that the low-pass filter Gs(e jω) should have a sufficient number of zeroes at π, the wavelet basis functions Ψkn(t) are sufficiently smooth. The smoothness requirement is perhaps the main new component brought into the filter bank theory from the wavelet theory. Its importance can be understood in a number of ways. Consider the expansion x(t) = Σk,n ck,n Ψkn(t). Suppose we truncate this to a finite number of terms, as is often done in practice. If the basis functions are not smooth, the error can produce perceptually annoying effects in applications such as audio and image coding, even though the L2 norm of the error may be small. Next, consider a tree-structured filter bank. An example is shown in Fig. 6.26. In the syntheses bank, the first path can be regarded as an effective interpolation filter, or an expander [e.g., ↑ 8 in Fig. 6.26(b)] L followed by a filter of the form Gs (e jω )Gs (e 2 jω )Gs (e 4 jω )LGs (e 2 jω ). The same finite product can be obtained by truncating to L + 1 terms the infinite product defining Φ(ω) (6.112), and making a change of variables. Similarly, the remaining paths can be related to interpolation filters which are various truncated versions of the infinite product defining Ψ(ω) in (6.112). Imagine we use the tree-structured system in subband coding. The quantization error in each subband is filtered through an interpolation filter. If the impulse response of the interpolation filter is not smooth enough [e.g., if it resembles Fig. 6.45 (b)], the filtered noise tends to show severe perceptual effects, for example, in image reconstruction. This explains, qualitatively, the importance of having “smooth impulse responses” for the synthesis filters.

Smoothness and Hölder Regularity Index We are familiar with the notion of continuous functions. We say that f (t) is continuous at t0 if, for any  > 0, we can find a δ > 0 such that  f (t) – f (t0) <  for all t satisfying t – t0 < δ. A stronger type of continuity, called Hölder continuity, is defined as follows: f (t) is Hölder continuous in a region  if  f (t0) – f (t1) ≤ ct0 – t1β for some c, β > 0, for all t0, t1 ∈ . This implies, in particular, continuity in the ordinary sense. If β > 1 the above would imply that f (t) is constant on . For this reason, we have the restriction 0 < β ≤ 1. As β increases from 0 to 1, the function becomes increasingly “smoother”. The constant β is called the Lipschitz constant of the function f (t). Suppose the function f (t) is n times differentiable in some region  and the nth derivative f (n)(t) is Hölder continuous with Lipschitz constant β. Define α = n + β. We say that f (t) belongs to the class C α. The coefficient α is called the Hölder regularity index of f (t). For example, C 3,4 is the class of functions

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(a) 1.0

case 2

Gs(e jω) 0.5

0.0 0.00

case 1

0.10

0.20 0.30 Normalized Frequency

0.40

0.50

1.5

(b)

case 1 0.5 ψ(t) −0.5

−1.5 0.0

2.0

4.0 t

6.0

8.0

1.5

(c)

case 2 0.5 ψ(t) −0.5

−1.5 0.0

2.0

4.0 t

6.0

8.0

FIGURE 6.45 Demonstrating the importance of zeroes at π. (a) The response of the FIR filter Gs(z) for two cases, and (b) and (c) the corresponding wavelet functions.

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that are three times differentiable and the third derivatives are Hölder continuous with Lipschitz constant equal to 0.4. The Hölder regularity index α is taken as a quantitative measure of regularity or smoothness of the function ψ(t). We sometimes say ψ(t) has regularity α. Qualitatively speaking, a function with a large Hölder index is regarded as more “smooth” or “well-behaved”. Because the dilation equations in the FIR case are finite summations, the Hölder indices of φ(t) and ψ(t) are identical. Some functions are differentiable an infinite number of times. That is, they belong to C ∞. Examples are et, sin t, and polynomials. C ∞ functions even exist that are compactly supported (i.e., have finite duration; they will not be discussed here).

Frequency-Domain Decay and Time-Domain Smoothness We can obtain time-domain smoothness of a certain degree by imposing certain conditions on the FT Ψ(ω). This is make possible by the fact that the rate of decay of Ψ(ω) as ω → ∞ (i.e., the asymptotic decay) governs the Hölder regularity index α of ψ(t). Suppose Ψ(ω) decays faster than (1 + ω)–(1+α): Ψ(ω ) ≤

c

(1 + ω )

1+ α + ∈

for all ω

(6.120)

for some c > 0, ∈ > 0. Then, Ψ(ω)(1+ω)α is bounded by the integrable function c/(1 + ω)1+, and is therefore (Lebesgue) integrable. Using standard Fourier theory it can be shown that this implies ψ(t) ∈ C α. In the wavelet construction of Section 6.11, which begins with a digital filter bank, the above decay of ψ(ω) can be accomplished by designing the digital filter Gs(e jω) such that it has a sufficient number of zeroes at ω = π. Thus, the decay in the frequency domain translates into regularity in the time domain. Similarly, one can regard time-domain decay as an indication of smoothness in frequency. When comparing two kinds of wavelets, we can usually compare them in terms of time domain regularity (frequency domain decay) and time domain decay (frequency domain smoothness). An extreme example is one in which ψ(t) is band-limited. This means that Ψ(ω) is zero outside the passband, and so the “decay” is the best possible. Correspondingly, the smoothness of ψ(t) is excellent; in fact, ψ(t) ∈ C ∞. However, the decay of ψ(t) may not be excellent (certainly it cannot be time-limited if it is band-limited). Return to the two familiar wavelet examples, the Haar wavelet (Fig. 6.12) and the bandpass wavelet (Figs. 6.9 and 6.11). We see that the Haar wavelet has poor decay in the frequency domain because Ψ(ω) decays only as ω–1. Correspondingly, the time-domain signal ψ(t) is not even continuous, hence, not differentiable.4 The bandpass wavelet, on the other hand, is band-limited, so the decay in frequency is excellent. Thus, ψ(t) ∈C ∞, but it decays slowly, behaving similarly to t–1 for large t. These two examples represent two extremes of orthonormal wavelet bases for L2. The game, therefore, is to construct wavelets that have good decay in time as well as good regularity in time. An extreme hope is where ψ(t) ∈C ∞, and has compact support as well. It can be shown that such ψ(t) can never give rise to an orthonormal basis, so we must strike a compromise between regularity in time and decay in time. Regularity and Decay in Early Wavelet Constructions In 1982, Stromberg showed how to construct wavelets in such a way that ψ(t) has exponential decay, and at the same time has arbitrary regularity (i.e., ψ(t) ∈C k for any chosen integer k). In 1985, Meyer constructed wavelets with band-limited ψ(t) [so ψ(t) ∈C ∞ as for the bandpass wavelet], but he also showed how to design this ψ(t) to decay faster than any chosen inverse polynomial, as t → ∞. It is true that ψ(t) is differentiable almost everywhere, but the discontinuities at the points t = 0, 0.5, 1.0 will be very noticeable if we take linear combinations such as Σ k,n ckn ψkn(t). 4

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Wavelet Transforms

ψ(t) 1 (a) Meyer wavelet

t −4

−2

2

4

ψ(t) 0.5 (b)

Battle– Lemarié wavelet 4

t

1

FIGURE 6.46 (a) An example of Meyer wavelet, and (b) an example of Battle–Lemarié wavelet.

Figure 6.46(a) shows an example of a Meyer wavelet; a detailed description of this wavelet can be found in [5]. In both of the above constructions the wavelets gave rise to orthonormal bases for L2. In 1987 and 1988, Battle and Lemarié independently constructed wavelets with similar properties as Stromberg’s wavelets, namely ψ(t) ∈C k for arbitrary k, and ψ(t) decays exponentially. Their construction is based on spline functions and an orthonormalization step, as described in Section 6.10. The resulting wavelets, while not compactly supported, decay exponentially and generate orthonormal bases. Figure 6.46(b) shows an example of the Battle–Lemarié wavelet. Table 6.1 gives a summary of the main features of these early wavelet constructions (first three entries). When these examples were constructed, the relation between wavelets and digital filter banks was not known. The constructions were not systematic or unified by a central theory. Moreover, it was not clear whether one could get a compactly supported (i.e., finite duration) wavelet ψ(t), which at the same time had arbitrary regularity (i.e., ψ(t) ∈C k for any chosen k), and generated an orthonormal wavelet basis. This was made possible for the first time when the relation between wavelets and digital filter banks was observed by Daubechies in [6]. Simultaneously and independently, Mallat invented the multiresolution framework and observed the relation between his framework, wavelets, and paraunitary digital filter banks (the CQF bank, Section 6.4). These discoveries have made the wavelet construction easy and

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TABLE 6.1

Summary of Several Types of Wavelet Bases for L2(R)

Type of Wavelet

Decay of ψ(t) in Time

Stromberg, 1982

Exponential

Meyer, 1985

Faster than any chosen inverse polynomial Exponential

Battle–Lemarié, 1987, 1988 (splines) Daubechies, 1988

Compactly supported

Regularity of ψ(t) in Time

Type of Wavelet Basis

ψ(t) ∈C k ; k can be chosen arbitrarily large ψ(t) ∈C ∞ (band limited)

Orthonormal

ψ(t) ∈C k ; k can be chosen arbitarily large ψ(t) ∈C α ; α can be chosen as large as we please

Orthonormal Orthonormal Orthonormal

systematic, as described in Sections 6.11 and 6.12. The way to obtain arbitrary wavelet regularity with this scheme is described next.

Time-Domain Decay and Time-Domain Regularity We now state a fundamental limitation which arises when trying to impose regularity and decay simul­ taneously [5]. Theorem 6.18: Vanishing Moments. Let {2k/2 ψ(2kt – n)}, –∞ ≤ k, n ≤ ∞ be an orthonormal set in L2. Suppose the wavelet ψ(t) satisfies the following properties: 1. ψ(t) ≤ c(1 + t)–(m+1+) for some integer m and some ∈ > 0; that is, the wavelet decays faster than (1 + t)–(m+1). 2. ψ(t) ∈ C m [i.e., ψ(t) differentiable m times], and the m derivatives are bounded.

∫

Then, the first m moments of ψ(t) are zero, that is, t i ψ(t )dt = 0 for 0 ≤ i ≤ m.

▫

Impossibility of Compact Support, Infinite Differentiability, and Orthonormality. Suppose we have an orthonormal wavelet basis such that ψ(t) is compactly supported, and infinitely differentiable [i.e., ψ(t) ∈ C∞]. Then all the conditions of Theorem 6.18 are satisfied. So the moments of ψ(t) are zero, and therefore ψ(t) = 0 for all t violating the unit-norm property of ψ(t). Thus, we cannot design compactly supported orthonormal wavelets which are infinitely differentiable; only a finite Hölder index can be accomplished. A similar observation can be made even when ψ(t) is not compactly supported as long as it decays faster than any inverse polynomial (e.g., exponential decay). The vanishing moment condition ∫t i ψ(t)dt = 0, 0 ≤ i ≤ m imples that the L2 - FT Ψ (ω) has m + 1 zeroes at ω = 0. This follows by using standard theorems on the L1 - FT [23].5 Thus, the first m derivatives of Ψ(ω) vanish at ω = 0. This implies a certain degree of flatness at ω = 0. Summarizing, we have the following result. Theorem 6.19, Flatness in Frequency and Regularity in Time: Suppose we have a compactly supported ψ(t) generating an orthonormal wavelet basis {2k/2 Ψ(2kt – n)}, and let ψ(t) ∈ Cm, with m derivatives bounded. Then, ψ(ω) has m + 1 zeroes at ω = 0. ▫ Return now to the wavelet construction technique described in Section 6.11. We started from a paraunitary FIR filter bank (Fig. 6.22(a)) and obtained the scaling function φ(t) and wavelet function ψ(t) as in (6.118) and (6.119). The FIR nature implies that ψ(t) has compact support (Section 6.12). With the mild conditions of Theorem 6.13 satisfied, we have an orthonormal wavelet basis for L2. We

5

Because ψ(t) ∈L2 and has compact support, ψ(t) ∈ L1 as well.

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see that if the wavelet ψ(t) has Hölder index α, it satisfies all the conditions of Theorem 6.19, where m is the integer part of α. Thus, ψ(ω) has m + 1 zeroes at ω = 0, but because Φ(0) ≠ 0 (Section 6.10), we conclude from the dilation equation Ψ(ω) = Hs(e jω/2)Φ(ω/2) that the high-pass FIR filter Hs(z) has m + 1 zeroes at ω = 0 (i.e., at z = 1). Using the relation Hs(e jω) = e jω Gs∗ (–e jω), we conclude that Gs(e jω) has m + 1 zeroes at ω = π; that is, the low-pass FIR filter Gs(z) has the form Gs(z) = (1 + z–1)m+1 F(z), where F(z) is FIR. Summarizing, we have the theorem below. Theorem 6.20, Zeroes at π and Regularity: Suppose we wish to design a compactly supported orthonorma wavelet basis for L2 by designing an FIR filter Gs(z) satisfying the conditions of Theorem 6.13. If ψ(t) must have the Hölder regularity index α then it is necessary that Gs(z) have the form Gs(z) = (1 + z–1)m+1 F(z), where F(z) is FIR, and m is the integer part of α. ▫ One zero at π is essential. From Theorem 6.10, we know that we must have Gs(e j0) = 1 for the infinite product (6.112a) to converge. Theorem 6.13 imposes further conditions that enable us to obtain an orthonormal wavelet basis for L2. One of these conditions is the power symmetric property Gs(e jω)2 + Gs(–e jω)2 = 1. Together with Gs(e j0) = 1, this implies Gs(e jπ) = 0. Thus, it is necessary to have at least one zero for Gs(e jω) at π. The filter that generates the Haar basis (Example 12) has exactly one zero at π, but the Haar wavelet ψ(t) is not even continuous. If we desire increased regularity (continuity, differen­ tiability, etc.), we need to put additional zeroes at π, as the above theorem shows. Design techniques for paraunitary filter banks do not automatically yield filters which have zeroes at π. This condition must be incorporated separately. The maximally flat filter bank solution (Section 6.4) does satisfy this property, and in fact even allows us to specify the number of zeroes at π.

Wavelets with Specified Regularity The fundamental connection between digital filter banks and continuous time wavelets, elaborated in the preceding sections, allows us to construct the scaling function φ(t) and the wavelet function ψ(t) with specified regularity index α. If Gs(z) has a certain number of zeroes at π, this translates into the Hölder regularity index α. What really matters is not only the number of zeroes at π, but also the order of the FIR filter Gs(z). For a given order N of the filter Gs(z), suppose we wish to put as many of its zeroes as possible at π. Let this number be K. What is the largest possible K? Not all N zeroes can be at π because we have imposed the power symmetric condition on Gs(z). The best we can do is to put all the unit circle zeroes ∆ at π. The power symmetric condition says that G(z) = G˜s(z)Gs(z) is a half-band filter. This filter has order 2N, with 2K zeroes at π. Because we wish to maximize K for fixed N, the solution for G(z) is the maximally flat FIR filter (Fig. 6.25), given in (6.45). As the filter in (6.45) has 2K zeroes at π and order 2N = 4K – 2, we conclude that K = (N + 1)/2. For example, if Gs(z) is a fifth-order power symmetric filter it can have at most three zeroes at π. The 20% Regularity Rule Suppose Gs(z) has been designed to be FIR power symmetric of order N, with the number K of zeroes at π adjusted to be maximum (i.e., K = (N + 1)/2). It can be shown that the corresponding scaling and wavelet functions have a Hölder regularity index α ≈ 0.2 K. This estimate is poor for small K, but improves as K grows. Thus, every additional zero at π contributes to ≈ 20% improvement in regularity. For K = 4 (i.e., seventh-order Gs(z)), we have α = 1.275, which means that the wavelet ψ(t) is once differentiable and the derivative is Hölder continuous with Lipschitz constant 0.275. For K = 10 [19th­ order Gs(z)] we have α = 2.9, so the wavelet ψ(t) is twice differentiable and the second derivative has Hölder regularity index 0.9. Design Procedure. The design procedure is therefore very simple. For a specified regularity index α, we can estimate K and hence N = 2K – 1. For this K, we compute the coefficients of the FIR half-band

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maximally flat filter G(z) using (6.45). From this, we compute a spectral factor Gs(z) of the filter G(z). Tables of the filter coefficients gs(n) for various values of N can be found in [5]. From the coefficients gs(n) of the FIR filter Gs(z), the compactly supported scaling and wavelet functions are fully determined via the dilation equations. These wavelets are called Daubechies wavelets and were first generated in [6]. Figure 6.45(c) is an example, generated with a ninth-order FIR filter Gs(z), where response is shown as case 2 in Fig. 6.45(a). The above regularity estimates, based on frequency domain behavior, give a single number α, which represents the regularity of ψ(t) for all t. It is also possible to define pointwise or local regularity of the function ψ(t) so that its smoothness can be estimated as a function of time t. These estimation methods, based on time domain iterations, are more sophisticated, but give a detailed view of the behavior of ψ(t). Detailed discussions on obtaining various kinds of estimates for regularity can be found in [5] and [26].

6.14 Concluding Remarks We introduced the WT, and studied its connection to filter banks and STFTs. A number of mathematical concepts such as frames and Riesz bases were reviewed and used later for a more careful study of wavelets. We introduced the idea of multiresolution analysis, and explained the connections both to filter banks and wavelets. This connection was then used to generate orthonormal wavelet bases from paraunitary filter banks. Such wavelets have compact support when the filter bank is FIR. The regularity or smoothness of the wavelet was quantified in terms of the Hölder exponent. We showed that we can achieve any specified Hölder exponent for compactly supported wavelets by restricting the low-pass filter of the FIR paraunitary filter bank to be a maximally flat power symmetric filter, with a sufficient number of zeroes at π.

Why Wavelets? Discussions comparing wavelets with other types of time-frequency transforms appear at several places in this chapter. Here is a list of these discussions: 1. Section 6.2 discusses basic properties of wavelets and gives an elementary comparison of wavelet basis with the Fourier basis. 2. Section 6.3 compares the WT with the STFT and shows the time-frequency tilings for both cases (e.g., see Figs. 6.18 and 6.20). 3. Section 6.9 gives a deeper comparison with the STFT in terms of stability properties of the inverse, existence of frames, etc. 4. Section 6.13 presents a comparison to the traditional filter bank design approach. In traditional designs, the appearance of zero(es) at π is not considered important. At the beginning of Section 6.13 (under “Why Regularity?”), we discuss the importance of these zeroes in wavelets as well as in tree-structured filter banks.

Further Reading The literature on wavelet theory and applications is enormous. This chapter is only a brief introduction, concentrating on one-dimensional orthonormal wavelets. Many results can be found on the topics of multidimensional wavelets, biorthogonal wavelets, and wavelets based on IIR filter banks. Two special issues of the IEEE Transactions have appeared on the topic thus far [27, 28]. Multidimensional wavelets are treated by several authors in the edited volume of [15], and the filter bank perspective can be found in the work by Kova˘cevic´ and Vetterli [27]. Advanced results on multidimensional wavelets can be found in [29]. Advanced results on wavelets constructed from M-channel filter banks can be found in the chapter by Gopinath and Burrus in the edited volume of [15], and in the work by Steffen et al. [28]. The reader can also refer to the collections of chapters in [15] and [16], and the many references therein.

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Acknowledgments The authors are grateful to Dr. Ingrid Daubechies, Princeton University, Princeton, NJ, for many useful e-mail discussions on wavelets. This work was supported in part by Office of Naval Research grant N00014-93-1-0231, Rockwell International, and Tektronix, Inc.

References [1] M. E. Van Valkenburg, Introduction to Modern Network Synthesis, New York: John Wiley & Sons, 1960. [2] A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing, Englewood Cliffs, NJ: Prentice Hall, 1989. [3] A. Grossman and J. Morlet, “Decomposition of Hardy functions into square integrable wavelets of constant shape,” SIAM J. Math. Anal., vol. 15, pp. 723–736, 1984. [4] Y. Meyer, Wavelets and Operators, Cambridge: Cambridge University Press, 1992. [5] I. Daubechies, Ten Lectures on Wavelets, SIAM, CBMS Series, Apr. 1992. [6] I. Daubechies, “Orthonormal bases of compactly supported wavelets,” Commun. Pure Appl. Math., vol. 41, pp. 909–996, Nov. 1988. [7] P. P. Vaidyanathan, Multirate Systems and Filter Banks, Englewood Cliffs, NJ: Prentice Hall, 1993. [8] M. Vetterli, “A theory of multirate filter banks,” IEEE Trans. Acoust. Speech Signal Process., vol. ASSP-35, pp. 356–372, Mar. 1987. [9] A. N. Akansu and R. A. Haddad, Multiresolution Signal Decomposition: Transforms, Subbands, and Wavelets, Orlando, FL: Academic Press, 1992. [10] H. S. Malvar, Signal Processing with Lapped Transforms, Norwood, MA: Artech House, 1992. [11] S. Mallat, “Multiresolution approximations and wavelet orthonormal bases of L2(R),” Trans. Am. Math. Soc., vol. 315, pp. 69–87, Sept. 1989. [12] C. E. Heil and D. F. Walnut, “Continuous and discrete wavelet transforms,” SIAM rev., vol. 31, pp. 628–666, Dec. 1989. [13] M. Vetterli and C. Herley, “Wavelets and filter banks,” IEEE Trans. Signal Process., vol. SP-40, 1992. [14] R. A. Gopinath and C. S. Burrus, “A tutorial overview of filter banks, wavelets, and interrelations,” Proc. IEEE Int. Symp. Circuits Syst., pp. 104–107, May 1993. [15] C. K. Chui, Vol. 1, An Introduction to Wavelets, and Vol. 2 (edited), Wavelets: A Tutorial in Theory and Applications, Orlando, FL: Academic Press, 1992. [16] J. J. Benedetto and M. W. Frazier, Wavelets: Mathematics and Applications, Boca Raton, FL: CRC Press, 1994. [17] J. B. Allen and L. R. Rabiner, “A unified theory of short-time spectrum analysis and synthesis,” Proc. IEEE, vol. 65, pp. 1558–1564, Nov. 1977. [18] M. J. T. Smith and T. P. Barnwell, III, “A procedure for designing exact reconstruction filter banks for tree structured subband coders,” Proc. IEEE Int. Conf. Acoust. Speech, Signal Proc., pp. 27.1.1–27.1.4, San Diego, CA, Mar. 1984. [19] F. Mintzer, “Filters for distortion-free two-band multirate filter banks,” IEEE Trans. Acoust., Speech Signal Process., vol. ASSP-33, pp. 626–630, June 1985. [20] P. P. Vaidyanathan, “Theory and design of M-channel maximally decimated quadrature mirror filters with arbitrary M, having perfect reconstruction property,” IEEE Trans. Acoustics, Speech Signal Process., vol. ASSP-35, pp. 476–492, Apr. 1987. [21] V. Belevitch, Classical Network Theory, San Francisco: Holden Day, 1968. [22] T. M. Apostol, Mathematical Analysis, Reading, MA: Addison-Wesley, 1974. [23] W. Rudin, Real and Complex Analysis, New York: McGraw-Hill, 1966. [24] R. M. Young, An Introduction to Nonharmonic Fourier Series, New York: Academic Press, 1980.

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[25] R. J. Duffin and A. C. Schaeffer, “A class of nonharmonic Fourier series,” Trans. Am. Math. Soc., vol. 72, pp. 341–366, 1952. [26] O. Rioul, “Sample regularity criteria for subdivision schemes,” SIAM J. Math. Anal., vol. 23, pp. 1544–1576, Nov. 1992. [27] Special issue on wavelet transforms and multiresolution signal analysis, IEEE Trans. Info. Theory, vol. 38, Mar. 1992. [28] Special issue on wavelets and signal processing, IEEE Trans. Signal Process, vol. 41, Dec. 1993. [29] A. Cohen and I. Daubechies, “Non-separable bidimensional wavelet bases,” Rev. Mat. IberoAm., vol. 9, pp. 51–137, 1993.

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7 Graph Theory

7.1 7.2 7.3 7.4

Introduction Basic Concepts Cuts, Circuits, and Orthogonality Incidence, Circuit, and Cut Matrices of a Graph

7.5

Orthogonality Relation and Ranks of Circuit and Cut Matrices Spanning Tree Enumeration Graphs and Electrical Networks Tellegen’s Theorem and Network Sensitivity Computation Arc Coloring Theorem and the No-Gain Property

Incidence Matrix • Cut Matrix • Circuit Matrix

Krishnaiyan Thulasiraman University of Oklahoma

7.6 7.7 7.8 7.9

7.1 Introduction Graph theory had its beginning in Euler’s solution of what is known as the Konigsberg Bridge problem. Kirchhoff developed the theory of trees in 1847 as a tool in the study of electrical networks. This was the first application of graph theory to a problem in physical science. Electrical network theorists have since played a major role in the phenomenal advances of graph theory that have taken place. A compre­ hensive treatment of these developments may be found in [1]. In this chapter, we develop most of those results which form the foundation of graph theoretic study of electrical networks. Our development of graph theory is self-contained, except for the definitions of standard set-theoretic operations and elementary results from matrix theory. We wish to note that the ring sum of two sets S1 and S2 refers to the set consisting of all those elements which are in S1 or in S2 but not in both S1 and S2.

7.2 Basic Concepts A graph G = (V, E) consists of two sets: a finite set V = (v1, v2 ,…, vn) of elements called vertices and a finite set E = (e1, e2 ,…, em ) of elements called edges. Each edge is identified with a pair of vertices. If the edges of G are identified with ordered pairs of vertices, then G is called a directed or an oriented graph. Otherwise G is called an undirected or a nonoriented graph. Graphs are amenable for pictorial repre­ sentations. In a pictorial representation each vertex is represented by a dot and each edge is represented by a line segment joining the dots associated with the edge. In directed graphs, we assign an orientation or direction to each edge. If the edge is associated with the ordered pair (vi , vj ), then this edge is oriented from vi to vj . If an edge e connects vertices vi and vj , then it is denoted by e = (vi , vj ). In a directed graph, (vi , vj ) refers to an edge directed from vi to vj. A graph and a directed graph are shown in Fig. 7.1. Unless explicitly stated, the term “graph” may refer to an undirected graph or to a directed graph. The vertices vi and vj associated with an edge are called the end vertices of the edge. All edges having the same pair of end vertices are called parallel edges. In a directed graph, parallel edges refer to edges

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FIGURE 7.1 (a) An undirected graph; (b) a directed graph.

connecting the same pair of vertices vi and vj oriented in the same direction from vi to vj or from vj to vi . For instance, in the graph of Fig. 7.1(a), the edges connecting v1 and v2 are parallel edges. In the directed graph of Fig. 7.1(b) the edges connecting v3 and v4 are parallel edges. However, the edges connecting v1 and v2 are not parallel edges because they are not oriented the same direction. If the end vertices of an edge are not distinct, then the edge is called a self-loop. The graph of Fig. 7.1(a) has one self-loop and the graph of Fig. 7.1(b) has two self-loops. An edge is said to be incident on its end vertices. In a directed graph the edge (vi , vj ) is said to be incident out of vi and is said to be incident into vj . Vertices vi and vj are adjacent if an edge connects vi and vj . The number of edges incident on a vertex vi is called the degree of vi and is denoted by d(vi). In a directed graph din(vi) refers to the number of edges incident into vertex vi, and it is called the in-degree of vi . dout(vi) refers to the number of edges incident out of vertex vi, and it is called the out-degree of vi . If d(vi) = 0, then vi is called an isolated vertex. If d(vi) = 1, then vi is called a pendant vertex. A selfloop at a vertex vi is counted twice while computing d(vi). As an example, in the graph of Fig. 7.1.(a), d(v1) = 3, d(v4) = 3, and v5 is an isolated vertex. In the directed graph of Fig. 7.1(b) din(v1) = 3, dout(v1) = 2. Note that in a directed graph, for every vertex vi ,

d ( vi ) = din ( vi ) + dout ( vi ) Theorem 1:

1. The sum of the degrees of the vertices of a graph G is equal to 2m, where m is the number of edges of G. 2. In a directed graph with m edges, the sum of the in-degrees and the sum of the out-degrees are both equal to m. PROOF.

1. Because each edge is incident on two vertices, it contributes 2 to the sum of the degrees of G. Hence, all edges together contribute 2m to the sum of the degrees. 2. Proof follows if we note that each edge is incident out of exactly one vertex and incident into exactly one vertex. ▫ Theorem 2: The number of vertices of odd degree in any graph is even. PROOF. By Theorem 1, the sum of the degrees of the vertices is even. Thus, the sum of the odd degrees must be even. This is possible only if the number of vertices of odd degree is even. ▫ Consider a graph G = (V, E). The graph G′ = (V′, E′) is a subgraph of G if V ′ ⊆ V and E′ ⊆ E. If every vertex in V ′ is an end vertex of an edge in E ′, then G ′ is called the induced subgraph of G on E′. As an example, a graph G and two subgraphs of G are shown in Fig. 7.2.

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FIGURE 7.2 (a) Graph G; (b) subgraph of G; (c) an edge-induced subgraph of G.

FIGURE 7.3 (a) An undirected graph; (b) a directed graph.

In a graph G, a path P connecting vertices vi and vj is an alternating sequence of vertices and edges starting at vi and ending at vj with all vertices except vi and vj being distinct. In a directed graph, a path P connecting vertices vi and vj is called a directed path from vi to vj if all the edges in P are oriented in the same direction as we traverse P from vi toward vj. If a path starts and ends at the same vertex, it is called a circuit.1 In a directed graph, a circuit in which all the edges are oriented in the same direction is called a directed circuit. It is often convenient to represent paths and circuits by the sequence of edges representing them. For example, in the undirected graph of Fig. 7.3.(a) P: e1, e2, e3, e4 is a path connecting v1 and v5 and C: e1, e2, e3, e4, e5, e6 is a circuit. In the directed graph of Fig. 7.3(b) P: e1, e2, e7, e5 is a directed path and C: e1, e2, e7, e6 is a directed circuit. Note that e7, e5, e4, e1, e2 is a circuit in this directed graph, although it is not a directed circuit. Two vertices vi and vj are said to be connected in a graph G if a path in G connects vi and vj . A graph G is connected if every pair of vertices in G is connected; otherwise, it is a disconnected graph. For example, the graph G in Fig. 7.4(a) is connected, but the graph in Fig. 7.4(b) is not connected. A connected subgraph G′ = (V′, E′) of a graph G = (V, E ) is a component of G if adding to G′ an edge e ∈ E – E′ results in a disconnected graph. Thus, a connected graph has exactly one component. For example, the graph in Fig. 7.4(b) is not connected and has two components. 1

In electrical network theory literature, the term loop is also used to refer to a circuit.

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FIGURE 7.4 (a) A connected graph; (b) a disconnected graph.

FIGURE 7.5 (a) Graph G; (b) a tree of graph G; (c) a spanning tree of G; (d) a 2-tree of G.

A tree is a graph that is connected and has no circuits. Consider a connected graph G. A subgraph of G is a spanning tree2 of G if the subgraph is a tree and contains all the vertices of G. A tree and a spanning tree of the graph of Fig. 7.5(a) are shown in Fig. 7.5(b) and (c), respectively. The edges of a spanning tree T are called the branches of T. Given a spanning tree of a connected graph G, the cospanning tree2 relative to T is the subgraph of G induced by the edges that are not present in T. For example, the cospanning tree relative to the spanning tree T of Fig. 7.5(c) consists of the edges e3, e6, and e7. The edges of a cospanning tree are called chords. A subgraph of a graph G is a k-tree of G if the subgraph has exactly k components and has no circuits. For example, a 2-tree of the graph of Fig. 7.5(a) is shown in Fig. 7.5(d). If a graph has k components, then a forest of G is a spanning subgraph that has k components and no circuits. Thus, each component of the forest is a spanning tree of a component of G. A graph G and a forest of G are shown in Fig. 7.6. 2In electrical network theory literature, the terms tree and cotree are usually used to mean spanning tree and cospanning tree, respectively.

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FIGURE 7.6 (a) Graph G; (b) a forest of G.

FIGURE 7.7 (a) Directed graph G; (b) a directed spanning tree of G with root v1.

Consider a directed graph G. A spanning tree T of G is called a directed spanning tree with root vi if T is a spanning tree of G, and din(vi) = 0 and din(vj) = 1 for all vj ≠ vi. A directed graph G and a directed spanning tree with root v1 are shown in Fig. 7.7. It can easily be verified that, in a tree, exactly one path connects any two vertices. Theorem 3: A tree on n vertices has n – 1 edges. PROOF. Proof is by induction on the number of vertices of the tree. Clearly, the result is true if a tree has one or two vertices. Assume that the result is true for trees on n ≥ 2 or fewer vertices. Consider now a tree T on n + 1 vertices. Pick an edge e = (vi, vj) in T. Removing e from T would disconnect it into exactly two components T1 and T2 . Both T1 and T2 are trees. Let n1 and m1 be the number of vertices and the number of edges in T1, respectively. Similarly n2 and m2 are defined. Then, by the induction hypothesis

m1 = n1 − 1 and

m2 = n2 −1 © 2003 by CRC Press LLC

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Thus, the number m of edges in T is given by

m = m1 + m2 + 1 = ( n1 −1) + ( n2 −1) + 1 = n1 + n2 − 1 = n −1 ▫

This completes the proof of the theorem.

If a connected graph G has n vertices, m edges, and k components, then the rank ρ and nullity µ of G are defined as follows: ρ (G ) = n − k

(7.1)

µ (G ) = m − n + k

(7.2)

Clearly, if G is connected, then any spanning tree of G has ρ = n – 1 branches and µ = m – n + 1 chords. We conclude this subsection with the following theorems. Proof of these theorems may be found in [2]. ▫ Theorem 4: A tree on n ≥ 2 vertices has at least two pendant vertices.

▫

Theorem 5: A subgraph of an n-vertex connected graph G is a spanning tree of G if and only if the subgraph has no circuits and has n – 1 edges. ▫ Theorem 6: If a subgraph G′ of a connected graph G has no circuits then there exists a spanning tree of G that contains G′. ▫

7.3 Cuts, Circuits, and Orthogonality We introduce here the notions of a cut and a cutset and develop certain results which bring out the dual nature of circuits and cutsets. Consider a connected graph G = (V, E) with n vertices and m edges. Let V1 and V2 be two mutually – disjoint nonempty subsets of V such that V = V1 ∪ V2. Thus, V2 = V 1, the complement of V1 in V. V1 and V2 are also said to form a partition of V. Then the set of all those edges which have one end vertex in V1 and the other in V2 is called a cut of G and is denoted by 〈V1, V2 〉. As an example, a graph G and a cut 〈V1, V2 〉 of G are shown in Fig. 7.8. The graph G′ which results after removing the edges in a cut will have at least two components and so will not be connected. G′ may have more than two components. A cutset S of a connected graph G is a minimal set of edges of G such that removal of S disconnects G into exactly two components. Thus, a cutset is also a cut. Note that the minimality property of a cutset implies that no proper subset of a cutset is a cutset. Consider a spanning tree T of a connected graph G. Let b be a branch of T. Removal of the branch b disconnects T into exactly two components, T1 and T2. Let V1 and V2 denote the vertex sets of T1 and T2, respectively. Note that V1 and V2 together contain all the vertices of G. We can verify that the cut 〈V1, V2 〉 is a cutset of G and is called the fundamental cutset of G with respect to branch b of T. Thus, for a given connected graph G and a spanning tree T of G, we can construct n – 1 fundamental cutsets, one for each branch of T. As an example, for the graph shown in Fig. 7.8, the fundamental cutsets with respect to the spanning tree T = [e1, e2, e6, e8] are Branch e1 : Branch e 2 : © 2003 by CRC Press LLC

(e1,e3 ,e 4 ) (e 2 ,e3 ,e 4 ,e5 )

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FIGURE 7.8 (a) Graph G; (b) cut 〈V1, V2〉 of G.

Branch e6 : Branch e8 :

(e6 ,e 4 ,e5 ,e7 ) (e8 ,e7 )

Note that the fundamental cutset with respect to branch b contains b. Furthermore, the branch b is not present in any other fundamental cutset with respect to T. Next, we identify a special class of circuits of a connected graph G. Again, let T be a spanning tree of G. Because exactly one path exists between any two vertices of T, adding a chord c to T produces a unique circuit. This circuit is called the fundamental circuit of G with respect to chord c of T. Note again that the fundamental circuit with respect to chord c contains c, and the chord c is not present in any other fundamental circuit with respect to T. As an example, the set of fundamental circuits with respect to the spanning tree T = (e1, e2, e6, e8) of the graph shown in Fig. 7.8 is Chord e3 : Chord e 4 : Chord e5 : Chord e7 :

(e3 ,e1,e 2 ) (e 4 ,e1,e 2 ,e6 ) (e5 ,e 2 ,e6 ) (e7 , e8 , e6 )

We now present a result that is the basis of what is known as the orthogonality relationship. Theorem 7: A circuit and a cutset of a connected graph have an even number of common edges. PROOF. Consider a circuit C and a cutset S = 〈V1, V2 〉 of G. The result is true if C and S have no common edges. Suppose that C and S possess some common edges. Let us traverse the circuit C starting from a vertex, e.g., v1 and V1. Because the traversing should end at v1, it is necessary that every time we encounter an edge of S leading us from V1 to V2 an edge of S must lead us from V2 back to V1. This is possible only if S and C have an even number of common edges. ▫ The above result is the foundation of the theory of duality in graphs. Several applications of this simple result are explored in different parts of this chapter. A comprehensive treatment of the duality theory and its relationship to planarity may be found in [2]. The following theorem establishes a close relationship between fundamental circuits and fundamental cutsets. © 2003 by CRC Press LLC

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Theorem 8: 1. The fundamental circuit with respect to a chord of a spanning tree T of a connected graph consists of exactly those branches of T whose fundamental cutsets contain the chord. 2. The fundamental cutset with respect to a branch of a spanning tree T of a connected graph consists of exactly those chords of T whose fundamental circuits contain the branch. PROOF. Let C be the fundamental circuit of a connected graph G with respect to a chord c of a spanning tree T of G. Let C contain, in addition to the chord c, the branches b1, b2,…, bk of T. Let Si be the fundamental cutset with respect to branch bi. We first show that each Si , 1 ≤ i ≤ k contains c. Note that bi is the only branch common to Si and C, and c is the only chord in C. Because by Theorem 7, Si and C must have an even number of common edges, it is necessary that Si contains c. Next, we show that no other fundamental cutset of T contains c. Suppose the fundamental cutset Sk+1 with respect to some branch bk+1 of T contains c. Then c will be the only edge common to Sk+1 and C, contradicting Theorem 7. Thus the chord c is present only in those cutsets defined by the branches b1, b2,…, bk . The proof for item 2 of the theorem is similary to that of item 1. ▫

7.4 Incidence, Circuit, and Cut Matrices of a Graph The incidence, circuit, and cut matrices are coefficient matrices of Kirchhoff ’s equations which describe an electrical network. We develop several properties of these matrices that have proved useful in the study of electrical networks. Our discussions are mainly in the context of directed graphs. The results become valid in the case of undirected graphs if addition and multiplication are in GF(2), the field of integers modulo 2. (Note that 1 + 1 = 0 in this field.)

Incidence Matrix Consider a connected directed graph G with n vertices and m edges and have no self-loop. The all-vertex incidence matrix Ac = [aij] of G has n rows, one for each vertex, and m columns, one for each edge. The element aij of Ac is defined as follows:  1, if the jth edge is incident out of the ith vertex ,  a ij =  −1, if the jth edge is incident into the ith vertex, 

 0 , if the jth edge is not incident on the i th vertex. A row of Ac will be referred to as an incidence vector. As an example, for the directed graph shown in Fig. 7.9, the matrix Ac is: e1 v1  1  v 2 −1  A c = v3  0  v4  0  v 5  0

© 2003 by CRC Press LLC

e2

e3

e4

e5

e6

0

0

0

0

1

1

0

0

0

0

−1

1

0

1

0

0

−1

−1

0

−1

0

0

1

−1

0

e7 −1  0  0  0  1

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FIGURE 7.9 A directed graph.

From the definition of Ac it should be clear that each column of this matrix has exactly two nonzero entries, one +1 and one –1, and therefore, we can obtain any row of Ac from the remaining rows. Thus, rank ( Ac ) ≤ n − 1

(7.3)

An (n – 1) rowed submatrix of Ac is referred to as an incidence matrix of G. The vertex which corresponds to the row of Ac that is not in A is called the reference vertex of A. Theorem 9: The determinant of an incidence matrix of a tree is ±1. PROOF. Proof is by induction on the number m of edges in the tree. We can easily verify that the result is true for any tree with m ≤ 2 edges. Assume that the result is true for all trees having m ≥ 2 or fewer edges. Consider a tree T with m + 1 edges. Let A be the incidence matrix of T with reference vertex vr . Because, by Theorem 4, T has at least two pendant vertices, we can find a pendant vertex vi ≠ vr . Let (vi, vj) be the only edge incident on vi . Then, the remaining edges form a tree T1. Let A1 be the incidence matrix of T1 with vertex vr as reference. Now let us rearrange the rows and columns of A so that the first n – 2 rows correspond to the vertices in T1 (except vr) and the first n – 1 columns correspond to the edges of T1. Then, we have A1 A3   A=  0 ±1 So det A = ±(det A1 )

(7.4)

A1 is the incidence matrix of T1 and T1 has m edges, it follows from the induction hypothesis that detA1 = ±1. Hence the theorem. ▫ Because a connected graph has at least one spanning tree, it follows from the above theorem that any incidence matrix A of a connected graph has a nonsingular submatrix of order n – 1. Therefore, rank ( Ac ) ≥ n − 1

(7.5)

Combining (7.3) and (7.5) yields the following theorem. Theorem 10: The rank of any incidence matrix of a connected directed graph G is equal to n – 1, the rank of G. ▫

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Cut Matrix – – Consider a cut 〈Va, Va 〉 in a connected directed graph G with n vertices and m edges. Recall that 〈Va, Va 〉 – consists of all those edges connecting vertices in Va to those in Va . This cut may be assigned on orientation – – – – from Va to Va or from Va to Va. Suppose the orientation of 〈Va ,Va 〉 is from Va to Va . Then the orientation – of an edge (vi, vj) is said to agree with the cut orientation if vi ∈ Va, and vj ∈ Va . The cut matrix Qc = [qij] of G has m columns, one for each edge, and has one row for each cut. The element qij is defined as follows:  1,     qij = – 1,     0 ,

if the jth edge is in the ith cut and its orientation agrees with the cut orientation, if the jth edge is in the ith cut and its orientation does not agree with the cut orientation, if the jth edge is not in the ith cut.

Each row of Qc is called a cut vector. The edges incident on a vertex form a cut. Thus, it follows that the matrix Ac is a submatrix of Qc . Next we identify another important submatrix of Qc . Recall that each branch of a spanning tree T of a connected graph G defines a fundamental cutset. The submatrix of Qc corresponding to the n – 1 fundamental cutsets defined by T is called the funda­ mental cutset matrix Q f of G with respect to T. Let b1, b2, …, bn – 1 denote the branches of T. Let us assume that the orientation of a fundamental cutset is chosen so as to agree with that of the defining branch. Suppose we arrange the rows and the columns of Qf so that the ith column corresponds to branch bi, and the ith row corresponds to the fundamental cutset defined by bi . Then, the matrix Qf can be displayed in a convenient form as follows:

[

Q f = U Q fc

]

(7.6)

where U is the unit matrix of order n – 1 and its columns correspond to the branches of T. As an example, the fundamental cutset matrix of the graph in Fig. 7.9. with respect to the spanning tree T = (e1, e2, e5, e6) is: e1 e1 1  e 2 0 Qf =  e5 0  e6 0

e2

e5 e6

e3

e4

e7

0

0

0

−1

−1

0

0

−1

−1

0

1

0

0

−1

0

0

1

1

1

−1  −1  −1  0

1

It is clear from (7.6) that the rank of Qf is n – 1. Hence, rank (Qc ) ≥ n − 1

(7.7)

Circuit Matrix Consider a circuit C in a connected directed graph G with n vertices and m edges. This circuit can be traversed in one of two directions, clockwise or counterclockwise. The direction we choose for traversing © 2003 by CRC Press LLC

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C is called the orientation of C. If an edge e = (vi, vj) directed from vi to vj is in C, and if vi appears before vj as we traverse C in the direction specified by its orientation, then we say that the orientation of e agrees with the orientation of C. The circuit matrix Bc = [bij] of G has m coloumns, one for each edge, and has one row for each circuit in G. The element bij is defined as follows:  1,     bij = – 1,     0 ,

if the jth edge is in the ith circuit and its orientation agrees with the circuit orientation, if the jth edge is in the ith circuit and its orientation does not agree with the circuit orientation, if the jth edge is not in the ith circuit.

Each row of Bc is called a circuit vector. The submatrix of Bc corresponding to the fundamental circuits defined by the chords of a spanning tree T is called the fundamental circuit matrix Bf of G with respect to the spanning tree T. Let c1, c2, …, cm – n+1 denote the chords of T. Suppose we arrange the columns and the rows of Bf so that the ith row corresponds to the fundamental circuit defined by the chord ci , and the ith column corresponds to the chord ci . If, in addition, we choose the orientation of a fundamental circuit to agree with the orientation of the defining chord, we can write Bf as

[ ]

B f = U B ft

(7.8)

where U is the unit matrix of order m – n + 1, and its columns correspond to the chords of T. As an example, the fundamental circuit matrix of the graph shown in Fig. 7.9 with respect to the tree T = (e1, e2, e5, e6) is given below: e3

e4

e7

e1

e2

e5

e6

e3  1  Bf = e4  0  e7  0

0

0

1

1

0

−1  −1  0

1

0

1

1

1

0

1

1

1

1

It is clear from (7.8) that the rank of Bf is m – n + 1. Hence, rank( Bc ) ≥ m − n + 1

(7.9)

7.5 Orthogonality Relation and Ranks of Circuit and Cut Matrices Theorem 11: If a cut and a circuit in a directed graph have 2k edges in common, then k of these edges have the same relative orientation in the cut and in the circuit, and the remaining k edges have one orientation in the cut and the opposite orientation in the circuit. – PROOF. Consider a cut 〈Va, Va 〉 and a circuit C in a directed graph. Suppose we traverse C starting from – – a vertex in Va. Then, for every edge e1 that leads from Va to Va , an edge e2 leads from Va to Va. Suppose the orientation of e1 agrees with the orientation of the cut and that of the circuit. Then we can easily © 2003 by CRC Press LLC

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FIGURE 7.10 Relative orientations of an edge in a cut and a circuit.

verify that e2 has one orientation in the cut and the opposite orientation in the circuit (see Fig. 7.10). On the other hand, we can also verify that if e1 has one orientation in the cut and the opposite orientation in the circuit, the e2 will have the same relative orientation in the circuit and in the cut. This proves the theorem. ▫ Next we prove the orthogonality relation. Theorem 12: If the columns of the circuit matrix Bc and the columns of the cut matrix Qc are arranged in the same edge order, then BcQct = 0

(7.10)

PROOF: Each entry of the matrix Bc Q ct is the inner product of a circuit vector and a cut vector. Suppose a circuit and a cut have 2k edges in common. The inner product of the corresponding vectors is zero, because by Theorem 11, this product is the sum of k 1’s and k –1’s. ▫ The orthogonality relation is a profound result with interesting applications in electrical network theory. Consider a connected graph G with m edges and n vertices. Let Qf be the fundamental cutset matrix and Bf be the fundamental circuit matrix of G with respect to a spanning tree T. If we write Qf and Bf as in (7.6) and (7.8), then using the orthogonality relation we get B f Qtf = 0 that is, U  =0 t   fc 

[B U ] Q ft

that is, B ft = − Qtfc

(7.11)

Using (7.11), each circuit vector can now be expressed as a linear combination of the fundamental circuit vectors. Consider a circuit vector β = [β1 , β 2 ,K, β ρ| β ρ+1 K β m ] of G where ρ = n – 1, is the rank of G. Then, again by the orthogonality relation we have U  βQtf = β1 , β 2 ,K,βρ βρ +1 Kβm   = 0 Qtfc   

[

© 2003 by CRC Press LLC

]

(7.12)

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Therefore,

[β , β ,K,β ] = − [β ,β Kβ ]Q = [β ,β Kβ ] B 1

ρ

2

ρ +1

ρ +1

ρ+ 2

m

ρ+ 2

m

t fc

ft

So,

[β , β ,K,β ] = [β 1

2

m

ρ +1

][ Kβ ]B

,βρ + 2 Kβm B ft

[

= βρ +1 ,βρ + 2

m

U

]

(7.13)

f

Thus, any circuit vector can be expressed as a linear combination of the fundamental circuit vectors. So

( )

rank( Bc ) ≤ rank B f = m − n + 1 Combining the above with (7.9) we obtain rank( Bc ) = m − n + 1

(7.14)

Starting from a cut vector and using the orthogonality relation, we can prove in an exactly similar manner that

( )

rank(Qc ) ≤ rank Q f = n − 1 Combining the above with (7.7) we get rank(Qc ) = n − 1 Summarizing, we have the following theorem. Theorem 13: For a connected graph G with m edges and n vertices rank( Bc ) = m − n + 1 rank(Qc ) = n − 1

▫

We wish to note from (7.13) that the vector corresponding to a circuit C can be expressed as an appropriate linear combination of the fundamental circuit vectors corresponding to the chords present in C. Similarly, the vector corresponding to a cut can be expressed as an appropriate linear combination of the fundamental cut vectors corresponding to the branches present in the cut. Because modulo 2 addition of two vectors corresponds to the ring sum of the corresponding subgraphs, we have the following results for undirected graphs. Theorem 14: Let G be a connected undirected graph. 1. Every circuit can be expressed as a ring sum of the fundamental circuits with respect to a spanning tree. 2. Every cut can be expressed as a ring sum of the fundamental cutsets with respect to a spanning tree. ▫ We can easily verify the following consequences of the orthogonality relation: 1. A linear relationship exists among the columns of the cut matrix (also of the incidence matrix), which correspond to the edges of a circuit. 2. A linear relationship exists among the columns of the circuit matrix, which correspond to the edges of a cut. © 2003 by CRC Press LLC

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The following theorem characterizes the submatrices of Ac , Qc and Bc which correspond to spanning trees and cospanning trees. Proof follows from the above results and may be found in [2]. Theorem 15: Let G be a connected graph G with n vertices, and m edges. 1. A square submatrix of order n – 1 of Qc (also of Ac) is nonsingular iff the edges corresponding to the columns of this submatrix form a spanning tree of G. 2. A square submatrix of order m – n + 1 of Bc is nonsingular iff the edges corresponding to the columns of this submatrix form a cospanning tree of G. ▫

7.6 Spanning Tree Enumeration Here, we first establish a formula for counting the number of spanning trees of an undirected graph. We then state a generalization of this result for the case of a directed graph. These formulas have played key roles in the development of topological formulas for electrical network functions. A detailed development of topological formulas for network functions may be found in Swamy and Thulasiraman [1]. The formula for counting the number of spanning trees of a graph is based on Theorem 9 and a result in matrix theory, known as the Binet–Cauchy theorem. A major of a matrix is a determinant of a maximum order. Consider a matrix P of order p × q and a matrix Q of order q × p, with p ≤ q. The majors of P and Q are of order p. If a major of P consists of columns i1, i2,…, ip , the corresponding major of Q is formed by rows i1, i2,…, ip of Q. For example, if

1 P= 2

−2

−2

3

−1

4  2

and

−2

4

3

2

 −5   2 Q=  −2   3

0  1  2  1 

then for the major

of P 2

1

3

1

is the corresponding major of Q. The Binet–Cauchy theorem is stated next. Proof of this theorem may be found in Hohn [3]. Theorem 16: If P is a p × q matrix and Q is a q × p matrix, with p ≤ q, then det( PQ) = Σ ( product of the corresponding majors of P and Q).

▫

Theorem 17: Let G be a connected undirected graph and A an incidence matrix of a directed graph obtained by assigning orientations to the edges of G. Then

( )

τ (G ) = det AAt where τ(G) is the number of spanning trees of G. © 2003 by CRC Press LLC

(7.15) ▫

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FIGURE 7.11 (a) An undirected graph G; (b) directed graph obtained after assigning arbitrary orientations to the edges of G.

PROOF: By the Binet–Cauchy theorem, we have

( )

(

)

det AAt = Σ product of the corresponding majors of A and At .

(7.16)

Recall from Theorem 15 that a major of A is nonzero iff the edges corresponding to the columns of the major form a spanning tree of G. Also, the corresponding majors of A and At have the same value equal to 0, 1, or –1 (Theorem 9). Thus, each nonzero term in the sum on the right-hand side of (7.16) has the value 1, and it corresponds to a spanning tree and vice versa — hence the theorem. ▫ For example, consider the undirected graph G shown in Fig. 7.11(a). Assigning arbitrary orientations to the edges of G, we obtain the directed graph in Fig. 7.11(b). If A is the incidence matrix of this directed graph with vertex v4 as reference vertex then it can be verified that  3  AAt = −1  −1

−1 2 0

−1  0  2

and det(AAt ) = 8. Thus, G has eight spanning trees. An interesting and useful interpretation of the matrix AAt now follows. Let v1, v2,…, vn be the vertices of an undirected graph G. The degree matrix K = [kij ] of G is an n × n matrix defined as follows. − p,  kij =  d  (v i ),

if i ≠ j and p parallel edges connect v i and v j if i = j

We may easily verify that K = Ac Atc , and that it is independent of the choice of orientations for the edges of G. Also, if vi is the reference vertex, AAt is obtained by removing row i and column i of K. In other words, det(AAt) is the (i, i) cofactor of K. It then follows from Theorem 17 that all of the cofactors of K are equal to the number of spanning trees of G. Thus, Theorem 17 may be stated in the following form originally presented by Kirchhoff [4]. Theorem 18: All the cofactors of the degree matrix of an undirected graph G have the same value equal to the number of spanning trees of G. ▫ Consider a connected undirected graph G. Let A be the incidence matrix of G with reference vertex vn. Let τi,n denote the number of spanning 2-trees of G such that the vertices vi and vn are in different components of these spanning 2-trees. Also, let τij,n denote the number of spanning 2-trees such that © 2003 by CRC Press LLC

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vertices vi and vj are in the same component, and vertex vn is in a different component of these spanning 2-trees. If ∆ij denotes the (i, j) cofactor of (AAt), then we have the following result, proof of which may be found in [2]. Theorem 19: For a connected graph G, τ i ,n = ∆ ii

(7.17)

τ ij , n = ∆ ij

(7.18) ▫

Consider next a directed graph G = (V, E) without self-loops and with V = (v1, v2,…, vn). The indegree matrix K = [kij] of G is an (n × n) matrix defined as follows: − p  kij = 

din (v i ),

if i ≠ j and p parallel edges are directed from v i to vj if i = j

The following result is due to Tutte [5]. Proof of this result may also be found in [2]. Theorem 20: Let K be the in-degree matrix of a directed graph G without self-loops. Let the ith row of K correspond to vertex vi . Then the number τd of directed spanning trees of G having vr as root is given by τ d = ∆ rr

(7.19) ▫

where ∆rr is the (r, r) co-factor of K.

Note the similarity between Theorem 18 and Theorem 20. To illustrate Theorem 20, consider the directed graph G shown in Fig. 7.12. The in-degree matrix K and G is  1  K = −1   0

−1 2 −1

−2  −1  3

Then  2 ∆11 =  −1

−1 =5 3

The five directed spanning trees of G with vertex v1 as root are (e1, e5), (e1, e6), (e1, e3), (e4, e5), and (e4, e6).

FIGURE 7.12 A directed graph G. © 2003 by CRC Press LLC

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7.7 Graphs and Electrical Networks An electrical network is an interconnection of electrical network elements such as resistances, capaci­ tances, inductances, voltage and current sources, etc. Each network element is associated with two variables, the voltage variable v(t) and the current variable i(t). We also assign reference directions to the network elements (see Fig. 7.13) so that i(t) is positive whenever the current is in the direction of the arrow, and v(t) is positive whenever the voltage drop in the network element is in the direction of the arrow. Replacing each element and its associated reference direction by a directed edge results in the directed graph representing the network. For example, a simple electrical network and the corresponding directed graph are shown in Fig. 7.14. The physical relationship between the current and voltage variables of a network element is specified by Ohm’s law. For voltage and current sources, the voltage and current variables are required to have specified values. The linear dependence among the voltage variables in the network and the linear dependence among the current variables are governed by Kirchhoff ’s voltage and current laws. Kirchhoff ’s Voltage Law (KVL): The algebraic sum of the voltages around any circuit is equal to zero. Kirchhoff ’s Current Law (KCL): The algebraic sum of the currents flowing out of a node is equal to zero.

FIGURE 7.13 A network element with reference convention.

FIGURE 7.14 (a) An electrical network N; (b) directed graph representation of N. © 2003 by CRC Press LLC

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As an example, the KVL equation for the circuit 1, 3, 5 and the KCL equation for the vertex b in the graph of Fig. 7.14 are Circuit: 1, 3, 5

v1 + v 3 + v 5 = 0

Vertex b:

−i1 + i2 + i 3 = 0

It can easily be seen that KVL and KCL equations for an electrical network N can be conveniently written as Ac I e = 0

(7.20)

BcVe = 0

(7.21)

and

where Ac and Bc are, respectively, the incidence and circuit matrices of the directed graph representing N, and Ie and Ve are, respectively, the column vectors of element currents and voltages in N. Because each row in the cut matrix Qc can be expressed as a linear combination of the rows of the matrix, in (7.20) we can replace Ac by Qc . Thus, we have: KCL:

Qc I e = 0

(7.22)

KVL:

BeVe = 0

(7.23)

From (7.22), we can see that KCL can also be stated as: The algebraic sum of the currents in any cut of N is equal to zero. If a network N has n vertices, m elements, and its graph is connected then there are only (n − 1) linearly independent cuts and only (m − n+1) linearly independent circuits (Theorem 13). Thus, in writing KVL and KCL equations we need to use only, Bf , a fundamental circuit matrix and Qf , a fundamental cutset matrix, respectively. Thus, we have KCL:

Q f Ie = 0

(7.24)

KVL:

B f Ve = 0

(7.25)

We note that the KCL and the KVL equations depend only on the way the network elements are interconnected and not on the nature of the network elements. Thus, several results in electrical network theory are essentially graph theoretic in nature. Some of these results and their usefulness in electrical network analysis are presented in the remainder of this chapter. In the following a network N and its directed graph are both denoted by N. Theorem 21: Consider an electrical network N. Let T be a spanning tree of N, and let Bf and Qf denote the fundamental circuit and the fundamental cutset matrices of N with respect to T. If Ie and Ve are the column vectors of element currents and voltages and Ic and Vt are, respectively, the column vector of currents associated with the chords of T and the column vector of voltages associated with the branches of T, then

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Loop Transformation: I e = Btf I c

(7.26)

Cutset Transformation: Ve = Qtf Vt

(7.27)

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PROOF. From Kirchhoff ’s laws, we have Q f Ie = 0

(7.28)

B f Ve = 0

(7.29)

and

Let us partition Ie and Ve as I c  Ie =   It  and Vc  Ve =   Vt  where the vectors that correspond to the chords and branches of T are distinguished by the subscripts c and t, respectively. Then (7.28) and (7.29) can be written as

[ Q

fc

I c  U  =0 It 

]

(7.30)

and Vc 

[ U B ] V  = 0 ft

(7.31)

 t

Recall (7.11) that B ft = −Qtfc Then, we get from (7.30) It = −Q fc I c = Btft I c Thus, U  I e =  t  I c = Btf I c B ft    This establishes the loop transformation.

Starting from (7.31), we can show in a similar manner that

Ve = Qtf Vt thereby establishing the cutset transformation.

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▫

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In the special case in which the incidence matrix A is used in place of the fundamental cutset matrix, the cutset transformation (7.27) is called the node transformation. The loop, cutset, and node trans­ formations have been extensively employed to develop different methods of network analysis. The loop method of analysis develops a system of network equations which involve only the chord currents as variables. The cutset (node) method of analysis develops a system of equations involving only the branch (node) voltages as variables. Thus, the loop and cutset (node) methods result in systems of equations involving m − n+1 and n − 1 variables, respectively. In the mixed-variable method of analysis, which is essentially a combination of both the loop and cutset methods, some of the independent variables are currents and the others are voltages. The minimum number of variables required in the mixed-variable method of analysis is determined by what is known as the principal partition of a graph introduced by Kishi and Kajitani in a classic paper [6]. Ohtsuki, Ishizaki, and Watanabe [7] discuss several issues relating to the mixed-variable method of analysis. A detailed discussion of the principal partition of a graph and the different methods of network analysis including the state-variable method may be found in [1].

7.8 Tellegen’s Theorem and Network Sensitivity Computation Here, we first present a simple and elegant theorem due to Tellegen [8]. The proof of this theorem is essentially graph theoretic in nature and is based on the loop and the cutset transformations, (7.26) and (7.27), and the orthogonality relation (Theorem 12). Using this theorem, we develop the concept of the adjoint of a network and its application in network sensitivity computations. ˆ such that the graphs associated with them are Theorem 22: Consider two electrical networks, N and N, ˆ respectively, and let I and Λ be the identical. Let Ve and ψe denote the element voltage vectors of N and N, e e corresponding element current vectors. Then, Vet Λ e = 0 I et ψ e = 0 ˆ ), then PROOF. If Bf and Qf are the fundamental circuit and cutset matrices of N (and hence also of N from the loop and cutset transformations, we obtain Ve = Qtf Vt and Λ e = Btf Λ c So

(

)

Vet Λ e = Vtt Q f Btf Λ c = 0, by Theorem 12 Proof of the second part follows in a similar manner.

▫

The adjoint network was introduced by Director and Rohrer [9], and our discussion is based on their work. A more detailed discussion may be found in [1]. Consider a lumped, linear time-invariant network N. We assume, without loss of generality, that N is ˆ be a 2-port network that is topologically equivalent to N. In other words, the a 2-port network. Let N ˆ ˆ are denoted by the same graph of N is identical to that of N. The corresponding elements of N and N © 2003 by CRC Press LLC

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FIGURE 7.15 (a) A 2-port network N; (b) adjoint network Nˆ of N.

ˆ so that N ˆ in conjunction with N can be used in symbol. Our goal now is to define the elements of N computing the sensitivities of network functions of N. Let Ve and Ie denote, respectively, the voltage and the current associated with the element e in N, and ψe and λe denote, respectively, the voltage and the current associated with the corresponding element e ˆ . Also, V and I , i = 1, 2, denote the voltage and current variables associated with the ports of N, in N i i ˆ (see Fig. 7.15). and ψi and λ i , i = 1, 2, denote the corresponding variables for the ports of N ˆ Applying Tellegen’s theorem to N and N, we get V1λ1 + V2λ 2 =

∑V λ

e

(7.32)

I1ψ1 + I 2 ψ 2 = ∑ I e ψ e

(7.33)

e

e

and

e

ˆ and the perturbed Suppose we now perturb the values of elements of N and apply tellegen’s theorem to N network N:

(V1 + ∆V1 )λ1 + (V2 + ∆V2 )λ 2 = ∑e (Ve + ∆Ve )λ e

(7.34)

(I1 + ∆I1 )ψ1 + (I 2 + ∆I 2 )ψ 2 = ∑e (Ie + ∆Ie )ψ e

(7.35),

and

where ∆V and ∆I represent the changes in the voltage and current which results as a consequence of the perturbation of the element values in N. Subtracting (7.32) from (7.34) and subtracting (7.33) from (7.35), ∆V1λ1 + ∆V2λ 2 =

∑ ∆V λ e

e

(7.36)

e

(7.37)

e

and ∆I1ψ1 + ∆I 2 ψ 2 =

∑ ∆I ψ e

e

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Subtracting (7.37) from (7.36) yields

(∆V1λ1 − ∆I1ψ1 ) + (∆V2λ 2 − ∆I 2ψ 2 ) = ∑ (∆Ve λ e − ∆Ie ψ e )

(7.38)

e

ˆ for every element in N so that each term in the We wish to define the corresponding element of N summation on the right-hand side of (7.38) reduces to a function of the voltage and current variables and the change in value of the corresponding network element. We illustrate this for resistance elements. Consider a resistance element R in N. For this element, we have VR = RI R

(7.39)

(VR + ∆VR ) = (R + ∆R)(I R + ∆I R )

(7.40)

Suppose we change R to ∆R, then

Neglecting second-order terms, (7.40) simplifies to VR + ∆VR = RI R + R∆I R + I R ∆R

(7.41)

∆VR = R∆ I R + I R ∆R

(7.42)

Subtracting (7.39) from (7.41),

Now using (7.42) the terms in (7.38) corresponding to the resistance elements of N can be written as

∑[Rλ

R

− ψ R ∆I R + I R λ R ∆R

]

(7.43)

ψψRR == RRλ λ RR

(7.44)

R

If we now choose

then (7.43) reduces to

∑ I λ ∆R R

R

(7.45)

R

ˆ and the changes in resistance which involves only the network variables in N (before perturbation) and N ˆ corresponding to a values. Equation (7.44) is the relation for a resistance. Therefore, the element in N resistance element of value R in N is also a resistance of value R. ˆ corresponding to other types of Proceeding in a similar manner we can determine the element of N ˆ so obtained is called network elements (inductance, capacitance, controlled sources, etc.) The network N the adjoint of N. A table defining adjoint elements corresponding to different types of network elements may be found in [1]. We now illustrate the application of the adjoint network in the computation of the sensitivity of a network function. Note that the sensitivity of a network function F with respect to a parameter x is a measure of the effect on F of an incremental change in x. Computing this sensitivity essentially involves determining ∂F/∂x. For the sake of simplicity, consider the resistance network shown in Fig. 7.16(a). Let us assume that resistance R is perturbed from its nominal value of 3Ω. Assume that no changes occur in the values of the other resistance elements. We wish to compute ∂F/∂R where F is the open-circuit voltage ratio, that is, © 2003 by CRC Press LLC

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FIGURE 7.16 (a) A 2-port network N; (b) adjoint network Nˆ .

F=

V2 V1

I2=0

In other words, to compute F, we connect a voltage source of value V1 = 1 across port 1 of N and opencircuit port 2 of N (so that I2 = 0). So, ∆V1 = 0 and ∆I2 = 0 and (7.38) reduces to −∆I1ψ1 + ∆V2λ 2 = I R λ R ∆R

(7.46)

Now we need to determine ∆V2 as a function of ∆R. This could be achieved if we set ψ1 = 0 and λ2 = 1 ˆ . Connect a current source of value λ = 1 across port 2 and short circuit port for the adjoint network N 2 ˆ ˆ defined as above, 1 of N. The resulting adjoint network is shown in Fig. 7.16(b). With port variables of N (7.46) reduces to ∆V2 = I R λ R ∆ R Thus, ∂F ∂R = ∂V2 ∂R = I R λ R ˆ shown in Fig. 7.16. Thus, in general, computing where IR and λR are the currents in the networks N and N ˆ under appropriate the sensitivity of a network function essentially reduces to the analysis of N and N excitations at their ports. Note that we do not need to express the network function explicitly in terms of network elements, nor do we need to calculate partial derivatives. For the example under consideration, we calculate IR = 1/12 A and λR = –7/12 A with the result that ∂F/∂R = –7/144. A further discussion of the adjoint network and related results may be found in Section 7.3. © 2003 by CRC Press LLC

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7.9 Arc Coloring Theorem and the No-Gain Property We know derive a profound result in graph theory, the arc coloring theorem for directed graphs, and discuss its application in establishing the no-gain property of resistance networks. In the special case of undirected graphs the arc coloring theorem reduces to the “painting” theorem. Both of these theorems (Minty [10]) are based on the notion of painting a graph. Given an undirected graph with edge set E, a painting of the graph is a partitioning of E into three subsets, R, G, and B, such that |G| = 1. We may consider the edges in the set R as being “painted red,” edge in G as being “painted green” and the edges in B as being “painted blue.” Theorem 23: For any painting of a graph, there exists a circuit C consisting of the green edge and no blue edges, or a cutset C ∗ consisting of the green edge and no red edges. PROOF. Consider a painting of the edge set E of a graph G. Assuming that there does not exist a required circuit, we shall establish the existence of a required cutset. Let E ′ = R ∪ G and T ′ denote a spanning forest of the subgraph induced by E′, containing the green edge. (Note that the subgraph induced by E′ may not be connected). Then, construct a spanning tree T of G such that T ′ ⊆ T . Now consider any red edge y that is not in T ′, and hence not in T. Because the fundamental circuit of y with respect to T is the same as the fundamental circuit of y with respect to T ′, this circuit consists of no blue edges. Furthermore, this circuit will not contain the green edge, for otherwise a circuit consisting of the green edge and no blue edges would exist contrary to our assumption. Thus, the fundamental circuit of a red edge with respect to T does not contain the green edge. Then, it follows from Theorem 8 that the fundamental cutset of the green edge with respect to T contains no red edges. Thus, this cutset satisfies the requirements of the theorem. ▫ A paining of a directed graph with edge set E is a partitioning of E into three sets R, G, and B, and the distinguishing of one element of the set G. Again, we may regard the edges of the graph as being colored red, green, or blue with exactly one edge of G being colored dark green. Note that the dark green edge is also to be treated as a green edge. Next, we state and prove Minty’s arc coloring theorem. Theorem 24: For any painting of a directed graph exactly one of the following is true. 1. A circuit exists containing the dark green edge, but no blue edges, in which all the green edges are similarly oriented. 2. A cutset exists containing the dark green edge, but no red edges, in which all the green edges are similarly oriented. PROOF. Proof is by induction on the number of green edges. If only one green edge exists, then the result will follow from Theorem 23. Assume then that the result is true when the number of green edges is m ≥ 1. Consider a painting in which m + 1 edges are colored green. Pick a green edge x other than the dark green edge (see Fig. 7.17). Color the edge x red. In the resulting painting we find m green edges. If a cutset of type 2 is now found, then the theorem is proved. On the other hand if we color the edge x blue and in the resulting painting a circuit of type 1 exists, then the theorem is proved. Suppose neither occurs. Then, using the induction hypothesis we have following: 1. A cutset of type 2 exists when x is colored blue. 2. A circuit of type 1 exists when x is colored red. Now let the corresponding rows of the circuit and cutset matrices be

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FIGURE 7.17 Painting of a directed graph.

dg

R

B

G

x

Cutset

+1

00L0 0

1 − 1L01

111L0

?

Circuit

+1

−11L0 − 1

0 0L00

011L0

?

Here, we have assumed, without loss of generality, that +1 appears in the dark green position of both rows. By the orthogonality relation (Theorem 7.12) the inner product of these two row vectors is zero. No contribution is made to this inner product from the red edges or from the blue edges. The contribution from the green edges is a non-negative integer p. The dark green edge contributes 1 and the edge x contributes an unknown integer q which is 0, 1, or –1. Thus, we have 1 + p + q = 0. This equation is satisfied only for p = 0 and q = – 1. Therefore, in one of the rows, the question mark is +1 and in the other it is –1. The row in which the question mark is 1 corresponds to the required circuit or cutset. Thus, either statement 1 or 2 of the theorem occurs. Both cannot occur simultaneously because the inner product of the corresponding circuit and cutset vectors will then be nonzero. ▫ Theorem 25: Each edge of a directed graph belongs to either a directed circuit or to a directed cutset, but no edge belongs to both. (Note: A cutset is a directed cutset if all its edges are similarly oriented.) PROOF. Proof will follow if we apply the arc coloring theorem to a painting in which all the edges are colored green and the given edge is colored dark green. ▫ We next present an application of the arc coloring theorem in the study of electrical networks. We prove what is known as the no-gain property of resistance networks. Our proof is the result of the work of Wolaver [11] and is purely graph theoretic in nature. Theorem 26: In a network of sources and (linear/nonlinear) positive resistances, the magnitude of the current through any resistance with nonzero voltage is not greater than the sum of the magnitudes of the currents through the sources. PROOF: Let us eliminate all the elements with zero voltage by considering them to be short-circuits and then assign element reference directions so that all element voltages are positive.

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Consider a resistance with nonzero voltage. Thus, no directed circuit can contain this resistance, for if such a directed circuit were present, the sum of all the voltages in the circuit would be nonzero, contrary to Kirchhoff ’s voltage law. It then follows from Theorem 25 that a directed cutset contains the resistance under consideration. Pick a directed cutset that contains the considered resistance. Let the current through this resistance be i0. Let R be the set of all other resistances in this cutset and let S be the set of all sources. Then, applying Kirchhoff ’s current law to the cutset, we obtain i0 +

∑ i + ∑ ± i = 0 k

k∈R

s

(7.47)

s∈S

Because all the resistances and voltages are positive, every resistance current is positive. Therefore, we can write the above equation as i0 +

∑ i + ∑ ±i = 0

(7.48)

∑ m i ≤ ∑ i

(7.49)

k

k∈R

s

s∈S

and so i0 ≤

s

s∈S

Thus follows the theorem.

s

s∈S

▫

The following result is the dual of the above theorem. Proof of this theorem follows in an exactly dual manner, if we replace current with voltage, voltage with current, and circuit with cutset in the proof of the above theorem. Theorem 27: In a network of sources and (linear/nonlinear) positive resistances, the magnitude of the voltage across any resistance is not greater than the sum of the voltages across all the sources. ▫ Chua and Green [12] used the arc coloring theorem to establish several properties of nonlinear networks and nonlinear multiport resistive networks.

References [1] M. N. S. Swamy and K. Thulasiraman, Graphs, Networks and Algorithms, New York: Wiley-Interscience, 1981. [2] K. Thulasiraman and M. N. S. Swamy, Graphs: Theory and Algorithms, New York: Wiley-Interscience, 1992. [3] F. E. Hohn, Elementary Matrix Algebra, New York: Macmillan, 1958. [4] G. Krichhoff, “Uber die Auflosung der Gleichungen auf welche mon bei der untersuchung der linearen Verteilung galvanischer strome gefuhrt wind,” Ann. Phys. Chem., vol. 72, pp. 497–508, 1847. [5] W. T. Tutte, “The dissection of equilateral triangles into equilateral triangles,” Proc. Cambr. Philos. Soc., vol. 44, pp. 203–217, 1948. [6] G. Kishi and Y. Kajitani, “Maximally distant trees and principal partition of a linear graph,” IEEE Trans. Circuit Theory, vol. CT-15, pp. 247–276, 1968. [7] T. Ohtsuki, Y. Ishizaki, and H. Watanabe, “Topological degrees of freedom and mixed analysis of electrical networks,” IEEE Trans. Circuit Theory, vol. CT-17, pp. 491–499, 1970.

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[8] B. D. H. Tellegen, “A general network theorem with applications,” Philips Res. Rep., vol. 7, pp. 259–269, 1952. [9] S. W. Director and R. A. Rohrer, “Automated network design—the frequency domain case,” IEEE Trans. Circuit Theory, vol. CT-16, pp. 330–337, 1969. [10] G. J. Minty, “On the axiomatic foundations of the theories of directed linear graphs, electrical networks and network programming,” J. Math. Mech., vol. 15. pp. 485–520, 1966. [11] D. H. Wolaver, “Proof in graph of the ‘no-gain’ property of resistor networks,” IEEE Trans. Circuit Theory, vol. CT-17, pp. 436–437, 1970. [12] L. O. Chua and D. N. Green, “Graph-theoretic properties of dynamic nonlinear networks,” IEEE Trans. Circuit Theory, vol. CAS-23, pp. 292–312, 1976.

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8 Signal Flow Graphs

Krishnaiyan Thulasiraman University of Oklahoma

8.1 8.2 8.3 8.4

Introduction Adjacency Matrix of a Directed Graph Coates’ Gain Formula Mason’s Gain Formula

8.1 Introduction Signal flow graph theory is concerned with the development of a graph theoretic approach to solving a system of linear algebraic equations. Two closely related methods proposed by Coates [1] and Mason [2, 3] have appeared in the literature and have served as elegant aids in gaining insight into the structure and nature of solutions of systems of equations. In this chapter, we develop these two methods. Our development follows these methods closely [4]. An extensive discussion of signal flow theory may be found in [5]. Applications of signal flow theory in the analysis and synthesis electrical networks may be found in Sections III and IV. Coates’ and Mason’s methods may be viewed as generalizations of a basic theorem in graph theory due to Harary [6], which provides a formula for finding the determinant of the adjacency matrix of a directed graph. Thus, our discussion begins with the development of this theorem. For graph theoretic terminology, the reader may refer to Chapter 7.

8.2 Adjacency Matrix of a Directed Graph Consider a directed graph G = (V, E) with no parallel edges. Let V = {v1, . . . , vn}. The adjacency matrix M = [mij] of G is an n × n matrix defined as follows: 1,  mij =  0,

( )

if v i , v j ∈E otherwise

The graph in Fig. 8.1 has the following adjacency matrix: v1 v1 1  v 2 0  M = v 3 1  v 4 1

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v2 1

v3 1

1

0

0

0

1

1

v4 0  0  1  1

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FIGURE 8.1 The graph G.

In the following, we shall develop a topological formula for det M. Toward this end, we introduce some basic terminology. A 1-factor of a directed graph G is a spanning subgraph of G in which the indegree and the out-degree of every vertex are both equal to 1. It is easy to see that a 1-factor is a collection of vertex-disjoint directed circuits. Because a self-loop at a vertex contributes 1 to the in-degree and 1 to the out-degree of the vertex, a 1-factor may have some self-loops. As an example, the three 1-factors of the graph of Fig. 8.1 are illustrated in Fig. 8.2. A permutation ( j1, j2, . . . , jn) of integers 1, 2, . . . , n is even (odd) if an even (odd) number of interchanges are required to rearrange it as (1, 2, . . . , n). The notation 1, 2,K, n     j1 , j 2 ,K, jn  is also used to represent the permutation ( j1, j2, . . . , jn ). As an example, the permutation (4, 3, 1, 2) is odd because it can be rearranged as (1, 2, 3, 4) using the following sequence of interchanges: 1. Interchange 2 and 4. 2. Interchange 1 and 2. 3. Interchange 2 and 3. For a permutation ( j ) = ( j1, j2, . . ., jn), εj1, j2, …, jn , is defined as equal to 1, if ( j ) is an even permutation; otherwise, εj1, j2, …, jn , is equal to –1. Given an n × n square matrix X = [xij ], we note that det X is given by det X =

∑ε

j1 , j2 , j3 ,..., jn

x1 j1 , x 2 j2 L x njn

( j)

where the summation Σ(j) is over all permutations of 1, 2, . . . , n [7]. The following theorem is due to Harary [6]. Theorem 1: Let Hi , i = 1, 2, . . . , p be the 1-factors of an n-vertex directed graph G. Let Li denote the number of directed circuits in Hi, and let M denote the adjacency matrix of G. Then,

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FIGURE 8.2 The three 1-factors of the graph of Fig. 8.1.

det M = (−1)

n

p

∑ (−1)

Li

i =1

PROOF. From the definition of a determinant, we have det M =

∑ε ( j)

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j1 , j2 , K, jn

m1 j1 ⋅ m2 j2 ⋅⋅⋅mnjn

(8.1)

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Proof will follow if we establish the following: 1. Each nonzero term m1j1 · m2j2 L mnjn corresponds to a 1-factor of G, and conversely, each 1-factor of G corresponds to a non-zero term m1j1 · m2j2 L mnjn. 2. εj1, j2, …, jn = (–1)n+L if the 1-factor corresponding to a nonzero m1j1 · m2j2 L mnjn has L directed circuits. A nonzero term m1j1 · m1j2 L mnjn corresponds to the set of edges (v1, vj1), (v2, vj2) … (vn, vjn). Each vertex appears exactly twice in this set, once as an initial vertex and once as a terminal vertex of a pair of edges. Therefore, in the subgraph induced by these edges, for each vertex its in-degree and its outdegree are both equal to 1, and this subgraph is a 1-factor of G. In other words, each non-zero term in the sum in (8.1) corresponds to a 1-factor of G. The fact that each 1-factor of G corresponds to a non­ zero term m1j1 · m2j2 L mnjn is obvious. Regarding εj1, j2, …, jn, consider a directed circuit C in the 1-factor corresponding to m1j1 · m2j2 L mnjn. Without loss of generality, assume that C consists of the w edges

(v1, v 2 ), (v 2 ,v3 ), K, (v w ,v1 ) It is easy to see that the corresponding permutation (2, 3, . . ., w, 1) can be rearranged as (1, 2, … , w) using w – 1 interchanges. If the 1-factor has L directed circuits with lengths w1, …, wL, the permutation ( j1, …, jn) can be rearranged as (1, 2, …, n) using

(w1 − 1) + (w 2 − 1) + L + (w L − 1) = n − L interchanges. So, ε j1 , j2 , jn = (−1)

n+L

▫

.

As an example, for the 1-factors (see Fig. 8.2) of the graph of Fig. 8.1, the corresponding Li are L1 = 3, L2 = 3, and L3 = 2. So, the determinant of the adjacency matrix of the graph of Fig. 8.1 is

(−1)4[(−1)3 + (−1)3 + (−1)2 ] = − 1 Consider next a weighted directed graph G in which each edge (vi, vj) as associated with a weight wij . Then we may define the adjacency matrix M = [mij] of G as follows:

(

w  ij mij =  0,

)

if v i ,v j ∈E otherwise

Given a subgraph H of G, let us define weight w (H ) of H as the product of the weights of all edges in H. If H has no edges, then we define w(H) = 1. The following result is an easy generalization of Theorem 1. Theorem 2: The determinant of the adjacency matrix of an n-vertex directed graph G is given by det M = (−1)

n

∑ (−1)

LH

w ( H ),

H

where H is a 1-factor, w(H) is the weight of H, and LH is the number of directed circuits in H. © 2003 by CRC Press LLC

▫

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8.3 Coates’ Gain Formula Consider a linear system described by the equation AX = Bx n+1

(8.2)

where A is a nonsingular n × n matrix, X is a column vector of unknown variables x1, x2, …, xn, B is a column vector of elements b1, b2, …, bn and xn+1 is the input variable. It is well known that

∑

n

xk = x n+1

i =1

bi ∆ ik (8.3)

det A

where ∆ik is the (i, k) cofactor of A. To develop Coates’ topological formulas for the numerator and the denominator of (8.3), let us first augment the matrix A by adding –B to the right of A and adding a row of zeroes at the bottom of the resulting matrix. Let this matrix be denoted by A′. The Coates flow graph1 Gc(A′), or simply the Coates graph, associated with matrix A′ is a weighted directed graph whose adjacency matrix is the transpose of the matrix A′. Thus, Gc(A′) has n + 1 vertices x1, x2, …, xn+1, and if aji … ≠ 0, Gc(A′) has an edge directed from xi to xj with weight aji. Clearly, the Coates graph Gc(A) associated with matrix A can be obtained from Gc(A′) by removing the vertex xn+1. As an example, for the following system of equations  3  −1   3

−2 2 −2

1  0  2

x1   3     x 2  =  1  x 4     x   − 2   3

(8.4)

the matrix A′ is  3  −1 A′ =   3   0

−2

1

2

0

−2

2

0

0

−3  −1  2  0

The Coates graphs Gc(A′) and Gc(A) are depicted in Fig. 8.3. Because a matrix and its transpose have the same determinant value, and because A is the transpose of the adjacency matrix of Gc(A), we obtain the following result from Theorem 2. Theorem 3: If a matrix A is nonsingular, then det A = (−1)

n

∑ (−1)

LH

w(H )

(8.5)

H

where H is a 1-factor of Gc(A), w(H) is the weight of H and LH is the number of directed circuits in H. ▫ To derive a similar expression for the sum in the numerator of (8.3), we first define the concept of a 1-factorial connection. A 1-factorial connection Hij from xi to xj in Gc(A ) is a spanning subgraph of G that contains a directed path P from xi to xj and a set of vertex-disjoint directed circuits, which include all the 1

In network and systems theory literature, the Coates graph is referred to as a flow graph.

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FIGURE 8.3 (a) The Coates graph Gc(A′); (b) the graph Gc(A); (c) A-factorial connection H4,3 of the graph Gc(A′).

vertices of Gc(A) other than those that lie on P. Similarly, a 1-factorial connection of Gc(A′) can be defined.

As an example, a 1-factorial connection from x4 to x3 of the graph Gc(A′) of Fig. 8.3(a) is also in Fig. 8.3(c).

Theorem 4: Let Gc(A′) be the Coates graph associated with an n × n matrix A. Then,

1. ∆ ii = (−1)

n−1

∑ (−1)

LH

w(H )

H

2. ∆ ij = (−1)

n−1

∑ (−1) w (H ) L′H

ij

Hij

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i≠ j

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where H is a 1-factor in the graph obtained by removing vertex xi from Gc(A), Hij is a 1-factorial connection in Gc(A) from vertex xi to vertex xj , and LH and L′H are the numbers of directed circuits in H and Hij , respectively. PROOF. 1. Note that ∆ii is the determinant of the matrix obtained from A by removing its row i and column i. Also, the Coates graph of the resulting matrix can be obtained from Gc(A) by removing vertex xi. Proof follows from these observations and Theorem 3. 2. Let Aα denote the matrix obtained from A by replacing its jth column by a column of zeroes, except for the element in row i, which is 1. Then it is easy to see that ∆ ij = det Aα Now, the Coates graph Gc(Aα ) can be obtained from Gc(A) by removing all edges incident out of vertex xj and adding an edge directed from xj to xi with weight 1. Then from Theorem 3, we get ∆ ij = det Aα

∑ (−1)

= (−1)

n

Lα

(8.6)

w(Hα )

Hα

where Hα is a 1-factor of Gc(Aα ) and Lα is the number of directed circuits in Hα. Consider now a 1-factor Hα in Gc(Aα ). Let C be the directed circuit of Hα containing xi. Because in Gc(Aα ), (xj , xi) is the only edge incident out of xj, it follows that xj also lies in C. If we remove the edge (xj , xi) from Hα we get a 1-factorial connection, Hij . Furthermore, L′H = Lα – 1 and w(Hij) = w(Hα ) because (xj , xi) has weight equal to 1. Thus, each Hα corresponds to a 1-factorial connection Hij of Gc(Aα ) with w(Hα ) = w(Hij) and L′H = Lα – 1. The converse of this is also easy to see. Thus, in (8.6) we can replace Hα by Hij and Lα by (L′H + 1). Then we obtain ∆ ij = (−1)

n−1

∑ (−1) w(H ) L′H

ij

▫

Hij

Having shown that each ∆ij can be expressed in terms of the weights of the 1-factorial connections Hij in Gc(A), we now show that Σbi∆ik can be expressed in terms of the weights of the 1-factorial connections Hn+1, k in Gc(A′). First, note that adding the edge (xn+1, xi) to Hik results in a 1-factorial connection Hn+1,k , with w(Hn+1,k) = – bi w(Hik). Also, Hn+1,k has the same number of directed circuits as Hik . Conversely, from each Hn+1, k that contains the edge (xn+1, xi) we can construct a 1-factorial connection Hik satisfying w(Hn+1,k) = – bi w(Hik). Also, Hn+1, k and the corresponding Hik will have the same number of directed circuits. Thus, a one-to­ one correspondence exists between the set of all 1-factorial connections Hn+1, k in Gc(A′ ) and the set of all 1-factorial connections in Gc(A) of the form Hik such that each Hn+1, k and the corresponding Hik have the same number of directed circuits and satisfy the relation w (Hn+1,k) = – bi w(Hik). Combining this result with Theorem 4, we get n

∑b ∆ i

i =1

= (−1)

n

ik

∑ (−1) w(H ) LH ′

n+1, k

(8.7)

Hn + 1,k

where the summation is over all 1-factorial connections, Hn+1,k in Gc(A′ ), and L′H is the number of directed circuits in Hn+1, k . From (8.5) and (8.7) we get the following theorem.

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Theorem 5: If the coefficient matrix A is nonsingular, then the solution of (8.2) is given by

∑ (−1) w(H ) ∑ (−1) w(H ) LH ′

xk = x n+1

n+1, k

Hn +l ,k

(8.8)

LH

H

for k = 1, 2, …, n, where Hn+1, k is a 1-factorial connection of Gc(A′) from vertex xn+1 to vertex xk, H is a ▫ 1-factor of Gc(A), and L′H and LH are the numbers of directed circuits in Hn+1,k and H, respectively. Equation (8.8) is the called Coates’ gain formula. We now illustrate Coates’ method by solving the system (8.4) for x2/x4. First, we determine the 1-factors of the Coates’ graph Gc(A) shown in Fig. 8.3(b). These 1-factors, along with their weights, are listed below. The vertices enclosed within parentheses represent a directed circuit. 1-Factor H

Weight w(H )

LH

12 6 4 2

3 2 2 1

(x1) (x2) (x3) (x2) (x1, x3) (x3) (x1, x2) (x1, x2, x3)

From the above we get the denominator in (8.8) as

∑ (−1)

LH

w ( H ) = (−1) ⋅12 + (−1) ⋅ 6 + (−1) ⋅ 4 + (−1) ⋅ 2 = −4 3

2

2

1

H

To compute the numerator in (8.8) we need to determine the 1-factorial connections H4, 2 in the Coates graph Gc(A′), shown in Fig. 8.3(a). They are listed below along with their weights. The vertices in a directed path from x4 to x2 are given within parentheses. 1-Factorial Connection H4,2

w(H4,2)

(x4 , x1, x2) (x3) (x4 , x2) (x61) (x3) (x4 , x2) (x13, x3) (x4 , x3, x1,2x2)

L′H

6

1 2 1 0

– – –

From the above we get the numerator in (8.8) as

∑ (−1) w(H ) = (−1) ⋅ 6 + (−1) (−6) + (−1) (−3) + (−1) (−2) = −11 LH ′

1

2

4, 2

H 4, 2

Thus, we get x 2 11 = x4 4

8.4 Mason’s Gain Formula Consider again the system of equations AX = Bx n+1 © 2003 by CRC Press LLC

1

0

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FIGURE 8.4 (a) The Mason graph Gm(A′); (b) the Mason graph Gm(A).

We can rewrite the above as

(

n

) ∑a

x j = a jj +1 x j +

x − b j x n+1 ,

jk k

j = 1, 2, K, n,

x n+1 = x n+1

(8.9)

k=1 k≠ j

Letting X′ denote the column vector of the variables x1, x2, … xn+ 1, and Un+1 denote the unit matrix of order n, we can write (8.9) in matrix form as follows:

( A′ + U n+1 )X ′ = X ′

(8.10)

where A′ is the matrix defined earlier in Section 8.3. The Coates graph Gc(A′ + Un+1) is called the Mason’s signal flow graph or simply the Mason graph2 associated with A′ and it is denoted by Gm(A′). The Mason graph Gm(A) is defined in a similar manner. The Mason graphs Gm(A′ ) and Gm(A) associated with the system (8.4) are illustrated in Fig. 8.4. Mason’s graph elegantly represents the flow of variables in a system. If we associate each vertex with a variable and if an edge is directed from xi to xj, then we may consider the variable xi as contributing (aji xi) to the variable xj. Thus, xj is equal to the sum of the products of the weights of the edges incident into vertex xj and the variables corresponding to the vertices from which these edges emanate. Note that, to obtain the Coates graph Gc(A) from the Mason graph Gm(A), we simply subtract one from the weight of each self-loop. Equivalently, we may add at each vertex of the Mason graph a self­ 2

In network and systems theory literature, Mason graphs are usually referred to as signal flow graphs.

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loop of weight –1. Let S denote the set of all such loops of weight –1 added to construct the Coates graph Gc from the Mason graph Gm(A). Consider now the Coates graph Gc constructed as above and a 1-factor H in Gc having j self-loops from the set S. If H has a total of LQ + j directed circuits, then removing the j self-loops from H will result in a subgraph Q of Gm(A), which is a collection of LQ vertex disjoint directed circuits. Also, w ( H ) = (−1) w (Q) j

Then, from Theorem 3 we get det A = (−1)

n

∑ (−1)

LQ + j

w(H )

H

= (−1)

n

∑ (−1)

LQ

w (Q)

(8.11)

Q

 n = (−1) 1 + 

∑ (−1)

LQ

Q

 w (Q) 

We can rewrite the above as:  n det A = (−1) 1 −  

∑Q + ∑Q − ∑Q j2

j1

j

j

j

j3

 L  

(8.12)

where each term in Σ j Qji is the weight of a collection of i vertex-disjoint directed circuits in Gm(A). Suppose we refer to (–1)n det A as the determinant of the graph Gm(A). Then, starting from Hn+1, k and reasoning exactly as above we can express the numerator of (8.3) as n

∑b ∆ i

= (−1)

n

ik

∑ w(P ) ∆ j n+1, k

j

(8.13)

j

i =1

j where Pn+1, k is a directed path from xn+1 to xk of Gm(A′) and ∆ j is the determinant of the subgraph of Gm(A′), which is vertex-disjoint from the path P jn+1,k. From (8.12) and (8.13), we get the following theorem.

Theorem 6: If the coefficient matrix A in (8.2) is nonsingular, then

xk = x n+1

∑ w ( P )∆ , j

j n + l ,k

∆

j

k = 1, 2, K, n

(8.14)

where P jn+1, k is the jth directed path from xn+1 to xk of Gm(A′), ∆ j is the determinant of the subgraph of Gm(A′), which is vertex-disjoint from the jth directed path P jn+1, k, and ∆ is the determinant of the graph of ▫ Gm(A). Equation (8.14) is known as Mason’s gain formula. In network and systems theory, Pnj+1, k is referred to as a forward path from vertex xn +1 to vertex xk. The directed circuits of Gm(A′) are called the feedback loops. We now illustrate Mason’s method by solving the system (8.4) for x2 /x4. To compute the denominator in (8.14), we determine the different collections of vertex-disjoint directed circuits of the Mason graph Gm(A) shown in Fig. 8.4(b). They are listed below along with their weights.

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Collection of Vertex-Disjoint Directed Circuits of Gm(A)

Weight

No. of Directed Circuits

(x1) (x2) (x3) (x1, x2) (x1, x3) (x1, x2, x3) (x1) (x2) (x1) (x3) (x2) (x3) (x2) (x1, x3) (x3) (x1, x2) (x1) (x2) (x3)

4 3 3 2 3 2 12 12 9 9 6 36

1 1 1 1 1 1 2 2 2 2 2 3

From the above we obtain the denominator in (8.14)

∆ = 1 + (−1) [ 4 + 3 + 3 + 2 + 3 + 2]

1

+ (−1) [12 + 12 + 9 + 9 + 6] + (−1) 36 = − 4 2

3

To compute the numerator in (8.14) we need the forward paths in Gm(A′) from x4 to x2. They are listed below with their weights. j

P j4, 2

Weight

1 2 3

(x4, x2) (x4, x1, x2) (x4, x3, x1, x2)

–1 3 –2

The directed circuits which are vertex-disjoint from P41, 2 are (x1), (x3), (x1, x3). Thus ∆1 = 1 − ( 4 + 3 + 3) + 12 = 1 − 10 + 12 = 3. (x3) is the only directed circuit which is vertex-disjoint from P42, 2 . So, ∆ 2 = 1 − 3 = −2. No directed circuit is vertex-disjoint from P43, 2 , so ∆3 = 1. Thus, the numerator in (8.14) is P41, 2 ∆1 + P41, 2 ∆ 2 + P41,3 ∆ 3 = −3 − 6 − 2 = −11 and x 2 11 = x4 4

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References [1] C. L. Coates, “Flow graph solutions of linear algebraic equations,” IRE Trans. Circuit Theory, vol. CT-6, pp. 170–187, 1959. [2] S. J. Mason, “Feedback theory: some properties of signal flow graphs,” Proc. IRE, vol. 41, pp. 1144–1156, 1953. [3] S. J. Mason, “Feedback theory: further properties of signal flow graphs,” Proc. IRE, vol. 44, pp. 920–926, 1956. [4] K. Thulasiraman and M. N. S. Swamy, Graphs: Theory and Algorithms, New York: Wiley Interscience, 1992. [5] W. K. Chen, Applied Graph Theory, Amsterdam: North Holland, 1971. [6] F. Harary, “The determinant of the adjacency matrix of a graph,” SIAM Rev., vol. 4, pp. 202–210, 1962. [7] F. E. Hohn, Elementary Matrix Algebra, New York: Macmillan, 1958.

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9 Theory of Two-Dimensional Hurwitz Polynomials 9.1 9.2

Introduction Preliminaries and Notations Infinite Distant Points • Analog Biplane • Isolated and Continuum of Zeroes

9.3

Value of Two-Variable Polynomial at Infinity

9.4

Various Analog Hurwitz Polynomials

Nonessential Singularities of the Second Kind (NSSK) Self-Paraconjugate Polynomial • Broad-Sense Hurwitz Polynomial (BHP) • Narrow-Sense Hurwitz Polynomial (NHP) • Scattering Hurwitz Polynomial (SHP) • Hurwitz Polynomial in the Strict Sense (HPSS) • Very Strict Hurwitz Polynomial (VSHP) • Self-Paraconjugate Hurwitz Polynomial (SPHP) • Reactance Hurwitz Polynomial (RHP) • Immittance Hurwitz Polynomial (IHP) • Summary

9.5

Testsets for Analog Hurwitz Polynomials

Hari C. Reddy

9.6 9.7

California State University, Long Beach, and University of California, Irvine

Two-Variable Very Strict Hurwitz Polynomials Application of Two-Dimensional Hurwitz Polynomials for Two-Variable Passive Networks and Stability

9.8

Conclusions

Continuity Property of the Zeroes of 2-V Polynomials

Application to Two-Dimensional Analog System Stability

9.1 Introduction The advances in two-dimensional (2-D) signal and image processing activities have stimulated active research in 2-D circuits and systems area. Two-variable (2-V) or 2-D Hurwitz polynomial study finds application in areas such as generation and testing of (2-V) reactance functions, bounded/positive real functions, and matrices; testing the stability of 2-D digital filters; and the generation of stable 2-D digital transfer functions. Stability analysis is an important aspect of the design of dynamic systems. This analysis is often carried out by examining for the absence of zeroes of the denominator polynomial of a system transfer function in some specified regions of the complex plane. One dimensional (1-D) systems are studied through the characterization whether or not the denominator polynomial is Hurwitz. By expand­ ing this idea, we can define and study 2-D (also called bivariate, 2-V) Hurwitz polynomials. In view of the diverse needs of several different applications a number of 2-D Hurwitz polynomials have been defined and their test procedures established. In this chapter, a detailed presentation of various 2-D

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Hurwitz polynomials and their relationships to one another is given. We also study their relevant applications. To highlight the relationships among the various Hurwitz polynomials, the definitions of all the Hurwitz polynomials are presented. This is done in terms of the absence of or the nature of their zerosets in specified regions such as the open or closed right half of the (S1, S2)-biplane. The goal is to make a tutorial exposition on 2-D Hurwitz polynomials. The second section gives some preliminaries and notations. We next present the definitions of a number of (S1, S2)-domain Hurwitz polynomials. Based on the continuity property of the zeroes of 2-V polyno­ mials, testsets for the various Hurwitz polynomials are given in the fifth section. Following that, a 2-D, very strict Hurwitz polynomial is discussed in detail because this is the counterpart of strict Hurwitz in the 1-D case. Some of the applications of the various Hurwitz polynomials are described in the final section.

9.2 Preliminaries and Notations Infinite Distant Points The following discussion is crucial to the understanding of certain classes of stable 2-D polynomials. The points at infinite distances in the (S1, S2)-biplane play an important role in the definition of certain 2-D Hurwitz polynomials. Some of the confusion that resulted in the application of these Hurwitz polynomials can be attributed to the neglect or omission of these infinite distant points. This chapter considers the extended (S1, S2)-biplane, which includes the infinite distance points. For the sake of clarity, we also explicitly indicate whether the infinite distant points are included in or excluded from the regions considered. The behavior of 2-V polynomials at infinite distant points is well described in the literature [2, 3]. Seemingly many infinite distant points in the 1-D plane, such as the S1-plane or the S2 -plane, may be assumed to merge to a single point. Thus, infinity is treated as a single point, and any shift from this infinite distant point, however small, leads to a finite distant point.

Analog Biplane Re(s) = Real part of the variable s

For i = 1, 2

Si+ = {siRe(si) > 0,  si < ∞}, open right half of the Si-plane Sio = {siRe(si) = 0,  si ≤ ∞}, imaginary axis of the Si-plane Si  = {siRe(si) ≥ 0,  si ≤ ∞}, closed right half of the Si-plane S 2+0 = {(s1, s2) Re(s1) > 0, Re(s2) = 0, s1 < ∞, s2 ≤ ∞}, open right half of the S1-plane and the imaginary axis of the S2-plane S 20+ = {(s1, s2) Re(s1) = 0, Re(s2) > 0, s1 ≤ ∞, s2 < ∞}, open right half of the S2-plane and the imaginary axis of the S1-plane S 2++ = {(s1, s2) Re(s1) > 0, Re(s2) > 0, s1 < ∞, s2 < ∞}, open right half of the (S1, S2)-biplane S 200 = {(s1, s2) Re(s1) = 0, Re(s2) = 0, s1 ≤ ∞, s2 ≤ ∞}, distinguished boundary of the (S1, S2)-biplane S 2 = {(s1, s2) Re(s1) ≥ 0, Re(s2) ≥ 0, s1 ≤ ∞, s2 ≤ ∞}, closed right half of the (S1, S2)-biplane PRF: Positive real function RF: Reactance function TPRF: 2-Variable positive real function TRF: 2-Variable reactance function TBRF: 2-Variable bounded real function TLBRF: 2-Variable lossless bounded real function B∗(s1 s2) = Paraconjugate of B(s1, s2) = [B(–s1∗, –s2∗)]∗, where s∗ represents complex conjugate of s Be(s1, s2) = Para-even part of B(s1, s2) = [B(s1, s2) + B∗(s1, s2)]/2 B0(s1, s2) = Para-odd part of B(s1, s2) =[B(s1, s2) – B∗(s1, s2)]/2 © 2003 by CRC Press LLC

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Definition A: A rational function F(s) with real coefficients such that Re[F(s)] > 0 for Re(s) > 0 is called a positive real function (PRF). Definition B: A PRF F(s) is said to be a strict PRF if Re[F(s)] > 0 for Re (s) ≥ 0. Definition C: A PRF F(s) is said to be a minimum reactive and susceptive if it has neither poles nor zeroes on the imaginary axis of the S-plane. Definition D: A PRF F(s) is called a reactance function (RF) if Re [F(s)] = 0 for Re(s) = 0. Definition E: A 2-V rational function F(s1, s2) with real coefficients such that Re[F(s1, s2)] > 0 for S 2++ is called a TPRF. A TPRF F(s1, s2) = –F(–s1, – s2) is called a TRF. Definition F: A 2-V rational function H(s1, s2) with real coefficients such that H(s1, s2) < 1 for S 2++ is called a TBRF. A TBRF H(s1, s2) satisfying the condition H(s1, s2) = 1 or 0/0 for S 200 is called TLBRF.

Isolated and Continuum of Zeroes Some types of Hurwitz polynomials are distinguished on the basis of whether they have isolated zeroes or a continuum of zeroes on S 200 . As a point on S 200 is characterized by s1 = jw1 and s2 = jw2, where w1 and w2 are real quantities, the region S 200 can be graphically represented by the (W1,W2)-plane. The isolated zeroes on S 200 are, thus, points on this plane and the continuum of zeroes is represented by continuous curves. Isolated and continuum of zeroes for the 2-D case are illustrated on the (W1,W2)-plane in Fig. 9.1, where zeroes of some simple polynomials are shown.

W2

(s2−jβ) β

(s1−jα)

α

W1

(s12+ s22 + 2) s1 + s2 + s1 s2

2 FIGURE 9.1 Zero distribution of some simple polynomials in (W1, W2) plane (S00 ). (Polynomial (s1 + s2 + s1s2) has 2 2 an isolated zero, whereas polynomials (s1 – jα), (s2 – jβ), and (s1 + s2 + 2) have a continuum of zeroes.)

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9.3 Value of a Two-Variable Polynomial at Infinity Because later in the chapter it is necessary to determine the value of a 2-V polynomial at infinite distance points, the following explanation is in order. In 1-D complex plane S the infinite distant points can be represented by a single point, and the value of any function at this point is found by applying some transformation which transforms the point at infinity to some finite point s′, and the value of the transformed function at s′ is determined. Often s = 1/u is the transformation used and infinity is mapped onto the origin. Using this transformation, the value of B(s) at infinity can be defined as B(∞) = B T (0), where B T (u) = B(1/u). In the 2-D biplane (S1, S2) consisting of two complex planes, S1 and S2, an infinite distant point can have infinite coordinates in either one or both of these planes, and thus an infinite number of infinite distant points exists. They can be classified into three categories [3]: 1. s1 = ∞ and s 2 = finite

(9.1a)

2. s1 = finite and s 2 = ∞

(9.1b)

3. s1 = ∞ and s 2 = ∞

(9.1c)

Applying the transformation method to each variable, the value of the function at each of the above points is defined as: B(∞, s′2 ) = B1 (0, s 2′ ) where B1 (u, s 2 ) = B(1 u , s 2 ), s′2 < ∞

(9.2a)

B(s′, 1 ∞) = B2 (s1′,0) where B2 (s1 , v ) = B(s1 , 1 v ), s′ 1 0, s2 < ∞. Note that to test for the absence of the zeroes of B(s1, s2) in s 20, we must test all the boundary points and we cannot leave any isolated point untested, as in the case of s 20+. Next, we discuss test procedure for the various Hurwitz polynomials. Theorem 9.2: A 2-V polynomial B(s1, s2) is a BHP iff B(jw1, s2) ≠ 0 in S2+ for all real finite w1, except possibly some isolated w1 and if the polynomial B(s1, b) has no zeroes in S1+ for some b ∈ S2+. Theorem 9.3: A 2-V polynomial B(s1, s2) is a NHP iff for all real finite w1, B(jw1, s2) ≠ 0 in S2+ ; the polynomial in s1, B(s1, b) ≠ 0 in S1+ for some b ∈ S2+, and B(s1, s2) has no factor of the type (s2 – jα), where α is a real constant. Theorem 9.4: A 2-V polynomial B(s1, s2) is a SHP iff for all real finite w1, B(jw1, s2) has no zeroes in S2+; the polynomial B(s1, b) has no zeroes in S1+ for some b ∈ S2+, and B(s1, s2) and B*(s1, s2) are relatively prime. Theorem 9.5: A 2-V polynomial B(s1, s2) is a HPSS iff for all finite w1, B(jw1, s2)has no zeroes in {s2: Re (s2) ≥ 0, s2 < ∞} and the polynomial, B(s1, b) has no zeroes in Re s1 ≥ 0, for some b ∈ S2+. It is easy to verify that only infinite distant points on S 200 are omitted from S 200 in testing for the zero locations of B(s1, s2). Hence, B(s1, s2) is a HPSS. Theorem 9.6: The necessary and sufficient conditions for a 2-V polynomial B(s1, s2) to be a VSHP are [19]: 1. 2a. 2b. 2c.

B(s1, s2) is a HPSS

B(∞, s2 ) ≠ 0/0 for Re(s2) = 0 and s2 < ∞

B(s1, ∞ ) ≠ 0/0 for Re(s1) = 0 and s1 < ∞

B(∞,∞) ≠ 0/0

The infinite point testing method shown in (9.2a) to (9.2c) could be followed for the testing of the three conditions under number 2 above. Let B(s1 , s 2 ) =

M

N

∑∑ b s s

i j ij 1 2

i=0

j=0

Then, conditions 2a to 2c are equivalent to: AM (s 2 ) =

N

∑b j=0

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s ≠ 0 for Re(s 2 ) = 0

j Mj 2

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BN (s1 ) =

M

∑b

s ≠ 0 for Re(s1 ) = 0

i iN 1

i=0

bMN ≠ 0 Theorem 9.7: Let B(s1 , s 2 ) =

N

∑ a (s )s j

1

j 2

j=0 M

=

∑ b (s )s i

2

i 1

i=0 M

=

N

∑∑ c i=0

i j ij 1 2

ss

j=0

Then, B(s1, s2) is a VSHP iff B(jw1, jw2) ≠ 0, – ∞ < wi < ∞ i = 1, 2, and aN (s1) ≠ 0 in S1⊕ , and bM (s2) ≠ 0 in S2⊕ , and cMN ≠ 0. Testests for SPHP, RHP, and IHP can be formulated easily based on their definitions and the testest of a BHP.

9.6 Two-Variable Very Strict Hurwitz Polynomials A brief, additional discussion of VSHPs is given in this section because this class of 2-V Hurwitz polynomials is a counterpart to the 1-V SHP, at least from the domain description of a closed right-half­ plane. We now state some of the properties of 2-V VSHPs. Let a two-variable transfer function T(s1, s2) be expressed as T (s1 , s 2 ) = P(s1 , s 2 ) Q(s1 , s 2 )

(9.3)

where P(s1 , s 2 ) =

∑∑ p s s

(i = 0,1,K, k; j = 0,1,K, l )

∑∑ q s s

(i = 0,1,K, m; j = 0,1,K, n)

i j ij 1 2

i

Q(s1 , s 2 ) =

j

i j ij 1 2

i

j

By applying the transformation method of (9.2a) to (9.2c) it can be shown that unless m ≥ k and n ≥ l, polar singularities exist at a set of infinite distant points in the closed right-half of the {S1, S2}-biplane. Therefore, assume the m ≥ k and n ≥ 1. Then, the following theorem regarding the singularity in the closed right-half biplane can be stated. Theorem 9.8: T (s1, s2) does not possess any singularity on the closed right-half of {S1, S2}-biplane defined 2 iff Q(s1, s2) is a VSHP. by S⊕⊕ PROOF. The proof of the theorem is straightforward if the infinite distant points are also taken into account.

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Some other useful properties of VSHPs are [2]: • B(s1, s2) = [B1(s1, s2). B2(s1, s2)] is a VSHP iff B1(s1, s2) and B2(s1, s2) are VSHPs. • If B(s1, s2) is a VSHP, then ∂/∂si [B(s1, s2)], i = 1, 2 are also VSHP’s. This property is not true for other 2-D Hurwitz polynomials. Let B(s1 , s 2 ) = AM (s 2 )s1M + AM −1 (s 2 )s1M −1 + L + A1 (s 2 )s1 + A0 (s 2 ) = C N (s1 )s 2N + C N −1 (s1 )s 2N −1 + L + C1 (s1 )s 2 + C0 (s1 )

(9.4) (9.5)

• Let B(s1, s2) be expressed as in (9.4) and (9.5). Then, Ai(s2), i = 0, 1, … , M and C j (s1), j = 0, 1, …, N are one-variable strict Hurwitz polynomials. This property readily follows from the preceding partial derivative property. • Let B(s1, s2) = Σ i Σ j bij s i 1 s 2j be a real 2-D VSHP. Then bMN bij > 0 for all i and j (i = 0, 1, …, M; j = 0, 1, … , N). • Let B(s1, s2) be expressed as in (9.4) and (9.5). Then, Ai (s2)/Ai–1 (s2) for i = 1, …, M and Cj (s1)/Cj – 1 (s1) for j = 1, … , N are minimum reactive, susceptive, strict PRFs. The preceding property gives the following the necessary and sufficient condition for B(s1, s2), which has a first degree in s1 and any degree in s2. The necessary and sufficient condition that allows a 2-V polynomial B(s1, s2) = B1(s2)s1 + B0 (s2) to be a VSHP is that the 1-V function F(s2) = B1(s2)/B0(s2) be a minimum reactive, susceptive, strict PRF. Finally, we give a transformation theorem that transforms a 1-D strict Hurwitz polynomial into a 2-D VSHP. This is called a reactance transformation. Theorem 9.9: Let D(s) be any strict Hurwitz polynomial of order n. Generate a 2-D polynomial in the following way:

[

] { }

B(s1 , s 2 ) = N (s1 , s 2 ) ⋅ D(s ) s = M (s1 , s 2 ) N (s1 , s 2 ) n

where M and N are, respectively, the even and odd 2-D polynomials. The necessary and sufficient condition for B(s1, s2) to be a VSHP is that M(s1, s2) + N(s1, s2) be a VSHP [2]. The odd TPRF Z(s1, s2) = M(s1, s2)/N (s1, s2) does not possess NSSK on the distinguished boundary 2 S00 and is called a proper or strict 2-D reactance function [2].

9.7 Application of Two-Dimensional Hurwitz Polynomials for Two-Variable Passive Networks and Stability This section enumerates some properties of 2-V passive network functions, with particular reference to the Hurwitz nature of the polynomials [24]. (The following assumes Re F (1, 1) > 0.) Let F (s1 , s 2 ) = N (s1 , s 2 ) D(s1 , s 2 ) be the driving-point immittance of a passive network. Then, N(s1, s2) and D(s1, s2) are BHPs. Let the common factors of N(s1, s2) and D(s1, s2) be cancelled out and the resulting polynomials be called N1(s1, s2) and D1(s1, s2). Then, N(s1, s2) and D1 (s1, s2) are immittance Hurwitz polynomials. Let F(s1, s2) = A(s1, s2)/B(s1, s2) be a relatively prime 2-V odd rational function. Then, F(s1, s2) is a 2–V reactance function if A(s1, s2) + B(s1, s2) is a VSHP. F(s1, s2) is A 2-V reactance function iff A(s1, s2) + B(s1, s2) is a scattering Hurwitz polynomial. The self-paraconjugate polynomials A(s1, s2) and B(s1, s2) satisfy the reactance Hurwitz properties. A relatively prime 2-V odd function F(s1, s2) = A(s1, s2)/B(s1, s2) having no second-kind singularities is a reactance function iff A(s1, s2) + B(s1, s2) is a VSHP. Such functions are called proper or strict reactance © 2003 by CRC Press LLC

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functions [2], and are useful as transformation functions to generate a (structurally stable) 2-D network from a stable 1-D network. This is one of the main applications of VSHP. Let us now consider a relatively prime function F(s1, s2) = N (s1, s2)/D(s1, s2). F(s1, s2) is a TPRF iff N(s1, s2) + D(s1, s2) is a scattering Hurwitz polynomial. Further, if no second-kind singularities exist for 2 , N(s1, s2) + D(s1, s2) will be a VSHP. From the previous discussion, we can conclude that F(s1, s2) on S 00 the Hurwitz nature determines important necessary conditions (and in some cases necessary and suffi­ cient conditions) of 2-V positive lossless functions. Hurwitz polynomials can be used to generate 2-V positive and lossless functions as in 1-V case through partial derivative operations [6]. The following property relates to sum separability and Hurwitz nature [20]. Let F(s1, s2) = N (s1, s2)/D(s1, s2) be a 2-V positive function. Assume D(s1, s2) is an immittance Hurwitz polynomial having self-paraconjugate factors. In other words, D(s1, s2) is written as D(s1, s2) = D1(s1, s2)D2(s1, s2), where D1(s1, s2) is a reactance Hurwitz and D1(s1, s2) is a scattering Hurwitz. Then, F(s1, s2) is sum separable as F (s1 , s 2 ) =

N1 (s1 , s 2 ) D1 (s1 , s 2 )

+

N 2 (s1 , s 2 ) D2 (s1 , s 2 )

where N1/D1 is a reactance function and N2/D2 is a positive function. Now, we turn our attention to some applications concerning transfer functions. Let T(s1, s2) = A(s1, s2)/B(s1, s2) be the transfer function of a singly terminated or doubly terminated 2-V lossless network. Then, B(s1, s2) is a scattering Hurwitz polynomial. References [21] and [22] provide a detailed discussion of networks with transfer functions having scattering and VSHP denominators. It is not necessary that the denominator of all RLC 2-V network transfer functions be scattering Hurwitz. In the most general case it could be a broad-sense Hurwitz. Another interesting observation is that in the 1-V case the voltage transfer function cannot have a pole at origin and infinity. Extending this to the 2-V situation, we find that the 2-V voltage transfer function, T(s1, s2) cannot have first-kind (polar) singularities at si = 0 or ∞ (i = 1, 2), but T(s1, s2) can be 0/0 at si = 0 or ∞ (i = 1, 2). Let H (s1 , s 2 ) = P(s1 , s 2 ) Q(s1 , s 2 ) be a 2-V bounded real or lossless bounded real function. Then, Q(s1, s2) is a scattering Hurwitz polynomial. If H(s1, s2) has no NSSK on S 200 then Q(s1, s2) must be a VSHP.

Application to Two-Dimensional Analog System Stability We consider the following important theorem [12]. Theorem 9.10: The 2-D analog transfer function T(s1 , s 2 ) = A(s1 , s 2 ) B(s1 , s 2 ) is bounded-input–bounded­ output (BIBO) stable only if B(s1, s2) is a scattering Hurwitz polynomial. The sufficient condition for stability is that B(s1, s2) be a VSHP (assume that T(s1, s2) has no polar singularities at infinite distant points). We conclude this section with the following unresolved problem of BIBO stability of 2-D continuous time systems [12]: Conjecture. The 2-D analog transfer function T(s1, s2) described in Theorem 9.10 is BIBO stable with no 2 NSSK on S00 iff B(s1, s2) is a VSHP. The sufficiency part of this statement is proved. The necessity has yet to be established.

9.8 Conclusions This chapter provides a comprehensive, yet compact treatment of the theory of two-dimensional (analog) Hurwitz polynomials. With the help of double bilinear transformation s1 = (1 – zi)/(1 + zi), i = 1, 2, most of the theory could easily be translated to the 2-D discrete case, and thus to the stability theory and design of two-dimensional digital filters [2, 24]. As in the 1-D case the 2-D Hurwitz polynomials pay a critical role in the study of 2-D circuits, systems, and filters. In this chapter, a detailed classification and © 2003 by CRC Press LLC

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testing (see theorems) of various 2-D Hurwitz polynomials is presented. Discussion of the properties of 2-D very strict Hurwitz polynomials is also given. The various testing procedures (algorithms) are not discussed. The test procedures can be found in [11, 12, 25, 26]. The chapter concludes by discussing how various Hurwitz polynomials arise in passive 2-V circuit theory and 2-D analog stability.

Acknowledgments As always, Dr. P. K. Rajan of the Tennessee Technological University and Dr. E. I. Jury of the University of California at Berkeley and the University of Miami provided constant encouragement. Dr. Rajan made significant contributions to the theory of stable 2-D polynomials discussed in this chapter. The material in this chapter is based mainly on references [2] and [24] (including Fig. 9.1).

References [1] H. G. Ansell,“On certain two-variable generalization of circuit theory with applications to networks and transmission lines of lumped reactances,” IEEE Trans. Circuit Theory, vol. CT-11, pp. 214–223, June 1964. [2] H. C. Reddy et al., “Generation of two-dimensional digital transfer functions without nonessential singularities of the second kind,” in Proc. IEEE Int. Conf. Acoust., Speech, Signal Processing, pp. 13–19, Apr. 1979. Also see P. K. Rajan et al., IEEE Trans. Acoust., Speech, Signal Processing, pp. 216–223, Apr. 1980. [3] V. S. Valdimirov, Method of Theory of Functions of Many Complex Variables, Cambridge, MA: MIT Press, 1966, pp. 36–38. [4] M. Satio, “Synthesis of transmission line networks by multivariable techniques,” in Proc. Symp. Generalized Networks, PIB, 1966, pp. 353–393. [5] D. C. Youla, “Synthesis of networks containing lumped and distributed elements,” in Proc. Symp. Generalized Networks, PIB, 1966, pp. 289–343. [6] V. Ramachandran, “Some similarities and dissimilarities between single variable and two-variable reactance functions,” IEEE Circuits Syst. Newsl., pp. 11–14, 1976. [7] A. Fettweis, “On the scattering matrix and the scattering transfer matrix of multidimensional lossless two-ports,” Arch. Elk. Ubertragung, vol. 36, pp. 374–381, Sept. 1982. [8] T. S. Huang, “Stability of two-dimensional recursive digital filters,” IEEE Trans. Audio Electroacoust., vol. AU–20, pp. 158–163, June 1972. [9] Ph. Delsarte, Y. Genin, and Y. Kamp, “Two–variable stability criteria,” Proc. IEEE Trans. Int. Symp. Circuits Syst., pp. 495–498, Jul. 1979. [10] A. Fettweis, “On Hurwitz polynomials in several variables,” in Proc. 1983 IEEE Int. Symp. Circuits and Syst., Newport Beach, CA, 1983, pp. 382–385. [11] N. K. Bose, Applied Multidimensional Systems Theory, New York: Van Nostrand Reinhold, 1982. [12] E. I. Jury, “Stability of multidimensional systems and related problems,” in Multidimensional Systems—Techniques and Applications, S. G. Tzafestas, Ed., New York: Marcel Dekker, 1986. [13] A. Fettweis and S. Basu, “On discrete scattering Hurwitz polynomials,” Int. J. Circuit Theory Appl., vol. 13, Jan. 1985. [14] A. Fettweis, “Some properties of scattering Hurwitz polynomials,” Arch. Elk. Ubertragung, vol. 38, pp. 171–176, 1984. [15] M. G. Strintzis, “Tests of stability of multidimensional filters,” IEEE Trans. Circuits and Syst., vol. CAS-24, Aug. 1977. [16] D. Goodman, “Some difficulties with double bilinear transformation in 2-D filter design,” Proc. IEEE, vol. 66, pp. 905–914, June 1977. [17] D. C Youla, “The analysis and synthesis of lumped passive n-dimensional networks—Part I—anal­ ysis,” Polytechnic Inst. New York, Brooklyn, Rep. MIR-1437-84, Jul. 1984.

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[18] A. Fettweis and S. Basu, “New results on multidimensional Hurwitz polynomials,” in Proc. Int. Symp. Circuits and Systems, Kyoto, Japan, June 1985, pp. 1359–1362. [19] H. C. Reddy and P. K. Rajan, “A simpler test-set for very strict Hurwitz polynomials,” Proc. IEEE, pp. 890–891, June 1986. [20] H. C. Reddy et al., “Separability of mutivariable network driving point functions,” IEEE Trans. Circuits Syst., vol. CAS-29, pp. 833–840, Dec. 1982. [21] H. C. Reddy et al., “Realization of resistively terminated two-variable lossless ladder networks,” IEEE Trans. Circuits Syst., vol. CAS–29, pp. 827–832, Dec. 1982. [22] H. C. Reddy et al., “Design of two-dimensional digital filters using analog reference filters without second kind singularities,” in Proc. IEEE Int. Conf. Acoust., Speech, Signal Processing, Apr. 1981, pp. 692–695. [23] D. Goodman, “Some stability properties of linear shift invariant digital filters,” IEEE Trans. Circuits SST., vol. 26, pp. 201–208, Apr. 1971. [24] H. C. Reddy and P. K. Rajan, “A comprehensive study of two-variable Hurwitz polynominals,” IEEE Trans. Educ., vol. 32, pp. 198–209, Aug. 1989. [25] H. C. Reddy and P. K. Rajan, “A test procedure for the Hurwitz of two-dimensional analog polynomials using complex lossless function theory,” Proc. IEEE Int. Symp. Circuits Systems, pp. 702–705, May 1987. [26] P. K. Rajan and H. C. Reddy, “Hermite matrix test for very strict Hurwitz polynomials,” Proc. Midwest Symp. Circuits Syst., pp. 670–673, Aug. 1986. [27] G. A. Bliss, Algebraic Functions. New York: American Mathematical Society, 1933.

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II Circuit Elements, Devices, and Their Models John Choma, Jr. University of Southern California 10 Passive Circuit Elements Stanistaw Nowak, Tomasz W. Postupolski, Gordon E. Carlson, B. M. Wilamowski Resistor • Capacitor • Inductor • Transformer • Semiconductor Diode

11 RF Passive IC Components Thomas H. Lee, Maria del Mar Hershenson, Sunderarajan S. Mohan, Kirad Samavati, C. Patrick Yue Introduction • Fractal Capacitors • Spiral Inductors • On-Chip Transformers

12 Circuit Elements, Modeling, and Equation Formulation Josef A. Nossek Lumped Circuit Approximation • Circuit Elements and Connecting Multiport • Characterizations of Circuit Elements • Connecting Multiport • Tableau Formation

13 Controlled Circuit Elements Edwin W. Greeneich, James F. Delansky Controlled Sources • Signal Converters

14 Bipolar Junction Transistor (BJT) Circuits David J. Comer, Donald T. Comer Introduction • Physical Characteristics and Properties of the BJT • Basic Operation of the BJT • Use of the BJT as an Amplifier • Representing the Major BJT Effects by an Electronic Model • Other Physical Effects in the BJT • More Accurate BJT Models • Heterojunction Bipolar Junction Transistors • Integrated Circuit Biasing Using Current Mirrors • The Basic BJT Switch • High-Speed BJT Switching • Simple Logic Gates • Emitter-Coupled Logic

15 Operational Amplifiers David G. Nairn, Sergio Franco The Ideal Operational Amplifier • The Nonideal Operational Amplifier • Frequency- and Time-Domain Considerations

16 High-Frequency Amplifiers Chris Toumazou, Alison Payne Introduction • The Current Feedback Op-Amp • RF Low-Noise Amplifiers • Optical Low-Noise Preamplifiers • Fundamentals of RF Power Amplifier Design • Applications of High-Q Resonators in IF-Sampling Receiver Architectures • Log-Domain Processing

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10 Passive Circuit Elements 10.1 Resistor Linear Resistor • Nonlinear • Dependence on Material Properties • Dependence on Geometry of Material • Nonideal Linear Resistor

10.2 Capacitor

Stanislaw Nowak University of Mining and Metallurgy

Tomasz W. Postupolski Institute of Electronic Materials Technology

Gordon E. Carlson University of Missouri, Rolla

B. M. Wilamowski University of Idaho

Introduction • Linear Capacitor • Nonlinear Capacitor • Dependence on Material Properties • Dependence on Geometry of Material • Nonideal Linear Capacitor

10.3 Inductor Basics • Air Inductor • Cored Inductor • Nonlinearity in Inductors • Magnetic Core Materials

10.4 Transformer Introduction • Ideal Transformer • Nonideal Transformer

10.5 Semiconductor Diode Nonlinear Static I–V Characteristics • Diode Capacitances • Depletion Capacitance • Diode as a Switch • Temperature Properties • Piecewise Linear Model

10.1 Resistor Stanis l aw Nowak Linear Resistor Introduction An ideal resistor is an electronic component, the fundamental feature of which is resistance R according to Ohm’s law expressed by the equation V = RI

(10.1)

where V represents voltage in volts, I is the current in amperes, and R the resistance in ohms. The main parameters of a resistor are nominal resistance value, nominal power dissipation, and limited voltage value. According to their construction and technology, we can divide resistors into five groups: wirewound resistors, foil resistors, thin film resistors, thick film resistors, and bulk resistors. Each group has some advantages and disadvantages; until now it has been impossible to manufacture all of the needed resistors within one technology. It is more interesting to divide resistors with respect to their application into two groups as follows: 1. fixed resistors, including low-power resistors of 0.05 to 2 W, high-power resistors of 2 to 100 W, high-voltage resistors, high-ohmic resistors, chip resistors, resistive networks, and 2. variable resistors (potentiometers), including rotary control potentiometers, slide control potentiometers, preset potentiometers, and special potentiometers.

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(a)

(b)

3

1

2

3

4

5

(c)

3 (d)

1

1

2

4

5 6

2 3

(e)

FIGURE 10.1 Typical fixed resistors: (a) film resistor: 1 — metal cap, 2 — electrode, 3 — resistive layer, 4 — groove, cut along screw line, 5 — termination; (b) bulk composition resistor: 1 — resistive composition, 2 — termination, 3 — pressed encapsulation; (c) high-voltage 100 MΩ thick film resistor; (d) wirewound power resistor, 1 — resistive wire, 2 — ceramic tube (substrate), 3 — termination, 4 — cement overcoating, 5 — welded point, 6 — cut for mechanical fixing of termination; (e) thick film resistor with radiator.

Fixed Resistor An ideal fixed resistor is an electronic component, the resistance value of which is constant with time and different environmental conditions. In practice, we can observe some changes of resistance in time and under high temperature, high humidity, frequency, and electrical load conditions, and so on. Those changes of a resistance, called the instability of resistor, are the basis for classification of resistors according to the requirements of the International Electrical Commission (IEC) and the International Organization for Standardization (ISO 9000–9004) in order to build in a reliability system. Figure 10.1 presents different kinds of fixed resistors. Each resistor is marked mainly by resistance value R and production tolerance δp (±). Nominal resistance is rated according to the E6, E12, E24, E48, and E96 series. It is very important for the user to know not only the production deviation δp but also dynamic tolerance ∆. Dynamic Tolerance  and Resistor Class. The author’s proposal for calculation of the dynamic tolerance ∆ is given by (10.2) and (10.3):

where

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∆ + = δ p( + ) + δ + c ∗ s

(10.2)

∆ − = δ p( − ) − δ − c ∗ s

(10.3)

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(a)

− δ p(+)

(b)

δ [%]

δ [%] 0.4

20 kΩ, +70 C, P = Pn

0.4

∆max

+0.06%

0.2

− − ∆=δ

0.2 t[h]

0

100

101

102

103

0

104

+0.3%

100

101

102

103

104

−0.2

−0.2 −0.4

− δ + 1.64s

− δ

t[h] −0.12%

−0.4

− δ − 1.64s

− δ p(−)

−0.55%

∆min –

–

FIGURE 10.2 Resistor tolerance in exploitation. (a) The changes of resistance δ in time t δ = ϕ1 (t), δ + 1.64 ∗ s = – ϕ2 (t) δ –1.64 ∗ s = ϕ3 (t). (b) Dynamic tolerance ∆ as a function of time. Test time 10,000 h, δp = ±0.25 percent. (a) 80

ni

(b) 80

1MΩ, 70°C 350 V

40

ni

2.4MΩ, 40°C 95% r.h.

40 δ1000 (%) 0.2

0.4

0.6

δ21 (%)

0.8

0.4

0.8

1.2

1.6

1.8

2.0

2.2

2 FIGURE 10.3 Distribution of δ (histogram). (a) Results after 1000 h endurance test: χ 2 = 5.01, χ0.05,5 = 11.7, n = – 2 2 150 pcs, δ = 0.45 percent, s = 0.24 percent. (b) Result after 21-day hot humidity test: χ = 100, χ0.05,8 = 15.5, n = – 246 pcs, δ = 0.79 percent, s = 0.47 percent, χ2 — chi square distribution.

δ=

δi =

1 n

n

∑δ

(10.4)

i

i =1

Ri (t ) − Ri (0) * 100% Ri (0)

(10.5)

n is the quantity of samples in test, t is the test time, and Ri is the resistance of i, the resistor.

s=

1 n

n

∑ (δ − δ)

2

(10.6)

i

i =1

–

c = 1.28 for probability level 90 percent cases inside the range δ ± 1.28 ∗ s, c = 1.64 for probability level – 95 percent cases inside the range δ ± 1.64 ∗ s. Figure 10.2 illustrates dynamic tolerance ∆ as an example of a thick film resistor endurance test prolonged up to 10 000 h. Resistors of 20 kΩ were manufactured by the Telpod factory (Poland) from Birox 1441 Du Pont paste. In (10.2) and (10.3), for the long-life stability test, the coefficient c is chosen for normal distribution of changes δi for tj = 1000 h because many experiments performed by author improved it with a high level of confidence. The hot humidity test causes distribution of changes asymmetrical, however. The results of tests obtained for 400 resistors are shown in Fig. 10.3(a) and (b). For asymmetrical – – distribution, the following values for c parameters are suggested: c1 = –1 for δi < δ and C2 = +3 for δi > δ.

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TABLE 10.1

Classes

δmax after Tests: Endurance Test Hot Humidity Test Climate Cycles Test

15 10 5 3 2 1 0.5 0.25

±(15% + 0.5Ω) ±(10% + 0.5Ω) ±(5% + 0.1Ω) ±(3% + 0.1Ω) ±(2% + 0.1Ω) ±(1% + 0.05Ω) ±(0.5% + 0.05Ω) ±(0.25% + 0.05Ω)

Recommended δp

Remarks

±20%, ±10%, ±5% ±2%, ±1%

Common use resistor

±5%, ±2%, ±1% ±0.5%, ±0.25% ±0.1%

Stable resistor

TABLE 10.2 Classes

δmax after Tests

Recommended δp

0.5 0.25 0.1 0.05

±(0.5% + 0.05Ω) ±(0.25% + 0.05Ω) ±(0.1% + 0.01Ω) ±(0.05% + 0.01Ω)

±1%, ±0.5%, ±0.25% ±0.1%, ±0.05% ±0.025% ±0.01%

Dynamic tolerance ∆ is recommended by IEC Publ. 115, 1982 because quality classes are connected – directly, with instability δmax, which is presented in Table 10.1. In practice, δmax = δ + cs according to (10.2). In accordance with IEC Publ. 115-5, 1982, the following classes of resistors are ranked according to precision group (see Table 10.2). Temperature Coefficient or Resistance — TCR. The influence of temperature on resistance might be observed: 1. When the resistor is exposed to high temperature for a long time; this results in irreversible changes in resistance. 2. When the resistor is exposed to thermal condition of short duration (0.5 h); this results in reversible changes in resistance that are measured as temperature coefficient of resistance (TCR). TCR may be calculated from (10.7) and in practice from (10.8) 1 ∂R R ∂T

(10.7)

1 RT − R0 R0 T − T0

(10.8)

TCR = TCR =

where R0 is the resistance measured at room temperature T0, RT is the resistance measured at temperature T, and T0 is room temperature. In Fig. 10.4, some curves R(T) are presented versus temperature for four types of resistors. It can be seen that in the tested range of temperature, TCR is positive and constant for curves 1 and 2 but negative and constant for curve 4. A different result is obtained for curve 3; at temperatures lower than Tm , TCR is negative, at higher temperatures than Tm , TCR is positive, and at Tm , TCR = 0. When Tm = 40°C, that type of resistor is the most interesting for users, because in the operating temperature range of 20˚C–60˚C, TCR is very small, almost zero.

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R (T)/R20 1.02

20 KΩ 3 2 1

1.01 3 1.00 0.99

−40

0

40

80

120 4

Tm

0.98

T (°C) 140

FIGURE 10.4 Dependence of resistance on ambient temperature. 1 — wirewound resistor; 2 — thin film resistor; 3 — thick film ruthenium based resistor; 4 — pyrolitic carbon resistor. TABLE 10.3 Number

TCR [ppm/K]

Number

TCR [ppm/K]

Number

TCR [ppm/K]

1 2 3 4 5

±2500 –800 – +2500 ±1000 –400 – –1000 ±500

6 7 8 9 10

±250 ±100 ±50 ±25 ±15

11 12 13 14 15

±25 ±20 ±15 ±10 ±5

(a)

(b) 3

6 1 2

R1

5 7 4

R2

FIGURE 10.5 Thick film resistive network, (a) Topography of divider: 1 — substrate; 2 — resistor R1; 3 — resistor R2; 4 — wire termination; 5 — soldering point; 6 — conductive path; 7 — insulating saddle; (b) electrical circuit.

As recommended by IEC Publ. 115, 1982, TCR limit values for different quality classes of resistors are shown in Table 10.3. Data in positions 1–5 refer to common use resistors, in positions 6–10, data refer to stable resistors, and in positions 11–15 to precision resistors. Resistive Network. In electronic circuits, resistors are often used as elements of dividers. In that case, it is more convenient to apply resistive networks (see Fig. 10.5). Because the resistive network is deposited on a substrate in one technological cycle, both the TCR and time instability δ are almost the same for different resistors in the network. It appears to be more important for a user of a circuit to know differences ∆ TCR and ∆δ instead of absolute values of TCR or δ. It is estimated that ∆ TCR can exhibit values of 1–3 ppm/K for TCR ≤ 50 ppm/K and ∆δ can get value of 0.02 percent for δ = 0.5 percent. Chip Resistor. The development of electronic circuit mounting technology is going towards reliability and flexibility improvement and this results in a new assembly technique, known as Surface Mounting Technology (SMT). Because SMT components have no terminations, their dimensions can be reduced. The smallest chip resistor is 2.5 mm long. Figure 10.6 depicts a 0.25 W chip resistor. Requirement

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protective coat (overglaze) resistor layer inner electrode

0.60 ± 0.1

end termination

ceramic substrate 0.50 ± 0.25 protective coat

1.6 ± 0.15

3.2

+0.15 −0.20

FIGURE 10.6 Chip resistor, nominal power 0.25 W [Philips Components Catalogue, 1989]. Dimensions are in millimeters.

parameters for chip resistors are the same as for fixed resistors with terminations. Thick film technology is often used in manufacturing chip resistors. High-Ohmic, High-Voltage Resistor. Usually resistors have resistances below 10 MΩ but sometimes resistors up to 10 GΩ are needed (for example in pH measurements, radiation particle detection, and so on). Only thick film technology enables production resistors of such high resistance values. Because the range of sheet resistance of the thick film layer changes from 1 Ω/square to 100 MΩ/square, we can easily get a resistance range from 1 to 10 GΩ. Laser trimming and shaping of the layer allows easily to get from 100 to 1000 squares of resistive layer. A very high value of sheet resistance decreases the thermal and long life stability of resistors, so it is advisable to design stable resistance with inks of 1 MΩ/square and to obtain the required resistance value by multiplying the number of squares. High-ohmic resistors can be used as high-voltage resistors if their resistive paths are long enough. The required voltage strength is a maximum of 2 kV/cm of resistive path. These types of resistors are used up to 10 kV in TV focusing systems. High-Power Resistor. Very often, in electrical systems as well as in some electronic circuits (for example, power suppliers, power amplifiers, R-TV transmitters, and radar equipment), resistors with dissipation power above 5 W are necessary. For dc and low-frequency applications up to 100 W, power resistors are realized by a cement layer but high parasitic inductance makes them useless for higher frequency performances. Film and band resistors have very good high-frequency characteristics and they are suggested for high-frequency applications. Resistive bands are made of boron–carbon or other compositions. Nominal resistance ranges are as follows: 50, 75, 300, 600 Ω. In Fig. 10.7, a band resistor of low inductance is shown. Variable Resistor The variable resistor, very often called a potentiometer, is an electronic component in which by movement of mechanical wiper the resistance is regulated. A variable resistor can regulate voltage when it is joined to the circuit as a fourth-pole element [Fig. 10.8(a)]. It can regulate current when it is joined to the © 2003 by CRC Press LLC

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150

mm

2

3 1 4

FIGURE 10.7 High-frequency resistor, nominal power 60 W. 1 — resistive band; 2 — band termination; 3 — hot pressed overcoat; 4 — holes for decreasing contact resistance.

(a)

(b)

I V1

V1 R V2

V2

RL

RL

FIGURE 10.8 Potentiometer in an electric circuit: (a) as four-pole, voltage divider; (b) as twin-pole, rheostat.

circuit as a twin-pole element in series with load RL [Fig. 10.8(b)]. Requirements for variable resistors are similar as for fixed resistors but several additional problems must be considered: mechanical endurance, rotational noise, contact resistance variation (CRV), the type of regulation curve (taper), and parallel curves in tandem potentiometers (stereo potentiometers). Variable potentiometers can be divided into three groups: rotary control potentiometers, slide control potentiometers, and preset potentiometers. In Fig. 10.9, photos of different types of potentiometers are shown. With respect to their application we can divided potentiometers into several categories: standard type (common use) potentiometers with a carbon polymer resistive layer, high-stability potentiometers with a cermet layer, precision potentiometers formed as wirewound, or thin film ones. To increase sensitivity of regulation, a lead screw actuated potentiometer is used, in which the screw moves the nut connected with the wiper. Slow displacement of the wiper causes fluent resistance regulation. Specially built potentiometers (helipots) are used for precise regulation (see Fig. 10.10). In that case, the wiper is moving along a screw line. This means that for 10 rotations of shaft, the total angle is 3600° and the way of wiper is 10 times longer than in a simple rotary potentiometer. In helipots, precision of adjustment depends on the diameter of potentiometer. This type of a potentiometer is manufactured by Beckman, Bourns, and others. Mechanical Endurance. During the test of mechanical endurance, the wiper has to perform many total cycles. For present potentiometers, the number of cycles is 100–500; for control potentiometers it is 105–106 cycles. Regulation Curves (Taper). The most popular regulation curve is a straight line; but as it is well known, our ear has a logarithmic characteristic. Therefore, for volume regulation in radios, audio amplifiers, and television sets, potentiometers with an exponential curve must be used. Figure 10.11 shows typical curves (tapers) of potentiometers. In practice, a nonlinear curve is exactly realized by a few linear segments of resistive layer. Because each segment has another resistivity, it is necessary to use several segments to obtain a better exponential © 2003 by CRC Press LLC

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FIGURE 10.9 Photos of different potentiometers.

FIGURE 10.10 Helipot — a principle of work. Source: Bourns, Inc., The Potentiometer Handbook, New York: McGraw-Hill, 1975.

100

R/RT [%] 3

50

1 2 X/XT [%]

0 50

100

FIGURE 10.11 The main tapers of potentiometers. 1 — linear; 2 — exponential; 3 — antiexponential. XT — total wiper direction, RT — total resistance. At the beginning and at the end of wiper movements there are very low resistive paths.

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or antiexponential approximation. The minimum number of segments to perform an exponential curve is two, but then some steps in regulation are unavoidable. In production, we can achieve potentiometers performing sinus, cosinus, and other curves. Curve Parallelism of Stereo Tandem Potentiometers. A stereo potentiometer with an exponential curve has to fulfill the additional requirement for parallel curves; both potentiometers are controlled by one roller (for example, at attenuation of 40 dB the difference between both curves must be smaller than 2 dB).

Nonlinear Varistor A voltage dependent resistor (VDR), called a varistor, is a resistor whose characteristic V versus I is not a straight line and a small change of voltage causes a significant change of current according to the equation V = CI β

(10.9)

where β is nonlinearity coefficient = 0.03–0.4 (it depends on the material and manufacturing technology), C is varistor dependent coefficient. The main parameters of varistor are nonlinearity coefficient β and varistor voltage Vv measured at constant current for example 1 mA. Comparisons of the characteristics of a linear resistor and two types of varistors are shown in Fig. 10.12. A varistor can be used for dc voltage stabilization and especially for electronic circuit protection against overvoltage pulses caused by industrial distortions and atmospheric discharges. Coefficient β is calculated from (10.10): β=

lg(V2 ) (V1 ) lg( I 2 ) ( I1 )

(10.10)

when I2 /I1 = 10, the denominator is equal to 1 and β = lg V2 − lg V1

(10.11)

To explain the above relation, Fig. 10.13 is helpful, where both V and I are in logarithmic scale. The slope of the straight line segment of this curve equals β. For SiC varistors (curve 2 in Fig. 10.12), β = 0.12–0.4; for ZnO varistors however β = 0.03–0.1.

V 3 2 1

VV I

1 2 3

FIGURE 10.12 Voltage vs. current characteristics: 1 — linear resistor; 2 — SiC varistor; 3 — ZnO varistor; Vv — varistor voltage.

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lgV(V)

lgV2

α

lgV1

lg I(A)

FIGURE 10.13 Log(V)/log(I) characteristic of a varistor for nonlinearity coefficient β description. β = tgα = log V2 – log V1 ; I2 /I = 10.

10−4 10−3 10−2 10−1 1

R [Ω] 105 104

FIGURE 10.14 Characteristic R = ϕ(T) of different thermistors. NTC — negative temperature coefficient thermistor; PTC — positive temperature coefficient thermistor; CTR — thermistor with critical temperature of resistance; index N-curve falling with temperature; index P-curve rising with temperature.

10

CTRP

NT

C

PTC

103 102

CTRN

10 50

100

T [°C]

150

Varistor voltage is in the range of 4 V up to 2 kV; it depends on varistor thickness (length). To get a higher operating voltage, disk varistors should be connected in pile. Maximum pulse current is in the range of 0.2 A up to 2 kA; it depends on the diameter of the varistor body. For pulse work, the following additional parameters are important: the capacity of the varistor (it is in the range of 100 pF up to 1 µF) and absorption energy (it is in the range of 1 J up to 2200 J) (see [10]). Thermistor A temperature-dependent resistor, called a thermistor, is a resistor with significant TCR, which can be positive (PTC) or negative (NTC). Some groups of thermistors are characterized by a very rapid change of resistance in temperature. Those thermistors are called critical temperature resistors (CTR). They can be positive CTRP or negative CTRN. Figure 10.14 presents typical characteristics R versus T for different types of thermistors. NTC and PTC thermistors are used for stabilization of the working point in temperature for different electric circuits and as well as for temperature measurement. CTR thermistors are applied as protective elements against overheating in electronic circuits. CTRP’s are used in degaussing circuits in color TV tubes. In some catalogs, CTRP’s are called PTC’s (see [7]). The electrical, climatic, and mechanical requirements of thermistors are almost the same as for fixed resistors but some additional parameters were introduced as well, such as thermal time constant (in seconds), heat capacity (in J/K), dissipation factor (in mW/K), switch temperature or critical temperature in ˚C (for CTR’s only). The first three are related to the thermistor dimensions, the remaining to the row material and technological process. Photoresistor A photoresistor is a film resistor whose resistance is sensitive to the light, that is, it depends on light intensity and light wavelength λ. The latter, in turn, depends on the kind of material used as follows. For Cd S: λ = 0.4–0.7 µm, (visible light), for Pb S: λ = 0.9–3.5 µm (infrared) for Ge Si-doped Zn: λ = 4–15 µm, for Ge doped Sb: λ = 30–100 µm. This means that for a different photoresistor there exists an

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VS/VN 200 150 100 50

FIGURE 10.15 Signal-to-noise ratio versus polarization voltage VDC of PbS photoresistor, Mullard type, 615 V [3]. VS — signal voltage, VN –noise voltage, photo source temperature 473 K, f = 800 Hz, ∆f = 50 Hz.

V [V] 100

200

300

optimal wavelength at which maximum sensitivity (maximum change of resistance between lightness and darkness) occurs. During the design of a circuit with a photoresistor it is necessary to know at which polarization voltage the smallest noise exists. Figure 10.15 presents Vs /VN versus polarization voltage for a PbS photoresistor made by Mullard. Magnetoresistor Some thin film multilayer ferromagnetic structures cause changes in magnetic field H. This phenomenon is called the magnetoresistive effect. An electronic component in which the magnetoresistive effect occurs is called a magnetoresistor and is usually used as a sensor. Special preparation of a ferromagnetic multilayer allows achievement of magnetosensitivity up to 100 MHz. The change of resistance is 1–5 percent at the change of magnetic field H of about 10 Oe. Very often, two magnetoresistors are joined in a Wheatstone bridge and then sensitivity of the sensor is doubled.

Dependence on Material Properties Materials selected for resistors have played a fundamental role in resistor production. Resistive elements are composed for a metal alloy, carbon, metal oxide, and mixtures of insulating and conducting particles such as polymer and black carbon, glass and bismuth ruthenate, as well as glass and metal oxide. Semiconductors are also good materials for resistors, especially for nonlinear resistors such as varistors, thermistors, and photoresistors. Influence of Resistive Material on TCR Nonmagnetic Metals. According to Grüneisenn’s principle [2], [3] temperature influences resistivity as follows: ρT = ρΘ

T − 0.15Θ for T ≥ 0.15Θ 0.85Θ

(10.12)

1 293 − 0.15Θ

(10.13)

hv max k

(10.14)

and TCR 20 =

Θ=

where h = 6.625, Js = Planck constant, k = 1.38 J/k Boltzmann constant, Θ = the Debye temperature (for several nonmagnetic metals is given in Table 10.4), νmax = the maximal elastic frequency of the atom in a lattice of metal, and ρΘ = the resistivity of the metal at the Debye temperature.

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TABLE 10.4 Debye Temperature and Resistivity of Nonmagnetic Metals [3] Metal

ρ20 at T = 293 K [10–8 Ω ∗m]

Θ [K]

0.15 Θ [K]

ρ at Θ [10–8 Ω ∗m]

Ag Cu Au Al Zn Pt Pb W

1.62 1.68 2.22 2.73 6.12 10.6 20.8 5.39

214 320 160 374 180 220 84.5 346

32 48 24 56 27 33 12.7 52

1.16 1.94 1.17 3.79 3.65 7.91 5.5 6.76

From Table 10.4, 0.15 Θ is in the range 10–60K, which means that TCR 20 =

1 1 to 283 233

(10.15)

that is, TCR = +3500 ppm/K up to +4300 ppm/K. For nonmagnetic metal, TCR20 is constant, and temperate dependency of resistivity can be written as follows: ρT = AρΘT

(10.16)

where A = constant. It appears that for nonmagnetic metal in the range of temperature T ≥ 015Θ, resistivity is proportional to the ambient temperature. On this basis the resistive platinum thermometer is built. Magnetic Metal. For magnetic metal, for example, Fe, Ni, Co, the relation ρT = f (T) is nonlinear and given by (10.17): ρT = CT 1.7 for T ≤ Tc where Tc is the Curie temperature (see Table 10.5). TCR’s measured for iron and nickel are about +4500 ppm/K. Pure metal, both magnetic and nonmagnetic, is not useful for resistor design due to its large TCR and low resistivity.

(10.17) TABLE 10.5 Metal

TC [K]

Fe Ni Co

1043 635 1400

Metal Alloy. Increasing of resistivity with temperature can be explained by atomic vibrations in the crystalline lattice. Those atoms cause obstructions to free electrons and the higher temperature causes an increase of resistance (obstruction). Such a resistivity is the first component ρs of an alloy resistivity ρ. According to Mathiessen’s rule [2], we can add the second component of resistivity ρi, that presents obstruction of free electrons by atoms of impurities in the metal lattice. ρ = ρs + ρi ρi = const, ρi ≠ ϕ(T )

(10.18)

where ρs is given by (10.16) and (10.17). When ρi  ρs, TCR is very small. In this case ρ  ρs as well. This means that a resistor made of a specially prepared metal alloy can have very small TCR and large resistivity ρ. That result is very remarkable for a metal alloy resistor design.

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Example. Constantin 60% Cu + 40% Ni: TCR20 = 1–5 ppm/K, ρ20 = 0.49 × 10–6 Ωm in contrast with pure copper: TCR = 4000 ppm/K and ρ20 = 0.0168 × 10–6 Ωm; Canthal 70% Fe + 23% Cr + 4.5% Al + 1% Co + 1.5% other metals: TCR20 = 50 ppm/K, ρ20 = 1.4 × 10–6 Ωm. This example demonstrates that, for alloys, TCR is from 100 up to 1000 times smaller and ρ20 is from 20 up to 100 times greater in comparison to pure metals (see also Table 10.4) This information is useful for wirewound and foil resistor design. Thin Film Resistor Over 90% of thin film resistors are made of metal alloy. A thin layer of metal alloy is deposited on ceramic or glass substrate. Sheet resistance R (Ω/square) of a metal alloy thin film resistor varies from 10 Ω/square up to 200 Ω/square; the nominal resistance range is from 10 Ω to 10 MΩ; TCR ≈ 15–150 ppm/K; classes 5, 3, 2, 1; precision resistors are available. For a high nominal resistance value, the resistance layer is specially shaped by laser trimming to get enough squares. Some features of thin film layer are a bit different from bulk metal alloy. Fuchs’s and Sondheimer’s Effect [2]. When the thickness of the resistive layer is smaller than a free path of the free electron, the resistivity increases. Figure 10.16 shows the influence of normalized thickness κ on resistivity ρ: κ=

t λ

(10.19)

where t is the thickness of a layer, λ is the free path of the electron, which equals 20–30 nm [2], and κ is expressed by (10.19). Grain Effect. Because free electrons are reflected and absorbed by edges of grains, the resistivity increases when the quantity of grains becomes greater. Annealing processes of the layer limit that effect. Figure 10.17 illustrates the result of the annealing process [2]. Small grains of the resistive layer are also the reason for the large absorption of humidity and gases that causes instability of the resistor. Pyrolytic Carbon Resistor Carbon deposited in vacuum on a ceramic substrate performs very inexpensively and produces a quite good quality resistive layer. Pyrolytic carbon has graphite structure sp3 ; three electrons create bonds and the fourth is a free electron. Surface resistance is 10 Ω/square up to 2 kΩ/square; the nominal resistance value is in range 10 Ω to 10 MΩ; encountered classes are 15, 10, 5, 3 (see Table 10.1); TCR ≡ –200 to –1000 ppm/K. About 50% of the produced resistors are carbon pyrolytic ones. Thick Film Resistor A thick film resistive layer is prepared from a composition called paste or ink that is a mixture of conducting particles and glass. Conducting particles have a metallic conduction mechanism. By mixing

p=0 4 q/q° 3 2 1 0.1

0.2 0.5 0.8 10

© 2003 by CRC Press LLC

1

x

10

FIGURE 10.16 Influence of layer thickness on resistivity of metal thin film [2]. ρ0 — resistivity of bulk metal; p — quantity of reflected electrons; 1– p — quantity of absorbed electrons.

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20 1

15 10 2

5 0

200

20°C −183°C 20°C −183°C 400

600

800

t [Å]

FIGURE 10.17 Influence of annealing process on resistance of thin film [2]. 1 — before annealing; 2 — after annealing.

different quantities of both particles, we can obtain a high-range surface resistance of 1 Ω/square to 10 MΩ/square. This means that the nominal resistance range might be 0.5 Ω up to 1 GΩ; classes are 5, 3, 2, 1, 0.5; TCR = ±100 ppm/K, and ±50 ppm/K; in a resistive network, ∆TCR = 3 ppm/K and 1 ppm/K. The theory of conduction mechanisms is not well known. Several models of conduction mechanisms are used, but one of them proposed by Pike and Seager is used [9]. Each conductive particle is surrounded by glass. There particles form the chains of MIM (metal–insulator–metal). Electrons are passed through the insulator by tunneling. In the layer of very high resistivity, electrons travel according to the hopping effect [6]. Investigations show that for the very low resistivity layer, chains without glass [6] are formed. The formula for the total resistance of such a chain is as follows: R(T ) = RMI M + RM + Rc

(10.20)

where RMI M =

sin aT  1 ∆E  R 1 + exp  2 bo aT  T 

(10.21)

Rm = Rmo (1 + bT )

(10.22)

Rc = κ 3 pc (Ts − T )

−

1 3

(10.23)

where RMI M is the resistance connected by tunneling [4], Rbo is the resistance in T = 0, a is the distance between particles, ∆E is the activation energy, k is the Boltzmann constant, Rm is the resistance of the conduction particle (the resistivity value is much higher than in bulk material because its diameter is very small (0.5 µm) and grain effect occurs), Rmo is the resistance in T = 0 K (obtained by line extrapolation), b is the TCR of the conducting particle, Rc is the resistance of contact between two particles without glass), Ts is the temperature of glass melting, and k3 is the constant coefficient. For high resistance, the most important parameter is RMI M . In that range of resistance, TCR is negative and the surrounding glass layers give large voltage coefficients of resistance, which is shown in Fig. 10.30. For low resistance, VCR is negligible, and TCR is positive, which means that Rm and Rc are important while an influence of RMI M may be neglected. Equations (10.20)–(10.23) also explain the physical meaning of Tm for curve 3 in Fig. 10.4. For the very high resistivity layer, both tunneling and hopping conduction occur. Parameters for this sort of resistor are not particularly good, but only in that technology can we get high-ohmic resistor in the range of 10 MΩ up to 1 GΩ.

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(a) RT R20

(b) 140 120

20

0.7 0.6 0.5 I[A] 0.4 0.3 0.2 0.1

0

0

100 80 60 40

0

20

40

60

80

100

120

IOFF Ta = 20°C

IN

UOFF 0

0,2

0,4

0,6

0,8

1

1,2

U[V]

T [°C]

FIGURE 10.18 Characteristics of multifuse resistor. (a) Normalized resistance versus ambient temperature. (b) Current versus voltage Voff — voltage above which current decreases.

Polymer Resistor About 70% of all potentiometers are manufactured as polymer resistor. The resistive layer consists of conductive particle (black carbon, graphite, as well as metal powder) and thermosetting or thermoplastic resin. Also, a polymer layer is used for printing resistors on PC boards or for manufacturing chips in surface mounting technology. The layer is deposited by screen printing, painting, or by some other methods. Classes are 20, 15, 10, 5; TCR = –1000 ppm/K or ±400 ppm/K; surface resistance 50–1 MΩ/square; the nominal resistance range is from 100 Ω to 10 MΩ. Thermoplastic polymer resistors have generated great interest [7] recently. At the softening temperature of a polymer a strong increase of resistance is observed. TCR ∼ 100 percent/K; and alter cooling resistance retains a previous value. This phenomenon is applied to the multifuse resistor, whose characteristics are shown in Fig. 10.18(a) and (b). A multifuse is needed for protection of the electronic power circuit against fire. Polymer layers are also used in keyboards as very hard and uncorrodible contact material. For example, that layer contains carbon and copper powder. Comparison of Parameters of Different Resistors — Suggestion for Application –

Figures 10.20 and 10.21 present average instability δ of resistors made in four technologies: metal thin film, thick film, pyrolytic carbon, and polymer carbon. An analysis of these figures as well as Fig. 10.19 (a)

(b) TCR [ppm/°C]

TCR

+200

100

1k

10k 100k 1M

10M

0

−400

1

+200 0

1

−200

−600

R[Ω]

00

1k

10k

100k 1M

10M

Ρ[Ω]

−200 −400

2

−600

−800

−800

−1000

−1000

2

FIGURE 10.19 TCR dependence on nominal resistance value. (a) 1 — thick film ruthenium-based resistors; 2 — pyrolytic carbon resistors. (b) 1 — thin film metal alloy resistors; 2 — polymer carbon resistors. The envelope of the TCR range is calculated statistically at ±1.64∗ s.

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− δ [%]

70°C; P = Pn; (V = Vnom) 1000h.

4 2

1

3

2

0 100

1k

10k

100k

1M

10M 100M R[Ω]

−2 −4

4

−6

–

FIGURE 10.20 The average change δ after 1000 h endurance test in relation to a nominal resistance value for different types of resistors. 1 — pyrolytic carbon, 2 — thick film ruthenium-based resistor, 3 — thin film metal alloy, 4 — polymer carbon. For the range 100 Ω – 240 kΩ P = Pn, above 240 kΩ P < Pn and V = Vmax.

− δ [%]

21 days, 40°C, 95% r.h. 4

10 8 6

3

4

2

1

2 100

1k

10k

100k

1M

10M 100M R[Ω]

FIGURE 10.21 The average change δ after 21-day humidity test dependence on the nominal resistance value of different types resistors. 1 — thin film metal alloy, 2 — thick film ruthenium-based resistor, 3 — pyrolytic carbon, 4 — polymer carbon.

gives us a clue as to how to choose a resistor for a specific application. For example, we would like to find a resistor of a nominal resistance value of 1 MΩ to operate under high humidity conditions. A thick film resistor would be the best. Taking into consideration the price, a pyrolytic carbon resistor, class 10 or 5 should be chosen. In an operational amplifier application, a thin film resistor or thick film network would be the best choice, although for a small-signal preamplifer considering the small noise level, a thin film resistor would be preferred. Considering our decision, we should pay attention to the results of the following tests: TCR = ϕ(R), endurance test ϕ(R) for 1000 h, humidity test, 21 days: δ = ϕ(R). Influence of Ceramic Substrate on Parameters of Resistor All resistive films are deposited on the ceramic substrate. Only polymer film can be put on the fenolic paper or on the epoxy resin substrate. Thick film, pyrolytic carbon, and metal alloy film are also deposited on the ceramic. Some of thin films may be deposited on the glass. It is observed that substrate affects the resistive layer in two ways, as follows: 1. When ion current related to alkali metals in substrate flows. Its destructive effect is shown in Fig. 10.22, where some pyrolytic carbon layers manufactured by the same technology were deposited on the three types of ceramic substrates. The densities of the ion current were 56 µA/mm2, © 2003 by CRC Press LLC

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− δ [%] 10 8

j = 56 µA/mm2 3

6

240 kΩ +70 “C, Pnom V = Vmax

4

j = 7.5 µA/mm2

2 2

t [hours] 0 1

500 1000 j = 1.05 µA/mm2 –

FIGURE 10.22 Influence of ion current density j on resistor stability δ versus time during endurance test. R = 240 kΩ (critical nominal resistance value); j is measured according to GOST 10449-63, that is, 400°C and 400 V; distance of cut layer 0.5 mm.

(a)

(b)

(c)

FIGURE 10.23 Different means of wire winding in wirewound resistors: (a) flat; (b) cross; (c) bifilar.

7 µA/mm2, and 0.5 µA/mm2. The results of long-life stability changes for resistors deposited on various substrates differ greatly from each other. This effect is observed only at dc voltages and at high temperatures. The smaller thickness of a layer and the destructive effect of ion current is more remarkable. During long-life tests at high temperatures, this phenomenon can also be observed for high-ohmic wirewound resistors [1]. 2. When the thermal expansion coefficient of a layer and substrate are much different, thermal dilatability becomes a large problem and results in plus or minus changes of TCR [1]. Encapsulation of resistors with lacquer, cement, and transfer molding cover causes similar problems.

Dependence on Geometry of Material The geometry of a resistive element affects either its high-frequency characteristic or its maximum temperature. Influence of Resistive Element Shape on the Frequency Range A wirebound resistor has many advantages but its inductance is very high. In Fig. 10.23, different ways of resistive wire winding are presented in order to decrease parasitic inductance. A special wirewound resistor can work up to 200 kHz. For higher frequencies, a thin film resistor must be used. Though a film resistor can work at high frequencies up to 1 GHz, some limitations occur in this area (see Fig. 10.24). For resistors of a low resistance value, that limitation is inductance of resistive elements and terminations. For resistors of a resistance above 10 kΩ, distributed capacitance is the main problem. Figure 10.25 presents the part of thin film layer deposited on a cylindrical ceramic substrate. To get many more squares, cutting along the screw line is performed. Each step of the screw wind [Fig. 10.27(a)] gives some elementary resistance Rr and elementary parasitic capacitance Cr. The maximum operating frequently fm is given by (10.24) as © 2003 by CRC Press LLC

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(a)

(b) R≈/R=

R>10kΩ

R≈/R=

12

1.0 0.5 11 winds

0.2

0.6 7–8 winds 4 winds

0.2 0 0.5 1

10

100

3

2

1

0.1 0.05 300

R*f [MΩ]*[MHz]

0.1

1.0

100 R*f [MΩ*MHz]

10

FIGURE 10.24 Dependence of R~ /R= on the product of nominal resistance value and frequency. (a) Pyrolytic carbon resistors, 0.25 W, cut according to screw line; different curves present resistors with different winds of cutting; (b) 1 — thin film, 2 — pyrolytic carbon, 3 — thick film ruthenium-based resistor [3].

C1

FIGURE 10.25 Part of a film resistor cut according to the screw line; Rr — elementary resistance, Cr — elementary capacitance.

R1

C2

Cr

R2

Rr

1 2

FIGURE 10.26 Coaxial resistor: 1 — resistive layer: 2 — electrode layer.

a)

b)

c)

100° ± 005° (2.54 + 13)

R4

5

2 1

3 4 5

100° (2.54)

4

1

R1 INPUT

R2 R3

OUTPUT

2

3

FIGURE 10.27 High-frequency attenuator [7]. (a) Overview; (b) pin localization; (c) electrical circuit.

2π f m =

1 RrCr

(10.24)

where Cr is bigger when the thickness of the layer is greater and the groove becomes narrower, but also when εr of the insulating cover is high; Rr is smaller when Ω/square is lower. This information suggests how to choose a resistor for high frequency. It is seen that a thin film with a low Ω/square is recommended. To reduce the termination capacitance for coaxial lines or cables, coaxial

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1 2

3 4

5 1-electrode layer 2-resistive layer 3-narrowing area of the resistive path 4-alumina substrate 5-wire termination

FIGURE 10.28 Fail-safe resistor.

resistors are used (see Fig. 10.26), which can work up to 20 GHz. For high-frequency applications, special shapes of resistors have been designed (Fig. 10.7). Strip resistors are connected to a microwave strip line. A special potentiometer of 75 Ω input and 75 Ω output works up to 1 GHz. This potentiometer has fluent regulation of the attenuation obtained by specific shapes of three resistive elements inside the potentiometer, which, in turn, are regulated by one appropriately shaped slider (a similar attenuator for 300 MHz is shown in Fig. 10.27). Sensitivity Improvement of Precision Potentiometer by Complication of Shape In Fig. 10.10, how a helipot works is explained. The wiper makes a rotation of 3600˚ and the precision is about 0.01 percent. The range of resistance is 100 Ω to 100 kΩ. The producers are Beckman, Bourns, and others. Influence of Resistor Shape on its Application The typical requirement for resistor construction is to establish a uniform temperature on the entire surface of the resistive element. This problem does not appear in the designing of a fail-safe resistor. The fail-safe resistor is shown in Fig. 10.28. At the center of the resistive layer a narrow resistive path is placed [6]. Under normal working conditions, the resistance of the circuit is stable. When a defect occurs in the circuit, the current doubles or triples in path and breaks the fail-safe resistor. This is important in protection against fire and avalanche devastation of the electronic set. The resistors utilizing the piezoresistive effect for pressure detection are also specially shaped.

Nonideal Linear Resistor The main features of the nonideal resistor is its instability in time, which is described in the introduction to the section on resistors and instability related to temperature, presented in the Introduction and in the section on the influence of resistive material on TCR. Catastrophic failure rate is estimated: for thin film resistors on the level of 10–9/h, for thick film resistors on the level of 10–10/h. Noise is also an important feature of the nonideal linear resistor. Noise Total noise is the sum of a number of factors, summarized as follows. Thermal Noise Called Johnson Noise or White Noise. The value of thermal noise can be calculated from (10.25): Vt (RMS) = 4kRT∆f

(10.25)

where VtRMS is the root-mean-square value of the noise voltage [V], R is resistance value [Ω], k is the Boltzmann constant (1.38 × 10–23 J/K), T is the temperature [K], and ∆f is the frequency bandwidth [Hz] over which the noise energy is measured. The spectral density of thermal noise is constant in the total frequency bandwidth (white noise). Total noise is the sum of VtRMS and current noise VtRMS : © 2003 by CRC Press LLC

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µVRMS/V= 10 c 1 b 0.1

a

R

0.01 1kΩ

10kΩ

100kΩ

1MkΩ

10MkΩ

FIGURE 10.29 Simplified current noise characteristics versus nominal resistance value for different types of resistors: (a) thin film, (b) pyrolytic carbon, (c) ruthenium-based thick film.

VRMS = VtRMS + ViRMS

(10.26)

Current Noise or Structural Noise. When dc voltage is applied to resistor, dc current causes ac voltage fluctuation. That ac voltage fluctuation depends on the structure of the resistive element and an applied voltage. Density of that noise can be described by (10.27): ViRMS = cf − γ V=α ∆f

(10.27)

where c, γ, and α are constants, V is the applied dc voltage, and ∆f is the frequency bandwidth, γ = 0.98 – 1.2; very often γ = 1 and this kind of noise is called “1/f noise”; α = 1–2 and depends on the structure of the resistive element. ViRMS is measured in [µV/V] or in dB, where 0 dB = 1 [µV/V]. For foil and wirewound resistors, ViRMS = 0 and this means that only thermal noise occurs there. Fig. 10.29 illustrates simplified characteristics of current noise for different types of film resistors. Voltage Coefficient of Resistance (VCR) A linear resistor can exhibit some deviations from Ohm’s law (10.1). This nonlinearity, called the voltage coefficient of resistance (VCR), is measured in [%/V] and is calculated from (10.28): VCR =

R1 − R2 ⋅100[% V ] R2 (V1 − V2 )

(10.28)

where R1 is the resistance at the rated voltage V1 and R2 is the resistance at 10 percent of the rated voltage V2. Metal alloy film resistors and pyrolytic resistors show a negligible small voltage coefficient but polymer resistors and thick film resistors have a remarkable one. In Fig 10.30, normalized R/R10 versus voltage stress for the ruthenium-based thick film resistors are presented, where R10 is resistance measured at stress 10 [V/mm]. Results are collected for low stress voltage in Fig. 10.30(a) and for high stress voltage in Fig. 10.30(b). It can be ovserved that for a resistor made of a low-resistivity ink up to 100 KΩ/square, VCR is small, but for inks of high resistance/square (for example, 500 MΩ/square), VCR is large [6]. VCR depends on the ink producer, as well [see R310 in Fig. 10.30(b)]. Rotational Noise and Contact Resistance Variation [CRV] When a potentiometer is supplied by dc voltage and its wiper is moving from the beginning to the end of resistive layer, some ac voltage appears on the output. It is noise, which is measured in [mV/V=]. The © 2003 by CRC Press LLC

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(b)

(a) R/R0 1.6

R/R10

293 k

1.5

1.0

500MΩ/

1.2 1.1 1.0

1.5MΩ/

20 30 40 50 60 70 80 100MΩ/

200kΩ/

0.8

100MΩ/ 1.5MΩ/ 50MΩ/

0.7

100MΩ/ + 0.1MΩ/

0.02 0.05 0.1 0.2 0.5 1

90 100 k [v/mm] 50MΩ/ 90kΩ/

0.9

1.4 1.3

10

2

5

500MΩ/

0.6 10

R310 DP

0.4

k [v/mm]

FIGURE 10.30 The change of resistance vs. stress voltage for thick film resistors: (a) for low stress; (b) for high stress [6]. (a)

R

3 no step

step 2

1

wiper way

(b) III

II S

FIGURE 10.31 Shaping of exponential curve: (a) resistance vs. wiper movement, the slopes 1, 2, 3 are proportional to resistivity of layer and ρ1 < ρ2 < ρ3; (b) junction of resistive layer area marked by s is the saw-tooth-shaped junction of segment II and segment III.

IEC standard requires that for a quality potentiometer this noise has to be smaller than 2[mV/V=]. The contact resistance variation (CRV) is important when the resistor works in series with the load or in a very sensitive instrument. This parameter is measured in percentage of total resistance; (1% is a typical value). CRV and rotational noise decrease if a multipoint wiper is used in potentiometers, for example, a wiper made from 20 wires. That parameter is also important in the construction of a precision wirewound potentiometer where CRV must be smaller than 1%. The proper choice of materials for the slider and resistive wire is the best way to solve this problem. Smoothness of Regulation Curve of Potentiometer Exponential Curve. In practice, an exponential resistive element consists of two or three linear segments of resistance. As a result, the line is not smooth but has some steps. Rotary noise also increases in that area. More experienced producers use several segments and then the junction is not very sharp but are sawtooth shaped (see Fig. 10.31). Linear Curve in a Helipot Precision Potentiometer. In a precision potentiometer, the resistance of the resistive element should be proportional to the distance traveled by wiper. In Fig. 10.32, ∆r1 and ∆r2 are the maximum deviation from a single line. The nonproportionality NP of a precision potentiometer is described by (10.29): NP =

∆r1 + ∆r2 ⋅ 100% Rc

(10.29)

The value of NP is 0.5–0.01 percent. Such a good result is obtained by fluent control of the proportionality over winding of the wire. © 2003 by CRC Press LLC

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R Rc

∆r2 ∆r1

0.5Rc

rotation angle 1800°

3600°

FIGURE 10.32 Resistance vs. rotation angle (wiper movement) in precision linear potentiometer.

References [1] G. W. A. Dummer, Fixed Resistors, London: Pitman, 1967. [2] L. I. Maissel and R. Glang, Eds., Handbook of Thin Film Technology, New York: McGraw-Hill, 1970. [3] Handbuch der Elektronik, S. Nowak, A. Wenta, and E. Kuzma, vol. 2 and A. Ambroziak et al., vol. 7, Munich: Franzis-Verlag, 1979. [4] C. A. Neugebauer and M. B. Webb, “Electrical conduction mechanism, in ultrathin evaporated metal films,” J. Appl. Phys., vol. 33, p. 74, 1962. [5] S. Nowak and D. Lusniak-Wojcicka, “Thick film fail-safe resistors,” Electrocompon, Sci. Technol., vol. 10, no. 4, p. 255, 1983. [6] S. Nowak, “Nonlinearity of thick film resistors,” Rozprawy Elektrotechniczne, vol. 4, 1989. [7] Philips Components Catalogue, Eindhoven, 1989. [8] Bourns, Inc., The Potentiometer Handbook, New York: McGraw-Hill, 1975. [9] Pike, G. E. and C. H. Seager “Electrical properties and conduction mechanism of Ru-based thick film (cermet) resistors,” J. Appl. Phys, vol. 48, no. 12, pp. 5152–5168, Dec. 1977. [10] Siemens Matsushita Components Catalogue, Munich, 1993. [11] R. W. Vest, “Conduction mechanism in thick film microcircuits,” Final Technical Report, Purdue Univ. Res. Foundat., Grant DAHC-15-70-67, DAHC-15-73-68, ARPA Order: 1642, December 1975.

10.2 Capacitor Stanis l aw Nowak Introduction A capacitor is a container of the electric energy W. This is expressed by (10.30). W=

CV 2 2

(10.30)

where C is the capacitance expressed in farads and V is the voltage on the capacitor plates expressed in volts. Capacitance C of the multiplate capacitor can be described by (10.31): C=

xε r (N − 1) A −13 10 d

(10.31)

where εr is the relative dielectric constant of the insulator, d is the distance between the plates, N is the number of plates, and A is the plate area, where x = 0.0885 for A and d expressed in centimeters or x = 0.225 for A and d in inches. © 2003 by CRC Press LLC

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TABLE 10.6 Comparison of Capacitor Dielectric Constants εr (Dielectric Constant)

Dielectric Air or vacuum Paper Plastic Mineral oil Silicone oil Quartz Glass Porcelain Mica Aluminium oxide Tantalum pentoxide Ceramic

1.0 2.0–6.0 2.1–6.0 2.2–2.3 2.7–2.8 3.8–4.4 4.8–8.0 5.1–5.9 5.4–8.7 8.4 26 12–400,000

Source: R. Dorf, Ed., The Electrical Engineering Handbook, 1993. Boca Raton, FL: CRC Press.

The relative dielectric constant value εr is equal to the ratio of capacity of a capacitor with plates separated by a dielectric to one separated only by vacuum. Dielectric constant values of various materials are presented in Table 10.6. Fundamental parameters of capacitor are as follows: capacitance C, nominal voltage VN, testing voltage Vt (note that Vt = (2–3) VN), temperature coefficient of capacitance TCC (for class 1 only), insulation resistance Ri (for dc voltage), and power PF (for ac voltage). Power factor PF is described by the (10.32) PF = rCω = 2πfr C

(10.32)

where r is an equivalent series resistance. Its inversion is a quality factor Q, given by (10.33). Because the power factor expresses total losses in capacitor, it is a sum of the dissipation factor and losses in electrodes as well as in terminations. Q=

1 1 = PF 2πfr C

(10.33)

According to IEC Publ 384/1988, capacitors are divided into two salient groups: class 1 and class 2 but also more detailed classifications are commonly used because of the wide range of capacitances and very different applications. The main applications of capacitors include filtering, coupling, tuning, dc blocking, ac passing, bypassing, phase shifting, compensation, through feeding, isolation, energy storage, noise suppressing, motor starting, and so on. Contemporary capacitors cover the 0.1 pF up to 10 F capacity range and the 2.5 V to 100 kV voltage range. Connecting a dc voltage source to the capacitor plates we can observe the given capacitor is gradually charged and current flowing through the capacitor, large at the beginning, decreases in time to negligible small value. On the other hand, ac source causes the current I, given by the (10.34), flowing permanently through the capacitor. I=

V V = = V 2πf C X c (1) (2πf C )

(10.34)

This current increases when capacitance, frequency, or applied voltage increase. The ac current can heat the capacitor, whose temperature would depend on its power factor, capacitor size, and cooling conditions. This phenomenon has to be taken into consideration in energetic 50 Hz equipment or in highfrequency power applications. Miniaturization and integration of electronic sets influences miniaturization © 2003 by CRC Press LLC

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The Circuits and Filters Handbook, Second Edition TABLE 10.7 υ′ Index of Various Capacitors Capacitor Definition Variable air Mica Ceramic (rutile) Ferroelectronic Ferroelectric multilayer Polystyrene Polyester (mylar) Polycarbonate — metalized Electrolytic Al(HV)a Electrolytic Al(LV)a “Golden” capacitor Electrolytic Ta (wet) Electrolytic Ta (dry)

Main Parameters

υ′ [cm3/µF]

500 pF/250 V 10 nF/500 V 1000 pF/500 V 40 nF /250 V 0.68 µF/50 V 2 µF/160 V 0.1 µF/160 V 0.15 µF/160 V 40 µF/350 V 120 µF/7 V 1 F/5.5 V 10 µF/100 V 5.6 µF/10 V

200,000 250 600 50 1.5 300 12.4 5.6 1.3 0.008 0.00001 0.038 0.0026

a

HV: High voltage, LV: low voltage. Source: L. Badian, Handbuch der Electronik., Munich: FranzisVerlag, Vol. 3, 1979.

of capacitors as well. The index υ′, called “own volume” (volume per capacitance) and expressed in [cm3/µF], might be of use during selection of a capacitor for a given circuit. Nominal voltage VN strongly affects the index υ′ value. Table 10.7 presents the index υ′ for capacitors with various dielectrics. From the user’s point of view, capacitors can be divided as follows: linear and nonlinear, fixed capacitors, adjusting capacitors, power energetic capacitors, start motor capacitors, and interference suppression capacitors.

Linear Capacitor The linearity of a capacitor depends on the polarity of the dielectric used for its manufacture. Several different polarization mechanisms can contribute to the total polarization. The most important are the following: 1. Electron polarity that exists in the insulator with covalent bonds between atoms; electrical stress causes deformation of the orbital shape but electrons cannot go out of orbit (relaxation time τ is smaller than 10–15 s). 2. Ion polarity that occurs in glass and high-quality ceramic; under electrical stress ion centers are displaced (τ < 10–13 s). 3. Dipole polarity that occurs in a polar polymer dielectric. Electric field causes rotation of dipoles in the dielectric. Generally dielectric constants εr depends on frequency, temperature, and voltage, but in limited ranges of these factors εr is stable. 4. Domain polarity that appears in some insulators, for example, ferrodielectrics. They contain domains that rotate with electric field. This effect is called ferroelectricity because of the analogy to ferromagnetism and gives rise to very high dielectric constant εr up to 400 000 (see Table 10.6). It strongly depends on voltage, frequency, and temperature. Ceramic capacitors with a domain polarity mechanism and high dielectric constant are very popular in electronic equipment. Only capacitors with electron polarity and ion polarity are classified in linear capacitor group 1. The linear capacitor group consists of fixed capacitors in class 1, adjusting capacitors, energetic capacitors, high-voltage capacitors, and interference suppression capacitors. Fixed Capacitor — Class 1 The main feature of a fixed linear capacitor with class 1 dielectric materials is its stability in time and under temperature. By analogy to resistors we can introduce dynamic tolerance ∆ (see the subsection on the fixed resistor in Section 10.1) for capacitance. Production tolerances δp (±) for class 1 capacitors are © 2003 by CRC Press LLC

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TABLE 10.8 TCC and Max Capacitance of Monolithic Ceramic Capacitor Maximum Capacitance [pF]

Dimension a × b [mm] TCC ppm/K 4×4 8×8 10 × 10 a

NP 0

N 75

N 150

N 750

Ferrodielectric

0 ± 30

– 75 ± 30

– 150 ± 30

– 750 ± 30

Large

47 680 4700

47 680 4700

47 680 4700

150 1600 6800

10,000 470,000 1,000,000a

Some producers offer maximum capacitance C = 4.7 µF at dimensions of 10 × 10 mm.

±0.25, ±0.5, ±1, ±2, ±5, ±10, and ±20%. The instability δmax expressed by (10.35) after the endurance test is up to 3% (IEC Publ. 384-8). δ max = δ + 1.64 ∗ s

(10.35)

–

where δ and s are accordance with the formula (10.4) and (10.6), respectively, and δi =

Ci (t ) − Ci (0) * 100% Ci (0)

(10.36)

δmax for capacitor is larger than for a stable resistor. This also means that dynamic tolerance ∆ for capacitors is larger than for resistors, which should be considered during active rc filter design. The temperature coefficient of capacitance (TCC), given in Table 10.8 describes temperature stability of capacitors. Negative TCC capacitor may be used to compensate positive temperature coefficient of inductance in resonant LC circuit. The next important parameter of capacitors in class 1 is a power factor that is required to be smaller than 30 ∗ 10 –4. Ceramic capacitors with low εr as well as styroflex and mica capacitors meet these conditions, which renders them very suitable for resonant circuits, stable analog filters, integrator circuits, and other circuits where stable capacitance and small losses are necessary. Ceramic capacitors are produced as tubular, disk, and multilayer (monolithic) capacitors. Disk and tubular ones are inexpensive. Multilayer capacitors are rather expensive but they have small dimensions and low index υ′. Figure 10.33 presents some types of fixed capacitors. Adjustable (Variable) Capacitor An adjustable capacitor is an electronic component whose capacitance can be mechanically regulated by the user. For example, an AM radio set tuner is adjusted using a variable capacitor of 10 pF up to 500 pF. The dielectric used in this type of capacitor is either air or plastic foil. The majority of variable capacitors are trimmer capacitors for precision adjustment of reactance in electronic circuits. Their insulator layer is made of air, ceramic of class 1, mica, polystyrene, or teflon. Typical trimmer capacitors are shown on Fig. 10.34. They have the following capacitance ranges: air trimmer, 1–15 pF; tubular ceramic trimmer, 0.1–7 pF; disk trimmer, 10–50 pF; special disk trimmer, 100 pF maximum. The power factor is small (1–20) ∗ 10–4. Insulating resistance is above 1010 Ω. Nominal voltage is 100–500 V. Energetic Power Capacitor To compensate inductance in electrical engines and other equipment, energetic power capacitors are used. Besides capacitance it is important to know their resistance power expressed in [VAr] (between vectors of voltage and of current there is an angle 90˚). They are rather large in size and weight of 10–50 kg per unit. The smaller ones are capacitors used to discharge lamps. They have a capacitance range 2.5–20 µF and ac working voltage of 150 V effective voltage up to 550 V. Starting motor capacitors also belong to © 2003 by CRC Press LLC

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(a)

(b) 3 4 I

II

2

1 (c)

(d)

(−)

(+)

(e)

(f)

seating plane

FIGURE 10.33 Typical fixed capacitors. (a) Multilayer ceramic (monolithic) [6]: 1,2 — termination, 3 — dielectric layer, 4 — inner termination; I,II — plates (capacitor electrodes). (b) Tubular taped [8] (connected in tapes for automatic assembling). (c) Aluminium electrolytic (wet) with axial terminations. (d) Tantalum electrolytic (dry) with radial terminations. (e) Polystyrene foil with axial terminations. (f) Metalized film [6].

3

3

2

2

1 4 5

1′

1 3 4

3 1 I II

2

2 (a)

1′ (b)

(c)

FIGURE 10.34 Typical trimmer capacitors. (a) Tubular ceramic: 1 — ceramic tube, 2 — hot electrode, 3 — soldering point, 4 — earthed electrode, 5 — screw for capacitance regulation. (b) Flat ceramic: I — grounded electrode (plate), 1 — roller for capacitance regulation (electrically connected with termination 1′); II — hot electrode connected with termination 2, 3 — ceramic plate. (c) Cylindrical air: 1 — grounded roller (screw) connected with termination 1′, 2 — hot electrode, 3 — coaxial cylinders; capacitance regulation is achieved by moving cylinders up and down.

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(a)

(b)

(c) Ib

IIb 1

Ib

IIb

Ib

IIb

Ia IIa

FIGURE 10.35 Metalized polypropylene capacitor. (a) The roll during winding; (b) cylindrical roll; (c) flat roll: 1 — polypropylene foils, Ia,IIa — metalized layer deposited in vacuum, plates (electrodes) of capacitor, Ib,IIb — contacts, deposited by high-pressure airbrush with melted metal.

this group of power capacitor. The majority of power capacitors have paper, polypropylene, or mixed dielectrics, and they are impregnated in vacuum against flashover. An impregnant substance, such as mineral or synthetic oil is used. It is very important to match the dielectric constant of the oil with that of the fixed dielectric because it will guarantee uniform distribution of the electric field inside the unit. In some capacitors of smaller size, polypropylene without an impregnant is used as an insulator. Electrodes are made of aluminium foil or deposited with thin metal film on the dielectric. The power factor of these capacitors is required to be low with respect to heat dissipation. According to IEC Publ. 384-17 the maximum power factor is < 50.10–4 at working frequency and for 1.25 Vn of nominal voltage. Under overheating, the capacitor reliability falls and lifetime shortens. Polypropylene is chosen as the insulator material because of its good dielectric properties. For example, its PF = (6–7) ∗ 10-4, εr = 2.1, TCC = –200 ppm/k and over the temperature range up to 110°C it is stable. The elementary cylindrical section of the power capacitor is presented in Fig. 10.35(a) depicts two polypropylene foils on which electrodes (Ia and IIa) were evaporated in vacuum. It is important to provide a fixed, multipoint junction between electrodes (Ia and Ib) and (IIa and IIb). It shortens the path of the current, which at ac voltage is high. That construction reduces the equivalent series inductance of the capacitor at high frequencies. High-Voltage Capacitor A high-voltage capacitor for dc voltage and low frequencies is made of polymer foil, but for high-frequencies ceramic capacitors are preferred. They can be disk shaped up to 6 kV (Fig. 10.36) or tube shaped for very high voltage applications. It is easier to protect a tube-shaped capacitor against flashover. Some additional information will be presented in the section on the shape of the high-voltage capacitor. To gain a high-voltage level it is sometimes necessary to connect several capacitors in series. In this case, initially we must select an elementary capacitor. In order to get equal voltage drops on each element we should choose elementary capacitors having the same capacitance for ac voltage and the same insulating resistance for dc voltage. Dielectric Absorption. According to (10.30), high electrical energy can be stored in power and highvoltage capacitors. Danger to human life may exist even several hours after switching off the circuits that contain such capacitors. Also, capacitors discharging by short circuiting are not nearly safe enough. Because of dielectric absorption some dangerous charge remains on the capacitor electrodes. To prevent accidents, high-energy capacitors should be shunted by high-ohmic resistors. Interference Suppression Capacitor This type of capacitor is characterized by low inductance. To accomplish this, a specific construction has been developed, where two or three capacitors are joined in a special way and put into one encapsulation. Figure 10.37 presents an example of this construction. Interference suppression capacitors are divided into two classes: X or Y. Capacitors of class X fulfill lower safety requirements because their breakdown is not dangerous to human life. Capacitors of class Y are used in extremely dangerous environments, where, for example, breakdown causes a short circuit between the body of the equipment and an energetic phase of 50 Hz. Properties of these two types of capacitors vary. For example, the 4 µF/250 V capacitor © 2003 by CRC Press LLC

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(a) × I

2 1

II

2

(b)

2

2

2

1 Ia

II

1

FIGURE 10.36 High-voltage ceramic capacitor. (a) Tubular: 1 — inner, high-voltage electrode, II — grounded electrode, 1 — ceramic tube, 2 — wire terminations. (b) Disk (bar) ceramic: I — ceramic bar, 2 — wire termination, Ia,IIa — plates of capacitor, made by screen printing; x — distance for high voltage.

(a)

(b) IV

III II I

4″ 5″

2

5 6 3 4 1

4′

6′

5′

(d)

(c) 1 VT

3

C1

C3 C2

2

1

C1

C3 VT

C2

2

FIGURE 10.37 Capacitor for radio interference suppression. (a) Construction principle of three capacitance interference suppression capacitor; I,II,III — Al foil electrode, IV — polymer foil insulator, 1,2,3 — wire terminations, 1,2 — wire leaded through, 4,5,6,4′,5′,6′,4″,5″ — pretinned copper foil contact. (b) Electrical circuit. (c) Circuit for testing in class X. (d) Circuit for testing in class Y. © 2003 by CRC Press LLC

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4 3

1

2

FIGURE 10.38 Feed-through capacitor. 1 — ceramic tube, 2 — wire termination lead through, connected with the inner electrode of the capacitor, 3 — external electrode, 4 — metal plate. Connection between 3 and 4 is made by soldering. ∆C C [%] 0 −40

0.4

1.2

2

2.8

3.6 E [KV/mm]

εr = 2000 εr = 7000

−80

FIGURE 10.39 Dependence of capacitance on stress voltage at different εr of ceramic capacitor of class 2.

that belongs to the X class, has a test voltage on the level of 1100 V; however, the one of the Y class has to withstand 2250 V. Also, circuits for testing these two types of capacitors (according to IEC Publ. 384-14, 1993) differ from each other [see Fig. 10.37(c) and (d)]. In Fig. 10.37(b), a lead-through capacitor is shown. The first capacitor is positioned between the two leads. The second and the third leads are arranged between separate leads and the ground. For radio frequencies, polymer capacitors may be used but for very-high-frequencies, ceramic ones are preferred. A special kind of feed-through ceramic capacitor is shown in Fig. 10.38. It should be noted that automotive capacitors have to fulfill some additional requirements to withstand ignition system pulses.

Nonlinear Capacitor As was described in the section on the fixed capacitor, the dipole and domain polarity mechanism in a dielectric is related to the nonlinearity of the capacitors. Ferrodielectric capacitors and polar polymer capacitors are nonlinear capacitors. Ferrodielectric Capacitor Ferrodielectric ceramic capacitors are known for strong depenTABLE 10.9 dence of their capacitance on temperature, voltage, and frequency. Maximal Changes of Cn They are constructed in tubular, disk and monolithic multilayer Subclass [%] versions. Each version fulfills requirements of class 2 ceramics. By 2B +10, –15 mixing different kinds of ceramics, we can get a dielectric compo2C +20, –30 sition of εr ranging from 1000 up to 30 000. The maximum available 2D +20, –40 εr is 400 000 (see Table 10.6). Nevertheless, it should be noted that 2E +22, –70 for production scale, such a dielectric constant is not reached 2F +30, –90 because of its poor stability. Figure 10.39 shows the effect of capacitance instability ∆C/C versus voltage stress for different εr values. If the 25% of change δ in capacitance is required, the maximum bias dc is 2000 V/mm (for εr = 2000); for stronger stress the change will be much greater. Great valve of εr , low series inductance, and small dimensions make ferrodielectric capacitors very useful in high-frequency applications up to 1 GHz. We can divide the class 2 ceramics into five subclasses: 2B, 2C, 2D, 2E, and 2F. Maximal changes of capacitance in the maximum category temperature are presented (in Table 10.9). This means that the ferromagnetic capacitor must have minimal capacitance but its stability is not as important. Figure 10.40 presents the © 2003 by CRC Press LLC

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(a) ∆ε/ε εr ≈ 1200 ÷ 2000

120

1 2

80 40 0 −60

T −40

−20

0

20

40

60

80 100°C

(b) ∆ε/ε

εr ≈ 3000 ÷ 4000

120 80

1 2

40 0 −60

T −40

−20

0

20

40

60

80 100°C

(c) ∆ε/ε εr ≈ 7000 ÷ 10000

120 80

1

40 0 −60

T

2 −40

−20

0

20

40

60

80 100°C

FIGURE 10.40 Normalized change of dielectric constant ∆ε/εr versus temperature for class 2 ceramic. Source: Handbuch der Electronik, vols. 2 and 3. Munich: Franzis-Verlag, 1979. (a) Dielectric constant εr = 1200–2000, (b) dielectric constant εr = 3000–4500, (c) dielectric constant εr = 7000–10th 000; curve 1 at very low voltage; curve 2 at bias 8 kV/mm.

dependence of the relative change ∆ε/εr [3] on temperature for various dielectric constants. Higher values of εr show larger inequality of curves. Changes are larger when voltage stress is smaller than what is depicted in Fig. 10.40(c). Figure 10.41 illustrates the influence of frequency on capacitance and power factor. It can be noted that up to 1 GHz the changes are acceptable. Production tolerance δp also differs from values in class 1, for example, –40, + 80%; –20, +80%; –20, +50%; ±20, ±10%. Series of nominal voltage are 25, 40, 63, 100, 160, 250 (200), 400(500), 630, 1000, and 1600 V. The maximal power factor is 350 ∗ 10–4; after an endurance test it can increase up to 500 ∗ 10–4 or 700 ∗ 10–4. Polar Polymer Dielectric Capacitor Miniaturization of a capacitor is so important in the design of electronic circuits that often a capacitor less stable but smaller in size may be chosen. The polar polymer capacitor exhibits such a feature; as an example, a metalized polycarbonate foil (macrofol) capacitor is used. Its construction is similar to the polypropylene capacitor shown in Fig. 10.35. Polycarbonate foil 3-µm thick is selectively covered by a thin (≤0.5 µm) layer of Al in the PVD process. An aluminium layer (marked by Ia and IIa) functions as © 2003 by CRC Press LLC

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(b) P.F.

(a) εr

1000

1500

500

1000 εr = 1500

500

εr = 1500

200 f [Hz]

100 f [Hz]

103 105 107 109 103 105 107 109

FIGURE 10.41 Dependence of dielectric constant and power factor on frequency. (a) εr vs. frequency; (b) PF vs. frequency. Source: Handbuch der Electronik, vols. 2 and 3. Munich: Franzis-Verlag, 1979.

the electrode of the capacitor. Very often a flat coil is used [see Fig. 10.35(c)] in capacitor construction; contacts Ib and IIb are deposited by a high pressure airbrush with melted metal; terminations are connected to the contacts by soldering; encapsulation is made by epoxy cover. It is a class 2 capacitor; the voltage series range is 63, 100, 160, and 250 V (for different polycarbonate foil thicknesses). Capacitances in series E-6 and E-12 range from 4.7 nF up to 10 µF. The power factor is ≤30 ∗ 10–4 and decreases with increasing temperature. The maximal frequency is about 1 MHz; at frequencies above 100 kHz, the power factor increases up to 200 ∗ 10–4 and the capacitance decreases several percent. The climatic categorization is –55/ + 100/56; the time constant is Ri ≥ 5000 s. It operates at both dc and ac voltages (for example, dc voltage of 630 V = corresponds to ac voltage of 220 Vrms).

Dependence on Material Properties Dielectrics have played a fundamental role in capacitor performance (see Tables 10.6 and 10.7). Air capacitors, mineral oil capacitors and mica capacitors, as well as polystyrene and teflon capacitors mentioned above, are ranked as class 1 capacitors. Capacitors with natural dielectrics (air, oil, mica) are primarily older types. Perspective dielectrics for capacitors are polymer, ceramics type I and type II, thin film oxide (electrolytic), and electric double layer. Nonorganic Capacitor Nonorganic insulating materials are often used as dielectrics in capacitors. Class 1 and class 2 ceramics were described earlier. A large group of capacitors is based on oxide thin film. Commonly used electrolytic capacitors are aluminium oxide and tantalum oxide capacitors. Although the εr of an oxide is not high, oxide film thickness can be very small, so capacitance per 1 cm3 is large. Oxide film is made by an electrochemical process. Popular oxides Al2O3 and Ta2O5 are utilized in aluminium electrolyte and tantalum electrolyte capacitor fabrication. The positive electrode is a metal (Al or Ta) and the negative electrode is a conductive electrolyte. Figure 10.42(a) depicts a segment of a wet aluminium foil electrolytic capacitor. Foil is etched to get a large active surface; the growth coefficient of the surface is above 10 and the theoretically for low voltage is 100. On the active surface, a thin layer of Al2O3 is produced electrochemically. It functions as a dielectric layer of the capacitor and its εr equals 8.4. The negative electrode is made as a conductive flux that usually is connected to the Al cover. The dc voltage range is from 6 up to 600 V. The capacitance range is from 4.7 µF to 10 mF in series E-3. In the reverse direction, the dielectric does not withstand high voltages and the maximal admitted voltage is only 10 percent of nominal voltage. During operation, the capacitors show better parameters than during storage because of the smaller value of the leakage current. A tantalum capacitor is also produced as a foil capacitor, but the dry tantalum capacitor is more popular. Fig. 10.42(b) shows a segment of that capacitor where tantalum balls (0.3 mm diameter) are sintered and function as the positive electrode. A thin film of Ta2O5 is produced by an electrochemical process on the surface of each ball. In the next step a conductive layer © 2003 by CRC Press LLC

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(a)

(+)

1

(−) 3

(b)

1 2 3 4

2 oxide film

(−) 5

(+) 5

FIGURE 10.42 Segment of electrolytic capacitor. (a) Al2O3 wet capacitor: 1 — Al foil, 2 — oxide layer, 3 — fluid (negative electrode). (b) Ta2O5 dry capacitor: 1 — tantalum balls, 2 — Ta2O5 layer, 3 — conductive layer (negative electrode), 4 — contact for negative termination.

(for example, a colloidal graphite layer) is deposited on Ta2O5 film in a chemical process. At the end, a contact for a negative electrode is made. An anode termination is welded to sintered balls and a cathode termination can be soldered to the negative electrode contact. Encapsulation is made using a tixotropic lacquer. Tantalum oxide electrolytic dry capacitors are produced for low dc voltages from 4 to 50V. The tantalum capacitor shows a smaller leakage current and higher work temperature, up to 125˚C. The aluminium capacitor can usually work nominally up to 70°C and up to 85°C maximum. Also, the tantalum capacitor exhibits better high-frequency characteristics. It is really a miniature capacitor; its υ′ index is very small (see Table 10.7). Al and Ta electrolytic capacitors are applied to do circuits but can also work at small ac voltage (ac amplitude must be smaller than 10–15% of dc nominal values). In a wet electrolytic capacitor, self-regeneration exists; that is, after a short breakdown, the capacitor can work further because the layer of oxide is regenerated around the breakdown point. Several firms manufacture bipolar electrolytic capacitors for ac voltages. Super Capacitor (with electric double layer) The super capacitor, also called the golden capacitor or golden series capacitor, has capacitances up to 10 F and its υ′ index is about 0.00001 cm3/µF. The origin of that capacitor comes from H.L.F. Helmholtz (1879), who discovered the electric double layer that exists on the interface of two different materials. The layer can store an electric charge. The charge value of the electric double layer increases as the effective contact surface and/or electric field go higher. The right choice of both materials and preparation technology can lead to a very thin (several angstroms) electric double layer for 1.2 V in one call. Cells are connected in series for higher nominal voltage values, which typically achieve 2.5 V up to 11 V for the whole super capacitor. In known practical constructions of super capacitors, small particles of activated carbon (with a large effective surface) are used in contact with diluted sulfuric acid; carbon in contact with acid yields the electric double layer. Carbon is the positive pole and acid connected with the metal case is the negative pole. The leakage current of supercap is very small, the time constant of the supercap is very high (over 1 month), and therefore it is very useful for backup purposes, such as maintaining the proper voltage level for reliable data storage of CMOS memories during host power supply failure. Supercapacitors are sometimes classified as electrolytic capacitors because of their inner wet solution, but the general principles of operation are quite different. Supercaps are manufactured by many companies, such as NEC and Panasonic, and others. Organic Capacitor This group includes paper and polymer capacitors. The paper capacitor is an obsolete construction and today is not very popular because paper drying and impregnation are rather expensive. Also, the parameters of paper capacitors are not sufficient. The family of polymer capacitors is very large and some of them were described in the section on nonlinear capacitors. © 2003 by CRC Press LLC

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Table 10.10 presents the features of various polymer capacitors. Special attention should be paid to the teflon capacitor, for instance, that the maximum operating temperature is 280°C and the power factor is ca 6 × 10–4; also, instability δ is < 0.5%/1000 h. For dc and low frequency operation, polyethylenetereftalate (mylar) foil capacitor is very popular. It withstands different fluxes and high temperatures up to 150°C. Its stability and power factor are quite good, but only for low frequencies.

Dependence on Geometry of Material Influence of Capacitor Construction on Equivalent Series Inductance (ESI) and Equivalent Series Resistance (ESR) Equivalent series inductance with capacitance C causes self-resonance at resonant frequency fo . Above frequency fo it has an inductance feature so it cannot fulfill its main function. So, reduction of ESL is a very important matter. Figure 10.43 shows the simplest rolling polymer capacitor with two terminations marked 3 and 4. During charging and discharging, current is flowing through capacitor electrodes that are marked 2 and 5. The electrodes are insulated by polymer foils marked by 6 in Fig. 10.43. Such a construction creates a roll which, in turn, adds significant ESL to the capacitor. The simplest way of decreasing ESL is to supply some additional terminations and connect them in parallel. The maximum number of contacts is shown in Fig. 10.35. Contacts are deposited with melted metal on the electrode by using a high-pressure airbrush. In that case minimal ESL occurs. In this way ESR also decreases, because the distance through which current is flowing becomes much shorter. Very small ESL occurs with the feed-through capacitor shown in Fig. 10.38. Influence of Plate Shape on Tuning Frequency in Air Variable Capacitors A variable capacitor consists of standing plates that are insulated usually from the ground and rotary plates that are connected to the ground. Variable capacitors are used for tuning an LC circuit, for example, to select the proper radio station. As we see from (10.37), resonant frequency f0 is not proportional to C. Proportionality is achieved by special shaping of the plates as a function of the rotation angle. The modified shape of plate is illustrated in Fig. 10.44. f0 =

1 b = 2π LC C

(10.37)

Equation (10.37) shows the resonant frequency of the LC circuit. Shape of the High-Voltage Capacitor The operation of a capacitor at high voltages is always accompanied by many problems, for example, how to achieve the proper distance between capacitor electrodes. Two drawings in Fig. 10.36 help us to overcome this obstacle by using either of the following: 1. A disk capacitor with a high dielectric thickness (actually, it is a bar instead of a disk); when the thickness of the dielectric increases, capacitance decreases. 2. A tubular capacitor when the thickness of the dielectric is satisfactory for high voltage, but the electrodes are far enough from each other with respect to flashover protection Chip Capacitor Surface mounted technology (SMT) requires electronic components with easily solderable contacts without wire terminations. Usually those contacts are pretinned during chip production. Figure 10.45(a) and (b) show us a tantalum electrolytic capacitor chip and a ceramic monolythic capacitor chip, respectively. The capacitance © 2003 by CRC Press LLC

Capacitor Name

© 2003 by CRC Press LLC

Smallest t δp [%]

300 300 200 50

1 1 1 2

0.5 0.5 1 5

10

2

5

5.6 12

2 2

10 5

12

2 2

5.6

Maximum Work Temperature [˚C]

Power Factor × 10–4

TCC ppm/K

±0.5 ±0.5 ±1 ±5

2–5 6 5 6–8

–100 –150 –500 –200

70 280 100 110

±0.5

6–8

–200

85

±10 ±10

50 (200 at 1 MHz) 50 (200 at 1 MHz)

— Large

— 150

10

±10

20

Large

100

10

±10

20

Large

100

Remarks For telecommunications filter Special applications

Neutral polymer

For ac pulse

Polar polymer

The Circuits and Filters Handbook, Second Edition

Polystyrene Teflon Polyethylene Polypropylene Metalized polypropylene Metalized Polyester Polyester (polyethylene tereftalate) Polycarbonate Metalized polycarbonate

Class

deltamax after 1000 h [%]

υ′ cm3/µ F

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TABLE 10.10

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Passive Circuit Elements

(a)

(b)

1

B−B 3

2

4 2 7

6 5

3

4 B

B 2 5

6

FIGURE 10.43 Simply polymer capacitor construction. (a) 1 — start part of roll, 2 — Al foil (electrode I), 3,4 — wire terminations. 5 — Al foil (electrode II), 6 — polymer dielectric foil, 7 — welding points; (b) cross section B-B.

B 5

5 B−B

2

2 1 3

3 4 4

FIGURE 10.44 Rotary capacitor construction. Shape of plates is modified in relation to the circle. 1 — shaft, 2 — moving plates, 3 — standing plates, 4 — insulator, 5 — insulating traverse.

of each of these two devices can range from 10 pF up to 10 mF and from 10 pF to 10 nF, respectively, in classes 2 and 1.

Nonideal Linear Capacitor The main source of capacitance instability of the capacitor is the operating frequency. Its influence on dielectric polarity was described in the section on linear capacitors. The change of capacitance with frequency increase in capacitors belonging to the class 1 might be also observed. Furthermore, an equivalent series resistance (ESR) decreases the effective capacitance Cef according to (10.38): Cef1 =

C 1 + ω 2r 2C 2

(10.38)

were r = ESR is calculated from the power factor (PF), which is measured at the operating frequency, and C is the capacitance at low frequencies. r=

© 2003 by CRC Press LLC

PF ωC

(10.39)

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(a)

(b) 3

W

IIb

1

1

2

1

3 4

IIa

Marking of positive pole

Marking

1

Ib

Ib

Ia Ib

Marking of positive pole

+8 +6 +4 +2 0 −2

POWER FACTOR

PERCENT CAPACITANCE CHANGE FROM 1 KHz

FIGURE 10.45 Chip capacitor. (a) Tantalum pentoxide capacitor. Positive pole is marked by a black bar and double external electrode; 1 — plastic encapsulation, 2 — external electrode for soldering, 3 — cutting in positive electrode, 4 — black bar. (b) Ceramic multilayer monolithic capacitor, 1 — ceramic layers, Ia,IIa — capacitor electrodes (plates), Ib,IIb — external electrodes.

100

1K

1M 10K 100K FREQUENCY IN HERTZ

10M

100M 150M

0.008 0.006 0.004 0.002 0

(a)

100

1K

1M 10K 100K FREQUENCY IN HERTZ

10M

100M 150M

(b)

FIGURE 10.46 Dependence of capacitance and power factor versus frequency for ceramic NPO capacitor — class 1. (a) Capacitance, (b) power factor [7].

On the other hand, an equivalent series inductance (ESL) increases the effective capacitance according to (10.40): Cef 2 =

C 1 − ω 2LC

(10.40)

where ESL = L can be measured at the self-resonant frequency [see (10.37)]. The ESR and ESL Data Cards for a given capacitor can be obtained from its manufacturer. Figure 10.46 shows the dependence of capacitance and power factor on frequency for class 1 ceramic capacitors. Figure 10.41 presents data for class 2 ceramic capacitors. In a ceramic multilayer capacitor, migration of metal particles through the dielectric is observed, which causes an increase of capacitance and sometimes breakdown. The problem can be solved by roll pressing of two wet ceramic layers into one dielectric during a production process. Self-Regeneration of Capacitor. The phenomenon of self-regeneration is exhibited in metalized dielectric capacitors as well as electrolyte capacitors. It is useful in some situations (for example, in long-life tests), but sometimes it is harmful (for example, in pulse counting equipment). To solve that problem, we should use a derated capacitor (for 25 V work voltage, 40 V nominal voltage is needed) or change the type of capacitor.

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IL/IL20

IL/ILN

10

1

1.0

1.0

0.1

0.1

0.01 T [°C] −40

0

40 (a)

80

120

VW/VN 0

0.5

1.0 (b)

FIGURE 10.47 Leakage current of tantalum electrolytic capacitor [1]. (a) Dependence of leakage current versus temperature; (b) dependence of leakage current versus working voltage; 1 — typical range of IL .

Leakage Current of Electrolytic Capacitor. The insulating resistance Ri in an electrolytic capacitor is not as high as in other capacitors. The result of law Ri is dc current called leakage current IL. For aluminium electrolytic capacitors, Siemens Matsushita Components Company in their catalog [6] propose to join IL in µA with capacitance C in µF and working voltage Vw in [V]. According empirical rule (10.41) I L ≤ 0.03CVW + 20 µA

(10.41)

I L ≤ 0.006CVW + 4 µA

(10.42)

for normal types and

for special long-life capacitors, where Vw ≤ VN . Tantalum electrolytic capacitors show smaller leakage currents and at a temperature 20°C their value is 0.5 up to 20 µA. That value also depends on C, Vw, and temperature. Dependence IL on ambient temperature T is shown in Fig. 10.47(a), and influence of working voltage value Vw is shown in Fig. 10.47(b). Those data are taken from the 1990 catalogue of the AVX Corporation Ltd. (Great Britain). It is necessary to know that after long-time storage the leakage current is going up. To prevent this, one should switch on the testing device containing the capacitors several hours before using. Noise in Capacitor. Foil capacitors can generate noise when contact between termination and electrode plate is not sufficiently fixed. In Fig. 10.43, the welding points of contact are introduced (marked 7) to improve the quality of a contact. Some producers do not use welding because at nominal voltages the noise generated by contact is negligible. You should pay attention to the fact that for very low signals poor contacts affect noise in a significant way. Welding removes that effect. Ionization Threshold. In a power capacitor, an ionization of the dielectric is possible, Fig. 10.48 shows the effect of this process. Although breakdown does not occur, the capacitor life shortens when operating voltage approaches maximum. Threshold is a minimal value VT of voltage at which ionization starts. This causes heterogeneity of the dielectric, for example, polypropylene and air between plates. Flat rolling of the dielectric layer is strongly suggested for use in a power capacitor, as well as vacuum impregnation of the capacitor. Insulating Resistance Ri . When a capacitor is used as a component of an RC time constant, insulation resistance should be taken into consideration. In that case, foil polymers (particularly polystyrene or teflon capacitors, where Ri is greater 100 GΩ) are preferred. Also, protection against dirt and humidity by hermetization improves Ri .

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V

Vt

t −Vt

FIGURE 10.48 Ionization threshold in a 50 Hz capacitor. Vt — threshold voltage on which ionization can start.

References [1] [2] [3] [4] [5] [6]

AVX Corporation Ltd., AVX Tantalum Capacitors Catalogue, Great Britain, 1990. R. Dorf, Ed. The Electrical Engineering Handbook, Boca Raton, FL: CRC Press, 1993. L. Badian, Handbuch der Electronik, Vol. 3, Munich: Franzis-Verlag, 1979. IEC Standard Publ. 384, pp. 1–17, 1988. “Capacitors,” Philips Components Catalogue, 1989, Eindhoven. “Aluminium electrolytic capacitors, ceramic capacitors, tantalum capacitors,” Siemens Matsushita Components Catalogue, Munich, 1993. [7] Sprague Electric Co., “Monolithic ceramic chip capacitors,” Sprague Eng. Bull, Brussels. [8] Taiyo Yuden Co. Ltd., Tubular Ceramic Capacitors Catalogue, Tokyo, 1988.

10.3 Inductor Tomasz W. Postupolski Basics An inductor is a device consisting of one or more associate windings, with or without a magnetic core, for introducing inductance into an electric circuit [1]. The origin of the word is from Latin: inducere–excite, induce, incite. Other appellations in use include inductance coil and coil, which are synonyms, and inductance, winding, bobbin, self, and self-inductance, which are jargon, as well as reactor and choke. Reactor and choke are inductors but not every inductor is a reactor or choke. The alphabetical symbol of inductor is L. Units of inductance include 1 henry = 1 H = 1 Vs/A and its submultiples nH (10–9), µH (10–6), and mH(10–3). Inductor graphical symbols: generally inductor or ideal inductor; inductor with magnetic core, cored inductor; XL inductive reactance XL = ωL; cored inductor with continuously changed inductance; cored inductor with adjuster; cored inductorcore with air gap; cored inductor, core of bonded magnetic powder.

Basic Relationships and Influencing Factors The main electrical attribute of the inductor is the inductance L. The inductance is the property of the electric circuit, whereby an electromotive force is induced in that circuit by a change of current in the circuit [1]. The electromotive force (voltage) e induced in the winding of the inductor is given by Faraday’s law, which can be written in various equivalent forms: © 2003 by CRC Press LLC

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n

µ

i

l L

e

A

Φ, B, H

e = −n

FIGURE 10.49 Inductor of a toroidal shape.

dΦ d dL   di = – ( Li ) = −  L + i   dt dt dt dt 

(10.43)

where nΦ = total magnetic flux linked with the current i flowing through all the n turns forming the winding of inductor having an inductance L. Equation (10.43) shows that the circuit “senses” the inductance only when the current in the circuit is changing and/or the inductance itself is changing. Generally, the inductance L can depend on the magnitude of current i and inversely a change in the magnitude of L can cause a change in amplitude of i, so e is an implicit function e[i(t), L(i, t), t].The well-known expression e = –Ldi/dt is fulfilled only if L is a constant independent of current, i, and time t (this restriction is often forgotten). In terms of the electromagnetic field theory, the inductance L is given by L=

Φ =n i

∫ BdA ∫ Hdl A

(10.44)

l

B = the normal component of the magnetic induction (flux density) through the area A and H = the magnetic field strength along its path l. For more about various forms of the electromagnetic field equations see courses on the theory of electromagnetic field, for example, [2]. In case of a radially thin toroid (that is, in which A/l → 0) and µ = const, the magnetic induction B, and field strength H, can be assumed as uniform, that is, Φ = BA; B = µ0µH; H = ni/l, the inductance L for a shape shown in Fig. 10.49 is L = µ 0µn 2 A l

(10.45)

where µ0 = 4π10–7 [H/m] is the magnetic constant and µ = magnetic permeability of the medium filling up the shape of the toroid. Equation (10.45) can be expressed in different equivalent forms; their use is optional.

© 2003 by CRC Press LLC

L = ALn 2

AL = µ 0µ A l

AL = L n 2

(10.46a)

L = µAL 0n2

AL 0 = µA l

AL 0 = AL µ

(10.46b)

L = µ 0Gmn2

Gm = µA l

Gm = µGm0

(10.46c)

L = µ 0n2 Rm

Rm = l µA

Rm = 1 Gm

(10.46d)

L = µ 0µGm0n2

Gm0 = A l

Gm0 = Gm µ

(10.46e)

L = µ 0µn2 Rm0

Rm0 = l A

Rm0 = 1 Gm0

(10.46f )

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where AL = inductance factor of inductor, AL0 = inductance factor of the winding or core shape (at µ = 1), Gm and Rm = core permeance and reluctance, respectively, Gm0 and Rm0 = permeance and reluctance of core shape (at µ = 1); inductance L is in [H] if l is in [m] and A in [m2]. If µ, B, and H cannot be assumed to be uniform, (10.45) and (10.46) take more complicated forms issuing from (10.44). The following fundamental observations can be inferred from (10.43) to (10.45): 1. The inductance L of the inductor depends on three factors: • square of number of turns n2 of the winding; • geometrical configuration of the magnetic flux Φ produced by the current i; this configuration is represented by the permeance or reluctance of the shape Gm0 or Rm0 , containing the magnetic flux; • magnetic properties of the medium or media filling up the shape associated with the carrying current winding, producing a magnetic flux Φ; these properties are represented by the magnetic permeability µ. Note: Magnetic permeability, depending on the approach, can be considered as a scalar (number), complex quantity, or a tensor. 2. The voltage induced across the inductor of inductance L depends on the following: • rate of change of the current flowing in the inductor winding di/dt; • changes in time of the inductance of inductor dL/dt; these changes result from the influence of external factors on inductance L, because dL = dt =

∑ ∂∂ξL

v

v

∑ v

∂ξv ∂t

 ∂L ∂µ ∂ξv ∂L ∂A ∂ξv ∂L ∂l ∂ξv  + +   ∂l ∂ξv ∂t   ∂µ ∂ξv ∂t ∂A ∂ξv ∂t

(10.47)

ν = 1,2,3, …, ξ = external stressing factors such as time, temperature, mechanical stresses, static and time-varying voltage or magnetic induction, current or magnetic field strength, frequency, moisture, radiation (nuclear, cosmic), and so on. The term dL/dt, (10.47), often forgotten in considerations, is however, of importance because it is responsible for any instability or variability introduced into an electric circuit by the inductors. Examples of various dL/dt contributions are listed in Table 10.11. Inductor: Qualifiers and Attributes Different qualifiers are, in practice, applied to inductors, depending on approach and related attributes. The most frequently used are listed in Table 10.12. These qualifiers are used separately or in combination, e.g., air inductor or linear cored inductor. Basic Functions of the Inductor The inductor has to perform four basic functions: • Impede (oppose) any change in the existing current; as the change is more rapid the opposition is stronger • Lag (to shift) the current in respect to induced voltage up to 90o for a sine wave • Differentiate the current waveform • Store the magnetic energy; this when in combination with electrical energy stored in capacitor, results in electrical resonance (LC — resonance) The more the real inductor approaches the ideal inductor, the higher the degree in performing these functions. © 2003 by CRC Press LLC

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313

Passive Circuit Elements TABLE 10.11 Exemplification of Various Stressing Factors ξ Causing Changes in Inductance L Influencing

Stressing Factor ξ Temperature Mechanical tensile, contracting or torsion stress

Magnetic induction B or magnetic field strength H (changes of static, time-varying or combined magnitude) Frequency

Humidity, moisture, aggressive agents (salts, acids, etc.)

Permeability µ, dµ/dξ, for example: Temperature changes of permeability Reversible changes of permeability under mechanical stresses, piezomagnetic effects, mechanomagnetic after-effects (relaxations) Strong and, generally, nonlinear dependence of µ on B and H; disturbance of the magnetic state of core material Strong dependence of µ on frequency: eddy current effects (magnetic skin and proximity effects), magnetic resonances (wall resonance, dimensional resonance, spin resonance), relaxation effects Corrosion effects in metallic cores, therefore structural changes of magnetic material; changes of dielectric properties in ferrites

Irradiation

Structural changes in magnetic material

Time

Changes of µ: reversible effects (dissaccommodation and accommodation), irreversible effects (so-called aging), thermal fluctuation effects in nonneutral states

Physical Dimensions A and l of Winding and/or Core; dA/dξ and dl/dξ, for example: Thermal changes of dimensions Changes of dimensions under mechanical stresses; mechanical relaxations of dimensions of core or winding Ponderometric effects in winding at, e.g., high current intensities or pulses; mechanical relaxation of winding or coil formers Skin and proximity effects in wires cause change of current density distribution in conductor, thus, the change of effective dimensions of coil Various agents’ effects as changes of dimensions and electrical and dielectric properties of coil formers, winding and interwinding insulation layers, substrates, etc. Structural changes in materials of coils, conductors, insulation, dielectric properties of coil formers, substrates, etc. For example, aging and rheological effects affecting materials of coil formers, insulation; diffusion effects between metallic conductor deposited e.g., on ceramic substrate

Parameters Characterizing the Inductor Primary Parameters: • Inductance L (for all excitation levels) • Power loss at low and middle excitation levels expressed facultatively in terms of resistance R = power loss/(square or rms value of current) tangent of loss angle δ, tgδ =R/2πfL quality factor Q = 2πfL/R = 1/tgδ • Power loss for high excitation levels, expressed directly in watts Secondary Parameters (Selected): • dc winding resistance • Self-capacitance • Self-resonance frequency • Temperature coefficient or factor of inductance • Time instability • Hysteresis loss • Pulse inductance • Adjustment range • Harmonic distortion • Magnetic radiation © 2003 by CRC Press LLC

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TABLE 10.12 Inductor Qualifiers and Attributes Inductor Qualifier Ideal, perfect

Nonideal

Linear

Nonlinear

Real

Air Cored Lumped or discrete Distributed

• • • • • •

Inductor: Attribute or Quality Linear inductor having only a “pure” inductance, i.e., no power loss is related to the flow of timevarying current through the inductor winding. In the ideal inductor, the current of sine wave lags the induced voltage by angle ϕ = 90˚ (π/2 rad). The concept of the ideal inductor is used only in idealized or simplified circuit analysis. Usually, a linear inductor in which the power loss in the winding and core is taken into account. The current of sine wave lags the induced voltage by angle 0˚ ≤ ϕ < 90˚ (90˚ for ideal, power lossfree inductor; 0˚ for pure resistor). The concept of nonideal inductor is used as a first order approximation of a real inductor. Inductor, ideal or nonideal, for which the induced voltage drop across it is proportional to the flowing time-varying current in its steady state. Linear inductor can be described or be used to describe the circuit in terms of transfer function. An air inductor is an example of linear inductor. Inductor for which the induced voltage drop is not proportional to the time-varying current flowing by it. As a rule, cored inductors (specifically if a core forms a closed magnetic circuit) are nonlinear. This is a consequence of the strong nonlinear dependence of magnetic induction B, proportional to voltage u = dL/dt, on magnetic field strength H, proportional to current i. Inductor with electrically behavioral aspects and characteristics that are all taken into account, e.g., magnetic power loss, magnetic flux leakage, self-winding and interwinding capacitances and related dielectric power loss, radiation power loss, parasitic couplings, and so on, and dependences of these factors on frequency, induction, temperature, time, etc. Inductor not containing magnetic materials as constituents or in its magnetically perceptible vicinity Inductor in which a magnetic material in the form of a core serves intentionally as a path, complete or partial, for guidance of magnetic flux generated by current flowing through inductor winding Inductor assumed to be concentrated at a single point Inductor with inductance and other properties that are distributed over a physical distance(s) which is(are) comparable to a wavelength

Influence of the static magnetic field Inductance rise factor Maximum winding temperature Temperature rise Immunity from mechanical stresses and environmental exposures Acoustic noise

To determine these parameters the following should be specified: frequency, excitation level (voltage or current), temperature, parameters of measuring coil (winding), type of magnetic conditioning to be used, and other details of measuring procedure, as well as conditions needed to ensure the required accuracy and repeatibility of measurement. The relevant measuring methods are described, e.g., [3], [4] and [5]. Circuit Representation of Inductor Circuit representation of the ideal inductor is that as shown by the first inductor graphical symbol. For a nonideal linear inductor, a series or parallel representation is used, Fig. 10.50. The transformation of a nonideal inductor shown in Fig. 10.50 is a purely formal operation serving only for the circuit analysis. Transformation results calculated for one specified frequency and specific operating conditions (e.g., B, temperature) can be extended over other frequencies and conditions only when L and R appear to be independent of these factors: L = const and R = const. Series and Parallel Connections of Inductors. When individual inductors are connected in series (with no mutual inductive couplings), the total inductance Lt = Lts will be a sum of individual inductances Li : Lts = ∑i Li ; similarly the equivalent loss resistances: Rts = ∑i Ri .

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(a) series representation is

Ls

(b) parallel representation

Rs

Lp

ip

Rp

us

up

Zö = jwLs + Rs

Zö = 1/Yö

tgd = Rs / wLs

tgd |s = tgd |p

Yö =

1

+

1

jw L p R p tgd = wLp /Rp

Ls = Lp/(1 + tg2 d) Rs = Rp/(1 + 1/tg2 d)

Lp = Ls (1 + tg2 d) Rp = Rs(1 + 1/tg2 d)

For ideal inductor: d = 0° For ideal resistor: d = 90°

tg d = 0; tg d = ¥;

Ls = L p; Ls = LP = 0;

Rs = 0; Rs = Rp

Rp = ¥ .

FIGURE 10.50 Equivalent circuit representation of the inductor and the respective expressions. Note: When subscript s is omitted, symbols L and R always refer to the series representation.

When individual inductors are connected in parallel, the total inductance Lt = Ltp and resistance Rtp will be Ltp = 1/ ∑i 1/Li and Rtp = 1/ ∑i 1/Ri , respectively. Thus, the series connection of inductors always increases a resultant inductance, parallel connection — decreases. Note: These connections rules (laws) apply only for sine waveforms in the steady state and these rules are applicable neither to the nonlinear inductors nor to transient states.

Air Inductor This type of inductor is assumed to be linear. This means that at stressing factors that are fixed, the inductance L and resistance R are characteristic constants, independent of the flowing current or applied voltage. Selected formulas for the inductance of some air inductors are given below. In Table 10.13 corresponding draftings are depicted. All dimensions of coils shown in Table 10.13 are in [cm]; n = number of turns. For more formulas for calculation of the inductance of air inductors see, e.g., [14] and [15]. • Single-layer cylindrical coil with a circular conductor, Table 10.13(a): L0 = KDn2 ⋅10

−9

[H]

(10.48a)

where K = coefficient whose values are listed in Appendix 1. • Single-layer rectangular coil with a circular conductor, Table 10.13(b): L0 = pn2 (G + H ) ⋅10

−9

[H]

(10.48b)

where G = fg(S1 /S2 ; l/S2) and H = fh(d/λ,n) = tabulated coefficients [14], [15]. • Single-layer toroidal coil, Table 10.13(c)

(

)

L0 = 2πn2 D − D2 − D12 ⋅10

−9

[mH]

(10.48c)

• Single-layer ring coil, Table 10.13(d): L0 = 2hn2 ln( Dz Dw ) ⋅10 © 2003 by CRC Press LLC

−9

[H]

(10.48d)

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TABLE 10.13 Inductance L0 of Various Air Inductors Dimensionally Similar but Having the Same Number of Turns When Coil Dimensions Are:

Winding (Coil) Dimensions

Inductance L0 for n=100 Turns Is:

l (a)

D1 = 2 cm l = 10 cm

19 µH

S1 = 1.5 cm S2 = 2.5 cm λ = 0.05 cm l = 10 cm d = 0.05 cm G (0.6;4) = 0.4 H (1;100) = 0

32 µH

D1 = 1 cm D2 = 3 cm

10.3 µH

D1 = 2 cm D2 = 3 cm

41 µH

D1 = 2 cm D2 = 4 cm h = 1 cm

13.9 µH

D1 = 1 cm D2 = 5 cm h = 2 cm

64.4 µH

D = 2 cm h = 0.5 cm l = 4 cm

74 µH

D = 2 cm h = 0.5 cm l = 0.2 cm

245 µH

D

λ

S1

d

(b)

S2 l

(c)

D1 D2

h

(d) D1 D2 l (e)

h D

l h (f) D

• Multilayer long cylindrical coil, Table 10.13(e):

[

]

L0 = Dn2 K − 2πh(0.693 + γ ) l ⋅10

−9

[H]

(10.48e)

K = coefficient as for the single-layer cylindrical coil; γ = coefficient whose values are listed in Appendix 2. • Multilayer short cylindrical coil, Table 10.13(f): L0 ≅

© 2003 by CRC Press LLC

25πD2n2 −9 ⋅10 [H] 3D + 9l + 10h

(10.48f )

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TABLE 10.14 Dimensional Proportions of Coil Providing Its Maximum Time Constant L/R Case Winding

(a) + (b)

Cylindrical, single layer

(c)

D ≈ 3l

D = (1.3–2)l

D = 5h + 3l

D = (1.3–1.6)l

Cylindrical

Long

Multilayer

Short

Single layer

Toroidal

D2 ≈ 3D1

—

Ring

D2 ≈ 1.6D1

—

D = (4–8)l D = (5–7)h

Design Guidance. As can be observed, L = ψDn 2, where ψ is a function of two factors: l/D and h/d; and the inductance of air inductor increase when: • • • •

Outer diameter of winding increases Ratio of outer to inner winding diameter decreases Width of winding decreases Diameter of wire decreases

This can also be inferred from the last column of Table 10.13 comparing the values of Lo for dimensionally similar air inductors. Inductance L0 can be readily calculated for a specified shape, dimensions, and number of turns of winding. However, this is not a design approach, because the design problem to be solved is inverse: to determine for a given value of L0 the dimensions, shape, and number of turns of winding. However, such calculations are impossible to perform. This is a consequence of the given geometry of winding of n turns, which results in one and only one geometry of the magnetic flux Φ, therefore, in only one value of the inductance L0 . Inversely, to a given value of L0 an infinite number of winding geometries may be attributed at any n value. Thus, the theoretical problem is to obtain the dimensions of the winding in combination with the suitable number of turns n from the specified value of L0 is mathematically insolvable. Therefore, the solutions are determined by experimental or iterative numerical methods. Quality Factor of Air Inductors. Usually it is required that the inductor would have the maximum Q-factor or time constant L/R. For the following cases in Table 10.14: (a) fixed copper (wire) volume; (b) fixed length of wire; (c) fixed coil volume, the L/R reaches maximum at following proportions of the coil winding. Quality factor of air inductor extends from several units to several hundred and depends on • • • • •

shape and dimensional proportions of winding (Table 10.14), wire pitch and the wire arrangement, operating frequency, coil self capacitance, material properties of coil former or substrate, wire insulation, proximity of conducting and/or magnetic parts.

Typical Frequency Ranges of Air Inductors When in Use In resonant circuits: • cylindrical multilayer 50–1000 kHz • cylindrical single layer 1 MHz–2 GHz © 2003 by CRC Press LLC

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As chokes: • multilayer (multisectional) 10–1000 kHz • single-layer 500 kHz–800 MHz Conductors (wires) used: • • • • • • •

solid insulated: dc–200 MHz solid uninsulated: 100 MHz–1 GHz stranded (litz wire): 50 kHz–10 MHz tubular: 3 MHz–3 GHz Cu-coated metal: 30 MHz–3 GHz Sn- or Ag-coated metal: 0.2–3 GHz Sn, Ag, Au conducting path: 0.2–3 GHz

Advantages of Air Inductors • High stability of properties versus temperature, time, and magnetic excitation levels (when compared with cored inductors) • Very low dependence of inductance on frequency (related mainly to changes of effective dimensions of winding due to skin and proximity effects in wires), therefore, a practically linear dependence of XL = ωL on frequency • Insaturable dependence of B on i (as opposed to cored inductors) allows the air inductors to produce very high pulses of induction B. Disadvantages of Air Inductors • Practical inability to obtain dimensionally small inductors of high inductance L, therefore, inherent inability to miniaturization • Air inductor acts both as an emitting and receiving antenna, therefore, it is (a) a source of unwanted electromagnetic radiation to surrounding circuitry and environment; (b) a receiver of electromagnetic signals introducing them into circuit as disturbance (usually) — electromagnetic interference (EMI). These strong coupling features make the air inductor a highly incompatible component in electronic circuitry, especially miniaturized, and in electronic and electrical environments. • Air inductors are made, as a rule, as inductors of fixed value of inductance L. If a change of L is required, connections to some wires (taps) positioned between winding extremities, or a sliding contact to wires for single-layer windings enable the inductance to be changed.

Cored Inductor Reason for Using the Magnetic Material in Inductors. If a winding of inductance L0 produces in vacuum (in air) a magnetic flux Φ0 distributed over some volume and that this volume is completely filled up with a magnetic material of permeability µ, then the inductance L of the so combined winding with the magnetic material is L = µL0. Cored Inductor and its Parameters in Electric Circuit. In Table 10.15 the parameters of the inductor are compared for cases when it is immersed in air (µ = 1) and in magnetic material of permeability µ. It is supposed that the magnetic flux Φ0 produced by the inductor winding runs completely through the magnetic material (the case of the complete coupling of winding with the magnetic material). In case (a), the voltage drop across inductor, magnetic induction, and flux remain unchanged while the current through inductor and magnetic field decreases µ times; in case (b), the current and magnetic field remain unchanged, whereas the voltage drop, magnetic induction, and flux increases µ times. The only parameter that increases µ times in all the cases, limit and intermediate ones, 0 < Ri < ∞, is the inductance L = µL0. The main reason for applying the magnetic material as a core in inductor is to increase its inductance. © 2003 by CRC Press LLC

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TABLE 10.15 Inductor-Related Parameters: Voltage drop u, Current i, Induction B, Magnetic Flux Φ, Field Strength H, Inductance L at the Absence and Presence of Magnetic Material Fully Coupled with Inductor Winding Is Shown for Two Limit Cases: (a) Inductor Operates in Circuit of Constant emf (Ri = 0) and (b) in Circuit of Constant Current (Ri = ∞). Magnetic Material of Permeability µ Absent

Present, Fully Coupled with Winding Case (b): Constant Current Source (Ri = ∞)

Case (a): Constant emf Source (Ri = 0)

Parameter

Any Source

u= i= B= Φ= H= L =a

u0 i0 B0 Φ0 H0 L0

u0 i0 /µ B0 Φ0 H0 /µ µL0

µu0 i0 µB0 µΦ0 H0 µL0

L = Φ/i =

Φ0 /i0 = L0

Φ0 /(i0 /µ) = µL0

µ Φ0 /i0 = µL0

a

i = i0

i

source

Ri

source

u = u0 L0

u Ri

L = µL0

i i

(a)

(b)

FIGURE 10.51 Examples of (a) closed magnetic circuits; (b) open magnetic circuit.

Inductor, Magnetic Core, Closed and Open Magnetic Circuit. If the magnetic flux Φ generated by a winding runs for the most of its part through the core being in the possibly strongest coupling with that winding, it is said that this core forms a closed or nearly closed magnetic circuit. If at the possibly strongest coupling of a winding with a core, the flux Φ runs for its nonnegligible part also through the outside of the core, it is said that the core forms an open magnetic circuit. The ring core and EE-core illustrate the closed magnetic circuits [Fig. 10.51(a)], whereas the rod core illustrates the open magnetic circuit [Fig. 10.51 (b)]. Closed Magnetic Circuit Equivalent Dimensions and Parameters. The permeance Gm of a toroidal core having a very small radial thickness, magnetic path length l, a uniform cross-section area A, and permeability µ, is given by (10.46c). If the shape of a core differs from the above radially thin toroid, the calculation of permeance becomes very complex, including the problem formulation and mathematics. To overcome these difficulties, a simplified standard procedure is recommended [3]: a core having the shape different from radially thin toroid, nonuniform cross-sectional are along magnetic path and often, nonuniform permeability, is replaced by a hypothetic equivalent toroid or ring having the same permeance as the nonuniform core, Fig. 10.52. The parameters of equivalent toroid: the equivalent magnetic path length le , equivalent area Ae , equivalent volume Ve , and equivalent permeability µe are calculated from the following formulas: © 2003 by CRC Press LLC

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lv, Av

l1, A1

l2, A2 le l3 A3

µe

lv−1, Av−1 li+1, Ai+1

Ae

Ve

li, Ai

FIGURE 10.52 Nonuniform core and its equivalent toroid or ring having the same permeance.

le = C12 C 2 ;

Ae = C1 C 2 ;

Ve = le Ae = C13 C 22

(10.49)

and equivalent magnetic parameters: v

µ e = C1

∑µ A ; li i

i =1

Be =

i

u C2 ⋅ ; ωn C1

(10.50)

u C12 ⋅ Φe = ωn C 22

C H e = ni 22 ; C1 The core coefficients C1 and C2 are calculated as v

C1 =

∑ i =1

li and C 2 = Ai

n

∑A i =1

li

(10.51)

2 i

Therefore, the permeances Gm and Gm0 and reluctances Rm and Rm0 are Gm = µ C1 ;

Gm0 = 1 C1 ;

Rm = C1 µ ;

Rm0 = C1

(10.52)

Inductance L is L = ALn 2 = µ e AL 0n 2 = µ 0Gmn 2 = µ 0µ eGm0n 2 = µ 0µ en 2 C1

(10.53)

The core coefficients C1, C2 , as well as equivalent dimensions le , Ae , and Ve for standardized cores are specified in relevant IEC standards and in core manufacturers’ catalogs. The previously described procedure is a standard averaging procedure (line and surface integrals are replaced by summation) of internationally accepted applicability. This procedure is commonly used in engineering, design, and measuring practice. Air Gap: Reason for Introduction. An intentional air gap is introduced into a magnetic circuit of inductors to improve its performance, namely to: • to decrease the magnetic material nonlinearity and/or lessen the effect of static magnetic field (bias field) on inductance, • to lessen the magnetic power loss, • to lessen excessive instabilities of the core magnetic material (e.g., thermal), • to make possible a smooth adjustment of inductance to a very precise value by a special adjusting device or a specially shaped air gap. © 2003 by CRC Press LLC

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Passive Circuit Elements

(a)

(b) le

le + lg ≅ le

le lg lg

µe

µeg

FIGURE 10.53 Ring cores (b) equivalent to the EE gapped core (a).

A closed magnetic circuit (in the form of EE core, made of a material of magnetic permeability in which an air-gap of length lg , is shown in Fig. 10.53. A succession of equivalent circuits and related permeabilities µe and µeg is also shown there. The length of intentional air-gap lg is usually small compared with magnetic path length l. A ratio lg /l usually does not exceed a fraction of a percent. Effect of an Air Gap on Core Permeability. The inductance of an inductor having a core with air-gap (at complete coupling between winding and core) is given by L=

µ 0µ e n 2 l   C1 1 + (µ e − 1) g  le  

=

µ 0µ eg n 2 C1

(10.54)

where lg   µ eg = µ e 1 + (µ e − 1)  le  

–1

(10.55)

µeg = equivalent permeability of the core with air-gap. The dependence (10.55) is shown in Fig. 10.54. Equation (10.55) and Fig. 10.52 ignore a bulging of the magnetic flux traversing the air gap, Fig. 10.55. Roughly, the bulging is greater as the term (µe – 1)lg /le = p is larger. The bulging, expressed as an apparent increase of the air-gap area A′g /Ae = κg , becomes perceptible at p > 1. The ratio κg , known as the bulging factor, can attain an amount of 2 for p = 30–60. A change in flux distribution within the core, resulting from the occurrence of a large reluctance of the air gap in the magnetic circuit, is also ignored in (10.55). In effect, the value of inductance L for larger air gaps is usually higher than that resulting from (10.54). µg µ = 105

4 104 10

103

103

102 102

3×102 30 10

101 1 10−5

10−4

© 2003 by CRC Press LLC

10−3

10−2

10−1 lg /l

FIGURE 10.54 Equivalent permeability of the core with air-gap vs. lg /l.

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µ=1

A′e

Ae = Ag µ

FIGURE 10.55 Bulging of the magnetic flux traversing the air-gap.

As the air gap increases, the inductance L becomes less and less dependent on any variation of the magnitude of permeability µe. This effect is known as the linearization of cored inductor by the air-gap. The air-gap effect can be summarized as follows. The cored inductor winding perceives not the core with material permeability µ, but a core with reduced permeability µg lower than µ (or µeg when dealing with µe). Reduction of permeability of gapped core follows (10.55) depicted in Fig. 10.54. The higher the permeability, the greater the reduction of µ, e.g., the air-gap of the same (relative) length lg /l = 0.01 reduces material permeability µ = 10000 by a factor of 100 and that of µ = 10 only by a factor of about 1.1. The use of high permeability materials as cores with larger air gaps is not effective. Inductor with Incomplete Coupling. In real cases, the magnetic material forming the core of the inductor does not occupy the whole space where the magnetic flux Φ0, emanating from the winding, is distributed. The following simplified quantitative approach is in use. The flux Φ0 is a sum of a leakage flux Φl , which runs completely outside the core and a hypothetical flux Φh, which runs completely inside the hypothetical equivalent toroid of permeability µe (or µeg ): Φ0 = Φh + Φl . These three fluxes are related with three respective inductances: L0 = inductance of winding without core, Lh = inductance of the shape of the hypothetical equivalent toroid, and Ll = leakage inductance whose flux Φl does not penetrate into the core: L0 = Lh + Ll

(10.56)

Therefore, the inductance of the cored inductor with leakage is L = µ e Lh + Ll = (µ e − 1)Lh + L0

(10.57)

This formula is very convenient to determine the equivalent permeability from an actual measurement. Because Lh = µ0n2/C1, L and L0 are taken from measurement, the equivalent permeability µe (or µeg for the gapped core) can be determined: µe =

L − L0 A − AL 0 C + 1 or µ e = L C1 + 1 µ 0n 2 1 µ0

(10.58)

For phenomenal considerations a so-called winding coupling coefficient Lh /L0 = kw introduced. Then,

[

]

L = L0 (µ e − 1)kw + 1

(10.59)

Apparent Permeability. A commonly used parameter quickly characterizing the cored inductor is the apparent permeability µapp : µ app = L L0 = (µ e − 1)kw + 1

(10.60)

Equation (10.60) demonstrates whether the winding is completely coupled with the core; then kw = 1, µapp = µe ; if kw = 0, µapp = 1: the inductor is coreless; for 0 < kw < 1 always µapp < µe as in most of the real cases. The coupling coefficient is readily calculated from the formula: © 2003 by CRC Press LLC

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(

) (µ − 1)

kw = µ app − 1

e

(10.61)

µapp shows directly how many times the presence of the core, being in a given coupling with the winding, increases its inductance L0. Low winding coupling strongly lowers the effect of high permeability on the inductance of cored inductor. The high permeability materials are effective only for windings strongly coupled with the core. Such are monolayer windings of the thinnest possible wire, tightly fitting the core along its whole length, with no spacing between neighboring turns. This is in distinct opposition to other practical requirements, such as current load, low self-capacitance, interwire insulation and electrical breakdown, and ease of manufacturing. Leakage Coefficient. Also for the phenomenal considerations, the inductor leakage coefficient σ = Ll /L is used. It shows what part of the total inductance L is not related with the core and its properties. The leakage coefficient is calculated as

(

)

σ = µ e − µ app µ app (µ e − 1) or σ = (1 − kw ) µ app

(10.62)

If kw = 1 or equivalently µe = µapp , σ = 0, the inductor is leakage-free; if k = 0, then µapp = 1 and σ = 1, which results in L = L0 = Ll — the leakage inductance is the inductance L0 of the coreless winding. Summarizing: • The coupling coefficient kw shows the part of the winding flux that is instrumental in carrying the core properties into the inductor properties. • The leakage coefficient σ shows what part of total inductor properties has no relation with the core properties. • The core, when not completely coupled with the winding, increases its inductance by amount of only µapp. • The apparent permeability µapp of the real cored inductor is always lower than the core permeability µ, µe, or µeg. Joint Effect of the Air Gap and Coupling on the Cored Inductor Inductance. Combining the effect of air-gap, (10.55), and that of coupling, (10.59), the formula for the inductance of cored inductor is L=

 µ e L0kw µ n2  −  L0 − 0  1 + (µ e − 1) l g κ g le  C1 

(10.63)

In this formula, two terms are to be distinguished: the first term, being roughly proportional to µe, is generally of nonlinear character and carries in itself all magnetic material properties including its instabilities. The second term, between parentheses, being effectively an air coreless inductance, is of purely linear character. Magnetic material properties “enter” inductor properties only by the first term. As the air-gap and leakage become larger, the share of the first term decreases for the benefit of the second term: the inductor linearizes or stabilizes. For the sake of example: for an inductor with an EE42/20 ferrite core of material permeability µ ≅ 1800, the ratio of the first to the second term for ungapped core is about 450. If an air-gap of length lg = 1 mm is cut in that core, this ratio drops to about 30. Thus, the linearization here reaches an amount of about 15. This effect is called the linearization or stabilization by the air-gap and/or by the leakage (or coupling). A cored inductor with coupling kw = 1 and with no air-gap behaves as a pure magnetic material itself, whereas for kw = 0 it becomes a coreless air inductor having the inductance L0. Open Magnetic Circuit The most commonly used open magnetic circuit is a cylindrical rod core. The inductor is built by axially placing the rod core inside a cylindrical coil as it is illustrated in Fig. 10.56. © 2003 by CRC Press LLC

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lc

dc

dr

lr

FIGURE 10.56 Open magnetic circuit having a rod core. µ = 400 100 70 40 20

µr 16 14 12 10 8 6 4 2

m, q (a)

(b)

1.0 m 0.8 q

0.6

10

0.4 1

2

3

4

lr /dr

0.0

0.2

0.4

0.6

0.8

1.0

lc /lr

1

1.4

1.8

2.2

2.6

3.0

dc /dr

FIGURE 10.57 (a) Equivalent permeability of the rod µr vs. ratio lr /dr for different material permeabilities µ; (b) experimental coefficients m vs. lc /lr and q vs. dc /dr .

Inductors of this type are built as variable and fixed inductance inductors. To vary the inductance the rod core is moved axially inside the coil. The central axial position of the rod in relation to the coil corresponds to the maximum inductance. In fixed inductance inductors the movement between the core and coil is not provided. If the rod core is enclosed by a centrally placed winding, as shown in Fig. 10.56, the inductance of such an inductor can be calculated from the following empirical formula:

[

]

L = L0 (µ r mq − 1)kwr + 1 = L0µ app

(10.64)

where L0 = the inductance of the winding without core; µr = equivalent (effective) magnetic permeability of the rod, of similar significance as µe for the closed magnetic circuit; m and q = experimentally determined coefficients; kwr = coupling coefficient. The permeability of the rod µr is a complicated function of the material permeability µ and of the ratio of the rod length to the rod diameter lr /dr [13]. This function is shown in Fig. 10.57(a). The experimental coefficients m = f(lc /lr) and q = f (dc /dr) are given in Fig 10.57(b). The coupling coefficient kwr is kwr = ALh AL 0 [nH] [nH]

(10.65)

where ALh = Kdr , K is the coefficient listed in Appendix 1; AL0 = L0 /n2, and L0 = winding inductance. The inaccuracy of the above calculations of L and µapp does not exceed several percent. As can be inferred from Fig. 10.57(b), the maximum inductance L is obtained for mq = 1, i.e., for lc ≅ 0.83lr and dc = dr: i.e., for the winding of width nearly equal to the rod length and closely fitting the rod diameter. As the winding diameter dc is larger and winding width is narrower, the core contributes less to the inductor inductance L. It is often of great importance to estimate the material permeability of the rod core. The calculation inverse to that of (10.64) can allow it: first one calculates µr = (µapp – 1 + kwr)/mqkwr , next for the © 2003 by CRC Press LLC

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so-determined µr and given lr /dr , the material permeability µ can be found from Fig. 10.57(a). This method, however, can practically distinguish µ < 400 only and needs to gather very accurate input data and may provide with only approximate µ-values providing that µ < 400. Emerging Inductor-Related Advances • Ongoing adaption of inductor core’s shapes and windings to: • surface mount technologies (SMT), • denser packing (per volume unit) of more and more miniaturized components, • the automatic assembling. Example: low-profile type of ferrite cores. • Expanding applications of “lumped” inductors over: • the UHF range (300 MHz–3 GHz) Example: planar spiral-type inductors and microinductors: • the frequency range of 300 MHz–1 GHz Example: “quasi-microwave-range” inductors (air-, cored-, wound, and planar ones). • Nanocrystalline-core inductors. • Inductor-based probes, sensors, and microsensors. Power Loss in Inductor Power loss (in an inductor) is a power that is converted in an inductor into heat and radiation. The total power loss in the inductor is admitted to be a sum of the following contributory losses: • • • •

resistive loss in winding Rres , magnetic loss in core magnetic material Rµ, dielectric loss related to self capacitance and other parasitic capacitances of the inductor Rd , other losses, e.g., radiation loss due to the electromagnetic radiation leaving inductor, loss due to dimensional resonance in the core, loss due to piezomagnetic effects. These losses are not discussed here.

For linear inductors and in the linear range of cored inductors, the power loss PL is expressed as a tangent of the loss angle δ, tgδ, (Fig. 10.50), or equivalently, as the Q-factor (Q = 1/tgδ). The inductor power loss PL and tgδ are related by the expressions PL =

2 urms 2 tgδ = irms ωLs tgδ ωL p

(10.66)

where urms = the rms value of voltage drop across the inductor and irms = rms value of current flowing through the inductor. At high excitation levels, especially in a nonlinear range, the power loss of inductors is expressed directly in watts. Resistive Loss in Winding. A loss due to a dc resistance (ohmic resistance) of a winding conductor increased by increments due to skin and proximity effects Rres referred to the inductive reactance of inductor ωL is tgδ res = Rres ωL

(10.67)

The precise determination of Rres and especially, a determination of skin and proximity effect contributions is rather difficult. If an optimization of such winding parameters as a type of conductor (solid, stranded), its diameter, etc., is sought, then a necessary calculation needs a theoretical background [13]. Rres has a linear voltage–current character. © 2003 by CRC Press LLC

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Magnetic Loss. Depending on whether the excitation level is low (1), middle (2), or high (3), three representations of magnetic loss are accustomed. They are presented next. (1) Low B (or H) Amplitude Excitation. A range of B or H amplitudes exists at which µ (B or H) = const. This corresponds to the case of cored inductors operating at small-signal levels. For this range the ˆ are used. notions of complex inductance Lˆ and complex permeability µ In series representation — Zˆ = jωL + Rs = jω Lˆ s: Lˆ s = µˆ s L0 , µˆ s = µ s′ − jµ s′′, Ls = µ s′L0 , and Rs = ωL0µ s′′

(10.68)

In parallel representation — Yˆ = 1/jωLp + 1/Rp = 1/ω Lˆ p: Lˆ p = µˆ p L0 , 1 µˆ p = 1 µ ′p − 1 jµ ′′p , L p = µ ′p L0 , and Rp = ωL0µ ′′p

(10.69)

Magnetic loss tangent tgδµ: tgδ µ = µ s′′ µ s′ = µ ′p µ ′′p

(

)

(10.70)

(

µ ′p = µ ′s 1 + tg 2δ µ ; µ ′′p = µ ′′s 1 + 1 tg 2δ µ

)

(10.71)

In these formulas, µ′(=µ′s or µ′p) and µ″ (= µ″s or µ″p) are real and imaginary components of the complex magnetic permeability µˆ (= µˆ s or µˆ p) in series or parallel representation, respectively. Note: When the subscript at µ is deleted, the symbol always refers to the series representation. The complex permeability µˆ and related parameters are restricted to linear voltage–current (or B–H) dependences of permeability and loss. It means that µ′ represents the dynamic initial permeability and µ″ the power loss, which are related solely to only reversible magnetization processes in magnetic material. In that convention the magnetic loss at low excitations is presented usually in form of tgδµ(f ) or relative (magnetic) loss factor tgδµ /µi(st) (µi(st) = static initial permeability). All previous considerations concerning the contribution of magnetic permeability to the cored inductor properties are extendable to deal with the magnetic loss. With that intent, the permeability µ or µe appearing in the formulas of interest should be replaced by the complex permeability µˆ . This simple formal operation results, however, in a serious complication of calculation because of the dealing with complex numbers. One of the most important results is that the air-gap reduces the loss resistance Rs and tgδµ by the ratio µ′eg /µ′:

(

Rsg = Rs µ ′eg µ ′

)

(

tgδ µg = tgδ µ µ ′eg µ ′

)

(10.72)

On the other hand, the power loss in magnetic material Pµ remains unchanged for the same core, gapped or ungapped, if it operates at the same induction B; this is because

(

) (

) (

) (

Pµ = ωB 2pVe 2µ 0 × tgδ µ µ ′ = ωB 2pVe 2µ 0 × tgδ µeg µ ′eg

)

(10.73)

where BP = peak value of B and Ve = core equivalent volume. (2) Middle B (or H) Amplitude Excitations. A range of B or H amplitudes exists where magnetic permeability increases linearly with H: µ = µi + vH, magnetic induction B is a parabolic function of H and the hysteresis effects occur (Rayleigh range). The magnetic loss tgδµ is here expressed as a sum of eddy current loss tgδF , residual loss tgδn, and hysteresis loss tgδh : © 2003 by CRC Press LLC

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Bp = 2B red

Bp = B

asu

tg δ

me

red

asu

me

ted

ola

rap ext

Bp = 0

tg δh tg δF tg δn

frequency

FIGURE 10.58 Determination of the magnetic loss tangents according to (10.74).

tgδ µ = tgδ h + tgδ F + tgδ n

(10.74)

tgδh is proportional to H or B, tgδF to frequency, tgδn is assumed to be a constant. This is visible when other notation (given by Legg) is used: Rs µfL = aB p + ef + c = 2πtgδ µ µ ′

(10.75)

where a, e, and c are the hysteresis, eddy current, and residual loss coefficients, respectively; BP = peak value of induction B. The particular loss tangents can be determined as it is shown in Fig. 10.58. (3) High B (or H) Amplitude Excitations. A range of the strongest dependence of the permeability µ on induction B (or field strength H) exists, therefore, of the strongest nonlinearity of µ versus excitation. As a rule, the power inductors and transformers operate in that range. In this range, the magnetic power loss Pµ is being expressed by the heuristic Steinmetz expression: Pµ = η f m Bnp

(10.76)

where η = numerical coefficient, m and n are experimentally determined Steinmetz exponents, which are approximately constant for a given magnetic material, for example, for power ferrites 1.2 < m < 1.4 and 2 < n < 3 at frequencies between 10 and 100 kHz. For Fe-Si alloys: 1.3 < n < 1.4 and 1.6 < m < 1.8 for f < 500 Hz. The plots log Pµ versus log f or versus log BP are therefore straight lines. If these plots deviate from the straight lines, the constancy of exponents m and n deteriorates and the applicability of (10.76) becomes less useful. Dielectric Loss. Every real inductor is inevitably associated with a shunting parasitic capacitance, called self capacitance CP and accompanied conductance GP⋅ CP and GP result from various capacitive and conductive couplings distributed over a real geometrical assembly of various materials (conducting, insulating) forming the physical body of the inductor. In practice, CP and GP are assumed to be as lumped, connected in parallel inductor elements of loss tangent tgδd = GP /ωCP . It is advisable to consider the contribution of tgδd to overall inductor loss for two cases (1) and (2), [13]. (1) Inductor (Ls of tgδ = Rs/ωLs) operating in an intentionally nonresonant circuit, Fig. 10.59(a), tgδ p = ω 2 L sC ptgδ d = tgδ d ( f f 0 ) where f0 = (1/2π) LsCp = inductor self-resonant frequency. © 2003 by CRC Press LLC

2

(10.77)

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Cp

Cp

(a) Gp

Gp

Rs

Ls

(b)

C

Rs

Ls

FIGURE 10.59 Self-capacitance CP and conductance GP of an inductor Ls, Rs in (a) intentionally nonresonant circuit and (b) in an intentionally series resonant circuit.

TABLE 10.16 Summary of Power-Loss Expressions for the Sinusoidally Excited Inductor Loss Representation

Low Excitation (µ′ = const) tgδ (

tgδt =

Middle Excitation (µ = µi + vH)

b)

µ 67 8 a tgδ tl = tgδ res + µ ′′ µ ′ + tgδ (c ) 144244 3

tgδ

tgδ (

High Excitation (µ — strongly nonlinear)

b)

644 47µ 444 8 a tgδ tm = tgδ res + tgδ h + tgδ F + tgδ n + tgδ (c ) Not applicable 14444244443 tgδ

Rs = Rp =

ωLs⋅tg δtl Rs(1 + 1/tg2 δtl)

ωLs⋅tg δtm Rs(1 +1/tg2 δtm)

Not applicable Not applicable

PL =

2 irms ⋅ ωLs tgδ tl or u2rms ⋅ tgδ tl ωL p

2 irms ⋅ ωLs tgδ tm or u2rms ⋅ tgδ tm ωL p

  Rres 2 urms  R 2 + ω 2 L2 + ωC ptgδ d   res  0

Pµ =

(ωB V

(ωB V

2 p

e

)(

2µ 0 ⋅ µ ′′ µ ′ 2

)

2 p

e

)(

2µ 0 ⋅ tg δ µ µ ′

)

c

η f mB np

Distinction: low, middle, and high excitation apply only to the cored inductors. tgδt = total loss tangent; tgδtl = total loss tangent at low excitation level; tg δtm = total loss tangent at middle excitation level. a

b c

tgδ = tgδ ⋅ ( f f ) d 0  p tgδ c  tgδ = (2tgδ + tgδ ) ⋅ ( f f )2 d 0  pr 2

for inductor operating in a nonresonant circuit, Fig. 10.59(a) for inductor operating in a series resonant circuit, Fig. 10.59(b).

For air inductors: tgδµ = 0 because µ′ = 1 and µ″, tgδh, tgδF , tgδn, Pµ equal zero. For air inductor. For cored inductor PL is practically not calculable because of the distorted signal.

(2) The same inductor operating in a series LC intentional resonant circuit, Fig. 10.57(b) and, due to the resonant circumstances, tgδP contributes in that case as tgδpr : tgδ pr = ω 2 L sC p (2tgδ + tgδ d ) = (2tgδ + tgδ d )( f f 0 )

2

(10.78)

Because the value of tg δd may come up even to 0.1, the product LsCp should be as low as possible to make the self-resonant frequency f0  f. As an example, for an inductor having tg δ = 0.004 (Q-factor = 250) and tg δd = 0.02, ( f /f0)2 = 0.1, the degraded Q-factor attains 170 in case (1) and 150 and in case (2). Additionally, tg δd is very sensible to any climatic factors and different agents; the case is known that a low value tgδd increased by nearly 200 times in a hot humidity environment. Inductor Total Power Loss. Different representations of total power loss in inductor are summarized in Table 10.16.

Nonlinearity in Inductors The cored inductors are nonlinear except when the excitation does not exceed the level where µ(B or H) = const. The most current three characteristics of inductor expose the extent of nonlinearity:

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• inductance versus ac current or applied voltage, • inductance versus dc bias current or voltage with superimposed ac current or voltage, • harmonic content versus specified excitation. The nonlinearity of a cored inductor is due to hysteretic properties of the core material, which result in coercive and remanence effects. That peculiarity of magnetic material causes both multivalent and multivalued characters of nonlinearity in cored inductors. In addition, in many circumstances the nonlinearity can also be time dependent, e.g., the harmonic content can vary with time. Generally, the nonlinearity occurs when the core permeability becomes excitation dependent. Such excitation-dependent permeability is termed as amplitude permeability µa. Numerous phenomenal expressions are used for dependence of amplitude permeability µa on excitation. The most well known are expressions for the Rayleigh range of excitations given by Rayleigh:

µ a = µ i + νH ;

(10.79)

Peterson:

µ a = α 0 + α1H + α 2 H 2 + L

(10.80)

where µi = initial permeability; ν = Rayleigh constant; α0, α1, α2, and so on = Peterson coefficients. Today, these expressions are of lesser importance because any experimentally obtained dependence of an inductor on excitation can be numerically processed and used for overall nonlinear analysis (e.g., of signal distortion) in a given circuit. All previously given relationships between the permeability and inductance are to be observed in that analysis. A practical manner of lowering the nonlinearity of an inductor (for a given core material) is to increase the air-gap length and/or to decrease the coupling coefficient kw , or to lower the induction B in the core. For the sake of an example, the third harmonic content, THC = emf3f /emff of the ungapped core is related to tangent of material hysteresis loss tgδh in the Rayleigh range by the formula THC = 0.6tgδ h

(10.81)

For the gapped core, this formula transforms into

(

THC gapped = THC ungapped × µ eg µ

)

(10.82)

Generally, for a given core material, the most nonlinear inductor is that equipped with a core having an ungapped magnetic circuit (e.g., a toroid); the least nonlinear is the inductor having an open short core (e.g., a rod core of low length to diameter ratio). The nonlinear core related relationships are strongly frequency dependent and, nearly as a rule, decrease as the frequency increases.

Magnetic Core Materials For inductor core applications, three families of soft magnetic materials are concerned: • ferrites, mainly Mn–Zn and Ni–Zn, being solid polycrystalline ceramics in whatever form they may be; • iron and/or nickel based alloys (Fe, Fe–Si, Fe–Ni, Fe–Co, Ni–Mn, Ni–Mn–Mo, etc.) in the form of laminations, strips, and ribbons; • pure iron and Fe–Ni or Ni–Mn, etc., alloys in the form of fine powders (2–150 µm) with individual particles that are bonded and electrically insulated by polymers. The most distinctive features of these three families are listed in Table 10.17.

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TABLE 10.17 Three Main Families of Magnetic Materials Used as Cores in Inductors Family

Bs [T]

Ferrites Fe, Ni alloys

Low:

B1

Pµ

= f(T)

f = const

B2

>

B1

B1

= f (f)

log of power loss P

Curie point

(2)

µa max

Tc

(1)

µ′

(1)

Permeability,

µ″

µi

Magnetic induction, B

Saturation induction, Bs

(1)

µa = B/µ0H

Power loss, Pµ

µ′

Magnetic field strength, H

(magnetic) Loss factor

µ′ and µ″ (log scale)

Series complex

permeability components

Magnetic field strength, H

µa max

µ =1

−Br

µi

Tc Curie point

µi=tg α Hc

1

Br

−Hc

µa = B/µ0H

B

Bs

Amplitude permeability,

Magnetic induction, B

µa

Passive Circuit Elements

Temperature, T

FIGURE 10.60 Basic characteristics of magnetic materials essential for inductor applications.

References [1] ANSI-IEEE Standard 100-1988. IEEE Standard Dictionary of Electrical and Electronic Terms, 4th ed., New York: IEEE, 1988. [2] M. Zahn, Electromagnetic Field Theory: A Problem Solving Aproach, New York: John Wiley & Sons, 1979. [3] IEC 60205 Ed. 2.0: Calculation of the effective parameters of magnetic piece parts. [4] IEC 60723-1 to 5 Ed. 1.0: Inductor and Transformer cores for telecommunications. [5] IEC 61007 Ed. 2.0: Transformers and inductors for use in telecommunication equipment — Measuring methods and test procedures. © 2003 by CRC Press LLC

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[6] IEC 61248-1 to 7 Ed. 1.0: Transformers and inductors for use in electronic and telecommunication equipment — Parts 1 to 7: Generic and Sectional Specifications. [7] IEC 61332 Ed. 1.0: Soft ferrite material classification. [8] IEC 62044-3 Ed. 1.1.0: Measuring methods — Part 3: Magnetic properties at high excitation level. [9] IEC 62024-1 (draft): High-frequency inductive components — Electrical characteristics and measuring methods - Part 1: Nanohenry chip inductor. [10] IEC 62025-1 (draft): High-frequency inductive components — Non-electrical characteristics and measuring methods - Part 1: Fixed, surface mounted inductors for use in electric and telecommunication equipment. [11] IEC 62211 (draft): Inductive components — Reliability management. [12] Other than [3] through [11], International Standards and Publications issued by the International Electrotechnical Commission, Technical Committee 51 (IEC/TC51): Magnetic Components and Ferrite Materials (search: http://www.iec.ch/catlg-e.htm) related to inductors and inductor's core magnetic materials. [13] E. C. Snelling, Soft Ferrites, Properties and Applications, 2nd ed., London: Butterworths, 1988. [14] H. Hartwig, Induktivitäten, Berlin: Verlag für Radio-Foto-Kinotechnik, GmbH, 1954. [15] F. E. Terman, Radio Engineering Handbook, 3rd ed., New York: McGraw-Hill, 1947. [16] R. C. Dorf, Ed., Electrical Engineering Handbook, Boca Raton, FL: CRC Press, 1993. [17] W. T. McLyman, Transformer and Inductor Design Handbook, 2nd ed., New York: Marcel Dekker, 1999. [18] C. J. Kaiser, Inductor Handbook, CJ Publishing, 1996. [19] Y. I. Ismail and E. G. Friedman, On-chip Inductance in High Speed Integrated Circuits, Dordrecht, The Netherlands: Kluwer Academic, 2001.

Further Information Several books provide comprehensive and in-depth information on inductors, choice of suitable magnetic material for core, design methods, and various applications: E. C. Snelling, 1988, Soft Ferrites. Properties and Applications, London: Butterworths, 1988; W. Kampczyk and E. Roess, Ferritkerne, Berlin, München: Siemens AG, A. Goldman, Modern Ferrite Technology, New York: Van Nostrand Reinhold, 1990; L. Michalowsky u.a., Magnettechnik, Fachbuchverlag Leipzig GmbH, 1993; R. Boll, Weichmagnetische Werkstoffe, Hanau, Berlin, München: Vacuumschmelze GmbH — Siemens AG, 1990; G. E. Fish, 1989, Soft magnetic materials, Proc. IEEE, vol. 78, no. 6, p. 947, 1989, review paper; McCurrie, R. A., Ferromagnetic Materials, Academic Press, 1994; Niknejad, A. M. and Mayer, R. G., Design, Simulation and Application of Inductors and Transformers for Si RF ICs, Dordrecht, The Netherlands: Kluwer Academic Publishers, 2000. The following journals and conference proceedings publish articles on inductors and related issues. Journals: IEEE Transactions on Magnetism; Journal of Magnetism and Magnetic Materials; Coil and Winding International. Conferences: INTERMAG; (American) Conference on Magnetism and Magnetic Materials (MMM); International Conference on Magnetism (ICM); International Conference on Ferrites (ICF); Soft Magnetic Materials Conference (SMM); European Magnetic Materials and Application Conference (EMMA); Intertech Business Conferences on Magnetic Materials, (American) Annual Applied Power Electronics Conference (APEC). Because of the enormous diversity of inductor applications, properties of various magnetic materials, inductors, and core shapes, it is suggested that one consult the relevant data published by inductor manufacturers in their catalogs and application notes. Chip inductors are described in Chapter 55 of this Handbook. The measuring methods concerning the inductors and magnetic core properties are given in Standards prepared by Technical Committee No. 51 of the International Electrotechnical Commission (IEC). Copies of these Standards may be obtained from the IEC Central Office: 1, rue de Varembé, Geneva, Switzerland or from the IEC National Committees. Standards on inductors and cores are also issued in the European Union by the CENELEC Electronic Components Committee (CECC), General Secretariat, Gartnerstrasse 179, D-6000 Frankfurt/Main, Germany. © 2003 by CRC Press LLC

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Appendices APPENDIX 1 Coefficient K = f (d/l) Figuring in (10.48a) [14] D/l

K

D/l

K

D/l

K

D/l

K

0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.30

0.1957 0.3882 0.5776 0.7643 0.9465 1.126 1.303 1.477 1.648 1.817 1.982 2.144 2.305 2.406 2.616

0.32 0.34 0.36 0.38 0.40 0.42 0.44 0.46 0.48 0.50 0.55 0.60 0.65 0.70 0.75

2.769 2.919 3.067 3.212 3.355 3.497 3.635 3.771 3.905 4.039 4.358 4.668 4.969 5.256 5.535

0.80 0.85 0.90 0.95 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00

5.803 6.063 6.171 6.559 6.795 7.244 7.670 8.060 8.453 8.811 9.154 9.480 9.569 10.09 10.37

2.20 2.40 2.60 2.80 3.00 3.50 4.00 4.50 5.00 6.00 7.00 8.00 9.00 10.00 12.00

10.93 11.41 12.01 12.30 12.71 13.63 14.43 15.14 15.78 16.90 17.85 18.68 19.41 20.07 21.21

APPENDIX 2 Coefficient γ = f(l/h) Figuring in (10.48e) [14] l/h

γ

l/h

γ

l/h

γ

l/h

γ

1 2 3 4 5 6 7 8

0.0000 0.1202 0.1753 0.2076 0.2292 0.2446 0.2563 0.2656

9 10 11 12 13 14 15 16

0.2730 0.2792 0.2844 0.2888 0.2927 0.2961 0.2991 0.3017

17 18 19 20 21 22 23 24

0.3041 0.3062 0.3082 0.3099 0.3116 0.3131 0.3145 0.3157

25 26 27 28 29 30

0.3169 0.3180 0.3190 0.3200 0.3209 0.3218

10.4 Transformer Gordon E. Carlson Introduction The transformer is a two-port passive circuit element that consists of two coils that are coupled magnetically, but have no conductive coupling. It is shown diagrammatically in Fig. 10.61, where the dots by one end of each coil indicate that the magnetic fluxes, φm1 and φm2 are in the same direction when both currents either enter or leave by the dot marked terminal. Coil 1 is connected to the transformer input terminals and is called the primary winding. Coil 2 is called the secondary winding and is connected to the transformer output terminals. A transformer can be used to connect a source to a load and comes in a wide range of sizes. The sizes include very large power-distribution transformers and very small transformers used in electronic equipment. The coils of some transformers used in electronic equipment are wound on a nonmagnetic core such as plastic. These transformers are called air-core transformers. All transformers used in power-distribution systems and some transformers used in electric equipment use an iron core, which produces a coupling coefficient of nearly unity. The coupling coefficient for an air-core transformer seldom exceeds 0.5. Four major characteristics of transformers are as follows: 1. accept energy at one voltage and deliver it at a different voltage, 2. change the load impedance as seen by the source,

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φm2 φm1

i1

i2

+

+ φl1

N1

v1

φl 2

N2

−

v2 −

Coil 1

Coil 2 Core Material

N1 = number of turns in coil 1

N2 = number of turns in coil 2

φl1 = leakage flux due to current i1

φl2 = leakage flux due to current i2

φm1 = magnetizing flux due to current i1

φm2 = magnetizing flux due to current i2

φ1 = φl1 + φm1 = total flux due to current i1

φ2 = φl1 + φm2 = total flux due to current i2

φm1 φ1 = coupling factor for coil 1

k2 =

φm2 φ2 = coupling factor for coil 2

k2 =

k1 = √k1k2 = transformer coupling coefficient < 1

FIGURE 10.61 Transformer diagram and definitions.

3. provide conductive isolation between two portions of a circuit, and 4. produce bandpass signal filters when combined with capacitors. The first characteristic indicated is commonly used in electric power-distribution systems since higher voltages are desired for electric energy transmission than can be safely used by the customer. The higher transmission voltage produces lower transmission current, which requires smaller transmission line conductors. The output stage of an audio amplifier may include a transformer to provide the second and third characteristics listed. In this way, the low impedance of the speaker is matched to the higher output impedance of the power amplifier to yield maximum power transfer for the signal. The isolation property permits the isolation of dc biasing voltages in the amplifier from the speaker coil to avoid magnetic flux saturation in the coil. Finally, a transformer may be used with capacitors for interstage coupling in a radio frequency amplifier. The inductance of the transformer coils and the capacitance of the capacitors can be adjusted to produce bandpass filtering for signals. This section presents linear mathematical models for transformers. The models are in terms of phasors and impedances; that is, they are frequency-domain models. The section begins with a first-order model © 2003 by CRC Press LLC

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I1

I2

n1:n2

+

+

V1

V2

−

−

FIGURE 10.62 Circuit symbol for the ideal transformer.

known as the ideal transformer. A nonideal linear transformer model that includes transformer inductive and resistive effects is then shown.

Ideal Transformer The ideal transformer models the first three transformer characteristics listed above with an ideal, lossless, circuit element. It is a reasonably good model for a transformer with a nearly unity coefficient of coupling and primary and secondary coil inductive impedances that are very large with respect to source and load impedances. Well-designed, iron-core transformers have approximately these characteristics over a reasonable range of frequencies and terminating impedances. A circuit symbol that is often used for an ideal transformer is shown in Fig. 10.62, where a = n1/n2 ≅ N1 /N2 is the effective turns ratio. In place of the lines between the coils, which are intended to indicate the similarity to an iron-core transformer, the word ideal or the equation k = 1 may be written below the coils to identify an ideal transformer. The equations that represent the ideal transformer model are V2 = V1/a and I2 = –aI1. Thus, the voltages are in the same ratio as the effective turns ratio. Also, the ideal transformer is lossless since the complex power supplied by the source V1I1∗ equals the complex power absorbed by the load –V2 I2∗. The hybridh-parameter two-port equation that represents the ideal transformer model is V1  0   =  I 2  −a

a   I1    0  V2 

(10.83)

If the load impedance ZL is connected to the output terminals of an ideal transformer, then V2 = –I2ZL. In this case, the impedance seen by a source connected to the input terminals is Z eq =

V1 (aV2 ) = a2Z L = I1  1   − I 2  a 

(10.84)

Thus, the impedance seen by the source is the square of the effective turns ratio times the load impedance.

Nonideal Transformer The ideal transformer is not an adequate transformer model when the coefficient of coupling is not near unity and/or the load and source impedances are not negligible with respect to the transformer-coil inductive impedances. Also, it cannot be used to investigate the signal filtering that can be performed with a transformer and capacitors. In these cases, a more detailed model is required. Linear Transformer The linear transformer model is shown in Fig. 10.63. R1 and R2 are the resistances and L1 and L2 are the self-inductances of the two transformer coils. M is the mutual inductance corresponding to the magnetic coupling of the coils. The linear transformer is a reasonable model for an air-core transformer since the magnetic flux is proportional to the current. The self-inductances are © 2003 by CRC Press LLC

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I1

jωM

R1

I2

R2

+

+ jωL1

V1

jωL2

V2

−

−

FIGURE 10.63 Linear transformer model.

R1 + V1

jω(L1 − M)

jω(L2 − M)

R2 +

I1

I2

jωM

−

V2 −

FIGURE 10.64 Equivalent T-network representation of a linear transformer.

L1 = N1

φ1 i1

and L2 = N 2

φ2 i2

(10.85)

and the mutual inductance is M = k L1 L 2

(10.86)

From Fig. 10.63, the impedance-parameter two-port equations for the linear-transformer model are V1  R1 + jωL1  = V2   jωM

jωM  I1    R + jωL2  I 2 

(10.87)

Except for its isolation characteristics, the linear transformer in Fig. 10.63 can be represented by the equivalent T-network shown in Fig. 10.64, since this network produces (10.87). The T-network is completely equivalent to the nonisolating linear transformer that is produced when the lower ends of the two coils are conductively connected. Leakage and Magnetizing Inductances The nonideal linear-transformer circuit model can be changed, so it is expressed in terms of leakage inductance and magnetizing inductance instead of self-inductance and mutual inductance. This is convenient because the effects produced by the coil resistance and leakage inductance are nearly linear. Thus, the approximation required to produce a linear model is primarily contained in the magnetizing inductance. From Fig. 10.61 and (10.85), the magnetizing and leakage inductances for coil 1 are, respectively, N1φm1 = k1L1 i1

(10.88)

N 1φ l1 = (1 − k1 )L1 i1

(10.89)

Lm1 = and L l1 =

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Therefore, L1 = L l1 + Lm1

(10.90)

Similarly, for coil 2, N 2 φ m2 = k2L2 i2

(10.91)

N 2φ l 2 = (1 − k2 )L2 i2

(10.92)

Lm 2 =

Ll 2 = and

L 2 = L l 2 + Lm 2

(10.93)

are the magnetizing, leakage, and self-inductances. Using Fig. 10.61 and (10.86), we can write the mutual inductance as M = k1k 2 L1L 2 = k1L1k 2 L 2 = Lm1Lm2

(10.94)

 1 = aLm2 =   Lm1  a where Lm1 n1 N ≡ =a≅ 1 Lm 2 n 2 N2

(10.95)

is the effective turns ratio. How closely the effective turns ratio n1 /n2 approximates the actual turns ratio N1 /N2 depends on how completely all magnetic flux links all coil turns. This is a function of the coil and core geometry. Circuit Model Substitution of the leakage inductances, magnetizing inductances, and effective turns ratio into (10.87) produces an alternate form for the impedance-parameter two-port equations for the linear transformer model. These equations are

[

]

 1 V1 = R1 + jω( Ll1 + Lm1 ) I1 + jωLm1   I 2  a

(10.96)

= ( R1 + jωLl1 )I1 + jωLm1 ( I1 − I a ) and

[

]

 1 V2 = jωLm1   I1 + R2 + jω( Ll 2 + Lm 2 ) I 2  a  1 =   Va + ( R2 + jωLl 2 )I 2  a

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(10.97)

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where  1 I a = −  I 2  a

(10.98)

and Va = jωLm1I1 + jωaLm 2 I 2

(10.99)

= jωLm1 ( I1 − I a )

The transformer circuit model that produces (10.96)–(10.99) is depicted in Fig. 10.65. The only energy losses in the transformer that are accounted for by the linear model depicted in Fig. 10.65 are the heating losses in the coils (called copper losses). An iron-core transformer also has heating losses in the core material (called core losses). The core losses have two components. The first component is hysteresis losses. Hysteresis is the nonlinear phenomenon that causes the magnetic flux response to increasing current to be different from the response to decreasing current. The plot of flux as a function of current traces out a closed curve that is called a hysteresis loop. The area inside this loop is proportional to the energy that produces core heat. The second component of transformer core losses is eddy-current losses. This is a heating loss caused by currents (called eddy currents) that flow in the transformer core due to the voltage induced in the core material by the changing flux. The eddy-current losses can be decreased by laminating the core material to reduce the voltage induced in an eddy-current path and thus the eddy current value. Core losses are caused by nonlinear effects in the magnetic circuit formed by the transformer core. However, they can be approximately included in a linear transformer circuit model by introducing a resistance in parallel with the magnetizing inductance. This improves the linear model accuracy in modeling terminal-characteristics of the transformer. The resulting circuit model is shown in Fig. 10.66, where Iel is called the excitation current, Iml is called the magnetization current, and Rcl is the resistance used to model the core losses. I1

Ia

+

R1

V1

jωLl 2

+

jωLl1 jωLm1

−

I2

n1:n2

+

R2

Va

V2

−

−

FIGURE 10.65 Linear circuit model for a nonideal transformer.

I1 +

R1

I2

n1:n2 jωLl1

jωLl2

Ie1

R2

+

Im1 V1

Rc1

jωLm1

−

FIGURE 10.66 Linear circuit model for a nonideal transformer — including core losses. © 2003 by CRC Press LLC

V2

−

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Passive Circuit Elements

339

Defining Terms Transformer: A two-port passive circuit element consisting of two magnetically coupled coils that are not conductively connected. Air-core transformer: A transformer with a nonmagnetic core. Source: Signal generator that supplies energy to a network. Load: Device that converts electrical energy supplied to a useful output. Modeled as an impedance. Magnetic flux: A magnetic field descriptor. It is thought of as lines indicating the direction of force that the magnetic field produces on a moving charge. The density of the lines indicates the force. Primary winding: Transformer input coil. Secondary winding: Transformer output coil. Leakage inductance: Magnetic flux that links only one coil. Magnetizing inductance: Magnetic flux that links both coils.

References [1] D. R. Cunningham and J. A. Stuller, Basic Circuit Analysis, Boston: Houghton Mifflin, 1991. [2] A. E. Fitzgerald, C. Kingsley, and S. D. Umans, Electric Machinery, 4th ed., New York: McGrawHill, 1983. [3] W. H. Hayt, Jr., and J. E. Kemmerly, Engineering Circuit Analysis, 4th ed., New York: McGraw-Hill, 1986. [4] P. Horowitz and W. Hill, The Art of Electronics, 2nd ed., Cambridge: Cambridge University Press, 1989. [5] J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics, Reading, MA: Addison-Wesley, 1991. [6] G. McPherson and R. D. Laramore, An Introduction to Electrical Machines and Transformers, 2nd ed., New York: John Wiley & Sons, 1990. [7] J. W. Nillson, Electric Circuits, 3rd ed., Reading, MA: Addison-Wesley, 1990. [8] D. L. Schilling and C. Belove, Electronic Circuits, 3rd ed., New York: McGraw-Hill, 1989.

Further Information More detailed developments of linear transformer circuit models can be found in most circuit analysis texts. Two example texts are [1] and [3]. Power transformers and their models are presented in considerable detail in electrical machinery texts such as [6]. These presentations also extend to multiple-coil, three-phase transformers, and tapped transformers. Included in most electrical machinery texts are in-depth discussions of hysteresis and eddy currents, and of methods for reducing losses due to these effects. Also included are procedures for measuring the parameters for transformer circuit models. The use of transformers in electronic circuits is considered in electronic circuit design texts and reference books such as [8] and [4]. Amplifier circuit models that include transformer circuit models are developed in some texts for tuned transformer coupled amplifier stages and transformer coupled load impedances. It is demonstrated how these models can be used to determine amplifier frequency response and power transfer to the load. Other uses indicated for transformers in electronic circuits occur in power supplies and isolation amplifiers.

10.5 Semiconductor Diode B. M. Wilamowski Semiconductor diodes are made out of p–n semiconductor junctions. Nonlinear current–voltage characteristics of such junctions are used to rectify and shape electrical signals. Exponential current–voltage characteristics are sometimes used to build logarithmic amplifiers. The variations of junction capacitances © 2003 by CRC Press LLC

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with applied voltages are used to tune high-frequency electronic circuits. The semiconductor p–n junction illuminated by light will generate a voltage on its terminals. Such a diode is known as a solar battery. Also, the reverse diode current is proportional to the light intensity at the junction. This phenomenon is used in photodiodes. If a diode is biased in the forward direction, it can generate a light. In order to obtain high emission efficiency the light emitting diode (LED) should be made out of a semiconductor material with a direct energy band structure. This way electrons and holes can recombine directly between valence and conduction bands. Typically, LEDs are fabricated using various compositions of Gay All–y AsxPl–x . The wavelength of generated light is inversely proportional to the potential gap of a junction material. When a light intensity is enhanced by additional micromirrors, then laser action occurs. The silicon diodes are not emitting light because the silicon has an indirect band structure and the probability of direct band-to-band recombination is very small. When both sides of the junction are very heavily doped, then for small forward-biasing voltages (0.1–0.3 V) a large tunneling current may occur. For larger forward voltages (0.4–0.5 V) this tunneling current vanishes. This way the current–voltage characteristic has a negative resistance region somewhere between from 0.2 to 0.4 V [Fig. 10.68(d)]. Germanium and other than silicon semiconductors are used to fabricate tunnel diodes. The backward diode has slightly lower impurity concentrations than the tunnel diode and the tunneling current in the forward direction does not occur [Fig. 10.68(e)]. The backward diode is characterized by very sharp knee near zero voltage, and it is used for detection (rectifications) of signals with very small magnitude. Diodes with high breakdown voltage have a p-i-n structure with an impurity profile shown in Fig. 10.67(d). Similar p-i-n structure is also used in microwave circuits as a switch or as an attenuating resistor. For reverse biasing such a microwave p-i-n diode represents an open circuit with a small parasitic junction capacitance. In the forward direction this diode operates as a resistor whose conductance is proportional to the biasing current. At very high frequencies electrons and holes will oscillate rather than flow. Therefore, the microwave p-i-n diode exhibits linear characteristics even for large modulating voltages. Another interesting “diode” structure has the impurity profile shown in Fig. 10.67(f). When reverse biasing exceeds the breakdown voltage, this element generates a microwave signal with a frequency related to the electron transient time through structure. Such a diode is known as an IMPATT (IMPact Avalanche Transit Time) diode. The switching time of a p–n junction from the forward to the reverse direction is limited by the storage time of minority carriers injected into the vicinity of the junction. Much faster operation is possible in the Schottky diode, where minority carrier injection does not exist. Another advantage of the Schottky diode is that the forward voltage drop is smaller than in the silicon p–n junction. This diode uses the metal–semiconductor contact for its operation. Schottky diodes are characterized by relatively small reverse breakdown voltage, rarely exceeding 30 V.

Nonlinear Static I–V Characteristics Semiconductor diodes are characterized by nonlinear current–voltage characteristics. Typical I–V diode characteristics are shown in Fig. 10.68. In the case of a common silicon diode, the forward-direction current increases exponentially at first, and then is limited by an ohmic resistance of the structure. A very small reverse current at first increases slightly with applied voltage and then starts to multiply near the breakdown voltage (Fig. 10.69). The current at the breakdown is limited by ohmic resistances of the structure. P–N Junction Equation The n-type semiconductor material has a positive impurity charge attached to the crystal lattice structure. This fixed positive charge is compensated by free moving electrons with negative charges. Similarly, the p-type semiconductor material has a lattice with a negative charge that is compensated by free moving holes, as Fig. 10.70 shows. The number of majority carriers (electrons in p-type and holes in n-type materials) are approximately equal to the donor or acceptor impurity concentrations, i.e., nn = ND and

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log(N)

log(N)

log(N)

p-type

p-type

x

p-type

x

x

n-type

n-type

(a)

n-type

(b)

log(N)

(c)

log(N)

log(N)

p-type

p-type

p-type

x

x

x

n-type

n-type

(d)

n-type

(e)

(f)

FIGURE 10.67 Impurity profiles for various diodes: (a) step junction, (b) linear junction, (c) diffusion junction, (d) p-i-n junction, (e) p–n+n junction, and (f) p-i-p-n junction.

pp = NA. The number of minority carriers (electrons in p-type and holes in n-type) can be found using the equations np =

ni2 ni2 ≈ pp N A

pn =

ni2 ni2 ≈ nn N D

(10.100)

The intrinsic carrier concentration ni is given by  V  ni2 = ξT 3 exp  – g  ;  VT 

VT =

kT q

(10.101)

where VT = kT/q is the thermal potential (VT = 25.9 mV at 300 K), T is absolute temperature in K, q = 1.6 10–16 C is the electron charge k = 8.62 10–5 eV/K is the Boltzmann constant, Vg is potential gap (Vg = 1.124 V for silicon), and ξ is a material constant. For silicon, intrinsic concentration ni is given by 3

 6522  ni = 7.98 ⋅1015 T 2 exp  −   T 

© 2003 by CRC Press LLC

(10.102)

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i

i

i

v

v

1V

(a)

(b)

i

v

1V

(c)

i

i

v

v

1V

(d)

1V

(e)

v

1V

(f) 1 V

FIGURE 10.68 Forward current–voltage characteristics of various types of diodes: (a) germanium diode, (b) silicon diode, (c) Schottky diode, (d) tunnel diode, (e) backward diode, and (f) LED diode.

− 10

v

− 100

v

1 nA

1 µA

(a)

(b)

FIGURE 10.69 Reverse current–voltage characteristics: (a) germanium diode and (b) silicon diode.

For silicon at 300 K, ni = 1.5 ⋅ 1010 cm–2. When a p–n junction is formed, the fixed electrostatic lattice charges form an electrical field at the junction. Electrons are pushed by electrostatic forces deeper into the n-type region and holes into the p-type region, as illustrated in Fig. 10.70. Between n-type and p-type regions, a depletion layer exists with a built-in potential, which is a function of impurity doping level and intrinsic concentration ni : © 2003 by CRC Press LLC

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Depletion Region p − + − + +

−

+

+ − +

+

−

− −

+

+

− +

n

−

− −

+ + −− + + − − + − + + − − − + + + + + − − −− + + − + − − + + − + − + − + −

FIGURE 10.70 Illustration of the p–n junction.

n   pp   nn p p  N N  V pn = VT ln A 2 D  = VT ln 2  = VT ln n  = Vt ln   ni   pn   ni   np 

(10.103)

The junction current as a function of biasing voltage is described by the diode equation:   v   i = I s exp  − 1   VT  

(10.104)

where   I s = Aqn VT    2 i

  + L  Lp n nndx p pdx   0 0 µp

∫

µn

∫

(10.105)

where nn ≈ ND , pP ≈ NA, µn and µp are mobility of electrons and holes, Ln and Lp are diffusion length for electrons and holes, and A is the device area. In the case of diodes made of silicon or other semiconductor materials with a high energy gap, the reverse-biasing current cannot be calculated from the diode Eq. (10.104). This is due to the carrier generation-recombination phenomenon. Lattice imperfection and most impurities are acting as generation-recombination centers. Therefore, the more imperfections there are in the structure, the larger the deviation from ideal characteristics. Forward I–V Diode Characteristics The diode Eq. (10.104) was derived with an assumption that injected carriers are recombining on the other side of the junction. The recombination within the depletion layer was neglected. In real forwardbiased diodes, electrons and holes are injected through the depletion region and they may recombine there. The recombination component of the forward-biased diode is given by irec = qwA

 v   v  ni = I r 0 exp  exp    2τ 0  2VT   2VT 

(10.106)

where w is the depletion layer thickness and τ0 is the carrier lifetime in the depletion region. The total diode current iT = i + irec where i and irec are defined by (10.104) and (10.106). The recombination component dominates at low current levels, as Fig. 10.71 illustrates. Also in very high current levels, the diode Eq. (10.104) is not valid. Two phenomena cause this deviation. First, an ohmic resistance always plays an important role for large current values. The second

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log(i) (c)

(a) (b)

v

FIGURE 10.71 Current–voltage characteristics of the p–n junction in the forward direction: (a) diffusion current, (b) recombination current, and (c) high-level injection current.

deviation is due to high concentration of injected minority carriers. For very high current levels, the injected minority carrier concentrations may approach, or even become larger than the impurity concentration. An assumption of the quasi-charge neutrality leads to an increase of the majority carrier concentration. Therefore, the effective diode current is lower, as can be seen from (10.105). The high current level in the diode follows the relation  v  ih = I h0 exp    2VT 

(10.107)

Figure 10.71 shows the diode I–V characteristics, which include generation-recombination, diffusion, and high current phenomena. For modeling purposes, the forward diode current can be approximated by  v  iD = I 0 exp    ηVT 

(10.108)

where η has a value between 1.0 and 2.0. Note, that the η coefficient is a function of current, as can be seen in Fig. 10.71. It has a larger value for small and large current regions and it is close to unity in the medium current region. Reverse I–V Characteristics The reverse leakage current in silicon diodes is mainly caused by the electron–hole generation in the depletion layer. This current is proportional to the number of generation-recombination centers. These centers are formed either by a crystal imperfection or deep impurities, which create energy states near the center of the energy gap. Once the reverse voltage is applied, the size of the depletion region and the number of generation-recombination centers increase. Thus, the leakage current is proportional to the thickness of the depletion layer w(v). For a step-abrupt junction

w=

(

2εε 0 V pn − v qN eff

For other impurity profiles, w can be approximated by

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)

(10.109)

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(

w = K V pn − v

)

1 m

(10.110)

The reverse-diode current for small and medium voltages can therefore be approximated by irev = Aw (v )

qni 2τ 0

(10.111)

where ni is given by (10.101) and w by (10.109) or (10.110). The reverse current increases rapidly near the breakdown voltage. This is due to the avalanche multiplication phenomenon. The multiplication factor is often approximated by m=

1  v  1−    BV 

(10.112)

m

where BV stands for the breakdown voltage and m is an exponent chosen experimentally. Note that, for the reverse biasing, both v and BV have negative values and the multiplication factor M reaches an infinite value for v = BV.

Diode Capacitances Two types of capacitances are associated with a diode junction. One capacitance, known as diffusion capacitance, is proportional to the diode current. This capacitance exists only for the forward-biased condition and has the dominant effect there. The second capacitance, known as the depletion capacitance, is a weak function of the applied voltage. Diffusion Capacitance In a forward-biased diode, minority carriers are injected into opposite sides of the junction. Those minority carriers diffuse from the junction and recombine with the majority carriers. Fig. 10.72 shows the distribution of minority carriers in the vicinity of the junction of uniformly doped n-type and p-type regions. The electron charge stored in the p-region corresponds to the area under the curve, and it is equal to Qn = qn0Ln. Similarly, the charge of stored holes Qp = qp0 Lp . The storage charge can also be expressed as Qn = In τn and Qp = Ip τp , where In and Ip are electron and hole currents at the junction and

po = pn exp v VT

no = np exp v VT

( Lx )

n(x) = no exp −

( )

p(x) = po exp −

x Lp

n

x Lp

Ln

FIGURE 10.72 Minority carrier distribution in the vicinity of the p–n junction biased in the forward direction.

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τn and τp are the lifetimes for minority carriers. Assuming τ = τn = τp and knowing that I = Ip + In the total storage charge at the junction is Q = Iτ. The diffusion capacitance can be then computed as

C dif =

 v   τI B dQ d  = τI 0 exp  = dv dv   ηVT   ηVT

(10.113)

As one can see, the diffusion capacitance Cdif is proportional to the storage time τ and to the diode biasing current IB. Note that the diffusion capacitance does not depend on the junction area, only on the diode current. The diffusion capacitances may have very large values. For example, for 100 mA current and τ = 1 µs the junction diffusion capacitance is about 4 µF. Fortunately, this diffusion capacitance is connected in parallel to the small-signal junction resistance r = ηVT /IB , and the time constant r Cdif is equal to the storage time τ.

Depletion Capacitance The reversed-biased diode looks like a capacitor with two “plates” formed of p-type and n-type regions and a dielectric layer (depletion region) between them. The capacitance of a reversed-biased junction can then be written as C dep = A

ε w

(10.114)

where A is a junction area, ε is the dielectric permittivity of semiconductor material, and w is the thickness of the depletion layer. The depletion layer thickness w is a weak function of the applied reverse-biasing voltage. In the simplest case, with a step-abrupt junction, the depletion capacitance is

Cj =

qN eff εε 0

(

2 Vpn − v

)

;

1 1 1 = + N eff N D N A

(10.115)

The steepest capacitance–voltage characteristics are in p+ – i – p – n+ diodes with the impurity profiles shown in Fig. 10.67(f). In general, for various impurity profiles at the junction, the depletion capacitance Cj can be approximated by 1

 v m C j = C j 0 1 −   V pn 

(10.116)

or using linear approximation as shown in Fig. 10.73:  v  C j = C j 0 1 −   Vj0 

(10.117)

Diode as a Switch The switching time of the p–n junction is limited mainly by the storage charge of injected minority carriers into the vicinity of the junction (electrons injected in p-type region and holes injected in n-type region). When a diode is switched from the forward to the reverse direction, these carriers may move freely through the junction. Some of the minority carriers recombine with time. Others are moved away to the other side of the junction. The diode cannot recover its blocking capability as long as a large

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Cj

Cjo

v Vjo

FIGURE 10.73 Capacitance–voltage characteristics for reverse-biased junction.

i

t

FIGURE 10.74 Currents in diode with large minority carrier lifetimes after switching from the forward to the reverse direction.

number of the minority carriers exist and can flow through the junction. An example of the current–time characteristics of a diode switching from the forward to the reverse direction is shown in Fig. 10.74. A few characteristics that are shown in the figure are for the same forward current and different reverse currents. Just after switching, these reverse currents are limited only by external circuitry. In this example, shown in Fig. 10.74, most of the minority carriers are moved to the other side of the junction by the reverse current, and the recombination mechanism is negligible. Note that the larger the reverse current flowing after switching, the shorter the time required to recover the blocking capability. This type of behavior is typical for commonly used high-voltage diodes. In order to shorten the switching time, diodes sometimes are doped with gold or other deep-level impurities to create more generation centers and to increase the carrier recombination. This way, the minority carrier lifetimes of such switching diodes are significantly reduced. The switching time is significantly shorter, but it is almost independent of the reverse-diode current after switching, as Fig. 10.75 shows. This method of artifically increasing recombination rates has some severe disadvantages. Such switching diodes are characterized by very large reverse leakage currents and small breakdown voltages. The best switching diodes utilize metal–semiconductor contacts. They are known as Schottky diodes. In such diodes there is no minority carrier injection phenomenon; therefore, these diodes recover the blocking capability instantaneously. Schottky diodes are also characterized by a relatively small (0.2–0.3 V) © 2003 by CRC Press LLC

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i

t

FIGURE 10.75 Currents in diode with small minority carrier lifetimes after switching from the forward to the reverse direction.

voltage drop in the forward direction. However, their reverse leakage current is larger, and the breakdown voltage rarely exceeds 20–30 V. Lowering the impurity concentration in the semiconductor material leads to slightly larger breakdown voltages, but at the same time, the series diode resistances increase significantly.

Temperature Properties Both forward and reverse diode characteristics are temperature dependent. These temperature properties are very important for correct circuit design. The temperature properties of the diode can be used to compensate for the thermal effects of electronic circuits. Diodes can be used also as accurate temperature sensors. The major temperature effect in a diode is caused by the strong temperature dependence of the intrinsic concentration ni [(10.101) and (10.102)] and by the exponential temperature relationship of the diode Eq. (10.104). By combining (10.101) and (10.104) and assuming the temperature dependence of carrier mobilities, the voltage drop on the forward-biased diode can be written as    i  v = ηVT ln a  + Vg   ξT   

(10.118)

α  (v η) − Vg T  T 0 i = I 0   exp  T  T0   VT0

(10.119)

or diode current

where Vg is the potential gap in semiconductor material, Vg = 1.124 V for silicon and Vg = 1.424 V for GaAs, and α is a material coefficient ranging between 2.5 and 4.0. The temperature dependence of the diode voltage drop dv/dT can be obtained by calculating the derivative of (10.118)

(

dv v − η Vg + αVT = dT T

)

(10.120)

For example, in the case of the silicon diode with a 0.6 voltage drop and assuming η = 1.1, α = 3.0, and T = 300 K, the dV/dT = 1.87 mV/°C.

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The reverse-diode current is a very strong function of the temperature. For diodes made of semiconductor material with a small potential gap, such as germanium, the diffusion component dominates. In this case, the reverse current is proportional to  qV  irev ∝ T α exp − g   kT 

(10.121)

For diodes made of silicon and semiconductors with a higher energy gap, the recombination is the dominant mechanism. In this case, reverse leakage current is proportional to  qV  irev ∝ T α exp − g   2kT 

(10.122)

Using (10.122), one may calculate that for silicon diodes at room temperatures, the reverse leakage current doubles for about every 10°C. The breakdown voltage is also temperature dependent. The tunneling effect dominates in diodes with small breakdown voltages. This effect is often known in literature as the Zener breakdown. In such diodes the breakdown voltage decreases with the temperature. The avalanche breakdown dominates in diodes with large breakdown voltages. When the avalanche mechanism prevails, then the breakdown voltage increases 0.06 percent to 0.1 percent /°C. For medium-range breakdown voltages, one phenomenon compensates the other, and temperature-independent breakdown voltage can be observed. This zero temperature coefficient exists for diodes with breakdown voltages equal to about 5 Vg. In the case of the silicon diode, this breakdown voltage, with a zero temperature coefficient, is equal to about 5.6 V.

Piecewise Linear Model Nonlinear diode characteristics are often approximated by a piecewise linear model. A few possible approaches can be used to linearize the diode characteristics (see Fig. 10.76). The parameters of the most accurate linearized diode model are shown in Fig. 10.77(a), and the linearized diode equivalent circuit is shown in Fig. 10.77(b). The modified diode Eq. (10.108) also can be written as  i  v = ηVT ln   I0 

(10.123)

For the biasing points VB and IB , the small-signal diode resistance dv/di can be computed from (10.123) as r=

dv ηVT = ; di IB

i

i

v

(a)

Vth0 = VB − ηVT

i

v

(b)

FIGURE 10.76 Various ways to linearize diode characteristics.

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(10.124)

i

v

(c)

v

(d)

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i

rD = ηVT /IB

+ −

IB1

Vtho = VB − ηVT

v Vtho VB (a)

VT

(b)

FIGURE 10.77 Linearization of the diode: (a) diode characteristics and (b) equivalent diagram.

and it is only the function of the thermal potential VT and the biasing current IB . Note that the smallsignal diode resistance is almost independent of the diode construction or semiconductor material used. If one requires that this linearized diode have IB current for VB voltage, then the piecewise diode characteristics should be as in Fig. 10.97(a). The equivalent Thevenin and Norton circuits are shown in Fig. 10.97(b). In the case of large-signal operation, the diode can be approximated by shifting the characteristics to the left by ∆V. In this case, the threshold voltage becomes Vth0 = VB – 2VT instead of Vth0 = VB – ηVT.

References [1] A. S. Grove, Physics and Technology of Semiconductor Devices, New York: John Wiley & Sons, 1967. [2] S. M. Sze, Physics of Semiconductor Devices, 2nd ed., New York: John Wiley & Sons, 1981. [3] G. W. Neudeck, The PN Junction Diode, vol. II, Modular Series on Solid-State Devices, Reading, MA: Addison-Wesley, 1983. [4] R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits, 2nd ed., New York: John Wiley & Sons, 1986. [5] E. S. Yang, Microelectronic Devices, New York: McGraw-Hill, 1988. [6] B. G. Streetman, Solid State Electronic Devices, 3rd ed., Englewood Cliffs, NJ: Prentice Hall, 1990. [7] D. A. Neamen, Semiconductor Physics and Devices, Homewood Irwin, 1992.

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11 RF Passive IC Components Thomas H. Lee Maria del Mar Hershenson Sunderarajan S. Mohan

11.1 Introduction 11.2 Fractal Capacitors Lateral Flux Capacitors • Fractals • Fractal Capacitor Structures

11.3 Spiral Inductors Understanding Substrate Effects • Simple, Accurate Expressions for Planar Spiral Inductances

Hirad Samavati C. Patrick Yue

11.4 On-Chip Transformers

Stanford University

Monolithic Transformer Realizations • Analytical Transformer Models

11.1 Introduction Passive energy storage elements are widely used in radio-frequency (RF) circuits. Although their impedance behavior often can be mimicked by compact active circuitry, it remains true that passive elements offer the largest dynamic range and the lowest power consumption. Hence, the highest performance will always be obtained with passive inductors and capacitors. Unfortunately, standard integrated circuit technology has not evolved with a focus on providing good passive elements. This chapter describes the limited palette of options available, as well as means to make the most use out of what is available.

11.2 Fractal Capacitors Of capacitors, the most commonly used are parallel-plate and MOS structures. Because of the thin gate oxides now in use, capacitors made out of MOSFETs have the highest capacitance density of any standard IC option, with a typical value of approximately 7 fF/µm2 for a gate oxide thickness of 5 nm. A drawback, however, is that the capacitance is voltage dependent. The applied potential must be well in excess of a threshold voltage in order to remain substantially constant. The relatively low breakdown voltage (on the order of 0.5 V/nm of oxide) also imposes an unwelcome constraint on allowable signal amplitudes. An additional drawback is the effective series resistance of such structures, due to the MOS channel resistance. This resistance is particularly objectionable at radio frequencies, since the impedance of the combination may be dominated by this resistive portion. Capacitors that are free of bias restrictions (and that have much lower series resistance) may be formed out of two (or more) layers of standard interconnect metal. Such parallel-plate capacitors are quite linear and possess high breakdown voltage, but generally offer two orders of magnitude lower capacitance density than the MOSFET structure. This inferior density is the consequence of a conscious and con­ tinuing effort by technologists to keep low the capacitance between interconnect layers. Indeed, the

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vertical spacing between such layers generally does not scale from generation to generation. As a result, the disparity between MOSFET capacitance density and that of the parallel-plate structure continues to grow as technology scales. A secondary consequence of the low density is an objectionably high capacitance between the bottom plate of the capacitor and the substrate. This bottom-plate capacitance is often a large fraction of the main capacitance. Needless to say, this level of parasitic capacitance is highly undesirable. In many circuits, capacitors can occupy considerable area, and an area-efficient capacitor is therefore highly desirable. Recently, a high-density capacitor structure using lateral fringing and fractal geometries has been introduced.1 It requires no additional processing steps, and so it can be built in standard digital processes. The linearity of this structure is similar to that of the conventional parallel-plate capacitor. Furthermore, the bottom-plate parasitic capacitance of the structure is small, which makes it appealing for many circuit applications. In addition, unlike conventional metal-to-metal capacitors, the density of a fractal capacitor increases with scaling.

Lateral Flux Capacitors Figure 11.1(a) shows a lateral flux capacitor. In this capacitor, the two terminals of the device are built using a single layer of metal, unlike a vertical flux capacitor, where two different metal layers must be used. As process technologies continue to scale, lateral fringing becomes more important. The lateral spacing of the metal layers, s, shrinks with scaling, yet the thickness of the metal layers, t, and the vertical spacing of the metal layers, tox, stay relatively constant. This means that structures utilizing lateral flux enjoy a significant improvement with process scaling, unlike conventional structures that depend on vertical flux. Figure 11.1(b) shows a scaled lateral flux capacitor. It is obvious that the capacitance of the structure of Fig. 11.1(b) is larger than that of Fig. 11.1(a).

FIGURE 11.1 Effect of scaling on lateral flux capacitors: (a) before scaling and (b) after scaling.

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353

FIGURE 11.2 Vertical flux vs. lateral flux: (a) astandard parallel-plate structure, and (b) cross-connected metal layers.

Lateral flux can be used to increase the total capacitance obtained in a given area. Figure 11.2(a) is a standard parallel-plate capacitor. In Fig. 11.2(b), the plates are broken into cross-connected sections.2 As can be seen, a higher capacitance density can be achieved by using lateral flux as well as vertical flux. To emphasize that the metal layers are cross connected, the two terminals of the capacitors in Fig. 11.2(b) are identified with two different shadings. The idea can be extended to multiple metal layers as well. Figure 11.3 shows the ratio of metal thickness to minimum lateral spacing, t/s, vs. channel length for various technologies.3–5 The trend suggests that lateral flux will have a crucial role in the design of capacitors in future technologies.

FIGURE 11.3 Ratio of metal thickness to horizontal metal spacing vs. technology (channel length).

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The increase in capacitance due to fringing is proportional to the periphery of the structure; therefore, structures with large periphery per unit area are desirable. Methods for increasing this periphery are the subject of the following sections.

Fractals A fractal is a mathematical abstract.6 Some fractals are visualizations of mathematical formulas, while others are the result of the repeated application of an algorithm, or a rule, to a seed. Many natural phenomena can be described by fractals. Examples include the shapes of mountain ranges, clouds, coastlines, etc. Some ideal fractals have finite area but infinite perimeter. The concept can be better understood with the help of an example. Koch islands are a family of fractals first introduced as a crude model for the shape of a coastline. The construction of a Koch curve begins with an initiator, as shown in the example of Fig. 11.4(a). A square is a simple initiator with M = 4 sides. The construction continues by replacing each segment of the initiator with a curve called a generator, an example of which is shown in Fig. 11.4(b) that has N = 8 segments. The size of each segment of the generator is r = 1 ⁄ 4 of the initiator. By recursively replacing each segment of the resulting curve with the generator, a fractal border is formed. The first step of this process is depicted in Fig. 11.4(c). The total area occupied remains constant throughout the succession of stages because of the particular shape of the generator. A more complicated Koch island can be seen in Fig. 11.5. The associated initiator of this fractal has four sides and its generator has 32 segments. It can be noted that the curve is self similar, that is, each section of it looks like the entire fractal. As we zoom in on Fig. 11.5, more detail becomes visible, and this is the essence of a fractal. Fractal dimension, D, is a mathematical concept that is a measure of the complexity of a fractal. The dimension of a flat curve is a number between 1 and 2, which is given by log( N ) D = ----------------1 log  --  r

(11.1)

where N is the number of segments of the generator and r is the ratio of the generator segment size to the initiator segment size. The dimension of a fractal curve is not restricted to integer values, hence the term “fractal.” In particular, it exceeds 1, which is the intuitive dimension of curves. A curve that has a high degree of complexity, or D, fills out a two-dimensional flat surface more efficiently. The fractal in Fig. 11.4(c) has a dimension of 1.5, whereas for the border line of Fig.11.5, D = 1.667. For the general case where the initiator has M sides, the periphery of the initiator is proportional to the square root of the area:

FIGURE 11.4 Construction of a Koch curve: (a) an initiator, (b) a generator, and (c) first step of the process.

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FIGURE 11.5 A Koch island with M = 4, N = 32, and r = 1/8.

P0 = k ⋅ A

(11.2)

where k is a proportionality constant that depends on the geometry of the initiator. For example, for a square initiator, k = 4; and for an equilateral triangle, k = 2 ⋅ 4 27 . After n successive applications of the generation rule, the total periphery is P = k A ⋅ (Nr)

n

(11.3)

and the minimum feature size (the resolution) is k A n l = ----------- ⋅ r M

(11.4)

Eliminating n from Eqs. (11.3) and (11.4) and combining the result with Eq. (11.1), we have D

( A) k - ⋅ -----------P = -----------D–1 D–1 l M

D

(11.5)

Equation (11.5) demonstrates the dependence of the periphery on parameters such as the area and the resolution of the fractal border. It can be seen from Eq. (11.5) that as l tend toward zero, the periphery goes to infinity; therefore, it is possible to generate fractal structures with very large perim­ eters in any given area. However, the total periphery of a fractal curve is limited by the attainable resolution in practical realizations.

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FIGURE 11.6 3-D representation of a fractal capacitor using a single metal layer.

Fractal Capacitor Structures The final shape of a fractal can be tailored to almost any form. The flexibility arises from the fact that a wide variety of geometries can be used as the initiator and generator. It is also possible to use different generators during each step. This is an advantage for integrated circuits where flexibility in the shape of the layout is desired. Figure 11.6 is a three-dimensional representation of a fractal capacitor. This capacitor uses only one metal layer with a fractal border. For a better visualization of the overall picture, the terminals of this square-shaped capacitor have been identified using two different shadings. As was discussed before, multiple cross-connected metal layers may be used to improve capacitance density further. One advantage of using lateral flux capacitors in general, and fractal capacitors in particular, is the reduction of the bottom-plate capacitance. This reduction is due to two reasons. First, the higher density of the fractal capacitor (compared to a standard parallel-plate structure) results in a smaller area. Second, some of the field lines originating from one of the bottom plates terminate on the adjacent plate, instead of the substrate, which further reduces the bottom-plate capacitance as shown in Fig. 11.7. Because of this property, some portion of the parasitic bottom-plate capacitor is converted into the more useful plate-to-plate capacitance. The capacitance per unit area of a fractal structure depends on the dimension of the fractal. To improve the density of the layout, fractals with large dimensions should be used. The concept of fractal dimension is demonstrated in Fig. 11.8. The structure in Fig. 11.8(a) has a lower dimension compared to the one in Fig. 11.8(b), so the density (capacitance per unit area) of the latter is higher. To demonstrate the dependence of capacitance density on dimension and lateral spacing of the metal layers, a first-order electromagnetic simulation was performed on two families of fractal structures. In Fig. 11.9, the boost factor is plotted vs. horizontal spacing of the metal layers. The boost factor is defined as the ratio of the total capacitance of the fractal structure to the capacitance of a standard parallel-plate structure with the same area. The solid line corresponds to a family of fractals with a moderate fractal dimension of 1.63, while the dashed line represents another family of fractals with D = 1.80 , which is a relatively large value for the dimension. In this first-order simulation, it is assumed that the vertical spacing and the thickness of the metal layers are kept

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FIGURE 11.7 Reduction of the bottom-plate parasitic capacitance.

FIGURE 11.8 Fractal dimension of (a) is smaller than (b).

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FIGURE 11.9 Boost factor vs. lateral spacing.

constant at a 0.8-µm level. As can be seen in Fig. 11.9, the amount of boost is a strong function of the fractal dimension as well as scaling. In addition to the capacitance density, the quality factor, Q, is important in RF applications. Here, the degradation in quality factor is minimal because the fractal structure automatically limits the length of the thin metal sections to a few microns, keeping the series resistance reasonably small. For applications that require low series resistance, lower dimension fractals may be used. Fractals thus add one more degree of freedom to the design of capacitors, allowing the capacitance density to be traded for a lower series resistance. In current IC technologies, there is usually tighter control over the lateral spacing of metal layers compared with the vertical thickness of the oxide layers, from wafer to wafer and across the same wafer. Lateral flux capacitors shift the burden of matching away from oxide thickness to lithography. Therefore, by using lateral flux, matching characteristics can improve. Furthermore, the pseudo-random nature of the structure can also compensate, to some extent, the effects of non-uniformity of the etching process. To achieve accurate ratio matching, multiple copies of a unit cell should be used, as is standard practice in high-precision analog circuit design. Another simple way of increasing capacitance density is to use an interdigitated capacitor depicted in Fig. 11.10.2,7 One disadvantage of such a structure compared to fractals is its inherent parasitic inductance. Most of the fractal geometries randomize the direction of the current flow and thus reduce the effective series inductance; whereas for interdigitated capacitors, the current flow is in the same direction for all the parallel stubs. In addition, fractals usually have lots of rough edges that accumulate electrostatic energy more efficiently compared to interdigitated capacitors, causing a boost in capacitance (generally of the order of 15%). Furthermore, interdigitated structures are more vulnerable to non-uniformity of the etching process. However, the relative simplicity of the interdigitated capacitor does make it useful in some applications. The woven structure shown in Fig. 11.11 may also be used to achieve high capacitance density. The vertical lines are in metal-2 and horizontal lines are in metal-1. The two terminals of the capacitor are identified using different shades. Compared to an interdigitated capacitor, a woven structure has much less inherent series inductance. The current flowing in different directions results in a higher self-resonant frequency. In addition, the series resistance contributed by vias is smaller than that of an interdigitated capacitor, because cross-connecting the metal layers can be done with greater ease. However, the capac­ itance density of a woven structure is smaller compared to an interdigitated capacitor with the same metal pitch, because the capacitance contributed by the vertical fields is smaller. © 2003 by CRC Press LLC

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FIGURE 11.10 An interdigitated capacitor.

FIGURE 11.11 A woven structure.

11.3 Spiral Inductors More than is so with capacitors, on-chip inductor options are particularly limited and unsatisfactory. Nevertheless, it is possible to build practical spiral inductors with values up to perhaps 20 nH and with Q values of approximately 10. For silicon-based RF ICs, Q degrades at high frequencies due to energy dissipation in the semiconducting substrate.8 Additionally, noise coupling via the substrate at GHz frequencies has been reported.9 As inductors occupy substantial chip area, they can potentially be the source and receptor of detrimental noise coupling. Furthermore, the physical phenomena underlying the substrate effects are complicated to characterize. Therefore, decoupling the inductor from the substrate can enhance the overall performance by increasing Q, improving isolation, and simplifying modeling. Some approaches have been proposed to address the substrate issues; however, they are accompanied by drawbacks. Some10 have suggested the use of high-resistivity (150 to 200 Ω-cm) silicon substrates to mimic the low-loss, semi-insulating GaAs substrate, but this is rarely a practical option. Another approach selectively removes the substrate by etching a pit under the inductor.11 However, the etch adds extra processing cost and is not readily available. Moreover, it raises reliability concerns such as packaging yield and long-term mechanical stability. For low-cost integration of inductors, the solution to substrate problems should avoid increasing process complexity.

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FIGURE 11.12 Lumped physical model of a spiral inductor on silicon.

In this section, we present the patterned ground shield (PGS),23 which is compatible with standard silicon technologies, and which reduces the unwanted substrate effects. The great improvement provided by the PGS reduces the disparity in quality between spiral inductors made in silicon and GaAs IC technologies.

Understanding Substrate Effects To understand why the PGS should be effective, consider first the physical model of an ordinary inductor on silicon, with one port and the substrate grounded, as shown in Fig. 11.12.8 An on-chip inductor is physically a three-port element including the substrate. The one-port connection shown in Fig. 11.12 avoids unnecessary complexity in the following discussion and at the same time preserves the inductor characteristics. In the model, the series branch consists of Ls, Rs, and Cs. Ls represents the spiral inductance, which can be computed using the Greenhouse method12 or well approximated by simple analytical formulas to be presented later. Rs is the metal series resistance whose behavior at RF is governed by the eddy current effect. This resistance accounts for the energy loss due to the skin effect in the spiral interconnect structure as well as the induced eddy current in any conductive media close to the inductor. The series feedforward capacitance, Cs, accounts for the capacitance due to the overlaps between the spiral and the center-tap underpass.13 The effect of the inter-turn fringing capacitance is usually small because the adjacent turns are almost at equal potentials, and therefore it is neglected in this model. The overlap capacitance is more significant because of the relatively large potential difference between the spiral and the center-tap underpass. The parasitics in the shunt branch are modeled by Cox, CSi, and RSi. Cox represents the oxide capacitance between the spiral and the substrate. The silicon substrate capacitance and resistance are modeled by CSi and RSi, respectively.14,15 The element RSi accounts for the energy dissipation in the silicon substrate. Expressions for the model element values are as follows: ρl - R s = --------------------------t –-­ δ  δw 1 – e  

© 2003 by CRC Press LLC

(11.6)

ε ox 2 C s = nw ⋅ ------------------t oxM1 – M2

(11.7)

ε ox ⋅l⋅w C ox = -------2t ox

(11.8)

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1 C Si = -- ⋅ l ⋅ w ⋅ C sub 2

(11.9)

2 R Si = -----------------------l ⋅ w ⋅ G sub

(11.10)

where ρ is the DC resistivity of the spiral; t is the overall length of the spiral windings; w is the line width; δ is the skin depth; n is the number of crossovers between the spiral and center-tap (and thus n = N – 1, where N is the number of turns); toxM1–M2 is the oxide thickness between the spiral and substrate; Csub is the substrate capacitance per unit area; and Gsub is the substrate conductance per unit area. In general, one treats Csub and Gsub as fitting parameters. Exploration with the model reveals that the substrate loss stems primarily from the penetration of the electric field into the lossy silicon substrate. As the potential drop in the semiconductor (i.e., across RSi in Fig. 11.12) increases with frequency, the energy dissipation in the substrate becomes more severe. It can be seen that increasing Rp to infinity reduces the substrate loss. It can be demonstrated that Rp approaches infinity as RSi goes either to zero or infinity. This observation implies that Q can be improved by making the silicon substrate either a perfect insulator or a perfect conductor. Using high-resistivity silicon (or etching it away) is equivalent to making the substrate an open circuit. In the absence of the freedom to do so, the next best option is to convert the substrate into a better conductor. The approach is to insert a ground plane to block the inductor electric field from entering the silicon. In effect, this ground plane becomes a pseudo-substrate with the desired characteristics. The ground shield cannot be a solid conductor, however, because image currents would be induced in it. These image currents tend to cancel the magnetic field of the inductor proper, decreasing the inductance. To solve this problem, the ground shield is patterned with slots orthogonal to the spiral as illustrated in Fig. 11.13. The slots act as an open circuit to cut off the path of the induced loop current. The slots should be sufficiently narrow such that the vertical electric field cannot leak through the patterned ground shield into the underlying silicon substrate. With the slots etched away, the ground strips serve as the termination for the electric field. The ground strips are merged together around the four outer edges of the spiral. The separation between the merged area and the edges is not critical. However, it is crucial that the merged area not form a closed ring around the spiral since it can potentially support unwanted loop current. The shield should be strapped with the top layer metal to provide a low-impedance path to ground. The general rule is to prevent negative mutual coupling while minimizing the impedance to ground. The shield resistance is another critical design parameter. The purpose of the patterned ground shield is to provide a good short to ground for the electric field. Because the finite shield resistance contributes to energy loss of the inductor, it must be kept small. Specifically, by keeping the shield resistance small compared to the reactance of the oxide capacitance, the voltage drop that can develop across the shield resistance is very small. As a result, the energy loss due to the shield resistance is insignificant compared to other losses. A typical on-chip spiral inductor has parasitic oxide capacitance between 0.25 and 1 pF, depending on the size and the oxide thickness. The corresponding reactance due to the oxide capacitance at 1 to 2 GHz is of the order of 100 Ω, and hence a shield resistance of a few ohms is sufficiently small not to cause any noticeable loss. With the PGS, one can expect typical improvements in Q ranging from 10 to 33%, in the frequency range of 1 to 2 GHz. Note that the inclusion of the ground shields increases Cp, which causes a fast rolloff in Q above the peak-Q frequency and a reduction in the self-resonant frequency. This modest improvement in inductor Q is certainly welcome, but is hardly spectacular by itself. However, a more dramatic improvement is evident when evaluating inductor-capacitor resonant circuits. Such LC tank circuits can absorb the parasitic capacitance of the ground shield. The energy stored in such parasitic elements is now part of the circuit, therefore, the overall circuit Q is greatly increased. Improvements of factors of approximately two are not unusual, so that tank circuits realized with PGS inductors possess roughly the same Q as those built in GaAs technologies. As stated earlier, substrate noise coupling can be an issue of great concern owing to the relatively large size of typical inductors. Shielding by the PGS improves isolation by 25 dB or more at GHz © 2003 by CRC Press LLC

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FIGURE 11.13 A close-up photo of the patterned ground shield.

frequencies. It should be noted that, as with any other isolation structure (such as a guard ring), the efficacy of the PGS is highly dependent on the integrity of the ground connection. One must often make a tradeoff between the desired isolation level and the chip area that is required to provide a lowimpedance ground connection.

Simple, Accurate Expressions for Planar Spiral Inductances In the previous section, a physically based model for planar spiral inductors was offered, and reference was made to the Greenhouse method as a means for computing the inductance value. This method uses as computational atoms the self- and mutual inductances of parallel current strips. It is relatively straight­ forward to apply, and yields accurate results. Nevertheless, simpler analytic formulas are generally pre­ ferred for design since important insights are usually more readily obtained. As a specific example, square spirals are popular mainly because of their ease of layout. Other polygonal spirals have also been used to improve performance by more closely approximating a circular spiral. However, a quantitative evaluation of possible improvements is cumbersome without analytical formulas for inductance. Among alternative shapes, hexagonal and octagonal inductors are used widely. Figures 11.14 through 11.16 and show the layout for square, hexagonal, and octagonal inductors, respectively. For a given shape, an inductor is completely specified by the number of turns n, the turn width w, the turn spacing s, and any one of the following: the outer diameter dout, the inner diameter din, the average diameter davg = 0.5(dout + din), or the fill ratio, defined as ρ = (dout – din)/(dout + din). The thickness of the inductor has only a very small effect on inductance and will therefore be ignored here. We now present three approximate expressions for the inductance of square, hexagonal, and octagonal planar inductors. The first approximation is based on a modification of an expression developed by © 2003 by CRC Press LLC

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FIGURE 11.14 Square inductor.

Wheeler16; the second is derived from electromagnetic principles by approximating the sides of the spirals as current sheets; and the third is a monomial expression derived from fitting to a large database of inductors (whose exact inductance values are obtained from a 3-D electromagnetic field solver). All three expressions are accurate, with typical errors of 2 to 3%, and very simple, and are therefore excellent candidates for use in design and optimization. Modified Wheeler Formula Wheeler16 presented several formulas for planar spiral inductors, which were intended for discrete induc­ tors. A simple modification of the original Wheeler formula allows us to obtain an expression that is valid for planar spiral integrated inductors: 2

n d avg L mw = K 1 µ 0 -----------------1 + K2 ρ

(11.11)

where ρ is the fill ratio defined previously. The coefficients K1 and K2 are layout dependent and are shown in Table 11.1 The fill factor ρ represents how hollow the inductor is: for small ρ, we have a hollow inductor (dout ≅ din), and for a large ρ we have a filled inductor (dout  din). Two inductors with the same average diameter but different fill ratios will, of course, have different inductance values; the filled one has a smaller inductance because its inner turns are closer to the center of the spiral, and so contribute less positive mutual inductance and more negative mutual inductance. Some degree of hollowness is generally desired because the innermost turns contribute little overall inductance, but significant resistance. Expression Based on Current Sheet Approximation Another simple and accurate expression for the inductance of a planar spiral can be obtained by approx­ imating the sides of the spirals by symmetrical current sheets of equivalent current densities.17 For example, in the case of the square, we obtain four identical current sheets: the current sheets on opposite sides are parallel to one another, whereas the adjacent ones are orthogonal. Using symmetry and the fact © 2003 by CRC Press LLC

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FIGURE 11.15 Hexagonal inductor.

FIGURE 11.16 Octagonal inductor. © 2003 by CRC Press LLC

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TABLE 11.1

Coefficients for Modified Wheeler Formula

Layout Square Hexagonal Octagonal

K1

K2

2.34 2.33 2.25

2.75 3.82 3.55

that sheets with orthogonal current sheets have zero mutual inductance, the computation of the induc­ tance is now reduced to evaluating the self-inductance of one sheet and the mutual inductance between opposite current sheets. These self- and mutual inductances are evaluated using the concepts of geometric mean distance (GMD) and arithmetic mean distance (AMD).17,18 The resulting expression is: 2

µn d avg - (c 1 (logc 2 ⁄ ρ) + c 3 ρ) L gmd = ----------------π

(11.12)

where the coefficients ci are layout dependent and are lsited in Table 11.2 TABLE 11.2

Coefficients for Current-Sheet Inductance Formula

Layout

c1

c2

c3

Square Hexagonal Octagonal

2.00 1.83 1.87

2.00 1.71 1.68

0.54 0.45 0.60

A detailed derivation of these formulas can be found in Ref. 19. Because this formula is based on a current sheet approximation, its accuracy worsens as the ratio s/w becomes large. In practice, this is not a problem because practical integrated spiral inductors are built with s < w. The reason is that a smaller spacing improves the inter-winding magnetic coupling and reduces the area consumed by the spiral. A large spacing is only desired to reduce the inter-winding capacitance. This is rarely a concern as this capacitance is always dwarfed by the under-pass capacitance.8 Data-Fitted Monomial Expression Our final expression is based on a data-fitting technique, in which a population of thousands of inductors are simulated with an electromagnetic field solver. The inductors span the entire range of values of relevance to RF circuits. A monomial expression is then fitted to the data, which ultimately yields: α2

α4 α5

α1 w d α3 n s L mon = βd avg avg

(11.13)

where the coefficients β and αi are layout dependent, and given in Table 11.3. TABLE 11.3

Coefficients for Monomial Inductance Formula

Layout

b

α1

α2

α3

α4

α5

Square Hexagonal Octagonal

1.66 × 10–3 1.33 × 10–3 1.34 × 10–3

–1.33 –1.46 –1.35

–0.13 –0.16 –0.15

2.50 2.67 2.56

1.83 1.80 1.77

–0.022 –0.030 –0.032

Of course, it is also possible to use other data-fitting techniques; for example, one which minimizes the maximum error of the fit, or one in which the coefficients must satisfy given inequalities or bounds. The monomial expression is useful because, similar to the other expressions, it is very accurate and very simple. Its real value, however, is that it can be used for the optimal design of inductors and © 2003 by CRC Press LLC

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FIGURE 11.17 Error distribution for three formulas, compared with field solver simulations.

circuits containing inductors, using geometric programming, which is a type of optimization method that requires monomial models.20,21 Figure 11.17 shows the absolute error distributions of these expressions. The plots show that typical errors are in the 1 to 2% range, and most of the errors are below 3%. These expressions for inductance, while quite simple, are thus sufficiently accurate that field solvers are rarely necessary. These expressions can be included in a physical, scalable lumped-circuit model for spiral inductors where, in addition to providing design insight, they allow efficient optimization schemes to be employed.

11.4 On-Chip Transformers Transformers are important elements in RF circuits for impedance conversion, impedance matching, and bandwidth enhancement. Here, we present an analytical model for monolithic transformers that is suitable for circuit simulation and design optimization. We also provide simple expressions for calculating the mutual coupling coefficient (k). We first discuss different on-chip transformers and their advantages and disadvantages. We then present an analytical model along with expressions for the elements in it and the mutual coupling coefficient.

Monolithic Transformer Realizations Figures 11.18 through 11.23 illustrate common configurations of monolithic transformers. The different realizations offer varying tradeoffs among the self-inductance and series resistance of each port, the mutual coupling coefficient, the port-to-port and port-to-substrate capacitances, resonant frequencies, symmetry, and area. The models and coupling expressions allow these trade-offs to be systematically explored, thereby permitting transformers to be customized for a variety of circuit design requirements. © 2003 by CRC Press LLC

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FIGURE 11.18 Tapped transformer.

FIGURE 11.19 Interleaved transformer. © 2003 by CRC Press LLC

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FIGURE 11.20 Stacked transformer with top spiral overlapping the bottom one.

The characteristics desired of a transformer are application dependent. Transformers can be configured as three or four-terminal devices. They may be used for narrowband or broadband applications. For example, in single-sided to differential conversion, the transformer might be used as a four-terminal narrowband device. In this case, a high mutual coupling coefficient and high self-inductance are desired, along with low series resistance. On the other hand, for bandwidth extension applications, the transformer is used as a broadband three-terminal device. In this case, a small mutual coupling coefficient and high series resistance are acceptable, while all capacitances need to be minimized.22 The tapped transformer (Fig. 11.18) is best suited for three-port applications. It permits a variety of tapping ratios to be realized. This transformer relies only on lateral magnetic coupling. All windings can be implemented with the top metal layer, thereby minimizing port-to-substrate capacitances. Because the two inductors occupy separate regions, the self-inductance is maximized while the port-to-port capacitance is minimized. Unfortunately, this spatial separation also leads to low mutual coupling (k = 0.3–0.5). The interleaved transformer (Fig. 11.19) is best suited for four-port applications that demand sym­ metry. Once again, capacitances can be minimized by implementing the spirals with top level metal so that high resonant frequencies may be realized. The interleaving of the two inductances permit moderate coupling (k = 0.7) to be achieved at the cost of reduced self-inductance. This coupling may be increased at the cost of higher series resistance by reducing the turn width (w) and spacing (s). The stacked transformer (Fig. 11.20) uses multiple metal layers and exploits both vertical and lateral magnetic coupling to provide the best area efficiency, the highest self-inductance, and highest coupling (k = 0.9). This configuration is suitable for both three- and four-terminal configurations. The main drawback is the high port-to-port capacitance, or equivalently a low self-resonant frequency. In some cases, such as narrowband impedance transformers, this capacitance may be incorporated as part of the resonant circuit. Also, in multi-level processes, the capacitance can be reduced by increasing the oxide thickness between spirals. For example, in a five-metal process, 50 to 70% reductions in port-to-port capacitance can be achieved by implementing the spirals on layers five and three instead of five and four. The increased vertical separation will reduce k by less than 5%. One can also trade off reduced coupling for reduced capacitance by displacing the centers of the stacked inductors (Figs. 11.21 and 11.22)

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FIGURE 11.21 Stacked transformer with top and bottom spirals laterally shifted.

FIGURE 11.22 Stacked transformer with top and bottom spirals diagonally shifted.

Analytical Transformer Models Figures 11.23 and 11.24 present the circuit models for tapped and stacked transformers, respectively. The corresponding element values for the tapped transformer model are given by the following equations (subscript o refers to the outer spiral, i to the inner spiral, and T to the whole spiral):

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FIGURE 11.23 Tapped transformer model.

FIGURE 11.24 Stacked transformer model.

2

2

9.375µ 0 n T AD T ­ L T = -----------------------------------11OD T – 7AD T 2

2

9.375µ 0 n o AD o ­ L o = ----------------------------------11OD o – 7AD o 2

(11.15)

2

9.375µ 0 n i AD i L i = ---------------------------------­ 11OD i – 7AD i

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(11.14)

(11.16)

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LT – Lo – Li M = -------------------------2 Lo Li

(11.17)

ρl o R so = --------------------------t –-­ δ  δw 1 – e  

(11.18)

ρl i - R si = --------------------------t –-­ δ  δw 1 – e  

(11.19)

ε ox 2 - ⋅ (n o – 1)w C ovo = ------------t ox, t – b

(11.20)

ε ox C oxo = -------⋅l w 2t ox o

(11.21)

ε ox C oxi = -------⋅ (l + l )w 2t ox o i

(11.22)

where ρ is the DC metal resistivity; δ is the skin depth; tox,t–b is the oxide thickness from top level metal to bottom metal; n is the number of turns; OD, AD, and ID are the outer, average, and inner diameters, respectively; l is the length of the spiral; w is the turn width; t is the metal thickness; and A is the area. Expressions for the stacked transformer model are as follows (subscript t refers to the top spiral and b to the bottom spiral): 2

2

9.375µ 0 n AD - L t = -----------------------------------11OD T – 7AD T

(11.23)

L b = L t

(11.24)

d k = 0.9 – -------s- AD

(11.25)

M = k L t L b

(11.26)

ρt l - R st = -----------------------------tt –---­  δ t δt w  1 – e    ρb l - R sb = ------------------------------tb –----­  δ b δb w  1 – e   

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(11.27)

(11.28)

ε ox A - ⋅ l ⋅ w ⋅ ------ovC ov = ---------------2t ox, t – b A

(11.29)

ε ox A – A ov - - ⋅ l ⋅ w ⋅ ---------------C oxt = --------2t oxt A

(11.30)

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ε ox ⋅l⋅w C oxb = -------2t ox

(11.31)

C oxm = C oxt + C oxb

(11.32)

where toxt is the oxide thickness from top metal to the substrate; toxb is the oxide thickness from bottom metal to substrate; k is the coupling coefficient; Aov is the overlap area of the two spirals; and ds is the center-to-center spiral distance. The expressions for the series resistances (Rso, Rsi, Rst, and Rsb), the port-substrate capacitances (Coxo, Coxi, Coxt, Coxb, and Coxm) and the crossover capacitances (Covo, Covi, and Cov) are taken from Reference 8. Note that the model accounts for the increase in series resistance with frequency due to skin effect. Patterned ground shields (PGS) are placed beneath the transformers to isolate them from resistive and capacitive coupling to the substrate.23 As a result, the substrate parasitics can be neglected. The inductance expressions in the foregoing are based on the modified Wheeler formula discussed earlier.24 This formula does not take into account the variation in inductance due to conductor thickness and frequency. However, in practical inductor and transformer realizations, the thickness is small com­ pared to the lateral dimensions of the coil and has only a small impact on the inductance. For typical conductor thickness variations (0.5 to 2.0 µm), the change in inductance is within a few percent for practical inductor geometries. The inductance also changes with frequency due to changes in current distribution within the conductor. However, over the useful frequency range of a spiral, this variation is negligible.23 When compared with field solver simulations, the inductance expression exhibits a maximum error of 8% over a broad design space (outer diameter OD varying from 100 to 480 µm, L varying from 0.5 to 100 nH, w varying from 2 µm to 0.3OD, s varying from 2 µm to w, and inner diameter ID varying from 0.2 to 0.8OD). For the tapped transformer, the mutual inductance is determined by first calculating the inductance of the whole spiral (LT), the inductance of the outer spiral (Lo), the inductance of the inner spiral (Li), and then using the expression M = (LT – Lo – Li)/2. For the stacked transformer, the spirals have identical lateral geometries and therefore identical inductances. In this case, the mutual inductance is determined by first calculating the inductance of one spiral (LT), the coupling coefficient (k) and then using the expression M = kLT. In this last case, the coupling coefficient is given by k = 0.9 – ds/(AD) for ds < 0.7AD, where ds is the center-to-center spiral distance and AD is the average diameter of the spirals. As ds increases beyond 0.7AD, the mutual coupling coefficient becomes harder to model. Eventually, k crosses zero and reaches a minimum value of approximately –0.1 at ds = AD. As ds increases further, k asymptotically approaches zero. At ds = 2AD, k = –0.02, indicating that the magnetic coupling between closely spaced spirals is negligible. The self-inductances, series resistances, and mutual inductances are independent of whether a trans­ former is used as a three- or four-terminal device. The only elements that require recomputation are the port-to-port and port-to-substrate capacitances. This situation is analogous to that of a spiral inductor being used as a single- or dual-terminal device. As with the inductance formulas, the transformer models obviate the need for full field solutions in all but very rare instances, allowing rapid design and optimization.

References 1. Samavati, H. et al., “Fractal capacitors,” 1998 IEEE ISSCC Dig. of Tech. Papers, Feb. 1998. 2. Akcasu, O. E., “High capacitance structures in a semiconductor device,” U.S. Patent 5 208 725, May 1993. 3. Bohr, M., “Interconnect scaling — The real limiter to high performance VLSI,” Intl. Electron Devices Meeting Tech. Digest, pp. 241-244, 1995. 4. Bohr, M. et al., “A high performance 0.25 µm logic technology optimized for 1.8V operation,” Intl. Electron Devices Meeting Tech. Digest, pp. 847-850, 1996. © 2003 by CRC Press LLC

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5. Venkatesan, S. et al., “A high performance 1.8V, 0.20 µm CMOS technology with copper metalli­ zation,” Intl. Electron Devices Meeting Tech. Digest, pp. 769-772, 1997. 6. Mandelbrot, B. B., The Fractal Geometry of Nature, W. H. Freeman, New York, 1983. 7. Pettenpaul, E. et al., “Models of lumped elements on GaAs up to 18 GHz,” IEEE Transactions on Microwave Theory and Techniques, vol. 36, no. 2, pp. 294-304, Feb. 1988. 8. Yue, C. P., Ryu, C., Lau, J., Lee, T. H., and Wong, S. S., “A physical model for planar spiral inductors on silicon,” International Electron Devices Meeting Technical Digest, pp. 155-158, Dec. 1996. 9. Pfost, M., Rein, H.-M., and Holzwarth, T., “Modeling substrate effects in the design of high speed Si-bipolar IC’s,” IEEE J. Solid-State Circuits, vol. 31, no. 10, pp. 1493-1501, Oct. 1996. 10. Ashby, K. B., Koullias, I. A., Finley, W. C., Bastek, J. J., and Moinian, S., “High Q inductors for wireless applications in a complementary silicon bipolar process,” IEEE J. Solid-State Circuits, vol. 31, no. 1, pp. 4-9, Jan. 1996. 11. Chang, J. Y.-C., Abidi, A. A., and Gaitan, M., “Large suspended inductors on silicon and their use in a 2-µm CMOS RF amplifier,” IEEE Electron Device Letters, vol. 14, no. 5, pp. 246-248, May 1993. 12. Greenhouse, H. M., “Design of planar rectangular microelectronic inductors,” IEEE Transactions on Parts, Hybrids, and Packing, vol. PHP-10, no. 2, pp. 101-109, June 1974. 13. Wiemer, L. and Jansen, R. H.,“Determination of coupling capacitance of underpasses, air bridges and crossings in MICs and MMICs,” Electronics Letters, vol. 23, no. 7, pp. 344-346, Mar. 1987. 14. Ho, I. T. and Mullick, S. K., “Analysis of transmission lines on integrated-circuit chips,” IEEE J. Solid-State Circuits, vol. SC-2, no. 4, pp. 201-208, Dec. 1967. 15. Hasegawa, H., Furukawa, M., and Yanai, H., “Properties of microstrip line on Si-SiO2 system,” IEEE Transactions on Microwave Theory and Techniques, vol. MTT-19, no. 11, pp. 869-881, Nov. 1971. 16. Wheeler, H. A., “Simple inductance formulas for radio coils,” Proc. of the IRE, vol. 16, no. 10, pp. 1398-1400, October 1928. 17. Rosa, E. B., “Calculation of the self-inductances of single-layer coils,” Bull. Bureau of Standards, vol. 2, no. 2, pp. 161-187, 1906. 18. Maxwell, J. C., A Treatise on Electricity and Magnetism, 3rd ed., Dover, 1967. 19. Mohan, S. S., “Formulas for planar spiral inductances,” Tech. Rep., IC Laboratory, Stanford Uni­ versity, Aug. 1998, http://www-smirc.stanford.edu. 20. Boyd, S. and Vandenberghe, L., “Introduction to convex optimization with engineering applica­ tions,” Course Notes, 1997, http://www-leland.stanford.edu/class/ee364/. 21. Hershenson, M., Boyd, S. P., and Lee, T. H., “GPCAD: A tool for CMOS op-amp synthesis,” in Digest of Technical Papers, IEEE International Conference on Computer-Aided Design, Nov. 1998. 22. Lee, T. H., The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, Cambridge, 1998. 23. Yue, C. P. et al., “On-chip spiral inductors with patterned ground shields for Si-based RF ICs,” IEEE J. Solid-State Circuits, vol. 33, pp. 743-752, May 1998. 24. Wheeler, H. A., “Simple inductance formulas for radio coils,” Proc. of the IRE, vol. 16, no. 10, pp. 1398-1400, Oct. 1928.

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12 Circuit Elements, Modeling, and Equation Formulation 12.1 Lumped Circuit Approximation 12.2 Circuit Elements and Connecting Multiport 12.3 Characterizations of Circuit Elements

Josef A. Nossek Technical University of Munich, Germany

Formal Methods of Characterization • Resistive Elements • Reactive Elements • Memristive Elements • Dynamic Models

12.4 Connecting Multiport 12.5 Tableau Formulation

12.1 Lumped Circuit Approximation Most texts on circuits, whether they deal with linear or nonlinear circuits, consider only lumped circuits. If this is not the case, such is normally stated explicitly (see, e.g., Section VI on distributed circuits). A physical circuit is considered to be a lumped circuit, if its size is small enough that for the situation under discussion, electromagnetic waves propagate across the circuit virtually instantaneously. If this is satisfied, voltages across ports and currents through terminals are well defined and, therefore, well suited to describe and analyze the behavior of a circuit. To check whether an actual circuit is lumped or not, the largest extension d of the circuit in any spatial dimension is compared to the shortest wavelength λ of interest or with the shortest time interval τ of interest. If d  λ = c f , d  τc

(12.1)

is fullfilled, the circuit is lumped. In (12.1) c is the propagation velocity of electromagnetic waves in the medium under consideration, and f is the frequency corresponding to the wavelength λ as well as to the period τ.

12.2 Circuit Elements and Connecting Multiport It is obvious that a nonlinear circuit is described by a set of nonlinear equations, which, generally speaking, can be solved only approximately. Moreover, we may not find a unique solution, but a set of different solutions. Because of this complicated situation (compared to the simple solution of a linear circuit), it is even more important here to exploit the structure of the equations that reflect the structural properties of the circuit. The most important step in this direction is to partition the circuit into two parts: one

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1

2

3

4

5

i1 + −

v1

vs

i2 R1

v2 i3

D1

v3 i4

D2

v4 i5

R2

v5 i6 − +

v6 i7 R2 D1 3 R1

1 + −

vs

v7

D2 4

2

− +

i8 RL OA

vL

v8

RL

vL

5 CMP (a)

(b)

FIGURE 12.1 (a) A nonlinear circuit conventionally drawn. (b) Partitioning into CMP and circuit elements.

containing all circuits elements separately and one containing the interconnections thereof only. The latter is called the connecting multiport (CMP). This partitioning is demonstrated with a real circuit in Fig. 12.1; it is obvious that this partitioning is completely independent of the nature of the utilized circuit elements: linear or nonlinear, two-terminal or multiterminal, time-variant, time-invariant, passive or active, and so forth. The equations that describe the CMP are merely Kirchhoff ’s current and voltage laws, (KCL, KVL) (see Section 12.4, “Connecting Multiport”), which are, of course, linear, while nonlinearities show up in the description of the circuit elements. First, the circuit element is described, and then some details of the CMP are discussed.

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y F

y0

x0

x

FIGURE 12.2 Plot of the one-port characteristic (Fig. 12.1).

12.3 Characterizations of Circuit Elements This section characterizes a circuit element, two-terminal or multiterminal, with algebraic equations. This necessitates a proper choice of variables. Because of the algebraic nature of this discussion, differential or integral operators cannot be used. Let us begin with a formal discussion, using variables x and y without elaborating on their physical meaning. Later, these methods are applied to specific circuit elements of practical relevance, and voltages, currents, charges, and fluxes are utilized instead of x and y.

Formal Methods of Characterization A relation between variables x and y can be given in an implicit form

{

}

 ⊂ R × R, x ∈ R, y ∈ R  = ( x , y ) f ( x , y ) = 0

(12.2)

Here,  is the characteristic of a two-terminal device which is described by a single implicit equation, f(x, y) = 0. Note that this equation is not unique. Various equivalent forms of f(x, y) = 0, exist which look quite different, but define the same one-port: g ( x, y ) = e f ( x , y ) − 1 = 0 ⇔ f ( x, y ) = 0

(12.3)

The two function f and g are quite different, but the tuples (x, y) defined by them constitute the same set . A simple example for such an implicit description is f ( x , y ) = ( y y 0 ) − arctan( x x 0 ) = 0

(12.4)

the plot of which in the (x, y)-plane is shown in Fig. 12.2. An alternative to the aforementioned implicit form is a parametric description, in which we use an additional parameter λ ∈ R to express the port variables as functions of this parameter: x = f x (λ )

y = f y (λ )

(12.5a)

with every tuple

(x, y ) = ( f x (λ), f y (λ)) ∈

(12.5b)

being an admissible element of . Using (12.4) with λ = y/yo we have x/x0 = tan λ and, therefore, x = f x (λ ) = x 0 tan λ y = f y (λ ) = y 0 λ λ ∈(−π 2, π 2)

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i iL(t0) = 0

i v

iL(t1) = 15 µ A iL(t2) = 30 µ A

10 µ A

v (a)

(b)

FIGURE 12.3 (a) Device symbol of a photodiode. (b) Device i-v characteristic.

Parameterized descriptions are also not unique, but if the parameter is properly chosen (so that fx and fy are continuous and differentiable), they are quite advantageous to work with. The most favorable description in practical applications is explicit, but it exists only if the relation (12.2) is unique in at least one of the variables x or y. If y is a function of x (or vice versa), we write y = f (x ) x = g ( y )

(12.7)

For this example, both explicit versions do exist: y = y 0 arctan( x x 0 ) x = x 0 tan( y y 0 )

y ∈(− y 0 π 2, y 0 π 2)

(12.8)

All these descriptive methods can be extended in a straightforward manner to the multiterminal case by simply replacing the scalars x and y by vectors x and y and the functions f and g by vectors of functions f and g. The formal approach is applied to actual circuit elements in the following section.

Resistive Elements A resistive element is, by definition, uniquely characterized by one of the aforementioned algebraic descriptions, where x and y are replaced by voltage, v, and current, i. This relation may depend on time, t (time-variant circuit element), but not on the history of the variables v and i. Many important circuit elements can be modeled resistively, as far as their main property is concerned. This is true for most semiconductor devices such as diodes, bipolar transistors, field effect transistors, operational amplifiers (op amps), and so forth. This section concentrates on the main effect, leaving a more detailed description, including parasitics, to later sections. An example of a time-variant (nonautonomous) resistive one-port is given in Fig. 12.3

{(

)

( (

) )

}

 (t ) = v (t ), i(t ) i(t ) = I s exp v (t ) VT − 1 − iL (t )

(12.9)

Using a reverse saturation current Is = 10 µA and a thermal voltage VT = 25 mV the individual charac­ teristics in Fig. 12.3(b) are obtained, illustrating the nonautonomous nature of the device with the photocurrent iL as the controlling parameter, which itself depends on the light intensity, which is assumed to be time dependent. An ordinary pn-junction diode is nothing more than a special case of (12.9), i.e., iL = 0. Given the device characteristic in graphical form such as Fig. 12.3(b), which may be the summary of a set of measurements, it is easy to check as to whether explicit descriptions i = g(u) or u = f (i) exist or not. A simple example of a device for which i = g(u) does exist, but g does not have an inverse, is the tunnel diode (Fig. 12.4). © 2003 by CRC Press LLC

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i i v v

(b)

(a)

FIGURE 12.4 (a) Symbol and (b) v-i characteristic of a tunnel diode.

e

ic

ie

c

ie

e

ic

c

i2

i1 ib b

veb

veb

vcb

αF i1

αRi2

vcb

b (b)

(a)

FIGURE 12.5 (a) Symbol and (b) equivalent circuit with two linear CCCSs and two diodes exactly representing Ebers–Moll Eq. (12.10).

Many more nonlinear resistive one-ports or models thereof can be found, but the basic concept is always the same. Therefore, we proceed with an important example of a multiterminal device, the transistor. Again, we have a multitude of various transistors [bipolar npn and pnp, unipolar field-effect insulated gate transistors (MOSFET) and junction type (JFET), n- and p-channel, enhancement and depletion, etc.]. Here, we demonstrate only the basic idea of a resistive two-port (or three-terminal emitter, collector, base) model of a bipolar npn transistor. Many more details are given in Section V. The so-called Ebers–Moll equations describe a bipolar npn transistor:

( = α I (exp( − v

) ( V ) − 1) − I (exp( − v

)

ie = − I es exp( − v eb VT ) − 1 + α R I cs exp( − v cb VT ) − 1 = − i1 + α Ri2 , ic

F es

eb

T

cs

cb

)

VT ) − 1 = α F i1 − i2 ,

(12.10)

which is an explicit two-port description i = f ( v)

(12.11)

with

i=

ie   ic 

v=

v eb   v cb 

using the base b as the common terminal. αF and αR are the forward and reverse current gain of the transistor in common base configuration as shown in Fig. 12.5. As with any device having more than two terminals, the device characteristics cannot be represented simply as a curve in a plane. In general it is a hypersurface in a multidimensional space. Especially in © 2003 by CRC Press LLC

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the case of the three-terminal transistor, it is a two-dimensional surface in four-dimensional space. Because this is not easy to visualize, it is normally split into two three-dimensional representations, which commonly are given as follows: ib = f1 (v be , v ce ) ≈ f1 (v be ) ic = f 2 (v be , v ce ) ≈ f 2′ (v ce , ib )

(12.12)

To obtain (12.12) from (12.10), we must use ib = − ie − ic

v ce = v cb − v eb

v be = − v eb

and ib is almost independent of vce . The first of the two Eqs. (12.12) is already well suited for having a v-i characteristic plotted in a veb-ib-plane. The second equation is normally plotted in the vce-ic-plane, with ib as a parameter. The device characteristics of this bipolar npn transistor, as well as those of many other multiterminal semiconductor devices, are today quite standard; they are given in data sheets and used by designers (discussed further in Section V). These nonlinear models are the basis for deriving linearized small signal models, where they are needed. Finally, we look at a higher level model of a multiterminal i− = 0 i0 = arbitrary − device, and model a complete op amp (containing a multitude i+ = 0 A0 of transistors) using a very simple, but nevertheless very powerful + v− v0 resistive model. An op amp, at a rather high level of abstraction, v+ is a four-terminal device, as depicted in Fig. 12.6. In this figure, everything dealing with power supply, biasing, and offset com­ pensation has been hidden. In this very simple model, we assume FIGURE 12.6 Symbolic representation the input currents to be zero and the output voltage to depend of an op amp. only on the difference of the two input voltages (common mode gain is zero): vd = v + − v −

(12.13)

in the following way Vsat  v o =  A0v d  −V  sat

vd ≥

Vsat A0

vd ≤

Vsat A0

vd ≤

−Vsat A0

(12.14)

Therefore, we have a piecewise linear transfer characteristic, consisting of three pieces (Fig. 12.7). Accord­ ing to the three pieces (I, II, and III) we have three equivalent circuits (Fig. 12.8). Even if we increase our idealization to A0 → ∞, the equivalent circuit in Fig. 12.8(b) reduces from the voltage-controlled voltage source (VCVS) to a nullor. (It is worth emphasizing that this surprisingly simple model of such a complex nonlinear functional unit as an op amp is capable of capturing all of the main effects of such a multitransistor circuit. For many practically important applications, it provides an accurate prediction of the behavior of real circuits.) If we are not satisfied with resistive models because of the bandwidth of signals to be processed, the model must be refined by including elements with memory. First, we need to set up a way to describe memory-possessing elements (see “Reactive Elements”) and then combine this with the resistive model into a dynamic model (see “Dynamic Models”). © 2003 by CRC Press LLC

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v0 +Vsat

III

−Vsat/A0

II

vd Vsat/A0

I

−Vsat

FIGURE 12.7 PWL transfer characteristic of an op amp. − vd +

− +

− vd +

Vsat

+ −

A0

− vd +

vd

(b)

(a)

+ −

Vsat

(c)

FIGURE 12.8 Equivalent circuit for an op amp (a) in the negative saturation region I (vd ≤ –Vsat /A0), (b) in the linear region II (vd ≤ Vsat /A0), and (c) in the positive saturation region III (vd ≥ Vsat /A0).

Reactive Elements To use algebraic description and to plot a characteristic such as a curve in an x-y-plane, we have to extend the set of variables from v and i (resistive case) to charge q and flux φ: q(t ) = q(t 0 ) +

∫ i(τ)dτ φ(t ) = φ(t ) + ∫ v(τ)dτ t

t

0

t0

(12.15)

t0

If the integrals exist for t0 → –∞ and if q(–∞) = 0 and φ(–∞) = 0, we can write q(t ) =

t

t

−∞

−∞

∫ i(τ)dτ φ(t ) = ∫ v(τ)dτ

which simply means to ignore the initial conditions of charge q and flux φ, which are unimportant for the electrical behavior of the component and the circuit. With this in mind, we define a capacitive (inductive) one-port in the following way: C =

{(v, q) f (v, q) = 0} C

{

}

 L = (i, φ) f L (i, φ) = 0

(12.16)

Other than this implicit algebraic description, parameterized or even explicit descriptions may exist, similar to the resistive case dealt with previously. Figure 12.9 gives examples of some nonlinear characteristics of a capacitive and an inductive reactance. It is obvious that this concept can be extended to the multiterminal case by replacing the scalars v and q or i and φ by vectors v and q or i and φ, respectively. This is useful when creating a first-order model of a multiport transformer.

Memristive Elements After having dealt with resistive and reactive elements and considering all the variables and their inter­ relations that we used (Fig. 12.10), an interesting question remains: What about an element with an algebraic characterization in the q-φ-plane? Because this missing element is characterized by an algebraic © 2003 by CRC Press LLC

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FIGURE 12.9 (a) Symbol and (b) characteristic of capacitor with dielectric material and (c) symbol and (d) characteristic of an inductor with ferromagnetic material. fR(v, i) = 0 v

i

fC (v, q) = 0

v=

φ

i=

•

•

q

fL(i, φ) = 0

??

q

φ

FIGURE 12.10 Interrelation between variables.

relation between the integral of current and the integral of voltage, it is a resistive element with memory, and is therefore called a memristor: M =

{(q, φ) f (q, φ) = 0} M

(12.17)

A real-world example of a memristor is the so-called Coulomb cell, which consists of a gold anode immersed in an electrolyte in a silver can cathode. Memristive descriptions, although not widely utilized, are very useful for modeling the behavior of electrochemical elements.

Dynamic Models Only a few examples are illustrated in this section, comprising resistive i and reactive elements, in order to achieve a realistic description of elec­ i′ i″ tronic devices, including dynamical effects. A pn-junction was described resistively earlier in the chapter, with an v exponential v-i characteristic, neglecting dynamical effects. To remove this shortcoming, we use the more elaborate dynamic model depicted in Fig. 12.11, which consist of a resistive pn-junction in parallel with a non­ linear capacitor. This extension can, of course, be carried on for the (multiterminal) transistor case, where we use dynamic diode models FIGURE 12.11 Dynamic pn(Fig. 12.12). junction model. The combination of the resistive and reactive models in one circuit leads to a description that makes use of differential and integral operators. It is almost always possible to reduce this to a set of nonlinear ordinary differential and algebraic equations. We return to this point later, but first we conclude this section with a dynamic model of an © 2003 by CRC Press LLC

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ic

ie i1

e

i2

Cbe

c

Cbc

α Ri2

α F i1 ib b

FIGURE 12.12 Dynamic transistor model.

−

i = gm (vd)

vd R

+

C

vc

+ −

v0 = µ (vc)

FIGURE 12.13 Dynamic op amp model.

i = gm (vd ) i0

gm0 vd

− i 0 /gm0

i 0 /gm0

− i0

FIGURE 12.14 Nonlinear VCCS in the input stage of the op amp.

op amp (Fig. 12.13), making use of nonlinear controlled sources (VCVS) and voltage-controlled circuit sources (VCCS). This simple model accounts for the following important practical properties of a realworld op amp: • First-order, low-pass behavior in the linear region of the controlled sources • Slew rate limitation is incorporated by the nonlinearity of gm(vd ) of the VCCS (Fig. 12.14) • Output voltage saturation is modeled with the aid of the nonlinearity of µ(vc) (Fig. 12.15) The 3-dB bandwidth of this op amp is given by ω3dB = 1/(RC) with a 20 dB/decade roll-off. The slew rate is given by SR = i0/C, while the DC open-loop gain A0 = gm0 Rµ0. Using this simple model, not all, but some, of the most important nonlinear dynamical effects are properly described. © 2003 by CRC Press LLC

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v0 = µ(vc) VSat

µ0 vc

− VSat /µ0

VSat /µ0

− VSat

FIGURE 12.15 Nonlinear VCVS in the output stage of the op amp.

12.4 Connecting Multiport After having dealt with the description of the circuit elements, we return to the interconnection structure, which is summarized in the CMP [see Fig. 12.1(b)]. This multiport is linear, lossless, and reciprocal and its description stated in implicit form is simply KCL and KVL equations B   0

0 v 0 0 B   =  v +  i =  ⇒ Bv = 0 and Ai = 0  0  A  i  A  0

(12.18)

From (12.18), the linearity is obvious, while the losslessness and reciprocity can be proven easily by making use of BA T = 0 AB T = 0 rank A + rank B = b

(12.19)

(b is the number of ports of the CMP). In addition to the perfect wires, which are the ingredients of CMP, ideal transformers (which are also linear, lossless, and reciprocal) can be accommodated in the CMP without changing the structure of (12.18) and (12.19). A is an (n – 1) × b incidence matrix containing the coefficients of any (n – 1) linearly independent nodal equations (or supernodal or cutset equations), while B is a (b – (n – 1)) × b incidence matrix, the entries of which are the coefficients of any (b – (n – 1)) linearly independent loop equations (or fundamental-loop equations).

12.5 Tableau Formulation Combining the description of the CMP and the description of all circuit elements into one tableau, all information about the circuit under consideration is at our fingertips: B   0

0  v 0   = , A  i  0

(

)

b linear algebraic equations

f v˙ , v, i˙, i, t = 0, b nonlinear differential equations

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(12.20)

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Circuit Elements, Modeling, and Equation Formulation

385

This set of equations is not unique, although their solution is unique for properly modeled circuits. · Instead of using derivatives v = dv/dt, i = di/dt, we could have used integrals, or we could have formulated · · the equations with q, φ, q, φ as variables. It is important to note that at least half of the equations are linear. To solve the nonlinear equations numerical techniques are commonly used, however, this is beyond the scope of this chapter.

References [1] L. O. Chua, C. A. Desoer, and E. S. Kuh, Linear and Nonlinear Circuits, New York: McGraw-Hill, 1987. [2] J. E. Solomon, “The monolithic opamp: a tutorial study,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 314–332, Dec. 1974. [3] W. Mathis, Theorie Nichtlinearer Netzwerke, Berlin: Springer-Verlag, 1987. [4] R. K. Brayton, L. O. Chua, J. D. Rhodes, and R. Spence, Modern Network Theory  An Introduction, Saphorin, Switzerland: Georgi Publishing, 1978.

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13 Controlled Circuit Elements 13.1 Controlled Sources Introduction • Voltage-Controlled Current Source • VoltageControlled Voltage Source • Current-Controlled Voltage Source • Current-Controlled Current Source

Edwin W. Greeneich Arizona State University

James F. Delansky

13.2 Signal Converters

Pennsylvania State University

Gyrator • Voltage Negative Impedance Converter • Current Negative Impedance Converter • Circulator

13.1 Controlled Sources Edwin W. Greeneich Introduction Controlled sources generate a voltage or current whose value depends on, or is controlled by, a voltage or current that exists at some other point in the circuit. Four such sources exist: (1) Voltage Controlled Current Source (VCCS), (2) Voltage Controlled Voltage Source (VCVS), (3) Current Controlled Current Source (CCCS), and (4) Current Controlled Voltage Source (CCVS). In an ideal controlled source, the generated voltage or current does not vary with the load to which it is connected; this implies a zero output impedance for a voltage source and an infinite output impedance for a current source. In practice, actual controlled sources have finite output impedance, which causes the generated source to vary somewhat with the load. Circuit representations of the four ideal controlled sources are given in Fig. 13.1. The input terminals on the left represent the controlling voltage or current, and the output terminals on the right represent the controlled voltage or current; the value of the controlled source is proportional to the controlling input through the constants g, µ, β, and r.

Voltage-Controlled Current Source A voltage-controlled current source produces an output current that is proportional to an input control voltage. The idealized small-signal low-frequency behavior of a field-effect transistor (FET) can be characterized by a VCCS, as illustrated in the equivalent circuit for an n-channel metal-oxide-semicon­ ductor field-effect transistor (MOSFET) in Fig. 13.2. In the circuit model, the small-signal drain current id of the transistor is proportional to the small-signal gate-to-source voltage vgs through the transcon­ ductance parameter gm . SPICE Format The format for a voltage-controlled current source in the circuit simulation program SPICE [Nagel, 1975] is illustrated in Fig. 13.3. In the data statement, GXXX represents the source name containing up to eight

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+

+

vx

vx

i = gv x

-

+ -

v = µv x

(b) VCVS

(a) VCCS

ix

+ -

ix

i = ßi x

(c) CCCS

v = ri x

(d) CCVS

FIGURE 13.1 Circuit representations of ideal controlled sources.

drain

id g

d + vgs

gate

source

s

-

g mv gs s

FIGURE 13.2 Small-signal equivalent circuit of a MOSFET.

FIGURE 13.3 SPICE format for a voltage-controlled current source.

3

5

4

+ Vx

-

2

6

GS1

7

3.4Vx 8

FIGURE 13.4 Example showing a portion of a circuit using a VCCS.

alphanumeric characters (the first character G signifying a VCCS), N+ and N– are the positive and negative nodes of the source, NC+ and NC– are the positive and negative nodes between which the controlling voltage is measured, and VALUE is the multiplicative constant giving the value of the current source. The convention used is that positive current flows from the N+ node through the source to the N– node. Figure 13.4 is an example of a circuit using a voltage-controlled current source. The SPICE data specification for the source is: GS1 8 6 3 6 3.4

© 2003 by CRC Press LLC

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Controlled Circuit Elements

389

R1 R1 Op-Amp

+ + Vx -

R1

R1 RL

Io =

Vx R1

= g Vx

FIGURE 13.5 Op-Amp implementation of a voltagecontrolled current source.

�� �

��

�� ��

� �

��

��

�� � � �� � ��� ��

�� ��

��

�� ��

FIGURE 13.6 Circuit that implements a voltage­ controlled current source.

Circuit Implementation A circuit implementing a voltage-controlled current source using an Operational Amplifier (Op-Amp) is depicted in Fig. 13.5. Assuming the Op-Amp to be ideal, it is easy to show that Io = gVx , where g = 1/R1, as indicated in the figure. An alternate form of the VCCS circuit that uses fewer components is illustrated in Fig. 13.6. In the circuit, Q1 and Q2 form a current mirror which, due to their equal base-emitter voltages, have the same collector currents, which are reflected in the collector currents of Q3 and Q4, causing them to have the same base-emitter voltages; the voltage at the emitter of Q4 is thus equal to the input control voltage Vx. The emitter current of Q4 is thus equal to Vx /R1, which is then (neglecting base currents) equal to the collector current of Q2. This current is mirrored by Q5 giving the voltage-controlled output current Io . This circuit derives from a general form of this configuration called a current conveyor [Ioumazou, Lidgey, and Haigh, 1990]. With this circuit (and as with all practical current sources), the output current is not totally independent of the output voltage across the source, but instead, Io shows a slight increase with increasing voltage. This is due to the finite output resistance of the source; in the circuit of Fig. 13.6, this resistance is equal to the collector-to-emitter resistance of transistor Q5. For an integrated circuit transistor, this resistance may be of the order of 50 kΩ or so.

Voltage-Controlled Voltage Source A voltage-controlled voltage source produces an output voltage that is proportional to an input control voltage. A voltage amplifier can be thought of as a VCVS; the output voltage is equal to the input voltage multiplied by the voltage gain, µ, of the amplifier. SPICE Format The SPICE format for a voltage-controlled voltage source is given in Fig. 13.7. The first character E in the source name signifies a VCVS. The output voltage of the source is given by the product of the VALUE constant and the control voltage Vx . © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 390 Thursday, September 19, 2002 10:55 AM

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���� �� �� ��� ��� ����� �

��

���

� �

�� �

���

�������� ��

FIGURE 13.7 SPICE format for a voltage-controlled voltage source.

Circuit Implementation Figure 13.8 is an implementation of the voltage-controlled voltage source using an Op-Amp. Here Vo = µVx where µ = 1 + R2 /R1. The VCCS circuit of Fig. 13.6 can be modified to produce a voltage-controlled voltage source. In Fig. 13.9, current sensing resistor R2 develops a voltage drop equal to Vx R2/R1, which is buffered by a unity-gain stage to reduce loading effects on R2. The output voltage Vo is thus proportional to the input control voltage Vx . The buffer should have a low output impedance to minimize variations in the output voltage, Vo , with load current drawn by the source.

Current-Controlled Voltage Source A current-controlled voltage source produces an output voltage that is proportional to an input control current. In this context, a CCVS may be thought of as a current-to-voltage transducer; the output voltage is equal to the input voltage multiplied by the transresistance, r, of the transducer. SPICE Format The SPICE format for a CCVS is given in Fig. 13.10. The first character H in the source name signifies a CCVS. There are no ammeters in SPICE, so currents are measured through voltage sources. VNAME R2 R1 Vo =

+

(1 +

+

R2 R1

)

Vx -

FIGURE 13.8 Circuit implementation of a voltage-controlled voltage source using an Op-Amp. VC C

Q1

Q2

Q3 Vx

+ -

Vx R1

Q 4 R 2 Vx R1 Vx R1

Q5 Vx R1 X1

R2

Vo =

unity-gain buffer

FIGURE 13.9 Circuit that implements a voltage-controlled voltage source. © 2003 by CRC Press LLC

R2 V = µVx R1 x

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391

Controlled Circuit Elements

HXXX N+ N- VNAME VALUE

N+ +

Ix

+ -

Vx -

VALUE*I x N­

FIGURE 13.10 SPICE format for a current-controlled voltage source.

Ix 3

VTEST +

4

7

6

HVS2

+ -

0.2I x

5

2

FIGURE 13.11 Example showing a portion of a circuit using a CCVS.

R2 R1 Op-Amp

+ IX

Vo = ( R 1 + R 2 ) I X = r I X

R1

FIGURE 13.12 An Op-Amp implementation of a current-controlled voltage source.

is the voltage source through which the control current Ix is measured. The output voltage of the source is given by the product of VALUE and Ix. If the point in the circuit at which the control current is to be measured does not contain a voltage source, a test voltage source of zero value can be inserted in the circuit. Figure 13.11 is an example of a circuit using a CCVS. The data statement for the source is: HVS2 3 2 VTEST 0.2 VTEST is a zero-valued voltage source inserted into the circuit to measure the control current Ix. Its data statement is: VTEST 6 7 0 Circuit Implementation An Op-Amp implementation of a current-controlled voltage source is given in Fig. 13.12. Here, Vo = rIx where r = R1+R2 . A simple circuit implementing a CCVS is shown in Fig. 13.13. In the current mirror comprising transistors Q1 and Q2 , the collector current of Q2 is equal (neglecting base currents) to the control current Ix. The voltage across R1 is then equal to R1Ix , which after the buffer, is the current-controlled output voltage.

Current-Controlled Current Source A current-controlled current source produces an output current that is proportional to the input control current. The idealized large-signal (and small-signal as well) low-frequency behavior of a bipolar tran­ sistor can be characterized by a CCCS, as illustrated in the equivalent circuit for an NPN transistor in © 2003 by CRC Press LLC

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VC C

Q1

Q2 Ix Vo = R1I x = r I x

X1

Ix

R1

unity-gain buffer

FIGURE 13.13 Circuit that implements a current-controlled voltage source.

IB

collector

I

C

= ßF IB

B

C ßF IB

base

emitter E

FIGURE 13.14 Large-signal equivalent circuit of a bipolar transistor.

���� �� �� ����� ����� ��

��

�

������� �

�� �

��

FIGURE 13.15 SPICE format for a current-controlled current source.

Fig. 13.14. In the circuit model, the collector current IC is proportional to the base current IB through the current gain parameter βF . SPICE Format The SPICE format for a current-controlled current source is given in Fig. 13.15. The first character F in the source name signifies a CCCS. The output current is given by the product of the VALUE constant and the control current Ix . As with the CCVS, the controlling current is measured through an independent voltage source. Circuit Implementation Figure 13.16 is an Op-Amp implementation of a current-controlled current source. Here, Io = βIx where β = 1 + R2 /R1. R2 R1 Op-Amp

+ IX

R1 R1

Io =

(1+

R2 R1

) IX

= ßIX

FIGURE 13.16 Op-Amp implementation of a current-controlled current source. © 2003 by CRC Press LLC

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393

Controlled Circuit Elements

VC C

Q1

Q5

Q2

Q7

Q6

Io =

Ix

Q3

Q4

R1 I = ßI x R2 x

X1

Ix

R1I x

R1

R2

buffer

R1 I R2 x

FIGURE 13.17 Circuit that implements a current-controlled current source.

The CCVS circuit in Fig. 13.13 can be combined with the VCCS circuit in Fig. 13.6 to produce a CCCS, as illustrated in Fig. 13.17. The output voltage of the CCVS stage is equal to R1Ix, which, applied at the emitter of Q3 , is the input voltage of the VCCS stage; the output current is equal to (R1 /R2)Ix , and thus proportional to the input control current.

References Nagel, L.W., 1975. “SPICE2: A computer program to simulate semiconductor circuits,” Electronics Research Laboratory Report No. ERL-M520, University of California, Berkeley. Ioumazou, C., Lidgey, F.J., and Haigh, D.G., eds., 1990. Analogue IC Design: The Current-Mode Approach, London: Peter Peregrinus Ltd.

13.2 Signal Converters James F. Delansky An accessible terminal pair of a network, regarded as a single entity to which an independent 2-terminal signal generator (source or input) is to be connected, is called a port of the network. An equivalent view of a port of a network is an accessible terminal pair such that the current entering one of the terminals of the pair is the same current leaving the other terminal of the pair. Thus, an accessible terminal pair of a network is a port when this terminal pair is terminated by (connected to) a 1-port network. For a given port of a network, the port voltage (the voltage drop between the two terminals) and the port current (the current entering one of the terminals) are to be associated as follows: the positive sign for the voltage (drop) is always assumed at the terminal at which the current (positive charges) enters the network. A 1-port, 2-port and general n-port are illustrated in Fig. 13.18. − v2 + 2′

2 i2

+

1

i1

+

v1

v1

−

− 1′

1

i1

i2 2

+

v2 − 1′

2′

+ v1 −

1

1′

i1

in n

(a)

(b)

FIGURE 13.18 (a) A 1-port. (b) A 2-port. (c) An n-port. © 2003 by CRC Press LLC

+ vn − (c)

n′

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In linear network theory, a class of n-ports (particularly n = 2), known as signal converters, has become salient as crucial building blocks. These 2-port signal converters include the various versions of the “transformer,” “controlled source,” and “operational amplifier” found elsewhere in Section II. This part of Chapter 13 will introduce the 2-port signal converters known as the “gyrator” and “negative impedance converter.” As extensions of these, the (n ≥ 2)-port “circulator” is developed and, as special cases, the 1-ports known as “nullator” and “norator” (properly viewed as degenerate cases) and the 2-port known as “nullor” are given. One of the most general external descriptions of a linear n-port network is the “scattering” matrix. In many cases, a linear n-port network may be externally described by one or more of the “open-circuit impedance,” “short-circuit admittance,” “hybrid,” “inverse hybrid,” “chain (transmission),” or “inverse chain (inverse transmission)” matrix. For details of these n-port descriptions, see [1]. As necessary or convenient, any of the above n-port descriptions will be utilized in this part of Chapter 13.

Gyrator The concept of reciprocity satisfied by a linear n-port network (n = 2, in particular) will be useful in the present context. Definition: A linear n-port network is said to be a reciprocal linear n-port network if the port voltages and currents satisfy n

∑ [v ( )i( ) − v ( )i( ) ] = 0 1 2 k k

2

k

1 k

(13.1)

k =1

where vk(1), ik(1) and vk(2), ik(2) are any two distinct sets of port voltages and currents that satisfy Kirchhoff ’s laws for the linear n-port. If (13.1) is not satisfied, the linear n-port is said to be nonreciprocal. [Note: for many useful linear n-port networks, (13.1) can be derived from Tellegen’s theorem in Chapter 7]. The idea of isolating the nonreciprocity of a linear passive n-port in a single network building block was first advanced by Tellegen [2]. The linear passive 2-port developed there, christened the gyrator, was shown to be necessary and sufficient for this purpose. This (ideal) 2-port gyrator is described by the skew-symmetric open-circuit impedance matrix z11 Z =  z 21

z12  0  =  z 22  r

−r  0 

(13.2)

where r (the gyrator transfer impedance parameter) is a real positive number, and is depicted in Fig. 13.19. It can be observed that v1 = –ri2 and v2 = ri1 (so the signal conversion is clear), and by multiplying these together to obtain rv1i1 = –rv2 i2 or v1i1 + v2 i2 = 0, then no energy is generated, dissipated, or stored. Thus, the ideal gyrator is a lossless passive nonreciprocal 2-port. Also easily shown is that, if port 2 is terminated with the 1-port (driving-point) impedance Z, then the driving-point impedance seen at port 1 is Z11 = –z12 z21/Z = r2/Z so that the ideal 2-port gyrator is also an ideal impedance invertor. This leads +

1

i1

r

i2

2

v1

v2

−

− 1′

FIGURE 13.19 The ideal 2-port gyrator. © 2003 by CRC Press LLC

+

2′

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395

Controlled Circuit Elements

− I1

Z1

Z2

+

Z3

Z4

+

+

V1

−

Z5

−

FIGURE 13.20 Antoniou’s circuit.

to another attribute of the ideal 2-port gyrator as a fundamental building block for the synthesis of linear networks. If Z in the above is the impedance of an ideal capacitor C, i.e., Z = 1/sC, then Z11′ =

r2 = r 2sC = L11′ s Z

(13.3)

which means that the driving-point impedance Z11′ is exactly equivalent to the impedance of an ideal inductor L11′ = r 2 C. This opens a viable avenue to the inductorless synthesis of linear passive RLC networks. The ideal 2-port gyrator is a 4-terminal passive network (device or element). For network (and physical realization) purposes, however, it is usually implemented with active elements (and thus considered as an “active” building block) and results in a 3-terminal or “common ground” 2-port. For this reason, the simulation of a nongrounded (“floating”) inductor in a network is not straightforward. The active realization of the ideal gyrator also results in a nonideal gyrator (i.e., in general z11 ≠ 0, z22 ≠ 0, z12 ≠ –z21). These concerns are treated elsewhere [3]. A circuit using two operational amplifiers and R’s and a single capacitor for inductor simulation (and thus a gyrator simulation) was proposed by Antoniou [4]. This circuit has subsequently become very widely used. Assuming ideal operational amplifiers and general RC 1-ports, this circuit is illustrated in Fig. 13.20. Analysis yields Z11 =

ZZ  V1 =  1 3  Z5 I1  Z2Z4 

(13.4)

For (13.4) to appear as (13.3), two choices exist because either Z2 and Z4 must be the impedance of the capacitor. The simplest choices then are A.

Z1 = R1 ,

Z2 =

1 , C 2s

Z 3 = R3 ,

RR R  Z11 =  1 3 5  C 2s = L11s  R4  © 2003 by CRC Press LLC

Z 4 = R4 ,

Z 5 = R5

results in

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B.

The Circuits and Filters Handbook, Second Edition

Z1 = R1 ,

Z 2 = R2 ,

Z 3 = R3 ,

Z4 =

1 , C 4s

Z 5 = R5

results in

RR R  Z11 =  1 3 5  C 4s = L11s  R2  These are known at type-A and type-B simulations, respectively. Assume the capacitor in A and B above is removed (pliers-type entry) from Fig. 13.20, thus forming a 2-port. With the proper choice of num­ bering port 2 terminals, the resulting 2-port is a 4-terminal ideal gyrator. On the other hand, forming the second port by removing Z5 from Fig. 13.20, and the obvious choice of numbering port 2 terminals, results in a grounded 2-port impedance converter with ZZ  Z11 =  1 3  Z 5 = K (s ) Z 5  Z2Z4 

(13.5)

This is Antoniou’s generalized impedance convertor (GIC). The rational function K(s) in Eq. (13.5) can, in general, be any function subject to Z1, Z2, Z3, and Z4 being driving-point impedances of RC 1-port networks. So if the GIC of Eq. (13.5) has Z1 = 1/C1s, Z2 = R2, Z3 = R3, but Z4 = R4 and Z5 = 1/C5s, then Z11 (s ) =

R3 1 = C1C5 R2 R4s 2 Ds 2

(13.6)

−1 = R11 ω 2 Dω 2

(13.7)

so that for sinusoidal excitations (s = jω) Z11 ( jω ) =

( )

Thus, Z11 of (13.7) is a frequency-dependent negative resistance (FDNR). Alternate realizations of FDNR are possible. The FDNR element plays an important role in the design of active RC networks.

Voltage Negative Impedance Converter Suppose a 2-port signal converter such that, with one of its ports terminated with an impedance, the driving-point impedance at the other port is proportional to the negative of the terminating impedance. Such a 2-port is known as a negative impedance converter (NIC) [5]. For a general 2-port terminated at port 2 with the impedance Z = 1/Y, the driving-point impedance seen at port 1 is, in terms of the hybrid parameters of the 2-port, Z11 =

h11 − h12h21 h22 + Y

(13.8)

Hence, necessary and sufficient conditions for a 2-port to be an NIC is that h11 = 0, h22 = 0, and h12 h21 > 0, so (13.8) becomes Z11 = − h12h21 Z = − kZ

(13.9)

where k > 0 is called the negative impedance parameter. Now h12 h21 > 0 holds in two cases for h12 and h21 real: A.

h12 < 0 and

h21 < 0

(13.10)

B.

h12 > 0 and

h21 > 0

(13.11)

© 2003 by CRC Press LLC

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397

Controlled Circuit Elements

1

2 − Nb

Na

1′

2′

FIGURE 13.21 Cascade of 2-ports designated Na and –Nb.

1

2

Na

NIC k=1

1′

Nb 2′

FIGURE 13.22 Equivalent to Fig. 13.21.

Consider an NIC satisfying (13.10). From the hybrid description, this 2-port signal converter has v1 = h12v2 and since h12 < 0 this implies a voltage reversal between the ports, while i2 = h21i1 and because h21 < 0 this implies the current direction remains the same. For this reason, (13.10) defines a voltage inversion negative impedance converter (VNIC).

Current Negative Impedance Converter Consider an NIC satisfying (13.11). From the hybrid description, this 2-port signal converter has v1 = h12v2 and since h12 > 0, this implies no voltage reversal between the ports, while i2 = h21i1 and because h21 > 0 this implies the current directions have reversed. For this reason, (13.11) defines the current inversion negative impedance converter (INIC). As with the gyrator, for network (and physical realization) purposes, the NIC is implemented with active devices but for a more fundamental reason. Consider k in (13.9) to be 1 with h12 = h21 to be either both 1 or –1. Then for VNIC or INIC this implies v1i1 – v2 i2 = 0 so the NIC is inherently active. Any physical realization of the NIC will result in a nonideal NIC (i.e., in general h11 ≠ 0, h22 ≠ 0, h12h21 ≠ 1). These concerns are treated elsewhere, e.g., [3]. An obvious use of an NIC in active network synthesis is to obtain negative elements, i.e., negative resistor or inductor or capacitor from positive resistor or inductor or capacitor, respectively. Another way an NIC is used in active network synthesis is the partitioning of a network using an NIC. Consider two cascaded 2-ports as shown in Fig. 13.21 to form an overall 2-port. Suppose in Fig. 13.21, Na is a 2-port with all positive elements and –Nb is a 2-port with all negative elements. Then it can be shown that the overall 2-port shown in Fig. 13.22 with an NIC of k = 1, and with Nb being the same as –Nb in Fig. 13.21, except it is now composed of all positive elements, is equivalent to the overall 2-port shown in Fig. 13.21. These and other methods of using NIC’s in active RC synthesis may be found elsewhere, e.g., [3].

Circulator As discussed in the section on the gyrator, the gyrator is the basic representation of nonreciprocity in linear networks. It is quite natural to believe this property can also be exploited to derive a means of controlling the power flow in n-port (n ≥ 2) linear networks from the input port to the remaining ports in a prescribed manner. This is indeed the situation and the most important of such n-ports are known as circulators. © 2003 by CRC Press LLC

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r01

I1

I2

+

+

a1

a2

Vg1

V1

b1

b2 V2

−

−

+

−

r02 + Vg2 −

FIGURE 13.23 General terminated 2-port network.

Circulators are best described in terms of the scattering matrix, since this makes their function very clear. A brief discussion of the scattering description for a 2-port network (extended in a natural way for n-port (n > 2) networks) follows. See [6]. Consider the terminated 2-port in Fig. 13.23. Assume r01 > 0 and r02 > 0. Define incident and reflected power waves a = [a1 a2]′ and b = [b1 b2]′, respectively, where the prime denotes matrix transpose, as a = (1 2)R0−1 2 (V + R0 I )

(13.12)

b = (1 2)R0−1 2 (V − R0 I )

(13.13)

where R0 = diag (r01, r02), V = [V1 V2]′ and I = [I1 I2]′. Assume that V = ZI for the 2-port and because Eqs. (13.12) and (13.13) are also linear relations between V and I, then a and b are also linearly related as b = Sa

(13.14)

where S is the scattering matrix with respect to R0. For the 2-port network in Fig. 13.23, (13.14) is explicitly b1 = S11a1 + S12a2 b2 = S21a1 + S22a2

(13.15)

Hence, the scattering parameters are determined as S jj =

bj

,

for ak = 0 and k ≠ j

(13.16)

bk , aj

for ak = 0 and k ≠ j

(13.17)

aj

and Skj =

The parameter Sjj is called the reflection coefficient at the jth port and Skj is called the transmission coefficient from port j to port k. The conditions in (13.16) and (13.17), together with (13.12) and (13.13), imply. S jj =

(Z (Z

) )

(13.18)

Ik Vg j

(13.19)

jj

− r0 j

jj

+ r0 j

and Skj = − 2 rojrok

© 2003 by CRC Press LLC

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399

Controlled Circuit Elements

1Ω

1

1

2

1′

2′

FIGURE 13.24 A 2-port circulator.

2

1

3

r

FIGURE 13.25 Matched 3-port circulator.

The network is said to be matched at port j if Sjj = 0, or from (13.18) r0j = Zjj. Also from (13.19) and Skj 2 = bk 2/aj 2, it is clear that Skj 2 is the power gain of the terminated n-port from the source at port j to the load resistor r0k at port k. For an example, consider the ideal 2-port gyrator with gyration transfer parameter r > 0 and r01 = r02 = r. Here,  S11 S= S21

S12  0 = S22  0

−1  1

(13.20)

The simplest type of circulator is the 2-port circulator. Consider the 2-port in Fig.13.24, which has (for r01 = r02 = 1).  S11 S= S21

S12  0 =  S22  1

0  0

(13.21)

This 2-port circulator has unity power transmission from port 1 to port 2, but zero power transmission from port 2 to port 1, and is also called an isolator or one-way line. Now a 3-port circulator may be defined by the scattering matrix S11  S = S21  S31 

S12 S22 S32

S13  0   S23  = S21   S33  0

0 0 S32

S13   0   0 

(13.22)

with each nonzero Skj = ±1, so it has unity power transfer from port 1 to 2, 2 to 3, and 3 to 1. This 3-port circulator is usually depicted as shown in Fig. 13.25, where the + and – terminals of each port depend on the selection of each nonzero Skj in (13.22). Likewise, a 4-port circulator may be defined by the scattering matrix © 2003 by CRC Press LLC

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S11  S21 S= S31  S  41

S12

S13

S22

S23

S32

S33

S42

S43

S14  0   S24  S21 =  S34  0   S44  0

0

0

0

0

S32

0

0

S43

S14   0   0   0 

(13.23)

with each nonzero Skj = ±1, and depicted as suggested in Fig. 13.25. Similarly, the n-port (n > 4) circulator may be defined and depicted as suggested in Fig. 13.25. See [6] for details. Nullator It is fact that every linear passive n-port network has a scattering description. However, to complete the description of general linear n-port networks (which may not have a scattering description), a few “pathological” or “degenerate” 1- and 2-ports must be included [7]. The first of these is the 1-port linear network denoted as the “nullator.” For the exact configuration obtained by terminating Fig. 13.25 (with normalization parameters equal to unity) at port 2 with –1Ω and at port 3 with +1Ω, the driving-point relations seen at port 1 are V1 = I1 = 0

(13.24)

so the resulting 1-port is at once a short and open circuit! This linear 1-port has been designated as the nullator. The circuit symbol for the nullator is depicted in Fig. 13.26. Norator Another degenerate 1-port can be obtained from the exact configuration obtained by terminating Fig. 13.25 (with unity normalization parameters) at port 2 with +1Ω and at port 3 with –1Ω. The resulting driving-point relations seen at port 1 are that V1 and I1 are completely independent

(13.25)

This (nonreciprocal) linear 1-port has been designated as the norator. The circuit symbol for the norator is shown in Fig. 13.27. Nullor The final building block for the most general n-port linear network is the 2-port designated as the nullor. It is defined as a 2-port which, at port 1, demands V1 = I1 = 0 while simultaneously at port 2, V2 and I2 I1

+ V1 −

+

FIGURE 13.26 The nullator (V1 = I1 = 0).

I1

V1 −

© 2003 by CRC Press LLC

FIGURE 13.27 The norator (V1 and I1 are arbitrary).

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+

I1

V1 −

I2

+ V2 −

FIGURE 13.28 The nullor (V1 = I1 = 0, V2, and I2 arbitrary).

are arbitrary! These relations can be obtained from a 4-port circulator with two of its ports appropriately terminated with negative and positive resistors. The symbol for the nullor is given in Fig. 13.28. Both 4 and 3 terminal equivalent circuits exist for the nullor. These singular network elements, the nullator, the norator, and the nullor, have been used to generate realizable circuits for the various signal converters discussed in this section. They have also been used to obtain realizable circuits for other widely used circuit elements such as the family of controlled sources, op amps, transistors, etc. See [3] and [7] for the applications mentioned above. Of course, many references are possible for the use of the network elements discussed in this section. Among others, [8] and [9] contain extensive bibliographies.

Defining Terms Reciprocal linear n-port: The port voltages and currents satisfy (13.1) and its restrictions.

Ideal gyrator: The basic nonreciprocal 2-port satisfying (13.2).

Generalized impedance converter (GIC): A 2-port that satisfies (13.5) and its conditions.

Frequency dependent negative resistor (FDNR): A 1-port that has the driving-point impedance of

(13.7). Voltage negative impedance converter (VNIC): A 2-port satisfying (13.10) and foregoing conditions. Current negative impedance converter (INIC): A 2-port satisfying (13.11) and foregoing conditions. The n-port (n ≥ 3) circulator: Described by it n-port scattering matrix with main-diagonal element zero and off-diagonal elements restricted to only one per row or column of unity magnitude. Nullator: A 1-port such that V1 = I1 = 0. Norator: A 1-port such that V1 and I1 and arbitrary. Nullor: A 2-port such that V1 = I1 = 0, while V2 and I2 are arbitrary.

References [1] R. W. Newcomb, Linear Multiport Synthesis, New York: McGraw-Hill, 1966. [2] B. D. H. Tellegen, “The gyrator, a new electric network element,” Phillips Res. Rep., vol. 3, pp. 81–101, 1948. [3] S. K. Mitra, Analysis and Synthesis of Linear Active Networks, New York: John Wiley & Sons, 1969. [4] A. Antoniou, “Realization of gyrators using operational amplifiers and their use in RC-active network synthesis,” Proc. IEE, vol. 116, pp. 1838–1850, 1969. [5] J. L. Merill Jr., “Theory of the negative impedance converter,” Bell System Tech. J., vol. 30, pp. 88–109, 1951. [6] H. J. Carlin and A. B. Giordano, Network Theory, Englewood Cliffs, NJ: Prentice Hall, 1964. [7] H. J. Carlin, “Singluar network elements,” IEEE Trans. Circuit Theory, vol. CT-11, pp. 67–72, 1964. [8] S. K. Mitra, Active Inductorless Filters, New York: IEEE, 1971. [9] M. Herpy and J.-C. Berka, Active RC Filter Design, New York: Elsevier Science, 1986.

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14 Bipolar Junction Transistor (BJT) Circuits 14.1 14.2 14.3 14.4 14.5

Introduction Physical Characteristics and Properties of the BJT Basic Operation of the BJT Use of the BJT as an Amplifier Representing the Major BJT Effects by an Electronic Model 14.6 Other Physical Effects in the BJT Ohmic Effects • Base-Width Modulation (Early Effect) • Reactive Effects

14.7 More Accurate BJT Models 14.8 Heterojunction Bipolar Junction Transistors 14.9 Integrated Circuit Biasing Using Current Mirrors Current Source Operating Voltage Range • Current Mirror Analysis • Current Mirror with Reduced Error • The Wilson Current Mirror

David J. Comer Brigham Young University

Donald T. Comer Brigham Young University

14.10 The Basic BJT Switch 14.11 High-Speed BJT Switching Overall Transient Response

14.12 Simple Logic Gates 14.13 Emitter-Coupled Logic A Closer Look at the Differential Stage

14.1 Introduction The bipolar junction transistor (or BJT) was the workhorse of the electronics industry from the 1950s through the 1990s. This device was responsible for enabling the computer age as well as the modern era of communications. Although early systems that demonstrated the feasibility of electronic computers used the vacuum tube, the element was too unreliable for dependable, long-lasting computers. The invention of the BJT in 19471 and the rapid improvement in this device led to the development of highly reliable electronic computers and modern communication systems. Integrated circuits, based on the BJT, became commercially available in the mid-1960s and further improved the dependability of the computer and other electronic systems while reducing the size and cost of the overall system. Ultimately, the microprocessor chip was developed in the early 1970s and the age of small, capable, personal computers was ushered in. While the metal-oxide-semiconductor (or MOS) device is now more prominent than the BJT in the personal computer arena, the BJT is still important in larger high-speed computers. This device also continues to be important in communication systems and power control systems.

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Because of the continued improvement in BJT performance and the development of the hetero­ junction BJT, this device remains very important in the electronics field, even as the MOS device becomes more significant.

14.2 Physical Characteristics and Properties of the BJT Although present BJT technology is used to make both discrete component devices as well as integrated circuit chips, the basic construction techniques are similar in both cases, with primary differences arising in size and packaging. The following description is provided for the BJT con­ structed as integrated circuit devices on a silicon substrate. These devices are referred to as “junction­ isolated” devices. The cross-sectional view of a BJT is shown in Fig. 14.1.2 This device can occupy a surface area of less than 1000 µm2. Three physical regions comprise the BJT: the emitter, the base, and the collector. The thickness of the base region between emitter and collector can be a small fraction of a micron, while the overall vertical dimension of a device may be a few microns. Thousands of such devices can be fabricated within a silicon wafer. They may be interconnected on the wafer using metal deposition techniques to form a system such as a microprocessor chip or they may be separated into thousands of individual BJTs, each mounted in its own case. The photolithographic methods that make it possible to simultaneously construct thousands of BJTs have led to continually decreasing size and cost of the BJT. Electronic devices, such as the BJT, are governed by current–voltage relationships that are typically nonlinear and rather complex. In general, it is difficult to analyze devices that obey nonlinear equations, much less develop design methods for circuits that include these devices. The basic concept of modeling an electronic device is to replace the device in the circuit with linear components that approximate the voltage–current characteristics of the device. A model can then be defined as a collection of simple components or elements used to represent a more complex electronic device. Once the device is replaced in the circuit by the model, well-known circuit analysis methods can be applied. Several different models are generally used for a given device. One may be more accurate than others, another may be simpler than others, another may model the dc voltage–current characteristics of the device, while still another may model the ac characteristics of the device. Models are developed to be used for manual analysis or to be used by a computer. In general, the models for manual analysis are simpler and less accurate, while the computer models are more complex and more accurate. Essentially, all models for manual analysis and most models for the computer include only linear elements. Nonlinear elements are included in some computer models, but increase the computation times involved in circuit simulation over the times in simulation of linear models.

FIGURE 14.1 An integrated npn BJT.

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FIGURE 14.2 Distribution of electrons in the active region.

14.3 Basic Operation of the BJT In order to understand the origin of the elements used to model the BJT, we will discuss a simplified version of the device as shown in Fig. 14.2. The device shown is an npn device that consists of a p-doped material interfacing on opposite sides to n-doped material. A pnp device can be created using an n-doped central region with p-doped interfacing regions. Because the npn type of BJT is more popular in present construction processes, the following discussion will center on this device. The geometry of the device implied in Fig. 14.2 is physically more like the earlier alloy transistor. This geometry is also capable of modeling the modern BJT (Fig. 14.1) as the theory applies almost equally well to both geometries. Normally, some sort of load would appear in either the collector or emitter circuit; however, this is not important to the initial discussion of BJT operation. The circuit of Fig. 14.2 is in the active region, that is, the emitter–base junction is forward-biased, while the collector–base junction is reverse-biased. The current flow is controlled by the profile of electrons in the p-type base region. It is proportional to the slope or gradient of the free electron density in the base region. The well-known diffusion equation can be expressed as3: qD n An ( 0 ) dn I = qD n A------ = – -----------------------dx W

(14.1)

where q is the electronic charge, Dn is the diffusion constant for electrons, A is the cross-sectional area of the base region, W is the width or thickness of the base region, and n(0) is the density of electrons at the left edge of the base region. The negative sign reflects the fact that conventional current flow is opposite to the flow of the electrons.

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The concentration of electrons at the left edge of the base region is given by: n ( 0 ) = n bo e

qV BE ⁄ kT

(14.2)

where q is the charge on an electron, k is Boltzmann’s constant, T is the absolute temperature, and nbo is the equilibrium concentration of electrons in the base region. Although nbo is a small number, n(0) can be large for values of applied base to emitter voltages of 0.6 to 0.7 V. At room temperature, this equation can be written as: n ( 0 ) = n bo e

V BE ⁄ 0.026

(14.3)

In Fig. 14.2, the voltage VEB = –VBE.. A component of hole current also flows across the base–emitter junction from base to emitter. This component is rendered negligible compared with the electron component by doping the emitter region much more heavily than the base region. As the concentration of electrons at the left edge of the base region increases, the gradient increases and the current flow across the base region increases. The density of electrons at x = 0 can be controlled by the voltage applied from emitter to base. Thus, this voltage controls the current flowing through the base region. In fact, the density of electrons varies exponentially with the applied voltage from emitter to base, resulting in an exponential variation of current with voltage. The reservoir of electrons in the emitter region is unaffected by the applied emitter-to-base voltage as this voltage drops across the emitter–base depletion region. This applied voltage lowers the junction voltage as it opposes the built-in barrier voltage of the junction. This leads to the increase in electrons flowing from emitter to base. The electrons injected into the base region represent electrons that were originally in the emitter. As these electrons leave the emitter, they are replaced by electrons from the voltage source, VEB. This current is called emitter current and its value is determined by the voltage applied to the junction. Of course, conventional current flows in the opposite direction to the electron flow. The emitter electrons flow through the emitter, across the emitter–base depletion region, and into the base region. These electrons continue across the base region, across the collector–base depletion region, and through the collector. If no electrons were “lost” in the base region and if the hole flow from base to emitter were negligible, the current flow through the emitter would equal that through the collector. Unfortunately, there is some recombination of carriers in the base region. When electrons are injected into the base region from the emitter, space charge neutrality is upset, pulling holes into the base region from the base terminal. These holes restore space charge neutrality if they take on the same density throughout the base as the electrons. Some of these holes recombine with the free electrons in the base and the net flow of recombined holes into the base region leads to a small, but finite, value of base current. The electrons that recombine in the base region reduce the total electron flow to the collector. Because the base region is very narrow, only a small percentage of electrons traversing the base region recombine and the emitter current is reduced by a small percentage as it becomes collector current. In a typical low-power BJT, the collector current might be 0.995IE. The current gain from emitter to collector, IC /IE, is called α and is a function of the construction process for the BJT. Using Kirchhoff ’s current law, the base current is found to equal the emitter current minus the collector current. This gives: I B = I E – I C = (1 – α)I E

(14.4)

If α = 0.995, then IB = 0.005IE. Base current is very small compared to emitter or collector current. A parameter β is defined as the ratio of collector current to base current resulting in: α β = -----------1–α

(14.5)

This parameter represents the current gain from base to collector and can be quite high. For the value of α cited earlier, the value of β is 199. © 2003 by CRC Press LLC

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FIGURE 14.3 A BJT amplifier.

14.4 Use of the BJT as an Amplifier Figure 14.3 shows a simple configuration of a BJT amplifier. This circuit is known as the common emitter configuration. A voltage source is not typically used to forward-bias the base–emitter junction in an actual circuit, but we will assume that VBB is used for this purpose. A value of VBB or VBE near 0.6 to 0.7 V would be appropriate for this situation. The collector supply would be a large voltage, such as 12 V. We will assume that the value of VBB sets the dc emitter current to a value of 1 mA for this circuit. The collector current entering the BJT will be slightly less than 1 mA, but we will ignore this difference and assume that IC = 1 mA also. With a 4-kΩ collector resistance, a 4-V drop will appear across RC, leading to a dc output voltage of 8 V. The distribution of electrons across the base region for the steady-sate or quiescent conditions is shown by the solid line of Fig. 14.3(a). If a small ac voltage now appears in series with VBB, the injected electron density at the left side of the base region will be modulated. Since this density varies exponentially with the applied voltage (see Eq. 14.2), a small ac voltage can cause considerable changes in density. The dashed lines in Fig. 14.3(a) show the distributions at the positive and negative peak voltages. The collector current may change from its quiescent level of 1 mA to a maximum of 1.1 mA as ein reaches its positive peak, and to a minimum of 0.9 mA when ein reaches its negative peak. The output collector voltage will drop to a minimum value of 7.6 V as the collector current peaks at 1.1 mA, and will reach a maximum voltage of 8.4 V as the collector current drops to 0.9 mA. The peak-to-peak ac output voltage is then 0.8 V. The peak-to-peak value of ein to case this change might be 5 mV, giving a voltage gain of A = –0.8/0.005 = –160. The negative sign occurs because when ein increases, the collector current increases, but the collector voltage decreases. This represents a phase inversion in the amplifier of Fig. 14.3. In summary, a small change in base-to-emitter voltage causes a large change in emitter current. This current is channeled across the collector, through the load resistance, and can develop a larger incremental voltage across this resistance. © 2003 by CRC Press LLC

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FIGURE 14.4 Large-signal model of the BJT.

FIGURE 14.5 A small-signal model of the BJT.

14.5 Representing the Major BJT Effects by an Electronic Model The two major effects of the BJT in the active region are the diode characteristics of the base–emitter junction and the collector current that is proportional to the emitter current. These effects can be modeled by the circuit of Fig. 14.4. The simple diode equation represents the relationship between applied emitter-to-base voltage and emitter current. This equation can be written as I E = I 1 (e

qV BE ⁄ kT

– 1)

(14.6)

where q is the charge on an electron, k is Boltzmann’s constant, T is the absolute temperature of the diode, and I1 is a constant at a given temperature that depends on the doping and geometry of the emitterbase junction. The collector current is generated by a dependent current source of value IC = αIE . A small-signal model based on the large-signal model of Fig. 14.4 is shown in Fig. 14.5. In this case, the resistance, rd , is the dynamic resistance of the emitter-base diode and is given by: kT r d = ------qI E

(14.7)

where IE is the dc emitter current.

14.6 Other Physical Effects in the BJT The preceding section pertains to the basic operation of the BJT in the dc and midband frequency range. Several other effects must be included to model the BJT with more accuracy. These effects will now be described. © 2003 by CRC Press LLC

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Ohmic Effects The metal connections to the semiconductor regions exhibit some ohmic resistance. The emitter contact resistance and collector contact resistance is often in the ohm range and does not affect the BJT operation in most applications. The base region is very narrow and offers little area for a metal contact. Furthermore, because this region is narrow and only lightly doped compared to the emitter, the ohmic resistance of the base region itself is rather high. The total resistance between the contact and the intrinsic base region can be 100 to 200 Ω. This resistance can become significant in determining the behavior of the BJT, especially at higher frequencies.

Base-Width Modulation (Early Effect) The widths of the depletion regions are functions of the applied voltages. The collector voltage generally exhibits the largest voltage change and, as this voltage changes, so also does the collector–base depletion region width. As the depletion layer extends further into the base region, the slope of the electron distribution in the base region becomes greater since the width of the base region is decreased. A slightly steeper slope leads to slightly more collector current. As reverse-bias decreases, the base width becomes greater and the current decreases. This effect is called base-width modulation and can be expressed in terms of the Early voltage,4 VA, by the expression: V CE I C = βI B  1 + ------- VA 

(14.8)

The Early voltage will be constant for a given device and is typically in the range of 60 to 100 V.

Reactive Effects Changing the voltages across the depletion regions results in a corresponding change in charge. This leads to an effective capacitance because dQ C = ------- dV

(14.9)

This depletion region capacitance is a function of voltage applied to the junction and can be written as4: C Jo C dr = -------------------------m (φ – V app )

(14.10)

where CJo is the junction capacitance at zero bias, φ is the built-in junction barrier voltage, Vapp is the applied junction voltage, and m is a constant. For modern BJTs, m is near 0.33. The applied junction voltage has a positive sign for a forward-bias and a negative sign for a reverse-bias. The depletion region capacitance is often called the junction capacitance. An increase in forward base–emitter voltage results in a higher density of electrons injected into the base region. The charge distribution in the base region changes with this voltage change, and this leads to a capacitance called the diffusion capacitance. This capacitance is a function of the emitter current and can be written as: C D = k 2 I E

(14.11)

where k2 is a constant for a given device.

14.7 More Accurate BJT Models Figure 14.6 shows a large-signal BJT model used in some versions of the popular simulation program known as SPICE.5 The equations for the parameters are listed in other texts5 and will not be given here. © 2003 by CRC Press LLC

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FIGURE 14.6 A more accurate large-signal model of the BJT.

FIGURE 14.7 The hybrid-π small-signal model for the BJT.

Figure 14.7 shows a small-signal SPICE model5 often called the hybrid-π equivalent circuit. The capacitance, Cπ, accounts for the diffusion capacitance and the emitter–base junction capacitance. The collector–base junction capacitance is designated Cµ. The resistance, rπ, is equal to (β + 1)rd. The transductance, gm, is given by: α g m = ---rd

(14.12)

The impedance, ro , is related to the Early voltage by: V r o = -----A- IC © 2003 by CRC Press LLC

(14.13)

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RB, RE, and RC are the base, emitter, and collector resistances, respectively. For hand analysis, the ohmic resistances RE and RC are neglected along with CCS, the collector-to-substrate capacitance.

14.8 Heterojunction Bipolar Junction Transistors In an npn device, all electrons injected from emitter to base are collected by the collector, except for a small number that recombine in the base region. The holes injected from base to emitter contribute to emitter junction current, but do not contribute to collector current. This hole component of the emitter current must be minimized to achieve a near-unity current gain from emitter to collector. As α approaches unity, the current gain from base to collector, β, becomes larger. In order to produce high-β BJTs, the emitter region must be doped much more heavily than the base region, as explained earlier. Although this approach allows the value of β to reach several hundred, it also leads to some effects that limit the frequency of operation of the BJT. The lightly doped base region causes higher values of base resistance, as well as emitter–base junction capacitance. Both of these effects are minimized in the heterojunction BJT (or HBJT). This device uses a different material for the base region than that used for the emitter and collector regions. One popular choice of materials is silicon for the emitter and collector regions, and a silicon/germanium material for the base region.6 The difference in energy gap between the silicon emitter material and the silicon/germanium base material results in an asymmetric barrier to current flow across the junction. The barrier for electron injection from emitter to base is smaller than the barrier for hole injection from base to emitter. The base can then be doped more heavily than a conventional BJT to achieve lower base resistance, but the hole flow across the junction remains negligible due to the higher barrier voltage. The emitter of the HBJT can be doped more lightly to lower the junction capacitance. Large values of β are still possible in the HBJT while minimizing frequency limitations. Current gain-bandwidth figures exceeding 60 GHz have been achieved with present industrial HBJTs. From the standpoint of analysis, the SPICE models for the HBJT are structurally identical to those of the BJT. The difference is in the parameter values.

14.9 Integrated Circuit Biasing Using Current Mirrors Differential stages are very important in integrated circuit amplifier design. These stages require a constant dc current for proper bias. A simple bias scheme for differential BJT stages will now be discussed. The diode-biased current sink or current mirror of Fig. 14.8 is a popular method of creating a constantcurrent bias for differential stages.

FIGURE 14.8 Current mirror bias stage. © 2003 by CRC Press LLC

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FIGURE 14.9 Multiple output current mirror.

The concept of the current mirror was developed specifically for analog integrated circuit biasing and is a good example of a circuit that takes advantage of the excellent matching characteristics that are possible in integrated circuits. In the circuit of Fig. 14.8, the current I2 is intended to be equal to or “mirror” the value of I1. Current mirrors can be designed to serve as sinks or sources. The general function of the current mirror is to reproduce or mirror the input or reference current to the output, while allowing the output voltage to assume any value within some specified range. The current mirror can also be designed to generate an output current that equals the input current multiplied by a scale factor K. The output current can be expressed as a function of input current as: I O = KI IN

(14.14)

where K can be equal to, less than, or greater than unity. This constant can be established accurately by relative device sizes and will not vary with temperature. Figure 14.9 shows a multiple output current source where all of the output currents are referenced to the input current. Several amplifier stages can be biased with this multiple output current mirror.

Current Source Operating Voltage Range Figure 14.10 shows an ideal or theoretical current sink in (a) and a practical sink in (b). The voltage at node A in the theoretical sink can be tied to any potential above or below ground without affecting the value of I. On the other hand, the practical circuit of Fig. 14.10(b) requires that the transistor remain in the active region to provide a current of: V B – V BE I = α-------------------R

(14.15)

This requires that the collector voltage exceed the voltage VB at all times. The upper limit on this voltage is determined by the breakdown voltage of the transistor. The output voltage must then satisfy: V B < V C < (V B + BV CE ) © 2003 by CRC Press LLC

(14.16)

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FIGURE 14.10 Current sink circuits: (a) ideal sink, (b) practical sink.

where BVCE is the breakdown voltage from collector to emitter of the transistor. This voltage range over which the current source operates is called the output voltage compliance range or the output compliance.

Current Mirror Analysis The current mirror is again shown in Fig. 14.11. If devices Q1 and Q2 are assumed to be matched devices, we can write: I E1 = I E2 = I EO e

V BE ⁄ V T

(14.17)

where VT = kT/q, IEO = AJEO , A is the emitter area of the two devices, and JEO is the current density of the emitters. The base currents for each device will also be identical and can be expressed as: I EO VBE ⁄ VT -e I B1 = I B2 = ----------β+1

(14.18)

Device Q1 operates in the active region, but near saturation by virtue of the collector–base connection. This configuration is called a diode-connected transistor. The collector-to-emitter voltage is very small, therefore, the collector current for device Q1 is given by Eq. 14.8, assuming VCE = 0. This gives: V BE ⁄ V T β I C1 = βI B1 ≈ ------------ I EO e β+1

(14.19)

The device Q2 does not have the constraint that VCE ≈ 0 as device Q1 has. The collector voltage for Q2 will be determined by the external circuit that connects to this collector. Thus, the collector current for this device is: V C2 I C2 = βI B2  1 + ------ VA 

(14.20)

where VA is the Early voltage. In effect, the output stage has an output impedance given by Eq. 14.13. The current mirror more closely approximates a current source as the output impedance becomes larger. © 2003 by CRC Press LLC

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FIGURE 14.11 Circuit for current mirror analysis.

If we limit the voltage VC2 to small values relative to the Early voltage, IC2 is approximately equal to IC1. For integrated circuit designs, the voltage required at the output of the current mirror is generally small, making this approximation valid. The input current to the mirror is larger than the collector current and is: I IN = I C1 + 2I B

(14.21)

Because IOUT = IC2 = IC1 = βIB , we can write Eq. 14.21 as: I IN = βI B + 2I B = (β + 2)I B

(14.22)

I IN β I OUT = ------------ I IN = -----------------β+2 1+2⁄β

(14.23)

Relating IIN to IOUT results in:

For typical values of β, these two currents are essentially equal. Thus, a desired bias current, IOUT, is generated by creating the desired value of IIN. The current IIN is normally established by connecting a resistance R1 to a voltage source VCC to set IIN to: V CC – V BE I IN = ----------------------R1

(14.24)

Control of collector/bias current for Q2 is then accomplished by choosing proper values of VCC and R1. Figure 14.12 shows a multiple-output current mirror. It can be shown that the output current for each identical device in Fig. 14.12 is: I IN I O = ---------------------N+1 1 + ------------­ β

(14.25)

where N is the number of output devices. The current sinks can be turned into current sources by using pnp transistors and a power supply of opposite polarity. The output devices can also be scaled in area to make IOUT be larger or smaller than IIN. © 2003 by CRC Press LLC

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FIGURE 14.12 Multiple-output current mirror.

Current Mirror with Reduced Error The difference between output current in a multiple-output current mirror and the input current can become quite large if N is large. One simple method of avoiding this problem is to use an emitter follower to drive the bases of all devices in the mirror, as shown in Fig. 14.13. The emitter follower, Q0, has a current gain from base to collector of β + 1, reducing the difference between IO and IIN to: N+1 I IN – I O = -------------I B β+1

(14.26)

The output current for each device is: I IN I O = ----------------------------N+1 1 + --------------------­ β(β + 1)

FIGURE 14.13 Improved multiple output current mirror. © 2003 by CRC Press LLC

(14.27)

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FIGURE 14.14 Wilson current mirror.

The Wilson Current Mirror In the simple current mirrors discussed, it was assumed that the collector voltage of the output stage was small compared with the Early voltage. When this is untrue, the output current will not remain constant, but will increase as output voltage (VCE) increases. In other words, the output compliance range is limited with these circuits due to the finite output impedance of the BJT. A modification of the improved output current mirror of Fig. 14.13 was proposed by Wilson7 and is illustrated in Fig. 14.14. The Wilson current mirror is connected such that VCB2 = 0 and VBE1 = VBE0. Both Q1 and Q2 now operate with a near-zero collector–emitter bias although the collector of Q0 might feed into a high-voltage point. It can be shown that the output impedance of the Wilson mirror is increased by a factor of β/2 over the simple mirror. This higher impedance translates into a higher output compliance. This circuit also reduces the difference between input and output current by means of the emitter follower stage.

14.10 The Basic BJT Switch In digital circuits, the BJT is used as a switch to generate one of only two possible output voltage levels, depending on the input voltage level. Each voltage level is associates with one of the binary digits, 0 or 1. Typically, the high voltage level may fall between 2.8 V and 5 V, while the low voltage level may fall between 0 V and 0.8 V. Logic circuits are based on BJT stages that are either in cutoff with both junctions reverse-biased or in a conducting mode with the emitter–base junction forward-biased. When the BJT is “on” or conducting emitter current, it can be in the active region or the saturation region. If it is in the saturation region, the collector–base region is also forward-biased. The three possible regions of operation are summarized in Table 14.1.

TABLE 14.1

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Regions of Operation

Region

Cutoff

Active

Saturation

C–B bias E–B bias

Reverse Reverse

Reverse Forward

Forward

Forward

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417

FIGURE 14.15 The BJT as a switch: (a) open switch, (b) closed switch.

The BJT very closely approximates certain switch configurations. For example, when the switch of Fig. 14.15(a) is open, no current flows through the resistor and the output voltage is +12 V. Closing the switch causes the output voltage to drop to zero volts and a current of 12/R flows through the resistance. When the base voltage of the BJT of Fig. 14.15(b) is negative, the device is cut off and no collector current flows. The output voltage is +12 V, just as in the case of the open switch. If a large enough current is now driven into the base to saturate the BJT, the output voltage becomes very small, ranging from 20 mV to 500 mV, depending on the BJT used. The saturated state corresponds closely to the closed switch. During the time that the BJT switches from cutoff to saturation, the active region equivalent circuit applies. For high-speed switching of this circuit, appropriate reactive effects must be considered. For lowspeed switching, these reactive effects can be neglected. Saturation occurs in the basic switching circuit of Fig. 14.15(b) when the entire power supply voltage drops across the load resistance. No voltage, or perhaps a few tenths of volts, then appears from collector to emitter. This occurs when the base current exceeds the value V CC – V CE ( sat) I B ( sat) = ------------------------------βR L

(14.28)

When a transistor switch is driven into saturation, the collector–base junction becomes forward-biased. This situation results in the electron distribution across the base region shown in Fig. 14.16. The forwardbias of the collector–base junction leads to a nonzero concentration of electrons in the base that is unnecessary to support the gradient of carriers across this region. When the input signal to the base switches to a lower level to either turn the device off or decrease the current flow, the excess charge must be removed from the base region before the current can begin to decrease.

14.11 High-Speed BJT Switching Three major effects can extend switching times in a BJT: 1. The depletion-region or junction capacitances are responsible for delay time when the BJT is in the cutoff region. 2. The diffusion capacitance and the Miller-effect capacitance are responsible for the rise and fall times of the BJT as it switches through the active region. 3. The storage time constant accounts for the time taken to remove the excess charge from the base region before the BJT can switch from the saturation region to the active region. © 2003 by CRC Press LLC

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FIGURE 14.16 Electron distribution in the base region of a saturated BJT.

Other second-order effects are generally negligible compared with the previously listed time lags. Because the transistor is generally operating as a large-signal device, the parameters such as junction capacitance or diffusion capacitance will vary as the BJT switches. One approach to the evaluation of time constants is to calculate an average value of capacitance over the voltage swing that takes place. Not only is this method used in hand calculations, but most computer simulation programs use average values to speed calculations.

Overall Transient Response Before discussing the individual BJT switching times, it is helpful to consider the response of a commonemitter switch to a rectangular waveform. Figure 14.17 shows a typical circuit using an npn transistor.

FIGURE 14.17 A simple switching circuit. © 2003 by CRC Press LLC

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FIGURE 14.18 Input and output waveforms.

A rectangular input pulse and the corresponding output are shown in Fig. 14.18. In many switching circuits, the BJT must switch from its “off ” state to saturation and later return to the “off ” state. In this case, the delay time, rise time, saturation storage time, and fall time must be considered in that order to find the overall switching time. The total waveform is made up of five sections: delay time, rise time, on time, storage time, and fall time. The following list summarizes these points and serves as a guide for future reference: td′ = Passive delay time; time interval between application of forward base drive and start of collectorcurrent response. td = Total delay time; time interval between application of forward base drive and the point at which IC has reached 10% of the final value. tr = Rise time; 10- to 90-% rise time of IC waveform. ts′= Saturation storage time; time interval between removal of forward base drive and start of IC decrease. ts = Total storage time; time interval between removal of forward base drive and point at which IC = 0.9IC(sat). tf = Fall time; 90- to 10-% fall time of IC waveform Ton = Total turn-on time; time interval between application of base drive and point at which IC has reached 90% of its final value. Toff = Total turn-off time; time interval between removal of forward base drive and point at which IC has dropped to 10% of its value during on time. Not all applications will require evaluation of each of these switching times. For instance, if the base drive is insufficient to saturate the transistor, ts will be zero. If the transistor never leaves the active region, the delay time will also be zero. © 2003 by CRC Press LLC

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The factors involved in calculating the switching times are summarized in the following paragraphs.8 The passive delay time is found from: E on + E off  t′d = τ d ln  --------------------------- E on – V BE ( on )

(14.29)

where τd is the product of the charging resistance and the average value of the two junction capacitances. The active region time constant is a function of the diffusion capacitance, the collector–base junction capacitance, the transconductance, and the charging resistance. This time constant will be denoted by τ. If the transistor never enters saturation, the rise time is calculated from the well-known formula: t r = 2.2τ

(14.30)

If the BJT is driven into saturation, the rise time is found from8: K – 0.1 t r = τ ln  -----------------  K – 0.9

(14.31)

where K is the overdrive factor or the ratio of forward base current drive to the value needed for saturation. The rise time for the case where K is large can be much smaller than the rise time for the nonsaturating case (K < 1). Unfortunately, the saturation storage time increases for large values of K. The saturation storage time is given by: I B1 – I B2  t′s = τ s ln  ----------------------- I B ( sat ) – I B2

(14.32)

where τs is the storage time constant, IB1 is the forward base current before switching, and IB2 is the current after switching and must be less than IB(sat). The saturation storage time can slow the overall switching time significantly. The higher speed logic gates utilize circuits that avoid the saturation region for the BJTs that make up the gate.

14.12 Simple Logic Gates Although the resistor-transistor-logic (RTL) family has not been used since the late 1960s, it demonstrates the concept of a simple logic gate. Figure 14.19 shows a four-input RTL NOR gate. If all four inputs are at the lower voltage level (e.g., 0 V), there is no conducting path from output to ground. No voltage will drop across RL, and the output voltage will equal VCC. If any or all of the inputs moves to the higher voltage level (e.g., 4 V), any BJT with base connected to the higher voltage level will saturate, pulling the output voltage down to a few tenths of a volt. If positive logic is used, with the high voltage level corresponding to binary “1” and the low voltage level to binary “0,” the gate performs the NOR function. Other logic functions can easily be constructed in the RTL family. Over the years, the performance of logic gates has been improved by different basic configurations. RTL logic was improved by diode-transistor-logic (DTL). Then, transistor-transistor-logic (TTL) became very prominent. This family is still popular in the small-scale integration (SSI) and medium-scale integration (MSI) areas, but CMOS circuits have essentially replaced TTL in large-scale integration (LSI) and very-large-scale integration (VLSI) applications. One popular family that is still prominent in very high-speed computer work is the emitter-coupled logic (ECL) family. Although CMOS packs many more circuits into a given area than ECL, the frequency performance of ECL leads to its popularity in supercomputer applications.

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FIGURE 14.19 A four-input RTL NOR gate.

14.13 Emitter-Coupled Logic Emitter-coupled logic (ECL) was developed in the mid-1960s and remains the fastest silicon logic circuit available. Present ECL families offer propagation delays in the range of 0.2 ns.9 The two major disadvan­ tages of ECL are: (1) resistors which require a great deal of IC chip area, must be used in each gate, and (2) the power dissipation of an ECL gate is rather high. These two shortcomings limit the usage of ECL in VLSI systems. Instead, this family has been used for years in larger supercomputers than can afford space and power to achieve higher speeds. The high speeds obtained with ECL are primarily based on two factors. No device in an ECL gate is ever driven into the saturation region and, thus, saturation storage time is never involved as devices switch from one state to another. The second factor is that required voltage swings are not large. Voltage excursions necessary to change an input from the low logic level to the high logic level are minimal. Although noise margins are lower than other logic families, switching times are reduced in this way. Figure 14.20 shows an older ECL gate with two separate outputs. For positive logic, X is the OR output while Y is the NOR output. Often, the positive supply voltage is taken as 0 V and VEE as –5 V due to noise considerations. The diodes and emitter follower Q5 establish a temperature-compensated base reference for Q4. When inputs A, B, and C are less than the voltage VB, Q4 conducts while Q1, Q2, and Q3 are cut off. If any one of the inputs is switched to the 1 level, which exceeds VB, the transistor turns on and pulls the emitter of Q4 positive enough to cut this transistor off. Under this condition, output Y goes negative while X goes positive. The relatively large resistor common to the emitters of Q1, Q2, Q3, and Q4 prevents these transistors from saturating. In fact, with nominal logic levels of –1.9 V and –1.1 V, the current through the emitter resistance is approximately equal before and after switching takes place. Thus, only the current path changes as the circuit switches. This type of operation is sometimes called current mode switching. Although the output stages are emitter followers, they conduct reasonable currents for both logic level outputs and, therefore, minimize the asymmetrical output impedance problem.

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FIGURE 14.20 An ECL logic gate.

In an actual ECL gate, the emitter follower load resistors are not fabricated on the chip. The newer version of the gate replaces the emitter resistance of the differential stage with a current source, and replaces the bias voltage circuit with a regulated voltage circuit.

A Closer Look at the Differential Stage Figure 14.21 shows a simple differential stage similar to the input stage of an ECL gate.2 Both transistors are biased by a current source, IT , called the tail current. The two input signals e1 and e2 make up a differential input signal defined as: ed = e1 – e2

(14.33)

This differential voltage can be expressed as the difference between the base–emitter junction voltages as: e d = V BE1 – V BE2

(14.34)

The collector currents can be written in terms of the base–emitter voltages as: I C1 = αI EO e I C2 = αI EO e where matched devices are assumed.

© 2003 by CRC Press LLC

V BE1 ⁄ V T

V BE2 ⁄ V T

≈ I EO e ≈ I EO e

V BE1 ⁄ V T

V BE2 ⁄ V T

(14.35) (14.36)

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FIGURE 14.21 A simple differential stage similar to an ECL input stage.

A differential output current can be defined as the difference of the collector currents, or (14.37)

I d = I C1 – I C2 Since the tail current is IT = IC1 + IC2, taking the ratio of Id to IT gives: I C1 – I C2 I ---d- = ------------------IT I C1 + I C2

(14.38)

Because VBE1 = ed + VBE2, we can substitute this value for VBE1 into Eq. 14.35 to write: (e d + V BE2 ) ⁄ V T

e d ⁄ V T V BE2 ⁄ V T

e

(14.39)

ed ⁄ VT ed I e –1 ----------d- = --------------------= tanh ed ⁄ VT 2V T IT +1 e

(14.40)

ed I d = I T tanh -------2V

(14.41)

I C1 = I EO e

= I EO e

Substituting Eqs. 14.36 and 14.39 into Eq. 14.38 results in:

or

T

This differential current is graphed in Fig. 14.22. When ed is zero, the differential current is also zero, implying equal values of collector currents in the two devices. As ed increases, so also does Id until ed exceeds 4VT, at which time Id has reached a constant value of IT . From the definition of differential current, this means that IC1 equals IT while IC2 is zero. As the differential input voltage goes negative, the differential current approaches –IT as the voltage reaches –4VT . In this case, IC2 = IT while IC1 goes to zero.

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FIGURE 14.22 Differential output current as a function of differential input voltage.

FIGURE 14.23 Differential input stage with current mirror load.

The implication here is that the differential stage can move from a balanced condition with IC1 = IC2 to a condition of one device fully off and the other fully on with an input voltage change of around 100 mV or 4VT . This demonstrates that a total voltage change of about 200 mV at the input can cause an ECL gate to change states. This small voltage change contributes to smaller switching times for ECL logic. The ability of a differential pair to convert a small change in differential base voltage to a large change in collector voltage also makes it a useful building block for analog amplifiers. In fact, a differential pair with a pnp transistor current mirror load, as illustrated in Fig. 14.23, is widely used as an input stage for integrated circuit op-amps.

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425

References 1. Brittain, J. E. (Ed.), Turning Points in American Electrical History, IEEE Press, New York, 1977, Sec. II-D. 2. Comer, D. T., Introduction to Mixed Signal VLSI, Array Publishing, New York, 1994, Ch. 7. 3. Sedra, A. S. and Smith, K. C., Microelectronic Circuits, 4th ed., Oxford University Press, New York, 1998, Ch. 4. 4. Gray, P. R. and Meyer, R. G., Analysis and Design of Analog Integrated Circuits, 3rd ed., John Wiley & Sons, Inc., New York, 1993, Ch. 1. 5. Vladimirescu, A., The Spice Book, John Wiley & Sons, Inc., New York, 1994, Ch. 3. 6. Streetman, B. G., Solid State Electronic Devices, 4th ed., Prentice Hall, Englewood Cliffs, NJ, 1995, Ch. 7. 7. Wilson, G. R., “A monolithic junction FET–NPN operational amplifier,” IEEE J. Solid State Circuits, vol. SC-3, pp. 341-348, Dec. 1968. 8. Comer, D. J., Modern Electronic Circuit Design, Addison-Wesley, Reading, MA, 1977, Ch. 8. 9. Motorola Technical Staff, High Performance ECL Data, Motorola, Inc., Phoenix, AZ, 1993, Ch. 3.

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15 Operational Amplifiers 15.1 The Ideal Operational Amplifier Open-Loop Equivalent Circuit • Voltage Op Amps • Op Amp Circuit Applications • Comparators • Other Op Amp Configurations • Summary

15.2 The Nonideal Operational Amplifier Finite Differential Gain • Output Saturation • Offset Voltage • Finite CMRR and PSRR • Finite Input Impedance and Nonzero Output Impedance • Input Bias Currents • Electrical Noise • Summary

David G. Nairn Queen’s University, Canada

Sergio Franco

15.3 Frequency- and Time-Domain Considerations

San Francisco State University, California

Voltage-Mode Op Amps • Block Diagram • Current-Mode Op Amps • Acknowledgment

15.1 The Ideal Operational Amplifier David G. Nairn The operational amplifier, or op amp, is a fundamental building block for many electronic circuits. Although the op amp itself is composed of numerous transistors, it is usually treated as a single circuit element known as the ideal operational amplifier. The ability to treat the op amp as an ideal circuit element simplifies its use in circuits such as amplifiers, buffers, filters, and data converters. With such varied uses, the op amp has been implemented in many different forms. Nevertheless, the behavior of each of these different forms can still be characterized as an ideal op amp.

Open-Loop Equivalent Circuit The op amp is primarily a high gain amplifier. Although the op amp can be used on its own, most op amps are part of larger circuits in which feedback is used to determine the circuit’s overall transfer function. Consequently, the op amp’s precise behavior is only a secondary interest. To simplify preliminary circuit analysis and design, an abstraction of the practical op amp, known as the ideal op amp is often used. The ideal op amp is characterized by the following four parameters: • • • •

infinite gain infinite bandwidth draws no signal power at its inputs is unaffected by loading of its output.

Although such specifications are not achieved in practice, the nonidealities of practical op amps (see Section 15.2, “The Nonideal Operational Amplifier”) can be neglected in most applications.

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in−

in−

−

in+

in+

+

out+

− +

out

out−

+ −

(a)

(b)

FIGURE 15.1 Circuit symbols for (a) the single-ended op amp and (b) the fully differential op amp.

The ideal op amp is represented schematically as a triangle with two inputs and either one or two outputs, as shown in Fig. 15.1. For the single output case, the output is referred to ground and the op amp is known as a single-ended op amp. For the two output case, the output is the difference between the out + and out – outputs and the op amp is known as a fully differential op amp. Because the op amp provides gain, it requires an external power source. For the ideal op amp, the power supply has no effect on the amplifier’s performance and is therefore not indicated in the circuit symbol. Based on the above description, the op amp’s input can be stimulated with either a voltage or current. Also, the controlled output can be either a voltage or a current. Consequently, there are four possible implementations of the ideal op amp: the voltage op amp, the transimpedance op amp, the current op amp, and the transconductance op amp, as shown in Table 15.1 and in Fig. 15.2. For most applications, the op amp is used in a closed-loop configuration with negative feedback. Due to the negative feedback, all four ideal op amp types perform the same function. When the limitations of practical op amps are considered, it will be found that different op amps are preferred for different applications. Of the four types, the voltage op amp is the most widely known. Therefore, the use of TABLE 15.1

in−

Input

Output

Gain

Type

V I I V

V V I I

Av Rm Ai Gm

Voltage Transimpedance Current Transconductance

in−

− out

vd in+

Ideal Op Amp Types

+

Av vd

out in+

+ −

ii

(a)

in− out

in+

Ai ii

(c)

+ −

(b)

in− ii

Rm ii

− out

vd in+

+

Gm vd

(d)

FIGURE 15.2 The four possible op amp configurations: (a) the voltage op amp, (b) the transimpedance op amp, (c) the current op amp, and (d) the transconductance op amp. © 2003 by CRC Press LLC

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op amps will be considered from the perspective of the voltage op amp. Then, the other three types will be considered.

Voltage Op Amps The ideal voltage op amp, illustrated in Fig. 15.2(a), is a voltage-controlled voltage source with infinite gain. If a potential difference vd exists between the noninverting terminal in+ and the inverting terminal in– the op amp’s output voltage vout will be v out = Avv d

(15.1)

where Av is the differential gain and is both infinite and frequency independent. Note that only the differential voltage is amplified. As an ideal voltage-controlled voltage source, the op amp has an infinite resistance and a zero output resistance. The properties of an ideal voltage op amp may be summarized as follows: • • • • •

infinite differential gain zero common-mode gain infinite bandwidth infinite input resistance zero output resistance.

With these ideal properties, the op amp is relatively easy to use in many circuit applications.

Op Amp Circuit Applications The op amp can be used in both open-loop configurations and closed-loop configurations. If the op amp is used open-loop, small voltages between the input terminals produced either a positive or negative infinite voltage due to the amplifier’s infinite gain. Consequently, the op amp can be used as a comparator. This application is discussed further in the section on comparators. In a closed-loop circuit, feedback allows the op amp’s output voltage to influence its input voltage (see Section IV). The op amp can then be made to perform many complex operations. Unity Gain Buffer The simplest feedback that can be applied to the op amp is depicted in Fig. 15.3. The op amp’s output is connected to the inverting input and an input signal Vin is applied to the noninverting input. The feedback forces the voltage at in– to equal Vout. By multiplying the differential voltage at the op amp’s input (i.e., Vin – Vout) by the op amp’s gain, Vout is found to be Vout = Av (Vin − Vout )

in−

+ Vin

in+

− + +

Vout −

−

FIGURE 15.3 A unity gain buffer. © 2003 by CRC Press LLC

(15.2)

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which can be rewritten as Vout 1 = Vin 1 + 1 Av

(15.3)

because Av is infinite, Vout equals Vin. Therefore, the circuit is a unity gain buffer. It is important to note that the op amp’s high gain and the use of negative feedback forces the voltage at the op amp’s two input terminals to be equal. Hence if Vin is varied, Vout will follow or track it. The op amp’s two input terminals have the same potential, but no current flows between them. Therefore, a virtual short is said to exist between the inputs. The unity gain buffer draws no current from the signal source due to the op amp’s infinite input resistance and the op amp’s zero output resistance ensures that loading does not affect the voltage at Vout. Simple Attenuator If an output equal to a fraction of Vin is required, the circuit is illustrated in Fig. 15.4(a). The noninverting terminal is now a fraction of Vin. Because Vout tracks the voltage at the noninverting terminal, the circuit’s output voltage will be  R1  Vout = Vin    R1 + R2 

(15.4)

Due to the op amp’s infinite input resistance, the voltage divider formed by R1 and R2 is not loaded by the op amp. Therefore, large values of R1 and R2 can be used to avoid loading the source voltage Vin. The Noninverting Amplifier Configuration Usually, it is more desirable to amplify a signal than to attenuate it. Therefore, instead of matching an attenuated Vin to Vout, at the op amp’s input an attenuated Vout can be matched to Vin, as illustrated in Fig. 15.4(b). Due to the negative feedback and the op amp’s finite gain, the op amp’s two inputs have the same potential. Therefore,  R1  Vin = Vout    R1 + R2 

(15.5)

Vout R =1+ 2 Vin R1

(15.6)

which is more commonly written as

This circuit configuration is commonly referred to as the noninverting configuration [1]. Gains greater than or equal to unity can be achieved simply by changing the ratio of R2 to R1. The actual values of R2 and R1 are unimportant. Only their ratio determines the gain. The op amp’s infinite input resistance R2 in− −

Vin R2

in+

in− −

Vout R1

+

Vin

in+

Vout

+

R1 (a)

(b)

FIGURE 15.4 (a) A simple buffer attenuator; (b) the noninverting amplifier configuration. © 2003 by CRC Press LLC

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R2 Vin

R1

−

I = Vin /R1

Vout

+

FIGURE 15.5 The inverting amplifier configuration.

ensures that no current is drawn from the source, therefore, Vin controls the voltage across R1 but does not supply the current flowing through it. The Inverting Configuration If the source Vin can supply current, Vin can be connected directly to R1, as illustrated in Fig. 15.5. In this case the voltage across R1 is still equal to Vin but of opposite polarity. The voltage at the op amp’s inverting input is now at ground potential, but no current flows to ground. Consequently, a virtual ground exists at the inverting input terminal. Because the current flowing through R1 cannot flow to ground or into the op amp, it flows through R2 , causing an output voltage of V  Vout = 0 − R2  in   R1 

(15.7)

Vout R =− 2 Vin R1

(15.8)

or

This circuit configuration is commonly referred to as the inverting configuration [1]. Both amplification and attenuation can be achieved by changing the ratio of R2 to R1. A very important difference between the inverting and noninverting configurations is that the inverting configuration draws a current equal to Vin /R1 from the source. Consequently, even though the op amp itself has an infinite input resistance, the inverting configuration only has an input resistance equal to R1. Fortunately, the gain only depends on the ratio of R2 to R1, thereby allowing both resistors to be increased, thus limiting the current drawn from Vin. Frequency Dependent and Nonlinear Transfer Functions Elements other than resistors can be used in both the inverting and noninverting configuration. By using the frequency dependent elements Z1 and Z2 in place of R1 and R2, circuits with arbitrary frequency responses can be generated. Two examples of this are illustrated in Fig. 15.6(a) and (c). In Fig. 15.6(a), a capacitor has been added in series with R1. The inverting amplifier now has the transfer function Vout −Z 2 s) = ( Vin Z1

(15.9)

where Z1 equals (1 + R1Cs)/(Cs) and Z2 equals R2. Therefore, the circuit’s transfer function is Vout −R Cs (s) = 1 + R2 Cs Vin 1

(15.10)

which is a simple high-pass filter, as illustrated in Fig. 15.6(b). Alternatively, a capacitor can be added in parallel with R2 as shown in Fig. 15.6(c). Now, Z1 equals R1 and Z2 equals R2 /(1 + R2Cs), which results in the transfer function © 2003 by CRC Press LLC

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R2

20log (R2/R1)

R1 −

Vout

+

20log (Vout/Vin)

Vin

C

1 R1C

(a)

Frequency (log scale)

(b) C

R2

20log (R2/R1)

−

20log (Vout/Vin)

R1

Vin

Vout

+

Frequency (log scale) 1 R2C

(c)

(d)

FIGURE 15.6 Frequency dependent circuits using the inverting configuration: (a) a simple high-pass filter and (b) its frequency response; (c) simple low-pass filter and (d) its frequency response.

Vin

R1

−

Vout

+

ID1 = Vin/R1

D1

0

0

(a)

VD = −Vout (b)

FIGURE 15.7 Obtaining the I–V characteristics of a diode: (a) circuit configuration; (b) oscilloscope display with Vout inverted.

Vout −R (s) = R 1 + R2 Cs Vin (1 2 )

(15.11)

This circuit performs as a low-pass filter, as illustrated in Fig. 15.6(d). By selecting Z1 and Z2, arbitrary transfer functions can be generated, thereby making op amp circuits useful for implementing active filters (see Section XII). When designing arbitrary transfer functions, the resulting circuits must be stable if they are to perform correctly [2]. If nonlinear elements such as diodes are used in place of R1 and R2, nonlinear transfer functions can be obtained [2]. For example, the I–V characteristics of a component can be obtained by replacing R2 in the inverting configuration with the desired nonlinear element, as depicted in Fig. 15.7(a). Then, by applying Vin and Vout to an oscilloscope, the element’s I–V characteristic can be displayed directly as depicted in Fig. 15.7(b). Due to the diode’s exponential characteristic, the circuit’s output is the logarithm of its input V  Vout = nVT ln in   R1I S 

(15.12)

The constants n and IS are determined by the diode while VT is the thermal voltage (see Chapter 10, Section 10.5). Circuits of this type are made possible by the presence of the virtual ground at the op amp’s input. © 2003 by CRC Press LLC

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Va

R1a

R2 Ia + Ib

Ia Vb

R1b

− Ib

Vout

+

FIGURE 15.8 A weighted summer.

R2 V1

R2

R1 −

V1

R1

V2

R1

−

Vout

V2 +

Vout

+ R2

(a)

(b)

FIGURE 15.9 Circuits for finding weighted differences: (a) a circuit based in the inverting and noninverting con­ figurations, (b) the differential configuration.

Multiple Input Circuits For the inverting configuration, the presence of the virtual ground at the op amp’s inverting input allow signals from many sources to be combined. As illustrated in Fig. 15.8, the currents Ia and Ib are determined independently by Va and Vb , respectively. These two currents are then summed at the virtual ground and forced through R2. The resulting output is a weighted sum of Va and Vb : Vout =

R2 R V − 2V R1a a R1b b

(15.13)

Any number of additional inputs can be added. The virtual ground prevents the different signals from interacting with each other. The noninverting input can also be used in the multiinput circuit. In this case though, the op amp’s input is no longer at virtual ground and its output ceases to be a weighted sum of the inputs. For example, if V1 and V2 are applied to the circuit of Fig. 15.9(a), the output depends on both V2 and the difference between V2 and V1: Vout = V2 +

R2 (V − V ) R1 2 1

(15.14)

This output can also be written as a weighted difference between V2 and V1  R  R Vout = 1 + 2  V2 − 2 V1 R1  R1 

(15.15)

If, as in Fig. 15.9(b), V2 is first attenuated by R2/(R1 + R2), a voltage only proportional to the difference between V1 and V2 can be obtained: © 2003 by CRC Press LLC

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Vout =

R2 (V − V ) R1 2 1

(15.16)

where it is evident that the circuit amplifies the difference between its inputs and rejects the common mode component. Consequently, the configuration is referred to as the differential configuration. Instrumentation Amplifiers The differential amplifier depicted in Fig. 15.9(b) is useful for detecting weak signals in a noisy environ­ ment. Unfortunately, its input resistance is only 2R1. To circumvent this problem, V1 and V2 can be buffered using two unity gain buffers. A better solution is to use the instrumentation amplifier illustrated in Fig. 15.10. This circuit combines two circuits of the type shown previously in Fig. 15.9(a) and the differential amplifer in Fig. 15.9.(b). Based on (15.15), the voltage at Va will be  R  R Va = 1 + 2  V1 − 2 V 2 R R1  1

(15.17)

 R  R Vb = 1 + 2  V2 − 2 V 1 R1  R1 

(15.18)

and the voltage at Vb will be

With Va and Vb applied to the differential amplifier, the instrumentation amplifier’s output voltage will be Vout =

R2 (V − Va ) R1 b

(15.19)

Due to the op amp’s ideally zero output resistance, the differential amplifier’s low input resistance does not load the other two circuits. Hence, by substituting (15.17) and (15.18) for Va and Vb , respectively, the output voltage can be expressed as  2R  R Vout = 1 + 2  4 (V2 − V1 ) R1  R3 

(15.20)

which allows the difference between V1 and V2 to be either amplified or attenuated without loading the signal sources. Only one R1 exists, therefore, it can be made variable to allow for an easily adjustable gain. Due to their usefulness, instrumentation amplifiers are available in a single package from many manufacturers.

+

V1

Va

−

R3

R2 R1

−

+

FIGURE 15.10 An instrumentation amplifier. © 2003 by CRC Press LLC

R3

R2 −

V2

R4

+ Vb

R4

Vout

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This last circuit illustrates the two primary characteristics of op amps when used in a closed-loop negative feedback configuration. First, a virtual short exists between the op amp’s input terminals allowing a high impedance source to set the potential of a circuit node. Second, the op amp’s low output resistance allows op amp circuits to be connected together without altering their individual transfer functions. These two characteristics greatly simplify the analysis and design of circuits containing many op amps.

Comparators If the op amp is not used in a closed-loop, its output will be either high or low, depending on the polarity of the voltage between its inputs. This appears to make op amps suitable for comparing two closely spaced signal levels. In practice, it is usually better to use a circuit called a comparator for this application. Comparators are similar to op amps but have been specifically designed to operate in an open-loop circuit. The basic comparator compares the voltage levels at its two inputs. If the voltage at the positive input, in+, exceeds that at the negative input, in–, the comparator will generate a logic high. If the voltage at in– exceeds that at in+, a logic low will be produced. Often, complementary outputs are also provided. The logic high and low levels are set either by the manufacturer or by the user. Typically, the logic levels are compatible with common logic families such as TTL, CMOS, or ECL. The comparator’s primary objective is to provide the correct output level as fast as possible while op amps are usually used in a closed-loop configuration. To ensure closed-loop stability, most op amps require some form of compensation (see Section 15.2 and [3]), which reduces their speed and bandwidth. On the other hand, comparators are specifically designed for open-loop operation thereby, making them better suited for high-speed comparisons. The comparator is usually used as a threshold comparator and often has added hysteresis. When used as a threshold detector, a reference level is applied to one input and the signal is applied to the other input. The choice of inputs determines the output’s polarity. Circuits of this type are commonly employed as level detectors and in analog-to-digital converters (see Chapter 19). In many cases, the input signal contains noise that causes the comparator’s output to oscillate as the signal passes the threshold level. To avoid this problem, the use of positive feedback, as depicted in Fig. 15.11(a), is used to generate hysteresis, as depicted in Fig. 15.11(b). The resistor R3 is included to reduce the effects of the comparator’s bias currents (see the section on input bias currents). For this circuit, the level that causes the output to go low, VINL, is VINL = VREF + (VREF − VOH ) K

(15.21)

where VOH is the output-high level and K is the ratio of the resistors depicted in Fig. 15.11(b). The level that causes the output to go high, VINH, is VINH = VREF + (VREF − VOL ) K

(15.22)

where VOL is the output-low level. By adjusting the ratio K, the amount of noise immunity can be adjusted.

Vout R3 VREF Vin

R1

Vout

− +

VOL KR1

(a)

VOH

VINL

VINH

(b)

FIGURE 15.11 (a) A comparator with hysteresis and (b) its input–output relationship. © 2003 by CRC Press LLC

Vin

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R2 I2 Vin

R1

in− Vout

I1 in+

ii Ai ii

FIGURE 15.12 The inverting amplifier configuration implementated with a current op amp.

Other Op Amp Configurations As mentioned in the first section, the ideal op amp can be implemented in any of four possible config­ urations: a voltage amplifier, a current amplifier, a transimpedance amplifier, and a transconductance amplifier. When used in a closed-loop configuration with negative-feedback, all four of the ideal op amps behave the same. In particular, the virtual short circuit between the two inputs remains and the output is unaffected by loading. Consequently, op amps of all four types exist. Due to practical limitations, some configurations are better suited than others for particular applications. To illustrate that the ideal op amp’s configuration does not affect the performance of an op amp circuit, the inverting op amp circuit in Fig. 15.12 has been implemented with a current op amp. The ideal current op amp displays zero resistance between its input terminals. The output, which is a current source, has an infinite output resistance. Hence, the current op amp is the dual of the voltage op amp. The circuit’s output voltage can be found by summing the currents at the op amp’s input. Since there is a physical short between the two input terminals, the current through R1 will be I1 =

Vin R1

(15.23)

I2 =

Vout R2

(15.24)

while the current through R2 will be

and due to the op amp’s current gain, Ai , the op amp’s input current will be ii =

Vout Ai R2

(15.25)

The sum of Eqs. (15.23), (15.24), and (15.25) must equal zero. Therefore, Vout R =− 2 Vin R1

 1    1 + 1 Ai 

(15.26)

which for Ai = ∞ results in the same gain as that produced by the inverting configuration implemented with an ideal voltage op amp. More important, the current through R1 equals the current through R2 and the op amp’s input current goes to zero. Hence, even with the physical short between the op amp’s inputs, only a virtual short exists in the closed-loop circuit because no current flows between the two terminals. At the output, the infinite gain of the ideal current op amp ensures that the output stays at © 2003 by CRC Press LLC

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the value indicated by (15.26) even if a load is added to the output. Consequently, the ideal op amp’s closed-loop behavior is preserved independent of the op amp’s configuration. Current Op Amps Ideally, the current op amp acts as a current-controlled current source with an infinite current gain. In practical current op amps, the gain is relatively low. Therefore, the assumption of an infinite gain is unrealistic for most applications. The primary purpose of current op amps is to boost the output current of a voltage op amp (see Section 15.2). Transimpedance Op Amps The ideal transimpedance op amp is a current-controlled voltage source with an infinite transimpedance gain. Op amps of this type are commonly referred to as current feed­ back op amps. Practical implementations of transimped­ ance op amps typically display a much higher speed than most voltage op amps (see Section 15.3 and [4]). Due to practical considerations, transimpedance op amps typically have a unity gain buffer between the noninverting and inverting input terminals as illustrated in Fig. 15.13. The added buffer has no effect on the ideal closed-loop performance, but it does increase the input resistance of the noninverting input for practical circuits.

in−

ii Vout

in+

1

Rm ii

+ −

FIGURE 15.13 A practical transimpedance op amp.

Transconductance Op Amps The ideal transconductance op amp is a voltage-controlled current source with an infinite transconduc­ tance gain. Practical transconductance op amps are usually implemented in MOS technologies [5]. MOSFET’s themselves are voltage-controlled current sources. Because a practical transimpedance op amp has a less that infinite output resistance, it is not suited for driving resistive loads. This does not pose a problem because most transimpedance op amps are used in switched-capacitor circuits, where they are used to drive capacitive loads.

Summary The ideal op amp is a high gain circuit element. When used in an open-loop configuration, the op amp can be used to compare closely spaced signal levels. It is generally much more useful when negative feedback is applied to control its output. With negative feedback, the differential voltage at its input approaches zero and the current between its input approaches zero. This makes it particularly useful for controlling the voltage or current in a circuit without drawing power from the controlling source. The ideal op amp model, although only approximated in practical op amps, is very useful for quickly analyzing and understanding the operation of larger circuits. Once the circuit’s behavior is understood, the effects of the op amp’s nonidealities can be considered.

References [1] A. S. Sedra and K. C. Smith, Microelectronic Circuits, 3rd ed., New York: Holt, Rinehart & Winston, 1991. [2] D. Sheingold, “Op amps and their characteristics,” in Analog Circuit Design, J. Williams, Ed., New York: Reed, 1991, ch. 30. [3] J. K. Roberge, Operational Amplifiers: Theory and Practice, New York: John Wiley & Sons, 1975. [4] E. Bruun, “Feedback analysis of transimpedance operational amplifier circuits,” IEEE Trans. Circuits Syst., vol. 40, pp. 275–278, pt. 1, Apr. 1993. [5] R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits, New York: John Wiley & Sons, 1986. © 2003 by CRC Press LLC

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15.2 The Nonideal Operational Amplifier David G. Nairn Practical op amps differ significantly from the ideal op amp. These differences limit the signal levels and range of impedances that can be used in op amp circuits. Fortunately, the nonidealities are only significant in certain applications. For these applications, circuit design precautions often reduce the effects of the nonidealities to acceptable levels. Alternatively, higher performance op amps can be used. The op amp’s dominant nonidealities, how they affect various applications, and techniques to compensate for their detrimental effects are discussed in the following sections.

Finite Differential Gain The op amp’s most critical nonideality is its finite gain. Unlike the infinite gain of the ideal op amp, the gain of a practical op amp is typically large at dc and decreases at high frequencies. Most op amps are internally compensated for a frequency dependent gain of the form vo AO = v i 1 + jω( AO ωt )

(15.27)

where AO , is the dc differential open-loop gain, ω is frequency, and ωt is the op amp’s unity gain frequency. Unity gain frequencies are typically in the MHz range. At low frequencies, the op amp’s gain simply becomes AO . At high frequencies, the op amp’s gain can be approximated as v o ωt = v i jω

(15.28)

Further details on the amp’s high-frequency behavior will be discussed in Section 15.3. The dc gain, AO , is typically quite large, hence it is usually expressed in decibels (dB). AO ranges from 40 dB for highspeed op amps to 120 dB for high precision op amps. General-purpose op amps usually have differential gains in the 100 dB region. Because AO is subject to wide variations, manufacturers usually specify a minimum and typical value. The op amp’s finite AO reduces the closed-loop gain of most op amp circuits. To illustrate the problem, the noninverting and inverting amplifiers shown in Fig. 15.14 can be analyzed assuming a finite op amp gain. The finite gain results in a nonzero differential voltage at the op amp’s input: vd =

vo AO

(15.29)

Consequently, the voltage at the inverting input is not equal to that at the noninverting input. Hence, the voltage across R1 and the current through it is changed. By equating the current in R1 and R2, it is seen that the non-inverting amplifier’s gain is reduced to i2 i1 R1

R2 − − vo A = Ao AO + + vi

(a)

i2 i1 vo

vi R1

R2 − − vo A = Ao AO + +

vo

(b)

FIGURE 15.14 Analysis of the noninverting (a) and inverting (b) configurations for an op amp with finite gain AO . © 2003 by CRC Press LLC

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Vo /Vi )) 1 + R2/R1 (20log (

Gain Deviation

Operational Amplifiers

0dB −0.09dB −10dB

−0.83dB

−6.02dB −20.8dB

−20dB 0.001 0.01 0.1 Desired closed-loop gain Op amp open-loop gain

1.0 10 1 + R2/R1 ( ) A0

FIGURE 15.15 Gain deviation for the noninverting configuration caused by a finite AO .

vo 1 + R2 R1 = v i 1 + (1 + R2 R1 ) AO

(15.30)

while the inverting amplifier’s gain is reduced to vo −R2 R1 = v i 1 + (1 + R2 R1 ) AO

(15.31)

For large values of AO , (15.30) and (15.31) reduce to the gains that would be obtained with an ideal op amp (i.e., vo /vi = 1 + R2 /R1 and vo /vi = –R2 /R1, respectively). It is only when AO and the desired closed-loop gain become comparable that the op amp’s finite gain leads to a significant reduction in the closed-loop gain. To illustrate this problem, the gain deviation for the noninverting amplifier versus (1 + R2 /R1)/AO is plotted in Fig. 15.15. Because AO is subject to wide variations, only gains that are at least 100 × lower than AO should be used to ensure a well-controlled gain. Consequently, the op amp’s finite open-loop differential gain places an upper limit on the closedloop gain that can be provided accurately.

Output Saturation Although op amps can provide high gains, the op amp’s maximum output voltage and current are limited. The maximum output voltage is limited by the op amp’s supply voltages, while the maximum output current is usually limited by the op amp’s allowable power dissipation. The op amp, similar to any electronic amplifier, requires a dc power supply. Most op amps require a positive, V +, and a negative, V –, power supply. Because V + and V – are typically the same size and of opposite polarity, they are referred to as dual or split supplies. Usually, the op amp has no connection to ground. The supply voltage typically ranges from ±5 V to ±18 V, with ±15 V being the most common. Specialpurpose op amps include low-voltage/low-power op amps for use with lower supply voltages, high-voltage op amps for use with supply voltages beyond ±18 V and single supply op amps for use with a single supply. Regardless of the op amp type, the maximum L+ and minimum L– output voltages cannot exceed the supply voltages. Typically, the output saturates within 1 to 3 volts of the supplies as shown in Fig. 15.16. Low-voltage op amps often feature a “rail-to-rail” output swing that allows the output signal to extend to both V + and V –. Due to the op amp’s limited output swing, the input signal must be kept small enough to avoid distortion caused by clipping the output signal. The second limitation on the op amp’s output signal is the op amp’s maximum output current specification. This limitation is determined by the maximum allowed power dissipation of the op amp. If the power dissipation limit is exceeded, the resulting temperature rise can damage the device. The worst case power dissipation usually occurs when the op amp has a load resistance of zero (i.e., the output © 2003 by CRC Press LLC

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vO Output Range L+

L+ IO (MAX)

RL (min) =

V+

IO L−

V−

−IO (MAX)

IO (MAX)

FIGURE 15.16 Voltage and current limitations on the op amp’s output signal swing.

is shorted to ground). In this situation, the full supply voltage appears across the op amp’s output stage and the power dissipation is PDisp = V + IO + PQ

(15.32)

PQ is the op amp’s quiescent power dissipation and usually much smaller than V+IO . Hence, to avoid an excessive temperature rise, IO must be limited to a safe value, IO(MAX). Many op amps are designed with short-circuit protection that limits IO(MAX) to a safe level. For general-purpose op amps, IO(MAX) is in the 20-mA range. The limitations imposed by the combination of L+, L–, and IO(MAX) are illustrated in Fig. 15.16. For loads below RL(min): RL ( min) = L+ / IO( MAX)

(15.33)

the op amp’s output swing will be limited by the op amp’s current limiting circuitry. For large values of RL, the signal swing will be limited by the op amp’s maximum and minimum output voltages. Therefore, to ensure that the signal peaks are not clipped, the equivalent load resistance seen by the op amp must be greater than RL(min) and the amplifier’s input signal must be small enough to ensure the output voltage will not exceed either L+ or L–.

Offset Voltage For an ideal op amp, a zero differential input voltage produces a zero output voltage. For a practical op amp, as illustrated in Fig. 15.17, a zero differential input voltage will, in general, produce a nonzero output. Due to the op amp’s high gain, the output will usually saturate at either L+ or L– if no feedback is applied. To obtain a zero output voltage, a nonzero input voltage, defined as the input offset voltage, VOS , must be applied between the input terminals. vO

vd

− +

VOS

− +

L+ Slope = AO

+ vo −

vd

L−

FIGURE 15.17 Transfer function of a practical op amp illustrating AO , L+, L–, and VOS . © 2003 by CRC Press LLC

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Cf R2 R1

−

vo

vi

R1

Rf

−

vo

+ +

VOS VOS (a)

(b)

FIGURE 15.18 Some circuits affected by the op amps offset voltage. (a) The inverting and noninverting configu­ rations. (b) Integrator circuits.

VOS is generally quite small. It arises from small mismatches in the devices used in the op amp’s input stage and circuit asymmetries. General-purpose op amps have offset voltages in the 0.1–10 mV range. Typically, op amps with FET input devices will have higher offset voltages than op amps with bipolar input devices. If a very low VOS is required, precision and low offset voltage op amps are available with offset voltages in the µV range. The offset voltage is not constant, it is subject to drift with time and changes in temperature. Consequently, its effects will be evident in most circuits. To analyze the effect of VOS , a voltage source of unknown polarity, equal to VOS is connected to one of the inputs of a ideal op amp. Then, using superposition, the circuit’s output voltage due to VOS and the input voltage can be determined. Because superposition applies, the effect of VOS on both the inverting and noninverting configurations is identical. As illustrated in Fig. 15.18(a), in which a practical op amp has been replaced with an ideal op amp in series with VOS , and vi set to zero, the output vo , due to VOS alone (i.e., the output offset voltage) is v o = VOS (1 + R2 R1 )

(15.34)

where it is evident that large dc gains result in a large output offset voltage. If dc gain is not required, a capacitor can be placed in series with R1 to reduce the dc gain to unity. The resulting output offset voltage then becomes VOS . Another group of circuits affected by VOS are integrating circuits such as the one in Fig. 15.18(b). If Rf is not included, VOS causes a dc current VOS /RI to flow through R1 and be integrated on Cf thereby causing the output voltage to saturate. Adding Rf limits the dc gain and hence, limits the output offset voltage. In situations where the smallest possible VOS is required, low VOS op amps can be used. Alternatively, many op amps are provided with one or two terminals to which an offset nulling circuit can be attached. The op amp’s VOS can then be trimmed to zero. Because the trimming can only be done for one temperature, VOS will still drift due to temperature and time and hence will limit the circuit’s dc accuracy.

Finite CMRR and PSRR If an op amp’s inputs are shorted together, as depicted in Fig. 15.19, variations in any one of the three voltages; vcm , the common-mode input voltage, V +, the positive supply voltage, or V –, the negative supply voltage, should not affect the output voltage. Nevertheless, if all three voltages are changed by the same amount, it is evident that the output voltage must also change by the same amount [3]. Hence, the op amp’s output voltage will be affected by changes in vcm, V + and V –. The relationship between changes in vcm and vo is usually characterized by the common-mode rejection ratio, CMRR. The effects of changes in the positive and negative supplies on vo are usually referred to as the power supply rejection ratios, PSRR+ and PSRR–, respectively. © 2003 by CRC Press LLC

V+ v−in + vcm −

− vo

v+in

+ V−

FIGURE 15.19 The op amp with its various input voltages.

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Common-Mode Rejection Ratio The op amp has two input terminals, therefore, two signal types exist: differential signals and commonmode signals. Referring to Fig. 15.19, the differential signal vd is the difference between the two input voltages, vin+ and vin– : + – v d = v in − v in

(15.35)

while the common-mode signal vcm is their average:

(

)

+ – v cm = v in + v in 2

(15.36)

Ideally, the op amp rejects (i.e., does not respond to) common-mode signals. For practical op amps, changes in vcm lead to changes in vo , resulting in a common-mode gain Acm : Acm =

vo v cm

(15.37)

Over a specified range, known as the common-mode range, Acm is relatively small. Beyond the commonmode range, Acm rises rapidly and the op amp ceases to function properly. Typically, the common-mode range does not extend to either the positive or negative supply. Single-supply op amps, however, are usually designed to have a common-mode range that extends down to and often slightly below the lower supply. Within the common-mode range, Acm is usually specified by the common-mode rejection ratio CMRR =

Ao Acm

(15.38)

The CMRR is usually expressed in decibels (dB) CMRR = 20 log

Ao Acm

(15.39)

and ranges from 60 dB to over 120 dB. An alternate interpretation of the CMRR is the ratio of a change in vcm to the resulting change in the op amp’s VOS . CMRR =

Vcm VOS

(15.40)

The two interpretations of CMRR are equivalent. A finite CMRR affects those circuits for which a sizable vcm is applied to the op amp. Hence, the inverting configuration, with a virtual ground at its input, is unaffected by the common-mode gain. On the other hand, circuits such as the noninverting configuration and the differential configuration in Fig. 15.20, have a nonzero vcm and hence display common-mode problems. The effects of a common-mode signal can be determined a follows. Because a finite CMRR can be interpreted as a change in the op amp’s VOS , due to the presence of a vcm , the VOS due to the nonzero vcm and the finite CMRR can be found as VOS = v cm CMRR

(15.41)

Then, the effect of the resulting VOS can be found by analyzing the op amp assuming the common-mode gain is zero. For example, the noninverting circuit in Fig. 15.20(a), has a vcm approximately equal to vi , which leads to an equivalent VOS of © 2003 by CRC Press LLC

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R2

R1

− vi

v2

R1

v1

R1

vo

+

R2 −

vo

+

R2 (a)

(b)

FIGURE 15.20 Some op amp circuits affected by a finite CMRR. (a) The noninverting configuration. (b) The differential configuration.

VOS = v i CMRR

(15.42)

v o = v i (1 + 1 CMRR)(1 + R2 R1 )

(15.43)

and a total output voltage of

Consequently, the CMRR leads to a gain error. For the differential configuration in Fig. 15.20(b), a finite CMRR leads to an output voltage of the form vo =

R2 (v − v ) + R2 v 1 R1 1 2 R1 CMRR

(15.44)

where if (v1 + v2)/2  v1 – v2, vi will be approximately equal to the signal’s common-mode voltage and it can be seen that the differential amplifier responds to both the differential and common-mode com­ ponents of the signal. Consequently, the op amp’s CMRR can lead to problems if both of the op amp’s terminal potentials vary with the input signal. Power Supply Rejection Ratio Ideally, changing either or both of an op amp’s power supplies should not effect the op amp’s performance. Practical op amps though, display a power-supply dependent gain and at higher frequencies, powersupply fluctuations are coupled into the op amp’s signal path, leading to variations in the output voltage. These problems can be characterized as an equivalent gain, AV+ and AV– from V + and V – terminals, respectively, to the output. Alternatively, the variation can be characterized as a power supply dependent variation in the op amp’s equivalent input offset voltage. Because the op amp is only supposed to amplify differential signals applied to its input, and reject signals applied to the power supplies, it is desirable to have AO  AV+ and AO  AV– . To measure this performance, the power-supply rejection ratios are used: PSRR + =

AO AV +

(15.45)

PSRR − =

AO AV −

(15.46)

Usually, the PSRRs are expressed in decibels (dB) PSRR + = 20 log

© 2003 by CRC Press LLC

AO AV +

(15.47)

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PSRR − = 20 log

AO AV −

(15.48)

PSRR’s of 60 to 100 dB are common at dc. At higher frequencies, the PSRR decreases. A noninfinite PSRR may pose a problem if there are variations in the power-supply voltages. Such variations can arise from either the ripple voltage of the supply itself or from large variations in the current being drawn from the supply. To reduce unwanted variations in the op amp’s output voltage, either an op amp with a better PSRR can be selected or power supply decoupling capacitors can be used. If decoupling capacitors are used, they should be placed as close as possible to the op amp’s power supply terminals. Finite Input Impedance and Nonzero Output Impedance Unlike the ideal op amp, practical op amps exhibit a finite input impedance and a nonzero output imped­ ance. The input impedance is composed of a differ­ ential and a common-mode component as illustrated Cicm/2 2Ricm + in Fig. 15.21 Rid and Cid represent the equivalent resis­ Ro Rid vd Cid tance and capacitance seen between the op amp’s two − Advd + input terminals. Ricm and Cicm represent the total resis­ − Cicm/2 2Ricm tance and capacitance to ground that would be seen by a common-mode signal applied to both input ter­ minals. Rid ranges from 100 kΩ to over 100 MΩ. The higher differential input resistances are found in op amps employing FET input stages. Ricm is typically FIGURE 15.21 Input and output impedance of two orders of magnitude higher than Rid. The input practical op amp. capacitances are generally in the picofarad range. The output resistance Ro is usually in the 50–100 Ω range. Generally, the use of negative feedback reduces the effects of these impedances to levels where they can be neglected. Nevertheless, problems can arise in some applications. The noninverting configuration is often used as a buffering amplifier due to its high input resistance. At low frequencies, the op amp’s input capacitances can be neglected and the negative feedback provided by the op amp’s high gain keeps the voltage across and the current through Rid negligible. Hence, the effective input resistance is approximately 2Ricm . At high frequencies, Cid shorts the input and the op amp’s decreasing gain causes the voltage across and hence, the current through Rid to increase resulting in a significantly decreased input impedance. Most op amps employ shunt sampling negative feedback, so the op amp’s effective output resistance is reduced. Hence, even relatively high values of Ro can be tolerated in most circuits. Nevertheless if the circuit is used to drive a capacitive load, problems can arise. Because the op amp’s gain decreases at higher frequencies (see “Finite Differential Gain” in this section), the amount of negative feedback also decreases leading to an output impedance that appears inductive (i.e., increases with frequency). This can be found by analyzing the output impedance of the circuit in Fig. 15.22(a). Approximating the op amp’s gain as (see “Finite Differential Gain”) A=

wt jw

(15.49)

and assuming that Ro  R1 + R2, the output impedance becomes Z out ≈ Ro jwLeff

© 2003 by CRC Press LLC

(15.50)

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R2

R2 R1

Vin

R1

Ro

− vd

Rout

Ad vd + − + (a)

Cc

− +

Rc

Vout

(b)

FIGURE 15.22 (a) Determining Rout for the inverting and noninverting configurations; (b) Compensating for large capacitive loads.

where Leff =

Ro  R1 + R2  wt  R1 

(15.51)

Consequently, if the circuit drives a large capacitor, it may become unstable due to the presence of Leff . To reduce this problem, a compensation network as illustrated in Fig. 15.22(b) is commonly used.

Input Bias Currents When operating, a current flows in each of the op amp’s input leads as depicted in Fig. 15.23. These input currrents, which are due to the internal structure of the op amp, give rise to errors in many circuits and prevent the practical realization of some circuit configurations. Because these currents cannot be avoided, they should be considered when designing op amp circuits. The input currents are determined by the devices used to implement the amplifier’s input stage. If BJT’s are used, their base currents determine the input currents. If FET’s are used, the input currents are due to the gate leakage current. In either case, the average of the two input currents, IB1 and IB2 is referred to as the input bias current, IB : I B = ( I B1 + I B 2 ) 2

−

+

IB1 vo IB2

FIGURE 15.23 An op amp showing its input bias currents.

(15.52)

where IB1 and IB2 are the input currents that cause the op amp’s output to go to zero with a zero commonmode input voltage. IB can range from 0.1 pA to 1 µA, which is much higher than would be expected based on the amplifier’s finite input resistance alone. Typically, op amps with FET inputs display a much lower IB than their bipolar counterparts. Due to mismatches, IB1 and IB2 are rarely equal. Their difference, referred to as the input offset current, IOS is defined as IOS = I B1 − I B 2

(15.53)

IOS is typically an order of magnitude lower than IB . Therefore, in all but the most critical applications, IOS can be neglected. The effects of nonzero bias currents on both the inverting and noninverting configurations are illustrated in Fig. 15.24(a). If IB is not compensated for, both op amp configurations will display an output voltage of vO = I B1R2

© 2003 by CRC Press LLC

(15.54)

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IB1 − I1

R2 i1 = 0

−IB1 R2 +

IB1

−

+ 0V −

R1

i1 ≠ 0 vo

+

IB2

IB1 −

R1 vcm = IB2 R3 R3 = R2//R1

vo = IB1 R2

R2

vo

+ IB2 vo = R2 (IB1 − IB2) (b)

(a)

FIGURE 15.24 Analysis of the inverting and noninverting configurations with nonzero IB. (a) Without bias current compensation; (b) with bias current compensation.

This voltage can be reduced either by reducing R2 or by selecting an op amp with lower bias currents. Alternatively, a resistor R3 equal to the parallel equivalent of R2 and R1 can be included in the positive terminal’s lead, as illustrated in Fig. 15.24(b). This added resistor causes the voltage at the op amp’s input to be equal to v cm = −I B 2 R1 R2

(15.55)

which, if two bias currents are equal (IOS = 0), causes vO to be zero. For the practical case of a nonzero offset current, vO becomes vO = IOS R2

(15.56)

Because IOS is usually much lower than IB , the error is greatly reduced. It is important to note that IB is a dc current. Hence, R3 should be equal to the equivalent dc resistance seen by the op amp’s negative terminal. All op amps require an IB for proper operation, therefore, a dc path between each input terminal and ground must be provided. For example, the ac coupled buffer of Fig. 15.25(a) requires the addition of Ri to provide a path for IB2. Unfortunately, Ri decreases the buffer’s input resistance. In Fig. 15.25(b), the difference between IB1 and IB2 R3 /R1 will flow to Cf , quickly leading to saturation of op amp’s output at either L+ or L–. By adding Rf , a dc path for the difference current is provided. Unfortunately, Rf makes the integrator nonideal at low frequencies. Consequently, the op amp’s bias currents restrict the dc accuracy and the frequency range of applications for op amp circuits. Cf Rf −

Ci vi

+

vo

R1

−

vo

+ R3

Ri (a)

(b)

FIGURE 15.25 Some op amp circuits affected by the op amp’s bias current. (a) The ac coupled buffer. (b) The inverting integrator. © 2003 by CRC Press LLC

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1000

100  en

Noiseless Op Amp  en (nV/√Hz)

 en

+

 in2

100

10 − in

10

1 10Hz (a)

fc 1

100Hz 1kHz Frequency (b)

− in (pA/√Hz)

−

 in1

0.1 10kHz

FIGURE 15.26 (a) Noise model of the op amp. (b) Input noise voltage and current densities versus frequency.  er2

R2 Source  er1  er2  in1  in2  en  ers

R1  er1 RS  ers

 in1  en

−

vo

+

 in2

vs

Output × √Hz  er1 (R2/R1)  er2  in1 R2  in2 RS (1 + R2/R1)  en (1 + R2/R1)  ers (1 + R2/R1)

FIGURE 15.27 An op amp circuit showing its noise sources.

Electrical Noise Similar to any electronic component, op amps generate noise that can degrade the system’s signal-to­ noise ratio (SNR). The amplifier’s noise is characterized by the equivalent noise sources in Fig. 15.26(a). – – – en is the equivalent input noise voltage density and is expressed in nV/ Hz.i n1 and i n2 are the equivalent – – input noise current density and are expressed in pA/ Hz. Usually, i n1 and i n2 have the same magnitude – – – and are both referred to as i n . The typical behavior of en and i n are illustrated in Fig. 15.26(b). At higher – frequencies, en and in are independent of frequency (i.e., white noise). In this range, values of en and – i n range from 50 nV/ Hz and 0.6 pA/ Hz, respectively, for general-purpose op amps to 2 nV/ Hz and 10 fA/ Hz for ultra low-noise op amps. At low frequencies, op amps display noise that increases with decreasing frequency (i.e., 1/f noise). To specify the low frequency noise, a plot such as the one in Fig. 15.26(b) may be provided. In some cases, only the noise corner frequency fc (see Fig. 15.26(b)) may be specified. To determine the effects of the op amp’s noise, the circuit in Fig. 15.26 can be used. The noise sources are generally uncorrelated, so the total noise is the square root of the sum of the square of each noise source acting independently. Therefore, the first step is to identify all the noise sources, as illustrated in Fig. 15.27. Each resistor may be modeled as a noiseless resistor in series with a noise voltage density of er = 4kTR

Hz

(15.57)

where k is Boltzmann’s constant and T is absolute temperature. Each noise source then gives rise to the output values shown in the table. The designer is free to choose R1 and R2, so the noise sources

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Increasing Noise

 in2 RS /√Hz  einput

√4kTRS /√Hz  en /√Hz

Increasing RS

FIGURE 15.28 The effect of RS on the total noise for the circuit of Fig. 15.26(a).

– –

–

en , ers , and i n2 typically determine the circuit’s total output noise voltage. The total rms white noise voltage at the output is 2

v output =

2

 R   R   R  π 2 BW e N2 1 + 2  + ers2 1 + 2  + in2 Rs 1 + 2  2 R1  R1  R1    

2

(15.58)

where BW is the op amp’s closed-loop bandwidth (see Section 15.3). The factor π/2 converts the closedloop bandwidth to the noise equivalent bandwidth, assuming the op amp is characterized by a single pole. The equivalent voltage white-noise density at the input is 2 e input = en2 + 4kTRS + in2 RS2

Hz

(15.59)

The relative importance of each of these three factors depends on the value of Rs as shown in Fig. 15.28. – – For low values of RS , en dominates. At high values of RS , i n2 dominates. In the middle region, RS dominates if 4kT > i n e n . Two measures are used to specify the circuit’s noise performance: the SNR and the noise figure (NF). The SNR is the ratio of the signal power to the total noise power, which assuming only white noise is present, can be expressed as SNR = 20 log

vs

e input

(πBW)

2

(15.60)

The second measure, NF, expresses the increase in noise due to the amplifier over that due to the source resistance alone: NF = 10 log

2 2 en2 + ers2 + in1 RS

ers2

(15.61)

Although a low NF is desirable, it is usually more important to minimize the total noise to achieve the highest possible SNR.

Summary Practical op amps suffer from a wide range of nonidealities. The dominant effect of these nonidealities is to limit the range of applications for which an op amp can be used. Problems such as the offset voltage, the CMRR, the bias currents, and the electrical noise will limit the accuracy of op amp circuits. The op amp’s finite gain and saturation levels will limit the maximum controllable gain of an op amp circuit. Factors such as the op amp’s saturation limits and its input and output impedances will limit the range © 2003 by CRC Press LLC

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of impedances that can be buffered by or driven by an op amp. In many cases, circuit techniques or special-purpose op amps can be used to reduce the detrimental effects of the op amp’s nonidealities.

References [1] E. J. Kennedy, Operational Amplifier Circuits: Theory and Applications, New York: Holt, Rinehart and Winston, 1988. [2] J. K. Roberge, Operational Amplifier: Theory and Practice, New York: Wiley, 1975. [3] E. Säckinger, J. Goette, and W. Guggenbühl, “A general relationship between amplifier parameters, and its application to PSRR improvement,” IEEE Trans. Circuits Syst., vol. 38, pp. 1173–1181, Oct. 1991. [4] A. S. Sedra and K. C. Smith, Microelectronic Circuits, 3rd Ed., New York: Holt, Rinehart and Winston, 1991.

15.3 Frequency- and Time-Domain Considerations Sergio Franco One of the most important limitations of practical op amps is gain rolloff with frequency. This limitation affects both the frequency-domain and the time-domain behavior of circuits built around op amps. We have linear effects, such as finite small-signal bandwidth and nonzero rise time, and nonlinear effects, such as slew-rate limiting and finite full-power bandwidth. Additional effects are the settling time and intermodulation distortion. We discuss these limitations both for voltage-mode and current-mode op amps [1].

Voltage-Mode Op Amps Conventional op amps, the most popular representative of which is without doubt the 741 type, are voltage-mode amplifiers because in order to produce an output they require an input imbalance of the voltage type. Consequently, when a negative feedback loop is created around the op amp, the signal returned to the input must be in the form of a voltage.

Block Diagram Shown in Fig. 15.29 is a simplified circuit diagram [2] that can be used to describe a wide variety of practical voltage-mode op amps, including the popular 741. As illustrated in block-diagram form in Fig. 15.30, the circuit is made up of three stages. 1) The input stage, consists of transistors Q1 through Q4, whose function is to sense any imbalance between the inverting and noninverting input voltages Vn and Vp, and convert it to a single-ended output current Io1. This stage is also designed to provide high input impedance and draw negligible input currents. Q1 and Q2 form a differential pair whose task is to split the bias current IA into two currents I1 and I2 in amounts controlled by the imbalance between Vn and Vp . If this imbalance is sufficiently small, we can write I1 – I2 = gm1(Vp – Vn), where gm1 is the transconductance of Q1 and Q2. Ignoring transistor base currents, we have I3 = I1. In response to current I3, Q3 develops a base-emitter voltage drop that is then applied to Q4 , forcing the latter to draw the same amount of current as the former, or I4 = I3. For obvious reasons, Q3 and Q4 are said to form a current mirror. Summing currents, we obtain Io1 = I2 – I4 = I2 – I3 = I2 – I1, or

(

)

I o1 = −g m1 Vp − Vn = −g m1 V d where Vd = Vp – Vn is called the differential input voltage. © 2003 by CRC Press LLC

(15.62)

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Vcc

IA

IB Q7 D1 Q2

Q1

Vn

I1

I2

I3

I4

Vp

Vo

D2 Q8

I01

Cc Q5

Q3

Q6 Q4

VEE

FIGURE 15.29 Simplified circuit diagram of a voltage-mode op amp. Cc

Vp

+

Vn

−

Io1

−gm1

−av2 Req

×1

Vo

Ceq

FIGURE 15.30 Voltage-mode op amp block diagram.

2) The intermediate stage consists of Darlington pair Q5 – Q6 and frequency-compensation capacitance Cc. Its function is to provide additional gain as well as to introduce a dominant pole in the open-loop response of the amplifier. Denoting the net equivalent resistance and capacitance between the input node of this stage and ground as Req and Ceq , the pole frequency is fOL =

1 2πReqCeq

(15.63)

By the Miller effect we have Ceq = (1+av2)Cc , where –a v2 is the voltage gain of the Darlington pair. 3) The output stage consists of emitter–followers Q7 and Q8, and biasing diodes D1–D2. Though the voltage gain of this stage is only unity, its current gain can be fairly high, indicating that this stage acts as a power amplifier. Its function is also to provide a low output impedance. Q7 and Q8 are referred to as a push-pull pair because in the presence of an output load, Q7 sources (or pushes) current to the load, and Q8 sinks (or pulls) current from the load. The small-signal transfer characteristic of the op amp is Vo = AOL ( jf )Vd © 2003 by CRC Press LLC

(15.64)

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��

��

�� ��

�

��

� ���

��� � �

�

���

��

�

��

���

��

�� ���

−�� ������ −��

�

�� ��� ���

�

−��

�

FIGURE 15.31 Frequency plots of the open-loop gain.

where AOL(jf ), called the open-loop voltage gain, is a complex function of frequency f, and j = –1 is the imaginary unit. With dominant pole compensation, this function can be approximated as AOL ( jf ) =

AOL0 1 + jf fOL

(15.65)

where AOL0 and fOL are, respectively, the dc value and bandwidth of AOL( jf ). For the circuit shown, AOL0 = gm1 Req av2 . As an example, the popular 741 op amp has AOL0  2 × 105 V/V and fOL  5 Hz. Figure 15.31 shows the Bode plots of AOL(jf ). We make the following observations. 1) For f  fOL we have AOL (jf )  AOL0 and AOL (jf )  0° indicating an approximately constant gain and negligible delay. 2) For f = fOL we have AOL ( jf ) = AOL0/ 2 and AOL ( jf ) = –45°. Rewriting as AOL ( jf )dB = 20 log10AOL (jf ) = AOL0dB – 3 dB explains why fOL is also referred to as the –3 dB frequency or the halfpower frequency of the open-loop response. 3) For f  fOL gain rolls off with frequency at a constant rate of –20 dB/dec, and it can be approximated as AOL (jf )  AOL0/( f /fOL) and AOL (jf )  –90° Rewriting as AOL ( jf ) × f AOL0 × fOL = ft

(15.66)

indicates that in the rolloff region the op amp exhibits a constant gain-bandwidth product (constant GBP). Increasing frequency by a given amount causes gain to decrease by the same amount. The frequency ft = AOL0 fOL at which gain drops to 0 dB is aptly called the transition frequency. For the 741 op amp, ft = 2 × 105 × 5 = 1 MHz. Closed-Loop Frequency Response Figure 15.32 shows a simplified model of the voltage-mode op amp, along with external circuitry to create the popular noninverting configuration. The resistors sample Vo and feed the voltage R1 V = βVo R1 + R2 o

(15.67)

R1 1 = R1 + R2 1 + R2 R1

(15.68)

Vn = back to the inverting input. The parameter β=

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+ Vi

+

Vd −

Vo

+ AOL Vd

Vn R2 R1

FIGURE 15.32 The noninverting configuration.

representing the fraction of the output being fed back to the input is called the feedback factor. By inspection, Vo = AOL ( jf )Vd = AOL ( jf )(Vi − βVo )

(15.69)

In negative-feedback parlance Vd = Vi – βVo is referred to as the error signal. Collecting and solving for the ratio Vo /Vi yields, after minor algebraic manipulations, ACL ( jf ) =

Vo  R2  1 = 1+  Vi  R1  1 + 1 T ( jf )

(15.70)

where ACL(jf ) is called the closed-loop gain, and T ( jf ) = AOL ( jf )β =

AOL ( jf ) 1 + R2 R1

(15.71)

is called the loop gain. This designation stems from the fact that a voltage propagating clockwise around the loop is first magnified by AOL (jf ), and then attenuated by β, thus experiencing an overall gain of T(jf ) = AOL (jf )β. By (15.70) we have lim ACL = 1 +

T →∞

R2 R1

(15.72)

a value aptly called ideal closed-loop gain. Clearly, T provides a measure of how close ACL is to ideal: the larger T, the better. To ensure a substantial loop gain for a range of closed-loop gains, op amp manufac­ turers strive to make AOL as large as possible. Consequently, Vd will assume extremely small values since Vd = Vo /AOL. In the limit AOL→ ∞ we obtain Vd → 0, that is, Vn→ Vp. This provides the basis for the familiar ideal voltage-mode op amp rule: When operated with negative feedback, an op amp will provide whatever output is needed to drive its error signal Vd to zero or, equivalently, to force Vn to track Vp . Substituting (15.65) into (15.71) and then into (15.70), and exploiting the fact that βAOL0  1, we obtain, after minor algebra, ACL ( jf ) = © 2003 by CRC Press LLC

A CL0 1 + jf fCL

(15.73)

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dB AOL0 |AOL|

|T |

|ACL| |1/β|

ACL0 f, dec

0

fOL

fCL

ft

FIGURE 15.33 Graphical interpretation of the loop gain.

where ACL0 = 1 +

R2 1 = R1 β

(15.74)

ft ACL0

(15.75)

is the closed-loop dc gain, and fCL = βft =

is the closed-loop small-signal bandwidth. The quantity 1/β is also called the dc noise gain because this is the gain with which the amplifier will magnify any dc noise present right at its input pins, such as the input offset voltage VOS. Equation (15.75) indicates a gain-bandwidth trade-off. As we raise the R2/R1 ratio to increase ACL0, we also decrease fCL in the process. Moreover, by Eq. (15.71), T(jf ) is also decreased, thus leading to a greater departure of ACL( jf ) from the ideal. The above concepts can be visualized graphically as follows. By (15.70) we can write TdB = 20 log10 T  = 20 log10 AOL  – 20 log10 (1/β), or T dB = A OL dB − 1 β dB

(15.76)

indicating that the loop gain can be found graphically as the difference between the decibel plot of the open-loop gain and that of the noise gain. This is illustrated in Fig. 15.33. The frequency at which the two curves meet is aptly called the crossover frequency. It is readily seen that at this frequency we have T = 1 –90° = –j, so ACL  = ACL0/1 + j = ACL0 / 2, by (15.70) and (15.74). Consequently, the crossover frequency represents the –3 dB frequency of ACL(jf ), that is, fCL. We now see that increasing ACL0 reduces T and causes the cross-point to move up the AOL curve, thus decreasing fCL. The circuit with the widest bandwidth and the highest loop gain is also the one with the lowest closed-loop gain. This is the familiar voltage follower, obtained by letting R1 = ∞ and R2 = 0. Then, by (15.74) and (15.75) we have ACL0 = 1 and fCL = ft . Let us now turn to another important configuration, namely, the popular inverting amplifier of Fig. 15.34. Since Vp = 0, it follows that Vd = –Vn . Applying the superposition priniciple we have Vd = − © 2003 by CRC Press LLC

R2 R1 −R2 V− V = V − βV0 R1 + R2 i R1 + R2 0 R1 + R2 i

(15.77)

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dB |AOL|

AOL0 R1

Vn

R2 |T|

Vi

+

− Vo

+

|ACL|

|ACL0|

|1/β|

ft f, dec fOL

fCL

FIGURE 15.34 The inverting configuration.

indicating that the feedback factor β = R1/(R1+R2) is the same as for the noninverting configuration. Substituting into (15.64), we find the closed-loop gain as ACL ( jf ) =

V0  R2  1 = −  Vi  R1  1 + 1 T ( jf )

(15.78)

Moreover, proceeding as for noninverting configuration, we get ACL ( jf ) =

ACL0 1 + if fCL

(15.79)

R2 R1

(15.80)

where ACL0 = − is the closed-loop dc gain, and fCL = βft

(15.81)

is the closed-loop small-signal bandwidth. We can again find this bandwidth as the intercept of the AOL  dB and 1/βdB curves. However, since we now have ACL0  < 1/β, it follows that the ACL  dB curve will be shifted downward, as explicitly shown in Fig. 15.34. Before concluding, we wish to point out that open-loop gain rolloff affects not only the closed-loop gain, but also the closed-loop input and output impedances. The interested reader can find additional information in the literature [3]. Closed-Loop Transient Response To fully characterize the dynamic behavior of an op amp circuit we also need to know its transient response. This response is usually specified for the case of the op amp operating as a unity-gain voltage follower. As we know, its small-signal transfer characteristic is Vo = Vi /(1 + jf /ft ). This is formally similar to that of an ordinary RC circuit. Subjecting a voltage follower to a step of suitably small amplitude Vm , as shown in Fig. 15.35, will cause an exponential output transition with the time constant τ=

1 2πft

(15.82)

The rise time tr, defined as the time it takes for Vo to swing from 10 to 90 percent of Vm , provides a measure of how rapidly the transition takes place. One can readily see that tr = τ ln 9  2.2τ. For the 741 op amp we have τ = 1/(2p × 106)  159 ns, and tr  350 ns. © 2003 by CRC Press LLC

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Volts Vi Vm − +

Vi

Vo

Vo

+ 0

t τ

0

FIGURE 15.35 Voltage follower and its small-signal step response. Volts Vi Vm Vo SR 0

t

FIGURE 15.36 Large-signal response of the voltage follower. ���

��

� �

��

− ��

FIGURE 15.37 Actual transfer characteristic of the first stage.

The rate at which Vo changes with time is highest at the beginning of the exponential transition, when its value is Vm /τ. Increasing the step magnitude Vm increases this initial rate, until a point is reached beyond which the rate saturates at a constant value called the slew rate (SR). The transition is now a ramp, rather than an exponential. Figure 15.36 shows the slew-rate limited response to a pulse. Slew-rate limiting stems from the limited ability of the internal circuitry to charge or discharge the compensation capacitance Cc. To understand this effect, refer to Fig. 15.37. As long as the input imbalance Vd is sufficiently small, (15.62) still holds and the step response is exponential. However, for large values of Vd , Io1 is no longer linearly proportional to Vd , but saturates at ±IA , where IA is the input-stage bias current depicted in Fig. 15.29. Turning now to Fig.15.30 and observing that the second stage acts as an integrator, we can state that the maximum rate at which Cc can be charged or discharged is (dVo /dt)max = IA /Cc . This is precisely the slew rate, © 2003 by CRC Press LLC

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Volts Vi Vm Vo 0

t

−Vm

FIGURE 15.38 Distortion when the FPBW is exceeded.

SR =

IA Cc

(15.83)

The 741 op amp has typically IA = 20 µA and C =30 pF, so SR = 10 × 10–6/(30 × 10–12) = 0.67 V/µs. To respond to a 10-V input step a 741 follower will take approximately 10/0.67 = 15 µs. The step magnitude corresponding to the onset of slew-rate limiting in such that Vm /τ = SR, or Vm = SR × τ = SR/(2πft). For the 741 op amp, Vm = 0.67 × 106/(2π × 106) = 106 mV. This means that as long as the input step is less than 106 mV, a 741 follower will respond with an exponential transition governed by τ  159 ns. For a greater input step, however, the output will slew at a constant rate of 0.67 V/µs, and it will do so until it comes within 106 mV of the final value, after which it will complete the transition in exponential fashion. In certain applications it is important to know the settling time ts, defined as the time it takes for the output to settle within a specified band around its final value, usually for a full-scale output transition. It is apparent that slew-rate limiting plays an important role in the settling-time characteristic of a circuit. Slew-rate limiting affects also the full-power bandwidth (FPBW), defined as the maximum frequency at which the circuit still yields an undistorted full-power output. Letting Vo = Vm sin 2πft, we have (dVo /dt)max = (2πf Vm cos2πft)max = 2πf Vm . Equating it to the slew rate SR and solving for f, whose value is the FPBW, we get FPBW =

SR 2πVm

(15.84)

For instance, for Vm = 10 V, the 741 op amp has FPBW = SR/(20π) = 10.6 kHz. Figure 15.38 shows the distorted response of a voltage follower to a full-power input with a frequency higher than the FPBW. From (15.63) and (15.83) it is apparent that the primary cause of frequency and slew-rate limitations is the capacitance Cc. Why not eliminate Cc altogether? Without Cc the open-loop response would exhibit a much wider bandwidth, but also a much greater phase lag because of the various poles introduced by the transistors making up the op amp. We are interested in the situation at the crossover frequency, where T = 1. Should the phase shift at this frequency reach –180˚, we would have T = 1 –180° = –1 which, after substitution into (15.70), would yield ACL → (1 + R2/R1)/(1 – 1) → ∞! The physical meaning of an infinite closed-loop gain is that the circuit would be capable of sustaining a nonzero output with a vanishingly small external input. But, this is the recipe for sustained oscillation! It is precisely to avoid this possibility that the manufacturer incorporates the frequency-compensation capacitance Cc . As mentioned, Cc causes gain to roll off, so that by the time the frequency of –180˚ phase lag is reached, AOL has already dropped well below 0 dB, making it impossible for the circuits of Figs. 15.32, 15.34, and 15.35 to achieve T = –1 at the crossover frequency, regardless of the values of R1 and R2. This requires that the dominant-pole frequency be suitably low, and thus, by (15.63), that Ceq be suitably large. To avoid the need to manufacture impractically large on-chip capacitances, it is customary to start out with a realistic value, such as 30 pF for the 741 op amp, and then exploit the multiplicative action of the Miller effect to raise it to the desired equivalent value. © 2003 by CRC Press LLC

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VCC

Q6

Q5

Q13

Q1

Q9

I1

Q3

Q11

I1

In

In

Vn

Vp

Vo I2

Q12

Q4 I2

Q2

Q10 Q7

Q8

Q14

VEE

FIGURE 15.39 Simplified circuit diagram of a current-mode op amp.

The hardest configuration to compensate is the unity-gain voltage follower because its crossover frequency is the closest to the frequency region of additional phase lag stemming from the higher-order poles of the op amp. This is why this particular configuration is usually chosen for the specification of the transient response.

Current-Mode Op Amps Current-mode op amps exploit a special circuit topology, along with high-speed complementary bipolar processes, to achieve much faster dynamics than their voltage-mode amplifier counterparts. The name stems from the fact that these amplifiers respond to an input imbalance of the current type, and the signal propagating around the feedback loop is thus in the form of a current rather than a voltage. Block Diagram Figure 15.39 shows the simplified circuit diagram of a current-mode op amp. Referring also to Fig. 15.40, we identify three functional blocks. 1) The first functional block is a unity-grain input buffer, consisting of transistors Q1 through Q4. Q1 and Q2 form a low output-impedance push-pull stage, while Q3 and Q4 provide VBE compensation as well as a Darlington function to raise the input impedance. This buffer forces Vn to follow Vp , very much like a voltage-mode op amp does via negative feedback. When the op amp is embedded in a circuit, current can easily flow in or out of its low-impedance inverting-input pin, though we shall see that in the steady-state (nonslewing) condition this current approaches zero. The function of the buffer is to sense this current, denoted as In, and produce an imbalance I1 − I 2 = I n between the push–pull transistor currents I1 and I2. © 2003 by CRC Press LLC

(15.85)

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VCC Current mirror I1

Vp

×1

I1 In

In

×1

Vn

I2

Req

I2

Vo

Ceq

Current mirror VEE

FIGURE 15.40 Current-mode op amp block diagram.

2) The second block is a pair of current mirrors Q5 –Q6 and Q7 –Q8 , which reflect currents I1 and I2 and sum them at a common junction node. The current into this node thus equals In, as shown. 3) Finally, a unity-gain output buffer, consisting of transistors Q9 through Q12, buffers the summing node voltage to the outside and provides a low output impedance for the overall op amp. Denoting the net equivalent resistance and capacitance of the summing node towards ground as Req and Ceq, we can write Vo = Z OL ( jf )I n

(15.86)

where ZOL (jf ), called the open-loop transimpedance gain, is the impedance due to the parallel combination of Req and Ceq. This impedance can be expressed as Z OL ( jf ) =

Z OL0 1+ jf fOL

(15.87)

where ZOL0 = Req, and fOL =

1 2πReqCeq

(15.88)

As an example in Fig. 15.40, the CLC401 current-mode op amp (Comlinear Co.) has ZOL0  710 kΩ, fCL  350 kHz, and Ceq = 1(2πReq fOL)  0.64 pF. We observe a formal similarity with voltage-mode op amps, except that now the error signal In is a current rather than a voltage, and the gain ZOL( jf ) is in V/A rather than in V/V. For this reason currentmode op amps are also referred to as transimpedance op amps. Than gain ZOL( jf ) is approximately constant from dc to fOL, after which it rolls off with frequency at a constant rate of –1 dec/dec. Closed-Loop Characteristics Figure 15.41 shows a simplified model of the current-mode op amp, along with an external feedback network to configure it as a noninverting amplifier. Any attempt to unbalance the inputs will cause the input buffer to source (or sink) an imbalance current In to the external network. By (15.86), this imbalance © 2003 by CRC Press LLC

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+

Vi

1

+

+

Vo

−

ZOLIn

In

R2 R1

FIGURE 15.41 Noninverting configuration.

causes Vo to swing in the positive (or negative) direction until the original imbalance current is neutralized via the negative feedback loop. Exploiting the fact that the input buffer keeps Vn = Vp = Vi , we can apply the superposition principle and write In =

Vi V Vi − o = − βVo R1 R2 R2 R1 R2

(15.89)

Clearly, the feedback signal Vo /R2 is now a current, and the feedback factor β=

1 R2

(15.90)

is now in A/V. Substituting into (15.86) and collecting, we get ACL ( jf ) =

Vo  R2  1 = 1+  Vi  R1  1 + 1 T ( jf )

(15.91)

where ACL( jf ) is the closed-loop gain of the circuit, and T ( jf ) = Z OL ( jf )β =

Z OL ( jf ) R2

(15.92)

is the loop gain. This designation is due again to the fact that a current propagating clockwise around the loop is first multipled by ZOL (jf ) to be converted to a voltage, and divided by R2 to be converted back to a current, thus experiencing an overall gain of T(jf ) = ZOL(jf )/R2. To make ACL( jf ) approach the ideal value 1 + R2/R1, it is desirable that T(jf ) be as large as possible. To ensure a substantial loop gain over a range of closed-loop gains, manufacturers strive to maximize ZOL( jf ) relative to R2. Consequently, since In = Vo /ZOL , the inverting input-pin current will be very small, even though this is a low-impedance node because of the input buffer. In the limit ZOL → ∞ we obtain In → 0, indicating that a current-mode op amp will ideally provide whatever output is needed to drive In to zero. Thus, the familiar op amp conditions Vn → Vp , In → 0, and Ip → 0 hold also for current-mode op amps, though for different reasons than their voltage-mode counterparts. © 2003 by CRC Press LLC

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Current-Mode Op Amp Dynamics Substituting (15.87) into (15.92) and then into (15.91), and exploiting the fact that ZOL0 /R2  1, we obtain ACL ( jf ) =

ACL0 1 + jf ft

(15.93)

R2 R1

(15.94)

where ACL0 = 1 + is the closed-loop dc gain, and ft =

Z OL0 fOL 1 = 2πR2Ceq R2

(15.95)

is the closed-loop bandwidth. With R2 in the kΩ range and Ceq in the pF range, ft is typically in range of 108 Hz. We can again visualize T and ft graphically by noting that if we define Tdec = log10 T, then we have, by (15.92), T dec = log10 ZOL (jf ) – log10 R2 , or T dec = Z OL ( jf )

dec

− R2 dec

(15.96)

As shown in Fig. 15.42, we can visualize the loop gain as the difference between the decade plot of ZOL(jf ) and that of R2, with the latter now acting as the noise gain. Since at the crossover frequency we have T = 1 –90° = –j, (15.91) and (15.94) yield ACL = ACL0/ 2. Consequently, the crossover frequency represents the –3 dB frequency of ACL ( jf ), that is, ft . We are now ready to make two important observations. 1) Equation (15.95) shows that for a given amplifier the closed-loop bandwidth depends only on R2. We can thus use R2 to select the bandwidth ft via (15.95), and R1 to select the dc gain AOL0 via (15.94). The ability to set gain independently of bandwidth, along with the absence of gain-bandwidth trade-off, constitutes the first major advantage of current-mode over voltage-mode op amps, see Fig. 15.43. 2) The other major advantage of current-mode op amps is the absence of slew-rate limiting. To justify, suppose we apply an input step Vi = Vm to the circuit of Fig. 15.41. Referring also to Fig. 15.40, we note that the resulting current imbalance In yields an output Vo such that In = CeqdVo /dt + Vo /Req. Substituting into Eq. (15.89), rearranging, and exploiting the fact that R2/ZOL0  1, we get

Ω, dec ZOL0 |ZOL|

|T| |1/β| R2 f, dec fOL

FIGURE 15.42 Graphical interpretation of the loop gain. © 2003 by CRC Press LLC

ft

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Gain, V/V

Gain, V/V

100

100

10

10 f, dec

1 f100 f10

f, dec

1

ft

f1

FIGURE 15.43 Comparing the gain-bandwidth characteristics of voltage-mode (left) and current-mode (right) op amps.

R2Ceq

dVo + Vo = AOL0Vm dt

(15.97)

indicating an exponential output transient regardless of Vm. The time constant governing the transient is T = R2Ceq

(15.98)

and is set by R2, regardless of ACL0. For instance, a CLC401 op amp with R2 = 1.5 kΩ has τ = R2 Ceq = 1.5 × 103 × 0.64 × 10–12  1 ns. The rise time is tr = 2.2 τ  2.2 ns, and the settling time within 0.1 percent of the final value is ts  7 τ  7 ns, in reasonable agreement with the data-sheet values tr = 2.5 ns and ts = 10 ns. Higher-Order Effects The above analysis indicates that once R2 has been set, the dynamics are unaffected by the closed-loop gain setting. In practice it is found that bandwidth and rise time do vary with gain somewhat, though not as drastically as for voltage-mode op amps. The main cause is the nonzero output resistance Rn of the input buffer, whose effect is to alter the loop gain and, hence, the closed-loop dynamics. Referring to Fig. 15.44, we again use the superposition principle and write + 1 Vi

+

+

Vo

Rn −

ZOLIn

In

R2 R1

FIGURE 15.44 Investigating the effect of Rn. © 2003 by CRC Press LLC

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In =

Vi − βVo Rn + R1 R2

(15.99)

where the feedback factor is found using the current divider formula and Ohm’s law, β=

R1 1 1 × = R1 + Rn R2 + Rn R1 R2 + ACL0 Rn

(

(15.100)

)

Comparing with (15.90), we observe that the effect of Rn is to replace R2 with R2 + ACL0Rn. The 1/β curve of Fig. 15.42 will thus be shifted upward, leading to a decrease in the crossover frequency, which we shall now denote as fCL. This frequency is obtained by letting R2 → (R2 + ACL0 Rn) in (15.95), fCL =

Z OL0 fOL 1 = R2 + ACL0Rn 2π( R2 + ACL0 Rn )Ceq

(15.101)

As an example, suppose an op amp has Rn = 50 Ω, R2 = 1.5 kΩ, and ft = 100 MHZ. Then, (15.101) yields fCL = ft/(1 + ACL0 Rn/R2) = 108/(1 + ACL0/30). The bandwidths corresponding to ACL0 = 1 V/V, 10 V/V, and 100 V/V are, respectively, f1 = 96.8 MHZ, f10 = 75.0 MHZ, and f10 = 23.1 MHZ, and are shown in Fig. 15.45. The corresponding rise times are, respectively, t1 = 3.6 ns, t10 = 4.7 ns, and t100 = 15.2 ns. We note that the above bandwidth reductions still compare favorably with voltage-mode op amps, where the reduction factors would be, respectively, 1, 10, and 100. The values of R1 and R2 can be predistorted to compensate for the bandwidth reduction. Using (15.101) we find R2 for a given bandwidth fCL and dc gain ACL0, R2 =

Z OL0 fOL − ACL0 Rn fCL

(15.102)

and using (15.94) we find R1 for the given dc gain ACL0, R1 =

R2 ACL0 −1

(15.103)

As an example, suppose an op amp with ZOL0 fOL = 1.5 × 1011 Ω × Hz and Rn = 50 Ω is to be configured for ACL0 = 10 V/V and fCL = 100 MHz. Then, using (15.102) and (15.103) we find R2 = 1.5 × 1011/108 – 10 × 50 = 1 kΩ, and R1 = 103/(10 – 1) = 111 Ω.

Gain, V/V

100

f100

10

f10 f1

1 0.1

1

10

100

FIGURE 15.45 Bandwidth reduction for different gain settings.

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MHZ

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Though our analysis has focused on the noninverting configuration, we can readily extend our line of reasoning to other circuits such as the popular inverting configuration. The latter is obtained by grounding the noninverting input of Fig. 15.44, and applying the source Vi via the bottom lead of R1. The bandwidth is still as in (15.101), but the dc gain is now –R2/R1. The interested reader can consult the literature [1], [5] for additional current-mode op amp circuits as well as application hints. We conclude by pointing out that current-mode op amps, though exhibiting much faster dynamics than their voltage-mode counterparts, in general suffer from poorer input offset voltage and input bias current characteristics. Moreover, having much wider bandwidths, they tend to be noisier. There is no question that the circuit designer must carefully weigh both advantages and disadvantages before deciding which amplifier type is best suited to the application at hand.

Acknowledgment Parts of this chapter are based on the author’s article “Current feedback amplifiers benefit high-speed designs.” This article appeared in the Jan. 5, 1989 issue of EDN on pages 161–172. Cahners Publishing Company of Newton, MA has granted permission for its appearance.

References [1] S. Franco, “Current feedback amplifiers benefit high-speed designs,” EDN, Jan. 1989. [2] J.E. Solomon, “The monolithic operational amplifier: A tutorial study,” IEEE Journal of Solid-State Circuits, vol. SC-9, Dec. 1974. [3] S. Franco, Design with Operational Amplifiers and Analog ICs, 3rd ed., New York: WCB/McGrawHill, 2001. [4] D. Nelson and S. Evans, “A new approach to op amp design,” Comlinear Corp. Applicat. Note 300-1, Mar. 1985. [5] D. Potson, “Current-feedback op amp applications circuit guide,” Comlinear Corp. Applicat. Note OA-07, May 1988.

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16 High-Frequency Amplifiers 16.1 Introduction 16.2 The Current Feedback Op-Amp Current Feedback Op-Amp Basics • CMOS Compound Device • Buffer and CFOA Implementation

16.3 RF Low-Noise Amplifiers Specifications • CMOS Common-Source LNA: Simplified Analysis • CMOS Common-Source LNA: Effect of Cgd • Cascode CS LNA

16.4 Optical Low-Noise Preamplifiers Front-End Noise Sources • Receiver Performance Criteria • Transimpedance (TZ) Amplifiers • Layout for HF Operation

16.5 Fundamentals of RF Power Amplifier Design PA Requirements • Power Amplifier Classification • Practical Considerations for RF Power Amplifiers • Conclusions

16.6 Applications of High-Q Resonators in IF-Sampling Receiver Architectures

Chris Toumazou Alison Payne Imperial College, University of London

IF Sampling • Linear Region Transconductor Implementation • A gm-C Bandpass Biquad

16.7 Log-Domain Processing Instantaneous Companding • Log-Domain Filter Synthesis • Performance Aspects • The Basic Log-Domain Integrator • Synthesis of Higher-Order Log-Domain Filters

16.1 Introduction As the operating frequency of communication channels for both video and wireless increases, there is an ever-increasing demand for high-frequency amplifiers. Furthermore, the quest for single-chip inte­ gration has led to a whole new generation of amplifiers predominantly geared toward CMOS VLSI. In this chapter, we will focus on the design of high-frequency amplifiers for potential applications in the front-end of video, optical, and RF systems. Figure 16.1 shows, for example, the architecture of a typical mobile phone transceiver front-end. With channel frequencies approaching the 2-GHz range, coupled with demands for reduced chip size and power consumption, there is an increasing quest for VLSI at microwave frequencies. The shrinking feature size of CMOS has facilitated the design of complex analog circuits and systems in the 1- to 2-GHz range, where more traditional low-frequency lumped circuit techniques are now becoming feasible. Since the amplifier is the core component in such systems, there has been an abundance of circuit design methodologies for high-speed, low-voltage, low-noise, and low distortion operation.

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FIGURE 16.1 Generic wireless transceiver architecture.

This chapter will present various amplifier designs that aim to satisfy these demanding requirements. In particular, we will review, and in some cases present new ideas for power amps, LNAs, and transcon­ ductance cells, which form core building blocks for systems such as Fig. 16.1. Section 16.2 begins by reviewing the concept of current-feedback, and shows how this concept can be employed in the devel­ opment of low-voltage, high-speed, constant-bandwidth CMOS amplifiers. The next two sections of the chapter focus on amplifiers for wireless receiver applications, investigating performance requirements and design strategies for optical receiver amplifiers (Section 16.3) and high-frequency low-noise ampli­ fiers (Section 16.4). Section 16.5 considers the design of amplifiers for the transmitter side, and in particular the design and feasibility of Class E power amps are discussed. Finally, Section 16.6 reviews a very recent low-distortion amplifier design strategy termed “log-domain,” which has shown enormous potential for high-frequency, low-distortion tunable filters.

16.2 The Current Feedback Op-Amp Current Feedback Op-Amp Basics The operational amplifier (op-amp) is one of the fundamental building blocks of analog circuit design.1,2 High-performance signal processing functions such as amplifiers, filters, oscillators, etc. can be readily implemented with the availability of high-speed, low-distortion op-amps. In the last decade, the devel­ opment of complementary bipolar technology has enabled the implementation of single-chip video op-amps.3–7 The emergence of op-amps with non-traditional topologies, such as the current feedback op-amp, has improved the speed of these devices even further.8–11 Current feedback op-amp structures are well known for their ability to overcome (to a first-order approximation) the gain-bandwidth tradeoff and slew rate limitation that characterizes traditional voltage feedback op-amps.12 Figure 16.2 shows a simple macromodel of a current feedback op-amp (CFOA), along with a simplified circuit diagram of the basic architecture. The topology of the current feedback op-amp differs from the conventional voltage feedback op-amp (VOA) in two respects. First, the input stage of a CFOA is a unitygain voltage buffer connected between the inputs of the op-amp. Its function is to force Vn to follow Vp , very much like a conventional VOA does via negative feedback. In the case of the CFOA, because of the low output impedance of the buffer, current can flow in or out of the inverting input, although in normal operation (with negative feedback) this current is extremely small. Secondly, a CFOA provides a high open-loop transimpedance gain Z(jω), rather than open-loop voltage gain as with a VOA. This is shown in Fig. 16.2, where a current-controlled current source senses the current IINV delivered by the buffer to the external feedback network, and copies this current to a high impedance Z(jω). The voltage conveyed to the output is given by Eq. (16.1): V OUT -( jω ) = Z ( jω ) V OUT = Z ( jω ) ⋅ I INV ⇒ ----------I INV

© 2003 by CRC Press LLC

(16.1)

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FIGURE 16.2 Current feedback op-amp macromodel.

When the negative feedback loop is closed, any voltage imbalance between the two inputs due to some external agent, will cause the input voltage buffer to deliver an error current IINV to the external network. This error current IINV = I1 – I2 = IZ is then conveyed by the current mirrors to the impedance Z, resulting in an ouput voltage as given by Eq. (16.1). The application of negative feedback ensures that VOUT will move in the direction that reduces the error current IINV and equalizes the input voltages. We can approximate the open-loop dynamics of the current feedback op-amp as a single pole response. Assuming that the total impedance Z(jω) at the gain node is the combination of the output resistance of the current mirrors Ro in parallel with a compensation capacitor C, we can write: Ro Ro - = ---------------Z ( jω ) = -----------------------1 + j ω Ro C ω 1 + j-----­ ωo

(16.2)

where ωo = 1/Ro ⋅ C represents the frequency where the open-loop transimpedance gain is 3 dB down from its low frequency value Ro. In general, Ro is designed to be very high in value. Referring to the non-inverting amplifier configuration shown in Fig. 16.3: V IN V OUT V IN V OUT – V IN - – -------------------------- = ----------------– ----------I INV = ------RF RG R G // R F RF

FIGURE 16.3 CFOA non-inverting amplifier configuration.

© 2003 by CRC Press LLC

(16.3)

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Substituting Eq. (16.1) into Eq. (16.3) yields the following expression for the closed-loop gain: R R Z ( jω ) 1 A CL ( jω ) =  1 + -----F- ⋅ -------------------------- =  1 + -----F- ⋅ -----------------------­    RF R G R F + Z ( jω ) R G 1 + ------------Z ( jω )

(16.4)

Combining Eqs. (16.2) and (16.4), and assuming that the low frequency value of the open-loop transimpedance is much higher than the feedback resistor (Ro  RF) gives: R A Vo 1 ­ A CL ( jω ) =  1 + -----F- ⋅ --------------------------- = ---------------- RF ⋅ ω R G ω 1 + j-----1 + j---------------ωα Ro ⋅ ωo

(16.5)

Referring to Eq. (16.5), the closed-loop gain AVo = 1 + RF /RG , while the closed-loop –3 dB frequency ωα is given by: R ω α = -----o ⋅ ω o RF

(16.6)

Eq. (16.6) indicates that the closed-loop bandwidth does not depend on the closed-loop gain as in the case of a conventional VOA, but is determined by the feedback resistor RF . Explaining this intuitively, the current available to charge the compensation capacitor at the gain node is determined by the value of the feedback resistor RF and not Ro , provided that Ro  RF . So, once the bandwidth of the amplifier is set via RF , the gain can be independently varied by changing RG . The ability to control the gain independently of bandwidth constitutes a major advantage of current feedback op-amps over conven­ tional voltage feedback op-amps. The other major advantage of the CFOA compared to the VFOA is the inherent absence of slew rate limiting. For the circuit of Fig. 16.3, assume that the input buffer is very fast and thus a change in voltage at the non-inverting input is instantaneously converted to the inverting input. When a step ∆VIN is applied to the non-inverting input, the buffer output current can be derived as: V IN – V OUT V IN + -------I INV = -------------------------RG RF

(16.7)

Eq. (16.7) indicates that the current available to charge/discharge the compensation capacitor is pro­ portional to the input step regardless of its size, that is, there is no upper limit. The rate of change of the output voltage is thus: –t ⁄ R ⋅ C I INV R dV OUT - ⇒ V OUT ( t ) = ∆V IN ⋅  1 + -----F- ⋅ ( 1 – e f ) -------------- = ------- C dt R G

(16.8)

Eq. (16.8) indicates an exponential output transition with time constant τ = RF ⋅ C. Similar to the small-signal frequency response, the large-signal transient response is governed by RF alone, regardless of the magnitude of the closed-loop gain. The absence of slew rate limiting allows for faster settling times and eliminates slew rate-related non-linearities. In most practical bipolar realizations, Darlington-pair transistors are used in the input stage to reduce input bias currents, which makes the op-amp somewhat noisier and increases the input offset voltage. This is not necessary in CMOS realizations due to the inherently high MOSFET input impedance. However, in a closed-loop CFOA, RG should be much larger than the output impedance of the buffer. In bipolar realizations, it is fairly simple to obtain a buffer with low output resistance, but this becomes more of a problem in CMOS due to the inherently lower gain of MOSFET devices. As a result, RG typically needs to © 2003 by CRC Press LLC

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be higher in a CMOS CFOA than in a bipolar realization, and consequently, RF needs to be increased above the value required for optimum high-frequency performance. Additionally, the fact that the input buffer is not in the feedback loop imposes linearity limitations on the structure, especially if the impedance at the gain node is not very high. Regardless of these problems, current feedback op-amps exhibit excellent highfrequency characteristics and are increasingly popular in video and communications applications.13 The following sections outline the development of a novel low-output impedance CMOS buffer, which is then employed in a CMOS CFOA to reduce the minimum allowable value of RG .

CMOS Compound Device A simple PMOS source follower is shown in Fig. 16.4. The output impedance seen looking into the source of M1 is approximately Zout = 1/gm , where gm is the small signal transconductance of M1. To increase gm , the drain current of M1 could be increased, which leads to an increased power dissipation. Alternatively, the dimensions of M1 can be increased, resulting in additional parasitic capacitance and hence an inferior frequency response. Figure 16.5 shows a configuration that achieves a higher transconductance than the simple follower of Fig. 16.3 for the same bias current.11 The current of M2 is fed back to M1 through the a:1 current mirror. This configuration can be viewed as a compound transistor whose gate is the gate of M1 and whose source is the source of M2. The impedance looking into the compound source can be approximated as Zout = (gm1 – a ⋅ gm2 )/(gm1 ⋅ gm2 ), where gm1 and gm2 represent the small signal transcon­ ductance of M1 and M2, respectively. The output impedance can be made small by setting the current mirror transfer ratio a = gm1/gm2. The p-compound device is practically implemented as in Fig. 16.6. In order to obtain a linear voltage transfer function from node 1 to 2, the gate-source voltages of M1 and M3 must cancel. The current mirror (M4-M2) acts as an NMOS-PMOS gate-source voltage matching circuit14 and compensates for the difference

FIGURE 16.4 Simple PMOS source follower.

FIGURE 16.5 Compound MOS device.

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FIGURE 16.6 Actual p-compound device implementation.

in the gate-source voltages of M1 and M3, which would normally appear as an output offset. DC analysis, assuming a square law model for the MOSFETs, shows that the output voltage exactly follows the input voltage. However, in practice, channel length modulation and body effects preclude exact cancellation.15

Buffer and CFOA Implementation The current feedback op-amp shown in Fig. 16.7 has been implemented in a single-well 0.6-µm digital CMOS process11; the corresponding layout plot is shown in Fig. 16.8. The chip has an area of 280 µm by 330 µm and a power dissipation of 12 mW. The amplifier comprises two voltage followers (input and output) connected by cascoded current mirrors to enhance the gain node impedance. A compensation capacitor (Cc = 0.5 pF) at the gain node ensures adequate phase margin and thus closed-loop stability. The

FIGURE 16.7 Current feedback op-amp schematic.

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FIGURE 16.8 Current feedback op-amp layout plot. TABLE 16.1 Voltage Buffer Performance Power Supply DC gain (no load) Output impedance HD2 (Vin = 200 mVrms)

IM3 (Vin=200 mVrms) Slew rate Input referred noise

5V

Dissipation

5 mW

–3.3dB 75Ω 1 MHz 10 MHz 20 MHz 20 MHz, ∆f = 200 KHz (Load = 10 pF) 10 nV Hz

Bandwidth Min. load resistance –50 dB –49 dB –45 dB –53 dB +130 V/µs

140 MHz 10 KΩ

–72 V/µs

Note: Load = 10 kΩ /10 pF, except for slew rate measurement.

voltage followers have been implemented with two compound transistors, p-type and n-type, in a pushpull arrangement. Two such compound transistors in the output stage are shown shaded in Fig. 16.7. The input voltage follower of the current feedback op-amp was initialy tested open-loop, and measured results are summarized in Table 16.1. The load is set to 10 kΩ/10 pF, except where mentioned otherwise, 10 kΩ being a limit imposed by overall power dissipation of the chip. Intermodulation distortion was measured with two tones separated by 200 kHz. The measured output impedance of the buffer is given in Fig. 16.9. It remains below 80 Ω up to a frequency of about 60 MHz, when it enters an inductive region. A maximum impedance of 140 Ω is reached around 160 MHz. Beyond this frequency, the output impedance is dominated by parasitic capacitances. The inductive behavior is characteristic of the use of feedback to reduce output impedance, and can cause stability problems when driving capacitive loads. Small-signal analysis (summa­ rized in Table 16.2) predicts a double zero in the output impedance.15 Making factor G in Table 16.2 small will reduce the output impedance, but also moves the double zero to lower frequencies and intensifies the inductive behavior. The principal tradeoff in this configuration is between output impedance magnitude and inductive behavior. In practice. the output impedance can be reduced by a factor of 3 while still maintaining good stability when driving capacitive loads. Figure 16.10 shows the measured frequency response of the buffer. Given the low power dissipation, excellent slew rates have been achieved (Table 16.2). © 2003 by CRC Press LLC

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FIGURE 16.9 Measured buffer output impedance characteristics.

TABLE 16.2 Voltage Transfer Function and Output Impedance of Compound Device

G Z out = ------------------------------------------------------------------------------------------------------­ (g m1 + g ds1 + g ds2 ) ⋅ (g m3 + g ds3 ) ⋅ (g m4 + g ds4 ) V out g m1 ⋅ g m3 ⋅ (g m4 + g ds4 ) -------- = -------------------------------------------------------------------------------------------------------------------------V in (g m1 + g ds1 + g ds2 ) ⋅ (g m3 + g ds3 ) ⋅ (g m4 + g ds4 ) + g L ⋅ G G = (g m1 + g ds1 + g ds2 ) ⋅ (g m4 + g ds4 + g ds3 ) – g m2 ⋅ g m3

FIGURE 16.10

Measured buffer frequency response.

After the characterization of the input buffer stage, the entire CFOA was tested to confirm the suitability of the compound transistors for the implementation of more complex building blocks. Open-loop transimpedance measurements are shown in Fig. 16.11. The bandwidth of the amplifier was measured at gain settings of 1, 2, 5, and 10 in a non-inverting configuration, and the feedback resistor was trimmed © 2003 by CRC Press LLC

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FIGURE 16.11

Measured CFOA open-loop transimpedance gain.

TABLE 16.3 Current Feedback Op-Amp Measurement Summary Power Supply Gain 1 2 5 10 Frequency 1 MHz

10 MHz

5V

Power Dissipation

12 mW

Input (mV rms)

Gain

HD2 (dB)

140 40 10 80 40 13

2 5 10 2 5 10

–51 –50 –49 –42 –42 –43

Bandwidth (MHz) 117 118 113 42

to achieve maximum bandwidth at each gain setting separately. CFOA measurements are summarized in Table 16.3, loading conditions are again 10 kΩ/10 pF. Fig. 16.12 shows the measured frequency response for various gain settings. The bandwidth remains con­ stant at 110 MHz for gains of 1, 2, and 5, consistent with the expected behavior of a CFOA. The bandwidth falls to 42 MHz for a gain of 10 due to the finite output impedance of the input buffer stage which series as the CFOA inverting input. Figure 16.13 illustrates the step response of the CFOA driving a 10 kΩ/10 pF load at a voltage gain of 2. It can be seen that the inductive behavior of the buffers has little effect on the step response. Finally, distortion measurements were carried out for the entire CFOA for gain settings 2, 5, and 10 and are summarized in Table 16.3. HD2 levels can be further improved by employing a double-balanced topology.A distortion spectrum is shown in Fig. 16.14; the onset of HD3 is due to clipping at the test conditions.

16.3 RF Low-Noise Amplifiers This section reviews the important performance criteria demanded of the front-end amplifier in a wireless communication receiver. The design of CMOS LNAs for front-end wireless communication receiver © 2003 by CRC Press LLC

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FIGURE 16.12

Measured CFOA closed-loop frequency response.

FIGURE 16.13

Measured CFOA step response.

applications is then addressed. Section 16.4 considers the related topic of low-noise amplifiers for optical receiver front-ends.

Specifications The front-end amplifier in a wireless receiver must satisfy demanding requirements in terms of noise, gain, impedance matching, and linearity. Noise Since the incoming signal is usually weak, the front-end circuits of the receiver must possess very low noise characteristics so that the original signal can be recovered. Provided that the gain of the front-end amplifier is sufficient so as to suppress noise from the subsequent stages, the receiver noise performance © 2003 by CRC Press LLC

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FIGURE 16.14

CFOA harmonic distortion measurements.

FIGURE 16.15

Three-stage building block with gain Gi and noise Ni per stage.

is determined predominantly by the front-end amplifier. Hence, the front-end amplifier should be a lownoise amplifier (LNA). Gain The voltage gain of the LNA must be high enough to ensure that noise contributions from the following stages can be safely neglected. As an example, Fig. 16.15 shows the first three stages in a generic frontend receiver, where the gain and output-referred noise of each stage are represented by Gi and Ni (i = 1, 2, 3), respectively. The total noise at the third stage output is given by: N out = N in G 1 G 2 G 3 + N 1 G 2 G 3 + N 2 G 3 + N 3

(16.9)

This output noise (Nout ) can be referred to the input to derive an equivalent input noise (Neq ): N out N2 N3 N out N - = ------------------ = N in + ------1 + ----------- + -----------------N eq = ----------Gain G1 G2 G3 G1 G1 G2 G1 G2 G3

(16.10)

According to Eq. 22.10, the gain of the first stage should be high in order to reduce noise contri­ butions from subsequent stages. However, if the gain is too high, a large input signal may saturate the subsequent stages, yielding intermodulation products which corrupt the desired signal. Thus, optimi­ zation is inevitable. Input Impedance Matching The input impedance of the LNA must be matched to the antenna impedance over the frequency range of interest, in order to transfer the maximum available power to the receiver. © 2003 by CRC Press LLC

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Linearity Unwanted signals at frequencies fairly near the frequency band of interest may reach the LNA with signal strengths many times higher than that of the wanted signal. The LNA must be sufficiently linear to prevent these out-of-band signals from generating intermodulation products within the wanted frequency band, and thus degrading the reception of the desired signal. Since third-order mixing products are usually dominant, the linearity of the LNA is related to the “third-order intercept point” (IP3), which is defined as the input power level that results in equal power levels for the output fundamental frequency component and the third-order intermodulation components. The dynamic range of a wireless receiver is limited at the lower bound by noise and at the upper band by non-linearity.

CMOS Common-Source LNA: Simplified Analysis Input Impedance Matching by Source Degeneration For maximum power transfer, the input impedance of the LNA must be matched to the source resistance, which is normally 50 Ω. Impedance-matching circuits consist of reactive components and therefore are (ideally) lossless and noiseless. Figure 16.16 shows the small signal equivalent circuit of a CS LNA input stage with impedance-matching circuit, where the gate-drain capacitance Cgd is assumed to have negligible effect and is thus neglected.16,17 The input impedance of this CS input stage is given by: gm 1 -L Z in = jω(L g + L s ) + ------------- + -----jωC gs C gs s

(16.11)

Thus, for matching, the two conditions below must be satisfied: (i)

1 2 ω o = ---------------------------(L g + L s )C gs

and

gm ------L = Rs C gs s

( ii )

(16.12)

Noise Figure of CS Input Stage Two main noise sources exist in a CS input stage as shown in Fig. 16.17; thermal noise from the source resistor Rs (denoted v Rs 2 ) and channel thermal noise from the input transistor (denoted i d 2 ). The output noise current due to v Rs 2 can be determined from Fig. 16.17 as: 2

2

2

gm g m v Rs 2 2 -2 v Rs i nout1 = -----------------------------------------= ------------------------2 2 2 2 4ω R C ω (g m L s + R s C gs ) s gs while the output noise current due to i d 2 can be evaluated as:

FIGURE 16.16

Simplified small-signal equivalent circuit of the CS stage.

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(16.13)

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FIGURE 16.17

Simplified noise equivalent circuit of the CS stage. V Rs 2 = 4kT Rs ; id 2 = KTΓg dc .

id 1 i nout2 = -------------------------- = --i d 2 gm Ls   1 + ----------­   R s C gs

1 2 2 ∴i nout2 = --i d 4

(16.14)

From Eqs. (16.13) and (16.14), the noise figure of the CS input stage is determined as: 2

2

Ls  ω o R s C gs  i nout2 = 1 + Γ  --------------NF = 1 + ------------2 = 1 + Γ  ---------------------    g L m s + Lg i nout1 2

(16.15)

In practice, any inductor (especially a fully integrated inductor) has an associated resistance that will contribute thermal noise, degrading the noise figure in Eq. (16.15). Voltage Amplifier with Inductive Load Referring to Fig. 16.15, the small signal current output is given by: gm vs - i out = ---------------------------------------------------------------------------------------------2 [1 – ω C gs (L g + L s )] + jω(g m L s + R s C gs )

(16.16)

For an inductive load (L1) with a series internal resistance rL1, the output voltage is thus: –(r L1 + jωL 1 )g m v s v out = – i out (r L1 + jωL 1 ) = ---------------------------------------------------------------------------------------------2 [1 – ω C gs (L g + L s )] + jω(g m L s + R s C gs )

(16.17)

Assuming that the input is impedance matched, the voltage gain at the output is given by: r L1 ω o L 1 2 1  L 1  L 1  ( r L1 ) + ( ω o ) ( L 1 ) v out = ------------------------------------------------ 1 +  ---------- ≅ --ω o ----- ------ = ------------------ 2  L s   r L1 2ω o L s r L1  2ω o L s vs 2

2

2

(16.18)

CMOS Common-Source LNA: Effect of Cgd In the analysis so far, the gate-drain capacitance (Cgd ) has been assumed to be negligible. However, at very high frequencies, this component cannot be neglected. Figure 16.18 shows the modified input stage of a CS LNA including Cgd and an input ac-coupling capacitance Cin . Small signal analysis shows that the input impedance is now given by: © 2003 by CRC Press LLC

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FIGURE 16.18

The Circuits and Filters Handbook, Second Edition

Noise equivalent circuit of the CS stage, including effects of Cgd.

gm Ls Z in = ---------------------------------------------------------------------------------------2 g m (1 – ω L s C gd ) C gs + C gd jωL s g m + -------------------------------------­ 1 ----- + jωC gd ZL

(16.19)

Equation 16.19 exhibits resonance frequencies that occur when: 2

1 – ω L s C gs = 0

2

1 – ω L g C in = 0

and

(16.20)

Equation 16.19 indicates that the input impedance matching is degraded by the load ZL when Cgd is included in the analysis. Input Impedance with Capacitive Load If the load ZL is purely capacitive, that is, 1 Z L = -----------jωC L

(16.21)

then the input impedance can be easily matched to the source resistor Rs . Substituting Eq. (16.21) for ZL, the bracketed term in the denominator of Eq. (16.19) becomes: 2

g m (1 – ω L s C gd ) d 1 = jωL s g m + -------------------------------------= 0 jω(C gd + C L )

(16.22)

under the condition that 2

1 – ω L s (2C gd + C L ) = 0

(16.23)

The three conditions in Eqs. (16.20) and (16.23) should be met to ensure input impedance matching. However, in practice, we are unlikely to be in the situation of using a load capacitor. Input Impedance with Inductive Load If ZL = jωLL, the CS LNA input impedance is given by: gm Ls Z in = ---------------------------------------------------------------------------------------- 1 – ω 2 L s C gd  C gs + jωC gd g m L s + L L  --------------------------- 2 1 – ω L L C gd © 2003 by CRC Press LLC

(16.24)

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479

In order to match to a purely resistive input, the value of the reactive term in Eq. (16.24) must be negligible, which is difficult to achieve.

Cascode CS LNA Input Matching As outlined in the paragraph above, the gate-drain capacitance (Cgd ) degrades the input impedance matching and therefore reduces the power transfer efficiency. In order to reduce the effect of Cgd , a cascoded structure can be used.18–20 Figure 16.19 shows a cascode CS LNA. Since the voltage gain from the gate to the drain of M1 is unity, the gate-drain capacitance (Cgd1) no longer sees the full input-output voltage swing which greatly improves the input-output isolation. The input impedance can be approxi­ mated by Eq. (16.11), thus allowing a simple matching circuit to be employed.18 Voltage Gain Figure 16.20 shows the small-signal equivalent circuit of the cascode CS LNA. Assuming that input is fully matched to the source, the voltage gain of the amplifier is given by: jωL 1 g m2 g m1 v out 1 -  ---------------------------- ----------------------------------------------------------------- = –--  ----------------------------2  1 – ω 2 L 1 C gd2  g m2 + jωC gs2 (1 – ω 2 L s C gs1 ) + jωL s g m1 vs

FIGURE 16.19

Cascode CS LNA.

FIGURE 16.20

Equivalent circuit of cascode CS LNA.

© 2003 by CRC Press LLC

(16.25)

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At the resonant frequency, the voltage gain is given by: v out 1 1 1 L 1 1 L - × -------------------------------- ≈ –--  -----1 × ---------------------­­ -------- ( ω o ) = – --  -----1  ------------------------------  vs L 2 2  L s   1 – ω o 2 L 1 C gd2 ω C s gs1 1 + jω o  -------1 + j  -----­o   g m2   ω T

(16.26)

From Eq. (16.26), the voltage gain is dependent on the ratio of the load and source inductance values. Therefore, high gain accuracy can be achieved since this ratio is largely process independent. Noise Figure Figure 16.21 shows an equivalent circuit of the cascode CS LNA for noise calculations. Three main noise sources can be identified: the thermal noise voltage from Rs, and the channel thermal noise currents from M1 and M2. Assuming that the input impedance is matched to the sources, the output noise current due to v RS 2 can be derived as: g m2 1  ------------------------------ v i out1 = ----------------------------------------------------2  g + jω o C gs2 RS m2 2jω o L s (1 – ω o L 1 C gd2 )

(16.27)

The output noise current contribution due to i d1 2 of M1 is given by: g m2 1 i -  ------------------------------i out2 = --------------------------------------d1 2  g + 2 ( 1 – ω o L 1 C gd2 ) m2 jω o C ds2

(16.28)

The output noise current due to i d2 2 of M2 is given by: jω o C gs2 - i d2 i out3 = ------------------------------------------------------------------------2 (1 – ω o L 1 C gd2 )(g m2 + jω o C gs2 )

(16.29)

The noise figure of the cascode CS LNA can thus be derived as: 2

2

2

2

i out2 i out3 4ω o C gs2  NF = 1 + ---------- + ----------- = 1 + Γ  1 + --------------------- 2 2 g m1 g m2  i out1 i out1

(16.30)

In order to improve the noise figure, the transconductance values (gm) of M1 and M2 should be increased. Since the gate-source capacitance (Cgs2) of M2 is directly proportional to the gate width, the gate width of M2 cannot be enlarged to increase the transconductance. Instead, this increase should be realized by increasing the gate bias voltage.

FIGURE 16.21

Noise equivalent circuit of cascode CS LNA.

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FIGURE 16.22

Front-end optical receiver.

FIGURE 16.23

Noise equivalent circuit of the front-end optical receiver.

481

16.4 Optical Low-Noise Preamplifiers Figure 16.22 shows a simple schematic diagram of an optical receiver, consisting of a photodetector, a preamplifier, a wide-band voltage amplifier, and a pre-detection filter. Since the front-end transimpedance preamplifier is critical in determining the overall receiver performance, it should possess a wide band­ width so as not to distort the received signal, high gain to reject noise from subsequent stages, low noise to achieve high sensitivity, wide dynamic range, and low inter-symbol-interference (ISI).

Front-End Noise Sources Receiver noise is dominated by two main noise sources: the detector (PIN photodiode) noise and the amplifier noise. Figure 16.23 illustrates the noise equivalent circuit of the optical receiver. PIN Photodiode Noise The noise generated by a PIN photodiode arises mainly from three shot noise contributions: quantum noise Sq( f ), thermally generated dark-current shot noise SD( f ), and surface leakage-current shot noise SL( f ). Other noise sources in a PIN photodiode, such as series resistor noise, are negligible in comparison. The quantum noise Sq( f ), also called signal-dependent shot noise, is produced by the light-generating nature of photonic detection and has a spectral density Sq( f ) = 2qIpd ∆f, where Ipd is the mean signal current arising from the Poisson statistics. The dark-current shot noise SD( f ) arises in the photodiode bulk material. Even when there is no incident optical power, a small reverse leakage current still flows, resulting in shot noise with a spectral density SD(f ) = 2qIDB ∆f, where IDB is the mean thermally generated dark current. The leakage shot noise SL(f ) occurs because of surface effects around the active region, and is described by SL(f ) = 2qISL∆f, where ISL is the mean surface leakage current. Amplifier Noise For a simple noise analysis, the pre- and post-amplifiers in Fig. 16.22 are merged to a single amplifier with a transfer function of Av (ω). The input impedance of the amplifier is modeled as a parallel com­ bination of Rin and Cin . © 2003 by CRC Press LLC

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If the photodiode noise is negligibly small, the amplifier noise will dominate the whole receiver noise performance, as can be inferred from Fig. 16.23. The equivalent noise current and voltage spectral densities of the amplifier are represented as Si (A2/Hz) and Sv (V2/Hz), respectively. Resistor Noise The thermal noise generated by a resistor is directly proportional to the absolute temperature T and is represented by a series noise voltage generator or by a shunt noise current generator21 of value: 2

v R = 4kTR∆f

or

1 2 i R = 4kT--- ∆f R

(16.31)

where k is Boltzmann’s constant and R is the resistance.

Receiver Performance Criteria

—

Equivalent Input Noise Current 〈 ieq2 〉 The transfer function from the current input to the amplifier output voltage is given by: R in V out -A ( ω ) Z T ( ω ) = -------- = Z in A v ( ω ) = -----------------------------------------1jωR in (C pd + C in ) v I pd

(16.32)

where Cpd is the photodiode capacitance, and Rin and Cin are the input resistance and capacitance of the amplifier, respectively. Assuming that the photodiode noise contributions are negligible and that the amplifier noise sources are uncorrelated, the equivalent input noise current spectral density can be derived from Fig. 16.23 as: Sv 1 2 2 = S i + S v ---------2 + (2πf) (C pd + C in ) S eq ( f ) = S i + ------------2 R in [ Z in ]

(16.33)

The total mean-square noise output voltage 〈 v no 2〉 is calculated by combining Eqs. (16.32) and (16.33) as follows: ∞ 2

〈 v no 〉 =

∫ Seq (f ) ZT ( f )

2

df

(16.34)

0

This total noise voltage can be referred to the input of the amplifier by dividing it by the squared dc gain 2 Z T ( 0 ) of the receiver, to give an equivalent input mean-square noise current: ∞

2

∞

2

〈 v no 〉 Sv  ZT ( f ) 2 2 ZT ( f ) 2 -2 df 〈 i eq 〉 = ------------------2 =  S i + --------2 ∫ -------------------2 df + S v [2π(C pd + C in )] ∫ f -----------------  ZT ( 0 ) ZT ( 0 ) R in 0 Z T ( 0 ) 0 2

(16.35)

Sv  2 3 =  S i + --------2 I 2 B + [2π(C pd + C in )] I 3 B S v   R in

where B is the operating bit-rate, and I2(= 0.56) and I3(= 0.083) are the Personick second and third integrals, respectively, as given in Reference 22. According to Morikoni et al.,23 the Personick integral in Eq. (16.35) is correct only if a receiver produces a raised-cosine output response from a rectangular input signal at the cut-off bit rate above which the frequency response of the receiver is zero. However, the Personick integration method is generally preferred when comparing the noise (or sensitivity) performance of different amplifiers.

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Optical Sensitivity Optical sensitivity is defined as the minimum received optical power incident on a perfectly efficient photodiode connected to the amplifier, such that the presence of the amplifier noise corrupts on average only one bit per 109 bits of incoming data. Therefore, a detected power greater than the sensitivity level guarantees system operation at the desired performance. The optical sensitivity is predicted theoretically by calculating the equivalent input noise spectral density of the receiver, and is calculated24 via Eq. (16.36): 1 hc 2 S = 10log 10 Q------ 〈 i eq 〉 ⋅ ------------- (dBm)  qλ 1mW

(16.36)

where h is Planck’s constant, c is the speed of light, q is electronic charge, and λ (µm) is the wavelength of light in an optical fiber. Q(= SNR) , where SNR represents the required signal-to-noise ratio (SNR). The value of Q should be 6 for a bit error rate (BER) of 10–9, and 7.04 for a BER of 10–12. The relation between Q and BER is given by: 2

exp(–Q ⁄ 2) BER = -----------------------------2πQ

(16.37)

Since the number of photogenerated electrons in a single bit is very large (more than 104) for optoelec­ tronic integrated receivers,25 Gaussian statistics of the above BER equation can be used to describe the detection probability in PIN photodiodes. SNR at the Photodiode Terminal22 Among the photodiode noise sources, quantum noise is generally dominant and can be estimated as: 2

〈 i n 〉 q = 2qI pd B eq

(16.38)

where Ipd is the mean signal current and Beq is the equivalent noise bandwidth. The signal-to-noise-ratio (SNR) referred to the photodiode terminal is thus given by: 2

I pd SNR = ----------------------------------------------------------------4kTB eq 2 2 〈 i n 〉 pd + ----------------- + 〈 i eq 〉 amp RB

(16.39)

where all noise contributions due to the amplifier are represented by the equivalent noise current where all noise contributions due to the amplifier are represented by the equivalent noise current 〈 i eq 2〉 amp . It is often convenient to combine the noise contributions from the amplifier and the photodiode with the thermal noise from the bias resistor, by defining a noise figure (NF): 4kTB eq NF 4kTB eq 2 2 〈 i n 〉 pd + ---------------- + 〈 i eq 〉 amp = -----------------------RB RB

(16.40)

The SNR at the photodiode input is thus given by: 2

I pd R B SNR ≅ -----------------------4kTB eq NF

(16.41)

Inter-Symbol Interference (ISI) When a pulse passes through a band-limited channel, it gradually disperses. When the channel bandwidth is close to the signal bandwidth, the expanded rise and fall times of the pulse signal will cause successive

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pulses to overlap, deteriorating the system performance and giving higher error rates. This pulse over­ lapping is known as inter-symbol interference (ISI). Even with raised signal power levels, the error performance cannot be improved.26 In digital optical communication systems, sampling at the output must occur at the point of maximum signal in order to achieve the minimum error rate. The output pulse shape should therefore be chosen to maximize the pulse amplitude at the sampling instant and give a zero at other sampling points; that is, at multiples of 1/B, where B is the data-rate. Although the best choice for this purpose is the sinc­ function pulse, in practice a raised-cosine spectrum pulse is used instead. This is because the sinc-function pulse is very sensitive to changes in the input pulse shape and variations in component values, and because it is impossible to generate an ideal sinc-function. Dynamic Range The dynamic range of an optical receiver quantifies the range of detected power levels within which correct system operation is guaranteed. Dynamic range is conventionally defined as the difference between the minimum input power (which determines sensitivity) and the maximum input power (limited by overload level). Above the overload level, the bit-error-rate (BER) rises due to the distortion of the received signal.

Transimpedance (TZ) Amplifers High-impedance (HZ) amplifiers are effectively open-loop architectures, and exhibit a high gain but a relatively low bandwidth. The frequency response is similar to that of an integrator, and thus HZ amplifiers require an output equalizer to extend their frequency capabilities. In contrast, the transim­ pedance (TZ) configuration exploits resistive negative feedback, providing an inherently wider bandwidth and eliminating the need for an output equalizer. In addition, the use of negative feedback provides a relatively low input resistance and thus the architecture is less sensitive to the photodiode parameters. In a TZ amplifier, the photodiode bias resistor RB can be omitted, since bias current is now supplied through the feedback resistor. In addition to wider bandwidth, TZ amplifiers offer a larger dynamic range because the transimpedance gain is determined by a linear feedback resistor, and not by a non-linear open-loop amplifier as is the case for HZ amplifiers. The dynamic range of TZ amplifiers is set by the maximum voltage swing available at the amplifier output, provided no integration of the received signal occurs at the front end. Since the TZ output stage is a voltage buffer, the voltage swing at the output can be increased with high current operation. The improvement in dynamic range in comparison to the HZ architecture is approximately equal to the ratio of open-loop to closed-loop gain.27 Conclusively, the TZ configuration offers the better performance compromise compared to the HZ topology, and hence this architecture is preferred in optical receiver applications. A schematic diagram of a TZ amplifier with PIN photodiode is shown in Fig. 16.24. With an openloop, high-gain amplifier and a feedback resistor, the closed-loop transfer function of the TZ amplifier is given by: Rf –R f - ≅ ---------------------------------------Z T ( s ) = -------------------------------------------------------------------------C + (1 + A)C C 1 + A in  ------------f - + sR f -----------------------------------1 + sR f  ------in- + C f A   A  A

(16.42)

where A is the open-loop mid-band gain of the amplifier which is assumed to be greater than unity, Rf is the feedback resistance, Cin is the total input capacitance of the amplifier including the photodiode and the parasitic capacitance, and Cf represents the stray feedback capacitance. The –3 dB bandwidth of the TZ amplifier is approximately given by: (1 + A) f –3d = -----------------2πR f C T

© 2003 by CRC Press LLC

(16.43)

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FIGURE 16.24

485

Schematic diagram of a transimpedance amplifier with photodiode.

where CT is the total input capacitance including the photodiode capacitance. The TZ amplifier can thus have wider bandwidth by increasing the open-loop gain, although the open-loop gain cannot be increased indefinitely without stability problems. However, a tradeoff between low noise and wide bandwidth exists, since the equivalent input noise current spectral density of TZ amplifier is given by: 4kT 4kT 1 1 2 2 2 S eq ( f ) = --------- + --------- + S i ( f ) + S v ( f )  ---- + ------ + (2πf ) ( C pd + C in )  R f R B Rf RB

(16.44)

where Cin is the input capacitance of the input transistor. Increasing the value of Rf reduces the noise current in Eq. (16.44) but also shrinks the bandwidth in Eq. (16.43). This conflict can be mitigated by making A in Eq. (16.43) as large as the closed-loop stability allows.28 However, the feedback resistance Rf cannot be increased indefinitely due to the dynamic range requirements of the amplifier, since too large a feedback resistance causes the amplifier to be overloaded at high signal levels. This overloading can be avoided by using automatic gain control (AGC) circuitry, which automatically reduces the tran­ simpedance gain in discrete steps to keep the peak output signal constant.27 The upper limit of Rf is set by the peak amplitude of the input signal. Since the dc transimpedance gain is approximately equal to the feedback resistance Rf , the output voltage is given by Ipd × Rf , where Ipd is the signal photocurrent. If this output voltage exceeds the maximum voltage swing at the output, the amplifier will be saturated and the output will be distorted, yielding bit errors. The minimum value of Rf is determined by the output signal level at which the performance of the receiver is degraded due to noise and offsets. For typical fiber-optic communication systems, the input signal power is unknown, and may vary from just above the noise floor to a large value enough to generate 0.5 mA at the detector diode.29 The TZ configuration has some disadvantages over HZ amplifiers. The power consumption is fairly high, partly due to the broadband operation provided by negative feedback. A propagation delay exists in the closed-loop of the feedback amplifier that may reduce the phase margin of the amplifier and cause peaking in the frequency response. Additionally, any stray feedback capacitance Cf will further deteriorate the ac performance. Among three types of TZ configuration in CMOS technology (common-source, common-drain, and common-gate TZ amplifiers), the common-gate configuration has potentially the highest bandwidth due to its inherently lower input resistance. Using a common-gate input configuration, the resulting amplifier bandwidth can be made independent of the photodiode capacitance (which is usually the limiting factor in achieving GHz preamplifier designs). Recently, a novel common-gate TZ amplifier has been demon­ strated, which shows superior performance compared to various other configurations.30,31

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Layout for HF Operation Wideband high-gain amplifiers have isolation problems irrespective of the choice of technology. Coupling from output to input, from the power supply rails, and from the substrate are all possible. Therefore, careful layout is necessary, and special attention must be given to stray capacitance, both on the integrated circuit and associated with the package.32 Input/Output Isolation For stable operation, a high level of isolation between I/O is necessary. Three main factors degrade the I/O isolation33,34: (1) capacitive coupling between I/O signal paths through the air and through the substrate; (2) feedback through the dc power supply rails and ground-line inductance; and (3) the package cavity resonance since at the cavity resonant frequency, the coupling between I/O can become very large. In order to reduce the unwanted coupling (or to provide good isolation, typically more than 60 dB) between I/O, the I/O pads should be laid out to be diagonally opposite each other on the chip with a thin ‘left-to-right’ geometry between I/O. The small input signal enters on the left-hand side of the chip, while the large output signal exits on the far right-hand side. This helps to isolate the sensitive input stages from the larger signal output stages.35,36 The use of fine line-widths and shielding are effective techniques to reduce coupling through the air. Substrate coupling can be reduced by shielding and by using a thin and low-dielectric substrate. Akazawa et al.33 suggest a structure for effective isolation: a coaxial-like signal-line for high shielding, and a very thin dielectric dc feed-line structure for low characteristic impedance. Reduction of Feedback Through the Power Supply Rails Careful attention should be given to layout of power supply rails for stable operation and gain flatness. Power lines are generally inductive; thus, on-chip capacitive decoupling is necessary to reduce the high-frequency power line impedance. However, a resonance between these inductive and capacitive components may occur at frequencies as low as several hundred MHz, causing a serious dip in the gain-frequency response and an upward peaking in the isolation-frequency characteristics. One way to reduce this resonance is to add a series damping resistor to the power supply line, making the Q factor of the LC resonance small. Additionally, the power supply line should be widened to reduce the characteristic impedance/inductance. In practice, if the characteristic impedance is as small as several ohms, the dip and peaking do not occur, even without resistive termination.33 Resonance also occurs between the IC pad capacitance (Cpd ) and the bond-wire inductance (Lbond ). This resonance frequency is typically above 2 GHz in miniature RF packages. Also in layout, the power supply rails of each IC chip stage should be split from the other stages in order to reduce the parasitic feedback (or coupling effect through wire-bonding inductance), which causes oscillation.34 This helps to minimize crosstalk through power supply rail. The IC is powered through several pads and each pad is individually bonded to the power supply line. I/O Pads The bond pads on the critical signal path (e.g., input pad and output pads) should be made as small as possible to minimize the pad-to-substrate capacitance.35 A floating n-well placed underneath the pad will further reduce the pad capacitance since the well capacitance will appear in series with the pad capacitance. This floating well also prevents the pad metal from spiking into the substrate. High-Frequency (HF) Ground The best possible HF grounds to the sources of the driver devices (and hence the minimization of interstage crosstalk) can be obtained by separate bonding of each source pad of the driver MOSFETs to the ground plane that is very close to the chip.36 A typical bond-wire has a self-inductance of a few nH, which can cause serious peaking within the bandwidth of amplifiers or even instability. By using multiple bond-wires in parallel, the ground-line inductance can be reduced to less than 1 nH.

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Flip-Chip Connection In noisy environments, the noise-insensitive benefits of optical fibers may be lost at the receiver connec­ tion between the photodiode and the preamplifier. Therefore, proper shielding, or the integration of both components onto the same substrate, is necessary to prevent this problem. However, proper shielding is costly, while integration restricts the design to GaAs technologies. As an alternative, the flip-chip interconnection technique using solder bumps has been used.37,38 Small solder bumps minimize the parasitics due to the short interconnection lengths and avoid damages by mechanical stress. Also, it needs relatively low-temperature bonding and hence further reduces damage to the devices. Easy alignment and precise positioning of the bonding can be obtained by a self-alignment effect. Loose chip alignment is sufficient because the surface tension of the molten solder during re-flow produces precise self-alignment of the pads.34 Solder bumps are fabricated onto the photodiode junction area to reduce parasitic inductance between the photodiode and the preamplifier.

16.5 Fundamentals of RF Power Amplifier Design PA Requirements An important functional block in wireless communication transceivers is the power amplifier (PA). The transceiver PA takes as input the modulated signal to be transmitted, and amplifies this to the power level required to drive the antenna. Because the levels of power required to transmit the signal reliably are often fairly high, the PA is one of the major sources of power consumption in the transceiver. In many systems, power consumption may not be a major concern, as long as the signal can be transmitted with adequate power. For battery-powered systems, however, the limited amount of available energy means that the power consumed by all devices must be minimized so as to extend the transmit time. Therefore, power efficiency is one of the most important factors when evaluating the performance of a wireless system. The basic requirement for a power amplifier is the ability to work at low supply voltages as well as high operating frequencies, and the design becomes especially difficult due to the tradeoffs between supply voltage, output power, distortion, and power efficiency that can be made. Moreover, since the PA deals with large signals, small-signal analysis methods cannot be applied directly. As a result, both the analysis and the design of PAs are challenging tasks. This section will first present a study of various configurations employed in the design of state-of-the­ art non-linear RF power amplifiers. Practical considerations toward achieving full integration of PAs in CMOS technology will also be highlighted.

Power Amplifier Classification Power amplifiers currently employed for wireless communication applications can be classified into two categories: linear power amplifiers and non-linear power amplifiers. For linear power amplifiers, the output signal is controlled by the amplitude, frequency, and phase of the input signal. Conversely, for non-linear power amplifiers, the output signal is only controlled by the frequency of input signal. Conventionally, linear power amplifiers can be classified as Class A, Class B, or Class AB. These PAs produce a magnified replica of the input signal voltage or current waveform, and are typically used where accurate reproduction of both the envelope and the phase of the signal is required. However, either poor power efficiency or large distortion prevents them from being extensively employed in wireless communications. Many applications do not require linear RF amplification. Gaussian Minimum Shift Keying (GMSK),39 the modulation scheme used in the European standard for mobile communications (GSM), is an example of constant envelope modulation. In this case, the system can make use of the greater efficiency and simplicity offered by non-linear PAs. The increased efficiency of non-linear PAs, such as Class C, Class D, and Class E, results from techniques that reduce the average collector voltage–current product (i.e., power

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Single-ended Class A power amplifier.

dissipation) in the switching device. Theoretically, these switching-mode PAs have 100% power efficiency since, ideally, there is no power loss in the switching device. Linear Power Amplifiers Class A The basic structure of the Class A power amplifier is shown in Fig. 16.25.40 For Class A amplification, the conduction angle of the device is 360°, that is, the transistor is in its active region for the entire input cycle. The serious shortcoming with Class A PAs is their inherently poor power efficiency, since the transistor is always dissipating power. The efficiency of a single-ended Class A PA is ideally limited to 50%. However, in practice, few designs can reach this ideal efficiency due to additional power loss in the passive components. In an inductorless configuration, the efficiency is only about 25%.41 Class B A PA is defined as Class B when the conduction angle for each transistor of a push-pull pair is 180° during any one cycle. Figure 16.26 shows an inductorless Class B power amplifier. Since each transistor only conducts for half of the cycle, the output suffers crossover distortion due to the finite threshold voltage of each transistor. When no signal is applied, there is no current flowing; as a result, any current through either device flows directly to the load, thereby maximizing the efficiency. The ideal efficiency can reach 78%,41 allowing this architecture to be of use in applications where linearity is not the main concern.

FIGURE 16.26

Inductorless Class B power amplifier.

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Class AB The basic idea of Class AB amplification is to preserve the Class B push-pull configuration while improv­ ing the linearity by biasing each device slightly above threshold. The implementation of Class AB PAs is similar to Class B configurations. By allowing the two devices to conduct current for a short period, the output voltage waveform during the crossover period can be smoothed, which thus reduces the crossover distortion of the output signal. Nonlinear Power Amplifiers Class C A Class C power amplifier is the most popular non-linear power amplifier used in the RF band. The conduction angle is less than 180° since the switching transistor is biased on the verge of conduction. A portion of the input signal will make the transistor operate in the amplifying region, and thus the drain current of the transistor is a pulsed signal. Figures 16.27(a) and (b) show the basic configuration of a Class C power amplifier and its corresponding waveforms; clearly, the input and output voltages are not linearly related. The efficiency of an ideal Class C amplifier is 100% since at any point in time, either the voltage or the current waveforms are zero. In practice, this ideal situation cannot be achieved, and the power efficiency should be maximized by reducing the power loss in the transistor. That is, minimize the current

FIGURE 16.27

(a) Class C power amplifier, and (b) Class C waveforms.

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FIGURE 16.28

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Class D power amplifier.

through the transistor when the voltage across the output is high, and minimize the voltage across the output when the current flows through the device. Class D A Class D amplifier employs a pair of transistors and a tuned output circuit, where the transistors are driven to act as a two-pole switch and the output circuit is tuned to the switching frequency. The theoretical power efficiency is 100%. Figure 16.28 shows the voltage-switching configuration of a Class D amplifier. The input signals of transistors Q1 and Q2 are out of phase, and consequently when Q1 is on, Q2 is off, and vice versa. Since the load network is a tuned circuit, we can assume that it provides little impedance to the operating frequency of the voltage vd and high impedance to other harmonics. Since vd is a square wave, its Fourier expansion is given by 2 1 2 v d ( ωt ) = V dc -- + --- sin( ωt ) + ------ sin ( 3ωt ) … 3π 2 π

(16.45)

The impedance of the RLC series load at resonance is equal to RL , and thus the current is given by: 2V dc i L ( ωt ) = ---------sin( ωt ) πR L

(16.46)

Each of the devices carries the current during one half of the switching cycle. Therefore, the output power is given by: 2

2 V dc P o = -----2 -------π RL

(16.47)

Design efforts should focus on reducing the switching loss of both transistors as well as generating the input driving signals. Class E The idea behind the Class E PA is to employ non-overlapping output voltage and output current waveforms. Several criteria for optimizing the performance can be found in Reference 42. Following these guidelines, Class E PAs have high power efficiency, simplicity, and relatively high tolerance to circuit variations.43 Since there is no power loss in the transistor as well as in the other passive components, the ideal power efficiency is 100%. Figure 16.29 shows a class E PA, and the corresponding waveforms are given in Fig. 16.30. © 2003 by CRC Press LLC

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FIGURE 16.29

Class E power amplifier.

FIGURE 16.30

Waveforms of Class E operation.

491

The Class E waveforms indicate that the transistor should be completely off before the voltage across it changes, and that the device should be completely on before it starts to allow current to flow through it. References 44 and 45 demonstrate practical Class E operation at RF frequencies using a GaAs process.

Practical Considerations for RF Power Amplifiers More recently, single-chip solutions for RF transceivers have become a goal for modern wireless com­ munications due to potential savings in power, size, and cost. CMOS must clearly be the technology of choice for a single-chip transceiver due to the large amount of digital baseband processing required. However, the power amplifier design presents a bottleneck toward full integration, since CMOS power amplifiers are still not available. The requirements of low supply voltage, gigahertz-band operation, and high output power make the implementation of CMOS PAs very demanding. The proposal of “microcell” communications may lead to a relaxed demand for output power levels that can be met by designs such as that described in Reference 46, where a CMOS Class C PA has demonstrated up to 50% power efficiency with 20 mW output power. Non-linear power amplifiers seem to be popular for modern wireless communications due to their inherent high power efficiency. Since significant power losses occur in the passive inductors as well as the switching devices, the availability of on-chip, low-loss passive inductors is important. The implemen­ tation of CMOS on-chip spiral inductors has therefore become an active research topic.47 © 2003 by CRC Press LLC

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Due to the poor spectral efficiency of a constant envelope modulation scheme, the high power efficiency benefit of non-linear power amplifiers is eliminated. A recently proposed linear transmitter using a non­ linear power amplifier may prove to be an alternative solution.48 The development of high mobility devices such as SiGe HBTs has led to the design of PAs demonstrating output power levels up to 23 dBm at 1.9 GHz with power-added efficiency of 37%.49 Practical power amplifier designs require that much attention be paid to issues of package and harmonic terminations. Power losses in the matching networks must be absolutely minimized, and tradeoffs between power-added efficiency and linearity are usually achieved through impedance matching. Although GaAs processes provide low-loss impedance matching structures on the semi-insulating substrate, good shielding techniques for CMOS may prove to be another alternative.

Conclusions Although linear power amplifiers provide conventional “easy-design” characteristics and linearity for modulation schemes such as π/4-DQPSK, modern wireless transceivers are more likely to employ non-linear power amplifiers due to their much higher power efficiency. As the development of highquality on-chip passive components makes progress, the trend toward full integration of the PA is becoming increasingly plausible. The rapid development of CMOS technology seems to be the most promising choice for PA integration, and vast improvements in frequency performance have been gained through device scaling. These improvements are expected to continue as silicon CMOS technologies scale further, driven by the demand for high-performance microprocessors. The further development of high mobility devices such as SiGe HBTs may finally see GaAs MOSFETs being replaced by wireless communication applications, since SiGe technology is compatible with CMOS.

16.6 Applications of High-Q Resonators in IF-Sampling Receiver Architectures Transconductance-C (gm-C) filters are currently the most popular design approach for realizing continuous-time filters in the intermediate frequency range in telecommunications systems. This section will consider the special application area of high-Q resonators for receiver architectures employ­ ing IF sampling.

IF Sampling A design approach for contemporary receiver architectures that is currently gaining popularity is IF digitization, whereby low-frequency operations such as second mixing and filtering can be performed more efficiently in the digital domain. A typical architecture is shown in Fig. 16.31. The IF signal is digitized, multiplied with the quadrature phases of a digital sinusoid, and lowpass filtered to yield the quadrature baseband signals. Since processing takes place in the digital domain, I/Q mismatch problems are eliminated. The principal issue in this approach, however, is the performance required

FIGURE 16.31

IF-sampling receiver.

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from the A/D converter (ADC). Noise referred to the input of the ADC must be very low so that selectivity remains high. At the same time, the linearity of the ADC must be high to minimize corruption of the wanted signal through intermodulation effects. Both the above requirements should be achieved at an input bandwidth commensurate with the value of the IF frequency, and at an acceptable power budget. Oversampling has become popular in recent years because it avoids many of the difficulties encountered with conventional methods for A/D and D/A conversion. Conventional converters are often difficult to implement in fine-line, very large-scale integration (VLSI) technology, because they require precise analog components and are very sensitive to noise and interference. In contrast, oversampling converters trade off resolution in time for resolution in amplitude, in such a way that the imprecise nature of the analog circuits can be tolerated. At the same time, they make extensive use of digital signal processing power, taking advantage of the fact that fine-line VLSI is better suited for providing fast digital circuits than for providing precise analog circuits. Therefore, IF-digitization techniques utilizing oversampling SigmaDelta modulators are very well suited to modern sub-micron CMOS technologies, and their potential has made them the subject of active research. Most Delta-Sigma modulators are implemented with discrete-time circuits, switched-capacitor (SC) implementations being by far the most common. This is mainly due to the ease with which monolithic SC filters can be designed, as well as the high linearity which they offer. The demand for high-speed Σ∆ oversampling ADCs, especially for converting bandpass signals, makes it necessary to look for a technique that is faster than switched-capacitor. This demand has stimulated researchers to develop a method for designing continuous-time ∆Σ ADCs. Although continuous-time modulators are not easy to integrate, they possess a key advantage over their discrete-time counterparts. The sampling operation takes place inside the modulator loop, making it is possible to “noise-shape” the errors introduced by sampling, and provide a certain amount of anti-aliasing filtering at no cost. On the other hand, they are sensitive to memory effects in the DACs and are very sensitive to jitter. They must also process continuous-time signals with high linearity. In communications applications, meeting the latter requirement is complicated by the fact that the signals are located at very high frequencies. As shown in Fig. 16.32, integrated bandpass implementations of continuous-time modulators require integrated continuous-time resonators to provide the noise shaping function. The gm-C approach of realizing continuous-time resonators offers advantages of complete system integration and total design freedom. However, the design of CMOS high-Q high-linearity resonators at the tens of MHz is very challenging. Since the linearity of the modulator is limited by the linearity of the resonators utilized, the continuous-time resonator is considered to be the most demanding analog sub-block of a bandpass con­ tinuous-time Sigma-Delta modulator. Typical specifications for a gm-C resonator used to provide the noiseshaping function in a Σ∆ modulator in a mobile receiver (see Fig. 16.32) are summarized in Table 16.4.

Linear Region Transconductor Implementation The implementation of fully integrated, high-selectivity filters operating at tens to hundreds of MHz provides benefits for wireless transceiver design, including chip area economy and cost reduction. The main disadvantages of on-chip active filter implementations when compared to off-chip passives include increased power dissipation, deterioration in the available dynamic range with increasing Q, and Q and resonant frequency integrity (because of process variations, temperature drifts, and aging, automatic tuning is often unavoidable, especially in high-Q applications). The transconductor-capacitor (gm-C) technique is a popular technique for implementing high-speed continuous time filters and is widely used in many industrial applications.52 Because gm-C filters are based on integrators built from an open-loop transconductance amplifier driving a capacitor, they are typically very fast but have limited linear dynamic range. Linearization techniques that reduce distortion levels can be used, but often lead to a compromise between speed, dynamic range, and power consumption. As an example of the tradeoffs in design, consider the transconductor shown in Fig. 16.33. This design consists of a main transconductor cell (M1, M2, M3, M4, M10, M11, and M14) with a negative resistance © 2003 by CRC Press LLC

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Continuous-time Σ∆ A/D in IF-sampling receiver. TABLE 16.4 Fully Integrated ContinuousTime Resonator Specifications Resonator Specifications Center frequency Quality factor Spurious free dynamic range Power dissipation

50 MHz 50 >30 dB Minimal

load (M5, M6, M7, M8, M9 , M12, and M13). Transistors M1 and M2 are biased in the triode region of operation using cascode devices M3 and M4 and determine the transconductance gain of the cell. In the triode region of operation, the drain current versus terminal voltage relation can be approximated (for simple hand calculations) as ID = K[2(VGS – VT)VDS – VDS2], where K and VT are the transconductance parameter and the threshold voltage respectively. Assuming that VDS is constant for both M1 and M2, both the differential mode and the common mode transconductance gains can be derived as GDM = GCM = 2KVDS , which can thus be tuned by varying VDS . The high value of common-mode transconductance is undesirable since it may result in regenerative feedback loops in high-order filters. To improve the CMRR transistor and avoid the formation of such loops, M10 is used to bias the transconductor, thus transforming it from a pseudo-differential to a fully differential transconductor.53 Transistors M11 and M14 constitute a floating voltage source, thus main­ taining a constant drain-source voltage for M1 and M2. The non-linearities in the voltage-to-current transfer of this stage are mainly due to three effects. The first is the finite impedance levels at the sources of the cascode devices, which cause a signal-dependent variation of the corresponding drain-source voltages of M1 and M2. A fast floating voltage source and large cascode transistors therefore need to be used to minimize this non-linearity. The second cause of non-linearity is the variation of carrier mobility µ of the input devices M1 and M2 with VGS – VT , which becomes more apparent when short-channel devices are used (K = µ ⋅ Cox ⋅ W/2 ⋅ L). A simple first-order model for transverse-field mobility degradation is given by µ = µ0 /(1 + θ ⋅ (VGS – VT)), where µ0 and θ

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FIGURE 16.33

495

Triode region transconductor.

are the zero field mobility and the mobility reduction parameter, respectively. Using this model, the third-order distortion can be determined by a Maclaurin series expansion as θ2/4(1 + θ(VCM – VT)).54 This expression cannot be regarded as exact, although it is useful to obtain insight. Furthermore, it is valid only at low frequencies, where reactive effects can be ignored and the coefficients of the Maclaurin series expansion are frequency independent. At high frequencies or when very low values of distortion are predicted by the Maclaurin series method, a generalized power series method (Volterra series) must be employed.55,56 Finally, a further cause of non-linearity is mismatch between M1 and M2, which can be minimized by good layout. A detailed linearity analysis of this transconductance stage is presented in Reference 60. To provide a load for the main transconductor cell, a similar cell implemented by p-devices is used. The gates of the linear devices M5 and M6 are now cross-coupled with the drains of the cascode devices M7 and M8. In this way, weak positive feedback is introduced. The differential-mode output resistance can now become negative and is tuned by the VDS of M5 and M6 (M12 and M13 form a floating voltage source), while the common-mode output resistance attains a small value. When connected to the output of the main transconductor cell as shown in Fig. 16.33, the crosscoupled p-cell forms a high-ohmic load for differential signals and a low-ohmic load for common-mode signals, resulting in a controlled common-mode voltage at the output.54,57 CMRR can be increased even further using M10, as described previously. Transistor M9 is biased in the triode region of operation and is used to compensate the offset common-mode voltage at the output. The key performance parameter of an integrator is the phase shift at its unity-gain frequency. Devia­ tions from the ideal –90° phase include phase lead due to finite dc gain and phase lag due to highfrequency parasitic poles. In the transconductor design of Fig. 16.33, dc gain is traded for phase accuracy, thus compensating the phase lag introduced by the parasitic poles. The reduction in dc gain for increased phase accuracy is not a major problem for bandpass filter applications, since phase accuracy at the center frequency is extremely important while dc gain has to be adequate to ensure that attenuation specifications are met at frequencies below the passband. From simulation results using parameters from a 0.8-µm CMOS process, with the transconductor unity gain frequency set at 50 MHz, third-order intermodulation components were observed at –78 dB with respect to the fundamental signals (two input signals at 49.9 MHz and 50.1 MHz were applied, each at 50 mVpp).

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FIGURE 16.34

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Biquad bandpass.

A gm-C Bandpass Biquad Filter Implementation The implementation of on-chip high-Q resonant circuits presents a difficult challenge. Integrated passive inductors have generally poor quality factors, which limits the Q of any resonant network in which they are employed. For applications in the hundreds of MHz to a few GHz, one approach is to implement the resonant circuit using low-Q passive on-chip inductors with additional Q-enhancing circuitry. How­ ever, for lower frequencies (tens of MHz), on-chip inductors occupy a huge area and this approach is not attractive. As disscussed above, an alternative method is to use active circuitry to eliminate the need for inductors. gm-C-based implementations are attractive due to their high-speed potential and good tunability. A bandpass biquadratic section based upon the transconductor of Fig. 16.33 is shown in Fig. 16.34. The transfer function of Fig. 16.34 is given by: (1 + s ⋅ R o ⋅ C ) g mi ⋅ R o Vo ⋅ --------------------------------------------------------------------------------------------------------- = -------------------2 Vi (R o ⋅ C)  2 2 ⋅ R o + g m 2 ⋅ R o 2 ⋅ R 1 + g m 2 ⋅ R o 2  - + ----------------------------  s + s ---------------------------------------------2 2 2 Ro ⋅ C Ro ⋅ C  

(16.48)

Ro represents the total resistance at the nodes due to the finite output resistance of the transconductors. R represents the effective resistance of the linear region transistors in the transconductor (see Fig. 16.33), and is used here to introduce damping and control the Q. From Eq. (16.48), it can be shown that ωo ≈ gm /C, Q ≈ gm ⋅ Ro /(2 + Ro ⋅ R ⋅ gm2), Q max = Q r = 0 = (g m ⋅ R o ) ⁄ 2 and Ao = gmi ⋅ Q. Thus, gm is used to set the central frequency, R is used to control the Q, and gmi controls the bandpass gain Ao. A dummy gmi is used to provide symmetry and thus better stability due to process variations, temperature, and aging. One of the main problems when implementing high-Q high-frequency resonators is maintaining the stability of the center frequency ωo and the quality factor Q. This problem calls for very careful layout and the implementation of an automatic tuning system. Another fundamental limitation regarding available dynamic range occurs: namely, that the dynamic range (DR) of high-Q gm-C filters has been found to be inversely proportional to the filter Q.57 The maximum dynamic range is given by: 2

2

V max V max ⋅ C DR = -------------2 = --------------------------------4 ⋅ k⋅T⋅ξ⋅Q V noise

(16.49)

where Vmax is the maximum rms voltage across the filter capacitors, C is the total capacitance, k is Boltzman’s constant, T is the absolute temperature, and ξ is the noise factor of the active circuitry (ξ = 1 corresponds to output noise equal to the thermal noise of a resistor of value R = 1/gm, where gm is the transconductor value used in the filter).

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In practice, the dynamic range achieved will be less than this maximum value due to the amplification of both noise and intermodulation components around the resonant frequency. This is a fundamental limitation, and the only solution is to design the transconductors for low noise and high linearity. The linearity performance in narrowband systems is characterized by the spurious-free dynamic range (SFDR). SFDR is defined as the signal-to-noise ratio when the power of the third-order intermodulation products equals the noise power. As shown in Reference 60, the SFDR of the resonator in Fig. 16.34 is given by: 2

3 ⋅ V o, peak ⋅ C 1 -  -----------------------------SFDR = -----------------------2 ⁄ 3  4 ⋅ ξ ⋅ IM  3, int 2 (k ⋅ T )

2⁄3

1 ------2 Q

(16.50)

where IM3, int is the third-order intermodulation point of the integrator used to implement the resonator. The spurious free dynamic range of the resonator thus deteriorates by 6 dB if the quality factor is doubled, assuming that the output swing remains the same. In contrast, implementing a resonant circuit using low-Q passive on-chip inductors with additional Q-enhancing circuitry leads to a dynamic range ampli­ fied by a factor Qo, where Qo is the quality factor of the on-chip inductor itself.59 However, as stated above, for frequencies in the tens of MHz, on-chip inductors occupy a huge area and thus the Qo improvement in dynamic range is not high enough to justify the area increase. Simulation Results To confirm operation, the filter shown in Fig. 16.34 has been simulated in HSPICE using process param­ eters from a commercial 0.8-µm CMOS process. Figure 16.35 shows the simulated frequency and phase response of the filter for a center frequency of 50 MHz and a quality factor of 50. Figure 16.36 shows the simulated output of the filter when the input consists of two tones at 49.9 MHz and 50.1 MHz, respectively, each at 40 mVpp. At this level of input signal, the third-order intermodulation components were found to be at the same level as the noise. Thus, the predicted SFDR is about 34 dB with Q = 50. Table 16.5 summarizes the simulation results.

FIGURE 16.35

Simulated bandpass frequency response.

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Simulated two-tone intermodulation test.

TABLE 16.5 Simulation Results Power dissipation (Supply voltage = 5 V) Common-mode output offset Center frequency Quality factor Output noise voltage (integrated over the band from 40 MHz to 60 MHz with Q = 50) Output signal voltage (so that intermodulation components are at the same level as the noise, Q = 50) Spurious free dynamic range (Q = 50)

12.5 mW 0, c > 0 d>0

The Type A factor corresponds to a pole on the –σ axis. If a = 0, then the factor corresponds to a pole on the imaginary axis, and so only one such factor is allowed. Type B factors correspond to poles in the left-half s-plane (LHP), and Type C factors correspond to poles on the imaginary axis. 6. The coefficients of the numerator and denominator polynomials of a driving-point network function of an LLFT network with no dependent sources are positive. The coefficients of the denom­ inator polynomial of a transfer network function are all one sign. Without loss of generality, we take the sign to be positive. But some or all of the coefficients of the numerator polynomial of a transfer network function may be negative. A polynomial made up of the factors listed in Table 23.3 would have the form:

[

]

(

)

Q(s ) = (s + a1 )L (s + b1 ) + c12 L s 2 + d12 L 2

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7. There are no missing powers of s in the numerator and denominator polynomials of a drivingpoint network function of an LLFT network with no dependent sources unless all even or all odd powers of s are missing or the constant term is missing. This statement holds for the denominator polynomials of transfer functions of such networks, but there may be missing powers of s in the numerator polynomials of transfer functions. Property 7 is easily illustrated by combining types of factors from Table 23.3. Thus, a polynomial consisting only of type A factors contains all powers of s between the highest power and the constant term unless one of the “a” constants is zero. Then, the constant term is missing. Two a constants cannot be zero because then there would be two roots on the imaginary axis at the same location. The roots on the imaginary axis would not be simple. A polynomial made up of only type B factors contains all powers of s, and a polynomial containing only type C factors contains only even powers of s. A polynomial constructed from type C factors except for one A type factor with a = 0 contains only odd powers of s. If a polynomial is constructed from type B and C factors, then it contains all power of s. 8. The orders of the numerator and denominator polynomials of a driving-point network function of an LLFT network, which contains no dependent sources can differ by no more than one. The limiting behavior at high frequency must be that of an inductor, a resistor, or a capacitor. That is, if Ndp(s) is a driving-point network function, then K1s  lim N dp (s ) = K 2 s→∞  K 3 s where Ki , = 1, 2, 3, are real constants. 9. The terms of lowest order in the numerator and denominator polynomials of a driving-point network function of an LLFT network containing no dependent sources can differ in order by no more than one. The limiting behavior at low frequency must be that of an inductor, a resistor, or a capacitor. That is, K 4s  lim N dp (s ) = K 5 s→0  K 6 s where the constants Ki , i = 4, 5, 6, are real constants. 10. The maximum order of the numerator polynomials of the dimensionless transfer functions G12 , G21, 12, and 21, of an LLFT network containing no dependent sources is equal to the order of the denominator polynomials. The maximum order of the numerator polynomial of the transfer functions Y12, Y21, Z12, and Z21 is equal to the order of the denominator polynomial plus 1. However, the minimum order of the numerator polynomial of any transfer function may be zero. If dependent sources are included in an LLFT network, then it is possible for the network to have poles in the RHP or multiple poles at locations on the imaginary axis. However, an important application of stable networks containing dependent sources is to mimic (simulate) the behavior of LLFT networks that contain no dependent sources. For example, networks that contain resistors, capacitors, and dependent sources can mimic the behavior of networks containing only resistors, capacitors, and inductors. Thus, low-frequency filters can be constructed without the need for heavy, expensive inductors that would ordinarily be required in such applications.

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23.2 Network Theorems In this section, we provide techniques, strategies, equivalences, and theorems for simplifying the analysis of LLFT networks or for checking the results of an analysis. They can save much work in the analysis of some networks if one remembers to apply them. Thus, it is convenient to have them listed in one place. To begin, we list nine equivalences that are often called source transformations.

Source Transformations Table 23.4 is a collection of memory aids for the nine source transformations. Source transformations are simple ways the elements and sources externally connected to a network N can be combined or eliminated without changing the voltages and currents within network N thereby simplifying the problem of finding a voltage or current within N. Source transformation one in Table 23.4 shows the equivalence between two voltage sources connected in series and a single voltage source having a value that is the sum of the voltages of the two sources. A double-headed arrow is shown between the two network representations because it is sometimes advan­ tageous to use this source transformation in reverse. For example, if a voltage source that has both DC and AC components is applied to a linear network N, it may be useful to represent that voltage source as two voltage sources in series — one a DC source and the other an AC source. Source transformation two shows two voltage sources connected in parallel. Unless V1 and V2 are equal, the network would not obey Kirchhoff ’s law as evidenced by a loop equation written in the loop formed by the two voltage sources. A network that does not obey Kirchhoff ’s laws is termed a contra­ diction. Thus, a single-headed arrow is shown between the two network representations. Source transformations three and four are duals, respectively, of source transformations two and one. The current sources must be equal in transformation three or else Kirchhoff ’s law would not be valid at the node indicated, and the circuit would be a contradiction. Source transformation five shows that the circuit M1 can be removed without altering any of the voltages and currents inside N. Whether M1 is connected as shown or is removed, the voltage applied to N remains Vs . However, the current supplied by the source Vs changes from Is to I1. Source transformation six shows that circuit M2 can be replaced by a short circuit without affecting voltages and currents in N. Whether M2 is in series with the current source I1 as shown or removed, the current applied to N is the same. However, if network M2 is removed, then the voltage across the current source changes from Vs to V1. Source transformation seven is sometimes termed a Thévenin circuit to Norton circuit transforma­ tion. This transformation, as shown by the double-headed arrow, can be used in the reverse direction. Thévenin’s theorem is discussed thoroughly later in this section. Source transformation eight is sometimes described as “pushing a voltage source through a node,” but we will term it as “splitting a voltage source.” Loop equations remain the same with this transfor­ mation, and the current leaving network N through the lowest wire continues to be Is. Source transformation nine shows that if a current source is not in parallel with one element, then it can be “split” as shown. Now, each one of the current sources I1 has an impedance in parallel. Thus, analysis of network N may be simplified because source transformation seven can be applied. Source transformations cannot be applied to all networks, but when they can be employed, they usually yield useful simplifications of the network. Example 2. Use source transformations to find V0 for the network shown. Initial current through the inductor in the network is zero. Solution. The network can be readily simplified by employing source transformation five from Table 23.4 to eliminate R1 and also I2 . Then, source transformation six can be used to eliminate V1 because it is an element in series with a current source. The results to this point are illustrated in Fig. 23.13(a). If we © 2003 by CRC Press LLC

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TABLE 23.4

Source Transformations 2.

1. + V1 −

+ −

N

+ − V 2

V1+V2

V1

N

3.

+ V2 −

+ −

V1 = V2 + −

N

4. I1

I1 + I2 N

N

N I1

I1 = I2

I2 5.

N

I2

6. Is

I1

I1 +

Vs

N

+ −

N

M1

Vs

+

M2

+ −

N

V1

+ Vs −

N

V1 I1

I1 −

N

−

7. I1 V1

I1

Z

+ −

V1 Z N

N

Z

8.

V1

I1

Z1

Is

Z2

+ −

N V1

Z1 I2 + −

+ −

Z2

N

V1

I1 + I2 = Is 9.

Z1

I1

Z1

I1

Z2

N I1

Z2

N

N is an arbitrary network in which analysis for a voltage or current is to be performed. M1 is an arbitrary oneport network or network element except a voltage source. M2 is an arbitrary one-port network or network element except a current source. It is assumed there is no magnetic coupling between N and M1 or M2. There are no dependent sources in N in Source Transformation 5 that depend on Is. Furthermore, there are no dependent sources in N in Source Transformation 6 that depend on Vs . However, M1 and M2 can have dependent sources that depend on voltages or currents in N. Z, Z1 and Z2 are one-port impedances. © 2003 by CRC Press LLC

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V1 + −

R1

I1

V2

R2

L

+ Vo

+ −

I2

−

L I1

R2

FIGURE 23.12 Network for Example 2.

+

Vo

+ V2 −

+

V2 sL

L

R2 Vo

I1

−

−

(a)

(b)

+ sL R2 sL + R2

V I1 + 2 sL

Vo −

(c)

FIGURE 23.13 (a, b, c) Applications of source transformations to the network in Fig. 23.12.

then apply transformation seven, we obtain the network in Fig. 23.13(b). Next, we can apply transfor­ mation four to obtain the single loop network in Fig. 23.13(c). The output voltage can be written in the frequency domain as V   sLR2   V0 =  I1 + 2    sL   sL + R2  Source transformations can often be used advantageously with the following theorems.

▫

Dividers Current dividers and voltage dividers are circuits that are employed frequently, especially in the design of electronic circuits. Thus, dividers must be analyzed quickly. The relationships derived next satisfy this need. Figure 23.14 is a current divider circuit. The source current Is divides between the two impedances, and we wish to determine the current through Z2. Writing a loop equation for the loop indicated, we have I 2 Z 2 − ( I s − I 2 ) Z1 = 0

(23.26)

from which we obtain I 2 = Is

Z1 Z1 + Z 2

I2 Is

Z1

Z2

FIGURE 23.14 A current divider. © 2003 by CRC Press LLC

(23.27)

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Frequency Domain Methods

A

Z1 V1

Z2 + V −0

+ −

+

− V2

FIGURE 23.15 Enhanced voltage divider.

A circuit that we term an enhanced voltage divider is depicted in Fig. 23.15. This circuit contains two voltage sources instead of the usual single source, but the enhanced voltage divider occurs more often in electronic circuits. Writing a node equation at node A and solving for V0 , we obtain V0 =

V1 Z 2 + V2 Z1 Z1 + Z 2

(23.28)

If V2 , for example, is zero, then the results from the enhanced voltage divider reduce to those of the single source voltage divider. Example 3. Use (23.28) to find V0 for the network in Fig. 23.16. V s

Z1

+ Z2

VA + −

VO

− VB +

−

FIGURE 23.16 Circuit for Example 3.

Solution. The network in Fig. 23.16 matches with the network used to derive (23.28) even though it is drawn somewhat differently and has three voltage sources instead of two. However, we can use (23.28) to write the answer for V0 by inspection. V0 =

(V − (V s))Z A

z

− VB Z1

Z1 + Z 2

▫ The following example illustrates the use of source transformations together with the voltage divider. Example 4. Find V0 for the network shown in Fig. 23.17. The units of K, the coefficient of the dependent source, are ohms, and the capacitor is initially uncharged. C R1 I

+ −

+ R2 KI

VO −

FIGURE 23.17 Network for Example 4.

Solution. We note that the dependent voltage source is not in series with any one particular element and that the independent current source is not in parallel with any one particular element. However, we can split both the voltage source and the current source using source transformations eight and nine, respectively, from Table 23.4. Then, employing transformations five and seven, we obtain the network configuration depicted in Fig. 23.18, for which we can use the voltage divider to write: © 2003 by CRC Press LLC

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+ C R2

R1 IR1

+ −

KI

+ −

VO KI

+ −

FIGURE 23.18 Results after employing source transformations on the network in Fig. 23.17.

−

V0 =

(

)

I ( K + R1 ) R2 + KI R1 + (1 sC )

R1 + R2 + (1 sC )

It should be mentioned that the method used to find V0 in this example is not the most efficient one. For example, loops can be chosen for the network in Fig. 23.17, so only one unknown loop is current. However, source transformations and dividers become more powerful analysis tools as they are coupled with additional network theorems.

Superposition Superposition is a property of all linear networks, and whether it is used directly in the analysis of a network or not, it is a concept that is valuable in thinking about LLFT networks. Consider the LLFT network shown in Fig. 23.19 in which, say, we wish to solve for I1. Assume the network has n independent loops, and, for simplicity, assume no sources are within the box in the figure and that initial voltages across capacitors and initial currents through inductors are zero or are represented by independent sources external to the box. Note that one dependent source is shown in Fig. 23.19 that depends on a voltage Vx in the network and that two independent sources, V1 and V2, are applied to the network. If loops are chosen so that each source has only one loop current flowing through it as indicated in Fig. 23.19, then the loop equations can be written as  V1     V2  z11    KVx  z 21   =   0  L     M  z  n1    0   

V1

+ −

+ −

L

z 22

L

L

O

z n2

L

z1n   z 2n   L  z nn 

 I1    I 2    M   I   n

(23.29)

I1 LLFT Network

KVx

z12

I2

+ −

V2

I3

FIGURE 23.19 LLFT network with three volt­ age sources, of which one is dependent. © 2003 by CRC Press LLC

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where the elements of the loop impedance matrix are defined in the section describing network functions. Solving for I1 using Cramer’s rule, we have: I1 = V1

∆11 ∆ ∆ + V2 21 + KVx 31 ∆ ∆ ∆

(23.30)

where ∆ is the determinant of the loop impedance matrix, and ∆j1, j = 1, 2, 3, are cofactors. The expression for I1 given in (23.30) is an intermediate and not a finished solution. The finished solution would express I1 in terms of the independent sources and the parameters (Rs, Ls, Cs, Ms, and Ks) of the network and not in terms of an unknown Vx . Thus, one normally has to eliminate Vx from the expression for I1; but the intermediate expression for I1 illustrates superposition. There are three components that add up to I1 in (23.30) — one for each source including one for the dependent source. Furthermore, we see that each source is multiplied by a transadmittance (or a driving-point admittance in the case of V1 ). Thus, we can write: I1 = V1Y11 + V2Y12 + KVxY13

(23.31)

where each admittance is found from the port at which a voltage source (whether independent or dependent) is applied. The response variable for each of these admittances is I1 at port 1. The simple derivation that led to (23.30) is easily extended to both types of independent excitations (voltage sources and current sources) and to all four types of dependent sources. The generalization of (23.30) leads to the conclusion: To apply superposition in the analysis of a network containing at least one independent source and a variety of other sources, dependent or independent, one finds the contribution to the response from each source in turn with all other source, dependent or independent, properly removed and then adds the individual contributions to obtain the total response. No distinction is made between independent and dependent sources in the application of superposition other than requiring the network to have at least one independent source. However, if dependent sources are present in the network, the quantities (call them Vx and Ix) on which the dependent sources depend must often be eliminated from the answer by additional analysis if the answer is to be useful unless Vx or Ix are themselves the variables of independent sources or the quantities sought in the analysis. Some examples will illustrate the procedure. Example 5. Find V0 for the circuit shown using superposition. In this circuit, only independent sources are present. C + V1 −

R1

+ R2

I1

R3

VO −

FIGURE 23.20 Network for Example 5.

Solution. Two sources in the network, therefore, we abstract two fictitious networks from Fig. 23.20. The first is shown in Fig. 23.21(a) and is obtained by properly removing the current source I1 from the original network. The impedance of the capacitor can then be combined in parallel with R1 + R2 , and the contribution to V0 from V1 can be found using a voltage divider. The result is 1 C ( R1 + R2 ) V0 due to V1 = V1 R + R2 + R3 s+ 1 C ( R1 + R2 )R3 s+

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C V1

+ −

+ R2

R1

R3

VO due to V1 −

(a)

C

+ R2

R1 I1

R3

VO due to I1 −

(b)

+ + I1R1 −

R1

R2 C

R3

VO due to I1 −

(c)

FIGURE 23.21 (a, b, c) Steps in the use of superposition for finding the response to two independent sources.

The second fictitious network, shown in Fig. 23.21(b), is obtained form the original network by properly removing the voltage source V1. Redrawing the circuit and employing source transformation seven (in reverse) yields the circuit in Fig. 23.21(c). Again, employing a voltage divider, we have R1 C ( R1 + R2 ) V0 due to I1 = I1 R + R2 + R3 s+ 1 C ( R1 + R2 )R3 Then, adding the two contributions, we obtain   R1 1 V1 s +  + I1 C ( R1 + R2 )  C ( R1 + R2 )  V0 =  R1 + R2 + R3 s+ C ( R1 + R2 )R3 The next example includes a dependent source. Example 6. Find i in the network shown in Fig. 23.22 using superposition. Solution. Since there are two sources, we abstract two fictitious networks from Fig. 23.22. The first one is shown in Fig. 23.23(a) and is obtained by properly removing the dependent current source. Thus, i due to v1 = © 2003 by CRC Press LLC

v1 R1 + R2

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βi

i R1

+ V1 −

R2

R3

FIGURE 23.22 Network for Example 6.

i due to βi

i due to v1 +

V1 −

βi

R1

R1 R2

R3

R2

V1

(a)

R3 (b)

FIGURE 23.23 (a, b) Steps in the application of superposition to the network in Fig. 23.22.

Next, voltage source v1 is properly removed yielding the fictitious network in Fig. 23.23(b). An important question immediately arises about this network. Namely, why is not i in this network zero? The reason i is not zero is that the network in Fig. 23.23(b) is merely an abstracted network that concerns a step in the analysis of the original circuit. It is an artifice in the application of superposition, and the dependent source is considered to be independent for this step. Thus, i due to βi = −

βiR2 R1 + R2

Adding the two contributions, we obtain the intermediate result: i=

βiR2 v1 − R1 + R2 R1 + R2

Collecting the terms containing i, we obtain the finished solution for i: i=

v1

(β +1)R2 + R1

We note that the finished solution depends only on the independent source v1 and parameters of the ▫ network, which are R1, R2, and β. The following example involves a network in which a dependent source depends on a voltage that is neither the voltage of an independent source nor the voltage being sought in the analysis. Example 7. Find V0 using superposition for the network shown in Fig. 23.24. Note that K, the coefficient of the VCCS, has the units of siemens. + V1

+ −

Vx

−

+

R2

R1 KVx

C

VO −

FIGURE 23.24 Network for Example 7.

Solution. When the dependent current source is properly removed, the network reduces to a simple voltage divider, and the contribution to V0 due to V1 can be written as: © 2003 by CRC Press LLC

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+

R2 R1

C

KVx

VO −

FIGURE 23.25 Fictitious network obtained when the voltage source is properly removed in Fig. 23.24.

V0 due to V1 = V1

1 sC ( R1 + R2 ) +1

Then, reinserting the current source and properly removing the voltage source, we obtain the fictitious network shown in Fig. 23.25. Using the current divider to obtain the current flowing through the capacitor and then multiplying this current by the impedance of the capacitor, we have: V0 due to KVx =

KVx R1 sC ( R1 + R2 ) + 1

Adding the individual contributions to form V0 provides the equation V0 =

V1 + KVx R1 sC ( R1 + R2 ) +1

This is a valid expression for V0. It is not a finished expression however, because it includes Vx , an unknown voltage. Superposition has taken us to this point in the analysis, but more work must be done to eliminate Vx . However, superposition can be applied again to solve for Vx, or other analysis tools can be used. The results for Vx are: Vx =

V1sCR1 sC R1 + R2 + R1R2 K + R1K +1

[

]

Then, eliminating Vx from the equation for V0, we obtain the finished solution as: V0 = V1

R1K +1 sC R1 + R2 + R1R2 K + R1K +1

[

]

Clearly, superposition is not the most efficient technique to use to analyze the network in Fig. 23.24. Analysis based on a node equation written at the top end of the current source would yield a finished result for V0 with less algebra. However, this example does illustrate the application of superposition when a dependent source depends on a rather arbitrary voltage in the network. ▫ If the dependent current source in the previous example depended on V1 instead of on the voltage across R1, the network would be a different network. This is illustrated by the next example. Example 8. Use superposition to determine V0 for the circuit in Fig. 23.26. + + V1 −

R1

R2 KV1

C

VO −

© 2003 by CRC Press LLC

FIGURE 23.26 Network for Example 8.

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Frequency Domain Methods

+

R2 R1

C

KV1

VO due to KV1 −

FIGURE 23.27 A step in the application of superposition to the network in Fig. 23.26.

Solution. If the current source is properly removed, the results are the same as for the previous example. Thus, V0 due to V1 =

V1 sC ( R1 + R2 ) +1

Then, if the current source is reinserted, and the voltage source is properly removed, we have the circuit depicted in Fig. 23.27. A question that can be asked for this circuit is why include the dependent source KV1 if the voltage on which it depends, namely V1, has been set to zero? However, the network shown in Fig. 23.27 is merely a fictitious network that serves as an aid in the application of superposition, and superposition deals with all sources, whether they are dependent or independent, as if they were inde­ pendent. Thus, we can write: V0 due to KV1 =

KV1R1 sC ( R1 + R2 ) +1

Adding the contributions to form V0 , we obtain V0 = V1

KR1 +1 sC ( R1 + R2 ) +1

and this is the finished solution. In this example, we did not have the task of eliminating an unknown quantity from an intermediate result for V0 because the dependent source depended on an independent source V1, which is assumed to be known. ▫ Superposition is often useful in the analysis of circuits having only independent sources, but it is especially useful in the analysis of some circuits having both independent and dependent sources because it deals with all sources as if they were independent.

Thévenin’s Theorem Thévenin’s theorem is useful in reducing the complexity of a network so that analysis of the network for a particular voltage or current can be performed more easily. For example, consider Fig. 23.28(a), which is composed of two subnetworks A and B that have only two nodes in common. In order to facilitate analysis in subnetwork B, it is convenient to reduce subnetwork A to the network in Fig. 23.28(b) which is termed the Thévenin equivalent of subnetwork A. The requirement on the Thévenin’s equivalent

Network A

2 (a)

1

ZTH

1 Network B

+ VTH −

2

Network B

(b)

FIGURE 23.28 (a) Two subnetworks having a common pair of terminals. (b) The Thévenin equivalent for subnet­ work A. © 2003 by CRC Press LLC

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1 Network A

2

Network A (Independent Sources Removed)

+ VTH −

(a)

1

+

2

−

ZTH

(b)

FIGURE 23.29 (a) Network used for finding VTH. (b) Network used for obtaining ZTH.

network is that, when it replaces subnetwork A, the voltages and currents in subnetwork B remain unchanged. We assume that no inductive coupling occurs between the subnetworks, and that dependent sources in B are not dependent on voltages or currents in A. We also assume that subnetwork A is an LLFT network, but subnetwork B does not have to meet this assumption. To find the Thévenin equivalent network, we need only determine VTH and ZTH . VTH is found by unhooking B from A and finding the voltage that appears across the terminals of A. In other words, we abstract a fictitious network from the complete network as depicted in Fig. 23.29(a), and find the voltage that appears between the terminals that were common to B. This voltage is VTH. ZTH is also obtained from a fictitious network that is created from the fictitious network used for finding VTH by properly removing all independent sources. The effects that dependent sources have on the procedure are discussed later in this section. The fictitious network used for finding ZTH is depicted in Fig. 23.29(b). Oftentimes, the expression for ZTH cannot be found by mere inspection of this network, and, therefore, we must excite the network in Fig. 23.29(b) by a voltage source or a current source and find an expression for the other variable at the port in order to find ZTH . Example 9. Find the Thévenin equivalent of subnetwork A in Fig. 23.30. 1

A + C

R V V1

+ −

B

− 2

FIGURE 23.30 Network for Example 9.

Solution. No dependent sources exist in subnetwork A, but the capacitor has an initial voltage V across it. However, the charged capacitor can be represented by an uncharged capacitor in series with a trans­ formed voltage source V/s. The fictitious network used for finding VTH is given in Fig. 23.31(a). It should be noted that although subnetwork B has been removed and the two terminals that were connected to B are now “open circuited” in Fig. 23.31(a), current is still flowing in network A. VTH is easily obtained using a voltage divider: VTH =

V1 (s ) + VCR sCR + 1 1

1 R

C

+ V1 −

V s

+ VTH

R

− (a)

2

FIGURE 23.31 (a) Network of finding VTH. (b) Network that yields ZTH. © 2003 by CRC Press LLC

ZTH

C

(b)

2

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ZTH is obtained from the fictitious network in Fig. 23.31(b), which is obtained by properly removing the independent source and the voltage representing the initial voltage across the capacitor in Fig. 23.31(a). We see by inspection that ZTH = R/(sCR + 1). Thus, if subnetwork A is removed from Fig. 23.30 and replaced by the Thévenin equivalent network, the voltages and currents in subnetwork B remain unchanged. It is assumed that B in Fig. 23.28 has no dependent sources that depend on voltages or currents in A, although dependent sources in B can depend on voltages and currents in B. However, A can have dependent sources, and these dependent sources create a modification in the procedure for finding the Thévenin equivalent network. There may be dependent sources in A that depend on voltages and currents that also exist in A. We call these dependent sources Case I-dependent sources. There may also be dependent sources in A that depend on voltages and currents in B, and we label these sources as Case II-dependent sources. Then, the procedure for finding the Thévenin equivalent network is: VTH is the voltage across the terminals of Fig. 23.29(a). The voltages and currents that Case I-dependent sources depend on must be eliminated from the expression for VTH unless they happen to be the voltages of independent voltage sources or the currents of independent current sources in A. Otherwise, the expression for VTH would not be a finished solution. However, Case II-dependent sources are handled as if they were independent sources. That is, Case II-dependent sources are included in the results for VTH just as independent sources would be. ZTH is the impedance looking into the terminals in Fig. 23.29(b). In this fictitious network, independent sources are properly removed and Case II-dependent sources are properly removed. Case I-dependent sources remain in the network and influence the result for the Thévenin impedance. The finished solution for ZTH is a function only of the parameters of the network in Fig. 23.29(b) which are Rs, Ls, Cs, Ms (there may be inductive coupling between coils in this network), and the coefficients of the Case I-dependent sources. Thus, Case II-dependent sources, sources that depend on voltages or currents in subnetwork B, are uniformly treated as if they were independent sources in finding the Thévenin equivalent network. Some examples will clarify the issue. Example 10. Find the Thévenin equivalent network for subnetwork A in Fig. 23.32. Assume the initial current through the inductor is zero. A − Vx +

V1

L + −

R2

R1 +

−

1 Network

B

KVx

2

FIGURE 23.32 Network for Example 10.

Solution. There is one independent source and one Case I-dependent source. Figure 23.33(a) depicts the fictitious network to be analyzed to obtain VTH. No current is flowing through R2 in this figure, therefore, we can write VTH = V1 – Vx. To eliminate Vx from our intermediate expression for VTH , we can use the results of the enhanced voltage divider to write: VTH =

V1R1 + sKL(V1 − VTH ) R1 + sL

The finished solution for VTH is VTH = V1 © 2003 by CRC Press LLC

sKL + R1

(K +1)sL + R1

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− Vx +

L

+ −

+ V1 −

+

R2

R1

VTH

− Vx +

L

+ −

−

KVx

R2

R1

+ V

KVx

(a)

I

−

(b)

FIGURE 23.33 (a) Abstracted network for finding VTH. (b) Abstracted network for finding ZTH.

ZTH is obtained from Fig. 23.33(b) where a current source excitation is shown already applied to the fictitious network. Two node equations, with unknown node voltages V and –Vx , enable us to obtain I in terms of V while eliminating Vx . We also note that ZTH consists of resistor R2 in series with some unknown impedance, so we could remove R2 (replaced it by a short) if we remember to add it back later. The finished result for ZTH is ZTH = R2 +

sLR1 (K +1)sL + R1

The following example involves a network having a Case II-dependent source.

▫

Example 11. Find the Thévenin equivalent network for subnetwork A in the network illustrated in Fig. 23.34. In this instance, subnetwork B is outlined explicitly. A

C R2

R1

B R3 I

KI V1 + −

R4 + V2 −

L

FIGURE 23.34 Network for Example 11.

Solution. Subnetwork A contains one independent source and one Case II-dependent source. Figure 23.35(a) is the abstracted network for finding VTH . Thus, VTH = V1 + KIR1 Then, both V1 and the dependent source KI are deleted from Fig. 23.35(a) to obtain Fig. 23.35(b), the network used for finding ZTH . Thus, ZTH = R1. Of course, the subnetwork for which the Thévenin equivalent is being determined may have both Case I- and Case II-dependent sources, but these sources can be handled concurrently using the proce­ dures given previously. Special conditions can arise in the application of Thévenin’s theorem. One condition is ZTH = 0 and the other is VTH = 0. The conditions for which ZTH is zero are:

KI V1

+

R1

VTH

+ −

R1

ZTH

− (a)

(b)

FIGURE 23.35 (a) Network used to find VTH. (b) Network for finding ZTH. © 2003 by CRC Press LLC

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Frequency Domain Methods

1. If the circuit (subnetwork A) for which the Thévenin equivalent is being determined has an independent voltage source connected between terminals 1 and 2, then ZTH = 0. Figure 23.36(a) illustrates this case. 2. If subnetwork A has a dependent voltage source connected between terminals 1 and 2, then ZTH is zero provided neither of the port variables associated with the port formed by terminals 1 and 2 is coupled back into the network. Figure 23.36(b) is a subnetwork A for which ZTH is zero. However, Fig. 23.36(c) depicts a subnetwork A in which the port variable I is coupled back into A by the dependent source K1I. If I is considered to be a variable of subnetwork A so that K1I is a Case I-dependent source, then ZTH is not zero. The other special condition, VTH = 0, occurs if subnetwork A contains only Case I-dependent sources, no independent sources, and no Case II-dependent sources. An example of such a network is given in Fig. 23.36(d). With subnetwork B disconnected, subnetwork A is a dead network, and its Thévenin voltage is zero. The network in Fig. 23.36(c) is of interest because the dependent source K1I can be considered as a Case I- or a Case II-dependent source hinging on whether I is considered a variable of subnetwork A or B. Example 12. Solve for I in Fig. 23.36(c) using two versions of the Thévenin equivalent for subnetwork A. For the first version, consider I to be associated with A, and therefore both dependent sources are Case I-dependent sources. In the second version, consider I to be associated with B.

�

� �� ���

��

��

��

+ −

�

� �

+

�

��

−

�

�� ���

��

�� ���

�

+ −

�

�

+

�

� ��

�

+ −

�

+

�

�

��

� �� �

+ − �� �

��

−

�� ���

−

��

� ���

��

��

+ −

�

� �

�� � �� � �

FIGURE 23.36 Special cases of Thévenin’s theorem. (a, b) ZTH equals zero. (c) A port variable is coupled back into A. (d) VTH is zero.

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+

VX

−

R1

L

K1I

+ −

K2VX

+

+ + −

VX

I

−

+

R1 L

V I −

K1I

+ −

K2VX

+ −

VTH −

(b)

(a)

FIGURE 23.37 (a) Network for finding ZTH when both sources are Case I-dependent sources. (b) Network for finding VTH when a Case II-dependent source exists in the network.

Solution. If I is considered as associated with A, then VTH is zero by inspection because A contains only Case I-dependent sources. Figure 23.37(a) depicts subnetwork A with a current excitation applied in order to determine ZTH. Clearly, V = K2Vx . Also, writing a loop equation in the loop encompassed by the two dependent sources, we obtain K1 I −

Vx (sL + R1 ) = V R1

Eliminating Vx , we have K1K 2 R1

V = ZTH = I sL + R1 ( K 2 +1)

Once ZTH is obtained, it is an easy matter to write from Fig. 23.36(c): I=

[

]

V1 sL + R1 ( K 2 +1) V1 = R2 + ZTH sLR2 + R1R2 ( K 2 +1) + K1K 2 R1

If I is associated with B, then VTH is found from the network in Fig. 23.37(b) with the source K1I treated as if it were independent. The equation for VTH may contain the variable I, but Vx must be eliminated from the finished expression for VTH . We obtain VTH = I

K1K 2 R1 sL + R1 ( K 2 +1)

Also, ZTH is zero because if K1I is removed, subnetwork A reduces to a network with only a Case Idependent source and a port variable is not coupled back into the network. Finally, I can be written as: I=

V1 − VTH R2

which yields the same result for I as was found previously.

▫

The following example illustrates the interplay that can be achieved among these theorems and source transformations. Example 13. Find V0 /V1 for the bridged T network shown in Fig. 23.38. Solution. The application of source transformation eight to the network yields the ladder network in Fig. 23.39(a). Thévenin’s theorem is particularly useful in analyzing ladder networks. If it is applied to © 2003 by CRC Press LLC

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Frequency Domain Methods

Z5 Z1 V1

Z3

+ −

Z2

+ Z4

V0 −

FIGURE 23.38 Network for Example 13.

(a) Z1

Z3

V1 + −

Z2

Z5

+ V0

V1 + −

Z4

−

(b) Z1||Z2 Z2 V1 Z +Z 1 2

Z3

+ −

+

Z4||Z5 + V Z4 1 Z +Z − 4 5

V0 −

FIGURE 23.39 (a) Results after applying source transformation eight to the network shown in Fig. 23.38. (b) Results of two applications of Thévenin’s theorem.

the left and right sides of the network, taking care not to obscure the nodes between which V0 exists, we obtain the single loop network in Fig. 23.39(b). Then, using a voltage divider, we obtain

[

]

Z 4 Z1 ( Z 2 + Z 3 ) + Z 2 Z 3 + Z 2 Z 5 V0 = V1 ( Z1 + Z 2 )( Z 3 Z 4 + Z 3 Z 5 + Z 4 Z 5 ) + Z1 Z 2 ( Z 4 + Z 5 )

Norton’s Theorem If a source transformation is applied to the Thévenin equivalent network consisting of VTH and ZTH in Fig. 23.28(b), then a Norton equivalent network, illustrated in Fig. 23.40(a), is obtained. The current source Isc = VTH /ZTH, ZTH ≠ 0. If ZTH equals zero in Fig. 23.28(b), then the Norton equivalent network does not exist. The subscripts “sc” on the current source stand for short circuit and indicate a procedure for finding the value of this current source. To find Isc for subnetwork A in Fig. 23.28(a), we disconnet subnetwork B and place a short circuit between nodes 1 and 2 of subnetwork A. Then, Isc is the current flowing through the short circuit in the direction indicated in Fig. 23.40(b). Isc is zero if subnetwork A has only Case I-dependent sources and no other sources. ZTH is found in the same manner as for Thévenin’s theorem. It is sometimes more convenient to find Isc and VTH instead of ZTH . 1 1

Isc

ZTH

A 2 2

(a)

(b)

FIGURE 23.40 (a) Norton equivalent network. (b) Reference direction for Isc . © 2003 by CRC Press LLC

Isc

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I1

+ − R1

V1 + −

L

KI1 B

R2

ZL

FIGURE 23.41 Network for Example 14. I1 V1 + −

+ −

L

R1

KI1 Isc

R2

(a) I1 + V1 −

R1

L

+ VTH −

+ − KI1 R2

(b)

FIGURE 23.42 (a) Network for finding Isc. (b) Network for VTH .

Example 14. Find the Norton equivalent for the network “seen” by ZL in Fig. 23.41. That is, ZL is subnetwork B and the rest of the network is A, and we wish to find the Norton equivalent network for A. Solution. Figure 23.42(a) is the network with ZL replaced by a short circuit. An equation for Isc can be obtained quickly using superposition. This yields I sc = I1 +

KI1 R2

but I1 must be eliminated from this equation. I1 is obtained as: I1 = V1 /(sL + R1). Thus,  K V1 1 +   R2  I sc = sL + R1 VTH is found from the network shown in Fig. 23.42(b). The results are: VTH =

V1 ( K + R2 )

sL + R1 + R2 + K

ZTH can be found as VTH /Isc .

Thévenin’s and Norton’s Theorems and Network Equations Thévenin’s and Norton’s theorems can be related to loop and node equations. Here, we examine the relationship to loop equations by means of the LLFT network in Fig. 23.43. Assume that the network N in Fig. 23.43 has n independent loops with all the loop currents chosen in the same direction. Without loss of generality, assume that only one loop current, say I1, flows through ZL as shown so that ZL appears © 2003 by CRC Press LLC

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LLFT Network N

ZL

I1

FIGURE 23.43 An LLFT network N with n independent loops.

in only one loop equation. For simplicity, assume that no dependent sources or inductive couplings in N exist, and that all current sources have been source-transformed so that only voltage source excitations remain. Then the loop equations are V1  z11    V2  z 21   =  M  M    V  z  n  n1

z12

L

z 22

L

M

O

z n2

L

z1n   z 2n   M   z nn 

I1    I 2    M    I   n

(23.32)

where Vi , i = 1, 2, …, n, is the sum of all voltage sources in the ith loop. Thus, Vi may consist of several terms, some of which may be negative depending on whether a voltage source is a voltage rise or a voltage drop. Also, the impedances zij are given by D   z ij = ± Rij + sLij + ij  s  

(23.33)

where i, j = 1, 2, …, n, and where the plus sign is taken if i = j, and the minus sign is used if i ≠ j. Rij is the sum of the resistances in loop i if i = j, and Rij is the sum of the resistances common to loops i and j if i ≠ j. Similar statements apply to the inductances Lij and to the reciprocal capacitances Dij . The currents Ii , i = 1, 2, …, n, are the unknown loop currents. Note that ZL is included only in z11 so that z11 can be written as z11 = z11A + ZL, where z11A is the sum of all the impedances around loop one except ZL. Solving for I1 using Cramer’s rule, we have

I1 =

V1

z12

L

z1n

V2

z 22

L

z 2n

M

M

O

M

Vn

z n2

L

z nn

∆

(23.34)

where ∆ is the determinant of the loop impedance matrix. Thus, we can write I1 =

V1∆11 + V2 ∆ 21 + L + Vn ∆ n1 z11∆11 + z 21∆ 21 + L + z n1∆ n1

(23.35)

or ∆ 21 ∆ + L + Vn n1 ∆11 ∆11 I1 = ∆ 21 ∆ z11 + z 21 + L + z n1 n1 ∆11 ∆11 V1 + V2

© 2003 by CRC Press LLC

(23.36)

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where ∆ij are cofactors of the loop impedance matrix. Then, forming the product of I1 and ZL, we have:  ∆ ∆  Z L  V1 + V2 21 + L + Vn n1  ∆11 ∆11   I1 Z L = ∆ 21 ∆ Z L + z11A + z 21 + L + z n1 n1 ∆11 ∆11

(23.37)

If we take the limit of I1ZL as ZL approaches infinity, we obtain the “open circuit” voltage VTH . That is,  ∆ ∆  lim I1 Z L = VTH =  V1 + V2 21 + L + Vn n1  ∆11 ∆11  

(23.38)

Z L →∞

and if we take the limit of I1 as ZL approaches zero, we obtain the “short circuit” current Isc : lim I1 = I sc =

Z L →0

VTH ∆ 21 ∆ z11A + z 21 + L + z n1 n1 ∆11 ∆11

(23.39)

Finally, the quotient of VTH and Isc yields: VTH ∆ ∆ = ZTH = z11A + z 21 21 + L + z n1 n1 I sc ∆11 ∆11

(23.40)

If network N contains coupled inductors (but not coupled to ZL ), then some elements of the loop impedance matrix may be modified in value and sign. If network N contains dependent sources, then auxiliary equations can be written to express the quantities on which the dependent sources depend in terms of the independent excitations and/or the unknown loop currents. Thus, dependent sources may modify the elements of the loop impedance matrix in value and sign, and they may modify the elements of the excitation column matrix [Vi ]. Nevertheless, we can obtain expressions similar to those obtained previously for VTH and Isc . Of course, we must exclude from this illustration dependent sources that depend on the voltage across ZL because they violate the assumption that ZL appears in only one loop equation and are beyond the scope of this discussion.

The π-T Conversion The π-T conversion is employed for the simplification of circuits, especially in power systems analysis. The “π” refers to a circuit having the topology shown in Fig. 23.44. In this figure, the left-most and rightmost loop currents have been chosen to coincide with the port currents for convenience of notation only. A circuit having the topology shown in Fig. 23.45 is referred to as a “T” or as a “Y.” We wish to determine equations for Z1, Z2, and Z3 in terms of ZA, ZB , and ZC so that the π can be replaced by a T I1 + V1

I1

ZA

−

FIGURE 23.44 A π network shown with loop currents.

© 2003 by CRC Press LLC

I2

ZC I3

+ ZB

I2 V2 −

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Frequency Domain Methods

I1

Z1

+

I1

V1

Z2

Z3

I2

I2

+ V2

−

−

FIGURE 23.45 A T network.

without affecting any of the port variables. In other words, if an overall circuit contains a π subcircuit, we wish to replace the π subscript with a T subscript without disturbing any of the other voltages and currents within the overall circuit. To determine what Z1, Z2, and Z3 should be, we first write loop equations for the π network. The results are: V1 = I1 Z A − I 3 Z A

(23.41)

V2 = I 2 Z B + I 3 Z B

(23.42)

0 = I 3 ( Z A + Z B + ZC ) − I1 Z A + I 2 Z B

(23.43)

But the T circuit has only two loop equations given by: V1 = I1 ( Z1 + Z 3 ) + I 2 Z 3

(23.44)

V2 = I1 Z 3 + I 2 ( Z 2 + Z 3 )

(23.45)

We must eliminate one of the loop equations for the π circuit, and so we solve for I3 in (23.43) and substitute the result into (23.41) and (23.42) to obtain:  Z ( Z + ZC )    Z AZB V1 = I1  A B  + I2    Z A + Z B + ZC   Z A + Z B + ZC 

(23.46)

 Z B ( Z A + ZC )    Z AZB V2 = I1    + I2   Z A + Z B + ZC   Z A + Z B + ZC 

(23.47)

From a comparison of the coefficients of the currents in (23.46) and (23.47) with those in (23.44) and (23.45), we obtain the following relationships. Replacing  with T Z1 =

Z A ZC Z Z Z Z ; Z 2 = B C ; Z3 = A B SZ SZ SZ

(23.48)

where SZ = Z A + Z B + ZC We can also replace a T network by a π network. To do this we need equations for ZA, ZB , and ZC in terms of Z1, Z2, and Z3. The required equations can be obtained algebraically from (23.48).

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From T to  Z A = Z1 + Z 3 +

Z1 Z 3 Z Z ZZ ; Z B = Z 2 + Z 3 + 2 3 ; ZC = Z1 + Z 2 + 1 2 Z2 Z1 Z3

(23.49)

Reciprocity If an LLFT network contains only Rs, Ls, Cs, and transformers but contains no dependent sources, then its loop impedance matrix is symmetrical with respect to the main diagonal. That is, if zij is an element of the loop impedance matrix (see (23.17)), occupying the position at row i and column j, then zji = zij , where zji occupies the position at row j and column i. Such a network has the property of reciprocity and is termed a reciprocal network. Assume that a reciprocal network, depicted in Fig. 23.46, has m loops and is in the zero state. It has only one excitation — a voltage source in loop j. To solve for the loop current in loop k, we write the loop equations: z11  z 21  M  z  j1 z  k1 M   z m1

z12

L

z 22

L

M

O

z j2

L

zk2

L

M

O

z m2

L

z1m   z 2m   M   z jm   z km   M   z mm 

I 2  0      I 2  0      M  M      I  = V   j  j I  0   k   M  M          I 0   m

(23.50)

The column excitation matrix has only one nonzero entry. To determine Ik using Cramer’s rule, we replace column k by the excitation column and then expand along this column. Only one nonzero term is in the column, therefore, we obtain a single term for Ik : Ik = Vj

∆ jk

(23.51)

∆

where ∆jk is the cofactor, and ∆ is the determinant of the loop impedance matrix. Next, we replace the voltage source by a short circuit in loop j, cut the wire in loop k, and insert a voltage source Vk . Figure 23.47 outlines the modifications to the circuit. Then, we solve for Ij obtaining Reciprocal Network Vj

+ −

Ij

Ik

Initial Conditions are Zero

FIGURE 23.46 A reciprocal network with m independent loops.

Reciprocal Network Ij

Initial Conditions are Zero

Ik

FIGURE 23.47 Interchange of the ports of excitation in the network in Fig. 23.46. © 2003 by CRC Press LLC

+ − V k

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Frequency Domain Methods

j

k Reciprocal Network

Ij

+ Vk −

Initial Conditions are Zero

m (a)

+ Vj −

Reciprocal Network Initial Conditions are Zero

Ik

(b)

FIGURE 23.48 (a) Reciprocal ungrounded network with a current source excitation. (b) Interchange of the ports of excitation and response.

I j = Vk

∆ kj ∆

(23.52)

Because the network is reciprocal, ∆jk = ∆kj so that Ik I j = V j Vk

(23.53)

Eq. (23.53) is the statement of reciprocity for the network in Figs. 23.46 and 23.47 with the excitations shown. Figure 23.48(a) is a reciprocal network with a current excitation applied to node j and a voltage response, labeled Vk, taken between nodes k and m. We assume the network has n independent nodes plus the ground node indicated and is not a grounded network (does not have a common connection between the input and output ports shown). If we write node equations to solve for Vk in Fig. 23.48(a) and use Cramer’s rule, we have: Vk = I j

∆ ′jk − ∆ ′jm ∆′

(23.54)

where the primes indicate node-basis determinants. Then, we interchange the ports of excitation and response as depicted in Fig. 23.48(b). If we solve for Vj in Fig. 23.48(b), we obtain Vj = Ik

∆ ′kj − ∆ mj ′ ∆′

(23.55)

Because the corresponding determinants in (23.54) and (23.55) are equal because of reciprocity, we have: Vk V j = Ij Ik

(23.56)

Note that the excitations and responses are of the opposite type in Figs. 23.46 and 23.48. The results obtained in (23.53) and (23.56) do not apply if the excitation and response are both voltages or both currents because when the ports of excitation and response are interchanged, the impedance levels of the network are changed [2]. © 2003 by CRC Press LLC

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Ui

+ 1 V2 −

1′

Uo I2

LLFT

Network

N

FIGURE 23.49 An arbitrary LLFT network.

Middlebrook’s Extra Element Theorem Middlebrook’s extra element theorem is useful in developing tests for analog circuits and for predicting the effects that parasitic elements may have on a circuit. This theorem has two versions: the parallel version and the series version. Both versions present the results of connecting an extra network element in the circuit as the product of the network function obtained without the extra element times a correction factor. This is a particularly convenient form for the results because it shows exactly the effects of the extra element on the network function. Parallel Version. Consider an arbitrary LLFT network having a transfer function A1(s). In the parallel version of the theorem, an impedance is added between any two independent nodes of the network. The modified transfer function is then obtained as A1(s) multiplied by a correction factor. Figure 23.49 is an arbitrary network in which the quantities Ui and U0 represent a general input and a general output, respectively, whether they are voltages or currents. The extra element is to be connected between terminals 1 and 1′ in Fig. 23.49, and the port variables for this port are V2 and I2. We can write: U o = A1U i + A2 I 2

(23.57)

V2 = B1U i + B2 I 2 where A1 =

Uo Ui

V B1 = 2 Ui

A2 = I 2 =0

I2

Uo I 2 U =0 i

(23.58)

V B2 = 2 I 2 U =0 =0 i

Note that A1 is assumed to be known. The extra element Z to be added across terminals 1 and 1′ is depicted in Fig. 23.50. It can be described as Z = V2 /(–I2 ) which yields I2 = V2 /(–Z). Substituting this expression for I2 into (23.57) results in:

I2

1 +

Z

V2 − 1′

© 2003 by CRC Press LLC

FIGURE 23.50 The extra element Z.

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Frequency Domain Methods

Ui

I2

1 + V2 −

Uo LLFT Network N

FIGURE 23.51 Network of Fig. 23.49 with two excitations applied.

1′

 −V  U o = A1U i + A2  2   Z   B  V2 1 + 2  = B1U i  Z

(23.59)

After eliminating V2 and solving for Uo /Ui , we obtain:  1  A B − A2 B1   1 +  1 2  Z A1 Uo   = A1   B2 Ui 1+   Z  

(23.60)

Next, we provide physical interpretations for the terms in (23.60). Clearly, B2 is the impedance seen looking into the network between terminals 1 and 1′ with Ui = 0. Thus, rename B2 = Zd where d stands for “dead network.” To find a physical interpretation of (A1 B2 – A2 B1)/A1, examine the network in Fig. 23.51. Here, two excitations are applied to the network, namely Ui and I2. Simultaneously adjust both inputs so as to null output Uo. Thus, with Uo = 0, we have from (23.57), Ui =

−A2 I A1 2

(23.61)

Substituting this result into the equation for V2 in (23.57), we have:  −A  V2 = B1  2  I 2 + B2 I 2  A1 

(23.62)

or V2 I2 U

= o =0

A1B2 − A2 B1 A1

Because the quantity (A1B2 – A2 B1)/A1 is the ratio of V2 to I2 with the output nulled, we rename this quantity as ZN . Then rewriting (23.60) with Zd and ZN , we have: ZN  1 + Z Uo = A1  Z Ui 1+ d Z 

    

(23.63)

Equation (23.63) demonstrates that the results of connecting the extra element Z into the circuit can be expressed as the product of A1, which is the network function with Z set to infinity, times a correction factor given in the brackets in (23.63). © 2003 by CRC Press LLC

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C

1

Vi + −

−

R1

1′

N

R2

+ Vo −

+

FIGURE 23.52 Ideal op amp circuit for Example 15.

I2

I2

1

+

V2

−

1′

1 + I2

R2 R1

I=0

V2

+ −

+

Vi

Vo −

+ −

R1

(a)

1′

−

R2 I=0

+ −

+ Vo = 0 −

(b)

FIGURE 23.53 (a) Network for finding Zd . (b) Network used to determine ZN .

Example 15. Use the parallel version of Middlebrook’s extra element theorem to find the voltage transfer function of the ideal op amp circuit in Fig. 23.52 when a capacitor C is connected between terminals 1 and 1′. Solution. With the capacitor not connected, the voltage transfer function is V0 Vi

=− Z =∞

R2 = A1 R1

Next, we determine Zd from the circuit illustrated in Fig. 23.53(a), where a model has been included for the ideal op amp, the excitation Vi has been properly removed, and a current excitation I2 has been applied to the port formed by terminals 1 and 1′. Because no voltage flows across R1 in Fig. 23.53(a), no current flows through it, and all the current I2 flows through R2. Thus, V2 = I2 R2, and Zd = R2 . We next find ZN from Fig. 23.53(b). We observe in this figure that the right end of R2 is zero volts above ground because Vi and I2 have been adjusted so that V0 is zero. Furthermore, the left end of R2 is zero volts above ground because of the virtual ground of the op amp. Thus, zero is current flowing through R2, and so V2 is zero. Consequently, ZN = V2 /I2 = 0. Following the format of (23.63), we have: V0 R  1  =− 2 Vi R1  1 + sCR2  Note that for V0 to be zero in Fig. 23.53(b), Vi and I2 must be adjusted so that Vi /R1 = –I2, although this information was not needed to work the example. ▫ Series Version. The series version of the theorem allows us to cut a loop of the network, add an impedance Z in series, and obtain the modified network function as A1(s) multiplied by a correction factor. A1 is the network function when Z = 0. Figure 23.54 is an LLFT network with part of a loop illustrated explicitly. The quantities Ui and U0 represent a general input and a general output, respectively, whether they be a voltage or a current. Define © 2003 by CRC Press LLC

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Ui

Uo LLFT Network N +

V2

I2

−

FIGURE 23.54 LLFT network used for the series version of Middlebrook’s extra element theorem.

Z

A1 =

U0 U A = 0 U i V =0 2 V2 U =0 2

I B1 = 2 Ui

i

(23.64)

I B2 = 2 V 2 U =0 V =0 2

i

where V2 and I2 are depicted in Fig. 23.54, and A1 is assumed to be known. Then using superposition, we have: U 0 = A1U i + A2V2

(23.65)

I 2 = B1U i + B2V2

The impedance of the extra element Z can be described by Z = V2 /(–I2) so that V2 = –I2 Z. Substituting this relation for V2 into (23.65) and eliminating I2, we have:   A  1 + Z  B2 − B1 2  

A1   U0  = A1   Ui 1 + B2 Z    

(23.66)

Again, as we did for the parallel version of the theorem, we look for physical interpretations of the quantities in the square bracket in (23.66). From (23.65) we see that B2 is the admittance looking into the port formed by cutting the loop in Fig. 23.54 with Ui = 0. This is depicted in Fig. 23.55(a). Thus, B2 is the admittance looking into a dead network, and so let B2 = 1/Zd . To find a physical interpretation of the quantity (A1B2 – A2B1)/A1, we examine Fig. 23.55(b) in which both inputs, V2 and Ui , are adjusted to null the output U0. From (23.65) with Uo = 0, we have: Ui = −

A2 V A1 2 Ui

Ui = 0

B2

(23.67)

LLFT Network N (a)

I2

Uo = 0

1

LLFT Network N

1′

(b)

V2 + −

FIGURE 23.55 (a) Looking into the network with Ui equal zero. (b) Ui and V2 are simultaneously adjusted to null the output U0. © 2003 by CRC Press LLC

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Then, eliminating Ui in (23.65) we obtain: A1B2 − A2 B1 I 2 = A1 V2 U

(23.68) 0 =0

Because this quantity is the admittance looking into the port formed by terminals 1 and 1′ in Fig. 23.55(b) with Uo nulled, rename it as 1/Zn. Thus, from (23.66) we can write Z  1 + Z Uo N = A1  Ui 1+ Z  Zd

    

(23.69)

Eq. (23.69) is particularly convenient for determining the effects of adding an impedance Z into a loop of a network. Example 16. Use the series version of Middlebrook’s extra element theorem to determine the effects of inserting a capacitor C in the location indicated in Fig. 23.56.

Rs + −

+

βIb

C

Vi

Rb

Vo

RL

Ib Re

−

FIGURE 23.56 Network for Example 16.

Solution. The voltage transfer function for the network without the capacitor is found to be: A1 =

V0 Vi

= Z =0

−βRL  R Rs + (β + 1)Re 1 + s  R  b

Next, we find Zd from Fig. 23.57(a). This yields: Zd =

[

V = Rs + Rb (β +1)Re I

]

The impedance Zn is found from Fig. 23.57(b) where the two input sources, Vi and V, are adjusted so that V0 equals zero. If V0 equals zero, then βIb equals zero because no current flows through RL. Thus, Ib equals zero, which implies that VRe, the voltage across Re as indicated in Fig. 23.57(b), is also zero. We see that the null is propagating through the circuit. Continuing to analyze Fig. 23.57(b), we see that IRb is zero so that we conclude that I is zero. Because ZN = V/I, we conclude that ZN is infinite. Using the format given by (23.69) with Z = 1/(sC), we obtain the result as: 1  V0  1 (sC ) = A1  1 + Vi  Rs + Rb (β + 1)Re 

[

]

    

▫ It is interesting to note that to null the output so that ZN could be found in Example 16, Vi is set to V, although this fact is not needed in the analysis. © 2003 by CRC Press LLC

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+

βIb Rs

I

+−

V RL

Ib Re

Rb

Vo −

(a)

βIb

Rs + −

I

Vi

+−

RL

V Ib

IRb

Rb

+ Vo = 0 −

+ Re

VRe −

(b)

FIGURE 23.57 (a) Network used to obtain Zd . (b) Network that yields ZN .

i(t) A

+ v(t) −

B

+ v(t) −

A

(a)

(b)

i(t)

A

(c)

FIGURE 23.58 (a) An LLFT network consisting of two subnetworks A and B connected by two wires. (b) A voltage source can be substituted for subnetwork B if v(t) is known in (a). (c) A current source can be substituted for B if i is a known current.

Substitution Theorem Figure 23.58(a) is an LLFT network consisting of two subnetworks A and B, which are connected to each other by two wires. If the voltage v(t) is known, the voltages and currents in subnetwork A remain unchanged if a voltage source of value v(t) is substituted for subnetwork B as illustrated in Fig. 23.58(b). Example 17. Determine i1 (t) in the circuit in Fig. 23.59. The voltage v1(t) is known from a previous analysis. Solution. Because v1(t) is known, the substitution theorem can be applied to obtain the circuit in Fig. 23.60. Analysis of this simplified circuit yields: © 2003 by CRC Press LLC

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R1

R3

C

i1(t) iIN(t)

R4

+ v1(t) −

R2

+ −

vA(t)

FIGURE 23.59 Circuit for Example 17.

R1

R3 i1(t)

iIN(t)

R2

+ −

v1(t)

FIGURE 23.60 Circuit that results when the Substitution Theorem is applied to the circuit in Fig. 23.59.

i1 = iin

R3 1 + v1 R 2 + R3 R2 + R3

If the current i(t) is known in Fig. 23.58(a), then the substitution in Fig. 23.58(c) can be employed.

23.3 Sinusoidal Steady-State Analysis and Phasor Transforms Sinusoidal Steady-State Analysis In this section, we develop techniques for analyzing lumped, linear, finite, time invariant (LLFT) networks in the sinusoidal steady state. These techniques are important for analyzing and designing networks ranging from AC power generation systems to electronic filters. To put the development of sinusoidal steady state analysis in its context, we list the following definitions of responses of circuits: A. The zero-input response is the response of a circuit to its initial conditions when the input excitations are set to zero. B. The zero-state response is the response of a circuit to a given input excitation or set of input excitations when the initial conditions are all set to zero. The sum of the zero-input response and the zero-state response yields the total response of the system being analyzed. However, the total response can also be decomposed into the forced response and the natural response if the input excitations are DC, real exponentials, sinusoids, and/or sinusoids multiplied by real exponentials and if the exponent(s) in the input excitation differs from the exponents appearing in the zero-input response. These excitations are very common in engineering applications, and the decomposition of the response into forced and natural components corresponds to the particular and complementary (homogeneous) solutions, respectively, of the linear, constant coefficient, ordinary dif­ ferential equations that characterize LLFT networks in the time domain. Therefore, we define: C. The forced response is the portion of the total response that has the same exponents as the input excitations. D. The natural response is the portion of the total response that has the same exponents as the zeroinput response.

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The sum of the forced and natural responses is the total response of the system. For a strictly stable LLFT network, meaning that the poles of the system transfer function T(s) are confined to the open left-half s-plane (LHP), the natural response must decay to zero eventually. The forced response may or may not decay to zero depending on the excitation and the network to which it is applied, and so it is convenient to define the terms steady-state response and transient response: E. The transient response is the portion of the response that dies away or decays to zero with time. F. The steady-state response is the portion of the response that does not decay with time. The sum of the transient and steady state responses is the total response, but a specific circuit with a specific excitation may not have a transient response or it may not have a steady state response. The following example illustrates aspects of these six definitions. Example 18. Find the total response of the network shown in Fig. 23.61, and identify the zero-state, zeroinput, forced, natural, transient, and steady-state portions of the response. 1Ω + vi = V1e−t + V2 sin t

+ −

Vc

+

vo (t)

1/2F

−

−

FIGURE 23.61 Circuit for Example 18.

Solution. Note that a nonzero initial condition is represented by Vc. Using superposition and the simple voltage divider concept, we can write: V  2 V  s   V V0 (s ) =  1 + 2 2  + c  1 1 2 s + s + s s  s + 2 +   The partial fraction expansion for V0 (s) is: V0 (s ) =

A B Cs + D + + s +1 s + 2 s 2 +1

where A = 2V1 B = −2V1 + 0.4V2 + Vc C = −0.4V2 D = 0.8V2 Thus, for t ≥ 0, v0 (t) can be written as: v 0 (t ) = 2V1e −t − 2V1e −2t + 0.4V2e −2t + Vc e −2t − 0.4V2 cost + 0.8V2 sint With the aid of the angle sum and difference formula sin(α ± β) = sinαcosβ ± cos α sinβ © 2003 by CRC Press LLC

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√5 1 θ 2

FIGURE 23.62 Sketch for determining the phase angle θ.

and the sketch in Fig. 23.62, we can combine the last two terms in the expression for v0 (t) to obtain: v 0 (t ) = 2V1e −t − 2V1e −2t + 0.4V2e −2t + Vc e −2t + 0.4 5V2 sin(t + θ) where  1 θ = − tan −1    2 The terms of v0(t) are characterized by our definitions as follows: zero-input response = Vc e −2t zero-state response = 2V1e −t − 2V1e −2t + 0.4V2e −2t + 0.4 5V2 sin(t + θ)

[

]

natural response = −2V1 + 0.4V2 + Vc e −2t forced response = 2V1e −t + 0.4 5V2 sin(t + θ)

[

]

transient response = 2V1e −t + −2V1 + 0.4V2 + Vc e −2t steady-state response = 0.4 5V2 sin(t + θ) As can be observed by comparing the preceding terms above with the total response, part of the forced response is the steady state response, and the rest of the forced response is included in the transient response in this example. ▫ If the generator voltage in the previous example had been vi = V1 + V2 sin(t), then there would have been two terms in the steady state response — a DC term and a sinusoidal term. On the other hand, if the transfer function from input to output had a pole at the origin and the excitation were purely sinusoidal, there would also have been a DC term and a sinusoidal term in the steady state response. The DC term would have arisen from the pole at the origin in the transfer function, and therefore would also be classed as a term in the natural response. Oftentimes, it is desirable to obtain only the sinusoidal steady state response, without having to solve for other portions of the total response. The ability to solve for just the sinusoidal steady state response is the goal of sinusoidal steady state analysis. The sinusoidal steady state response can be obtained based on analysis of the network using Laplace transforms. Figure 23.63 illustrates an LLFT network that is excited by the voltage sine wave vi(t) = V sin(ωt), where V is the peak amplitude of the sine wave and ω is the frequency of the sine wave in radians/second. Assume that the poles of the network transfer function V0 (s)/Vi (s) = T(s) are confined to the open left-half s-plane (LHP) except possibly for a single pole at the origin. Then, the forced response of the network is © 2003 by CRC Press LLC

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+ T (s)

+ −

vi(t) = V sin ωt

vo(t) LLFT −

FIGURE 23.63 LLFT network with transfer function T (s).

v oss (t ) = V T ( jω ) sin(ωt + θ)

(23.70)

where the extra subscripts “ss” on v0(t) indicate sinusoidal steady state, and where  T ( jω )  θ = tan −1    T ( jω ) 

(23.71)

The symbols  and  are read as “imaginary part of ” and “real part of,” respectively. In other words, the LLFT network modifies the sinusoidal input signal in only two ways at steady state. The network multiplies the amplitude of the signal by T(jω) and shifts the phase by θ. If the transfer function of the network is known beforehand, then the sinusoidal steady state portion of the total response can be easily obtained by means of Eqs. (23.70) and (23.71). To prove (23.70) and (23.71), we assume that T(s) = V0(s)/Vi (s) in Fig. 23.63 is real for s real and that the poles of T(s) are confined to the open LHP except possibly for a single pole at the origin. Without loss of generality, assume the order of the numerator of T(s) is at most one greater than the order of the denominator. Then the transform of the output voltage is V0 (s ) = Vi (s )T (s ) =

Vω T (s ) s2 + ω2

If V0(s) is expanded into partial fractions, we have: V0 (s ) =

A B + + other terms due to the poles of T (s ) s − jω s + jω

The residue A is

[

]

A = (s − jω )Vo (s ) =

s = jω

  Vω = T (s )  s = jω  s + jω

V T ( jω ) 2j

But T ( jω ) = T ( jω ) e jθ where θ = tan −1 Thus, we can write the residue A as A=

© 2003 by CRC Press LLC

V T ( jω ) e jθ 2j

T ( jω ) T ( jω )

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Also, B = A* where “*” denotes “conjugate,” and so B=− =−

(

V V T (− jω ) = − T ( jω ) * 2j 2j

)

V V T * ( jω ) = − T ( jω ) e − jθ 2j 2j

In the equation for the residue B, we can write T((jω)*) = T*(jω) because of the assumption that T(s) is real for s real (see Property 1 in Section 23.1 on “Properties of LLFT Network Functions”). All other terms in the partial fraction of V0(s) will yield, when inverse transformed, functions of time that decay to zero except for a term arising from a pole at the origin of T(s). A pole at the origin yields, when its partial fraction is inverse transformed, a DC term that is part of the steady-state solution in the time domain. However, only the first two terms in V0(s) will ultimately yield a sinusoidal function. We can rewrite these two terms as: Voss (s ) =

 e jθ V e − jθ  T ( jω )  −  2j  s − jω s + jω 

The extra subscripts “ss” denote sinusoidal steady state. The time-domain equation for the sinusoidal steady state output voltage is v oss (t ) =

[

V T ( jω ) e j θe jωt − e − jθe − jωt 2j

]

= V T ( jω ) sin(ωt + θ) where θ is given by (23.71). This completes the proof. Example 19. Verify the expression for the sinusoidal steady-state response found in the previous example. Solution. The transfer function for the network in Fig. 23.61 is T(s) = 2/(s + 2), and the frequency of the sinusoidal portion of vi (t) is ω = 1 rad/s. Thus, T ( jω ) =

2 = j+2

2 e jθ 4 +1

where  −2   1 θ = tan −1   = − tan −1    4  2 If the excitation in Fig. 23.63 were vi (t) = V sin (ωt + Φ), then the sinusoidal steady-state response of the network would be: v oss (t ) = V T ( jω ) sin(ωt + Φ + θ)

(23.72)

where θ is given by (23.71). Similarly, if the excitation were vi(t) = V [cos(ωt + Φ)], then the sinusoidal steady-state response would be expressed as: v oss (t ) = V T ( jω ) cos(ωt + Φ + θ) with θ again given by (23.71). © 2003 by CRC Press LLC

(23.73)

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Phasor Transforms In the sinusoidal steady-state analysis of stable LLFT networks, we find that both the inputs and outputs are sine waves of the same frequency. The network only modifies the amplitudes and the phases of the sinusoidal input signals; it does not change their nature. Thus, we need only keep track of the amplitudes and phases, and we do this by using phasor transforms. Phasor transforms are closely linked to Euler’s identity: e ± jωt = cos(ωt ) ± j sin(ωt )

(23.74)

If, for example, vi (t) = V sin(ωt + Φ), then we can write vi(t) as

[

] [

]

(23.75)

] [

]

(23.76)

v i (t ) =  Ve j (ωt +Φ ) =  Ve jΦe jωt Similarly, if vi (t) = V cos(ωt + Φ), then we can write

[

v i (t ) =  Ve j (ωt +Φ ) =  Ve j Φe jωt

If we confine our analysis to single-frequency sine waves, then we can drop the imaginary sign and the term e jωt in (23.75) to obtain the phasor transform. That is,

[ ] [

] {[

℘ v i (t ) =℘ V sin(ωt + Φ) =℘  Ve jΦe jωt

]} = Ve

jΦ

(23.77)

The first and last terms in (23.77) are read as “the phasor transform of vi(t) equals Ve jΦ”. Note that vi(t) is not equal to Ve jΦ as can be seen from the fact that vi(t) is a function of time while Ve jΦ is not. Phasor transforms will be denoted with bold letters that are underlined as in ℘[vi(t)] = V i . If our analysis is confined to single-frequency cosine waves, we perform the phasor transform in the following manner:

[

] { [

℘ V cos(ωt + Φ) =℘  Ve jΦe jωt

]} = Ve

jΦ

=V

(23.78)

In other words, to perform the phasor transform of a cosine function, we drop both the real sign and the term e jωt. Both sines and cosines are sinusoidal functions, but when we transform them, they lose their identities. Thus, before starting an analysis, we must decide whether to perform the analysis all in sines or all in cosines. The two functions must not be mixed when using phasor transforms. Furthermore, we cannot simultaneously employ the phasor transforms of sinusoids at two different frequencies. However, if a linear network has two excitations which have different frequencies, we can use superpo­ sition in an analysis for a voltage or current, and add the solutions in the time domain. Three equivalent representations are used for a phasor V : Ve jΦ   V = V (cosΦ + j sin Φ)  V∠Φ

exponential form rectangular form

(23.79)

polar form

If phasors are to be multiplied or divided by a complex number, the exponential or polar forms are the most convenient. If phasors are to be added or subtracted, the rectangular form is the most convenient. The relationships among the equivalent representations are illustrated in Fig. 23.64. In this figure, the phasor V is denoted by a point in the complex plane. The magnitude of the phasor, V  = V, is illustrated © 2003 by CRC Press LLC

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Imag. V − |V −|

Vsin Φ Φ

Real

Vcos Φ

FIGURE 23.64 Relationships among phasor representations.

by the length of the line drawn from the origin to the point. The phase of the phasor, Φ, is shown measured counterclockwise from the horizontal axis. The real part of V is V cos Φ and the imaginary part of V is V sin Φ. Phasors can be developed in a way that parallels, to some extent, the usual development of Laplace transforms. In the following theorems, we assume that the constants V1, V2,Φ1, and Φ2 are real. Theorem 1: For sinusoids of the same type (either sines or cosines) and of the same frequency ω,℘[V1sin(ωt + Φ1) + V2sin(ωt + Φ2)] = V1℘[sin(ωt + Φ1)] + V2℘[sin(ωt + Φ2)]. A similar relation can be written for cosines. This theorem demonstrates that the phasor transform is a linear transform. Theorem 2: If ℘[V1sin(ωt + Φ)] = V1e jΦ, then d  ℘ V1 sin(ωt + Φ) = jωV1e jΦ dt  

(23.80)

To prove Theorem 2, we can write:   d d   ℘ V1  e jΦe jωt  =℘V1  e j Φ e jωt     dt  dt  

(

)

[

]

=℘ V1 e jΦ jωe jωt = V1 jωe jΦ Note the interchange of the derivative and the imaginary sign in the proof of the theorem. Also, Theorem 2 can be generalized to:   dn n ℘ n V1 sin(ωt + Φ) = ( jω ) V1e jΦ   dt

(23.81)

These results are useful for finding the sinusoidal steady state solutions of linear, constant-coefficient, ordinary differential equations assuming the roots of the characteristic polynomials lie in the open LHP with possibly one at the origin. Theorem 3: If ℘[V1sin(ωt + Φ)] = V1e jΦ, then

[∫

]

℘ V1 sin(ωt + Φ) dt = The proof of Theorem 3 is easily obtained by writing: © 2003 by CRC Press LLC

1 V e jΦ jω 1

(23.82)

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] [∫ [ =℘[∫ V e

[∫

] ]

℘ V1 sin(ωt + Φ) dt =℘  V1e j (ωt +Φ ) dt 1

j ( ωt +Φ )

]

dt =

V1 jΦ e jω

It should be noted that no constant of integration is employed because a constant is not a sinusoidal function and is therefore not permitted when using phasors. A constant of integration arises in LLFT network analysis because of initial conditions, and we are interested only in the sinusoidal steady-state response and not in a zero-input response. No limits are used with the integral either, because the (constant) lower limit would also yield a constant, which would imply that we are not at sinusoidal steady state. Theorem 3 is easily extended to the case of n integrals:

[∫

]

℘ ... V1 sin(ωt + Φ)(dt ) =

∫

n

V1

( jω)n

e jΦ

(23.83)

This result is useful for finding the sinusoidal steady-state solution of integro-differential equations.

Inverse Phasor Transforms To obtain time domain results, we must be able to inverse transform phasors. The inverse transform operation is denoted by ℘ –1. This is an easy operation that consists of restoring the term e jωt, restoring the imaginary sign (the real sign if cosines are used), and dropping the inverse transform sign. That is,

[

] [

℘−1 V1e jΦ =  V1e jΦe jωt

]

= V1 sin(ωt + Φ)

(23.84)

The following example illustrates both the use of Theorem 2 and the inverse transform procedure. Example 23. Determine the sinusoidal steady-state solution for the differential equation: d 2 f (t ) df (t ) +4 + 3 f (t ) = V sin(ωt + Φ) dt 2 dt Solution. We note that the characteristic polynomial, D2 + 4D + 3, has all its roots in the open LHP. The next step is to phasor transform each term of the equation to obtain: −ω 2 F + 4 jωF + 3F = Ve jΦ where F (jω) = ℘[f(t)]. Therefore, when we solve for F, we obtain F=

Ve jΦ 3 − ω 2 + j4ω

(

=

)

Ve j Φe jθ

(3 − ω ) 2

2

+16ω 2

where θ = tan −1

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4ω −4ω = tan −1 2 3 − ω2 ω −3

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Thus, F=

V ω + 10ω + 9 4

2

e j ( φ +θ )

To obtain a time-domain function, we inverse transform F to obtain:

[

]

℘−1 F ( jω ) = f (t ) =

V ω +10ω 2 + 9 4

sin(ωt + Φ + θ)

In this example, we see that the sinusoidal steady-state solution consists of the sinusoidal forcing term, V sin(ωt + Φ), modified in amplitude and shifted in phase.

Phasors and Networks Phasors are time-independent representations of sinusoids. Thus, we can define impedances in the phasor transform domain and obtain Ohm’s law-like expressions relating currents through network elements with the voltages across those elements. In addition, the impedance concept allows us to combine dissimilar elements, such as resistors with inductors, in the transform domain. The time-domain expressions relating the voltages and currents for Rs, Ls, and Cs, repeated here for convenience, are: v R (t ) = iR (t )R

v L (t ) =

LdiL dt

v c (t ) =

1 i dt C C

∫

Note that initial conditions are set to zero. Then, performing the phasor transform of the time-domain variables, we have ZR = R

Z L = jωL

ZC =

1 jωC

We can also write the admittances of these elements as YR = 1/ZR, YL = 1/ZL, and YC = 1/ZC. Then, we can extend the impedance and admittance concepts for two-terminal elements to multiport networks in the same manner as was done in the development of Laplace transform techniques for network analysis. For example, the transfer function of the circuit shown in Fig. 23.65 can be written as: V0 ( jω ) Vi ( jω )

= G21 ( jω )

where the “jω” indicates that the analysis is being performed at sinusoidal steady state [1]. It is also assumed that no other excitations exist in N in Fig. 23.65. With impedances and transfer functions defined, then all the theorems developed for Laplace transform analysis, including source transforma­ tions, have a phasor transform counterpart. 1

vi(t) = V sin ωt

2

vo (t) LLFT 1′

FIGURE 23.65 An LLFT network excited by a sinusoidal voltage source. © 2003 by CRC Press LLC

+

N

+ −

2′

−

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Frequency Domain Methods

Example 21. Use phasor analysis to find the transfer function G21 (jω) and voss (t) for the circuit in Fig. 23.66. R1

vi(t) = V cos ωt

+ −

+

R2

C

vo (t) L

−

FIGURE 23.66 Circuit for Example 21.

Solution. The phasor transform of the output voltage can be obtained easily by means of the simple voltage divider. Thus, Vo = Vi

jωL + R2

R1 jωL + R2 + 1 + jωCR1

To obtain G21(jω), we form V 0 /V i , which yields V0 Vi

= G21 ( jω ) =

(R2 + jωL)(1 + jωCR1 )

(R2 + jωL)(1 + jωCR1 ) + R1

Expressing the numerator and denominator of G21 in exponential form produces:

G21 =

(R

2

)

− ω 2 LCR1 + (ωL + ωCR1R2 ) e jα

(R + R 1

2

2

)

− ω 2 LCR1 + (ωL + ωCR1R2 ) e jβ

2

2

2

where α = tan −1 β = tan −1

(ωL + ωCR1R 2 ) R2 − ω 2 LCR1

(ωL + ωCR1R2 )

R1 + R2 − ω 2 LCR1

Thus, G21 ( jω ) = Me jθ where

M=

(R

2

(R + R 1

)

− ω 2 LCR1 + (ωL + ωCR1R2 ) 2

2

)

− ω 2 LCR1 + (ωL + ωCR1R2 ) 2

and θ = α −β © 2003 by CRC Press LLC

2 2



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The phasor transform of vi (t) is

[

]

Vi =℘ V e jωt = Ve j0 = V and, therefore, the time-domain expression for the sinusoidal steady-state output voltage is: v oss (t ) = VM cos(ωt + θ)

▫

Driving point impedances and admittances as well as transfer functions are not phasors because they do not represent sinusoidal waveforms. However, an impedance or transfer function is a complex number at a particular real frequency, and the product of a complex number times a phasor is a new phasor. The product of two arbitrary phasors is not ordinarily defined because sin2 (ωt) or cos2 (ωt) are not sinusoidal and have no phasor transforms. However, as we will see later, power relations for AC circuits can be expressed in efficient ways as functions of products of phasors. Because such products have physical interpretations, we permit them in the context of power calculations. Division of one phasor by another is permitted only if the two phasors are related by a driving point or transfer network function such as V 0/V i = G21(jω).

Phase Lead and Phase Lag The terms “phase lead” and “phase lag” are used to describe the phase shift between two or more sinusoids of the same frequency. This phase shift can be expressed as an angle in degrees or radians, or it can be expressed in time as seconds. For example, suppose we have three sinusoids given by: v1 (t ) = V1 sin(ωt )

v 2 (t ) = V2 sin(ωt + Φ)

v 3 = V3 sin(ωt − Φ)

where V1 , V2 , V3 , and Φ are all positive. Then, we say that v2 leads v1 and that v3 lags v1. To see this more clearly, we rewrite v2 and v3 as:

[

]

[

v 2 = V2 sin ω(t + t 0 )

]

v 3 = V3 sin ω(t − t 0 )

where the constant t0 = Φ/ω. Figure 23.67 plots the three sinusoids sketched on the same axis, and from this graph we see that the zero crossings of v2(t) occur t0 seconds before the zero crossing of v1(t). Thus, v2(t) leads v1(t) by t0 seconds. Similarly, we see that the zero crossings of v3(t) occur t0 seconds after the zero crossings of v1(t). Thus, v3(t) lags v1(t). We can also say that v3(t) lags v2(t). When comparing the phases of sine waves with V sin(ωt), the key thing to look for in the arguments of the sines are the signs of the angles following ωt. A positive sign means lead and a negative sign means lag. If two sines or two cosines have the same phase angle, then they are called “in phase.” If we have i1(t) = I1 [cos(ωt – π/4)] and i2(t) = I2 [cos(ωt – π/3)], then i2 lags i1 by π/12 rad or 15° because even though the phases of both cosines are negative, the phase of i1(t) is less negative than the phase of i2(t). We can also say that i1 leads i2 by 15°. volts v1

v2

v3 π + to) (ω

−to

to

π − to) (ω

FIGURE 23.67 Three sinusoids sketched on a time axis. © 2003 by CRC Press LLC

π ω

2π ω

t seconds

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Frequency Domain Methods

Example 22. Suppose we have five signals with equal peak amplitudes and equal frequencies but with differing phases. The signals are: i1 = I [sin (ωt)], i2 = I [cos(ωt)], i3 = I [cos(ωt + θ)], i4 = –I [sin(ωt + ψ)], and i5 = –I [cos(ωt – Φ)]. Assume I, θ, ψ, and Φ are positive. A. How much do the signals i2 through i5 lead i1? B. How much do the signals i1 and i3 through i5 lead i2? Solution. For part (A), we express i2 through i5 as sines with lead angles. That is, π  i2 = I cos(ωt ) = I sin ωt +   2 π  i3 = I cos(ωt + θ) = I sin ωt + θ +   2 i4 = −I sin(ωt + ψ ) = I sin(ωt + ψ ± π) i5 = −I cos(ωt − Φ) = I cos(ωt − Φ ± π) π  = I sin ωt − Φ ± π +   2 Thus, i2 leads i1 by π/2 rad, and i3 leads i1 by θ + π/2. For i4, we can take the plus sign in the argument of the sign to obtain ψ + π, or we can take the minus sign to obtain ψ – π. The current i5 leads i1 by (3π/2 – Φ) or by (–π/2 – Φ). An angle of ± 2π can be added to the argument without affecting lead or lag relationships. For part (B), we express i1 and i3 through i5 as cosines with lead angles yielding: π  i1 = I sin(ωt ) = I cos ωt −   2 i3 = I cos(ωt + θ) i4 = −I sin(ωt + ψ ) = I sin(ωt + ψ ± π) π  = I cos ωt + ψ ± π −   2 i5 = −I cos(ωt − Φ) = I cos(ωt − Φ ± π) We conclude that i1 leads i2 by (–π/2) rad. (We could also say that i1 lags i2 by (π/2) rad.) Also, i3 leads i2 by θ. The current i4 leads i2 by (ψ + π/2) where we have chosen the plus sign in the argument of the ▫ cosine. Finally, i5 leads i2 by (π – Φ), where we have chosen the plus sign in the argument. In the previous example, we have made use of the identities: π  cos(α ) = sin α +  ;  2 −cos(α ) = cos(α ± π);

− sin(α ) = sin(α ± π) π  sin(α ) = cos α −   2

The concepts of phase lead and phase lag are clearly illustrated by means of phasor diagrams, which are described in the next section. © 2003 by CRC Press LLC

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Phasor Diagrams Phasors are complex numbers that represent sinusoids, so phasors can be depicted graphically on a complex plane. Such graphical illustrations are called phasor diagrams. Phasor diagrams are valuable because they present a clear picture of the relationships among the currents and voltages in a network. Furthermore, addition and subtraction of phasors can be performed graphically on a phasor diagram. The construction of phasor diagrams is demonstrated in the next example. Example 23. For the network in Fig. 23.68(a), find I 1, V R1, and V C. For Fig. 23.68(b), find I 2, V R2 , and V L. Construct phasor diagrams that illustrate the relations of the currents to the voltage excitation and the other voltages of the networks. Solution. For Fig. 23.68(a), we have

[ ]

℘ v (t ) = V∠0o

[ ]

℘ i1 (t ) = I 1 =

and

V R1 +

1 jωC

Rewriting I 1, we have: I1 =

VjωC VjωC 1 − jωCR1  =   1 + jωCR1 1 + jωCR1 1 − jωCR1 

 ω 2C 2 R + jωC  VωC e jθ1 = V  2 21 2 = 2 2 2 C R +1 ω ω C R1 + 1 1   where θ1 = tan −1

1 ωC = tan −1 ω 2C 2 R1 ωCR1

Note that we have multiplied the numerator and denominator of I 1 by the conjugate of the denominator. The resulting denominator of I 1 is purely real, and so we need only consider the terms in the numerator of I 1 to obtain an expression for the phase. Thus, the resulting expression for the phase contains only one term which has the form: θ1 = tan −1

i1(t)

+ − vR1

i2(t) +

R1 + −

(numerator) (numerator)

v= Vsinωt

C

vC

+ − vR2 R2

+ −

v= Vsinωt

L

vL −

− (a)

FIGURE 23.68 (a) An RC network. (b) An RL network.

© 2003 by CRC Press LLC

+

(b)

0912 S1-S8 Frame55.book Page 737 Saturday, October 5, 2002 10:06 PM

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Frequency Domain Methods

We could have obtained the same results without application of this artifice. In this case, we would have obtained θ1 =

π − tan −1 ωCR1 2

For ωCR1 ≥ 0, it is easy to show that the two expressions for θ1 are equivalent. Because the same current flows through both network elements, we have VR1 =

VωCR1 ω 2C 2 R12 + 1

e jθ1

and  1  − jV V Vc = I1  e jθ1 = e jψ = 2 2 2 2  jωC  ω C R1 +1 ω C 2 R12 +1 where ψ=−

π + θ = − tan −1 ωCR1 2 1

For I 2 in Fig. 23.68(b), we obtain I2 =

V∠0o = R2 + jωL

V R22 + w 2 L2

e jθ2

where θ2 is given by θ 2 = − tan −1

ωL R2

The phasor current I 2 flows through both R2 and L. So we have: VR2 = I 2 R2 and VL = jωL I 2 =

VωL ω 2 L2 + R22

e jΦ

where Φ=

π + θ2 2

To construct the phasor diagram in Fig. 23.69(a) for the RC network in Fig. 23.68(a), we first draw a vector corresponding to the phasor transform V = V∠0° of the excitation. Because the phase of this phasor is zero, it is represented as a vector along the positive real axis. The length of this vector is  V . Then we construct the vector representing I 1 =  I 1  e jθ1. Again, the length of the vector is  I 1 , and it is

© 2003 by CRC Press LLC

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738

The Circuits and Filters Handbook, Second Edition

� ��

�����

�����

��

�� �

θ�

� θ�

����

��

����

�� ���

���

���

FIGURE 23.69 (a) Phasor diagram for the voltages and currents in Fig. 23.68(a). (b) Phasor diagram for Fig. 23.68(b).

drawn at the angle θ1. The vector representing V R1 lies along I 1 because the voltage across a resistor is always in phase or 180° out of phase with the current flowing through the resistor. The vector representing the current leads V C by exactly 90°. It should be noted from the phasor diagram that V R1 and V C add ▫ to produce V as required by Kirchhoff ’s law. Figure 23.69(b) presents the phasor diagram for the RL network in Fig. 23.68(b). For this network, I 2 lags V L by exactly 90°. Also, the vector sum of the voltages V L and V R2 must be the excitation voltage V as indicated by the dotted lines in Fig. 23.69(b). If the excitation V sin(ωt) had been V sin(ωt + Φ) in Fig. 23.68 in the previous example, then the vectors in the phasor diagrams in Fig. 23.69 would have just been rotated around the origin by Φ. Thus, for example, I 1 in Fig. 23.69(a) would have an angle equal to θ1 + Φ. The lengths of the vectors and the relative phase shifts between the vectors would remain the same. If R1 in Fig. 23.68(a) is decreased, then from the expression for θ1 = tan–1 (1/(ωCR1)), we see that the phase of I 1 is increased. As R1 is reduced further, θ1 approaches 90°, and the circuit becomes more nearly like a pure capacitor. However, as long as I 1 leads V , we label the circuit as capacitive. As R2 in Fig. 23.68(b) is decreased, then θ2 in Fig. 23.69(b) decreases (becomes more negative) and approaches –90°. Nevertheless, as long as I 2 lags V , we refer to the circuit as inductive. If both inductors and capacitors are in a circuit, then it is possible for the circuit to appear capacitive at some frequencies and inductive at others. An example of such a circuit is provided in the next section.

Resonance Resonant networks come in two basic types: the parallel resonant network and the series resonant (sometimes called antiresonant) network. More complicated networks may contain a variety of both types of resonant circuits. To see what happens at resonance, we examine a parallel resonant network at sinusoidal steady state [1]. Figure 23.70 is a network consisting of a capacitor and inductor connected in parallel, often called a tank circuit or tank, and an additional resistor R1 connected in parallel with the tank. The phasor transforms of the excitation and the currents through the elements in Fig. 23.70 are: V = V∠0o ; I R1 =

V V ; I = jωCV ; I L = R1 C jωL

(23.85)

i1(t)

v(t) = Vsin ωt

+ −

FIGURE 23.70 Parallel resonant circuit. © 2003 by CRC Press LLC

iR1

R1

iC C

iL L

0912 ch23(739) frame55 Page 739 Sunday, October 27, 2002 8:38 PM

739

Frequency Domain Methods

where V is the peak value of the excitation. The transform of the current supplied by the source is 1 1   I1 = I1 ∠ θ1 = I R1 + I C + I L = V  + jωC 1 − 2    ω LC    R1

(23.86)

The peak value of the current i1(t) at steady state is 2

2 1 1   I1 = V   + ω 2C 2 1 − 2   ω LC   R1 

(23.87)

It is not difficult to determine that the minimum value of I1 occurs at ω=

1 LC

(23.88)

which is the condition for resonance, and I1min is given by I1min =

V R1

(23.89)

This result is somewhat surprising since it means that at resonance, the source in Fig. 23.70 delivers no current to the tank at steady state. However, this result does not mean that the currents through the capacitor and inductor are zero. In fact, for ω2 = 1/(LC) we have: I C = jV

C C and I L = − jV L L

That is, the current through the inductor is 180° out of phase with the current through the capacitor, and, because their magnitudes are equal, their sum is zero. Thus, at steady state and at the frequency given by (23.88), the tank circuit looks like an open circuit to the voltage source. Yet, a circulating current occurs in the tank, labeled I T in Fig. 23.71, which can be quite large depending on the values of C and L. That is, at resonance, I T = jV

C = I C = − I L L

(23.90)

Therefore, energy is being transferred back and forth between the inductor and the capacitor. If the inductor and capacitor are ideal, the energy transferred would never decrease. In practice, parasitic resistances, especially in a physical inductor, would eventually dissipate this energy. Of course, parasitic resistances can be modeled as additional elements in the network.

�

�� = −

�

��

� + −

��

��

�

��

��

�

FIGURE 23.71 Circuit of Fig. 23.70 at resonance. No current is supplied to the tank by the source, but a circulating current occurs in the tank. © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 740 Saturday, October 5, 2002 10:06 PM

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The Circuits and Filters Handbook, Second Edition



�����

�����

ω < �

�����

ω = �

� ��

��

�

�

��

��

�

� ����

����

����

ω > �

�� ���

���

� ��

���

FIGURE 23.72 Phasor diagrams for the circuit in Fig. 23.70. (a) ω2 < 1/LC. (b) Diagram at resonance. (c) ω2 > 1/(LC).

�

+

�

�

� �

−

+

��

−

+

�� − +

�� −

FIGURE 23.73 Series resonant circuit.

Another interesting aspect of the network in Fig. 23.70 is that, at low frequencies (ω2 < 1/(LC)), I 1 lags V , and so the network appears inductive to the voltage source. At high frequencies (ω2 > 1/(LC)), I 1 leads V , and the network looks capacitive to the voltage source. At resonance, the network appears as only a resistor R1 to the source. Figure 23.72 depicts phasor diagrams of V and I 1 at low frequency, at resonance, and at high frequency. Figure 23.73 is the second basic type of resonant circuit — a series resonant circuit which is excited by a sinusoidal current source with phasor transform I = I ∠0°. This circuit is dual to the circuit in Fig. 23.70. The voltages across the network elements can be expressed as:  1  VR = IR; VC = − j   I; VL = jωLI  ωC 



(23.91)

Then, the voltage V is  1   V = I R + j  ωL −     ωC 

(23.92)

The peak value of V is 1   V = I R 2 +  ωL −   ωC 

2

(23.93)

where I is the peak value of I . The minimum value of V is Vmin = IR



(23.94)

and this occurs at the frequency ω = 1/ (LC), which is the same resonance condition as for the circuit in Fig. 23.70. Equation (23.94) demonstrates that at resonance, the voltage across the LC subcircuit in Fig. 23.73 is zero. However, the individual voltages across L and across C are not zero and can be quite large in magnitude depending on the values of the capacitor and inductor. These voltages are given by:

© 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 741 Saturday, October 5, 2002 10:06 PM

741

Frequency Domain Methods

L L and VL = jI C C

VC = − jI

(23.95)

and therefore the voltage across the capacitor is exactly 180° out of phase with the voltage across the inductor. At frequencies below resonance, V lags I in Fig. 23.73, and therefore the circuit looks capacitive to the source. Above resonance, V leads I, and the circuit looks inductive to the source. If the frequency of the source is ω = 1/ ( LC ) the circuit looks like a resistor of value R to the source.

Power in AC Circuits If a sinusoidal voltage v(t) = V sin(ωt + θV) is applied to an LLFT network that possibly contains other sinusoidal sources having the same frequency ω, then a sinusoidal current i(t) = I sin(ωt + θ1) flows at steady state as depicted in Fig. 23.74. The instantaneous power delivered to the circuit by the voltage source is p(t ) = v (t )i(t ) = VI sin(ωt + θ v ) sin(ωt + θ I )

(23.96)

where the units of p(t) are watts (W). With the aid of the trigonometric identity sinα sinβ =

[

]

1 cos(α − β) − cos(α + β) 2

we rewrite (23.96) as

[

]

1 p(t ) = VI cos(θ v − θ I ) − cos(2ωt + θ v + θ I ) 2

(23.97)

The instantaneous power delivered to the network in Fig. 23.74 has a component that is constant and another component that has a frequency twice that of the excitation. At different instances of time, p(t) can be positive or negative, meaning that the voltage source is delivering power to the network or receiving power from the network, respectively. In AC circuits, however, it is usually the average power P that is of more interest than the instantaneous power p(t) because average power generates the heat or performs the work. The average over a period of a periodic function f (t) with period T is

[ f (t )]

avg

=F =

1 T

∫

T

0

f (t )dt

(23.98)

i = Isin (ωt + θI)

v = Vsin (ωt + θv)

+ −

LLFT Network

FIGURE 23.74 LLFT network that may contain other sinusoidal sources at the same frequency as the external generator.

© 2003 by CRC Press LLC

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The period of p(t) in (23.97) is T = π/ω, and so

[ ] p(t )

avg

=P=

ω π

∫

π ω

0

1 p(t )dt = VI cos(θV − θ I ) 2

(23.99)

The cosine term in (23.99) plays an important role in power calculations and so is designated as the Power Factor (PF). Thus, Power Factor = PF = cos(θV − θ I )

(23.100)

If θV – θI = π/2, then PF = 0, and the average power delivered to the network in Fig. 23.74 is zero; but if PF = 1, then P delivered to the network by the source is VI/2. If 0 < θv – θI < π/2, then P is positive, and the source is delivering average power to the network. However, the network delivers average power to the source when P is negative, and this occurs if π/2 < θv – θI < 3π/2. If the current leads the voltage in Fig. 23.74, the convention is to consider PF as leading, and if current lags the voltage, the PF is regarded as lagging. However, it is not possible from PF alone to determine whether a current leads or lags voltage. Example 24. Determine the average power delivered to the network shown in Fig. 23.68(a). Solution. The phasor transform of the applied voltage is V = V 0°, and we determined in Example 23 that the current supplied was I1 =

VωCe jθ1 2

θ1 = tan −1

,

ω C R +1 2

2 1

1 ωCR1

The power factor is PF = cos(0 − θ1 ) = cos(θ1 ) which, with the aid of the triangle in Fig. 23.75, can be rewritten as PF =

ωCR1

(ωCR1 )

2

+1

Thus, the average power delivered to the circuit is

P=

1 2

   2 (ωCR1 ) +1  V 2ωC

 2 2 2 2  = V ω C R1 = I1 R1 2 2 2  2 (ωCR1 ) +1  2 ω C R1 +1 2 ωCR1

(

)

▫

We note that if R1 were zero in the previous example, then P = 0 because the circuit would be purely capacitive, and PF would be zero.

√ �ω �����+� �

θ� ω��� © 2003 by CRC Press LLC

FIGURE 23.75 Triangle for determining PF.

0912 S1-S8 Frame55.book Page 743 Saturday, October 5, 2002 10:06 PM

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Frequency Domain Methods

If no sources are in the network in Fig. 23.74, then the network terminal variables are related by: V = I Z ( jω )

(23.101)

where Z(jω) is the input impedance of the network. Because Z is, general and complex, we can write it as: Z ( jω ) = R(ω ) + jX (ω ) = Z e jθZ

(23.102)

where R(ω ) = Z ( jω );

X (ω ) = Z ( jω )

 X (ω )  and θ Z = tan −1    R(ω ) 

(23.103)

In (23.103), the (real) function X(ω) is termed the reactance. Employing the polar form of the phasors, we can rewrite (23.101) as V ∠ θV = I ∠ θ I Z ∠ θ Z = I Z ∠ (θ I + θ Z )

(23.104)

Equating magnitudes and angles, we obtain V = I Z and θV = θ I + θ Z

(23.105)

Thus, we can express P delivered to the network as 1 1 P = VI cos(θV − θ I ) = I 2 Z cosθ Z 2 2

(23.106)

But Z cos(θz) = R(ω) so that P=

1 2 I R(ω ) 2

(23.107)

Eq. (23.107) indicates that the real part of the impedance absorbs the power. The imaginary part of the impedance, X(ω), does not absorb average power. Example 24 in this section provides an illustration of (23.107). An expression for average power in terms of the input admittance Y(jω) = 1/Z(jω) can also be obtained. Again, if no sources are within the network, then the terminal variables in Fig. 23.74 are related by I = V Y ( jω )

(23.108)

Y ( jω ) = Y ( jω ) e jθY = G(ω ) + jB(ω )

(23.109)

The admittance Y(jω) can be written as

where G(ω) is conductance and B(ω) is susceptance, and where G(ω ) = Y ( jω );

B(ω) = Y ( jω )

 B(ω )  and θY = tan −1    G(ω )  © 2003 by CRC Press LLC

(23.110)

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Then, average power delivered to the network can be expressed as: 1 1 P = V 2 Y cosθY = V 2G(ω ) 2 2

(23.111)

If the network contains sinusoidal sources, then (23.99) should be employed to obtain P instead of (23.107) or (23.111). Consider a resistor R with a voltage v(t) = V sin(ωt) across it and therefore a current i(t) = I sin(ωt) = v(t)/R through it. The instantaneous power dissipated by the resistor is p(t ) = v (t )i(t ) =

v 2 (t ) 2 = i (t )R R

(23.112)

The average power dissipated in R is P=

1 T

T

∫ i (t ) Rdt = I 2

0

2 eff

R

(23.113)

where we have introduced the new constant Ieff . From (23.113), we can express Ieff as I eff =

1 T

T

∫ i (t )dt 2

(23.114)

0

This expression for Ieff can be read as “the square root of the mean (average) of the square of i(t)” or, more simply, as “the root mean square value of i(t),” or, even more succinctly, as “the RMS value of i(t).” Another designation for this constant is Irms. Equation (23.114) can be extended to any periodic voltage or current. The RMS value of a pure sine wave such as i(t) = I sin(ωt + θ1) or v(t) = V sin(ωt + θv ) is I rms =

I V or Vrms = 2 2

(23.115)

where I and V are the peak values of the sine waves. Normally, the voltages and currents listed on the nameplates of power equipment and household appliances are given in terms of RMS values instead of peak values. For example, a 120-V, 100-W lightbulb is expected to dissipate 100 W when a voltage 120( 2 )[sin(ωt)] is impressed across it. The peak value of this voltage is 170 V. If we employ RMS values, (23.99) can be rewritten as P = Vrms I rms PF

(23.116)

Eq. (23.116) emphasizes the fact that the concept of RMS values of voltages and currents was developed in order to simplify the calculation of average power. Because PF = cos(θv – θ1), we can rewrite (23.116) as

[

P = Vrms I rms cos(θV − θ I ) =  Vrmse jθV I rmse − jθI

[ ]

= V I

]

(23.117)

*

where I ∗ is the conjugate of I. If P =  [V I ∗], the question arises as to what the imaginary part of V I ∗ represents. This question leads naturally to the concept of complex power, denoted by the bold letter S, which has the units of volt-amperes (VA). If P represents real power, then we can write © 2003 by CRC Press LLC

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745

Frequency Domain Methods

� �θ�−θΙ�

�

�

FIGURE 23.76 Power triangle for a capacitive circuit.

S = P + jQ

(23.118)

where S =V I

∗

(23.119)

and where

[ ]

Q =  V I = Vrms I rms sin(θV − θ I ) *

(23.120)

Thus, Q represents imaginary or reactive power. The units of Q are VARs, which stands for volt-amperes reactive. Reactive power is not available for conversion into useful work. It is needed to establish and maintain the electric and magnetic fields associated with capacitors and inductors [4]. It is an overhead required for delivering P to loads, such as electric motors, that have a reactive part in their input impedances. The components of complex power can be represented on a power triangle. Figure 23.76 is a power triangle for a capacitive circuit. Real and imaginary power are added as shown to yield the complex power S. Note that (θv – θ1) and Q are both negative for capacitive circuits. The following example illustrates the construction of a power triangle for an RL circuit. Example 25. Determine the components of power delivered to the RL circuit in Fig. 23.77. Provide a phasor diagram for the current and the voltages, construct a power triangle for the circuit, and show how the power diagram is related to the impedances of the circuit. i

v = Vsin ωt

R

+ vR −

L

+ vL −

+ −

FIGURE 23.77 Network for Example 25.

Solution. We have V = Ve j0 and I =

Ve jθI R 2 + (ωL)

where θ I = − tan −1 © 2003 by CRC Press LLC

ωL R

2

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Because θv = 0, PF is PF = cos(θV − θ I ) =

R R + (ωL) 2

2

and is lagging. The voltages across R and L are given by: VR = IR =

V Re jθI R 2 + (ωL)

VL = jωL ˚I =

2

VωL R + (ωL) 2

2

e

(

j π2 + θ I

)

and Z is Z = R + jωL = R 2 + (ωL) e − jθI 2

The real and imaginary components of the complex power are simply calculated as: 2 P = I rms R(ω ) =

Q=

2 Vrms R

R 2 + (ωL)

2

2 Vrms ωL

R 2 + (ωL)

2

Figure 23.78 presents the phasor diagram for this circuit in which we have taken the reference phasor as I and therefore have shown V leading I by (θv – θ1). Also, we have moved V L parallel to itself to form a triangle. These operations cause the phasor diagram to be similar to the power triangle. Figure 23.79(a) shows a representation for the impedance in Fig. 23.77. If each side of the triangle in Fig. 23.79(a) is multiplied by Irms , then we obtain voltage triangle in Fig. 23.79(b). Next, we multiply the sides of the voltage triangle by Irms again to obtain the power triangle in Fig. 23.79(c). The horizontal side is the average power P, the vertical side is Q, and the hypotenuse has a length that represents the magnitude of the complex power S. All three triangles in Fig. 23.79 are similar. The angles between sides are preserved. ▫ If P remains constant in Fig. 23.76, but the magnitude of the angle becomes larger so that the magnitude of Q increases, then [S] increases. If the magnitude of the voltage is fixed, then the magnitude of the current supplied must increase. But then, either power would be lost in the form of heat in the wires supplying the load or larger diameter, more expensive wires, would be needed. For this reason, power companies that supply power to large manufacturing firms that have many large motors impose unfa­ vorable rates. However, the manufacturing firm can improve its rates if it improves its power factor. The following example illustrates how improving (correcting) PF is done. �� �

�θ�−θ��

�

© 2003 by CRC Press LLC

��

FIGURE 23.78 Phasor diagram for Example 25.

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Frequency Domain Methods

���

= √ ��+�ω���

ω� = ��

�θ�−θ�� � ���

�

� =� ����ω�

= ��

�

� ���ω�

=�

�θ�−θ��

�θ�−θ�� ���� �

� = �� �

� ��� ��

���� ��

�

= ��

� ��� �

=�

���

���

FIGURE 23.79 (a) Impedance triangle for circuit in Example 25. (b) Corresponding voltage triangle. (c) Power triangle.

Example 26. Determine the value of the capacitor to be connected in parallel with the RL circuit in Fig. 23.80 to improve the PF of the overall circuit to one. The excitation is a voltage source having an amplitude of 120 V RMS and frequency 2π(60 Hz) = 377 rad/s. What are the RMS values of the current supplied by the source at steady state before and after the capacitor is connected?

�

��� ��

�=

�

�

Ω

�

∠�° + −

� FIGURE 23.80 Circuit for Example 26.

Solution. The current through the RL branch in Fig. 23.80 is Ve jθ

I RL =

R 2 + (ωL)

2

; θ = − tan −1

ωL R

and the current through the capacitor is I C = jωCV = VωCe j ( π 2) Thus, the current supplied by the source to the RLC network is I = I RL + I C =

© 2003 by CRC Press LLC

�

V cosθ R 2 + (ωL)

2

 −ωL  + jV  2 2 + ωC  R + (ωL) 

������ �

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To improve the PF to one, the current I should be in phase with V. Thus, we set the imaginary term in the equation for I equal to zero, yielding: C=

L R 2 + (ωL)

2

= 530 µF

a rather large capacitor. Before this capacitor is connected, the RMS value of the current supplied by the voltage source is Irms = 26.833 amps. After the capacitor is connected, the source has to supply only 12 amps RMS, a considerable reduction. In both cases, P delivered to the load is the same. The following example also illustrates PF improvement. Example 27. A load with PF = 0.7 lagging, depicted in Fig. 23.81, consumes 12 kW of power. The line voltage supplied is 220 V RMS at 60 Hz. Find the size of the capacitor needed to correct the PF to 0.9 lagging, and determine the values of the currents supplied by the source both before and after the PF is corrected.

� � = �∠�°

� ����

��

+ −

����

�

FIGURE 23.81 Circuit for Example 27 showing the load and the capacitor to be connected in parallel with the load to improve the power factor.

Solution. We will take the phase of the line voltage to be 0°. From P = Vrms Irms PF = 12 kW, we obtain Irms = 77.922 amps. Because PF is 0.7 lagging, the phase of the current through the load relative to the phase of the line voltage is –cos–1(0.7) = –45.57o. Therefore, I load = 77.922(– 45.57°) amps RMS. When C is connected in parallel with the load, I = I C + I load = 220(377) jC + 77.922e − j0.7954 = 54.54 − j[55.64 − 82, 940C ] If the PF were to be corrected to unity, we would set the imaginary part of the previous expression for current to zero; but this would require a larger capacitor (671 µF), which may be uneconomical. Instead, to retain a lagging but improved PF = 0.9, and corresponding to the current lagging the voltage by 25.84°, we write 0.9 =

54.54 54.54 + (55.64 − 82, 940C ) 2

2

Therefore, C = 352 µF. The line current is now

(

)

I = I C + I load = 60.615∠ −25.87o amps RMS

▫

Previous examples have employed ideal voltage sources to supply power to networks. However, in many electronic applications, the source has a fixed impedance associated with it, and the problem is to

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Frequency Domain Methods

i

ZS + v = Vsin ωt −

Z

FIGURE 23.82 Zs is fixed, and Z is to be chosen so that maximum average power is transferred to Z.

obtain the maximum average power transferred to the load [2]. Here, we assume that the resistance and reactance of the load can be independently adjusted. Let the source impedance be: Z S ( jω ) = RS (ω ) + jX S (ω ) The load impedance is denoted as Z ( jω ) = R(ω ) + jX (ω ) Figure 23.82 depicts these impedances. We assume that all the elements, including the voltage source, within the box formed by the dotted lines are fixed. The voltage source is v(t) = V sin(ωt), and thus i(t) = I sin(ωt+θ), where V and I are peak values and  X (ω ) + X (ω )  θ = − tan −1  S   RS (ω ) + R(ω )  The average power delivered to Z is 2 P = I rms R(ω )

where Irms = I/ 2 and I=

V

[R (ω) + R(ω)] + [ X (ω) + X (ω)] 2

S

2

(23.121)

S

Thus, the average power delivered to Z can be written as P=

2 Vrms R(ω )

[R (ω) + R(ω)] + [ X (ω) + X (ω)] 2

S

2

(23.122)

S

To maximize P, we first note that the term [Xs(ω) + X(ω)]2 is always positive, and so this term always contributes to a larger denominator unless it is zero. Thus, we set X (ω ) = − X S (ω )

(23.123)

and (23.122) becomes P=

2 Vrms R(ω )

[R (ω) + R(ω)] S

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2

(23.124)

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Second, we set the partial derivative with respect to R(ω) of the expression in (23.124) to zero to obtain R + R) − 2R( RS + R) ∂P 2 ( S = Vrms =0 4 ∂R ( R + R)

(23.125)

R(ω ) = RS (ω )

(23.126)

2

S

Eq. (23.125) is satisfied for

and this value of R(ω) together with X(ω) = –Xs(ω), yields maximum average power transferred to Z. Thus, we should adjust Z to: Z ( jω ) = Z S* ( jω )

(23.127)

and we obtain Pmax =

2 Vrms 4R(ω )

(23.128)

Example 28. Find Z for the network in Fig. 23.83 so that maximum average power is transferred to Z. Determine the value of Pmax . R1

v = Vsin ωt

+ −

Z

C

FIGURE 23.83 Circuit for Example 28.

Solution. We first obtain the Thévenin equivalent of the circuit to the left of the dotted arc in Fig. 23.83 in order to reduce the circuit to the form of Fig. 23.82. VTH =

V 1 + jωR1C

ZTH =

R1 1 + jωR1C

Thus, * Z = ZTH =

R1 = 1 − jωR1C

R1 ωR1C 1+ j

1 j R1 jR1 ωC = = j + ωR1C R + j 1 1 ωC

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Frequency Domain Methods

R1 + v = Vsin ωt −

L= 1 ω2C

C

R1

LOAD

FIGURE 23.84 Circuit with load chosen to obtain maximum average power.

The term j(ωC) appears inductive (at a single frequency), and so we equate it to jωL to obtain: L=

1 ω 2C

The impedance Z is therefore formed by the parallel connection of a resistor R1 with the inductor L. Figure 23.84 depicts the resulting circuit. To determine Pmax , we note that the capacitor and inductor constitute a parallel circuit which is resonant at the frequency of excitation. It therefore appears as an open circuit to the source. Thus, Pmax is easily obtained as: 2 Pmax = I rms R1 =

where V is the peak value of v(t).

V2 8R1 ▫

Suppose Z is fixed and Zs is adjustable in Fig. 23.82. What should Zs be so that maximum average power is delivered to Z? This is a problem that is applicable in the design of electronic amplifiers. The average power delivered to Z is given by (23.122), and to maximize P, we set Xs(ω) = –X(ω) as before. We therefore obtain (23.124) again; but if Rs is adjustable instead of R, we see from (23.124) that Pmax is obtained when Rs equals zero.

Acknowledgments The author conveys his gratitude to Dr. Jacek Zurada, Mr. Tongfeng Qian, and to Dr. K. Wang for their help in proofreading this manuscript, and to Dr. Zbigniew J. Lata and Mr. Peichu (Peter) Sheng for producing the drawings.

References [1] A. Budak, Circuit Theory Fundamentals and Applications, 2nd ed., Englewood Cliffs, NJ: Prentice Hall, 1987. [2] L. P. Huelsman, Basic Circuit Theory with Digital Computations, Englewood Cliffs, NJ: Prentice Hall, 1972. [3] L. P. Huelsman, Basic Circuit Theory, 3rd ed., Englewood Cliffs, NJ: Prentice Hall, 1991. [4] S. Karni, Applied Circuit Analysis, New York: John Wiley & Sons, 1988. [5] L. Weinberg, Network Analysis and Synthesis, New York: McGraw-Hill, 1962.

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24 Symbolic Analysis

24.1 Introduction and Definition 24.2 Frequency-Domain Analysis 24.3 Traditional Methods (Single Expressions)

Benedykt S. Rodanski University of Technology, Sydney

Marwan M. Hassoun Iowa State University

Indefinite Admittance Matrix Approach • Two-Graph-Based Tableau Approach

24.4 Hierarchical Methods (Sequence of Expressions) 24.5 Approximate Symbolic Analysis 24.6 Time-Domain Analysis Fully Symbolic • Semi-Symbolic

24.1 Introduction and Definition Symbolic circuit analysis, simply stated, is a term that describes the process of studying the behavior of electrical circuits using symbols instead of, or in conjunction with, numerical values. As an example to illustrate the concept, consider the input resistance of the simple circuit in Fig. 24.1. Analyzing the circuit using the unique symbols for each resistor without assigning any numerical values to them yields the input resistance of the circuit in the form: Vin R1R2 + R1R3 + R1R4 + R2 R3 + R2 R4 = I in R2 + R3 + R4

(24.1)

Equation (24.1) is the symbolic expression for the input resistance of the circuit in Fig. 24.1. The formal definition of symbolic circuit analysis can be written as: Definition 1. Symbolic circuit analysis is the process of producing an expression that describes a certain behavioral aspect of the circuit with one, some, or all the circuit elements represented as symbols. The idea of symbolic circuit analysis is not new; engineers and scientists have been using the process to study circuits since the inception of the concept of circuits. Every engineer has used symbolic circuit analysis during his or her education process. Most engineers still use it in their everyday job functions. As an example, all electrical engineers have symbolically analyzed the circuit in Fig. 24.2. The equivalent resistance between nodes i and j is known to be: 1 1 1 = + Rij R1 R2 or Rij =

R1R2 R1 + R2

This is the most primitive form of symbolic circuit analysis.

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I in

R1

R3

+

Vin

R2

R4

FIGURE 24.1 Symbolic circuit analysis example.

i

R1

R2 j

FIGURE 24.2 Common symbolic analysis problem.

The basic justification for performing symbolic analysis rather than numerical analysis on a circuit can be illustrated by considering the circuit in Fig. 24.1 again. Assume that the values of all the resistances R1 through R4 are given as 1Ω and that the input resistance was analyzed numerically. The result obtained would be Vin 5 = ≈ 1.667 Ω I in 3

(24.2)

Now, consider the problem of increasing the input resistance of the circuit by adjusting only one of the resistor values. Equation (24.2) provides no insight into which resistor has the greatest impact on the input resistance. However, Eq. (24.1) clearly demonstrates that changing R2, R3, or R4 would have very little impact on the input resistance because the terms appear in both the numerator and the denominator of the symbolic expression. It can also be observed that R1 should be the resistor to change because it only appears in the numerator of the expression. Symbolic analysis has provided an insight into the problem. From a circuit design perspective, numerical results from the simulation of a circuit can be obtained by evaluating the results of the symbolic analysis at a specific numerical point for each symbol. Ideally, only one simulation run is needed in order to analyze the circuit, and successive evaluations of the results replaces the need for any extra iterations through the simulator. Other applications include sensitivity analysis, circuit stability analysis, device modeling and circuit optimization [5, 18, 32, 41]. Although the previous “hand calculations” and somewhat trivial examples are used to illustrate sym­ bolic circuit analysis, the thrust of the methods developed for symbolic analysis are aimed at computer implementations that are capable of symbolically analyzing circuits that cannot be analyzed “by hand.” Several such implementations have been developed over the years [4, 10, 12, 15, 17, 22, 25, 26, 28, 29, 31, 34, 35, 37, 38, 47, 48, 53, 54, 56–61, 66]. Symbolic circuit analysis, referred to simply as symbolic analysis for the rest of this section, in its current form is limited to linear,1 lumped, and time-invariant2 networks. The scope of the analysis is 1Some references are made to the ability to analyze "weakly nonlinear" circuits [18, 63]; however, the actual symbolic analysis is performed on a linearized model of the weakly nonlinear circuit. Other techniques are applicable to circuits with only a single strongly nonlinear variable [65]. 2One method is reported in Reference [36] that is briefly discussed in Section 24.6 that does deal with a limited class of time-variant networks.

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Symbolic Analysis

primarily concentrated in the frequency domain, both s-domain [10, 12, 15, 17, 22, 25, 28, 29, 34, 38, 43, 47, 48, 54, 56, 59–61, 66] and z-domain [4, 31, 35, 44]; however, the predominant development has been in the s-domain. Also, recent work has expanded symbolic analysis into the time domain [3, 24, 36]. The next few subsections will discuss the basic methods used in symbolic analysis for mainly s-domain frequency analysis. However, Section 24.6 highlights the currently known time-domain techniques.

24.2 Frequency-Domain Analysis Traditional symbolic circuit analysis is performed in the frequency domain where the results are in terms of the frequency variable s. The main goal of performing symbolic analysis on a circuit in the frequency domain is to obtain a symbolic transfer function of the form H (s , x ) =

N (s , x ) , x = x1 D(s, x )

[

]

K

x2

x p , p ≤ pall

(24.3)

The expression is a rational function of the complex frequency variable s, and the variables x1 through xp representing the variable circuit elements, where p is the number of variable circuit elements and pall is the total number of circuit elements. Both the numerator and the denominator of H(s,x) are polyno­ mials in s with real coefficients. Therefore, we can write m

H (s, x ) =

∑

m

ai ( x )s i

∏[s − z (x)] i

=

i=0 n

i=1 n

∑ b (x)s ∏[s − p (x)] i

i

i

i=0

i=1

Most symbolic methods to date concentrate on the first form of H(s,x) and several algorithms exist to obtain coefficients ai(x) and bi(x) in fully symbolic, partially symbolic (semi-symbolic), or numerical form. The zero/pole representation of H(s,x), although more useful in gaining insight into circuit behav­ ior, proved to be very difficult to obtain in symbolic form for anything but very simple circuits. For large circuits, various approximation techniques must be employed [9, 26]. A more recent approach to representing the above network function emerged in the 1980s and is based on a decomposed hierarchical form of Eq. (24.3) [22, 25, 51, 61, 62]. This hierarchical representation is referred to as a sequence of expressions representation to distinguish it from the single expression repre­ sentation of Eq. (24.3) and is addressed in Section 24.4. Several methodologies exist to perform symbolic analysis in the frequency domain. The early work was to produce a transfer function H(s) with the frequency variable s being the only symbolic variable. Computer programs with these capabilities include: CORNAP [54] and NASAP [47]. The interest in symbolic analysis today is in the more general case when some or all of the circuit elements are represented by symbolic variables. The methods developed for this type of analysis fall under one of the following categories: Traditional methods (single expression): 1. Tree enumeration methods • Single graph methods • Two graph methods 2. Signal flow graph methods 3. Parameter extraction methods • Modified nodal analysis-based methods • Tableau formulation-based methods 4. Interpolation method © 2003 by CRC Press LLC

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Hierarchical methods (sequence of expressions): 1. Signal flow graph methods 2. Modified nodal analysis-based methods The preceding classification includes the exact methods only. For large circuits, the traditional methods suffer from exponential growth of the number of terms in the formula with circuit size. If a certain degree of error is allowed, it may be possible to simplify the expression considerably, by including only the most significant terms. Several approximate symbolic methods have been investigated [26, 28, 69]. The next three sections discuss the basic theory for the above methods. Circuit examples are illustrated for all major methods except for the interpolation method due to its limited current usage3 and its inability to analyze fully symbolic circuits.

24.3 Traditional Methods (Single Expressions) This class of methods attempts to produce a single transfer function in the form of Eq. (24.3). The major advantage of having a symbolic expression in that form is the insight that can be gained by observing the terms in both the numerator and the denominator. The effects of the different terms can, perhaps, be determined by inspection. This process is valid for the cases where relatively few symbolic terms are in the expression. Before indulging in the explanation of the different methods covered by this class, some definition of terms is in order. Definition 2. RLCgm circuit is one that may contain only resistors, inductors, capacitors, and voltagecontrolled current sources with the gain (transconductance) designated as gm. Definition 3. Term cancellations is the process in which two equal symbolic terms cancel out each other in the symbolic expression. This can happen in one of two ways: by having two equal terms with opposite signs added together, or by having two equal terms (regardless of their signs) divided by each other. For example, the equation ab(ab + cd ) − ab(cd − ef ) ab(cd − gh)

(24.4)

where a, b, c, d, e, f, g, and h are symbolic terms, can be reduced by observing that the terms ab in the numerator and denominator cancel each other and the terms +cd and –cd cancel each other in the numerator. The result is: ab + ef cd − gh

(24.5)

Definition 4. Cancellation-free: Equation (24.4) is said to be a cancellation-free equation (that is, no possible cancellations exist in the expression) while Eq. (24.5) is not. Definition 5. Cancellation-free algorithm: The process of term cancellation can occur during the execu­ tion of an algorithm where a cancellation-free equation is generated directly instead of generating an

3

The main applications of the polynomial interpolation method in symbolic analysis are currently in numerical reference generation for symbolic approximation [14] and calculation of numerical coefficients in semi-symbolic analysis [50].

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Symbolic Analysis

expression with possible term cancellations in it. Cancellation-free algorithms are more desirable because, otherwise, an overhead is needed to generate and keep the terms that are to be canceled later. The different methods that fall under the traditional class are explained next. 1. The tree enumeration methods Several programs have been produced based on this method [6, 16, 42, 46]. Practical implementations of the method can only handle small circuits in the range of 15 nodes and 30 branches [7]. The main reason is the exponential growth in the number of symbolic terms generated. The method can only handle one type of controlled source, namely, voltage controlled current sources. So only RLCgm circuits can be analyzed. Also, the method does not produce any symbolic term cancellations for RLC circuits, and produces only a few for RLCgm circuits. The basic idea of the tree enumeration method is to construct an augmented circuit (a slightly modified version of the original circuit), its associated directed graph, and then enumerating all the directed trees of the graph. The admittance products of these trees are then used to find the node admittance matrix determinant and cofactors (the matrix itself is never constructed) to produce the required symbolic transfer functions. For a circuit with n nodes (with node n designated as the reference node) where the input is an excitation between nodes 1 and n and the output is taken between nodes 2 and n, the transfer functions of the circuit can be written as: V1 ∆11 = ∆ I1

(24.6)

Vo V2 ∆12 = = I in I1 ∆

(24.7)

Vo V2 ∆12 = = Vin V1 ∆11

(24.8)

Z in =

where ∆ is the determinant of the node admittance matrix Yn (dimension n-1 × n-1) and ∆ij is the ijth cofactor of Yn . It can be shown that a simple method for obtaining ∆, ∆11, and ∆12 is to construct another circuit comprised of the original circuit with an extra admittance yˆs in parallel with a voltage controlled current source, gˆmV2 , connected across the input terminals (nodes 1 and n). The determinant of Yˆ n (the node admittance matrix for the new, slightly modified, circuit) can be written as: ∆ˆ = ∆ + yˆ S ∆11 + gˆ m ∆12

(24.9)

This simple trick allows the construction of the determinant expression of the original circuit and its two needed cofactors by simply formulating the expression for the new augmented circuit. Example 24.1 below illustrates this process. The basic steps of the tree enumeration algorithm are (condensed from [7]): 1. Construct the augmented circuit from the original circuit by adding an admittance yˆs and a transconductance gˆ mV2 , in parallel between the input node and the reference node. 2. Construct a directed graph Gind associated with the augmented circuit. The stamps used to generate Gind are illustrated in Fig. 24.3. 3. Find all directed trees for Gind. A directed tree rooted at node i is a subgraph of Gind with node i having no incoming branches and each other node having exactly one incoming branch. 4. Find the admittance product for each directed tree. An admittance product of a directed tree is simply a term that is the product of all the weights of the branches in that tree. 5. Apply the following theorem:

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y

y i

j

i

j y

p + Vpq -q

i gmVpq

p

j

q

-gm gm

i gm

-gm

j

FIGURE 24.3 Element stamps for generating Gind.

Theorem 24.1 [7]: For any RLCgm circuit, the determinant of the node admittance matrix (with any node as the reference node) is equal to the sum of all directed tree admittance products of Gind (with any node as the root). In other words ∆ˆ =

∑ tree admittance products

(24.10)

Arranging Eq. (24.10) in the form of Eq. (24.9) results in the necessary determinant and cofactors of the original circuit and the required transfer functions are generated from Eqs. (24.6), (24.7), and (24.8). Example 1. A circuit and its augmented counterpart are illustrated in Fig. 24.4. The circuit is the smallsignal model of a simple inverting CMOS amplifier, shown with the coupling capacitance CC taken into account. Figure 24.5 depicts the directed graph associated with the augmented circuit constructed using the rules in Fig. 24.3. The figure also presents all the directed trees rooted at node 3 of the graph. Parallel branches heading in the same direction are combined into one branch with a weight equal to the sum of the weights of the individual parallel branches.

FIGURE 24.4 Circuit of Example 24.1 and its augmented equivalent diagram.

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sCc -gm

sCc -g m

gm +ys

gm +ys

2

go + gm go +g m

3

FIGURE 24.5 Graph and its directed trees of Example 24.1.

Applying Eq. (24.10) and rearranging the terms results in: ∆ˆ = ( g m + yˆ S )( g o + gˆ m ) + (sCC − g m )( g o + gˆ m ) + ( g m + yˆ S )(sCC − gˆ m ) = sCC ( g m + g o ) + yˆ S (sCC − g o ) + gˆ m (sCC − g m ) 14 4244 3 1424 3 14243 ∆ ∆11 ∆12

(24.11)

Note the fact that Eq. (24.11), which is the direct result of the algorithm, is not cancellation-free. Some terms cancel out to result in the determinant of the original circuit and its two cofactors of interest. The final transfer functions can be obtained readily by substituting the preceding results into Eq. (24.6) through (24.8). 2. The signal flow graph method Two types of flow graphs are used in symbolic analysis. The first is referred to as a Mason’s SFG and the second as Coates graph. Mason’s SFG is by far a more popular and well-known SFG that has been used extensively in symbolic analysis among other controls applications. Both the Mason’s SFG and the Coates graph are used as a basis for hierarchical symbolic analysis. However, the Coates graph was introduced to symbolic analysis by Starzyk and Konczykowska [61] solely for the purpose of performing hierarchical symbolic analysis. This section covers the Mason’s SFG only. The symbolic methods developed here are based on the idea formalized by Mason [45] in the 1950s. Formulation of the signal flowgraph and then the evaluation of the gain formula associated with it (Mason’s formula) is the basis for symbolic analysis using this method. This method is used in the publicly available programs NASAP [47, 49] and SNAP [38]. The method has the same circuit size limitations as the tree enumeration method due to the exponential growth in the number of symbolic terms. However,

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the signal flowgraph method allows all four types of controlled sources to be analyzed which made it a more popular method for symbolic analysis. The method is not cancellation-free, which contributes to the circuit size limitation mentioned earlier. An improved signal flowgraph method that avoids term cancellations was described in [48]. The analysis process of a circuit consists of two parts: the first is constructing the SFG for the given circuit and the second is to perform the analysis on the SFG. Some definitions are needed before proceeding to the details of these two parts. Definition 6. Signal Flow Graph: An SFG is a weighted directed graph representing a system of simul­ taneous linear equations. Each node (xi) in the SFG represents a circuit variable (node voltage, branch voltage, branch current, capacitor charge, or inductor flux) and each branch weight (wij) represents a coefficient relating xi to xj . Every node in the SFG can be looked at as a summer. For a node xk with m incoming branches xk =

∑w x

(24.12)

ik i

i

where i spans the indices of all incoming branches from xi to xk . Definition 7. Path Weight: The weight of a path from xi to xj (Pij ) is the product of all the branch weights in the path. Definition 8. Loop Weight: The weight of a loop is the product of all the branch weights in that loop. This also holds for a loop with only one branch in it (self-loop). Definition 9. nth Order Loop: An nth order loop is a set of n loops that have no common nodes between any two of them. The weight of an nth order loop is the product of the weights of all n loops. Any transfer function xj /xi , where xi is a source node, can be found by the application of Mason’s formula: xj xi

=

1 ∆

∑P ∆ k

k

(24.13)

k

where ∆ =1−

∑ directed loop weights all

+

∑ 2nd-order loop weights all

−

(24.14)

∑ 3rd-order loop weights all

+L Pk = weight of the kth path from the source node x i to xj ∆k = ∆ with all loop contributions that are touching Pk eliminated The use of the preceding equations can be illustrated via an example.

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(24.15)

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I C CC

1

2

I V1

go

+

3

g mV1 FIGURE 24.6 Circuit for Example 24.2 with its tree highlighted.

V1 sC C gm I

-sCC -1/go

IC 1/g o V2 FIGURE 24.7 SFG for Example 24.2.

Example 2. Consider the circuit in Fig. 24.6. The formulation of the SFG for this circuit takes on the following steps: 1. Find a tree and a co-tree of the circuit such that all current sources are in the co-tree and all voltage sources are in the tree. 2. Use Kirchhoff ’s current law (KCL), branch admittances, and tree branch voltages to find an expression for every co-tree link current. In the case of a controlled source, simply use the branch relationship. For the previous example, this yields: IC = sCC (V1 − V2 ) = sCCV1 − sCCV2 I = g mV1 3. Use Kirchhoff ’s voltage law (KVL), branch impedances, and co-tree link currents to find an expression for every tree branch voltage. In the case of a controlled source, simply use the branch relationship. For the previous example, this yields: Vg o = V2 =

1 ( − I + IC ) go

4. Create the SFG by drawing a node for each current source, voltage source, tree branch voltage, and co-tree link current. 5. Use Eq. (24.12) to draw the branches between the nodes that realize the linear equations developed in the previous steps. Figure 24.7 is the result of executing the preceding steps on the example circuit. This formulation is referred to as the compact SFG. Any other variables that are linear combinations of the variables in the SFG (e.g., node voltages) can be added to the SFG by simply adding the extra node and implementing the linear relationship using SFG branches. A more detailed discussion of SFGs can be found in [7] and [40]. Now applying Eqs. (24.14) and (24.15) yields: P1 = −

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 sC  gm sC sC , P2 = C , L1 = − C , ∆ = 1 −  − C  , ∆1 = 1, ∆ 2 = 1 go go go  go 

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Equation (24.13) then produces the final transfer function V2 = V1

1 sC 1+ C go

 g m sCC  sCC − g m  − g + g  = sC + g  o o  C o

3. The parameter extraction method This method is best suited when few parameters in a circuit are symbolic while the rest of the parameters are in numeric form (s being one of the symbolic variables). The method was introduced in 1973 [2]. Other variations on the method were proposed later in [50, 56, 59]. The advantage of the method is that it is directly related to the basic determinant properties of widely used equation formulation methods such as the modified nodal method [27] and the tableau method [21]. As the name of the method implies, it provides a mechanism for extracting the symbolic parameters out of the matrix formulation, breaking the matrix solution problem into a numeric part and a symbolic part. The numeric part can then be solved using any number of standard techniques and recombined with the extracted symbolic part. The method has the advantage of being able to handle larger circuits than the previously discussed fully symbolic methods if only a few parameters are represented symbolically. If the number of symbolic parameters in a circuit is high, the method will exhibit the same exponential growth in the number of symbolic terms generated and will have the same circuit size limitations as the other algorithms previously discussed. The method does not limit the type of matrix formulation used to analyze the circuit. However, the extraction rules depend on the pattern of the symbolic parameters in the matrix. Alderson and Lin [1] use the indefinite admittance matrix as the basis of the analysis and the rules depend on the appearance of a symbolic parameter in four locations in the matrix: (i,i), (i,j), (j,i), and (j,j). Singhal and Vlach [59] use the tableau equations and can handle a symbolic parameter that only appears once in the matrix. Sannuti and Puri [56] force the symbolic parameters to appear only on the diagonal using a two-graph method [7] to write the tableau equations. The parameter extraction method was further simplified in [50], where the formula is given to calculate a coefficient (generally a polynomial in s) at every symbol combination. Some invalid symbol combinations (i.e., the ones that do not appear in the final formula) can be eliminated before calculations by topological considerations. To illustrate both approaches to parameter extraction, this section presents the indefinite admittance matrix (IAM) formulation and the most recent two-graph method. Details of other formulations can be found in [40, 48, 56, 59].

Indefinite Admittance Matrix Approach One of the basic properties of the IAM is the symmetric nature of the entries sometimes referred to as quadrantal entries [7, 40]. A symbolic variable α will always appear in four places in the indefinite admittance matrix, +α in entries (i, k) and (j, m), and -α in entries (i, m) and (j, k) as demonstrated in the following equation: k  M  iα   M  j −α   M 

m L

L

M   −α   M   −α   M 

where i ≠ j and k ≠ m. For the case of an admittance y between nodes i and j, we have k = i and j = m. The basic process of extracting the parameter (the symbol) α can be performed by applying the following equation [2, 7]: © 2003 by CRC Press LLC

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cofactor of Yind = cofactor of Yind, α=0 + (−1)

j +m

α(cofactor of Yα )

(24.16)

where Yα is a matrix that does not contain α and is obtained by: 1. Adding row j to row i 2. Adding column m to column k 3. Deleting row j and column m For the case where several symbols exist, the previous extraction process can be repeated and would result in cof ( Yind ) =

∑ P cof (Y ) j

j

j

where Pj is some product of symbolic parameters including the sign and Yj is a matrix with the frequency variable s, possibly being the only symbolic variable. The cofactor of Yj may be evaluated using any of the usual evaluation methods [7, 64]. Programs implementing this technique include NAPPE2 [40] and SAPWIN [37]. Example 4 [7]. Consider the resistive circuit in Fig. 24.8. The goal is to find the input impedance Z14 using the parameter extraction method where gm is the only symbolic variable in the circuit. In order to use Eqs. (24.6) and (24.9), an admittance yˆs is added across the input terminals of the circuit to create the augmented circuit. The IAM is then written as (conductances in siemens [S])

Yˆ ind

 6 + yˆ S   gm − 5 = −g m −1   − yˆ S 

−5

−1

15.1

−g m −10

−10

g m +13

−0.1

−2

− yˆ S   −0.1   −2   yˆ S + 2.1

Applying Eq. (24.16) to extract yˆs results in

( )

cof Yˆ ind

 6   gm − 5 = cof  −g m −1   0 

−5

−1

15.1

−g m −10

−10

g m +13

−0.1

−2

0    8.1  −0.1  + yˆ S cof g m − 5.1  −2    −g m −3  2.1 

R2

1

R1 1.0

2

0.2

R7 0.1

3

ys

R3 0.5

g mV13 R6 10.0

4

FIGURE 24.8 Circuit for the parameter extraction method (resistances in ohms [Ω]).

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−5.1 15.1 −10

−3

  −g m −10  g m +13 

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Applying Eq. (24.16) again to extract gm yields 6  −5 = cof   −1  0 

( )

cof Yˆ ind

−5

−1

15.1

−10

−10

+13

−0.1

−2

 8.1  + yˆ S cof −5.1   −3

−5.1

0   5  −0.1  + g m cof −3  −2   −2 2.1 

−5 5.1 −0.1

−3    5.1 −10 + yˆ S g m cof   −5.1 13 

15..1 −10

0   −2.1  2.1 

−5.1  5.1 

After evaluating the cofactors numerically, the equation reduces to

( )

cof Yˆ ind = 137.7 + 10.5 g m + 96.3 yˆ S + 5.1 yˆ S g m From Eq. (24.9), this results in Z14 =

∆11 96.3 + 5.1g m = ∆ 137.7 + 10.5 g m

Two-Graph-Based Tableau Approach [50] This approach also employs the circuit augmentation by yˆs and gˆmVo, as in the tree enumeration method. It calls for the construction of two graphs: the voltage graph (GV or V-graph) and the current graph (GI or I-graph). For the purpose of parameter extraction (as well as generation of approximate symbolic expressions; see Section 24.5), it is required that both graphs have the same number of nodes (n). This means that the method can be directly applied only to RLCgm circuits. (All basic circuit components, including ideal op amps, can be handled by this approach after some circuit transformations [40, 64]. For the sake of simplicity, however, only RLCgm circuits will be considered in this presentation.) The two graphs are constructed based on the element stamps shown in Fig. 24.9. Once the two graphs are constructed, a common spanning tree (i.e., a set of n-1 branches that form a spanning tree in both voltage and current graphs) is chosen. Choosing the common spanning tree (referred to just as “tree” in the remainder of this section) uniquely determines the co-tree in each graph.

y

i

p + Vpq -

q

Element

j

i

i gmVpq

p

j

q

j

i

i

p

y

j

i gm

gm j

Current graph

FIGURE 24.9 Element stamps for generating GV and GI.

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y

q

j

Voltage graph

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The tableau equation for such a network can be written as 1  BT Hx =  0  0 

0

−ZT

1

0

0

1

−YC

0

0 VT    0  VC    = 0 QC  IT     1   IC 

(24.17)

The first and last row of the system matrix H in Eq. (24.17) consists of tree (●T ) and co-tree (●C ) branch voltage-current relationships, and the second and third rows consist of fundamental loop and funda­ mental cut-set equations for GV and GI, respectively. Let the circuit have n nodes and b branches and contain k symbolic components (YS1, …, YSk ) in the co-tree branches (links) and l symbolic components (ZS1, …, ZSl ) in the tree branches; we define w = b – n – k + 1, t = n – l – 1. Diagonal matrices YC and ZT can be partitioned as follows YCs YC =   0

0  ZTs , ZT =   0 YCn 

0   ZTn 

(24.18)

where subscript s denotes immitances of symbolic components and subscript n denotes immitances of components given numerically. Matrices BT (fundamental loop matrix in GV) and QC (fundamental cut-set matrix in GI ) can also be partitioned as follows:  B11 BT =  B 21

B12   Q11 , QC =  Q 21 B 22 

Q12   Q 22 

(24.19)

Rows of B11 and B12 correspond to symbolic co-tree branches (in GV) and their columns correspond to symbolic and numeric tree branches, respectively. Rows of B21 and B22 correspond to numeric co-tree branches. Rows of Q11 and Q12 correspond to symbolic tree branches and their columns correspond to symbolic and numeric co-tree branches, respectively. Rows of Q21 and Q22 correspond to numeric tree branches. The submatrices are therefore of the following order: B11: k × l, B22: w × t, Q11: l × k, Q22: t × w. Let Sx = {1, 2, …, x}. For a given matrix F of order a × b let F(Iu, Jv) be the submatrix of F consisting of the rows and columns corresponding to the integers in the sets Iu , Jv , respectively. The sets Iu = {i1, i2 , …, iu} and Jv = {j1, j2, …, jv} are subsets of Sa and Sb , respectively. Let us also introduce the following notation:

[

1cd = diag e1

e2

L

]

ed ; c < d

0  for x ∈{1, 2,K,c} ex =  1  for x ∈{c +1,c + 2, K,d} The determinant of the system matrix H in Eq. (24.17), when some parameters take fixed numerical values, is det H = a +

b(α ) Z s ∑ J v

v

+

∑∑ I J u

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v

j1

Zs L Zs + j2 jv

c (β )Ys Ys ∑ I u

i1

u

d(α vβu ) Z s Z s L Z s Ys Ys LYs j1 j2 jv i1 i 2 iu

i2

LYs

iu

(24.20)

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where the summations are taken over all possible symbol combinations αv (symbolic tree elements) and βu (symbolic co-tree elements), and the numerical coefficients are given by:

[

]

[

a = det 1w + B′22 (−Q′22 ) = det 1t + (−Q′22 )B′22

]

 −Q12 ( J v , I w )  B′21 ( I w , J v ) b(α v ) = det 1tv+v +    −Q′   22  

 B′22   

 B12 ( I u , J t )  −Q′21 ( J t , I u ) c (βu ) = det 1uw +u +    B′   22  

 −Q′22   

[

[

 −Q11 ( J v , I u )   d(α vβu ) = det  1vv +t +u +  −Q′21 ( J t , I u )     1u  

]

]

−Q12 ( J v , I w )   B11 ( I u , J v ) −Q′22    B′ ( I , J )   21 w v 0 

(24.21)

B12 ( I u , J t ) B′22

 −1u   0   

In the preceding equations, 0 represents a zero matrix of appropriate order, and the submatrices B′ij and Q′ij are defined as: B′21 ( I w , J v ) = YCnB 21 ( I w , J v ) , B′22 = YCnB 22 Q′21 ( J t , I u ) = ZTnQ 21 ( J t , I u ) , Q′22 = ZTnQ 22

(24.22)

where the submatrix B21(Iw , Jv) is obtained from the submatrix B21 by including all of its rows and only columns corresponding to a particular combination (αv) of symbolic tree elements; submatrix Q21(Jt , Iu ) is obtained from the submatrix Q21 by including all of its rows and only columns corresponding to a particular combination (βu ) of symbolic co-tree elements. Application of Eqs. (24.20) and (24.21) for a circuit with m symbolic parameters requires, theoretically, the calculation of 2m determinants. Not all of these determinants may need to be calculated due to the following property of the determinants in Eq. (24.21). If a set of symbolic tree elements (αv) forms a cut-set in GI (symbolic tree cut-set), then the corresponding coefficients b(αv ) and d(αv βu) in Eq. (24.20) equal to zero. Likewise, if the set of symbolic co-tree elements (βu ) forms a loop in GV (symbolic co-tree loop), the corresponding coefficients c(βu ) and d(αv βu ) in Eq. (24.20) equal to zero. Once the determinant det(H) is obtained from Eq. (24.20), the sorting scheme, identical to that expressed in Eq. (24.9), is applied and the required network function(s) can be calculated using Eqs. (24.6) through (24.8). The main feature of this approach is the fact that each coefficient at a valid symbol combination is obtained directly by calculating a single, easily formulated determinant (a polynomial in s, in general case). The method was implemented in a computer program called UTSSNAP [52]. The following example illustrates this technique of parameter extraction. Example 5. Consider again the circuit in Fig. 24.8. Assume this time that two components, R1 and gm , are given symbolically. The goal is again to find the input impedance Z41 in a semi-symbolic form using the parameter extraction method based on the two-graph tableau formulation. The voltage and current graphs of the circuit are shown in Fig. 24.10. The common spanning tree chosen is T = {R1, R2, R3} with one symbolic element. For this circuit, we have: n = 4, b = 7, k = 2, l = 1, w = 2, and t = 2.

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R2

1

R1

2

R2

1

R7

R1

R6

R6

3

R7

gm

gm ys

2

3

ys

R3

R3

GI

4

GV

4

FIGURE 24.10 The current and voltage graphs for the circuit in Fig. 24.8 with the common spanning tree highlighted.

The matrices YC , Z T , QC , and BT can now be determined as:  yˆ S   YC =      1  QC = 0  1

      10

gm 0.1

1

1

−1

−1

0

1

R1  ZT =    −1  −1 BT =  −1  −1 

1  −1  0 

0.2

0 0 1 1

    0.5 −1  0  −1  0 

′: Using Eq. (24.22), we can calculate matrices B′22 and Q 22 0.1 B′22 =   0

0  1  10 1

−1 0.1 = 0   10

−0.1 0.2  , Q′22 =   0 0 

0  −1  0.5  1

−1 −0.2 = 0   0.5

−0.2  0 

Now, applying Eq. (24.21), the coefficient a in Eq. (24.20) is calculated as:  1 a = det    0 

0 0.1 + 1  10

−0.1  0.2  0  −0.5

0.2 1.07  = det   2 0 

0.02  = 3.17 3 

Because only one symbolic tree element exists, namely R1, we have: αv = {R1} and the associated sets: Jv = {1}, Iw = {1,2}. Using Eq. (24.22), we calculate 0.1 B′21 ( I w , J v ) = YCnB 21 ( I w , J v ) =   0 The coefficient b(R1) can now be obtained from:

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0  −1 −0.1   =   10 −1  −10 

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 0  b(R1) = det  0   0 

0  −1   0 +  0.2   1 −0.5

0 1 0

 10.1  = det −2.02   0.05

−10.1

−1   −0.1 0.2    −10 0 

0.1 10

 −0.1  0   

0.1   −0.02 = 10.6  1.05 

3.02 −0.05

Other numerical coefficients in Eq. (24.20) are calculated in a similar way: c ( yˆ S ) = 1.51, c ( g m ) = 0, c ( yˆ S g m ) = 0, d( R1 yˆ S ) = 8.12 , d( R1 g m ) = 1.05 , d( R1 yˆ S g m ) = 0.51 Adding all terms, sorting according to Eq. (24.9), and applying Eq. (24.6) finally results in: Z 41 =

1.51 + 8.12R1 + 0.51R1 g m 3.17 +10.6 R1 +1.05R1 g m

Matrices in Eq. (24.21) may contain terms dependent on the complex frequency s. Determinants of such matrices are polynomials in s as long as all matrix elements are of the form: a = α + sβ. An interpolation method may be used to calculate the coefficients of those polynomials. One such method is briefly described in the next paragraph. 4. The interpolation method This method is best suited when s is the only symbolic variable. In such case, a transfer function has the rational form m

N (s ) H (s ) = = D(s )

∑a s

i

i

i=0 n

∑b s

i

i

i=0

where N(s) and D(s) are polynomials in s with real coefficients and m ≤ n. Coefficients of an nth-order polynomial P (s ) =

n

∑p

k

k

k=0

can be obtained by calculating the value of P(s) at n + 1 distinct points si and then solving the following set of equations: 1  1    1 

© 2003 by CRC Press LLC

s0

s02

L

s1

s12

L

sn2

L

M sn

s0n   p0   P(s0 )     s1n   p1   P(s1 )     =   M   M      snn   pn  P(sn )

(24.23)

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Because the matrix in Eq. (24.23) is nonsingular, the unique solution exists. It is well known [58, 64] that for numerical accuracy and stability, the best choice of the interpolation points is a set of q ≥ n + 1 points si uniformly spaced on the unit circle in the complex plane. Once all the values of P(si) are known, the polynomial coefficients can be calculated through the discrete Fourier transform (DFT). To apply this technique to the problem of finding a transfer function, let us assume that a circuit behavior is described by a linear equation Ax = b

(24.24)

in which the coefficient matrix has entries of the form: a = α + sβ (both the modified nodal and the tableau methods have this property). Then, each transfer function of such circuit has the same denom­ inator D(s) = A. If the circuit Eq. (24.24) is solved by LU factorization at s = si , both the transfer function H(si) and its denominator D(si ) are obtained simultaneously. The value of the numerator is then calculated simply as N(si) = H(si )D(si ). Repeating this process for all points si (i = 0, 1, …, q) and then applying the DFT to both sets of values, D(si ) and N(si ), gives the required coefficients of the numerator and denominator polynomials. If the number of interpolation points is an integer power of 2 (q = 2k), the method has the advantage that the fast Fourier transform can be used to find the coefficients. This greatly enhances the execution time [40]. The method has been extended to handle several symbolic variables in addition to s [58]. The program implementation [64] allows a maximum of five symbolic parameters in a circuit. With the emergence of approximate symbolic analysis, the polynomial interpolation method has attracted new interest. (It is desirable to know the accurate numerical value of polynomial coefficients before one attempts an approximation.) Recently, a new adaptive scaling mechanism was proposed [14] that significantly increases the circuit size that can be handled accurately and efficiently. Other classifications of symbolic methods have been reported [18]. These methods can be considered as variations on the previous basic four methods. The reported methods include elimination algorithms, recursive determinant-expansion algorithms, and nonrecursive nested-minors method. All three are based on the use of Cramer’s rule to find the determinant and the cofactors of a matrix. Another reported class of algorithms uses Modified Nodal Analysis [27] as the basis of the analysis, sometimes referred to as a direct network approach [22, 36]. This class of methods is covered in the next section. The first generation of computer programs available for symbolic circuit simulation based on these methods includes NASAP [47] and SNAP [38]. Research in the late 1980s and early 1990s produced newer symbolic analysis programs. These programs include ISSAC [18], SCAPP [22], ASAP [12], EASY [60], SYNAP [57], SAPEC [43], SAPWIN [37], SCYMBAL [31], GASCAP [29], SSPICE [66], and STAINS [53].

24.4 Hierarchical Methods (Sequence of Expressions) All the methods presented in the previous section have circuit size limitations. The main problem is the exponential growth of the number of symbolic terms involved in the expression for the transfer function in Eq. (24.3) as the circuit gets larger. The solution to analyzing large-scale circuits lies in a total departure from the traditional procedure of trying to state the transfer function as a single expression and using a sequence of expressions (SoE) procedure instead. The idea is to produce a succession of small expressions with a backward hierarchical dependency on each other. The growth of the number of expressions in this case will be, at worst case, quadratic [22]. The advantage of having the transfer function stated in a single expression lies in the ability to gain insight to the relationship between the transfer function and the network elements by inspection [39]. For large expressions, though, this is not possible and the single expression loses that advantage. ISSAC [67], ASAP [13], SYNAP [57], and Analog Insydes [26] attempt to handle larger circuits by maintaining the single expression method and using circuit dependent approximation techniques. The tradeoff is

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accuracy for insight. Therefore, the SoE approach is more suitable for accurately handling large-scale circuits. The following example illustrates the features of the sequence of expressions. Example 6. Consider the resistance ladder network in Fig. 24.11. The goal is to obtain the input impedance function of the network, Zin = Vin /Iin . The single expression transfer function Z4 is: Z4 =

R1R3 + R1R4 + R2 R3 + R2 R4 + R3 R4 R1 + R2 + R3

The number of terms in the numerator and denominator are given by the Fibonacci numbers satisfying the following difference equation: y k+2 = y k+1 + y k ; k = 0,1, 2,K; y 0 = 0, y1 = 1 An explicit solution to the preceding equation is: n

yn =

n

1 1+ 5  1− 5  − ≈ 0.168 ⋅1.618n for large n 5  2   2 

The solution demonstrates that the number of terms in Zn increases exponentially with n. Any single expression transfer function has this inherent limitation. Now, using the SoE procedure, the input impedance can be obtained from the following expressions: Z1 = R1 ; Z 2 = Z1 + R2 ; Z 3 =

Z 2 R3 ; Z 4 = Z 3 + R4 Z 2 + R3

It is obvious for each additional resistance added, the sequence of expressions will grow by one expression, either of the form Zi – 1 + Ri or Zi – 1 Ri/Zi –1 + Ri . The number of terms in the sequence of expressions can be calculated from the formula: 2  .5n − 2 for n even yn =  2.5n −1.5 for n odd which exhibits a linear growth with respect to n. Therefore, to find the input impedance of a 100-resistor ladder network, the single expression methods would produce 7.9 × 1020 terms, which requires unreal­ istically huge computer storage capabilities. On the other hand, the SoE method would produce only 248 terms, which is even within the scope of some desk calculators. Another advantage of the SoE is the number of arithmetic operations needed to evaluate the transfer function. To evaluate Z9, for example, the single expression methods would require 302 multiplications n+1

R2n

n

R2n-2 R2n-1

n-1

3

R4

2

R2n-3

R2

1

R3

R1

0

Z2n

Z 2n-1

FIGURE 24.11 Resistive ladder network.

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Z4

Z3

Z2

Z1

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771

and 87 additions. The SoE method would only require eight multiplications and eight additions, a large reduction in computer evaluation time. All this makes the concept of symbolic circuit simulation of large-scale networks very possible. Two topological analysis methods for symbolic simulation of large-scale circuits have been proposed in [61] and in [25]. The first method utilizes the SoE idea to obtain the transfer functions. The method operates on the Coates graph [8] representing the circuit. A partitioning is proposed onto the flowgraph and not the physical network. The second method also utilizes the sequence of expressions and a Mason’s signal flow graph [45] representation of the circuit. The method makes use of partitioning on the physical level instead of on the graph level. Therefore, for a hierarchical circuit, the method can operate on the subcircuits in a hierarchical fashion in order to produce a final solution. The fundamentals of both signal flow graph methods were described in the previous section. Another hierarchical approach is one that is based on Modified Nodal Analysis [27]. This method [22] exhibits a linear growth (for practical circuits) in the number of terms in the symbolic solutions. The analysis methodology introduces the concept of the RMNA (Reduced Modified Nodal Analysis) matrix. This allows the characterization of symbolic circuits in terms of only a small subset of the network variables (external variables) instead of the complete set of variables. The method was made even more effective by introducing a locally optimal pivot selection scheme during the reduction process [53]. For a circuit containing several identical4 subcircuits, the analysis algorithm is most efficient when network partitioning is used. For other circuits, the best results (the most compact SoE) are obtained when the entire circuit is analyzed without partitioning. The SoE generation process starts with the formulation of a symbolic Modified Node Admittance Matrix (MNAM) for a circuit [40, 64]. Then all internal variables are suppressed one by one using Gaussian elimination with locally optimal pivot selection. Each elimination step produces a series of expressions and modifies some entries in the remaining portion of the MNAM. When all internal variables are suppressed, the resulting matrix is known as the Reduced Modified Node Admittance Matrix (RMNAM). Usually it will be a 2 × 2 matrix of a two-port.5 Most transfer functions of interest to a circuit designer can be represented by formulas involving the elements of RMNAM and the terminating admit­ tances. A detailed discussion of the method can be found in [53]. Based on this approach, a computer program called STAINS was developed. For a circuit with several identical subcircuits, the reduction process is first applied to all internal variables6 of the subcircuit, resulting in an intermediate RMNAM describing the subcircuit. Those RMNAMs are then recombined with the MNAM of the remaining circuit and the reduction process is repeated on the resulting matrix. To further illustrate the SoE approach, we present the following example. Example 7. Consider a bipolar cascode stage with bootstrap capacitor CB illustrated in Fig. 24.12 [18]. With the BJTs replaced by their low-frequency hybrid-π models (with rB , gm , and ro only), the full symbolic analysis yields the output admittance formula outlined in Fig. 24.13. The formula requires 48 additions and 117 multiplication/division operations. STAINS can generate several different sequences of expres­ sions. One of them is presented in Fig. 24.14. It requires only 24 additions and 17 multiplications/divisions.7

4The subcircuits have to be truly identical, i.e., they must have the same topology and component symbols. A typical example would be a large active filter containing a number of identical, nonideal op amps. 5In sensitivity calculations using SoE [5], the final RMNAM may need to be larger than 2 × 2. 6The internal variables are the variables not directly associated with the subcircuit’s connections to the rest of the circuit. 7Counting of visible arithmetic operations gives only a rough estimate of the SoE complexity, especially when complex numbers are involved. Issues related to SoE computational efficiency are discussed in Reference [55].

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I bias Vdd1

Vo Zo

0.5mA Q2

CB

R2 10k

Q1 Vin

100p

+ R1 0.5k

Vdd2

FIGURE 24.12 Bipolar cascode stage.

Zo = (G2*Gm1*Gm2+G1*G2*Gm1+G2*Gm2*Gp1+G2*Gm1*Gp2+Gm2*Go1*Gp1+G1*G2*Gp1+G2*Gm2*Go1+…

G2*Gm1*Go2+G1*Go2*Gp1+G2*Gp1*Gp2+G1*Go1*Gp1+G1*G2*Go2+G1*G2*Go1+Go2*Gp1*Gp2+…

Go1*Gp1*Gp2+G2*Go2*Gp1+G2*Go1*Gp2+G2*Go2*Gp2+Go1*Go2*Gp1+G2*Go1*Go2+…

s*(Cb*Gm1*Gm2+Cb*G1*Gm1+Cb*Gm1*Gp2+Cb*G2*Gm1+Cb*G1*Gp1+Cb*Gm2*Go1+Cb*Gp1*Gp2+…

Cb*G1*Go2+Cb*G2*Gp1+Cb*G1*Go1+Cb*Go1*Gp2+Cb*Go2*Gp2+Cb*Go1*Gp1+Cb*G2*Go1+…

Cb*G2*Go2+Cb*Go1*Go2))/…

(Go1*G2*Gm2*Gp1+Go1*G1*G2*Gp1+Go1*G2*Gp1*Gp2+Go1*G1*Go2*Gp1+Go1*G1*G2*Go2+…

Go1*Go2*Gp1*Gp2+Go1*G2*Go2*Gp2+Go1*G2*Gp2*Gp1+…

s*(Cb*Go1*G1*Gp1+Cb*Go1*Gp1*Gp2+Cb*Go1*G2*Gp1+Cb*Go1*G1*Go2+Cb*Go1*Go2*Gp2+…

Cb*Go1*G2*Go2));

FIGURE 24.13 Full symbolic expression for Zo of the cascode in Fig. 24.12.

d1 x1 x2 d2 x3 x4 d3 x5 x6 Yo Zo

= = = = = = = = = = =

-(G2+Gp2+s*Cb)/(s*Cb);

(Go1+Gm1)*d1-Gp2-Gm2;

-s*Cb-(G1+Gp1+Go1+Gm1+s*Cb)*d1;

Gp2/(s*Cb);

Go1+Gp2+Go2+Gm2+(Go1+Gm1)*d2;

-Go1-(G1+Gp1+Go1+Gm1+s*Cb)*d2;

x2/(x4);

Gm2+(Go2+Gm2)*d3;

x1-x3*d3;

Go2+x5*Go2/(x6);

1/Yo;

FIGURE 24.14 The SoE generated by STAINS for the cascode in Fig. 24.12.

24.5 Approximate Symbolic Analysis The SoE approach offers a solution for the exact symbolic analysis of large circuits. For some applications, it may be more important to obtain a simpler inexact expression, but the one that would clearly identify the dominant circuit components and their role in determining circuit behavior. Approximate symbolic © 2003 by CRC Press LLC

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linear circuit analysis problem

enter circuit description remove insignificant components (netlist or schematic data capture) from the small-signal eqv. circuit netlist

formulate equations or signal flow graphs

SBG remove insignificant terms/branches/nodes

matrix or graph

calculate network function from matrix or SFG

SDG generate only largest terms of transfer function

rational expression

perform algebraic postprocessing

SAG

remove insignificant terms from transfer function

rational expression

FIGURE 24.15 Classification of symbolic approximation techniques [26].

analysis provides the answer. Of course, manual approximation (simplification) techniques have been known and practiced by engineers for decades. To obtain compact and meaningful expressions by computer, symbolic analysis software must be capable of performing those approximations that are applied in manual circuit analysis in an automatic fashion. In addition to that, computer algorithms should be able to employ simplification strategies not available (or impractical) in manual approximation. In the last decade, a number of symbolic approximation algorithms have been developed and imple­ mented in symbolic circuit analysis programs. Depending on the stage in the circuit analysis process in which they are applied, these algorithms can be categorized as: simplification before generation (SBG), simplification during generation (SDG), and simplification after generation (SAG). Figure 24.15, adapted from [26], presents an overview of the three types of approximation algorithms. SBG involves removing circuit components and/or individual entries in the circuit matrix (the sifting approach [28]) or eliminating some graph branches (the sensitivity-based two-graph simplification [69]) that do not contribute significantly to the final formula. SDG is based on generation of symbolic terms in a decreasing order of magnitude. The generation process is stopped when the error reaches the specified level. The most successful approach to date is based on the two-graph formulation [68]. It employs an algorithm to generate the common spanning trees in strictly decreasing order of magnitude [30]. In the case of frequency-dependent circuit, this procedure is applied separately to different powers of s. Mathematical formalism of matroids is well suited to describe problems of SDG [69]. When applied alone, SAG is a very ineffective technique, because it requires generation and storage of a large number of unnecessary terms. When combined with SBG and SDG methods, however, it can produce the most compact expressions by pruning redundant terms not detected earlier in the simplifi­ cation process. All simplification techniques require careful monitoring of the approximation amplitude and phase errors (εA and εp). The error criteria can be expressed as follows: H (s, x ) − H * (s, x ) H (s, x )

≤ εA

∠H (s, x ) − ∠H * (s, x ) ≤ ε p © 2003 by CRC Press LLC

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10

x 10 4 Cascode: Output Impedance vs Frequency

9 8

|Zo| [kohm]

7 6 5 4 3 2 1 0 4 10

10

5

6

10

frequency [Hz]

10

7

10

8

FIGURE 24.16 Plot of  Zo  of the cascode, obtained numerically from the exact formula.

for s = jω, ω ∈ (ω1,ω2), and x ∈ (x1,x2), where H(s,x) is the exact transfer function, defined by Eq. (24.3), and H*(s,x) is the approximating function. The majority of the approximation methods developed to date use the simplified criteria, where the errors are measured only for a given set of circuit parameters x0 (the nominal design point) [33]. The following example, although quite simple, illustrates very well the advantages of approximate symbolic analysis. Example 8 [18]. Consider again the bipolar cascode stage, depicted in Fig. 24.12 and its fully symbolic expression for the output impedance, depicted in Fig. 24.13. Even for such a simple circuit, the full symbolic result is very hard to interpret and therefore not able to provide insight into the circuit behavior. Sequential form of the output impedance formula, presented in Fig. 24.14, is more compact than the full expression but also cannot be utilized for interpretation. A plot of Zo for a nominal set of component values (rπ = 5 kΩ, gm = 20 mS, ro = 100 kΩ for both BJTs), obtained numerically from the SoE in Fig. 24.14, is plotted in Fig. 24.16. By examining the plot, one can appreciate the general behavior of the function, but it is difficult to predict the influence of various circuit components on the output impedance. Applying symbolic approximation techniques we can obtain less accurate but still more revealing formulas. If a 10% maximum amplitude error is accepted, the simplified function takes the following form: Z o(10% ) =

g m1 ( g m2 + G1 )(G2 + sC B )

[

]

g o1 g π1 G2 ( g m2 + G1 ) + sC B (G1 + g π2 )

If we allow a 25% magnitude error,8 the output impedance formula can be simplified further: Z o( 25% ) =

g m1 g m2 (G2 + sC B )

g o1 g π1 (G2 g m2 + sC BG1 )

(24.25)

8It is important to note that the approximate expressions were developed taking into account variations of BJT parameters; the fact that both simplified formulas give identical results at the nominal design point is purely coincidental.

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�� � �

� �� � �� �� �π � ��� � �� �π� ���

��� � �� ��

�� ��� �� ��

FIGURE 24.17 Asymptotic plot of  Zo  of the cascode based on Eq. (24.26).

The impedance levels as well as pole and zero estimates can be easily obtained from Eq. (24.25):

Z o ( low f ) ≅

β g m1 = 1 g π1 g o1 g o1

Z o ( high f ) ≅

g m1 g m2 g = m2 Z ( low f ) g π1 g o1G1 G1 o

(24.26)

G z≅− 2 CB p≅ −

g m2G2 G1C B

An asymptotic plot of Zo , based on Eq. (24.26), is plotted in Fig. 24.16.

24.6 Time-Domain Analysis The previous sections discussed the different frequency domain techniques for symbolic analysis. Sym­ bolic analysis methods in the transient domain did not appear until the beginning of the 1990s [3, 24, 36]. The main limitation to symbolic time-domain analysis is the difficulty in handling the symbolic integration and differentiation needed to handle the energy storage elements (mainly capacitors and inductors). This problem, of course, does not exist in the frequency domain because of the use of Laplace transforms to represent these elements. Although symbolic algebra software packages are available, such as MATHMATICA, MAXIMA, and MAPLE, which can be used to perform integration and differentia­ tions, they have not been applied to transient symbolic analysis due to the execution time complexity of these programs. All but one of the approaches in the time domain are actually semi-symbolic. The semisymbolic algorithms use a mixture of symbolic and numeric techniques to perform the analysis. The work here is still in its infancy. This section briefly discusses the three contributions published in the literature thus far. All symbolic time domain techniques deal with linear circuits and can be classified under one of the two categories.

Fully Symbolic Only one method has been reported in the literature that is fully symbolic [20]. This method utilizes a direct and hierarchical symbolic transient analysis approach similar to the one reported in [22]. The formulation is based on the well-known discrete models for numerical integration of linear differential © 2003 by CRC Press LLC

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equations. Three of these integration methods are implemented symbolically: the Backward Euler, the Trapezoidal, and Gear’s 2nd-Order Backward Differentiation [20]. The inherent accuracy problems due to the approximations in these methods show up when the symbolic expressions are evaluated numeri­ cally. A detailed discussion of this method can be found in [20].

Semi-Symbolic Three such algorithms have been reported in the literature thus far. Two of them [24, 36] simply take the symbolic expressions in the frequency domain, evaluate them numerically for a range of frequencies, and then perform a numeric inverse laplace transformation or a fast Fourier transformation (FFT) on the results. The approach reported in [36] uses an MNA, then a state-variable symbolic formulation to get the frequency domain response and can handle time-varying circuits, namely, switch power convert­ ers. The approach in [24] uses a hierarchical network approach [22] to generate the symbolic frequency domain response. The third algorithm reported in [3] is a hierarchical approach that uses an MNA and a state-variable symbolic formulation and then uses the eigenvalues of the system to find a closed-form numerical transient solution.

References [1] G. E. Alderson, P. M. Lin, “Integrating Topological and Numerical Methods for Semi-Symbolic Network Analysis,” Proc. of the 13th Midwest Symposium on Circuit Theory, 1970. [2] G. E. Alderson, P. M. Lin, “Computer Generation of Symbolic Network Functions — A New Theory and Implementation,” IEEE Trans. on Circuit Theory, vol. CT-20, pp. 48–56, Jan. 1973. [3] B. Alspaugh, M. Hassoun, “A Mixed Symbolic and Numeric Method for Closed-Form Transient Analysis,” Proc. ECCTD, Davos, 1993. [4] Z. Arnautovic, P. M. Lin, “Symbolic Analysis of Mixed Continuous and Sampled Data Systems,” Proc. IEEE ISCAS, pp. 798–801, 1991. [5] F. Balik, B. Rodanski, “Calculation of First-Order Symbolic Sensitivities in Sequential Form via the Transimpedance Method,” Proc. SMACD, Kaiserslautern, Germany, Oct. 1998, pp. 169–172. [6] D. A. Calahan, “Linear Network Analysis and Realization — Digital Computer Programs and Instruction Manual,” University of Ill. Bull., vol. 62, Feb. 1965. [7] L. O. Chua, P. M. Lin, Computer-Aided Analysis of Electronic Circuits — Algorithms and Computa­ tional Techniques. Englewood Cliffs, NJ: Prentice Hall, 1975. [8] C. L. Coates, “Flow graph Solutions of Linear Algebraic Equations,” IRE Trans. on Circuit Theory, vol. CT-6, pp. 170–187, 1959. [9] F. Constantinescu, M. Nitescu,“Computation of Symbolic Pole/Zero Expressions for Analog Circuit Design,” Proc. SMACD, Haverlee, Belgium, Oct. 1996. [10] G. DiDomenico et al., “BRAINS: A Symbolic Solver for Electronic Circuits,” Proc. SMACD, Paris, Oct. 1991. [11] G. Dröge, E. H. Horneber, “Symbolic Calculation of Poles and Zeros,” Proc. SMACD, Haverlee, Belgium, Oct. 1996. [12] F. V. Fernandez, A. Rodriguez-Vazquez, J. L. Huertas, “An Advanced Symbolic Analyzer for the Automatic Generation of Analog Circuit Design Equations,” Proc. IEEE ISCAS, Singapore, pp. 810–813, June 1991. [13] F. V. Fernandez et al., “On Simplification Techniques for Symbolic Analysis of Analog Integrated Circuits,” Proc. IEEE ISCAS, San Diego, CA, pp. 1149–1152, May 1992. [14] F. V. Fernandez et al., “Symbolic Analysis of Large Analog Integrated Circuits: The Numerical Reference Generation Problem,” IEEE Trans. on Circuits and Systems — II: Analog and Digital Signal Processing, vol. 45, no. 10, pp. 1351–1361, Oct. 1998. [15] J. K. Fidler, J. I. Sewell, “Symbolic Analysis for Computer-Aided Circuit Design — The Interpolative Approach,” IEEE Trans. on Circuit Theory, vol. CT-20, Nov. 1973. © 2003 by CRC Press LLC

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[16] T. F. Gatts, N. R. Malik, “Topoloigical Analysis Program For Linear Active Networks (TAPLAN),” Proc. of the 13th Midwest Symposium on Circuit Theory, 1970. [17] G. Gielen, H. Walscharts, W. Sansen, “ISSAC: A Symbolic Simulator for Analog Integrated Circuits,” IEEE J. of Solid-State Circuits, vol. SC-24, pp. 1587–1597, Dec. 1989. [18] G. Gielen, W. Sansen, Symbolic Analysis for Automated Design of Analog Integrated Circuits. Boston, MA: Kluwer Academic, 1991. [19] S. Greenfield, Transient Analysis for Symbolic Simulation, MS Thesis, Iowa State University, Dec. 1993. [20] S. Greenfield, M. Hassoun, “Direct Hierarchical Symbolic Transient Analysis of Linear Circuits,” Proc. ISCAS, 1994. [21] G. D. Hachtel et al., “The Sparse Tableau Approach to Network and Design,” IEEE Trans. on Circuit Theory, vol. CT-18, pp. 101–113, Jan 1971. [22] M. M. Hassoun, P. M. Lin, “A New Network Approach to Symbolic Simulation of Large-Scale Networks,” Proc. IEEE ISCAS, pp. 806–809, May 1989. [23] M. M. Hassoun, P. M. Lin, “An Efficient Partitioning Algorithm for Large-Scale Circuits,” Proc. IEEE ISCAS, New Orleans, pp. 2405–2408, May 1990. [24] M. M. Hassoun, J. E. Ackerman, “Symbolic Simulation of Large Scale Circuits in Both Frequency and Time Domains,” Proc. IEEE MWSCAS, Calgary, pp. 707–710, Aug. 1990. [25] M. Hassoun, K. McCarville, “Symbolic Analysis of Large-Scale Networks Using a Hierarchical Signal Flow Graph Approach,” J. of Analog VLSI and Signal Processing, Jan. 1993. [26] E. Henning, Symbolic Approximation and Modeling Techniques for Analysis and Design of Analog Circuits. Doctoral Dissertation, University of Kaiserslautern. Aachen: Shaker Verlag, 2000. [27] C. Ho, A. E. Ruehli, P. A. Brennan, “The Modified Nodal Approach to Network Analysis,” IEEE Trans. on Circuits and Systems, vol. CAS-25, pp. 504–509, June 1975. [28] J. J. Hsu, C. Sechen, “Low-Frequency Symbolic Analysis of Large Analog Integrated Circuits,” Proc. CICC, 1993, pp. 14.7.1–14.7.4. [29] L. Huelsman, “Personal Computer Symbolic Analysis Programs for Undergraduate Engineering Courses,” Proc. ISCAS, pp. 798–801, 1989. [30] N. Katoh, T. Ibaraki, H. Mine, “An Algorithm for Finding k Minimum Spanning Trees,” SIAM J. Comput., vol. 10, no. 2, pp. 247–255, May 1981. [31] A. Konczykowska, M. Bon, “Automated Design Software for Switched Capacitor ICs with Symbolic Simulator SCYMBAL,” Proc. DAC, pp. 363–368, 1988. [32] A. Konczykowska et al., “Symbolic Analysis as a Tool for Circuit Optimization,” Proc. IEEE ISCAS, San Diego, CA, pp. 1161–1164, May 1992. [33] A. Konczykowska, “Symbolic circuit analysis,” in Wiley Encyclopedia of Electrical and Electronics Engineering, J. G. Webster, Ed. New York: John Wiley & Sons, 1999. [34] J. Lee, R. Rohrer, “AWEsymbolic: Compiled Analysis of Linear(ized) Circuits Using Asymptotic Waveform Evaluation,” Proc. DAC, pp. 213-218, 1992. [35] B. Li, D. Gu, “SSCNAP: A Program for Symbolic Analysis of Switched Capacitor Circuits,” IEEE Trans. on CAD, vol. 11, pp. 334–340, 1992. [36] A. Liberatore et al., “Simulation of Switching Power Converters Using Symbolic Techniques,” Alt Frequenza, vol. 5, no. 6, Nov. 1993. [37] A. Liberatore et al., “A New Symbolic Program Package for the Interactive Design of Analog Circuits,” Proc. IEEE ISCAS, Seattle, WA, pp. 2209–2212, May 1995. [38] P. M. Lin, G. E. Alderson, “SNAP — A Computer Program for Generating Symbolic Network Functions,” School of EE, Purdue University, West Lafayette, IN, Rep. TR-EE 70-16, Aug. 1970. [39] P. M. Lin, “A Survey of Applications of Symbolic Network Functions,” IEEE Trans. on Circuit Theory, vol. CT-20, pp. 732–737, Nov. 1973. [40] P. M. Lin, Symbolic Network Analysis. Amsterdam: Elsevier Science, 1991. [41] P. M. Lin, “Sensitivity Analysis of Large Linear Networks Using Symbolic Programs,” Proc. IEEE ISCAS, San Diego, CA, pp. 1145–1148, May 1992. © 2003 by CRC Press LLC

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[42] V. K. Manaktala, G. L. Kelly, “On the Symbolic Analysis of Electrical Networks,” Proc. of the 15th Midwest Symposium on Circuit Theory, 1972. [43] S. Manetti, “New Approaches to Automatic Symbolic Analysis of Electric Circuits,” Proc. IEE, pp. 22–28, Feb. 1991. [44] M. Martins et al.,“A Computer-Assisted Tool for the Analysis of Multirate SC Networks by Symbolic Signal Flow Graphs,” Alt Frequenza, vol. 5, no. 6, Nov. 1993. [45] S. J. Mason, “Feedback Theory — Further Properties of Signal Flow Graphs,” Proc. IRE, vol. 44, pp. 920–926, July 1956. [46] J. O. McClanahan, S. P. Chan, “Computer Analysis of General Linear Networks Using Digraphs,” Int. J. of Electronics, no. 22, pp. 153–191, 1972. [47] L.P. McNamee, H. Potash, A User’s and Programmer’s Manual for NASAP, University of California at Los Angeles, Rep. 63-38, Aug. 1968. [48] R. R. Mielke, “A New Signal Flowgraph Formulation of Symbolic Network Functions,” IEEE Trans. on Circuits and Systems, vol. CAS-25, pp. 334–340, June 1978. [49] H. Okrent, L. P. McNamee, NASAP-70 User’s and Programmer’s Manual, UCLA, Technical Report ENG-7044, 1970. [50] M. Pierzchala, B. Rodanski, “A New Method of Semi-Symbolic Network Analysis,” Proc. IEEE ISCAS, Chicago, IL, pp. 2240–2243, May 1993. [51] M. Pierzchala, B. Rodanski, “Efficient Generation of Symbolic Network Functions for Large-Scale Circuits,” Proc. MWSCAS, Ames, IO, pp. 425–428, August 1996. [52] M. Pierzchala, B. Rodanski,“Direct Calculation of Numerical Coefficients in Semi-Symbolic Circuit Analysis,” Proc. SMACD, Kaiserslautern, Germany, Oct. 1998, pp. 173–176. [53] M. Pierzchala, B. Rodanski, “Generation of Sequential Symbolic Network Functions for LargeScale Networks by Circuit Reduction to a Two-Port,” IEEE Trans. on Circuits and Systems — I: Fundamental Theory and Applications, vol. 48, no. 7, July 2001. [54] C. Pottle, CORNAP User Manual, School of Electrical Engineering, Cornell University, Ithaca, NY, 1968. [55] B. Rodanski, “Computational Efficiency of Symbolic Sequential Formulae,” Proc. SMACD, Lisbon, Portugal, pp. 45-50, Oct. 2000. [56] P. Sannuti, N. N. Puri, “Symbolic Network Analysis — An Algebraic Formulation,” IEEE Trans. on Circuits and Systems, vol. CAS-27, pp. 679–687, Aug. 1980. [57] S. Seda, M. Degrauwe, W. Fichtner, “Lazy-Expansion Symbolic Expression Approximation in SYNAP,” 1992 Int. Conf. Computer-Aided Design, Santa Clara, CA, pp. 310–317, 1992. [58] K. Singhal, J. Vlach, “Generation of Immittance Functions in Symbolic Form for Lumped Distrib­ uted Active Networks,” IEEE Trans. on Circuits and Systems, vol. CAS-21, pp. 57–67, Jan. 1974. [59] K. Singhal, J. Vlach, “Symbolic Analysis of Analog and Digital Circuits,” IEEE Trans. on Circuits and Systems, vol. CAS-24, pp. 598–609, Nov. 1977. [60] R. Sommer, “EASY — An Experimental Analog Design System Framework,” Proc. SMACD, Paris, Oct. 1991. [61] J. A. Starzyk, A. Konczykowska, “Flowgraph Analysis of Large Electronic Networks,” IEEE Trans. on Circuits and Systems, vol. CAS-33, pp. 302–315, March 1986. [62] J. A. Starzyk, J. Zou “Direct Symbolic Analysis of Large Analog Networks,” Proc. MWSCAS, Ames, IO, pp. 421–424, Aug. 1996. [63] M. D. Topa, “On Symbolic Analysis of Weakly-Nonlinear Circuits,” Proc. SMACD, Kaiserslautern, Germany, Oct. 1998, pp. 207–210. [64] J. Vlach, K. Singhal, Computer Methods for Circuit Analysis and Design, 2nd ed. New York: Van Nostrand Reinhold, 1994. [65] C. Wen, H. Floberg, Q. Shui-sheng, “A Unified Symbolic Method for Steady-State Analysis of Non­ linear Circuits and Systems,” Proc. SMACD, Kaiserslautern, Germany, Oct. 1998, pp. 218–222.

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[66] G. Wierzba et al., “SSPICE — A Symbolic SPICE Program for Linear Active Circuits,” Proc. MWS­ CAS, 1989. [67] P. Wambacq, G. Gielen, W. Sansen, “A Cancellation-Free Algorithm for the Symbolic Simulation of Large Analog Circuits,” Proc. ISCAS, San Diego, CA, pp. 1157–1160, May 1992. [68] P. Wambacq, G. E. Gielen, W. Sansen, “Symbolic Network Analysis Methods for Practical Analog Integrated Circuits: A Survey,” IEEE Trans. on Circuits and Systems — II: Analog and Digital Signal Processing, vol. 45, no. 10, pp. 1331–1341, Oct. 1998. [69] Q. Yu, C. Sechen, “A Unified Approach to the Approximate Symbolic Analysis of Large Analog Integrated Circuits,” IEEE Trans. on Circuits and Systems — I: Fundamental Theory and Applications, vol. 43, no. 8, pp. 656–669, Aug. 1996.

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25 Analysis in the

Time Domain

25.1 Signal Types Introduction • Step, Impulse, and Ramp • Sinusoids • Periodic and Aperiodic Waveforms

25.2 First-Order Circuits Introduction • Zero-Input and Zero-State Response • Transient and Steady-State Responses • Network Time Constant

Robert W. Newcomb University of Maryland

25.3 Second-Order Circuits Introduction • Zero-Input and Zero-State Response • Transient and Steady-State Responses • Network Characterization

25.1 Signal Types Introduction Because information into and out of a circuit is carried via time domain signals we look first at some of the basic signals used in continuous time circuits. All signals are taken to depend on continuous time t over the full range –∞ < t < ∞. It is important to realize that not all signals of interest are functions in the strict mathematical sense; we must go beyond them to generalized functions (e.g., the impulse), which play a very important part in the signal processing theory of circuits.

Step, Impulse, and Ramp The unit step function, denoted 1(·), characterizes sudden jumps, such as when a signal is turned on or a switch is thrown; it can be used to form pulses, to select portions of other functions, and to define the ramp and impulse as its integral and derivative. The unit step function is discontinuous and jumps between two values, 0 and 1, with the time of jump between the two taken as t = 0. Precisely, 1  1(t ) =  0 

if t > 0 if t < 0

(25.1)

which is illustrated in Fig. 25.1 along with some of the functions to follow. Here, the value at the jump point, t = 0, purposely has been left free because normally it is immaterial and specifying it can lead to paradoxical results. Physical step functions used in the laboratory are actually continuous functions that have a continuous rise between 0 and 1, which occurs over a very short time. Nevertheless, instances occur in which one may wish to set 1(0) equal to 0 or to 1 or to 1/2 (the latter, for example, when calculating the values of a Fourier series at a discontinuity). By shifting the time

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1(t)

r(t) slope = 1

1

0

t

0

Unit Step Function

t

Unit Ramp Function

to Infinity unit area

0

t

Impulse Generalized Function

FIGURE 25.1 Step, ramp, and impulse functions.

argument the jump can be made to occur at any time, and by multiplying by a factor the height can be changed. For example, 1(t – t0) has a jump at time t0 and a[1(t) – 1(t – t0)] is a pulse of width t0 and height a going up to a at t = 0 and down to 0 at time t0. If a = a(t) is a function of time, then that portion of a(t) between 0 and t0 is selected. The unit ramp, r(·) is the continuous function which ramps up linearly (with unit slope) from zero starting at t = 0; the ramp results from the unit step by integration r (t ) =

t

if t > 0



if t < 0

 ∫ 1(τ)dτ = t1(t ) = 0 t

−∞

(25.2)

As a consequence the unit step is the derivative of the unit ramp, while differentiating the unit step yields the unit impulse generalized function, δ(·) that is δ(t ) =

d1 (t ) d 2r (t ) = dt dt 2

(25.3)

In other words, the unit impulse is such that its integral is the unit step; that is, its area at the origin, t = 0, is 1. The impulse acts to sample continuous functions which multiply it, i.e., a(t )δ(t − t 0 ) = a(t 0 )δ(t − t 0 )

(25.4)

This sampling property yields an important integral representation of a signal x(·) x (t ) = =

∞

∫ x(τ)δ(t − τ)dτ −∞

∫

∞ −∞

x (t )δ(t − τ)dτ = x (t )

∫

∞ −∞

δ(t − τ)dτ

(25.5)

where the validity of the first line is seen from the second line, and the fact that the integral of the impulse through its jump point is unity. Equation (25.5) is actually valid even when x(·) is discontinuous and, consequently, is a fundamental equation for linear circuit theory. Differentiating δ(t) yields an even more discontinuous object, the doublet δ′(·). Strictly speaking, the impulse, all its derivatives, and signals of © 2003 by CRC Press LLC

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that class are not functions in the classical sense, but rather they are operators [1] or functionals [2], called generalized functions or, often, distributions. Their evaluations take place via test functions, just as voltages are evaluated on test meters. The importance of the impulse lies in the fact that if a linear time-invariant system is excited by the unit impulse, then the response, naturally called the impulse response, is the inverse Laplace transform of the network function. In fact, if h(t) is the impulse response of a linear time-invariant (continuous and continuous time) circuit, the forced response y(t) to any input u(t) can be obtained without leaving the time domain by use of the convolution integral, with the operation of convolution denoted by ∗, y (t ) = h ∗ u =

∞

∫ h(t − τ)u(τ)dτ

(25.6)

−∞

Equation (25.6) is mathematically rigorous, but justified on physical grounds through (25.5) as follows. If we let h(t) be the output when δ(t) is the input, then, by time invariance, h(t – τ) is the output when the input is shifted to δ(t – τ). Scaling the latter by u(τ) and summing via the integral, as designated in (25.5), we obtain a representation of the input u(t). This must result in the output representation being in the form of (25.6) by linearity of the system through similar scaling and summing of h(t – τ), as was performed on the input.

Sinusoids Sinusoidal signals are important because they are self-reproducing functions (i.e., eigenfunctions) of linear time-invariant circuits. This is true basically because the derivatives of sinusoids are sinusoidal. As such, sinusoids are also the natural outputs of oscillators and are delivered in power sources, including laboratory signal generators and electricity for the home derived from the power company. Eternal Eternal signals are defined as being of the same nature for all time, –∞ < t < ∞, in which case an eternal cosine repeats itself eternally in both directions of time, with an origin of time, t = 0, being arbitrarily fixed. Because eternal sinusoids have been turned on forever, they are useful in describing the steady operation of circuits. In particular, the signal A cos(ωt + θ) over –∞ < t < ∞ defines an eternal cosine of amplitude A, radian frequency ω = 2π f (with f being real frequency, in Hertz, which are cycles per second), at phase angle θ (in radians and with respect to the origin of time), with A, ω, and θ real numbers. When θ = π/2 this cosine also represents a sine, so that all eternal sinusoidal signals are contained in the expression A cos (ωt + θ). At times, it is important to work with sinusoids that have an exponential envelope, with the possibility that the envelope increases or decreases with time, that is, with positively or negatively damped sinusoids. These are described by Ae st cos(ωt + θ), where the real number is the damping factor, giving signals that damp out in time when the damping factor is positive and signals that increase with time when the damping factor is negative. Of most importance when working with this class of signals is the identity

[

]

e σ t + jωt = e st = e σt cos(ωt ) + j sin(ωt )

(25.7)

where s = σ + jω with j = –1. Here, s is called the complex frequency, with its imaginary part being the real (radian) frequency, ω. When no damping is present, s = jω, in which case the exponential form of (25.7) represents pure sinusoids. In fact, we see in this expression that the cosine is the real part of an exponential and the sine is its imaginary part. Because exponentials are usually easier than sinusoids to treat analytically, the consequence for real linear networks is that we can do most of the calculations with exponentials and convert back to sinusoids at the end. In other words, if a real linear system has a cosine or a damped cosine as a true input, it can be analyzed by using instead the exponential of which it is the real part as its (fictitious) input, finding the resulting (fictitious) exponential output, and then taking © 2003 by CRC Press LLC

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the real part at the end of the calculations to obtain the true output for the true input. Because expo­ nentials are probably the easiest signals to work with in theory, the use of exponentials rather than sinusoids usually greatly simplifies the theory and calculations for circuits operating under steady-state conditions. Causal Because practical circuits have not existed since t = –∞ they usually begin to be considered at a suitable starting time, taken to be t = 0, in which case the associated signals can be considered to be zero for t < 0. Mathematically, these functions are said to have support bounded on the left. The support of a signal is (the closure of) that set of times for which the signal is non-zero, therefore, the support of these signals is bounded on the left by zero. When signals are discontinuous functions they have the important property that they can be represented by multiplying with unit step functions signals which are differ­ entiable and have nonbounded support. For example, g(t) = est · 1(t) has a jump at t = 0 with support at the half line 0 to ∞ but has est infinitely differential of “eternal” support. A causal circuit is one for which the response is only nonzero after the input becomes nonzero. Thus, if the inputs are zero for t < 0, the outputs of causal circuits are also zero for t < 0. In such cases the impulse response, h(t), or the response to an input impulse of “infinite jump” at t = 0, satisfies h(t) = 0 for t < 0 and the convolution form of the output, (25.4), takes the form  y (t ) =  

 ∫ h(t − τ)u(τ)dτ1(t ) t

(25.8)

0

Periodic and Aperiodic Waveforms The pure sinusoids, although not the sinusoids with nonzero damping, are special cases of periodic signals. In other words, ones which repeat themselves in time every T seconds, where T is the period. Precisely, a time-domain signal g(·) is periodic of period T if g(t) = g(t + T), where normally T is taken to be the smallest nonzero T for which this is true. In the case of the sinusoids, A cos(ωt + θ) with ω = 2πf, the period is given by T = 1/f because {2π[ f (t + T)] + θ} = {2π ft + 2π( fT) + θ} = {2π ft + (2π + θ)}, and sinusoids are unchanged by a change of 2π in the phase angle. Periodic signals need to be specified over only one period of time, e.g., 0 ≤ t < T, and then can be extended periodically for all time by using t = t mod(T) where mod(·) is the modulus function; in other words, periodic signals can be looked upon as being defined on a circle, if we imagine the circle as being a clock face. Periodic signals represent rhythms of a system and, as such, contain recurring information. As many phycial systems, especially biomedical systems, either possess directly or to a very good approximation such rhythms, the periodic signals are of considerable importance. Even though countless periodic signals are available besides the sinusoids, it is important to note that almost all can be represented by a Fourier series. Exponentials are eigenfunctions for linear circuits, thus, the Fourier series is most conveiently expressed for circuit considerations in terms of the exponential form. If g(t) = g(t + T), then g (t ) ≅

∞

∑ c e n

j ( 2πnt T )

(25.9)

n=−∞

where the coefficients are complex and are given by cn =

1 T

∫

T

0

− j 2πnt T ) g (t )e ( dt = an + jbn

(25.10)

Strictly speaking, the integral is over the half-open interval [0,T ) as seen by considering g(·) defined on the circle. In (25.9), the symbol  is used to designate the expression on the right as a representation

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785

Analysis in the Time Domain

that may not exactly agree numerically with the left side at every point when g(·) is a function; for example, at discontinuities the average is obtained on the right side. If g(·) is real, that is, g(t) = g(t)∗, where the superscript * denotes complex conjugate, then the complex coefficients cn satisfy cn = c–∗n . In this case the real coefficients an and bn in (25.10) are even and odd in the indices; n and the an combine to give a series in terms of cosines, and the bn gives a series in terms of sines. As an example the square wave, sqw(t), can be defined by

(

)

sqw(t ) = 1(t ) − 1 t − [T 2] 0 ≤ t < T

(25.11)

and then extended periodically to –∞ < t < ∞ by taking t = tmod(T). The exponential Fourier series coefficients are readily found from (25.10) to be if n = 0

1 2   cn =  0  1   jπn  1 

if n = 2k ≠ 0 (even ≠ 0)

(25.12)

if n = 2k + 1 (odd )

for which the Fourier series is sqw(t ) ≅

1 + 2

∞

1

∑ jπ[2k + 1] e

j 2 π[ 2k + 1]t T

(25.13)

k=−∞

The derivative of sqw(t) is a periodic set of impulses

[

] = δ(t ) − δ(t − [T 2] ) 0 ≤ t < T

d sqw(t ) dt

(25.13)

for which the exponential Fourier series is easily found by differentiating (25.13), or by direct calculation from (25.10), to be ∞

∑( i=−∞

(

δ(t − iT ) − δ t − iT − [T 2]

∞

) ≅ ∑ 2 e j(2π[2k + 1]t T ) k=−∞

T

(25.15)

Combining the exponentials allows for a sine representation of the periodic generalized function signal. Further differentiation can take place, and by integrating (25.15) we get the Fourier series for the square wave if the appropriate constant of integration is added to give the DC value of the signal. Likewise, a further integration will yield the Fourier series for the sawtooth periodic signal, and so on. The importance of these Fourier series representations is that a circuit having periodic signals can always be considered to be processing these signals as exponential signals, which are usually self-repro­ ducing signals for the system, making the design or analysis easy. The Fourier series also allows visual­ ization of which radian frequencies, 2πn/T, may be important to filter out or emphasize. In many common cases, especially for periodically pulsed circuits, the series may be expressed in terms of impulses. Thus, the impulse response of the circuit can be used in conjunction with the Fourier series.

References [1] J. Mikusinski, Operational Calculus, 2nd ed., New York; Pergamon Press, 1983. [2] A. Zemanian, Distribution Theory and Transform Analysis, New York: McGraw-Hill, 1965.

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25.2 First-Order Circuits Introduction First-order circuits are fundamental to the design of circuits because higher order circuits can be con­ sidered to be constructed of them. Here, we limit ourselves to single-input-output linear time-invariant circuits for which we take the definition of a first-order circuit to be one described by the differential equation d1 ⋅

dy du + d0 ⋅ y = n1 ⋅ + n0 ⋅ u dt dt

(25.16)

where d0 and d1 are “denominator” constants and n0 and n1 are “numerator” constants, y = y (·) is the output and u = u (·) is the input, and both u and y are generalized functions of time t. So that the circuit truly will be first order, we require that d1 · n0 – d0 · n1 ≠ 0, which guarantees that at least one of the derivatives is actually present, but if both derivatives occur, the expressions in y and in u are not proportional, which would lead to cancellation, forcing y and u to be constant multiples of each other. Because a factorization of real higher-order systems may lead to complex first-order systems, we will allow the numerator and denominator constants to be complex numbers; thus, y and u may be complexvalued functions. If the derivative is treated as an operator, p = d[·]/dt, then (25.16) can be conveniently written as  n n   1 p + 0 u d0  n p + n0  d0 y = 1 u =   d1 p + d0  n1 + d1n0 − d0n1 u   d p + (d0 d1 )   1

if d1 = 0 (25.17) if d1 ≠ 0

where the two cases in terms of d1 are of interest because they provide different forms of responses, each of which frequently occurs in first-order circuits. As indicated by (25.17), the transfer function H ( p) =

n1 p + n0 d1 p + d0

(25.18)

is an operator (as a function of the derivative operator p), which characterizes the circuit. Table 25.1 lists some of the more important types of different first-order circuits along with their transfer functions and causal impulse responses. The following treatment somewhat follows that given in [1], although with a slightly different orien­ tation in order to handle all linear time-invariant continuous time continuous circuits.

Zero-Input and Zero-State Response The response of a linear circuit is, via the linearity, the sum of two responses, one due to the input when the circuit is initially in the zero state, called the zero-state response, and the other due to the initial state when no input is present, the zero-input response. By the linearity the total response is the sum of the two separate responses, and thus we may proceed to find each separately. In order to investigate these two types of responses, we introduce the state vector x(·) and the state-space representation (as previously p = d[·]/dt) px = Ax + Bu y = Cx + Du + Epu

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(25.19)

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TABLE 25.1

Typical Transfer Functions of First-Order Circuits

Transfer Function

Description

Impulse Response

n1 p d0

Differentiator

n1 δ ′(t ) d0

n0 d1 p

Integrator

n0 1(t ) d1

n1 p + n0 d1

Leaky differentiator

n0 n δ(t ) + 1 δ ′(t ) d1 d1

n0 d1 p + d0

Low-pass filter; lossy integrator

n0 − d01 t ⋅1(t ) e d1

n1 p d1 p + d0

High-pass filter

n1 n d − 0t δ(t ) + 1 20 e d1 ⋅1(t ) d1 d1

n1 p − (d0 d1 ) d1 p + (d0 d1 )

All-pass filter

d  n1  d − 0t δ(t ) − 2 0 e d1 ⋅1(t ) d1  d1  

d

d

where A, B, C, D, E are constant matrices. For our first-order circuit two cases are exhibited, depending upon d1 being zero or not. In the case of d1 = 0, y = (n1 d0 )u + (n1 d0 ) pu

d1 = 0

(25.20a)

Here, C = 0 and A and B can be chosen anything, including empty. When d1 ≠ 0, our first-order circuit has the following set of (minimal size) state-variable equations  d  px = − 0  ⋅ x + d1n0 − d0n1 ⋅ u  d1 

[

]

d1 ≠ 0

n  y = [1 ] ⋅ x +  1  ⋅ u  d1 

(25.20b)

By choosing u = 0 in (25.2), we obtain the equations that yield the zero input response. Specifically, the zero-input response is 0  y (t ) =  − d0 t d1 ⋅ y (0) e 

if d1 = 0 (25.21)

if d1 ≠ 0

which is also true by direct substitution into (25.16). Here, we have set, in the d1 ≠ 0 case, the initial value of the state, x(0), equal to the initial value of the output, y(0), which is valid by our choice of statespace equations. Note that (25.21) is valid for all time and y at t = 0 assumes the assigned initial value y(0), which must be zero when the input is zero and no derivative occurs on the output. The zero-state response is explained as the solution of (25.21) when x(0) = 0. In the case that d1 = 0, the zero-state response is y=

© 2003 by CRC Press LLC

n  n 0 n n u + 1 pu =  0 δ(t ) + 1 δ′(t ) ∗ u d0 d0 d0  d0 

d1 = 0

(25.22a)

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where ∗ denotes convolution, δ(·) is the unit impulse, and 1(·) is the unit step function. While in the case that d1 ≠ 0 d  n   d n − d0n1  − d01 t y =  1 δ(t ) +  1 0 e 1(t ) ∗ u  d1  d1   

d1 ≠ 0

(25.22b)

which is found by eliminating x from (25.20b) and can be checked by direct substitution into (25.16). The terms in the braces are the causal impulse responses, h(t), which are checked by letting u = δ with otherwise zero initial conditions, that is, with the circuit initially in the zero state. Actually, infinitely many noncausal impulse responses could be used in (25.22b). One such response is found by replacing 1(t) by –1(–t)]. However, physically the causal responses are of most interest. If d1 ≠ 0, the form of the responses is determined by the constant d0 /d1, the reciprocal of which (when d0 ≠ 0) is called the time constant, tc, of the circuit because the circuit impulse response decays to 1/e at time tc = d1 /d0. If the time constant is positive, the zero-input and the impulse responses asymptotically decay to zero as time approaches positive infinity, and the circuit is said to be asymptotically stable. On the other hand, if the time constant is negative, then these two responses grow without bounds as time approaches plus infinity, and the circuit is called unstable. It should be noted that as time goes in the reverse direction to minus infinity, the unstable zero-input response decays to zero. If d0 /d1 = 0 the zeroinput and impulse responses are still stable, but neither decay nor grow as time increases beyond zero. By linearity of the circuit and its state-space equations, the total response is the sum of the zero-state response and the zero-input response; thus, even when d0 = 0 or d1 = 0 y (t ) = e

d − 0 d1

y 0 + h(t ) ∗ u(t )

(25.23)

Assuming that u and h are zero for t < 0 their convolution is also zero for t < 0, although not necessarily at t = 0, where it may even take on impulsive behavior. In such a case, we see that y0 is the value of the output instantaneously before t = 0. If we are interested only in the circuit for t > 0, surprisingly, an input will yield the zero input response. That is, an equivalent input u0 exists, which will yield the zero input response for t > 0, this being u0(t) = d1y0 exp(–td0 /d1)1(t). Thus, y = h ∗ (u + u0) gives the same result as (25.23). When d1 = 0, the circuit acts as a differentiator and within the state-space framework it is treated as a special case. However, in practice it is not a special case because the current, i, versus voltage, v, for a capacitor of capacitance C, in parallel with a resistor of conductance G is described by i = Cpv + Gv. Consequently, it is worth noting that all cases can be handled identically in the semistate description d1  0

d1 −1 −d0  px =   0 0 

−d0  n0  x +  u n1  1 

(25.24)

y = [1 1]x where x(·) is the semistate instead of the state, although the first components of the two vectors agree in many cases. In other words, the semistate description is more general than the state description, and handles all circuits in a more convenient fashion [2].

Transient and Steady-State Responses This section considers stable circuits, although the techniques are developed so that they apply to other situations. In the asymptotically stable case, the zero input response decays eventually to zero; that is, transient responses due to initial conditions eventually will not be felt and concentration can be placed © 2003 by CRC Press LLC

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upon the zero-state response. Considering first eternal exponential inputs, u(t) = U exp(st) for –∞ < t < ∞ at the complex frequency s = σ + jω, where s is chosen as different from the natural frequency sn = –d0 /d1 = –1/tc and U is a constant, we note that the response is y(t) = Y(s) exp(st), as is observed by direct substitution into (25.16); this substitution yields directly Y (s ) =

n1s + n0 ⋅U d1s + d0

(25.25)

where y(t) = Y(s) exp(st) for u(t) = U exp(st) over –∞ < t < ∞. That is, an exponential excitation yields an exponential response at the same (complex) frequency s = σ + jω as that for the input. When σ = 0, the excitation and response are both sinusoidal and the resulting response is called the sinusoidal steady state (SSS). Equation (25.25) shows that the SSS response is found by substituting the complex frequency s = jω into the transfer function, now evaluated on complex numbers instead of differential operators as in (25.18), H (s ) =

n1s + n0 d1s + d0

(25.26)

This transfer function represents the impulse response, h(t), of which it is actually the Laplace transform, and as we found earlier, the causal impulse response is n1 n0  d δ(t ) + d δ′(t ),  0 0 h(t ) =  d  − 0t  n d  1 δ(t ) +  1n0 − d0n1 e d1 1(t ), d d1    1

if d1 = 0 (25.27) if d1 ≠ 0

However, practical signals are started at some finite time, normalized here to t = 0, instead of at t = –∞, as used for the preceding exponentials. Thus, consider an input of the same type but applied only for t > 0; i.e., let u(t) = U exp(st)1(t). The output is found by using the convolution y = h ∗ u; after a slight amount of calculation is evaluated to y (t ) = h(t ) ∗Ue st 1(t ) n1  st H (s )Ue 1(t ) + d Uδ(t )  0 = d − 0 d st H (s )Ue 1(t ) − 1n0 − d0n1 Ue d1 1(t )  d1s + d0

[

]

for d1 = 0

(25.28)

for d1 ≠ 0

For t > 0, the SSS remains present, while there is another term of importance when d1 ≠ 0. This is a transient term, which disappears after a sufficient waiting time in the case of an asymptotically stable circuit. That is, the SSS is truly a steady state, although one may have to wait for it to dominate. If a nonzero zero-input response exists, it must be added to the right side of (25.28), but for t > 0 this is of the same form as the transient already present, therefore, the conclusion is identical (the SSS eventually predominates over the transient terms for an asymptotically stable circuit). Because a cosine is the real part of a complex exponential and the real part is obtained as the sum of two terms, we can use linearity of the circuit to quickly obtain the output to a cosine input when we know the output due to an exponential. We merely write the input as the sum of two complex conjugate exponentials and then take the complex conjugates of the outputs that are summed. In the case of real coefficients in the transfer function, this is equivalent to taking the real part of the output when we take the real part of the input; that is, y = (h ∗ u3) = h ∗ u, when u = (ue), if y is real for all real u. © 2003 by CRC Press LLC

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Network Time Constant The time constant, tc , was defined earlier as the time for which a transient decays to 1/e of the intial value. As such, the time constant shows up in signals throughout the circuit and is a very useful parameter when identifying a circuit from its responses. In an RC circuit, the time constant physically results from the interaction of the equivalent capacitor (of which only one exists in a first-order circuit) of capacitance Ceq, and the Thévenin’s equivalent resistor, of resistance Req, that it sees. Thus, tc = ReqCeq. Closely related to the time constant is the rise time. Considering the low-pass case, the rise time, tr is defined as the time for the unit step response to go between 10% and 90% of its final value from its initial value. This is easily calculated because the unit step response is given by y1(⋅) (t ) = h(t ) ∗1(t ) =

d − 0t  n0  1 − e d1  ⋅1(t ) d0   

(25.29)

Assuming a stable circuit and setting this equal to 0.1 and 0.9 times the final value, n0/d0, it is readily found that tr =

[

]

d1 ⋅ ln(9) = ln (9) ⋅ t c ≈ 2.2t c d0

(25.30)

At this point, it is worth noting that for theoretical studies the time constant can be normalized to 1 by normalizing the time scale. Thus, assuming d1 and d0 ≠ 0 the differential equation can be written as d    dy dy d0 ⋅  1 ⋅ + y  = d0  + y dt  d0 d(d1 d0 ) t (d1 d0 )    n  

(

)

(25.31)

where tn = (d0/d1)t is the normalized time.

References [1] L. P. Huelsman, Basic Circuit Theory with Digital Computations, Englewood Cliffs, NJ: Prentice Hall, 1972. [2] R. W. Newcomb and B. Dziurla, “Some circuits and systems applications of semistate theory,” Circuits, Systems, and Signal Processing, vol. 8, no. 3, pp. 235–260, 1989.

25.3 Second-Order Circuits Introduction Because real transfer functions can be factored into real second-order transfer functions, second-order circuits are probably the most important circuits available; most designs are based upon them. As with first-order circuits, this chapter is limited to single-input-single-output linear time-invariant circuits, and unless otherwise stated, here real-valued quantities are assumed. By definition a second-order circuit is described by the differential equation d2 ⋅

d 2 y dy d 2u du + d ⋅ + d ⋅ y = n ⋅ + n1 ⋅ + n0 ⋅ u 1 0 2 2 2 dt dt dt dt

(25.32)

where di and ni are “denominator” and “numerator” constants, i = 0, 1, 2, which, unless mentioned to the contrary, are taken to be real. Continuing the notation used for first-order circuits, y = y(·) is the output and u = u(·) is the input; both u and y are generalized functions of time t. Assume that d2 ≠ 0, © 2003 by CRC Press LLC

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which is the normal case because any of the other special cases can be considered as cascades of real degree one circuits. Again, treating the derivative as an operator, p = d[·]/dt, (25.32) is written as y=

n2 p 2 + n1 p + n0 u d2 p 2 + d1 p + d0

(25.33)

with the transfer function H ( p) =

1 d2

  n p 2 + n1 p + n0  2 2   p + (d1 d2 ) p + (d0 d2 ) 

(

) (

n1 − (d1 d2 )n2 p + n0 − (d0 d2 )n2 1  n2 + = d2  p 2 + (d1 d2 ) p + (d0 d2 ) 

) 

(25.34)

 

where the second form results by long division of the denominator into the numerator. Because they occur most frequently when second-order circuits are discussed, we rewrite the denominator in two equivalent customarily used forms: p2 +

d1 d ω p + 0 = p 2 + n p + ω n2 = p 2 + 2ζω n p + ω n2 d2 d2 Q

(25.35)

where ωn is the undamped natural frequency ≥ 0, Q is the quality factor, and ζ is the damping factor = 1/(2Q). The transfer function is accordingly H ( p) =

1 d2

 n p2 + n p + n  1  n p2 + n p + n  1 0 2 1 0 =  2 2  2 2 2 ω + ω 2 ζω ω p + Q p d p p + + ( ) n n 2  n n  

(25.36)

Table 25.2 lists several of the more important transfer functions, which, as in the first-order case, are operators as functions of the derivative operator p.

Zero-Input and Zero-State Response Again, as in the first-order case, a convenient tool for investigating the time-domain behavior of a secondorder circuit is the state variable description. Letting the state vector be x(·), the state-space represen­ tation is px = Ax + Bu y = Cx + Du

(25.37)

where, as above, p = d[·]/dt, and A, B, C, D are constant matrices. In the present case, these matrices are real and one convenient choice, among many, is  0 px =  d0 −  d2

d   n1 − 1 n2 1    d 2  u d1  x +  −  d0   d1    d2   n0 − d n2  −  n1 − d n2      2 2 

n  1  y= 0 x +  1  u d  d2   2  © 2003 by CRC Press LLC

(25.38)

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TABLE 25.2

Typical Second-Order Circuit Transfer Functions

Transfer Function

Description

n0 1 d2 p2 + 2ζω n p + ω 2n

Impulse Response e −ζωnt

hlp (t ) =

n0 d2

   

hhp (t ) =

 ω e −ζωnt n2  δ(t ) − n sin 1 − ζ 2 ω nt + 2θ 1(t )   2 d2   1− ζ  

   

hbp (t ) =

n1 e −ζωnt cos  1 − ζ 2 ω nt + θ 1(t )   d2 1 − ζ 2

Low-pass

1 − ζ 2ω n

sin  1 − ζ 2 ω nt  1(t )  

High-pass n2 p2 2 d2 p + 2ζω n p + ω 2n

 ζ θ = arctan2  1 − ζ2  Bandpass

n1 p d2 p2 + 2ζω n p + ω 2n

 ζ θ = arctan2   1 − ζ2 

n2 p2 + ω 20 d2 p2 + 2ζω n p + ω 2n

Band-stop

hbs (t ) = hhp (t ) +

n2 p2 − 2ζω n p + ω 2n d2 p2 + 2ζω n p + ω 2n

All-pass

hap (t ) =

 n2  4ζω ne −ζωnt δ(t ) − cos  1 − ζ 2 ω nt + θ 1(t )   2 d2   1− ζ  

n0 1 d2 p2 + ω 2n

Oscillator,

hosc (t ) =

n0 sin (ω nt ) ⋅1(t ) d2

y(t )

= y(0) ⋅cos(ω nt ) +

when u = 0

R10 R11

− +

E3

1

−u

+ −

V1

R8 {d2/d0}

− +

−x1

⋅ sin(ω nt )

{d2/n1}

R6 1

R5 {d2}

− +

E5 y

+

C2

1 E4

E1

− +

{d2/d1} R7

ωn

R12

1

R1

1 R3

y′(0)

C1

1

R4

{d2/(n1+d2−d1+n2)}

u =0

n2ω 20 h (t ) n0 lp

1

R2 1

− +

E2

−x2

R9 {d2/((n0+d2−d0+n2)−(n1+d2−d1+n2))}

FIGURE 25.2 Generic, second-order op-amp RC circuit.

Here, the state is the 2-vector x = [x1 x2]T, with the superscript T denoting transpose. Normally, the state would consist of capacitor voltages and/or inductor currents, although at times one may wish to use linear combinations of these. From these state variable equations, a generic operational-amplifier (opamp) RC circuit to realize any of this class of second-order circuits is readily designed and given in Fig. 25.2. In the figure, all voltages are referenced to ground and normalized capacitor and resistor values are listed. Alternate designs in terms of only CMOS differential pairs and capacitors can also be given [3], while a number of alternate circuits exist in the catalog of Sallen and Key [4].

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Because (25.38) represents a set of linear constant coefficient differential equations, superposition applies and its solution can again be broken into two parts, the part due to initial conditions, x(0), called the zero-input response, and the part due solely to the input u, the zero-state response. The zero-input response is readily found by solving the state equations with u = 0 and initial conditions x(0). The result is y(t) = C exp(At) x(0), which can be evaluated by several means, including the following. Using a prime to designate the time derivative, first note that when u = 0, x1(t) = d2 y(t) and (from the first row of A) x1(t)′ = x2 (t) = d2 y(t)′. Thus, x1 (0) = d2 y(0) and x2 (0) = d2 y′(0), which allow the initial conditions to be expressed in terms of the measurable output quantities. To evaluate exp(At), note that its terms are linear combinations of terms with complex frequencies that are zeroes of the characteristic polynomial −1

 s det(s12 − A) = det  2  ωn

 2 2  = s + 2ζω ns + ω n s + 2ζω n 

(25.39)

= (s − s − )(s − s + ) For which the roots, called natural frequencies, are

(

) (

s ± = −ζ ± ζ 2 − 1 ω n = −1 ± 1 − 4Q 2

) 2Qω n

(25.40)

The case of equal roots will only occur when ζ2 = 1, which is the same as Q 2 = 1/4, for which the roots are real. Indeed, if the damping factor, ζ, is > 1 in magnitude, or equivalently, if the quality factor, Q, is 0.25, which is the same as ζ2 < 1, in which case the roots are complex conjugates, s– = s+∗

(

) (

s ± = −ζ ± j 1 − ζ 2 ω n = −1 ± j 4Q 2 − 1

) 2Qω ,

j = −1

n

(25.41)

By writing y(t) = a · exp(s+ t) + b · exp(s–t), for unknown constants a and b, differentiating and setting t = 0 we can solve for a and b, and after some algebra and trigonometry obtain the zero-input response y (t ) =

 y′(0) e −ζωnt  2 ⋅ sin 1 − ζ 2 ω nt   y (0) ⋅ cos 1 − ζ ω nt − θ + 2 ωn 1−ζ  

(

2

)

(

)

(25.42)

where θ = arctan2(ζ/ 1 – ζ )with arctan2(·) being the arc tangent function that incorporates the sign of its argument. The form given in (25.42) allows for some useful observations. Remembering that this assumes ζ2 < 1, first note that if no damping occurs, that is, ζ = 0, then the natural frequencies are purely imaginary, s+ = jωn and s– = –s+, and the response is purely oscillatory, taking the form shown in the last line of Table 25.2. If the damping is positive, as it would be for a passive circuit having some loss, usually via positive resistors, then the natural frequencies lie in the left half s-plane, and y decays to zero at positive infinite time so that any transients in the circuit die out after a sufficient wait. The circuit is then called asymptotically stable. However, if the damping is negative, as it could be for some positive feedback circuits or those with negative resistance, then the response to nonzero initial conditions increases in amplitude without bound, although in an oscillatory manner, as time increases, and the circuit is said to be unstable. In the unstable case, as time decreases through negative time the amplitude also damps out to zero, but usually the responses backward in time are not of as much interest as those forward in time. © 2003 by CRC Press LLC

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For the zero-state response, the impulse response, h(t), is convoluted with the input, that is, y = h ∗ u, for which we can use the fact that h(t) is the inverse Laplace transform of H(s) = C[sl2 – A]–1B. The denominator of H(s) is det(sl2 – A) = s2 + 2ζωns + ω 2n , for which the causal inverse Laplace transform is  e s+t − e s−t 1(t )  e s+t 1(t ) ∗ e s−t 1(t ) =  s + − s − te s+t 1(t ) 

if s − ≠ s +

(25.43)

if s − = s +

Here, the bottom case is ruled out when only complex natural frequencies are considered, following the assumption of handling real natural frequencies in first-order circuits, made previously. Consequently, e s+t 1(t ) ∗ e s−t 1(t ) =

(

)

e s+t − e s−t e −ζωnt sin 1 − ζ 2ω nt ⋅1(t ) 1(t ) = 2 s+ − s− 1 − ζ ωn

(25.44)

Again, assuming ζ2 < 1 using the preceding calculations give the zero-state response as y (t ) =

1 d2

 e −ζωnt sin 1 − ζ 2 ω nt 1(t ) ∗  2  1 − ζ ω n

(

)

    d  d   n1 − 1 n2  δ′(t ) +  n0 − 0 n2  δ(t ) + n2δ(t ) * u(t ) d2  d2      =

1 d2

(25.45)

 e −ζωnt sin 1 − ζ 2 ω nt 1(t ) ∗  2  1 − ζ ω n

(

)

[n δ′′(t ) + n δ′(t ) + n δ(t )]} ∗ u(t ) 2

1

0

The bottom equivalent form is easily seen to result from writing the transfer function H(p) as the product of two terms 1/[d2(p2 + 2ζωn p + ω 2n ) and [n2 p2 + n1 p + n0] convoluting the causal impulse response (the inverse of the left half-plane converging Laplace transform), of each term. From (25.45), we directly read the impulse response to be h(t ) =

1 d2

 e −ζωnt sin 1 − ζ 2 ω nt 1(t )  2 ζ ω 1 −  n

(

)

(25.46)

]}

[

∗ n2δ′′(t ) + n1δ′(t ) + n0δ(t )

Equations (25.45) and (25.46) are readily evaluated further by noting that the convolution of a function with the second derivative of the impulse, the first derivative of the impulse, and the impulse itself is the second derivative of the function, the first derivative of the function, and the function itself, respectively. For example, in the low-pass case we find the impulse response to be, using (25.46), hlp (t ) =

n0 d2

e −ζωnt 1 − ζ2 ωn

(

)

sin 1 − ζ 2 ω nt 1(t )

(25.47)

By differentiating we find the bandpass and then high-pass impulse responses to be, respectively, © 2003 by CRC Press LLC

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hhp (t ) =

(

)

n1 e −ζωnt cos 1 − ζ 2 ω nt + θ 1(t ) d2 1 − ζ 2

(25.48)

 ω e −ζωnt n2  δ(t ) − n sin 1 − ζ 2 ω nt + 2θ 1(t ) d2   1 − ζ2  

(25.49)

hbp (t ) =

(

)

2

In both cases, the added phase angle is given, as in the zero input response, via θ = arctan2(ζ/ 1 – ζ ). By adding these last three impulse responses suitably scaled the impulse responses of the more general

second-order circuits are obtained.

Some comments on normalizations are worth mentioning in passing. Because d2 ≠ 0, one could assume d2 to be 1 by absorbing its actual value in the transfer function numerator coefficients. If ωn ≠ 0, time could also be scaled so that ωn = 1 could be taken, in which case a normalized time, tn, is introduced. Thus, t = ωn tn and, along with normalized time, comes a normalized differential operator pn = d[·]/dtn = d[·]/d(t/ωn ) = ωn p. This, in turn, leads to a normalized transfer function by substituting p = pn /ωn into H(p). Thus, much of the treatment could be carried out on the normalized transfer function x H n ( pn ) = H ( p) =

n2n pn2 + n1n pn + n0n pn2 + 2ζpn + 1

pn = ω n p

(25.50)

In this normalized form, it appears that the most important parameter in fixing the form of the response is the damping factor ζ = 1/(2Q).

Transient and Steady-State Responses Let us now excite the circuit with an eternal exponential input, u(t) = U exp(st) for –∞ < t < ∞ at the complex frequency s = σ + jω, where s is chosen as different from either of the natural frequencies, s± , and U is a constant. As with the first-order and, indeed, any higher-order, case the response is y(t) = Y(s) exp(st), as is observed by direct substitution into (25.32). This substitution yields directly Y (s ) =

1 d2

 n2s 2 + n1s + n0  ⋅U  2 2  s + 2ζω ns + ω n 

(25.51)

where y(t) = Y(s) exp(st) for u(t) = U exp(st) over –∞ < t < ∞. That is, an exponential excitation yields an exponential response at the same (complex) frequency s = σ + jω as that for the input, as long as s is not one of the two natural frequencies. (s may have positive as well as negative real parts and is best considered as a frequency and not as the Laplace transform variable because the latter is limited to regions of convergence.) Because the denominator polynomial of Y(s·) has roots which are the natural frequencies, the magnitude of Y becomes infinite as the frequency of the excitation approaches s+ or s– . Thus, the natural frequencies s+ and s– are also called poles of the transfer function. When σ = 0 the excitation and response are both sinusoidal and the resulting response is called the sinusoidal steady state (SSS). From (25.51), the SSS response is found by substituting the complex frequency s = jω into the transfer function, now evaluated on complex numbers rather than differential operators as above, H (s ) =

1 d2

 n2s 2 + n1s + n0   2 2  s + 2ζω ns + ω n 

(25.52)

Next, an exponential input is applied, which starts at t = 0 instead of at t = –∞; i.e., u(t) = U exp(st)1(t). Then, the output is found by using the convolution y = h ∗ u, which, from the discussion at (25.45), is expressed as © 2003 by CRC Press LLC

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y (t ) = h ∗ u =

[

]

1 s+t e 1(t ) ∗ e s−t 1(t ) ∗ n2δ" (t ) + n1δ' (t ) + n0δ(t ) ∗ e st 1(t ) d2

  N (s )  1 = H (s )Ue st 1(t ) +  + n2 (s + s + ) + n1  e s+t    d2 (s + − s − )  s + − s

(25.53)

 N (s )    − + n2 (s + s − ) + n1  e s−t 1(t )  s+ − s    in which N(s) is the numerator of the transfer function and we have assumed that s is not equal to a natural frequency. The second term on the right within the braces varies at the natural frequencies and as such is called the transient response, while the first term is the term resulting directly from an eternal exponential, but now with the negative time portion of the response removed. If the system is stable, the transient response decays to zero as time increases and, thus, if we wait long enough the transient response of a stable system can be ignored if the complex frequency of the input exponential has a real part that is greater than that of the natural frequencies. Such is the case for exponentials that yield sinusoids; in that case σ = 0, or s = jω. In other words, for an asymptotically stable circuit the output approaches that of the SSS when the input frequency is purely imaginary. If we were to excite at a natural frequency then the first part of (25.53) still could be evaluated using the time-multiplied exponential of (25.43); however, the transient and the steady state are now mixed, both being at the same “frequency.” Because actual sinusoidal signals are real, we use superposition and the fact that the real part of a complex signal is given by adding complex conjugate terms:

[ ]

cos(ωt ) = ℜ e jωt =

e jωt + e − jωt 2

(25.54)

This leads to the SSS response for an asymptotically stable circuit excited by u(t) = U cos (ωt)1(t) to be y (t ) =

H ( jω )Ue jωt + H (− jω )U *e − jωt 2

(

= H ( jω ) U cos ωt + ∠H ( jω ) + ∠U

)

(25.55)

Here, we assumed that the circuit has real-valued components such that H(– jω) is the complex conjugate of H(jω). In which case, the second term in the middle expression is the complex conjugate of the first.

Network Characterization Although the impulse response is useful for theoretical studies, it is difficult to observe it experimentally due to the impossibility of creating an impulse. However, the unit step response is readily measured, and from it the impulse response actually can be obtained by numerical differentiation if needed. However, it is more convenient to work directly with the unit step response and, consequently, practical charac­ terizations can be based upon it. The treatment most conveniently proceeds from the normalized lowpass transfer function

H ( p) =

1 , 0 < ζ t0, the behavior of the circuit is completely characterized by these variables. In view of the preceding, a definition for the state of a circuit can now be given. Definition: The state of a circuit at time t0 is the minimum amount of information at t0 that, along with the input to the circuit for t ≥ t0, uniquely determines the behavior of the circuit for t ≥ t0 . The concept of states is closely related to the order of complexity of the circuit. The order of complexity of a circuit is the minimum number of initial conditions which, along with the input, is sufficient to determine the future behavior of the circuit. Furthermore, if a circuit is described by an nth-order linear differential equation, it is well known that the general solution for t ≥ t0 contains n arbitrary constants which are determined by n initial conditions. This set of n initial conditions contains information concerning the circuit prior to t = t0 and constitutes the state of the circuit at t = t0. Thus, the order of complexity or the order of a circuit is the same as the order of the differential equation that describes the circuit, and it is also the same as the number of state variables that can be defined in a circuit. For an nth-order circuit, the state of the circuit at t = t0 consists of a set of n numbers that denotes a vector in an n-dimensional state space spanned by the n corresponding state variables. This key number n can simply be obtained by inspection of the circuit. Knowing the total number of energy storage elements, nLC , the total number of independent capacitive loops, nC , and the total number of independent inductive cutsets, nL , the order of complexity n of a circuit is given by n = nLC − nL − nC

(26.1)

A capacitive loop is defined as one that consists of only capacitors and possibly voltage sources while an inductive cutset represents a cutset that contains only inductors and possibly current sources. The following two examples illustrate the concept of states.

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R t = to vin

+ vC −

C

FIGURE 26.1 A simple RC circuit.

Example 1. Consider a simple RC-circuit in Fig. 26.1. The circuit equation is

RC

dv c (t ) + v c (t ) = v in dt

for

t ≥ t0

(26.2)

and the corresponding capacitor voltage is easily obtained as

[

]

v c (t ) = v c (t 0 ) − v in e

−

1 (t −t0 ) RC

+ v in

for

t ≥ t0

(26.3)

For this first-order circuit, it is clear from (26.3) the capacitor voltage for t ≥ t0 is uniquely determined by the initial condition vc(t0) and the input voltage vin for t ≥ t0. This is independent of the charging circuit for the capacitor prior to t0. Hence, vc (t0) is the state of the circuit at t = t0 and vc (t) is regarded as the state variable of the circuit. Example 2. As another illustration, consider the circuit of Fig. 26.2, which is a slight modification of the circuit considered in the previous example. The circuit equation and its corresponding solution are readily obtained as dvC1 (t ) dt

=−

1 1 v (t ) + v R(C1 + C 2 ) C1 R(C1 + C 2 ) in

(26.4)

and −1

( R C +C vC1 (t ) = vC1 (t 0 ) − v in e ( 1 2 )

(

)

t −t 0 )

+ v in for

t ≥ t0

(26.5)

respectively. Even though two energy storage elements exist, one can only arbitrarily specify one inde­ pendent initial condition. Once the initial condition on C1, vC1(t0), is specified, the initial voltage on C2 is automatically constrained by the loop equation vC2(t) = VC1(t) – E at t0. The circuit is thus still first order and only one state variable can be assigned for the circuit. It is clear from (26.5) that with the input vin , vC1(t0) is the minimum amount of information that is needed to uniquely determine the behavior of this circuit. Hence, vC1(t) is the state variable of the circuit. One can just as well analyze the circuit by solving a first-order differential equation in terms of vC2(t) with vC2(t0) defined as the state of the circuit at t = t0. The selection of state variables is thus not unique. In this example, either vC1(t) or vC2(t) can be defined as the state variable of the circuit. In fact, it is easily shown that any linear combination of vC1(t) and vC 2(t) can also be regarded as state variables. R

vin

E

C1

+ vC1 −

C2

+ vC2 −

FIGURE 26.2 The circuit for Example 2. © 2003 by CRC Press LLC

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26.2 State-Variable Formulation via Network Topology Various mathematical descriptions of circuits are available. Depending on the type of analysis used, different formulations of circuit equations may result. In the state variable formulation, a system of n first-order differential equations is written in the form x˙ = f (x, t )

(26.6)

where x is an n x 1 vector consisting of n state variables for an nth-order circuit and t represents the time variable. This set of equations is usually referred to as the state equation in normal form. When compared with other circuit descriptions, the state-variable representation is not necessarily the simplest. It does, however, simultaneously provide the solution of all state variables and hence yields the behavior of the entire circuit. The state equation is also particularly suitable for analysis by numerical techniques. Another distinct advantage of the state-variable approach is that it can be easily extended to nonlinear and/or time varying circuits. Example 3. Consider the linear circuit of Fig. 26.3. By inspection, the order of complexity of this circuit is three. Hence, three state variables are selected as x1 = vC1, x2 = vC2, and x3 = iL. Because the left-hand side of the normal form equation is the derivative of the state vector, it is necessary to express the voltage across the inductors and the currents through the capacitors in terms of the state variables and the input sources. The current through C1 can be obtained by writing a Kirchhoff ’s current law (KCL) equation at node 1 to yield dvC1

C1

= iR1 − iL

dt

=

(

)

1 v − v − iL R1 s C1

or dvC1 (t ) dt

=−

1 1 1 v − i + v R1C1 C1 C1 L R1C1 s

(26.7)

In a similar manner, applying KCL to node 2 gives

C2

dvC2 dt

= iL − iR3 + is = iL −

1 v +i R3 C2 s

or dvC2 (t ) dt 1

R1 iR1 vs

C1

L + vC1 −

© 2003 by CRC Press LLC

=−

+ v R2

(26.8)

2

R2 iL

1 1 1 v + i + i R3C 2 C2 C 2 L C 2 s

− C2

+ vC2 R3 −

iR3 is

FIGURE 26.3 The circuit for Example 3.

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The expression for the inductor voltage is derived by applying KVL to the mesh containing L, R2, C2, and C1 yielding L

diL = vC1 − vC2 − R2iL dt

or diL 1 R 1 = vC1 − vC2 − 2 iL dt L L L

(26.9)

Equations (26.7), (26.8), and (26.9) are the state equations that can be expressed in matrix form as  dvC1   1   − R C  dt   1 1  dvC2  =  0  dt    di   1  L   dt    L

−

1  C1   1  C2  R  − 2 L −

0 1 R3C 2 1 − L

 1 v c1   R1C1    v c  +  0  2  iL      0 

 0   1  C2   0  

v s    is 

(26.10)

Any number of branch voltages and/or currents may be chosen as output variables. If iR1 and vR2 are considered as outputs for this example, then the output equations, written as a linear combination of state variables and input sources become iR1 =

(

1 v −v R1 s C1

)

(26.11)

v R2 = R2iL

(26.12)

or in matrix form  1 iR1  −   =  R1  v R   2  0

0 0

 0  R2 

vC1  1   vC  +  R1   2  0 iL   

 0  0

v s    is 

(26.13)

In general, for an nth-order linear circuit with r input sources and m outputs, the state and output equations are represented by x˙ = Ax + Bu

(26.14)

y = Cx + Du

(26.15)

and

where x is an n × 1 state vector, u is an r × 1 vector representing the r input sources, m × 1-vector y denotes the m output variables, A, B, C, and D are of order n × n, n × r, m × n, and m × r, respectively. In the preceding example, the state equations are obtained by inspection for a simple circuit by writing voltage equations for inductors and current equations for capacitors and properly eliminating the nonstate variables. For more complicated circuits, a systematic procedure for eliminating the nonstate vari­ ables is desirable. Such a procedure can be generated with the aid of a proper tree. A proper tree is a tree obtained from the associated network graph that contains all capacitors, independent voltage sources, and possibly some resistive elements, but does not contain inductors and independent current sources. © 2003 by CRC Press LLC

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The selection of such a tree is always possible if the circuit contains no capacitive loops and no inductive cutsets. The reason for providing such a tree for writing state equations is obvious. With each tree branch, there is a unique cutset known as the fundamental cutset that contains only one tree branch and some links. Thus, if capacitors are in the tree, a fundamental cutset equation may be written for the corre­ sponding currents through the capacitors. Similarly, every link (together with some tree branches) forms a unique loop called a fundamental loop. If inductors are selected as links, inductor voltages may be obtained by writing the corresponding fundamental loop equations. With the selection of a proper tree, state variables can be defined as the capacitor tree-branch voltages and inductive link currents. In view of the above observation, a systematic procedure for writing state equations can now be stated as follows: STEP 1: From the associated directed graph, pick a proper tree. STEP 2: Write fundamental cutset equations for the capacitive tree branches and express the capacitor currents in terms of link currents. STEP 3: Write fundamental loop equations for the inductive links and express the inductor voltages in terms of tree-branch voltages. STEP 4: Define the state variables. Capacitive tree-branch voltages and inductive link currents are selected as state variables. Other quantities such as capacitor charges and inductor fluxes may also be used. STEP 5: Group the branch relations and the remaining fundamental equations according to their element types into three sets: resistor, inductor, and capacitor equations. Solve for the nonstate variables that appeared in the equations obtained in Steps 2 and 3 from the corresponding set of equations in terms of the state variables and independent sources. STEP 6: Substitute the result of Step 5 into the equations obtained in Steps 2 and 3, and rearrange them in normal form. Example 4. Consider again the same circuit in Fig. 26.3. The various steps outlined previously are used to write the state equations. STEP 1: The associated graph and the proper tree of the circuit are shown in Fig. 26.4. The tree branches include vs , C1, C2, and R2. STEP 2: The fundamental cutset associated with C1 consists of tree branch C1 and two links R1 and L. By writing the current equation for this cutset, the capacitor current ic1 is expressed in terms of link currents as iC1 = iR1 − iL

R1

L

C1

(26.16)

R2

C2

vs

FIGURE 26.4 The directed graph associated with the circuit of Fig. 26.3. © 2003 by CRC Press LLC

R3 is

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Similarly, the fundamental cutset {L, C2, R3, is} associated with C2 leads to iC2 = iL − iR3 + is

(26.17)

STEP 3: The fundamental loop associated with link L consists of L and tree branches R2, C2, and C1. By writing the voltage equation around this loop, the inductor voltage can be written in terms of tree-branch voltages as v L = vC1 − vC2 − v R2

(26.18)

STEP 4: The tree-branch capacitor voltages vC1 , VC2 ,and inductive link current iL are defined as the state variables of the circuit.

STEP 5: The branch relation and the remaining two fundamental loops for R1 and R2, and the fundamental

cutset equation for R2 are grouped into three sets.

Resistor equations: v R1 + vC1 − v s = 0

(26.19)

1 v R1 R1

(26.20)

iR2 − iL = 0

(26.21)

v R2 = R2iR2

(26.22)

v R3 − vC2 = 0

(26.23)

v R3 = R3iR3

(26.24)

iR1 =

Inductor equations: φ L = LiL or v L =

dφ L di =L L dt dt

(26.25)

q1 = C1vC1 or iC1 =

dvC1 dq1 = C1 dt dt

(26.26)

q2 = C 2vC2 or iC2 =

dvC2 dq2 = C2 dt dt

(26.27)

Capacitor equations:

The resistive link currents rR1, iR3, and resistive tree-branch voltage VR2 are solved from (26.19)–(26.24) in terms of the inductive link current iL, the capacitive tree-branch voltages vC1 and vC2, and sources as iR1 =

© 2003 by CRC Press LLC

(

1 v −v R1 s C1

)

(26.28)

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805

State-Variable Techniques

1 v R3 C2

(26.29)

v R2 = R2iL

(26.30)

iR3 = and

For this example, iL, vC1, and vC2 have already been defined as state variables. STEP 6: Substituting (26.28)–(26.30) into (26.16), (26.17), and (26.18) yields the desired state equation in matrix form:  dvC1   1   −  dt   R1C1  dvC2  =  0  dt    di    L   1 dt   L  

1  C1   1  C2  R  − 2 L −

0 −

1 R3C 2 1 − L

 1 vC1   R1C1    vC  +  0  2   iL   0    

 0   1  C2  0   

v s     is 

(26.31)

which, as expected, is the same as (26.10) obtained previously by inspection. As mentioned earlier, the selection of state variables is not unique. Instead of using capacitor voltages and inductor currents as state variables, basic quantities such as the capacitor charges and inductor fluxes may also be considered. If q1, q2, and φL are defined as state variables in Step 4, the inductive link current iL and capacitive tree-branch voltages, vC1 and vC2, can be solved from the inductor and capacitor equations in terms of state variables and possibly sources in Step 5 as iL =

1 φ L L

(26.32)

vC1 =

1 q C1 1

(26.33)

vC2 =

1 q C2 2

(26.34)

Finally, state equations are obtained by substituting Eqs. (26.28)–(26.30) and (26.32)–(26.34) into (26.16)–(26.18) as  dq1  − 1  dt   R1C1  dq    2= 0  dt    dφ L   1  dt    C1

0 1 R3C 2 1 − C2

−

1   L  1  L   R − 2 L  −

1  q1      R1  q2  +  0    Φ L   0   

 0  1  0 

v s     is 

(26.35)

In the systematic procedure outlined previously, it is assumed that the network exists with neither inductive cutsets nor capacitive loops so that the selection of proper tree is always guaranteed. For networks that do have these constraints, it is not possible to include all the capacitors in a tree without forming a closed path. Also, in order for a tree to contain all the nodes, some inductors will have to be included in a

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tree. A tree that includes independent voltage sources, some resistors, and a maximum number of capacitors but no independent current sources is called a modified proper tree. In writing a state equation for such networks, the same systematic procedure can be applied with the selection of a modified proper tree. However, if capacitor tree-branch voltages and inductive link currents are defined as the state variables, the standard (A, B, C, D) description (26.14) and (26.15) may not exist. In fact, if inductive cutsets contain independent current sources and/or capacitive loops contain independent voltage sources, the derivative of these sources will appear in the state equation and the general equation is of the form x˙ = Ax + B1u + B 2u˙

(26.36)

where B1 and B2 are n × r matrices and A, x, and u are defined as before. To recast (26.36) into the standard form, it is necessary to redefine. z = x − B 2u

(26.37)

as new state variables. Substituting (26.37) into (26.36), yields z˙ = Az + Bu

(26.38)

B = B1 + AB 2

(26.39)

where

It is noted from (26.37), the new state variables represent a linear combination of sources and capacitor voltages or inductor currents which, except for the mathematical convenience, may not have sound physical significance. To avoid such state variables and transformation (26.37), Step 4 of the systematic procedure described earlier needs to be modified. By defining state variables as the algebraic sum of capacitor charges in the fundamental cutset associated with each of the capacitor tree branches, and the algebraic sum of inductor fluxes in the fundamental loop associated with each of the inductive links, the resulting state equation will be in the standard form. The preceding generalizations are illustrated by the following two examples. Example 5. As a simple illustration, consider the same circuits given in Fig. 26.2, where the constant DC voltage source E is replaced by a time-varying source e(t). It can easily be demonstrated that the equation describing the circuit now becomes dvC1 (t ) dt

=−

de(t ) C2 1 1 vC1 + v in (t ) + R(C1 + C 2 ) R(C1 + C 2 ) R(C1 + C 2 ) dt

(26.40)

The preceding equation is the same as the state Eq. (26.4) with the exception of an additional term involving the first-order derivative of source e(t). Equation (26.40) is clearly not the standard state equation described in (26.41) with capacitor voltage vC1 defined as the state variable. Example 6. As another illustration, consider the circuit shown in Fig. 26.5 which consists of an inductive cutset {L1, L2, is} and a capacitive loop (C1, vs 2, C2). The state equations are determined from the systematic procedure by first using the transformation (26.37) and then by defining the algebraic sum of charges and fluxes as state variables. STEP 1: The directed graph of the circuit is shown in Fig. 26.6 where branches denoted by vs1, vs2, C1, R2, and L2 are selected to form a modified proper tree.

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vs2 + −

iL1 R1 vs1

iR1 + −

C1

L1 iC1 L2 R2

is iL2 C 2

iC2

R3

iR3

iR2

FIGURE 26.5 A circuit with a capacitive loop and an inductive cutset.

vs2 R1

L1

is L2

C1 vs1

C2

R3

R2

FIGURE 26.6 The directed graph associated with the circuit of Fig. 26.5.

STEP 2: The fundamental cutset associated with C1 consists of branches R1, C1, L1, is, C2, and R3. Applying KCL to this cutset yields iC1 = −iR1 − iL1 − is − iC2 − iR3

(26.41)

STEP 3: The fundamental loop equation associated with the inductive link L1 is given by v L1 = vC1 + v L2 − v R2

(26.42)

where the link voltage vL1 has been expressed in terms of tree-branch voltages. STEP 4: In the first illustration, the tree-branch capacitor voltage vC1 and the inductive link current iL1 are defined as the state variables.

STEP 5: The branch relation and the remaining two fundamental equations are grouped into the following

three sets: Resistor equations:

© 2003 by CRC Press LLC

v R1 + v s1 − vC1 = 0

(26.43)

v R1 = R1iR1

(26.44)

iR 2 − iL1 − is = 0

(26.45)

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v R2 = R2iR 2

(26.46)

v R3 − vC1 + v s2 = 0

(26.47)

v R3 = R3iR 3

(26.48)

iL2 + iL1 + is = 0

(26.49)

Inductor equations:

diL1

φ L1 = L1iL1 or v L1 = L1

dt diL2

φ L2 = L2iL2 or v L2 = L2

dt

(26.50)

(26.51)

Capacitor equations: vC2 − vC1 + v s2 = 0 q1 = C1vC1 or iC1 = C1

(26.52) dvC1

q2 = C 2vC2 or iC2 = C 2

dt dvC2 dt

(26.53)

(26.54)

For this example, the nonstate variables are identified as iR1, vR2, iR3, vL2, and iC2, from (26.41) and (26.42). These variables are now solved from the corresponding group of equations in terms of state variables and independent sources: iR1 =

(

)

(26.55)

(

)

(26.56)

(

)

(26.57)

dis dt

(26.58)

1 v −v R1 C1 s1

v R2 = R2 iL1 + is iR3 =

1 v −v R3 C1 s2

v L2 = −L2

iC2 = C 2

diL1 dt

dvC1 dt

− L2

− C2

dv s2 dt

(26.59)

STEP 6: Assuming the existence of the first-order derivatives of sources with respect to time and substi­ tuting eqs. (26.50), (26.53), and (26.55)–(26.59) into (26.41) and (26.42) yields

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809

State-Variable Techniques

R1 + R3  dvC1  − R R C + C   ( 2)  dt  =  1 3 1 di 1  L  1   dt  L1 + L2  1   R (C + C ) 2 + 1 1  0    0 + 0  

1  C1 + C 2   R2  − L1 + L2 

−

 v s  1   s2 R2    − L1 + L2   is 

1 R3 (C1 + C 2 )

−

0

 0   L2  − L1 + L2 

C2 (C1 + C2 ) 0

vC1     iL   1 1

(C1 + C2 )  v

(26.60)

 dv s1     dt   dv s2   dt   di   s   dt 

Clearly, Eq. (26.60) is not in the standard form. Applying transformation (26.37) with x1 = vc1, x1 = iL2, u1 = vs1, u2 = vs2, and u3 = is gives the state equation in normal form R1 + R2   dz1  − R R C + C  dt  1 3( 1 2)  dz  =  1   2   dt  L1 + L2  1  R C +C ( 1 1 2) +   0  

1  C1 + C 2   R2  − L1 + L2 

−

R1C1 − R3C 2

z1    z 2 



R1R3 (C1 + C 2 ) C2 (L1 + L2 )(C1 + C2 ) 2

−

L1



R2 L1

  

(L1 + L2 )(C1 + C2 )  −

(L1 + L2 )

2

(26.61)

v s1    × v s2 

 

 is 

  where new state variables are defined as   z1  vC1 z=  =  z 2   i  L1 

C2  v C1 + C 2 s2   L2 + is  L1 + L2 

−

(26.62)

Alternatively, if the state variables are defined in Step 4 as

© 2003 by CRC Press LLC

qa = q1 + q2

(26.63)

φb = φ1 φ 2

(26.64)

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then Eqs. (26.41) and (26.42) become dqa dq1 dq2 = + = −iR1 − iL1 − is − iR3 dt dt dt

(26.65)

dφb dφ1 dφ 2 = − = −v L1 − v L2 = vC1 − v R2 dt dt dt

(26.66)

respectively. In Step 5, the resistive link currents iR1, iR3, and the resistive tree-branch voltage VR2 are solved from resistive eqs. (26.43)–(26.48) in terms of inductive link currents, capacitive tree-branch voltages, and independent sources. The results are those given in (26.55)–(26.57). By solving the inductor Eqs. (26.49), (26.50), and (26.64), inductive link current iL1 is expressed as a function of state variables and independent sources: iL1 =

1 (φ − L2is ) L1 + L2 b

(26.67)

Similarly, solving vC1 from capacitor Eqs. (26.52)–(26.54), and (26.63), yields the capacitor tree-branch voltage vC1 =

(

1 q + C 2v s2 C1 + C 2 a

)

(26.68)

Finally, in Step 6, Eqs. (26.55)–(26.57), (26.67), and (26.68) are substituted into (26.65) and (26.66) to form the state equation in normal form: R1 + R3  dqa  −  dt   R1R3 (C 1 +C 2 )  dφ  =  1  b   dt   C1 + C 2 

1 1   L1 + L 2  qa   R1  + R2  φ    b  0 − L1 + L 2   −

R1C 1 − R3C 2 R1R3 (C 1 +C 2 ) C2 (C1 + C 2 )

L1  v  s1 (L1 + L 2 )  v  (26.69) R2 L1   s 2  − (L1 + L 2 )   is  −

26.3 Natural Response and State Transition Matrix In the preceding section, the state-variable description has been presented for linear time-invariant circuits. The response of the circuit depends on the solution of the state equation. The behavior of the circuit due to any arbitrary input sources can easily be obtained once the zero-input response or the natural response of the circuit is known. In order to find its natural response, the homogeneous state equation of the circuit. x˙ = Ax

(26.70)

is considered, where independent source term u(t) has been set equal to zero. The preceding state equation is analogous to the scalar equation x˙ = ax

(26.71)

x (t ) = e at x (0)

(26.72)

where the solution is given by

for any arbitrary initial condition x(0) given at t = 0, or © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 811 Sunday, October 27, 2002 8:45 PM

811

State-Variable Techniques a t −t x (t ) = e ( 0 ) x (t 0 )

(26.73)

if the initial time is specified at t = t0. It is thus reasonable to assume a solution for (26.70) of the form x(t ) = e (

t −t 0 ) λ

(26.74)

p

where λ is a scalar constant and p is a constant n-vector. Substituting (26.74) into (26.70) leads to Ap = λp

(26.75)

Therefore, (26.74) is a solution of (26.70) precisely when p is an eigenvector of A associated with the eigenvalue λ. For simplicity, it is assumed that A has n distinct eigenvalues λ1, λ2, …, λn. Because the corresponding eigenvectors denoted by p1, p2, …, pn are linearly independent, the general solution of (26.70) can be uniquely written as a linear combination of n distinct normal modes of the form (26.74): x(t ) = c1e (

t −t o ) λ1

p1 + c 2e (

t −t 0 ) λ 2

p2 +L+ c ne (

t −t 0 ) λ n

pn

(26.76)

where c1, c2, …, cn are n arbitrary constants determined by the given initial conditions. Specifically, x(t 0 ) = c1p1 + c 2p2 +L+ c npn

(26.77)

The general solution (26.76) can also be written in the form x (t ) = e (

t −t o ) A

x (t 0 )

(26.78)

where the exponential function of a matrix is defined by a power series: e(

t −t o ) A

= I + (t − t 0 ) A + ∞

=

∑ k=0

(t − t 0 )

(t − t 0 ) 2!

2

A 2 +L (26.79)

k

k!

Ak

In fact, taking the derivative of (26.78) with respect to t yields dx d = dt dt

2  (t − t 0 ) A 2 +Lx(t ) I + (t − t 0 )A + 0 2!    

2  (t − t 0 ) A3 +Lx(t ) = A + (t − t 0 )A 2 + 0 2!     2   t − t0 ) 2 ( A +Lx(t 0 ) = A I + (t − t 0 )A + 2!    

= Ae (

t −t 0 ) A

Also, at t = t0, (26.78) gives © 2003 by CRC Press LLC

x(t 0 ) = Ax(t )

(26.80)

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x(t 0 ) = Ix(t 0 ) = x(t 0 )

(26.81)

Thus, expression (26.78) satisfies both eq. (26.70) and the initial conditions and hence is the unique solution. The matrix e(t–t0)A, usually denoted by (t – t0), is called the state transition matrix or the fundamental matrix of the circuit described by (26.70). The transition of the initial state x(t0) to the state x(t) at any time t is thus governed by x(t ) = (t − t 0 ) x(t 0 )

(26.82)

where Φ(t − t 0 ) = e (

t −t 0 ) Α

(26.83)

is an n × n matrix with the following properties: Φ(t 0 − t 0 ) = Φ(0) = I

(26.84)

Φ(t + τ) = Φ(t )Φ(τ)

(26.85)

Φ(t 2 − t1 ) Φ(t1 − t 0 ) = Φ(t 2 − t 0 )

(26.86)

Φ(t 2 − t1 ) = Φ −1 (t1 − t 2 )

(26.87)

Φ −1 (t ) = Φ(−t )

(26.88)

Once the state transition matrix is known, the solution of the state equation can be obtained from (26.82). In general, it is rather difficult to obtain a closed-form solution from the infinite series representation of the state transition matrix. The formula given by (26.79) is useful only if numerical solution by digital computer is desired. Several methods are available for finding a closed form expression for (t – t0). The relationship between solution (26.76) and the state transition matrix is first established. For simplicity, let t0 = 0. According to (26.82), the first column of (t) is the solution of the state equation generated by the initial condition 1   0   x(0) = x(1) (0) = 0   M    0  

(26.89)

Indeed, if (26.89) is substituted into (26.82), then

φ11  φ 21 ∆ (1) 1) ( x(t ) = x (t ) = (t )x (0) =   M  φ  n1

© 2003 by CRC Press LLC

φ12

L

φ 22

L

M

M

φn2

L

φ1n   φ 2n   M   φnn 

1   φ11  0     φ 21  0 =      M  M      φ  0  n1   

(26.90)

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State-Variable Techniques

which can be computed from (26.76) and the arbitrary constants ci =∆ ci(1) for i = 1, 2, …, n are solved from (26.77). The first column of the state transition matrix is thus given by φ11    φ 21    = c1(1)e λ1t p1 + c 2(1)e λ2t p 2 + L + c n(1)e λnt p n M    φ   n1 

(26.91)

0   1    x(0) = x( 2) (0) = 0   M    0  

(26.92)

Instead of (26.89), if

is used, the arbitrary constants c1, c2, …, cn denoted by c1(2), c2(2), … cn(2) are solved. Then, the second column of (t) is given  φ12    φ 22    = c1( 2)e λ1t p1 + c 2( 2)e λ2t p 2 +L+ c n( 2)e λnt p n  M    φ   n2 

(26.93)

In a similar manner, the remaining columns of (t) are determined. The closed form expression for state transition matrix can also be obtained by means of a similarity transformation of the form AP = PJ or J = P −1AP

(26.94)

where P is a nonsingular matrix. If the eigenvalues of A, λ1, λ2, …, λn , are assumed to be distinct, J is a diagonal matrix with eigenvalues on its main diagonal: λ1  0 J= M  0 

0

L

λ2

L

M

O

0

L

0  0  M  λ n 

(26.95)

and

[

P = p1 p2 L pn

© 2003 by CRC Press LLC

]

(26.96)

0912 S1-S8 Frame55.book Page 814 Sunday, October 27, 2002 8:45 PM

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where pi’s, for i = 1,2,… n, are the corresponding eigenvectors associated with the eigenvalue λi , for i = 1,2,….,n. Substituting (26.94) into (26.83), the state transition matrix can now be written in the closed form Φ(t − t 0 ) = e (

t −t 0 ) Α

= Pe (

= e(

t −t 0 )PJP−1

t −t 0 ) J

(26.97)

P −1

where e (t −to )λ1   0 t − t J e( o ) =   M    0

L

0 e(

t −t o ) λ 2

L

M

O

0

L

  0   M  t −t λ  e( o ) n  0

(26.98)

is a diagonal matrix. In the more general case, where the A matrix has repeated eigenvalues, a diagonal matrix of the form (26.95) may not exist. However, it can be shown that any square matrix A can be transformed by a similarity transformation to the Jordan canonical form J1  0 J= M  0 

0

L

J2

L

M

O

0

L

0  0  M  J l 

(26.99)

where Ji’s, for i = 1, 2,…, l are known as Jordan blocks. Assuming that A has m distinct eigenvalues, λi , with multiplicity ri , for i = 1, 2, …, m, and r1 + r2 + ⋅ ⋅ ⋅+ rm = n. Associated with each λi there may exist several Jordan blocks. A Jordon block is a block diagonal matrix of order k × k(k ≤ ri ) with λi on its main diagonal, all 1’s on the superdiagonal, and zeros elsewhere. In the special case when k = 1, the Jordan block reduces to a 1 × 1 scalar block with only one element λi. In fact, the number of Jordan blocks associated with the eigenvalue λi is equal to the dimension of the null space of (λi I – A). For each k × k Jordan block J(k) associated with the eigenvalue λi of the form λ i  0 J (k ) =  M  0 

1

0

0

L

λi

1

0

L

M

M

M

O

0

0

0

L

0   0   1   λ i 

(26.100)

the exponential function of J(k) takes the form  1   t −t 0 ) J ( k ) ( e = 0  M  0 © 2003 by CRC Press LLC

t

t2 2!

L

1

t

L

M

M

O

0

0

L

t k −1  (k − 1)!  t k−2  (t −t )λ 0 i (k − 2)! e M   1 

(26.101)

0912 S1-S8 Frame55.book Page 815 Sunday, October 27, 2002 8:45 PM

815

State-Variable Techniques

and the corresponding k columns of P, known as the generalized eigenvectors, satisfy the equations

(λ iI − A)pi(1) = 0 (λ iI − A)pi( 2) = −pi(1)

(26.102)

M

(λ iI − A)pi(k) = −pi(k−1) The closed form expression (t – t0) for this general case now becomes Φ(t − t 0 ) = Pe (

t −t 0 ) J

P −1

(26.103)

where e (t −t0 ) J1   0 t −t J e( 0 ) =   M    0

  0   M  t −t J  e( 0 ) l 

L

0 e(

t −t 0 ) J 2

0

L

M

O

0

L

(26.104)

and each of the e(t–t0)Ji, for i = 1, 2, …, l, is of the form given in (26.101). The third approach for obtaining closed form expression for the state transition matrix involves the Laplace transform technique. Taking the Laplace transform of (26.70) yields sX(s) – x(0) = AX(s) or X(s) = (sI – A)–1 x(0)

(26.105)

where (sI – A)–1 is known as the resolvent matrix. The time response

[

]

x(t ) = + −1 (sI − A ) x(0) −1

(26.106)

is obtained by taking the inverse Laplace transform of (26.105). It is observed by comparing (26.106) to (26.82) and (26.83) with t0 = 0 that

[

Φ(t ) = e tΑΑ =  −1 (sΙΙ − Α)

−1

]

(26.107)

By way of illustration, the following example is considered. The state transition matrix is obtained by using each of the three approaches presented previously. Example 7. Consider the parallel RLC circuit in Fig. 26.7. The state equation of the circuit is obtained as  di L    dt   0  dv  =  1  C  −   C  dt 

© 2003 by CRC Press LLC

1 

i   0 

L   L  +  1 i 1  v    s   C  C 

− RC 

(26.108)

0912 S1-S8 Frame55.book Page 816 Sunday, October 27, 2002 8:45 PM

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FIGURE 26.7 A parallel RLC circuit.

With R = 2/3 Ω, L = 1 H, and C = 1/2 F, the A matrix becomes

 0 A= −2

1  −3

(26.109)

(a) Normal Mode Approach: The eigenvalues and the corresponding eigenvectors of the A are found to be λ1 = –1

λ2 = –2

(26.110)

and 1 1 p1 =   , p2 =   −1 −2

(26.111)

Therefore, the natural response of the circuit is given as a linear combination of the two distinct normal modes as  iL (t )  1 1   = c1e −t   + c 2e −2t   vC (t ) −1 −2  

(26.112)

When evaluated at t = 0, (26.112) becomes  iL (0)   c1 + c 2   =  vC (0) −c1 − 2c 2   

(26.113)

In order to find the first column of (t), it is assumed that  iL (0)  1  =  vC (0) 0  

(26.114)

With this initial condition, the solution of (26.113) becomes c1 ∆ c1( ) = 2 and c 2 ∆ c 2( ) = −1 1

1

(26.115)

Substituting (26.115) into (26.112) results in the first column of (t):  φ11   2e −t − e −2t    = φ 21  −2e −t + 2e −2t  © 2003 by CRC Press LLC

(26.116)

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State-Variable Techniques

Similarly, for  iL (0)  0  =   vC (0) 1  

(26.117)

constants c1 and c2 are solved from (26.113) to give c1 = c 2( 2) = 1 and c 2 = c 2( 2) = −1

(26.118)

φ12   e −t − e −2t    = φ 22  −e −t + 2e −2t   

(26.119)

∆

∆

The second column of (t):

is obtained by substituting (26.118) into (26.112). Combining (26.116) and (26.119) yields the state transition matrix in closed form  2e −t − e −2t Φ(t ) =  −2e −t + 2e −2t

e −t − e −2t   −e −t + 2e −2t 

(26.120)

(b) Similarity Transformation Method: The eigenvalues are distinct, so the nonsingular transformation P is constructed from (26.96) by the eigenvectors of A:

[

P = p1

1

2

1  −2

] = 

−1

(26.121)

with 2 P −1 =  −1

1  −1

(26.122)

Substituting λ1, λ2, and P into (26.97) and (26.98) yields the desired state transition matrix 1 Φ(t ) = Pe tJ P −1 =  −1  2e −t − e −2t = −2e −t + 2e −2t

1  −2

e −t   0

0   e −2t 

2  −1

1  −1

(26.123)

e −t − e −2t   −e −t + 2e −2t 

which is in agreement with (26.120). (c) Laplace Transform Technique: The state transition matrix can also be computed in the frequency domain from (26.107). The resolvent matrix is

(sI − A)

−1

s =  2

−1   s + 3

−1

s +3   (s +1)(s + 2) =  −2   (s + 1)(s + 2)  © 2003 by CRC Press LLC

 (s +1)(s + 2)  s  (s + 1)(s + 2)  1

(26.124)

0912 ch26(818) frame55 Page 818 Monday, October 28, 2002 10:47 AM

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The Circuits and Filters Handbook, Second Edition

1  2  s +1 − s + 2 =  2 2  +  s +1 s + 2

1 1  − s +1 s + 2  1 2   − + s +1 s + 2

where partial-fraction expansion has been applied. Taking the inverse Laplace transform of (26.124) yields the same closed form expression as given previously in (26.120) for (t).

26.4 Complete Response When independent sources are present in the circuit, the complete response depends on the initial states of the circuits as well as the input sources. It is well known that the complete response is the sum of the zero-input (or natural) response and the zero-state (or forced) response and satisfies the nonhomoge­ neous state equation x˙ (t ) = Ax(t ) + Bu(t )

(26.125)

subject to the given initial condition x(t0) = x0. Equation (26.125) is again analogous to the scalar equation x˙ (t ) = ax (t ) + bu(t )

(26.126)

which has the unique solution of the form x (t ) = e (

t −t 0 )a

x (t 0 ) +

t

∫t e

()

(t −τ )abu τ dτ

0

(26.127)

It is thus assumed that the solution to the state equation is given by x(t ) = e (

t −t 0 ) A

t

x(t 0 ) +

∫t e

()

(t −τ ) A Bu τ dτ

0

= (t − t 0 )x(t 0 ) +

(26.128)

t

∫t

0

(t − τ)Bu(τ)dτ

Indeed, one can show by direct substitution that (26.128) satisfies the state Eq. (26.125). Differentiating both sides of (26.128) with respect to t yields d d x˙ (t ) = (t − t 0 )x(t 0 ) + dt dt t

t

∫t (t − τ)Bu(τ)dτ 0

= A(t − t 0 )x(t 0 ) +

∫t

= A(t − t 0 )x(t 0 ) +

∫t A(t − τ)Bu(τ)dτ + Bu(t )

 = A (t − t 0 )x(t 0 ) + 

0

d (t − τ)Bu(τ)dτ + (t − t )Bu(t ) dt

t

(26.129)

0



t

∫t (t − τ)Bu(τ)dτ + Bu(t ) 0

= Ax(t ) + Bu(t ) Also, at t = t0, (26.128) becomes x(t 0 ) = (t 0 − t 0 )x(t 0 ) + = Ix(t 0 ) + 0 = x(t 0 ) © 2003 by CRC Press LLC

t0

∫t (t 0

0

− τ)Bu(τ)dτ

(26.130)

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The assumed solution (26.128) thus satisfies both the state Eq. (26.125) and the given initial condition. Hence, x(t) as given by (26.128) is the unique solution. It is observed from (26.128) that if u(t) is set to zero, the solution reduces to the zero-input response or the natural response given in (26.82). On the other hand, if the original circuit is relaxed, i.e., x(t0) = 0, the solution represented by the convolution integral, the second term on the right-hand side of (26.128), is the forced response on the zero-state response. Thus, Eq. (26.128) verifies the fact that the complete response is the sum of the zero-input response and the zero-state response. The previous result is illustrated by means of the following example. Example 8. Consider again the same circuit given in Example 7, where the input current source is assumed to be a unit step function applied to the circuit at t = 0. The state equation of the circuit is found from (26.108) to be  diL   dt   0  dv  =   C  −2  dt 

1  iL  0   +  is (t ) −3 vC  2

(26.131)

where the state transition matrix (t) is given in (26.120). The zero-state response for t > 0 is obtained by evaluating the convolution integral indicated in (26.128): − (t − τ ) − e −2(t − τ ) t  2e Φ(t − τ)Βu(τ)dτ =  − (t − τ ) 0 0 + 2e −2(t τ ) −2e

∫

t

∫

e − (t −τ ) − e −2(t −τ )   −e − (t − τ ) + 2e −2(t τ ) 

0   dτ 2

e − (t − τ ) − e −2(t −τ )    dτ =2 −2(t τ )  0  − (t − τ ) −e + 2e  

∫

t

(26.132)

1 − 2e −t + e −2t   =   2e −t − 2e −2t  By adding the zero-input response represented by (t)x(0) to (26.132), the complete response for any given initial condition x(0) becomes  iL (t )   2e −t − e −2t  = vC (t ) −2e −t + 2e −2t   

e −t − e −2t  iL (0)  1 − 2e −t + 2e −2t  +   −t −2t    v 0 e e 2 2 −e −t + 2e −2t  − ( )  C   

(26.133)

for t > 0.

References [1] T. C. Chen, Linear System Theory and Design, New York: Holt, Rinehart & Winston, 1970. [2] W. K. Chen, Linear Networks and Systems, Monterey, CA: Brooks/Cole Engineering Division, 1983. [3] L. O. Chua and P. M. Lin, Computer-Aided Analysis of Electronics Circuits: Algorithms and Compu­ tational Techniques, Englewood Cliffs, NJ: Prentice Hall, 1969. [4] P. M. DeRusso, R. J. Roy, and C. M. Close, State Variables for Engineers, New York: John Wiley & Sons, 1965. [5] C. A. Desoer and E. S. Kuh, Basic Circuit Theory, New York: McGraw-Hill, 1969. [6] B. C. Kuo, Linear Networks and Systems, New York: McGraw-Hill, 1967. [7] K. Ogata, State Space Analysis of Control Systems, Englewood Cliffs, NJ: Prentice Hall, 1967.

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[8] R. A. Rohrer, Circuit Theroy: An Introduction to the State Variable Approach, New York: McGrawHill, 1970. [9] D. G. Schultz and J. L. Melsa, State Functions and Linear Control Systems, New York: McGraw-Hill, 1967. [10] T. E. Stern, Theory of Nonlinear Networks and Systems: An Introduction, Reading MA: AddisonWesley, 1965. [11] L. K. Timothy and B. E. Bona, State Space Analysis: An Introduction, New York: McGraw Hill, 1968. [12] L. A. Zadeh and C. A. Desoer, Linear System Theory, New York: McGraw-Hill, 1963.

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IV

Feedback Circuits Wai-Kai Chen University of Illinois 27 Feedback Amplifier Theory John Choma, Jr. Introduction • Methods of Analysis • Signal Flow Analysis • Global Single-Loop Feedback • Pole Splitting Open-Loop Compensation • Summary

28 Feedback Amplifier Configurations John Choma, Jr. Introduction • Series-Shunt Feedback Amplifier • Shunt-Series Feedback Amplifier • ShuntShunt Feedback Amplifier • Series-Series Feedback Amplifier • Dual-Loop Feedback • Summary

29 General Feedback Theory Wai-Kai Chen Introduction • The Indefinite-Admittance Matrix • The Return Difference • The Null Return Difference

30 The Network Functions and Feedback Wai-Kai Chen Blackman’s Formula • The Sensitivity Function

31 Measurement of Return Difference Wai-Kai Chen Blecher’s Procedure • Impedence Measurements

32 Multiple-Loop Feedback Amplifiers Wai-Kai Chen Multiple-Loop Feedback Amplifier Theory • The Return Difference Matrix • The Null Return Difference Matrix • The Transfer-Function Matrix and Feedback • The Sensitivity Matrix • Multiparameter Sensitivity

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27 Feedback Amplifier Theory 27.1 27.2 27.3 27.4

Introduction Methods of Analysis Signal Flow Analysis Global Single-Loop Feedback Driving-Point I/O Resistance • Dimished Closed-Loop Damping Factor • Frequency Invariant Feedback Factor • Frequency Variant Feedback Factor (Compensation)

27.5 Pole Splitting Open-Loop Compensation

John Choma, Jr. University of Southern California

The Open-Loop Amplifier • Pole Splitting Analysis

27.6 Summary

27.1 Introduction Feedback, whether intentional or parasitic, is pervasive of all electronic circuits and systems. In general, feedback is comprised of a subcircuit that allows a fraction of the output signal of an overall network to modify the effective input signal in such a way as to produce a circuit response that can differ substantially from the response produced in the absence of such feedback. If the magnitude and relative phase angle of the fed back signal decreases the magnitude of the signal applied to the input port of an amplifier, the feedback is said to be negative or degenerative. On the other hand, positive (or regenerative) feedback, which gives rise to oscillatory circuit responses, is the upshot of a feedback signal that increases the magnitude of the effective input signal. Because negative feedback produces stable circuit responses, the majority of all intentional feedback architectures is degenerative [1], [2]. However, parasitic feedback incurred by the energy storage elements associated with circuit layout, circuit packaging, and secondorder high-frequency device phenomena often degrades an otherwise degenerative feedback circuit into either a potentially regenerative or severely underdamped network. Intentional degenerative feedback applied around an analog network produces four circuit perfor­ mance benefits. First, negative feedback desensitizes the gain of an open-loop amplifier (an amplifier implemented without feedback) with respect to variations in circuit element and active device model parameters. This desensitization property is crucial in view of parametric uncertainties caused by aging phenomena, temperature variations, biasing perturbations, and nonzero fabrication and manufacturing tolerances. Second, and principally because of the foregoing desensitization property, degenerative feed­ back reduces the dependence of circuit responses on the parameters of inherently nonlinear active devices, thereby reducing the total harmonic distortion evidenced in open loops. Third, negative feedback broadbands the dominant pole of an open-loop amplifier, thereby affording at least the possibility of a closedloop network with improved high-frequency performance. Finally, by modifying the driving-point input and output impedances of the open-loop circuit, negative feedback provides a convenient vehicle for implementing voltage buffers, current buffers, and matched interstage impedances.

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The disadvantages of negative feedback include gain attenuation, a closed-loop configuration that is disposed to potential instability, and, in the absence of suitable frequency compensation, a reduction in the open-loop gain-bandwidth product. In uncompensated feedback networks, open-loop amplifier gains are reduced in almost direct proportion to the amount by which closed-loop amplifier gains are desen­ sitized with respect to open-loop gains. Although the 3-dB bandwidth of the open-loop circuit is increased by a factor comparable to that by which the open-loop gain is decreased, the closed-loop gain-bandwidth product resulting from uncompensated degenerative feedback is never greater than that of the open-loop configuration [3]. Finally, if feedback is incorporated around an open-loop amplifier that does not have a dominant pole [4], complex conjugate closed-loop poles yielding nonmonotonic frequency responses are likely. Even positive feedback is possible if substantive negative feedback is applied around an openloop amplifier for which more than two poles significantly influence its frequency response. Although the foregoing detail is common knowledge deriving from Bode’s pathfinding disclosures [5], most circuit designers remain uncomfortable with analytical procedures for estimating the frequency responses, I/O impedances, and other performance indices of practical feedback circuits. The purposes of this section are to formulate systematic feedback circuit analysis procedures and ultimately, to dem­ onstrate their applicability to six specific types of commonly used feedback architectures. Four of these feedback types, the series-shunt, shunt-series, shunt-shunt, and series-series configurations, are singleloop architectures, while the remaining two types are the series-series/shunt-shunt and seriesshunt/shunt-series dual-loop configurations.

27.2 Methods of Analysis Several standard techniques are used for analyzing linear feedback circuits [6]. The most straightforward of these entails writing the Kirchhoff equilibrium equations for the small-signal model of the entire feedback system. This analytical tack presumably leads to the idealized feedback circuit block diagram abstracted in Fig. 27.1. In this model, the circuit voltage or current response, XR , is related to the source current or voltage excitation, XS , by ∆

Gcl =

XR Go G = ≡ o X S 1+ f Go 1+ T

(27.1)

where Gcl is the closed-loop gain of the feedback circuit, the feedback factor ƒ is the proportion of circuit response fed back for antiphase superposition with the source signal, and Go represents the open-loop gain. The product ƒGo is termed the loop gain T. Equation (27.1) demonstrates that, for loop gains with magnitudes that are much larger than one, the closed-loop gain collapses to 1/ƒ, which is independent of the open-loop gain. To the extent that the

+ XS

OPEN LOOP AMPLIFIER

(Go)

FEEDBACK FACTOR

(f )

−

Feedback Amplifier

FIGURE 27.1 Block diagram model of a feedback network. © 2003 by CRC Press LLC

XR

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Feedback Amplifier Theory

825

open-loop amplifier, and not the feedback subcircuit, contains circuit elements and other parameters that are susceptible to modeling uncertainties, variations in the fabrication of active and passive elements, and nonzero manufacturing tolerances, large loop gain achieves a desirable parametric desensitization. Unfortunately, the determination of Go and ƒ directly from the Kirchhoff relationships is a nontrivial task, especially because Go is rarely independent of ƒ in practical electronics. Moreover, (27.1) does not illuminate the manner in which the loop gain modifies the driving-point input and output impedances of the open-loop amplifier. A second approach to feedback network analysis involves modeling the open-loop, feedback, and overall closed-loop networks by a homogeneous set of two-port parameters [7]. When the two-port parameter model is selected judiciously, the two-port parameters for the closed-loop network derive from a superposition of the respective two-port parameters of the open-loop and feedback subcircuits. Given the resultant parameters of the closed-loop circuit, standard formulas can then be exploited to evaluate closed-loop values of the circuit gain and the driving-point input and output impedances. Unfortunately, several limitations plague the utility of feedback network analysis predicated on twoport parameters. First, the computation of closed-loop two-port parameters is tedious if the open-loop configuration is a multistage amplifier, or if multiloop feedback is utilized. Second, the two-loop method of feedback circuit analysis is straightforwardly applicable to only those circuits that implement global feedback (feedback applied from output port to input port). Many single-ended feedback amplifiers exploit only local feedback, wherein a fraction of the signal developed at the output port is fed back to a terminal pair other than that associated with the input port. Finally, the appropriate two-port param­ eters of the open-loop amplifier can be superimposed with the corresponding parameter set of the feedback subcircuit if and only if the Brune condition is satisfied [8]. This requirement mandates equality between the preconnection and postconnection values of the two-port parameters of open-loop and feedback cells, respectively. The subject condition is often not satisfied when the open-loop amplifier is not a simple three-terminal two-port configuration. The third method of feedback circuit analysis exploits Mason’s signal flow theory [9–11]. The circuit level application of this theory suffers few of the shortcomings indigenous to block diagram and twoport methods of feedback circuit analysis [12]. Signal flow analyses applied to feedback networks effi­ ciently express I/O transfer functions, driving-point input impedances, and driving-point output imped­ ances in terms of an arbitrarily selected critical or reference circuit parameters, say P. An implicit drawback of signal flow methods is the fact that unless P is selected to be the feedback factor ƒ, which is not always transparent in feedback architectures, expressions for the loop gain and the open-loop gain of feedback amplifiers are obscure. However, by applying signal flow theory to a feedback circuit model engineered from insights that derive from the results of two-port network analyses, the feedback factor can be isolated. The payoff of this hybrid analytical approach includes a conventional block diagram model of the I/O transfer function, as well as convenient mathematical models for evaluating the closed-loop driving-point input and output impedances. Yet, another attribute of hybrid methods of feedback circuit analysis is its ability to delineate the cause, nature, and magnitude of the feedforward transmittance produced by interconnecting a certain feedback subcircuit to a given openloop amplifier. This information is crucial in feedback network design because feedforward invariably decreases gain and often causes undesirable phase shifts that can lead to significantly underdamped or unstable closed-loop responses.

27.3 Signal Flow Analysis Guidelines for feedback circuit analysis by hybrid signal flow methods can be established with the aid of Fig. 27.2 [13]. Figure 27.2(a) depicts a linear network whose output port is terminated in a resistance, RL . The output signal variable is the voltage VO , which is generated in response to an input port signal whose Thévenin voltage and resistance are respectively, VS and RS. Implicit to the linear network is a current-controlled voltage source (CCVS) Pib , with a value that is directly proportional to the indicated network branch current ib . The problem at hand is the deduction of the voltage gain Gv(RS, RL) = VO /VS , © 2003 by CRC Press LLC

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ib

Rin

Rout +

RS + VS

LINEAR NETWORK

VO −

− Pib

+

ib

Rino

+

RS +

RL VS

LINEAR NETWORK

P=0

−

VO = Gv (RS,RL) VS

VO = Gvo (RS, RL) VS

(a)

(b) iy

LINEAR NETWORK

0

VO −

− +

vx

−

iy vx = Qs (RS, RL) (c)

RL

−

+

−

+ +

VO

−

iy

RS

Routo

+

RS +

RL VS

LINEAR NETWORK

0

RL

−

− +

vx

−

iy vx = Qr (RS,RL) (d)

FIGURE 27.2 (a) Linear network with an identified critical parameter P. (b) Model for calculating the P = 0 value of voltage gain. (c) The return ratio with respect to P is PQs (RS , RL ). (d) The null return ratio with respect to P is PQr (RS , RL ).

the driving-point input resistance (or impedance) Rin, and the driving-point output resistance (or imped­ ance) Rout, as explicit functions of the critical transimpedance parameter P. Although the following systematic procedure is developed in conjunction with the diagram in Fig. 27.2, with obvious changes in notation, it is applicable to determining any type of transfer relationship for any linear network in terms of any type of reference parameter [14]. 1. Set P = 0, as depicted in Fig. 27.2(b), and compute the resultant voltage gain Gvo (RS, RL), where the indicated notation suggests an anticipated dependence of gain on source and load resistances. Also, compute the corresponding driving-point input and output resistances Rin, and Rout, respec­ tively. In this case, the “critical” parameter P is associated with a controlled voltage source. Accordingly, P = 0 requires that the branch containing the controlled source be supplanted by a short circuit. If, for example, P is associated with a controlled current source, P = 0 mandates the replacement of the controlled source by an open circuit. 2. Set the Thévenin source voltage VS to zero, and replace the original controlled voltage source Pib by an independent voltage source of symbolic value, vx. Then, calculate the ratio, iy /vx , where, as illustrated in Fig. 27.2(c), iy flows in the branch that originally conducts the controlling current ib . Note, however, that the reference polarity of iy is opposite to that of ib . The computed transfer function iy /vx is denoted by QS (RS, RL). This transfer relationship, which is a function of the source and load resistances, is used to determine the return ratio Ts (P, RS , RL ) with respect to parameter P of the original network. In particular, © 2003 by CRC Press LLC

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Feedback Amplifier Theory

Ts ( P, RS , RL ) = PQs ( RS , RL )

(27.2)

If P is associated with a controlled current source, the controlled generator Pib is replaced by a current source of value ix . If the controlling variable is a voltage, instead of a current, the ratio vy /vx , is computed, where vy , where the polarity is opposite to that of the original controlling voltage, is the voltage developed across the controlling branch. 3. The preceding computational step is repeated, but instead of setting VS to zero, the output variable, which is the voltage VO in the present case, is nulled, as indicated in Fig. 27.2(d). Let the computed ratio iy /vx , be symbolized as Qr (RS , RL ). In turn, the null return ratio Tr (P, RS , RL ), with respect to parameter P is Tr ( P, RS , RL ) = PQr ( RS , RL )

(27.3)

4. The desired voltage gain Gv (RS , RL ), of the linear network undergoing study can be shown to be [5, 12] Gv ( RS , RL ) =

1 + PQr ( RS , RL )  VO = Gvo ( RS , RL )  VS  1 + PQs ( RS , RL ) 

(27.4)

5. Given the function Qs(RS , RL ), the driving-point input and output resistances follow straightfor­ wardly from [12]  1 + PQs (0, RL )  Rin = Rino   1 + PQs (∞, RL ) 

(27.5)

 1 + PQs ( RS ,0)  Rout = Routo   1 + PQs ( RS , ∞) 

(27.6)

An important special case entails a controlling electrical variable ib associated with the selected param­ eter P that is coincidentally the voltage or current output of the circuit under investigation. In this situation, a factor P of the circuit response is fed back to the port (not necessarily the input port) defined by the terminal pair across which the controlled source is incident. When the controlling variable ib is the output voltage or current of the subject circuit Qr (RS , RL ), which is evaluated under the condition of a nulled network response, is necessarily zero. With Qr (RS , RL ) = 0, the algebraic form of (27.4) is identical to that of (27.1), where the loop gain T is the return ratio with respect to parameter P; that is, PQs ( RS , RL ) Q ( R r

S ,RL

) =0 = T

(27.7)

Moreover, a comparison of (27.4) to (27.l) suggests that Gv(RS, RL) symbolizes the closed-loop gain of the circuit, Gvo (RS , RL ) represents the corresponding open-loop gain, and the circuit feedback factor ƒ is f =

PQS ( RS , RL ) Gvo ( RS , RL )

(27.8)

27.4 Global Single-Loop Feedback Consider the global feedback scenario illustrated in Fig. 27.3(a), in which a fraction P of the output voltage VO is fed back to the voltage-driven input port. Figure 27.3(b) depicts the model used to calculate © 2003 by CRC Press LLC

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Rin

Rin

Rout

+

RS

LINEAR NETWORK

+ VS −

VO

Rout

−

RS RL

LINEAR NETWORK

+ 0

−

vy

RL

+

−

+

+

PVO −

−

vx

(a)

(b)

FIGURE 27.3 (a) Voltage-driven linear network with global voltage feedback. (b) Model for the calculation of loop gain.

the return ratio Qs(RS, RL), where, in terms of the branch variables in the schematic diagram, Qs(RS, RL) = vy /vx . An inspection of this diagram confirms that the transfer function vy/vx, is identical to the P = 0 value of the gain VO /VS , which derives from an analysis of the structure in Fig. 27.3(a). Thus, for global voltage feedback in which a fraction of the output voltage is fed back to a voltage-driven input port, Qs(RS, RL) is the open-loop voltage gain; that is, Qs(RS, RL) ≡ Gvo(RS, RL). It follows from (27.8) that the feedback factor ƒ is identical to the selected critical parameter P. Similarly, for the global current feedback architecture of Fig. 27.4(a), in which a fraction P of the output current, IO, is feed back to the currentdriven input port ƒ = P. As implied by the model of Fig. 27.4(b), Qs(RS, RL) ≡ Gio(RS, RL), the open-loop current gain. Rin

IS

RS

Rout

PIO

LINEAR NETWORK

RL IO

(a)

0

RS

LINEAR NETWORK

ix

RL iy

(b)

FIGURE 27.4 (a) Current-driven linear network with global current feedback. (b) Model for the calculation of loop gain.

© 2003 by CRC Press LLC

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Feedback Amplifier Theory

Driving-Point I/O Resistances Each of the two foregoing circuit architectures has a closed-loop gain where the algebraic form mirrors (27.1). It follows that for sufficiently large loop gain [equal to either PGvo(RS, RL) or PGio(RS, RL)], the closed-loop gain approaches (1/P) and is therefore desensitized with respect to open-loop gain param­ eters. However, such a desensitization with respect to the driving-point input and output resistances (or impedances) cannot be achieved. For the voltage feedback circuit in Fig. 27.3(a), Qs(∞, RL), is the RS = ∞ value, Gvo(RS,RL), of the open-loop voltage gain. This particular open-loop gain is zero, because RS = ∞ decouples the source voltage from the input port of the amplifier. On the other hand, Qs(0, RL) is the RS = 0 value, Gvo(0, RL), of the open-loop voltage gain. This gain is at least as large as Gvo(RS, RL), since a short circuited Thévenin source resistance implies lossless coupling of the Thévenin signal to the amplifier input port. Recalling (27.5), the resultant driving-point input resistance of the voltage feedback amplifier is

[

]

[

]

Rin = Rino 1 + PGvo (0, RL ) ≥ Rino 1 + PGvo ( RS , RL )

(27.9)

which shows that the closed-loop driving-point input resistance is larger than its open-loop counterpart and is dependent on open-loop voltage gain parameters. Conversely, the corresponding driving-point output resistance in Fig. 27.3(a) is smaller than the openloop output resistance and approximately inversely proportional to the open-loop voltage gain. These assertions derive from the facts that Qs(RS, 0) is the RL = 0 value of the open-loop voltage gain Gvo(RS, RL). Because RL = 0 corresponds to the short-circuited load resistance, Gvo(RS, 0) = 0. In contrast, Qs(RS, ∞), is the RL = ∞ value, Gvo(RS, ∞), of the open-loop gain, which is a least as large as Gvo(RS, RL). By (27.6), Rout =

Routo Routo ≤ 1 + PGvo ( RS , ∞) 1 + PGvo ( RS , RL )

(27.10)

Similarly, the driving-point input and output resistances of the global current feedback configuration of Fig. 27.4(a) are sensitive to open-loop gain parameters. In contrast to the voltage amplifier of Fig. 27.3(a), the closed-loop, driving-point input resistance of current amplifier is smaller than its openloop value, while the driving-point output resistance is larger than its open-loop counterpart. Noting that the open-loop current gain Gio(RS, RL) is zero for both RS = 0 (which short circuits the input port), and RL = ∞ (which open circuits the load port), (27.5) and (27.6) give Rin =

Rino 1 + PGio (∞, RL )

[

(27.11)

]

Rout = Routo 1 + PGio ( RS ,0)

(27.12)

Diminished Closed-Loop Damping Factor In addition to illuminating the driving-point and forward transfer characteristics of single-loop feedback architectures, the special case of global single-loop feedback illustrates the potenital instability problems pervasive of almost all feedback circuits. An examination of these problems begins by returning to (27.1) and letting the open-loop gain, Go, be replaced by the two-pole frequency-domain function, Go ( s ) =

© 2003 by CRC Press LLC

Go (0)  s  s  1 + p  1 + p   1  2

(27.13)

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where Go(0) symbolizes the zero-frequency open-loop gain. The pole frequencies p1 and p2 in (27.13) are either real numbers or complex conjugate pairs. Alternatively, (27.13) is expressible as Go ( s ) =

Go (0) 2ζol s2 1+ s+ 2 ω nol ω nol

(27.14)

where ω nol = p1 p2

(27.15)

represents the undamped natural frequency of oscillation of the open-loop configuration, and ζol =

1  p2 +  2  p1

p1   p2 

(27.16)

is the damping factor of the open-loop circuit. In (27.1), let the feedback factor ƒ be the single left-half-plane zero function, s  f (s ) = f o  1 +   z

(27.17)

where z is the frequency of the real zero introduced by feedback, and ƒo is the zero-frequency value of the feedback factor. The resultant loop gain is s  T ( s ) = f o  1 +  Go ( s )  z

(27.18)

the zero-frequency value of the loop gain is T (0) = foGo (0)

(27.19)

and the zero frequency closed-loop gain Gcl(0), is Gcl (0) =

Go (0) G (0) = o 1 + foGo (0) 1 + T (0)

(27.20)

Upon inserting (27.14) and (27.17) into (27.1), the closed-loop transfer function is determined to be Gcl (s ) =

Gcl (0) 2ζcl s2 1+ s+ 2 ω ncl ω ncl

(27.21)

where the closed-loop undamped natural frequency of oscillation ωncl relates to its open-loop counterpart ωnol , in accordance with ω ncl = ω nol 1 + T (0)

© 2003 by CRC Press LLC

(27.22)

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831

Feedback Amplifier Theory

Moreover, the closed-loop damping factor ζ cl is

ζcl =

 T (0)  ω  T (0)  ω ncl ζol  nol + + =  1 + T (0)  1 + T (0)  2z 1 + T (0) 1 + T (0)  2z ζol

(27.23)

A frequency invariant feedback factor ƒ (s) applied to the open-loop configuration whose transfer function is given by (27.13) implies an infinitely large frequency, z, of the feedback zero. For this case, (27.23) confirms a closed-loop damping factor that is always less than the open-loop damping factor. Indeed, for a smaller than unity open-loop damping factor (which corresponds to complex conjugate open-loop poles) and reasonable values of the zero-frequency loop gain T(0), ζ cl  1. Thus, constant feedback applied around an underdamped two-pole open-loop amplifier yields a severely underdamped closed-loop configuration. It follows that the closed-loop circuit has a transient step response plagued by overshoot and a frequency response that displays response peaking within the closed-loop passband. Observe that underdamping is likely even in critically damped (identical real open-loop poles) or overdamped (distinct real poles) open-loop amplifiers, which, respectively, correspond to ζol = 1 and ζol > 1, when a large zero-frequency loop gain is exploited. Underdamped closed-loop amplifiers are not unstable systems, but they are nonetheless unacceptable. From a practical design perspective, closed-loop underdamping predicted by relatively simple mathe­ matical models of the loop gain portend undesirable amplifier responses or even closed-loop instability. The problem is that simple transfer function models invoked in a manual circuit analysis are oblivious to presumably second-order parasitic circuit layout and device model energy storage elements with effects that include a deterioration of phase and gain margins.

Frequency Invariant Feedback Factor Let the open-loop amplifier be overdamped, such that its real satisfy the relationship p2 = κ 2 p1

(27.24)

If the open-loop amplifier pole p1 is dominant, κ2 is a real number that is greater than the magnitude, Go(0), of the open-loop zero frequency gain, which is presumed to be much larger than one. The openloop damping factor in (27.16) resultantly reduces to ζo1 ≈ κ/2. With κ2 > Go(0)  1, which formally reflects the dominant pole approximation, the 3-dB bandwidth Bol of the open-loop amplifier is given approximately by [15] Bol ≈

 κ2  ω nol 1 = =  2  p1 1 1  κ +1  2ζol + p1 p2

(27.25)

As expected, (27.25) predicts an open-loop 3-dB bandwidth that is only slightly smaller than the frequency of the open-loop dominant pole. The frequency, z, in (27.23) is infinitely large if frequency invariant degenerative feedback is applied around on open-loop amplifier. For a critically damped or overdamped closed-loop amplifier, ζ cl > 1. Assuming open-loop pole dominance, this constraint imposes the open-loop pole requirement,

[

]

p2 ≥ 4 1 + T (0) p1

(27.26)

Thus, for large zero-frequency loop gain, T(0), an underdamped closed-loop response is avoided if and only if the frequency of the nondominant open-loop pole is substantially larger than that of the dominant

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open-loop pole. Unless frequency compensation measures are exploited in the open loop, (27.26) is difficult to satisfy, especially if feedback is implemented expressly to realize a substantive desensitization of response with respect to open-loop parameters. On the chance that (27.26) can be satisfied, and if the closed-loop amplifier emulates a dominant pole response, the closed-loop bandwidth is, using (27.22), (27.23), and (27.25), Bcl ≈

ω ncl ≈ 1 + T (0) Bol ≈ 1 + T (0) p1 2ζcl

[

]

[

]

(27.27)

Observe from (27.27) and (27.26) that the maximum possible closed-loop 3-dB bandwidth is 2 octaves below the minimum acceptable frequency of the nondominant open-loop pole. Although (27.27) theoretically confirms the broadbanding property of negative feedback amplifiers, the attainment of very large closed-loop 3-dB bandwidths is nevertheless a challenging undertaking. The problem is that (27.26) is rarely satisfied. As a result, the open-loop configuration must be suitably compensated, usually by pole splitting methodology [16–18], to force the validity of (27.26). However, the open-loop poles are not mutually independent, so any compensation that increases p2 is accompanied by decreases in p1. The pragmatic upshot of the matter is that the closed-loop 3-dB bandwidth is not directly proportional to the uncompensated value of p1 but instead, it is proportional to the smaller, compensated value of p1.

Frequency Variant Feedback Factor (Compensation) Consider now the case where the frequency, z, of the compensating feedback zero is finite and positive. Equation (27.23) underscores the stabilizing property of a left-half-plane feedback zero in that a suffi­ ciently small positive z renders a closed-loop damping factor ζ cl that can be made acceptably large, regardless of the value of the open-loop damping factor ζol. To this end, ζ cl > 1/ 2 is a desirable design objective in that it ensures a monotonically decreasing closed-loop frequency response. If, as is usually a design goal, the open-loop amplifier subscribes to pole dominance, (27.23) translates the objective, ζcl > 1/ 2, into the design constraint  T (0)   ω ncl 1 + T (0)  z≤ ω ncl 2− 1 + T (0) Bol

[

(27.28)

]

where use is made of (27.25) to cast ζ in terms of the open-loop bandwidth Bol. When the closed-loop damping factor is precisely equal to 1/ 2 a maximally flat magnitude closed-loop response results for which the 3-dB bandwidth is ωncl. Equation (27.28) can then be cast into the more useful form zGcl (0) =

GBPol  GBPol  2  −1  GBPcl 

(27.29)

where (27.20) is exploited, GBPol is the gain-bandwidth product of the open-loop circuit, and GBPcl is the gain-bandwidth product of the resultant closed-loop network. For a given open-loop gain-bandwidth product GBPol, a desired low-frequency closed-loop gain, Gcl (0), and a desired closed-loop gain-bandwidth product, GBPcl, (27.29) provides a first-order estimate of the requisite feedback compensation zero. Additionally, note that (27.29) imposes an upper limit on the achievable high-frequency performance of the closed-loop configuration. In particular, because z must be positive to ensure acceptable closed-loop damping, (27.29) implies © 2003 by CRC Press LLC

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GBPol >

GBPcl 2

(27.30)

In effect, (27.30) imposes a lower limit on the required open-loop gain-bandwidth product commensurate with feedback compensation implemented to achieve a maximally flat, closed-loop frequency response.

27.5 Pole Splitting Open-Loop Compensation Equation (27.26) underscores the desirability of achieving an open-loop dominant pole frequency response in the design of a feedback network. In particular, (27.26) shows that if the ultimate design goal is a closed-loop dominant pole frequency response, the frequency, p2, of the nondominant open-loop amplifier pole must be substantially larger than its dominant pole counterpart, p1. Even if closed-loop pole dominance is sacrificed as a trade-off for other performance merits, open-loop pole dominance is nonetheless a laudable design objective. This contention follows from (27.23) and (27.16), which combine to suggest that the larger p2 is in comparison to p1, the larger is the open-loop damping factor. In turn, the unacceptably underdamped closed-loop responses that are indicative of small, closed-loop damping factors are thereby eliminated. Moreover, (27.23) indicates that larger, open-loop damping factors impose progressively less demanding restrictions on the feedback compensation zero that may be required to achieve acceptable closed-loop damping. This observation is important because in an actual circuit design setting, small z in (27.23) generally translates into a requirement of a correspondingly large RC time constant, where implementation may prove difficult in monolithic circuit applications. Unfortunately, many amplifiers, and particularly broadbanded amplifiers, earmarked for use as openloop cells in degenerative feedback networks, are not characterized by dominant pole frequency responses. The frequency response of these amplifiers is therefore optimized in accordance with a standard design practice known as pole splitting compensation. Such compensation entails the connection of a small capacitor between two high impedance, phase inverting nodes of the open-loop topology [17, 19–21]. Pole splitting techniques increase the frequency p2 of the uncompensated nondominant open-loop pole to a compensated value, say p2c . The frequency, p1, of the uncompensated dominant open-loop pole is simultaneously reduced to a smaller frequency, say plc . Although these pole frequency translations com­ plement the design requirement implicit to (27.26) and (27.23), they do serve to limit the resultant closed-loop bandwidth, as discussed earlier. As highlighted next, they also impose other performance limitations on the open loop.

The Open-Loop Amplifier The engineering methods, associated mathematics, and engineering trade-offs underlying pole splitting compensation are best revealed in terms of the generalized, phase inverting linear network abstracted in Fig. 27.5. Although this amplifier may comprise the entire open-loop configuration, in the most general case, it is an interstage of the open loop. Accordingly, Rst in this diagram is viewed as the Thévenin equivalent resistance of either an input signal source or a preceding amplification stage. The response to the Thévenin driver, Vst , is the indicated output voltage, Vl , which is developed across the Thévenin load resistance, Rlt , seen by the stage under investigation. Note that the input current conducted by the amplifier is Is , while the current flowing into the output port of the unit is denoted as Il. The dashed branch containing the capacitor Cc , which is addressed later, is the pole splitting compensation element. Because the amplifier under consideration is linear, any convenient set of two-port parameters can be used to model its terminal volt–ampere characteristics. Assuming the existence of the short circuit admittance, or y parameters, I s   y11  =  I l   y 21 © 2003 by CRC Press LLC

y12  Vi    y 2  Vl 

(27.31)

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Cc Vi

Vl Is

Rst + Vst −

Il PHASE­ INVERTING LINEAR AMPLIFIER

Rlt

FIGURE 27.5 A linear amplifier for which a pole splitting compensation capacitance Cc is incorporated.

Defining y o =∆ y11 + y12 y o =∆ y 22 + y12 (27.32) y f =∆ y 21 + y12 y r =∆ − y12 (27.31) implies I s = y iVi + y r (Vi − Vl )

(27.33)

I l = y f Vi + y oV1 + y r (Vl − Vi )

(27.34)

The last two expressions produce the y-parameter model depicted in Fig. 27.6(a), in which yi represents an effective shunt input admittance, yo is a shunt output admittance, yf is a forward transadmittance, and yr reflects voltage feedback intrinsic to the amplifier. Amplifiers amenable to pole splitting compensation have capacitive input and output admittances; that is, yi and yo are of the form yi =

1 + sCi Ri

(27.35)

1 yo = + sCo Ro Similarly, y f = G f − sC f yr =

1 + sCr Rr

(27.36)

In (27.36), the conductance component Gf of the forward transadmittance yf positive in a phase-inverting amplifier. Moreover, the reactive component –sCf of yf produces an excess phase angle, and hence, a group © 2003 by CRC Press LLC

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Vi

Is

Il

Vl

yr Rst yf Vi

yi

+

yo

Rlt

Vst −

(a) Vi

Is

Cr

Il

Vl

Rst +

Ri

Gf Vi

Ci

Ro

Co

Rlt

Vst −

(b)

FIGURE 27.6 (a) The y-parameter equivalent circuit of the phase-inverting linear amplifier in Fig. 27.5. (b) An approximate form of the model in (a).

delay, in the forward gain function. This component, which deteriorates phase margin, can be ignored to first order if the signal frequencies of interest are not excessive in comparison to the upper-frequency limit of performance of the amplifier. Finally, the feedback internal to many practical amplifiers is predominantly capacitive so that the feedback resistance Rr can be ignored. These approximations allow the model in Fig. 23.6(a) to be drawn in the form offered in Fig. 27.6(b). It is worthwhile interjecting that the six parameters indigenous to the model in Fig. 27.6(b) need not be deduced analytically from the small-signal models of the active elements embedded in the subject interstage. Instead, SPICE can be exploited to evaluate the y parameters in (27.31) at the pertinent biasing level. Because these y parameters display dependencies on signal frequency, care should be exercised to evaluate their real and imaginary components in the neighborhood of the open-loop, 3-dB bandwidth to ensure acceptable computational accuracy at high frequencies. Once the y parameters in (27.31) are deduced by computer-aided analysis, the alternate admittance parameters in (27.23), as well as numerical estimates for the parameters, Ri , Ci , Ro , Co , Cr , and Gf , in (27.35) and (27.36) follow straightforwardly.

Pole Splitting Analysis An analysis of the circuit in Fig. 27.6(b) produces a voltage transfer function Av(s) of the form   s   1− Vl (s ) zr   Av (s ) = = Av (0) Vst (s )  s  s   1 +  1 +   p1   p2    

(27.37)

Rll = Rlt Ro

(27.38)

Letting

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an inspection of the circuit in Fig. 27.6(b) confirms that  Ri  Av (0) = −G f Rll    Ri + Rst 

(27.39)

is the zero frequency voltage gain. Moreover, the frequency, zr, of the right-half-plane zero is zr =

G f

(27.40)

Cr

The lower pole frequency, p1, and the higher pole frequency, p2, derive implicitly from

[ (

) ]

1 1 + = Rll (Co + Cr ) + Rss Ci + 1 + G f Rll Cr p1 p2

(27.41)

  C + Ci   1 = Rss RllCo Ci +  o  Cr  p1 p2  Co   

(27.42)

and

where ∆

Rss = Rst = Ri

(27.43)

Most practical amplifiers, and particularly amplifiers realized in bipolar junction transistor technology, have very large forward transconductance, Gf , and small internal feedback capacitance, Cr . The combi­ nation of large Gf and small Cr renders the frequency in (27.40) so large as to be inconsequential to the passband of interest. When utilized in a high-gain application, such as the open-loop signal path of a feedback amplifier, these amplifiers also operate with a large effective load resistance, Rll . Accordingly, (27.41) can be used to approximate the pole frequency p1 as p1 ≈

[ (

1

) ]

Rss Ci + 1 + G f Rll Cr

(27.44)

Substituting this result into (27.42), the approximate frequency p2 of the high-frequency pole is

p2 ≈

(

)

Ci + 1 + G f Rll Cr   C + Ci   RllCo Ci +  o  Cr   Co   

(27.45)

Figure 27.7 illustrates asymptotic frequency responses corresponding to pole dominance and to a twopole response. Figure 27.7(a) depicts the frequency response of a dominant pole amplifier, which does not require pole splitting compensation. Observe that its high-frequency response is determined by a single pole (p1 in this case) through the signal frequency at which the gain ultimately degrades to unity. In this interpretation of a dominant pole amplifier, p2 is not only much larger than p1, but is in fact larger than the unity gain frequency, which is indicated as ωu in the figure. This unity gain frequency, which can be viewed as an upper limit to the useful passband of the amplifier, is approximately, Av (0)p1. To the extent that p1 is essentially the 3-dB bandwidth when p2  p1, the unity gain frequency is also the © 2003 by CRC Press LLC

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Feedback Amplifier Theory

| Av(jω) | | Av(0) | Sl e:

op 0

−2 ec

/d

db

P2 1

ω

ωu

P1

− 40 ec

db/d

(a) | Av(jω) |

e:

op

Sl

| Av(0) |

0

−2 ec

/d

db

1

P2

−40

P1

ωu

ω

dec

db/

(b)

FIGURE 27.7 (a) Asymptotic frequency response for a dominant pole amplifier. Such an amplifier does not require pole splitting compensation because the two lowest frequency amplifier poles, p1 and p2, are already widely separated. (b) The frequency response of an amplifier with high-frequency response that is strongly influenced by both of its lowest frequency poles. The basic objective of pole splitting compensation is to transform the indicated frequency response to a form that emulates that depicted in (a).

gain-bandwidth product (GBP) of the subject amplifier. In short, with Av(jωu) =∆ 1, p2  p1 in (27.37) implies ω u ≈ Av (0) p1 ≈ GBP

(27.46)

The contrasting situation of a response indigenous to the presence of two significant open-loop poles is illustrated in Fig. 27.7(b). In this case, the higher pole frequency p2 is smaller than ωu and hence, the amplifier does not emulate a single-pole response throughout its theoretically useful frequency range. The two critical frequencies, p1 and p2, remain real numbers, and as long as p2 ≠ p1, the corresponding damping factor, is greater than one. However, the damping factor of the two-pole amplifier (its response is plotted in Fig. 27.7(b)) is nonetheless smaller than that of the dominant pole amplifier. It follows that, for reasonable loop gains, unacceptable underdamping is more likely when feedback is invoked around © 2003 by CRC Press LLC

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the two-pole amplifier, as opposed to the same amount of feedback applied around a dominant pole amplifier. Pole splitting attempts to circumvent this problem by transforming the pole conglomeration of the two pole amplifier into one that emulates the dominant pole situation inferred by Fig. 27.7(a). To the foregoing end, append the compensation capacitance Cc between the input and the output ports of the phase-inverting linear amplifier, as suggested in Fig. 27.5. With reference to the equivalent circuit in Fig. 27.6(b), the electrical impact of this additional element is the effective replacement of the internal feedback capacitance Cr by the capacitance sum (Cr + Cc). Letting ∆

C p = Cr + Cc

(27.47)

it is apparent that (27.40)–(27.42) remain applicable, provided that Cr in these relationships is supplanted by Cp . Because Cp is conceivably significantly larger than Cc , however, the approximate expressions for the resultant pole locations differ from those of (27.44) and (27.45). In particular, a reasonable approx­ imation for the compensated value, say P1c , of the lower pole frequency is now p1c ≈

[ (

1

) ]

Rll + 1 + G f Rll Rss C p

(27.48)

while the higher pole frequency, p2c , becomes p2 c ≈

1  1   Rss Rll G  (Co + Ci )  f 

(27.49)

Clearly, p1c < p1 and p2c > p2. Moreover, for large Gf , p2c is potentially much larger than p1c. It should also be noted that the compensated value, say, zrc , of the right-half-plane zero is smaller than its uncompen­ sated value, zr , because (27.40) demonstrates that z rc =

Gf Cp

 Cr  = zr    Cr + Cc 

(27.50)

Although zrc can conceivably exert a significant influence on the high-frequency response of the com­ pensated amplifier, the following discussion presumes tacitly that zrc > p2c [2]. Assuming a dominant pole frequency response, the compensated unity gain frequency, ωuc , is, using (27.39), (27.46), and (27.48),  1   1  G f  Rss Rll  ω uc ≈ Av (0) p1c ≈   G f    RstC p    

(27.51)

 1  ω uc <    RstC p 

(27.52)

It is interesting to note that

that is, the unity gain frequency is limited by the inverse of the RC time constant formed by the Thévenin source resistance Rst and the net capacitance Cp appearing between the input port and the phase inverted output port. The subject inequality comprises a significant performance limitation, for if p2c is indeed © 2003 by CRC Press LLC

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much larger than pic , ωuc is approximately the GBP of the compensated cell. Accordingly, for a given source resistance, a required open-loop gain, and a desired open-loop bandwidth, (27.52) imposes an upper limit on the compensation capacitance that can be exploited for pole splitting purposes. In order for the compensated amplifier to behave as a dominant pole configuration, p2c must exceed ωuc , as defined by (27.51). Recalling (27.49), the requisite constraint is found to be 2

 1  RstC p > G f  Rss Rll (C + Ci ) G f  o 

(27.53)

Assuming Gf (Rss/Rll)  1, (27.53) reduces to the useful simple form C f Rst >

Co + Ci Cp

(27.54)

which confirms the need for large forward transconductance Gf if pole splitting is to be an effective compensation technique.

27.6 Summary The use of negative feedback is fundamental to the design of reliable and reproducible analog electronic networks. Accordingly, this chapter documents the salient features of the theory that underlies the efficient analysis and design of commonly used feedback networks. Four especially significant points are postulated in this section. 1. By judiciously exploiting signal flow theory, the classical expression, (27.1), for the I/O transfer relationship of a linear feedback system is rendered applicable to a broad range of electronic feedback circuits. This expression is convenient for design-oriented analysis because it clearly identifies the open-loop gain, Go, and the loop gain, T. The successful application of signal flow theory is predicated on the requirement that the feedback factor, to which T is proportional and that appears in the signal flow literature as a “critical” or “reference” parameter, can be identified in a given feedback circuit. 2. Signal flow theory, as applied to electronic feedback architectures, proves to be an especially expe­ dient analytical tool because once the loop gain T is identified, the driving-point input and output impedances follow with minimal additional calculations. Moreover, the functional dependence of T on the Thévenin source and terminating load impedances unambiguously brackets the magni­ tudes of the driving point I/O impedances attainable in particular types of feedback arrangements. 3. The damping factor concept is advanced herewith as a simple way of assessing the relative stability of both the open and closed loops of a feedback circuit. The open-loop damping factor derives directly from the critical frequencies of the open-loop gain, while these frequencies and any zeros appearing in the loop gain unambiguously define the corresponding closed-loop damping factor. Signal flow theory is once again used to confirm the propensity of closed loops toward instability unless the open-loop subcircuit functions as a dominant pole network. Also confirmed is the propriety of the common practice of implementing a feedback zero as a means of stabilizing an otherwise potentially unstable closed loop. 4. Pole splitting as a means to achieve dominant pole open-loop responses is definitively discussed. Generalized design criteria are formulated for this compensation scheme, and limits of perfor­ mance are established. Of particular interest is the fact that pole splitting limits the GBP of the compensated amplifier to a value that is determined by a source resistance-compensation capac­ itance time constant. © 2003 by CRC Press LLC

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References [1] J. A. Mataya, G. W. Haines, and S. B. Marshall, “IF amplifier using Cc -compensated transistors,” IEEE J. Solid-State Circuits, vol. SC-3, pp. 401–407, Dec. 1968. [2] W. G. Beall and J. Choma, Jr., “Charge-neutralized differential amplifiers,” J. Analog Integrat. Circuits Signal Process., vol. 1, pp. 33–44, Sep. 1991. [3] J. Choma, Jr., “A generalized bandwidth estimation theory for feedback amplifiers,” IEEE Trans. Circuits Syst., vol. CAS-31, pp. 861–865, Oct. 1984. [4] R. D. Thornton, C. L. Searle, D. O. Pederson, R. B. Adler, and E. J. Angelo, Jr., Multistage Transistor Circuits, New York: John Wiley & Sons, 1965, chaps. 1, 8. [5] H. W. Bode, Network Analysis and Feedback Amplifier Design, New York: Van Nostrand, 1945. [6] P. J. Hurst, “A comparison of two approaches to feedback circuit analysis,” IEEE Trans Education, vol. 35, pp. 253–261, Aug. 1992. [7] M. S. Ghausi, Principles and Design of Linear Active Networks, New York: McGraw-Hill, 1965, pp. 40–56. [8] A. J. Cote, Jr. and J. B. Oakes, Linear Vacuum-Tube and Transistor Circuits, New York: McGrawHill, 1961, pp. 40–46. [9] S. J. Mason, “Feedback theory — Some properties of signal flow graphs,” Proc. IRE, vol. 41, pp. 1144–1156, Sep. 1953. [10] S. J. Mason, “Feedback theory — Further properties of signal flow graphs,” Proc. IRE, vol. 44, pp. 920–926, July 1956. [11] N. Balabanian and T. A. Bickart, Electrical Network Theory, New York: John Wiley & Sons, 1969, pp. 639–669. [12] J. Choma, Jr., “Signal flow analysis of feedback networks,” IEEE Trans. Circuits Syst., vol. 37, pp. 455–463, April 1990. [13] J. Choma, Jr., Electrical Networks: Theory and Analysis, New York: Wiley Interscience, 1985, pp. 589–605. [14] P. J. Hurst, “Exact simulation of feedback circuit parameters,” IEEE Trans. Circuits Syst., vol. 38, pp. 1382–1389, Nov. 1991. [15] J. Choma, Jr. and S. A. Witherspoon, “Computationally efficient estimation of frequency response and driving point impedance in wideband analog amplifiers,” IEEE Trans. Circuits Syst., vol. 37, pp. 720–728, June 1990. [16] R. G. Meyer and R. A. Blauschild, “A wide-band low-noise monolithic transimpedance amplifier,” IEEE J. Solid-State Circuits, vol. SC-21, pp. 530–533, Aug. 1986. [17] Y. P. Tsividis, “Design considerations in single-channel MOS analog integrated circuits,” IEEE J. Solid-State Circuits, vol. SC-13, pp. 383–391, June 1978. [18] J. J. D’Azzo and C. H. Houpis, Feedback Control System Analysis and Synthesis, New York: McGrawHill, 1960, pp. 230–234. [19] P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, New York: John Wiley & Sons, 1977, pp. 512–521. [20] P. R. Gray, “Basic MOS operational amplifier design — An overview,” in Analog MOS Integrated Circuits, P. R. Gray, D. A. Hodges, and R. W. Brodersen, Eds., New York: IEEE, 1980, pp. 28–49. [21] J. E. Solomon, “The monolithic op-amp: A tutorial study,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 314–332, Dec. 1974.

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28 Feedback Amplifier Configurations 28.1 Introduction 28.2 Series-Shunt Feedback Amplifier Circuit Modeling and Analysis • Feed-Forward Compensation

28.3 Shunt-Series Feedback Amplifier 28.4 Shunt-Shunt Feedback Amplifier Circuit Modeling and Analysis • Design Considerations

28.5 Series-Series Feedback Amplifier 28.6 Dual-Loop Feedback Series-Series/Shunt-Shunt Feedback Amplifier • SeriesShunt/Shunt-Series Feedback Amplifier

John Choma, Jr. University of Southern California

28.7 Summary

28.1 Introduction Four basic types of single-loop feedback amplifiers are available: the series-shunt, shunt-series, shuntshunt, and series-series architectures [1]. Each of these cells is capable of a significant reduction of the dependence of forward transfer characteristics on the ill-defined or ill-controlled parameters implicit to the open-loop gain; but none of these architectures can simultaneously offer controlled driving-point input and output impedances. Such additional control is afforded only by dual global loops comprised of series and/or shunt feedback signal paths appended to an open-loop amplifier [2], [3]. Only two types of global dual-loop feedback architectures are used: the series-series/shunt-shunt feedback amplifier and the series-shunt/shunt-series feedback amplifier. Although only bipolar technology is exploited in the analysis of the aforementioned four single-loop and two dual-loop feedback cells, all disclosures are generally applicable to metaloxide-silicon (MOS), heterostructure bipolar transistor (HBT), and III–V compound metal-semiconductor field-effect tran­ sistor (MESFET) technologies. All analytical results derive from an application of a hybrid, signal flow/two-port parameter analytical tack. Because the thought processes underlying this technical approach apply to all feedback circuits, the subject analytical procedure is developed in detail for only the series-shunt feedback amplifier.

28.2 Series-Shunt Feedback Amplifier Circuit Modeling and Analysis Figure 28.1(a) depicts the ac schematic diagram (a circuit diagram divorced of biasing details) of a seriesshunt feedback amplifier. In this circuit, the output voltage VO, which is established in response to a single source represented by the Thévenin voltage VST , and the Thévenin resistance, RST , is sampled by

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I2A Rin

Q2 I1A VI

Q1

Rout

IO

I2F

RLT

R

+ RST

VO

V1A

+

I1F

−

VST

+ V1F −

−

RF REE FEEDBACK NETWORK (a)

Rin VI RST

+

rb

rb I1A rπ

I2A

−

V1A

Rout

IV βI1A

R

rπ

IO

βIV

+ VST

VO

I2F re

RLT

re

(β + 1)I1A = I1F − + V1F −

RF

REE

FEEDBACK

NETWORK

(b)

FIGURE 28.1 (a) The ac schematic diagram of a bipolar series-shunt feedback amplifier. (b) Low-frequency smallsignal equivalent circuit of the feedback amplifier.

the feedback network composed of the resistances, REE and RF . The sampled voltage is fed back in such a way that the closed-loop input voltage, VI , is the sum of the voltage, V1A, across the input port of the amplifier and the voltage V1F , developed across REE in the feedback subcircuit. Because VI = V1A + V1F , the output port of the feedback configuration can be viewed as connected in series with the amplifier input port. On the other hand, output voltage sampling constrains the net load current, IO, to be the algebraic sum of the amplifier output port current, I2A, and the feedback network input current, I2F. Accordingly, the output topology is indicative of a shunt connection between the feedback subcircuit and the amplifier output port. The fact that voltage is fed back to a voltage-driven input port renders the driving point input resistance, Rin, of the closed-loop amplifier large, whereas the driving-point output resistance, Rout, seen by the terminating load resistance, RLT , is small. The resultant closed-loop amplifier is therefore best suited for voltage amplification, in the sense that the closed-loop voltage gain, VO /VST , can be made approximately independent of source and load resistances. For large loop gain, this voltage transfer function is also nominally independent of transistor parameters. Assuming that transistors Q1 and Q2 are identical devices that are biased identically, Fig. 28.1(b) is the applicable low-frequency equivalent circuit. This equivalent circuit exploits the hybrid-π model [4] of a bipolar junction transistor, subject to the proviso that the forward Early resistance [5] used to emulate base conductivity modulation is sufficiently large to warrant its neglect. Because an infinitely large forward © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 843 Sunday, October 6, 2002 5:16 PM

Early resistance places the internal collector resistance (not shown in the figure) of a bipolar junction transistor in series with the current controlled current source, this collector resistance can be ignored as well. The equivalent circuit of Fig. 28.1(b) can be reduced to a manageable topology by noting that the ratio of the signal current, IV , flowing into the base of transistor Q2 to the signal current, I1A, flowing into the base of transistor Q1 is IV ∆ βR αR = − Kβ = − =− R + rb + rπ + (β + 1)re rib + (1 − α )R I1A

(28.1)

where α=

β β +1

(28.2)

is the small-signal, short-circuit common base current gain, and rib = re +

rπ + rb β +1

(28.3)

symbolizes the short-circuit input resistance of a common base amplifier. It follows that the current source βIv in Fig. 28.1(b) can be replaced by the equivalent current (–βKβ I1A). A second reduction of the equivalent circuit in Fig. 28.1(b) results when the feedback subcircuit is replaced by a model that reflects the h-parameter relationships V1F  hif  =  I 2F  h ff

hrf  I1F    hof   Vo 

(28.4)

where V1F (VO ) represents the signal voltage developed across the output (input) port of the feedback subcircuit and I1F (I2F) symbolizes the corresponding current flowing into the feedback output (input) port. Although any homogeneous set of two-port parameters can be used to model the feedback subcir­ cuit, h parameters are the most convenient selection herewith. In particular, the feedback amplifier undergoing study is a series-shunt configuration. The h-parameter equivalent circuit represents its input port as a Thévenin circuit and its input port as a Norton configuration, therefore, the h-parameter equivalent circuit is likewise a series-shunt structure. For the feedback network at hand, which is redrawn for convenience in Fig. 28.2(a), the h-parameter equivalent circuit is as depicted in Fig. 28.2(b). The latter diagram exploits the facts that the short-circuit input resistance hif is a parallel combination of the resistance REE and RF , and the open-circuit output conductance hof , is 1/(REE + RF ). The open-circuit reverse voltage gain hrf is REE REE + RF

(28.5)

REE = −hrf REE + RF

(28.6)

hrf = while the short-circuit forward current gain hff is h ff =

Figure 28.2(c) modifies the equivalent circuit in Fig. 28.2(b) in accordance with the following two argu­ ments. First, hrf in (28.5) is recognized as the fraction of the feedback subcircuit input signal that is fed © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 844 Sunday, October 6, 2002 5:16 PM

I2F

I1F

V1F

VO RF REE

(a) I1F

REE//RF

I2F

V1F = (β + 1)I1A

VO

+ hrf VO

hff I1F

−

REE + RF

(b)

V1F

I1F

REE//RF

= (β + 1)I1A

I2F VO

+ f (β + 1)I1A

f VO

REE + RF

−

(c)

FIGURE 28.2 (a) The feedback subcircuit in the series-shunt feedback amplifier of Fig. 28.1(a). (b) The h-parameter equivalent circuit of the feedback subcircuit. (c) Alternative form of the h-parameter equivalent circuit.

back as a component of the feedback subcircuit output voltage, V1F . But this subcircuit input voltage is identical to the closed-loop amplifier output signal VO . Moreover, V1F superimposes with the Thévenin input signal applied to the feedback amplifier to establish the amplifier input port voltage, V1A. It follows that hrf is logically referenced as a feedback factor, say f, of the amplifier under consideration; that is, hrf =

REE ∆ =f REE + RF

(28.7)

REE = −f REE + RF

(28.8)

and by (28.6), h ff = −

Second, the feedback subcircuit output current, I1F , is, as indicated in Fig. 28.1(b), the signal current, (β + 1)I1A. Thus, in the model of Fig. 28.2(b), h ff I1F = − f (β +1)I1A

(28.9)

If the model in Fig. 28.2(c) is used to replace the feedback network in Fig. 28.1(b) the equivalent circuit of the series-shunt feedback amplifier becomes the alternative structure offered in Fig. 28.3. In arriving © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 845 Sunday, October 6, 2002 5:16 PM

Rin

Rout VI

rb

IN

VO

I1A RST

rπ

Kβ β I1A

f (β + 1)I1A

REE + RF

RLT

+ VST

re

−

(β + 1)I1A β I1A

REE//RF + f VO −

FIGURE 28.3 Modified small-signal model of the series-shunt feedback amplifier.

at this model, care has been exercised to ensure that the current flowing through the emitter of transistor Q1 is (β + 1)I1A. It is important to note that the modified equivalent circuit delivers transfer and driving point impedance characteristics that are identical to those implicit to the equivalent circuit of Fig. 28.1(b). In particular, the traditional analytical approach to analyzing a series-shunt feedback amplifier tacitly presumes the satisfaction of the Brune condition [6] to formulate a composite structure where the h-parameter matrix is the sum of the respective h-parameter matrices for the open-loop and feedback circuits. In contrast, the model of Fig. 28.3 derives from Fig. 28.1(b) without invoking the Brune require­ ment, which is often not satisfied. It merely exploits the substitution theorem; that is, the feedback network in Fig. 28.1(b) is substituted by its h-parameter representation. In addition to modeling accuracy, the equivalent circuit in Fig. 28.3 boasts at least three other advan­ tages. The first is an illumination of the vehicle by which feedback is implemented in the series-shunt configuration. This vehicle is the voltage controlled voltage source, f VO, which feeds back a fraction of the output signal to produce a branch voltage that algebraically superimposes with, and thus modifies, the applied source voltage effectively seen by the input port of the open-loop amplifier. Thus, with f = 0, no feedback is evidenced, and the model at hand emulates an open-loop configuration. But even with f = 0, the transfer and driving-point impedance characteristics of the resultant open-loop circuit are functionally dependent on the feedback elements, REE and RF , because appending the feedback network to the open-loop amplifier incurs additional impedance loads at both the input and the output ports of the amplifier. The second advantage of the subject model is its revelation of the magnitude and nature of feedforward through the closed loop. In particular, note that the signal current, IN, driven into the effective load resistance comprised of the parallel combination of (REE + RF) and RLT , is the sum of two current components. One of these currents, βKβ I1A , materializes from the transfer properties of the two transistors utilized in the amplifier. The other current, f (β + 1)I1A, is the feed-forward current resulting from the bilateral nature of the passive feedback network. In general, negligible feed-forward through the feedback subcircuit is advantageous, particularly in high-frequency signal-processing applications. To this end, the model in Fig. 28.3 suggests the design requirement, f  αK β

(28.10)

When the resistance, R, in Fig. 28.1(a) is the resistance associated with the output port of a PNP current source used to supply biasing current to the collector of transistor Q1 and the base of transistor Q2, Kβ approaches β, and (28.10) is easily satisfied; however, PNP current sources are undesirable in broadband low-noise amplifiers. In these applications, the requisite biasing current must be supplied by a passive © 2003 by CRC Press LLC

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resistance, R, connected between the positive supply voltage and the junction of the Q1 collector and the Q2 base. Unfortunately, the corresponding value of Kβ can be considerably smaller than β, with the result that (28.10) may be difficult to satisfy. Circumvention schemes for this situation are addressed later. A third attribute of the model in Fig. 28.3 is its disposition to an application of signal flow theory. For example, with the feedback factor f selected as the reference parameter for signal flow analysis, the openloop voltage gain Gvo(RST , RLT), of the series-shunt feedback amplifier is computed by setting f to zero. Assuming that (28.10) is satisfied, circuit analysis reveals this gain as  (REE + RF ) RLT  Gvo ( RST , RLT ) = αK β   rib + (1 − α )RST + REE RF   

(

(28.11)

)

The corresponding input and output driving point resistances, Rino and Routo , respectively, are

(

Rino = rB + rπ + (β + 1) rE + REE RF

)

(28.12)

and Routo = REE + RF

(28.13)

It follows that the closed-loop gain Gv (RST, RLT) of the series-shunt feedback amplifier is Gv ( RST , RLT ) =

Gvo ( RST , RLT )

(28.14)

1+T

where the loop gain T is  REE  T = f Gvo ( RST , RLT ) =   Gvo ( RST , RLT )  REE + RF     REE RLT   = αK β    REE + RF + RLT   rib + (1 − α )RST + REE RF   

(

(28.15)

)

For T  1, which mandates a sufficiently large Kβ in (28.11), the closed-loop gain collapses to Gv ( RST , RLT ) ≈

R 1 =1+ F f REE

(28.16)

which is independent of active element parameters. Moreover, to the extent that T  1 the series-shunt feedback amplifier behaves as an ideal voltage controlled voltage source in the sense that its closed-loop voltage gain is independent of source and load terminations. The fact that the series-shut feedback network behaves approximately as an ideal voltage amplifier implies that its closed-loop driving point input resistance is very large and its closed-loop driving point output resistance is very small. These facts are confirmed analytically by noting that

[

]

Rin = Rino 1 + f Gvo (0, RL ) ≈ f RinoG vo (0, RL )   REE = βK β   RLT + + R R R  EE F LT 

© 2003 by CRC Press LLC

(28.17)

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and Rout =

Routo Routo ≈ 1 + f Gvo ( RS , ∞) f Gvo ( RS , ∞) (28.18)

 R   r + (1 − α )RST + REE RF  = 1 + F   ib  R αK β   EE   

To the extent that the interstage biasing resistance, R, is sufficiently large to allow Kβ to approach β, observe that Rin in (28.17) is nominally proportional to β2, while Rout in (28.18) is inversely proportional to β.

Feed-Forward Compensation When practical design restrictions render the satisfaction of (28.10) difficult, feed-forward problems can be circumvented by inserting an emitter follower between the output port of transistor Q2 in the circuit diagram of Fig. 28.1(a) and the node to which the load termination and the input terminal of the feedback subcircuit are incident [2]. The resultant circuit diagram, inclusive now of simple biasing subcircuits, is shown in Fig. 28.4. The buffer transistor Q3 increases the original short-circuit forward current gain, Kββ, of the open-loop amplifier by a factor approaching (β + 1), while not altering the feed-forward factor implied by the feedback network in Fig. 28.1(a). In effect, Kβ is increased by a factor of almost (β + 1), thereby making (28.10) easy to satisfy. Because of the inherently low output resistance of an emitter follower, the buffer also reduces the driving-point output resistance achievable by the original configuration. The foregoing contentions can be confirmed through an analysis of the small-signal model for the modified amplifier in Fig. 28.4. Such an analysis is expedited by noting that the circuit to the left of the current controlled current source, KββI1A, in Fig. 28.3 remains applicable. For zero feedback, it follows that the small-signal current I1A flowing into the base of transistor Q1 derives from I1A VST

= f =0

1− α rib + (1 − α )RST + REE RF

(

(28.19)

)

The pertinent small-signal model for the buffered series-shunt feedback amplifier is resultantly the configuration offered in Fig. 28.5. +VOC R1 Q3

R Q2

Rin

Rout

Q1 VO RST REE

+ VST −

RF

R2

RLT

−VEE

FIGURE 28.4 A series-shunt feedback amplifier that incorporates an emitter follower output stage to reduce the effects of feed-forward through the feedback network. © 2003 by CRC Press LLC

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Rin rb

VI

I1A RST + VST

rπ

−

re (β+1)I1A

βI1A

REE//RF + f VO −

rb

Kβ β I1A

rπ

R1

βI

I re

f (β+1)I1A

R2

Rout VO

REE + RF

RLT

FIGURE 28.5 Small-signal model of the buffered series-shunt feedback amplifier.

Letting R′ = R2 ( REE + RF ) RLT

(28.20)

an analysis of the structure in Figure 28.5 reveals   VO R′ = (β + 1)  αK β R1 + f rib + (1 − α )R1 I1 A  R′ + rib + (1 − α )R1 

{

[

]}

(28.21)

which suggests negligible feed-forward for f

αK β R1

rib + (1 − α )R1

(28.22)

Note that for large R1, (28.22) implies the requirement f  βKβ, which is easier to satisfy than is (28.10).

Assuming the validity of (28.22), (28.21), and (28.19) deliver an open-loop voltage gain,. Gvo(RST , RLT), of

   R1 R′ Gvo ( RST , RLT ) = αK β     rib + (1 − α )RST + REE RF  R′ + rib + (1 − α )R1 

(28.23)

Recalling (28.1), which demonstrates that Kβ approaches β for large R, (28.23) suggests an open-loop gain that is nominally proportional to β2 if R1 is also large. © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 849 Sunday, October 6, 2002 5:16 PM

+VOC R1

Vbias

Q3 Q4 R Rin

Q2 Rout

Q1 CF

RST

VO

+ VST

−

−VEE REE

RF

R2

RLT

FIGURE 28.6 Buffered series-shunt feedback amplifier with common base cascode compensation of the common emitter amplifier formed by transistor Q2. A feedback zero is introduced by the capacitance CF to achieve acceptable closed-loop damping.

Using the concepts evoked by (28.17) and (28.18), the driving-point input and output impedances can now be determined. In a typical realization of the buffered series-shunt feedback amplifier, the resistance, R2, in Fig. 28.4 is very large because it is manifested as the output resistance of a common base current sink that is employed to stabilize the operating point of transistor Q3. For this situation, and assuming the resistance R1 is large, the resultant driving-point input resistance is larger than its predecessor input resistance by a factor of approximately (β + 1). Similarly, it is easy to show that for large R1 and large R2, the driving-point output resistance is smaller than that predicted by (28.18) by a factor approaching (β + 1). Although the emitter follower output stage in Fig. 28.4 all but eliminates feed-forward signal trans­ mission through the feedback network and increases both the driving point input resistance and output conductance, a potential bandwidth penalty is paid by its incorporation into the basic series-shunt feedback cell. The fundamental problem is that if R1 is too large, potentially significant Miller multipli­ cation of the base-collector transition capactiance of transistor Q2 materializes. The resultant capacitive loading at the collector of transistor Q1 is exacerbated by large R, which may produce a dominant pole at a frequency that is too low to satisfy closed-loop bandwidth requirements. The bandwidth problem may be mitigated by coupling resistance R1 to the collector of Q2 through a common base cascode. This stage appears as transistor Q4 in Fig. 28.6. Unfortunately, the use of the common base cascode indicated in Fig. 28.6 may produce an open-loop amplifier with transfer characteristics that do not emulate a dominant pole response. In other words, the frequency of the compensated pole established by capacitive loading at the collector of transistor Q1 may be comparable to the frequencies of poles established elsewhere in the circuit, and particularly at the base node of transistor Q1. In this event, frequency compensation aimed toward achieving acceptable closed-loop damping can be implemented by replacing the feedback resistor RF with the parallel combi­ nation of RF and a feedback capacitance, say CF, as indicated by the dashed branch in Fig. 28.6. The resultant frequency-domain feedback factor f (s) is  s   1+ z  f (s ) = f  fs  1 +   z  © 2003 by CRC Press LLC

(28.24)

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where f is the feedback factor given by (28.7) and z is the frequency of the introduced compensating zero, is z=

1 RFC F

(28.25)

The pole in (28.24) is inconsequential if the closed-loop amplifier bandwidth Bcl satisfies the restriction, f Bcl RF CF = Bcl(REE RF)CF 1.

28.3 Shunt-Series Feedback Amplifier Although the series-shunt circuit functions as a voltage amplifier, the shunt-series configuration (see the ac schematic diagram depicted in Fig. 28.7(a)) is best suited as a current amplifier. In the subject circuit, the Q2 emitter current, which is a factor of (1/α) of the output signal current, IO, is sampled by the feedback network formed of the resistances, REE and RF . The sampled current is fed back as a current in

V1F

Q1

Rout RLT

R I2F

I1F

RST

IST

IO

Q2

Ri

V2F RF REE FEEDBACK NETWORK (a) Rin V1F

rb

Rout

rb IW

IV IST

RST

rπ

β IV

IO

rπ

R

βIW

I1F

re

re V2F f IO

RLT

I2F REE//RF

REE + RF

+ α f V1F − − (b)

FIGURE 28.7 (a) AC schematic diagram of a bipolar shunt-series feedback amplifier. (b) Low-frequency smallsignal equivalent circuit of the feedback amplifier.

© 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 851 Sunday, October 6, 2002 5:16 PM

shunt with the amplifier input port. Because output current is fed back as a current to a current-driven input port, the resultant driving point output resistance is large, and the driving-point input resistance is small. These characteristics allow for a closed-loop current gain, G1(RST , RLT) = Io /IST , that is relatively independent of source and load resistances and insensitive to transistor parameters. In the series-shunt amplifier, h parameters were selected to model the feedback network because the topology of an h-parameter equivalent circuit is, similar to the amplifier in which the feedback network is embedded, a series shunt, or Thévenin–Norton, topology, In analogous train of thought compels the use of g-parameters to represent the feedback network in Fig. 28.7(a). With reference to the branch variables defined in the schematic diagram, 1   I1F   R + R F   =  EE V2F   REE  REE + RF 

−

REE  REE + RF  V1F    REF RF   I 2F   

(28.26)

Noting that the feedback network current, I2F , relates to the amplifier output current, IO , in accordance with I 2F = −

IO α

(28.27)

and letting the feedback factor, f, be f =

1  RΕΕ  α  RΕΕ + RF 

(28.28)

the small-signal equivalent circuit of shunt-series feedback amplifier becomes the network diagrammed in Fig. 28.7(b). Note that the voltage controlled voltage source, αf V1F , models the feed-forward transfer mechanism of the feedback network, where the controlling voltage, V1F , is

[

]

V1F = rb + rπ + (β +1)rc IV = (β +1)rib IV

(28.29)

An analysis of the model in Fig. 28.7(b) confirms that the second-stage, signal-base current Iw relates to the first-stage, signal-base current Iv as α( R + frib ) IW =− IV rib + REE RF + (1 − α )R

(28.30)

For f

R rib

(28.31)

which offsets feed-forward effects, IW αR ∆ ≈− = − Kr IV rib + REE RF + (1 − α )R

(28.32)

Observe that the constant Kr tends toward β for large R, as can be verified by an inspection of Fig. 28.7(b). © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 852 Sunday, October 6, 2002 5:16 PM

Using (28.32), the open-loop current gain, found by setting f to zero, is

GIO ( RST , RLT ) =

IO I ST

 RST ( REE + RF )  = αK r   rib + (1 − α ) RST ( REE + RF ) f =0

[

]

   

(28.33)

and, recalling (28.28), the loop gain T is T = fGIO ( RST , RLT ) =

1  REE  G (R , R ) α  REE + RF  IO ST LT

   REE RST = Kr    REE + RF + RST   rib + (1 − α ) RST ( REE + RF ) 

[

]

   

(28.34)

By inspection of the model in Fig. 28.7(b), the open-loop input resistance, Rino , is

[

Rino = ( REE + RF ) (β +1)rib

]

(28.35)

and, within the context of an infinitely large Early resistance, the open-loop output resistance, Routo , is infinitely large. The closed-loop current gain of the shunt-series feedback amplifier is now found to be G1 ( RST , RLT ) =

GIO ( RST , RLT ) 1+T

 R  ≈ α 1 + F   REE 

(28.36)

where the indicated approximation exploits the presumption that the loop gain T is much larger than one. As a result of the large loop-gain assumption, note that the closed-loop gain is independent of the source and load resistances and is invulnerable to uncertainties and perturbations in transistor param­ eters. The closed-loop output resistance, which exceeds its open-loop counterpart, remains infinitely large. Finally, the closed-loop driving point input resistance of the shunt-series amplifier is

Rin =

 Rino R  r ≈ 1 + F  ib 1 + f GIO (∞, RLT )  REE  K r

(28.37)

28.4 Shunt-Shunt Feedback Amplifier Circuit Modeling and Analysis The ac schematic diagram of the third type of single-loop feedback amplifier, the shunt-shunt triple, is drawn in Fig. 28.8(a). A cascade interconnection of three transistors Q1, Q2, and Q3, forms the open loop, while the feedback subcircuit is the single resistance, RF. This resistance samples the output voltage, VO, as a current fed back to the input port. Output voltage is fed back as a current to a current-driven input port, so both the driving point input and output resistances are very small. Accordingly, the circuit operates best as a transresistance amplifier in that its closed-loop transresistance, RM (RST, RLT) = VO /IST, is nominally invariant with source resistance, load resistance, and transistor parameters. The shunt-shunt nature of the subject amplifier suggests the propriety of y-parameter modeling of the feedback network. For the electrical variables indicated in Fig. 28.8(a), © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 853 Sunday, October 6, 2002 5:16 PM

FEEDBACK NETWORK

RF

I1F

I2F Rout VO

Rin Q1

Q2

Q3

V1F RST

IST

R1

RLT

R2

(a)

Rout

Rin VO

V1F I1F IST

IV

RST f VO

RF

K∈βIV

I2F

(β + 1)rib f V1F

RF

RLT

(b)

FIGURE 28.8 (a) AC schematic diagram of a bipolar shunt-shunt feedback amplifier. (b) Low-frequency smallsignal equivalent circuit of the feedback amplifier.

 1  I1F   R  = F I 2F  − 1  RF

1  RF  V1F    1  V   O RF 

−

(28.38)

which implies that a resistance, RF , loads both the input and the output ports of the open-loop threestage cascade. The short-circuit admittance relationship in (28.38) also suggests a feedback factor, f, given by f =

1 RF

(28.39)

The foregoing observations and the small-signal modeling experience gained with the preceding two feedback amplifiers lead to the equivalent circuit submitted in Fig. 28.8(b). For analytical simplicity, the model reflects the assumption that all three transistors in the open loop have identical small-signal parameters. Moreover, the constant, Kε, which symbolizes the ratio of the signal base current flowing into transistor Q3 to the signal base current conducted by transistor Q1, is given by    αR1 αR2 K∈ =     rib + (1 − α ) R1   rib + (1 − α ) R2 

(28.40)

Finally, the voltage-controlled current source, f V1F , accounts for feed-forward signal transmission through the feedback network. If such feed-forward is to be negligible, the magnitude of this controlled current © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 854 Sunday, October 6, 2002 5:16 PM

must be significantly smaller than KεβIv , a current that emulates feed-forward through the open-loop amplifier. Noting that the input port voltage, V1F , in the present case remains the same as that specified by (28.29), negligible feed-forward through the feedback network mandates RF 

rib αK ε

(28.41)

Because the constant Kε in (28.40) tends toward β2 if R1 and R2 are large resistances, (28.41) is relatively easy to satisfy. With feed-forward through the feedback network ignored, an analysis of the model in Fig. 28.8(b) provides an open-loop transresistance, RMO(RST, RLT), of  RF RST RMO ( RST , RLT ) = −αK ε   rib (1 − α ) RF RST 

(

  RF RLT  

)(

)

(28.42)

while the loop gain is T = fRMO ( RST , RLT ) = −

RMO ( RST , RLT ) RF

RF RST  RST   = αK ε   R R +  − r 1 α ) RF RST F  ib (  ST 

(

)

   

(28.43)

For T  1, the corresponding closed-loop transresistance RM (RST, RLT) is RM ( RST , RLT ) =

RMO ( RST , RLT ) 1+T

≈ −RF

(28.44)

Finally, the approximate driving-point input and output resistances are, respectively,  r  R  Rin ≈  ib  1 + F   αK ε   RLT 

(

 r + (1 − α ) R R ib F ST Rout ≈  αK ε  

(28.45)

)  1 + R   

 F RST 

(28.46)

Design Considerations Because the shunt-shunt triple uses three gain stages in the open-loop amplifier, its loop gain is signifi­ cantly larger than the loop gains provided by either of the previously considered feedback cells. Accord­ ingly, the feedback triple affords superior desensitization of the closed-loop gain with respect to transistor parameters and source and load resistances; but the presence of a cascade of three common emitter gain stages in the open loop of the amplifier complicates frequency compensation and limits the 3-dB band­ width. The problem is that, although each common emitter stage approximates a dominant pole amplifier, none of the critical frequencies in the cluster of poles established by the cascade interconnection of these units is likely to be dominant. The uncompensated closed loop is therefore predisposed to unacceptable underdamping, thereby making compensation via an introduced feedback zero difficult. At least three compensation techniques can be exploited to optimize the performance of the shuntshunt feedback amplifier [3], [7–9]. The first of these techniques entail pole splitting of the open-loop © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 855 Sunday, October 6, 2002 5:16 PM

CF Rout

RF

CC

VO

Rin Q1

Q2

RST

IST

Q3 RLT

R2

R1

FIGURE 28.9 AC schematic diagram of a frequency compensated shunt-shunt triple. The capacitance, Cc , achieves open-loop pole splitting, while the capacitance, CF , implements a compensating feedback network zero.

interstage through the introduction of a capacitance, Cc, between the base and the collector terminals of transistor Q2, as depicted in the ac schematic diagram of Fig. 28.9. In principle, pole splitting can be invoked on any one of the three stages of the open loop; but pole splitting of the interstage is most desirable because such compensation of the first stage proves effective only for large source resistance. Moreover, the resultant dominant pole becomes dependent on the source termination. On the other hand, pole splitting of the third stage produces a dominant pole that is sensitive to load termination. In conjunction with pole splitting, a feedback zero can be introduced, if necessary, to increase closed-loop damping by replacing the feedback resistance, RF, by the parallel combination of RF and a feedback capacitance, CF , as illustrated in Fig. 28.9. This compensation produces left-half-plane zero in the feedback factor at s = –(1/RF ). A second compensation method broadbands the interstage of the open-loop amplifier through local current feedback introduced by the resistance, RX , in Fig. 28.10. Simultaneously, the third stage is broadbanded by way of a common base cascode transistor Q4. Because emitter degeneration of the interstage reduces the open-loop gain, an emitter follower (transistor Q5) is embedded between the feedback VO

RF CF

Rout Q5

Q4

RLT

Rin Q1

IST

RST

Q3

Q2

R1

RX

R2

FIGURE 28.10 AC schematic diagram of an alternative compensation scheme for the shunt-shunt triple. Transistor Q2 is broadbanded by the emitter degeneration resistance RX and transistor Q3 is broadbanded by the common base cascode transistor Q4. The emitter follower transistor, Q5, minimizes feed-forward signal transmission through the feedback network. © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 856 Sunday, October 6, 2002 5:16 PM

RF

Rout

Q3A CF Rin

Q2A Q1A

R2

R1

+ IST

RST

VO

RLT

−

Q1B

R1 Q2B

CF

R2 Q3B

RF

FIGURE 28.11 AC schematic diagram of a differential realization of the compensated shunt-shunt feedback ampli­ fier. The balanced stage boasts improved bandwidth over its single-ended counterpart because of its use of only two high-gain stages in the open loop. The emitter follower pair Q3A and Q3B diminishes feed-forward transmission through the feedback network composed of the shunt interconnection of resistor RF with capacitor CF .

network and the output port of the open-loop third stage. As in the case of the series-shunt feedback amplifier, the first-order effect of this emitter follower is to increase feed-forward signal transmission through the open-loop amplifier by a factor that approaches (β + 1). A final compensation method is available if shunt-shunt feedback is implemented as the balanced differential architecture (see the ac schematic diagram offered in Fig. 28.11). By exploiting the antiphase nature of opposite collectors in a balanced common emitter topology, a shunt-shunt feedback amplifier can be realized with only two gain stages in the open loop. The resultant closed loop 3-dB bandwidth is invariably larger than that of its three-stage single-ended counterpart, because the open loop is now characterized by only two, as opposed to three, fundamental critical frequencies. Because the forward gain implicit to two amplifier stages is smaller than the gain afforded by three stages of amplification, a balanced emitter follower (transistors Q3A and Q3B) is incorporated to circumvent the deleterious relative effects of feed-forward signal transmission through the feedback network.

28.5 Series-Series Feedback Amplifier Figure 28.12(a) is the ac schematic diagram of the series-series feedback amplifier. Three transistors, Q1, Q2, and Q3, are embedded in the open-loop amplifier, while the feedback subcircuit is the wye config­ uration formed of the resistances RX, RY , and RZ . Although it is possible to realize series-series feedback via emitter degeneration of a single-stage amplifier, the series-series triple offers substantially more loop gain and thus better desensitization of the forward gain with respect to both transistor parameters and source and load terminations.

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0912 S1-S8 Frame55.book Page 857 Sunday, October 6, 2002 5:16 PM

IV

Q1

Q2 R1

RST + VST

Rin

IO

Q3

Rout RLT

R2

I1F

I2F

− RX

RY RZ

V1F

V2F FEEDBACK NETWORK

(a) Rout

rb

IV

IW (β+1)rib

RST + VST −

Rin

K1 β IV

IO RLT

V1F

re

I1F β IV

βIW

rπ

R2

V2F

RX +RZ +

I2F RY +RZ

f IO

−

−

+ −

f β IV

(b)

FIGURE 28.12 (a) AC schematic diagram of a bipolar series-series feedback amplifier. (b) Low-frequency, smallsignal equivalent circuit of the feedback amplifier.

In Fig. 28.12(a), the feedback wye senses the Q3 emitter current, which is a factor of (1/α) of the output signal current Io . This sampled current is fed back as a voltage in series with the emitter of Q1. Because output current is fed back as a voltage to a voltage-driven input port, both the driving point input and output resistances are large. The circuit is therefore best suited as a transconductance amplifier in the sense that for large loop gain, its closed-loop transconductance, GM (RST , RLT) = IO /VST , is almost independent of the source and load resistances. The series-series topology of the subject amplifier conduces z-parameter modeling of the feedback network. Noting the electrical variables delineated in the diagram of Fig. 28.12(a), V1F  RX + RZ  = V2F   RZ

I1F    RY + RZ  I 2F  RZ

(28.47)

Equation (28.47) suggests that the open-circuit feedback network resistances loading the emitters of transistors Q1 and Q3 are (RX + RZ ) and (RY + RZ ), respectively, and the voltage fed back to the emitter of transistor Q1 is RZ I2F . Because the indicated feedback network current I2F is (–IO /α), this fed back voltage is equivalent to (–RZ IO /α), which suggests a feedback factor, f, of

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0912 S1-S8 Frame55.book Page 858 Sunday, October 6, 2002 5:16 PM

f =

RZ α

(28.48)

Finally, the feed-forward through the feedback network if RZ I1F . Because I1F relates to the signal base current IV flowing into transistor Q1 by I1F = (β + 1)Iv , this feed-forward voltage is also expressible as (–f βIv ). The foregoing observations and the hybrid-pi method of a bipolar junction transistor produce the small-signal model depicted in Fig. 28.12(b). In this model, all transistors are presumed to have identical corresponding small-signal parameters, and the constant, K1, is K1 =

αR1 rib + (1 − α )R1

(28.49)

An analysis of the model of Fig. 28.12(b) confirms that the ratio of the signal current, IW , flowing into the base of transistor Q3 to the signal base current, IV , of transistor Q1 is  f  αK1R2 1 +  IW  K1R2  = IV rib + RY + RZ + (1 − α )R2

(28.50)

This result suggests that feed-forward effects through the feedback network are negligible if  f   K1R2, which requires RZ αK1R2

(28.51)

In view of the fact that the constant, K1, approaches β for large values of the resistance, R1, (28.51) is not a troublesome inequality. Introducing a second constant, K2, such that ∆

K2 =

αR2 rib + RY + RZ + (1 − α )R2

(28.52)

the ratio IW /IV in (28.50) becomes IW ≈ K1 K 2 IV

(28.53)

assuming (28.51) is satisfied. Given the propriety of (28.50) and using (28.53) the open-loop transconductance, GMO(RST , RLT) is found to be   αK1K 2 GMO ( RST , RLT ) = −    rib + RX + RZ + (1 − α )RST 

(28.54)

and recalling (28.48), the loop gain T is K1K 2 RZ R  T = − Z  GMO ( RST , RLT ) =  α rib + RX + RZ + (1 − α )RST

(28.55)

It follows that for T  1, the closed-loop transconductance is GM ( RST , RLT ) = © 2003 by CRC Press LLC

GMO ( RST , RLT ) 1+T

≈−

α RZ

(28.56)

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Rout

Cc Rin Q1

Q2

Q3 R2

R1

RST

IO RLT

+ VST −

CF

RX

RY RZ

FIGURE 28.13 AC schematic diagram of a frequency compensated series-series feedback triple. The capacitance, Cc, achieves pole splitting in the open-loop configuration, while the capacitance, CF , introduces a zero in the feedback factor of the closed-loop amplifier.

The Early resistance is large enough to justify its neglect, so the open-loop, and thus the closed-loop, driving-point output resistances are infinitely large. On the other hand, the closed-loop driving point input resistance Rin can be shown to be

[

]

Rin = Rino 1 + f GMO (0, RLT ) ≈ (β +1)K1K 2 RZ

(28.57)

Similar to its shunt-shunt counterpart, the series-series feedback amplifier uses three open-loop gain stages to produce large loop gain. However, also similar to the shunt-shunt triple, frequency compensation via an introduced feedback zero is difficult unless design care is exercised to realize a dominant pole open-loop response. To this end, the most commonly used compensation is pole splitting in the open loop, combined, if required, with the introduction of a zero in the feedback factor. The relevant ac schematic diagram appears in Fig. 28.13 where the indicated capacitance, Cc , inserted across the basecollector terminals of transistor Q3 achieves the aforementioned pole splitting compensation. The capac­ itance, CF, in Fig. 28.13 delivers a frequency-dependent feedback factor, f (s) of   s   + 1   z f (s ) = f    RZ 1 + s   z  R + R R   Z X Y  

(28.58)

where the frequency z of the introduced zero derives from  R R  1 = ( RX + RY )1 + X Y  C F z RZ  

(28.59)

The corresponding pole in (28.58) is insignificant if the closed-loop amplifier is designed for a bandwidth, Bcl that satisfies the inequality, Bc1(RX + RY)CF  1. As is the case with shunt-shunt feedback, an alternative frequency compensation scheme is available if series-series feedback is implemented as a balanced differential architecture. The pertinent ac schematic © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 860 Sunday, October 6, 2002 5:16 PM

Q2A

Rin

Rout

Q1A

R

RF

IO RST +

CF RU

RV

RU

RV

RLT

VST −

CF

RF Q1B

R Q2B

FIGURE 28.14 AC schematic diagram of a balanced differential version of the series-series feedback amplifier. The circuit utilizes only two, as opposed to three, gain stages in the open loop.

I1F

RX

RY

V1F

I2F

RF

I1F

I2F

V2F V1F RZ

V2F RU

RV

FIGURE 28.15 Transformation of the wye feedback subcircuit used in the amplifier of Fig. 28.13 to the delta subcircuit exploited in Fig. 28.14. The resistance transformation equations are given by (28.60)–(28.62).

diagram, inclusive of feedback compensation, appears in Fig. 28.14. This diagram exploits the fact that the feedback wye consisting of the resistances, RX , RY , and RZ as utilized in the single-ended configurations of Figs. 28.12(a) and 28.13 can be transformed into the feedback delta of Fig. 28.15. The terminal voltampere characteristics of the two networks in Fig. 28.15 are identical, provided that the delta subcircuit elements, RF , RU , and RV , are chosen in accordance with

© 2003 by CRC Press LLC

 R R  RF = ( RX + RY )1 + X Y  RZ  

(28.60)

RU RZ = RF RY

(28.61)

RV RZ = RF RX

(28.62)

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28.6 Dual-Loop Feedback As mentioned previously, a simultaneous control of the driving point I/O resistances, as well as the closedloop gain, mandates the use of dual global loops comprised of series and shunt feedback signal paths. The two global dual-loop feedback architectures are the series-series/shunt-shunt feedback amplifier and the series-shunt/shunt-series feedback amplifier. In the following subsections, both of these units are studied by judiciously applying the relevant analytical results established earlier for pertinent singleloop feedback architectures. The ac schematic diagrams of these respective circuit realizations are pro­ vided, and engineering design considerations are offered.

Series-Series/Shunt-Shunt Feedback Amplifier Figure 28.16 is a behavioral abstraction of the series-series/shunt-shunt feedback amplifier. Two port z parameters are used to model the series-series feedback subcircuit, for which feed-forward is tacitly ignored and the feedback factor associated with its current controlled voltage source is fss. On the other hand, y parameters model the shunt-shunt feedback network, where the feedback factor relative to its voltage controlled current source is fpp . As in the series-series network, feed-forward in the shunt-shunt subcircuit is presumed negligible. The four-terminal amplifier around which the two feedback units are connected has an open loop (meaning fss = 0 and fpp = 0, but with the loading effects of both feedback circuits considered) transconductance of GMO (RST, RLT). With fpp set to zero to deactivate shunt-shunt feedback, the resultant series-series feedback network is a transconductance amplifier with a closed-loop transconductance, GMS (RST , RLT), is GMS ( RST , RLT ) =

IO GMO(RST , RLT ) 1 = ≈ VST 1 + fssGMO ( RST , RLT ) fss

(28.63)

where the loop gain, fssGMO (RST, RLT), is presumed much larger than one, and the loading effects of both the series-series feedback subcircuit and the deactivated shunt-shunt feedback network are incorporated

Shunt-Shunt Feedback

fppVO

Amplifier +

RST

VO + VST

−

RLT

− + fss IO

IO

− Series-Series Feedback

FIGURE 28.16 System-level diagram of a series-series/shunt-shunt dual-loop feedback amplifier. Note that feedforward signal transmission through either feedback network is ignored.

© 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 862 Sunday, October 6, 2002 5:16 PM

into GMO(RST , RLT). The transresistance, RMS(RST , RLT), implied by (28.63), which expedites the study of the shunt-shunt component of the feedback configuration, is RMS ( RST , RLT ) =

VO I R R = RST RLT O ≈ ST LT I ST VST fss

(28.64)

The series-series feedback input and output resistances Rins and Routs , respectively, are large and given by

[

]

[

]

Rins = Rino 1 + fssGMO (0, RLT )

(28.65)

and Routs = Routo 1 + fssGMO ( RST ,0)

(28.66)

where the zero feedback (fss = 0 and fpp = 0) values, Rino and Routo , of these driving point quantities are computed with due consideration given to the loading effects imposed on the amplifier by both feedback subcircuits. When shunt-shunt feedback is applied around the series-series feedback cell, the configuration becomes a transresistance amplifier. The effective open-loop transresistance is RMS(RST, RLT), as defined by (28.64). Noting a feedback of fpp , the corresponding closed-loop transresistance is RST RLT fss RM ( RST , RLT ) ≈ R R  1 + f pp  ST LT   fss 

(28.67)

which is independent of amplifier model parameters, despite the unlikely condition of an effective loop gain fpp RST RLT /fss that is much larger than one. It should be interjected, however, that (28.67) presumes negligible feed-forward through the shunt-shunt feedback network. This presumption may be inappro­ priate owing to the relatively low closed-loop gain afforded by the series-series feedback subcircuit. Ignoring this potential problem temporarily, (28.67) suggests a closed-loop voltage gain AV (RST , RLT) of AV ( RST , RLT ) =

VO RM ( RST , RLT ) RLT = ≈ VS RST fss + f pp RST RLT

(28.68)

The closed-loop, driving-point output resistance Rout , can be straightforwardly calculated by noting that the open circuit (RLT → ∞) voltage gain, AVO , predicted by (28.68) is AVO = 1/fpp RST . Accordingly, (28.68) is alternatively expressible as AV ( RST , RLT ) ≈ AVO

RLT    fss    RLT + f pp RST  

(28.69)

Because (28.69) is a voltage divider relationship stemming from a Thévenin model of the output port of the dual-loop feedback amplifier, as delineated in Fig. 28.17, it follows that the driving-point output resistance is Rout ≈

© 2003 by CRC Press LLC

fss f pp RST

(28.70)

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RST

1

3

+ VST

+

Series-Series/ Shunt-Shunt Amplifier

−

VO

RLT

−

2

4

Rin I

1

Rout

3

AVOVS

VO

+

RST RINS

+

fppVO

+

−

VST − 2

RLT

−

4

FIGURE 28.17 Norton equivalent input and Thévenin equivalent output circuits for the series-series/shunt-shunt dual-loop feedback amplifier.

Observe that, similar to the forward gain characteristics, the driving-point output resistance is nominally insensitive to changes and other uncertainties in open-loop amplifier parameters. Moreover, this output resistance is directly proportional to the ratio fss /fpp of feedback factors. As is illustrated in preceding sections, the individual feedback factors, and thus the ratio of feedback factors, is likely to be proportional to a ratio of resistances. In view of the fact that resistance ratios can be tightly controlled in a monolithic fabrication process, Rout in (28.70) is accurately prescribed for a given source termination. The driving-point input resistance Rin can be determined from a consideration of the input port component of the system level equivalent circuit depicted in Fig. 28.17. This resistance is the ratio of VST to I, under the condition of RS = 0. With RS = 0, (28.68) yields VO = RLTVST /fss and thus, Kirchhoff ’s voltage law (KVL) applied around the input port of the model at hand yields Rin =

Rins fss ≈ f pp RLT Rins f pp RLT 1+ fss

(28.71)

where the “open-loop” input resistance Rins , defined by (28.65), is presumed large. Similar to the drivingpoint output resistance of the series-series/shunt-shunt feedback amplifier, the driving-point input resis­ tance is nominally independent of open-loop amplifier parameters. It is interesting to observe that the input resistance in (28.71) is inversely proportional to the load resistance by the same factor (fss /fpp) that the driving-point output resistance in (28.70) is inversely proportional to the source resistance. As a result, fss ≈ Rin RLT ≡ Rout RST f pp

(28.72)

Thus, in addition to being stable performance indices for well-defined source and load terminations, the driving-point input and output resistances track one another, despite manufacturing uncertainties and changes in operating temperature that might perturb the individual values of the two feedback factors fss and fpp .

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The circuit property stipulated by (28.72) has immediate utility in the design of wideband commu­ nication transceivers and other high-speed signal-processing systems [10–14]. In these and related appli­ cations, a cascade of several stages is generally required to satisfy frequency response, distortion, and noise specifications. A convenient way of implementing a cascade interconnection is to force each member of the cascade to operate under the match terminated case of RST = Rin = RLT = Rout =∆ R. From (28.72) match terminated operation demands feedback factors selected so that R=

fss f pp

(28.73)

which forces a match terminated closed-loop voltage gain A∗V of AV∗ ≈

1 1 = 2 f pp R 2 f pp fss

(28.74)

The ac schematic diagram of a practical, single-ended series-series/shunt-shunt amplifier is submitted in Fig. 28.18. An inspection of this diagram reveals a topology that coalesces the series-series and shuntshunt triples studied earlier. In particular, the wye network formed of the three resistances, RXx, RY , and RZ , comprises the series-series component of the dual-loop feedback amplifier. The capacitor, Cc, nar­ rowbands the open-loop amplifier to facilitate frequency compensation of the series-series loop through the capacitance, CF1. Compensated shunt feedback of the network is achieved by the parallel combination of the resistance, RF and the capacitance, CF2. If CF1 and Cc combine to deliver a dominant pole seriesseries feedback amplifier, CF2 is not necessary. Conversely, CF1 is superfluous if CF2 and Cc interact to provide a dominant pole shunt-shunt feedback amplifier. As in the single ended series-series configura­ tion, transistor Q3 can be broadbanded via a common base cascode. Moreover, if feedback through the feedback networks poses a problem, an emitter follower can be inserted at the port to which the shunt feedback path and the load termination are incident. CF2

RF

Rout

Cc

VO

Rin Q2

Q1

Q3 R2

R1

RST

IO RLT

+ VST −

CF1

RY

RX RZ

FIGURE 28.18 AC schematic diagram of a frequency-compensated, series-series/shunt-shunt, dual-loop feedback amplifier. The compensation is affected by the capacitances CF1 and CF2, while Cc achieves pole splitting in the openloop amplifier. © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 865 Sunday, October 6, 2002 5:16 PM

A low-frequency analysis of the circuit in Fig. 28.18 is expedited by assuming high beta transistors having identical corresponding small-signal model parameters. This analysis, which in contrast to the simplified behavioral analysis, does not ignore the electrical effects of the aforementioned feed-forward through the shunt-shunt feedback network, yields a voltage gain AV (RST , RLT), of  Rin  RLT  αRF  −1 AV ( RST , RLT ) ≈ −     Rin + RST   RLT + RF   RZ

(28.75)

where the driving-point input resistance of the amplifier Rin is Rin ≈

RF + RLT αR 1 + LT RZ

(28.76)

The driving-point output resistance Rout is Rout ≈

RF + RST αR 1 + ST Rz

(28.77)

As predicted by the behavioral analysis Rin, Rout, and AV (RST , RLT), are nominally independent of transistor parameters. Observe that the functional dependence of Rin on the load resistance, RLT , is identical to the manner in which Rout is related to the source resistance RST . In particular, Rin ≡ Rout if RST ≡ RLT . For the match terminated case in which RST = Rin = RLT = Rout =∆ R, R≈

RF RZ α

(28.78)

The corresponding match terminated voltage gain in (28.75) collapses to  R − R AV∗ ≈ − F   2R 

(28.79)

Similar to the series-series and shunt-shunt triples, many of the frequency compensation problems implicit to the presence of three open-loop stages can be circumvented by realizing the series-series/shunt­ shunt amplifier as a two-stage differential configuration. Figure 28.19 is the acschematic diagram of a compensated differential series-series/shunt-shunt feedback dual.

Series-Shunt/Shunt-Series Feedback Amplifier The only other type of global dual loop architecture is the series-shunt/shunt-series feedback amplifier; the behavioral diagram appears in Fig. 28.20. The series-shunt component of this system, which is modeled by h-parameters, has a negligibly small feed-forward factor and a feedback factor of fsp . Hybrid g-parameters model the shunt-series feedback structure, which has a feedback factor of fps and a presum­ ably negligible feed-forward factor. The four-terminal amplifier around which the two feedback units are connected has an open-loop (meaning fsp = 0 and fps = 0, but with the loading effects of both feedback circuits considered) voltage gain of AVO(RST, RLT). For fps = 0, the series-shunt feedback circuit voltage gain AVS (RST, RLT), is AVS ( RST , RLT ) = © 2003 by CRC Press LLC

AVO ( RST , RLT ) VO 1 = ≈ VST 1 + fsp AVO ( RST , RLT ) fsp

(28.80)

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RF2 Rout CF2

Rin

Q2A

Q1A

R

RF1

+

CF1

RST

RU

+

VO

RV

RLT

−

VST −

RU

RV

IO

CF1

RF1 Q1B

R Q2B CF2

RF2

FIGURE 28.19 AC schematic diagram of the differential realization of a compensated series-series/shunt-shunt feedback amplifier.

Shunt-Shunt Feedback

fps IO + VO

RLT

− Amplifier

IO

RST + VST

−

+ fspVO − Series-Series Feedback

FIGURE 28.20 System level diagram of a series-shunt/shunt-series, dual-loop feedback amplifier. Note that feedforward signal transmission through either feedback network is ignored.

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0912 S1-S8 Frame55.book Page 867 Sunday, October 6, 2002 5:16 PM

where the approximation reflects an assumption of a large loop gain. When the shunt-series component of the feedback amplifier is activated, the dual-loop configuration functions as a current amplifier. Its effective open-loop transfer function is the current gain, AIS (RST, RLT), established by the series-shunt amplifier; namely, AIS ( RST , RLT ) =

IO  RST  VO R ≈ ST =  I ST  RLT  VST fsp RLT

(28.81)

It follows that the current gain, AI (RST , RLT), of the closed loop is RST fsp RLT RST = AI ( RST , RLT ) ≈  R  fsp RLT + f ps RST 1 + f ps  ST   fsp RLT 

(28.82)

while the corresponding voltage gain, AV (RST , RLT), assuming negligible feed-forward through the shuntseries feedback network, is AV ( RST , RLT ) =

RLT RLT AI ( RST , RLT ) ≈ RST fsp RLT + f ps RST

(28.83)

Repeating the analytical strategy employed to determine the input and output resistances of the seriesseries/shunt-shunt configuration, (28.83) delivers a driving-point input resistance of Rin ≈

fsp RLT

(28.84)

f ps

and a driving-point output resistance of Rout ≈

f ps RST

(28.85)

fsp

Similar to the forward voltage gain, the driving-point input and output resistances of the seriesshunt/shunt-series feedback amplifier are nominally independent of active element parameters. Note, how­ ever, that the input resistance is directly proportional to the load resistance by a factor (fsp /fps ), which is the inverse of the proportionality constant that links the output resistance to the source resistance. Specifically, fsp f ps

=

Rin RST = RLT Rout

(28.86)

Thus, although Rin and Rout are reliably determined for well-defined load and source terminations, they do not track one another as well as they do in the series-series/shunt-shunt amplifier. Using (28.86), the voltage gain in (28.83) is expressible as AV ( RST , RLT ) ≈

© 2003 by CRC Press LLC

1 

R R  fsp 1 + out ST   R in RLT  

(28.87)

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Rout VO

Rin

Q2 Q1

RST

RLT

R

RF2 +

VST

RF1

−

REE1

REE2

FIGURE 28.21 AC schematic diagram of a series-shunt/shunt-series, dual-loop feedback amplifier.

The simplified ac schematic diagram of a practical series-shunt/shunt-series feedback amplifier appears in Fig. 28.21. In this circuit, series-shunt feedback derives from the resistances, REE1 and RF1, and shuntseries feedback is determined by the resistances, REE2 and RF2 . Because this circuit topology merges the series-shunt and shunt-series pairs, requisite frequency compensation, which is not shown in the subject figure, mirrors the relevant compensation schemes studied earlier. Note, however, that a cascade of only two open-loop gain stages renders compensation easier to implement and larger 3-dB bandwidths easier to achieve in the series-series/shunt-shunt circuit, which requires three open-loop gain stages for a singleended application. For high beta transistors having identical corresponding small-signal model parameters, a low-fre­ quency analysis of the circuit in Fig. 28.21 gives a voltage gain of  αRin   R  1 + F1  AV ( RST , RLT ) ≈     Rin + αRS   REE1 

(28.88)

where the driving-point input resistance, Rin, of the subject amplifier is   R 1 + F2   REE2  Rin ≈ αRLT   1 + RF1 + RLT   REE1 REE1 REE2  

(28.89)

The driving-point output resistance, Rout, is

Rout

© 2003 by CRC Press LLC

  R 1 + F1   REE1  ≈ RST   1 + RF2 + RST   REE2 REE1 REE2  

(28.90)

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28.7 Summary This section documents small-signal performance equations, general operating characteristics, and engi­ neering design guidelines for the six most commonly used global feedback circuits. These observations derive from analyses based on the judicious application of signal flow theory to the small-signal model that results when the subject feedback network is supplanted by an appropriate two-port parameter equivalent circuit. Four of the six fundamental feedback circuits are single-loop architectures. 1. The series-shunt feedback amplifier functions best as a voltage amplifier in that its input resistance is large, and its output resistance is small. Because only two gain stages are required in the open loop, the amplifier is relatively easy to compensate for acceptable closed-loop damping and features potentially large 3-dB bandwidth. A computationally efficient analysis aimed toward determining loop gain, closed-loop gain, I/O resistances, and the condition that renders feed-forward through the feedback network inconsequential is predicated on replacing the feedback subcircuit with its h-parameter model. 2. The shunt-series feedback amplifier is a current amplifier in that its input resistance is small, and its output resistance is large. Similar to its series-shunt dual, only two gain stages are required in the open loop. Computationally efficient analyses are conducted by replacing the feedback subcircuit with its g-parameter model. 3. The shunt-shunt feedback amplifier is a transresistance signal processor in that both its input and output resistances are small. Although this amplifier can be realized theoretically with only a single open-loop stage, a sufficiently large loop gain generally requires a cascade of three open-loop stages. As a result, pole splitting is invariably required to ensure an open-loop dominant pole response, thereby limiting the achievable closed-loop bandwidth. In addition compensation of the feedback loop may be required for acceptable closed-loop damping. The bandwidth and stability problems implicit to the use of three open-loop gain stages can be circumvented by a balanced differential realization, which requires a cascade of only two open-loop gain stages. Computationally efficient analyses are conducted by replacing the feedback subcircuit with its y-parameter model. 4. The series-series feedback amplifier is a transconductance signal processor in that both its input and output resistances are large. Similar to its shunt-shunt counterpart, its implementation gen­ erally requires a cascade of three open-loop gain stages. Computationally efficient analyses are conducted by replacing the feedback subcircuit with its z-parameter model. The two remaining feedback circuits are dual-loop topologies that can stabilize the driving-point input and output resistances, as well as the forward gain characteristics, with respect to shifts in active element parameters. One of these latter architectures, the series-series/shunt-shunt feedback amplifier, is partic­ ularly well suited to electronic applications that require a multistage cascade. 1. The series-series/shunt-shunt feedback amplifier coalesces the series-series architecture with its shunt-shunt dual. It is particularly well suited to applications, such as wideband communication networks, which require match terminated source and load resistances. Requisite frequency com­ pensation and broadbanding criteria mirror those incorporated in the series-series and shuntshunt single-loop feedback topologies. 2. The series-shunt/shunt-series feedback amplifier coalesces the series-shunt architecture with its shunt-series dual. Although its input resistance can be designed to match the source resistance seen by the input port of the amplifier, and its output resistance can be matched to the load resistance driven by the amplifier, match terminated operating (Rin = RST = RLT = Rout) is not feasible. Requisite frequency compensation and broadbanding criteria mirror those incorporated in the series-shunt and shunt-series single-loop feedback topologies.

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References [1] J. Millman and A. Grabel, Microelectronics, 2nd ed., New York: McGraw-Hill, 1987, chap. 12. [2] A. B. Grebene, Bipolar and MOS Analog Integrated Circuit Design, New York: Wiley-Interscience, 1984, pp. 424–432. [3] R. G. Meyer, R. Eschenbach, and R. Chin, “A wideband ultralinear amplifier from DC to 300 MHz,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 167–175, Aug. 1974. [4] A. S. Sedra and K. C. Smith, Microelectronic Circuits, New York: Holt, Rinehart Winston, 1987, pp. 428–441. [5] J. M. Early, “Effects of space-charge layer widening in junction transistors,” Proc. IRE, vol. 46, pp. 1141–1152, Nov. 1952. [6] A. J. Cote Jr. and J. B. Oakes, Linear Vacuum-Tube And Transistor Circuits, New York: McGrawHill, 1961, pp. 40–46. [7] R. G. Meyer and R. A. Blauschild, “A four-terminal wideband monolithic amplifier,” IEEE J. SolidState Circuits, vol. SC-17, pp. 634–638, Dec. 1981. [8] M. Ohara, Y. Akazawa, N. Ishihara, and S. Konaka, “Bipolar monolithic amplifiers for a gigabit optical repeater,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 491–497, Aug. 1985. [9] M. J. N. Sibley, R. T. Univin, D. R. Smith, B. A. Boxall, and R. J. Hawkins, “A monolithic transim­ pedance preamplifier for high speed optical receivers,” British Telecommunicat. Tech. J., vol. 2, pp. 64–66, July 1984. [10] J. F. Kukielka and C. P. Snapp, “Wideband monolithic cascadable feedback amplifiers using silicon bipolar technology,” IEEE Microwave Millimeter-Wave Circuits Symp. Dig., vol. 2, pp. 330, 331, June 1982. [11] R. G. Meyer, M. J. Shensa, and R. Eschenbach, “Cross modulation and intermodulation in amplifiers at high frequencies,” IEEE J. Solid-State Circuits, vol. SC-7, pp. 16–23, Feb. 1972. [12] K. H. Chan and R. G. Meyer, “A low distortion monolithic wide-band amplifier,” IEEE J. SolidState Circuits, vol. SC-12, pp. 685–690, Dec. 1977. [13] A. Arbel, “Multistage transistorized current modules,” IEEE Trans. Circuits Syst., vol. CT-13, pp. 302–310, Sep. 1966. [14] A. Arbel, Analog Signal Processing and Instrumentation, London: Cambridge University, 1980, chap. 3. [15] W. G. Beall, “New feedback techniques for high performance monolithic wideband amplifiers,” Electron. Res. Group, University of Southern California, Tech. Memo., Jan. 1990.

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29 General Feedback Theory1 Wai-Kai Chen University of Illinois, Chicago

29.1 29.2 29.3 29.4

Introduction The Indefinite-Admittance Matrix The Return Difference The Null Return Difference

29.1 Introduction In Chapter 27.2, we used the ideal feedback model to study the properties of feedback amplifiers. The model is useful only if we can separate a feedback amplifier into the basic amplifier µ(s) and the feedback network β(s). The procedure is difficult and sometimes virtually impossible, because the forward path may no be strictly unilateral, the feedback path is usually bilateral, and the input and output coupling networks are often complicated. Thus, the ideal feedback model is not an adequate representation of a practical amplifier. In the remainder of this section, we shall develop Bode’s feedback theory, which is applicable to the general network configuration and avoids the necessity of identifying the transfer functions µ(s) and β(s). Bode’s feedback theory [2] is based on the concept of return difference, which is defined in terms of network determinants. We show that the return difference is a generalization of the concept of the feedback factor of the ideal feedback model, and can be measured physically from the amplifier itself. We then introduce the notion of null return difference and discuss its physical significance. Because the feedback theory will be formulated in terms of the first- and second-order cofactors of the elements of the indefinite-admittance matrix of a feedback circuit, we first review briefly the formulation of the indefinite-admittance matrix.

29.2 The Indefinite-Admittance Matrix Figure 29.1 is an n-terminal network N composed of an arbitrary number of active and passive network elements connected in any way whatsoever. Let V1, V2, …, Vn be the Laplace-transformed potentials measured between terminals 1, 2, …, n and some arbitrary but unspecified reference point, and let I1, I2, …, In be the Laplace-transformed currents entering the terminals 1, 2, …, n from outside the network. The network N together with its load is linear, so the terminal current and voltages are related by the equation

1

References for this chapter can be found on page 917.

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V1

I1

+ 1 V2

I2

+ 2

n-terminal network N

In Vn + n − − − Reference-potential point

FIGURE 29.1 The general symbolic representation of an n-terminal network.

I1   y11 y12 L y1n  V1   J1         I 2   y 21 y 22 L y 2n  V2   J 2   =   +  M   M M M M  M   M        I   y y L y  V   J  nn   n   n   n   n1 n2

(29.1)

I ( s ) = Y( s ) V( s ) + J ( s )

(29.2)

or more succinctly as

where Jk (k = 1,2, …, n) denotes the current flowing into the kth terminal when all terminals of N are grounded to the reference point. The coefficient matrix Y(s) is called the indefinite-admittance matrix because the reference point for the potentials is some arbitrary but unspecified point outside the network. Notice that the symbol Y(s) is used to denote either the admittance matrix or the indefinite-admittance matrix. This should not create any confusion because the context will tell. In the remainder of this section, we shall deal exclusively with the indefinite-admittance matrix. We remark that the short-circuit currents Jk result from the independent sources and/or initial con­ ditions in the interior of N. For our purposes, we shall consider all independent sources outside the network and set all initial conditions to zero. Hence, J(s) is considered to be zero, and (29.2) becomes I ( s ) = Y( s ) V( s )

(29.3)

where the elements yij of Y(s) can be obtained as y ij =

Ii Vj

(29.4) v x =0, x ≠ j

As an illustration, consider a small-signal equivalent model of a transistor in Fig. 29.2. Its indefiniteadmittance matrix is found to be  g1 + sC1 + sC 2  Y(s ) =  g m − sC 2  − g − sC − g m 1  1 © 2003 by CRC Press LLC

− sC 2 g 2 + sC 2 − g2

− g1 − sC1

   − g 2 − gm  g1 + g 2 + g m + sC1 

(29.5)

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873

General Feedback Theory

C2 1

2

+ C1

g1

g2

gmV

V −

3

3

FIGURE 29.2 A small-signal equivalent network of a transistor.

Observe that the sum of elements of each row or column is equal to zero. The fact that these properties are valid in general for the indefinite-admittance matrix will now be demonstrated. To see that the sum of the elements in each column of Y(s) equals zero, we add all n equations of (29.1) to yield n

n

n

n

∑∑ y V = ∑ I − ∑ J ji i

i=1

m

j=1

m=1

m

=0

(29.6)

m=1

The last equation is obtained by appealing to Kirchhoff ’s current law (KCL) for the node corresponding to the reference point. Setting all the terminal voltages to zero except the kth one, which is nonzero, gives n

Vk

∑y

jk

=0

(29.7)

j=1

Because Vk ≠ 0, it follows that the sum of the elements of each column of Y(s) equals zero. Thus, the indefinite-admittance matrix is always singular. To demonstrate that each row sum of Y(s) is also zero, we recognize that because the point of zero potential may be chosen arbitrarily, the currents Jk and Ik remain invariant when all the terminal voltages Vk are changed by the same but arbitrary constant amount. Thus, if V0 is an n-vector, each element of which is v0 ≠ 0, then

[

]

I(s ) − J (s ) = Y(s ) V(s ) + V0 = Y(s ) V(s ) + Y(s )V0

(29.8)

which after invoking (29.2) yields that Y(s ) V0 = 0

(29.9)

or n

∑ y = 0,

i = 1, 2, L, n

ij

(29.10)

j=1

showing that each row sum of Y(s) equals zero. Thus, if Yuv denotes the submatrix obtained from an indefinite-admittance matrix Y(s) by deleting the uth row and vth column, then the (first-order) cofactor, denoted by the symbol Yuv , of the element yuv of Y(s), is defined by Yuv = (−1)

u+v

det Yuv

(29.11)

As a consequence of the zero-row-sum and zero-column-sum properties, all the cofactors of the elements of the indefinite-admittance matrix are equal. Such a matrix is also referred to as the equicofactor matrix. If Yuv and Yij are any two cofactors of the elements of Y(s), then © 2003 by CRC Press LLC

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The Circuits and Filters Handbook, Second Edition

Yuv = Yij

(29.12)

for all u, v, i and j. For the indefinite-admittance matrix Y(s) of (29.5) it is straightforward to verify that all of its nine cofactors are equal to Yuv = s 2C1C 2 + s(C1 g 2 + C 2 g1 + C 2 g 2 + g mC 2 ) + g1 g 2

(29.13)

for u, v = 1, 2, 3. Denote by Yrp,sq the submatrix obtained from Y(s) by striking out rows r and s and columns p and q. Then the second-order cofactor, denoted by the symbol Yrp,sq of the elements yrp, and ysq of Y(s) is a scalar quantity defined by the relation Yrp,sq = sgn (r − s ) sgn ( p − q)(−1)

r + p +s +q

det Yrp,sq

(29.14)

where r ≠ s and p ≠ q, and sgn u = +1 if u > 0

(29.15a)

sgn u = −1 if u < 0

(29.15b)

The symbols Yuv and Yuv or Yrp,sq and Yrp,sq should not create any confusion because one is in boldface whereas the other is italic. Also, for our purposes, it is convenient to define Yrp, sq = 0,

r = s or p = q

(29.16a)

or sgn 0 = 0

(29.16b)

This convention will be followed throughout the remainder of this section. As an example, consider the hybrid-pi equivalent network of a transistor in Fig. 29.3. Assume that each node is an accessible terminal of a four-terminal network. Its indefinite-admittance matrix is:  0.02   0 Y( s ) =  −0.02    0

�

��

0

−0.02

5 × 10 −12 s

0.2 − 5 × 10 −12 s

−5 × 10 −12 s

0.024 + 105 × 10 −12 s

0

−0.204 − 10 −10 s

   −0.2  −10  −0.004 − 10 s   0.204 + 10 −10 s  0

(29.17)

� ��

Ω

�

�

+ ���

Ω

�

��� ��

���

�

− �

FIGURE 29.3 The hybrid-pi equivalent network of a transistor.

© 2003 by CRC Press LLC

�

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875

Ipq

Isr Isr

+ Vrs

r

−

s

p

+ Vpq

q

−

N

ideal voltmeter

General Feedback Theory

FIGURE 29.4 The symbolic representation for the measurement of the transfer impedance.

The second-order cofactor Y31,42 and Y11,34 of the elements of Y(s) of (29.17) are computed as follows:

Y31, 42 = sgn(3 − 4) sgn(1 − 2)(−1)

3+1+ 4+ 2

−0.02  det  0.2 − 5 × 10 −12 s

0   −0.2

(29.18a)

= 0.004

Y11,34 = sgn(1 − 3) sgn(1 − 4)(−1)

1+1+ 3+ 4

(

= 5 × 10 −12 s 0.204 + 10 −10 s

5 × 10 −12 s det   0 

0.2 − 5 × 10 −12 s   −10  −0.204 − 10 s 

(29.18b)

)

The usefulness of the indefinite-admittance matrix lies in the fact that it facilitates the computation of the driving-point or transfer functions between any pair of nodes or from any pair of nodes to any other pair. In the following, we present elegant, compact, and explicit formulas that express the network functions in terms of the ratios of the first- and/or second-order cofactors of the elements of the indefiniteadmittance matrix. Assume that a current source is connected between any two nodes r and s so that a current Isr is injected into the rth node and at the same time is extracted from the sth node. Suppose that an ideal voltmeter is connected from node p to node q so that it indicates the potential rise from q to p, as depicted symbolically in Fig. 29.4. Then the transfer impedance, denoted by the symbol zrp,sq , between the node pairs rs and pq of the network of Fig. 29. 4 is defined by the relation z rp,sq =

Vpq I sr

(29.19)

with all initial conditions and independent sources inside N set to zero. The representation is, of course, quite general. When r = p and s = q, the transfer impedance zrp,sq , becomes the driving-point impedance zrr,ss between the terminal pair rs.

In Fig. 29.4, set all initial conditions and independent sources in N to zero and choose terminal q to

be the reference-potential point for all other terminals. In terms of (29.1), these operations are equivalent to setting J = 0, Vq = 0, Ix = 0 for x ≠ r, s and Ir = –Is = Isr . Because Y(s) is an equicofactor matrix, the equations of (29.1) are not linearly independent and one of them is superfluous. Let us suppress the sth equation from (29.1), which then reduces to I − s = Ysq V−q

(29.20)

where I –s and V–q denote the subvectors obtained from I and V of (29.3) by deleting the sth row and qth row, respectively. Applying Cramer’s rule to solve for Vp yields © 2003 by CRC Press LLC

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The Circuits and Filters Handbook, Second Edition

VP =

˜ det Y sq

(29.21)

det Ysq

˜ is the matrix derived from Y by replacing the column corresponding to V by I . We recognize where Y sq sq p –s that I–s is in the pth column if p < q but in the (p – 1)th column if p > q. Furthermore, the row in which Isr appears is the rth row if r < s, but is the (r – 1)th row if r > s. Thus, we obtain

(−1)s+q det Y˜ sq = IsrYrp,sq

(29.22)

det Ysq = (−1) Ysq

(29.23)

In addition, we have s +q

Substituting these in (29.21) in conjunction with (29.19), we obtain Yrp,sq

z rp,sq =

(29.24)

Yuv Yrr ,ss Yuv

z rr ,ss =

(29.25)

in which we have invoked the fact that Ysq = Yuv . The voltage gain, denoted by grp, sq , between the node pairs rs and pq of the network of Fig. 29.4 is defined by Vpq

g rp,sq =

(29.26)

Vrs

again with all initial conditions and independent sources in N being set to zero. Thus, from (29.24) and (29.25) we obtain g rp,sq =

z rp,sq z rr ,ss

=

Yrp,sq

(29.27)

Yrr ,ss

The symbols have been chosen to help us remember. In the numerators of (29.24), (29.25), and (29.27), the order of the subscripts is as follows: r, the current injecting node; p, the voltage measurement node; s, the current extracting node; and q the voltage reference node. Nodes r and p designate the input and output transfer measurement, and nodes s and q form a sort of double datum. As an illustration, we consider the hybrid-pi transistor equivalent network of Fig. 29.3. For this transistor, suppose that we connect a 100-Ω load resistor between nodes 2 and 4, and excite the resulting circuit by a voltage source V14, as depicted in Fig. 29.5. To simplify our notation, let p = 10–9 s. The indefinite-admittance matrix of the amplifier is:  0.02   0 Y( s ) =  −0.02   0  © 2003 by CRC Press LLC

0

–0.02

0.01 + 0.005 p

0.2 − 0.005 p

−0.005 p

0.024 + 0.105 p

−0.01

−0.204 − 0.1 p

   −0.21  −0.004 − 0.1 p  0.214 + 0.1 p  0

(29.28)

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877

General Feedback Theory

���

��

�

� ��

Ω

��

� �

�

+

+ ���

���

Ω

−

�

+ ��� ��

���

�

−

�

��

���

Ω

−

�

�

FIGURE 29.5 A transistor amplifier used to illustrate the computation of grp,sq.

To compute the voltage gain g12, 44, we appeal to (29.27) and obtain g12, 44 =

V24 Y12, 44 p − 40 = = V14 Y11, 44 5p 2 + 21.7 p + 2.4

(29.29)

The input impedance facing the voltage source V14 is determined by z11, 44 =

V14 Y11, 44 Y11, 44 50p 2 + 217p + 24 = = = 2 I 41 Yuv Y44 p + 4.14 p + 0.08

(29.30)

To compute the current gain defined as the ratio of the current I24 in the 100-Ω resistor to the input current I41, we apply (29.24) and obtain Y I 24 V 0.1 p − 4 = 0.01 24 = 0.01z12, 44 = 0.01 12, 44 = 2 I 41 I 41 Y44 p + 4.14 p + 0.08

(29.31)

Finally, to compute the transfer admittance defined as the ratio of the load current I24 to the input voltage V14, we appeal to (29.27) and obtain Y I 24 V p − 40 = 0.01 24 = 0.01g12, 44 = 0.01 12, 44 = V14 V14 Y11, 44 500p 2 + 2170p + 240

(29.32)

29.3 The Return Difference In the study of feedback amplifier response, we are usually interested in how a particular element of the amplifier affects that response. This element is either crucial in terms of its effect on the entire system or of primary concern to the designer. It may be the transfer function of an active device, the gain of an amplifier, or the immittance of a one-port network. For our purposes, we assume that this element x is the controlling parameter of a voltage-controlled current source defined by the equation I = xV

(29.33)

To focus our attention on the element x, Fig. 29.6 is the general configuration of a feedback amplifier in which the controlled source is brought out as a two-port network connected to a general four-port network, along with the input source combination of Is and admittance Y1 and the load admittance Y2. We remark that the two-port representation of a controlled source (29.33) is quite general. It includes the special situation where a one-port element is characterized by its immittance. In this case, the controlling voltage V is the terminal voltage of the controlled current source I, and x become the oneport admittance. © 2003 by CRC Press LLC

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+ V

xV

− + Vab + Is

Y1

r

a

−

Ipq d

b

c p

Vpq

Vrs −

+

q

s

Y2

−

FIGURE 29.6 The general configuration of a feedback amplifier.

The return difference F(x) of a feedback amplifier with respect to an element x is defined as the ratio of the two functional values assumed by the first-order cofactor of an element of its indefinite-admittance matrix under the condition that the element x assumes its nominal value and the condition that the element x assumes the value zero. To emphasize the importance of the feedback element x, we express the indefinite-admittance matrix Y of the amplifier as a function of x, even though it is also a function of the complex-frequency variable s, and write Y = Y(x). Then, we have [3] F (x ) ≡

Yuv ( x ) Yuv (0)

(29.34)

where Yuv (0) = Yuv ( x )

(29.35)

x=0

The physical significance of the return difference will now be considered. In the network of Fig. 29.6, the input, the output, the controlling branch, and the controlled source are labeled as indicated. Then, the element x enters the indefinite-admittance matrix Y(x) in a rectangular pattern as shown next: a

a  b Y( x ) =  cx d − x

b

c

d

−x x

      

(29.36)

If in Fig. 29.6 we replace the controlled current source xV by an independent current source of x A and set the excitation current source Is to zero, the indefinite-admittance matrix of the resulting network is simply Y(0). By appealing to (29.24), the new voltage Vab′ appearing at terminals a and b of the controlling branch is: Vab′ = x

Yda ,cb (0) Y (0) = − x ca ,db Yuv (0) Yuv (0)

Notice that the current injecting point is terminal d, not c.

© 2003 by CRC Press LLC

(29.37)

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879

General Feedback Theory

−

����

��

�′��

−

+

� �

��

�

−

−

�

+

+

+

−

+

�

�

�

�

��

��

�

�

FIGURE 29.7 The physical interpretation of the return difference with respect to the controlling parameter of a voltage-controlled current source.

0

+

µβ

∑

µ(s)

1

+ β(s)

FIGURE 29.8 The physical interpretation of the loop transmission.

The preceding operation of replacing the controlled current source by an independent current source and setting the excitation Is to zero can be represented symbolically as in Fig. 29.7. Observe that the controlling branch is broken off as marked and a 1-V voltage source is applied to the right of the breaking mark. This 1-V sinusoidal voltage of a fixed angular frequency produces a current of x A at the controlled current source. The voltage appearing at the left of the breaking mark caused by this 1-V excitation is then Vab′ as indicated. This returned voltage Vab′ has the same physical significance as the loop transmis­ sion µβ defined for the ideal feedback model in Chapter 27. To see this, we set the input excitation to the ideal feedback model to zero, break the forward path, and apply a unit input to the right of the break, as depicted in Fig. 29.8. The signal appearing at the left of the break is precisely the loop transmission. For this reason, we introduce the concept of return ratio T, which is defined as the negative of the voltage appearing at the controlling branch when the controlled current source is replaced by an inde­ pendent current source of x A and the input excitation is set to zero. Thus, the return ratio T is simply the negative of the returned voltage Vab′ , or T = – Vab′ . With this in mind, we next compute the difference between the 1-V excitation and the returned voltage Vab′ obtaining 1 − Vab′ = 1 + x

Yca ,db Yuv (0) + xYca ,db Ydb (0) + xYca ,db = = Yuv (0) Yuv (0) Ydb (0)

Y ( x ) Yuv ( x ) = db = = F (x ) Ydb (0) Yuv (0) in which we have invoked the indentities Yuv = Yij and

© 2003 by CRC Press LLC

(29.38)

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880

The Circuits and Filters Handbook, Second Edition

+ 25 V

150 kΩ

10 kΩ

47 kΩ

4.7 kΩ 10 µF

5 µF 5 µF

+ 5 µF

+ 33 kΩ 50 µF

4.7 kΩ

−

50 µF

−

4.7 kΩ

47 kΩ Vs

V2

4.7 kΩ

100 Ω

FIGURE 29.9 A voltage-series feedback amplifier together with its biasing and coupling circuitry.

Ydb ( x ) = Ydb (0) + xYca ,db

(29.39)

We remark that we write Yca,db (x) as Yca,db because it is independent of x. In other words, the return difference F(x) is simply the difference of the 1-V excitation and the returned voltage Vab′ as illustrated in Fig. 29.7, and hence its name. Because F ( x ) = 1 + T = 1 − µβ

(29.40)

we conclude that the return difference has the same physical significance as the feedback factor of the ideal feedback model. The significance of the previous physical interpretations is that it permits us to determine the return ratio T or –µβ by measurement. Once the return ratio is measured, the other quantities such as return difference and loop transmission are known. To illustrate, consider the voltage-series or the series-parallel feedback amplifier of Fig. 29.9. Assume that the two transistors are identical with the following hybrid parameters: hie = 1.1 kΩ,

h fe = 50,

hre = hoe = 0

(29.41)

After the biasing and coupling circuitry have been removed, the equivalent network is presented in Fig. 29.10. The effective load of the first transistor is composed of the parallel combination of the 10, 33, 47, and 1.1-kΩ resistors. The effect of the 150- and 47-kΩ resistors can be ignored; they are included in the equivalent network to show their insignificance in the computation. To simplify our notation, let ˜ k = α × 10 –4 = α k

© 2003 by CRC Press LLC

h fe hie

= 455 × 10 –4 ,

k = 1, 2

(29.42)

0912 S1-S8 Frame55.book Page 881 Sunday, October 6, 2002 5:16 PM

881

General Feedback Theory

�����

���

+

µ���

���

µ���

µ���

���� ���

−

�

�

+

��

��

���

�

µ���

���

+

�

−

−

∼ α

���

��� �

�����

+

∼ α

����

�

���

µ���

− �

FIGURE 29.10 An equivalent network of the feedback amplifier of Fig. 29.9.

The subscript k is used to distinguish the transconductances of the first and the second transistors. The indefinite-admittance matrix of the feedback amplifier of Fig. 29.9 is:  9.37   0   −4 −9.09 − α 1 Y = 10   α1    − 0.28 

0 4.256 − 2.128 0 − 2.128

− 9.09

− 0.28

   − 2.128 − 2.128 − α 2 α2   111.218 + α 1 0 −100    − α1 10.61 −10.61   −100 −10.61 − α 2 113.018 + α 2   0

(29.43)

By applying (29.27), the amplifier voltage gain is computed as g12, 25 =

V 25 V12, 25 211.54 ×10 –7 = = = 45.39 4.66 ×10 –7 Vs V11, 25

(29.44)

˜ k of the transistors, we shortTo calculate the return differences with respect to the transconductances α circuit the voltage source Vs. The resulting indefinite-admittance matrix is obtained from (29.43) by adding the first row to the fifth row and the first column to the fifth column and then deleting the first ˜ k are: row and column. Its first-order cofactor is simply Y11,55. Thus, the return differences with respect to α ˜ 1) = F (α

˜ 2) = F (α

© 2003 by CRC Press LLC

˜ 1) Y11,55 (α

=

466.1 ×10 –9 = 93.70 4.97 ×10 –9

(29.45a)

˜ 2) Y11,55 (α

=

466.1×10 –9 = 18.26 25.52 ×10 –9

(29.45b)

Y11,55 (0)

Y11,55 (0)

0912 S1-S8 Frame55.book Page 882 Sunday, October 6, 2002 5:16 PM

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The Circuits and Filters Handbook, Second Edition

29.4 The Null Return Difference In this section, we introduce the notion of null return difference, which is found to be very useful in measurement situations and in the computation of the sensitivity for the feedback amplifiers. ˆ of a feedback amplifier with respect to an element x is defined to be The null return difference F(x) the ratio of the two functional values assumed by the second-order cofactor Yrp,sq of the elements of its indefinite-admittance matrix Y under the condition that the element x assumes its nominal value and the condition that the element x assumes the value zero where r and s are input terminals, and p and q are the output terminals of the amplifier, or Y (x ) Fˆ ( x ) = rp,sq Yrp,sq (0)

(29.46)

ˆ with respect to a voltage-controlled current source I = xV, is the Likewise, the null return ratio T, negative of the voltage appearing at the controlling branch when the controlled current source is replaced by an independent current source of x A and when the input excitation is adjusted so that the output of the amplifier is identically zero. Now, we demonstrate that the null return difference is simply the return difference in the network under the situation that the input excitation Is has been adjusted so that the output is identically zero. In the network of Fig. 29.6, suppose that we replace the controlled current source by an independent current source of x A. Then by applying formula (29.24) and the superposition principle, the output current Ipq at the load is:  Y (0) Y (0)  I pq = Y2 I s rp,sq + x dp,cq  Yuv (0)   Yuv (0)

(29.47)

 Y (0)  I s ≡ I 0 = −x  dp,cq   Yrp,sq (0) 

(29.48)

Setting Ipq = 0 or Vpq = 0 yields

in which Ydp,cq is independent of x. This adjustment is possible only if a direct transmission occurs from the input to the output when x is set to zero. Thus, in the network of Fig. 29.7, if we connect an independent current source of strength I0 at its input port, the voltage Vab′ is the negative of the null return ratio Tˆ. Using (29.24), we obtain [4] Y (0) Y (0) Tˆ = −Vab′ = − x da ,cb − I 0 ra ,sb Yuv (0) Yuv (0) =−

=

[

]

x Yda ,cb (0)Yrp,sq (0) − Yra ,sb (0)Ydp,cq (0)

xY˙rp,sq

Yrp,sq (0)

Yuv (0)Yrp,sq (0)

=

Yrp,sq ( x ) Yrp,sq (0)

(29.49)

−1

where dY ( x ) Y˙rp,sq ≡ rp,sq dx © 2003 by CRC Press LLC

(29.50)

0912 S1-S8 Frame55.book Page 883 Sunday, October 6, 2002 5:16 PM

883

General Feedback Theory

I′13

3 ∼ V′ α 2 45

212.8 µmho

0.01 mho

I0

28 µmho

909 µmho

∼ α 1 + V′45 −

4 1061 µmho

1

5

˜ 1) by its physical interpretation. FIGURE 29.11 The network used to compute the null return difference Fˆ(α

This leads to Fˆ ( x ) = 1 + Tˆ = 1 − Vab′

(29.51)

ˆ which demonstrates that the null return difference F(x) is simply the difference of the 1-V excitation applied to the right of the breaking mark of the broken controlling branch of the controlled source and the returned voltage Vab′ appearing at the left of the breaking mark under the situation that the input signal Is is adjusted so that the output is identically zero. As an illustration, consider the voltage-series feedback amplifier of Fig. 29.9, an equivalent network of which is presented in Fig. 29.10. Using the indefinite-admittance matrix of (29.43) in conjunction with (29.42), the null return differences with respect to αˆ k are: –7 ˜ Y α ˜ 1 ) = 12,55 ( 1 ) = 211.54 ×10–12 = 103.07 ×103 Fˆ (α Y12,55 (0) 205.24 ×10

(29.52a)

–7

˜ Y α ˜ 2 ) = 12,55 ( 2 ) = 211.54 ×10–10 = 2018.70 Fˆ (α Y12,55 (0) 104.79 ×10

(29.52b)

˜ 1 ) can be computed by using its physical interpretation as follows. Replace the con­ Alternatively, Fˆ(α ˜ 1V13 in Figure 29.10 by an independent current source of α ˜ 1 A. We then adjust the voltage trolled source α source Vs so that the output current I25 is identically zero. Let I0 be the input current resulting from this source. The corresponding network is presented in Fig. 29.11. From this network, we obtain ˜ 1 ) = 1 + Tˆ = 1 − V13′ = 1 − 100V35′ + α 2V45′ − α1 = 103.07 ×103 Fˆ (α 9.09 ˜ 2 ). Likewise, we can use the same procedure to computer the return difference Fˆ(α

© 2003 by CRC Press LLC

(29.53)

0912 S1-S8 Frame55.book Page 885 Sunday, October 27, 2002 8:45 PM

30 The Network Functions and Feedback1 Wai-Kai Chen University of Illinois, Chicago

30.1 Blackman’s Formula 30.2 The Sensitivity Function

We now study the effects of feedback on amplifier impedance and gain and obtain some useful relations among the return difference, the null return difference, and impedance functions in general. Refer to the general feedback configuration of Fig. 29.6. Let w be a transfer function. As before, to emphasize the importance of the feedback element x, we write w = w(x). To be definite, let w (x) for the time being be the current gain between the output and input ports. Then, from (29.24) we obtain

w ( x) =

I pq

=

Y2Vpq

=

Yrp,sq ( x )



Y2

(30.1)

w ( x ) Yrp,sq ( x ) Yuv (0) Fˆ ( x )

= = w (0) Yuv ( x ) Yrp,sq (0) F ( x )

(30.2)

Is

Is

Yuv ( x )

yielding

provided that w(0) ≠ 0. This gives a very useful formula for computing the current gain:

w ( x ) = w (0)

Fˆ ( x ) F (x )

(30.3)

Equation (30.3) remains valid if w(x) represents the transfer impedance zrp,sq = Vpq /IS instead of the current gain.

30.1 Blackman’s Formula In particular, when r = p and s = q, w(x) represents the driving-point impedance zrr,ss(x) looking into the terminals r and s, and we have a somewhat different interpretation. In this case, F(x) is the return difference with respect to the element x under the condition Is = 0. Thus, F(x) is the return difference for the situation when the port where the input impedance is defined is left open without a source and

1

References for this chapter can be found on page 917.

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The Circuits and Filters Handbook, Second Edition

we write F(x) = F(input open circuited). Likewise, from Fig. 29.6, Fˆ (x) is the return difference with respect to x for the input excitation Is and output response Vrs under the condition Is is adjusted so that Vrs is identically zero. Thus, Fˆ (x) is the return difference for the situation when the port where the input impedance is defined is short circuited, and we write Fˆ (x) = F(input short-circuited). Consequently, the input impedance Z(x) looking into a terminal pair can be conveniently expressed as Z ( x ) = Z (0)

F (input short circuited) F (input open circuited)

(30.4)

This is the well-known Blackman’s formula for computing an active impedance. The formula is extremely useful because the right-hand side can usually be determined rather easily. If x represents the controlling parameter of a controlled source in a single-loop feedback amplifier, then setting x = 0 opens the feedback loop and Z(0) is simply a passive impedance. The return difference for x when the input port is short circuited or open circuited is relatively simple to compute because shorting out or opening a terminal pair frequently breaks the feedback loop. In addition, Blackman’s formula can be used to determine the return difference by measurements. Because it involves two return differences, only one of them can be identified and the other must be known in advance. In the case of a single-loop feedback amplifier, it is usually possible to choose a terminal pair so that either the numerator or the denominator on the righthand side of (30.4) is unity. If F(input short circuited) = 1, F(input open circuited) becomes the return difference under normal operating condition and we have F (x ) =

Z (0) Z (x )

(30.5)

On the other hand, if F(input open-circuited) = 1, F(input short-circuited) becomes the return difference under normal operating condition and we obtain F (x ) =

Z (x ) Z (0)

(30.6)

Example 1. The network of Fig. 30.1 is a general active RC one-port realization of a rational impedance. We use Blackman’s formula to verify that its input admittance is given by Y =1+

Z3 − Z 4 Z1 − Z 2

(30.7)

Appealing to (30.4), the input admittance written as Y = Y(x) can be written as Y ( x ) = Y (0)

F (input open circuited) F (input short circuited)

(30.8)

where x = 2/Z3. By setting x to zero, the network used to compute Y(0) is shown in Fig. 30.2. Its input admittance is: Y (0) =

Z1 + Z 2 + Z 3 + Z 4 + 2 Z1 + Z 2

(30.9)

When the input port is open-circuited, the network of Fig. 30.1 degenerates to that depicted in Fig. 30.3. The return difference with respect to x is:

© 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 887 Sunday, October 27, 2002 8:45 PM

887

The Network Functions and Feedback

I

1Ω Z2 2V3 Z3

Z4

Y

I − Z1

V3 1Ω

Z3

+

FIGURE 30.1 A general active RC one-port realization of a rational function.

I

Z1+Z2

Y(0)

1+Z3+Z4

I

1Ω

FIGURE 30.2 The network used to compute Y(0).

1Ω Z2 2 Z3

Z4

− V′3

Z1 1Ω

FIGURE 30.3 The network used to compute F(input open-circuited).

© 2003 by CRC Press LLC

+

Z3

0912 S1-S8 Frame55.book Page 888 Sunday, October 27, 2002 8:45 PM

888

The Circuits and Filters Handbook, Second Edition

I

1Ω Z2 Z4

2/Z3

I − V″3

Z1 1Ω

Z3

+

FIGURE 30.4 The network used to compute F(input short-circuited).

F (input open-circuited) = 1 − V3′ =

Z1 + Z 3 − Z 2 − Z 4 2 + Z1 + Z 2 + Z 3 + Z 4

(30.10)

where the returned voltage V3′ at the controlling branch is given by V3′ =

2(1 + Z 2 + Z 4 )

(30.11)

2 + Z1 + Z 2 + Z 3 + Z 4

To compute the return difference when the input port is short circuited, we use the network of Fig. 30.4 and obtain F (input short-circuited) = 1 − V3′′ =

Z1 − Z 2 Z1 + Z 2

(30.12)

where the return voltage V ″3 at the controlling branch is found to be V3′′ =

2Z 2 Z1 + Z 2

(30.13)

Substituting (30.9), (30.10), and (30.12) in (30.8) yields the desired result. Y =1+

Z3 − Z 4 Z1 − Z 2

(30.14)

To determine the effect of feedback on the input and output impedances, we choose the series-parallel feedback configuration of Fig. 30.5. By shorting the terminals of Y2, we interrupt the feedback loop, therefore, formula (30.5) applies and the output impedance across the load admittance Y2 becomes Z out ( x ) =

© 2003 by CRC Press LLC

Z out (0) F (x )

(30.15)

0912 S1-S8 Frame55.book Page 889 Sunday, October 27, 2002 8:45 PM

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The Network Functions and Feedback

Na Z1 Y2 Vs

Nf

FIGURE 30.5 The series-parallel feedback configuration.

demonstrating that the impedance measured across the path of the feedback is reduced by the factor that is the normal value of the return difference with respect to the element x, where x is an arbitrary element of interest. For the input impedance of the amplifier looking into the voltage source Vs of Fig. 30.5, by open circuiting or removing the voltage source Vs, we break the feedback loop. Thus, formula (30.6) applies and the input impedance becomes Z in ( x ) = F ( x ) Z in (0)

(30.16)

meaning that the impedance measured in series lines is increased by the same factor F(x). Similar conclusions can be reached for other types of configurations discussed in Chapter 28 by applying Black­ man’s formula. Again, refer to the general feedback configuration of Fig. 29.6 If w(x) represents the voltage gain Vpq /Vrs or the transfer admittance Ipq /Vrs . Then, from (29.27) we can write w ( x ) Yrp,sq ( x ) Yrr ,ss (0) = w (0) Yrp,sq (0) Yrr ,ss ( x )

(30.17)

ˆ The first term in the product on the right-hand side is the null return difference F(x) with respect to x for the input terminals r and s and output terminals p and q. The second term is the reciprocal of the null return difference with respect to x for the same input and output port at terminals r and s. This reciprocal can then be interpreted as the return difference with respect to x when the input port of the amplifier is short circuited. Thus, the voltage gain or the transfer admittance can be expressed as w ( x ) = w (0)

Fˆ ( x ) F (input short-circuted)

(30.18)

Finally, if w (x)denotes the short circuit current gain Ipq /Is as Y2 approaches infinity, we obtain w ( x ) Yrp,sq ( x ) Ypp,qq (0) = w (0) Yrp,sq (0) Ypp,qq ( x )

(30.19)

The second term in the product on the right-hand side is the reciprocal of the return difference with respect to x when the output port of the amplifier is short-circuited, giving a formula for the short circuit current gain as w ( x ) = w (0)

© 2003 by CRC Press LLC

Fˆ ( x ) F (output short-circuited)

(30.20)

0912 S1-S8 Frame55.book Page 890 Sunday, October 27, 2002 8:45 PM

890

The Circuits and Filters Handbook, Second Edition

Again, consider the voltage-series or series-parallel feedback amplifier of Fig. 29.9 an equivalent net­ ˜ k ) and ˜ k ), the null return differences Fˆ (α work of which is given in Fig. 29.10. The return differences F(α the voltage gain w were computed earlier in (29.45), (29.52), and (29.44), and are repeated next: ˜ 1 ) = 93.70, F (α

˜ 2 ) = 18.26 F (α

˜ 1 ) = 103.07 × 103 , Fˆ (α ˜ 2 ) = 2018.70 Fˆ (α w=

V25 ˜ 1 ) = w (α ˜ 2 ) = 45.39 = w (α Vs

(30.21a) (30.21b) (30.21c)

We apply (30.18) to calculate the voltage gain w, as follows: ˜ 1 ) = w (0) w (α

˜ 1) Fˆ (α

F (input short-circuited)

= 0.04126

103.07 × 103 = 45.39 93.699

(30.22)

where w (0) =

˜ 1) Y12,55 (α ˜ Y11,55 (α1 )

= α˜ 1 =0

F (input short-circuited) =

205.24 × 10 –12 = 0.04126 497.41 × 10 –11

˜ 1) Y11,55 (α Y11,55 (0)

=

466.07 × 10 –9 = 93.699 4.9741 × 10 –9

(30.23a)

(30.23b)

and ˜ 2 ) = w (0) w (α

˜ 2) Fˆ (α

F (input short-circuited)

= 0.41058

2018.70 = 45.39 18.26

(30.24)

where w (0) =

˜ 2) Y12,55 (α ˜ Y11,55 (α 2 )

= α˜ 2 =0

F (input short-circuited) =

104.79 × 10 –10 = 0.41058 255.22 × 10 –10

˜ 2) Y11,55 (α Y11,55 (0)

=

466.07 × 10 –9 = 18.26 25.52 × 10 –9

(30.25a)

(30.25b)

30.2 The Sensitivity Function One of the most important effects of negative feedback is its ability to make an amplifier less sensitive to the variations of its parameters because of aging, temperature variations, or other environment changes. A useful quantitative measure for the degree of dependence of an amplifier on a particular parameter is known as the sensitivity. The sensitivity function, written as (x), for a given transfer function with respect to an element x is defined as the ratio of the fractional change in a transfer function to the fractional change in x for the situation when all changes concerned are differentially small. Thus, if w(x) is the transfer function, the sensitivity function can be written as ( x ) = lim

∆x→0

© 2003 by CRC Press LLC

∆w w x ∂w ∂1n w = =x ∂x ∆x x w ∂x

(30.26)

0912 S1-S8 Frame55.book Page 891 Sunday, October 27, 2002 8:45 PM

891

The Network Functions and Feedback

Refer to the general feedback configuration of Fig. 29.6, and let w(x) represent either the current gain Ipq /Is or the transfer impedance Vpq /Is for the time being. Then, we obtain from (29.24) w ( x ) = Y2

Yrp,sq ( x ) Yuv ( x )

or

Yrp, sq ( x ) Yuv ( x )

(30.27)

As before, we write ∂Y ( x ) Y˙uv ( x ) = uv ∂x

(30.28a)

∂Y ( x ) Y˙rp,sq ( x ) = rp,sq ∂x

(30.28b)

Yuv ( x ) = Yuv (0) + xY˙uv ( x )

(30.29a)

Yrp,sq ( x ) = Yrp,sq (0) + xY˙rp,sq ( x )

(30.29b)

obtaining

Substituting (30.27) in (30.26), in conjunction with (30.29), yields ( x ) = x

Y˙rp,sq ( x ) Yrp,sq ( x )

−x

Y˙uv ( x ) Yrp,sq ( x ) − Yrp,sq (0) Yuv ( x ) − Yuv (0) = − Yuv ( x ) Yrp,sq ( x ) Yuv ( x )

Y (0) Y (0) 1 1 = uv − rp,sq = − ˆ Yuv ( x ) Yrp,sq ( x ) F (x ) F (x )

(30.30)

Combining this with (30.3), we obtain ( x ) =

1 F (x )

 w (0)  1 −   w ( x ) 

(30.31)

1 F (x )

(30.32)

Observe that if w(0) = 0, (30.31) becomes ( x ) =

meaning that sensitivity is equal to the reciprocal of the return difference. For the ideal feedback model, the feedback path is unilateral. Hence, w(0) = 0 and =

1 1 1 = = F 1 + T 1 − µβ

(30.33)

For a practical amplifier, w(0) is usually very much smaller than w(x) in the passband, and F ≈ 1/ may be used as a good estimate of the reciprocal of the sensitivity in the same frequency band. A singleloop feedback amplifier composed of a cascade of common-emitter stages with a passive network pro­ viding the desired feedback fulfills this requirements. If in such a structure any one of the transistors fails, the forward transmission is nearly zero and w(0) is practically zero. Our conclusion is that if the failure of any element will interrupt the transmission through the amplifier as a whole to nearly zero, the sensitivity is approximately equal to the reciprocal of the return difference with respect to that element. © 2003 by CRC Press LLC

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The Circuits and Filters Handbook, Second Edition

In the case of driving-point impedance, w(0) is not usually smaller than w(x), and the reciprocity relation is not generally valid. Now assume that w(x) represents the voltage gain. Substituting (30.27) in (30.26) results in ( x ) = x

Y˙rp,sq ( x ) Yrp,sq ( x )

−x

Y˙rr ,ss ( x ) Yrp,sq ( x ) − Yrp,sq (0) Yrr ,ss ( x ) − Yrr ,ss (0) = − Yrr ,ss ( x ) Yrp,sq ( x ) Yrr ,ss ( x )

Y (0) Yrp,sq (0) 1 1 = rr ,ss − = − Yrr ,ss ( x ) Yrp,sq ( x ) F (input short-circuited) Fˆ ( x )

(30.34)

Combining this with (30.18) gives ( x ) =

1 F (input short-circuited)

 w (0)  1 −   w ( x ) 

(30.35)

Finally, if w(x) denotes the short circuit current gain Ipq /Is as Y2 approaches infinity, the sensitivity function can be written as ( x ) =

Ypp,qq (0)

Ypp,qq ( x )

−

Yrp,sq (0)

Yrp,sq ( x )

=

1 1 − F (output short-circuited) Fˆ ( x )

(30.36)

which when combined with (30.20) yields ( x ) =

1 F (output short-circuited)

 w (0)  1 −   w ( x ) 

(30.37)

We remark that formulas (30.31), (30.35), and (30.39) are quite similar. If the return difference F(x) is interpreted properly, they can all be represented by the single relation (30.31). As before, if w(0) = 0, the sensitivity for the voltage gain function is equal to the reciprocal of the return difference under the situation that the input port of the amplifier is short-circuited, whereas the sensitivity for the short circuit current gain is the reciprocal of the return difference when the output port is short-circuited. Example 2. The network of Fig. 30.6 is a common-emitter transistor amplifier. After removing the biasing circuit and using the common-emitter hybrid model for the transistor at low frequencies, an equivalent network of the amplifier is presented in Fig. 30.7 with

VCC RB1

Rc C2

C1

R1 + Vs

R2

RB2 RE

−

FIGURE 30.6 A common-emitter transistor feedback amplifier. © 2003 by CRC Press LLC

CE

0912 S1-S8 Frame55.book Page 893 Sunday, October 27, 2002 8:45 PM

893

The Network Functions and Feedback

�µ

�

�

�

= �2 �� ��

+

�

�′� = ��� � � ����π

+

��

�π

���

�

�

��

�

�

�′

�′

−

−

�

FIGURE 30.7 An equivalent network of the feedback amplifier of Fig. 30.6.

Vs R1 + rx

(30.38a)

1 1 1 = + R′1 R1 + rx rπ

(30.38b)

1 1 1 = + R′2 R2 Rc

(30.38c)

I′s = G′1 =

G′2 =

The indefinite admittance matrix of the amplifier is: G1′ + sC π + sCµ  − sCµ − G1′ − sC π    Y =  g m − sCµ − G 2′ − g m G2′ + sCµ     − G2′ G1′ + G2′ + sC π + g m  −G1′ − sC π − g m

(30.39)

Assume that the controlling parameter gm is the element of interest. The return difference and the null return difference with respect to gm in Fig. 30.7 with I′s as the input port and R 2′ , as the output port, are: F(gm ) =

(G′ + sC )(G′ + sC ) + sC (G′ + g ) (0) (G′ + sC )(G′ + sC ) + sC G ′

Y33 ( g m ) Y33

π

1

=

1

µ

2

π

µ

2

µ

2

µ

m

(30.40)

2

Y ( g ) sC − g m g Fˆ ( g m ) = 12,33 m = µ =1− m sCµ Y12,33 (0) sCµ

(30.41)

The current gain I23 /I s′ as defined in Fig. 30.7, is computed as w( g m ) =

Y12,33 ( g m )

R2′Y33 ( g m )

=

[

(

sCµ − g m

]

)

R2′ (G1′ + sC π ) G2′ + sCµ + sCµ (G2′ + g m )

(30.42)

Substituting these in (30.30) or (30.31) gives ( g m ) = −

© 2003 by CRC Press LLC

(sC

(

)(

g m G′1 + sC π + sCµ G′2 + sCµ

µ

)[

(

)

)

]

− g m (G1′ + sC π ) G2′ + sCµ + sCµ (G2′ + g m )

(30.43)

0912 S1-S8 Frame55.book Page 894 Sunday, October 27, 2002 8:45 PM

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The Circuits and Filters Handbook, Second Edition

Finally, we compute the sensitivity for the driving-point impedance facing the current source Is′. From (30.31), we obtain ( g m ) =

1 F(gm )

 sCµ g m Z (0)  1 − =− (G′1 + sCπ ) G′2 + sCµ + sCµ (G′2 + g m )  Z ( g m ) 

(

)

(30.44)

where Z(gm ) =

© 2003 by CRC Press LLC

Y11,33 ( g m ) Y33 ( g m )

=

G2′ + sCµ

(G′ + sC )(G′ + sC ) + sC (G′ + g ) 1

π

2

µ

µ

2

m

(30.45)

0912 S1-S8 Frame55.book Page 895 Sunday, October 6, 2002 5:16 PM

31 Measurement of Return Difference1 Wai-Kai Chen University of Illinois, Chicago

31.1 Blecher’s Procedure 31.2 Impedance Measurements

The zeros of the network determinant are called the natural frequencies. Their locations in the complexfrequency plane are extremely important in that they determine the stability of the network. A network is said to be stable if all of its natural frequencies are restricted to the open left-half side (LHS) of the complex-frequency plane. If a network determinant is known, its roots can readily be computed explicitly with the aid of a computer if necessary, and the stability problem can then be settled directly. However, for a physical network there remains the difficulty of getting an accurate formulation of the network determinant itself, because every equivalent network is, to a greater or lesser extent, an idealization of the physical reality. As frequency is increased, parasitic effects of the physical elements must be taken into account. What is really needed is some kind of experimental verification that the network is stable and will remain so under certain prescribed conditions. The measurement of the return difference provides an elegant solution to this problem. The return difference with respect to an element x in a feedback amplifier is defined by F (x ) =

Yuv ( x ) Yuv (0)

(31.1)

Because Yuv(x) denotes the nodal determinant, the zeros of the return difference are exactly the same as the zeros of the nodal determinant provided that there is no cancellation of common factors between Yuv(x) and Yuv(0). Therefore, if Yuv(0) is known to have no zeros in the closed right-half side (RHS) of the complex-frequency plane, which is usually the case in a single-loop feedback amplifier when x is set to zero, F(x) gives precisely the same information about the stability of a feedback amplifier as does the nodal determinant itself. The difficulty inherent in the measurement of the return difference with respect to the controlling parameter of a controlled source is that, in a physical system, the controlling branch and the controlled source both form part of a single device such as a transistor, and cannot be physically separated. In the following, we present a scheme that does not require the physical decomposition of a device. Let a device of interest be brought out as a two-port network connected to a general four-port network as shown in Fig. 31.1. For our purposes, assume that this device is characterized by its y parameters, and represented by its y-parameter equivalent two-port network as indicated in Fig. 31.2, in which the

1

References for this chapter can be found on page 917.

© 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 896 Sunday, October 6, 2002 5:16 PM

Two-port network

a

r Is

b

c

d

p

Four-port network

Y1

Y2 q

s

FIGURE 31.1 The general configuration of a feedback amplifier with a two-port device.

+ ���

+

�

+

��

′�� −

�����

−

���

�� �����

−

���

− �

��

�

�

�

+ �

�

��������� �������

�� �

�� �

FIGURE 31.2 The representation of a two-port device in Fig. 31.1 by its y parameters.

parameter y21 controls signal transmission in the forward direction through the device, whereas y12 gives the reverse transmission, accounting for the internal feedback within the device. Our objective is to measure the return difference with respect to the forward short circuit transfer admittance y21.

31.1 Blecher’s Procedure [1] Let the two-port device be a transistor operated in the common-emitter configuration with terminals a, b = d, and c representing, respectively, the base, emitter, and collector terminals. To simplify our notation, let a = 1, b = d = 3 and c = 2, as exhibited explicitly in Fig. 31.3. To measure F(y21), we break the base terminal of the transistor and apply a 1-V excitation at its input as exhibited in Fig. 31.3. To ensure that the controlled current source y21V13 drives a replica of what it sees during normal operation, we connect an active one-port network composed of a parallel combination of the admittance y11 and a controlled current source y12V23 at terminals 1 and 3. The returned voltage V13 is precisely the negative of the return ratio with respect to the element y21. If, in the frequency band of interest, the externally applied feedback is large compared with the internal feedback of the transistor, the controlled source y12V23 can be ignored. If, however, we find that this internal feedback cannot be ignored, we can simulate it by using an additional transistor, connected as shown in Fig. 31.4. This additional transistor must be matched as closely as possible to the one in question. The one-port admittance yo denotes the admittance presented to the output port of the transistor under consideration as indicated in Figs. 31.3 and 31.4. For a common-emitter state, it is perfectly reasonable to assume that yo  y12 and y11  y12. Under these assumptions, it is straightforward to show that the Norton equivalent network looking into the two-port network at terminals 1 and 3 of Fig. 31.4 can be approximated © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 897 Sunday, October 6, 2002 5:16 PM

������

��� +

�

+ −

1�

��� −

��� + ��

−

�

� �

��

� ��

��������� �������

�

�

FIGURE 31.3 A physical interpretation of the return difference F(y21) for a transistor operated in the commonemitter configuration and represented by its y parameters yij . −���

���

+

��

+

� ��

−

��

−

���

+

��

−

�

� �

� ��

��������� �������

�

�

FIGURE 31.4 The measurement of return difference F(y21) for a transistor operated in the common-emitter con­ figuration and represented by its y parameters yij .

by the parallel combination of y11 and y12V23, as indicated in Fig. 31.3. In Fig. 31.4, if the voltage sources have very low internal impedances, we can join together the two base terminals of the transistors and feed them both from a single voltage source of very low internal impedance. In this way, we avoid the need of using two separate sources. For the procedure to be feasible, we must demonstrate the admittances y11 and −y12 can be realized as the input admittances of one-port RC networks. Consider the hybrid-pi equivalent network of a common-emitter transistor of Fig. 31.5, the short circuit admittance matrix of which is found to be

Ysc =

(

 g g + sC + sC 1 π µ  x π g x + g π + sC π + sCµ  g x g m − sCµ 

(

)

)

  sCµ ( g x + g π + sC π + g m )  −g x sCµ

(31.2)

It is easy to confirm that the admittance y11 and −y12 can be realized by the one-port networks of Fig. 31.6.

31.2 Impedance Measurements In this section, we show that the return difference can be evaluated by measuring two driving-point impedances at a convenient port in the feedback amplifier [8]. © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 898 Sunday, October 6, 2002 5:16 PM

�

�

�� = ����

�′

�µ

�

�

�

+

�π = ���π

�π

���

�

−

�

�

�

FIGURE 31.5 The hybrid-pi equivalent network of a common-emitter transistor.

��

�π

��

�π�µ����+�π�

�π + �µ

�

�� �� + �π��µ� −���

���

���

FIGURE 31.6 (a) The realization of y11 and (b) the realization of −y12.

Refer again to the general feedback configuration of Fig. 31.2. Suppose that we wish to evaluate the return difference with respect to the forward short circuit transfer admittance y21. The controlling parameters y12 and y21 enter the indefinite-admittance matrix Y in the rectangular patterns as shown next: a a  b Y( x ) =  c  y 21 d − y 21

b

c

d

y12

− y12   y12     

− y12 − y 21 y 21

(31.3)

To emphasize the importance of y12 and y21, we again write Yuv(x) as Yuv(y12, y21) and zaa,bb(x) as zaa,bb(y12, y21). By appealing to formula (29.25), the impedance looking into terminals a and b of Fig. 31.2 is: z aa ,bb ( y12 , y 21 ) =

Yaa ,bb ( y12 , y 21 ) Ydd ( y12 , y 21 )

(31.4)

The return difference with respect to y21 is given by F ( y 21 ) = © 2003 by CRC Press LLC

Ydd ( y12 , y 21 ) Ydd ( y12 ,0)

(31.5)

0912 S1-S8 Frame55.book Page 899 Sunday, October 6, 2002 5:16 PM

+ F(y12) − + y22 1V −

Two-port device

r a

b

d

c p

Four-port network

Y1

Y2

s

q

FIGURE 31.7 The measurement of the return difference F(y12) with y21 set to zero.

�

�

�

�����

�����

�������� ������

��

�

�

�

�

� �

��������� �������

�

�

�

�

�

FIGURE 31.8 The measurement of the driving-point impedance zaa,bb(0, 0).

Combining these yields F ( y 21 )z aa ,bb ( y12 , y 21 ) =

Yaa ,bb ( y12 , y 21 ) Ydd ( y12 ,0)

=

Yaa ,bb (0, 0) Ydd ( y12 ,0)

Y (0, 0) Ydd (0, 0) z (0, 0) = aa ,bb = aa ,bb Ydd (0, 0) Ydd ( y12 , 0) F ( y12 )

(31.6)

y21 =0

obtaining a relation F ( y12 )

y21 =0

F ( y 21 ) =

z aa ,bb (0, 0) z aa ,bb ( y12 , y 21 )

(31.7)

among the return differences and the driving-point impedances. F(y12)y21 =0 is the return difference with respect to y12 when y21 is set to zero. This quantity can be measured by the arrangement of Fig. 31.7. zaa,bb(y12, y21) is the driving-point impedance looking into terminals a and b of the network of Fig. 31.2. Finally, zaa,bb(0, 0) is the impedance to which zaa,bb(y12, y21) reduces when the controlling parameters y12 and y21 are both set to zero. This impedance can be measured by the arrangement of Fig. 31.8. Note that, in all three measurements, the independent current source Is is removed. Suppose that we wish to measure the return difference F(y21) with respect to the forward transfer admittance y21 of a common-emitter transistor shown in Fig. 31.2. Then, the return difference F(y12) © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 900 Sunday, October 6, 2002 5:16 PM

z11,33 (y12, y21)

1

r

3

2

p

Four-port network

Y1

Y2

s

q

FIGURE 31.9 The measurement of the driving-point impedance z11,33(y12, y21). z11,33 (0,0)

y11

r

1

3

2

p

Four-port network

Y1 s

Y2 q

FIGURE 31.10 The measurement of the driving-point impedance z11,33(0, 0).

when y21 is set to zero, for all practical purposes, is indistinguishable from unity. Therefore, (31.7) reduces to the following simpler form: F ( y 21 ) ≈

z11,33 (0, 0) z11,33 ( y12 , y 21 )

(31.8)

showing that the return difference F(y21) effectively equals the ratio of two functional values assumed by the driving-point impedance looking into terminals 1 and 3 of Fig. 31.2 under the condition that the controlling parameters y12 and y21 are both set to zero and the condition that they assume their nominal values. These two impedances can be measured by the network arrangements of Figs. 31.9 and 31.10.

© 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 901 Sunday, October 6, 2002 5:16 PM

32 Multiple-Loop Feedback Amplifiers

Wai-Kai Chen Unitersity of Illinois, Chicago

32.1 32.2 32.3 32.4 32.5 32.6

Multiple-Loop Feedback Amplifier Theory The Return Difference Matrix The Null Return Difference Matrix The Transfer-Function Matrix and Feedback The Sensitivity Matrix Multiparameter Sensitivity

So far, we have studied the single-loop feedback amplifiers. The concept of feedback was introduced in terms of return difference. We found that return difference is the difference between the unit applied signal and the returned signal. The returned signal has the same physical meaning as the loop transmission in the ideal feedback mode. It plays an important role in the study of amplifier stability, its sensitivity to the variations of the parameters, and the determination of its transfer and driving point impedances. The fact that return difference can be measured experimentally for many practical amplifiers indicates that we can include all the parasitic effects in the stability study, and that stability problem can be reduced to a Nyquist plot. In this section, we study amplifiers that contain a multiplicity of inputs, outputs, and feedback loops. They are referred to as the multiple-loop feedback amplifiers. As might be expected, the notion of return difference with respect to an element is no longer applicable, because we are dealing with a group of elements. For this, we generalize the concept of return difference for a controlled source to the notion of return difference matrix for a multiplicity of controlled sources. For measurement situations, we introduce the null return difference matrix and discuss its physical significance. We demonstrate that the determinant of the overall transfer function matrix can be expressed explicity in terms of the determinants of the return difference and the null return difference matrices, thereby allowing us to generalize Black­ man’s formula for the input impedance.

32.1 Multiple-Loop Feedback Amplifier Theory The general configuration of a multiple-input, multiple-output, and multiple-loop feedback amplifier is presented in Fig. 32.1, in which the input, output, and feedback variables may be either currents or voltages. For the specific arrangement of Fig. 32.1, the input and output variables are represented by an n-dimensional vector u and an m-dimensional vector y as

© 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 902 Sunday, October 6, 2002 5:16 PM

902

The Circuits and Filters Handbook, Second Edition

� +−

+−

+−

+−

φ�

φ�

θ�

θ� ��

���

���

�

��

���

�

��� �

+ ���

−

�

+

+�

�� + �

−

+ ����−��

���� + ��

+

�

��

−

−

���

FIGURE 32.1 The general configuration of a multiple-input, multiple-output, and multiple-loop feedback amplifier.

u1  I s1      u2  I s 2      M  M      u  I

  k   sk  u(s ) =  = , uk + 1  V s1         uk + 2  Vs 2      M  M      un  Vs(n − k ) 

 y1  I1       y 2  I 2      M  M       y  I   r  r  y (s ) =  = y  V   r +1   r +1       y r + 2  Vr + 2      M  M       y m  Vm 

(32.1)

respectively. The elements of interest can be represented by a rectangular matrix X of order q × p relating the controlled and controlling variables by the matrix equation θ1  x11    θ 2  x 21 Θ= = M   M    θ   x  q   q1

x12

L

x 22

L

M

M

x q2

L

x1p  φ1    x 2 p  φ 2     = XΦ Φ M  M    x qp  φ p 

(32.2)

where the p-dimensional vector  is called the controlling vector, and the q-dimensional vector  is the controlled vector. The controlled variables θk and the controlling variables Φk can either be currents or voltages. The matrix X can represent either a transfer-function matrix or a driving-point function matrix. © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 903 Sunday, October 6, 2002 5:16 PM

903

Multiple-Loop Feedback Amplifiers

�

Φ

�

Θ

�

�

FIGURE 32.2 The block diagram of the general feedback configuration of Fig. 32.1.

If X represents a driving-point function matrix, the vectors  and  are of the same dimension (q = p) and their components are the currents and voltages of a p-port network. The general configuration of Fig. 32.1 can be represented equivalently by the block diagram of Fig. 32.2 in which N is a (p + q + m + n)-port network and the elements of interest are exhibited explicitly by the block X. For the (p + q + m + n)-port network N, the vectors u and are  are its inputs, and the vectors  and y its outputs. Since N is linear, the input and output vectors are related by the matrix equations Φ = Α Α + Βu

(32.3a)

y = C + Du

(32.3b)

where A, B, C, and D are transfer-function matrices of orders p × q, p × n, m × q, and m × n, respectively. The vectors  and  are not independent and are related by  = XΦ Φ

(32.3c)

The relationships among the above three linear matrix equations can also be represented by a matrix signal-flow graph as shown in Fig. 32.3 know as the fundamental matrix feedback-flow graph. The overall closed-loop transfer-function matrix of the multiple-loop feedback amplifier is defined by the equation y = W( X )u

(32.4)

where W(X) is of order m × n. As before, to emphasize the importance of X, the matrix W is written as W(X) for the present discussion, even though it is also a function of the complex-frequency variable s. Combining the previous matrix equations, the transfer-function matrix is:

(

W( X ) = D + CX 1p − AX

)

−1

B

(32.5a)

� Φ

�

�

� � © 2003 by CRC Press LLC

Θ

�

�

FIGURE 32.3 The fundamental matrix feedback-flow graph.

0912 S1-S8 Frame55.book Page 904 Sunday, October 6, 2002 5:16 PM

904

The Circuits and Filters Handbook, Second Edition

or

(

W( X ) = D + C 1q − XA

)

−1

XB

(32.5b)

where 1p denotes the identity matrix of order p. Clearly, we have W( 0 ) = D

(32.6)

In particular, when X is square and nonsingular, (32.5) can be written as

(

W( X ) = D + C X –1 − A

)

−1

(32.7)

B

Example 3. Consider the voltage-series feedback amplifier of Fig. 29.9. An equivalent network is shown in Fig. 32.4 in which we have assumed that the two transistors are identical with hie = 1.1 kΩ, hfe = 50, hre = hoe = 0. Let the controlling parameters of the two controlled sources be the elements of interest. Then we have I a  Θ =   = 10 −4 I b 

455   0

0  V13     = XΦ Φ 455 V45 

(32.8)

Assume that the output voltage V25 and input current I51 are the output variables. Then the sevenport network N defined by the variables V13, V45, V25, I51, Ia, Ib, and Vs can be characterized by the matrix equations V13   − 90.782 Φ= = V45  −942.507

45.391 I a  0.91748  +  V s 0  I b   0 

[ ]

(32.9a)

Θ + Bu = AΘ −2372.32

V25  45.391 y= = I 51  −0.08252

 I a  0.041260  +  Vs 0.04126 I b  0.000862

[ ]

(32.9b)

= CΘ Θ + Du

212.8 µmho −4

1

V13

+

Ia = 455×10 V13 3 4

−

2

909 µmho

−

−4

1061 µmho

V45

Ib =455 ×10 V45

−

0.01 mho

Vs

+ 28 µmho

+

I25 +

V25

− 5

FIGURE 32.4 An equivalent network of the voltage-series feedback amplifier of Fig. 29.9. © 2003 by CRC Press LLC

212.8 µmho

I51

0912 S1-S8 Frame55.book Page 905 Sunday, October 6, 2002 5:16 PM

905

Multiple-Loop Feedback Amplifiers

According to (32.4), the transfer-function matrix of the amplifier is defined by the matrix equation V25  w11  y =   =   Vs = W( X )u I 51  w 21 

[ ]

(32.10)

Because X is square and nonsingular, we can use (32.7) to calculate W(X):

(

W( X ) = D + C X –1 − A

)

−1

 45.387  w11  B=  =  −4 0.369 × 10  w 21 

(32.11)

where

(X

–1

−A

)

−1

4.856  = 10 − 4  −208.245

10.029  24.914

(32.12)

obtaining the closed-loop voltage gain w11 and input impedance Zin facing the voltage source Vs as w11 =

V25 = 45.387, Vs

Z in =

Vs 1 = = 27.1 k I 51 w 21

(32.13)

32.2 The Return Different Matrix In this section, we extend the concept of return difference with respect to an element to the notion of return difference matrix with respect to a group of elements. In the fundamental matrix feedback-flow graph of Fig. 32.3, suppose that we break the input of the branch with transmittance X, set the input excitation vector u to zero, and apply a signal p-vector g to the right of the breaking mark, as depicted in Fig. 32.5. Then the returned signal p-vector h to the left of the breaking mark is found to be h = AXg

(32.14)

The square matrix AX is called the loop-transmission matrix and its negative is referred to as the return ratio matrix denoted by T( X ) = − AX

(32.15)

�

Φ

��

�

�

�

Θ

�

�

�=�

�

FIGURE 32.5 The physical interpretation of the loop-transmission matrix.

© 2003 by CRC Press LLC

�

0912 S1-S8 Frame55.book Page 906 Sunday, October 6, 2002 5:16 PM

906

The Circuits and Filters Handbook, Second Edition

The difference between the applied signal vector g and the returned signal vector h is given by

(

)

g – h = 1p − AX g

(32.16)

The square matrix 1p – AX relating the applied signal vector g to the difference of the applied signal vector g and the returned signal vector h is called the return difference matrix with respect to X and is denoted by F( X ) = 1p − AX

(32.17)

F( X ) = 1p + T( X )

(32.18)

Combining this with (32.15) gives

For the voltage-series feedback amplifier of Fig. 32.4, let the controlling parameters of the two con­ trolled current sources be the elements of interest. Then the return ratio matrix is found from (32.8) and (32.9a)  – 90.782 T( X ) = − AX = −  –942.507  4.131 = 42.884

45.391 455 × 10 − 4  0   0

−2.065  0 

  455 × 10 − 4  0

(32.19)

obtaining the return difference matrix as  5.131 F( X ) = 12 + T( X ) =  42.884

−2.065  1 

(32.20)

32.3 The Null Return Difference Matrix A direct extension of the null return difference for the single-loop feedback amplifier is the null return difference matrix for the multiple-loop feedback networks. Refer again to the fundamental matrix feedback-flow graph of Fig. 32.3. As before, we break the branch with transmittance X and apply a signal p-vector g to the right of the breaking mark, as illustrated in Fig. 32.6. We then adjust the input excitation n-vector u so that the total output m-vector y resulting from the inputs g and u is zero. From Fig. 32.6, the desired input excitation u is found: Du + CXg = 0

(32.21)

u = − D –1CXg

(32.22)

or

provided that the matrix D is square and nonsingular. This requires that the output y be of the same dimension as the input u or m = n. Physically, this requirement is reasonable because the effects at the output caused by g can be neutralized by a unique input excitation u only when u and y are of the same dimension. With these inputs u and g, the returned signal h to the left of the breaking mark in Fig. 32.6 is computed as © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 907 Sunday, October 6, 2002 5:16 PM

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Multiple-Loop Feedback Amplifiers

�

Φ

�� �

�

�

Θ

�

� �

�

�=�

FIGURE 32.6 The physical interpretation of the null return difference matrix.

(

)

h = Bu + AXg = −BD –1CX + AX g

(32.23)

obtaining

(

)

g − h = 1p − AX + BD –1CX g

(32.24)

ˆ Fˆ ( X ) = 1p + Tˆ ( X ) = 1p − AX + BD –1CX = 1p − AX

(32.25)

The square matrix

relating the input signal vector g to the difference of the input signal vector g, and the returned signal vector h is called the null return difference matrix with respect to X, where ˆ Tˆ ( X ) = − AX + BD −1CX = − AX

(32.26a)

Aˆ = A − BD −1C

(32.26b)

ˆ ) is known as the null return ratio matrix. The square matrix T(X Example 4. Consider again the voltage-series feedback amplifier of Fig. 29.9, an equivalent network of which is illustrated in Fig. 32.4. Assume that the voltage V25 is the output variable. Then from (32.9) V13   − 90.782 Φ= = V45  −942.507

45.391 I a  0.91748  +  Vs 0  I b   0 

[ ]

(32.27a)

= AΘ + Bu

[ ]

y = V25 = [ 45.391

I a  −2372.32]   + [0.04126] Vs I b 

[ ]

(32.27b)

Θ + Du = CΘ Substituting the coefficient matrices in (32.26b), we obtain −1100.12 Aˆ = A − BD −1C =   −942.507 © 2003 by CRC Press LLC

52, 797.6  0 

(32.28)

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giving the null return difference matrix with respect to X as −2402.29   1

51.055 ˆ = Fˆ ( X ) = 12 − AX 42.884

(32.29)

Suppose that the input current I51 is chosen as the output variable. Then, from (32.9b) we have

[ ]

y = I 51 = [−0.08252

I a  0.04126]   + [0.000862] Vs = CΘ Θ + Du I b 

[ ]

(32.30)

The corresponding null return difference matrix becomes 1.13426 ˆ =  Fˆ ( X ) = 12 − AX 42.8841

– 0.06713  1 

(32.31)

where  −2.95085 Aˆ =  −942.507

1.47543  0 

(32.32)

32.4 The Transfer-Function Matrix and Feedback In this section, we show the effect of feedback on the transfer-function matrix W(X). Specifically, we express det W(X) in terms of the det X(0) and the determinants of the return difference and null return difference matrices, thereby generalizing Blackman’s impedance formula for a single input to a multi­ plicity of inputs. Before we proceed to develop the desired relation, we state the following determinant identity for two arbitrary matrices M and N of order m × n and n × m: det(1m + MN) = det(1n + NM)

(32.33)

a proof of which may be found in [5, 6]. Using this, we next establish the following generalization of Blackman’s formula for input impedance. Theorem 1. In a multiple-loop feedback amplifier, if W(0) = D is nonsingular, then the determinant of the transfer-function matrix W(X) is related to the determinants of the return difference matrix F(X) and the null return difference matrix Fˆ (X) by det W( X ) = det W(0)

det Fˆ ( X ) det F( X )

(

)

(32.34)

PROOF: From (32.5a), we obtain W( X ) = D 1n + D −1CX 1p − AX  yielding

© 2003 by CRC Press LLC

−1

B 

(32.35)

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Multiple-Loop Feedback Amplifiers

(

[

]

[

]

[

] [

det W( X ) = det W(0) det 1n + D –1CX 1p − AX 

)

−1

(

= det W(0) det 1p + BD –1CX 1p − AX 

)

B  −1

 

](

= det W(0) det 1p − AX + BD CX 1p − AX =

–1

)

−1

(32.36)

det W(0) det Fˆ ( X ) det F( X )

The second line follows directly from (32.33). This completes the proof of the theorem. As indicated in (30.4), the input impedance Z(x) looking into a terminal pair can be conveniently expressed as Z ( x ) = Z (0)

F (input short-ciruited) F (input open-circuited)

(32.37)

A similar expression can be derived from (32.34) if W(X) denotes the impedance matrix of an n-port network of Fig. 32.1. In this case, F(X) is the return difference matrix with respect to X for the situation when the n ports where the impedance matrix are defined are left open without any sources, and we write F(X) = F(input open-circuited). Likewise, Fˆ (X) is the return difference matrix with respect to X for the input port-current vector Is and the output port-voltage vector V under the condition that Is is adjusted so that the port-voltage vector V is identically zero. In other words, Fˆ (X) is the return difference matrix for the situation when the n ports, where the impedance matrix is defined, are short-circuited, and we write Fˆ (X) = F(input short-circuited). Consequently, the determinant of the impedance matrix Z(X) of an n-port network can be expressed from (32.34) as det Z( X ) = det Z(0)

det F(input short-circuited) det F(input open-circuited)

(32.38)

Example 5. Refer again to the voltage-series feedback amplifier of Fig. 29.9, an equivalent network of which is illustrated in Fig. 32.4. As computed in (32.20), the return difference matrix with respect to the two controlling parameters is given by −2.065  1 

 5.131 F( X ) = 12 + T( X ) =  42.884

(32.39)

the determinant of which is: det F( X ) = 93.68646

(32.40)

If V25 of Fig. 32.4 is chosen as the output and Vs as the input, the null return difference matrix is, from (32.29), 51.055 ˆ = Fˆ ( X ) = 12 − AX 42.884 the determinant of which is: © 2003 by CRC Press LLC

–2402.29   1

(32.41)

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The Circuits and Filters Handbook, Second Edition

det Fˆ ( X ) = 103, 071

(32.42)

By appealing to (32.34), the feedback amplifier voltage gain V25 /Vs can be written as w(X ) =

det Fˆ ( X ) V25 103, 071 = w (0 ) = 0.04126 = 45.39 Vs det F( X ) 93.68646

(32.43)

confirming (29.44), where w(0) = 0.04126, as given in (32.27b). Suppose, instead, that the input current I51 is chosen as the output and Vs as the input. Then, from (32.31), the null return difference matrix becomes 1.13426 Fˆ ( X ) = 12 − Aˆ ( X ) =  42.8841

−0.06713  1 

(32.44)

the determinant of which is: det Fˆ ( X ) = 4.01307

(32.45)

By applying (32.34), the amplifier input admittance is obtained as w(X ) =

det Fˆ ( X ) I 51 = w (0 ) det F( X ) Vs

= 8.62 × 10 − 4

(32.46)

4.01307 = 36.92 µmho 93.68646

or 27.1 kΩ, confirming (32.13), where w(0) = 862 µmho is found from (32.30). Another useful application of the generalized Blackman’s formula (32.38) is that it provides the basis of a procedure for the indirect measurement of return difference. Refer to the general feedback network of Fig. 32.2. Suppose that we wish to measure the return difference F(y21) with respect to the forward short circuit transfer admittance y21 of a two-port device characterized by its y parameters yij . Choose the two controlling parameters y21 and y12 to be the elements of interest. Then, from Fig. 31.2 we obtain I a  y 21 Θ =   =  I b   0

0  V1     = XΦ Φ y12  V2 

(32.47)

where Ia and Ib are the currents of the voltage-controlled current sources. By appealing to (32.38), the impedance looking into terminals a and b of Fig. 31.2 can be written as z aa ,bb ( y12 , y 21 ) = z aa ,bb (0, 0)

det F(input short-circuited) det F(input open-circuited)

(32.48)

When the input terminals a and b are open-circuited, the resulting return difference matrix is exactly the same as that found under normal operating conditions, and we have F11 F(input open-circuited) = F( X ) =  F21

© 2003 by CRC Press LLC

F12   F22 

(32.49)

0912 S1-S8 Frame55.book Page 911 Sunday, October 6, 2002 5:16 PM

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Multiple-Loop Feedback Amplifiers

�

Φ�

��

��

�

FIGURE 32.7 The block diagram of a multivariable open-loop control system.

Because F( X ) = 12 − AX

(32.50)

the elements F11 and F21 are calculated with y12 = 0, whereas F12 and F22 are evaluated with y21 = 0. When the input terminals a and b are short circuited, the feedback loop is interrupted and only the second row and first column element of the matrix A is nonzero, and we obtain det F(input short-circuited) = 1

(32.51)

Because X is diagonal, the return difference function F(y21) can be expressed in terms of det F(X) and the cofactor of the first row and first column element of F(X): F ( y 21 ) =

det F( X ) F22

(32.52)

Substituting these in (32.48) yields F ( y12 )

y21 = 0

F ( y 21 ) =

z aa ,bb (0, 0)

(

z aa ,bb y12, y 21

)

(32.53)

where F22 = 1 − a22 y12 y

21 = 0

= F ( y12 )

y21 = 0

(32.54)

and a22 is the second row and second column element of A. Formula (32.53) was derived earlier in (31.7) using the network arrangements of Figs. 31.7 and 31.8 to measure the elements F(y12)y21 =0 and zaa,bb(0,0), respectively.

32.5 The Sensitivity Matrix We have studied the sensitivity of a transfer function with respect to the change of a particular element in the network. In a multiple-loop feedback network, we are usually interested in the sensitivity of a transfer function with respect to the variation of a set of elements in the network. This set may include either elements that are inherently sensitive to variation or elements where the effect on the overall amplifier performance is of paramount importance to the designers. For this, we introduce a sensitivity matrix and develop formulas for computing multiparameter sensitivity function for a multiple-loop feedback amplifier [7]. Figure 32.7 is the block diagram of a multivariable open-loop control system with n inputs and m outputs, whereas Fig. 32.8 is the general feedback structure. If all feedback signals are obtainable from the output and if the controllers are linear, no loss of generality occurs by assuming the controller to be of the form given in Fig. 32.9. Denote the set of Laplace-transformed input signals by the n-vector u, the set of inputs to the network X in the open-loop configuration of Fig. 32.7 by the p-vector o , and the set of outputs of the network © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 912 Sunday, October 6, 2002 5:16 PM

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The Circuits and Filters Handbook, Second Edition

�

��

�

Φ�

�

FIGURE 32.8 The general feedback structure.

� �

+

∑

Φ�

��

�

��

+

��

FIGURE 32.9 The general feedback configuration.

X of Fig. 32.7 by the m-vector yo. Let the corresponding signals for the closed-loop configuration of Fig. 32.9 be denoted by the n-vector u, the p-vector c, and the m-vector yc , respectively. Then, from Figs. 32.7 and 32.9, we obtain the following relations: y o = XΦ Φo

(32.55a)

Φo = H1u

(32.55b)

y c = XΦ Φc

(32.55c)

Φc = H 2 (u + H3 y c )

(32.55d)

where the transfer-function matrices X, H1, H2, and H3 are of order m × p, p × n, p × n and n × m, respectively. Combining (32.55c) and (32.55d) yields

(1m − XH2H3 )y c = XH2u

(32.56)

y c = (1m − XH 2H3 ) XH 2u

(32.57)

or −1

The closed-loop transfer function matrix W(X) that relates the input vector u to the output vector yc is defined by the equation y c = W( X )u identifying from (32.57) the m × n matrix © 2003 by CRC Press LLC

(32.58)

0912 S1-S8 Frame55.book Page 913 Tuesday, October 8, 2002 12:50 PM

913

Multiple-Loop Feedback Amplifiers

W( X ) = (1m − XH 2H3 ) XH 2 −1

(32.59)

Now, suppose that X is perturbed from X to X + X. The outputs of the open-loop and closed-loop systems of Fig. 32.7 and 32.9 will no longer be the same as before. Distinguishing the new from the old variables by the superscript +, we have y o+ = X + Φo

(32.60a)

y c+ = X + Φc+

(32.60b)

(

Φc+ = H 2 u + H3 y c+

)

(32.60c)

where o remains the same. We next proceed to compare the relative effects of the variations of X on the performance of the openloop and the closed-loop systems. For a meaningful comparison, we assume that H1, H2, and H3 are such that when there is no variation of X, yo = yc. Define the error vectors resulting from perturbation of X as E o = y o − y o+

(32.61a)

E c = y c − y c+

(32.61b)

A square matrix relating Eo to Ec is called the sensitivity matrix (X) for the transfer function matrix W(X) with respect to the variations of X: E c = ( X )E o

(32.62)

In the following, we express the sensitivity matrix (X) in terms of the system matrices X, H2, and H3. The input and output relation similar to that given in (32.57) for the perturbed system can be written as

(

y c+ = 1m − X + H 2H3

)

−1

X + H 2u

(32.63)

Substituting (32.57) and (32.63) in (32.61b) gives

(

E c = y c − y c+ = (1m − XH 2H3 ) XH 2 − 1m − X + H 2H3  −1

(

= 1m − X + H 2H3

(

+

= 1m − X H 2H3

(

) {[1 − (X + δX)H H ](1 −1

2

m

)

−1

= − 1m − X + H 2H3

3

[XH − δXH H (1 2

)

−1

2

3

m

[

m

)

−1

X + H 2 u 

}

− XH 2H3 ) XH 2 − ( X + δX )H 2 u −1

]

(32.64)

− XH 2H3 ) XH 2 − XH 2 − δXH 2 u −1

]

δXH 2 1n + H3 W( X ) u

From (32.55d) and (32.58), we obtain

[

]

Φc = H 2 1n + H3 W( X ) u

(32.65)

Because by assuming that yo = yc, we have

[

]

Φo = Φc = H 2 1n + H3 W( X ) u © 2003 by CRC Press LLC

(32.66)

0912 S1-S8 Frame55.book Page 914 Sunday, October 6, 2002 5:16 PM

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The Circuits and Filters Handbook, Second Edition

yielding

(

)

[

]

E o = y o − y o+ = X − X + Φo = − δXH 2 1n + H3 W( X ) u

(32.67)

Combining (32.64) and (32.67) yields an expression relating the error vectors Ec and Eo of the closedloop and open-loop systems by

(

E c = 1m − X + H 2H3

)

−1

Eo

(32.68)

)

(32.69)

obtaining the sensitivity matrix as

(

( X ) = 1m − X + H 2H3

−1

For small variations of X, X+ is approximately equal to X. Thus, in Fig. 32.9, if the matrix triple product XH2H3 is regarded as the loop-transmission matrix and –XH2H3 as the return ratio matrix, then the difference between the unit matrix and the loop-transmission matrix, 1m − XH 2H3

(32.70)

can be defined as the return difference matrix. Therefore, (32.69) is a direct extension of the sensitivity function defined for a single-input, single-output system and for a single parameter. Recall that in (30.33) we demonstrated that, using the ideal feedback model, the sensitivity function of the closed-loop transfer function with respect to the forward amplifier gain is equal to the reciprocal of its return difference with respect to the same parameter. In particular, when W(X), X, and X are square and nonsingular, from (32.55a), (32.55b), and (32.58), (32.61) can be rewritten as

[

]

E c = y c − y c+ = W( X ) − W + ( X ) u = − δW( X )u

[

]

E o = y o − y o+ = XH1 − X + H1 u = − δXH1u

(32.71a) (32.71b)

If H1 is nonsingular, u in (32.71b) can be solved for and substituted in (32.71a) to give E c = δW( X )H1−1 (δX ) E o −1

(32.72)

As before, for meaningful comparison, we require that yo = yc or XH1 = W( X )

(32.73)

From (32.72), we obtain E c = δW( X )W −1 ( X )X(δX ) E o

(32.74)

( X ) = W( X )W −1 ( X )X(X )

(32.75)

−1

identifying that −1

This result is to be compared with the scalar sensitivity function defined in (30.26), which can be put in the form ( x ) = (δw )w −1x (δx ) © 2003 by CRC Press LLC

−1

(32.76)

0912 S1-S8 Frame55.book Page 915 Tuesday, October 8, 2002 12:50 PM

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Multiple-Loop Feedback Amplifiers

32.6 Multiparameter Sensitivity In this section, we derive formulas for the effect of change of X on a scalar transfer function w(X). Let xk , k = 1, 2, …, pq, be the elements of X. The multivariable Taylor series expansion of w(X) with respect to xk is given by δw =

pq

∂w

∑ ∂x

k =1

pq pq

∂ 2w δx j δx k +L 2! j k

(32.77)

δx k

(32.78)

∑ ∑ ∂x ∂x

δx k +

j =1k =1

k

The first-order perturbation can then be written as δw ≈

pq

∂w

∑ ∂x

k =1

k

Using (30.26), we obtain δx δw pq ≈ ∑ ( x k ) k w k =1 xk

(32.79)

This expression gives the fractional change of the transfer function w in terms of the scalar sensitivity functions (xk). Refer to the fundamental matrix feedback-flow graph of Fig. 32.3. If the amplifier has a single input and a single output from (32.35), the overall transfer function w(X) of the multiple-loop feedback amplifier becomes

(

w ( X ) = D + CX 1p − AX

)

−1

B

(32.80)

When X is perturbed to X+ = X + X, the corresponding expression of (32.80) is given by

(

w ( X ) + δw ( X ) = D + C( X + δX ) 1p − AX − AδX

)

−1

B

(32.81)

or

(

δw ( X ) = C ( X + δX ) 1p − AX − AδX 

)

−1

(

− X 1p − AX

)

−1

B 

(32.82)

As X approaches zero, we obtain

(

δw ( X ) = C ( X + δX ) − X 1p − AX 

(

= C δX + X 1p − AX 

( ) ≈ C(1 − XA )

= C 1q − XA q

)

−1

) (1 −1

p

)(

− AX − AδX  1p − AX − AδX 

(

AδX  1p − AX − AδX 

−1

(δX )(1p − AX − AδX )

−1

(δX )(1p − AX )

−1

−1

)

−1

)

−1

B

B (32.83)

B

B

where C is a row q vector and B is a column p vector. Write

[

C = c1 © 2003 by CRC Press LLC

c2

L

cq

]

(32.84a)

0912 S1-S8 Frame55.book Page 916 Sunday, October 6, 2002 5:16 PM

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The Circuits and Filters Handbook, Second Edition

[

B′ = b1

(

˜ = X 1 − AX W p

L

b2

bp

) = (1 − XA) −1

−1

q

]

(32.84b)

[ ]

X = w˜ ij

(32.84c)

The increment δw(X) can be expressed in terms of the elements of (32.84) and those of X. In the case where X is diagonal with

[

X = diag x1

L

x2

xp

]

(32.85)

where p = q, the expression for δw(X) can be succinctly written as δw ( X ) =

p

p

p

i

i =1 k =1 j =1 p

=

 w˜ ik   w˜ kj   (δx k ) x  b j  k k 

∑∑∑ c  x p

p

∑∑∑ i =1 k =1 j =1

(32.86) c iw˜ ikw˜ kjb j δx k xk xk

Comparing this with (32.79), we obtain an explicit form for the single-parameter sensitivity function as ( x k ) =

p

p

∑∑

c iw˜ ikw˜ kjb j

i =1 j =1

(32.87)

x kw ( X )

Thus, knowing (32.84) and (32.85), we can calculate the multiparameter sensitivity function for the scalar transfer function w(X) immediately. Example 6. Consider again the voltage-series feedback amplifier of Fig. 29.9, an equivalent network of which is shown in Fig. 32.4. Assume that Vs is the input and V25 the output. The transfer function of interest is the amplifier voltage gain V25 /Vs. The elements of main concern are the two controlling parameters of the controlled sources. Thus, we let ˜1 α X=  0

0  0.0455 = ˜ 2   0 α

  0.0455 0

(32.88)

From (32.27) we have  −90.782 A= −942.507 B′ = [0.91748 C = [ 45.391

45.391  0 

(32.89a)

0]

(32.89b)

−2372.32]

(32.89c)

yielding  4.85600 ˜ = X(1 − AX )−1 = 10 −4  W 2 −208.245 © 2003 by CRC Press LLC

10.02904   24.91407

(32.90)

0912 S1-S8 Frame55.book Page 917 Sunday, October 6, 2002 5:16 PM

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Multiple-Loop Feedback Amplifiers

Also, from (32.13) we have w(X ) =

V25 = 45.387 Vs

(32.91)

˜ 2, we apply (32.87) and obtain ˜ 1 and α To compute the sensitivity functions with respect to α c i w˜ i1w˜ 1 j b j c 1w˜ 11w˜ 11b1 + c 1w˜ 11w˜ 12b2 + c 2w˜ 21w˜ 11b1 + c 2w˜ 21w˜ 12b2 = = 0.01066 (32.92a) ˜ ˜ 1w α i = 1 j = 1 α 1w ( X ) 2

2

˜ 1) = ∑ ∑  (α

˜ 2) =  (α

c 1w˜ 12w˜ 21b1 + c 1w˜ 12w˜ 22b2 + c 2w˜ 22w˜ 21b1 + c 2w˜ 22w˜ 22b2 = 0.05426 ˜ 2w α

(32.92b)

As a check, we use (30.30) to compute these sensitivities. From (29.45) and (29.52), we have ˜ 1 ) = 93. 70 F (α

(32.93a)

˜ 2 ) = 18. 26 F (α

(32.93b)

) ˜ 1 ) = 103.07 × 103 F (α

(32.93c)

) ˜ 2 ) = 2018. 70 F (α

(32.93d)

Substituting these in (30.30) the sensitivity functions are: ˜ 1) =  (α

1 1 − = 0. 01066 ˜ 1 ) Fˆ (α ˜ 1) F (α

(32.94a)

˜ 2) =  (α

1 1 − = 0.05427 ˜ 2 ) Fˆ (α ˜ 2) F (α

(32.94b)

confirming (32.92). ˜ 2 by 6%. The fractional change of the voltage gain w(X) is ˜ 1 is changed by 4% and α Suppose that α found from (32.79) as ˜ ˜ δα δα δw ˜ 1 ) 1 +  (α ˜ 2 ) 2 = 0. 003683 ≈  (α ˜1 ˜2 w α α

(32.95)

or 0.37%.

References [1] F. H. Blecher, “Design principles for single loop transistor feedback amplifiers,” IRE Trans. Circuit Theory, vol. CT-4, pp. 145–156, 1957. [2] H. W. Bode, Network Analysis and Feedback Amplifier Design, Princeton, NJ: Van Nostrand, 1945. [3] W.-K. Chen, “Indefinite-admittance matrix formulation of feedback amplifier theory,” IEEE Trans. Circuits Syst., vol. CAS-23, pp. 498–505, 1976. [4] W.-K. Chen, “On second-order cofactors and null return difference in feedback amplifier theory,” Int. J. Circuit Theory Appl., vol. 6, pp. 305–312, 1978. © 2003 by CRC Press LLC

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[5] W.-K. Chen, Active Network and Feedback Amplifier Theory, New York: McGraw-Hill, 1980, chaps. 2, 4, 5, 7. [6] W.-K. Chen, Active Network and Analysis, Singapore: World Scientific, 1991, chaps. 2, 4, 5, 7. [7] J. B. Cruz, Jr. and W. R. Perkins, “A new approach to the sensitivity problem in multivariable feedback system design,” IEEE Trans. Autom. Control, vol. AC-9, pp. 216–223, 1964. [8] S. S. Haykin, Active Network Theory, Reading, MA: Addison-Wesley, 1970. [9] E. S. Kuh and R. A. Rohrer, Theory of Linear Active Networks, San Francisco: Holden-Day, 1967. [10] I. W. Sandberg, “On the theory of linear multi-loop feedback systems,” Bell Syst. Tech. J., vol. 42, pp. 355–382, 1963.

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V

Nonlinear Circuits Leon O. Chua University of California 33 Qualitative Analysis Martin Hasler Introduction • Resistive Circuits • Autonomous Dynamic Circuits • Nonautonomous Dynamic Circuits

34 Synthesis and Design of Nonlinear Circuits A. Rodriguez-Vázquez, M. Delgado-Restituto, J. L. Huertas, F. Vidal Introduction • Approximation Issues • Aggregation, Scaling, and Transformation Circuits • Piecewise-Linear Circuitry • Polynomials, Rational, and Piecewise-Polynomial Functions • Sigmoids, Bells, and Collective Computation Circuits • Extension to Dynamic Systems

35 Representation, Approximation, and Identification Guanrong Chen Introduction • Representation • Approximation • Identification

36 Transformation and Equivalence Wolfgang Mathis General Equivalence Theorems for Nonlinear Circuits • Normal Forms • Dimensionless Form • Equivalence between Nonlinear Resistive Circuits • Equivalence of Lumped n-Port Networks • Equivalence between Nonlinear Dynamic Circuits

37 Piecewise-Linear Circuits and Piecewise-Linear Analysis J. Vandewalle, L. Vandenberghe Introduction and Motivation • Hierarchy of Piecewise-Linear Models and Their Representations • Piecewise-Linear Models for Electronic Components • Structural Properties of Piecewise-Linear Resistive Circuits • Analysis of Piecewise-Linear Resistive Circuits • Piecewise-Linear Dynamic Circuits • Efficient Computer-Aided Analysis of PWL Circuits

38 Simulation Erik Lindberg Numerical Solution of Nonlinear Algebraic Equations • Numerical Integration of Nonlinear Differential Equations • Use of Simulation Programs

39 Cellular Neural Networks Tamás Roska Introduction: Definition and Classification • The Simple CNN Circuit Structure • The Stored Program CNN Universal Machine and the Analogic Supercomputer Chip • Applications • Template Library: Analogical CNN Algorithms • Recent Advances

40 Birfurcation and Chaos Michael Peter Kennedy Introduction to Chaos • Chua’s Circuit: A Paradigm for Chaos • Chua’s Oscillator • Van der Pol Neon Bulb Oscillator • Synchronization of Chaotic Circuits • Applications of Chaos

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33 Qualitative Analysis 33.1 Introduction 33.2 Resistive Circuits Number of Solutions of a Resistive Circuit • Bounds on Voltages and Currents • Monotonic Dependence

33.3 Autonomous Dynamic Circuits Introduction • Convergence to DC-Operating Points

Martin Hasler

33.4 Nonautonomous Dynamic Circuits

Swiss Federal Institute of Technology

Introduction • Boundedness of the Solutions • Unique Asymptotic Behavior

33.1 Introduction The main goal of circuit analysis is to determine the solution of the circuit, i.e., the voltages and the currents in the circuit, usually as functions of time. The advent of powerful computers and circuit analysis software has greatly simplified this task. Basically, the circuit to be analyzed is fed to the computer through some circuit description language, or it is analyzed graphically, and the software will produce the desired voltage or current waveforms. Progress has rendered the traditional paper-and-pencil methods obsolete, in which the engineer’s skill and intution led the way through series of clever approximations, until the circuits equations can be solved analytically. A closer comparison of the numerical and the approximate analytical solution reveals, however, that the two are not quite equivalent. Although the former is precise, it only provides the solution of the circuit with given parameters, whereas the latter is an approximation, but the approximate solutions most often is given explicity as a function of some circuit parameters. Therefore, it allows us to assess the influence of these parameters on the solution. If we rely entirely on the numerical solution of a circuit, we never get a global picture of its behavior, unless we carry out a huge number of analyses. Thus, the numerical analysis should be complemented by a qualitative analysis, one that concentrates on general properties of the circuit, properties that do not depend on the particular set of circuit parameters.

33.2 Resistive Circuits The term resistive circuits is not used, as one would imagine, for circuits that are composed solely of resistors. It admits all circuit elements that are not dynamic, i.e., whose constitutive relations do not involve time derivatives, integrals over time, or time delays, etc. Expressed positively, resistive circuit elements are described by constitutive relations that involve only currents and voltages at the same time instants. Physical circuits can never be modeled in a satisfactory way by resistive circuits, but resistive circuits appear in many contexts as auxiliary constructs. The most important problem that leads to a resistive circuit is the determination of the equilibrium points, or, as is current use in electronics, the DC-operating points, of a dynamic circuit. The DC-operating points of a circuit correspond in a one-to-one fashion

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V

I

FIGURE 33.1 Symbols of the V- and the I-resistor.

to the solutions of the resistive circuit obtained by removing the capacitors and by short circuiting the inductors. The resistive circuit associated with the state equations of a dynamic circuit in discussed in [1]. Among the resistive circuit elements we find, of course, the resistors. For the purposes of this intro­ duction, we distinguish between, linear resistors, V-resistors and I-resistors. V-resistors are voltage controlled, i.e., defined by constitutive relations of the form i = g (v )

(33.1)

In addition, we require that g is a continuous, increasing function of v, defined for all real v. Dually, an I-resistor is current controlled, i.e., defined by a constitutive relation of the form v = h(i )

(33.2)

In addition, we require that h is a continuous, increasing function of i, defined for all real i. We use the symbols of Fig. 33.1 for V- and I-resistor. Linear resistors are examples of both I- and V-resistors. An example of a V-resistor that is not an I-resistor is the junction diode, modeled by its usual exponential constitutive relation

(

)

i = I s e v nVT − 1

(33.3)

Although (33.3) could be solved for v and thus the constitutive relation could be written in the form (33.2), the resulting function h would be defined only for currents between –Is and +∞, which is not enough to qualify for an I-resistor. For the same reason, the static model for a Zener diode would be an I-resistor, but not a V-resistor. Indeed, the very nature of the Zener diode limits its voltages on the negative side. A somewhat strange by-product of our definition of V- and I-resistors is that independent voltage sources are I-resistors and independent current sources are V-resistors. Indeed, a voltage source of value E has the constitutive relation v=E

(33.4)

which clearly is of the form (33.2), with a constant function h, and a current source of value I has the form i=I

(33.5)

which is of the form (33.1) with a constant function g. Despite this, we shall treat the independent sources as a different type of element. Another class of resistive elements is the controlled sources. We consider them to be two-ports, e.g., a voltage-controlled voltage source (VCVS). A VCVS is the two-port of Fig. 33.2, where the constitutive relations are

+ V1 − © 2003 by CRC Press LLC

i1

i2 + −

v1 = αv 2

(33.6)

i1 = 0

(33.7)

+ V2 −

FIGURE 33.2 VCVS as a two-port.

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+ V1 −

i1

+ + −

∞

i2

+ V − 2

i1

i2

+

V1

V2

−

−

FIGURE 33.3 Operational amplifier as a juxtaposition of a nullator and a norator.

βRi′ βFi i

i′

FIGURE 33.4 Equivalent circuit of a bipolar npn transistor.

The other controlled sources have similar forms. Another useful resistive circuit element is the ideal operational amplifier. It is a two-port defined by the two constitutive relations v1 = 0

(33.8)

i1 = 0

(33.9)

This two-port can be decomposed into the juxtaposition of two singular one-ports, the nullator and the norator, as shown in Fig. 33.3. the nullator has two constitutive relations: v = 0 i = 0

(33.10)

whereas the norator has no constitutive relation. For all practical purposes, the resistive circuit elements mentioned thus far are sufficient. By this we mean that all nonlinear resistive circuits encountered in practice possess an equivalent circuit composed of nonlinear resistors, independent and controlled sources, and nullator–norator pairs. Figure 33.4 illus­ trates this fact. Here, the equivalent circuit of the bipolar transistor is modeled by the Ebers–Moll equations: 1  1+  i1   βF   =  i  2   −1 

  1 1 +  βR  −1

 g (v1 )    g (v )  2

(33.11)

The function g is given by the right-hand side of (33.3). Actually, the list of basic resistive circuit elements given so far is redundant, and the nullator–norator pair renders the controlled sources superfluous. An example of a substitution of controlled sources by nullator–norator pairs is given in Fig. 33.4. Equivalent circuits exist for all four types of controlled sources with nullator–norator pairs. Figure 33.5 gives an equivalent circuit for a voltage-controlled current source (VCCS), where the input port is floating with respect to the output port. The system of equations that describes a resistive circuit is the collection of Kirchhoff equations and the constitutive relations of the circuit elements. It has the following form (if we limit ourselves to resistors, independent sources, nullators, and norators): © 2003 by CRC Press LLC

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+

V1/R

V1 −

R

FIGURE 33.5 Equivalent circuit for a floating voltage-controlled current source.

Ai = 0 (Kirchhoff ’s voltage law)

(33.12)

Bv = 0 (Kirchhoff ’s voltage law)

(33.13)

ik = g (v k ) (V − resistor)

(33.14)

v k = h(ik )

(33.15)

(I − resistor)

vk = E k (independent voltage source)

(33.16)

ik = I k (independent current source)

(33.17)

v k = 0  ik = 0

(33.18)

(nullators)

In this system of equations, the unknowns are the branch voltages and the branch currents v1    v2 v =   M    v   b

i1     i2  i =   M    i   b

(33.19)

where the b is the number of branches. Because we have b linearly independent Kirchhoff equations [2], the system contains 2b equations and 2b unknowns. A solution ξ =  vi  of the system is called a solution of the circuit. It is a collection of branch voltages and currents that satisfy (33.12) to (33.19).

Number of Solutions of a Resistive Circuit As we found earlier, the number of equations of a resistive circuit equals the number of unknowns. One may therefore expect a unique solution. This may be the norm, but it is far from being generally true. It is not even true for linear resistive circuits. In fact, the equations for a linear resistive circuit are of the form H = e

(33.20)

where the 2b × 2b matrix H contains the resistances and elements of value 0, ±1, whereas the vector e contains the source values and zeroes. The solution of (33.20) is unique iff the determinant of H differs from zero. If it is zero, then the circuit has either infinitely many solutions or no solution at all. Is such a case realistic? The answer is yes and no. Consider two voltages sources connected as shown in Fig. 33.6.

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i

E1

+

+

−

−

E2

FIGURE 33.6 Circuit with zero or infinite solutions.

i

E1

+ −

+ −

E2

FIGURE 33.7 Circuit with exactly one solution.

R2

R1 E

R3

− + + −

R4

FIGURE 33.8 Circuit with one, zero, or infinite solutions.

If E1 ≠ E2 , the constitutive relations of the sources are in contradiction with Kirchhoff ’s voltage law (KVL), and thus the circuit has no solution, whereas when E1 = E2, the current i in Fig. 33.6 is not determined by the circuit equations, and thus the circuit has infinitely many solutions. One may object that the problem is purely academic, because in practice wires as connections have a small, but positive, resistance, and therefore one should instead consider the circuit of Fig. 33.7, which has exactly one solution. Examples of singular linear resistive circuits exist that are much more complicated. However, the introduction of parasitic elements always permits us to obtain a circuit with a single solution, and thus the special case in which the matrix H in (33.9) is singular can be disregarded. Within the framework of linear circuits, this attitude is perfectly justified. When a nonlinear circuit model is chosen, however, the situation changes. An example clarifies this point. Consider the linear circuit of Fig. 33.8. It is not difficult to see that it has exactly one solution, except when R1R3 = R2 R4

(33.21)

In this case, the matrix H in (33.29) is singular and the circuit of Fig. 33.8 has zero or infinitely many solutions, depending on whether E differs from zero. From the point of view of linear circuits, we can disregard this singular case because it arises only when (33.21) is exactly satisfied with infinite precision. Now, replace resistor R4 by a nonlinear resistor, where the characteristic is represented by the bold line in Fig. 33.9. The resulting circuit is equivalent to the connection of a voltage source, a linear resistor, and the nonlinear resistor, as shown in Fig. 33.10. Its solutions correspond to the intersections of the nonlinear resistor characteristic and the load line (Fig. 33.9). Depending on the value of E, either one, two, or three solutions are available. Although we still need infinite precision to obtain two solutions, this is not the case for one or three solutions. Thus, more than one DC-operating point may be observed in electronic circuits. Indeed, for static memories, and multivibrators in general, multiple DC-operating points are an essential feature.

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i

v E

load line

nonlinear resistor characteristic

R2 R1

FIGURE 33.9 Characteristic of the nonlinear resistor and solutions of the circuit of Fig. 33.10.

R3

− +

+ E −

i − + E −

R1R3 R2

+ v −

FIGURE 33.10 Circuit with one, two or three solutions.

The example of Fig. 33.10 shows an important aspect of the problem. The number of solutions depends on the parameter values of the circuit. In the example the value of E determines whether one, two, or three solutions are available. This is not always the case. An important class of nonlinear resistive circuits always has exactly one solutions, irrespective of circuit parameters. In fact, for many applications, e.g., amplification, signal shaping, logic operations, etc., it is necessary that a circuit has exactly one DC-oper­ ating point. Circuits that are designed for these functionalities should thus have a unique DC-operating point for any choice of element values. If a resistive circuit contains only two-terminal resistors with increasing characteristics and sources, but no nonreciprocal element such as controlled sources, operational amplifiers, or transistors, the solution is usually unique. The following theorem gives a precise statement. Theorem 33.1: A circuit composed of independent voltage and current sources and strictly increasing resistors without loop of voltage sources and without cutset of current sources has at most one solution. The interconnection condition concerning the sources is necessary. The circuit of Fig. 33.6 is an illustration of this statement. Its solution is not unique because of the loop of voltage sources. The loop is no longer present in the circuit of Fig. 33.7, which satisfies the conditions of Theorem 33.1, and which indeed has a unique solution. If the resistor characteristics are not strictly increasing but only increasing (i.e., if the v-i curves have horizontal or vertical portions), the theorem still holds, if we exclude loops of voltage sources and I – resistors, and cutsets of current sources and V – resistors. Theorem 33.1 guarantees the uniqueness of the solution, but it cannot assure its existence. On the other hand, we do not need increasing resistor characteristics for the existence. Theorem 33.2: Let a circuit be composed of independent voltage and current sources and resistors whose characteristics are continuous and satisfy the following passivity condition at infinity: v → + ∞ ⇔ i → + ∞ and v → − ∞ ⇔ i → − ∞ © 2003 by CRC Press LLC

(33.22)

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FIGURE 33.11 Feedback structure.

FIGURE 33.12 Short-open-circuit combinations for replacing the transistors.

If no loop of voltage sources and no cutset of current sources exist, then we have at least one solution of the circuit. For refinements of this theorem, refer to [1] and [3]. If we admit nonreciprocal elements, neither Theorem 33.1 nor 33.2 remain valid. Indeed, the solution of the circuit of Fig. 33.10 may be nonunique, even though the nonlinear resistor has a strictly increasing characteristic. In order to ensure the existence and uniqueness of a nonreciprocal nonlinear resistive circuit, nontrivial constraints on the interconnection of the elements must be observed. The theorems below give different, but basically equivalent, ways to formulate these constraints. The first results is the culminating point of a series of papers by Sandberg and Wilson [3]. It is based on the following notion. Definition 33.1. • The connection of the two bipolar transistors shown in Fig. 33.11 is called a feedback structure. The type of the transistors and the location of the collectors and emitters is arbitrary. • A circuit composed of bipolar transistors, resistors, and independent sources contains a feedback structure, if it can be reduced to the circuit of Fig. 33.11 by replacing each voltage source by a short circuit, each current source by an open circuit, each resistor and diode by an open or a short circuit, and each transistor by one of the five short-open-circuit combinations represented in Fig. 33.12. Theorem 33.3: Let a circuit be composed of bipolar transistors, described by the Ebers–Moll model, positive linear resistors, and independent sources. Suppose we have no loop of voltage sources and no cutset of current sources. If the circuit contains no feedback structure, it has exactly one solution. This theorem [4] is extended in [5] to MOS transistors. The second approach was developed by Nishi and Chua. Instead of transistors, it admits controlled sources. In order to formulate the theorem, two notions must be introduced. Definition 33.2. A circuit composed of controlled sources, resistors, and independent sources satisfies the interconnection condition, if the following conditions are satisfied: • No loop is composed of voltage sources, output ports of (voltage or current) controlled voltage sources, and input ports of current controlled (voltage or current) sources. • No cutset is composed of current sources, outputs ports of (voltage or current) controlled current sources, and input ports of voltage controlled (voltage or current) sources. © 2003 by CRC Press LLC

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Definition 33.3. A circuit composed exclusively of controlled sources has a complementary tree structure if both the input and output ports each form a tree. The fundamental loop matrix of the input port tree has the form

[ ]

B = BT 1

(33.23)

The circuit is said to have a positive (negative) complementary tree structure, if the determinant of BT is positive (negative). Theorem 33.4: Suppose a circuit composed of controlled sources, strictly increasing resistors satisfying (33.22), and independent sources satisfies the interconnection condition. If, by replacing each resistor either by a short circuit or an open circuit, all independent and some dependent voltage sources by short circuits, and all independent and some dependent current sources by open circuits, one never obtains a negative complemen­ tary tree structure, the circuit has exactly one solution [6]. A similar theorem for circuits with operational amplifiers instead of controlled sources is proved in [7]. The third approach is that of Hasler [1, 8]. The nonreciprocal elements here are nullator–norator pairs. Instead of reducing the circuit by some operations in order to obtain a certain structure, we must orient the resistors in certain way. Again, we must first introduce a new concept. Definition 33.4. Let a circuit be composed of nullator-norator pairs, resistors, and independent voltage and current sources. A partial orientation of the resistors is uniform, if the following two conditions are satisfied: • Every oriented resistor is part of an evenly directed loop composed only of oriented registors and voltages sources • Every oriented resistor is part of an evenly directed cutset composed only of norators, oriented resistors, and voltage sources Theorem 33.5: Let a circuit be composed of nullator-norator pairs, V- and I-resistors, and independent voltage and current sources. If the following conditions are satisfied, the circuit has exactly one solutions: • The norators, I-resistors, and the voltage sources together form a tree. • The nullators, I-resistors, and the voltage sources together form a tree. • The resistors have no uniform partial orientation, except for the trivial case, in which no resistor is oriented. We illustrate the conditions of this theorem with the example of Fig. 33.10. In Fig. 33.13 the resistors are specified as V- and I-resistors and a uniform orientation of the resistors is indicated. Note that the nonlinear resistor is a V-resistor, but not an I-resistor, because its current saturates. The linear resistors, however, are both V- and I-resistors. The choice in Fig. 33.13 is made in order to satisfy the first two conditions of Theorem 33.5. Correspondingly, in Fig. 33.14 and 33.15 the norator–I-resistor–voltage source tree and the nullator-I-resistor voltage source tree are represented. Because the third condition is not satisfied, Theorem 33.5 cannot guarantee a unique solution. Indeed, as explained earlier, this circuit may have three solutions. Theorem 33.5 has been generalized to controlled sources, to resistors that are increasing but neither voltage nor current controlled (e.g., the ideal diode), and to resistors that are decreasing instead of increasing [9]. Theorems 33.3, 33.4, and 33.5 have common features. Their conditions concern the circuit structure — the circuit graph that expresses the interconnection of the elements and the type of elements that occupy the branches of the graph, but not the element values. Therefore, the theorems guarantee the existence and uniqueness of the solution for whole classes of circuits, in which the individual circuits differ by

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V

I

I V

FIGURE 33.13 Circuit of Fig. 33.10 with nullator and norator.

I

I

+ −

FIGURE 33.14 Norator–I-resistor–voltage source tree.

I

I

+ −

FIGURE 33.15 Nullator–I-resistor–voltage source tree.

their element values and parameters. In this sense the conditions are not only sufficient, but also necessary. This means, for example, in the case of Theorem 33.5 that if all circuits with the same structure have exactly one solution, then the three conditions must be satisfied. However, by logical contraposition, if one of the three conditions is not satisfied for a given circuit structure, a circuit with this structure exists which has either no solution or more than one solutions. On the other hand, if we consider a specific circuit, the conditions are only sufficient. They permit us to prove that the solution exists and is unique, but some circuits do not satisfy the conditions and still have exactly one solution. However, if the parameters of such a circuit are varied, one eventually falls onto a circuit with no solution or more than one solution. The main conditions of Theorems 33.3 and 33.4 have an evident intuitive meaning. The orientations to look for in Theorems 33.5 are linked to the sign of the currents and the voltages of the difference of two solutions. Because the resistors are increasing, these signs are the same for the voltage and current differences. If we extend the analysis of the signs of solutions or solution differences to other elements, we must differentiate between voltages and currents. This approach, in which two orientations for all branches are considered, one corresponding to the currents and one corresponding to the voltages, is pursued in [10].

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The conditions of Theorems 33.3 to 33.5 can be verified by inspection for small circuits. For larger circuits, one must resort to combinatorial algorithms. Such algorithms are proposed in [11,12]. As can be expected from the nature of conditions, the algorithms grow exponentially with the number of resistors. It is not known whether algorithms of polynomial complexity exist. Some circuits always have either no solution or an infinite number of solutions, irrespective of the element and parameter values. Figure 33.6 gives the simplest example. Such circuits clearly are not very useful in practice. The remaining circuits are those that may have a finite number n > 1 of solutions if the circuit parameters are chosen suitably. These are the circuits that are useful for static memories and for multivibrators in general. This class is characterized by the following theorem. Theorem 33.6: Let circuit be composed of nullator-norator pairs, V- and I-resistors, and independent voltage and current sources. If the following three conditions are satisfied, the circuit has more than one, but a finite number of solutions for a suitable choice of circuit parameters: • The norators, I-resistors, and the voltage sources together form a tree. • The nullators, I-resistors, and the voltage sources together form a tree. • A nontrivial, uniform partial orientation of the resistors occurs. Can we be more precise and formulate conditions on the circuit structure that guarantee four solutions, for example? This is not possible because changing the parameters of the circuit will lead to another number of solutions. Particularly with a circuit structure that satisfies the conditions of Theorem 33.6, there is a linear circuit that always has an infinite number of solutions. If we are more restrictive on the resistor characteristics, e.g., imposing convex or concave characteristics for certain resistors, it is possible to determine the maximum number of solutions. A method to determine an upper bound is given in [14], whereas the results of [15] allow us to determine the actual maximum number under certain conditions. Despite these results, however, the maximum number of solutions is still an open problem.

Bounds on Voltages and Currents It is common sense for electrical engineers that in an electronic circuit all node voltages lie between 0 and the power supply voltage, or between the positive and the negative power supply voltages, if both are present. Actually, this is only true for the DC-operating point, but can we prove it in this case? The following theorems give the answer. They are based on the notion of passivity. Definition 33.5. A resistor is passive if it can only absorb, but never produce power. This means that for any point (v, i) on its characteristic we have v ⋅i ≥ 0

(33.24)

A resistor is strictly passive, if in addition to (33.24) it satisfies the condition v ⋅i = 0 → v = i = 0

(33.25)

Theorem 33.7: Let a circuit be composed of strictly passive resistors and independent voltage and current sources. Then, for every branch k of the circuit the following bounds can be given: vk ≤

∑

vj

(33.26)

∑

ij

(33.27)

source branches j

ik ≤

source branches j

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+ E −

+ − R1

+ R2

v −

FIGURE 33.16 Voltage amplifier.

If, in addition, the circuit is connected and all sources have a common node, the ground node, then the maximum and the minimum node voltage are at a source terminal. The theorem implies in particular that in a circuit with a single voltage source, all branch voltages are bounded by the source voltage in magnitude, and all node voltages lie between zero and the source voltage. Similarly, if a circuit has a single current source, all branch currents are bounded by the source current in magnitude. Finally, if several voltage sources are present that are all connected to ground and have positive value, then the node voltages lie between zero and the maximum source voltage. If some sources have positive values and others have negative values, then all node voltages lie between the maximum and the minimum source values. This theorem and various generalizations can be found in [1]. The main drawback is that it does not admit nonreciprocal elements. A simple counterexample is the voltage amplifier of Fig. 33.16. The voltage of the output node of the operational amplifier is v=

R1 + R2 E R1

(33.28)

Thus, the output node voltage is higher than the source voltage. Of course, the reason is that the operational amplifier is an active element. It is realized by transistors and needs a positive and a negative voltage source as the power supply. The output voltage of the operational amplifier cannot exceed these supply voltages. This fact is not contained in the model of the ideal operational amplifier, but follows from the extension of Theorem 33.7 to bipolar transistors [1, 16]. Theorem 33.8: Let a circuit be composed of bipolar transistors modeled by the Ebers–Moll equations, of strictly passive resistors, and of independent voltage and current sources. Then, the conclusion of Theorem 33.7 hold. At first glance, Theorem 33.8 appears to imply that it is impossible to build an amplifier with bipolar transistors. Indeed, it is impossible to build such an amplifier with a single source, the input signal. We need at least one power supply source that sets the limits of dynamic range of the voltages according to Theorem 33.8. The signal source necessarily has a smaller amplitude and the signal can be amplified roughly up to the limit set by the power supply source. Theorem 33.8 can be extended to MOS transistors. The difficulty is that the nonlinear characteristics of the simplest model is not strictly increasing, and therefore some interconnection condition must be added to avoid parts with undetermined node voltages.

Monotonic Dependence Instead of looking at single solutions of resistive circuits, as done earlier in the chapter, we consider here a solution as a function of a parameter. The simplest and at the same time the most important case is the dependence of a solution on the value of a voltage or current source. To have a well-defined situation, we suppose that the circuit satisfies the hypotheses of Theorem 33.5. In this case [1, 8], the solution is a continuous function of the source values. As an example, let us consider the circuit of Fig. 33.17. We are interested in the dependence of the various currents on the source voltage E. Because the circuit contains only strictly increasing resistors, © 2003 by CRC Press LLC

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R1 R3

i1

R5

E R2

i5 R4

FIGURE 33.17 Circuit example for source dependence.

[A] i5

1

E −10

0

10 [V]

FIGURE 33.18 Nonmonotonic dependence.

we expect all currents to be strictly monotonic functions of E. This is not true. In Fig. 33.18, the current i5(E) is represented for R1 = R2 = R3 = 2R4 = R5 = 1 Ω and for standard diode model parameters. Clearly, it is nonmonotonic.

33.3 Autonomous Dynamic Circuits Introduction This section adds to the resistive elements of the previous section — the capacitors and the inductors. A nonlinear capacitor is defined by the constitutive relation v = h(q )

(33.29)

where the auxiliary variable q is the charge of the capacitor, which is linked to the current by i=

dq dt

(33.30)

The dual element, the nonlinear inductor, is defined by i = g (ϕ )

(33.31)

where the auxiliary variable ϕ, the flux, is linked to the voltage by v=

dϕ dt

The symbols of these two elements are represented in Fig. 33.19.

FIGURE 33.19 Symbols of the nonlinear capacitor and the nonlinear inductor. © 2003 by CRC Press LLC

(33.32)

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The system of equations that describes an autonomous dynamic circuit is composed of (33.12) to (33.17), completed with (33.29) and (33.30) for capacitor branches and (33.31) and (33.32) for inductor branches. Hence, it becomes a mixed differential–nondifferential system of equations. Its solutions are the voltages, currents, charges, and fluxes as functions of time. Because it contains differential equations, we have infinitely many solutions, each one determined by some set of initial conditions. If all variables except the charges and fluxes are eliminated from the system of equations, one obtains a reduced, purely differential system of equations dq = f (q,ϕ) dt

(33.33)

dϕ = g (q,ϕ) dt

(33.34)

where q and ϕ are the vectors composed of, respectively, the capacitor charges and the inductor fluxes. These are the state equations of the circuit. Under mild assumptions on the characteristics of the nonlinear elements (local Lipschitz continuity and eventual passivity), it can be shown that the solutions are uniquely determined by the initial values of the charges and fluxes at some time t0, q(t0), and ϕ(t0), and that they exist for all times t0 ≤ t < ∞ [1, 17]. It cannot be taken for granted, however, that the circuit equations actually can be reduced to that state Eqs. (33.33) and (33.34). On the one hand, the charges and fluxes may be dependent and thus their initial values cannot be chosen freely. However, the state equations may still exist, in terms of a subset of charges and fluxes. This means that only these charges and fluxes can be chosen independently as initial conditions. On the other hand, the reduction, even to some alternative set of state variables, may be simply impossible. This situation is likely to lead to impasse points, i.e., nonexistence of the solution at a finite time. We refer the reader to the discussion in [1]. In the sequel we suppose that the solutions exist from the initial time t0 to +∞ and that they are determined by the charges and fluxes at t0. We are interested in the asymptotic behavior, i.e., the behavior of the solutions when the time t goes to infinity. If the dynamic circuit is linear and strictly stable, i.e., if all its natural frequencies are in the open left half of the complex plane, then all solutions converge to 1 and the same DC-operating (equi­ librium) point. This property still holds for many nonlinear circuits, but not for all by far. In particular, the solutions may converge to different DC-operating points, depending on the initial conditions (static memories), they may converge to periodic solutions (free-running oscillators), or they may even show chaotic behavior (e.g., Chua’s circuit). Here, we give conditions that guarantee the solutions converge to a unique solution or one among several DC-operating points.

Convergence to DC-Operating Points The methods to prove convergence to one or more DC-operating points is based on Lyapunov functions. A Lyapunov function is a continuously differentiable function W(ξ), where ξ is the vector composed of the circuit variables (the voltages, currents, charges, and fluxes). In the case of autonomous circuits, a Lyapunov function must have the following properties: 1. W is bounded below, i.e., there exists a constant W0 such that W (ξ) ≥ W0 for all ξ

(33.35)

2. The set of voltages, currents, charges, and fluxes of the circuit such that W(ξ) ≤ E is bounded for any real E. 3. For any solution ξ(t) of the circuit

( )

d W ξ(t ) ≤ 0 dt © 2003 by CRC Press LLC

(33.36)

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4. If

( )

d W ξ(t ) = 0 dt

(33.37)

then ξ(t) is a DC-operating point. If an autonomous circuit has a Lyapunov function and if it has at least one, but a finite number of DCoperating points, then every solution converges to a DC-operating point. The reason is that the Lyapunov function must decrease along each solution, and thus must result in a local minimum, a stable DCoperating point. If more than one DC-operating point exists, it may, as a mathematical exception that cannot occur in practice, end up in a saddle point, i.e., an unstable DC-operating point. The problem with the Lyapunov function method is that it gives no indication as to how to find such a function. Basically, three methods are available to deal with this problem: 1. Some standard candidates for Lyapunov functions, e.g., the stored energy. 2. Use a certain kind of function and adjust the parameters in order to satisfy 2 and 3 in the previous list. Often, quadratic functions are used. 3. Use an algorithm to generate Lyapunov functions [18-20]. The following theorems were obtained via approach 1, and we indicate which Lyapunov was used to prove them. At first glance, this may seem irrelevant from an engineering point of view. However, if we are interested in designing circuits to solve optimization problems, we are likely to be interested in Lyapunov functions. Indeed, as mentioned previously, along any solution of the circuit, the Lyapunov function decreases and approaches a minimum of the function. Thus, the dynamics of the circuit solve a minimization problem. In this case, we look for a circuit with a given Lyapunov function, however, usually we look for a Lyapunov function for a given circuit. Theorem 33.9: Let a circuit be composed of capacitors and inductors with a strictly increasing characteristic, resistors with a strictly increasing –characteristic, and independent voltage and current sources. Suppose the circuit has a DC-operating point ξ. By Theorem 33.1, this DC-operating point is unique. Finally, suppose the circuit has no loop composed of capacitors, inductors, and voltage sources and no– cutset composed of capacitors, inductors, and current sources. Then, all solutions of the circuit converge to ξ. The Lyapunov function of this circuit is given by a variant of the stored energy in the capacitors and – the resistors, the stored energy with respect to ξ [1, 17]. If the constitutive relations of the capacitors and the inductors are given by vk = hk (qk) and ik = gk (vk), respectively, then this Lyapunov function becomes

∑ ∫ (h (q) − h (q ))dq qk

W (ξ ) =

capacitor branches k

+

k

qk

k

k

∑ ∫ ( g (ϕ) − g (ϕ ))dϕ ϕk

inductor branches k

ϕk

k

k

(33.38)

k

The main condition (33.36) for a Lyapunov function follows from the fact that the derivative of the stored energy is the absorbed power, here in incremental form: d W (ξ ) = dt

© 2003 by CRC Press LLC

∑

capacitor and inductor branches k

∆v k ∆ik = −

∑

resistor branches k

∆v k ∆ik ≤ 0

(33.39)

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Various generalizations of Theorem 33.9 have been given. The condition “strictly increasing resistor – characteristic” has been relaxed to a condition that depends on ξ in [1, 17] and mutual inductances and capacitances have been admitted in [17]. The next theorem admits resistors with nonmonotonic characteristics. However, it does not allow for both inductors and capacitors. Theorem 33.10: Let a circuit be composed of capacitors with a strictly increasing characteristic, voltagecontrolled resistors such that v → + ∞ ⇒ i > I + > 0 and v → − ∞ ⇒ i < I − < 0

(33.40)

and independent voltage sources. Furthermore, suppose that the circuit has a finite number of DC-operating points. Then every solution of the circuit converges toward a DC-operating point. This theorem is based on then following a Lyapunov function, called cocotent:

∑∫

( )

W ξ(t ) =

resistor branches k

vk o

g k (v )dv

(33.41)

where ik = gk(vk) is the constitutive relation of the resistor on branch k. The function W is decreasing along a solution of the circuit because

( ) ∑

d W ξ(t ) = dt

resistor branches k

=−

dv k i =− dt k

∑

capacitor branches k

∑

capacitor branches k

dv k i dt k (33.42)

dhk 2 i ≤0 dq k

where hk (qk) is the constitutive relation of the capacitor on branch k. Theorem 33.10 has a dual version. It admits inductors instead of capacitors, current-controlled resis­ tors, and current sources. The corresponding Lyapunov function is the content: W (ξ ) =

∑∫

resistor branches k

ik o

hk (i )di

(33.43)

where vk = hk(ik) is the constitutive relation of the resistor on branch k. The main drawback of the two preceding theorems is that they do not admit nonreciprocal elements such as controlled sources, operational amplifiers, etc. In other words, no statement about the analog neural network of Fig. 33.20 can be made. In this network the nonreciprocal element is the VCVS with the nonlinear characteristics v2 = σ(v1). However, Theorem 33.10 can be generalized to a reciprocal voltage controlled N-port resistor closed on capacitors and voltage sources. Such an N-port (Fig. 33.21) is described by a constitutive relation of the form ik = g k (v1 , ... , v N )

(33.44)

and it is reciprocal, if for all v, and all k, j we have ∂g ∂g k v) = j (v) ( ∂v j ∂v k

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(33.45)

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R1N

R12

R11 σ

I1 R2N

R22

R21

R1

C σ

I2

R2

RNN

RN2

C

RN1 σ

IN

RN

C

FIGURE 33.20 Analog neural network.

+ v1 −

i1

resistive N-port

iN

+ vN −

FIGURE 33.21 Resistive N-port.

Theorem 33.11: Let a circuit be composed of charge-controlled capacitors with a strictly increasing charac­ teristic and independent voltage sources that terminate a reciprocal voltage-controlled N-port with constitutive relation (33.42) so that we find constants V and P > 0 such that N

v ≥V ⇒g ⋅v =

∑g

k

( v ) vk ≥ P

(33.46)

k =1

If the number of DC-operating points is finite, then all solutions converge toward a DC-operating point. The proof of this theorem is based on the Lyapunov function W(v) that satisfies ∂W (v) = gk (v) ∂v k

(33.47)

Thanks to condition (33.45), function W exists. The first two conditions for a Lyapunov function are a consequence of (33.46). Finally,

(

) ∑

gk (v)

∑

dv ik k dt

d W ξ (t ) = dt =

resistor branches k

resistor branches k

© 2003 by CRC Press LLC

dv k dt (33.48)

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=–

∑

capacitor branches k

dhk 2 i ≤0 dq k

where hk(qk) is the constitutive relation of the capacitor on branch k. To illustrate how Theorem 33.11 can be applied when Theorem 33.10 fails, consider the analog neural network of Fig. 33.20. If the capacitor voltages are denoted by ui and the voltages at the output of the voltage sources by vi , the state equations for the network of Fig. 33.1 become −Ci

dui ui = + dt Ri

N

∑

ui − v j

+ Ii

Rij

j =1

(33.49)

Suppose that the nonlinear characteristic σ(u) is invertible. The state equations can be written in terms of the voltages vi : −C

N

dv dσ − 1 v i ) i = Gi σ − 1 (v i ) − ( dv dt

∑R

vj

j =1

+ Ii

(33.50)

ij

where Gi =

1 + Ri

N

∑ R1

(33.51)

ij

j =1

Equations (33.40) can be reinterpreted as the equations of a resistive N-port with the constitutive relations g i ( v ) = Gi σ − 1 (v i ) −

N

∑R j =1

vj

+ Ii

(33.52)

ij

closed on nonlinear capacitors with the constitutive relation  q v=σ  C

(33.53)

If σ is a sigmoidal function, as is most often supposed in this context (i.e., a strictly increasing function with s(u) → ±1 for u → ±∞), then the capacitors have a strictly increasing characteristic, as required by Theorem 33.11. Furthermore, the resistive N-port is reciprocal if for i ≠ j ∂g ∂g i 1 1 =− = j =− ∂v j Rij ∂v i R ji

(33.54)

Rij = R ji

(33.55)

In other words, if for all i, j

On the other hand, inequality (33.46) must be modified because the sigmoids have values only in the interval [–1, +1] and thus (33.50) are defined only on the invariant bounded set S = {v  – 1 < vi < +1}. Therefore, inequality (33.50) must be satisfied for vectors v sufficiently close to the boundary of S. This © 2003 by CRC Press LLC

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is indeed the case, because σ–1(v) → ±∞ as v → ±1, whereas the other terms of the right-hand side of (33.52) remain bounded. It follows that all solutions of the analog neural network of Fig. 33.20 converge to a DC-operating point as t → ∞, provided σ is a sigmoid function and the connection matrix Rij (synaptic matrix) is symmetrical. The Lyapunov function can be given explicitly: W (v) =

N

∑

Gi

i =1

1 N v iv j vi −1 σ v dv − + ( ) ∫0 2 i , j = 1 Rij

∑

N

∑v I

i i

(33.56)

i =1

33.4 Nonautonomous Dynamic Circuits Introduction This section is a consideration of circuits that contain elements where constitutive relations depend explicitly on time. However, we limit time dependence to the independent sources. For most practical purposes, this is sufficient. A time-dependent voltage source has a constitutive relation v = e(t )

(33.57)

i = e(t )

(33.58)

and a time-dependent current source

where e(t) is a given function of time which we suppose here to be continuous. In information processing circuits, e(t) represents a signal that is injected into the circuit, whereas in energy transmission circuits e(t) usually is a sinusoidal or nearly sinusoidal function related to a generator. The time-dependent sources may drive the voltages and the currents to infinity, even if they only inject bounded signals into the circuit. Therefore, the discussion begins with the conditions that guarantee the boundedness of the solutions.

Boundedness of the Solutions In electronic circuits, even active elements become passive when the voltages and currents grow large. This is the reason that solutions remain bounded. Definition 33.6. A resistor is eventually passive if, for sufficiently large voltages and/or currents, it can only absorb power. More precisely, eventual passivity means that constants V and I exist such that, for all points (v, i) on the resistor characteristic with v > V or i  > I, we have v ⋅i ≥ 0

(33.59)

Note that sources are not eventually passive, but as soon as an internal resistance of a source is taken into account, the source becomes eventually passive. The notion of eventual passivity can be extended to time-varying resistors. Definition 33.7. A time-varying resistor is eventually passive if constants V and I are independent of time and are such that all points (v, i), with v > V or i > I that at some time lie on the characteristic of the resistor, satisfy the passivity condition (33.59). According to this definition, time-dependent sources with internal resistance are eventually passive if the source signal remains bounded.

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Eventual passivity allows us to deduce bounds for the solutions. These bounds are uniform in the sense that they do not depend on the particular solution. To be precise, this is true only asymptotically, as t → ∞. Definition 33.8. The solutions of a circuit are eventually uniformly bounded if there exist constants V, I, Q, and Φ are such that, for any solution there exists a time T such that for any t > T, the voltages vk (t) are bounded by V, the currents ik (t) are bounded by I, the charges qk (t) are bounded by Q, and the fluxes ϕk(t) are bounded by Φ. Another manner of expressing the same property is to say that an attracting domain exists in state space [1]. Theorem 33.12: A circuit composed of eventually passive resistors with v · i → +∞ as v → ∞ or i → ∞, capacitors with v → ±∞ as q → ≠∞, and inductors with i → ±∞ as ϕ → ∞ has eventually uniformly bounded solutions if no loop or cutset exists without a resistor [1,17]. Again, this theorem is proved by using a Lyapunov function, namely the stored energy W (ξ ) =

∑∫

capacitor branches k

qk 0

hk (q)dq +

∑∫

capacitor branches k

ϕk 0

g k (ϕ)dϕ

(33.60)

Inequality (33.36) holds only outside of a bounded domain.

Unique Asymptotic Behavior In the presence of signals with complicated waveforms that are injected into a circuit, we cannot expect simple waveforms for the voltages and the currents, not even asymptotically, as t → ∞. However, we can hope that two solutions, starting from different initial conditions, but subject to the same source, have the same steady-state behavior. The latter term needs a more formal definition. Definition 33.9. A circuit has unique asymptotic behavior if the following two conditions are satisfied: 1. All solutions are bounded. 2. For any two solutions ξ1(t) and ξ2(t) ξ1 (t ) − ξ 2 (t ) →t→∞ 0

(33.61)

In order to prove unique asymptotic behavior, it is necessary to extend the notion of the Lyapunov function [1]. This does not lead very far, but at least it permits us to prove the following therorem. Therorem 33.13: Suppose a circuit is composed of resistors with a strictly increasing characteristic such that v · i → ∞ as v → ∞ or i → ∞, positive linear capacitors, positive linear inductors, time-depending voltage (current) sources with bounded voltage (current) and a positive resistor in series (parallel). If no loop or cutset is composed exclusively of capacitors and inductors, the circuit has unique asymptotic behavior [1, 17]. This theorem is unsatisfactory because linear reactances are required and real devices are never exactly linear. It has been shown that slight nonlinearities can be tolerated without losing the unique asymptotic behavior [21]. On the other hand, we cannot expect to get much stronger general results because nonautonomous nonlinear circuits may easily have multiple steady-state regimes and even more com­ plicated dynamics, such as chaos, even if the characteristics of the nonlinear elements are all strictly increasing. Another variant of Theorem 33.13 considers linear resistors and nonlinear reactances [17].

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References [1] M. Hasler and J. Neirynck, Nonlinear Circuits, Boston: Artech House, 1986. [2] L. O. Chua, C. A. Desoer, and E. S. Kuh, Linear and Nonlinear Circuits, Electrical & Electronic Engineering Series, Singapore: McGraw-Hill International Editors, 1987. [3] A. N. Willson, Ed., Nonlinear Networks: Theory and Analysis, New York: IEEE Press, 1974. [4] R. O. Nielsen and A. N. Willson, “A fundamental result concerning the topology of transistor circuits with multiple equilibria,” Proc. IEEE, vol. 68, pp. 196–208, 1980. [5] A. N. Willson, “On the topology of FET circuits and the uniqueness of their dc operating points,” IEEE Trans. Circuits Syst., vol. 27, pp. 1045–1051, 1980. [6] T. Nishi and L. O. Chua, “Topological criteria for nonlinear resistive circuits containing controlled sources to have a unique solution,” IEEE Trans. Circuits Syst., vol. 31, pp. 722–741, Aug. 1984. [7] T. Nishi and L. O. Chua, “Nonlinear op-amp circuits: Existence and uniqueness of solution by inspection,” Int. J. Circuit Theory Appl., vol 12, pp. 145–173, 1984. [8] M. Hasler, “Nonlinear nonreciprocal resistive circuits with a unique solution,” Int. J. Circuit Theory Appl., vol. 14, pp. 237–262, 1986. [9] M. Fosséprez, Topologie et Comportement des Circuits non Linéaires non Réciproques, Lausanne: Presses Polytechnique Romands, 1989. [10] M. Hasler, “On the solution of nonlinear resistive networks,” J. Commun. (Budapest, Hungary), special issue on nonlinear circuits, July 1991. [11] T. Parker, M. P. Kennedy, Y. Lioa, and L. O. Chua, “Qualitative analysis of nonlinear circuits using computers,” IEEE Trans. Circuits Syst., vol. 33, pp. 794–804, 1986. [12] M. Fosséprez and M. Hasler, “Algorithms for the qualitative analysis of nonlinear resistive circuits,” IEEE ISCAS Proc., pp. 2165–2168, May 1989. [13] M. Fosséprez and M. Hasler, “Resistive circuit topologies that admit several solutions,” Int. J. Circuit Theory Appl., vol. 18, pp. 625–638, Nov. 1990. [14] M. Fosséprez, M. Hasler, and C. Schnetzler, “On the number of solutions of piecewise linear circuits,” IEEE Trans. Circuits Syst., vol. CAS-36, pp. 393–402, March 1989. [15] T. Nishi and Y. Kawane, “On the number of solutions of nonlinear resistive circuits,” IEEE Trans., vol. E74, pp. 479–487, 1991. [16] A. N. Willson, “The no-gain property for networks containing three-terminal elements,” IEEE Trans. Circuits Syst., vol. 22, pp. 678–687, 1975. [17] L. O. Chua, “Dynamic nonlinear networks: state of the art, “IEEE Trans. Circuits Syst., vol. 27, pp. 1059–1087, 1980. [18] R. K. Brayton and C.H. Tong, “Stability of dynamical systems,” IEEE Trans. Circuits Syst., vol. 26, pp. 224–234, 1979. [19] R. K. Brayton and C. H. Tong, “Constructive stability and asymptotic stability of dynamical systems,” IEEE Trans. Circuits Syst., vol. 27, pp. 1121–1130, 1980. [20] L. Vandenberghe and S. Boyd, “A polynomial-time algorithm for determining quadratic Lyapunov functions for nonlinear systems,” Proc. ECCTD-93, pp. 1065–1068, 1993. [21] M. Hasler and Ph. Verburgh, “Uniqueness of the steady state for small source amplitudes in nonlinear nonautonomous circuits,” Int. J. Circuit Theory Appl., vol. 13, pp. 3–17, 1985.

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34 Synthesis and Design

of Nonlinear Circuits

34.1 Introduction 34.2 Approximation Issues Unidimensional Functions • Piecewise-Linear and PiecewisePolynomial Approximants • Gaussian and Bell-Shaped Basis Functions • Multidimensional Functions

34.3 Aggregation, Scaling, and Transformation Circuits Transformation Circuits • Scaling and Aggregation Circuitry

34.4 Piecewise-Linear Circuitry Current Transfer Piecewise-Linear Circuitry • Transresistance Piecewise-Linear Circuitry • Piecewise-Linear Shaping of Voltage-to-Charge Transfer Characteristics

A. Rodríguez-Vázquez Universidad de Sevilla, Spain

M. Delgado-Restituto Universidad de Sevilla, Spain

J. L. Huertas Universidad de Sevilla, Spain

F. Vidal Universidad de Malaga, Spain

34.5 Polynomials, Rational, and Piecewise-Polynomial Functions Concepts and Techniques for Polynomic and Rational Functions • Multiplication Circuitry • Multipliers Based on Nonlinear Devices

34.6 Sigmoids, Bells, and Collective Computation Circuits. Sigmoidal Characteristics • Bell-Like Shapes • Collective Computation Circuitry

34.7 Extension to Dynamic Systems 34.8 Appendix A: Catalog of Primitives 34.9 Appendix B: Value and Slope Hermite Basis Functions

34.1 Introduction Nonlinear synthesis and design can be informally defined as a constructive procedure to interconnect components from a catalog of available primitives, and to assign values to their constitutive parameters to meet a specific nonlinear relationship among electrical variables. This relationship is represented as an implicit integro-differential operator, although we primarily focus on the synthesis of explicit algebraic functions, y = f ( x )

(34.1)

where y is a voltage or current, f (·) is a nonlinear real-valued function, and x is a vector with components that include voltages and currents. This synthesis problem is found in two different circuit-related areas: device modeling [8, 76] and analog computation [26]. The former uses ideal circuit elements as prim­ itives to build computer models of real circuits and devices (see Chapter 33). The latter uses real circuit components, available either off the shelf or integrable in a given fabrication technology, to realize hardware for nonlinear signal processing tasks. We focus on this second area, and intend to outline

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vbc Primitives for Synthesis

ic ic = Is (evbe/vt − evbe/vt)

vbe

Nonlinear Operators

Interconnection Law

Elementary Functions

Nonlinear Circuit

Approximation Procedure

Nonlinear Task

Φ (x) = (x − E)r sgn (x − E)

Q

f(x) ≈ g (x) =

∑ Wj Φj (x) j=1

FIGURE 34.1 Hierarchical decomposition of the synthesis problem.

systematic approaches to devise electronic function generators. Synthesis relies upon hierarchical decompo­ sition, conceptually shown in Fig. 34.1, which encompasses several subproblems listed from top to bottom: • Realization of nonlinear operators (multiplication, division, squaring, square rooting, logarithms, exponentials, sign, absolute value, etc.) through the interconnection of primitive components (transistors, diodes, operational amplifiers, etc.). • Realization of elementary functions (polynomials, truncated polynomials, Gaussian functions, etc.) as the interconnection of the circuit blocks devised to build nonlinear operators. • Approximation of the target as a combination of elementary functions and its realization as the interconnection of the circuit blocks associated with these functions. Figure 34.1 illustrates this hierarchical decomposition of the synthesis problem through an example in which the function is approximated as a linear combination of truncated polynomials [30], where realization involves analog multipliers, built by exploiting the nonlinearities of bipolar junction transistors (BJTs) [63]. Also note that the subproblems cited above are closely interrelated and, depending on the availability of primitives and the nature of the nonlinear function, some of these phases can be bypassed. For instance, a logarithmic function can be realized exactly using BJTs [63], but requires approximation if our catalog includes only field-effect transistors whose nonlinearities are polynomic [44]. The technical literature contains excellent contributions to the solution of all these problems. These contributions can hardly be summarized or even quoted in just one section. Many authors follow a blockbased approach which relies on the pervasive voltage operational amplifier (or op amp), the rectification properties of junction diodes, and the availability of voltage multipliers, in the tradition of classical analog computation. Examples are [7], [59], and [80]. Remarkable contributions have been made which focus on qualitative features such as negative resistance or hysteresis, rather than the realization of well-defined approximating functions [9, 20, 67]. Other contributions focus on the realization of nonlinear operators in the form of IC units. Translinear circuits, BJTs [23, 62] and MOSFETs [79] are particularly well suited to realize algebraic functions in IC form. This IC orientation is shared by recent developments in analog VLSI computational and signal processing systems for neural networks [75], fuzzy logic [81], and other nonlinear signal processing paradigms [56, 57, 71]. © 2003 by CRC Press LLC

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Synthesis and Design of Nonlinear Circuits

This chapter is organized to fit the hierarchical approach in Fig. 34.1. We review a wide range of approximation techniques and circuit design styles, for both discrete and monolithic circuits. It is based on the catalog of primitives shown in Appendix A. In addition to the classical op-amp-based continuoustime circuits, we include current-mode circuitry because nonlinear operators are realized simply and accurately by circuits that operate in current domain [23, 57, 62, 79]. We also cover discrete-time circuits realized using analog dynamic techniques based on charge transfer, which is very significant for mixedsignal processing and computational microelectronic systems [27, 72]. Section 34.2 is devoted to approx­ imation issues and outlines different techniques for uni- and multidimensional functions, emphasizing hardware-oriented approaches. These techniques involve several nonlinear operators and the linear operations of scaling and aggregation (covered in Section 34.3, which also presents circuits to perform transformations among different kinds of characteristics). Sections 34.4 and 34.5 present circuits for piecewise-linear (PWL) and piecewise-polynomial (PWP) functions, 34.6 covers neural and fuzzy approx­ imation techniques, and 34.7 outlines an extension to dynamic circuits.

34.2 Approximation Issues Unidimensional Functions Consider a target function, f (x), given analytically or as a collection of measured data at discrete values of the independent variable. The approximation problem consists of finding a multiparameter function, g (x, w), which yields proper fitting to the target, and implies solving two different subproblems: (1) which approximating functions to use, and (2) how to adjust the parameter vector, w, to render optimum fitting. We only outline some issues related to this first point. Detailed coverage of both problems can be found in mathematics and optimization textbooks [73, 78]. Other interesting views are found in circuit-related works [6, 11, 30], and the literature on neural and fuzzy networks [12, 21, 33, 43, 51]. An extended technique to design nonlinear electronic hardware for both discrete [63, 80] and mono­ lithic [35, 62, 79] design styles uses polynomial approximating functions, g (x ) =

Q

∑α x

j

(34.2)

j

j=0

obtained through expansion by either Taylor series or orthogonal polynomials (Chebyshev, Legendre, or Laguerre) [26]. Other related approaches use rational functions,

∑αx g (x ) = ∑β x

j

j

j = 0, Q

j

(34.3)

j

j 0, R

to improve accuracy in the approximation of certain classes of functions [14]. These can be realized by polynomial building blocks connected in feedback configuration [63]. In addition, [39] presents an elegant synthesis technique relying on linearly controlled resistors and conductors to take advantage of linear circuits synthesis methods (further extended in [28]). From a more general point of view, hardware-oriented approximating functions can be classified into two major groups: 1. Those involving the linear combination of basis functions g (x ) =

© 2003 by CRC Press LLC

Q

∑ w j Φj ( x )

j =1

(34.4)

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δ11 x w11 Φ1(x)

x

Φ2(x)

+

W2

+ +

∑

h(•)

w21

h(•)

w22

δ12

W1

− w12

g(x)

+

+ ΦQ(x)

− ∑

∑

+ ∑

+ +

δ1Q w1Q

(a)

+

(b)

∑

g(x)

− δ2

−

WQ

h(•)

h(•)

w2Q

FIGURE 34.2 Block diagram for approximating function hardware. (a) Using linear combination of basis functions; (b) using two layers of nested sigmoids.

which include polynomial expansions. PWL and PWP interpolation and radial basis functions (RBF). The hardware for these functions consists of two layers, as shown in Fig. 34.2 (a). The first layer contains Q nonlinear processing nodes to evaluate the basis functions; the second layer scales the output of these nodes and aggregates these scaled signals in a summing node. 2. Those involving a multilayer of nested sigmoids [51]; for instance, in the case of two layers [82],    g ( x ) = h  ∑ w 2 jh w1 j x − δ1 j  − δ 2   j=1, Q  

(

)

(34.5)

2 −1 1 + exp( −λx )

(34.6)

with the sigmoid function given by h( x ) =

where λ > 0 determines the steepness of the sigmoid. Figure 34.2(b) shows a hardware concept for this approximating function, also consisting of two layers.

Piecewise-Linear and Piecewise-Polynomial Approximants A drawback of polynomial and rational approximants is that their behavior in a small region determines their behavior in the whole region of interest [78]. Consequently, they are not appropriate to fit functions that are uniform throughout the whole region [see Fig. 34.3 (a)]. Another drawback is their lack of modularity, a consequence of the complicated dependence of each fitting parameter on multiple target data, which complicates the calculation of optimum parameter values. These drawbacks can be overcome by splitting the target definition interval into Q subintervals, and then expressing approximating function as a linear combination of basis functions, each having compact support over only one subinterval, i.e., �� � �

�� � � ���������

�����������

�

���

������

FIGURE 34.3 Example of nonuniform function. © 2003 by CRC Press LLC

�

���

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945

Synthesis and Design of Nonlinear Circuits

zero value outside this subinterval. For the limiting case in which Q → ∞, this corresponds to interpolating the function by its samples associated to infinitely small subintervals [Fig. 34.3(b)]. Such action is functionally equivalent to expressing a signal as its convolution with a delta of Dirac [10]. This splitting and subsequent approximation can be performed ad hoc, by using different functional dependences to fit each subregion. However, to support the systematic design of electronic hardware it is more convenient to rely on well-defined classes of approximating functions. In particular, Hermite PWPs provide large modularity by focusing on the interpolation of measured data taken from the target function. Any lack of flexibility as compared to the ad hoc approach may be absorbed in the splitting of the region. Consider the more general case in which the function, y = f (x), is defined inside a real interval [δ0, δN+1] and described as a collection of data measured at knots of a given interval partition, ∆ = {δ0, δ1, δ2, …, δN, δN+1}. These data may include the function values at these points, as well as their derivatives, up to the (M – 1)th order, dk k f ( ) δi = k f (x ) dx x=δ

( )

i = 0,1, 2, ... , N , N + 1

(34.7)

i

where k denotes the order of the derivative and is zero for the function itself. These data can be interpolated by a linear combination of basis polynomials of degree 2M – 1, g (x ) =

N +1 M −1

∑∑ f ( ) (δ )Φ (x) k

i

(34.8)

ik

i=0 k=0

where the expressions for these polynomials are derived from the interpolation data and continuity conditions [78]. Note that for a given basis function set and a given partition of the interval, each coefficient in (34.8) corresponds to a single interpolation kust. The simplest case uses linear basis functions to interpolate only the function values, g (x ) =

N +1

∑ f (δ )l (x) i

(34.9)

i

i=0

with no function derivatives interpolated. Figure 34.4 shows the shape of the inner jth linear basis function, which equals 1 at δi and decreases to 0 at δi–1 and δ i+1. Figure 34.5(a) illustrates the represen­ tation in (34.9). By increasing the degree of the polynomials, the function derivatives also can be interpolated. In particular, two sets of third-degree basis functions are needed to retain modularity in the interpolation of the function and its first derivative at the knots g (x ) =

N +1

∑ i=0

f (δ i )v i ( x ) +

N +1

∑ f ( ) (δ )s (x) 1

i

i

(34.10)

i=0

where Appendix B shows the shapes and expressions of the value, vi (x), and slope, si (x), basis functions. ��� � �

���

���

���

δ�−�

© 2003 by CRC Press LLC

δ�

δ�+�

�

FIGURE 34.4 Hermite linear basis function.

0912 ch34 frame55 Page 946 Wednesday, October 30, 2002 12:53 PM

946

The Circuits and Filters Handbook, Second Edition ��� ��� �

�

���

���

FIGURE 34.5 Decomposition of a PWL function using the extension operator.

The modularity of Hermite polynomials is not free; their implementation is not cheapest in terms of components and, consequently, may not be optimal for application in which the target function is fixed. These applications are more conveniently handled by the so-called canonical representation of PWP functions. A key concept is the extension operator introduced in [6]; the basic idea behind this concept is to build the approximating function following an iterative procedure. At each iteration, the procedure starts from a function that fits the data on a subinterval, enclosing several pieces of the partition interval, and then adds new terms to also fit the data associated to the next piece. Generally, some pieces are fit from left to right and others from right to left, to yield g (x ) = g 0 (x ) +

N+

∑

−1

∑ ∆ g (x )

∆+ g i ( x ) +

i =1

−

i

(34.11)

i = –N −

It is illustrated in Fig. 34.5(b). The functions in (34.11) have the following general expressions ∆+ g ( x ) = wu+ ( x − δ) ≡ w ( x − δ) sgn( x − δ) ∆− g ( x ) = wu− ( x − δ) ≡ w ( x − δ) sgn(δ – x )

(34.12)

g 0 ( x ) = ax + b where sgn (·) denotes the sign function, defined as an application of the real axis onto the discrete set {0,1}. This representation, based on the extension operator, is elaborated in [6] to obtain the following canonical representation for unidimensional PWL functions: g ( x ) = ax + b +

N

∑w x − δ i

(34.13)

i

i =1

which has the remarkable feature of involving only one nonlinearity: the absolute value function. The extension operator concept was applied in [30] to obtain canonical representations for cubic Hermite polynomials and B-splines. Consequently, it demonstrates that a PWP function admits a global expression consisting of a linear combination of powers of the input variable, plus truncated powers of shifted versions of this variable. For instance, the following expression is found for a cubic B-spline: g (x ) =

N

3

∑ r =0

αr x r +

∑ β (x − δ ) sgn(x − δ ) 3

i

i

i

(34.14)

i =1

with αr and βi obtainable through involved operations using the interpolation data. Other canonical PWP representations devised by these authors use

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947

Synthesis and Design of Nonlinear Circuits

(x − δi )

r

sgn( x − δ i ) =

{

}

r −1 1 x − δi + (x − δi ) (x − δi ) 2

(34.15)

to involve the absolute value, instead of the sign function, in the expression of the function.

Gaussian and Bell-Shaped Basis Functions The Gaussian basis function belongs to the general class of radial basis functions [51, 52], and has the following expression:  ( x − δ )2  Φ( x ) = exp  −   2σ 2  

(34.16)

plotted in Fig. 34.6. The function value is significant only for a small region of the real axis centered around its center, δ, and its shape is controlled by the variance parameter, σ2. Thus, even through the support of Gaussian functions is not exactly compact, they are negligible except for well-defined local domains of the input values. By linear combination of a proper number of Gaussians, and a proper choice of their centers and variances, as well as the weighting coefficients, it is possible to approximate nonlinear functions to any degree of accuracy [51]. Also, the local feature of these functions renders this adjustment process simpler than for multilayer networks composed of nested sigmoids, whose components are global [43, 50]. A similar interpolation strategy arises in the framework of fuzzy reasoning, which is based on local membership functions whose shape resembles a Gaussian. For instance, in the ANFIS system proposed by Jang [33] Φ( x ) =

1  x − δ  2  1 +        σ 

(34.17)

β

as plotted in Fig. 34.7(a) where the shape is controlled by β and σ, and the position is controlled by δ. Other authors, for instance, Yamakawa [81], use the PWL membership function shape of Fig. 34.7(b), Φ(x) 1.0 0.5 0.0

x

δ

FIGURE 34.6 Guassian basis function.

Φ(x)

Φ(x)

1.0

1.0

slope = −β/2σ

0.5 0.0 (a)

0.5 δ 2σ

0.0

x (b)

FIGURE 34.7 Fuzzy membership functions: (a) polynomial; (b) piecewise-linear. © 2003 by CRC Press LLC

slope = −β

δ 2σ

x

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The Circuits and Filters Handbook, Second Edition

which is similar to the Hermite linear basis function of Fig. 34.4. From a more general point of view, cubic B-splines [78] used to build hardware [59] and for device modeling [76] also can be considered to be members of this class of functions.

Multidimensional Functions Approximation techniques for multidimensional functions are informally classified into five groups: 1. 2. 3. 4. 5.

Sectionwise piecewise polynominal functions [6, 30] Canonical piecewise linear representations [11] Neuro-fuzzy interpolation [33, 81] Radial basis functions [51, 52] Multilayers of nested sigmoids [82]

Sectionwise Piecewise Polynomial Functions This technique reduces the multidimensional function to a sum of products of functions of only one variable: g (x ) =

M1 M 2

MP

∑∑ ∑ L

k1 = 1 k2 = 1

kP = 1

α(k1 , k2 ,L,kP )

P

∏ Φ (x ) kj

j

(34.18)

j =1

where α(k1, k2, …, kP ) denotes a constant coefficient. These function representations were originally proposed by Chua and Kang for the PWL case [6] where

( )

( ) ( ) L Φ (x ) = x − δ

Φ1 x j = 1 Φ 2 x j = x j Φ3 x j = x j − δ j1 MP

j

(34.19)

jM P −2

j

Similar to the unidimensional case, the only nonlinearity involved in these basis functions is the absolute value. However, multidimensional functions not only require weighted summations, but also multipli­ cations. The extension of (34.18) to PWP functions was covered in [30], and involves the same kind of nonlinearities as (34.14) and (34.15). Canonical Piecewise Linear Representations The canonical PWL representation of (34.13) can be extended to the multidimensional case, based on the following representation: g (x ) = aT x + b +

Q

∑c w x − δ i

T i

i

(34.20)

i =1

where a and wi are P-vectors; b, ci, and δi are scalars; and Q represents the number of hyperplanes that divide the whole space RP into a finite number of polyhedral regions where g(·) can be expressed as an affine representation. Note that (34.20) avoids the use multipliers. Thus, g(·) in (34.20) can be realized through the block diagram of Fig. 34.8, consisting of Q absolute value nonlinearities and weighted summers. Radial Basis Functions The idea behind radial basis function expansion is to represent the function at each point of the input space as a linear combination of kernel functions whose arguments are the radial distance of the input point to a selected number of centers

© 2003 by CRC Press LLC

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Synthesis and Design of Nonlinear Circuits

�

�

��� +

∑ +

�

��

���� +

� ∑

�

�

�

�

− �

��

δ�

���� +

∑ −

∑

����

δ�

�

��

��� �

+

��

∑ − δ�

FIGURE 34.8 Canonical block diagram for a canonical PWL function.

g (x ) =

∑w Φ ( x − δ ) Q

j

j

j

(34.21)

j =1

where · denotes a norm imposed on RP, usually assumed Euclidean. The most common basis function is a Gaussian kernel similar to (34.16),  x −δ 2 Φ( x ) = exp  −   2σ 2  

(34.22)

although many other alternatives are available [51], for instance,

(

Φ(r ) = σ 2 + r 2

)

–α

Φ(r ) = r

α ≥ −1

(34.23)

where r is the radial distance to the center of the basis function, r ≡ x – δ. Micchelli [42] demonstrated that any function where the first derivative is monotonic qualifies as a radial basis function. As an example, as (34.23) displays, the identity function Φ(r) = r falls into this category, which enables connecting the representation by radial basis functions to the canonical PWL representation [40]. Figure 34.9 is a block diagram for the hardware realization of the radial basis function model. Neuro-Fuzzy Interpolation This technique exploits the interpolation capabilities of fuzzy inference, and can be viewed as the multidimensional extension of the use of linear combination of bell-shaped basis functions to approxi­ mate nonlinear functions of a single variable [see (34.4) and (34.17)]. Apart from its connection to approximate reasoning and artificial intelligence, this extension exhibits features similar to the sectionwise PWP representation, namely, it relies on a well-defined class of unidimensional functions. However, neuro-fuzzy interpolation may be advantageous for hardware implementation because it requires easyto-build collective computation operators instead of multiplications. Figure 34.10 depicts the block diagram of a neuro-fuzzy interpolator for the simplest case in which inference is performed using the singleton algorithm [33] to obtain © 2003 by CRC Press LLC

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950

The Circuits and Filters Handbook, Second Edition

δ� É

�

�

�

�

Φ�.�

�

�

Φ�.�

�

�

x

δ� É

∑

x

δ� É

��

��

x�

��

Φ�.�

x

FIGURE 34.9 Concept of radial basis function hardware.

��

��

���

���

���

���

�� ��

�

��

�

��

∑

��

���

��

���

�

��� �

��

∑ FIGURE 34.10 Conceptual architecture of a neuro-fuzzy interpolator.

g (x ) =

s j (x )

Q

∑ w ∑ s (x )

(34.24)

j

j =1

i

i = 1,Q

where the functions si (x), called activities of the fuzzy rules, are given as

{

}

s j ( x ) = Γ Φ j1 ( x1 ), Φ j 2 ( x 2 ),K, Φ jP ( x P )

(34.25)

where Γ(·) is any T-norm operator, for instance, the minimum, and Φ(·) has a bell-like shape (see Fig. 34.7). Multilayer Perceptron Similar to (34.5), but consists of the more general case of several layers, with the input to each nonlinear block given as a linear combination of the multidimensional input vector [82].

34.3 Aggregation, Scaling, and Transformation Circuits The mathematical techniques presented in Section 34.2 require several nonlinear operators and the linear operators of scaling and aggregation (covered for completeness in this section). This section also covers © 2003 by CRC Press LLC

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951

Synthesis and Design of Nonlinear Circuits

ii

iy

+ vi −

+ vi −

Y

Z ix

ix

X

FIGURE 34.11 First-order models for voltage op amps and CCIIs using nullators and norators.

�� +

��

+

�� −

��

+

��

����

−

�

+

��

�

∑

+

���

+

� = �−

�

���

� = �−

�

��

��

��

�� � ���� � �

���

�

−�

+

−

−

���

�=�

��

��

�

−

+

+

+

��

−

−

���

−

��

+ −

� = β���−���

FIGURE 34.12 Voltage-to-current transformation: (a) using an OTA; (b) using voltage feedback; (c) using a current conveyor; (d) using virtual ground of an op amp; (e) same as d, but with active resistors.

transformation circuits. This is because in many practical situations we aim to exploit some nonlinear mechanism which intrinsically involves a particular kind of characteristics. For instance, a MOS transistor has inherent square-law transconductance, while a diode exhibits an exponential driving-point. Similarly, many nonlinear operators are naturally realized in current-mode domain and involve currents at both the input and the output. Thus, transformation circuits are needed to exploit these mechanisms for other types of characteristics.

Transformation Circuits Two basic problems encountered in the design of transformation circuits are how to convert a voltage node into a current node and vice versa. We know no unique way to realize these functions. Instead, there are many alternatives which depend on which active component from Appendix A is used. The OTA can be represented to a first-order model as a voltage-controlled current source (VCCS) with linear transconductance parameter gm. Regarding the op amp and CCII, it is convenient to represent them by the first-order models of Fig. 34.11, which contain nullators and norators.1 A common appealing feature of both models is the virtual ground created by the input nullator. It enables us to sense the current drawn by nodes with fixed voltage — fully exploitable to design transformation circuits. Voltage-to-Current Transformation A straightforward technique for voltage-to-current conversion exploits the operation of the OTA as a VCCS [see Fig. 34.12(a)] to obtain i0 = gm vi , where gm is the OTA transconductance parameter [22]. A 1

A nullator simultaneously yields a short circuit and an open circuit, while the voltage and the current at a norator are determined by the external circuitry. The use of a nullator to model the input port of an op amp is valid only if the component is embedded in a negative feedback configuration. With regard to the CCII, the required feedback is created by the internal circuitry. © 2003 by CRC Press LLC

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The Circuits and Filters Handbook, Second Edition

drawback is that its operation is linear only over a limited range of the input voltage. Also, the scaling factor is inaccurate and strongly dependent on temperature and technology. Consequently, voltage-to­ current conversion using this approach requires circuit strategies to increase the OTA linear operation range [17, 70], and tuning circuits to render the scaling parameter accurate and stable [70]. As counterparts, the value of the scaling factor is continuously adjustable through a bias voltage or current. Also, because the OTA operates in open loop, its operation speed is not restricted by feedback-induced pole displacements. The use of feedback attenuates the linearity problem of Fig. 34.12(a) by making the conversion rely on the constitutive equation of a passive resistor. Figure 34.12(b) illustrates a concept commonly found in op-amp-based voltage-mode circuits [29, 59]. The idea is to make the voltage at node  of the resistor change linearly with vo , v1 = vo + avi , and thus render the output current independent of vo , to obtain io = G(vo + avi – vo) = aGvi . The summing node in Fig. 34.12 (b) is customarily realized using op amps and resistors, which is very costly in the more general case in which the summing inputs have high impedance. The circuits of Fig. 34.12(c) and (d) reduce this cost by direct exploitation of the virtual ground at the input of current conveyors [Fig. 34.12(c)] and op amps [Fig. 34.12 (d)]. For both circuits, the virtual ground forces the input voltage vi across the resistor. The resulting current is then sensed at the virtual ground node and routed to the output node of the conveyor, or made to circulate through the feedback circuitry of the op amp, to obtain io = Gvi . Those implementations of Fig. 34.12(b), (c), and (d) that use off-the-shelf passive resistors overcome the accuracy problems of Fig. 34.12(a). However, the values of monolithic components are poorly con­ trolled. Also, resistors may be problematic for standard VLSI technologies, where high-resistivity layers are not available and consequently, passive resistors occupy a large area. A common IC-oriented alter­ native uses the ohmic region of the MOS transistor to realize an active resistor [69] [Fig. 34.12(e)]. Tuning and linearity problems are similar to those for the OTA. Circuit strategies to overcome the latter are ground in [13, 32, 66, 69]. Current-to-Voltage Transformation The most straightforward strategy consists of a single resistor to draw the input current. It may be passive [Fig. 34.13(a)] or active [Fig. 34.13(b)]. Its drawback is that the node impedance coincides with the resistor value, and thus makes difficult impedance matching to driving and loading stages. These matching problems are overcome by Fig. 34.13(c), which obtains low impedances at both the input and the output ports. On the other hand, Fig. 34.13(d) obtains low impedance at only the input terminal, but maintains the output impedance equal to the resistor value. All circuits in Fig. 34.13 obtain vo = Rii , where R = g –1 m for the OTA. Voltage/Charge Domain Transformations for Sampled-Data Circuits The linearity and tuning problems of previous IC-related transformation approaches are overcome through the use of dynamic circuit design techniques based on switched-capacitors [72]. The price is that the operation is no longer asynchronous: relationships among variables are only valid for a discrete set of time instants. Variables involved are voltage and charge, instead of current, and the circuits use capacitors, switches, and op amps.

ii

ii R

+ vo −

(a)

+ vo − (b)

ii − +

−

gm

+ (c)

R −1

+ vo −

Y CCII Z X ii

R

+ vo −

(d)

FIGURE 34.13 Current-to-voltage transformation: (a) using a resistor; (b) using a feedback OTA; (c) using op amps; (d) using current conveyors.

© 2003 by CRC Press LLC

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Synthesis and Design of Nonlinear Circuits

C ϕe

vi−

ϕe

∆q

vi+

ϕo

ϕo

∆q

C

ϕe

−

ϕo

+

(a)

n

vo

n+1

(b)

FIGURE 34.14 Transformations for sampled-data circuits: (a) V-to-q; (b) q-to-V.

a12/a11 − 1/a11

x

+

∑

x′ a22

f(⋅) y′

+

∑

y +

a21 A=

cos θ − sin θ sin θ cos θ

A=

cos 2θ sin 2θ sin 2θ cos 2θ

FIGURE 34.15 Concept of linear transformation converter for transfer characteristics: general architecture, and transformation matrices for rotation (left) and reflection (right).

Figure 34.14(a) is for voltage-to-charge transformation, while Fig. 34.14(b) is for charge-to-voltage transformation. The switches in Fig. 34.14(a) are controlled by nonoverlapping clock signals, so that the structure delivers the following incremental charge to the op amp virtual ground node:

(

)

∆q e = C v i + − v i – = − ∆q o

(34.26)

where the superscript denotes the clock phase during which the charge is delivered. Complementarily, the structure of Fig. 34.14(b) initializes the capacitor during the even clock phase, and senses the incre­ mental charge that circulates through the virtual ground of the op amp during the odd clock phase. Thus, it obtains

( )

v 0o = C ∆q o

(34.27)

References [45, 46] and [68] contain alternative circuits for the realization of the scaling function. Such circuits have superior performance in the presence of parasitics of actual monolithic op amps and capacitors. Transformation among Transfer Characteristics Figure 34.15 depicts the general architecture needed to convert one kind of transfer characteristics, e.g., voltage transfer, into another, e.g., current transfer. Variables x′ and y ′ of the original characteristics can be either voltage or current, and the same occurs for x and y of the converted characteristic. The figure depicts the more general case, which also involves a linear transformation of the characteristics themselves: x x′ a11   = A  =   y   y′  a21 © 2003 by CRC Press LLC

a12 x′   a22  y′ 

(34.28)

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io

Y CCII Z X

+ vi

+

R′

− +

−

(b)

− R′

vi (a)

f (ii)

ii

+

ii = f (vi)

−

io

ii = f (vi)

vo = −f (ii)

− +

vo = f (ii)

(c)

FIGURE 34.16 From driving-point to transfer characteristics: (a) and (b) transconductance from voltage-controlled driving-point; (c) transimpedance from current-controlled driving-point.

For example, the figure encloses the matrices to rotate the characteristics by an angle θ, and to reflect the characteristics with respect to an edge with angle θ. This concept of linear transformation converters and its applications in the synthesis of nonlinear networks was proposed initially by Chua [5] for drivingpoint characteristics, and further extended by different authors [24, 29]. In the simplest case, in which the nondiagonal entries in (34.28) are zero, the transformation performed over the characteristics is scaling, and the circuits of Figs. 34.12 and 34.13 can be used directly to convert x into x′ at the input front end, and y ′ at the output front end. Otherwise, aggregation operation is also required, which can be realized using the circuits described elsewhere. From Driving-Point to Transfer and Vice Versa Figure 34.16 illustrates circuits to transform driving-point characteristics into related transfer character­ istics. Figure 34.16(a) and (b) use the same principle as Fig. 34.12(c) and (d) to transform a voltagecontrolled driving-point characteristic, ii = f (vi ), into a transconductance characteristics. On the other hand Fig. 34.16(c) operates similarly to Fig. 34.13(c) to transform a current-controlled driving-point characteristic, vi = f (ii ), into a transimpedance characteristic. If the resistance characteristics of the resistor in Fig. 34.16(a) and (b), or the conductance characteristic of the resistor in Fig. 34.16(c), is invertible, these circuits serve to invert nonlinear functions [63]. For instance, using a common base BJT in Fig. 34.16(c) obtains a logarithmic function from the BJT exponential transconductance. Also, the use of a MOST operating in the ohmic region serves to realize a division operation. Lastly, let us consider how to obtain driving-point characteristics from related transfer characteristics. Figure 34.17(a) and (b) correspond to the common situation found in op amp-based circuits, where the transfer is between voltages. Figure 34.17(a) is for the voltage-controlled case and Fig. 34.17(b) is for the current-controlled case. They use feedback strategies similar to Fig. 34.17(b) to render either the input ii

ii

R

+

∑

+

−a

+

vi

−1

vi

1

−

R

+

+

− f (.)

(a)

+ ∑

1

(b)

ii = aR−1f (vi)

vi = af (Rii)

∑ +

ii

+ − (c)

vi

+

f (.)

Rii

vi −

ii (d)

FIGURE 34.17 From transfer to driving-point characteristics. © 2003 by CRC Press LLC

f (.)

ii io

Y CCII Z X

+ vi −

vo

a

−1

ii ii

+

f (.)

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955

Synthesis and Design of Nonlinear Circuits

voltage or the input current independent of the linear contributions of the other port variable. A general theory for this kind of transformation converter can be found in [29]. Note that these figures rely on a Thévenin representation. Similar concepts based on Norton repre­ sentations allow us to transform current transfer characteristics into driving-point characteristics. How­ ever, careful design is needed to preserve the input current while sensing it. Other interesting transformation circuits are depicted in Fig. 34.17(c) and (d). The block in Fig. 34.17(c) is a transconductor that obtains io = –f (vi ) with very large input impedance. Then, application of feedback around it obtains a voltage-controlled resistor, io = f (vi ). Figure 34.17(d) obtains a current-controlled resistor, vi = f (ii ), using a current conveyor to sense the input current and feedback the output voltage of a transimpedance device with vo = f (ii ).

Scaling and Aggregation Circuitry Scaling Operation Whenever the weights are larger than unity, or are negatives, the operation of scaling requires active devices. Also, because any active device acts basically as a transconductor, the scaling of voltages is performed usually through the transformation of the input voltage into an intermediate current and the subsequent transformation of this current into the output voltage. Figure 34.18 illustrates this for an op-amp-based amplifier and an OTA-based amplifier. The input voltage is first scaled and transformed in io , and then this current is scaled again and transformed into the output voltage. Thus, the scaling factor depends on two design parameters. Extra control is achieved by also scaling the intermediate current. Let us now consider how to scale currents. The most convenient strategy uses a current mirror, whose simplest structure consists of two matched transistors connected as shown in Fig. 34.19(a) [25]. Its oper­ ating principle relies on functional cancellation of the transistor nonlinearities to yield a linear relationship   i  p io = p2 f (v i ) = p2 f  f −1  i   = 2 ii   p1   p1

(34.29)

R2 R1 vi io

vi − +

+g −

vo vo = −

(a)

R2 v R1 i

vo

− gm1 +

m2

io

gm2 vo = g vi m1

(b)

FIGURE 34.18 Mechanisms for voltage scaling. ii

p1 (a)

io

+ M1 vi −

M2

p2

io ∼

ii

p2 i p1 i

p1

io1 −

+

−

+

−

FIGURE 34.19 Current scaling using current mirrors.

Q1

io2

+ (b)

© 2003 by CRC Press LLC

io

ii

+ vi −

p2 Q2

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The Circuits and Filters Handbook, Second Edition

i1

v1

v-i conversion

v2

v-i conversion

i2

io1 io2

X CCII Z ip

vp

Y

p

io1 = ∑ ik (vk) k=1

v-i conversion

FIGURE 34.20 Aggregation of voltages through intermediate currents and current conveyor.

where p1 and p2 are parameters with value that can be designer controlled; for instance, β of the MOST or Is of the BJT (see Appendix A and [44]). The input and output currents in Fig. 34.19(a) must be positive. Driving the input and output nodes with bias currents IB and (p2 /p1 )IB , respectively, one obtains ii = ii′ + IB and io = Io′ + (p2 /p1 )IB, and this enables bilateral operation on ii′ and io′. In practical circuits, this simple design concept must be combined with circuit strategies to reduce errors due to nonnegligible input current of BJTs, DC voltage mismatch between input and output terminals, finite input resistance, and finite output resistance. Examples of these strategies can be found in [25, 56, 77]. On the other hand, sizing and layout strategies for other problems related to random mismatches between input and output devices are found in [41] and [48], which are applicable to most matching problems in MOS IC design. The current mirror concept is extensible to any pair of matched transconductors, provided their transconductance characteristics are invertible and parameterized by a designer-controlled scale factor p, and that the dependence of the output current with the output voltage is negligible. In particular, the use of differential transconductors enables us to obtain bilateral operation simply, requiring no currentshifted biasing at the input and output nodes. It also simplifies achieving noninverting amplification (that is, positive scale factors), as Fig. 34.19(b) illustrates. This figure also serves to illustrate the extension of the mirror concept to multiple current outputs. Note that except for loading considerations, no other limitations exist on the number of output transconductors that can share the input voltage. Also, because fan-out of a current source is strictly one, this replication capability is needed to enable several nodes to be excited by a common current. On the other hand, the fact that the different current output replicas can be scaled independently provides additional adjusting capability for circuit design. Signal Aggregation As for the scaling operation, aggregation circuitry operates in current domain, based on Kirchhoff ’s current law (KCL). Thus, the aggregation of voltages requires that first they be transformed into currents (equivalently, charge packets in the switched-capacitor circuitry) and then added through KCL, while currents and incremental charges are added by routing all the components to a common node. If the number of components is large, the output impedance of the driving nodes is not large enough, and/or the input importance of the load is not small enough, this operation will encompass significant loading errors due to variations of the voltage at the summing node. This is overcome by clamping the voltage of this node using a virtual ground, which in practical circuits is realized by using either the input port of an op amp, or terminals X and Y of a current conveyor. Figure 34.20 illustrates the current conveyor case.

34.4 Piecewise-Linear Circuitry Consider the elementary PWL function that arise in connection with the different methods of represen­ tation covered in Section 34.2: • Two-piece concave and convex characteristics [see (34.12)] • Hermite linear basis function (see Fig. 34.4 and Appendix B) • Absolute value [see (34.13)] © 2003 by CRC Press LLC

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957

Synthesis and Design of Nonlinear Circuits

where rectification is the only nonlinear operator involved. The circuit primitives in Appendix A exhibit several mechanisms which are exploitable in order to realize rectification: • Cut-off of diodes and transistors — specifically, current through a diode negligible for negative voltage, output current of BJTs, and MOSTs negligible under proper biasing • Very large resistance and zero offset voltage of an analog switch for negative biasing of the control terminal • Digital encoding of the sign of a differential voltage signal using a comparator Similar to scaling and aggregation operations, rectification is performed in current domain, using the mechanisms listed previously to make the current through a branch negligible under certain conditions. Three techniques are presented, which use current transfer in a transistor-based circuit, current-to-voltage transfer using diodes and op amp, and charge transfer using switches and comparators, respectively.

Current Transfer Piecewise-Linear Circuitry Figure 34.21(a) and (b) presents the simplest technique to rectify the current transferred from node  to node . They exploit the feature of diodes and diode-connected transistors to support only positive currents. Figure 34.21(a) operates by precluding negative currents to circulate from node  to node , while Fig. 34.21(b) also involves the nonlinear transconductance of the output transistor Mo ; negative currents driving the node  force vi to become smaller than the cut-in voltage and, consequently, the output current becomes negligible. A drawback to both circuits is that they do not provide a path for negative input currents, which accumulates spurious charge at the input node and forces the driving stage to operate outside its linear operating regime. Solutions to these problems can be found in [57] and [61]. Also, Fig. 34.21(a) produces a voltage displacement equal to the cut-in voltage of the rectifying device, which may be problematic for applications in which the voltage at node  bears information. A common strategy to reduce the voltage displacements uses feedback to create superdiodes (shown in Fig. 34.21(c) for the grounded case and Fig. 34.21(d) for the floating case), and where the reduction of the voltage displacement is proportional to the DC gain of the amplifier. Figure 34.22(a), called a current switch, provides paths for positive and negative currents entering node , and obtains both kinds of elementary PWL characteristics exploiting cut-off of either BJTs or MOSTs. It consists of two complementary devices: npn (top) and pnp BJTs, or n-channel (top) and p-channel MOSTs. Its operation is very simple: any positive input current increases the input voltage, turning the bottom device ON. Because both devices share the input voltage, the top device becomes OFF. Similarly, the input voltage decreases for negative input currents, so that the top device becomes

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−

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+

−

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+

��

−

FIGURE 34.21 (a) and (b) circuit techniques for current rectification; (c) and (d) superdiodes. © 2003 by CRC Press LLC

�

0912 ch34 frame55 Page 958 Wednesday, October 30, 2002 12:53 PM

958

The Circuits and Filters Handbook, Second Edition

�� ��

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+

�� �

+

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−

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+ −

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− � +

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δ �

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FIGURE 34.22 Current switch and its application for different basic PWL curves.

ON and the bottom OFF. In sum, positive input currents are drawn to the bottom device, while negative currents are drawn to the top device. An inconvenience of Fig. 34.22(a) is the dead zone exhibited by its input driving-point characteristics, which is very wide for MOSTs. It may produce errors due to nonlinear loading of the circuitry that drives the input node. Figure 34.22(b) overcomes this by using a circuit strategy similar to that of the superdiodes. The virtual ground at the op amp input renders the dead-zone centered around the voltage level E, and its amplitude is reduced by a factor proportional to the amplifier DC gain. Some considerations related to the realization of this amplifier are found in [58]. Proper routing and scaling of the currents ip and in in Fig. 34.22(a) gives us the concave and convex basic characteristics with full control of the knot and position and the slope in the conducting region. Figure 34.33(c) is the associated circuit, in which the input bias current controls the knot position, and the slope in the conducting region is given by the gain of the current mirrors. Note that this circuit also obtains the absolute value characteristics, while Fig. 34.22(d) obtains the Hermite linear basis function. The way to obtain the PWL fuzzy membership function from this latter circuit is straightforward, and can be found in [58].

Transresistance Piecewise-Linear Circuitry The circuit strategies involved in PWL current transfer can be combined in different ways with the transformation circuits discussed previously to obtain transconductance and voltage-transfer PWL cir­ cuits. In many cases design ingenuity enables optimum merging of the components and consequently, simpler circuits. Figure 34.23(a) depicts what constitutes the most extended strategy to realize the ele­ mentary PWL functions using off-the-shelf components [63, 80]. The input current is split by the feedback circuitry around the op amp to make negative currents circulate across Dn and positive currents © 2003 by CRC Press LLC

0912 ch34 frame55 Page 959 Wednesday, October 30, 2002 12:53 PM

959

Synthesis and Design of Nonlinear Circuits

��

��

��

��

��

� � ��

���

�

���

− + ���

+

�� −

�′ �′

�″

�′

�′″

− +

�′

��

−

�′

+

���

��

+

�′

���

�� ��

−

−

� � ��

���

�′

�

��

���

�′

+

FIGURE 34.23 PWL transimpedance circuits.

circulate across Dp . Consequently, this feedback renders the input node of the op amp a virtual ground and thus reduces errors due to finite diode cut-in voltage in the transresistance characteristics. Similar to Fig. 34.22, the position of the knot in these elementary characteristics is directly controlled by an input bias current. Also note that the virtual ground can be exploited to achieve voltage-to-current transfor­ mation using the strategy of Fig. 34.12(d) and thus, voltage-transfer operation. Algebraic combination of the elementary curves provided by Fig. 34.23(a) requires transforming the voltages von and vop into currents and then aggregating these currents by KCL. For example, Fig. 34.23(b) is the circuit for the absolute value and Fig. 34.23(c) presents a possible implementation of the Hermite basis function. Other related contributions found in the literature focus on the systematic realization of PWL drivingpoint resistors, and can be found in [7] and [10].

Piecewise-Linear Shaping of Voltage-to-Charge Transfer Characteristics The realization of PWL relationships among sampled-data signals is based on nonlinear voltage-to-charge transfer and uses analog switches and comparators. Figure 34.24(a) is a circuit structure, where one of the capacitor terminals is connected to virtual ground and the other to a switching block. Assume that nodes  and  are both grounded. Note that for (v – δ) > 0 the switch arrangement set node  to δ, while node  is set to v. For (v – δ) < 0, nodes  and  are both grounded. Consequently, voltage at node  in this latter situation does not change from one clock phase to the next, and consequently, the

ϕe 1 δ

−

v

+

ϕe

5

ϕo

ϕo C − (b)

FIGURE 34.24 Circuits for rectification in voltage-to-charge domain. © 2003 by CRC Press LLC

C

∆q 3

2 (a)

4

δ

+ v

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960

The Circuits and Filters Handbook, Second Edition

R2 x

+ ∑ e −

A

z

R1 x

i1

y

(a)

z = α(x/y)

(b)

− +

io

y

i2

x z

z = −α(x/y) (R2/R1)

(c)

i1 + gm1 − y

io

z

z = α(x/y)gm1

FIGURE 34.25 Division operator using a feedback multiplier: (a) concept; (b) with voltage multiplier and op amp; (c) with transconductance multiplier and OTA.

incremental charge becomes null for (v – δ) < 0. On the other hand, for (v – δ) > 0, the voltage at node  changes from one clock phase to the next, and generates an incremental charge ∆q e = C (v − δ) = − ∆q o

(34.30)

which enables us to obtain negative and positive slopes using the same circuit, as shown in Fig. 34.24(a). To make the characteristics null for (v – δ) > 0, it suffices to interchange the comparator inputs. Also, the technique is easily extended to the absolute value operation by connecting terminal  to v, and terminal  to δ. The realization of the Hermite linear basis function is straightforward and can be found in [55]. Other approaches to the realization of PWL switched-capacitor circuitry use series rectification of the circulating charge through a comparator-controlled switch [Fig. 34.24(b)], and can be found in [16] and [31]. The latter also discusses exploitation of these switched-capacitor circuits to realize continuous time driving-point characteristics, the associated transformation circuits, and the dynamic problematics.

34.5 Polynomials, Rational, and Piecewise-Polynomial Functions These functions use rectification (required for truncation operation in the PWP case) and analog multiplication, z=

xy α

(34.31)

as basic nonlinear operators.2 Joining the two inputs of the multiplier realizes the square function. Analog division is realized by applying feedback around a multiplier, illustrated at the conceptual level in Fig. 34.25(a); the multiplier obtains e = (zy)/α, and, for A → ∞, the feedback forces x = e. Thus, if y ≠ 0, the circuit obtains z = α(x/y). Joining y and z terminals, the circuit realizes the square root, z = (αx)1/2. This concept of division is applicable regardless of the physical nature of the variables involved. In the special case in which e and x are current and z is a voltage, the division can be accomplished using KCL to yield x = e. Figure 34.25(b) shows a circuit for the case in which the multiplication is in voltage domain, and Fig. 34.25(c) is for the case in which multiplication is performed in transconductance domain. The transconductance gain for input z in the latter case must be negative to guarantee stability.

Concepts and Techniques for Polynomic and Rational Functions Figure 34.26 illustrates conceptual hardware for several polynomials up to the fifth degree. Any larger degree is realized similarly. Figure 34.27 uses polynomials and analog division to realize rational functions

2Scale factor α in (34.31) must be chosen to guarantee linear operation in the full variation range of inputs and outputs.

© 2003 by CRC Press LLC

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961

Synthesis and Design of Nonlinear Circuits

α2

α0 +

x

α2

+

∑ +

x

α4

+

g(x)

+ + ∑

∑ +

α0 + +

g(x)

α3

α1

α1

α3

x

α3

α0 + + ∑ + + g(x)

α2

α5

x

α4

α1

α1

+ ∑ + α2

α0 + + ∑ + + g(x) +

FIGURE 34.26 Conceptual hardware for polynomial functions.

x

g(x)

Q

∑ αj x j

j=0

+

∑

A −

R

∑ βj x j

j=0

FIGURE 34.27 Rational function generation through feedback division.

∑α x g (x ) = ∑ β x

j

j

i=0,Q

j

(34.32)

j

j=0,R

For simplicity, we have assumed that the internal scaling factors of the multipliers in Fig. 34.26 and Fig. 34.27 equal one. An alternative technique to realize rational functions is based on linearly controlled resistors, described as v = (Lx)i, and linearly controlled conductors, i = (Cx)v, where L and C are real parameters. This technique exploits the similarity between these characteristics and those which describe inductors and capacitors in the frequency domain, to take advantage of the synthesis techniques for rational transfer function in the s-plane through interconnection of these linear components [28] [39] (Fig. 34.28). As for the previous cases, realization of linearly controlled resistors and conductors require only multipliers and, depending upon the nature of the variables involved in the multipliers, voltage-to-current and current-to-voltage transformation circuits.

Multiplication Circuitry Two basic strategies realize multiplication circuitry: using signal processing and exploiting some nonlinear mechanism of the primitive components. Signal processing multipliers rely on the generation of a pulsed signal whose amplitude is determined by one of the multiplicands and its duty cycle by the other, so that the area is proportional to the result of the multiplication operation. Figure 34.29(a) presents an implemen­ tation concept based on averaging. This is performed by a low-pass filter where the input is a pulse train © 2003 by CRC Press LLC

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The Circuits and Filters Handbook, Second Edition

i

i + v

+

x

x

v −

− i = (Cx)v

H(x)

Interconnecting these components and controlled sources generates rational network functions in s.

H(s)

v = (Lx)i

I(s)

I(s)

+ V(s)

+ V(s) −

C

−

Interconnecting these components and controlled sources generates rational network functions in x.

I(s) = sC V(s)

L

V(s) = sL I(s)

FIGURE 34.28 Usage of linearly controlled resistors to synthesize rational network functions.

vc LP Filter

x vc

z 2T

T −

ref (t)

y

+

t

3T

ref (t) y (a)

T x

α

t

3T

S

z(t)

Sample & Hold

hz(t)

− (b)

2T

z(τ)

+ y

hy(t)

FIGURE 34.29 Signal processing multipliers: (a) by averaging; (b) by shaping in time domain.

with amplitude proportional to x and duty cycle proportional to y. The latter proportionality is achieved through nonlinear sampling by comparing y with a time reference sawtooth signal. Thus, the area under each pulse in the train is the product of x × y, extracted by the low-pass filter. This implementation concept is discussed in further detail in classical texts on analog computation [63], and applied more recently to analog VLSI signal processing [72]. Figure 34.29(b) is an alternative implementation concept based on signal shaping in the time domain. It uses two linear blocks with normalized unit step response given as hz (t) and hy (t). The first is driven by level x to obtain z (t ) = xhz (t ) 0 ≤ t < τ

(34.33)

where τ denotes the duration of the time interval during which the switch S remains closed. The other is driven by a references level α, to render τ given by  y τ = hy−1    α

© 2003 by CRC Press LLC

(34.34)

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Synthesis and Design of Nonlinear Circuits

963

Assuming both linear blocks are identical and the time function invertible, one obtains the steady-state value of z, z(τ), as the product of levels x and y. The simplest implementation of Fig. 34.29 uses integrators, i.e., h(t) = t, as linear blocks [see Fig. 34.41(b)]. Also note that the principle can be extended to the generation of powers of an input signal by higher order shaping in time domain. In this case, both linear blocks are driven by reference levels. The block hy (t) consists of a single integrator, τ = y/α. The other consists of the cascade of P integrators, and obtains z(t) = βtp. Thus, z(t) = β(y/α)p. Realizations suitable for integrated circuits are found in [34] and [55].

Multipliers Based on Nonlinear Devices The primitives in Appendix A display several mechanisms that are exploitable to realize analog multipliers: • Exponential functionals associated to the large-signal transconductance of BJTS, and the possibility of obtaining logarithmic dependencies using feedback inversion • Square-law functionals associated to the large-signal transconductance of the MOS transistor operating in saturation region • Small-signal transconductance of a BJT in active region as a linear function of collector current • Small-signal transconductance of a MOST in saturation as a linear function of gate voltage • Small-signal self-conductance of a MOS transistor in ohmic region as a linear function of gate voltage These and related mechanisms have been explained in different ways and have resulted in a huge catalog of practical circuits. To quote all the related published material is beyond the scope of this section. The references listed at the end were selected because of their significance, and their cross-references contain a complete view of the state of the art. Also, many of the reported structures can be grouped according to the theory of translinear circuits, which provides a unified framework to realize nonlinear algebraic functions through circuits [23, 62, 79]. Log-Antilog Multipliers Based on the exponential large-signal transconductance of the BJT, and the following relationships, z′ = ln( x ) + ln( y ) = ln( xy ) z = e z′ = e ln( xy ) = xy

(34.35)

which can be realized as illustrated in Fig. 34.30(a) [65]. This circuit operates on positive terminal currents to obtain i0 = (i1 i2 )/i3 , which can be understood from translinear circuit principles by noting that the four base-to-emitter voltages define a translinear loop, 0 = v be1 + v be 2 − v be3 − v be 4  i  i  i  i  = ln  1  + ln 2  − ln 3  − ln o   Is   Is   Is   Is 

(34.36)

The circuit can be made to operate in four-quadrant mode, though restricted to currents larger than –IB , by driving each terminal with a bias current source of value IB . Also, because all input terminals are virtual ground the circuit can be made to operate on voltages by using the voltage-to-current transfor­ mation concept of Fig. 34.12(d). Similarly, the output current can be transformed into a voltage by using an extra op amp and the current-to-voltage transformation concept of Fig. 34.13(c). Extension of this

© 2003 by CRC Press LLC

0912 ch34 frame55 Page 964 Wednesday, October 30, 2002 12:53 PM

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The Circuits and Filters Handbook, Second Edition

�

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+ −

�

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− +

�

− +

�

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− +

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�α − +

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− +

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�α

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0, a Volterra polynomial Pn(·) exists, with n determined by ε, such that sup  ( x ) − Pn ( x ) x∈Ω

T

[ f ]T (t ) = 

Then, form a normed linear space Xe, called the extended linear space associated with X, by

{

X e = f ∈X [ f ]T

X

}

< ∞, ∀T < ∞

For a subset D ⊆ X e, any (linear or nonlinear) operator : D → Y e satisfying

[ (x )] − [ (x )] 1

2

T

T Y

≤L

[x ] − [x ] 1 T

2 T X

, ∀x1 , x 2 ∈ D,∀T ∈[0, ∞)

for some constant L < ∞, is called a generalized Lipschitz operator defined on D. The least of such constants L is given by the semi-norm of the operator :

 : sup

[ (x )] − [ (x )] 1

sup

T ∈[ 0, ∞ ) x1 ,x2 ∈D [ x1 ] ≠ [ x2 ] T

T

T

2

[x ] − [x ] 1 T

T Y

2 T X

and the operator norm of  is defined via this semi-norm by 

Lip

=  (x0 ) +  Y

for an arbitrarily chosen and fixed x0 ∈D. The following result has been established [45]. Theorem 35.7: The family of generalized Lipschitz operators

(

)

{

Lip D, Y e = : D ⊆ X e → Y e 

Lip

}

< ∞ on D

is a Banach space. Based on this theorem, a best approximation problem for generalized Lipschitz operators can be similarly formulated, and many fundamental approximation results can be obtained. In addition, gen­ eralized Lipschitz operators provide a self-unified framework for both left and right coprime factorization © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 991 Sunday, October 6, 2002 11:32 PM

991

Representation, Approximation, and Identification

representations of nonlinear feedback systems. Under this framework, the overall closed-loop system shown in Fig. 35.4 can have a causal, stable, and well-posed coprime factorization representation, which can be applied to optimal designs such as tracking and disturbance rejection [45]. We now discuss briefly a different kind of min-max (uniform) approximation: the best Hankel norm approximation, where the norm (35.27) is replaced by the operator norm of a Hankel operator defined as follows [32, 77]. Consider, for instance, the transfer function H ( z ) = α 0 + α1z −1 + α 2 z −2 +L of a discrete time linear time-invariant system. The Hankel operator associated with this series is defined as the infinite matrix

[ ]

Γα := α i − j

α 0   α1 =  α 2  M 

α1

α2

α2

L

L

L       

which is a linear operator on a normed linear space of sequences. The operator norm of Γα over the l2-space is called the Hankel norm of Γα. One important feature of the Hankel operators is reflected in the following theorem [32, 77]. Theorem 35.8: An infinite Hankel matrix has a finite rank iff its corresponding functional series is rational (it sums up to a rational function); and this is true iff the rational series corresponds to a finite-dimensional bilinear system. Another useful property of Hankel operators in system approximation is represented in the following theorem [28]. Theorem 35.9: The family of compact Hankel operators is an M-ideal in the space of Hankel operators that are defined on a Hilbert space of real-valued functions. Here, a compact operator is one that maps bounded sets to compact closures and an M-ideal is a closed subspace X of a Banach space Z such that X⊥, the orthogonal complemental subspace of X in Z, is the range of the projection P from the dual space Z* to X⊥ that has the property f = P( f ) + f − P( f ) ∀f ∈ Z * The importance of the M-ideal is that it is a proximinal subspace with certain useful approximation characteristics, where the proximinal property is defined as follows. Let L(X) and C(X) be the classes of bounded linear operators and compact operators, respectively, both defined on a Banach space X. If every ∈ L(X) has at least one best approximant from C(X), then C(X) is said to be proximinal in L(X). A typical result would be the following: for any 1 < p < ∞, C(lp) is proximinal in L(lp). However, C(X) is not proximinal in L(X) if X = C [a, b], the space of continuous functions defined on [a, b], or X = Lp[a, b] for all 1 < p < ∞ except p = 2.

Best (Uniform) Approximation of Signals (Functions) Best approximations of signals for circuits and systems are also important. For example, two (different) systems (e.g., circuits) are considered to be equivalent over a set Ω of admissible input signals iff the same input from Ω yields the same outputs through the two systems. Thus, the problem of using a system to best approximate another may be converted, in many cases, to the best approximation problem for their output signals. © 2003 by CRC Press LLC

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A signal is a function of time, usually real valued and one-dimensional. The most general formulation for best approximation of functions can be stated as follows. Let X be a normed linear space of realvalued functions and Ω be a subset of X. For a given f in X but not in Ω, find a g* ∈ Ω such that f − g * X = inf f − g g ∈Ω

(35.29)

X

In particular, if X = L∞, l∞, or H∞, the optimal solution is the best result for the worst case. If such a g* exists, then it is called a best approximant of f from the subset Ω. In particular, if Ω1 ⊂ — Ω2 ⊂ ··· is a sequence of subspaces in X, such that Ωn = X, an important practical problem is to find a sequence of best approximants g*n ∈Ωn satisfying the requirement (35.29) for each n = 1, 2, …, such that g n* – g*X → 0 as n → ∞. In this way, for each n, one may be able to construct a simple approximant g*n for a complicated (even unknown) function f, which is optimal in the sense of the min-max approximation (35.29). Existence of a solution is the first question about this best approximation. The fundamental result is the following [22, 36]. Theorem 35.10: For any f ∈ X, a best approximant g* of f in Ω always exists, if Ω is a compact subset of X; or Ω is a finite-dimensional subspace of X. Uniqueness of a solution is the second question in approximation theory, but it is not as important as the existence issue in engineering applications. Instead, characterization of a best approximant for a specific problem is significant in that it is often useful for constructing a best approximant. As a special case, the preceding best approximation reduces to the least-squares approximation if X is a Hilbert space. The basic result is the following (compare it with Theorem 35.4, and see Fig. 35.5). Theorem 33:11: Let H be a Hilbert space of real-valued functions, and let Hn be its n-dimenstional subspace. Then, given an f ∈ H, the least-squares approximation problem f − hn*

H

= infhn ∈Hn f − hn

H

is always uniquely solvable, with the optimal solution given by hn* (t ) =

n

∑ f,h

k H hk

(t )

k =1

where {hk}kn=1 is an orthonormal basis of Hn. Here, the orthonormal basis of Hn is a Chebyshev system, a system of functions which satisfy the Haar condition that the determinant of the matrix [hi (tj)] is nonzero at n distinct points t1 < L < nn in the domain. Chebyshev systems include many commonly used functions, such as algebraic and trigonometric polynomials, splines, and radial functions. Best approximation by these functions is discussed in more detail below. We remark that the least-squares solution shown in Theorem 35.11 is very general, which includes the familiar truncations of the Fourier series [36] and the wavelet series [29] as best approximation. Polynomial and Rational Approximations Let πn be the space of all algebraic polynomials pn(t) of degree not greater than n. For any continuous function f (t) defined on [a, b], one is typically looking for a best approximant p n* ∈πn for a fixed n, such that f − pn* © 2003 by CRC Press LLC

L∞ [ a ,b ]

= min pn ∈πn f − pn

L∞ [ a ,b ]

(35.30)

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This is a best (min-max and uniform) algebraic polynomial approximation problem. Replacing the algebraic polynomials by the nth-order trigonometrix polynomials of the form Σnk=0(ak cos(kt) + bk sin(kt)) changes the problem to the best trigonometric polynomial approximation, in the same sense as the best algebraic polynomial approximation, for a given function f∈C[–π,π]. This can be much further extended to any Chebyshev system, such as the radial basis functions and polynomial spline functions, which are discussed later. According to the second part of Theorem 35.10, the best uniform polynomial approximation problem (35.30) always has a solution that, in this case, is unique. Moreover, this best approximant is characterized by the following important sign-alternation theorem. This theorem is also valid for the best uniform approximation from any other Chebyshev system [22,36]. Theorem 35.12: The algebraic polynomial pn* is a best uniform approximant of f ∈ C[a, b] from πn iff there exist n + 2 points a ≤ t0 < L < tn +1 ≤ b such that f (t k ) = pn* (t k _ = c (−1) f − pn* k

k = 0, 1,K, n +1

L∞ [ a ,b ]

where c = 1 or –1. An efficient Remes (exchange) algorithm is available for constructing such a best approximant [79]. Another type of function is related to algebraic polynomials: the algebraic rational functions of the form rn,m (t) = pn (t)/qm (t), which has finite values on [a, b] with coprime pn ∈πn and qm ∈πm. We denote by Rn,m the family of all such rational functions, or a subset of them, with fixed integers n ≥ 0 and m ≥ 1. Although Rn,m is not a compact set or a linear space, the following result can be established [22]. * (t)∈R Theorem 35.13: For any given function f∈C [a, b], there exists a unique rn,m n,m such that

f − rn*,m

L∞ [ a ,b ]

= infrn,mεRn,m f − rn,m

L ∞[ a , b ]

(35.31)

The optimal solution r n* ,m (t) of (35.31) is called the best uniform rational approximant of f (t) on [a, b] from Rn,m. Note that the unique best rational approximant may have different expressions unless it is coprime, as assumed previously. The following theorem [22] characterizes such a best approximant, in which we use d(pn) to denote the actual degree of pn, 0 ≤ d (pn) ≤ n. * Theorem 35.14: A rational function r n,m = pn* /q*m is a best uniform approximant of f∈C [a, b] from Rn,m iff there exist s points a ≤ t1 < L < ts ≤ b, with s = 2 + min{n +d(qm), m+d(pn)}, such that

f (t k ) − rn*,m (t k ) = c (−1) f − rn*,m L∞[a ,b] k

k = 1,K, s

where c = 1 or –1. The Remes (exchange) algorithm [79] also can be used for constructing a best rational approximant. An important type of function approximation, which utilizes rational functions, is the Padé approx­ imation. Given a formal power series of the form f (t ) = c 0 + c1t + c 2t 2 +L

t ∈[−1, 1]

not necessarily convergent, the question is to find a rational function pn(t)/qm(t), where n and m are both fixed, to best approximate f (t) on [–1, 1], in the sense that f (t ) −

© 2003 by CRC Press LLC

pn (t ) ≤c t qm (t )

l

t ∈[−1, 1]

(35.32)

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for a “largest possible” integer l. It turns out that normally the largest possible integer is l = n + m + 1. If such a rational function exists, it is called the [n, m]th-order Padé approximant of f(t) on [-1, 1]. The following result is important [22]. Theorem 35.15: If f(t) is (n + m + 1) times continuously differntiable in a neighborhood of t = 0, then the [n, m]th-order Padé approximant of f (t) exists, with l > n. If l ≤ n + m + 1, then the coefficients {ak}kn=0 and {bk}km=0 of pn(t) and qm(t) are determined by the following linear system of algebraic equations: i

∑ j=0

f j (0) b =a j! i − j i

i = 0, 1,K,l − 1

with an+j = bm+j = 0 for all j = 1, 2, …. Moreover, if pn/qm is the [n, m]th-order Padé approximant of f(t) = Σ∞{ak}nk=0 fkt k, then the approximation error is given by f (t ) −

∞  pn (t ) =  qm (t ) k = n + 1 

m

∑ ∑f j=0

 tk b  qm (t ) 

t ∈[−1, 1]

k− j j

Padé approximation can be extended from algebraic polynomials to any other Chebyshev systems [22]. Approximation via Splines and Radial Functions Roughly speaking, spline functions, or simply splines, are piecewise smooth functions that are structurally connected and satisfy some special properties. The most elementary and useful splines are polynomial splines, which are piecewise algebraic polynomials, usually continuous, with a certain degree of smooth­ ness at the connections. More precisely, let a = t 0 < t1 < L < t n < t n+1 = b be a partition of interval [a, b]. The polynomial spline of degree m with knots {tk }kn=1 on [a, b] is defined to be the piecewise polynomial gm(t) that is a regular algebraic polynomial of degree m on each subinterval [tk, tk+1], k = 0, …, n, and is (m – 1) times continuously differentiable at all knots [41, 88]. We denote the family of these algebraic polynomial splines by Sm(t1, …, tn), which is an (n + m + 1)-dimensional linear space. Given a continuous function f (t) on [a, b], the best uniform spline approximation problem is to find a gm* ∈Sm(t1, …, tn) such that f − g m*

L∞ [ a ,b ]

= inf g m ∈Sm f − g m

(35.33)

L∞ [ a ,b ]

According to the second part of Theorem 35.10, this best uniform approximation problem always has a solution. A best spline approximant can be characterized by the following sign-alteration theorem [72], which is a generalization of Theorem 35.12, from polynomials to polynomial splines. Theorem 35.16: The polynomial spline gm* (t) is a best uniform approximant of f ∈C [a, b] from Sm(t1, …, tn) iff there exists a subinterval [tr ,tr+s ] ⊂ [a, b], with integers r and s ≤ 1, such that the maximal number γ of sign-alteration points on this subinterval [tr , tr+s ], namely, f (t k ) − g m (t k ) = c (−1) f − g m k

satisfies γ ≥ m + s + 1, where c = 1 or –1.

© 2003 by CRC Press LLC

L∞ [ a ,b ]

[

t k ∈ t r , t r +s

]

k = 1,K, γ

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Polynomial splines can be used for least-squares approximation, just like regular polynomials, if the L∞-norm is replaced by the L2-norm in (35.33). For example, B-splines, i.e., basic splines with a compact support, are very efficient in least-squares approximation. The spline quasi-interpolant provides another type of efficient approximation, which has the following structure g m (t ) =

∑ f (t ) φ (t ) m k

k

(35.34)

k

and can achieve the optimal approximation order, where {φmk } is a certain linear combination of B-splines of order m [18]. Spline functions have many variants and generalizations, including natural splines, perfect splines, various multivariate splines, and some generalized splines defined by linear ordinary or partial differntial operators with initial-boundary conditions [27, 41, 42, 44, 88]. Splines are essentially local, in the sense of having compact supports, perhaps with the exception perhaps of the thin-plate splines [94], where the domains do not have a boundary. Radial functions are global, with the property φ(r) → ∞ as r → ∞ and, normally, φ(0) = 0. Wellconditioned radial functions include r2m+1, r2m log(r), (r2 + a2)±1/2, 0 < a  1, etc. [80]. Many radial functions are good candidates for modeling nonlinear circuits and systems [63, 64]. For example, for l distinct points t1, …, tl in Rn, the radial functions {φ(t – tk )}lk=1 are linearly independent, and thus the minimization

min {ck }

f ( t) −

l

∑ (

c kφ t − tk

k=1

)

2

(35.35)

at some scattered points can yield a best least-squares approximant for a given function f (t), with some especially desirable features [81]. In particular, an affine plus radial function in the form l

a⋅t +b+

∑ c φ( t − t ) k

k

t ∈Rn

(35.36)

k=1

where a, b, {ck}lk=1 are constants, provides a good modeling framework for the canonical piecewise linear representation (35.12) of a nonlinear circuit [63]. Approximation by Means of Interpolation Interpolation plays a central role in function approximation theory. The main theme of interpolation is this: suppose that an unknown function exists for which we are given some measurement data such as its function values, and perhaps some values of its derivatives, at some discrete points in the domain. How can we use this information to construct a new function that interpolates these values at the given points as an approximant of the unknown function, preferably in an optimal sense? Constructing such a function, called an interpolant, is usually not a difficult problem, but the technical issue that remains is what kind of functions should be used as the interpolant so that a certain meaningful and optimal objective is attained? Algebraic polynomial interpolation is the simplest approach for the following Lagrange interpolation problem [22, 36]. Theorem 35.17: For arbitrarily given n + 1 distinct points 0 ≤ t0 < t1 < L < tn ≤ 1 and n + 1 real values v0, v1,…, vn, there exists a unique polynomial pn(t) of degree n, which satisfies pn (t k ) = v k © 2003 by CRC Press LLC

k = 0, 1,K, n

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This polynomial is given by pn (t ) =

n

∑ v L (t ) k k

k=0

with the Lagrange basis polynomials

(t − t 0 )L(t − t k−1 )(t − t k+1 )(t − t n )

Lk (t ): =

(t k − t 0 )L(t k − t k−1 )(t k − t k+1 )(t k − t n )

k = 0,K,n

Moreover, if f(t) is l (≤ n + 1) times continuously differentiable on [a, b], then the interpolation error is bounded by f − pn

L∞ [ 0,1]

≤

1 (l ) f n!

L∞ [ 0,1]

hL

∞

[0,1]

where h(t) = ∏ k =0(t – tk), and hL∞[0,1] attains its minimum at the Chebyshev points tk = cos (2k + 1) π/2(n + 1)), k = 0, 1,…, n. Note that the set {Lk (t)}nk =0 is a Chebyshev system on the interval [t0, tn], which guarantees the existence and uniqueness of the solution. This set of basis functions can be replaced by any other Chebyshev system to obtain a unique interpolant. If not only functional values, but also derivative values, are available and required to be interpolated by the polynomial, n–1

pn( k ) (t k ) = v k ,ik i

ik = 0,K, mk

k = 0, 1,K, n

then we have a Hermite interpolation problem. An algebraic polynomial of degree d = n + Σnk=0 mk always exists as a Hermite interpolant. An explicit closed-form formula for the Hermite interpolant also can be constructed. For example, if only the functional values {vk}nk=0 and the first derivative values {wk }nk=0 are given and required to be interpolated, then the Hermite interpolant is given by p2n (t ) =

n

∑ {v A (t ) + w B (t )} k

k

k k

k=0

where, with notation L′k(tk ): = (d/dt)Lk (t) t=t k ,

[

]

Ak (t ) = 1 − 2(t − t k )Lk′ (t k ) L2k (t ) and Bk (t ) = (t − t k )L2k (t ) in which Lk (t) are Lagrange basis polynomials, k = 0, 1, …, n. However, if those derivative values are not consecutively given, we have a Hermite–Birkhoff interpo­ lation problem, which is not always uniquely solvable [61]. The preceding discussions did not take into consideration any optimality. The unique algebraic poly­ nomial interpolant obtained previously may not be a good result in many cases. A well-known example is provided by Runge, in interpolating the continuous and smooth function f (t) = 1/(1 + 25t2) at n + 1 equally spaced points on the interval [–1, 1]. The polynomial interpolant pn(t) shows extremely high oscillations near the two end-points (t > 0.726,…). Hence, it is important to impose an additional optimality requirement (e.g., a uniform approximation requirement) on the interpolant. In this concern, the following result is useful [36].

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Theorem 35.18: Given a continuous function f∈C [–1, 1], let {tk}kn=1 be the Chebyshev points on [–1, 1]; namely, tk = cos ((2k – 1) π/(2n)), k = 1,…, n. Let also P2n–1 (t) be the polynomial of degree 2n – 1 that satisfies the following special Hermite interpolation conditions: P2n–1 (tk) = f (tk) and P2n–1 (tk ) = f (tk ) and P2′n–1(tk ) = 0, k = 1, …, n. Then, the interpolant P2n(t) has the uniform approximation property f − P2n−1

L∞ [ −1, 1]

→ 0 as n → ∞

Because polynomial splines are piecewise algebraic polynomials, similar uniform approximation results for polynomial spline interpolants may be established [41, 72, 88]. Finally, a simultaneous interpolation and uniform approximation for a polynomial of a finite (and fixed) degree may be very desirable in engineering applications. The problem is that given and f ∈ C [a, b] with n +1 points a ≤ t0 < t1 < L < tn ≤ b and a given ε > 0, find a polynomial p(t) of finite degree (usually, larger than n) that satisfies both f −pL

∞

[ a ,b ]

0

)

(36.45)

Obviously, the set of all extensions generates Abel’s group of transformations on Z that is a (n + m)­ parameter Lie group. This group is denoted by Diag{ei, fk}. Any subgroup H ⊂ Diag{ei , fk } is called an extension group of Z. We now consider extension groups H r, with 0 < r ≤ n + m. Ovsiannikov demonstrated that extensions of H r can be represented, choosing a parametric group, in the form r

x˜ i = x i

∏ α=1

(aα )

λiα

r

y˜ k = y k

∏ (a ) α

µ kα

(36.46)

α=1

where i = 1, …, n and k = 1, …, m. The main property of transformation groups is that they induce equivalence relations decomposing the subjects into equivalence classes on which the group acts. If hp acts on elements x ∈ X, and p ∈  p is the vector of parameters, an orbit U of a point x ∈ X is defined by the set U := {ξ∈X = hp (x,p), for all p ∈ p. In this sense, the points of an orbit can be identified by a transformation group.—A transformation group acts transitive on X if there exists an orbit U that is an open subset of X, with U = X. To study so-called local Lie groups with actions that are defined near a null neighborhood of the parameter space (includes its vector 0), we can discuss the Lie algebra that characterizes the local behavior of the associated local Lie group. In finite dimensional parameter spaces, a Lie algebra is generated by certain partial differential operators. Using the representations (36.46) of H r, the operators are of the form

© 2003 by CRC Press LLC

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Transformation and Equivalence

n

∑

λiα x i

i=1

∂ + ∂x i

m

∑µ y

k k α

k=1

∂ ∂y k

(36.47)

where i = 1, …, n and k = 1, …, m. These operators can be represented in a matrix form

{

}

(36.48)

µ1m   M   µ mr 

(36.49)

M(z ) := M1 o diag x1 ,…, x n ; y1 ,…, y m

where  λ11  M1 :=  M   λ1  r

L

λn1 , µ11

L

L L

L λnr ,µ1r

L

Obviously, H r is intransitive if r < n + m. In order to solve the main problem of dimension theory, we need to introduce invariants of a Lie group. Let F: X → Y be a function on X and let transformation hp of a transformation group act on X, then F is an invariant of the group if F [ha(x)] = F(x) holds for any x ∈ X and p. The invariant J: X →Y is called a universal invariant if there exists, for any invariant F: X → Y of the group, a function Φ such that F = Φ ° J. The following main theorem can be proved for the extension group. Theorem 6: For the extension group H′ on Z, there exists a universal invariant J : Z → n+m–r if the condition r < n + m is satisfied. The independent components of J have the monomial form J τ (z ) =

n

m

∏ (x ) ⋅ ∏ ( y ) i

i=1

θiτ

k

σkτ

(36.50)

k=1

where τ = 1,…, n + m – r. If dimensional analysis considers only scale transformations (36.43), this theorem contains the essential result of the so-called Pi-theorem. For this purpose we present a connection between the dimensionalities and the extension group H r (see [42]). The group H r of the space n, defined only by the dimensions of the physical quantities φk with respect to the set of symbols {Eα}, has a one-to-one correspondence with every finite set {φk } of n physical quantities, which can be measured in the system of symbols {Eα} consisting of r independent measurement units [see (36.41)]. The transformations belonging to the group H r give the rule of change, in the form r

φ˜ = φ

∏ (a ) α

λα

(36.51)

α=1

of the numerical values φκ as a result of the transition from the units {E α } to {E˜α } by means of (36.43). As a consequence of this relationship, a quantity φ is dimensionless if and only if its numerical value is an invariant of the group H r. Thus, the problem to determine the independent physical quantities of a given set of quantities is solved by the construction of a universal invariant of H r stated by the Pitheorem (see also [5]). Normalization, as well as the popular method of dimension comparison, are consequences of the invariance of physical equations with respect to the group of analogy transformations. In applications of dimensional theory, a normal form that has certain advantageous properties is desired. For example, it is useful to reduce the number of parameters in physical equations. Normal forms of this type are used very often in practice, but with no clarification of their mathematical foundation.

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Network equations, similar to other physical equations, contain numerous parameters. In applications, it is often desired to suppress some of these properties and they should be replaced by the numerical value 1. For this purpose Desloge [27], chooses a new system of units {Eα}. A theory of Desloge’s method, based on analogy transformations (36.42) instead of scale transformations (36.43), was presented by Mathis and Chua [38]. The main idea behind this method is that, beside the foundation units time [T], voltage [E], and charge [Q] that are useful in network theory, the units of other parameters are considered foundational units. We denote the units by [Aα] instead of Eα. For example, in the case of the tunneldiode circuit (see Fig. 36.2), [T], [E], and [Q], as well as [R], [C], and [L] need to be discussed. As a consequence of Desloge’s method, three of the four parameters can be suppressed and the other variables will be normalized. The method works in the case of linear as well as nonlinear networks. The method is illustrated using the tunnel-diode circuit (see (36.32) and (36.43). At first, the dimen­ sional matrix is determined by [T ]

[ E]

[R]  1

1

−1 

1

−1 

 [L]  2  [C]  0

−1

[Q]



(36.52)

 1 

that characterizes the relation between the dimensions of t, v, q, R, C, L. Desloge now considers another set of power independent dimensional scalars A1, A2, A3 with

[ A ] = [T ] [E ] [Q] a1i

ai2

ai3

i

(i = 1,2,3)

(36.53)

These relations are interpreted as an analogy transformation (36.42). Applying the map L(·) that has the same properties as the logarithmic function (see [38]) to (36.53), the symbols L([A1]), L([A2]), L([A3]) are represented by linear combinations of L([T]), L([E]), L([Q]). The coefficient matrix in (36.53) is regular and contains the exponents. Solving these linear equations using “antilog,” the [T], [E], [Q] are products of powers of [A1], [A2], [A3]. In this manner, dimensionless versions of differential equations of the tunnel diode can be derived. By using the independent units A1 := L, A2 := C, A3 := V0 to replace V0 , L , C → 1 (with respect to the new units), the following equation is derived by the approach sketched previously: [T ]

[E ]

[V0 ]  0  [L]  2  [C]  0

1

[Q] 0   −1   1 

1 −1

In([T ])  In([V0 ])      In([E ]) =  In([L])       In([Q])  In([C]) 

(36.54)

Multiplying (36.54) with the inverse of the dimensional matrix [V0 ] [T ]  0  [E ]  1  [Q]  1 and applying “antilog” to the result, we obtain © 2003 by CRC Press LLC

[L]

[C]

12

1 2  0   1 

0 0

(36.55)

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Transformation and Equivalence

[T ] = [L]1 2[C ]1 2 [E ] = [V0 ] [Q] = [V0 ][C ]

(36.56)

From these equations, the relations between the old and the new units can be derived (see [38]). T, E, and Q are expressed by the new units L, C, and V0 and the parameters and variables in (36.34) and (36.35) can be reformulated if the numerical values of V0, L, and C are added: T=L

−1 2

C

−1 2 1 2

L C1 2 ,

−1

−1

E = V0 V0 ,

−1

Q = V0 C V0C

(36.57)

These relations represent parameters and variables of the tunnel-diode network with respect to the new V0, L and C. R=

iL =

RC

L1 2C −1 2 ,

12

L

iL L

12

V0 = 1 ⋅ V0 ,

12

V0 C

12

V0 L−1 2C1 2 ,

vC =

vC V0

L = 1 ⋅ L, C = 1 ⋅ C

V0 , t =

t L

12

C

12

(36.58)

L1 2C1 2

(36.59)

The dimensional exponents for these quantities can be found by finding the inverse dimensional matrix (36.55): 1. T, E, Q: their exponents correspond the associated rows of (36.55). 2. V0, L, C, R: premultiply (36.55) with the corresponding row (36.52). ∆

For example, taking [C] = (0 – 1 1) results in [V0 ]

[T ] [E ] [Q] [C ](0 −1 1)

[T ]  0  [E ]  1  [Q]  1

[L]

[C]

[ ] [L] [C ]

0

V0 1/ 2  0  = [C ]( 0  1 

[L]

[C]

1/ 2 0

1

)

[L]

[C]

12

−1 2

)

0

(36.60)

∆

or with (36.52) [R] = (1 1 –1) [V0 ] [T ] [R](1

[E ] 1

[Q] − 1)

[T ] 0  [E ]  1  [Q]  1

12 0 0

[V0 ] 1 2  0  = [R]( 0  1 

(36.61)

With these representations of the dimensional quantities, we can obtain a dimensionless representation of (36.34) and (36.35)

© 2003 by CRC Press LLC

dvC = iL − f (vC ) dt

(36.62)

diL = 1 − ε iL − vC dt

(36.63)

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where

vc :=

vC V0

,

t :=

iL :=

t

ε :=

LC iL L

RC L

12

12

(36.64)

12

V0 C

12

(36.65)

Furthermore, the dimensionless tunnel-diode current f is defined by

f (vC ) := V0−1L1 2C −1 2 f (V0vC )

(36.66)

The associated dimensionless form of the (36.34) and (36.35) can be derived by another scaling of the current i L := ε iL. Obviously, the dimensionless normal form is not unique. The classical dimensional analysis shows that R2C/L is the only dimensionless constant of (36.32) and (36.33). Because the parallel LCR circuit includes the same constants and variables, the results of the previous dimensional analysis of the tunnel-diode circuit can be used to normalize (36.37). Further interesting applications of Desloge’s approach of suppressing superfluous parameters can be found in the theory of singular perturbations. The reader is referred to the monograph of Smith [43] for further details. Miranker [41] demonstrated that the differential equations of the tunnel-diode circuit can be studied on three time scales τ1 = L/R, τ2 = RC, and τ3 = LC with different phenomena arising. The corresponding dimensionless equations can be derived in a systematic manner by Desloge’s method. In this way, normalized differential equations describing Chua’s circuit (see [39]) can be obtained but other representations of these differential equations are possible using dimensional analysis.

36.4 Equivalence between Nonlinear Resistive Circuits In this section, we consider equivalence of nonlinear resistive n-ports. (We do not discuss resistive networks without accessible ports.) Although the explanations that follow are restricted to resistive n-ports, this theory can be extended to capacitive and inductive n-ports (see [23]). In Section 36.5, we give a definition of those n-ports. At first, we consider linear resistive 1-ports that contain Ohmic resistors described by vk = Rk ik or/and ik = Gk ik , and independent current and voltages sources v k = V0k and ik = I 0k . We can use Thevenin’s or Norton’s theorem to compare any two of those 1-ports and reduce a complex 1-port to a simple “normal” form. Therefore, two of those 1-ports are called equivalent if they have the same Thévenin (or Norton) 1-port. Clearly, by this approach, an equivalence relation is defined in the set linear resistive 1-ports and it is decomposed into “rich” classes of 1-ports. To calculate these normal forms, ∆-Y and/or Y-∆ trans­ formations are needed (see [20, 47]). It is known that this approach is not applicable to nonlinear resistive networks because ∆–Y and Y–∆ transformations generally do not exist for nonlinear networks. (This was observed by Millar [40] for the first time.) Certain networks where these transformations can be per­ formed were presented by Chua [14]. More recently, Boyd and Chua [6, 7] clarified the reasons behind this difficulty from the point of view of a Volterra series. As a conclusion, the set of nonlinear resistive 1-ports can be decomposed into equivalence classes, but, no reasonably large class of equivalent 1-ports exists. More general studies of this subject are based on the well-known substitution theorem, which can be extended to a certain class of nonlinear networks (see [26], [29]). Some results applicable to 1-ports can be generalized to linear resistive n-ports (“extraction of independent sources”), but this point of view is not suitable for nonlinear resistive n-ports. Better understanding of nonlinear resistive n-ports and the problem of equivalence cannot be based on the “operational” approach mentioned earlier. Instead, a geometric approach that was developed by © 2003 by CRC Press LLC

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Transformation and Equivalence

Brayton and Moser [9] is more useful. These authors (see also [8]) characterize a resistive n-port in a generic manner by n independent relations between the 2n port variables, n-port currents i1, …, in and n-port voltages v1, …, vn . Geometrically, this means that in the 2n-dimensional space of port variables the external behavior of a resistive n-port can be represented generically by an n-dimensional surface. The classical approach formulates a system of equations y1 − f1 ( x1 , K, x n ) = 0 M

(36.67)

y n − fn ( x1 , K, x n ) = 0 where x’s and y’s are the port variables. The zero set of equations (36.67) corresponds to the n-dimensional surface. Therefore, two n-ports are called equivalent if they are different parameterizations of the same surface. As an application of this point of view, Brayton and Moser [9] demonstrated that a 2-port consisting of a Y-circuit and a circuit consisting of a ∆-circuit cannot be equivalent, in general. For example, they proved by means of Legendre transformations that a Y-circuit with two ohmic resistors and a third resistor can be equivalent to a ∆-circuit if and only if the third resistor is also linear. Therefore, the operational approach is not a very useful concept for nonlinear n-ports. The subject of synthesizing a prescribed input–output behavior of nonlinear resistive n-ports is closely related to the problem of the equivalence. Several results were published in this area using ideal diodes, concave and convex resistors, dc voltage and current sources, ideal op amps, and controlled sources. Therefore, we give a short review of some results. We do not consider here the synthesis of resistive n-ports. Although the synthesis of nonlinear resistive n-ports was of interest to many circuit designers since the beginning of this century, the first systematic studies of this subject were published by Chua [13], [14]. Chua’s synthesis approach is based on the introduction of new linear 2-ports (R-rotator, R-reflector, and scalors) as well as their electronic realizations. Now, curves in the i–v space of port current i and port voltage v that characterize a (nonlinear) resistive 1-port can be reflected and scaled in a certain manner. Chua suggested that a prescribed behavior of an active or passive nonlinear resistive 1-port can be reduced essentially to the realization of passive i–v curves. Piecewise-linear approximations of char­ acteristics of different types of diodes, as well as the previously mentioned 2-ports, are used to realize a piecewise-linear approximation of any prescribed passive i-v curve. In a succeeding article, Chua [15] discussed a unified procedure to synthesize a nonlinear dc circuit mode that represents a prescribed family of input and output curves of any strongly passive 3-terminal device (e.g, transistor). It was assumed that the desired curves are piecewise-linear. Since then, this research area has grown very rapidly and piecewise-linear synthesis and modeling has become an essential tool in the simulation of nonlinear circuits. (see [19], [35], [37] for further references.)

36.5 Equivalence of Lumped n-Port Networks In this section, we consider more general n-ports that can be used in for device modeling (see [16]). Although many different lumped multiterminal and multiport networks are used, a decomposition into two mutually exclusive classes is possible: algebraic and dynamic multiterminal and multiport networks. Adopting the definition of Chua [16], an (n + 1)-terminal or n-port network is called an algebraic element if and only if its constitutive relations can be expressed symbolically by algebraic relationships involving at most two dynamically independent variables for each port. In the case of a 1-port, a so-called memristor is described by flux and charge, a resistor by voltage and current, a inductor by flux and current, and a capacitor by voltage and charge. An element is called a dynamic element if and only if it is not an algebraic element. Despite the fact that the class of all dynamic elements is much larger than that of algebraic ones, the following theorem of Chua [16] suggests that resistive multiports are essential for dynamic elements, too. © 2003 by CRC Press LLC

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Theorem 7: Every lumped (n + 1)-terminal or n-port element can be synthesized using only a finite number m of linear 2-terminal capacitors (or inductors) and one (generally nonlinear) (n + m)-port resistor with n accessible ports and m ports for the capacitors. Theorem 7 demonstrates that any n-port made of lumped multiterminal and/or multiport elements is equivalent to a multiterminal network where all of its nonlinear elements are memoryless. This fact offers a possibility to classify (n+1)-terminal and n-port elements in an operational manner. The proof of this theorem provides the answer of a fundamental question: what constitutes a minimal set if network elements from which all lumped elements can be synthesized? Theorem 8: The following set  of network elements constitutes the minimal basic building blocks in the sense that any lumped multiterminal or multiport element described by a continuous constitutive relation on any closed and bounded set can be synthesized using only a finite number of elements of , and that this statement is false if even one element is deleted from : 1. 2. 3. 4.

Linear 2-terminal capacitors (or inductors) Nonlinear 2-terminal resistors Linear 2-port current-controlled voltage sources (CCVS) defined by v1 = 0 and v2 = ki1 Linear 2-port current-controlled current sources (CCCS) defined by i1 = 0 and i2 = kv1

The proof of Theorem 8 (see [16]), is based on a remarkable theorem of Kolmogoroff, which asserts that a continuous function f: n →  can always be decomposed over the unit cube of n into a certain sum of functions of a single variable. Although the proof of Theorem 8 is constructive, it is mainly of theoretical interest because the number of controlled sources needed in the realization is often excessive.

36.6 Equivalence between Nonlinear Dynamic Circuits As already mentioned in Section 36.1, a set of networks can be decomposed into classes of equivalent networks by some type of equivalence relation. Such equivalence relations are introduced in a direct manner with respect to the descriptive equations, using a transformation group or classifying the behavior of the solution of the descriptive equations. In the last three sections, several useful ideas for defining equivalence relations were discussed that can be suitable for circuit theory. In this section, equivalent dynamic circuits are discussed in more details. It should be emphasized again that equivalence has a different meaning depending of the applied equivalence relation. As the so-called state-space equations in network and system theory arose in the early 1960s, a first type of equivalence was defined because various networks can be described by the same state-space equations that induced an equivalence relation. (For further references, see [46].) Although this approach is interesting, in some cases different choices of variables for describing nonlinear networks exist that need not lead to equivalent state-space equations (see [17]). In other words, the transformations of coordinates are not well conditioned. This approach was applied also to nonlinear input–output systems. A study of equivalence of a subclass of nonlinear input–output networks was presented by Verma [45] and Varaiya and Verma [44]. These authors discussed nonlinear reciprocal networks that can be formu­ lated by a so-called mixed potential function. This approach was developed by Brayton and Moser [9]. If x∈n is the state-space vector, u∈m the input vector, and e∈m is the output vector, then the statespace equations can be generated by a matrix-valued function A(x): n → n×n and a real-valued function P: n × m →  A( x )

dx ∂P = − (x, u) dt ∂x

e=

∂P (x, u) ∂u

(36.68)

(36.69)

For two such networks N1 = {A1, P1} and N2 = {A2, P2}, Varaiya and Verma defined the following equivalence. © 2003 by CRC Press LLC

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Transformation and Equivalence

Definition 4. Networks N1 and N2 A1 ( x )

∂P dx = − 1 (x, u) dt ∂x

e1 =

∂P1 (x, u) ∂u

(36.70)

(36.71)

and A 2 ( y)

∂P dy = − 2 ( y, u) dt ∂y

(36.72)

∂P2 (y, u) ∂u

(36.73)

e2 =

are equivalent if there exists a diffeomorphism y = φ(x), such that for all x0 ∈n, all input functions u, and all t ≥ 0: 1. φ[ξ(t , ξ 0 , υ)] = ψ(t , j(ξ 0 ), υ) 2. e1(t , x0 , u) = e 2 (t , φ(x0 ), u) The diffeomorphism φ is called the equivalance map. Thus, two networks are equivalent if their external behavior is identical, i.e., if for the same input and corresponding states they yield the same output. It is clear that this definition yields an equivalence relation on the set of all dynamical networks under consideration. In their paper, Varaiya and Verma showed that, under an additional assumption of controllability, the diffeomorphism φ establishes an isometry between the manifold with the (local) pseudo-Riemannian metric (dx , dx): = dx, A1dx and the manifold with the (local) pseudo-Riemannian metric (dy , dy): = dy, A 2dy in many interesting cases of reciprocal nonlinear networks. This statement has an interesting interpretation in the network context. It can be proven that φ must relate the reactive parts of the networks N1 and N2 in such a way that, if N1 is in the state x and N2 is in the state y = φ(x), and if the input u is applied, then di di dv dv d˜i ˜ ˜ d˜i dv˜ ˜ dv˜ , L( i ) , C( v ) ,Li , C( v˜ ) − = − dt dt dt dt dt dt dt dt

()

(36.74)

The concept of equivalence defined in a certain subset of nonlinear dynamic networks with input and output terminals given by Varaiya and Verma is based on diffeomorphic coordinate transformations (the transformation group of diffeomorphisms). Unfortunately, the authors presented no ideas about the kind of “coarse graining” produced in the set of networks by their equivalence relation. However, a comparison to C k conjugacy or C k equivalence of vector fields in Section 36.1 implies that input–output equivalence leads to a “fine” decomposition in the set of these networks. To classify the main features of the dynamics of networks, the concept of topological equivalence (the transformation group of homeomorphisms) is useful. On the other hand, in the case of networks with nonhyperbolic fixed points, the group of diffeomorphisms is needed to distinguish the interesting features. An interesting application of C 1 equivalence of vector fields is given by Chua [18]. To compare nonlinear networks that generate chaotic signals, Chua applied the concept of equivalence relation and concluded that the class of networks and systems that are C 1 equivalent to Chua’s circuit (Fig. 36.5) is relatively small. The nonlinearity in this network is described by a piecewise linear i–v characteristic. (See [39] for further details.) The equations describing the circuit are dvC1 dt © 2003 by CRC Press LLC

=

[(

) ( )]

1 G vC2 − vC1 − f vC1

C1

(36.75)

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G=

1 R

iR

R0 VC2

VC1

C1 L

VR

C2

iL

FIGURE 36.5 Modified Chua’s circuit.

dvC2 dt

=

((

) )

(36.76)

)

(36.77)

1 G vC1 − vC2 + iL C2

(

diL I = v − R0iL dt L C2

where R0 = 0 and the piecewise linear function is defined by

( )

f vC1 := GbvC1 +

(

1 (G − Gb ) vC1 + E − vC1 − E 2 a

)

(36.78)

Chua’s extended approach to study the set of the piecewise linear networks that include Chua’s circuit introduces the concept of global unfoldings. This concept can be considered as an analogy to the theory of “local unfoldings” of nonhyperbolic systems in a small neighborhood of singularities [3], [30]. Heu­ ristically, a minimum number of parameters in a given nonhyperbolic system is introduced, and, as the parameters are varied “any other system” near the nonhyperbolic system is obtained. Chua demonstrated that Chua’s circuit with arbitrary (R0 ≠ 0) can be considered as an “unfolding” of the original circuit. Furthermore, he proved that a class of networks that can be described without loss of generality by x˙ = Ax + b,

x1 ≤ −1

(36.79)

= A 0 x,

− 1 ≤ x1 ≤ 1

(36.80)

x1 ≥ 1

(36.81)

= Ax + b,

is equivalent to the unfolded Chua’s circuit if certain conditions are satisfied. In the associated parameter space, these conditions define a set of measure zero. The proof of this theorem as well as some applications are included in [18]. The ideas of normal forms presented in Section 36.2 can be applied to nonlinear networks with hyperbolic and nonhyperbolic fixed points. A similar theory of normal forms of maps can be used to study limit cycles, but this subject is beyond our scope. (See [3] for further details.) In any case the vector field has to be reduced to lower dimensions and that can be achieved by the application of the so-called center manifold theorem. Altman [2] illustrated this approach by calculating the center manifold and a normal form of Chua’s circuit in a tutorial style. To perform the analytical computations the piecewise nonlinearity (36.78) is replaced by a cubic function f (x) = c0 x + c1 x 3. Based on this normal form, Altman studied bifurcations of Chua’s circuit. Another application of normal forms in nonlinear dynamical networks is discussed by Keidies and Mathis [36]. In this approach, nonlinear dynamical networks with constant sources are considered and are described by nonlinear differential equations in state-space form: x˙ = f ( x ), © 2003 by CRC Press LLC

f:n → n

(36.82)

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1027

Transformation and Equivalence

linear dynamic network

Snl = fnl (X1,…,Xn)

Source Snl non-resonant

Xi

Source Snl resonant Normal Form Transformation

linear dynamic network

Yi

Snltrafo

Sres = fnl (X1 ,…, Xn)

Xi

linear dynamic network

Xi

FIGURE 36.6 Decomposition of nonlinear dynamic networks.

where all nonlinear reactances are replaced by linear reactances, nonlinear resistors, and linear controlled

sources. The nonlinearities are interpreted as nonlinear controlled sources. The network is decomposed

into a linear part that consists of linear reactances and resistive elements, and the nonlinear sources that

are used as input sources (Fig. 36.6). The network is described by the vector of state-space variables x.

Now, normal form theorems are used to transform the nonlinear sources to the input. In other words,

if the RHS f of (36.82) is decomposed into a linear and a nonlinear part, f (x) = Ax + ˜f (x), where ˜f corresponds the nonlinear sources, the system can be decomposed into two equations:

y˙ = Ay

(36.83)

x = y + F( y )

(36.84)

We now have to define the nonresonant and resonant terms of vector fields that depend on the eigenvalues of the linear part A of f and the degrees of the polynomial nonlinearities. Under certain conditions, a finite recursive process exists, such that all nonlinear sources can be transformed to the input of the linear part of a network. In these cases, the networks are described by (36.82) and (36.83). In other cases, a number of new sources are generated during the recursive process that cannot transform sources to the input. This effect is shown in Fig. 36.7(a) and (b). It should be mentioned that this idea is related in

+ iNL = vC1vC2

G1

C1

vC1 −

+ G2

C2

vC2 −

(a)

FIGURE 36.7 Decomposition of a simple nonlinear network. © 2003 by CRC Press LLC

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+ 4 ~v 1 ~ C18 v C2

1 3 v C2 v~C14 ~

1 2 v C2 v~C12 ~

G1

C1

~ v C1 −

G2

C2

+ 1 2

~ v C1 ~ v C2 −+

vC1 −

+

+

~ v C2

vC2

−

−

(b)

FIGURE 36.7 (continued).

certain sense to the so-called exact linearization that is studied in the theory of nonlinear control systems (see [34]). Therefore, this application of normal form theorems can be interpreted as a kind of extraction of nonlinear controlled sources from a nonlinear dynamic network.

References [1] V. I. Arnold, Geometrical Methods in the Theory of Ordinary Differential Equations, New York: Springer-Verlag, 1983. [2] E. J. Altman, “Bifurcation analysis of Chua’s circuit with application for low-level visual sensing,” in Chua’s Circuit: A Paradigm for Chaos, R. N. Madan, Ed., Singapore: World Scientific, 1993. [3] D. K. Arrowsmith and C. M. Place, An Introduction to Dynamical Systems, Cambridge: Cambridge Univ., 1993. [4] M. Ashkenazi and S.-N. Chow, “Normal forms near critical points for differential equations and maps,” IEEE Trans. Circuits Syst., vol. 35, pp. 850–862, 1988. [5] G. W. Bluman and S. Kumei, Symmetries and Differential Equations, New York: Springer-Verlag, 1989. [6] S. Boyd and L. O. Chua, “Uniqueness of a Basic Nonlinear Structure,” IEEE Trans. Circuits Syst., vol. CAS-30, pp. 648–651, 1983. [7] S. Boyd and L. O. Chua, “Uniqueness of circuits and systems containing one nonlinearity,” IEEE Trans. Automat. Control, vol. AC-30, pp. 674–681, 1985. [8] R. K. Brayton, “Nonlinear reciprocal networks,” in Mathematical Aspects of Electrical Network Analysis, Providence, RI: AMS, 1971. [9] R. K. Brayton and J. K. Moser, “Nonlinear networks, I, II,” Quart. Appl. Math., vol. 23, pp. 1–33, 81–104, 1964. [10] A. D. Bruno, Local Methods in Nonlinear Differential Equations, New York: Springer-Verlag, 1989. [11] J. Carr, Applications of Center Manifold Theorem, New York: Springer-Verlag, 1981. [12] L. O. Chua, “∆–Y and Y–∆ transformation for nonlinear networks,” Proc. IEEE, vol. 59, pp. 417–419, 1971. [13] L. O. Chua, “The rotator — a new network element,” Proc IEEE. vol. 55, pp. 1566–1577, 1967. [14] L. O. Chua, “Synthesis of new nonlinear network elements” Proc. IEEE, vol. 56 pp. 1325–1340, 1968. [15] L. O. Chua, “Modeling of three terminal devices: A black box approach,” IEEE Trans. Circuit Theory, vol. CT-19, pp. 555–562, 1972. [16] L. O. Chua, “Device modeling via basic nonlinear circuit elements,” IEEE Trans. Circuits Syst. vol. CAS-27, pp. 1014–1044, 1980 © 2003 by CRC Press LLC

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1029

[17] L. O. Chua “Dynamical nonlinear networks: State of the Art,” IEEE Trans. Circuits Syst., vol. CAS-27, pp. 1059–1087, 1980. [18] L. O. Chua, “Global unfolding of Chua’s circuit” IEICE Trans. Fundam., vol. E76-A, pp. 704–734, 1993. [19] L. O. Chua and A. C. Deng, “Canonical piecewise linear representation,” IEEE Trans. Circuits Syst., vol. 33, pp. 101–111, 1988. [20] L. O. Chua, C. A. Desoer, and E. S. Kukh, Linear and Nonlinear Circuits, New York: McGraw-Hill, 1987. [21] L. O. Chua and H. Kokubo, “Normal forms for nonlinear vector fields — Part I: Applications,” IEEE Trans. Circuits Syst.,vol. 36, pp. 51–70, 1989. [22] L. O. Chua and H. Kokubo, “Normal forms for nonlinear vector fields — Part II: Theory and algorithm,” IEEE Trans. Circuits Syst., vol. 35, pp. 863–880, 1988. [23] L. O. Chua and Y.-F. Lam, “A theory of algebraic n-ports,” IEEE Trans. Circuit Theory, vol. CT-20, pp. 370–382, 1973. [24] L. O. Chua and H. Oka, “Normal forms of constrained nonlinear differential equations — Part I: Theory,” IEEE Trans. Circuits Syst., vol. 35, pp. 881–901, 1988. [25] L. O. Chua and H. Oka, “Normal forms of constrained nonlinear differential equations — Part II: Bifurcation, IEEE Circuits Syst., vol. 36, pp. 71–88, 1989. [26] C. A. Desoer and E. S. Kuh, Basic Circuit Theory, New York: McGraw-Hill, 1969. [27] E. A. Desloge, “Suppression and restoration of constants in physical equations,” Amer. J. Phys., vol. 52, pp. 312–316, 1984. [28] J. Guckenheimer and P. Holmes, Nonlinear Oscillations, Dynamical Systems, and Bifurcations of Vector Fields, New York: Springer-Verlag, 1990. [29] J. Haase, “On generalizations and applications of the substitution theorem,” in Proc. ECCTD ’85, Praha, Sep. 2–6, 1985, pp. 220–223. [30] S. Hale and H. Kocak, Dynamics and Bifurcations, New York: Springer-Verlag, 1991. [31] B. D. Hassard, N. D. Kazarinoff, and Y.-H. Wan, Theory and Applications of the Hopf Bifurcation, Cambridge: Cambridge Univ., 1980. [32] B. D. Hassard and Y.-H. Wan, “Bifurcation formulae derived from center manifold theorem,” J. Math. Anal. Applicat., vol. 63, pp. 297–312, 1978. [33] R. A. Horn and C. R. Johnson, Matrix Analysis, Cambridge: Cambridge Univ., 1992. [34] A. Isidori, Nonlinear Control Systems, Berlin: Springer-Verlag, 1989. [35] J. Jess, “Piecewise Linear Models for Nonlinear Dynamic Systems,” Frequenz, vol. 42, pp. 71–78, 1988. [36] C. Keidies and W. Mathis, “Applications of normal forms to the analysis of nonlinear circuits,” in Proc. 1993 Int. Symp. Nonlinear Theory, Applicat., Hawaii, Dec. 1993. [37] T. A. M. Kevenaar and D. M. W. Leenaerts, “A comparison of piecewise-linear model descriptions,” IEEE Trans. Circuits Syst. I, vol. 39, pp. 996–1004, 1992. [38] W. Mathis and L. O. Chua “Applications of dimensional analysis to network theory,” Proc. ECCTD ’91, Copenhagen, Sep. 4–6, 1991. [39] R. N. Madan, Ed., Chua’s Circuit: A Paradigm for Chaos, Singapore: World Scientific, 1993. [40] W. Millar, “The nonlinear resistive 3-pole: Some general concepts,” in Proc. Symp. Nonlinear Circuit Anal., Polytech. Instit., Brooklyn, NY: Interscience, 1957. [41] W. L. Miranker, Numerical Methods for Stiff Equations and Singular Perturbation Problems, Dor­ drecht: D. Reidel, 1981. [42] L. V. Ovsiannikov, Group Analysis of Differential Equations, New York: Academic Press, 1982. [43] D. R. Smith, Singular-Perturbation Theory, Cambridge: Cambridge University, 1985. [44] P. P. Varaiya and J. P. Verma, “Equivalent nonlinear reciprocal networks,” IEEE Trans. Circuit Theory, vol. CT-18, pp. 214–217, 1971. [45] J. P. Verma, “Equivalence of nonlinear networks,” Ph.D. dissertation, University of California, Berkeley, 1969. [46] A. N. Willson, Jr., Nonlinear Networks: Theory and Analysis, New York: IEEE, 1975. [47] W. Mathis and R. Pauli, “Networks Theorems,” in Wiley Encyclopedia of Electrical and Electronics Engineering, vol. 14, New York: John Wiley & Sons, 1999. © 2003 by CRC Press LLC

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37 Piecewise-Linear Circuits and PiecewiseLinear Analysis

J. Vandewalle Katholieke Universiteit

L. Vandenberghe University of California, Los Angeles

37.1 Introduction and Motivation 37.2 Hierarchy of Piecewise-Linear Models and Their Representations 37.3 Piecewise-Linear Models for Electronic Components 37.4 Structural Properties of Piecewise-Linear Resistive Circuits 37.5 Analysis of Piecewise-Linear Resistive Circuits 37.6 Piecewise-Linear Dynamic Circuits 37.7 Efficient Computer-Aided Analysis of PWL Circuits

37.1 Introduction and Motivation In this chapter, we present a comprehensive description of the use of piecewise-linear methods in modeling, analysis, and structural properties of nonlinear circuits. The main advantages of piecewise linear circuits are fourfold. (1) Piecewise-linear circuits are the easiest in the class of nonlinear circuits to analyze exactly, because many methods for linear circuits can still be used. (2) The piecewise-linear approximation is an adequate approximation for most applications. Moreover, certain op amp, opera­ tional transconductance amplifier, diode and switch circuits are essentially piecewise linear. (3) Quite a number of methods exist to analyze piecewise-linear circuits. (4) Last, but not least, piecewise-linear circuits exhibit most of the phenomena of nonlinear circuits while still being manageable. Hence, PWL circuits provide unique insight in nonlinear circuits. The section consists of six parts. First, the piecewise-linear models will be presented and interrelated. A complete hierarchy of models and representations of models is presented. Rather than proving many relations, simple examples are given. Second, the piecewise-linear models for several important electronic components are presented. Third, since many PWL properties are preserved by interconnection, a short discussion on the structural properties of piecewise-linear circuits is given in Section 37.4. Fourth, analysis methods of PWL circuits are presented, ranging from the Katzenelson algorithm to the linear comple­ mentarity methods and the homotopy methods. Fifth, we discuss PWL dynamic circuits, such as the famous Chua circuit, which produces chaos. Finally, in Section 37.7, efficient computer-aided analysis of PWL circuits and the hierarchical mixed-mode PWL analysis are described. A comprehensive reference list is included. For the synthesis of PWL circuits, we refer to Chapter 34. In order to situate these subjects in the general framework of nonlinear circuits, it is instructive to interrelate the PWL circuit analysis methods (Fig. 37.1). In the horizontal direction of the diagrams, one does the PWL approximation of the dc analysis from left to right. In the vertical direction, we show the conversion from a circuit to a set of equations by network equation formulation and the conversion from

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general resistive nonlinear circuits

approximation PWL modeling

network equation formulation

general circuit with resistive PWL components

circuit with linear resistors and ideal diodes

network equation formulation

nonlinear algebraic equations

network equation formulation generalized linear complementary equation GLCP

linear equations in polyhedral regions

iterative equation solving

one or more solutions (a)

general dynamic piecewise linear circuits

general resistive piecewise linear circuits

dc analysis

network equation formulation

network equation formulation set of piecewise linear algebraic equations

set of piecewise linear differential equations solving

solving one or more equilibrium or dc value

waveforms (b)

FIGURE 37.1 Interrelation of PWL circuit analysis methods: (a) resistive and (b) dynamic nonlinear circuits.

equations to solutions (waveforms or dc values) by solution methods. The specific methods and names used in the figure are described in detail in the different parts.

37.2 Hierarchy of Piecewise-Linear Models and Their Representations In the past 25 years, much progress has been achieved in the representations of piecewise-linear resistive multiports and their relationships (see references). From a practical point of view, a clear trade-off exists © 2003 by CRC Press LLC

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i1 + v1 −

in +

vn

−

FIGURE 37.2 Resistive n-port.

i2

i1 +

+ G

v1

v2 −

−

FIGURE 37.3 2-port configuration of a bipolar transistor.

between the efficiency of a representation in terms of the number of parameters and the ease of evaluation (explicit versus implicit models) on the one hand and the generality or accuracy on the other hand. Here, we go from the easiest and most efficient to the most general representations. We define here a resistive multiport (Fig. 37.2) as an n-port whose port variables (the vector of port currents i = [i1…in]T and the vector of port voltages v = [v1…vn]T ) are related by m algebraic equations called constitutive equations ϕ(i, v ) = 0

(37.1)

where i, v∈n and φ(.,.) maps 2n into m. For example, for a bipolar transistor (Fig. 37.3), one obtains the explicit form i1 = f1(v1 , v 2 ) and i2 = f 2 (v1 , v 2 ) and i = [i1, i2]T and v = [v1, v2]T. These relations can be measured with a curve tracer as dc characteristic curves. Clearly, here φ(.,.) is a map from 4 → 2 in the form i1 − f1 (v1 , v 2 ) = 0

(37.2)

i2 − f 2 (v1 , v 2 ) = 0

(37.3)

It is easy to see that a complete table of these relationships would require an excessive amount of computer storage already for a transistor. Hence, it is quite natural to describe a resistive n-port with a piecewiselinear map f over polyhedral regions Pk by v = f (i ) = ak + Bki ,

i ∈ Pk ,

{

}

k ∈ 0, 1, ...., 2l −1

(37.4)

where the Jacobian Bk ∈ n×n and the offset vector ak ∈n are defined over the polyhedral region Pk , separated by hyperplanes c iT x − di = 0, i = 1, ..., l and defined by

{

Pk = x ∈n c Tj x − d j ≥ 0, j ∈I k ,c Tj x − d j ≤ 0, j ∉ I k where k = Σj∈Ik 2j–1, Ik ⊆ {1, 2, …, l} and cj∈n, dj∈n. © 2003 by CRC Press LLC

}

(37.5)

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�

�� � − �� = �

��

� = �� + � � �

��

�

�� � − �� = �

�� � = �� + � � � ��

� = �� + � � �

�� � = �� + � � �

��

�

FIGURE 37.4 A PWL function defined in four polyhedral regions in n defined by c T1 i – d1  0 and c T2 i  d2 > 0.

In other words, the hyperplanes c iT x − di = 0, i = 1, ..., l separate the space n into 2l polyhedral regions Pk (see Fig. 37.4) where the constitutive equations are linear. The computer storage requirements for this representation is still quite large, especially for large multiports. A more fundamental problem with this rather intuitive representation is that it is not necessarily continuous at the boundaries between two polyhedral regions. In fact, the continuity of the nonlinear map is usually desirable for physical reasons and also in order to avoid problems in the analysis. The canonical PWL representation [6] is a very simple, attractive, and explicit description for a resistive multiport that solves both problems: v = f (i ) = a + Bi +

l

∑e

j

c Tj i − d j

(37.6)

j =1

One can easily understand this equation by looking at the wedge form of the modulus map (see Fig. 37.5). It has two linear regions: in the first x ≥ 0 and y = x, while in the second x ≤ 0 and y = –x. At the boundary the function is clearly continuous. Equation (37.6) is hence also continuous and is linear in each of the polyhedral regions Pk described by (37.5). If l modulus terms are in (37.6), there are 2l polyhedral regions where the map (37.6) is linear. Because the map is represented canonically with n + n2 + l(n + 1) real parameters, this is a very compact and explicit representation. Several examples of canonical PWL models for components are given in Section 37.3. y = |x|

x

FIGURE 37.5 The absolute value function y =  x . © 2003 by CRC Press LLC

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1035

i

+

v

v

0

− (a)

FIGURE 37.6 (a) The ideal diode and (b) the (i–v) rela­ tion of an ideal diode.

(b)

From Fig. 37.5, it should be clear that the right and left derivative of y = x at 0 are different, their difference being 2. Hence, the Jacobian J+ and J– of (37.6) will be different on the boundary between the two neighboring polyhedral regions where (c ji − d j ) ≥ 0 and (c ji − d j ) ≤ 0 J + − J − = 2e jc Tj

(37.7)

Observe that this difference is a rank 1 matrix, which is also called a dyadic or outer vector product of ej and cj . Moreover, this difference is independent of the location of the independent variable i on the boundary. This important observation is made in [24], and is called the consistent variation property [10] and essentially says that the variation of the Jacobian of a canonical PWL representation is inde­ pendent of the place where the hyperplane cj i – dj = 0 is crossed. Of course, this implies that the canonical PWL representation (37.6) is not the most general description for a continuous explicit PWL map. In [26] and [29] two more general representations, which include nested absolute values, are presented. These are too complicated for our discussion. Clearly, the canonical PWL representation (37.6) is valid only for single-valued functions. It can clearly not be used for an important component: the ideal diode (Fig. 37.6) characterized by the multivalued (i, v) relation. It can be presented analytically by introducing a real scalar parameter ρ [31].

(

)

(37.8)

(

)

(37.9)

i=

1 ρ+ ρ 2

v=

1 ρ− ρ 2

This parametric description can easily be seen to correspond to Fig. 37.6(b) because i = ρ and v = 0 for ρ ≥ 0, while i = 0 and v = ρ when ρ ≤ 0. Such a parametric description i = f (ρ) and v = g(ρ) with f and g PWL can be obtained for a whole class of unicursal curves (see[6]). When we allow implicit representations between v and i for a multiport, we obtain an LCP (linear complementarity problem) model (37.10)–(37.12) with an interesting state space like form [55]: v = Ai + Bu + f

(37.10)

s = Ci + Du + g

(37.11)

u ≥ 0, s ≥ 0, uT s = 0

(37.12)

where A∈ n×n, B∈ n×l, f∈ n×n, c∈ l×n, D∈ l×l are the parameters that characterize the relationship between v and i. In the model, u and s are called the state vectors and we say that u ≥ 0 when all its components are nonnegative. Clearly, (37.12) dictates that all components of u and s should be nonnegative and that, whenever a component uj satisfies uj > 0, then sj = 0 and, vice versa, when sj > 0, then uj = 0. © 2003 by CRC Press LLC

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This is called the linear complementarity property, which we have seen already in the ideal diode (37.8) and (37.9) where i ≥ 0, v ≥ 0 and iv = 0. Hence, an implicit or LCP model for the ideal diode (37.8) and (37.9) is v =u

(37.13)

s=i

(37.14)

u ≥ 0 s ≥ 0 us = 0

(37.15)

In order to understand that the general equations (37.10)–(37.12) describe a PWL relation such as (37.4)–(37.5) between i and v over polyhedral regions, one should observe first that v = Ai + f is linear when u = 0 and s = Ci + g ≥ 0. Hence, the relation is linear in the polyhedral region determined by Ci + g ≥ 0. In general, one can consider 2l possibilities for u and s according to

(u ≥ 0 and s = 0) or (u j

j

j

)

= 0 and s j = 0 , for j = 1, 2, ..., l

Denote sets of indexes U and S for certain values of u and s satisfying (37.12)

{

}

(37.16)

{

}

(37.17)

U = j u j ≥ 0 and s j = 0 S = j u j = 0 and s j ≥ 0

then, clearly, U and S are complementary subsets of {1, 2, …, l} when for any j, uj , and sj cannot be both zero. Clearly, each of these 2l possibilities corresponds to a polyhedral region PU in n, which can be determined from u j ≥ 0, (Ci + Du + g ) j = 0 for j ∈U

(37.18)

u j = 0, (Ci + Du + g ) j ≥ 0 for j ∈S

(37.19)

The PWL map in region PU is determined by solving the uj for j ∈U from (37.18) and substituting these along with uj = 0 for j ∈S into (37.10). This generates, of course, a map that is linear in the region PU. When (37.11) is replaced by the implicit equation Es + Ci + Du + gα = 0 α ≥ 0 in (37.10)–(37.13), we call the problem a generalized linear complementarity problem (GLCP). A nontrivial example of an implicit PWL relation (LCP model) is the hysteresis one port resistor (see Fig. 37.7). Its equations are:

P{2}

v 1

P{}

P{1}

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0

1

i

FIGURE 37.7 The hysteresis nonlinear resistor.

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1037

u1  v = −i + [−1 1]   +1 u2 

(37.20)

s1  –1 –1 1 u1  1   =  i +    +  s 2   1 1 –1 u2  0

(37.21)

s1 ≥ 0, s 2 ≥ 0,

u1 ≥ 0, u2 ≥ 0, u1s1 + u2s 2 = 0

(37.22)

In the first region P, we have s1 = −i + 1 ≥ 0, s 2 = i ≥ 0, and v = −i +1

(37.23)

The region P{1,2}, on the other hand, is empty because the following set of equations is contradictory: s1 = s 2 = 0,

− i – u1 + u2 +1 = 0,

i +u1 − u2 = 0

(37.24)

The region P[1] is u1 ≥ 0,

s1 = −i − u1 +1 = 0,

u2 = 0,

s 2 = i + u1 ≥ 0

(37.25)

Hence, u1 = –i + 1 and s2 = 1 and v = –i + i – 1 + 1 =0, while i ≤ 1. Finally, the region P[2] is u1 ≥ 0,

s1 = −i + u2 + 1 ≥ 0,

u2 ≥ 0,

s 2 = i − u2 = 0

Hence, u2 = i and s1 = 1 and v = −i + i + 1 = 1, while i ≥ 0

(37.26)

It is now easy to show in general that the canonical PWL representation is a special case of the LCP model. Just choose uj ≥ 0 and sj ≥ 0 for all j as follows:

(

)

(37.27)

(

)

(37.28)

c Tj i − d j =

1 u +s 2 j j

c Tj i − d j =

1 u −s 2 j j

then, u and s are complementary vectors, i.e., u≥0

s≥0

uT s = 0

Observe that the moduli in (37.6) can be eliminated with (37.27) to produce an equation of the form (37.10) and that (37.28) produces an equation of the form (37.11). More generally, it has been proven [36] that the implicit model includes all explicit models. Because it also includes the parametric models, one obtains the general hierarchy of models as depicted in Fig. 37.8. A general remark should be made about all models that have been presented until now. Although the models have been given for resistive multiports where the voltages v at the ports are expressed in terms of the currents i, analogous equations can be given for the currents i in terms of the voltages, or hybrid

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explicit models with nested moduli [Güzelis, Göknar] [Kahlert, Chua]

implicit models LCP [van Bokhoven] GLCP [Vandenberghe e.a.]

canonical PWL model [Chua, Kang] satisfies constant variation property

parametric models [Chua, Kang]

FIGURE 37.8 The interrelation of the PWL models.

variables. It can even be adapted for piecewise linear capacitors, inductors, or memristors, where the variables are, respectively, q, v for capacitors, ϕ, i for inductors, and q, ϕ for memristors.

37.3 Piecewise-Linear Models for Electronic Components In order to simulate nonlinear networks with a circuit or network simulator, the nonlinear behavior of the components must be modeled fist. During this modeling phase, properties of the component that are not considered important for the behavior of the system may be neglected. The nonlinear behavior is often important, therefore, nonlinear models have to be used. In typical simulators such as SPICE, nonlinear models often involve polynomials and transcendental functions for bipolar and MOS transis­ tors. These consume a large part of the simulation time, so table lookup methods have been worked out. However, the table lookup methods need much storage for an accurate description of multiports and complex components. The piecewise-linear models constitute an attractive alternative that is both efficient in memory use and in computation time. We discuss here the most important components. The derivation of a model usually requires two steps: first, the PWL approximation of constitutive equations, and second, the algebraic representation. Two PWL models for an ideal diode (Fig. 37.6) have been derived, that is, a parametric model (37.8) and (37.9) and an implicit model (37.13)–(37.15), while a canonical PWL model does not exist. The piecewise-linear models for operational amplifiers (op amps) and operational transconductance amplifiers (OTA’s) are also simple and frequently used. The piecewise-line approximation of op amps and OTA’s of Fig. 37.9 is quite accurate. It leads to the following representation for the op amp, which is in the linear region for – Esat ≤ v0 ≤ Esat with voltage amplification Av and positive and negative saturation Esat and –Esat v0 =

Av  E E  v + sat − v i − sat  2  i Av Av  i− = i+ = 0

(37.29)

(37.30)

This is called the op amp finite-gain model. In each of the three regions, the op amp can be replaced by a linear circuit. For the OTA, we have similarly in the linear region for − I sat ≤ i0 ≤ I sat with transconductance gain gm and positive and negative saturation Isat and –Isat i0 =

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gm  I I  v i + sat − v i− sat   2  gm gm 

(37.31)

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vo

i

−

− vi +

−

Esat +

+ i

AV

vo +

− Esat/AV

−

Esat/AV

vi

− Esat

(a)

io i

−

− vi +

−

gm

+

+ i

Isat

io

+

−Isat/gm

−

Isat/gm

vi

−Isat

(b)

FIGURE 37.9 (a) Op amp and PWL model and (b) OTA and PWL model.

i− = i+ = 0

(37.32)

Next, for a tunnel diode, one can perform a piecewise-linear approximation for the tunnel-diode characteristic as shown in Fig. 37.10. It clearly has three regions with conductances g1, g2, and g3. This PWL characteristic can be realized by three components [(Fig. 37.10(b)] with conductances, voltage sources, and diodes. The three parameters G0, G1, and G2 of Fig. 37.10(b) must satisfy in Region 1:

G0 = g 1

(37.33)

in Region 2:

G0 + G1 = g 2

(37.34)

in Region 3:

G0 + G1 + G2 = g 3

(37.35)

Thus, G0 = g1, G1 = –g1 + g2, and G2 = –g2 + g3. We can derive the canonical PWL representation as follows: i=−

1 1 1  1 1  G1E1 + G2E 2 ) +  G0 + G1 + G2  v + G1 v − E1 + G2 v − E 2 (   2 2 2 2 2

(37.36)

Next, we present a canonical piecewise-linear bipolar transistor model [12]. Assume a npn bipolar transistor is connected in the common base configuration with v1 = vBE , v2 = vBC , i1 = iE , and i2 = iC , as shown in Fig. 37.3. We consider data points in a square region defined by 0.4 ≤ v1 ≤ 0.7 and 0.4 ≤ v2 ≤ 0.7, and assume the terminal behavior of the transistor follows the Ebers–Moll equation; namely,

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(

) (

)

(37.37)

(

) (

)

(37.38)

i1 =

I s v1 VT e −1 − I s e v2 VT −1 αf

i2 =

I s v2 VT e −1 − I s e v1 VT −1 αr

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i

g3 g2

(a) 0 E1

E2

v

g1

+ region 1

region 2

G1

region 3 v

G0 E1

−

i

G2

E2

G0 (c)

G2

(b)

E1 E2

v

G1

FIGURE 37.10 (a) Piecewise-linear approximation of the tunnel-diode characteristic. The three-segment approxi­ mation defines the three regions indicated. (b) Decomposition of the piecewise-linear characteristic (a) into three components, and (c) the corresponding circuit.

with Is = 10–14 A, VT = 26 mV, αf = 0.99, and αr = 0.5. In [12], the following canonical piecewise-linear model is obtained, which optimally fits the data points (Fig. 37.11) i1  a1  b11   =  + i 2  a 2  b12

b21 v1  c 11    +   m1v1 − v 2 +t 1 b22  v 2  c 21 

c 12  c 13  +   m 2v1 − v 2 +t 2 +   m3v1 − v 2 +t 3 c 22  c 23  where a1   5.8722 × 10 −3  b11   3.2392 × 10 −2   = 

 = a2  −3.2652 × 10 −2  b21  −3.2067 × 10 −2 

b12  −4.0897 × 10 −2  c11   3.1095 × 10 −6    =  = b22   8.1793 × 10 −2  c 21  −3.0784 × 10 −6  © 2003 by CRC Press LLC

(37.39)

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iE(mA)

iE(mA)

4.976 2.996 1.015 −0.965 −2.946 −4.926 0.70 0.64 0.58 0.52 0.46 vBE(Volt) 0.40

0.40 0.46 0.52 0.58 0.64 v (Volt) BC 0.70

4.032 2.428 0.824 −0.779 −2.383 −3.987 0.70 0.64 0.58 0.52 0.46 vBE(Volt)

0.70

0.4

(a)

0.40 0.46 0.52 0.58 0.64 vBC(Volt)

(b)

iC(mA)

iC(mA)

9.853 6.897 3.941 0.985 -1.971 -4.926 0.40 0.46 0.52 0.58 0.64 vBE(Volt) 0.70

0.70 0.64 0.58 0.52 0.46 v (Volt) BC 0.40

7.974 5.581 3.188 0.796 -1.597 -3.990 0.40 0.46 0.52 vBE(Volt) 0.58 0.64

0.70 0.64 0.58 0.52 vBC(Volt) 0.46 0.40

0.70

(c)

(d) IC (mA) I8 = 50µA

5

I8 = 40µA

4

I8 = 30µA

3

I8 = 20µA

2

I8 = 10µA

1 1 I8 = 10µA I8 = 10µA

−020 −015 −010 −005

I8 = 10µA I8 = 20µA I8 = 30µA I8 = 40µA I8 = 50µA

005 010 015 020

2

3

4

5

VCE (Volt)

VCE (Volt)

−20 −40 −60 −80 −100

IC (µA)

FIGURE 37.11 Three-dimensional plots for the emitter current in the Ebers-Moll model given by (37.37) and (37.38). (b) Three-dimensional plot for the emitter current in the canonical piecewise-linear model given by [10, (B.1)] (low-voltage version). (c) Three-dimensional plot for the collector current in the Ebers-Moll model given by (37.37) and (37.38). (d) Three-dimensional plot for the collector current in the canonical piecewise-linear model given by [10, (B.1)] (low-voltage version). (e) Comparison between the family of collector currents in the EbersMoll model (dashed line) and the canonical piecewise-linear model (solid line). Source: L.O. Chua and A. Deng, “Canonical piecewise linear modeling,” IEEE Trans. Circuits Syst., vol. CAS-33, p. 519,  1986, IEEE.

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i2 i1 + v1 −

G

+ D v2 S −

FIGURE 37.12 2-port configuration of the MOSFET.

c12  −9.9342 × 10 −3    = −2 c 22   1.9868 × 10  m1   1.002 × 10 4      m2  =  −1.4 × 10 –4      m  1.574 × 10 –6   3

c13  −3.0471 × 10 −2    = −2 c 23   6.0943 × 10 

t1   −6472     t 2  = 0.61714     t  0.66355  3

Next, a canonical piecewise-linear MOS transistor model is presented. Assume the MOS transistor is connected in the common source configuration with v1 = vGS , v2 = vDS , i1 = iG , and i2 = iD , as illustrated, in Fig. 37.12, where both v1 , v 2 are in volts, and i1, i2 are in microamperes. The data points are uniformly spaced in a grid within a rectangular region defined by 0 ≤ v1 ≤ 5, and 0 ≤ v2 ≤ 5. We assume the data points follow the Shichman–Hodges model, namely, i1 = 0

[

]

i2 = k (v1 − Vt )v 2 − 0.5v 22 , if v1 − Vt ≥ v 2 or

[

]

i2 = 0.5k(v1 − Vt ) 1 + λ(v 2 − v1 + Vt ) , if v1 − Vt < v 2 2

(37.40)

with k = 50 µA/V 2, Vt = 1 V, λ = 0.02 V –1. Applying the optimization algorithm of [11], we obtain the following canonical piecewise-linear model (see Fig. 37.13): i2 = a2 + b21v1 + b22v 2 + c 21 m1v1 − v 2 + t1 + c 22 m2v1 − v 2 + t 2 + c 23 m3v1 − v 2 + t 3

(37.41)

where a2 = −61.167,

b21 = 30.242,

b22 = 72.7925

c 21 = −49.718,

c 22 = −21.027,

c 23 = 2.0348

m1 = 0.8175,

m2 = 1.0171,

m3 = −23.406

t1 = −2.1052,

t 2 = −1.4652,

t 3 = 69

Finally, a canonical piecewise-linear model of GaAs FET is presented. The GaAs FET has become increasingly important in the development of microwave circuits and high-speed digital IC’s due to its fast switching speed.

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408.0 326.4 244.8 163.2 81.6 0

iD(µA)

MOSFET OUTPUT CHAR.

5 1

vGS(Volt)

500

4 2

3

vDS(Volt)

1

4

vGS = 5

375

0 iO(µA)

5 (a)

382.9 302.6 222.3 142.0 61.72 −18.57 0 1 vGS(Volt)

Eq. (4.39) Eq. (4.43)

3

2

iD(µA)

vGS = 4

250

vGS = 3

125

vGS = 2 0 0

1

5

2

3

2

4 5

0

1

4

5

vDS(Volts)

4 3

2

3

(c)

vDS(Volt)

(b)

FIGURE 37.13 (a) Three-dimensional plot of drain current from the Shichman–Hodges model. (b) Three-dimen­ sional plot of the drain current from the canonical piecewise-linear model. (c) Family of drain currents modeled by (37.40) (dashed line) and (37.41) (solid line). Source: L. O. Chua and A. Deng, “Canonical piecewise-linear modeling,” IEEE Trans. Circuits Syst., vol. CAS-33, p. 520, 1986.  1986 IEEE.

i2 = a2 + b21v1 + b22v 2 + c 21 m1v1 − v 2 + t 2 + c 22 m2v1 − v 2 + t 2 + c 23 m3v1 − v 2 + t 3

(37.42)

where v1 = vGS (volt), v2 = vDS (volt), i2 – iD (mA), and a2 = 6.3645,

b21 = 2.4961,

b22 = 32.339

c 21 = 0.6008,

c 22 = 0.9819,

c 23 = −29.507

m1 = −19.594,

m2 = −6.0736,

m3 = 0.6473

t1 = −44.551,

t 2 = −8.9962,

t 3 = 1.3738

Observe that this model requires only three absolute-value functions and 12 numerical coefficients and compares rather well to the analytical model (Fig. 37.14). More piecewise-linear models for timing analysis of logic circuits can be found in [21]. In the context of analog computer design, even PWL models of other nonlinear relationships have been derived in [51].

37.4 Structural Properties of Piecewise-Linear Resistive Circuits When considering interconnections of PWL resistors (components), it follows from the linearity of KVL and KCL that the resulting multiport is also a piecewise-linear resistor. However, if the components have a canonical PWL representation, the resulting multiport may not have a canonical PWL representation. This can be illustrated by graphically deriving the equivalent one port of the series connection of two © 2003 by CRC Press LLC

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GaAs FET OUTPUT CHAR. 125 vGS = 0

100

iD(mA)

vGS = −0.5 75

vGS = −1.0

50

vGS = −1.5

25

vGS = −2.0 vGS = −2.5

0 0

1

2 3 vDS(Volt)

4

5

FIGURE 37.14 Comparison of the canonical piecewise-linear described by (37.42) (solid line) and the analytical model (dashed line) for the ion-implanted GaAs FET. Source: L. O. Chua and A. Deng, “Canonical piecewise-linear modeling,” IEEE Trans. Circuits Syst., vol. CAS-33, p. 522, 1986,  1986 IEEE.

(a)

(b) +

+

i

i1

v1

v

− +

−

−

i1 4 3

i2

2

2 1

0

(c)

i

i2

1

2

3

4

5

6 v1

(d)

4 3 2 1

0

1

2

3

4

v2

FIGURE 37.15 (a) The series connection of two tunnel diodes, (b) and (c), their i-v characteristics, and (d) the composite i–v plot, which consists of two unconnected parts.

tunnel diodes [3] (Fig. 37.15). Both resistors have the same current, so we have to add the corresponding voltages v = v1 + v2 and obtain an i – v plot with two unconnected parts. Values of i correspond to 3 values of v1 for R1 and 3 values of v2 for R2, and hence to 9 values of the equivalent resistor [Fig. 37.15(d)]. This illustrates once more that nonlinear circuits may have more solutions than expected at first sight.

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Although the two tunnel diodes R1 and R2 have a canonical PWL representation, the equivalent one port of their series connection has neither a canonical PWL voltage description, nor a current one. It, however, has a GLCP description because KVL, KCL, and the LCP of R1 and R2 constitute a GLCP. If the v-i PWL relation is monotonic, the inverse i-v function exists and then some uniqueness properties hold. These observations are, of course, also valid for the parallel connection of two PWL resistors and for more complicated interconnections. In Section 37.3 we illustrated with an example how a PWL one-port resistor can be realized with linear resistors and ideal diodes. This can be proven in general. One essentially needs a diode for each breakpoint in the PWL characteristic. Conversely, each one port with diodes and resistors is a PWL one port resistor. This brings us to an interesting class of circuits composed of linear resistors, independent sources, linear controlled sources, and ideal diodes. These circuits belong to the general class of circuits with PWL components [see Fig. 37.1(a)] and can be described by GLCP equations. Such networks have not only shown their importance in analysis but also in the topologic study of the number of solutions and more general qualitative properties. When only short-circuit and open-circuit branches are present, one inde­ pendent voltage source with internal resistance and ideal diodes, an interesting loop cut set exclusion property holds that is also called the colored branch theorem or the arc coloring theorem (see Chapter 7.9). It says that the voltage source either forms a conducting loop with forward-oriented diodes and some short circuits or there is a cut set of the voltage source, some open circuits, and blocking diodes. Such arguments have been used to obtain [23] topologic criteria for upper bounds of the number of solutions of PWL resistive circuits. In fact, diode resistor circuits have been used extensively in PWL function generators for analog computers [51]. These electrical analogs can also be used for mathematical pro­ gramming problems (similar to linear programming) and have reappeared in the neural network literature.

37.5 Analysis of Piecewise-Linear Resistive Circuits It is first demonstrated that all conventional network formulation methods (nodal, cut, set, hybrid, modified nodal, and tableau) can be used for PWL resistive circuits where the components are described with canonical or with LCP equations. These network equations may have one or more solutions. In order to find solutions, one can either search through all the polyhedral regions Pk by solving the linear equations for that region or by checking whether its solution is located inside that region Pk . Because many regions often exist, this is a time-consuming method, but several methods can be used to reduce the search [28], [61]. If one is interested in only one solution, one can use solution tracing methods, also called continuation methods or homotopy methods, of which the Katzenelson method is best known. If one is interested in all solutions, the problem is more complicated, but some algorithms exist.

Theorem Canonical PWL (Tableau Analysis) [8] Consider a connected resistive circuit N containing only linear two-terminal resistors, dc independent sources, current-controlled and voltage-controlled piecewise-linear two-terminal resistors, linear- and piecewise-linear-controlled sources (all four types) and any linear multiterminal resistive elements. A composite branch of this circuit is given in Fig. 37.16. If each piecewise-linear function is represented in the canonical form (37.6), then the tableau formulation also has the canonical PWL form f ( x ) = a + Bx +

p

∑c α x − β i

T i

i

=0

(37.43)

i+1

where x = [i T, v T, v Tn ]T and i, respectively v, is the branch current voltage vector (Fig. 37.16) and vn is the node-to-datum voltage vector.

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Îk +

ik + −

ˆ V k

Vk

− Jk

+

−

Ek

FIGURE 37.16 A composite branch.

PROOF. Let A be the reduced incidence matrix of N relative to some datum node, then KCL, KVL, and element constitutive relations give Ai = AJ

(37.44)

v = AT v n + E

(37.45)

f I (i ) + f v (v ) = S

(37.46)

where we can express f1(·) and fv(·) in the canonical form (37.6)

(

)

(

)

f I (i ) = a1 + BI i + C I abs DlT e − e1

f v (v ) = av + Bvv + C vabs DvT v − e v

(37.47) (37.48)

Substituting (37.47) and (37.48) into (37.46), we obtain A  – AJ      –E  + 0    B a I + a v – S     I   abs    

 DI  0  0 

0 DV 0

0 1 Bv 0  0  0

0   AT   0 

i  0    v  = 0    v n  C I   

i  e I      v  − eV      v n  0     

   = 0   

0 0 Cv

0  0  0

(37.49)

Clearly, (37.49) is in the canonical form of (37.43). Of course, an analogous theorem can be given when the PWL resistors are given in LCP form. Then the tableau constitute a GLCP. Moreover, completely in line with the section on circuit analysis (see Chapter 22), one can derive nodal, cut set, loop, hybrid, and modified nodal analysis from the tableau analysis by eliminating certain variables. Alternatively, one can also directly derive these equations. Whatever the description for the PWL components may be, one can always formulate the network equations as linear equations 0 = f ( x ) = ak + Bk x, © 2003 by CRC Press LLC

x ∈Pk

(37.50)

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in the polyhedral region Pk defined by (37.50). The map f is a continuous PWL map. A solution x of (37.50) can then be computed in a finite number of steps with the Katzenelson algorithm [4], [33], by tracing the map f from an initial point (x(1),y(1)) to a value (x*,0) (see Fig. 37.18).

Algorithm STEP 1. Choose an initial point x(1) and determine its polyhedral region P (1), and compute

( )

y (1) = f x (1) = a(1) + B(1) x and set

j=1

STEP 2. Compute

( ) (0 − y ( ) )

xˆ = x ( j ) + B( j )

−1

j

(37.51)

STEP 3. If xˆ ∈P (j ), we have obtained a solution xˆ of f (xˆ ) = 0. Stop. STEP 4. Otherwise, compute

(

x ( j +1) = x ( j ) + λ( j ) xˆ − x ( j )

)

(37.52)

where λ(j) is the largest number such that x ( j+1) ∈ P( j ) , i.e., x ( j+1) is on the boundary between P (j) and P (j+1) (see Fig. 37.17). STEP 5. Identify P (j+1) and the linear map y = a (j+1) + B (j+1) x in the polyhedral region P (j+1) and compute

(

y ( j +1) = y ( j ) + λ( j ) y * − y ( j )

)

(37.53)

Set j = j + 1. Go step 2. f

x-space

y-space 0

x* y(3) x(3)

y(1)

x(2)

x(1)

y(2)

p(3)

p(2)

FIGURE 37.17 The iteration in the Katzenelson algo­ rithm for solving y = f (x) = 0.

p(1)

x2

x1 © 2003 by CRC Press LLC

FIGURE 37.18 Simplicial subdivision.

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This algorithm converges to a solution in a finite number of steps if the determinants of all matrices B (j) have the same sign. This condition is satisfied when the i-v curves for the PWL one port resistors are monotonic. The Katzenelson algorithm was extended in [45] by taking the sign of the determinants into account in (37.52) and (37.53). This requires the PWL resistors to be globally coercive. If by accident in the iteration the point x (j+1) is not on a single boundary and instead is located on a corner, the region P (j+1) is not uniquely defined. However, with a small perturbation [1], one can avoid this corner and still be guaranteed to converge. This algorithm was adapted to the canonical PWL equation (37.49) in [8]. It can also be adapted to the GLCP. However, there exist circuits where this algorithm fails to converge. For the LCP problem, one can then use other algorithms [20], [40], [56]. One can also use other homotopy methods [43], [57], [60], which can be shown to converge based on eventual passivity arguments. In fact, this algorithm extends the rather natural method of source stepping, where the PWL circuit is solved by first making all sources zero and then tracing the solution for increasing (stepping up) the sources. It is instructive to observe here that these methods can be used successfully in another sequence of the steps in Fig. 37.1(a). Until now, we always first performed the horizontal step of PWL approximation or modeling and then the vertical step of network equation formulation. With these methods, one can first perform the network equation formulation and then the PWL approximation. The advantage is that one can use a coarser grid in the simplicial subdivision far away from the solution, and hence dynamically adapt the accuracy of the PWL approximation. In any case, if all solutions are requested, all these homotopy-based methods are not adequate, because not all solutions can be found even if the homotopy method is started with many different x (1). Hence, special methods have been designed. It is beyond the scope of this text to give a complete algorithm [39], [59], but the solution of the GLCP basically involves two parts. First, calculate the solution set of all nonnegative solutions to (37.10) and (37.11). This is a polyhedral cone where extremal rays can be easily determined [44], [54]. Second, this solution set is intersected with a hyperplane and the complementarity condition uTs = 0 implies the elimination of vertices (respectively, convex combinations) where these complementarity (respectively, cross complementarity) is not satisfied. This has allowed to systematically obtain the complete solution set for the circuit of Fig. 37.15 and for circuits with infinitely many solutions. A more recent method [46] covers the PWL i-v characteristic with a union of polyhedra and hierar­ chically solves the circuit with finer and finer polyhedra. An important improvement in efficiency for the methods is possible when the PWL function f(·) is separable, i.e., there exist f i :  → n i = 1, 2, …, n such that f (x ) =

n

∑ f (x ) i

i

(37.54)

i=1

This happens when there are only two terminal PWL resistors, linear resistors, and independent sources, and if the bipolar transistors are modeled by the Ebers–Moll model [see (37.39)]. Then, the subdivision for x is rectangular and each rectangle is subdivided into simplices (see Fig. 37.18). This property can be used to eliminate certain polyhedral regions without solutions [62] and also to speed up the Katzenelson­ type algorithm [60], [62]. If there are MOS transistors, the map f is not separable but one can apply the extended concept of pairwise separable map [62].

37.6 Piecewise-Linear Dynamic Circuits As mentioned at the end of Section 37.2, the piecewise linear descriptions of Section 37.2 can be used also for PWL capacitors, respectively, inductors and memristors, by replacing the port voltages v and currents i by q, v, respectively, ϕ, i and ϕ, q. Whenever we have a network obtained by interconnecting linear and/or PWL resistors, inductors, capacitors, and memristors, we have a dynamic piecewise-linear © 2003 by CRC Press LLC

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1049

circuits. Of course, such networks are often encountered because it includes the networks with linear R, L, C, and linear dependent sources, diodes, switches, op amps, and components such as bipolar and MOS transistors, and GaAs FET’s with PWL resistive models. This includes several important and famous nonlinear circuits such as Chua’s circuit [18], [19], and the cellular neural networks (CNN’s) [48], which are discussed in Chapter 39 and Chapter 40.2. Of course, PWL dynamic circuits are much more interesting and much more complicated and can exhibit a much more complex behavior than resistive circuits and hence this subject is much less explored. It is clear from the definition of a PWL dynamic circuit that it can be described by linear differential equations over polyhedral regions. Hence, it can exhibit many different types of behavior. They may have many equilibria, which can essentially be determined by solving the resistive network (see Section 37.5 and Fig. 37.1) obtained by opening the capacitive ports and short circuiting the inductive ports (dc analysis). When there is no input waveform, the circuit is said to be autonomous and has transients. Some transients may be periodic and are called limit cycles but they may also show chaotic behavior. Next, one may be interested in the behavior of the circuit for certain input waveforms (transient analysis). This can be performed by using integration rules in simulations. For the analysis of limit cycles, chaos, and transients, one can of course use the general methods for nonlinear circuits, but some improvements can be made based on the PWL nature of the nonlinearities. Here, we only describe the methods briefly. If one is interested in the periodic behavior of a PWL dynamic circuit (autonomous or with a periodic input), then one can, for each PWL nonlinearity, make some approximations. First, consider the case that one is only interested in the dc and fundamental sinusoidal contributions in all signals of the form i(t) = A0 + A1 cos ωt. The widely used describing function method [6] for PWL resistors v = f(i) consists of approximating this resistor by an approximate resistor where vˆ(t) = D0 + D1 cos ωt has only the dc and fundamental contribution of v(t). This is often a good approximation since the remainder of the circuit often filters out all higher harmonics anyway. Using a Fourier series, one can then find D0 and D1 as D0 ( A0 , A1 ) =

1 2π

2π

∫ f ( A + A cosφ)dφ

1 D1 ( A0 , A1 ) = πA1

0

1

0

2π

∫ f ( A + A cos φ)dφ 0

1

0

By replacing all PWL components by their describing functions, one can use linear methods to set up the network equations in the Laplace–Fourier domain. When this approximation is not sufficient, one can include more harmonics. Then, one obtains the famous harmonic balance method, because one is balancing more harmonic components. Alternatively, one can calculate the periodic solution by simulating the circuit with a certain initial condition and considering the map F: x0 → x1 from the initial condition x0 to the state x1 one period later. Of course, a fixed point x* = F(x*) of the map corresponds to a periodic solution. It has been demonstrated [27] that the map F is differentiable for PWL circuits. This is very useful in setting up an efficient iterative search for a fixed point of F. This map is also useful in studying the eventual chaotic behavior and is then called the Poincaré return map. In transient analysis of PWL circuits, one is often interested in the sensitivity of the solution to certain parameters in order to optimize the behavior. As a natural extension of the adjoint network for linear circuits in [22], the adjoint PWL circuit is defined and used to determine simple sensitivity calculations for transient analysis. Another important issue is whether the PWL approximation of a nonlinear characteristic in a dynamic circuit has a serious impact on the transient behavior. In [63], error bounds were obtained on the differences of the waveforms. © 2003 by CRC Press LLC

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37.7 Efficient Computer-Aided Analysis of PWL Circuits Transient analysis and timing verification is an essential part of the VLSI system design process. The most reliable way of analyzing the timing performance of a design is to use analog circuit analysis methods. Here as well, a set of algebraic-differential equations has to be solved. This can be done by using implicit integration formulas that convert these equations into a set of algebraic equations, which can be solved by iterative techniques like Newton–Raphson (see Chapter 38). The computation time then becomes excessive for large circuits. It mainly consists of linearizations of the nonlinear component models and the solution of the linear equations. In addition, the design process can be facilitated substantially if this simulation tool can be used at many different levels from the top level of specifications over the logic and switch level to the circuit level. Such a hierarchical simulator can support the design from top to bottom and allow for mixtures of these levels. In limited space, we describe here the main simulation methods for improving the efficiency and supporting the hierarchy of models with piecewise-linear methods. We refer the reader to Chapter 53 for general simulation of VLSI circuits and to the literature for more details on the methods and for more descriptions on complete simulators. It is clear from our previous discussion that PWL models and circuit descriptions can be used at many different levels. An op amp, for example, can be described by the finite gain model [see Fig. 37.9 and (37.29) and (37.30)], but when it is designed with a transistor circuit it can be described by PWL circuit equations as in Section 37.5. Hence, it is attractive to use a simulator that can support this top-down design process [35]. One can then even incorporate logic gates into the PWL models. One can organize the topological equations of the network hierarchically, so that it is easy to change the network topology. The separation between topological equations and model descriptions allows for an efficient updating of the model when moving from one polyhedral region into another. Several other efficiency issues can be built into a hierarchical PWL simulator. An important reduction in computation time needed for solving the network equations can be obtained by using the consistent variation property. In fact, only a rank one difference exists between the matrices of two neighboring polyhedral regions, and hence, one inverse can be easily derived from the other [8], [35]. In the same spirit, one can at the circuit level take advantage of the PWL transistor models (see [62] and separability discussion in Section 34.5). In [53], the circuit is partitioned dynam­ ically into subcircuits during the solution process, depending on the transistor region of operation. Then, the subcircuits are dynamically ordered and solved with block Gauss–Seidel for minimal or no coupling among them. Interesting savings can be obtained [34] by solving the linear differential equations in a polyhedral region with Laplace transformations and by partitioning the equations. However, the computation of the intersection between trajectories in neighboring polyhedral regions can be a disadvantage of this method.

Acknowledgment This work was supported by the Research Council Kuleuven Project MEFISTO666GOA.

References [1] M. J. Chien, “Piecewise-linear homeomorphic resistive networks,” IEEE Trans. Circuits Syst., vol. CAS-24, pp. 118–127, Mar. 1977. [2] M. J. Chien and E. S. Kuh,”Solving nonlinear resistive network using piecewise-linear analysis and simplicial subdivision,” IEEE Trans. Circuits Syst., vol. CAS-24, pp. 305–317, 1977. [3] L. O. Chua, “Analysis and synthesis of multivalued memoryless nonlinear networks,” IEEE Trans. Circuit Theory, vol. CT-14, pp. 192–209, June 1967. [4] L. O. Chua and P. M. Lin, Computer-Aided Analysis of Electronic Circuits: Algorithms and Compu­ tational Techniques, Englewood Cliffs, NJ: Prentice Hall, 1975. © 2003 by CRC Press LLC

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[5] L. O. Chua and P. M. Lin, “A switching-parameter algorithm for finding multiple solutions of nonlinear resistive circuits,” Int. J. Circuit Theory, Appl., vol. 4, pp. 215–239, 1976. [6] L. O. Chua and S. M. Kang, “Section-wise piecewise-linear functions: Canonical representation properties and applications,” Proc. IEEE, vol. 65, pp. 915–929, June 1977. [7] L. O. Chua and D. J. Curtin, “Reciprocal n-port resistor represented by continuous n-dimensional piecewise-linear function realized by circuit with 2-terminal piecewise-linear resistor and p+g port transformer,” IEEE Trans. Circuits Syst., vol. CAS-27, pp. 367–380, May 1980. [8] L. O. Chua and R. L. P. Ying, “Finding all solutions of piecewise-linear circuits,” Int. J. Circuit Theory, Appl., vol. 10, pp. 201–229, 1982. [9] L. O. Chua and R. L. P. Ying, “Canonical piecewise-linear analysis,” IEEE Trans. Circuits Syst., vol. CAS-30, pp. 125–140, 1983. [10] L. O. Chua and A C. Deng, “Canonical piecewise-linear analysis — Part II: Tracing driving-point and transfer characteristics,” IEEE Trans. Circuits Syst., vol. CAS-32, pp. 417–444, May 1985. [11] L. O. Chua and A. C. Deng, “Canonical piecewise-linear modeling, unified parameter optimization algorithm: Application to pn junctions, bipolar transistors, MOSFETs, and GaAs FETs, IEEE Trans. Circuits Syst.,vol. CAS-33, pp. 511–525, May 1986. [12] L. O. Chua and A. C. Deng, “Canonical piecewise linear modeling,” IEEE Trans. Circuits Syst., vol. CAS-33, pp. 511–525, May 1986. [13] L. O. Chua and A. C. Deng, “Canonical piecewise linear analysis: Generalized breakpoint hopping algorithm,” Int. J. Circuit Theory, Appl., vol. 14, pp. 35–52, 1986. [14] L. O. Chua and A. C. Deng, “Canonical piecewise linear representation,” IEEE Trans. Circuits Syst., vol. 35, pp. 101–111, Jan. 1988. [15] L. O. Chua and A. C. Deng, “Canonical piecewise-linear modeling,” ERL Memo. UCB/ERL M85/35, Univ. California, Berkeley, April 26, 1985. [16] L. O. Chua and G. Lin, “Canonical realization of Chaua’s circuit family,” IEEE Trans. Circuits Syst., vol. 37, pp. 885–902, July 1990. [17] L. O. Chua and G. Lin, “Intermittency in piecewise-linear circuit,” IEEE Trans. Circuits Syst., vol. 38, pp. 510–520, May 1991. [18] L. O. Chua, “The genesis of Chua’s circuit,” Archiv Elektronik Übertragungstechnik, vol. 46, no. 4, pp. 250–257, 1992. [19] L. O. Chua, C.-W. Wu, A.-S. Huang, and G.-Q. Zhong, “A Universal circuit for studying and generating chaos,” IEEE Trans. Circuits Syst. I, vol. 40, no. 10, pp. 732–744, 745–761, Oct. 1993. [20] R. Cottle, J.-S. Pang, and R. Stone, The Linear Complementarity Problem, New York: Academic Press, 1992. [21] A. C. Deng, “Piecewise-linear timing model for digital CMOS circuits,” IEEE Trans. Circuits Syst., vol. 35, pp. 1330–1334, Oct. 1988. [22] Y. Elcherif and P. Lin, “Transient analysis and sensitivity computation in piecewise-linear circuits,” IEEE Trans. Circuits Syst., vol. 36, pp. 1525–1533, Dec. 1988. [23] M. Fossepréz, M. J. Hasler, and C. Schnetzler, “On the number of solutions of piecewise-linear resistive circuits,” IEEE Trans. Circuits Syst., vol. 36, pp. 393–402, March 1989. [24] T. Fujisawa, E. S. Kuh, “Piecewise-linear theory of nonlinear networks,” SIAM J. Appl. Math., vol. 22, no. 2, pp. 307–328, March 1972. [25] T. Fujisawa, E. S. Kuh, and T. Ohtsuki, “A sparse matrix method for analysis of piecewise-linear resistive circuits,” IEEE Trans. Circuit Theory, vol.19, pp. 571–584, Nov. 1972. [26] G. Güzelis and I. Göknar, “A canonical representation for piecewise affine maps and its applications to circuit analysis,” IEEE Trans. Circuits Syst., vol. 38, pp. 1342–1354, Nov. 1991. [27] I. N. Hajj and S. Skelboe, “Dynamic systems: Steady-state analysis,” IEEE Trans. Circuits Syst., vol. CAS-28, pp. 234–242, March 1981. [28] Q. Huang and R. W. Liu, “A simple algorithm for finding all solutions of piecewise-linear networks,” IEEE Trans. Circuits Syst., vol. 36, pp. 600–609, April 1989.

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[29] C. Kahlert and L. O. Chua, “A generalized canonical piecewise-linear representation,” IEEE Trans. Circuits Syst., vol. 37, pp. 373–383, March 1990. [30] C. Kahlert and L. O. Chua, “Completed canonical piecewise-linear representation: Geometry of domain space,” IEEE Trans. Circuits Syst., vol. 39, pp. 222–236, March 1992. [31] S. M. Kang and L. O. Chua, “A global representation of multidimensional piecewise-linear functions with linear partitions,” IEEE Trans. Circuits Syst., vol. CAS-25, pp. 938–940, Nov. 1978. [32] S. Karamardian, “The complementarity problem,” Mathemat. Program., vol. 2, pp. 107–129, 1972. [33] S. Karamardian and J. Katzenelson, “An algorithm for solving nonlinear resistive networks,” Bell Syst. Tech. J., vol. 44, pp. 1605–1620, 1965. [34] R. J. Kaye and A. Sangiovanni-Vincentelli, “Solution of piecewise-linear ordinary differential equa­ tions using waveform relaxation and Laplace transforms,” IEEE Trans. Circuits Syst., vol. CAS-30, pp. 353–357, June 1983. [35] T. A. M. Kevenaar and D. M. W. Leenaerts, “A flexible hierarchical piecewise-linear simulator,” Integrat., VLSI J., vol. 12, pp. 211–235, 1991. [36] T. A. M. Kevenaar and D. M. W. Leenaerts, “A comparison of piecewise-linear model descriptions,” IEEE Trans. Circuits Syst., vol. 39, pp. 996–1004, Dec. 1992. [37] M. Kojima and Y. Yamamoto, “Variable dimension algorithms: Basic theory, interpretations and extensions of some existing methods,” Mathemat. Program., vol. 24, pp. 177–215, 1982. [38] S. Lee and K. Chao, “Multiple solution of piecewise-linear resistive networks,” IEEE Trans. Circuits Syst., vol. CAS-30, pp. 84–89, Feb. 1983. [39] D. M. W. Leenaerts and J. A. Hegt, “Finding all solutions of piecewise-linear functions and the application to circuits design,” Int. J. Circuit Theory, Appl., vol. 19, pp. 107–123, 1991. [40] C. E. Lemke, “On complementary pivot theory,” in Nonlinear Programming, J. B. Rosen, O. L. Mangasarian, and K. Ritten, Eds., New York: Academic Press, 1968, pp. 349–384. [41] J. Lin and R. Unbehauen, “Canonical piecewise-linear approximations,” IEEE Trans. Circuits Syst., vol. 39, pp. 697–699, Aug. 1992. [42] R. Lum and L. O. Chua, “Generic properties of continuous piecewise-linear vector fields in 2-D space,” IEEE Trans. Circuits Syst., vol. 38, pp. 1043–1066, Sep. 1991. [43] R. Melville, L. Trajkovic, S.-C. Fang, and L. Watson, “Artificial homotopy methods for the DC operating point problem,” IEEE Trans Comput.-Aided Design Integrat. Circuits Syst., vol. 12, pp. 861–877, June 1993. [44] T. S. Motzkin, H. Raiffa, G. L. Thompson, and R. M. Thrall, “The double description method,” in Contributions to the Theory of Games, Ann. Mathemat. Studies, H.W. Kuhn and A.W. Tucker, Eds., Princeton: Princeton Univ. Press, 1953, pp. 51–73. [45] T. Ohtsuki, T. Fujisawa, and S. Kumagai, “Existence theorem and a solution algorithm for piecewiselinear resistor circuits,” SIAM J. Math. Anal., vol. 8, no. 1, pp. 69–99, 1977. [46] S. Pastore and A. Premoli, “Polyhedral elements: A new algorithm for capturing all the equilibrium points of piecewise-linear circuits,” IEEE Trans. Circuits Syst. I., vol. 40, pp. 124–132, Feb. 1993. [47] V. C. Prasad and V. P. Prakash, “Homeomorphic piecewise-linear resistive networks,” IEEE Trans. Circuits Syst., vol. 35, pp. 251–253, Feb. 1988. [48] T. Roska and J. Vandewalle, Cellular Neural Networks, New York: John Wiley & Sons, 1993. [49] I. W. Sandberg, “A note on the operating-point equations of semiconductor-device networks,” IEEE Trans. Circuits Syst., vol. 37, p. 966, July 1990. [50] A. S. Solodovnikov, System of Linear Inequalities, translated by L. M. Glasser and T. P. Branson, Chicago: Univ. Chicago, 1980. [51] T. E. Stern, Theory of Nonlinear Networks and Systems: An Introduction, Reading, MA: AddisonWesley, 1965. [52] S. Stevens and P.-M. Lin, “Analysis of piecewise-linear resistive networks using complementary pivot theory,” IEEE Trans Circuits Syst., Vol. CAS-28, pp. 429–441, May 1981. [53] O. Tejayadi and I. N. Hajj, “Dynamic partitioning method for piecewise-linear VLSI circuit simu­ lation,” Int. J. Circuit Theory, Appl., vol. 16, pp. 457–472,1988. © 2003 by CRC Press LLC

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[54] S. N. Tschernikow, Lineare Ungleichungen. Berlin: VEB Deutscher Verlag der Wissenschaften, 1971; translation from H. Weinert and H. Hollatz, Lineinye Neravenstva, 1968, into German. [55] W. M. G. van Bokhoven, Piecewise-Linear Modelling and Analysis. Deventer: Kluwer Academic, 1980. [56] C. Van de Panne, “A complementary variant of Lemke’s method for the linear complementary problem,” Mathemat. Program., vol. 7, pp. 283–310, 1974. [57] L. Vandenberghe and J. Vandewalle, “Variable dimension algorithms for solving resistive circuits,” Int. J. Circuit Theory Appl., vol. 18, pp. 443–474, 1990. [58] L. Vandenberghe and J. Vandewalle, “A continuous deformation algorithm for DC-analysis of active nonlinear circuits,” J. Circuits, Syst., Comput., vol. 1, pp. 327–351, 1991. [59] L. Vandenberghe, B. L. De Moor, and J. Vandewalle, “The generalized linear complementarity problem applied to the complete analysis of resistive piecewise-linear circuits,” IEEE Trans. Circuits Syst., vol. 36, pp. 1382–1391, 1989. [60] K. Yamamura and K. Horiuchi, “A globally and quadratically convergent algorithm for solving resistive nonlinear resistive networks,” IEEE Trans. Computer-Aided Design Integrat. Circuits Syst., vol. 9, pp. 487–499, May 1990. [61] K. Yamamura and M. Ochiai, “Efficient algorithm for finding all solutions of piecewise-linear resistive circuits,” IEEE Trans. Circuits Syst., vol. 39, pp. 213–221, March 1992. [62] K. Yamamura, “Piecewise-linear approximation of nonlinear mappings containing Gummel-Poon models or Shichman-Hodges models,” IEEE Trans. Circuits Syst., vol. 39, pp. 694–697, Aug. 1992. [63] M. E. Zaghloul and P. R. Bryant, “Nonlinear network elements: Error bounds,” IEEE Trans. Circuits Syst., vol. CAS-27, pp. 20–29, Jan. 1980.

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38 Simulation

Erik Lindberg Technical University of Denmark

38.1 Numerical Solution of Nonlinear Algebraic Equations 38.2 Numerical Integration of Nonlinear Differential Equations 38.3 Use of Simulation Programs SPICE • APLAC • NAP2 • ESACAP • DYNAST

This chapter deals with the simulation or analysis of a nonlinear electrical circuit by means of a computer program. The program creates and solves the differential-algebraic equations of a model of the circuit. The basic tools in the solution process are linearization, difference approximation, and the solution of a set of linear equations. The output of the analysis may consist of (1) all node and branch voltages and all branch currents of a bias point (dc analysis); (2) a linear small-signal model of a bias point that may be used for analysis in the frequency domain (ac analysis); or (3) all voltages and currents as functions of time in a certain time range for a certain excitation (transient analysis). A model is satisfactory if there is good agreement between measurements and simulation results. In this case, simulation may be used instead of measurement for obtaining a better understanding of the nature and abilities of the circuit. The crucial point is to set up a model that is as simple as possible, in order to obtain a fast and inexpensive simulation, but sufficiently detailed to give the proper answer to the questions concerning the behavior of the circuit under study. Modeling is the bottleneck of simulation. The model is an equivalent scheme — “schematics-capture” — or a branch table — “net-list” — describing the basic components (n-terminal elements) of the circuit and their connection. It is always possible to model an n-terminal element by means of a number of 2-terminals (branches). These internal 2-terminals may be coupled. By pairing the terminals of an n-terminal element, a port description may be obtained. The branches are either admittance branches or impedance branches. All branches may be interpreted as controlled sources. An admittance branch is a current source primarily controlled by its own voltage or primarily controlled by the voltage or current of another branch (transadmittance). An imped­ ance branch is a voltage source primarily controlled by its own current or primarily controlled by the current or voltage of another branch (transimpedance). Control by signal (voltage or current) and control by time-derivative of signal is allowed. Control by several variables is allowed. Examples of admittance branches are (1) the conductor is a current source controlled by its own voltage; (2) the capacitor is a current source sontrolled by the time-derivative of its own voltage; and (3) the open circuit is a zero-valued current source (a conductor with value zero). Examples of impedance branches are (1) the resistor is a voltage source controlled by its own current; (2) the inductor is a voltage source controlled by the time-derivative of its own current; and (3) the short circuit is a zero-valued voltage source (a resistor with value zero) A component may often be modeled in different ways. A diode, for example, is normally modeled as a current source controlled by its own voltage such that the model can be linearized into a dynamic conductor in parallel with a current source during the iterative process of finding the bias point of the diode. The diode may also be modeled as (1) a voltage source controlled by its own current (a dynamic resistor in series with a voltage source); (2) a static conductor being a function of the voltage across the

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diode; or (3) a static resistor being a function of the current through the diode. Note that in the case where a small signal model is wanted, for frequency analysis, only the dynamic model is appropriate. The primary variables of the model are the currents of the impedance branches and the node potentials. The current law of Kirchhoff (the sum of all the currents leaving a node is zero) and the current-voltage relations of the impedance branches are used for the creation of the equations describing the relations between the primary variables of the model. The contributions to the equations from the branches are taken one branch at a time based on the question: will this branch add new primary variables? If yes, then a new column (variables) and a new row (equations) must be created and updated, or else the columns and rows corresponding to the existing primary variables of the branch must be updated. This approach to equation formulation is called the extended nodal approach or the modified nodal approach (MNA). In the following, some algorithms for solving a set of nonlinear algebraic equations and nonlinear differential equations are briefly described. Because we are dealing with physical systems and because we are responsible for the models, we assume that at least one solution is possible. The zero solution is, of course, always a solution. It might happen that our models become invalid if we, for example, increase the amplitudes of the exciting signals, diminish the risetime of the exciting signals, or by mistake create unstable models. It is important to define the range of validity for our models. What are the consequences of our assumptions? Can we believe in our models?

38.1 Numerical Solution of Nonlinear Algebraic Equations Let the equation system to be solved be f(x,u) = 0, where x is the vector of primary variables and u is the the excitation vector. Denote the solution by xs. Then, if we define a new function g(x) = α(f(x,u)) + x, where α may be some function of f(x,u), which is zero for f(x,u) = 0, then we can define an iterative scheme where g(x) converges to the solution xs by means of the iteration: xk+1 = g(xk) = α(f(xk ,u)) + xk where k is the iteration counter. If for all x in the interval [xa , xb ] the condition g(xa) – g(xb) ≤ L ∗ xa – xb  for some L < 1 is satisfied, the iteration is called a contraction mapping. The condition is called a Lipschitz condition. Note that a function is a contraction if it has a derivative less than 1. For α = –1, the iterative formula becomes: xk+1 = g(xk) = –f(xk ,u) + xk . This scheme is called the Picard method, the functional method, or the contraction mapping algorithm. At each step, each nonlinear component is replaced by a linear static component corresponding to the solution xk . A nonlinear conductor, for example, is replaced by a linear conductor defined by the straight line through the origin and the solution point. Each iterative solution is calculated by solving a set of linear equations. All components are updated and the next iteration is made. When two consecutive solutions are within a prescribed tolerance, the solution point is accepted. For α = –1/(df/dx), the iterative formula becomes: xk+1 = g(xk) = –f(xk ,u)/(df(xk ,u)/dx) + xk . This scheme is called the Newton–Raphson method or the derivative method. At each step, each nonlinear component is replaced by a linear dynamic component plus an independent source corresponding to the solution xk. A nonlinear conductor, for example, is replaced by a linear conductor defined by the derivative of the branch current with respect to the branch voltage (the slope of the nonlinearity) in parallel with a current source corresponding to the branch voltage of the previous solution. A new solution is then caculated by solving a set of linear equations. The components are updated and the next iteration is made. When the solutions converge within a prescribed tolerance, the solution point is accepted. It may, of course, happen that the previously mentioned iterative schemes do not converge before the iteration limit kmax is reached. One reason may be that the nonlinearity f(x) changes very rapidly for a small change in x. Another reason could be that f(x) possess some kind of symmetry that causes cycles in the Newton–Raphson iteration scheme. If convergence problems are detected, the iteration scheme can be modified by introducing a limiting of the actual step size. Another approach may be to change the modeling of the nonlinear branches from voltage control to current control or vice versa. Often, the user of a circuit analysis program may be able to solve convergence problems by means of proper modeling and adjustment of the program options [1, 2, 3, 8, 11]. © 2003 by CRC Press LLC

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38.2 Numerical Integration of Nonlinear Differential Equations The dynamics of a nonlinear electronic circuit may be described by a set of coupled first order differential equations–algebraic equations of the form: dx/dt = f(x, y, t) and g(x, y, t) = 0, where x is the vector of primary variables (node potentials and impedance branch currents), y is the vector of variables that cannot be explicitly eliminated, and f and g are nonlinear vector functions. It is always possible to express y as a function of x and t by inverting the function g and inserting it into the differential equations such that the general differential equation form dx/dt = f(x, t) is obtained. The task is then to obtain a solution x(t) when an initial value of x is given. The usual methods for solving differential equations reduce to the solution of difference equations, with either the derivatives or the integrals expressed approximately in terms of finite differences. Assume, at a given time t0, we have a known solution point x0 = x(t0). At this point, the function f can be expanded in Taylor series: dx/dt = f(x0, t) + A(x0)(x – x0) + … where A(x0) is the Jacobian of f evaluated at x0. Truncating the series, we obtain a linearization of the equations such that the small-signal behavior of the circuit in the neighborhood of x0 is described by dx/dt = A ∗ x + k, where A is a constant matrix equal to the Jacobian and k is a constant vector. The most simple scheme for the approximate solution of the differential equation dx/dt = f(x, t) = Ax + k is the forward Euler formula x(t) = x(t0) + hA(t0) where h = t – t0 is the integration time step. From the actual solution point at time t0, the next solution point at time t is found along the tangent of the solution curve. It is obvious that we will rapidly leave the vicinity of the exact solution curve if the integration step is too large. To guarantee stability of the computation, the time step h must be smaller than 2/λ where λ is the largest eigenvalue of the Jacobian A. Typically, h must not exceed 0.2/λ. The forward Euler formula is a linear explicit formula based on forward Taylor expansion from t0. If we make backward Taylor expansion from t we arrive at the backward Euler formula: x(t) = x(t0) + hA(t). Because the unknown appears on both sides of the equation, it must in general be found by iteration so the formula is a linear implicit formula. From a stability point of view, the backward Euler formula has a much larger stability region than the forward Euler formula. The truncation error for the Euler formulas is of order h2. The two Euler formulas can be thought of as polynomials of degree one that approximate x(t) in the interval [t0, t]. If we compute x(t) from a second-order polynomial p(t) that matches the conditions that p(t0) = x(t0), dp/dt(t0) = dx/dt(t0) and dp/dt(t) = dx/dt(t), we arrive at the trapezoidal rule: x(t) = x(t0) + 0.5hA(t0) + 0.5hA(t). In this case, the truncation error is of order h3. At each integration step, the size of the local truncation error can be estimated. If it is too large, the step size must be reduced. An explicit formula such as the forward Euler may be used as a predictor giving a starting point for an implicit formula like the trapezoidal, which in turn is used as a corrector. The use of a predictor-corrector pair provides the base for the estimate of the local truncation error. The trapezoidal formula with varying integration step size is the main formula used in the SPICE program. The two Euler formulas and the trapezoidal formula are special cases of a general linear multistep formula Σ(aixn–i + bi h(dx/dt)n–i), where i goes from –1 to m – 1 and m is the degree of the polynomial used for the approximation of the solution curve. The trapezoidal rule, for example, is obtained by setting a–1 = –1, a0 = +1 and b–1 = b0 = 0.5, all other coefficients being zero. The formula can be regarded as being derived from a polynomial of degree r which matches r + 1 of the solution points xn-i and their derivatives (dx/dt)n–i . Very fast transients often occur together with very slow transients in electronic circuits. We observe widely different time constants. The large spread in component values, for example, from large decoupling capacitors to small parasitic capacitors, implies a large spread in the modules of the eigenvalues. We say that the circuits are stiff. A family of implicit multistep methods suitable for stiff differential equations has been proposed by C.W. Gear. The methods are stable up to the polynomial of order 6. For example, the second-order Gear formula for fixed integration step size h may be stated as: xn+1 = –(1/3)xn–1 + (4/3)xn + (2/3)h(dx/dt)n+1. By changing both the order of the approximating polynomial and the integration step size, the methods adapt themselves dynamically to the performance of the solution curve. The family of Gear formulas is © 2003 by CRC Press LLC

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modified into a “stiff-stable variable-order variable-step predictor-corrector” method based on implicit approximation by means of backward difference formulas (BDFs). The resulting set of nonlinear equa­ tions is solved by modified Newton–Raphson iteration. Note that numerical integration, in a sense, is a kind of low-pass filtering defined by means of the minimum integration step [1, 2, 3, 8, 11].

38.3 Use of Simulation Programs Since 1960, a large number of circuit-simulation programs have been developed by universities, industrial companies, and commercial software companies. In particular, the SPICE program has become a standard simulator both in the industry and in academia. Here, only a few programs, which together cover a very large number of simulation possibilities, are presented. Due to competition, there is a tendency to develop programs that are supposed to cover any kind of analysis so that only one program should be sufficient (“the Swiss Army Knife Approach”). Unfortunately this implies that the programs become very large and complex to use. Also, it may be difficult to judge the correctness and accuracy of the results of the simulation having only one program at your disposal. If you try to make the same analysis of the same model with different programs, you will frequently see that the results from the programs may not agree completely. By comparing the results, you may obtain a better feel for the correctness and accuracy of the simulation. The programs SPICE and APLAC supplemented with the programs NAP2, ESACAP, and DYNAST have proven to be a good choice in the case where a large number of different kinds of circuits and systems are to be modeled and simulated (“the Tool Box Approach”). The programs are available in inexpensive evaluation versions running on IBM compatible personal computers. The “net-list” input languages are very close, making it possible to transfer input data easily between the programs. In order to make the programs more “user-friendly” graphics interphase language “schematics-capture,” where you draw the circuit on the screen, has been introduced. Unfortunately, this approach makes it a little more difficult for the user to transfer data between the programs. In the following, short descriptions of the programs are given and a small circuit is simulated in order to give the reader an idea of the capabilities of the programs.

SPICE The first versions of SPICE (Simulation Program with Integrated Circuit Emphasis version 2), based on the modified nodal approach, were developed in 1975 at the Electronics Research Laboratory, College of Engineeering, University of California, Berkeley, CA. SPICE is a general-purpose circuit analysis program. Circuit models may contain resistors, capacitors, inductors, mutual inductors, independent sources, controlled sources, transmission lines, and the most common semiconductor devices: diodes, bipolar junction transistors, and field effect transistors. SPICE has very detailed built-in models for the semiconductor devices, which may be described by about 50 parameters. Besides the normal dc, ac, and transient analyses, the program can make sensitivity, noise, and distorsion analysis and analysis at different temperatures. In the various commercial versions of the program many other possibilities have been added; for example, analog behavior modeling (poles and zeros) and statistical analysis. In order to give an impression of the “net-list” input language, the syntax of the statements describing controlled sources is the following: Voltage Voltage Current Current

Controlled Controlled Controlled Controlled

Current Voltage Current Voltage

Source: Source: Source: Source:

Gxxx Exxx Fxxx Hxxx

N+ N+ N+ N+

NNNN-

NC+ NC- VALUE

NC+ NC- VALUE

VNAM VALUE

VNAM VALUE

where the initial characters of the branch name G, E, F, and H indicate the type of the branch, N+ and N– are integers (“node numbers”) indicating the placement and orientation of the branch, respectively, NC+ NC– and VNAM indicate from where the control comes (VNAM is a dummy dc voltage source © 2003 by CRC Press LLC

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with value 0 inserted as an ammeter!), and VALUE specifies the numerical value of the control, which may be a constant or a polynomial expression in case of nonlinear dependent sources. Independent sources are specified with Ixxx for current and Vxxx for voltage sources. The following input file describes an analysis of the Chua oscillator circuit. It is a simple harmonic oscillator with losses (C2, L2, and RL2) loaded with a linear resistor (R61) in series with a capacitor (C1) in parallel with a nonlinear resistor. The circuit is influenced by a sinusoidal voltage source VRS through a coil L1. Comments may be specified either as lines starting with an asterisk “*” or by means of a semicolon “;” after the statement on a line. A statement may continue by means of a plus “+” as the first character on the following line. PSpice input file CRC-CHUA.CIR, first line, title line * *: The Chua Oscillator, sinusoidal excitation, F=150mV > * : RL2=1 ohm, RL1=0 ohm f=1286.336389 Hz * : ref. K. Murali and M. Lakshmanan, * : Effect of Sinusoidal Excitation on the Chua’s Circuit, * : IEEE Transactions on Circuits and Systems — 1: * : Fundamental Theory and Applications, * : vol.39, No.4, April 1992, pp. 264-270 * : input source; : - - - - - - - - - - - - - - - - - - - - - - VRS 7 0 sin(0 150m 1.2863363889332e+3 0 0) * : choke L1 6 17 80e-3 ; mH VRL1 17 7 DC 0 ; ammeter for measure of IL1 * : harmonic oscillator; : - - - - - - - - - - - - - - - - - - L2 6 16 13m RL2 16 0 1 C2 6 0 1.250u * : load; : - - - - - - - - - - - - - - - - - - - - - - - - - - r61 6 10 1310 vrrC1 10 11 DC 0 C1 11 0 0.017u * i(vrr10)=current of nonlinear resistor vrr10 10 1 DC 0 * : non-linear circuit; : - - - - - - - - - - - - - - - - - - - .model n4148 d (is=0.1p rs=16 n=1); vt=n*k*T/q d13 1 3 n4148 d21 2 1 n4148 rm9 2 22 47k vrm9 22 0 DC -9 ; negative power supply rp9 3 33 47k vrp9 33 0 DC +9 r20 2 0 3.3k r30 3 0 3.3k * : ideal op. amp.; :- - - - - - - - - - - - - - - - - - - - - evop 4 0 1 5 1e+20 r14 1 4 290 r54 5 4 290 r50 5 0 1.2k * : - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .TRAN 0.05m 200m 0 0.018m UIC .plot tran v(11) © 2003 by CRC Press LLC

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The Circuits and Filters Handbook, Second Edition .probe .options acct nopage opts gmin=1e-15 reltol=1e-3 abstol=1e-12 vntol=1e-12 tnom=25 itl5=0 limpts=15000 .end

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The analysis is controlled by means of the statements: .TRAN, where, for example, the maximum integration step is fixed to 18 µ sec, and .OPTIONS, where, for example, the relative truncation error is set to 1e-3. The result of the analysis is presented in Fig. 38.1. It is seen that transition from chaotic behavior to a period 5 limit cycle takes place at about 100 m sec. A very important observation is that the result of the analysis may depend on: (1) the choice of the control parameters; and (2) the order of the branches in the “net-list,” for example, if the truncation error is set to 1e-6 instead of 1e-3 previously, the result becomes quite different. This observation is valid for all programs [4–7, 9–11].

APLAC The program APLAC (originally Analysis Program for Linear Active Circuits) [11] has been under constant development at the Helsinki University of Technology, Finland, since 1972. Over time it has developed into an object-oriented analog circuits and systems simulation and design tool. Inclusion of a new model into APLAC requires only the labor of introducing the parameters and equations defining the model under the control of “C-macros.” The code of APLAC itself remains untouched. The APLAC Interpreter immediately understands the syntax of the new model. APLAC accepts SPICE “net-lists” by means of the program Spi2a (SPICE to APLAC netlist converter). APLAC is capable of carrying out dc, ac, transient, noise, oscillator, and multitone harmonic steadystate analyses and measurements using IEEE-488 bus. Transient analysis correctly handles, through convolution, components defined by frequency-dependent characteristics. Monte Carlo analysis is avail­ able in all basic analysis modes and sensitivity analysis in dc and ac modes. N-port z, y, and s parameters, as well as two-port h parameters, are available in ac analysis. In addition, APLAC includes a versatile collection of system level blocks for the simulation and design of analog and digital communication systems. APLAC includes seven different optimization methods. Any parameter in the design problem can be used as a variable, and any user-defined function may act as an objective. Combined time and frequency domain optimization is possible. The file below is the APLAC “net-list” of the Chua oscillator circuit created by the Spi2a converter program with the PSpice file CRC-CHUA.CIR above as input. Comments are indicated by means of the dollar sign $ or the asterisk *. Unfortunately, it is necessary to manually change the file. Comments semicolon “;” and colon “:” must be replaced with “$;” and “$:”. Also, Spi2a indicates a few statements as “$ not implemented.” $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$

$$ $$ Spi2a — SPICE to APLAC netlist converter, version 1.26 $$ $$ This file is created at Tue Jul 17 14:48:02 2001 $$

$$ with command: spi2a C:\WINDOWS\DESKTOP\crc-chua.cir $$

$$ $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$

$$

$$

$$

$$

$PSpice input file CRC-CHUA.CIR, first line, title line

$:

Prepare gmin=1e-15 ERR=1e-3 ABS_ERR=1e-12 TNOM=(273.15+(25))

$ .options acct nopage opts gmin=1e-15 reltol=1e-3 $+ abstol=1e-12 vntol=1e-12 tnom=25 itl5=0

$:

$:

© 2003 by CRC Press LLC

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200uA

0A

–200uA

0s

40ms

80ms

120ms

160ms

200ms

I (C1) Time

200uA

0A

–200uA

–1.99V

–1.00V

0V

1.00V

2.00V

I (C1) v(11)

FIGURE 38.1 (a) PSPICE analysis. The current of C1: I(C1) as function of time in the interval 0 200 ms. (b) The current of C1: I(C1) as function of the voltage of C1: V(11). (c) The current of C1: I(C1) as function of the voltage of C1: V(11) in the time interval 100 to 200 ms. (d) The voltage of C2: V(6) as function of the voltage of C1: V(11) in the time interval 100 to 200 ms.

$+ limpts=15000 $ .MODEL and .PARAM definitions Model “n4148” is=0.1p rs=16 n=1

+ $;=vt n*k*T/q $ Circuit definition $ Not implemented $ VRS 7 0 sin(0 150m 1.2863363889332e+3 0 0) © 2003 by CRC Press LLC

$:

$:

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$:

$:

$:

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200uA

0A

–200uA

–1.99V

–1.00V

0V

1.00V

2.00V

1.00V

2.00V

I (C1) v(11) 400mV

0V

–400mV –1.99V

–1.00V

0V

V (6) v(11)

FIGURE 38.1 (continued).

Volt VRS 7 0 sin=[0, 150m, 1.2863363889332e+3, 0, 0]

* $: choke $:

Ind L1 6 17 80e-3 $; mH $:

Volt VRL1 17 7 DC={VRL1=0} $ $; ammeter for measure of IL1 $:

* $: harmonic oscillator$; $: - - - - - - - - - - - - - - - - - - - - - - - $:

+ I=I_VRL1

Ind L2 6 16 13m $:

Res RL2 16 0 1 $:

Cap C2 6 0 1.250u $:

Res r61 6 10 1310 $:

© 2003 by CRC Press LLC

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1063

$ Not implemented $:

$ vrrC1 10 11 DC 0 $:

Volt vrrC1 10 11 DC={vrrC1=0}

+ I=IC1

Cap C1 11 0 0.017u $:

$ Not implemented $:

$ vrr10 10 1 DC 0 $:

Volt vrr10 10 1 DC={vrr10=0}

+ I=IRNL

* $: non-linear circuit$; $:- - - - - - - - - - - - - - - - - - - - - - - - $:

Diode d13 1 3 MODEL=“n4148” $:

Diode d21 2 1 MODEL=“n4148” $:

Res rm9 2 22 47k $:

Volt vrm9 22 0 DC={vrm9=-9} $ $; negative power supply $:

+ I=I_vrm9

Res rp9 3 33 47k $:

$ Not implemented $:

$ vrp9 33 0 DC +9 $:

Volt vrp9 33 0 DC={vrp9=9} $ +9 must be 9

Res r20 2 0 3.3k $:

Res r30 3 0 3.3k $:

VCVS evop 4 0 1 1 5 [1e+20] LINEAR $:

Res r14 1 4 290 $:

Res r54 5 4 290 $:

Res r50 5 0 1.2k $:

$$ Analysis commands $$ .TRAN 0.05m 200m 0 0.018m UIC $ Sweep “TRAN Analysis 1”

$+ LOOP (1+(200m-(0))/(0.05m)) TIME LIN 0 200m TMAX=0.018m

$+ NW=1 $ UIC $$ .plot tran v(11) $ Show Y Vtran(11) $ $ EndSweep

$ the following lines are added and the sweep above is commented

Sweep “TRAN Analysis 2”

+ LOOP (4001) TIME LIN 0 200m TMAX=0.018m

$+ NW=1 $ UIC $ .plot tran v(11) Show Y Itran(IC1) X Vtran(11) $ EndSweep

$.probe

$:

$:

$:

$:

$:

$:

$:

$:

$:

The result of the analysis is presented in Fig. 38.2. It is observed that limit cycle behavior is not obtained in the APLAC analysis in the time interval from 0 to 200 ms.

NAP2 The first versions of NAP2 (Nonlinear Analysis Program version 2) [9], based on the extended nodal equation formulation were developed in 1973 at the Institute of Circuit Theory and Telecommunication, Technical University of Denmark, Lyngby, Denmark. © 2003 by CRC Press LLC

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TRAN Analysis 1 Aplac 7.60 Student version FOR NON-COMMERICAL USE ONLY 2.00

1.00

0.00

–1.00

–2.00 0.000

0.050

0.100 t/s

0.150

0.200

Vtran (11)

TRAN Analysis 2 Aplac 7.60 Student version FOR NON-COMMERICAL USE ONLY 250.00u

125.00u

0.00

–125.00u

–250.00u –2.000

–1.000

0.000

1.000

2.000

t/s Itran (IC1)

FIGURE 38.2 (a) The voltage of C1: V(11) as function of time in the interval 0 to 200 ms. (b) The current of C1: IC1 as function of the voltage of C1: V(11).

NAP2 is a general-purpose circuit analysis program. Circuit models may contain resistors, conductors, capacitors, inductors, mutual inductors, ideal operational amplifiers, independent sources, controlled sources, and the most common semiconductor devices: diodes, bipolar junction transistors, and field © 2003 by CRC Press LLC

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effect transistors. NAP2 has only simple built-in models for the semiconductor devices, which require about 15 parameters. Besides the normal dc, ac, and transient analyses, the program can make parameter variation analysis. Any parameter (e.g., component value or temperature) may be varied over a range in an arbitrary way and dc, ac, or transient analysis may be performed for each value of the parameter. Optimization of dc bias point (“given: voltages, find: resistors”) is possible. Event detection is included so that it is possible to interrupt the analysis when a certain signal, for example, goes from a positive to a negative value. The results may be combined into one output plot. It is also possible to calculate the poles and zeros of driving point and transfer functions for the linearized model in a certain bias point. Eigenvalue technique (based on the QR algorithm by J. G. F. Francis) is the method behind the calculation of poles and zeros. Group delay (i.e., the derivative of the phase with respect to the angular frequency) is calculated from the poles and zeros. This part of the program is available as an independent program named ANP3 (Analytical Network Program version 3). In order to give an impression of the “net-list” input language, the syntax of the statements describing controlled sources is as follows: Voltage Voltage Current Current

Controlled Controlled Controlled Controlled

Current Voltage Current Voltage

Source: Source: Source: Source:

Ixxx Vxxx Ixxx Vxxx

N+ N+ N+ N+

NNNN-

VALUE VALUE VALUE VALUE

VByyy

VByyy

IByyy

Ibyyy

where the initial characters of the branch name I and V indicate the type of the branch, N+ and N- are integers (“node numbers”) indicating the placement and orientation of the branch, respectively, and VALUE specifies the numerical value of the control, which may be a constant or an arbitrary functional expression in case of nonlinear control. IB and VB refer to the current or voltage of the branch, respec­ tively, from where the control comes. If the control is the time derivative of the branch signal, SI or SV may be specified. Independent sources must be connected to a resistor R or a conductor G as follows: Rxxx N+ N- VALUE E = VALUE and Gxxx N+ N- VALUE J = VALUE, where VALUE may be any function of time, temperature, and components. The input file “net-list” below describes the same analysis of the Chua oscillator circuit as performed by means of SPICE and APLAC. The circuit is a simple harmonic oscillator with losses (C2, L2 and RL2) loaded with a linear resistor (R61) in series with a capacitor (C1) in parallel with a nonlinear resistor. The circuit is excitated by a sinusoidal voltage source through a coil L1. The frequency is specified as angular frequency in rps. It is possible to specify more than one statement on one line. Colon “:” indicate start of a comment statement and semicolon “;” indicates end of a statement. The greater than character “>” indicates continuation of a statement on the following line. It is observed that most of the lines are comment lines with the PSPICE input statements. *circuit; *list 2, 9; : file CRC-CHUA.NAP

*: PSpice input file CRC-CHUA.CIR, first line, title line > :

: translated into NAP2 input file

: The Chua Oscillator, sinusoidal excitation, F=150mV > :

: RL2=1 ohm, RL1=0 ohm f=1286.336389 Hz :

: ref. K. Murali and M. Lakshmanan, :

: Effect of Sinusoidal Excitation on the Chua’s Circuit, :

: IEEE Transactions on Circuits and Systems — 1: :

: Fundamental Theory and Applications, :

: vol.39, No.4, April 1992, pp. 264-270 :

: input source; : - - - - - - - - - - - - - - - - - - - - - - - - - - - - -:

: VRS 7 0 sin(0 150m 1.2863363889332e+3 0 0) :

sin/sin/; Rs 7 0 0 e=150m*sin(8.0822898994674e+3*time) :

: choke ; L1 6 17 80mH; RL1 17 7 0 :

© 2003 by CRC Press LLC

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: L1 6 17 80e-3 ;:mH : VRL1 17 7 DC 0 ;:ammeter for measure of IL1 : : - - - - - - - - - - - - - - - - - - - - - : harmonic oscillator; L2 6 16 13mH; RL2 16 0 1 C2 6 0 1.250uF : L2 6 16 13m : RL2 16 0 1 : C2 6 0 1.250u : :- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - : load; r61 6 10 1310; rrc1 10 11 0; c1 11 0 0.017uF rr10 10 1 0: irr10=current of nonlinear resistor : r61 6 10 1310 : vrrC1 10 11 DC 0 : C1 11 0 0.017u : i(vrr10)=current of nonlinear resistor : vrr10 10 1 DC 0 : non-linear circuit; : - - - - - - - - - - - - - - - - - - - - - : .model n4148 d (is=0.1p rs=16 n=1); vt=n*k*T/q n4148 /diode/ is=0.1p gs=62.5m vt=25mV; td13 1 3 n4148; td21 2 1 n4148; : d13 1 3 n4148 : d21 2 1 n4148 rm9 2 0 47k e=-9; rp9 3 0 47k E=+9; : rm9 2 22 47k : vrm9 22 0 DC -9; negative power supply : rp9 3 33 47k : vrp9 33 0 DC +9 r20 2 0 3.3k; r30 3 0 3.3k; : r20 2 0 3.3k : r30 3 0 3.3k : ideal op. amp.; : - - - - - - - - - - - - - - - - - - - - - - - - - - gop 1 5 0; vop 4 0 vgop: no value means infinite value; : evop 4 0 1 5 1e+20 r14 1 4 290; r54 5 4 290; r50 5 0 1.2k; : r14 1 4 290 : r54 5 4 290 : r50 5 0 1.2k :- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - *time time 0 200m : variable order, variable step : .TRAN 0.05m 200m 0 0.018m UIC *tr vnall *plot(50 v6) v1 *probe : .plot tran v(11) : .probe *run cycle=15000 minstep=1e-20 > trunc=1e-3 step=50n : .options acct nopage opts gmin=1e-15 reltol=1e-3 :+ abstol=1e-12 vntol=1e-12 tnom=25 itl5=0 :+ limpts=15000 : .end *end

© 2003 by CRC Press LLC

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250.0uA 200.0uA

0.0uA

–200.0uA –250.0uA 0ms

20ms

40ms

60ms

80ms

100ms

I (C1) TIME

250.0uA 200.0uA

0.0uA

–200.0uA –250.0uA –2.0V

–1.0V

0.0V

1.0V

2.0V

I (C1) v(11)

FIGURE 38.3 (a) NAP2 analysis. The current of C1: I(C1) as function of time in the interval 0 to 100 ms. (b) The current of C1: I(C1) as function of the voltage of C1: V(11) in the time interval 0 to 100 ms. (c) The current of C1: I(C1) as function of time in the interval 180 to 200 ms. (d) The current of C1: I(C1) as function of the voltage of C1: V(11) in the time interval 100 to 200 ms.

The program options are set by means of the statement *RUN, where, for example, the minimum integration step is set to 1e-20 s and the relative truncation error is set to 1e-6. The result of the analysis is presented in Fig. 38.3. It can be observed that transition from chaotic behavior to a period 5 limit cycle takes place at about 50 ms. If we compare to the results obtained above by means of SPICE and APLAC, we see that although the three programs are “modeled and set” the same way, for example, with the same relative tolerance 1e-3, the results are different due to the chaotic nature of the circuit and possibly also due to the different strategies of equation formulation and solution used in the three programs. For example, SPICE uses the trapezoidal integration method with variable step; APLAC and NAP2 use the Gear integration methods with variable order and variable step.

© 2003 by CRC Press LLC

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200uA

100uA

0.0uA

–100uA

–200uA 180ms

185ms

190ms

195ms

200ms

i (c1) time 200uA

100uA

0.0uA

–100uA

–200uA –2.0V

–1.5V

–1.0V

–0.5V

0.0V

0.5V

1.0V

1.5V

2.0V

i (c1) v (11)

FIGURE 38.3 (continued).

ESACAP The first versions of ESACAP (Engineering System and Circuit Analysis Program) based on the extended nodal equation formulation were developed in 1979 at Elektronik Centralen, Hoersholm, Denmark, for ESA (the European Space Agency) as a result of a strong need for a simulation language capable of handling interdisciplinary problems (e.g., coupled electrical and thermal phenomena). ESACAP was therefore born with facilities that have only recently been implemented in other simulation programs (e.g., facilities referred to as behavioral or functional modeling). ESACAP carries out analyses on nonlinear systems in dc and in the time domain. The nonlinear equations are solved by a hybrid method combining the robustness of the gradient method with the good convergence properties of the Newton–Raphson method. The derivatives required by the Jacobian matrix are symbolically evaluated from arbitrarily complex arithmetic expressions and are therefore exact. The symbolic evaluation of derivatives was available in the very first version of ESACAP. It has now become a general numerical discipline known as automatic differentiation. The time-domain solution is found by numerial integration implemented as backward difference formulas, BDFs, of © 2003 by CRC Press LLC

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variable step and orders 1 through 6 (modified Gear method). An efficient extrapolation method (the epsilon algorithm) accelerates the asymptotic solution in the periodic steady-state case. Frequency-domain analyses may be carried out on linear or linearized systems (e.g., after a dc analysis). Besides complex transfer functions, special outputs such as group delay and poles/zeros are available. The group delay is computed as the sum of the frequency sensitivities of all the reactive components in the system. Poles and zeros are found by a numerical interpolation of transfer functions evaluated on a circle in the complex frequency plane. ESACAP also includes a complex number postprocessor by means of which any function of the basic outputs can be generated (e.g., stability factor, s-parameters, complex ratios). Sensitivities of all outputs with respect to all parameters are available in all analysis modes. The automatic differentiation combined with the adjoint network provides exact partial derivatives in the frequency domain. In the time domain, integration of a sensitivity network (using the already LU-factorized Jacobian) provides the partial derivatives as functions of time The ESACAP language combines procedural facilities, such as if-then-else, assignment statements and do-loops, with the usual description by structure (nodes/branches). Arbitrary expressions containing system variables and their derivatives are allowed for specifying branch values thereby establishing any type of nonlinearity. System variables of non-potential and non-current type may be defined and used everywhere in the description (e.g., for defining power, charge). The language also accepts the specification of nonlinear differential equations. Besides all the standard functions known from high-level computer languages, ESACAP provides a number of useful functions. One of the most important of these functions is the delay function. The delay function returns one of its arguments delayed by a specified value, which in turn may depend on system variables. Another important function is the threshold switch — the ZEROREF function — used in if-then-else constructs for triggering discontinuities. The ZEROREF function interacts with the integration algorithm that may be reinitialized at the exact threshold crossing. The ZEROREF function is an efficient means for separating cause and action in physical models thereby eliminating many types of causality problems. Causality problems are typical examples of bad modeling techniques and the most frequent reason for divergence in the simulation of dynamic systems. Typical ESACAP applications include electronics as well as thermal and hydraulic systems. The frequency domain facilities have been a powerful tool for designing stable control systems including nonelectronics engineering disciplines. In order to give an idea of the input language, the syntax of the statements describing sources is as follows: Current Source: Voltage Source:

Jxxx(N+, N-)=VALUE;

Exxx(N+, N-)=VALUE;

where the initial characters of the branch name: J and E indicate the type of the branch, N+ and N- are node identifiers (character strings), which, as a special case, may be integer numbers (“node numbers”). The node identifiers indicate the placement and orientation of the branch. The VALUE specifies the numerical value of the source, which may be an arbitrary function of time, temperature, and parameters as well as system variables (including their time derivatives). Adding an apostrophe references the time derivative of a system variable. V(N1,N2)’, for example, is the time derivative of the voltage drop from node N1 to node N2. The next input file — actually, a small program written in the ESACAP language — describes an analysis of a tapered transmission line. The example shows some of the powerful tools available in the ESACAP language such as: (1) the delay function; (2) the do-loop; and (3) the sensitivity calculation. The description language of ESACAP is a genuine simulation and modeling language. However, for describing simple systems, the input language is just slightly more complicated than the languages of SPICE, APLAC, and NAP2. Data is specified in a number of blocks (“chapters” and “sections”) starting with $$ and $. Note how the line model is specified in a do-loop where ESACAP creates nodes and branches of a ladder network [10]. © 2003 by CRC Press LLC

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Example.155 Tapered line in the time domain.

# Calculation of sensitivities.

# This example shows the use of a do-loop for the discretization of a

# tapered transmission line into a chain of short line segments. The

# example also demonstrates how to specify partial derivatives of any

# parameter for sensitivity calculations.

$$DESCRIPTION # chapter — - — - — - — - — - — - — - — - — - ­

$CON: n_sections=60; END; # section — - — - — - — - — - — - ­

# n_sections is defined as a globally available constant.

# Only this constant needs to be modified in order to change

# the resolution of discretization

# Transmission line specified by characteristic impedance and length.

# Modelled by the ESACAP delay function (DEL).

$MODEL: LineCell(in,out): Z0,length;

delay=length/3e8;

J_reverse(0,in)=DEL(2*V(out)/Z0-I(J_forward), delay);

J_forward(0,out)=DEL(2*V(in)/Z0-I(J_reverse), delay);

G1(in,0)=1/Z0; G2(out,0)=1/Z0;

END; # end of section — - — - — - — - — - ­

# Tapered line specified by input and output impedance and length

# This model calls LineCell n_sections times in a do-loop.

$MODEL: TaperedLine(in,out): Z1,Z2,length;

ALIAS_NODE(in,1); # Let node in and 1 be the same. ALIAS_NODE(out,[n_sections+1]); # Let node out and n_sections+1 be # the same. # Notice that values in square brackets become part of an identifier

FOR (i=1, n_sections) DO

X[i]([i],[i+1])=LineCell(Z1+i*(Z2-Z1)/n_sections, length/n_sections);

ENDDO;

END; # end of section — - — - — - — - — - ­

# Main network calls the model of the tapered line and terminates

# it by a 50 ohm source and 100 ohm load.

$NETWORK: # section — - — - — - — - — - ­

IF(TIME.LT.1n) THEN

Esource(source,0)=0;

ELSE

Esource(source,0)=1;

ENDIF;

# Esource(source,0)=TABLE(TIME,(0,0),(1n,0),(1.001n,1),(10n,1));

Rsource(source,in)=50;

Rload(out,0)=100;

Z1=50; Z2=100; length=1;

X1(in,out)=TaperedLine(Z1,Z2,length);

END; # end of section — - — - — - — - — - ­

# Time-domain analysis

$$TRANSIENT # chapter — - — - — - — - — - — - — - — - ­

# Analysis parameters

$PARAMETERS: # section — - — - — - — - — - — - — - — - ­

TIME=0,20n; # Total time sweep

HMAX=2p; # Max integration step

END; # end of section — - — - — - — - — - — - — ­

© 2003 by CRC Press LLC

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1.0000

V(out) V(in)

V(out)

V(in)

0.0000 0.0000

20.00n

TIME

d(V(out))/d(Z1) d(V(in))/d(Z1)

5.000m

d(V(in))/d(Z1)

d(V(out))/d(Z1) 0.0000 0.0000

20.00n

TIME

FIGURE 38.4 (a) ESACAP analysis. The input voltage of the tapered line: V(in) and the output voltage of the tapered line: V(out) as functions of time in the interval from 0 to 20 ns. (b) The sensitivities of V(in) and V(out) with respect to Z1.

# Specification of desired results. Adding an exclamation mark (!) to an

# output will show the value on the ESACAP real-time graphics display.

$DUMP: # section — - — - — - — - — - — - — - — - ­

FILE=; TIME=0,20n,20p;

TIME; V(in)!; V(out)!;

(V(in),DER(Z1))!; # Partial derivatives with respect

(V(out),DER(Z1))!; # to Z1

END; # end of section — - — - — - — - — ­

$$STOP # chapter — - — - — - — - — - — - — - — ­

The result of the analysis is presented in Fig. 38.4.

DYNAST DYNAST (DYNAmic Simulation Tool) [5] was developed in 1992 in a joint venture between The Czech Technical University, Prague, the Czech Republic and Katholieke Universiteit Leuven, Heverlee, Belgium. The program was developed as an interdisciplinary simulation and design tool in the field of “mecha­ tronics” (mixed mechanical/electrical systems). The main purpose of DYNAST is to simulate dynamic systems decomposed into subsystems defined independently of the system structure. The structure can be hierarchical. DYNAST is a versatile software tool for modeling, simulation, and analysis of general linear as well as nonlinear dynamic systems, both in time and frequency domain. Semisymbolic analysis is possible (poles and zeros of network functions, inverse Laplace transformation using closed-form formulas). © 2003 by CRC Press LLC

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Three types of subsystem models are available in DYNAST. The program admits systems descriptions in the form of (1) a multipole diagram respecting physical laws; (2) a causal or an acausal block diagram; (3) a set of equations; or (4) in a form combining the above approaches. 1) In DYNAST the physical-level modeling of dynamic systems is based on subsystem multipole models or multiterminal models. These models respect the continuity and compatibility postulates that apply to all physical energy-domains. (The former postulate corresponds to the laws of conservation of energy, mass, electrical charge, etc.; the latter is a consequence of the system connectedness). The multipole poles correspond directly to those subsystem locations in which the actual energetic interactions between the subsystems take place (such as shafts, electrical terminals, pipe inlets, etc.). The interactions are expressed in terms of products of complementary physical quantity pairs: the through variables flowing into the multipoles via the individual terminals, and the across variables identified between the terminals. 2) The causal blocks, specified by explicit functional expressions or transfer functions, are typical for any simulation program. But the variety of basic blocks is very poor in DYNAST, as its language permits definition of the block behavior in a very flexible way. Besides the built-in basic blocks, user specified multi-input multi-output macroblocks are available as well. The causal block interconnections are restricted by the rule that only one block output may be connected to one or several block inputs. In the DYNAST block variety, however, causal blocks are also available with no restrictions imposed on their inteconnections, as they are defined by implicit-form expressions. 3) DYNAST can also be used as an equation solver for systems of nonlinear first-order algebro­ differential and algebraic equations in the implicit form. The equations can be submitted in a natural way (without converting them into block diagrams) using a rich variety of functions including the Boolean, event-dependent, and tabular ones. The equations, as well as any other input data, are directly interpreted by the program without any compilation. The equation formulation approach used for both multipoles and block diagrams evolved from the extended method of nodal voltages (MNA) developed for electrical systems. Because all the equations of the diagrams are formulated simultaneously, no problems occur with the algebraic loops. As the formulated equations are in the implicit form, it does not create any problems with the causality of the physical models. The integration method used to solve the nonlinear algebro-differential and algebraic equations is based on a stiff-stable implicit backward-differentiation formula (a modified Gear method). During the integration, the step length as well as the order of the method is varied continuously to minimize the computational time while respecting the admissible computational error. Jacobians necessary for the integration are computed by symbolic differentiation. Their evaluation as well as their LU decomposi­ tion, however, is not performed at each iteration step if the convergence is fast enough. Considerable savings of computational time and memory are achieved by a consistent matrix sparsity exploitation. To accelerate the computation of periodic responses of weakly damped dynamic systems, the iterative epsilon-algorithm is utilized. Also, fast-Fourier transformation is available for spectral analysis of the periodic steady-state responses. DYNAST runs under DOS- or WINDOWS-control on IBM-compatible PCs. Because it is coded in FORTRAN 77 and C-languages, it is easily implemented on other platforms. It is accompanied by a menu-driven graphical environment. The block and multiport diagrams can be submitted in a graphical form by a schematic capture editor. DYNAST can be easily augmented by various pre- and postprocessors because all its input and output data are available in the ASCII code. Free “net-list” access to DYNAST is possible by means of e-mail or online over the Internet [5].

References [1] Calahan, D. A., Computer-Aided Network Design, New York: McGraw-Hill, 1972. [2] Chua, L. O. and P.-M. Lin, Computer-Aided Analysis of Electronic Circuits, Englewood Cliffs, NJ: Prentice Hall, 1975. [3] Dertouzos, M. L. et al., Systems, Networks, and Computation: Basic Concepts, New York: McGrawHill, 1972. © 2003 by CRC Press LLC

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[4] Intusoft, IsSpice3 — ICAPS System Packages, San Pedro, CA: Intusoft, 1994, http://www.intusoft.com/. [5] Mann, H., DYNAST — A Multipurpose Engineering Simulation Tool, Prague, Czech Republic: The Czech Technical University, 1994, http://www.it.dtu.dk/ecs/teacher.htm, http://icosym.cvut.cz/cacsd/ msa/onlinetools.html, http://icosym.cvut.cz/dyn/download/public/. [6] Meta-Software, HSPICE User’s Manual H9001, Campbell, CA: Meta-Software, 1990. [7] MicroSim, PSpice — The Design Center, Irvine, CA: MicroSim, 1994, http://www.cadencepcb.com and http://www.pspice.com/. [8] Ostrowski, A.M., Solution of Equations and Systems of Equations, New York: Academic Press, 1966. [9] Rübner-Petersen, T., NAP2 — A Nonlinear Analysis Program for Electronic Circuits, version 2, Users Manual 16/5-73, Report IT-63, ISSN-0105-8541, Lyngby, Denmark: Institute of Circuit Theory and Telecommunication, Technical University of Denmark, 1973, http://www.it.dtu.dk/ecs/pro­ grams.htm#nnn, http://www.it.dtu.dk/ecs/napanp.htm. [10] Stangerup, P., ESACAP User’s Manual, Nivaa, Denmark: StanSim Research Aps., 1990, http://www.it.dtu.dk/ecs/esacap.htm. [11] Valtonen, M. et.al., APLAC — An Object-Oriented Analog Circuit Simulator and Design Tool, Espoo, Finland: Circuit Theory Lab., Helsinki University of Technology and Nokia Corporation Research Center, 1992, http://www.aplac.hut.fi/aplac/general.html, http://www.aplac.com/. [12] Vlach, J. and K. Singhal, Computer Methods for Circuit Analysis and Design, New York: Van Nostrand Reinhold, 1983. [13] Funk, D. G. and Christiansen, D. Eds., Electronic Engineers’ Handbook, 3rd ed., New York: McGrawHill, 1989.

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39 Cellular Neural Networks Tamás Roska Computer and Automation Research Institute of the Hungarian Academy of Sciences and the Pázmány P. Catholic University, Budapest

Ákos Zarándy Hungarian Academy of Science

Csaba Rekeczky Hungarian Academy of Sciences

39.1 Introduction: Definition and Classification 39.2 The Simple CNN Circuit Structure 39.3 The Stored Program CNN Universal Machine and the Analogic Supercomputer Chip 39.4 Applications Image Processing — Form, Motion, Color, and Depth • Partial Differential Equations • Relation to Biology

39.5 Template Library: Analogical CNN Algorithms 39.6 Recent Advances

39.1 Introduction: Definition and Classification Current VLSI technologies provide for the fabrication of chips with several million transistors. With these technologies a single chip may contain one powerful digital processor, a huge memory containing millions of very simple units placed in a regular structure, and other complex functions. A powerful combination of a simple logic processor placed in a regular structure is the cellular automaton invented by John von Neumann. The cellular automaton is a highly parallel computer architecture. Although many living neural circuits resemble this architecture, the neurons do not function in a simple logical mode: they are analog “devices.” The cellular neural network architecture, invented by Leon O. Chua and his graduate student Lin Yang [1] has both properties: the cell units are nonlinear continuous time dynamic elements placed in a cellular array. Of course, the resulting nonlinear dynamics in space could be extremely complex. The inventors, however, showed that these networks can be designed and used for a variety of engineering purposes, while maintaining stability and keeping the dynamic range within well-designed limits. Subsequent developments have uncovered the many inherent capabilities of this architecture (IEEE conferences: CNNA-90, CNNA-92, CNNA-94, 96, 98, 00, 02; Special issues: Int. J. Circuit Theory and Applications, 1993, 1996, 1998, 2002 and IEEE Transactions on Circuits and Systems, I and II, 1993, 1999, etc.). In the circuit implementation, unlike analog computers or general neural networks, the CNN cells are not the ubiquitous high-gain operational amplifiers. In most practical cases, they are either simple unity gain amplifiers or simple second- or third-order simple dynamic circuits with one to two simple nonlinear components. Tractability in the design and the possibility for exploiting the complex nonlinear dynamic phenomena in space, as well as the trillion operations per second computing speed in a single chip are but some of the many attractive properties of cellular neural networks. The trade-off is in the accuracy; however, in many cases, the accuracy achieved with current technologies is enough to solve a lot of real-life problems. The cellular neural/nonlinear network (henceforth called CNN) is a new paradigm for multidimen­ sional, nonlinear, dynamic processor arrays [1], [23]. The mainly uniform processing elements, called cells or artificial neurons, are placed on a regular geometric grid (with a square, hexagonal, or other pattern).

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FIGURE 39.1 A CNN grid structure with the processing elements (cells) located at the vertices. ��� �����

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This grid may consist of several two-dimensional layers packed upon each other (Fig. 39.1). Each pro­ cessing element or cell is an analog dynamical system, the state (x), the input (u), and the output (y) signals are analog (real-valued) functions of time (both continuous-time and discrete-time signals are allowed). The interconnection and interaction pattern assumed at each cell is mainly local within a neighborhood Nr, where Nr denotes the first “r” circular layers of surrounding cells. Figure 39.2 shows a two-dimensional layer with a square grid of interconnection radius of 1 (nearest neighborhood). Each vertex contains a cell and the edges represent the interconnections between the cells. The pattern of interaction strengths between each cell and its neighbors is the “program” of the CNN array. It is called a cloning template (or just template). Depending on the types of grids, processors (cells), interactions, and modes of operation, several classes of CNN architectures and models have been introduced. Although the summary below is not complete, it gives an impression of vast diversities. Typical CNN Models • Grid type: square

hexagonal

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Cellular Neural Networks

planar

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linear memoryless

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39.2 The Simple CNN Circuit Structure The simplest first-order dynamic CNN cell used in the seminal paper [1] is illustrated in Fig. 39.3. It is placed on the grid in the position ij (row i and column j). It consists of a single state capacitor with a parallel resistor and an amplifier [f (xij)]. This amplifier is a voltage-controlled current source (VCCS), where the controlling voltage is the state capacitor voltage. To make the amplifier model self-contained, a parallel resistor of unit value is assumed to be connected across the output port. Hence, the voltage transfer characteristic of this amplifier is also equal to f (·). In its simplest form this amplifier has a unity gain saturation characteristic (see Fig. 39.7 for more details). The aggregate feed-forward and feedback interactions are represented by the current sources iinput and ioutput, respectively. Figure 39.4 shows these interactions in more detail. In fact, the feedforward interaction term iinput is a weighted sum of the input voltages (ukl ) of all cells in the neighborhood (Nr ). Hence, the feedforward template, the so-called B template, is a small matrix of size (2r + 1) × (2r + 1) containing the template elements bkl , which can be implemented by an array of linear voltage-controlled current sources. The controlling voltages of these controlled sources are the input voltages of the cells within the neighborhood of radius r. This means, for example, that b12 is the VCCS controlled by the input voltage of the cell lying north from the cell ij. In most practical cases the B template is translation invariant, i.e., the interaction pattern (the B template) is the same for all cells. Hence, the chip layout will be very regular (as in memories or PLAs). The feedback interaction term ioutput is a weighted sum of the output voltages �����

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(ykl) of all cells in the neighborhood (Nr ). The weights are the elements of a small matrix A called the A template (or feedback template). Similar arguments apply for the A template as for the B template discussed previously. If the constant threshold term is translation invariant as denoted by the constant current source I, then in the case of r = 1, the complete cloning template contains only 19 numbers (A and B and I, i.e., 9 + 9 + 1 terms), irrespective of the size of the CNN array. These 19 numbers define the task which the CNN array can solve. What kind of tasks are we talking about? The simplest, and perhaps the most important, are imageprocessing tasks. In the CNN array computer, the input and output images are coded as follows. For each picture element (called pixel) in the image, a single cell is assigned in the CNN. This means that a one-to-one correspondence exists between the pixels and the CNN cells. Voltages in the CNN cells code the gray-scale values of the pixels. Black is coded by +1 V, white is –1 V, and the gray-scale values are in between. Two independent input images can be defined pixel by pixel: the input voltages uij and the initial voltage values of the capacitors xij (0) (cell by cell). Placing these input images onto the cell array and starting the transient, the steady state outputs yij will encode the output image. The computing time is equal to the settling time of the CNN array. This time is below one microsecond using a CNN chip made with a 1.0–1.5 µm technology containing thousands of CNN processing elements, i.e., pixels, in an area of about 2 cm2. This translates to a computing power of several hundred billion operations per second (GXPS). The first tested CNN chip [4] was followed by several others implementing a discrete-time CNN model [6] and chips with on-chip photosensors in each cell [5]. For example, if we place the array of voltage values defined by the image shown in Fig. 39.5(b) as the input voltage and the initial state capacitor voltage values in the CNN array with the cloning template shown in Fig. 39.5(a), then after the transients have settled down, the output voltages will encode the output image of Fig. 39.5(c). Observe that the vertical line has been deleted. Since the image contains 40 × 40 pixels, the CNN array contains 40 × 40 cells. It is quite interesting that if we had more than one vertical line, the computing time would be the same. Moreover, if we had an array of 100 × 100 cells on the chip, the computing time would remain the same as well. This remarkable result is due to the fully parallel nonlinear dynamics of the CNN computer. Some propagating-type templates induce wave-like phenomena. Their settling times increase with the size of the array.

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For other image-processing tasks, processing form, motion, color, and depth, more than 100 cloning templates have been developed to date and the library of new templates is growing rapidly. Using the Cellular Neural Network Workstation Tool Kit [10], they can be called in from a CNN Template Library (CTL). New templates are being developed and published continually. The dynamics of the CNN array is described by the following set of differential equations: dx ij dt = −x ij + I + ioutput + iinput

( )

y ij = f x ij

i = 1, 2,K, N and

j = 1, 2, K, M (the array has N × M cells)

where the last two terms in the state equation are given by the sums shown in Fig. 39.4. We can generalize the domain covered by the original CNN defined via linear and time-invariant templates by introducing the “nonlinear” templates (denoted by ^) and the “delay” templates (indicated by τ in the superscript) as well, to obtain the generalized state equation shown below. The unity-gain nonlinear sigmoid characteristics f are depicted in Fig. 39.6. f(V)

1 −1 1 −1

FIGURE 39.6 The simple unity-gain sigmoid characteristics.

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Several strong results have been proved that assure stable and reliable operations. If the A template is symmetric, then the CNN is stable. Several other results have extended this condition [6,7]. The sum of the absolute values of all the 19 template elements plus one defines the dynamic range within which the state voltage remains bounded during the entire transient, if the input and initial state signals are less than 1 V in absolute value [1]. In a broader sense, the CNN is defined [2] as shown in Fig. 39.7. •

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39.3 The Stored Program CNN Universal Machine and the Analogic Supercomputer Chip For different tasks, say image-processing, we need different cloning templates. If we want to implement them in hardware, we would need different chips. This is inefficient except for dedicated, mass-production applications. The invention of the CNN universal machine [8] has overcome the problem above. It is the first stored program array computer with analog nonlinear array dynamics. One CNN operation, for example, solving thousands of nonlinear differential equations in a microsecond, is just one single instruction. In addition, a single instruction is represented by just a few analog (real) values (numbers). In the case when the nearest neighborhood is used, only 19 numbers are generated. When combining several CNN templates, for example extracting first contours in a gray-scale image, then detecting those areas where the contour has holes, etc., we have to design a flowchart-logic that satisfies the correct sequence of the different templates. The simple flowchart for the previous example is shown in Fig. 39.8. One key point is input: gray scale image

contour detection template

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hole detection template

output image

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FIGURE 39.8 A flowchart representing the logic sequence of two templates.

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FIGURE 39.9 The global architecture of the CNN Universal Machine. Source: T. Roska and L. O. Chua, “The CNN Universal Machine: An analogic array computer,” IEEE Trans. Circuits Syst. I, vol. 40, pp. 163–173, 1993.  1993 IEEE.

that, in order to exploit the high speed of the CNN chips, we have to store the intermediate results cell by cell (pixel by pixel). Therefore, we need a local analog memory. By combining several template actions we can write more complex flowcharts for implementing almost any analogic algorithms. The name analogic is an acronym for “analog and logic.” It is important to realize that analogic computation is completely different from hybrid computing. To cite just one point, among others, no A/D or D/A conversions occur during the computation of an analogic program. As with digital microprocessors, to control the execution of an analogic algorithm, we need a global programming unit. The global archi­ tecture of the CNN universal machine is shown in Fig. 39.9. As we can see from this figure, the CNN nucleus described in the previous section has been generalized to include several crucial functions depicted in the periphery. We have already discussed the role of the local analog memory (LAM) that provides the local (on-chip) storage of intermediate analog results. Because the results of many detection tasks in applications involve only black-and-white logic values, adding a local logic memory (LLM) in each cell is crucial. After applying several templates in a sequence, it is often necessary to combine their results. For example, to analyze motion, consecutive snapshots processed by CNN templates are compared. The local analog output unit (LAOU) and the local logic unit (LLU) perform these tasks, both on the local analog (gray scale) and the logical (black-and-white) values. The local communication and control unit (LCCU) of each cell decodes the various instructions coming from the global analogic program unit (GAPU). The global control of each cell is provided by the GAPU. It consists of four parts: 1. The analog program (instruction) register (APR) stores the CNN template values (19 values for each CNN template instruction in the case of nearest interconnection). The templates stored here will be used during the run of the prescribed analogical algorithm. 2. The global logic program register (LPR) stores the code for the local logic units. © 2003 by CRC Press LLC

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3. The flexibility of the extended CNN cells is provided by embedding controllable switches in each cell. By changing the switch configurations of each cell simultaneously, we can execute many tasks using the same cell. For example, the CNN program starts by loading a given template, storing the results of this template action in the local analog memory, placing this intermediate result back on the input to prepare the cell, starting the action with another template, etc. The switch configurations of the cells are coded in the switch configuration register (SCR). 4. Finally, the heart of the GAPU is the global analogic control unit (GACU), which contains the physical machine code of the logic sequence of analogical algorithm. It is important to emphasize that here the control code is digital; hence, although its internal operation is analog and logical, a CNN universal chip can be programmed with the same flexibility and ease as a digital micro­ processor — except the language is much simpler. Indeed, a high-level language, a compiler, an operating system, and an algorithm development system are available for CNN universal chip architectures. Moreover, by fabricating optical sensors cell-by-cell on the chip [5], the image input is directly interfaced. The CNN universal chip is called supercomputer chip because the execution speed of an analogic algorithm falls in the same range as the computing power of today’s average digital supercomputers (a trillion operations per second). Another reason for this enormous computing power is that the repro­ gramming time of a new analog instruction (template) is of the same order, or less, than the analog array execution time (less than a microsecond). This is about one million times faster than some fully inter­ connected analog chips. Based on the previously mentioned novel characteristics, the CNN universal chip can be considered to be an analogic microprocessor.

39.4 Applications In view of its flexibility and its very high speed in image-processing tasks, the CNN Universal Machine is ideal for many applications. In the following, we briefly describe three areas. For more applications, the reader should consult the references at the end of this chapter.

Image Processing — Form, Motion, Color, and Depth Image processing is currently the most popular application of CNN. Of the more than 100 different templates currently available, the vast majority are for image-processing tasks. Eventually, we will have templates for almost all conceivable local image-processing operations. Form (shape), motion, color, and depth can all be ideally processed via CNN. The interested reader can find many examples and applications in the references. CNN handles analog pixel values, so gray-scale images are processed directly. Many templates detect simple features like different types of edges, convex or concave corners, lines with a prescribed orientation, etc. Other templates detect semiglobal features like holes, groups of objects within a given size of area, or delete objects smaller than a given size. There are also many CNN global operations like calculating the shadow, histogram, etc. Halftoning is commonly used in fax machines, laser printers, and newspapers. In this case, the local gray level is represented by black dots of identical size, whose density varies in accordance with the gray level. CNN templates can do this job as well. A simple example is shown in Fig. 39 .10. The original gray-scale image is shown on the left-hand side, the halftoned image is shown on the right-hand side. The “smoothing” function of our eye completes the image processing task. More complex templates detect patterns defined within the neighborhood of interaction. In this case, the patterns of the A and B templates somehow reflect the pattern of the object to be detected. Because the simplest templates are translation invariant, the detection or pattern recognition is trans­ lation invariant as well. By clever design, however, some rotationally invariant detection procedures have been developed as well.

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FIGURE 39.10 Halftoning: an original gray-scale image (LHS) and its halftoned version (RHS). A low resolution is deliberately chosen in (b) in order to reveal the differing dot densities at various regions of the image.

Combining several templates according to some prescribed logic sequence, more complex pattern detection tasks can be performed, e.g., halftoning. Color-processing CNN arrays represent the three basis colors by single layers via a multilayer CNN. For example, using the red-green-blue (RGB) representation in a three-layer CNN, simple color-process­ ing operations can be performed. Combining them with logic, conversions between various color rep­ resentations are possible. One of the most complex tasks that has been undertaken by an analogic CNN algorithm is the recognition of bank notes. Recognition of bank notes in a few milliseconds is becoming more and more important. Recent advances in the copy machine industry have made currency counterfeiting easier. Therefore, automatic bank note detection is a pressing need. Figure 39.11 shows a part of this process (which involves color processing as well). The dollar bill shown in the foreground is analyzed and the circles of a given size are detected (colors are not shown). The “color cube” means that each color intensity is within prescribed lower and upper limit values. Motion detection can be achieved by CNN in many ways. One approach to process motion is to apply two consecutive snapshots to the input and the initial state of the CNN cell. The CNN array calculates the various combinations between the two snapshots. The simplest case is just taking the difference to detect motion. Detecting direction, shape, etc. of moving objects are only the simplest problems that can be solved via CNN. In fact, even depth detection can be included as well.

Partial Differential Equations As noted in the original paper [1], even the simple-cell CNN with the linear template 0  A = 1  0

1 −3 1

0  1  0

B = 0

I = 0/

can approximate the solution of a diffusion-type partial differential equation on a discrete spatial grid. This solution maintains continuity in time, a nice property not possible in digital computers. By adding just a simple capacitor to the output, i.e., by placing a parallel RC circuit across the output port of the cell of Fig. 39.3, the following wave equation will be represented in a discrete space grid: d 2 p(t ) dt 2 = ∆p where p(t) = P(x, y, t) is the state (intensity) variable on a two-dimensional plane (x, y), and ∆ is the Laplacian operator (the sum of the second derivatives related to x and y).

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FIGURE 39.11 Some intermediate steps in the dollar bill recognition process. An input image (a) shown here in single color, results in the “color cube” (b), the convex objects (c), and the size classification (d). Source: A. Zarándy, F. Werblin, T. Roska, L. O. Chua, and “Novel type of analogical CNN algorithms for recognizing bank notes,” Memorandum UCB/ERL, M94/29 1994, Electron. Res. Lab., Univ. California, Berkeley, 1994.

In some cases, it is useful to use a cell circuit that is chaotic. Using the canonical Chua’s circuit, other types of partial differential equations can be modeled, generating effects like auto-waves, spiral waves, Turing patterns, and so on, e.g., Perez-Munuzuri et al. in [7].

Relation to Biology Many topographical sensory organs have processing neural-cell structures very similar to the CNN model. Local connectivity in a few sheets of regularly situated neurons is very typical. Vision, especially the retina, reflects these properties strikingly. It is not surprising that, based on standard neurobiological models, CNN models have been applied to the modeling of the subcortical visual pathway [9]. Moreover, a new method has been devised to use the CNN universal machine for combining retina models of different species in a programmed way. Modalities from other sensory organs can be modeled similarly and combined with the retina models [12]. This has been called Bionic Eye. Many of these models are neuromorphic. This means that there is a one-to-one correspondence between the neuroanatomy and the CNN structure. Moreover, the CNN template reflects the interconnection © 2003 by CRC Press LLC

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FIGURE 39.12 The length tuning effect. The input image on the LHS contains bars of different lengths. The out image on the RHS contains only those that are smaller than a given length. Source: T. Roska, J. Hámori, E. Lábos, K. Lotz. J. Takács, p. Venetianer, Z. Vidnyánszki and A. Zarándy, “The use of CNN models in the subcortical visual pathway,” IEEE Trans. Circuits Syst. I, vol. pp. 182–195, 1993. © 1993 IEEE.

pattern of the neurons (called receptive field organizations). Length tuning is such an example. A corresponding input and output picture of the neuromorphic length tuning model is shown in Fig. 39.12. Those bars are detected that have lengths smaller than or equal to 3 pixels.

39.5 Template Library: Analogical CNN Algorithms During the last few years, after the invention of the cellular neural network paradigm and the CNN universal machine, many new cloning templates have been discovered. In addition, the number of innovative analogical CNN algorithms, combining both analog cloning templates and local as well as global logic, is presently steadily increasing at a rapid rate. As an illustration, let us choose a couple of cloning templates from the CNN library [1], [11]. In each case, a name, a short description of the function, the cloning templates, and a representative input–output image pair are shown. With regard to the inputs, the default case means that the input and initial state are the same. If B = 0, then the input picture is chosen as the initial state. Name: AVERAGE Function. Spatial averaging of pixel intensities over the r = 1 convolutional window. 0  A = 1  0 Example. Input and output picture.

© 2003 by CRC Press LLC

1 2 1

0  1  0

0  B = 0  0

0 0 0

0  0  0

I =0

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Name: AND Function. Logical “AND” function of the input and the initial state pictures. 0  A = 0  0

0 1.5 0

0  0  0

0  B = 0  0

0 1.5 0

0  0  0

I = −1

Example. Input, initial state, and output picture. INPUT 1

INPUT 2

OUTPUT 2

Name: CONTOUR Function. Gray-scale contour detector. 0  A = 0  0

0 2 0

0  0  0

a  B = a  a

a a a

a  a  a 

a 0.5 –0.18

0.18 v

–1

Example. Input and output picture.

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x1 j - v xk1

I = 0.7

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Name: CORNER Function. Convex corner detector.

0  A = 0  0

−0.25  B = −0.25  −0.25

0  0  0

0 2 0

−0.25 2 −0.25

−0.25  −0.25  −0.25

I = −3

Example. Input and output picture.

INPUT 1

OUTPUT 1

Name: DELDIAG1 Function. Deletes one pixel wide diagonal lines (5).

0  A = 0  0

0 2 0

0  0  0

−0.25  B=  0  −0.25

0 0 0

−0.25  0   −0.25

I = −2

Example. Input and output picture.

INPUT 1

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OUTPUT 2

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Name: DIAG Function. Detects approximately diagonal lines situated in the SW-NE direction. 0  0  A = 0  0  0

0

0

0

0

0

0

0

2

0

0

0

0

0

0

0

0  0  0  0  0

 −1   −1  B = −0.5   0.5   1

−1

−0.5

0.5

−0.5

1

1

1

5

1

1

1

−0.5

0.5

−0.5

−1

1   0.5   −0.5  −1   −1 

I = −9 Example. Input and output picture.

Name: EDGE Function. Black and white edge detector. 0  A = 0  0

0 2 0

0  0  0

−0.25  B = −0.25  −0.25

−0.25 2 −0.25

−0.25  −0.25  −0.25

I = −1.5

Example. Input and output picture. INPUT 1

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OUTPUT 1

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Name: MATCH Function. Detects 3 × 3 patterns matching exactly the one prescribed by the template B, namely, having a black/white pixel where the template value is +1/–1, respectively.

0  A = 0  0

0  0  0

0 1 0

v  B = v  v

v  v  v 

v v v

I = −N + 0.5

where v = +1, if corresponding pixel is required to be black; v = 0, if corresponding pixel is don’t care; v = –1, if corresponding pixel is required to be white; N = number of pixels required to be either black or white, i.e., the number of nonzero values in the B template. Example. Input and output picture, using the following values:

0  A = 0  0

0  0  0

0 1 0

1  B = 0  1

−1 1 −1

1  0  1

INPUT 1

I = −6.5

OUTPUT 1

Name: OR Function. Logical “OR” function of the input and the initial state.

0  A = 0  0

© 2003 by CRC Press LLC

0 3 0

0  0  0

0  B = 0  0

0 3 0

0  0  0

I =2

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Example. Input, initial state, and output picture. INPUT 1

INPUT 2

OUTPUT 2

Name: PEELIPIX Function. Peels one pixel from all directions. 0  A = 0.4   0

0.4 1.4 0.4

0  0.4  0 

 4.6  B = −2.8   4.6

−2.8 1 −2.8

4.6   −2.8  4.6 

I = −7.2

Example. Input and output picture. INPUT 1

OUTPUT 1

39.6 Recent Advances After the first few integrated circuit implementations of the basic CNN circuits, stored programmable analogic CNN Universal Machine chips have been fabricated. Indeed, a full-fledged version of them [13] is the first visual microprocessor, all the 4096 cell processors of it contain an optical sensor right on the surface of the chip (a focal plane). This implementation represents, at the same time, the most complex operational, stored programmable analog CMOS integrated circuit ever reported, in terms of the number of transistors operating in analog mode (about 1 million). The equivalent digital computing power of this visual microprocessor is about a few TeraOPS (trillion operations per second). It processes grayscale input images and has a gray-scale output. A 128 × 128 processor version has recently been fabricated. A binary input/output CNN Universal Machine Chip with 48 × 48 cell processors has a higher cell density [14], and another circuit design strategy [18] is aiming to implement 5 × 5 or even higher neighborhood templates.

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1091

These chips are the first examples of a new, analogic, topographic (spatial-temporal) computing technology. Its computational infrastructure (high level language, called Alpha, compiler, operating system, etc.) has also been developed [15], and the industrial applications have been started in a couple of companies worldwide. Moreover, a key application area of this technology is sensor-computing [17]. Integrating 2-D topographic sensor arrays with the CNN universal machine on a single chip, providing a direct, dynamic interaction with tuning of the sensors, this is a capability no other technology offers with comparable computational power. Recently, it has been shown that partial differential equation (PDE)-based techniques, the most advanced methods for complex image processing problems, could solve tasks intractable with other methods. Their only drawback is the excessive digital computing power they need. In our cellular com­ puting technology, however, the elementary instruction could be a solution of a PDE. It has been shown that, in addition to the simple diffusion PDE implementation described previously, almost all PDEs can be implemented by CNN [16]. Indeed, active waves [23] have been successfully applied using operational analogic CNN Universal Machine Chips with 4096 cell processors, manifesting at least 3 orders of mag­ nitude speed advantage compared to fully digital chips of comparable IC technology feature size. Following the first steps in modeling living sensory modalities, especially vision, motivated especially by a breakthrough in understanding the neurobiological constructs of the mammalian retina [19], new models and a modeling framework [20] have been developed based on CNNs. Their implementation in Complex Cell CNN Universal Machines [24] are under construction. Studies in complexity related to CNN models and implementations have been emerging recently. Following the groundbreaking theoretical studies of Turing on the morphogenesis of CNN-like coupled nonlinear units [21] and a few experimental case studies of the well-publicized “complex systems”, as well as many exotic waves generated by coupled A template CNNs, the root of complexity in pattern formation at the edge of chaos has been discovered [22]. As far as the computational complexity is concerned, the study of a new quality of computational complexity has been explored [25], showing qualitatively different properties compared to the classical digital complexity theory as well as the com­ plexity on reals [30]. To further explore the vast amount of literature on CNN technology and analogic cellular computing, the interested reader could consult the bibliography at the Website of the Technical Committee on Cellular Neural Networks and Array Computing of the IEEE Circuits and Systems Society (http://www.ieee­ cas.org/~cnnactc), some recent monographs [26, 27, 28], and an undergraduate textbook [29].

References [1] L. O. Chua and L. Yang, “Cellular neural networks: Theory,” IEEE Trans. Circuits Syst., vol. 35, pp. 1257–1272, 1988;. [2] L. O. Chua and L. Yang, “Cellular neural networks: Applications,” IEEE Trans. Circuits Syst., vol. 35, pp. 1273–1290, 1988. [3] L. O. Chua and T. Roska, “The CNN paradigm,” IEEE Trans. Circuits Syst., I vol. 40, pp. 147–156, 1993. [4] J. Cruz and L. O. Chua, “A CNN chip for connected component detection,” IEEE Trans. Circuits Syst., vol. 38, pp. 812–817, 1991. [5] R. Dominguez-Castro, S. Espejo, A. Rodriguez-Vazquez, and R. Carmona, “A CNN Universal Chip in CMOS Technology,” Proc. IEEE 3rd Int. Workshop on CNN and Applications, (CNNA-94), Rome, pp. 91–96, 1994. [6] H. Harrer, J.A. Nossek, and R. Stelzl, “An analog implementation of discrete-time cellular neural networks,” IEEE Trans. Neural Networks, vol. 3, pp. 466–476, 1992. [7] J. A. Nossek and T. Roska, Eds. Special Issues on Cellular Neural Networks, IEEE Trans. Circuits Syst. I, vol. 40, Mar. 1993; Special Issue on Cellular Neural Networks, IEEE Trans. Circuits Syst. II, vol. 40, Mar. 1993.

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[8] T. Roska, and L. O. Chua, “The CNN universal machine: An analogic array computer,” IEEE Trans. Circuits Syst. II, vol. 40, pp. 163–173, 1993. [9] T. Roska, J. Hamori, E. Labos, K. Lotz, K. Takacs, P. Venetianer, Z. Vidnyanszki, and A. Zarandy. “The use of CNN models in the subcortical visual pathway,” IEEE Trans. Circuits Syst., I, vol. 40, pp. 182–195, 1993. [10] T. Roska and J. Vandewalle, Eds., Cellular Neural Networks. Chischester: Wiley, 1993. [11] CANDY (CNN Analogic Nonlinear Dynamics) Simulator, guide and program (student Version) http://lab.analogic.sztaki.hu. [12] F. Werblin, T. Roska, L.O. Chua, “The analogic cellular neural network as a bionic eye”, Int. J. CircuitTheory and Applications, (CTA), Vol.23. N.6. pp. 541-569, 1995. [13] G. Linán, S. Espejo, R. Dominguez-Castro, E. Roca, and A.Rodriguez-Vázquez, “CNNUC3: A mixed signal 64x64 CNN Universal Chip”, Proceedings of MicroNeuro, pp. 61-68, 1999. [14] A. Paasio, A. Davidzuk, K. Halonen, and V. Porra, “Minimum-size 0.5 micron CMOS Program­ mable 48 by 48 Test Chip”, Proceedings of ECCTD 97, pp.154-156, 1997. [15] T. Roska, Á. Zarándy, S. Zöld, P. Földesy and P. Szolgay, “The Computational Infrastructure of Analogic CNN Computing — Part I: The CNN-UM Chip Prototyping System”, IEEE Trans. on Circuits and Systems I: Special Issue on Bio-Inspired Processors and Cellular Neural Networks for Vision, (CAS-I Special Issue), vol. 46, No.2, pp. 261-268, 1999. [16] T. Roska, L. O. Chua, D. Wolf, T. Kozek, R. Tetzlaff, and F. Puffer, “ Simulating Nonlinear Waves and Partial Differential Equations via CNN”, IEEE Trans. on Circuits and Systems I,vol.42, pp. 807­ 815, 1995. [17] T. Roska, “Computer-Sensors: spatial-temporal computers for analog array signals, dynamically integrated with sensors”, J. VLSI Signal Processing Systems, vol. 23, pp. 221-238, 1999. [18] W. C. Yen, C. Y. Wu, “The Design of Neuron-Bipolar Junction Transistor (vBJT) Cellular Neural Network (CNN) Structure with Multi-Neighborhood-Layer Templates”, Proceedings of IEEE Int. Workshop on Cellular Neural Networks and Their Applications, (CNNA’2000), pp. 195-200, 2000. [19] B. Roska and F. S. Werblin, “Vertical interactions across ten parallel, stacked representations in the mammalian retina”, Nature, vol. 410, pp.583-587, March 29, 2001. [20] F. Werblin, B. Roska, D. Bálya, Cs. Rekeczky, T. Roska, “Implementing a Retinal Visual Language in CNN: a Neuromorphic Case Study”, Proceedings of IEEE ISCAS 2001, Vol. III, pp.333-336, 2001. [21] A. M. Turing, “The chemical basis of morphogenesis”, Philos.Trans. R. Soc., London, vol. B237, pp. 37-72, 1952. [22] L. O. Chua, CNN: A Paradigm for Complexity, World Scientific, Singapore, 1998. [23] Cs. Rekeczky and L. O. Chua, “Computing with Front Propagation- Active Contours and Skeleton Models in Continuous-time CNN”, J. VLSI Signal Processing Systems, vol. 23, pp. 373-402, 1999. [24] Cs. Rekeczky, T. Serrano, T. Roska, and Á. Rodríguez-Vázquez, “A stored program 2nd order/3­ layer Complex Cell CNN-UM”, Proceedings of IEEE Int.Workshop on Cellular Neural Networks and Their Applications (CNNA-2000), pp.15-20, 2000. [25] T. Roska, “AnaLogic Wave Computers – Wave-type Algorithms: Canonical Description, Computer Classes, and Computational Complexity”, Proceedings of IEEE ISCAS 2001, vol. III, pp.41-44, 2001. [26] G. Manganaro, P. Arena, and L. Fortuna, Cellular Neural Networks – Chaos, Complexity and VLSI Processing, Springer, Berlin, 1999. [27] M. Hänggi and G. Moschitz, Cellular Neural Networks – Analysis, Design and Optimization, Kluwer Academic Publishers, Boston, 2000. [28] T. Roska and Á. Rodríguez-Vázquez (eds), Towards the Visual Microprocessor – VLSI Design and the Use of Cellular Neural Network Universal Machine, J. Wiley, New York, 2001. [29] L. O. Chua and T. Roska, Cellular Neural Network and Visual Computing — Foundations and Applications, Cambridge University Press, New York, 2002. [30] L. Blum, F. Cucker, M. Shub, and S. Smale, Complexity and Real Computation, Springer, New York, 1998.

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40 Bifurcation and Chaos

40.1 Introduction to Chaos Electrical and Electronic Circuits as Dynamical Systems • Classification and Uniqueness of Steady-State Behaviors • Stability of Steady-State Trajectories • Horseshoes and Chaos • Structural Stability and Bifurcations

40.2 Chua’s Circuit: A Paradigm for Chaos Dynamics of Chua’s Circuit • Chaos in Chua’s Circuit • SteadyStates and Bifurcations in Chua’s Circuit • Manifestations of Chaos • Practical Realization of Chua’s Circuit • Experimental Steady-State Solutions • Simulation of Chua’s Circuit • Dimensionless Coordinate and the α–β Parameter-Space Diagram

40.3 Chua’s Oscillator State Equations • Topological Conjugacy • Eigenvalues-toParameters Mapping Algorithm for Chua’s Oscillator • Example: Torus

40.4 Van der Pol Neon Bulb Oscillator Winding Numbers • The Circle Map • Experimental Observations of Mode-Locking and Chaos in van der Pol’s Neon Bulb Circuit • Circuit Model

40.5 Synchronization of Chaotic Circuits Linear Mutual Coupling • Pecora–Carroll Drive-Response Concept

40.6 Applications of Chaos

Michael Peter Kennedy University College, Dublin Ireland

Pseudorandom Sequence Generation • Spread-Spectrum and Secure Communications • Vector Field Modulation • Example: Communication via Vector Field Modulation Using Chua’s Circuits • Miscellaneous

40.1 Introduction to Chaos Electrical and Electronic Circuits as Dynamical Systems A system is something having parts that may be perceived as a single entity. A dynamical system is one that changes with time; what changes is the state of the system. Mathematically, a dynamical system consists of a space of states (called the state space or phase space) and a rule, called the dynamic, for determining which state corresponds at a given future time to a given present state [8]. A deterministic dynamical system is one where the state, at any time, is completely determined by its initial state and dynamic. In this section, we consider only deterministic dynamical systems. A deterministic dynamical system may have a continuous or discrete state space and a continuoustime or discrete-time dynamic.

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A lumped1 circuit containing resistive elements (resistors, voltage and current sources) and energystorage elements (capacitors and/or inductors) may be modeled as a continuous-time deterministic dynamical system in n. The evolution of the state of the circuit is described by a system of ordinary differential equations called state equations. Discrete-time deterministic dynamical systems occur in electrical engineering as models of switchedcapacitor and digital filters, sampled phase-locked loops, and sigma–delta modulators. Discrete-time dynamical systems also arise when analyzing the stability of steady-state solutions of continuous-time systems. The evolution of a discrete-time dynamical system is described by a system of difference equations. Continuous-Time Dynamical Systems Theorem 1: (Existence and Uniqueness of Solution for a Differential Equation) Consider a continuoustime deterministic dynamical system defined by a system of ordinary differential equations of the form

(

X˙ (t ) = F X(t ), t

)

(40.1)

where X(t)∈n is called the state, X˙ (t ) denotes the derivative of X(t) with respect to time, X(t 0 ) = X 0 is called the initial condition, and the map F(·,·):n × + → n is (i) continuous almost everywhere 2 on n × + and (ii) globally Lipschitz3 in X. Then, for each (X0, t0) ∈ n × +, there exists a continuous function φ(·; X0, t0): + → n such that φ(t 0 ; X 0 , t 0 ) = X 0 and

(

φ˙ (t; X 0 , t 0 ) = F φ (t; X 0 , t 0 ), t

)

(40.2)

Furthermore, this function is unique. The function φ(·; X0, t0) is called the solution or trajectory (X0, t0) of the differential equation (40.1). The image {φ(t; X0, t0)∈nt∈+}of the trajectory through (X0, t0) is a continuous curve in n called the orbit through (X0, t0). F(·, ·) is called the vector field of (40.1) because its image F(X, t) is a vector that defines the direction and speed of the trajectory through X at time t. The vector field F generates the flow φ, where φ(·;·,·):+ × n × + → n is a collection of continuous maps {φ(t ;·,·):n × + → nt∈+}. In particular, a point X0 ∈n at t0 is mapped by the flow into X(t ) = φt (t ; X 0 , t 0 ) at time t. Autonomous Continuous-Time Dynamical Systems If the vector field of a continuous-time deterministic dynamical system depends only on the state and is independent of time t, then the system is said to be autonomous and may be written as

[

]

X˙ (t ) = F X(t ) 1

A lumped circuit is one with physical dimensions that are small compared with the wavelengths of its voltage and current waveforms [2]. 2By continuous almost everywhere, we mean the following: let D be a set in  that contains a countable number + of discontinuities and for each X ∈n, assume that the function t∈+\D → F(X, t)∈n is continuous and for any τ ∈D the left-hand and right-hand limits F(X, τ–) and F(X, τ+), respectively, are finite in n [1]. This condition includes circuits that contain switches and/or squarewave voltage and current sources. 3There is a piecewise continuous function k(·):  →  such that F(X, t) – F(X′, t) ≤ k(t) X – X′, ∀t∈ , + + + ∀X, X′ ∈n. © 2003 by CRC Press LLC

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φt

φt (Br(X0))

Br(X0) X0

φt (X0)

Bε(X0)

φt (Bε(X0))

FIGURE 40.1 The vector field F of an autonomous continuous-time dynamical system generates a flow φ that maps a point X 0 in the state space to its image φt (X0) t seconds later. A volume of state space Br (X0) evolves under the flow into a region φt [Br (X0)]. Sufficiently close to the trajectory φt (X0), the linearized flow maps a sphere of radius ε into an ellipsoid.

or simply X˙ = F( X )

(40.3)

If, in addition, the vector field F(·): n → n is Lipschitz 4, then there is a unique continuous function φ(·, X0): + → n (called the trajectory through X0), which satisfies,

[

]

φ˙ (t, X 0 ) = F φ (t, X 0 ) ,

φ(t 0 , X 0 ) = X 0

(40.4)

Because the vector field is independent of time, we choose t0 ≡ 0. For shorthand, we denote the flow by φ and the map φ(t,·): n → n by φt . The t-advance map φt takes a state X0 ∈n to state X(t) = φt (X0) t seconds later. In particular, φ0 is the identity mapping. Furthermore, φt+s = φt φs, because the state Y = φs(X) to which X evolves after time s evolves after an additional time t into the same state Z as that to which X evolves after time t + s:

[

]

Z = φt (Y ) = φt φs ( X ) = φt +s ( X ) A bundle of trajectories emanating from a ball Br (X 0 ) of radius r centered at X 0 is mapped by the flow into some region φt [Br (X 0 )] after t seconds (see Fig. 40.1). Consider a short segment of the trajectory φt (X 0 ) along which the flow is differentiable with respect to X: in a sufficiently small neighborhood of this trajectory, the flow is almost linear, so the ball Bε(X0) of radius ε about X0 evolves into an ellipsoid φt[Bε(X0)], as shown. An important consequence of Lipschitz continuity in an autonomous vector field and the resulting uniqueness of solution of (40.3) is that a trajectory of the dynamical system cannot go through the same point twice in two different directions. In particular, no two trajectories may cross each other; this is called the noncrossing property [18]. Nonautonomous Dynamical Systems A nonautonomous, n-dimensional, continuous-time dynamical system may be transformed to an (n + 1)­ dimensional autonomous system by appending time as an additional state variable and writing

[

]

X˙ (t ) = F X(t ), X n+1 (t ) X˙ n+1 (t ) = 1 4

There exists a finite k∈n such that F(X) – F(X′) ≤ k X – X′, ∀X, X′ ∈n.

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(40.5)

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In the special case where the vector field is periodic with period T, as for example in the case of an oscillator with sinusoidal forcing, the periodically forced system (40.5) is equivalent to the (n + 1)st order autonomous system

(

X˙ (t ) = F X(t ), θ(t )T

) (40.6)

1 θ˙ (t ) = T

where θ(t) = Xn+1 /T. By identifying the n-dimensional hyperplanes corresponding to θ = 0 and θ = 1, the state space may be transformed from n × + into an equivalent cylindrical state space n × S1, where S1 denotes the circle. In the new coordinate system, the solution through (X0, t0) of (40.6) is  X(t )   φ ( X , t )  t 0 0   =   θ 1 (t )  t T mod 1  S  where θ(t) ∈+ is identified with a point on S 1 (which has normalized angular coordinate θS1 (t)∈[0, 1)) via the transformation θS1(t) = θ(t) mod 1. Using this technique, periodically forced nonautonomous systems can be treated like autonomous systems. Discrete-Time Dynamical Systems Consider a discrete-time deterministic dynamical system defined by a system of difference equations of the form

(

X(k + 1) = G X(k ), k

)

(40.7)

where X(k)∈n is called the state, X(k0 ) = X 0 is the initial condition, and G(·,·): n × + → n maps the current state X(k) into the next state X(k + 1), where k0 ∈+. By analogy with the continuous-time case, there exists a function φ(·,X0,k0):+ → n such that φ(k0 ; X 0 , k0 ) = X 0 and

(

φ(k + 1; X 0 , k0 ) = G φ(k; X 0 , k0 ), k

)

The function φ(·; X0, k0): + → n is called the solution or trajectory through (X 0 , k0 ) of the difference equation (40.7). The image {φ(k; X0, k0) ∈n k ∈+} in n of the trajectory through (X 0 , k0 ) is called an orbit through (X 0 , k0 ). If the map G(⋅ , ⋅) of a discrete-time dynamical system depends only on the state X(k) and is independent of k then the system is said to be autonomous and may be written more simply as X k+1 = G ( X k )

(40.8)

where Xk is shorthand for X(k) and the initial iterate k0 is chosen, without loss of generality, to be zero. Using this notation, Xk is the image X0 after k iterations of the map G(·): n → n. Example: Nonlinear Parallel RLC Circuit. Consider the parallel RLC circuit in Fig. 40.2. This circuit contains a linear inductor L, a linear capacitor C2, and a nonlinear resistor NR′, where the continuous piecewise-linear driving-point (DP) characteristic (see Fig. 40.3) has slope Ga′ for VR′ ≤ E and slope G ′b for VR′ > E. The DP characteristic of N R′ may be written explicitly © 2003 by CRC Press LLC

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C2

L I3

I′R

+

+

V2

V′R

−

−

N′R

FIGURE 40.2 Parallel RLC circuit where the nonlinear resistor N R′ has a DP characteristic as illustrated in Fig. 40.3. By Kirchhoff ’s voltage law, VR′ = V2.

I′R

I′R

G′b

G′a

G′b

−E

0′

−E ′ VR

E

G′b

(a)

G′b

G′a 0′

E

′ VR

(b)

FIGURE 40.3 DP characteristic of NR′ in Fig. 40.2 when (a) Ga′ and (b) G a′ > 0.

I R′ (VR′ ) = Gb′VR′ +

1 2

(G′a − G′b ) ( VR′ + E − VR′ − E )

This circuit may be described by a pair of ordinary differential equations and is therefore a secondorder, continuous-time dynamical system. Choosing I 3 and V2 as state variables, we write dI 3 1 = − V2 dt L dV2 1 1 = I − I ′ (V ) dt C2 3 C2 R 2 with I3(0) = I30 and V2(0) = V20. We illustrate the vector field by drawing vectors at uniformly-spaced points in the two-dimensional state space defined by (I3, V2). Starting from a given initial condition (I30, V20), a solution curve in state space is the locus of points plotted out by the state as it moves through the vector field, following the direction of the arrow at every point. Fig. 40.4 illustrates typical vector fields and trajectories of the circuit. If L, C2, and Gb′ are positive, the steady-state behavior of the circuit depends on the sign of Ga′ . When Ga′ > 0, the circuit is dissipative everywhere and all trajectories collapse toward the origin. The unique steady-state solution of the circuit is the stable dc equilibrium condition I3 = V2 = 0. If Ga′ > 0, NR′ looks like a negative resistor close to the origin and injects energy into the circuit, pushing trajectories away. Further out, where the characteristic has positive slope, trajectories are pulled in by the dissipative vector field. The resulting balance of forces produces a steady-state orbit called a limit cycle, which is approached asymptotically by all initial conditions of this circuit. This limit cycle is said to be attracting because nearby trajectories move toward it and is structurally stable in the sense that, for almost all values of Ga′, a small change in the parameters of the circuit has little effect on it. In the special case when Ga′ ≡ 0, a perturbation of Ga′ causes the steady-state behavior to change from an equilibrium point to a limit cycle; this is called a bifurcation. In the following subsections, we consider in detail steady-state behaviors, stability, structural stability, and bifurcations. © 2003 by CRC Press LLC

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(a)

(b)

FIGURE 40.4 Vector fields for the nonlinear RLC circuit in Fig. 40.2. L = 18 mH, C2 = 100 nF, E = 0.47 V. (a) G ′a = 242.424 µS, Gb′ = 1045.455 µS: all trajectories converge to the origin (b) G a′ = –257.576 µS, G b′ = 545.455 µS: the unique steady-state solution is a limit cycle. Horizontal axis: I3, 400 µA/div; vertical axis: V2, 200 mV/div. Source: M. P. Kennedy, “Three steps to chaos — Part I: Evolution,” IEEE Trans. Circuits Syst. I, vol. 40, p. 647, Oct. 1993. © 1993 IEEE.

Classification and Uniqueness of Steady-State Behaviors A trajectory of a dynamical system from an initial state X0 settles, possibly after some transient, onto a set of points called a limit set. The -limit set corresponds to the asymptotic behavior of the system as t → +∞ and is called the steady-state response. We use the idea of recurrent states to determine when the system has reached steady-state. A state X of a dynamical system is called recurrent under the flow φ if, for every neighborhood Bε(X) of X and for every T > 0, there is a time t > T such that φt(X) I Bε(X) ≠ ∅. Thus, a state X is recurrent if, by waiting long enough, the trajectory through X repeatedly returns arbitrarily close to X [7]. Wandering points correspond to transient behavior, while steady-state or asymptotic behavior corre­ sponds to orbits of recurrent states. A point Xω is an ω-limit point of X 0 if and only if lim k→+∞ φtk (X 0 ) = X ω for some sequence {tkk∈+ such that tk → +∞. The set L(X0) of ω-limit points of X0 is called ω-limit set of X0.5 A limit set L is called attracting if there exists a neighborhood U of L such that L(X)0 = L for all X 0 ∈U. Thus, nearby trajectories converge toward an attracting limit set as t → ∞. An attracting set  that contains at least one orbit that comes arbitrarily close to every point in  is called an attractor [7]. In an asymptotically stable linear system the limit set is independent of the initial condition and unique so it makes sense to talk of the steady-state behavior. By contrast, a nonlinear system may possess several different limit sets and therefore may exhibit a variety of steady-state behaviors, depending on the initial condition. The set of all points in the state space that converge to a particular limit set L is called the basin of attraction of L. Because nonattracting limit sets cannot be observed in physical systems, the asymptotic or steady-state behavior of a real electronic circuit corresponds to motion on an attracting limit set.

The set of points to which trajectories converge from X0 as t → –∞ is called the α-limit set of X0. We consider only positive time, therefore, by limit set, we mean the ω-limit set. 5

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Equilibrium Point The simplest steady-state behavior of a dynamical system is an equilibrium point. An equilibrium point or stationary point of (40.3) is a state XQ at which the vector field is zero. Thus, F(XQ) = 0 and φt (XQ) = XQ; a trajectory starting from an equilibrium point remains indefinitely at that point. In state space, the limit set consists of a single nonwandering point XQ. A point is a zero-dimensional object. Thus, an equilibrium point is said to have dimension zero. In the time domain, an equilibrium point of an equilibrium circuit is simply a dc solution or operating point. An equilibrium point or fixed point of a discrete-time dynamical system is a point XQ that satisfies

( )

G XQ = XQ Example: Nonlinear Parallel RLC Circuit. The nonlinear RLC circuit shown in Fig. 40.2 has just one equilibrium point (I3Q, V2Q ) = (0,0). When Ga′ is positive, a trajectory originating at any point in the state converges to this attracting dc steady-state [as shown in Fig. 40.4(a)]. The basin of attraction of the origin is the entire state space. All trajectories, and not just those that start close to it, converge to the origin, so this equilibrium point is said to be a global attractor. When Ga′ < 0, the circuit possesses two steady-state solutions: the equilibrium point at the origin, and the limit cycle Γ. The equilibrium point is unstable in this case. All trajectories, except that which starts at the origin, are attracted to Γ. Periodic Steady-State A state X is called periodic if there exists T > 0 such that φT (X) = X. A periodic orbit which is not a stationary point is called a cycle. A limit cycle Γ is an isolated periodic orbit of a dynamical system [see Fig. 40.5(b)]. The limit cycle trajectory visits every point on the simple closed curve Γ with period T. Indeed, φt (X) = φt+T (X)∀ X ∈Γ. Thus, every point on the limit cycle Γ is a nonwandering point. A limit cycle is said to have dimension one because a small piece of it looks like a one-dimensional object: a line. Then, n components X i (t ) of a limit cycle trajectory X(t) = [X1(t), X2(t), …, Xn(t)]T in n are periodic time waveforms with period T. Every periodic signal X(t) may be decomposed into a Fourier series — a weighted sum of sinusoids at integer multiples of a fundamental frequency. Thus, a periodic signal appears in the frequency domain as a set of spikes at integer multiples (harmonics) of the fundamental frequency. The amplitudes of these spikes correspond to the coefficient in the Fourier series expansion of X(t). The Fourier transform is an extension of these ideas to aperiodic signals; one considers the distribution of the signal’s power over a continuum of frequencies rather than on a discrete set of harmonics. The distribution of power in a signal X(t) is most commonly quantified by means of the power density spectrum, often simply called the power spectrum. The simplest estimator of the power spectrum is the periodogram [17], which given N uniformly spaced samples X(k/fs), k = 0, 1, …, N – 1 of X (t), yields N/2 + 1 numbers P(nfs/N), n = 0, 1, …, N/2, where fs is the sampling frequency. If one considers the signal X(t) as being composed of sinusoidal components at discrete frequencies, then P(nfs /N) is an estimate of the power in the component at frequency nfs /N. By Parseval’s theorem, the sum of the power in each of these components equals the mean squared amplitude of the N samples of X(t) [17]. If X(t) is periodic with period T, then its power will be concentrated in a dc component, a fundamental frequency component 1/T, and harmonics. In practice, the discrete nature of the sampling process causes power to “leak” between adjacent frequency components; this leakage may be reduced by “windowing” the measured data before calculating the periodogram [17].

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6 4 2 0 −2 −4 −6

V1

0

5

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0

−20

−40

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I3

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−80

−100

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0.5

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2.5

(a) 6

4

2

0

−2

−4

−6

0

V1

5

10

15

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25

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−20

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I3

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−80

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0

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(b) 6

4

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−2

−4

−6

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V1

5

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35

40

45

50

0 −20 −40

V2

I3

−60 −80 −100

0

0.5

1

1.5

2

2.5

(c)

FIGURE 40.5 Quasiperiodicity (torus breakdown) route to chaos in Chua’s oscillator. Simulated state space trajec­ tories, time waveforms V1(t), and power spectra of V2(t). (a) Quasiperiodic steady-state — the signal is characterized by a discrete power spectrum with incommensurate frequency components; (b) periodic window — all spikes in the power spectrum are harmonically related to the fundamental frequency; (c) chaotic steady-state following breakdown of the torus — the waveform has a broadband power spectrum. Time plots; horizontal axis — t (ms); vertical axis — V1(V). Power spectra: horizontal axis — frequency (kHz); vertical axis — power (mean squared amplitude) of V2(t) (dB).

Example: Periodic Steady-State Solution. Figure 40.5(b) depicts a state-space orbit, time waveform, and power spectrum of a periodic steady-state solution of a third-order, autonomous, continuous-time dynam­ ical system. The orbit in state space is an asymmetric closed curve consisting of four loops. In the time domain, the waveform has four crests per period and a dc offset. In the power spectrum, the dc offset manifests itself as a spike at zero frequency. The period of approximately 270 Hz produces a fundamental component at that frequency. Notice that the fourth harmonic (arising from “four crests per period”) has the largest magnitude. This power spectrum is reminiscent of subharmonic mode locking in a forced oscillator. © 2003 by CRC Press LLC

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Subharmonic Periodic Steady-State A subharmonic periodic solution or period-K orbit of a discrete-time dynamical system is a set of K points {X1, X2, …, Xk} that satisfy X 2 = G ( X1 )

X 3 = G ( X 2 )…X K = G ( X K −1 )

X1 = G ( X K )

More succinctly, we may write Xi = G(K)(Xi), where G(K) = G[G(L[G(·)]L)] denotes G applied K times to the argument of the map; this is called Kth iterate of G. Subharmonic periodic solutions occur in systems that contain two or more competing frequencies, such as forced oscillators or sampled-data circuits. Subharmonic solutions also arise following perioddoubling bifurcations (see the section on structural stability and bifurcations). Quasiperiodic Steady-State The next most complicated form of steady-state behavior is called quasiperiodicity. In state space, this corresponds to a torus [see Fig. 40.5(a)]. Although a small piece of a limit cycle in 3 looks like a line, a small section of two-torus looks like a plane; a two-torus has dimension two. A quasiperiodic function is one that may be expressed as a countable sum of periodic functions with incommensurate frequencies, i.e., frequencies that are not rationally related. For example, X (t ) = sin(t) + sin(2πt) is a quasiperiodic signal. In the time domain, a quasiperiodic signal may look like an amplitudeor phase-modulated waveform. Although the Fourier spectrum of a periodic signal consists of a discrete set of spikes at integer multiples of a fundamental frequency, that of a quasiperiodic solution comprises a discrete set of spikes at incom­ mensurate frequencies, as presented in Fig. 40.5(a). In principle, a quasiperiodic signal may be distinguished from a periodic one by determining whether the frequency spikes in the Fourier spectrum are harmonically related. In practice, it is impossible to determine whether a measured number is rational or irrational; therefore, any spectrum that appears to be quasiperiodic may simply be periodic with an extremely long period. A two-torus in a three-dimensional state space looks like a doughnut. Quasiperiodic behavior on a higher dimensional torus is more difficult to visualize in state space but appears in the power spectrum as a set of discrete components at incommensurate frequencies. A K-torus has dimension K. Quasiperiodic behavior occurs in discrete-time systems where two incommensurate frequencies are present. A periodically-forced or discrete-time dynamical system has a frequency associated with the period of the forcing or sampling interval of the system; if a second frequency is introduced that is not rationally related to the period of the forcing or the sampling interval, then quasiperiodicity may occur. Example: Discrete Torus. Consider a map from the circle S1 onto itself. In polar coordinates, a point on the circle is parameterized by an angle θ. Assume that θ has been normalized so that one complete revolution of the circle corresponds to a change in θ of 1. The state of this system is determined by the normalized angle θ and the dynamics by θk+1 = (θk + Ω) mod1 If Ω is a rational number (of the form J/K where J, K ∈ +), then the steady-state solution is a period-K (subharmonic) orbit. If Ω is irrational, we obtain quasiperiodic behavior. Chaotic Steady-State DC equilibrium periodic as well as quasiperiodic steady-state behaviors have been correctly identified and classified since the pioneering days of electronics in the 1920s. By contrast, the existence of more exotic steady-state behaviors in electronic circuits has been acknowledged only in the past 30 years. Although the notion of chaotic behavior in dynamical systems has existed in the mathematics literature since the turn of the century, unusual behaviors in the physical sciences as recently as the 1960s were © 2003 by CRC Press LLC

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described as “strange.” Today, we classify as chaos the recurrent6 motion in a deterministic dynamical system, which is characterized by a positive Lyapunov exponent. From an experimentalist’s point of view, chaos may be defined as bounded steady-state behavior in a deterministic dynamical system that is not an equilibrium point, nor periodic, and not quasiperiodic [15]. Chaos is characterized by repeated stretching and folding of bundles of trajectories in state space. Two trajectories started from almost identical initial conditions diverge and soon become uncorrelated; this is called sensitive dependence on initial conditions and gives rise to long-term unpredictability. In the time domain, a chaotic trajectory is neither periodic nor quasiperiodic, but looks “random.” This “randomness” manifests itself in the frequency domain as a broad “noise-like” Fourier spectrum, as presented in Fig. 40.5(c). Although an equilibrium point, a limit cycle, and a K-torus each have integer dimension, the repeated stretching and folding of trajectories in a chaotic steady state gives the limit set a more complicated structure that, for three-dimensional continuous-time circuits, is something more than a surface but not quite a volume. Dimension The structure of a limit set L ⊂ n of a dynamical system may be quantified using a generalized notion of dimension that considers not just the geometrical structure of the set, but also the time evolution of trajectories on L. Capacity (D0 Dimension). The simplest notion of dimension, called capacity (or D0 dimension) considers a limit set simply as set of points, without reference to the dynamical system that produced it. To estimate the capacity of L, cover the set with n-dimensional cubes having side length ε. If L is a D0-dimensional object, then the minimum number N(ε) of cubes required to cover L is proportional to ε –D0. Thus, N(ε) α ε–D0. The D0 dimension is given by D0 = lim− ε→0

ln N (ε) ln ε

When this definition is applied to a point, a limit cycle (or line), or a two-torus (or surface) 3, the calculated dimensions are 0, 1, and 2, respectively, as expected. When applied to the set of nonwandering points that comprise a chaotic steady state, the D0 dimension is typically noninteger. An object that has noninteger dimension is called a fractal. Example: The Middle-Third Cantor Set. Consider the set of points that is obtained by repeatedly deleting the middle third of an interval, as indicated in Fig. 40.6(a). At the first iteration, the unit interval is divided into 21 pieces of length 1/3 each; after k iterations, the set is covered by 2k pieces of length 1/3k. By contrast, the set that is obtained by dividing the intervals into thirds but not throwing away the middle third each time [Fig. 40.6(b)] is covered at the kth step by 3k pieces of length 1/3k. Applying the definition of capacity, the dimension of the unit interval is lim

k→∞

k ln 3 = 1.00 k ln 3

By contrast, the middle-third Cantor set has dimension lim

k→∞

k ln 2 ≈ 0.63 k ln 3

6Because a chaotic steady-state does not settle down onto a single well-defined trajectory, the definition of recurrent states must be used to identify posttransient behavior.

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N(ε)

ε

N(ε)

20

30

30

21

3−1

31

22

3−2

32

23

3−3

33

24

3−4

34

(a)

(b)

FIGURE 40.6 (a) The middle-third Cantor set is obtained by recursively removing the central portion of an interval. At the kth step, the set consists of N(ε) = 2k pieces of length ε = 3–k. The limit set has capacity 0.63. (b) By contrast, the unit interval is covered by 3k pieces of length 3–k. The unit interval has dimension 1.00.

(a)

(b)

FIGURE 40.7 Coverings of two limit sets La (a) and Lb (b) with squares of sidelength ε0 and ε0/2, respectively.

The set is something more than a zero-dimensional object (a point) but not quite one-dimensional (like a line segment); it is a fractal. Correlation (D2 ) Dimension. The D2 dimension considers not just the geometry of a limit set, but also the time evolution of trajectories on the set. Consider the two limit sets La and Lb in 2 shown in Fig. 40.7(a) and (b), respectively. The D0 dimension of these sets may be determined by iteratively covering them with squares (two-dimensional “cubes”) of sidelength ε = ε0 /2k, k = 0, 1, 2, …, counting the required number of squares N(ε) for each ε, and evaluating the limit D0 =

ln N (ε) lim − ln(ε) k→∞

For the smooth curve La, the number of squares required to cover the set grows linearly with 1/ε; hence D0 = 1.0. By contrast, if the kinks and folds in set Lb are present at all scales, then the growth of N(ε) versus 1/ε is superlinear and the object has a noninteger D0 dimension between 1.0 and 2.0. © 2003 by CRC Press LLC

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Imagine now that La and Lb are not simply static geometrical objects but are orbits of discrete-time dynamical systems. In this case, a steady-state trajectory corresponds to a sequence of points moving around the limit set. Cover the limit set with the minimum number N(ε) of “cubes” with sidelength ε, and label the boxes 1, 2…, i, …, N(ε). Count the number of times ni (N, ε) that a typical steady-state trajectory of length N visits box i and define n i (N, ε) N

pi = lim

N→∞

where pi is the relative frequency with which a trajectory visits the ith cube. The D2 dimension is defined as N (ε)

ln D2 = lim

∑p

2 i

i=1

ln ε

ε→0

In general, D2 ≤ D0 with equality when a typical trajectory visits all N(ε) cubes with the same relative frequency p = 1/N(ε). In this special case, N (ε)

ln D2 = lim

ε→0

2

i=1

ln ε

ε→0

= lim−

∑ N (1ε)

ln N (ε) ln ε

= D0 An efficient algorithm (developed by Grassberger and Procaccia) for estimating D2 is based on the 2 1 ---approximation Σ N(ε) 2 (the number of pairs of points (Xi , Xj ) such i=1 p i ≈ C(ε) [15], where C(ε) = lim N→0 N that Xi – Xj  < ε) is called the correlation. The D2 or correlation dimension is given by D2 = lim ε→0

lnC (ε) ln ε

Example: Correlation (D2) Dimension. The correlation dimension of the chaotic attractor in Fig. 40.5(c), estimated using INSITE, is 2.1, 2 while D2 for the uniformly covered torus in Fig. 40.5(a) is 2.0.

Stability of Steady-State Trajectories Consider once more the nonlinear RLC circuit in Fig. 40.2. IF Ga′ is negative, this circuit settles to a periodic steady state from almost every initial condition. However, a trajectory started from the origin will, in principle, remain indefinitely at the origin since this is an equilibrium point. The circuit has two possible steady-state solutions. Experimentally, only the limit cycle will be observed. Why? If trajectories starting from states close to a limit set converge to that steady-state, the limit set is called an attracting limit set. If, in addition, the attracting limit set contains at least one trajectory that comes arbitrarily close to every point in the set, then it is an attractor. If nearby points diverge from the limit set, it is called a repellor. In the nonlinear RLC circuit with Ga′ < 0, the equilibrium point is a repellor and the limit cycle is an attractor.

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Stability of Equilibrium Points Qualitatively, an equilibrium point is said to be stable if trajectories starting close to it remain nearby for all future time and unstable otherwise. Stability is a local concept, dealing with trajectories in a small neighborhood of the equilibrium point. To analyze the behavior of the vector field in the vicinity of an equilibrium point XQ, we write X = X Q + x and substitute into (40.3) to obtain

( ) F( X ) + x˙ ≈ F( X ) + D F( X )x X˙ Q + x˙ = F X Q + x Q

Q

x

Q

where we have kept just the first two terms of the Taylor series expansion of F(X) about XQ. The Jacobian matrix D XF(X) is the matrix of partial derivatives of F(X) with respect to X:  ∂Fi ( X )   ∂X1  ∂F2 ( X ) D X F( X ) =  ∂X1   M  ∂Fn ( X )   ∂X1

∂F1 ( X ) ∂X 2 ∂F2 ( X ) ∂X 2 M ∂Fn ( X ) ∂X 2

L L O L

∂F1 ( X )   ∂X n  ∂F2 ( X )   ∂X n  M  ∂Fn ( X )   ∂X n 

Subtracting F(X Q ) from both sides of (40.9) we obtain the linear system

( )

x˙ = D xF X Q x

(40.9)

where the Jacobian matrix is evaluated at XQ. This linearization describes the behavior of the circuit in the vicinity of XQ; we call this the local behavior. Note that the linearization is simply the small-signal equivalent circuit at the operating point XQ. In general, the local behavior of a circuit depends explicitly on the operating point XQ. For example, a pn­ junction diode exhibits a small incremental resistance under forward bias, but a large small-signal resistance under reverse bias. Eigenvalues If XQ is an equilibrium point of (40.3), a complete description of its stability is contained in the eigenvalues of the linearization of (40.3) about XQ. These are defined as the roots λ of the characteristic equation

[

( )]

det λI − D XF X Q = 0

(40.10)

where I is the identity matrix. If the real parts of all of the eigenvalues DxF(XQ) are strictly negative, then the equilibrium point XQ is asymptotically stable and is called a sink because all nearby trajectories converge toward it. If any of the eigenvalues has a positive real part, the equilibrium point is unstable; if all of the eigenvalues have positive real parts, the equilibrium point is called a source. An equilibrium point that has eigenvalues with both negative and positive real parts is called a saddle. A saddle is unstable. An equilibrium point is said to be hyperbolic if all the eigenvalues of DxF(XQ) have nonzero real parts. All hyperbolic equilibrium points are either unstable or asymptotically stable. © 2003 by CRC Press LLC

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WS(XQ) ES(XQ)

XQ

EU(XQ)

WU(XQ)

FIGURE 40.8 Stable and unstable manifolds W s (XQ) and W u (XQ) of an equilibrium point XQ. The stable and unstable eigenspaces E s (XQ) and E u (XQ) derived from the linearization of the vector field at XQ are tangent to the corresponding manifolds W s and W u at XQ. A trajectory approaching the equilibrium point along the stable manifold is tangential to E s (XQ) at XQ; a trajectory leaving XQ along the unstable manifold is tangential to E u (XQ) at XQ.

Discrete-Time Systems The stability of a fixed point XQ of a discrete-time dynamical system X k+1 = G ( X k ) is determined by the eigenvalues of the linearization DXG(XQ) of the vector field G, evaluated at XQ. The equilibrium point is classified as stable if all of the eigenvalues of DXG(XQ) are strictly less than unity in modulus, and unstable if any has modulus greater than unity. Eigenvectors, Eigenspaces, Stable and Unstable Manifolds →

Associated with each distinct eigenvalue λ of the Jacobian matrix DXF(XQ) is an eigenvector v defined by r r D XF X Q ν = λν

( )

→

A real eigenvalue γ has a real eigenvector η. Complex eigenvalues of a real matrix occur in pairs of → → the form σ ± jω. The real and imaginary parts of the associated eigenvectors ηr ± j ηc span a plane called a complex eigenplane. The ns-dimensional subspace of n associated with the stable eigenvalues of the Jacobian matrix is called the stable eigenspace, denoted E s (XQ). The nu-dimensional subspace corresponding to the unstable eigenvalues is called the unstable eigenspace, denoted E u (XQ). The analogs of the stable and unstable eigenspaces for a general nonlinear system are called the local stable and unstable manifolds7 W s(XQ) and Wu(XQ). The stable manifold W s(XQ) is defined as the set of all states from which trajectories remain in the manifold and converge under the flow to XQ. The unstable manifold W u(XQ) is defined as the set of all states from which trajectories remain in the manifold and diverge under the flow from XQ. By definition, the stable and unstable manifolds are invariant under the flow (if X ∈ W s, then φt(X)∈W s). Furthermore, the ns- and nu-dimensional tangent spaces to W s and W u at XQ are E s and E u (as shown in Fig. 40.8). In the special case of a linear or affine vector field F, the stable and unstable manifolds are simply the eigenspaces E s and E u.

An m-dimensional manifold is a geometrical object every small section of which looks like m. More precisely, M is an m-dimensional manifold if, for every x ∈ M, there exists an open neighborhood U of x and a smooth invertible map which takes U to some open neighborhood of m. For example, a limit cycle of a continuous-time dynamical system is a one-dimensional manifold. 7

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WS(XQ2)

XQ2

WU(XQ) ∑ XQ1

XQ

WU(XQ1) WS(XQ)

FIGURE 40.9 (a) A homoclinic orbit joins an isolated equilibrium point XQ to itself along its stable and unstable manifolds. (b) A heteroclinic orbit joins two distinct equilibrium points, XQ1 and XQ2, along the unstable manifolds of one and the stable manifold of the other.

Chaos is associated with two characteristic connections of the stable and unstable manifolds. A homoclinic orbit [see Fig. 40.9(a)] joins an isolated equilibrium point XQ to itself along its stable and unstable manifolds. A heteroclinic orbit [Fig. 40.9(b)] joins two distinct equilibrium points, XQ1 and XQ2, along the unstable manifold of one and the stable manifold of the other. Stability of Limit Cycles Although the stability of an equilibrium point may be determined by considering the eigenvalues of the linearization of the vector field near the point, how does one study the stability of a limit cycle, torus, or chaotic steady-state trajectory? The idea introduced by Poincaré is to convert a continuous-time dynamical system into an equivalent discrete-time dynamical system by taking a transverse slice through the flow. Intersections of trajectories with this so-called Poincaré section define a Poincaré map from the section to themselves. Since the limit cycle is a fixed point XQ of the associated discrete-time dynamical system, its stability may be determined by examining the eigenvalues of the linearization of the Pioncaré map at XQ. Poincaré Sections A Pioncaré section of an n-dimensional autonomus continuous-time dynamical system is an (n – 1)­ dimensional hyperplane ∑ in the state space that is intersected transversally8 by the flow. Let Γ be a closed orbit of the flow of a smooth vector field F, and let XQ be a point of intersection of Γ with ∑. If T is the period of Γ and X ∈ ∑ is sufficiently close to XQ, then the trajectory φt (X) through X will return to ∑ after a time τ(X) ≈ T and intersect the hyperplane at a point φτ(X)(X), as illustrated in Fig. 40.10. This construction implicitly defines a function (called a Poincaré map or first return map) G:U → ∑ G(X) = φτ(X)(X) where U is a small region of ∑ close to XQ. The corresponding discrete-time dynamical system Xk+1 = G(Xk) has a fixed point at XQ. The stability of the limit cycle is determined by the eigenvalues of the linearization DXG(XQ) of G at XQ. If all of the eigenvalues of DXG(XQ) have modulus less than unity, the limit cycle is asymptotically stable; if any has modulus greater than unity, the limit cycle is unstable. 8A transverse intersection of manifolds in n is an intersection of manifolds such that, from any point in the intersection, all directions in n can be generated by linear combinations of vectors tangent to the manifolds.

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U X φτ(x)(X)

∑

XQ Γ

FIGURE 40.10 A transverse Poincaré section ∑ through the flow of a dynamical system induces a discrete Poincaré map from a neighborhood U of the point of intersection XQ to ∑.

FIGURE 40.11 Experimental Poincaré sections corresponding to a torus breakdown sequence in Chua’s oscillator. (a) Torus, (b) period-four orbit, (c) chaotic attractor resulting from torus breakdown. Source: L. O. Chua, C. W. Wu, A. Hung, and G.-Q. Zhong, “A universal circuit for studying and generating chaos — Part I: Routes to chaos,” IEEE Trans. Circuits Syst., vol. 40, pp. 738, 739, Oct. 1993. 1993 IEEE.

Note that the stability of the limit cycle is independent of the position and orientation of the Poincaré plane, provided that the intersection is chosen transverse to the flow. For a nonautonomous system with periodic forcing, a natural choice for the hyperplane is at a fixed phase θo of the forcing. In the Poincaré section, a limit cycle looks like a fixed point. A period-K subharmonic of a nonautono­ mous system with periodic forcing appears as a period-K orbit of the corresponding map [see Fig. 40.11(b)]. The Poincaré section of a quasiperiodic attractor consisting of two incommensurate frequencies looks like a closed curve — a transverse cut through a two-torus [Fig. 40.11(a)]. The Poincaré section of chaotic attractor has fractal structure, as depicted in Fig. 40.11(c).

Horseshoes and Chaos Chaotic behavior is characterized by sensitive dependence on initial conditions. This phrase emphasizes the fact that small differences in initial conditions are persistently magnified by the dynamics of the system so that trajectories starting from nearby initial conditions reach totally different states in a finite time. Trajectories of the nonlinear RLC circuit in Fig. 40.2 that originate near the equilibrium point are initially stretched apart exponentially by the locally negative resistance in the case G ′a < 0. Eventually, however, they are squeezed together onto a limit cycle, so the stretching is not persistent. This is a consequence of the noncrossing property and eventual passivity. Although perhaps locally active, every physical resistor is eventually passive meaning that, for a large enough voltage across its terminals, it dissipates power. This in turn limits the maximum values of the voltages and currents in the circuit giving a bounded steady-state solution. All physical systems are bounded, so how can small differences be magnified persistently in a real circuit?

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G(3)

1 2 3 4 5 G(5)

G(1)

(a)

(b)

(c)

(d)

(e)

(f)

FIGURE 40.12 The Smale horseshoe map stretches the unit square (a), folds it into a horseshoe (b), and lays it back on itself (c), so that only points lying in bands 2 and 4 of (a) are mapped into the square. At the next iteration, only those points in (G(2) ∪ G(4)) ∩ (2 ∪ 4) (d) are mapped back to the square. Repeated iterations of the map (d)–(f) remove all points from the square except an invariant (fractal) set of fixed points.

Chaos in the Sense of Shil’nikov Consider a flow φ in  3 that has an equilibrium point at the origin with a real eigenvalue γ > 0 and a pair of complex conjugate eigenvalues σ ± jω with σ < 0 and ω ≠ 0. Assume that the flow has a homoclinic orbit Γ through the origin. One may define a Poincaré map for this system by taking a transverse section through the homoclinic orbit, as illustrated in Fig. 40.9(a). Theorem 2 (Shil’nikov): If σ/γ < 1, the flow φ can be perturbed to φ′ such that φ′ has a homoclinic orbit Γ′ near Γ and the Poincaré map of φ′ defined in a neighborhood of Γ′ has a countable number of horseshoes in its discrete dynamics. The characteristic horseshoe shape in the Poincaré map stretches and folds trajectories repeatedly (see Fig. 40.12). The resulting dynamics exhibit extreme sensitivity to initial conditions [7]. The presence of horseshoes in the flow of a continuous-time system that satisfies the assumptions of Shil’nikov’s theorem implies the existence of countable numbers of unstable periodic orbits of arbitrarily long period as well as an uncountable number of complicated bounded nonperiodic chaotic solutions [7]. Horseshoes. The action of the Smale horseshoe map is to take the unit square [Fig. 40.12(a)], stretch it, fold it into a horseshoe shape [Fig. 40.12(b)], and lay it down on itself [Fig. 40.12(c)]. Under the action of this map, only four regions of the unit square are returned to the square.

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D1 D0 D−1

X0 P− Er(P−) Ec(P−)

FIGURE 40.13 Stretching and folding mechanism of chaos generation in Chua’s circult. A trajectory spirals away from the equilibrium point P– along the eigenplane E c (P–) until it enters the D0 region, where it is folded back into D–1 and returns to the unstable eigenplane E c (P–) close to P–. Source: M. P. Kennedy, “Three steps to chaos — Part II: A Chua’s circuit primer,” IEEE Trans. Circuits Syst. I, vol. 40, p. 657, Oct. 1993.  1993 IEEE.

Successive iterations of the horseshoe map return smaller and smaller regions of square to itself, as shown in Fig. 34.12(d)–(f). If the map is iterated ad infinitum, the unit square is ultimately mapped onto a set of points. These points form an invariant (fractal) limit set L that contains a countable set of periodic orbits of arbitrarily long periods, an uncountable set of bounded nonperiodic orbits, and at least one orbit that comes arbitrarily close to every point in L. The properties of the map still hold if the horseshoe is distorted by a perturbation of small size but arbitrary shape. Thus, the dynamical behavior of the horseshoe map is structurally stable.9 Although the invariant limit set of a horseshoe map consists of nonwandering points, it is not attracting. Therefore, the existence of a horseshoe in the flow of a third-order system does not imply that the system will exhibit chaotic steady-state behavior. However if a typical trajectory in the Poincaré map remains in a neighborhood of the invariant set, then the system may exhibit chaos. Thus, although Shil’nikov’s theorem is a strong indicator of choas, it does not provide definitive proof that a system is chaotic. Example: Chaos in a Piecewise-Linear System. Although we have stated them for the case σ < 0, γ > 0, Shil’nikov’s theorem also applies when the equilibrium point at the origin has an unstable pair of complex conjugate eigenvalues and a stable real eigenvalue. In that case, it is somewhat easier to visualize the stretching and folding of bundles of trajectories close to a homoclinic orbit. Consider the trajectory in a three-region piecewise-linear vector field in Fig. 40.13. We assume that the equilibrium point P– has a stable real eigenvalue γ1 [where the eigenvector is E r(P–)] and an unstable complex conjugate pair of eigenvalues σ1 ± jω1, the real and imaginary parts of whose eigenvectors span the plane E c(P_) [2], as illustrated. A trajectory originating from a point X0 on E c(P_) spirals away from the equilibrium point along E c(P_) until it enters the D0 region, where it is folded back into D–1. Upon reentering D–1, the trajectory is pulled toward P_ roughly in the direction of the real eigenvector E r(P_), as illustrated. Now imagine what would happen if the trajectory entering D–1 from D0 were in precisely the direction E r (P_). Such a trajectory would follow E r (P_) toward P_, reaching the equilibrium point asymptotically as t → ∞. Similarly, if we were to follow this trajectory backward in time through D0 and back onto E c (P_) in D–1, it would then spiral toward P_, reaching it asymptotically as t → –∞. The closed curve thus formed would be a homoclinic orbit, reaching the same equilibrium point P_ asymptotically in forward and reverse time. Although the homoclinic orbit itself is not structurally stable, and therefore cannot be observed experimentally, horseshoes are structurally stable. A flow φ that satisfies the assumptions of Shil’nikov’s 9

Structural stability is discussed in more detail in the section on structural stability and bifurcations.

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theorem contains a countable infinity of horseshoes; for sufficiently small perturbations φ′ of the flow, finitely many of the horseshoes will persist. Thus, both the original flow and the perturbed flow exhibit chaos in the sense of Shil’nikov. In Fig. 40.13, we see that a trajectory lying close to a homoclinic orbit exhibits similar qualitative behavior: it spirals away from P_ along the unstable complex plane E c (P_), is folded in D0, reenters D–1 above E c (P_), and is pulled back toward E c (P_), only to be spun away from P_ once more. Thus, two trajectories starting from distinct initial states close to P_ on E c (P_) are stretched apart exponentially along the unstable eigenplane before being folded in D1 and reinjected close to P_; this gives rise to sensitive dependence on initial conditions. The recurrent stretching and folding continues ad infinitum, producing a chaotic steady-state solution. Lyapunov Exponents The notion of sensitive dependence on initial conditions may be made more precise through the intro­ duction of Lyapunov exponents (LEs). Lyapunov exponents quantify the average exponential rates of separation of trajectories along the flow. The flow in a neighborhood of asympototically stable trajectory is contracting so the LEs are zero or negative.10 Sensitive dependence on initial conditions results from a positive LE. To determine the stability of an equilibrium point, we considered the eigenvalues of the linearization of the vector field in the vicinity of equilibrium trajectory. This idea can be generalized to any trajectory of the flow. The local behavior of the vector field along a trajectory φt(X0) of an autonomous continuous time dynamical system (40.3) is governed by the linearized dynamics · X = DXF(X)X,

x(0) = x0

= DXF[φt(X0)]x This is a linear time-varying system where the state transition matrix, Φt(X0), maps a point x0 into x(t). Thus, x (t ) = Φt ( X 0 )x 0 Note that Φt is a linear operator. Therefore, a ball Bε(X0) of radius ε about X0 is mapped into an ellipsoid as presented in Fig. 40.1. The principal axes of the ellipsoid are determined by the singular values of Φt . The singular values σ1(t), σ2(t), …, σn(t) of Φt are defined as the square roots of the eigenvalues of Φ Ht Φt , where Φ Ht is the complex conjugate transpose of Φt . The singular values are ordered so that σ1(t)> σ2(t)> … > σn(t). In particular, a ball of radius ε is mapped by the linearized flow into an ellipsoid (see Fig. 40.1) the maximum and minimum radii of which are bounded by σ1(t)ε and σn(t)ε, respectively. The stability of a steady-state orbit is governed by the average local rates of expansion and contraction of volumes of state space close to the orbit. The Lyapunov exponents (LEs) λi , are defined by λ i = lim t→∞

1 ln σ i (t ) t

whenever this limit exists. The LEs quantify the average exponential rates of separation of trajectories along the flow. 10A continuous flow that has a bounded trajectory not tending to an equlibrium point has a zero Lyapunov exponent (in the direction of flow).

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The LEs are a property of a steady-state trajectory. Any transient effect is averaged out by taking the limit as t → ∞. Furthermore, the LEs are global quantities of an attracting set that depend on the local stability properties of a trajectory within the set. The set {λi, i, = 1, 2, …, n} is called the Lyapunov spectrum. An attractor has the property that the sum of its LEs is negative. Lyapunov Exponents of Dicrete-Time Systems. The local behavior along an orbit of the autonomous discrete-time dynamical system (40.8) is governed by the linearized dynamics Xk+1 = DxG(Xk)xk,

k = 0, 1, 2, …

where the state transition matrix, Φk(X0), maps a point x0 into xk. Thus, xk = k(X0)x0 The Lyapunov exponents λi for the discrete-time dynamical system (40.8) are defined by λ i = lim t→∞

1 ln σ i (k ) k

whenever this limit exists. σi(k) denotes the ith singular value of Φ Hk Φk . Lyapunov Exponents of Steady-State Solutions. Consider once more the continuous-time dynamical ˜ system (40.3). If DxF were constant along the flow, with n distinct eigenvalues λi i = 1, 2, …, n, then

( )

 exp λ˜ t 1   0 Φt =   M   0 

0

( )

  0    M  ˜ exp λ n t 

L

exp λ˜ 2 t

L

M

O

0

L

0

( )

and

( ( ))

 exp 2 Re λ˜ t 1   0 ΦtH Φt =   M   0 

0

L

exp 2 Re λ˜ 2 t

L

M

O

0

L

( ( ))

   0   M  exp 2 Re λ˜ n t  

˜ )t) and giving σi(t) = exp(Re(λ i λ i = lim t →∞

[ ( )]

1  ln exp Re λ˜ i t  t 

( )

= Re λ˜ i

In this case, the LEs are simply the real parts of the eigenvalues of DXF.

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( ( ))

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TABLE 40.1 Classification of Steady-State Behaviors According to their Limit Sets, Power Spectra, LEs, and Dimension Steady State

Limit Set

Spectrum

LEs

DC Periodic

Fixed Point Closed Curve

Quasiperiodic

K-Torus

Chaotic

Fractal

Spike at DC Fundamental Plus Integer Harmonics Incommensurate Frequencies Broad Spectrum

0 > λ1 ≥ … ≥ λn λ1 = 0 0 > λ2 ≥ … ≥ λn λ1 = … = λK = 0 0 > λK+1 ≥ … ≥ λn λ1 > 0 Σni=1 λ i < 0

Dimension 0 1 K Noninteger

All the eigenvalues of a stable equilibrium point have negative real parts and therefore the largest Lyapunov exponent of an attracting equilibrium point is negative. Trajectories close to a stable limit cycle converge onto the limit cycle. Therefore, the largest LE of a periodic steady-state is zero (corresponding to motion along the limit cycle [15]), and all its other LEs are negative. A quasiperiodic K-torus has K zero LEs because the flow is locally neither contracting nor expanding along the surface of the K-torus. S chaotic trajectory is locally unstable and therefore has a positive LE; this produces sensitive depen­ dence on initial conditions. Nevertheless, in the case of a chaotic attractor, this locally unstable chaotic trajectory belongs to an attracting limit set to which nearby trajectories converge. The steady-state behavior of a four-dimensional continuous-time dynamical system which has two positive, one zero, and one negative LE is called hyperchaos. The Lyapunov spectrum may be used to identify attractors, as summarized in Table 40.1.

Structural Stability and Bifurcations Structural stability refers to the sensitivity of a phenomenon to small changes in the parameter of a system. A structurally stable vector field F is one for which sufficiently close vector fields F′ have equivalent11 dynamics [18]. The behavior of a typical circuit depends on a set of parameters one or more of which may be varied in order to optimize some performance criteria. In particular, one may think of a one-parameter family of systems .

X = Fµ ( X )

(40.11)

where the vector field is parametrized by a control parameter µ. A value µ0 of (40.11) for which the flow of (40.11) is not structurally stable is a bifurcation value of µ [7]. The dynamics in the state space may be qualitatively very different from one value of µ to another. In the nonlinear RLC circuit example, the steady-state solution is a limit cycle if the control parameter Ga′ is negative and an equilibrium point if Ga′ is positive. If Ga′ is identically equal to zero, trajectories starting from I30 = 0, V20 < E yield sinusoidal solutions. These sinusoidal solutions are not structurally stable because the slightest perturbation on Ga′ will cause the oscillation to decay to zero or converge to the limit cycle, depending on whether Ga′ is made slightly larger or smaller than zero. If we think of this circuit as being parametrized by Ga′, then its vector field is not structurally stable at Ga′ ≡ 0. We say that the equilibrium point undergoes a bifurcation (from stability to instability) as the value of the bifurcation parameter Ga′ is reduced through the bifurcation point Ga′ = 0. 11

Equivalent means that there exists a continuous invertible function h that transforms F into F′.

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Bifurcation Types In this section, we consider three types of local bifurcation: the Hopf bifurcation, the saddle-node bifurcation, and the period-doubling bifurcation [18]. These bifurcations are called local because they may be understood by linearizing the system close to an equilibrium point or limit cycle. Hopf Bifurcation. A Hopf bifurcation occurs in a continuous-time dynamical system (40.3) when a simple pair of complex conjugate eigenvalues of the linearization DxF(XQ) of the vector field at an equilibrium point XQ crosses the imaginary axis. Typically, the equilibrium point changes stability from stable to unstable and a stable limit cycle is born. The bifurcation at Ga′ ≡ 0 in the nonlinear RLC circuit is Hopf-like.12 When an equilibrium point undergoes a Hopf bifurcation, a limit cycle is born. When a limit cycle undergoes a Hopf bifurcation, motion on a two-torus results. Saddle-Node Bifurcation. A saddle-node bifurcation occurs when a stable and an unstable equilibrium point merge and disappear; this typically manifests itself as the abrupt disappearance of an attractor. A common example of a saddle-node bifurcation in electronic circuits is switching between equilibrium states in a Schmitt trigger. At the threshold for switching, a stable equilibrium point corresponding to the “high” saturated state merges with the high-gain region’s unstable saddle-type equilibrium point and disappears. After a switching transient, the trajectory settles to the other stable equilibrium point, which corresponds to the “low” state. A saddle-node bifurcation may also manifest itself as a switch between periodic attractors of different size, between a periodic attractor and a chaotic attractor, or between a limit cycle at one frequency and a limit cycle at another frequency. Period-Doubling Bifurcation. A period-doubling bifurcation occurs in a discrete-time dynamical system (40.8) when a real eigenvalue of the linearization DXG(XQ) of the map G at an equilibrium point crosses the unit circle at –1 [7]. In a continuous-time system, a period-doubling bifurcation occurs only from a periodic solution (an equilibrium point of the Poincaré map). At the bifurcation point, a periodic orbit with period T changes smoothly into one with period 2T, as illustrated in Fig. 40.14(a) and (b). Blue Sky Catastrophe. A blue sky catastrophe is a global bifurcation that occurs when an attractor disappears “into the blue,” usually because of a collision with a saddle-type limit set. Hysteresis involving a chaotic attractor is often caused by a blue sky catastrophe [18]. Routes to Chaos Each of the three local bifurcations may give rise to a distinct route to chaos, and all three have been reported in electronic circuits. These routes are important because it is often difficult to conclude from experimental data alone whether irregular behavior is due to measurement noise or to underlying chaotic dynamics. If, upon adjusting a control parameter, one of the three prototype routes is observed, this indicates that the dynamics might be chaotic. Periodic-Doubling Route to Chaos. The period-doubling route to chaos is characterized by a cascade of period-doubling bifurcations. Each period-doubling transforms a limit cycle into one at half the fre­ quency, spreading the energy of the system over a wider range of frequencies. An infinite cascade of such doublings results in a chaotic trajectory of infinite period and a broad frequency spectrum that contains 12

Note that the Hopf bifurcation theorem is proven for sufficiently smooth systems and does not strictly apply to piecewise-linear systems. However, a physical implementation of a piecewise-linear characteristic, such as that of NR, is always smooth.

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V1

V2

I3

6 4 2

0 −2

−4

−6

0

2

4

6

8

10

0

−20

−40

−60

−80

−100

0

2

4

6

8

10

2

4

6

8

10

0

2

4

6

8

10

6

4

2

0 −2 −4 −6 0

2

4

6

8

10

0

2

4

6

8

10

6 4 2

0 −2

−4

−6

0

2

4

6

8

10

0

−20

−40

−60

−80

−100

0

2

4

6

8

10

(a) 6 4 2

0 −2

−4

−6

0

V1

V2

I3

0 −20 −40 −60 −80 −100

(b) V1

V2

I3

0 −20 −40 −60 −80 −100

(c)

V1

V2

I3

(d)

FIGURE 40.14 Period-doubling route to chaos in Chua’s oscillator. Simulated state space trajectories, time wave­ forms V1(t), and power spectra of V2(t) (a) G = 530 µS: periodic steady-state — the signal is characterized by a discrete power spectrum with energy at integer multiples of the fundamental frequency f0; (b) G = 537 µS; periodtwo — after a period-doubling bifurcation, the period of the signal is approximately twice that of (a). In the power spectrum, a spike appears at the new fundamental frequency ≈ f0/2. (c) G = 539 µS: period-four — a second perioddoubling bifurcation gives rise to a fundamental frequency of ≈ f0/4; (d) G = 541 µS: spiral Chua’s attractor — a cascade of period doublings results in a chaotic attractor that has a broadband power spectrum. Time plots: horizontal axis — t (ms); vertical axis — V1(V). Power spectra: horizontal axis — frequency (kHz); vertical axis — power [mean squared amplitude of V2 (t)] (db).

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energy at all frequencies. Figure 40.14 is a set of snapshots of the period-doubling route to chaos in Chua’s oscillator. An infinite number of period-doubling bifurcations to chaos can occur over a finite range of the bifurcation parameter because of a geometric relationship between the intervals over which the control parameter must be moved to cause successive bifurcations. Period-doubling is governed by a universal scaling law that holds in the vicinity of the bifurcation point to chaos µ∞. Define the ratio δk of successive interval µ, in each of which there is a constant period of oscillation, as follows, δk =

µ 2 k − µ 2 k −1 µ 2 k +1 − µ 2k

where µ2k is the bifurcation point for the period from 2k T to 2k+1T. In the limit as k → ∞, a universal constant called the Feigenbaum number δ is obtained: lim δ k = δ = 4.6692…

k→ ∞

The period-doubling route to chaos is readily identified from a state-space plot, time series, power spectrum, or a Poincaré map. Intermittency Route to Chaos. The route to chaos caused by saddle-node bifurcations comes in different forms, the common feature of which is direct transition from regular motion to chaos. The most common type is the intermittency route and results from a single saddle-node bifurcation. This is a route and not just a jump because straight after the bifurcation, the trajectory is characterized by long intervals of almost regular motion (called laminar phases) and short bursts of irregular motion. The period of the oscillations is approximately equal to that of the system just before the bifurcation. This is illustrated in Fig. 40.15. As the parameter passes through the critical value µc at the bifurcation point into the chaotic region, the laminar phases become shorter and the bursts become more frequent, until the regular intervals disappear altogether. The scaling law for the average interval of the laminar phases depends on µ – µc , so chaos is not fully developed until some distance from the bifurcation point [13]. Intermittency is best characterized in the time domain because its scaling law governs on the length of laminar phases. Another type of bifurcation to chaos associated with saddle-nodes is the direct transition from a regular attractor (fixed point or limit cycle) to a coexisting chaotic one, without the phenomenon of intermittency. Quasiperiodic (Torus Breakdown) Route to Chaos. The quasiperiodic route to chaos results from a sequence of Hopf bifurcations. Starting from a fixed point, the three-torus generated after three Hopf bifurcations is not stable in the sense that there exists an arbitrarily small perturbation of the system (in terms of parameters) for which the three-torus gives way to chaos. A quasiperiodic–periodic–chaotic sequence corresponding to torus breakdown in Chua’s oscillator is given in Fig. 40.5. Quasiperiodicity is difficult to detect from a time series; it is more readily identified by means of a power spectrum or Poincaré map (see Fig. 40.11, for example). Bifurcation Diagrams and Parameter Space Diagrams Although state space, time- and frequency-domain measurements are useful for characterizing steadystate behaviors, nonlinear dynamics offers several other tools for summarizing qualitative information concerning bifurcations. A bifurcation diagram is a plot of the attracting sets of a system versus a control parameter. Typically, one chooses a state variable and plots this against a single control parameter. In discrete systems, one © 2003 by CRC Press LLC

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2

1

V1

0

−1

−2

0

10

20

30

40

50

60

70

80

90

100

0

I3

V2

−20 −40 −60 −80 −100 0

1

2

3

4

5

(a) 2

V1

1 0 −1 −2

0

10

20

30

40

50

60

70

80

90

100

0

I3

V2

−20

−40

−60

−80

−100

0

1

2

3

4

5

(b) 2

V1

1 0 −1 −2

0

10

20

30

40

50

60

70

80

90

100

0

I3

V2

−20

−40

−60

−80

−100

0

1

2

3

4

5

(c)

FIGURE 40.15 Intermittency route to chaos in Chua’s oscillator. Simulated state space trajectories, time waveforms V1(t) and power spectra of V2(t) (a) Periodic steady-state — the signal is characterized by a discrete power spectrum with energy at integer multiples of the fundamental frequency; (b) onset of intermittency — the time signal contains long regular “laminar” phases and occasional “bursts” of irregular motion — in the frequency domain, intermittency manifests itself as a raising of the noise floor; (c) fully developed chaos-laminar phases are infrequent and the power spectrum is broad. Time plots: horizontal axis — t (ms); vertical axis — V1 (V). Power spectra: horizontal axis — frequency (kHz); vertical axis — power [mean squared amplitude of V2(t)] (dB).

simply plots successive values of a state variable. In the continuous-time case, some type of discretization is needed, typically by means of a Poincaré section. Figure 40.16 is a bifurcation diagram of the logistic map Xk+1 = µXk (1 – Xk ) for µ ∈[2.5, 4] and Xk ∈[0, 1]. Period doubling from period-one to period-two occurs at µ2; the next two doublings in the period-doubling cascade occur at µ2 and µ4, respectively. A periodic window in the chaotic region is indicated by µ3. The map becomes chaotic by the period-doubling route if µ is increasing from µ3 and by the intermittency route if µ is reduced out of the window. When more than one control parameter is present in a system, the steady-state behavior may be summarized in a series of bifurcation diagrams, where one parameter is chosen as the control parameter, © 2003 by CRC Press LLC

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Iterates of map xn

1 0.8 0.6 0.4 0.2 0

2.5

2.8

µ1

3.2

3.6 µ2 µ4

µ3

4

Bifurcation parameter µ

FIGURE 40.16 Bifurcation diagram for the logistic map: Xk+1 = µXk (1 – Xk ). The first period-doubling bifurcation occurs at µ = µ1, the second at µ2, and the third at µ4 · µ3 corresponds to a period-three window. When µ = 4, the entire interval (0, 1) is visited by a chaotic orbit {Xk , k = 0, 1, …}. Source: C. W. Wu and N. R. Rul’kov, “Studying chaos via 1-D maps — A tutorial,” IEEE Trans. Circuits Syst. I, vol. 40, p. 708, Oct. 1993.  1993 IEEE.

with the others held fixed, and only changed from one diagram to the next. This provides a complete but cumbersome representation of the dynamics [13]. A clearer picture of the global behavior is obtained by partitioning the parameter space by means of bifurcation curves, and labeling the regions according to the observed steady-state behaviors within these regions. Such a picture is called a parameter space diagram.

40.2 Chua’s Circuit: A Paradigm for Chaos Chaos is characterized by a stretching and folding mechanism; nearby trajectories of a dynamical system are repeatedly pulled apart exponentially and folded back together. In order to exhibit chaos, as autonomous circuit consisting of resistors, capacitors, and inductors must contain (i) at least one locally active resistor, (ii) at least one nonlinear element, and (iii) at least three energy-storage elements. The active resistor supplies energy to separate trajectories, the nonlinearity provides folding, and the three-dimensional state space permits persistent stretching and folding in a bounded region without violating the noncrossing property of trajectories. Chua’s circuit (see Fig. 40.17) is the simplest electronic circuit that satisfies these criteria. It consists of a linear inductor, a linear resistor, two linear capacitors, and a single nonlinear resistor NR . The circuit is readily constructed at low cost using standard electronic components and exhibits a rich variety of bifurcation and chaos [10].

R

C2

L I3

+

+

V2

V1

−

−

+ C1

VR

IR NR

−

FIGURE 40.17 Chua’s circuit consists of a linear inductor L, two linear capacitors (C2,C1), a linear resistor R, and a voltage-controlled nonlinear resistor NR.

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IR Gb (Gb−Ga)E −E

Ga 0

VR

E

(Ga−Gb)E

Gb

FIGURE 40.18 The driving-point characteristic of the nonlinear resistor NR in Chua’s circuit has breakpoints at ±E and slopes Ga and Gb in the inner and outer regions, respectively.

Dynamics of Chua’s Circuit State Equations Chua’s circuit may be described by three ordinary differential equations. Choosing V1, V2, and I3 as state variables, we write dV1 G 1 = (V − V1 ) − f (V1 ) dt C1 2 C1 dV2 G = (V − V2 ) + C1 I3 dt C2 1 2

(40.12)

dI 3 1 = – V2 dt L where G = 1/R and f (VR) = GbVR + 1/2(Ga + Gb) (VR + E – VR – E), as depicted in Fig. 40.18. Because of the piecewise-linear nature of NR, the vector field of Chua’s circuit may be decomposed into three distinct affine regions: V1 < –E, V1 ≤ E, and V1 > E. We call these the D–1, D0 and D1 regions, respectively. The global dynamics may be determined by considering separately the behavior in each of the three regions (D–1, D0 and D1) and then gluing the pieces together along the boundary planes U–1 and U1. Piecewise-Linear Dynamics In each region, the circuit is governed by a three-dimensional autonomous affine dynamical system of the form X˙ = AX + b

(40.13)

where A is the (constant) system matrix and b is a constant vector. The equilibrium points of the circuit may be determined graphically by intersecting the load line IR = –GVR with the DP characteristic IR = f(VR ) of the nonlinear resistor NR , as presented in Fig. 40.19 [2]. When G > Ga or G > Gb, the circuit has a unique equilibrium point at the origin (and two virtual equilibria P– and P+); otherwise, it has three equilibrium points at P–, 0, and P+. The dynamics close to an equilibrium point XQ are governed locally by the linear system x˙ = Ax

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(40.14)

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G>|Ga|

IR

Ga

|Gb| 0 and ω ≠ 0, xc(t) spirals away from XQ along the complex eigenplane E c, and if σ < 0, xc(t) spirals toward XQ and E c. © 2003 by CRC Press LLC

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We remark that the vector E r and plane E c are invariant under the flow of (40.13): if X(0) ∈E r, then X(t ) ∈E r for all t; if X(0) ∈E c , then X(t ) ∈E c for all t. An important consequence of this is that a trajectory X(t) cannot cross through the complex eigenspace E c ; suppose X(t 0 ) ∈E c at some time t0, then X(t ) ∈E c , for all t > t 0 .

Chaos in Chua’s Circuit In the following discussion, we consider a fixed set of component values: L = 18 mH, C2 = 100 nF, C1 = 10 nF, Ga = –50/66 mS = –757.576 µS, Gb = –9/22 mS = –409.091 µS, and E = 1 V. When G = 550 µS, three equilibrium points occur at P+, 0, and P–. The equilibrium point at the origin (0) has one unstable real eigenvalue γ0 and a stable complex pair σ0 ± jω0. The outer equilibria (P– and P+) each have a stable real eigenvalue γ1 and an unstable complex pair σ0 ± jω1. Dynamics of D0 A trajectory starting from some initial state X0 in the D0 region may be decomposed into its components along the complex eigenplane E c(0) and along the eigenvector E r(0). When γ0 > 0 and σ0 < 0, the component along E c(0) spirals toward the origin along this plane while the component in the direction E r(0) grows exponentially. Adding the two components, we see that a trajectory starting slightly above the stable complex eigenplane E c(0) spirals toward the origin along the E c(0) direction, all the while being pushing away from E c(0) along the unstable direction E r(0). As the (stable) component along E c(0) shrinks in magnitude, the (unstable) component grows exponentially, and the trajectory follows a helix of exponentially decreasing radius whose axis lies in the direction of E r(0); this is illustrated in Fig. 40.20. Dynamics of D–1 and D1 Associated with the stable real eigenvalue γ1 in the D1 region is the eigenvector E r(P+). The real and imaginary parts of the complex eigenvectors associated with σ1 ± jω1 define a complex eigenplane E c(P+). A trajectory starting from some initial state X0 in the D1 region may be decomposed into its components along the complex eigenplane E c(P+) and the eigenvector E r(P+). When γ1 < 0 and σ1 > 0, the component on E c(P+) spirals away from P+ along this plane while the component in the direction of E r(0) tends asymptotically toward P+. Adding the two components, we see that a trajectory starting close to the stable real eigenvector E r(P+) above the complex eigenplane moves toward E c(P+) along a helix of exponentially increasing radius. Because the component along E r(P+) shrinks exponentially in magnitude and the component on E c(P+) grows exponentially, the trajectory is quickly flattended onto E c(P+), where it spirals away from P+ along the complex eigenplane; this is illustrated in Fig. 40.21.

V1 Er(0)

D0

I3

V2 0 Ec(0)

FIGURE 40.20 Dynamics of the D0 region. A trajectory starting slightly above the stable complex eigenplane E c(0) spirals toward the origin along this plane and is repelled close to 0 in the direction of the unstabe eigenvector E r(0). Source: M. P. Kennedy, “Three steps to chaos — Part II: A Chua’s circuit primer,” IEEE Trans. Circuits Syst. I, vol. 40, p. 660, Oct. 1993.  1993 IEEE. © 2003 by CRC Press LLC

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V1

Er(P+)

Ec(P+) P+

D1

V2

I3

Er(P−)

P−

Ec(P−)

FIGURE 40.21 Dynamics of the D1 region. A trajectory starting above the unstable complex eigenplane E c(P+) close to the eigenvector E r(P+) moves toward the plane and spirals away from P+ along E c(P+). By symmetry, the D–1 region has equivalent dynamics. Source: M. P. Kennedy, “Three steps to chaos — Part II: A Chua’s circuit primer,” IEEE Trans. Circuits Syst., vol. 40, p. 662, Oct. 1993. © 1993 IEEE.

By symmetry, the equilibrium point P– in the D–1 region has three eigenvalues: γ1 and σ1 ± jω1. The eigenvector E r(P–) is associated with the stable real eigenvalue γ1; the real and imaginary parts of the eigenvectors associated with the unstable complex pair σ1 ± jω1 define an eigenplane E c(P–), along which trajectories spiral away from P–. Global Dynamics With the given set of parameter values, the equilibrium point at the orgin has an unstable real eigenvalue and a stable pair of complex conjugate eigenvalues; the outer equilibrium point P– has a stable real eigenvalue and an unstable complex pair. In particular, P– has a pair of unstable complex conjugate eigenvalues σ1 ± ω1 (σ1 > 0, ω1 ≠ 0) and a stable real eigenvalue γ1, where σ1 < ω1. In order to prove that the circuit is chaotic in the sense of Shil’nikov, it is necessary to show that it possesses a homoclinic orbit for this set of parameter values. A trajectory starting on the eigenvector E r(0) close to 0 moves away from the equilibrium point until it crosses the boundary U1 and enters D1, as illustrated in Fig. 40.20. If this trajectory is folded back into D0 by the dynamics of the outer region, and reinjected toward 0 along the stable complex eigenplane E c(0) then a homoclinic orbit is produced. That Chua’s circuit is chaotic in the sense of Shil’nikov was first proven by Chua et al. [21] in 1985. Since then, there has been an intensive effort to understand every aspect of the dynamics of this circuit with a view to developing it as a paradigm for learning, understanding, and teaching about nonlinear dynamics and chaos [3].

Steady-States and Bifurcations in Chua’s Circuit In the following discussion, we consider the global behavior of the circuit using our chosen set of parameters with R in the range 0 ≤ R ≤ 2000 Ω (500 µ s ≤ G < ∞ s). Figure 40.14 is a series of simulations of the equivalent circuit in Fig. 40.26 with the following param­ eter values: L = 18 mH, C2 = 100 nF, C1 = 10 nF, Ga = –50/66 mS = –757.576 µS, Gb = –9/22 mS = –409.091 µS, and E = 1 V. R0 = 12.5 Ω, the parasitic series resistance of a real inductor. R is the bifurcation parameter. Equilibrium Point and Hopf Bifurcation When R is large (2000 Ω), the outer equilibrium points P– and P+ are stable (γ1 < 0 and σ1 < 0, ω1 ≠ 0); the inner equilibrium point 0 is unstable (γ0 > 0 and σ0 < 0,ω0 ≠ 0). Depending on the initial state of the circuit, the system remains at one outer equilibrium point or the other. Let us assume that we start at P+ in the D1 region. This equilibrium point has one negative real © 2003 by CRC Press LLC

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eigenvalue and a complex pair with negative real parts. The action of the negative real eigenvalue γ 1 is to squeeze trajectories down onto the complex eigenplane E c(P+), where they spiral toward the equilibrium point P+. As the resistance R is decreased, the real part of the complex pair of eigenvalues changes sign and becomes positive. Correspondingly, the outer equilibrium points become unstable as σ1 passes through 0; this is a Hopf-like bifurcation.13 The real eigenvalue of P+ remains negative so trajectories in the D1 region converge toward the complex eigenplane E c(P+). However, they spiral away from the equilibrium point P+ along E c(P+) until they reach the dividing plane U1 (defined by V1 ≡ E) and enter the D0 region. The equilibrium point at the origin in the D0 region has a stable complex pair of eigenvalues and an unstable real eigenvalue. Trajectories that enter the D0 region on the complex eigenplane E c(0) are attracted to the origin along this plane. Trajectories that enter D0 from D1 below or above the eigenplane either cross over to D–1 or are turned back toward D1, respectively. For R sufficiently large, trajectories that spiral away from P+ along E c(P+) and enter D0 above E c(0) are returned to D1, producing a stable period-one limit cycle. This is illustrated in Fig. 40.14. Period-Doubling Cascade As the resistance R is decreased further, a period-doubling bifurcation occurs. The limit cycle now closes on itself after encircling P+ twice; this is called a period-two cycle because a trajectory takes approximately twice the time to complete this closed orbit as to complete the preceding period-one orbit [see Fig. 40.14(b)]. Decreasing the resistance R still further produces a cascade of period-doubling bifurcations to periodfour [Fig. 40.14(c)], period-eight, period-sixteen, and so on until an orbit of infinite period is reached, beyond which we have chaos [see Fig. 40.14(d)]. This is a spiral Chua’s chaotic attractor. The spiral Chua’s attractor in Fig. 40.14(d) looks like a ribbon or band that is smoothly folded on itself; this folded band is the simplest type of chaotic attractor [18]. A trajectory from an initial condition X0 winds around the strip repeatedly, returning close to X0, but never closing on itself. Periodic Windows Between the chaotic regions in the parameter space of Chua’s circuit, there exist ranges of the bifurcation parameter R over which stable periodic motion occurs. These regions of periodicity are called periodic windows and are similar to those that exist in the bifurcation diagram of the logistic map (see Fig. 40.16). Periodic windows of periods three and five are readily found in Chua’s circuit. These limit cycles undergo period-doubling bifurcations to chaos as the resistance R is decreased. For certain sets of parameters, Chua’s circuit follows the intermittency route to chaos as R is increased out of the period-three window. Spiral Chua’s Attractor Figure 40.22 outlines three views of another simulated spiral Chua’s chaotic attractor. Figure 40.22(b) is a view along the edge of the outer complex eigenplanes E c(P+) and E c(P–); notice how trajectories in the D1 region are compressed toward the complex eigenplane E c(P+) along the direction of the stable real eigenvector E c(P+) and they spiral away from the equilibrium point P+ along E c(P+). When a trajectory enters the D0 region through U1 from D1, it is twisted around the unstable real eigenvector E r(0) and returned to D1. Figure 40.22(c) illustrates clearly that when the trajectory enters D0 from D1, it crosses U1 above the eigenplace E c(0). The trajectory cannot cross through this eigenplane and therefore it must return to the D1 region. Double-Scroll Chua’s Attractor Because we chose a nonlinear resistor with a symmetric nonlinearity, every attractor that exists in the D1 and D0 regions has a counterpart (mirror image) in the D–1 and D0 regions. As the coupling resistance 13Recall that the Hopf bifurcation theorem strictly applies only for sufficiently smooth systems, but that physical implementations of piecewise-linear characteristics are typically smooth.

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V1

V1

D1

Er(P+)

Ec(P+)

P+ U1

U1 I3

V2

D0 I3

0

Er(0) U−1

V2 U−1

D−1

P−

(a)

(b) V1

U1 Ec(0) Er(0)

I3

V2 U−1

(c)

FIGURE 40.22 Three views of a simulated spiral Chua’s attractor in Chua’s oscillator with G = 550µS. (a) Reference view [compare with Fig. 40.14(d)]. (b) View of the edge of the outer complex eigenplanes E c(P+) and E c(P–); note how trajectory in D1 is flattened onto E c(P+). (c) View along the edge of the complex eigenplane E c(0); trajectories cannot cross this plane. Source: M. P. Kennedy, “Three steps to chaos — Part II: A Chua’s circuit primer,” IEEE Trans. Circuits Syst. I, vol. 40, p. 664, Oct. 1993. © 1993 IEEE.

R is decreased further, the spiral Chua’s attractor “collides” with its mirror image and the two merge to form a single compound attractor called a double-scroll Chua’s chaotic attractor [10], as presented in Fig. 40.23. Once more, we show three views of this attractor in order to illustrate its geometrical structure. Figure 40.23(b) is a view of the attractor along the edge of the outer complex eigenplanes E c(P+) and E c (P_). Upon entering the D1 region form D0, the trajectory collapses onto E c(P+) and spirals away from P+ along this plane. Figure 40.23(c) is a view of the attractor along the edge of the complex eigenplane E c(0) in the inner region. Notice once more that when the trajectory crosses U1 into D0 above E c(0), it must remain above E c(0) and so returns to D1. Similarly, if the trajectory crosses U1 below E c(0), it must remain below E c(0)and therefore crosses over to the D–1 region. Thus, E c(0) presents a knife-edge to the trajectory as it crosses U1 into the D0 region, forcing it back toward D1 or across D0 to D–1. Boundary Crisis Reducing the resistance R still further produces more regions of chaos, interspersed with periodic windows. Eventually, for a sufficiently small value of R, the unstable saddle trajectory that normally resides outside the stable steady-state solution collides with the double-scroll Chua’s attractor and a blue sky catastrophe called a boundary crisis [10] occurs. After this, all trajectories become unbounded.

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V1

V1

Er(P+)

D1

P+

Ec(P+)

U1 D0

I3

V2

I3

0 U−1

D−1

P−

V2

Er(P−)

Ec(P−)

(a)

(b) V1

U1 Ec(0) Er(0)

I3

V2 U−1

(c)

FIGURE 40.23 Three views of a simulated double-scroll Chua’s attractor in Chua’s oscillator with G = 565 µS. (a) Reference view [compare with Fig. 40.14(d)]. (b) View along the edge of the outer complex eigenplanes E c(P+) and E c(P–); note how the trajectory in D1 is flattened onto E c(P+) and onto E c(P–) in D–1. (c) View along the edge of the complex eigenplane E c(0); a trajectory entering D0 from D1 above this plane returns to D1 while one entering D0 below E c(0) crosses to D–1. Source: M. P. Kennedy, “Three steps to chaos — Part II: A Chua’s circuit primer,” IEEE Trans. Circuits Syst. I, vol. 40, p. 665, Oct. 1993. © 1993 IEEE.

Manifestations of Chaos Sensitive Dependence on Initial Conditions Consider once more the double-scroll Chau’s attractor shown in Fig. 40.23. Two trajectories starting from distinct but almost identical initial states in D1 will remain “close together” until they reach the separating plane U1. Imagine that the trajectories are still “close” at the knife-edge, but that one trajectory crosses into D0 slightly above E c(0) and the other slightly below E c(0). The former trajectory returns to D1 and the latter crosses over to D1: their “closeness” is lost. The time-domain waveforms V1(t) for two such trajectories are shown in Fig. 40.24. These are solutions of Chua’s oscillator with the same parameters as in Fig. 40.23; the initial conditions are (I3, V2, V1) = (1.810 mA, 222.014 mV, –2.286 V) [solid line] and (I3, V2, V1) = (1.810 mA, 222.000 mV, –2.286 V) [dashed line]. Although the initial conditions differ by less than 0.01 percent in just one component (V2), the trajectories diverge and become uncorrelated within 0.01 percent in just one component (V2), the trajec­ tories diverge and become uncorrelated within 5 ms because one crosses the knife-edge before the other. This rapid decorrelation of trajectories that originate in nearby initial states, commonly called sensitive dependence on initial conditions, is a generic property of chaotic systems. It gives rise to an apparent randomness in the output of the system and long-term unpredictability of the state.

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6 4 2 0 −2 −4 −6

0

1

2

3

4

5

FIGURE 40.24 Sensitive dependence on initial conditions. Two time waveforms V1(t) from Chua’s oscillator with G = 550 µS, starting from (I3, V2, V1) = (1.810 mA, 222.01 mV, –2.286 V) [solid line] and (I3, V2, V1) = (1.810 mA, 222.000 mV, –2.286 V) [dashed line]. Note that the trajectories diverge within 5 ms. Horizontal axis: t (ms); vertical axis: V1 (V). Compare with Fig. 40.23.

“Randomness” in the Time Domian Figures 40.14(a), (b), (c), and (d) show the state-space trajectories of period-one, period-two, and periodfour periodic attractors, a spiral Chua’s chaotic attractor, respectively, and the corresponding voltage waveforms V1(t). The “period-one” waveform is periodic; it looks like a slightly distorted sinusoid. The “period-two” waveform is also periodic. It differs qualitatively from the “period-one” in that the pattern of a large peak followed by a small peak repeats approximately once every two cycles of the period-one signal; that is why it is called “period-two.” In contrast with these periodic time waveforms, V1(t) for the spiral Chua’s attractor is quite irregular and does not appear to repeat itself in any observation period of finite length. Although it is produced by a third-order deterministic differential equation, the solution looks “random.” Broadband “Noise-Like” Power Spectrum In the following discussion, we consider 8192 samples of V2(t) recorded at 200 kHz; leakage in the power spectrum is controlled by applying a Welch window [17] to the data. We remarked earlier that the period-one time waveform corresponding to the attractor in Fig. 40.14(a), is almost sinusoidal; we expect, therefore, that most of its power should be concentrated at the funda­ mental frequency. The power spectrum of the period-one waveform V2(t) shown in Fig. 40.14(a) consists of a sharp spike at approximately 3 kHz and higher harmonic components that are over 30 dB below the fundamental. Because the period-two waveform repeats roughly once every 0.67 ms, this periodic signal has a fundamental frequency component at approximately 1.5 kHz [see Fig. 40.14(b)]. Notice, however, that most of the power in the signal is concentrated close to 3 kHz. The period-four waveform repeats roughly once every 1.34 ms, corresponding to a fundamental frequency component at approximately 750 Hz [See Fig. 40.14(c)]. Note once more that most of the power in the signal is still concentrated close to 3 kHz. The spiral Chua’s attractor is qualitatively different from these periodic signals. The aperiodic nature of its time-domain waveforms is reflected in the broadband noise-like power spectrum [Fig. 40.14(d)]. No longer is the power of the signal concentrated in a small number of frequency components; rather, it is distributed over a broad range of frequencies. This broadband structure of the power spectrum persists even if the spectral resolution is increased by sampling at a higher frequency fs. Notice that the spectrum still contains a peak at approximately 3 kHz that corresponds to the average frequency of rotation of the trajectory about the fixed point.

Practical Realization of Chua’s Circuit Chua’s circuit can be realized in a variety of ways using standard or custom-made electronic components. All the linear elements (capacitor, resistor, and inductor) are readily available as two-terminal devices. A

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R

1 +

L

+

V2

C2

IR

2

V1

C1

+ A1 −

VR

I3

R6

R3

+

V+ 3 V−

+ A2 −

R2 −

V−

R5

R1

−

5

6

4 −

V+

R4

0 NR

FIGURE 40.25 Practical implementation of Chua’s circuit using two op amps and six resistors to realize the Chua diode [10]. Component values are listed in Table 40.2.

TABLE 40.2 Component List for the Practical Implementation of Chua’s Circuit, depicted in Fig. 40.25 Element A1 A2 C1 C2 R R1 R2 R3 R4 R5 R6 L

Description Op Amp ( 1--2 AD712, TL082, or Equivalent) ( 1--2 AD712,

Tolerance

—

—

W Resistor

— 10 nF 100 nF 2 kΩ 3.3 kΩ

— ±5% ±5% — ±5%

W Resistor

22 kΩ

±5%

W Resistor

22 kΩ

±5%

Op Amp Capacitor Capacitor Potentiometer 1-4 1-4 1-4 1-4 1-4 1-4

Value

TL082, or Equivalent)

W Resistor W Resistor

W Resistor Inductor (TOKO-Type 10 RB, or Equivalent)

2.2 kΩ 220 Ω 220 Ω 118 mH

±5% ±5% ±5% ±10%

nonlinear resistor NR with the prescribed DP characteristic (called a Chua diode [10]) may be imple­ mented by connecting two negative resistance converters in parallel as outlined in Fig. 40.25. A complete list of components is given in Table 40.2. The op amp subcircuit consisting of A1, A2 and R1–R6 functions as a negative resistance converter NR with driving-point characteristic as shown in Fig. 40.28(b). Using two 9-V batteries to power the op amps gives V + = 9 V and V – = – 9 V. From measurements of the saturation levels of the AD712 outputs, Esat ≈ 8.3 V, giving E ≈ 1 V. With R2 = R3 and R5 = R6, the nonlinear characteristic is defined by Ga = –1/R1 – 1/R4 = –50/66 mS, Gb = 1/R3 – 1/R4 = –9/22 mS, and E = R1Esat/(R1 + R2) ≈ 1 V[10]. The equivalent circuit of Fig. 40.25 is presented in Fig. 40.26, where the real inductor is modeled as a series connection of an ideal linear inductor L and a linear resistor R0. When the inductor’s resistance is modeled explicitly in this way, the circuit is called Chua’s oscillator [5].

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R

L I3 C2 R0

+

+

V2

V1

−

−

+ C1

VR

IR

NR

−

FIGURE 40.26 Chua’s oscillator.

Experimental Steady-State Solutions A two-dimensional projection of the steady-state attractor in Chua’s circuit may be obtained by connect­ ing V2 and V1 to the X and Y channels, respectively, of an oscilloscope in X–Y mode. Bifurcation Sequence with R as Control Parameter By reducing the variable resistor R in Fig. 40.25 from 2000 Ω toward zero, Chua’s circuit exhibits a Hopf bifurcation from dc equilibrium, a sequence of period-doubling bifurcations to a spiral Chua’s attractor, periodic windows, a double-scroll Chua’s chaotic attractor, and a boundary crisis, as illustrated in Fig. 40.27. Notice that varying R in this way causes the size of the attractors to change: the period-one orbit is large, period-two is smaller, the spiral Chua’s attractor is smaller again, and the double-scroll Chua’s attractor shrinks considerably before it dies. This shrinking is due to the equilibrium points P+ and P– moving closer towards the origin as R is decreased. Consider the load line in Fig. 40.19(b): as R is decreased, the slope G increases, and the equilibrium points P– and P+ move toward the origin. Compare also the positions of P+ in Figs. 40.22(a) and 40.23(a) The Outer Limit Cycle No physical system can have unbounded trajectories. In particular, any physical realization of a Chua diode is eventually passive, meaning simply that for a large enough voltage across its terminals, the instantaneous power PR(t) [= VR(t)IR(t)] consumed by the device is positive. Hence, the DP characteristic of a real Chua diode must include at least two outer segments with positive slopes which return the characteristic to the first and third quadrants [see Fig. 40.28(b)]. From a practical point of view, as long as the voltages and currents on the attractor are restricted to the negative resistance region of the characteristic, these outer segments will not affect the circuit’s behavior. The DP characteristic of the op-amp-based Chua diode differs from the desired piecewise linear characteristic depicted in Fig. 40.28(a) in that it has five segments, the outer two of which have positive slopes Gc = 1/R5 = 1/220 S. The “unbounded” trajectories that follow the boundary crisis in the ideal three-region system are limited in amplitude by these dissipative outer segments and a large limit cycle results, as illustrated in Fig. 40.27(i). This effect could, of course, be simulated by using a five-segment DP characteristic for NR as illustrated in Fig. 40.28(b). The parameter value at which the double-scroll Chua’s attractor disappears and the outer limit cycle appears is different from that at which the outer limit cycle disappears and the chaotic attractor reappears. This “hysteresis” in parameter space is characteristic of a blue sky catastrophe.

Simulation of Chua’s Circuit Our experimental observations and qualitative descriptive description of the global dynamics of Chua’s circuit may be confirmed by simulation using a specialized nonlinear dynamics simulation package such as INSITE [15] or by employing a customized simulator such as “ABC” [10]. © 2003 by CRC Press LLC

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(a)

(b)

(c)

(d)

(e)

(f)

(g)

(h)

(i)

FIGURE 40.27 Typical experimental bifurcation sequence in Chua’s circuit (component values as in Table 40.2) recorded using a digital storage oscilloscope. Horizontal axis V2 (a)–(h) 200 mV/div, (i) 2 V/div; vertical axis V1 (a)–(h) 1 V/div, (i) 2 V/div. (a) R = 1.83 kΩ, period–1; (b) R = 1.82 kΩ, period-2; (c) R = 1.81 kΩ, period-4; (d) R = 1.80 kΩ, spiral Chua’s attractor; (e) R = 1.797 kΩ, period-3 window; (f) R = 1.76 kΩ, spiral Chua’s attractor; (g) R = 1.73 kΩ, double-scroll Chua’s attractor; (h) R = 1.52 kΩ, double-scroll Chua’s attractor; (i) R = 1.42 kΩ, large limit cycle corresponding to the outer segments of the Chua diode’s DP characteristic. Source: M. P. Kennedy, “Three steps to chaos — Part II: A Chua’s circuit primer,” IEEE Trans. Circuit Syst. I, vol. 40, pp. 669, 670, Oct. 1993. © 1993 IEEE.

For electrical engineers who are familiar with the SPICE circuit simulator but perhaps not with chaos, we present a net-list and simulation results for a robust op-amp-based implementation of Chua’s circuit. The AD712 op amps in this realization of the circuit are modeled using Analog Devices’ AD712 macromodel. The TOKO 10RB inductor has a nonzero series resistance that we have included in the SPICE net-list; a typical value of RO for this inductor is 12.5 Ω. Node numbers are as Fig. 40.25: the power rails © 2003 by CRC Press LLC

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IR

IR Gb

Gb Gc −E′

Ga −E

−Esat

VR

E

Ga −E

Esat E′

E

Gb

Gb

(a)

VR Gc

(b)

FIGURE 40.28 (a) Required three-segment piecewise-linear DP characteristic for the Chua diode in Fig. 40.17. (b) Every physically realizable nonlinear resistor NR is eventually passive — the outermost segments (while not necessarily linear as presented here) must lie completely within the first and third quadrants of the VR–IR place for sufficiently large VR and IR.

are 111 and 222; 10 is the “internal” node of the physical inductor, where its series inductance is connected to its series resistance. A double-scroll Chua’s attractor results from a PSPICE simulation using the input deck shown in Fig. 40.29; this attractor is plotted in Fig. 40.30.

Dimensionless Coordinates and the – Parameter-Space Diagram Thus far, we have discussed Chua’s circuit equations in terms of seven parameters: L, C2, G, C1, E, Ga, and Gb. We can reduce the number of parameters by normalizing the nonlinear resistor such that its breakpoints are at ±1 V instead of ±E V. Furthermore, we may write Chua’s circuit equations (40.12) in normalized dimensionless form by making the following change of variables: X1 = V1 /E, X2 = V2 /E, X3 = I3/(EG), and τ = tG/C2. The resulting state equations are

[

]

dX1 = α X 2 − X1 − f ( X1 ) dτ dX 2 = X1 − X 2 + X 3 dτ

(40.15)

dX 3 = −βX 2 dτ where α = C2 /C1, β = C2 /(LG2), and f(X) = bX + 1/2 (a – b) (X + 1 – X – 1); a = Ga /G and b = Gb /G. Thus, each set of seven circuit parameters has an equivalent set of four normalized dimensionless parameters {α, β, a, b}. If we fix the values of a and b (which correspond to the slopes Ga and Gb of the Chua diode), we can summarize the steady-state dynamical behavior of Chua’s circuit by means of a two-dimensional parameter-space diagram. Figure 40.31 presents the (α,β) parameter-space diagram with a = –8/7 and b = –5/7. In this diagram, each region denotes a particular type of steady-state behavior: for example, an equilibrium point, periodone orbit, period-two, spiral Chua’s attractor, double-scroll Chua’s attractor. Typical state-space behaviors are shown in the insets. For clarity, we show chaotic regions in a single shade; it should be noted that these chaotic regions are further partitioned by periodic windows and “islands” of periodic behavior. To interpret the α–β diagram, imagine fixing the value of β = C2 /(LG2) and increasing α = C2 /C1 from a positive value to the left of the curve labeled “Hopf at P ±”; experimentally, this corresponds to fixing the parameters L, C2, G, E, Ga , and Gb , and reducing the value of C1 — this is called a “C1 bifurcation sequence.” Initially, the steady-state solution is an equilibrium point. As the value of C1 is reduced, the circuit undergoes a Hopf bifurcation when α crosses the “Hopf at P ±” curve. Decreasing C1 still further, the © 2003 by CRC Press LLC

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Bifurcation and Chaos

ROBUST OP AMP REALIZATION OF CHUA’S CIRCUIT V+ 111 0 DC 9

V− 0 222 DC 9

L 1 10 0.018

R0 10 0 12.5

R 1 2 1770

C2 1 0 100.0N

C1 2 0 10.0N

XA1 2 4 111 222 3 AD712

R1 2 3 220

R2 3 4 220

R3 4 0 2200

XA2 2 6 111 222 5 AD712

R4 2 5 22000

R5 5 6 22000

R6 6 0 3300

* AD712 SPICE Macro-model

1/91, Rev. A

* Copyright 1991 by Analog Devices, Inc. (reproduced with permission) * .SUBCKT AD 712 13 15 21 16 14 * VOS 15 8 DC 0 EC 9 0 14 0 1 C1 6 7 .5P RP 16 12 12K GB 11 0 3 0 1.67K RD1 6 16 16k RD2 7 16 16k ISS 12 1 DC 100U CCI 3 11 150P GCM 0 3 0 1 1.76N GA 3 0 7 6 2.3M RE 1 0 2.5MEG RGM 3 0 1.69K VC 12 2 DC 2.8 VE 10 16 DC 2.8 RO1 11 14 25 CE 1 0 2P RO2 0 11 30 RS1 1 4 5.77K RS2 1 5 5.77K J1 6 13 4 FET J2 7 8 5 FET DC 14 2 DIODE DE 10 14 DIODE DP 16 12 DIODE D1 9 11 DIODE D2 11 9 DIODE IOS 15 13 5E-12 .MODEL DIODE D .MODEL FET PJF(VTO = −1 BETA = 1M IS = 25E−12) .ENDS .IC V(2) = 0.1 V(1) = 0 .TRAN 0.01MS 100MS 50MS .OPTIONS RELTOL = 1.0E−4 ABSTOL = 1.0E−4 .PRINT TRAN V(2) V(1) .END

FIGURE 40.29 SPICE deck to simulate the transient response of the dual op amp implementation of Chua’s circuit. Node numbers are as in Fig. 40.25. The op amps are modeled using the Analog Devices AD712 macro-model. RO models the series resistance of the real inductor L.

steady-state behavior bifurcates from period-one to period-two to period-four and so on to chaos, periodic windows, and a double-scroll Chua’s attractor. The right-hand side edge of the chaotic region is delimited by a curve corresponding to the boundary crisis and “death” of the attractor. Beyond this curve, trajectories diverge toward infinity. Because of eventual passivity in a real circuit, these divergent trajectories will of course converge to a limit cycle in any physical implementation of Chua’s circuit.

40.3 Chua’s Oscillator Chua’s oscillator [5] (see Fig. 40.26) is derived from Chua’s circuit by adding a resistor R0 in series with the inductor L. The oscillator contains a linear inductor, two linear resistors, two linear capacitors, and © 2003 by CRC Press LLC

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4.0V

2.0V

0V

−2.0V

−4.0V −800mV

−600mV

−400mV

−200mV

0V

200mV

400mV

600mV

800mV

FIGURE 40.30 PSpice (evaluation version 5.4, July 1993) simulation of Fig. 40.25 using the input deck from Fig. 40.29 yields this double-scroll Chua’s attractor. Horizontal axis V2 (V); vertical axis V1 (V).

a single Chua diode NR. NR is a voltage-controlled piecewise-linear resistor whose continuous oddsymmetric three-segment driving-point characteristic (see Fig. 40.18) is described explicitly by the rela­ tionship

(

I R = GbVR + 12 (Ga − Gb ) VR + E − VR − E

)

The primary motivation for studying this circuit is that the vector field of Chua’s oscillator is topo­ logically conjugate to the vector field of a large class of three-dimensional, piecewise-linear vector fields. In particular, the oscillator can exhibit every dynamical behavior known to be possible in an autonomous three-dimensional, continuous-time dynamical system described by a continuous odd-symmetric threeregion piecewise-linear vector field. With appropriate choices of component values, the circuit follows the period-doubling, intermittency, and quasiperiodic routes to chaos.

State Equations Choosing V1, V2, V, and I3 as state variables, Chua’s oscillator may be described by three ordinary differential equations: dV1 G 1 = (V − V ) − f (V1 ) dt C1 2 1 C1 dV2 G = (V − V2 ) + C1 I3 dt C2 1 2 dI 3 R 1 = − V2 − 0 I 3 dt L L where G = 1/R and f (VR) = Gb VR + 1/2 (Ga – Gb) (VR + E –  VR – E). © 2003 by CRC Press LLC

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1133

0

p−

4 p+

20

p+ 15

3 E

p+

0

2

BI RT H

p−

p−

5 F 0

p−

6

β

0

G

p+

0

O ER

p−

T HE

7 H 0

M DE AT D H

25

D

C

p+

HO

p+

p−

2

1

30

0

OD

p−

B

p+

PE RI

A 0

f at ± p

p+

Hop

35

SP I WI RAL ND OW

Bifurcation and Chaos

p−

1 2

3

7 9 4 5 6 8 10 11

7

10

I + 0 p− p

p+

p−

9

8 5

J 0

K

p+

0

p−

L

p+

0

p−

11

10 0 0

5

α

10

15

FIGURE 40.31 α–β parameter space diagram for the normalized dimensionless Chua’s circuit equations (40.31) with a = –8/7 and b = –5/7. Source: M. P. Kennedy, “Three steps to chaos — Part II: A Chua’s circuit primer,” IEEE Trans. Circuits Syst. I, vol. 40, p. 673, Oct. 1993.  1993 IEEE.

The vector field is parameterized by eight constants: L, C2, G, C1, R0, E, Ga, and Gb . We can reduce the number of parameters by normalizing the nonlinear resistor such that its breakpoints are at ±1 V instead of ±E V, scaling the state variables, and scaling time. By making the following change of variables: X1 = V1/E, X2 = V2/E, X3 = I3/(EG), τ = tG/C2 , and k = sgn (G/C2),14 we can rewrite the state equations (40.16) in normalized dimensionless form:

[

]

dX1 = kα X 2 − X1 − f ( X1 ) dτ dX 2 = k( X1 − X 2 + X 3 ) dτ dX 3 = − k(βX 2 + γX 3 ) dτ

where α = C2 /C1, β = C2 /(LG2), γ = R0C2 /(LG), and f (x) = bX +1/2(a – b)(X + 1 – X – 1) with a = Ga /G and b = Gb /G. Thus, each set of eight circuit parameters has an equivalent set of six normalized dimensionless parameters {α, β, γ, a, b, k}.

14

The signum function is defined by sgn(x) = x if x > 0, sgn(x) = –x if x < 0, and sgn(0) = 0.

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Topological Conjugacy Two vector fields F and F′ are topologically conjugate if there exists a continuous map h (which has a continuous inverse) such that h maps trajectories of F into trajectories of F′, preserving time orientation and parametrization of time. If φt and φ′t are the flows of F and F′, respectively, then φt ° h = h ° φ′t for all t. This means that the dynamics of F and F′ are qualitatively the same. If h is linear, then F and F′ are said to be linearly conjugate. Class  The three-dimensional, autonomous, continuous-time dynamical system defined by the state equation X˙ = F( X )

X ∈3

is said to belong to class  iff 1. F: 3 → 3 is continuous 2. F is odd-symmetric, i.e., F(–X) = –F(X) 3. 3 is partitioned by two parallel boundary planes U1 and U–1 into an inner region D0, which contains the origin, and two outer regions D1 and D–1, and F is affine in each region. Without loss of generality, the boundary planes and the regions they separate can be chosen as follows: D−1 = {X: X1 ≤ −1} U −1 = {X: X1 = −1}

{

}

D0 = X: X1 ≤ 1

U −1 = {X: X1 = 1} D1 = {X: X1 ≥ 1} Any vector field in the family  can then be written in the form A −1X − b X1 ≤ − 1  − 1 ≤ X1 ≤ 1 X˙ = A 0 X   A1X + b X1 ≥ 1 where a11  A −1 = A1 = a21  a  31

a12 a22 a32

a13  b1     a23  and b = b2     b  a33   3

By continuity of the vector field across the boundary planes, (a11 + b1 )  A 0 = (a21 + b2 )   (a31 + b3 ) © 2003 by CRC Press LLC

a12 a22 a32

a13   a23   a33 

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Bifurcation and Chaos

Equivalent Eigenvalue Parameters Let (µ1, µ2, µ3) denote the eigenvalues associated with the linear vector field in the D0 region and let (ν1, ν2, ν3) denote the eigenvalues associated with the affine vector fields in the outer regions D1 and D–1. Define p1 = µ1 + µ 2 + µ 3

  p2 = µ1µ 2 + µ 2µ 3 + µ 3µ1    p3 = µ1µ 2µ 3     q1 = v1 + v2 + v3   q2 = v1v2 + v2 v3 + v3 v1    q3 = v1v2 v3

(40.16)

Because the six parameters {p1, p2, p3, q1, q2, q3} are uniquely determined by the eigenvalues {µ1, µ2, µ3, ν1, ν2, ν3} and vice versa, the former are called the equivalent eigenvalue parameters. Note that the equivalent eigenvalues are real; they are simply the coefficients of the characteristic polynomials:

(s − µ1 )(s − µ 2 )(s − µ3 ) = s3 − p1s 2 + p2s − p3 (s − ν1 )(s − ν2 )(s − ν3 ) = s3 − q1s 2 + q2s − q3 Theorem 3 (Chua et al.) [5]: Let {µ1, µ2, µ3, ν1, ν2, ν3} be the eigenvalues associated with a vector field F(X)∈/0, where 0 is the set of measure zero in the space of equivalent eigenvalue parameters where one of (40.17) is satisfied. Then, Chua’s oscillator with parameters defined by (40.18) and (40.19) is linearly conjugate to this vector field. p1 − q1 = 0   p2 − q 2   p1 − p − q  = 0  1 1    p −q  k −  2 2  − 1 = 0   p1 − q1  k2   p −q   −k1k3 + k2  3 3  = 0  p1 − q1    0    a13  = a12k33 − a13k32 = 0    K 33  

 p −q   p −q  p2 −  3 3  −  2 2   p1 − q1   p1 − q1 

1  det K = det a11  K  31

0 a12 K 32

(40.17)

where 3

K 3i =

∑a a

1 j ji

i = 1, 2, 3

j=i

˜ ˜ We denote by  the set of vector fields /0. Two vector fields in  are linearly conjugate if they have the same eigenvalues in each region.

© 2003 by CRC Press LLC

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Eigenvalues-to-Parameters Mapping Algorithm for Chua’s Oscillator Every continuous, third-order, odd-symmetric, three-region, piecewise-linear vector field F′ in  may be mapped onto a Chua’s oscillator (where the vector field F is topologically conjugate to F′) by means of the following algorithm [5]: 1. Calculate the eigenvalues (µ1′ , µ ′2 , ′) 3 and (ν1′, ν 2′ , 3′) associated with the linear and affine regions, respectively, of the vector field F′ of the circuit or system whose attractor is to be reproduced (up to linear conjugacy) by Chua’s oscillator. 2. Find a set of circuit parameters {C1 , C 2 , L, R, R0 , Ga , Gb , E} (or dimensionless parameters {α, β, γ, a, b, k}) so that the resulting eigenvalues µj and vj for Chua’s oscillator satisfy µj = µ′j and νj = ν′,j j = 1, 2, 3. Let { p1 , p2 , p3 , q1 , q2 , 3 } be the equivalent eigenvalue parameters defined by (40.16). Furthermore, let      p3 − q3   p2 − q2   p2 − q 2   k 2 = p2 −    p1 − p − q    −  p1 − q1   p1 − q1   1 1     p2 − q 2  k1 k3 = −  −k − p q  1 1 2    p3 − q3   k4 =− k1k3 + k2     p1 − q1    p − q3  k1 = − p3 +  3   p1 − q1 

 p2 − q 2   p1 − p − q   1 1 

(40.18)

The corresponding circuit parameters are given by C1 = 1

   k2 C2 = − 2  k3   2 k3  L=−  k4   k3  R=−  k2   2 kk  R0 = − 1 3  k2k4   p2 − q 2  k 2  Ga = − p1 +  +   p1 − q1  k3    p2 − q 2  k 2  Gb = −q1 +  +   p1 − q1  k3 

(40.19)

The breakpoint E of the piecewise-linear Chua diode can be chosen arbitrarily because the choice of E does not affect either the eigenvalues or the dynamics; it simply scales the circuit variables. In a practical realization of the circuit, one should scale the voltages and currents so that they lie within the inner three segments of the nonlinear resistor NR. © 2003 by CRC Press LLC

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Bifurcation and Chaos

1

R

6 +

R6

+

A2

0

−

R5

V−

V+

IR +

+ 4

5 L

C2

R1 R2

V2

C1

V1

VR

I3 −

−

− 2

R4

− A1 +

V+ 3 V−

R3 NR

FIGURE 40.32 Practical implementation of Chua’s oscillator using an op amp and four resistors to realize the Chua diode [10]. The negative resistor G is realized by means of a negative resistance converter (a2, R5, R6, and positive resistor R). If R2 = R3 and R5 = R6, and Ga = 1/R4 – 1/R1, Gb = 1/R4 + 1/R2, and G = –1/R. Component values are listed in Table 40.3.

The dimensionless parameters can be calculated as follows:     k  β = 42 k2k3    k1 γ=  k2k3   k3  p2 − q 2    a = −1 +  p1 − k2  p1 − q1    k3  p2 − q 2   b = −1 +  q1 −  k2  p1 − q1     k = sgn(k3 ) 

α=−

k2 k3 2

(40.20)

Example: Torus Figure 40.32 shows a practical implementation of Chua’s oscillator that exhibits a transition to chaos by torus breakdown. A complete list of components is given in Table 40.3. A SPICE simulation of this circuit produces a quasiperiodic voltage V(2) (= –V1), as expected (see Fig. 40.33). The resistor RO is not explicitly added to the circuit, but models the dc resistance of the inductor.

40.4 Van der Pol Neon Bulb Oscillator In a paper titled “Frequency Demultiplication,” the eminent Dutch electrical engineer Balthazar van der

Pol described an experiment in which, by tuning the capacitor in a neon bulb RC relaxation oscillator

© 2003 by CRC Press LLC

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TABLE 40.3

Component List for the Chua Oscillator in Fig. 40.32

Element

Description Op Amp( --12 AD712, TL082, or Equivalent)

A1

Amp( 1--2 AD712,

A2

Value

Tolerance

—

—

— 47 nF 820 nF

— ±5% ±5%

-1 W Resistor 4

6.8 kΩ

±5%

R2

œmp W Resistor

47 kΩ

±5%

R3

1- W Resistor 4

47 kΩ

±5%

R4 R5

Potentiometer W Resistor

2 kΩ 220 Ω

— ±5%

R6

1- W Resistor 4

220 Ω

±5%

R L

Potentiometer Inductor(TOKO-Type 10 RB, or Equivalent)

C1 C2

Op Capacitor Capacitor

R1

TL082, or Equivalent)

2 kΩ 18 mH

— ±10%

2.0V

0V

−2.0V

−4.0V

−6.0V 50MS

60MS

70MS

80MS

90MS

100MS

FIGURE 40.33 PSpice simulation (.TRAN 0.01MS 100 MS 50 MS) of Fig. 40.32 with initial conditions .IC V(2) = –0.1

V(1) = –0.1 and tolerances .OPTIONS RELTOL = 1 E -4 ABSTOL = 1 E – 4 yields this quasiperiodic voltage waveform at node 2.

i R Ne

E

Es

+ _

C

Rs

FIGURE 40.34 Sinusoidally driven neon bulb relaxation oscillator. Ne is the neon bulb.

driven by a sinusoidal voltage source (see Fig. 40.34), “currents and voltages appear in the system which are whole submultiples of the driving frequency” [11]. The circuit consists of a high-voltage dc source E attached via a large series resistance R to a neon bulb and capacitor C that are connected in parallel; this forms the basic relaxation oscillator. Initially, the capacitor is discharged and the neon bulb is nonconducting. The dc source charges C with time constant © 2003 by CRC Press LLC

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1139

Bifurcation and Chaos

SYSTEM PERIOD/T 14

12

10

8

6

4

2

0 0

4

8

12

16

20

24

28

C (nF)

FIGURE 40.35 Normalized current pulse pattern repetition rate vs. C for the sinusoidally driven neon relaxation oscillator in Fig. 40.34, showing a coarse staircase structure of mode-lockings. Source: M. P. Kennedy and L. O. Chua, “Van der Pol and Chaos,” IEEE Trans. Circuits Syst., vol. CAS-33, p. 975, Oct. 1986.  1986 IEEE.

RC until the voltage across the neon bulb is sufficient to turn it on. Once lit, he bulb presents shunt low resistance path to the capacitor. The voltage across the capacitor falls exponentially until the neon arc is quenched, the bulb is returned to its “off” state, and the cycle repeats. In series with the neon bulb is inserted a sinusoidal voltage source Es = E0 sin(2π fs t); its effect is to perturb the “on” and “off ” switching thresholds of the capacitor voltage. Experimental results for this circuit are summarized in Fig. 40.35, where the ratio of the system period (time interval before the pattern of current pulses repeats itself) to the period T of the forcing is plotted versus the capacitance C. Van der Pol noted that as the capacitance was increased from that values (C0) for which the natural frequency f0 of the undriven relaxation oscillator equaled that of the sinusoidal source (system period/T = 1), the system frequency made “discrete jumps from one whole submultiple of the driving frequency to the next” (detected by means of “a telephone coupled loosely in some way to the system”). Van der Pol noted that “often an irregular noise is heard in the telephone receiver before the frequency jumps to the next lower value”; van der Pol had observed chaos. Interested primarily in frequency demultiplication, he dismissed the “noise” as “a subsidiary phenomenon.” Typical current waveforms, detected by means of a small current-sensing resistor Rs placed in series with the bulb are shown in Fig. 40.36. These consist of a series of sharp spikes, corresponding to the periodic firing of the bulb. Figure 40.36(c) shows a nonperiodic “noisy” signal of the type noticed by van der Pol. The frequency locking behavior of the driven neon bulb oscillator circuit is characteristic of forced oscillators that contain two competing frequencies: the natural frequency f0 of the undriven oscillator © 2003 by CRC Press LLC

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i (µA) 800

i (µA)

800

600

600

400

400

200

200

0

0 20.0

21.0

22.0

23.0

24.0 t (ms)

20.0

21.0

T

22.0

23.0

24.0 t (ms)

2T

(a)

(b) i (µA)

800

600

400

200

0 80

100

120

140

160 t (ms)

(c)

FIGURE 40.36 Periodic and chaotic neon bulb current waveforms. (a) One current pulse per cycle of Es :fs /fd = 1/1; (b) one current pulse every two cycles of Es : fs /fd = 2/1; (c) “noisy” current waveform.

and the driving frequency fs . If the amplitude of the forcing is small, either quasiperiodicity or modelocking occurs. For a sufficiently large amplitude of the forcing, the system may exhibit chaos.

Winding Numbers Subharmonic frequency locking in a forced oscillator containing two competing frequencies f1 and f2 may be understood in terms of a winding number. The concept of a winding number was introduced by Poincaré to describe periodic and quasiperiodic trajectories on a torus. A trajectory on a torus that winds around the minor axis of the torus with frequency f1 revolutions per second, and completes revolution of the major axis with frequency f2, may be parametrized by two angular coordinates θ1 ≡ f1t and θ2 ≡ f2t, as illustrated in Fig. 40.37. The angles of rotation θ1 and θ2 about the major and minor axes of the torus are normalized so that one revolution corresponds to a change in θ of 1. A Poincaré map for this system can be defined by sampling the state θ1 with period τ = 1/f2. Let θk = θ1 (kτ). The Poincaré map has the form θk+1 = G(θk ), © 2003 by CRC Press LLC

k = 0, 1, 2, …

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1141

Bifurcation and Chaos

∑

θk

θ1

G(θk)

θ2

FIGURE 40.37 A trajectory on a torus is characterized by two normalized angular coordinates. θ1 = f1 t is the angle of rotation about the minor axis of the torus, while θ2 = f2 t is the angle of rotation along the major axis, where f1 and f2 are the frequencies of rotation about the corresponding axes. A Poincaré map θk+1 = G(θk) is defined by sampling the trajectory with frequency 1/f2. The winding number w counts the average number of revolutions in the Poincaré section per iteration of the map.

If f1 /f2 = p/q is rational, then the trajectory is periodic, closing on itself after completing q revolutions about the major axis of the torus. In this case, we say that the system is periodic with period q and completes p cycles per period. If the ratio p/q is irrational then the system is quasiperiodic; a trajectory covers the surface of the torus, coming arbitrarily close to every point on it, but does not close on itself. The winding number w is defined by

w = lim

k→ ∞

G (k ) (θ0 ) k

where G (k) denotes the k-fold iterate of G and θ0 is the initial state. The winding number counts the average number of revolutions in the Poincaré section per iteration. Equivalently, w equals the average number of turns about the minor axis per revolution about the major axis of the torus.15 Periodic orbits possess rational winding numbers and are called resonant; quasiperiodic trajectories have irrational winding numbers.

The Circle Map A popular paradigm for explaining the behavior of coupled nonlinear oscillators with two competing frequencies is the circle map: K   θk+1 =  θk + sin(2πθk ) + Ω mod 1, k = 0, 1, 2, …   2π

(40.21)

so-called because it maps the circle into itself. The sinusoidal term represents the amplitude of the forcing, and Ω is the ratio of the natural frequency of the unperturbed system and the forcing frequency [18]. When K ≡ 0, the steady state of the discrete-time dynamical system (40.22) is either periodic or quasiperiodic, depending on whether Ω is rational or irrational.

15Either frequency may be chosen to correspond to the major axis of the torus, so the winding number and its reciprocal are equivalent.

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1.0 0.8 0.6 0.4

1 4

1 3

2 5

1 2

3 5

3 4

2 3 0.24

0.22

1 5

0.2

0.25

0.0 0.0

0.2

0.4

Ω

0.6

3 14

3 2 13 9

0.26

0.8

0.27

1.0

FIGURE 40.38 Devil’s staircase for the circle map with K = 1. The steps indicate the regions in which w is constant. The staircase is self-similar in the sense that its structure is reproduced qualitatively at smaller scales (see inset). Source: J. A. Glazier and A. Libchaber, “Quasi-periodicity and dynamical systems: An experimentalist’s view,” IEEE Trans. Circuits Syst., vol. 35, p. 793, July 1988. © 1988 IEEE.

If the amplitude K of the forcing is nonzero but less than unity, the steady-state is q-periodic when Ω = p/q is rational. In this case, a nonzero mode-locked window [Ωmin(w), Ωmax(w)] occurs, over which w = p/q. A mode-locked region is delimited by saddle-node bifurcations at Ωmin(w) and Ωmax(w) [18]. The function w(Ω) in Fig. 40.38 is monotone increasing and forms a Devil’s staircase with plateaus at every rational value of w — for example, the step with winding number 1/2 is centered at Ω = 0.5. An experimental Devil’s staircase for the driven neon bulb circuit, with low-amplitude forcing, is shown in Fig. 40.39. As the amplitude k is increased, the width of each locked interval in the circle map increases so that mode-locking becomes more common and quasiperiodicity occurs over smaller ranges of driving fre­ quencies. The corresponding (K, Ω) parameter space diagram (see Fig. 40.40) consists of a series of distorted triangles, known as Arnold Tongues, with apexes that converge to rational values of Ω at K = 0. Within a tongue, the winding number is constant, yielding one step of the Devil’s staircase. The winding numbers of adjacent tongues are related by a Farey tree structure. Given two periodic windows with winding number w1 = p/q and w2 = r/s, another periodic window with winding number w = (αp + βr)/(αq + βs) can always be found, where p, q, r, and s are relatively prime and α and β are strictly positive integers. Furthermore, the widest mode-locked window between w1 and w2 has winding number (p + r)/(q + s). For example, the widest step between those with winding numbers 1/2 and 2/3 in Fig. 40.38 has w = 3/5. The sum of the widths of the mode-locked states increases monotonically from zero at K = 1 to unity at K = 1. Below the critical line K = 1, the tongues bend away from each other and do not overlap. At K = 1, tongues begin to overlap, a kink appears in the Poincaré section and the Poincaré map develops a horseshoe; this produces coexisting attractors and chaos. The transition to chaos as K is increased through K = 1 may be by a period-doubling cascade within a tongue, intermittency, or directly from a quasiperiodic trajectory by the abrupt disappearance of that trajectory (a blue sky catastrophe). This qualitative behavior is observed in van der Pol’s neon bulb circuit.

Experimental Observations of Mode-Locking and Chaos in van der Pol’s Neon Bulb Circuit With the signal source Es zeroed, the natural frequency of the undriven relaxation oscillator is set to 1 kHz by tuning capacitance C to C0. A sinusoidal signal with frequency 1 kHz and amplitude E0 is applied as shown in Fig. 40.34. The resulting frequency of the current pulses (detected by measuring the voltage across Rs) is recorded with C as the bifurcation parameter.

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Bifurcation and Chaos

fs/fd

FORCED NEON BULB CIRCUIT

3.00 2.80 2.60 2.40 2.20 2.00 1.80 1.60 1.40 1.20 1.00 1.00

1.50

2.00

2.50 fs (kHz)

FIGURE 40.39 Experimentally measured staircase structure of lockings for a forced neon bulb relaxation oscillator. The winding number is given by fs /fd, the ratio of the frequency of the sinusoidal driving signal to the average frequency of current pulses through the bulb. Source: M. P. Kennedy, K. R. Krieg, and L. O. Chua, “The Devil’s staircase: The electrical engineer’s fractal,” IEEE Trans. Circuits Syst., vol. 36, p. 1137, Aug. 1989. © 1989 IEEE.

1.50 1.25 1 1 5 4

1 3

2 5

1 2

3 5

2 3

3 4 4 5

k

1.0 0.75 0.50 0.25 0.0

0.0

0.2

0.4

Ω

0.6

0.8

1.0

FIGURE 40.40 Parameter space diagram for the circle map showing Arnold tongue structure of lockings in the K – Ω plane. The relative widths of the tongues decrease as the denominator of the winding number increases. Below the critical line K = 1, the tongues bend away from each other and do not overlap; for K > 1, the Poincaré map develops a fold and chaos can occur. Source: J. A. Glazier and A. Libchaber, “Quasi-periodicity and dynamical systems: An experimentalist’s view,” IEEE Trans. Circuits Syst., vol. 35, p. 793, July 1988. © IEEE.

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C Bifurcation Sequence If a fixed large-amplitude forcing Es is applied and C is increased slowly, the system at first continues to oscillate and 1 kHz [Fig. 40.36(a)] over a range of C, until the frequency “suddenly” drops to 1000/2 Hz [Fig. 40.36(b)], stays at that value over an additional range of capacitance, drops to 1000/3 Hz, then 1000/4 Hz, 1000/5 Hz, and so on as far as 1000/20 Hz. These results are summarized in Fig. 40.35. Between each two submultiples of the oscillator driving frequency, a further rich structure of submul­ tiples is found. At the macroscopic level (the coarse structure examined by van der Pol) increasing the value of C causes the system periods to step from T (1 ms) to 2T, 3T, 4T, …, where the range of C for which the period is fixed is much greater than that over which the transitions occur (Fig. 40.35). Examining the shaded transition regions more closely, one finds that between any two “macroscopic” regions where the period is fixed at (n – 1)T and nT (n > 1), respectively, there lies a narrower region over which the system oscillates with stable period (2n – 1)T. Further, between (n – 1)T and (2n –1)T, one finds a region of C for which the period is (3n – 2)T, and between (2n – 1)T and nT, a region with period (3n – 1)T. Indeed, between any two stable regions with periods (n – 1)T and nT, respectively, a region with period (2n –1)T can be found. Figure 40.41 depicts an enlargement of the C axis in the region of the T to 2T macro-transition, showing the finer period-adding structure. Between T and 2T is a region with stable period 3T. Between this and 2T, regions of periods 5T, 7T, 9T, … up to 25T are detected. Current waveforms corresponding to period-3 and period-5 steps, with winding numbers 3/2 and 5/3, respectively, are shown in Fig. 40.42.

SYSTEM PERIOD/T

26 24 22 20 18 16 14 12 10 8 6 4 2 0 0

C0

2.0

2.5

3.0

3.5

C (nF)

FIGURE 40.41 Experimental pulse pattern repetition rate versus C for van der Pol’s forced neon bulb oscillator, showing fine period-adding structure. Source: M. P. Kennedy and L. O. Chua, “Van der Pol and chaos,” IEEE Trans, Circuits Syst., vol. CAS-33, p. 975, Oct. 1986 © 1986 IEEE.

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1145

Bifurcation and Chaos

i (µA) 800

i (µA)

800

600

600

400

400

200

200

0

0 20.0

22.0

24.0

26.0

28.0 t (ms)

20.0

3T (a)

22.0

24.0

26.0

28.0 t (ms)

5T (b)

FIGURE 40.42 Neon bulb current waveforms. (a) Two pulses every three cycles of Ezis :fs /fd = 3/2; (b) three pulses every five cycles fs /fd = 5/3.

A region of period 4T lies between T and 3T, with steps 7T, 10T, 13T, … up to 25T between that and 3T. In practice, it becomes difficult to observe cycles with longer periods because stochastic noise in the experimental circuit can throw the solution out of the narrow window of existence of a high period orbit. Experimental fs Bifurcation Sequence with Low-Amplitude Forcing An experimental Devil’s staircase may be plotted for this circuit by fixing the parameters of the relaxation oscillator and the amplitude of the sinusoidal forcing signal, and choosing the forcing frequency fs as the bifurcation parameter. The quantity fs /fd is the equivalent winding number in this case, where fd is the average frequency of the current pulses through the neon bulb. Experimental results for the neon bulb circuit with low-amplitude forcing are presented in Figs. 40.39 and 40.43. The monotone staircase of lockings is consistent with a forcing signal of small amplitude. Note that the staircase is self-similar in the sense that its structure is reproduced qualitatively at smaller scales of the bifurcation parameter. If the amplitude of the forcing is increased, the onset of chaos is indicated by a nonmonotonicity in the staircase.

Circuit Model The experimental behavior of van der Pol’s sinusoidally driven neon bulb circuit may be reproduced in simulation by an equivalent circuit (see Fig. 40.44) in which the only nonlinear element (the neon bulb) is modeled by a nonmonotone current-controlled resistor with a series parasitic inductor Lp . The corresponding state equations are dVC 1 1 E V − I + =− dt RC C C L RC f ( I L ) E 0 sin(2πfst ) dI L R 1 − = VC − s I L − dt Lp Lp Lp Lp where V = f(I) is the driving-point characteristic of the current-controlled resister (see Fig. 40.45). © 2003 by CRC Press LLC

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1146

fs/fd

The Circuits and Filters Handbook, Second Edition

FORCED NEON BULB CIRCUIT

fs/fd

3.00

FORCED NEON BULB CIRCUIT

2.85

2.90 2.80 2.80 2.75

2.70 2.60

2.70

2.50 2.65

2.40 2.30

2.60

2.20 2.55

2.10 2.00

2.40 2.40

2.50

2.60

2.56

2.70 fs (kHz)

2.58

2.60

2.62

2.64 fs (kHz)

FIGURE 40.43 Magnification of Fig. 40.39 showing self-similarity. Source: M. P. Kennedy, K. R. Krieg, and L. O. Chua, “The Devil’s staircase: The electrical engineer’s fractal,” IEEE Trans. Circuits Syst., vol. 36, p. 1137, Aug. 1989. © 1989 IEEE.

iL

R Lp + E

VC

+ C

V = f(iL)

−

−

Es

+ −

Rs

FIGURE 40.44 Van der Pol’s neon bulb circuit — computer model. The bulb is modeled by a nonmonotonic current-controlled nonlinear resistor with parasitic transit inductance Lp.

40.5 Synchronization of Chaotic Circuits Chaotic steady-state solutions are characterized by sensitive dependence on initial conditions; trajectories of two identical autonomous continuous-time dynamical systems started from slightly different initial © 2003 by CRC Press LLC

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1147

Bifurcation and Chaos

i (µA)

i (µA)

300

300

250

250

200

200

150

150

100

100

50

50

0

0 0

50

60 v(V) (a)

70

80

0

50

60 v(V) (b)

70

80

FIGURE 40.45 Neon bulb driving-point characteristics: (a) measured and (b) simulated. Source: M. P. Kennedy and L. O. Chua, “Van der Pol and chaos,” IEEE Trans. Circuit Syst., vol. CAS-33, p. 976, Oct. 1986. © 1986 IEEE.

conditions quickly become uncorrelated. Surprisingly perhaps, it is nevertheless possible to synchronize these systems in the sense that a trajectory of one asymptotically approaches that of the other. Two trajectories X1(t) and X2(t) are said to synchronize if lim X1 (t ) − X 2 (t ) = 0

t→ ∞

In this section, we describe two techniques for synchronizing chaotic trajectories.

Linear Mutual Coupling The simplest technique for synchronizing two dynamical systems X˙ 1 = F1 ( X1 )

X1 (0) = X10

X˙ 2 = F2 ( X 2 )

X 2 (0) = X 20

is by linear mutual coupling of the form X˙ 1 = F1 ( X1 ) + K( X 2 − X1 )

X1 (0) = X10

X˙ 2 = F2 ( X 2 ) + K( X 2 − X1 )

X 2 (0) = X 20

(40.22)

where X1,X2 ∈n and K = diag(K11, K22, …, Knn)T. Here, X1(t ) is called the goal dynamics. The synchronization problem may be stated as follows: find K such that © 2003 by CRC Press LLC

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The Circuits and Filters Handbook, Second Edition

lim X1 (t ) − X 2 (t ) = 0

t→ ∞

that is, that the solution X 2 (t ) synchronizes with the goal trajectory X1(t). In general, it is difficult to prove that synchronization occurs, unless an appropriate Lyapunov func­ tion16 of the error system E(t ) = X1(t ) – X 2 (t ) can be found. However, several examples exist in the liter­ ature where mutually coupled chaotic systems synchronize over particular ranges of parameters. Example: Mutually Coupled Chua’s Circuits. Consider a linear mutual coupling of two Chua’s circuits. In dimensionless coordinates, the system under consideration is

[

]

dX1 = α X 2 − X1 − f ( X1 ) + K11 ( X 4 − X1 ) dt dX 2 = X1 − X 2 − X 3 + K 22 ( X 5 − X 2 ) dt dX 3 = −βy + K 33 ( X 6 − X 3 ) dt

(

)

dX 4 = α X 5 − X 4 − f ( X 4 ) + K11 ( X1 − X 4 ) dt dX 5 = X 4 − X 5 − X 6 + K 22 ( X 2 − X 5 ) dt dX6 = −βX 5 + K 33 ( X 3 − X 6 ) dt Two mutually coupled Chua’s circuits characterized by α = 10.0, β = 14.87, a = –1.27, and b = –0.68 will synchronize (the solutions of the two systems will approach each other asymptotically) for the following matrices K: X1 – coupling K11 > 0.5, K22 = K33 = 0 X2 – coupling K22 > 5.5, K11 = K33 = 0 X3 – coupling 0.7 < K33 < 2, K11 = K22 = 0 Coupling between states X1 and X 4 may be realized experimentally by connecting a resistor between the tops of the nonlinear resistors, as shown in Fig. 40.46. States X 2 and X 5 may be coupled by connecting the tops of capacitors C 2 by means of a resistor. An INSITE simulation of the system, which confirms synchronization of the two chaotic Chau’s circuits in the case of linear mutual coupling between state VC1 and VC′1 is presented in Fig. 40.47.

Pecora–Carroll Drive-Response Concept The drive-response synchronization scheme proposed by Pecora and Carroll applies to systems that are drive-decomposable [16]. A dynamical system is called drive-decomposable if it can be partitioned into two subsystems that are coupled so that the behavior of the second (called the response subsystem) depends on that of the first, but the behavior of the first (called the drive subsystem) is independent of that of the second. To construct a drive-decomposable system, an n-dimensional autonomous continuous-time dynamical system

16

For a comprehensive exposition of Lyapunov stability theory, see [19].

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1149

Bifurcation and Chaos

R

C2

L IL

+

+

+

VC2

VC1

−

−

−

+

+

+

V′C2

V′C1

−

−

IR

C1 VR

NR RX

R

L

C2 I′L

C1 V′R

I′R NR

−

FIGURE 40.46 Synchronization of two Chua’s circuits by means of resistive coupling between VC1 and V C′1 . 0.816

0.816

0.411

0.411

0.006 x[2]

−0.400

0.006

x[5]

−0.400

−0.805

−3.662

−1.838

−0.015 x[1]

−0.805 1.808

3.632

−3.662

0.816

5.577

0.411

2.802

0.006 x[5]

−0.400

0.026

x[6]

−2.750

−0.805

−0.805

−0.400

−5.525 0.006 x[2]

0.411

0.816

−5.525

−1.838

−0.015 x[4]

1.808

3.632

−2.750

0.026 x[3]

2.802

5.577

FIGURE 40.47 INSITE simulation of the normalized dimensionless form of Fig. 40.46, illustrating synchronization by mutual coupling of state variables. Identify {x[1], x[2], x[3]} with {VC1, VC2, IL } and {x[4], x[5], x[6]} with {V C′ 1, V C′2, I L′ } synchronizes with VC2 (t) and I ′L(t) synchronizes with IL(t). Source: L. O. Chua, M. Itoh, L. Ko˘carev, and K. Eckert, “Chaos synchronization in Chua’s Circuit,” J. Circuits Syst. Comput., vol. 3, no. 1, p. 99, Mar. 1993.

X˙ = F( X )

X(0) = X 0

(40.23)

where X = (X1 , X 2 , ... , X n )T and F(X) = [F1(X), F2(X), …, Fn(X)]T, is first partitioned into two subsystems X˙ 1 = F1 ( X1 , X 2 )

X1 (0) = X10

(40.24)

X˙ 2 = F2 ( X1 , X 2 )

X 2 (0) = X 20

(40.25)

where X1 = (X1 , X 2 ,..., X m )T , X 2 = (X m+1 , X m+2 ,..., X n )T, © 2003 by CRC Press LLC

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The Circuits and Filters Handbook, Second Edition

 F1 ( X1 , X 2 )     F (X , X )  2 1 2  F1 ( X1 , X 2 ) =    M      Fm ( X1 , X 2 ) and  Fm + 1 ( X1 , X 2 )     F ( X , X ) m+2 1 2  F2 ( X1 , X 2 ) =    M      Fn ( X1 , X 2 )  An identical (n – m)-dimensional copy of the second subsystem, with X 3 as state variable and X1 as input, is appended to form the following (2n – m)-dimensional coupled drive-response system: X˙ 1 = F1 ( X1 , X 2 )

X1 (0) = X10

(40.26)

X˙ 2 = F2 ( X1 , X 2 )

X 2 (0) = X 20

(40.27)

X˙ 3 = F2 ( X1 , X 3 )

X 3 (0) = X 30

(40.28)

The n-dimensional dynamical system defined by (40.26) and (40.27) is called the drive system and (40.28) is called the response subsystem. Note that the second drive subsystem (40.27) and the response subsystem (40.28) lie in state spaces of dimension (n – m) and have identical vector fields F2 and inputs X1 . Consider a trajectory X 3 (t ) of (40.29) that originates from an initial state X30 “close” to X20. We may think of X2(t) as a perturbation of X3(t). In particular, define the error X3(t) = X2(t) – X3(t). The trajectory X2(t) approaches X3(t) asymptotically (synchronizes) if X2 → 0 as t → ∞. Equivalently, the response subsystem (40.29) is asymptotically stable when driven with X1(t). The stability of an orbit of a dynamical system may be determined by examining the linearization of the vector field along the orbit. The linearized response subsystem is governed by

(

)

x˙ 3 = D X3 F2 X 1 (t ), X 3 x 3 ,

x 3 (0) = x 30

where Dx3F2(X1(t), X3) denotes the partial derivatives of the vector field F2 of the response subsystem with respect to X3. This is linear time-varying system whose state transition matrix Φt (X10, X30) maps a point x30 into X3(t). Thus,

(

)

x 3 (t ) = Φt X 10 , X 30 x 30 Note that Φt is a linear operator. Therefore, an (n – m)-dimensional ball Bε(X30 ) of radius ε about X30 is mapped into an ellipsoid whose principal axes are determined by the singular values of Φt . In particular, a ball of radius ε is mapped by Φt into an ellipsoid, the maximum and minimum radii of which are bounded by the largest and smallest singular values, respectively, of Φt . © 2003 by CRC Press LLC

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Bifurcation and Chaos

The conditional Lyapunov exponents λi (X10, X20) (hereafter denoted CLE) are defined by

(

[(

)

)]

1 λ i X 10 , X 20 = lim ln σ i φt X 10 , X 20 , t→∞ t

i = 1, 2, …, (n − m)

whenever the limit exists. The term conditional refers to the fact that the exponents depend explicitly on the trajectory φt (X10, X20 ) of the drive system. Given that ε remains infinitesimally small, one of considering the local linearized dynamics along the flow determined by φt (X10, X20) and determining the average local exponential rates of expansion and contraction along the principal axes of an ellipsoid. If all CLEs are negative, the response subsystem is asymptotically stable. A subsystem, where all the CLEs are negative, is called a stable subsystem. A stable subsystem does not necessarily exhibit dc steady-state behavior. For example, while an asymp­ totically stable linear parallel RLC circuit has all negative LEs, the system settles to a periodic steady-state solution when driven with a sinusoidal current. Although the RLC subcircuit has negative CLEs in this case, the complete forced circuit has one nonnegative LE corresponding to motion along the direction of the flow. Theorem 4 (Pecora and Carroll): The trajectories X2(t) and X3(t) will synchronize only if the CLEs of the response system (40.28) are all negative. Note that this is a necessary but not sufficient condition for synchronization. If the response and second drive subsystems are identical and the initial conditions X20 and X30 are sufficiently close, and the CLEs of (40.28) are all negative, synchronization will occur. However, if the systems are not identical or the initial conditions are not sufficiently close, synchronization might not occur, even if all of the CLEs are negative. Although we have described it only for an autonomous continuous-time system, the drive-response technique may also be applied for synchronizing nonautonomous and discrete-time circuits. Cascaded Drive-Response Systems The drive-response concept may be extended to the case where a dynamical system can be partitioned into more than two parts. A simple two-level drive-response cascade is constructed as follows. Divide the dynamical system X˙ = F( X ),

X(0) = X 0

(40.29)

into three parts: X˙ 1 = F1 ( X 1 , X 2 , X 3 )

X 1 (0) = X 10

(40.30)

X˙ 2 = F2 ( X 1 , X 2 , X 3 )

X 2 (0) = X 20

(40.31)

X˙ 3 = F3 ( X 1 , X 2 , X 3 )

X 3 (0) = X 30

(40.32)

Now, construct an identical copy of the subsystems corresponding to (40.31) and (40.32) with X1(t) as input: X˙ 4 = F2 ( X 1 , X 4 , X 5 )

X 4 (0) = X 40

(40.33)

X˙ 5 = F3 ( X 1 , X 4 , X 5 )

X 5 (0) = X 50

(40.34)

If all the CLEs of the driven subsystem composed of (40.33) and (40.34) are negative then, after the transient decays, X4(t) = X2(t) and X5(t) = X3(t). © 2003 by CRC Press LLC

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Note that (40.30)–(40.34) together define one large coupled dynamical system. Hence, the response subsystem can exhibit chaos even if all of its CLEs are negative. Proceeding one step further, we reproduce subsystem (40.30): X˙ 6 = F1 ( X 6 , X 4 , X 5 )

X 6 (0) = X 60

(40.35)

As before, if all of the conditional Lyapunov exponents of (40.35) are negative, then X6(t) – X1(t) → 0. If the original system could be partitioned so that (40.30) is one-dimensional, then using (40.33)–(40.35) as a driven response system, all of the variables in the drive system could be reproduced by driving with just one variable X1(t). This principle can be exploited for spread-spectrum communi­ cation using a chaotic carrier signal. Example: Synchronization of Chua’s Circuits Using the Drive-Response Concept. Chua’s circuit may be partitioned in three distinct ways to form five-dimensional, drive-decomposable systems: X1-drive configuration

[

]

dX1 = α X 2 − X1 − f ( X1 ) dt dX 2 = X1 − X 2 − X 3 dt dX 3 = −βX 2 dt dX 4 = X1 − X 4 − X 5 dt dX 5 = −βX 5 dt

With α = 10.0, β = 14.87, a = –1.27, and b = – 0.68, the CLEs for the (X2, X3) subsystem (calculated using INSITE) are (–0.5, –0.5). X2-drive configuration dX 2 = X1 − X 2 − X 3 dt

[

]

dX1 = α X 2 − X1 − f ( X1 ) dt dX 2 = −βX 2 dt

[

]

dX 4 = α X2 − X4 − f (X4 ) dt dX 5 = −βX 5 dt

This case is illustrated in Fig. 40.48. The CLEs of the (X1, X3) subsystem are 0 and – 2.5 ± 0.05. Because of the zero CLE, states X5 (t) and X3 (t) remain a constant distance X30 – X50  apart, as depicted in Fig. 40.49. © 2003 by CRC Press LLC

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1153

Bifurcation and Chaos

R

C2

L

+

+

VC2

VC1

−

−

−

+

+

IL

+

IR

C1 VR

NR

R − + L

C1 V′R

V′C1 −

I′L

I′R NR

−

FIGURE 40.48 Synchronization of two Chua’s circuits using the Pecora–Carroll drive-response method with VC2 as drive variable. 5.570

2.770

2.795

−0.005

0.019 x[3]

−2.781

x[5]

−2.757

−5.557

−5.532 −3.660

−1.833

−0.006 x[1]

1.821

3.648

−8.332

−3.660

3.648

2.770

1.821

−0.005

−0.006 x[4]

−1.833

−2.781

x[5]

−5.557

−3.660 −3.660

−1.833

−0.006 x[1]

1.821

3.648

−8.332

−5.532

−1.833 −0.006 x[4]

1.821

3.648

0.019 x[3]

2.795

5.570

−2.757

FIGURE 40.49 INSITE simulation of the normalized dimensionless form of Fig. 40.48, illustrating synchronization of state variables. Identify {x[1], x[2], x[3]} with {VC1, VC2, IL }, and {x[4], x[5]} with {VC′1 , I L′ } · V C′ 1(t) synchronizes with V C′ 1(t), and I L′(t) synchronizes with IL (t). Because one of the CLEs of the response subsystem is zero, the difference in the initial conditions IL0 – IL0 does not decay to zero. Source: L. O. Chua, M. Itoh, L. Ko˘carev, and K. Eckert, “Chaos synchronization in Chua’s circuits,” J. Circuits Syst. Comput., vol. 3, no. 1, p. 106, Mar. 1993.

X3-drive configuration dX 3 = −βX 2 dt

[

]

dX1 = α X 2 − X1 − f ( X1 ) dt dX 2 = X1 − X 2 − X 3 dt © 2003 by CRC Press LLC

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[

]

dX 4 = α X5 − X 4 − f (X 4 ) dt dX 5 = X 4 − X5 − X3 dt

The CLEs in this case are 1.23 ± 0.03 and –5.42 ± 0.02. Because the (X1, X2 ) subsystem has a positive CLE, the response subsystem does not synchronize.

40.6 Applications of Chaos Pseudorandom Sequence Generation One of the most widely used deterministic “random” number generators is the liner congruential gen­ erator, which is a discrete-time dynamical system of the form X k+1 = ( AX k + B) mod M,

k = 0, 1, …

(40.36)

where A, B, and M are called the multiplier, increment, and modulus, respectively. If A > 1, then all equilibrium points of (40.36) are unstable. With the appropriate choice of constants, this system exhibits a chaotic solution with a positive Lyapunov exponent equal to In A. However, if the state space is discrete, for example in the case of digital implementations of (40.37), then every steadystate orbit is periodic with a maximum period equal to the number of distinct states in the state space; such orbits are termed pseudorandom. By using in analog state space, a truly “random” chaotic sequence can be generated. A discrete-time chaotic circuit with an analog state space may be realized in switched-capacitor (SC) technology. Figure 40.50 is an SC realization of the parabolic map x k+1 = V − 0.5x k2

(40.37)

which, by the change of variables X k = Ax k + B

e

o

o

e

C

V e

o

C/2

X2k

C

− +

Xk

FIGURE 40.50 Switched-capacitor (SC) realization of the parabolic map xk+1 = V – 0.5 Xk2. The switches labeled o and e are driven by the odd and even phases, respectively, of a nonoverlapping two-phase clock.

© 2003 by CRC Press LLC

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1155

Bifurcation and Chaos

with µ = 1/(2A), B = 0.5, and A = (−1 ± 1 + 2V ) /(4V), is equivalent to the logistic map X k+1 = µX k (1 − X k )

(40.38)

The logistic map is chaotic for µ = 4 with Lyapunov exponent ln 2 [18]. Figure 40.16 is a bifurcation diagram of (40.38) with 0 ≤ µ ≤ 4. For V < 1.5, the steady-state solution of the SC parabolic map described by (40.37) is a fixed point. As the bifurcation parameter V is increased from 1.5 to 3 V, the circuit undergoes a series of perioddoubling bifurcations to chaos. V = 4 corresponds to fully developed chaos on the open interval (0 < Xk < 1) in the logistic map with µ = 4.

Spread-Spectrum and Secure Communications Modulation and coding techniques for mobile communication systems are driven by two fundamental requirements: that the communication channel should be secure and the modulation scheme should be tolerant of multipath effects. Security is ensured by coding and immunity from multipath degradation may be achieved by using a spread-spectrum transmission. With appropriate modulation and demodulation techniques, the “random” nature and “noise-like” spectral properties of chaotic circuits can be exploited to provide simultaneous coding and spreading of a transmission. Chaotic Switching The simplest idea for data transmission using a chaotic circuit is use the data to modulate some param­ eter(s) of the transmitter. This technique is called parameter modulation, chaotic switching, or chaos shift keying (CSK). In the case of binary data, the information signal is encoded as a pair of circuit parameter sets which produce distinct attractors in a dynamical system (the transmitter). In particular, a single control param­ eter µ may be switched between two values µ0, corresponding to attractor 0 and µ1, corresponding to 1. By analogy with FSK and PSK, this technique is known as chaos shift keying. The binary sequence to be transmitted is mapped into the appropriate control signal µ(t) and the corresponding trajectory switches, as required, between 1 and 0. One of the state variables of the transmitter is conveyed to the receiver, where the remaining state variables are recovered by drive-response synchronization. These states are then applied to the second stage of a drive-response cascade. At the second level, two matched receiver subsystems are constructed, one of which synchronizes with the incoming signal if a “zero” was transmitted, the other of which synchronizes only if a “one” was transmitted. The use of two receiver circuits with mutually exclusive synchronization properties improves the reliability of the communication system. Chaos shift keying has been demonstrated both theoretically and experimentally. Figure 40.51 depicts a CSK transmitter and receiver based on Chua’s circuit. The control parameter is a resistor with conduc­ tance ∆G whose effect is to modulate the slopes Ga and Gb of the Chua diode. Switch S is opened and closed by the binary data sequence and VC 1 is transmitted. At the receiver, the first subsystem (a copy of the (VC 2 , IL ) subsystem of the transmitter) synchronizes with the incoming signal, recovering VC 2 (t). Thus, VC 21 (t) → VC 2 (t). The synchronized local copy of VC 1 (t) is then used to synchronize two further subsystems correspond­ ing to the VC 1 subsystem of the transmitter with and without the resistor ∆G. If the switch is closed at the transmitter, V ′C 12 (but not VC 12 ) synchronizes with VC 1 and if the switch is open, VC 12 (but not VC′12 ) synchronizes with VC 1 . Figure 40.52 presents simulated results for a similar system consisting of two Chua’s circuits. At the receiver, a decision must be made as to which bit has been transmitted. In this case, bout was derived using the rule © 2003 by CRC Press LLC

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1156

The Circuits and Filters Handbook, Second Edition

R

C2

L

+

+

VC2

VR

−

IL

IR

+

S C1

NR ∆G

−

VC1 −

TRANSMITTER − +

R

+

+ L

VC1

C2

−

VC21 −

FIRST RECEIVER SUBSYSTEM R “ONE” + NR

− +

C1

VC12 −

+ VC21

R “ZERO”

−

+ NR ∆G

C1

V′C12 −

SECOND RECEIVER SUBSYSTEMS

FIGURE 40.51 Chaos shift keying communication system using Chua’s circuit. When a “one” is transmitted, switch

S remains open, VC21 (t) synchronizes with VC2 (t), VC12 (t) synchronizes with VC1 (t), and VC′12 (t) falls out of synchro­

nization with VC1 (t). When a “zero” is transmitted, switch S is closed, VC21(t) synchronizes with VC2(t), VC12(t) falls out of synchronization with VC1(t), and V C′ 12(t) synchronizes with VC1(t).

bout

0, bold = 0  1, bold = 1 = bold  1 − b  old

for for for for

a0 < ε, a1 > ε  a0 > ε, a1 < ε  a0 < ε, a1 < ε  a0 > ε, a1 > ε

where bold is the last bit received and bout is the current bit [14]. Chaotic Masking Chaotic masking is a method of hiding an information signal by adding it to a chaotic carrier at the transmitter. The drive-response synchronization technique is used to recover the carrier at the receiver. Figure 40.53 is a block diagram of a communication system using matched Chua’s circuits. The receiver has the same two-layer structure as in the previous example. The first subcircuit, which has very negative © 2003 by CRC Press LLC

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Bifurcation and Chaos

1.5

(a)

1

bin

0.5 0 (b) 2 s 1 2

(c)

∆0 1 0 −1 (d) 2

∆1

0

(e)

0.8 a0 0.6 0.4 0.2 0

(f)

1 a1 0.5 0 1.5

(g)

bout 1 0.5 0 0

10

20 time [ms]

30

40

FIGURE 40.52 Chaos shift keying waveforms. (a) Binary input signal bin; (b) transmitted signal s(t);(c) response ∆0 = VC12 – VC1; (d) response ∆0 = VC′12 – VC1; (e) 40-point moving average of ∆0; (f) 40-point moving average of ∆1; (g) output binary signal bout when ε = 0.1. Source: M. Ogorzalek, “Taming chaos — Part I: Synchronization,” IEEE Trans. Circuits Syst. I, vol. 40, p. 696, Oct. 1993. © 1993 IEEE.

conditional Lyapunov exponents, synchronizes with the incoming signal, despite the perturbation s(t), and recovers VC 2 . The second subcircuit, when driven by VC 2, produces the receiver’s copy of VC 1 . The information signal r(t) is recovered by subtracting the local copy of VC 1 from the incoming signal VC 1 +s(t).

Vector Field Modulation With vector field modulation, an information-carrying signal is added to the vector field at the transmitter and recovered at the receiver [9]. A dynamical system is partitioned as follows: © 2003 by CRC Press LLC

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The Circuits and Filters Handbook, Second Edition

R

L

C2

− +

+

+

VC2

VR

−

−

IL

IR

+

+

NR C1

+

+ VC1 + s(t)

s(t)

VC1 −

−

TRANSMITTER

− +

R

+

+

VC1 + s(t)

L

C2

VC21

−

− FIRST RECEIVER SUBSYSTEM

− +

R

− + +

+ VC21

+

NR C1

VC12

−

−

−

+

VC1 + s(t) r(t) −

SECOND RECEIVER SUBSYSTEM

FIGURE 40.53 Chaos masking using Chua’s circuits. At the transmitter, the information signal s(t) is added to the chaotic carrier signal VC1 (t). Provided s(t) is sufficiently small and the first receiver subsystem is sufficiently stable, VC21 (t) synchronizes with VC2 (t). This signal is applied to a second receiver subsystem, from which an estimate VC12(t) of the unmodulated carrier VC1 (t) is derived. VC12 is subtracted from the incoming signal VC1 + s(t) to yield the received signal r(t). The method works well only if s(t) is much smaller than VC1 (t).

X˙ 1 = F1 ( X 1 , X 2 )

X 1 (0) = X 10

X˙ 2 = F2 ( X 1 , X 2 )

X 2 (0) = X 20

The information signal S(t) is added into the transmitter X˙ 1 = F1 ( X 1 , X 2 ) + S(t ) X˙ 2 = F2 ( X 1 , X 2 ) and the state X1(t) transmitted.

© 2003 by CRC Press LLC

X 1 (0) = X 10 X 2 (0) = X 20

(40.39) (40.40)

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Bifurcation and Chaos

R

C2

L

+

+

VC2

VR

−

−

IL

IR

+ NR

s(t) C1

VC1 −

TRANSMITTER

− +

R

r(t)

+

+

VC1

V′R

−

−

I′R NR C1

+

+

V′C1

V′C2

−

−

C2

L I′L

RECEIVER

FIGURE 40.54 Vector field modulation using Chua’s circuit. The signal s(t) to be transmitted is applied as pertur­ bation of the vector field at the transmitter. The receiver’s (V C′2 , I L′ ) subsystem synchronizes with the corresponding subsystem at the transmitter. This synchronized subsystem drives the V C′1 subsystem. The transmitted signal s(t) is recovered as an excess current r(t) at the receiver.

The receiver contains a copy of the second drive subsystem (40.41) X˙ 3 = F2 ( X 1 , X 3 )

X 3 (0) = X 30

where the state X3(t) synchronizes with X2(t), and a demodulator, R(t ) = X˙ 1 − F1 ( X 1 , X 3 ) which is used to recover S(t). If all of the CLEs of the response system are negative, and the initial conditions are sufficiently close, then X 3 (t ) → X 2 (t ) and the recovered signal R(t) equals S(t).

Example: Communication via Vector Field Modulation Using Chua’s Circuits A communication system based on Chua’s circuit that uses the vector field modulation technique and a chaotic carrier is illustrated in Fig. 40.54. In this case, the signal to be transmitted is the scalar current s(t), which is recovered as a current r(t) at the receiver. The state equations of the coupled drive-response system are:

C1 C2

dVC1 dt dVC2 dt

L

© 2003 by CRC Press LLC

(

) ( )

(

)

= G VC2 − VC1 − f VC1 + s(t ) = G VC1 − VC2 + I L

dI L = − VC2 dt

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The Circuits and Filters Handbook, Second Edition

C2

dVC′2 dt L

(

)

= G VC1 − VC′2 + I′L

dI′L = − VC′2 dt

Because the CLEs of the (VC2, IL) subsystem are negative, VC′2 (t) → VC2 (t) and I L′ (t) → IL (t). The current r(t) at the receiver is given by r (t ) = C1 = C1

dVC1 dt dVC1 dt

(

) ( )

(

) ( )

− G VC′2 − VC1 − f VC1 − G VC2 − VC1 − f VC1

= s(t )

Miscellaneous Chaotic circuits may also be used for suppressing spurious tones in Σ∆ modulators, for modeling musical instruments, fractal pattern generation, image-processing, and pattern recognition [3]. A chaotic attractor contains an infinite number of unstable periodic trajectories of different periods. Various control schemes for stabilizing particular orbits in chaotic circuits have been successfully dem­ onstrated [14].

References [1] F. M. Callier and C. A. Desoer, Linear System Theory, New York: Springer-Verlag, 1991. [2] L. O. Chua, C. A. Desoer, and E. S. Kuh, Linear and Nonlinear Circuits, New York: McGraw-Hill, 1987. [3] L. O. Chua and M. Hasler, Eds., Special Issue on Chaos in Nonlinear Electronic Circuits, Part A: Tutorials and Reviews, IEEE Trans. Circuits Syst. I, Fundament. Theory Applicat., vol. 40, Oct. 1993; Part B: Bifurcation and Chaos, IEEE Trans. Circuits Syst. I, Fundament. Theory Applicat., vol. 40, Nov. 1993; Part C: Applicat., IEEE Trans. Circuits Syst. II, Analog and Digital Signal Process., vol. 40, Oct. 1993. [4] L. O. Chua, M. Itoh, L. Ko˘carev, and K. Eckert, “Chaos synchronization in Chua’s circuit,” J. Circuits Syst. Comput., vol. 3, no. 1, pp. 93–108, Mar. 1993. [5] L. O. Chua, C. W. Wu, A. Huang, and G.-Q. Zhong, “A universal circuit for studying and generating chaos — Part I: Routes to chaos,” IEEE Trans. Circuits Syst. I, Fundamental Theory Applicat., vol. 40, pp. 732–744, Oct. 1933. [6] J. A. Glazier and A. Libchaber, “Quasi-periodically and dynamical systems: An experimentalist’s view,” IEEE Trans. Circuits Syst., vol. 35, pp. 790–809, July 1988. [7] J. Guckenheimer and P. Holmes, Nonlinear Oscillations, Dynamical Systems, and Bifurcations of Vector Fields, New York: Springer-Verlag, 1983. [8] M. W. Hirsch, “The dynamical systems approach to differential equations,” Bull. Amer. Math. Soc., vol. 11, no. 1, pp. 1–64, July 1984. [9] M. Itoh, H. Murakami, K. S. Halle, and L. O. Chua, “Transmission of signals by chaos synchroni­ zation,” IEICE Tech. Rep., CAS93-39, NLP93-27, pp. 89–96, 1993. [10] M. P. Kennedy, “Three steps to chaos — Part I: Evolution,” IEEE Trans. Circuits and Systems I, Fundament. Theory Applicat., vol. 40, pp. 640–656, Oct. 1993; “Three steps to chaos — Part II: A Chua’s circuit primer,” IEEE Trans. Circuits Syst. I, Fundament. Theory Applicat., vol. 40, pp. 657–674, Oct. 1993. [11] M. P. Kennedy and L. O. Chua, “Van der Pol and chaos,” IEEE Trans. Circuits Syst., vol. CAS-33, pp. 974–980, Oct. 1986. © 2003 by CRC Press LLC

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Bifurcation and Chaos

1161

[12] M. P. Kennedy, K. R. Krieg, and L. O. Chua, “The Devil’s staircase: The electrical engineer’s fractal,” IEEE Trans. Circuits Syst., vol. 36, pp. 1133–1139, 1989. [13] W. Lauterborn and U. Parlitz, “Methods of chaos physics and their application to acoustics,” J. Acoust. Soc. Amer., vol. 84, no. 6, pp. 1975–1993, Dec. 1988. [14] M. Ogarzalek, “Taming chaos — Part I: Synchronization,” IEEE Trans. Circuits Syst. I, Fundament. Theory Applicat., vol. 40, pp. 693–699, Oct. 1993; “Taming chaos — Part II: Control,” IEEE Trans. Circuits Syst. I, Fundament. Theory Applicat., vol. 40, pp. 700–706, Oct. 1993. [15] T. S. Parker and L. O. Chua, Practical Numerical Algorithms for Chaotic Systems, New York: SpringerVerlag, 1989. [16] L. M. Pecora and T. Carroll, “Driving systems with chaotic signals,” Phys. Rev., vol. 44, no. 4, pp. 2374–2383, Aug. 15, 1991. [17] W. H. Press, B. P. Flannery, S. A. Teukolsky, and W. T. Vetterling, Numerical Recipes in C, Cambridge: Cambridge Univ., 1988. [18] J. M. T. Thompson and H. B. Stewart, Nonlinear Dynamics and Chaos, New York: Wiley, 1986. [19] M. Vidyasagar, Nonlinear Systems Analysis, Englewood Cliffs, NJ: Prentice-Hall, 1978. [20] C. W. Wu and N. F. Rul’kov, “Studying chaos via 1-D maps — A tutorial,” IEEE Trans. Circuits Syst. I, Fundament. Theory Applicat., vol. 40, pp. 707–721, Oct. 1993. [21] L. O. Chua, M. Komuro, and T. Matsumoto, “The Double Scroll Family, Parts I and II,” IEEE Trans. Circuits Syst., vol. 33, pp. 1073–1118, Nov. 1986.

Further Information Current Research in Chaotic Circuits. The August 1987 issue of the Proceedings of the IEEE is devoted to “Chaotic Systems.” The IEEE Transactions on Circuits and Systems, July 1988, focuses on “Chaos and Bifurcations of Circuits and Systems.” A three-part special issue of the IEEE Transactions on Circuits and Systems on “Chaos in Electronic Circuits” appeared in October (parts I and II) and November 1993 (part I). This Special Issue contains 42 papers on various aspects of bifurcations and chaos. Two Special Issues (March and June 1993) of the Journal of Circuits, Systems and Computers are devoted to “Chua’s Circuit: A Paradigm for Chaos.” These works, along with several additional papers, a pictorial guide to forty-five attractors in Chua’s oscillator, and the ABC simulator, have been compiled into a book of the same name — Chua’s Circuit: A Paradigm for Chaos, R. N. Madan, Ed. Singapore: World Scientific, Singapore 1993. Developments in the field of bifurcations and chaos, with particular emphasis on the applied sciences and engineering, are reported in International Journal of Bifurcation and Chaos, which is published quarterly by World Scientific, Singapore 9128. Research in chaos in electronic circuits appears regularly in the IEEE Transactions on Circuits and Systems. Simulation of Chaotic Circuits. A variety of general-purpose and custom software tools has been developed for studying bifurcations and chaos in nonlinear circuits systems. ABC (Adventures in Bifurcations and Chaos) is a graphical simulator of Chua’s oscillator, which runs on IBM-compatible PCs. ABC contains a database of component values for all known attractors in Chua’s oscillator, initial conditions, and parameter sets corresponding to homoclinic and heteroclinic trajecto­ ries, and bifurcation sequences for the period-doubling, intermittency, and quasiperiodic routes to chaos. The program and database are available from Dr. Michael Peter Kennedy Department of Electronic and Electrical Engineering University College Dublin Dublin 4, Ireland E-mail: [email protected] © 2003 by CRC Press LLC

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In “Learning about Chaotic Circuits with SPICE,” IEEE Transactions on Education, vol. 36, pp. 28–35, Jan. 1993, David Hamill describes how to simulate a variety of smooth chaotic circuits using the generalpurpose circuit simulator SPICE. A commercial variant of SPICE, called PSpice, is available from MicroSim Corporation 20 Fairbanks Irvine, CA 92718 Telephone: (714) 770-3022 The free student evaluation version of this program is sufficiently powerful for studying simple chaotic circuits. PSpice runs on both workstations and PCs. INSITE is a software toolkit that was developed at the University of California, Berkeley, for studying continuous-time and discrete-time dynamical systems. The suite of nine programs calculates and displays trajectories, power spectra, and state delay maps, draws vector fields of two-dimensional systems, recon­ structs attractors from time series, calculates Poincaré sections, dimension, and Lyapunov exponents. The package runs on DEC, HP, IBM, and Sun workstations under UNIX, and on IBM-compatible PCs under DOS. For additional information, contact INSITE Software P.O. Box 9662

Berkeley, CA 94709

Telephone: (510) 530-9259

© 2003 by CRC Press LLC

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VI

Distributed Circuits T. K. Ishii Marquette University 41 Transmission Lines T. K. Ishii Generic Relations • Two-Wire Lines • Coxial Lines • Waveguides • Microstrip Lines • Coplanar Waveguides

42 Multiconductor Transmission Lines Danïel De Zutter, Luc Martens Introduction: Frequency vs. Time Domain Analysis • Telegrapher’s Equations for Uniform Multiconductor Transmission Lines

43 Time and Frequency Domain Responses Luc Martens, Danïel De Zutter Time Domain Reflectometry • Frequency Domain Network Analysis

44 Distributed RC Networks Vladimir Székely Uniform Distributed RC Lines • Nonuniform Distributed RC Lines • Infinite-Length RC Lines • Inverse Problem for Distributed RC Circuits

45 Synthesis of Distributed Circuits T. K. Ishii Generic Relations • Synthesis of a Capacitance • Synthesis of an Inductance • Synthesis of a Resistance • Synthesis of Transformers • Synthesis Examples • Synthesis of Couplers

© 2003 by CRC Press LLC

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41 Transmission Lines

41.1 Generic Relations Equivalent Circuit • Transmission Line Equations • General Solutions and Propagation Constant • Characteristic Impedance • Wavelength • Phase Velocity • Voltage Reflection Coefficient at the Load • Voltage Reflection Coefficient at the Input • Input Impedance • Input Admittance

41.2 Two-Wire Lines Geometric Structure • Transmission Line Parameters • Wavelength and Phase Velocity

41.3 Coaxial Lines Geometric Structure • Transmission Line Parameters • Wavelength and Phase Velocity

41.4 Waveguides Rectangular Waveguides • Waveguide Parameters • Circular Waveguides

41.5 Microstrip Lines Geometric Structure • Transmission Line Parameters • Wavelength and Phase Velocity

T. K. Ishii

41.6 Coplanar Waveguide

Marquette University, Wisconsin

Geometric Structure • Transmission Line Parameters • Wavelength and Phase Velocity

41.1 Generic Relations Equivalent Circuit The equivalent circuit of a generic transmission line in monochromatic single frequency operation is · shown in Fig. 41.1 [1–3], where Z is a series impedance per unit length of the transmission line (Ω/m) · and Y is a shunt admittance per unit length of the transmission line (S/m). For a uniform, nonlinear · · · · transmission line, either Z or Y or both Z and Y are functions of the transmission line voltage and current, · · but both Z and Y are not functions of location on the transmission line. For a nonuniform, linear · · transmission line, both Z and Y are functions of location, but not functions of voltage and current on · · · · the transmission line. For a nonuniform and nonlinear transmission line, both Z and Y or Z or Y are functions of the voltage, the current, and the location on the transmission line.

Transmission Line Equations Ohm’s law of a transmission line, which is the amount of voltage drop on a transmission line per unit distance of voltage transmission is expressed as dV˙ /˙ ˙ = − IZ dz

© 2003 by CRC Press LLC

(V m)

(41.1)

0912 S1-S8 Frame55.book Page 1166 Monday, October 7, 2002 10:38 AM

. Z

. Z . Y

. Z

. Z

. Y

. Y

. Y

FIGURE 41.1 Equivalent circuit of a generic transmission line.

· · where V is the transmission line voltage (Volt), I is the transmission line current (Ampere), Z is the series impedance per unit length of the transmission line (Ω), and z is a one-dimensional coordinate placed in parallel to the transmission line (meter). The equation of current decrease per unit length is dI˙ ˙˙ = −YV dz

(A m)

(41.2)

· where Y is the shunt admittance per unit distance of the transmission line (S/m). Combining (41.1) and (41.2), the Telegrapher’s equation or Helmholtz’s wave equation for the trans­ mission line voltage is [1–3]. d 2V˙ ˙ ˙ ˙ − ZYV = 0 dz 2

( V m )2

(41.3)

The Telegrapher’s equation or Helmholtz’s wave equation for the transmission line current is [1–3] d 2 I˙ ˙ ˙ ˙ − ZY I = 0 dz 2

(A m ) 2

(41.4)

General Solutions and Propagation Constant The general solution of the Telegrapher’s equation for transmission line voltage is [1–3] ˙ ˙ V˙ = V˙ F ε −γ z + V˙ R ε γ z

(41.5) · · where VF is the amplitude of the voltage waves propagating in +z-direction, VR  is the amplitude of the voltage waves propagating –z-direction, and γ˙ is the propagation constant of the transmission line [1].

(m )

˙ ˙ = α + γβ ˙ γ˙ = ± ZY

–1

(41.6)

where the + sign is for forward propagation or propagation in +z-direction, and the – sign is for the backward propagation or propagation in –z-direction. α is the attenuation constant and it is the real part of propagation constant γ˙ : ˙ /˙ α = ℜγ˙ = ℜ ZY

(m ) –1

(41.7)

In (41.6), β is the phase constant and it is the imaginary part of the propagation constant γ· : ˙ ˙ β = ℑγ˙ = ℑ ZY

(m ) –1

(41.8)

Characteristic Impedance The characteristic impedance of the transmission line is [1–3] Z0 = © 2003 by CRC Press LLC

Z˙ Y˙

(Ω )

(41.9)

0912 S1-S8 Frame55.book Page 1167 Monday, October 7, 2002 10:38 AM

���

��� � � � ���

� � � ��� � ��

�� � � � ���

�

� � ���

· · FIGURE 41.2 Incident wave V i and reflected wave V r.

Wavelength The wavelength of the transmission line voltage wave and transmission line current wave is λ=

2π 2π = ˙ ˙ β ℑ ZY

(m )

(41.10)

Phase Velocity The phase velocity of voltage wave propagation and current wave propagation is υp = f λ =

ω β

( m s)

(41.11)

where f is the frequency of operation and the phase constant is β=

2π λ

(m ) −1

(41.12)

Voltage Reflection Coefficient at the Load · If a transmission line of characteristic impedance Z0 is terminated by a mismatched load impedance ZL, · as shown in Fig. 41.2, a voltage wave reflection occurs at the load impedance ZL. The voltage reflection coefficient is [1–3] ˜ V˙ r (l ) Z˙ − Z 0 Z˙ L −1 ρ˙ (l ) = ˙ i = ˙ L = ˜ V (l ) Z L + Z 0 Z˙ +1

L

(41.13)

˜ · where ρ(l) is the voltage reflection coefficient at z = l, and Z˙ = Z˙ L Z 0 is the normalized load impedance. · · Vi (l) is the incident voltage at the load at z = l. When Z0 is a complex quantity Z0, then Z˙ − Z 0∗ ρ˙ (l ) = ˙ L Z L + Z 0∗

(41.14)

· where Z0∗ is a conjugate of Z0.

Voltage Reflection Coefficient at the Input Input Fig. 41.2 V˙ i (l) is caused by V˙ i (0), which is the incident voltage at the input z = 0 of the transmission line. V˙ r (l) produces, V˙ r (0), which is the reflected voltage at the input z = 0. The voltage reflection coef­ ficient at the input occurs, then, by omitting transmission line loss [1–3] V˙ r (0) = ρ˙ (l )ε −2 jβl ρ˙ = ˙ i V (0) © 2003 by CRC Press LLC

(41.15)

0912 S1-S8 Frame55.book Page 1168 Monday, October 7, 2002 10:38 AM

Input Impedance At the load z = l, from (41.13), 1 + ρ˙ (l ) ˜ Z˙ L = 1 − ρ˙ (l )

(41.16)

1 + ρ˙ (l ) Z˙ L = Z 0 1 − ρ˙ (l )

(41.17)

1 + ρ˙ (0) ˜ Z˙ (0) = 1 − ρ˙ (0)

(41.18)

1 + ρ˙ (l )ε −2 jβl ˜ Z˙ (0) = 1 − ρ˙ (l )ε −2 jβl

(41.19)

˜ Z˙ + j tanβl ˜ Z˙ (0) = ˜ 1 + jZ˙ L tanβl

(41.20)

Z˙ + jZ tanβl ˜ Z˙ (0) = L ˙ 0 Z 0 + jZ L tanβl

(41.21)

γ˙ = α + j β

(41.22)

Z˙ + Z˙ 0∗ tanh γ˙ l Z˙ (0) = Z˙ 0∗ L∗ Z˙ 0 + Z˙ L tanh γ˙/l

(41.23)

or

At the input of the transmission line z = 0

Using (41.15),

Inserting (41.13), [1–3]

or

If the line is lossy and

then [1]

· · where Z0∗ is the complex conjugate of Z0.

Input Admittance The input admittance at z = 0 is Y˙ + Y˙ ∗ tanh γ˙ l Y˙ (0) = Y˙0∗ L∗ 0 Y˙0 + Y˙L tanh γ˙ l

(41.24)

where Y˙ (0) is the input admittance of the transmission line, Y˙0 is the characteristic admittance of the transmission line, which is 1 Y˙0 = Z˙

0

© 2003 by CRC Press LLC

(41.25)

0912 S1-S8 Frame55.book Page 1169 Monday, October 7, 2002 10:38 AM

· · and Y˙0∗ is the conjugate of Y0 · YL is the load admittance; i.e., 1 Y˙L = ˙ ZL

(41.26)

γ˙ = jβ

(41.27)

Z˙ + jZ 0 tanβl Z˙ (0) = L Z 0 + jZ L tanβl

(41.28)

When the line is lossless,

then [1–3]

41.2 Two-Wire Lines Geometric Structure A structural diagram of the cross-sectional view of a commercial two-wire line is shown in Fig. 41.3. As observed in this figure, two parallel conductors, in most cases made of hard-drawn copper, are positioned by a plastic dielectric cover.

Transmission Line Parameters In a two-wire line Z˙ = R + jX = R + jωL

(Ω m )

(41.29)

· where Z is the impedance per unit length of the two-wire line (Ω/m), R is the resistance per unit length (Ω/m), X is the reactance per unit length (Ω/m), ω = 2π f is the operating angular frequency (s –1), and L is the inductance per unit length (H/m). For a two-wire line made of hard-drawn copper [4] R = 8.42

f a

(µΩ m)

(41.30)

where f is the operating frequency and a is the radius of the conductor [4]: L = 0.4 ln

b a

(µH m) b

(41.31)

conductor

a a

dielectric conductor

FIGURE 41.3 Cross-sectional view of a two-wire line. © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 1170 Monday, October 7, 2002 10:38 AM

where b is the wire separation or the center-to-center distance of the two-wire line as illustrated in Fig. 41.3.

(S m )

Y˙ = G + jB = G + jω C

(41.32)

·

where Y is a shunt admittance per unit length of the two-wire line (S/m), G is a shunt conductance per unit length of the two-wire line (S/m), B is a shunt susceptance per unit length (S/m), and C is a shunt capacitance per unit length (F/m) G=

3.14σ d  b cosh−1    2a 

(pS m)

(41.33)

where σd is the insulation conductivity of the plastic dielectric surrounding the two parallel conductors, and C=

27.8ε r  b cosh −1    2a 

(pF m)

(41.34)

where ε r is the relative permittivity of the plastic insulating material [5]. If R and G are negligibly small, the characteristic impedance is [6] Z 0 = 277 log10

b a

(Ω )

(41.35)

The attenuation constant of a generic two-wire line is, including both R and G [1],

α=

R GZ 0 + 2Z 0 2

(m ) –1

(41.36)

and the phase constants is [1]   (ωLB − RG) + β =   

(RG − ωLB)2 + (ωLG + BR)2 

1 2

(m ) –1

  

2

(41.37)

Wavelength and Phase Velocity The wavelength on a lossless two-wire line (R = 0, G = 0) is λ0 =

ω = β0

1 LC

(m )

(41.38)

where β0 is the phase constant of the lossless two-wire line

(m )

β0 = ω LC

–1

(41.39)

The wavelength on a lossy two-wire line (R ≠ 0, G ≠ 0) is  2π  λ= = β  (ωLB − RG) +  © 2003 by CRC Press LLC

1

2 8π   2 2 (RG − ωLB) + (ωLG + BR)  2

(m )

(41.40)

0912 S1-S8 Frame55.book Page 1171 Monday, October 7, 2002 10:38 AM

The phase velocity of transverse electromagnetic (TEM) waves on a lossless two-wire line is v0 = f λ 0 =

ω = β0

1 LC

( m s)

(41.41)

The phase velocity of TEM waves on a lossy two-wire line is ω  v = f λ = =  β  (ωLB − RG ) +

1

 2  (RG − ωLB)2 + (ωLG + BR)2  2ω 2

( m s)

(41.42)

41.3 Coaxial Lines Geometric Structure A generic configuration of a coaxial line is shown in Fig. 41.4. The center and outer conductors are coaxially situated and separated by a coaxial insulator. Generally, coaxial lines are operated in the TEM mode, in which both the electric and magnetic fields are perpendicular to the direction of propagation. The propagating electric fields are in the radial direction and propagating magnetic fields are circumfer­ ential to the cylindrical surfaces. In Fig. 41.4, a is the radius of the center conductor, b is the inner radius of the outer conductor, and c is the outer radius of the outer conductor.

Transmission Line Parameters The series resistance per unit length of the line for copper is [7],  1 1 R = 4.16 f  +   a b

(µΩ m)

(41.43)

The series inductance per unit length is L = 0.2 ln

b a

(µH m)

c b

center conductor

outer conductor

insulator

FIGURE 41.4 Generic configuration of a coaxial line. © 2003 by CRC Press LLC

a

(41.44)

0912 S1-S8 Frame55.book Page 1172 Monday, October 7, 2002 10:38 AM

The shunt conductance per unit length is 6.28σ i ln(b a)

G=

(S m )

(41.45)

where σi is the conductivity of the insulator between the conductors. The shunt capacitance per unit length is C=

55.5ε r ln(b a)

(pF m)

(41.46)]

where ε r is the relative permittivity of the insulator. When the loss of the line is small, the characteristic impedance of the coaxial line is Z0 =

138 b log10 a εr

(Ω )

(41.47)

when the line is lossy [1] Z˙ R + jωL = = R0 + jX 0 Y˙ G + jωC

Z˙ 0 =

(41.48) 1

 2 RG + ω LC +  R0 =

(

X0 =

2 RG + ω LC + (ωLG – ωRC )   2 2 2 G +ω C 2

)

2

2

1 ωLG − ωCR ⋅ 2R0 G 2 + ω 2C 2

(41.49)

(41.50)

The propagation constant of the coaxial line is γ˙ = α + jβ

(41.51)

The attenuation constant is [1] α=

ωLG + ωCR 2β

(41.52)

where the phase constant is 1

 2  ω LC − RG + β=  

(

) (RG − ω LC ) + (ωLG + ωRC ) 2

2

2

2

2    

(41.53)

Wavelength and Phase Velocity The phase velocity on the coaxial line is υp =

ω β

(41.54)

λ1 =

2π β

(41.55)

The wavelength on the line is

© 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 1173 Monday, October 7, 2002 10:38 AM

41.4 Waveguides Rectangular Waveguides Geometric Structure A rectangular waveguide is a hollow conducting pipe of rectangular cross section as depicted in Fig. 41.5. Electromagnetic microwaves are launched inside the waveguide through a coupling antenna at the transmission site. The launched waves are received at the receiving end of the waveguide by a coupling antenna. In this case, a rectangular coordinate system is set up on the rectangular waveguide (Fig. 41.5). The z-axis is parallel to the axis of the waveguide and is set coinciding with the lower left corner of the waveguide. The wider dimension of the cross section of the waveguide a and the narrower dimension of the cross section of the waveguide is b, as shown in the figure. Modes of Operation The waveguide can be operated in either H- or E-modes, depending on the excitation configuration. An H-mode is a propagation mode in which the magnetic field, H, has a z-component, Hz, as referred to in Fig. 41.5. In this mode, the electric field, E, is perpendicular to the direction of propagation, which is the +z-direction. Therefore, an H-mode is also called a transverse electric (TE) mode. An E-mode is a propagation mode in which the electric field, E, has a z-component, Ez, as referred to in Fig. 41.5. In this mode, the magnetic field, H, is perpendicular to the direction of propagation, which is the +z-direction. Therefore, an E-mode is also called a transverse magnetic (TM) mode. Solving Maxwell’s equations for H-modes [1], mπ x n π y − γ˙ z + j ω t H˙ z = H˙ 0 cos cos ε a b

(41.56)

· · where H0 is the amplitude of Hz . Waveguide loss was neglected. Constants m and n are integral numbers 0, 1, 2, 3, … and are called the mode number, and γ· is the propagation constant. Both m and n cannot equal 0 simultaneously. Solving Maxwell’s equations for E-modes [1],

Y

b o

X

a

conducting wall

Z

FIGURE 41.5 A rectangular waveguide and rectangular coordinate system. © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 1174 Monday, October 7, 2002 10:38 AM

mπx nπy − γ˙z + jωt ε E˙ z = E˙ 0 sin sin a b

(41.57)

· · where E0 is the amplitude of Ez. Neither m nor n can equal 0. The waveguide loss was neglected. An H-mode is expressed as the Hmn-mode or TEmn-mode. An E-mode is expressed as the Emn-mode or TMmn-mode.

Waveguide Parameters Propagation constant γ˙ of a rectangular waveguide made of a good conductor [1]: λ γ˙ = jβ0 1 −    λc 

2

(m ) −1

(41.58)

where β0 is the phase constant of free space, which is β0 =

(m )

2π λ

−1

(41.59)

Here, λ is the wavelength in free space, and λc is the cutoff wavelength of the waveguide. Electromagnetic waves with λ > λc cannot propagate inside the waveguide. It is given for both Emn-mode and Hmn-mode operation by [1]: 2

λc =

2

 m  n   +   a   b

(m )

2

(41.60)

This means that if the waveguide is made of a good conductor, the attenuation constant

(m ) −1

α≈0

(41.61)

and the phase constant is λ β g = β0 1 −    λc 

2

(41.62)

The wavelength in the waveguide, i.e., waveguide wavelength λg , is longer than the free-space wavelength λ: λg =

λ λ 1−    λc 

(41.63)

2

Then, the speed of propagation vp is > c = f λ. vp = f λg =

© 2003 by CRC Press LLC

fλ  λ 1−    λc 

2

=

c  λ 1−    λc 

2

(41.64)

0912 S1-S8 Frame55.book Page 1175 Tuesday, October 8, 2002 12:50 PM

For an Hmn-mode, the wave impedance is

−E˙ E˙ ηH = ˙ y = ˙ x = Hx Hy

µ0 ε0 λ 1−    λc 

(Ω )

2

(41.65)

For an Emn-mode the wave impedance is 2 −E˙ λ E˙ ηE = ˙ y = ˙ x = 1 −   Hx Hy  λc 

µ0 ε0

(Ω )

(41.66)

Circular Waveguides Geometric Structure A circular waveguide is a hollow conducting pipe of circular cross section, as depicted in Fig. 41.6. Electromagnetic microwaves are launched inside the waveguide through a coupling antenna at the transmission site. The launched waves are received at the receiving end of the waveguide by a coupling antenna. In this case, a circular coordinate system (r, φ, z) is set up in the circular waveguide, as depicted in Fig. 41.6. The z-axis is coincident with the axis of the cylindrical waveguide. The inside radius of the circular waveguide is a. Modes of Operation The circular waveguide can be operated in either H- or E-modes, depending on the excitation configu­ ration. An H-mode is a propagation mode in which the magnetic field, H, has a z-component, Hz, as referred to in Fig. 41.6. In this mode the electric field, E, is perpendicular to the direction of propagation, which is the +z-direction. Therefore, an H-mode is also called a TE mode. In the mode Ez = 0. An E-mode is a propagation mode in which the electric field, E, has a z-component, Ez , as referred to in Fig. 41. 6. In this mode the magnetic field, H, is perpendicular to the direction of propagation, which is the +z-direction. Therefore, an E-mode is also called a TM mode. Solving Maxwell’s equations [1], ˙ H˙ z = H˙ 0 J n (k′cmr ) cosnφε − γz + jωt

(41.67)

Y

(r,φ,z) a X o

z

Z

r

© 2003 by CRC Press LLC

φ

FIGURE 41.6 A circular waveguide and cylindrical coordinate system.

0912 S1-S8 Frame55.book Page 1176 Monday, October 7, 2002 10:38 AM

· · Here, H0 is the amplitude of Hz, n and m are integral numbers 0, 1, 2, 3, … and are called the mode ′ r) is the Bessel function of nth order, with the argument that kcm ′ r, kcm ′ is the mth root of number, Jn (kcm J′n (kcm a) = 0, which is k′cm =

u′nm a

(41.68)

where u′nm is the mth root of the derivative of the Bessel function of order n, i.e., J n′(x) = 0, where x is a generic real argument. The propagation constant is γ˙ . Solving Maxwell’s equations for E-modes, ˙ E˙ z = E˙ 0 J n (kcmr ) cosnφε − γz + jωt

(41.69)

kcm is an mth root of Jn (kc a) = 0, which is kcm =

unm a

(41.70)

where unm is the mth root of the Bessel function of order n, i.e., Jn (x) = 0, where x is a generic real argument. An H-mode in a circular waveguide is expressed as the Hnm-mode or the TMnm-mode. An E-mode is expressed as the Enm-mode or the TMnm-mode. Waveguide Parameters The propagation constant γ˙ of a circular waveguide made of a good conductor is [1] λ γ˙ = jβ0 1 −    λc 

(m ) −1

(41.71)

where β0 is the phase constant of free space, which is β0 =

(m )

2π λ

−1

(41.72)

Here, λ is the wavelength in free space, and λc is the cutoff wavelength of the waveguide. Electromagnetic waves with λ > λc cannot propagate inside the waveguide. It is given for an Hnm-mode [1] λCH =

2πa u′nm

(m )

(41.73)

λCE =

2πa unm

(m )

(41.74)

For Enm-mode operation,

This means that if the waveguide is made of a good conductor, the attenuation constant is α≈0

(m ) −1

(41.75)

and the phase constant is λ β g = β0 1 −    λc  © 2003 by CRC Press LLC

2

(m ) −1

(41.76)

0912 S1-S8 Frame55.book Page 1177 Monday, October 7, 2002 10:38 AM

The waveguide wavelength is λ

λg =

(m ) −1

λ 1−    λc 

2

(41.77)

The speed of propagation (phase velocity) is vp = f λg =

c  λ 1−    λc 

( m s)

2

(41.78)

For an Hnm-mode, the wave impedence is E˙ −E˙ φ jωµ 0 ηH = ˙ r = ˙ = Hφ Hr γ˙ =

ωµ 0 λ β0 1 −    λc 

(Ω )

2

(41.79)

For an Enm-mode, the wave impedance is −E˙ E˙ γ˙ ηE = ˙ r = ˙ φ = Hφ Hr jωε 0

=

λ β0 1 −    λc  ωε 0

(41.80)

2

(Ω )

41.5 Microstrip Lines Geometric Structure Figure 41.7 presents a general geometric structure of a microstrip line. A conducting strip of width, w, and thickness, t, is laid on an insulating substrate of thickness, H, and permittivity, ε = ε0 εr . The dielectric substrate has a groundplate underneath, as presented in Fig. 41.7.

Transmission Line Parameters The characteristic impedance, Z0, of a microstrip line, as shown in Fig. 41.7, is given by [8–10]

Z0 =

  4H  ln 1+   ε r +1   w ′ 

42.4

2   14 + 8 ε r   4H   14 + 8ε r   4H  1 + 1 ε r 2   π  (41.81) +  +        11   w ′  2  11   W ′  

where w′ is an effective width of the microstrip, which is given by

© 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 1178 Monday, October 7, 2002 10:38 AM

conducting strip

insulating substrate

∈ = ∈o∈r

t W H

ground plate

FIGURE 41.7 Geometric structure of a microstrip line.

w′ = w +

1 + 1 εr t ⋅ ln 2 π

10.87  1π   t    +    H  w t + 1.10  2

2

(41.82)

The attenuation constant of a microstrip line is α=

p + p′ Z 01 2π 2 Z0 λ0

(Np m)

(41.83)

where   1  8H  Z 01 ≡ 30 ln 1 +    2  w′ 

2    8H +  8H  + π 2    w′   w′   

(41.84)

Z 01 Z 0δ

(41.85)

and p ≡1− where   1  8( H + δ)  Z 0δ ≡ 30 ln 1 +    2  w ′ 

 8H + δ ) +  8H + δ  2 + π 2       w′   w′   

(41.86)

1 π f µσ

(41.87)

and δ=

is the skin depth of the conducting strip of conductivity σ p′ ≡

© 2003 by CRC Press LLC

Pk 1/ q −1 1− εr

(41.88)

0912 S1-S8 Frame55.book Page 1179 Monday, October 7, 2002 10:38 AM

where ε r = ε r′ − jε r′′

(41.89)

 ε′′ PK = sin tan −1 r  ε r′  

(41.90)

2  1  Z 01  −1 q=   ε r −1  Z 0    

(41.91)

and

and

Wavelength and Phase Velocity The transmission line wavelength is Z0 λ Z 01 0

(41.92)

2π Z 01 λ0 Z0

(41.93)

λ1 = The phase constant of the microstrip line is then β=

The phase velocity of electromagnetic waves on the microstrip line is v p = 3 × 108

Z0 Z 01

(41.94)

41.6 Coplanar Waveguide Geometric Structure A cross-sectional view of a coplanar waveguide (CPW) is given in Fig. 41.8. The waveguide consists of a narrow, central conducting strip of width s(m) and very wide conducting plates on both sides of the central conducting strip, with gap widths w. These conductors are developed on a surface of dielectric substrate of thickness d, as presented in the figure. The electromagnetic waves propagate in the gap between the outer conducting plates and the center conducting strip.

center metal plate outer metal plate

w

outer metal plate

w s

substrate

FIGURE 41.8 Cross-sectional view of a coplanar waveguide. © 2003 by CRC Press LLC

d

0912 S1-S8 Frame55.book Page 1180 Monday, October 7, 2002 10:38 AM

Transmission Line Parameters The attenuation constant of a coplanar waveguide is given by [11]

5

 π α =   ⋅2⋅  2

1–

ε eff ( f ) εr

⋅

ε eff ( f )

(s + 2w )2 εr3/2 Np m ( ) c 3 K ′(k )K (k )

(41.95)

εr where the effective dielectric constant is given by ε eff ( f ) = ε q +

εr − εq  f  1 + a    f TE 

−b

(41.96)

and εq =

ε r +1 2

(41.97)

εr is the relative permittivity of the substrate material, f TE =

c 4d ε r −1

(41.98)

is the TE mode cutoff frequency, k ≡ s (s + 2w )

(41.99)

K (k) is the complete ellipitic integral of the first kind of the argument k, and c is the speed of light in vacuum, which is 3 × 108 m/s. The parameter a is [11] s   a ≈ log −1 u log + v  w  

(41.100)

u ≈ 0.54 − 0.64q + 0.015q 2

(41.101)

v ≈ 0.43 − 0.86q + 0.54q 2

(41.102)

q ≈ log

s d

(41.103)

The parameter b is an experimentally determined constant b ≈ 1.8 K ′(k ) = K

© 2003 by CRC Press LLC

(41.104)

( 1−k ) 2

(41.105)

0912 S1-S8 Frame55.book Page 1181 Monday, October 7, 2002 10:38 AM

The phase constant of the coplanar waveguide is β( f ) = 2π

f c

ε eff ( f )

(rad m)

(41.106)

The characteristic impedence of the coplanar waveguide is [11] Z0 =

K ′(k ) ε eff ( f ) 4K (k )

120π

(Ω )

(41.107)

Wavelength and Phase Velocity The wavelength of electromagnetic waves propagating on a coplanar waveguide is obtained from (41.106): λl =

2π 1 c = ⋅ = β( f ) f ε eff ( f )

λ

ε eff ( f )

(m )

(41.108)

The phase velocity of the waves on the coplanar waveguide is, then, v p = f λ1 =

c ε eff ( f )

(m s)

(41.109)

References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]

T. K. Ishii, Microwave Engineering, San Diego, CA: Harcount, Brace, Jovanovich, 1989. J. R. Wait, Electromagnetic Wave Theory, New York: Harper & Row, 1985. V. F. Fusco, Microwave Circuits, Englewood Cliffs, NJ: Prentice Hall, 1987. L. A. Ware and H. R. Reed, Communications Circuits. New York: John Wiley & Sons, 1949. E. A. Guillemin, Communications Networks, New York: John Wiley & Sons, 1935. F. E. Terman, Radio Engineering, New York: McGraw-Hill, 1941. H. J. Reich, P. F. Ordung, H. L. Krauss, and J. G. Skalnik, Microwave Theory and Techniques, Princeton, NJ: D. Van Nostrand, 1953. H. A. Wheeler, “Transmission-line properties of parallel strips separated by a dielectric sheet,” IEEE Trans. MTT, vol. MTT-13, pp. 172–185, Mar. 1965. H. A. Wheeler, “Transmission-line properties of parallel strips by a conformal-mapping approxi­ mation,” IEEE Trans. MTT, vol. MTT-12, pp. 280–289, May 1964. H. A. Wheeler, “Transmission-line properties of a strip on a dielectric sheet on a plane,” IEEE Trans. MTT, vol. MTT-25, pp. 631–647, Aug. 1977. M. Y. Frankel, S. Gupta, J. A. Valdmanis, and G. A. Mourou, “Terahertz attenuation and dispersion characteristics of coplanar transmission lines.” IEEE Trans. MTT, vol. 39, no. 6, pp. 910–916, June 1991.

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0912 ch42(1183) frame55 Page 1183 Wednesday, October 30, 2002 1:02 PM

42 Multiconductor Transmission Lines Daniël De Zutter Gent University, Belgium

Luc Martens Gent University, Belgium

42.1 Introduction: Frequency vs. Time Domain Analysis 42.2 Telegrapher’s Equations for Uniform Multiconductor Transmission Lines Generalities • Low-Frequency or Quasi-Transverse Electromagnetic Description • Analytical Expressions for Some Simple Multiconductor Transmission Line Configurations

42.1 Introduction: Frequency vs. Time Domain Analysis Multiconductor transmission lines (MTL), or multiconductor buses as they are also often called, are found in almost every electrical packaging technology and on every technology level from digital chips, over MMICs (monolithic microwave integrated circuits) to MCMs (multichip modules), boards, and backplanes. Multiconductor transmission lines are electrical conducting structures with a constant crosssection (the x, y-plane) which propagates signals in the direction perpendicular to that cross-section (the z-axis) (see also Fig. 42.1). Being restricted to a constant cross-section we are in fact dealing with the socalled uniform MTL. The more general case using a nonuniform cross-section is much more difficult to handle and constitutes a fully three-dimensional problem. It is not the purpose of this chapter to give a detailed account of the physical properties and the use of the different types of MTL. The literature on this subject is abundant and any particular reference is bound to be both subjective and totally incomplete. Hence, we put forward only [1], [2], and [3] as references here, as they contain a wealth of information and additional references. In the frequency domain, i.e., for harmonic signals, solution of Maxwell’s sourceless equations yields a number of (evanescent and propagating) modes characterized by modal propagation factors exp (±j βz) and by a modal field distribution, which depends only upon the (x, y)-coordinates of the cross-section. In the presence of losses and for evanescent modes β can take complex values, and jβ is then replaced by γ = α + jβ (see Eq. 42.30). In the propagation direction, the modal field amplitudes essentially behave as voltage and current along a transmission line. This immediately suggests that MTL should be repre­ sented on the circuit level by a set of coupled circuit transmission lines. The relationship between the typical circuit quantities, such as voltages, currents, coupling impedances, and signal velocities, on the one hand, and the original field quantities (modal fields and modal propagation factors) is not straight­ forward [4]. In general, the circuit quantities will be frequency dependent. The frequency domain circuit model parameters can be used as the starting point for time domain analysis of networks, including multiconductor lines. This is, again, a vast research topic with important technical applications. Section 42.2 describes the circuit modeling in the frequency domain of uniform MTL based on the Telegrapher’s equations. The meaning of the voltages and currents in these equations is explained both at lower frequencies in which the quasi-transverse electromagnetic (TEM) approach is valid as well as

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1

air 2

3 dielectric

1

2

layered substrate

ground plane shield (a)

(b)

FIGURE 42.1 Two examples of cross sections of multiconductor lines.

in the so-called full-wave regime valid for any frequency. The notions TEM, quasi-TEM, and full-wave are elucidated. We introduce the capacitance, inductance, resistance, and conductance matrices together with the characteristic impedance matrix of the coupled transmission line model. Finally, for some simple MTL configurations analytical formulas are presented expressing the previous quantities and the prop­ agation factors as a function of the geometric and electrical parameters of these configurations. It would be a formidable task to give a comprehensive overview of all the methods that are actually used for the time domain analysis of MTL. In the remaining part of this paragraph a very short overview (both for uniform and nonuniform structures) is presented along with some references. In the case of linear loads and drivers, frequency domain methods in combination with (fast) Fourier transform techniques are certainly most effective [5–7]. In the presence of nonlinear loads and drivers other approaches must be used. Simulations based on harmonic balance techniques [8, 9] are, again, mainly frequency domain methods. All signals are approximated by a finite sum of harmonics and the nonlinear loads and drivers are taken into account by converting their time domain behavior to the frequency domain. Kirchhoff laws are then imposed for each harmonic in an iterative way. Harmonic balance techniques are not very well suited for transient analysis or in the presence of strong nonlinearities, but are excellent for mixers, amplifiers, filters, etc. Many recent efforts were directed toward the development of time domain simulation methods (for both uniform and nonuniform interconnection structures) based on advanced convolution-type approaches. It is, of course, impossible to picture all the ramifica­ tions in this research field. We refer the reader to a recent special issue of IEEE Circuits and Systems Transactions [10], to the “Simulation Techniques for Passive Devices and Structures” section of a special issue of IEEE Microwave Theory and Techniques Transactions [11], and to a 1994 special issue of the Analog Integrated Circuits and Signal Processing Journal [12] and to the wealth of references therein. Both frequency and time domain experimental characterization techniques for uniform and nonuni­ form multiconductor structures can be found in Chapter 43.

42.2 Telegrapher’s Equations for Uniform Multiconductor Transmission Lines Generalities Figures 42.1(a) and (b) show the cross-sections of two general coupled lossy MTLs consisting of N + 1 conductors. These conductors either can be perfectly conducting or exhibit finite conductivity. Their cross-section remains constant along the propagation or longitudinal direction z. The (N +1)th conductor is taken as reference conductor. In many practical cases, this will be the ground plane at the top or bottom © 2003 by CRC Press LLC

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[(Fig. 42.1(a)] of the layered dielectric in which the conductors are embedded or is the shielding sur­ rounding the other conductors [(Fig. 42.1(b)]. We restrict the analysis to the frequency domain, i.e., all field components and all voltages and currents have a common time dependence, exp(jωt), which is suppressed in the sequel. The generalized Telegrapher’s equations governing the circuit representation of the MTL of Fig. 42.1 in terms of a set of C-coupled circuit transmission lines is given by [4]: dV + ZI = 0 dz

(42.1)

dI + YV = 0 dz V and I are column vectors, the C elements of which are the voltages and currents of the circuit model; Z and Y are the C × C impedance and admittance matrices. Equation (42.1) is a good circuit description of the wave phenomena along a MTL if only the fundamental modes of the corresponding field problem are of importance. In that case C = N (C = 3 in Fig. 42.1(a) and C = 2 in Fig. 42.1(b)) if a ground plane is present, and C = N –1 in the absence of a ground plane. For the relationship between the actual electromagnetic field description in terms of modes and the circuit model (42.1), we refer the reader to [4] and [13]. The general solution to (42.1) is given by

( )

V( z ) = 2 ITm

−1

( )

e − j?z K + + 2 ITm

−1

e j?z K − (42.2)

I( z ) = Ime − j?z K + − Ime j?z K −

K+ and K– are column vectors with C elements. β is a diagonal C × C matrix with the propagation factors β f ( f = 1, 2,K , C) of the C fundamental eigenmodes as diagonal elements. This matrix reduces to a single propagation factor for a single transmission line (see Eq. 41.6). For the calculation of the fields and of the propagation constants many different methods can be found in the literature [14]. Solution (42.2) of the differential equations (42.1) is the extension of the corresponding equations (41.5) for a single transmission line to the coupled line case. It also consists of waves respectively traveling in positive and negative z-directions. The Im is a C × C matrix, the columns of which are the current eigenvectors of the circuit model. The following relationships hold:

( ) β(I )

Z = jωL + R = 2j ITm

−1

−1

m

j Y = jωC + G = ImβITm 2

(42.3)

L, R, C and G are the C × C (frequency dependent) inductance, resistance, capacitance, and conductance matrices. The C × C characteristic impedance matrix of the transmission line models is given by Z char = 2(ITm )−1(Im )−1 . The matrix Zchar replaces the simple characteristic impedance number of (41.9). In general the mapping of the wave phenomenon onto the circuit model [(42.1) to (42.3)] depends on the choice of Im. We refer the reader to the detailed discussions in [4]. For MTLs the most adopted definition for the elements of Im is [15]

I m, jf =

∫H cj

tr, f

⋅ dl

j , f = 1, 2, …, C

(42.4)

where cj is the circumference of conductor j and where Htr, f is the transversal component of the magnetic field of eigenmode f. This means than Im, jf is the total current through conductor j due to eigenmode f. This definition is used in the power-current impedance definition for microstrip and stripline problems © 2003 by CRC Press LLC

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[9]. For slotline circuits, a formulation that parallels the one given above must be used, but in this case it makes much more sense to introduce the voltage eigenvectors and to define them as line integrals of the electric field (see Appendix B of [16]). As Z and Y in (42.3) are frequency dependent, the time domain equivalent of (42.1) involves convo­ lution integrals between Z and I on the one hand and Y and V on the other hand. The propagation factors βf are also frequency dependent, hence the signal propagation will show dispersion, i.e., the signal waveform becomes distorted while propagating.

Low-Frequency or Quasi-Transverse Electromagnetic Description In the previous section, the reader was given a very general picture of the MTL problem, valid for any frequency. This analysis is the so-called full-wave analysis. The present section is restricted to the lowfrequency or quasi-static regime. Here, the cross-section of the MTL is small with respect to the relevant wavelengths, the longitudinal field components can be neglected and the transversal field components can be found from the solution of an electrostatic or magnetostatic problem in the cross-section of the MTL. A detailed discussion of the theoretical background can be found in [17]. In the quasi-TEM limit and in the absence of losses R and G are zero and L and C become frequency independent and take their classical meaning. Both skin-effect losses and small dielectric losses can be accounted for by a perturbation approach [18]. In that case a frequency dependent R and G must be reintroduced. If R and G are zero and L and C are frequency independent, the following Telegrapher’s equations hold: ∂v ∂i = −L ⋅ ∂z ∂t

(42.5)

∂i ∂v = −C ⋅ ∂z ∂t

Equation (42.5) is the time domain counterpart of (42.1). We have replaced the capital letters for voltages and currents with lower case letters to distinguish between time and frequency domain. L and C are related to the total charge Qi per unit length carried by each conductor and to the total magnetic flux Fi between each conductor and the reference conductor: Q = C⋅V

(42.6)

F = L⋅I

where Q and F are C × 1 column vectors with elements Qi and Fi , respectively. For a piecewise homo­ geneous medium, one can prove that the inductance matrix L can be derived from an equivalent socalled vacuum capacitance matrix Cv with L = C −v 1 and where Cv is calculated in the same way as C, but with the piecewise constant ε everywhere replaced by the corresponding value of 1/µ. For nonmagnetic materials, this operation corresponds with taking away all dielectrics and working with vacuum, thus explaining the name of the matrix Cv. Other properties of C and L are: C and L are symmetric, i.e., Cij = Cji and Lij = Lji C is real, Cii > 0 and Cij < 0 (i ≠ j) l is real, Lii > 0 and Lij > 0 The propagation factors βf which form the elements of β in (42.2) are now given by the eigenvalues of (LC)1/2 or equivalently of (CL)1/2. The current eigenvectors which form the columns of Im are now solutions of the following eigenproblem (where ω is the circular frequency):

( )

ω 2 (CL)I = β f I

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2

(42.7)

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The corresponding eigenvoltages are solutions of:

( )

ω 2 (LC)V = β f V 2

(42.8)

Hence, corresponding voltage and current eigenmodes propagate with the same propagation factors and as L, C, V, and I are frequency independent, βf is proportional with ω and can be rewritten as β f = ωβ′f , proving that the propagation is nondispersive with velocity v f = 1 / β′f . Remember that the subindex f takes the values 1, 2,…, C, i.e., for a three-conductor problem above a ground plane [N = C = 3, see Fig. 42.1(a)], three distinct propagation factors and corresponding eigenmode profiles exist for currents and voltages. Note, however, that for the same βf the eigenvector for the currents differs from the eigenvector of the voltages. We conclude this section by remarking that, for MTL embedded in a homogeneous medium (such as the simple stripline or the coaxial cable with homogeneous filling), (LC) = ε µ1, where 1 is the unity matrix. Thus, the eigenmodes are purely TEM, i.e., electric and magnetic fields have only transversal components and the longitudinal ones are exactly zero. All propagation factors βf take the same value [c / (ε r µ r )1/ 2 ], where c is the velocity of light in vacuum. Note, however, that even for identical βf different eigenmodes will be found. Numerical calculation of L and C can be performed by many different numerical methods (see the reference section of [18]), and for sufficiently simple configurations analytical formulas are available. For a line with one conductor and a ground plane (N = C = 1) the characteristic impedance Z 0 = (L / C)1/ 2 and the signal velocity vp is v p = (LC)−1/ 2 .

Analytical Expressions for Some Simple Multiconductor Transmission Line Configurations Symmetric Strip Line Sections 41.3 through 41.6 presented a number of MTL consisting of a single conductor and a ground plane (N = C = 1). Here, we add another important practical example, the symmetric stripline config­ uration of Fig. 42.2. We restrict ourselves to the lossless case. A perfectly conducting strip of width w and thickness t is symmetrically placed between two perfectly conducting ground planes with spacing b. The insulating substrate has a permittivity ε = ε0 εr , and is nonmagnetic. This case has a single fundamental mode. The characteristic impedance Z0 is given by [19]:   4 b−t Z 0 ε r = 30ln 1 +  π W ′

2    8 b − t +  8 b − t  + 6.27    π W′  π W′   

(42.9)

with W′ W ∆W = + b−t b−t b−t

b

t w

FIGURE 42.2 Strip line configuration. © 2003 by CRC Press LLC

(42.10)

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b

t w

s

w

FIGURE 42.3 Coupled, symmetric strip line configuration.

where m  2  ∆W x  1  x   0.0796 x      = 1 − ln +    b − t π(1 − x )  2  2 − x   W b +1.1x       −1

 2 x  m = 21 +  , x =t b  3 1− x  For W′/(b – t) < 10 (42.9) is 0.5% accurate. The signal velocity vp is given by c/(εr)1/2, where c is the velocity of light in vacuum. The corresponding L and C are given by L = Z0 /vp and C = 1/(Z0vp ). Coupled Strip Lines The configuration is depicted in Fig. 42.3. It consists of the symmetric combination of the structure of Fig. 42.2. There are now two fundamental TEM modes (N = C = 2). The even mode (index e) corresponds to the situation in which both central conductors are placed at the same voltage (speaking in lowfrequency terms, of course). The odd mode (index o) corresponds to the situation where the central conductors are placed at opposite voltages. The impedances of the modes (respectively, Z0, e and Z0, o ) are given by: Z 0e ,o =

30π(b − t ) bC   ε r  W + f Ae ,o  2π  

(42.11)

with Ae = 1 +

ln(1 + tanh θ) ln 2

Ao = 1 +

ln(1+ coth θ) ln 2

θ=

πS 2b

 2b − t  t  t (2b − t )   C f (t b) = 2 ln  − ln  b − t  b  (b − t )2    The signal velocity is the same for both modes (c/(ε r)1/2), and the L and C of both modes can be found by replacing Z0 in the “Symmetric Strip Line” section by Z0, e and Z0, o , respectively.

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t h

w

s

w

FIGURE 42.4 Coupled, symmetric microstrip configuration.

Coupled Microstrip Lines The configuration is depicted in Fig. 42.4. It consists of the symmetric combination of the structure of Fig. 41.7. Again, we have two fundamental modes, but the modes are hybrid, i.e., not purely TEM. Much work has been done on this configuration. The formulas proposed in the literature are quite lengthy; and we refer the reader to [20] and [21]. Reference [20] gives a very good overview together with some simple approximations, and [21] gives the most accurate formulas, taking into account the frequency dependence. It is important to remark here that the two impedances, Z0, e and Z0, o , can be found. They depend upon frequency. Both modes now have a different velocity. The data found in literature are typically expressed in terms of the effective dielectric constant. The modal field lines are both found in the air above the substrate and in the substrate itself. Hence, the field experiences an effective dielectric constant that is smaller than the dielectric constant of the substrate. The effective dielectric constant for the even mode (εr, e ) will be higher than for the odd mode (εr, o ), and are frequency dependent. The corresponding modal velocities are given by c/(εr, e )1/2 and c/(εr, o )1/2. Two-Wire Line See Section 41.2.

References [1] T. Itoh, Ed., Numerical Techniques for Microwave and Millimeter-Wave Passive Structures, New York: John Wiley & Sons, 1989. [2] J. A. Kong, Ed., Progress in Electromagnetics Research, Volumes 1–5, New York: Elsevier, 1989–1991. [3] C. F. Coombs, Ed., Printed Circuits Handbook, 3rd ed., New York: McGraw-Hill, 1988. [4] N. Faché, F. Olyslager, and D. De Zutter, Electromagnetic and Circuit Modelling of Multiconductor Transmission Lines, Oxford Engineering Series 35, Oxford: Clarendon Press, 1993. [5] T. R. Arabi, T. K. Sarkar, and A. R. Djordjevic, “Time and frequency domain characterization of multiconductor transmission lines,” Electromagnetics, vol. 9, no. 1, pp. 85–112, 1989. [6] J. R. Griffith and M. S. Nakhla, “Time domain analysis of lossy coupled transmission lines,” IEEE Trans. MTT, vol. 38, no. 10, pp. 1480–1487, Oct. 1990. [7] B. J. Cooke, J. L. Prince, and A. C. Cangellaris, “S-parameter analysis of multiconductor, integrated circuit interconnect systems,” IEEE Trans. Computer-Aided Design, vol. CAD-11, no. 3, pp. 353–360, March 1992. [8] V. Rizzoli et al., “State of the art and present trends in nonlinear microwave CAD techniques,” IEEE Trans. MTT, vol. 36, no. 2, pp. 343–363, Feb. 1988. [9] R. Gilmore, “Nonlinear circuit design using the modified harmonic balance algorithm,” IEEE Trans. MTT, vol. 34, no. 12, pp. 1294–1307, Dec. 1986. [10] IEEE Trans. Circuits Syst. Transactions, I: Fundamental Theory and Applications, Special Issue on Simulation, Modelling and Electrical Design of High-Speed and High-Density Interconnects, vol. 39, no. 11, Nov. 1992. [11] IEEE Trans. MTT, Special Issue on Process-Oriented Microwave CAD and Modeling vol. 40, no. 7, July 1992. [12] Analog Integrated Circuits Signal Process., Special Issue on High-Speed Interconnects, vol. 5, no. 1, pp. 1–107, Jan. 1994. © 2003 by CRC Press LLC

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[13] F. Olyslager, D. De Zutter, and A. T. de Hoop, “New reciprocal circuit model for lossy waveguide structures based on the orthogonality of the eigenmodes,” IEEE Trans. MTT, vol. 42, no. 12, pp. 2261–2269, Dec. 1994. [14] F. Olyslager and D. De Zutter, “Rigorous boundary integral equation solution for general isotropic and uniaxial anisotropic dielectric waveguides in multilayered media including losses, gain and leakage,” IEEE Trans. MTT, vol. 41, no. 8, pp. 1385–1392, Aug. 1993. [15] R. H. Jansen and M. Kirschning, “Arguments and an accurate model for the power-current for­ mulation of microstrip characteristic impedance,” Arch. Elek. Übertragung, vol. 37, no. 3/4, pp. 108–112, 1983. [16] T. Dhaene and D. De Zutter, “CAD-oriented general circuit description of uniform coupled lossy dispersive waveguide structures,” IEEE Trans. MTT, Special Issue on Process-Oriented Microwave CAD and Modeling, vol. 40, no. 7, pp. 1445–1554, July 1992. [17] I. V. Lindell, “On the quasi-TEM modes in inhomogeneous multiconductor transmission lines,” IEEE Trans. MTT, vol. 29, no. 8, pp. 812–817, 1981. [18] F. Olyslager, N. Faché, and D. De Zutter, “New fast and accurate line parameter calculation of general multiconductor transmission lines in multilayered media,” IEEE Trans, MTT, vol. MTT­ 39, no. 6, pp. 901–909, June 1991. [19] H. A. Wheeler, “Transmission line properties of a stripline between parallel planes,” IEEE Trans. MTT, vol. 26, pp. 866–876, Nov. 1978. [20] T. Edwards, Foundations for Microstrip Circuit Design, 2nd ed., Chichester, U.K.: John Wiley & Sons, 1992. [21] M. Kirschning and R. H. Jansen, “Accurate wide-range design equations for the frequency-depen­ dent characteristics of parallel coupled microstrip lines,” IEEE Trans. MTT, vol. 32, no. 1, pp. 83–90, Jan. 1984.

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43 Time and Frequency

Domain Responses

43.1 Time Domain Reflectometry

Luc Martens Gent University, Belgium

Daniël De Zutter Gent University, Belgium

Principles • One-Port Time Domain Reflectometry • Time Domain Reflectometry Pictures for Typical Loads • Time Domain Reflectometric Characterization of an Interconnection Structure

43.2 Frequency Domain Network Analysis Introduction • Network Analyzer: Block Diagram • Measurement Errors and Calibration

43.1 Time Domain Reflectometry Principles Time domain reflectometry is used to characterize interconnections in the time domain. The setup essentially consists of a time domain step generator and a digital sampling oscilloscope (Fig. 43.1) [1]. The generator produces a positive-going step signal with a well-defined rise time. The step is applied to the device under test. The reflected and the transmitted signals are shown on the oscilloscope. Measuring the reflected signal is called time domain reflectometry (TDR); the transmitted signal is measured using the time domain transmission (TDT) option. The characteristic impedance levels and delay through an interconnection structure can be derived from the TDR measurements. The TDT measurement gives information about the losses (decrease of magnitude) and degradation of the rise time (filtering of high-frequency components). The TDR/TDT measurements also are used to extract an equivalent circuit consisting of transmission lines and lumped elements. The fundamentals of TDR are discussed in detail in [2] and [3]. Reference [4] describes the applications of TDR in various environments including PCB/backplane, wafer/hybrids, IC packages, connectors, and cables.

One-Port Time Domain Reflectometry Figure 43.2 demonstrates that the device under test is a simple resistor with impedance ZL. In this case, a mismatch with respect to the reference or system impedance Z0 exists. A reflected voltage wave will appear on the oscilloscope display algebraically added to the incident wave. The amplitude of the reflected voltage wave, Er , is determined by the reflection coefficient of the load impedance, ZL , with respect to the system impedance Z0 : E r = ρE i =

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Z L − Z0 E Z L + Z0 i

(43.1)

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Tee generator

two-port DUT

TDR TDT

trigger

FIGURE 43.1 Setup of TDR/TDT measurements. DUT = device under test.

oscilloscope

Z0 = 50Ω Z0, τ

Vm(t)

2Ei

ZL

coaxial cable Vm(t)

Ei+Er

Ei 0

2τ

FIGURE 43.2 TDR measurement of an impedance ZL .

Figure 43.2 also depicts the time domain picture shown on the oscilloscope for a load, the impedance ZL , that is larger than Z0. From the measurement of the magnitude Er of the reflected voltage wave, the load impedance ZL can be derived.

Time Domain Reflectometry Pictures for Typical Loads The most simple loads to be measured are the open circuit and the short circuit. For ideal open-circuit and short-circuit loads the reflection coefficient is, respectively, 1 and –1. This means that the measured voltage doubles in the first case and goes to zero in the second case, when the reflected voltage wave arrives at the oscilloscope (Fig. 43.3). For any other real load impedance, the reflection coefficient lies between –1 and 1. If the real load impedance is larger than the reference impedance, the reflected voltage wave is a positive-going step signal. In this case the amplitude of the voltage is increased when the reflected wave is added to the input step (Fig. 43.4). The reverse happens when the load impedance is lower than the reference impedance. For complex load impedances, the step response is more complicated. For example, in the case of a series connection of a resistance and an inductance or a parallel connection of a resistance and a capacitance, a first-order step response is obtained. From the two pictures in Fig. 43.5, we learn that a series inductance gives a positive dip, while the capacitance produces a negative dip.

Time Domain Reflectometric Characterization of an Interconnection Structure One of the advantages of TDR is its ability to determine impedance levels and delays through an interconnection structure with multiple discontinuities. An example is shown in Fig. 43.6 for a microstrip line connected to the measurement cable. We assume a perfect junction of the two transmission lines. The line is terminated in a load with impedance ZL. Observe that two mismatches produce reflections that can be analyzed separately. The mismatch at the junction of the two transmission lines generates a reflected wave Er1 = ρl Ei . Similarly, the mismatch at the load creates a reflection due to its reflection coefficient ρ2. Both reflection coefficients are defined as: © 2003 by CRC Press LLC

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Vm(t) 2Ei Ei

t

2τ Z0 2Ei

Vm(t)

Z0, τ

ZL

ZL = ∞, ρ = +1 = open circuit

Vm(t)

Ei

t

2τ

Z0

2Ei

Vm(t)

Z0, τ

ZL = 0, ρ = −1 = short circuit

ZL

FIGURE 43.3 TDR pictures of an open- and a short-circuit termination.

ρ1 =

Z′0 − Z 0 Z 0′ + Z 0

ρ2 =

Z L − Z 0′ Z L + Z′0

(43.2)

After a time τ, the reflection at the junction of the transmission lines occurs. The voltage wave associated with this reflection adds to the oscilloscope’s picture at the time instant 2τ. The voltage wave that propagates further in the microstrip line is (1 + ρ1) Ei and is incident on ZL. The reflection at ZL occurs at the time τ + τ′ and is given by: E rL = ρ2 (1 + ρ1 )E i

(43.3)

After a time τ + 2τ′, a second reflection is generated at the junction. The reflection is now determined by the reflection coefficient ρ1′ = −ρ1 . The voltage wave Er2 that is transmitted through the junction and propagates in the direction of the generator adds to the time domain picture at time instant 2τ + 2τ′ and is given by:

(

)

E r 2 = (1 + ρ1 )E rL = (1 − ρ1 )ρ2 (1 + ρ1 )E i = 1 − ρ12 ρ2E i © 2003 by CRC Press LLC

(43.4)

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Vm(t)

4/3Ei Ei t 2τ

Z0 2Ei

Vm(t)

Z0, τ

ZL = 2Z0, ρ = +1/3

2Z0

ZL

Vm(t)

Ei 2/3Ei t

2τ Z0 2Ei

Vm(t)

Z0, τ

ZL

Z0 2

ZL = Z0/2, ρ = −1/3

FIGURE 43.4 TDR pictures of real impedance terminations (ZL = 2Z0 and ZL = Z0 /2).

If ρ1 is small in comparison to 1, then E r 2 ≈ ρ2E i

(43.5)

which means that ρ2 can be determined from the measurement of Er2. In this example, the measurement cable was perfectly matched to the generator impedance so that no reflection occurred at the generator side, which simplifies the time domain picture. In the case of an interconnection with many important discontinuities (high reflection coefficient), multiple reflections can prevent a straightforward interpretation of the oscilloscope’s display.

43.2 Frequency Domain Network Analysis Introduction A distributed circuit also can by analyzed in the frequency domain. At low frequencies the circuits are characterized by their Z- or Y-parameters. At high frequencies, circuits are better characterized by S-parameters. We focus only on S-parameter characterization.

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Vm(t) 2Ei

Ei

1 + R − Z0  E  R + Z0  i

t

2τ Z0 2Ei

R

Z0, τ

Vm(t)

ZL

ZL = R + jωL

L

Vm(t) 1 + R − Z0  E  R + Z0  i

Ei t 2τ Z0 Vm(t)

2Ei

Z0, τ

ZL

ZL =

C

R

R 1 + jωRC

FIGURE 43.5 TDR pictures of two complex impedance terminations.

ρ1

Z0

2Ei

Z0, τ

Vm(t)

Z′0, τ′

coaxial cable

Vm(t)

ρ2

ZL

microstrip line ρ′1

Z0 >Z′0 0, the distribution can be calculated by dividing the U(x) function into ∆ξ → 0 elementary slices. These may be considered to be individual Dirac-δ excitations and the responses given to them can be summarized by integration: v(x, t ) =

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1 2 πt rc

∞

∫

−∞

 (x − ξ)2  U (ξ) exp −  dξ  4t rc 

(44.5)

0912 S1-S8 Frame55.book Page 1203 Monday, October 7, 2002 10:38 AM

FIGURE 44.2 Effect of an impulse-like charge injection at x = 0. (a) Voltage distribution in subsequent time instants. (b) Voltage transients in different distances from the injection point.

FIGURE 44.3 DRC line transients. (a) An arbitrary initial voltage distribution. (b) Solution for the initial stepfunction case.

Evaluating this equation for the special case of having 2U0 voltage on the x < 0 side at t = 0, while x > 0 is voltageless, results in v(x, t ) =

2U 0 2 πt rc

 x   (x − ξ)2  exp − dξ = U 0 erfc     4t rc   2 t rc  −∞ 0

∫

(44.6)

where the integral of the GAUSS function is notated by erfc(x), the complementary error function.1 The originally abrupt voltage step is getting increasingly less steep with time [Fig. 44.3(b)]. In the middle at x = 0, the voltage remains U0.

1

2 x 2 ∞ erfc(x) = 1 – ------ ∫0 exp(–y2) dy = ------ ∫x exp(–y2) dy π

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π

0912 S1-S8 Frame55.book Page 1204 Monday, October 7, 2002 10:38 AM

FIGURE 44.4 Semi-infinite uniform DRC line. (a) Notation. (b) Normalized solution for the initially relaxed line.

Semi-Infinite Line Our next model is a bit closer to practice; the uniform RC line extends to x ≥ 0 only. At x = 0 the port is characterized by the V(t) voltage and the I(t) current (Fig. 44.4). If the line is relaxed and a I(t) = δ(t) current (a Dirac-δ current pulse) is forced to the port, a unit charge is introduced at x = 0. The result will be similar to that of Fig. 44.2(a), but instead of symmetrical spreading the charge moves towards the positive x direction only. This means that a unit charge generates a twice-larger voltage wave v(x, t ) =

 x2  1c exp −   4t rc  πt rc

(44.7)

Let us consider the case in which step function excitation is given to the port of Fig. 44.4. At t < 0, the port and the whole line are voltage free; at t ≥ 0 a constant U0 voltage is forced to the port. Comparing this situation with the problem of Fig. 44.3(b), it can be observed that the boundary conditions for the x > 0 semi-infinite line are the same as in our current example, so that the solution must to be similar as well [see Fig. 44.4(b)]:  x  v ( x , t ) = U 0 erfc    2 t rc 

(44.8)

Applying at the t = 0 instant an arbitrary W(t) forced voltage excitation to the initially relaxed line, the response is given by the Duhamel integral as follows: t

w(x, t ) =

∫ 0

  dW (τ) x erfc   dτ  2 (t − τ) rc  dτ  

(44.9)

Finite DRC Line Let the DRC line of length L of Fig. 44.5(a) be closed at x = L with a short circuit. Let the line at t < 0 be relaxed and assume a W(t > 0) voltage excitation at the x = 0 port. Using the w(x, t) voltage response of the semi-infinite line (44.9), the response function for the short-terminated line of length L © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 1205 Monday, October 7, 2002 10:38 AM

FIGURE 44.5 Finite-length uniform DRC line. (a) DRC line with short-circuit at x = L. (b) Visualization of the mirroring procedure.

v(x, t ) =

∞

∑ (−1) ⋅w(2iL + (−1) x, t ) i

i

i=0

(44.10)

∞

=

∑ (w(2kL + x, t ) − w(2kL + 2L − x, t )) k=0

This result is illustrated in Fig. 44.5(b). The v(x, t) function is given as the sum of the shifted, negated, and mirrored replicas of the w(x, t) function, so that it is a valid solution as well. The x = L boundary condition is the short circuit v(x = L, t) = 0. The i = 0 and i = 1 functions are the same size with different signs at x = L, so they cancel each other. The same is true for i = 2 and 3, and so on. The x = 0 boundary condition v = W(t) is fulfilled by the i = 0 function, while the further functions cancel each other in pairs (the i = 1 and 2, etc.). The result can be interpreted as the response of the semi-infinite line being mirrored with negative sign on the short termination. In the case of Fig. 44.5(a), the termination on both the x = 0 and x = L ends is assured by zero impedance short circuit; the resultant voltage function comes from the successive back and forth mirroring between these two “mirrors”. It is easy to understand that a termination with an open circuit results in mirroring without sign change. (At this termination the current equals to zero so that the dv/dx derivative equals to zero as well. This requirement is always fulfilled in the mirroring point summarizing the continuous incident function with its mirrored version.) According to this, the voltage on the open-terminated line of Fig. 44.6(a) is v(x, t ) =

∞

∑ (−1) (w(2kL + x, t ) + w(2kL + 2L − x, t )) k

(44.11)

k=0

which in the case of step function excitation with U0 amplitude is v(x, t ) = U 0

∞







k

k=0

This function is given in Fig. 44.6(b) for some time instants. © 2003 by CRC Press LLC





+x 2kL + 2L − x  + erfc   ∑ (−1) erfc  2kL 2 t rc   2 t rc  

(44.12)

0912 S1-S8 Frame55.book Page 1206 Monday, October 7, 2002 10:38 AM

FIGURE 44.6 Finite-length uniform DRC line. (a) Open-circuit at the far end. (b) Normalized solution for the initially relaxed line.

Solution in the Frequency Domain To find the solution of the differential Eq. (44.3), the following trial function can be used v ( x , t ) = v ⋅ exp( jωt ) ⋅ exp( γx )

(44.13)

Substituting this function into (44.3) results in the following so-called dispersion equation: γ=

jωrc = (1 + j )

1 ωrc 2

(44.14)

This means that a wave-like solution exists as well. However, it is strongly collapsing because the real and imaginary parts of γ are always equal, which means that the attenuation on a path of λ wavelength is exp (–2π)  1/535. The lossless DRC line can be considered to be a special telegraph line having neither serial inductance nor shunt conductance. The telegraph line theory can be conveniently used at the calculation of uniform DRC networks. The γ propagation constant and the Z0 characteristic impedance for the present case are: γ = src

Z0 =

r sc

(44.15)

With these the two-port impedance parameters and chain parameters of an RC line of length L can be given as follows:  cth γL Z ij = Z 0  1 sh γL

1 sh γL   cth γL 

A  C

B   ch γL = 1 D  Z sh γL  0

Z 0 sh γL  ch γL  

(44.16)

If one of the ports is terminated by the impedance of Zt, the following impedance can be “seen” on the opposite port

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0912 S1-S8 Frame55.book Page 1207 Monday, October 7, 2002 10:38 AM

Z in = Z 0

Zt ch γL + Z 0 sh γL Zt sh γL + Z 0 ch γL

(44.17)

Uniform, Lossy DRC Lines In some cases, the DRC structure also has shunt conductance, which means that it is lossy. The value of this conductance for the unit length is notated by g. In such a case, without giving the details of the calculation, the v(x, t) line voltage can be determined by the solution of the equation ∂v 1 ∂ 2v g = − v ∂t rc ∂x 2 c

(44.18)

The following forms of the characteristic impedance and the propagation constant can be used now in the frequency domain γ = r ( g + sc )

Z0 =

r g + sc

(44.19)

It is an interesting fact that the charge carrier motion in the base region of homogeneously doped bipolar transistors can be described by formally similar equations, so that the intrinsic transients of the bipolar transistors can be exactly modeled by lossy DRC two-ports [5]. Example 44.1 Wiring Delays: Neither the series resistance nor the stray capacitances of the interconnec­ tion leads of integrated circuits are negligible. As an example, in the case of a polysilicon line of 1 µm width r ≅ 50 kΩ/mm, c ≅ 0.04 pF/mm. This means that these wires should be considered to be DRC lines. The input logical levels appear on their output with a finite delay. Let us determine the delay of a wire of length L. From (44.12), v ( L, t ) = U 0

∞

∑ 2(−1) erfc((2k +1)ϑ) k

k=0

where ϑ=

L 2 t rc

The value of the summation over k will reach 0.9 at ϑ = 0.5, so that the voltage at the end of the line will reach the 90% of U0 after a time delay of t delay ≅ rcL2

(44.20)

Note that the time delay increases with the square of the length of the wire. In the case of L = 1 mm the time delay of this polysilicon wire is already 2 ns, which is more than the time delay of a CMOS logical gate. For lengthy wires (> 0.2 ÷ 0.5 mm), metal wiring must be applied with its inherently small resistivity. Example 44.2 Parasitic Effects of IC Resistors: In an IC amplifier stage the transistor is loaded with, e.g., R = 10 kΩ [Fig. 44.7(a)]. This resistor has been fabricated by the base diffusion, the sheet resistance is 200 Ω, and the parasitic capacitance is 125 pF/mm2. The width of the resistor is 4 µm. Let us determine the impedance of the resistor in the 1 to 1000 MHz range.

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0912 S1-S8 Frame55.book Page 1208 Monday, October 7, 2002 10:38 AM

FIGURE 44.7 A simple IC amplifier stage. (a) The load resistor is in fact a DRC line. (b) The amplitude and phase plot of the load.

The resistance can be realized in 4 µm × 200 µm size. The total parasitic capacitance is Cp = 0.1 pF. The impedance of the transistor-side port can be calculated according to (44.17), considering that the opposite port is short-terminated, as Z port = Z 0 th γL =

(

r th sc

)

src L =

R th sRC p sC p

(44.21)

Using the s = jω substitution, along with the actual data, the amplitude and phase functions of Fig. 44.7(b) can be obtained for the impedance. At 10 MHz, the phase shift caused by the parasitic capacitance is negligible, but at 100 MHz it is already considerable. It is important to recognize that in the case of half size linewidths the size of the resistor will be only 2 × 100 µm, which results in one-fourth of the previous value in Cp . This means that the capacitance becomes disturbing only at four times larger frequencies. Note in Fig. 44.7(b) that the amplitude function shows a 10 dB/decade decay and the phase keeps to 45°, as if the load would be characterized by a “half pole”. This 10 dB/decade frequency dependence often can be experienced at DRC lines.

44.2 Nonuniform Distributed RC Lines In some cases, the capacitance and/or the resistance of the DRC line shows a spatial dependency. This happens if the width of the lead strip is modulated in order to reach some special effects (Fig 44.8(a), tapered RC line). In case of a biased IC resistance, the capacitance changes along the length of the structure as well because of the voltage dependency of the junction capacitance. These structures are referred to as nonuniform DRC lines. Let the spatially dependent resistance and capacitance pro unit length be notated by r(x) and c(x), respectively. The following equations can be given for the structure: ∂v = −r ( x )i ∂x

∂i ∂v = −c ( x ) ∂x ∂t

(44.22)

With these, the following differential equation can be written: 1 ∂  1 ∂v  ∂v = ∂t c ( x ) ∂x  r ( x ) ∂x  © 2003 by CRC Press LLC

(44.23)

0912 S1-S8 Frame55.book Page 1209 Monday, October 7, 2002 10:38 AM

FIGURE 44.8 Nonuniform distributed RC lines. (a) Tapered line. (b) Exponentially tapered line.

We can obtain a more convenient form if we consider as an independent variable (instead of the x spatial co-ordinate) the total ρ resistance related to a given reference point (e.g., to the x = 0 point), as follows: x

ρ( x ) =

∫ r(ξ)dξ

r(x ) =

0

∂ρ ∂x

(44.24)

The variable defined this way can be considered as a kind of arc-length parameter. It has been introduced by [2]. With this new variable ∂ν 1 ∂ 2v = ∂t K (ρ) ∂ρ2

(44.25)

where

(

c x ) r((x ))

K (ρ) = K ρ( x ) =

(44.26)

The K(ρ) function describes well the spatial parameter changes of the RC line; that is, the structure of the line. Therefore, the K(ρ) function is called the structure function. Those DRC structures for which the K(ρ) functions are the same are considered to be electrically equivalent. Reference [2] uses the σ(ρ) integral or cumulative version of the structure function: ρ

x (ρ)

0

0

∫

σ(ρ) = K (ρ) dρ =

∫

c ( x ) dρ dx = r ( x ) dx

x (ρ)

∫ c(x) dx

(44.27)

0

This is the total capacitance related to the x = 0 point. This means that the cumulative srtucture function is the total capacitance versus total resistance map of the structure. An example of such a map is plotted in Fig. 44.9. The differential Eq. (44.25) is homogeneous and linear; therefore, superposition can be used. Because this equation is of variable coefficient type, however, analytic solution can be expected only rarely. Such a case is that of the K = K0 /ρ4 structure function for which v (ρ,t ) = const

 K  1 exp − 02  t 3/ 2  4ρ t 

(44.28)

Another form of (44.25) is also known. To obtain this form, we should turn to the s domain with sv = © 2003 by CRC Press LLC

1 ∂ 2v K (ρ) ∂ρ2

(44.29)

0912 S1-S8 Frame55.book Page 1210 Monday, October 7, 2002 10:38 AM

FIGURE 44.9 Cumulative structure function.

Let us introduce the following new variable: Z(ρ) =

v (s, ρ) v v = =− ∂v i(s, ρ) − 1 ∂v r ∂x ∂ρ

(44.30)

This variable is in fact the impedance of the line at the location of ρ. After rearrangements, the dZ = 1 + sK (ρ)Z 2 dρ

(44.31)

equation can be obtained. This is called the Riccati differential equation. In the case of a known K(ρ) structure function, the one-port impedance of the nonuniform line can be determined from it by integration. In some cases, even the analytic solution is known. Such a case is the exponentially tapered line of Fig. 44.8(b), for which r(x ) =

Rs exp(−Bx ) w0

c ( x ) = C pw 0 exp( Bx )

K (ρ) =

RsC p 1 B 2 ρ2

(44.32)

where Rs is the sheet resistance of the structure, Cp is the capacitance per unit area, and ρ is related to the point in the infinity. If the port in the infinity is shorted, the impedance of the location of ρ is Z(s ) =

1 + 4sRsC p B 2 −1 2sRsC p B 2

ρ

(44.33)

In other cases, numerical integration of (44.31) leads to the solution.

Approximation with Concatenated Uniform Sections The following model can be used for approximate calculation of nonuniform structures. We split the structure function into sections [see Fig. 44.10(a)] and use stepwise approximation. Inside the sections, K = constant, so that they are uniform sections. Concatenating them according to Fig. 44.10(b) an approximate model is obtained. © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 1211 Monday, October 7, 2002 10:38 AM

FIGURE 44.10 Approximation with concatenated uniform sections. (a) Stepwise approximation of the structure function. (b) Approximate model.

In the frequency domain, the overall parameters of the resultant two-port can be easily calculated. The chain parameter matrices of the concatenated sections have to be multiplied in the appropriate order. The time domain behavior can be calculated by inverse Laplace transformation.

Asymptotic Approximation for Large s The chain parameters of a nonuniform DRC line can be approximately written as A  C

 λ B 1  ≅ exp ∆ s   s µ D 2 

s  1 λ 

µ

( )

(44.34)

where R0

∆=

∫

K (ρ) dρ

R0 = ρ( L)

0

 K ( R0 )  λ=   K (0) 

1/ 4

(

)

µ = K ( R0 )K (0)

−1/ 4

This approximation is valid for large s values and for sufficiently smooth function K(ρ) [2].

Lumped Element Approximation Distributed RC networks can be approximated by lumped element RC networks as well. The case of a lossless line is depicted in Fig. 44.11(a). The element values can be determined in either of the following two ways. 1. In the case of a known structure spatial discretization can be used. The nonuniform line must be split into sections of width h [see Fig. 44.11(b)]. A node of the network is associated with the

FIGURE 44.11 Lumped element approximation. (a) Network model. (b) The line split into sections. © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 1212 Monday, October 7, 2002 10:38 AM

FIGURE 44.12 Cauer equivalent circuit (ladder structure).

middle of each section. The total capacitance of the section must be calculated, and this gives the value of the lumped capacitance connected to the node of the section. The resistance between the middle points of two adjacent sections must be calculated, and this has to be connected between the nodes of the appropriate sections. It is obvious that the accuracy can be increased by decreasing h. The price is the increasing number of lumped elements. With h → 0, we obtain the exact model. 2. When we know the impedance function, we can build the model using the pole-zero pattern of the network. For example, let us investigate a uniform RC line of finite length L, short-circuited at the far end. The corresponding impedance expression, according to (44.21), is Z(s) =

1 th R0 sK 0 sK 0

(44.35)

where K0 = c/r, R0 = r · L. This function has poles and zeroes on the negative real axis in an infinite number. The zero and pole frequencies are σ zi = (2i )

2

π2 1 4 R02 K 0

σ pi = (2i + 1)

2

π 2 1 4 R02 K 0

(44.36)

where i = 1, 2, …, ∞. Neglecting all the poles and zeroes situated well above the frequency range of interest and eliminating successively the remainder poles and zeroes from the (44.37) impedance function the element values of the ladder network in Fig. 44.12 (Cauer equivalent) can be obtained from z

Z(s) = R0

∏ (1 + s σ ) zi

i =1 p

∏(

1 + s σ pi

i =1

)

(44.37)

44.3 Infinite-Length RC Lines It was demonstrated earlier in the chapter that the DRC network can be described with the help of the pole-zero set of its impedance, as in the case of lumped element circuits. However, the number of these poles and zeroes is infinite. The infinite-length DRC lines generally do not have this property. For this network category the exact description by discrete poles and zeroes is not possible. For example, let us consider an infinitely long uniform DRC line. Its input impedance is the charac­ teristic impedance: Z(s ) =

r sc

(44.38)

Evidently, this impedance function does not have poles and zeroes on the negative σ axis. This is the general case for a more complex, nonuniform distributed network if the length of the structure is infinite. The characteristic feature of these impedance functions is that jω factors appear in them. This is why in the logarithmic amplitude vs. frequency diagram (Bode plot) regions with 10 dB/decade slope appear, as pointed out in [1]. © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 1213 Tuesday, October 8, 2002 12:50 PM

This section provides a generalization of the pole and zero notions and the time-constant represen­ tation in order to make them suitable to describe infinitely long distributed one-ports as well. Before developing new ideas let us summarize the normal, well-known descriptions of a lumped element RC one-port. The port impedance of such a circuit is described by a rational function with real coefficients, as Z(s) = R0

(1 + s σ z1 )(1 + s σ z 2 )K(1 + s σ zn−1 )

(1 + s σ )(1 + s σ )K(1 + s σ ) p1

p2

(44.39)

pn

where R0 is the overall resistance, σp are the poles, and σz are the zeroes (as absolute values). The pole and zero values, together with the overall resistance value, hold all the information about the one-port impedance. Thus, an unambiguous representation of this impedance is given by a set of pole and zero values, and an overall resistance value. This will be called the pole-zero representation. Expression (44.39) can be rearranged as Z(s ) =

n

∑ i=1

Ri = 1 + s σ pi

n

∑ 1 + sτ Ri

i=1

(44.40) i

where τ i = 1 σ pi

(44.41)

which corresponds directly to the v(t) voltage response for a step-function current excitation: v (t ) =

n

∑ R ( 1 − exp(−t τ )) i

i

(44.42)

i=1

In this case, the impedance is described in terms of the τi time-constants of its response and of the Ri magnitudes related to it. This will be called the time-constant representation.

Generalization of the Time Constant Representation2 A lumped element one-port can be represented by a finite number of τ time-constants and R magnitudes. A graphic representation of this is demonstrated in Fig. 44.13. Each line of this plot represents a time constant, and the height of the line is proportional to the magnitude. This figure can be regarded as

FIGURE 44.13 A lumped element one-port can be represented with a discrete set of time constants. (From [4], reprinted with permission, © 1991 IEEE.)

2

Portions reprinted with permission from [4]. © 1991 IEEE.

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0912 S1-S8 Frame55.book Page 1214 Monday, October 7, 2002 10:38 AM

some kind of a spectrum, the spectrum of the time constants that appeared in the step-function response of the network. The port-impedance of a lumped element network has discrete “spectrum lines” in finite number. An infinite distributed network has no discrete lines, but it can be described with the help of a continuous time constant spectrum. The physical meaning of this idea is that in a general response any time constant can occur in some amount, some density, so that a density spectrum may suitably represent it. We define the spectrum function by first introducing a new, logarithmic variable for the time and the time constants: z = lnt

ζ = ln τ

(44.43)

Let us consider a DRC one-port, the response of which contains numerous exponentials having different time constants and magnitudes. The time constant density is defined as R(ζ) = lim

∆ζ→0

sum of magnitudes between ζ and ζ + ∆ζ ∆ζ

(44.44)

From this definition directly follows the fact that the step-function response can be composed from the time-constant density: ∞

∫ R(ζ)[1 − exp(−t exp(ζ))] dζ

v (t ) =

(44.45)

−∞

This integral is obviously the generalization of the summation in (44.42). If the R(ζ) density function consists of discrete lines (Dirac-δ pulses), (44.42) is given back. Using the logarithmic time variable in the integral of (44.45) v(z ) =

∞

∫ R(ζ)[1 − exp(− exp(z − ζ))] dζ

(44.46)

−∞

a convolution-type differential equation is obtained. Differentiating both sides with respect to z, we obtain d v ( z ) = R( z ) ⊗ W ( z ) dz

(44.47)

(

(44.48)

where

)

W ( z ) = exp z − exp( z )

is a fixed weighting function with shape depicted in Fig. 44.14, and ⊗ is the symbol of the convolution operation [3]. It can be proved that the area under the function W(z) is equal to unity ∞

∫ W ( z ) dz = 1

(44.49)

−∞

This means that ∞

∫ R(z ) dz = v(t → ∞) = R

0

(44.50)

−∞

where R0 is the zero-frequency value of the impedance. In other words, the finite step-function response guarantees that the time-constant density has finite integral. © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 1215 Monday, October 7, 2002 10:38 AM

FIGURE 44.14 The shape of the W(z) function. (From [4], reprinted with permission, © 1991 IEEE.)

Generalization of the Pole-Zero Representation The task is now to substitute the pole-zero pattern of the lumped network with a continuous (eventually excepting some discrete points) function to describe the general distributed parameter network. As emphasized above, the Bode plot of a distributed parameter network frequently shows regions with a 10 dB/decade slope. Figure 44.15 presents such an amplitude diagram. Using poles and zeroes, we can only approximate this behavior. If we place to point ω1 a pole, the Bode plot turns to the decay of 20 dB/decade, which is too steep. If a zero is placed, the diagram returns to the zero-slope. However, if we alternate poles and zeroes in a manner that the mean value of the slope should give the prescribed one, then any slope can be approximated. (For the previously-mentioned case, if the zeroes are situated exactly midway between the adjacent poles, then the mean slope is 10 dB/decade.) The suitability of the approximation depends on the density of poles and zeroes and can be improved by increasing the density. In this case, the network-specific information is not carried by the number of poles and zeroes (their number tends to infinity), but by the relative position of the zeroes between the adjacent poles. An alternative interpretation is also possible. The pair of a neighboring pole and zero constitutes a dipole. The “intensity” of that dipole depends on the distance between the pole and the zero. If they coincide and cancel each other, then the intensity is equal to zero. If the zero is situated at the maximal distance from the pole (i.e., it is at the next pole), the intensity reaches its maximal value. We choose this to be the unity.

FIGURE 44.15 The 10 dB/decade decay of a DRC line amplitude plot can be approximated with an alternative sequence of poles and zeroes. (From [4], reprinted with permission, © 1991 IEEE.) © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 1216 Monday, October 7, 2002 10:38 AM

For later convenience, we turn to a logarithmic variable on the negative σ-axis: Σ = ln(−σ)

(44.51)

Let us investigate a ∆Σ interval of the logarithmic Σ-axis bounded by two adjacent poles. The distance between the left-hand pole and the inner zero is δΣ. Now, suppose that the density of the poles tends to infinity; i.e., ∆Σ becomes infinitely small. In this case the dipole intensity function is I d ( Σ ) = lim

∆Σ→0

δΣ ∆Σ

(44.52)

Considering that the poles and zeros of an RC port-impedance alternate, it follows that 0 ≤ Id ≤ 1. For an infinite, distributed RC two-pole the dipole intensity generally has regions in which the Id value is between 0 and 1. For example, if the Bode plot shows a slope of 10 dB/decade, the value of Id equals 0.5. This occurs in the case of an infinite, uniform RC line. For discrete circuits, the Id function has only two possible values: 0 or 1.

Relations among R(), Id () and the Impedance Function Obviously, we needed one-to-one relations between the time constant density or the dipole intensity representation and the impedance expression of the one-port. [For the lumped element case (44.39) and (44.40) give these correspondences]. Rather simple relations exist among the R(ζ), Id (Σ), and the Z(s) impedance function (see below). An interesting feature of these relations is a striking mathematical symmetry: the same expression couples the time constant density to the impedance and the dipole intensity to the logarithmic impedance. The detailed proofs of the relations presented here are given in [4]. If the Z(s) complex impedance function is known, R(ζ) or Id (Σ) can be calculated as3 R(ζ) = Id (Σ) =

(

)

1 Im Z s = − exp(−ζ) π

( (

(44.53)

))

1 Im ln Z s = − exp( Σ ) π

(44.54)

If the R(ζ) or Id (Σ) function is known Z(S) = R0 −

∞

exp(S − x )

∫ R(−x) 1 + exp(S − x) dx

(44.55)

−∞

ln Z(S) = ln R0 −

∞

exp(S − x )

∫ I (x) 1 + exp(S − x) dx d

(44.56)

−∞

where S is the complex-valued logarithm of the complex frequency: S = ln s

(44.57)

Using the integral Eqs. (44.55) and (44.56), however, we must keep at least one from the two conditions:

3

For (44.53) Z(s → ∞) = 0 is supposed.

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0912 S1-S8 Frame55.book Page 1217 Monday, October 7, 2002 10:38 AM

1. s is not located on the negative real axis. 2. If s is located on the negative real axis then, at this point, and in a ε → 0 neighborhood, R(ζ) or Id (Σ) must be equal to 0. Note that (44.53) to (44.56) are closely related to the Cauchy integral formula of the complex function theory. Substituting (44.53) into (44.55) and exploiting some inherent properties of the RC impedance functions after some mathematics, the Cauchy integral results. The same is true for (44.54) and (44.56). An important feature of the transformations of (44.53) and (44.55) is that they are linear. This means that the Z(s) ↔ R(ζ) transformation and the summation are interchangeable.

Practical Calculation of the R(ζ) Function4 Equation (44.53) suggests that only the jω imaginary frequency has to be replaced by the s = −exp(−z) complex frequency, and then the imaginary part of the calculated complex response multiplied by 1/π provides the time-constant spectrum. However, the procedure is not as simple as that because of the use of (44.53). This equation requires a great amount of caution. As the equation shows, the imaginary part of the Z impedance has to be calculated along the negative real axis of the complex plane. Along this axis, singularities usually lie: the poles of the network equation of lumped circuits or some singular lines in the case of distributed systems. These singularities can prevent the use of (44.53) for the calculation of the time-constant spectrum. We can overcome these difficulties by adapting an approximate solution. In order to walk around the “dangerous” area, we have to avoid following the negative real axis. A line that is appropriately close to this axis might be used instead [9], like: s = −(cosδ + j sinδ) exp(−z )

(44.58)

Obviously, the δ angle has to be very small, not more than 2 to 5°. Even if this angle is small, an error is introduced into the calculation. It can be proven that the calculated RC (z) time-constant spectrum can be expressed with the exact one by the following convolution equation: RC ( z ) =

π−δ R( z ) ⊗ er ( z ) π

(44.59)

where er ( z ) =

sin δ exp(−z ) 1 π − δ 1 − 2 cosδ exp(−z ) + exp(−2z )

)

(44.60)

This function is a narrow pulse of unity area. The error of the calculation is represented by this function. Diminishing δ the er(z) function becomes narrower and narrower. Thus, any accuracy requirement can be fulfilled by choosing an appropriately small δ angle. The half-value width, which is a measure of the resolution, is given by  ∆ e = 2ln 2 − cosδ + 

(2 − cosδ)2 −1 ≅ 2δ

(44.61)

If, for example, δ = 2°, then the resolution is 0.1 octave, which means that two poles can be distinguished if the ratio between their frequencies is greater than 1.072. Obviously, the calculated result has to be corrected with the factor of π/(π − δ). Example 44.3 A tight analogy exists between electrical conductance and heat flow. Heat-conducting media, which can be characterized with distributed heat resistance and distributed heat capacitance, behave similarly to the electrical DRC networks. The analogous quantities are as follows: 4

Portions reprinted, with permission, from [9]. © 2000 IEEE.

© 2003 by CRC Press LLC

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(a)

(b)

FIGURE 44.16 A transistor package and its time-constant spectrum. (From [9], reprinted with permission. © 2000 IEEE.)

Voltage Current Resistance Capacitance

→ → → →

Temperature Power flow Thermal resistance Heat capacitance

In the simplest model law, 1-V voltage corresponds to 1°C, 1 A current to 1 W power, etc., but different mapping can be applied as well. The described analogy means that the tool set that is used to treat DRC networks can be applied to the calculation of heat-flow problems as well. This fact provides a direct way to calculate time-constant spectra in thermal field solver programs. These are thermal simulation tools suitable to solve the model equations in the s-domain. By using the substitution of (44.58), some of these programs calculate directly the thermal time-constant spectrum of different structures [9]. As an example, a transistor package, presented in Fig. 44.16(a), was simulated. The time-constant spectrum calculated by the field solver is plotted in Fig. 44.16(b). It is clearly visible that besides the two dominant time-constants a large number of further time-constants appear in the spectrum.

44.4 Inverse Problem for Distributed RC Circuits Equation (44.47) offers a direct way to determine the time-constant density from the (measured or calcu­ lated) response function, which means that it is a method for the identification of RC one-ports. Using (44.47) for a measured time domain response function, the time-constant density of the one-port impedance can be determined. By using this method, equivalent circuits can be constructed easily. This possibility is of considerable practical importance [8]; however, only approximate results can be obtained because the calculation leads to the inverse operation of the convolution. This operation can be done only approximately. A possibility exists for identification in the frequency domain as well. Introducing the Ω = ln ω notation for the frequency axis, convolution-type equations can be found [8] between the R(ζ) time-constant density and the Z(ω) complex impedance: −

d Re Z(Ω) = R(ζ = −Ω) ⊗WR (Ω) dΩ

(44.62)

−Im Z(Ω) = R(ζ = −Ω) ⊗WI (Ω)

(44.63)

where the weight-functions are WR (Ω) =

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2⋅ exp(2Ω)

(1 + exp(2Ω))

2

(44.64)

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WI (Ω) =

exp(Ω) 1 + exp(2Ω)

(44.65)

Moreover, a direct convolution relation exists between the Bode diagram of the impedance and the dipole intensity. Considering the Bode amplitude and phase diagrams, i.e., by using ln(Z(Ω)) = ln abs(Z(Ω)) + j·arcus(Z(Ω)), we obtain −

(

)

(44.66)

−arcus Z(Ω) = I d (Ω) ⊗WI (Ω)

(44.67)

d ln abs Z(Ω) = I d (Ω) ⊗WR (Ω) dΩ

(

)

These equations may also be used for identification.

Network Identification by Deconvolution All the relations between the R(ζ) time-constant spectrum and the different network responses are of convolution type (44.47), (44.62), and (44.63). Knowing some kind of network responses the inverse operation of the convolution: the deconvolution leads to the R(ζ) function. The same is true for the relations (44.66), (44.67) of the Id (Σ) dipole intensity. This means that the problem of identification of DRC networks is reduced to a deconvolution step. This method, called NID (network identification by deconvolution), is discussed in detail in [8], together with the appropriate deconvolution methods. An important fact is that if we know the time response or only the real or the imaginary part of the frequency response, the network can be completely identified. (Noise effects produce practical limits — see later.) Example 44.4 For the sake of simplicity, a lumped circuit problem will be discussed first. The investigated RC network is given in Fig. 44.17(a). We have calculated the frequency response of the Z(s) portimpedance of this circuit by using a standard circuit-simulator program, with a 40 point/frequency­ decade resolution. Both the real and the imaginary parts of this impedance are plotted in Fig. 44.17(b). In order to apply (44.62), the derivative of the real part was calculated numerically. The result is shown in Fig. 44.18(a). In the next step, this function was deconvolved by the WR(Ω) function. The result is plotted in Fig. 44.18(b). This function is the approximate time-constant density of the network. We expect that this function depicts the pole-pattern of the circuit. This is in fact obtained: the four peaks of the function are lying at f = 497.7 Hz, 1585 Hz, 4908 Hz, and 15850 Hz. These values correspond to the time constants of 320 µs, 100.4 µs, 32.43 µs, and 10.04 µs, respectively. The ratios of the peak areas are about 1:2:1:2. These data agree well with the actual parameters of the circuit in Fig. 44.17(a).5 Notice that the noise corrupting the Z(ω) function considerably affects the result of the identification. In order to reach 1 octave resolution of R(ζ) along the frequency axis, about 68 dB noise separation is needed in Z(ω). Detailed discussion of the noise effects on the identification can be found in [8]. Example 44.5 As a second example, let us discuss the thermal identification of a semiconductor package + heat sink structure. The analogy between electrical current and heat flow introduced in Example 44.3 will be applied again. Between a semiconductor chip and its ambient a complex distributed thermal structure exists con­ sisting of many elements. The main parts of it are the chip itself, the soldering, the package, mounting to the heat sink, the heat sink itself, and the ambience. This is obviously a distributed thermal RC network, the input-port of which is the top surface of the chip and the far end is the ambience (“the world”).

5

Example reprinted with permission from [8]. © 1998 IEEE.

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(a)

(b)

FIGURE 44.17 RC ladder and the frequency response of the Z(ω) impedance. (From [8], reprinted with permission. © 1998 IEEE.)

(a)

(b)

FIGURE 44.18 Identification steps. (a) Derivative of Real(Z). (b) The identified time-constant spectrum. (From [8], reprinted with permission. © 1998 IEEE.)

Thus, the structure can be considered practically infinite. This means that we have to examine a nonuniform infinite-length DRC network. Investigations in the time domain require recording the thermal step-response of the system. A thermal test chip can be used for this purpose, containing appropriate heating elements that can assure stepfunction power excitation. The temperature rise is measured by the forward voltage change of a pn junction integrated into the test chip as well. This is the thermal response function. Such a thermal response is plotted in Fig. 44.19(a). The time range of the measurement is strikingly wide: 9 decades, from 10 µs to some thousand s. This is indispensable since the thermal time constants of the heat-flow structure vary over a wide range. According to (44.47), after numerical derivation of the step-response and by a consecutive deconvo­ lution, the time constant density function R(z) can be obtained [see Fig. 44.19(b)]. Because of the quantization noise and measuring error the deconvolution operation can be done only approximately with a 1 ÷ 1.5 octave resolution. A suitable algorithm is discussed in [7]. Figure 44.19(b) illustrates that, in the 100 µs to 10 s interval, time constants spread over a relative wide range. This refers to the distributed structure of the chip and the package. At τ ≈ 1000 s, a relatively sharp, distinct time constant appears. This can be identified as originating from the heat capacitance of the whole heat sink and the heat sinkambience thermal resistance. Splitting the resultant time constant spectrum into ∆τ time slots, each of these slots can be approxi­ mated by a Dirac-δ spectrum line proportional in height to the appropriate slot area. These give the data of a lumped element approximation according to (44.40). Now, the equivalent circuit of the heat-flow structure can be generated either in Foster or in Cauer normal form. © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 1221 Monday, October 7, 2002 10:38 AM

(a)

(b)

FIGURE 44.19 Thermal identification of a package + heat sink structure. (a) Thermal response between 10 µs and 4000 s. (b) The R(z) time-constant density function.

FIGURE 44.20 Cumulative structure function of the package + heat sink structure identified from the response function.

Using the Cauer-approximation of the DRC line we can calculate the approximate K(ρ) and σ(ρ) structure functions. From these functions, the heat-conducting cross section areas, the heat flow path length, etc. can be derived. This means that geometric and physical data of the heat-flow structure can be extracted and checked with the help of an electrical measurement. The structure function calculated from the measurement results of Fig. 44.19 is plotted in Fig. 44.20. It is easy to read out, e.g., the Chs heat capacitance of the heat sink. For more details, see [6],[10].

References [1] M. S. Ghausi and J. J. Kelly, Introduction to Distributed Parameter Networks, New York: Holt, Rinehart and Winston, 1968. [2] E. N. Protonotarios and O. Wing, “Theory of nonuniform RC lines, Part I,” IEEE Transactions on Circuit Theory, vol. 14, pp. 2-12, Mar. 1967 [3] D. G. Gardner, J. C. Gardner, G. Laush and W. W. Meinke: “Method for the analysis of multicom­ ponent exponential decay curves”, Journal of Chemical Physics, vol. 31, no. 4, pp. 978-986, Oct. 1959 [4] V. Székely, “On the representation of infinite-length distributed RC one-ports”, IEEE Transactions on Circuits and Systems, vol. 38, pp. 711-719, July 1991. © 2003 by CRC Press LLC

0912 ch44(1222) frame55 Page 1222 Tuesday, October 29, 2002 1:42 PM

[5] R L. Pritchard, Electrical Characteristics of Transistors, New York: McGraw-Hill, 1967 [6] V. Székely and Tran Van Bien, “Fine structure of heat flow path in semiconductor devices: a measurement and identification method,” Solid-State Electronics, vol. 31, pp. 1363-1368, Sept. 1988. [7] T. J. Kennett, W. V. Prestwich, A. Robertson, “Bayesian deconvolution. I: convergent properties”, Nuclear Instruments and Methods, no. 151, pp. 285-292, 1978. [8] V. Székely, “Identification of RC Networks by Deconvolution: Chances and Limits”, IEEE Transac­ tions on Circuits and Systems-I. Theory and applications, vol. 45, no. 3, pp. 244-258, March 1998. [9] V. Székely, M. Rencz, “Thermal dynamics and the time constant domain”, IEEE Transactions on Components and Packaging Technologies, vol. 23, no. 3, pp. 587-594, Sept. 2000. [10] V. Székely, “Restoration of physical structures: an approach based on the theory of RC networks”, Proceedings of the ECCTD’99, European Conference on Circuit Theory and Design, 29 Aug.–2. Sept. 1999, Stresa, Italy, pp. 1131-1134.

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45 Synthesis of Distributed Circuits 45.1 45.2 45.3 45.4 45.5 45.6

Generic Relations Synthesis of a Capacitance Synthesis of an Inductance Synthesis of a Resistance Synthesis of Transformers Synthesis Examples Series L-C Circuit • Parallel L-C Circuit • Series L-C-R Circuit • Parallel L-C-R Circuit • Low-Pass Filters • High-Pass Filters • Bandpass Filters • Bandstop Filters • Further Comments on Distributed Circuit Filters

45.7 Synthesis of Couplers

T. K. Ishii

Generic Relations • Proximity Couplers • Quarter-Wavelength Couplers • Lange Couplers

Marquette University, Wisconsin

45.1 Generic Relations The starting procedure for the synthesis of distributed circuits is the same as for the conventional synthesis of lumped parameter circuits. If a one-port network is to be synthesized, then a desired driving-point immittance H(s) must be defined first, where s = σ + jω

(45.1)

is the complex frequency, σ is the damping coefficient of the operating signal, and ω is the operating angular frequency. If a two-port network is to be synthesized, then a desired transmittance T(s) must be defined first. According to conventional principles of network synthesis [1], for the one-port network, H(s) is represented by H (s ) =

P(s ) ans n + an−1s n−1 + L + a1s + a0 = Q(s ) bms m + bm−1s m−1 + L + b1s + b0

(45.2)

where an and bm are constants determined by the network parameters, Q(s) is a driving function, and P(s) is the response function. For a two-port network T (s ) =

© 2003 by CRC Press LLC

P(s ) ans n + an−1s n−1 + L + a1s + a0 = Q(s ) bms m + bm−1s m−1 + L + b1s + b0

(45.3)

0912 S1-S8 Frame55.book Page 1224 Monday, October 7, 2002 10:38 AM

Both H(s) and T(s) should be examined for realizability [1] before proceeding. If the summation of even-order terms of P(s) is M1(s) and the summation of odd-order terms of P(s) is N1(s), then P(s ) = M1 (s ) + N1 (s )

(45.4)

Q( s ) = M 2 ( s ) + N 2 ( s )

(45.5)

Similarly,

For a one-port network the driving-point impedance is synthesized by [1] Z (s ) =

N1 (s ) M 2 (s )

(45.6)

Z (s ) =

M1 (s ) N 2 (s )

(45.7)

or

For a two-port network [1], if P(s) is even, the transadmittance is y 21 =

P (s ) N 2 (s )

[

]

1 + M 2 (s ) N 2 (s )

(45.8)

the open-circuit transfer admittance is y 21 =

P (s ) N 2 (s )

(45.9)

y 22 =

M 2 (s ) N 2 (s )

(45.10)

and the open-circuit output admittance is

If P(s) is odd, y 21 =

P (s ) N 2 (s )

[

]

1 + M 2 (s ) N 2 (s )

(45.11)

y 21 =

P (s ) M 2 (s )

(45.12)

y 22 =

N 2 (s ) M 2 (s )

(45.13)

and

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0912 S1-S8 Frame55.book Page 1225 Monday, October 7, 2002 10:38 AM

In both cases, y11 =

y 21 (s ) n

(45.14)

where n is the current-ratio transfer function from port 1 to port 2. From these y- or z-parameters, the required values for the network components, i.e., L, C, and R, can be determined [1]. In high-frequency circuits the L, C, and R may be synthesized using distributed circuit components. The synthesis of distributed components in microstrip line and circuits is the emphasis of this chapter.

45.2 Synthesis of a Capacitance If the required capacitive impedance is –jXc Ω, the capacitance is C=

1 ωXC

(45.15)

where XC > 0

(45.16)

and ω is the operating angular frequency. In a distributed circuit the capacitance C is often synthesized using a short section of a short-circuited transmission line of negligibly small transmission line loss. If the characteristic impedance of such a transmission line is Z0, the operating transmission line wavelength is λl , and the length of the transmission line is l in meters, then [2] jX c = jZ 0 tan

2πl λl

(45.17)

where λl λ 0. For example, the function 3.7x11.4 x 2 3 + 1.8x1–1 x 32.3 is a posynomial in the variables x1, x2, x3. Roughly speaking, a posynomial is a function that is similar to a polynomial except that the coefficients γj must be positive, and an exponent αij could be any real number, and not necessarily a positive integer, unlike a polynomial. A posynomial has the useful property that it can be mapped onto a convex function through an elementary variable transformation, (xi) = (e zi) when xi > 0 ∀ i. Such functional forms are useful since in the case of an optimization problem where the objective function and the constraints are posynomial, the problem can easily be mapped onto a convex programming problem.

Constrained Optimization Methods Most problems in integrated circuit design involve the minimization or maximization of a cost function subject to certain constraints. In this section, a few prominent techniques for constrained optimization are presented. The reader is referred to [1] for details on unconstrained optimization. Linear Programming Linear programming is a special case of nonlinear optimization, and is the convex programming problem where the objective and constraints are all linear functions. The problem is stated as minimize CT x

subject to Ax ≤ b where c, x ∈R n , b ∈R m , A ∈R m×n © 2003 by CRC Press LLC

(49.9)

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1305

Design by Optimization

It can be shown that any solution to a linear program must necessarily occur at a vertex of the constraining polytope. The most commonly used technique for solution of linear programs, the simplex method [1], is based on this principle. The computational complexity of this method can show an exponential behavior for pathological cases, but for most practical problems, it has been observed to grow linearly with the number of variables and sublinearly with the number of constraints. Algorithms with polynomial time worst-case complexity do exist; these include Karmarkar’s method and the Shor–Khachiyan ellipsoidal method. The computational complexity of the latter, however, is often seen to be impractical from a practical standpoint. Some examples of computer-aided design (CAD) problems that are posed as linear programs include placement, gate sizing, clock skew optimization, layout compaction, etc. In several cases, the structure of the problem can be exploited to arrive at graph-based solutions, for example, in layout compaction. Lagrange Multiplier Methods These methods are closely related to the first-order Kuhn–Tucker necessary conditions on optimality, which state that given an optimization problem of the form in Eq. (49.1), if f and g are differentiable at x*, then there is a vector λ∈Rm, (λ)i ≥ 0, such that

( )

( )

∇f x * + λT ∇g x * = 0

( )

T g x * = 0

(49.10) (49.11)

These correspond to m + 1 equations in m + 1 variables; the solution to these provides the solution to the optimization problem. The variables λ are known as the Lagrange multipliers. Note that since g1(x*) ≤ 0, and because of the nonnegativity constraint on the Lagrange multipliers, λ, it follows from Eq. (49.11) that (λ)i = 0 for inactive constraints (constraints with gi (x) < 0). Penalty Function Methods These methods convert the constrained optimization problem in Eq. (49.1) into an equivalent uncon­ strained optimization problem, since such problems are easier to solve than constrained problems, as minimize h( x ) = f ( x ) + c ⋅ P( x )

(49.12)

where P(x): Rn → R is known as a penalty function and c is a constant. The value of P(x) is zero within the feasible region, and positive outside the region, with the value becoming larger as one moves farther from the feasible region; one possible choice when the gi (x)’s are continuous is given by P( x ) =

m

∑ max(0, –g (x)) i

(49.13)

i=1

For large c, it is clear that the minimum point of Eq. (49.12) will be in a region where P is small. Thus, as c is increased, it is expected that the corresponding solution point will approach the feasible region and minimize f. As c → ∞, the solution of the penalty function method converges to a solution of the constrained optimization problem. In practice, if one were to begin with a high value of c, one may not have very good convergence properties. The value of c is increased in each iteration until c is high and the solution converges. Method of Feasible Directions The method of feasible directions is an optimization algorithm that improves the objective function – without violating the constraints. Given a point x, a direction d is feasible if there is a step size α > 0 – such that x + α·d∈ ∀ 0 ≤ α ≤ α, where  is the feasible region. More informally, this means that one © 2003 by CRC Press LLC

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1306

The Circuits and Filters Handbook, Second Edition –

can take a step of size up to α along the direction d without leaving the feasible region. The method of feasible direction attempts to choose a value of α in a feasible direction d such that the objective function f is minimized along the direction, and α is such that x + α·d is feasible. One common technique that uses the method of feasible direction is as follows. A feasible direction at x is found by solving the following linear program: minimize ∈ (49.14)

subject to ∇f ( x ) ⋅ d ≤ ∈ ∇g i ( x ) ⋅ d ≤ ∈

(49.15)

and normalization requirements on d. where the second set of constraints is chosen for all gi ≥ –b, where b serves to incorporate the effects of near-active constraints to avoid the phenomenon of jamming (also known as zigzagging) [1]. The value of b is brought closer to 0 as the optimization progresses. One common method that is used as a normalization requirement is to set dT d = 1. This constraint is nonlinear and nonconvex, and is not added to the linear program as an additional constraint; rather, it is exercised by normalizing the direction d after the linear program has been solved. An appropriate step size in this direction is then chosen by solving a one-dimensional optimization problem. Feasible direction methods are popular in finding engineering solutions because the value of x at each interation is feasible, and the algorithm can be stopped at any time without waiting for the algorithm to converge, and the best solution found so far can be used. Vaidya’s Convex Programming Algorithm As mentioned earlier, if the objective function and all constraints in Eq. (49.1) are convex, the problem is a convex programming problem, and any local minimum is a global minimum. The first large-scale practical implementation of this algorithm is described in [3]. Initially, a polytope ∈Rn that contains the optimal solution, xopt , is chosen. The objective of the algorithm is to start with a large polytope, and in each iteration, to shrink its volume while keeping the optimal solution, xopt , within the polytope, until the polytope becomes sufficiently small. The polytope  may, for example, be initially selected to be an n-dimensional box described by the set

{x x

min

≤ x i ≤ x max

}

(49.16)

where xmin and xmax are the minimum and maximum values of each variable, respectively. The algorithm proceeds iteratively as follows. STEP 1. A center xc deep in the interior of the polytope  is found. STEP 2. An oracle is invoked to determine whether the center xc lies within the feasible region . This may be done by verifying that all of the constraints of the optimization problem are met at xc. If the point xc lies outside , it is possible to find a separating hyperplane passing through xc that divides  into two parts, such that  lies entirely in the part satisfying the constraint cT x ≥ β

(49.17)

where c = –[∇gp (x)]T is the negative of the gradient of a violated constraint, gp and β = cTxc. The separating hyperplane above corresponds to the tangent plane to the violated constraint. © 2003 by CRC Press LLC

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1307

Design by Optimization

X

S

X xc

X

xopt f decreasing (a)

(b)

X

X X

X

(d)

(c)

FIGURE 49.4 Example illustrating the convex programming algorithm.

If the point xc lies within the feasible region , then there exists a hyperplane (49.17) that divides the polytope into two parts such that xopt is contained in one of them, with

[

]

c = − ∇f ( x )

T

(49.18)

being the negative of the gradient of the object function, and β being defined as β = cTxc once again. STEP 3. In either case, the constraint (49.17) is added to the current polytope to give a new polytope that has roughly half the original volume. STEP 4. Go to Step 1; the process is repeated until the polytope is sufficiently small. Example. The algorithm is illustrated by using it to solve the following problem minimize f ( x1 , x 2 ) such that ( x1 , x 2 ) ∈S

(49.19)

where S is a convex set and f is a convex function. The shaded region in Fig. 49.4(a) is the set S, and the dotted lines show the level curves of f. The point xopt is the solution to this problem. 1. The expected solution region is bounded by a rectangle, as shown in Fig. 49.4(a). 2. The center, xc, of this rectangle is found. 3. The oracle is invoked to determine whether xc lies within the feasible region. In this case, it can be seen that xc lies outside the feasible region. Hence, the gradient of the constraint function is used to construct a hyperplane through xc, such that the polytope is divided into two parts of roughly equal volume, one of which contains the solution xopt . This is illustrated in Fig. 49.4(b), where the shaded region corresponds to the updated polytope. 4. The process is repeated on the new smaller polytope. Its center lies inside the feasible region; hence, the gradient of the objective function is used to generate a hyperplane that further shrinks the size of the polytope, as shown in Fig. 49.4(c). 5. The r esult of another iteration is illustrated in Fig. 49.4(d). The process continues until the polytope has been shrunk sufficiently. © 2003 by CRC Press LLC

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The Circuits and Filters Handbook, Second Edition

Other Methods The compact nature of this handbook makes it unfeasible to enumerate or describe all of the methods that are used for nonlinear optimization. Several other methods, such as Newton’s and modified New­ ton/quasi-Newton methods, conjugate gradient methods etc., are often useful in engineering optimiza­ tion. For these and more, the reader is referred to a standard text on optimization, such as [1].

Multicriterion Optimization and Pareto Criticality Most integrated circuit design problems involve tradeoffs between multiple objectives. In cases where one objective can be singled out as the most important one, and a reasonable constraint set can be defined in terms of the other objectives, the optimization problem can be stated using the formulation in Eq. (49.1). This is convenient since techniques for the solution of a problem in this form have been extensively studied, and a wide variety of optimization algorithms is available. Let f be a vector of design objectives that is a function of the design variables x, where

(

)

f ( x ): R n → R m = f1 ( x ), f 2 ( x ),…, fm ( x )

(49.20)

It is extremely unlikely in a real application that all of the fi’s will be optimal at the same point, and hence one must trade off the values of the fi’s in search for the best design point. In this context, we note that at a point x, we are interested in taking a step δ in a direction d,d = 1, so that fi ( x + δ ⋅ d ) ≤ fi ( x )∀1 ≤ i ≤ m

(49.21)

A Pareto critical point is defined as a point x where no such small step of size less than δ exits in any direction. If a point is Pareto critical for any step size from the point x, then, x is a Pareto point. The notion of a Pareto critical point is, therefore, similar to that of a local minimum, and that of a Pareto point to a global minimum. In computational optimization, one is concerned with the problem of finding a local minimum since, except in special cases, it is the best that one can be guaranteed of finding without an exhaustive search. If the set of all Pareto critical points is Pc, and the set of Pareto points is P, then clearly P ⊂ Pc. In general, there could be an infinite number of Pareto points, but the best circuit design must necessarily occur at a Pareto point x∈P. In Fig. 49.5, the level curves of two objective functions are plotted in R2. f1 is nonlinear and has a minimum at P*. f2 is linear and decreases as both x1 and x2 decrease. The Pareto critical set, Pc, is given by the dashed curve. At a few of the points, the unit normal to the level lines of f1 and f2, i.e., the negative gradients of f1 and f2 is shown. From the figure, it can be seen that if the unit normals at the point x are not equal and opposite, then the unit normals with have a common downhill direction allowing a simultaneous decrease in f1 and f2, and hence, x would not be a Pareto critical point. Therefore, a Pareto critical point is one where the gradients of f1 and f2 are opposite in direction, i.e., λ ∇f1 = – ∇f2, where λ is some scale factor. In higher dimensions, a Pareto critical point is characterized by the existence of a set of weights, wi > 0 ∀ 1 ≤ i ≤ m, such that m

∑ w ∇f = 0 i

i

(49.22)

i=1

Some of the common methods that are used for multicriterion optimizations are Weighted sums optimization: The multiple objectives, f1(x), ..., fm (x) are combined as: F (x ) =

m

∑ w f (x ) i

i

i=1

where w i > 0∀ i = 1 . . . m, and the function F(x) is minimized. © 2003 by CRC Press LLC

(49.23)

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Level lines of f1

P2

P*

Downhill for f2

Downhill for f1

Pareto critical set, Pc

P1 Level lines of f2

FIGURE 49.5 Exact conflict at a Pareto critical point [2].

At any local minimum point of F(x), the relation in Eq. (49.22) is seen to be valid, and hence, x∈Pc . In general, P ≠ Pc , but it can be shown that when each fi is a convex function, then P = Pc ; if so, it can also be shown that all Pareto points can be obtained by optimizing the function F in Eq. (49.23). However, for nonconvex functions, there are points x∈P that cannot be obtained by the weighted sum optimization since Eq. (49.22) is only a necessary condition for the minimum of F. A characterization of the Pareto points that can be obtained by this technique is provided in [2]. In practice, the wi’s must be chosen to reflect the magnitudes of the fi ’s. For example, if one of the objectives is a voltage quantity whose typical value is a few volts, and another is a capacitor value that is typically a few picofarads, the weight corresponding to the capacitor value would be roughly 1012 times that for the voltage, in order to ensure that each objective has a reasonable contribution to the objective function value. The designer may further weigh the relative importance of each objective in choosing the wi’s. This objective may be combined with additional constraints to give a formulation of the type in Eq. (49.1). Minmax optimization: The following objective function is used for Eq. (49.1) minimize

F ( x ) = max w i fi ( x ) 1≤ i ≤ m

(49.24)

where the weights wi > 0 are chosen as in the case of weighted sums optimization. The preceding objective function can equivalently be written as the following constrained optimization problem: minimize r subject to w i fi ( x ) ≤ r

(49.25)

Minimizing the objective function described by Eq. (49.24) with different sets of wi values can be used to obtain all Pareto points [2]. Since this method can, unlike the weighted-sums optimization method, be used to find all Pareto critical points, it would seem to be a more natural setting for obtaining Pareto points than the weighted sum minimization. However, when the fi ’s are convex, the weighted sums approach is preferred since it © 2003 by CRC Press LLC

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is an unconstrained minimization, and is computationally easier than a constrained optimization. It must be noted that when the fi ’s are not all convex, the minmax objective function is nonconvex, and finding all local minima is a nontrivial process for any method.

49.3 The Transistor Sizing Problem for CMOS Digital Circuits Problem Description Circuit delays in integrated circuits often have to be reduced to obtain faster response times. A typical CMOS digital integrated circuit consists of multiple stages of combinational logic blocks that lie between latches that are clocked by system clock signals. For such a circuit, delay reduction must ensure that valid signals are produced at each output latch of a combinational block, before any transition in the signal clocking the latch. In other words, the worst-case input-output delay of each combinational stage must be restricted to be below a certain specification. Given the circuit topology, the delay of a combinational circuit can be controlled by varying the sizes of transistors in the circuit. Here, the size of a transistor is measured in terms of its channel width, since the channel lengths of MOS transistors in a digital circuit are generally uniform. In coarse terms, the circuit delay can usually be reduced by increasing the sizes of certain transistors in the circuit. Hence, making the circuit faster usually entails the penalty of increased circuit area. The area-delay trade-off involved here is, in essence, the problem of transistor size optimization. Three formal statements of the problem are stated next: 1. Minimize Area subject to Delay ≤ Tspec 2. Minimize Delay subject to Area ≤ Aspec 3. Minimize Area · [Delay]c

(49.26) (49.27) (49.28)

where c is a constant. Of all of these, the first form is perhaps the most useful practical form, since a designer’s objective is typically to meet a timing constraint dictated by a system clock.

Delay Modeling We examine the delay modeling procedure used in TImed LOgic Synthesizer (TILOS) at the transistor, gate, and circuit levels. Most existing transistor-sizing algorithms use minor variations on this theme. Transistor Level Model An MOS transistor is modeled as a voltage-controlled switch with an on-resistance, Ron , between drain and source, and three grounded capacitances, Cd , Cs , and Cg , at the drain, source, and gate terminals, respectively, as shown in Fig. 49.6. The behaviors of the resistance and capacitances associated with a MOS transistor of channel width x are modeled as Ron ∝1 x

(49.29)

Cd , Cs , C g ∝x

(49.30)

Cd Cg Cs

FIGURE 49.6 An RC transistor model.

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n3

external load capacitance CL

X3

“1” n2

R3

C2

n2 X2

R2

C1,VC (0) = 0 1

n1

n1 X1

“1”

C3 n3

R1

(a)

(b)

FIGURE 49.7 (a) A sample pull-down network. (b) Its RC representation.

Gate Level Model At the gate level, delays are calculated in the following manner. For each transistor in a pull-up or pulldown network of a complex CMOS gate, the largest resistive path from the transistor to the gate output is computed, as well an the largest resistive path from the transistor to a supply rail. Thus, for each transistor, the network is transformed into an RC line, and its Elmore time constant [4] is computed and is taken to be the gate delay. While finding the Elmore delay, the capacitances that lie between the switching transistor and the supply rail are assumed to be at the voltage level of the supply rail at the time of the switching transition and do not contribute to the Elmore delay. For the example in Fig. 49.7, the capacitance at node n1 is ignored while computing the Elmore delay, the expression for which is

(R1 + R2 )C2 + (R1 + R2 + R3 )C3

(49.31)

Each Ri is inversely proportional to the corresponding transistor size, xi, and each Ci is some constant (for wire capacitance) plus a term proportional to the width of each transistor whose gate, drain, or source is connected to node i. Thus, Eq. (49.31) can be written as

( A x1 + A x 2 )(Bx 2 + Cx3 + D) + ( A x1 + A x 2 + A x3 )(Bx3 + E ) which is a posynomial function (see Section 49.2) of x1, x2, and x3. Circuit Level Model At the circuit level, the PERT technique, which will be described shortly, is used to find the circuit delay. The procedure is best illustrated by means of a simple example. Consider the circuit in Fig. 49.8, where each box represents a gate and the number within the box represents its delay. We assume that the worstcase arrival time for a transition at any primary input, i.e., at the inputs to boxes A, B, C, and D, is 0. A component is said to be ready for processing when the signal arrival time information is available for all of its inputs. Initially, since signal arrival times are known only at the primary inputs, only those components that are fed solely by primary inputs are ready for processing. These are placed in a queue and are scheduled for processing. In the iterative process, the component at the head of the queue is scheduled for processing. Each processing step consists of

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A 1

1

B 3

3

C 1 D 2

E 1 1 2

G 2

6

4

F 1

5

H 3

9

FIGURE 49.8 The PERT technique.

• Finding the latest arriving input to the component, which triggers the output transition. This involves finding the maximum of all worst-case arrival times of inputs of the component. • Adding the delay of the component to the latest arriving input time to obtain the worst-case transition time at the output. • Checking all of the components that the current component fans out to, to find out whether they are ready for processing. If so, the component is added to the tail of the queue. The iterations end when the queue is empty. In the example, the algorithm is executed as follows: STEP 1. Initially, Queue = {A, B, C, D}. STEP 2. Schedule A; DelayA = 0 + 1 = 1. Queue = {B, C, D}. STEP 3. Schedule B; DelayB = 0 + 3 = 3. Queue = {C, D}. STEP 4. Schedule C; DelayC = 0 + 1 = 1. Queue = {D, E}. (E is added to the queue). STEP 5. Schedule D; DelayD = (0 + 2) = 2. Queue = {E}. STEP 6. Schedule E; DelayE = (max(3, 1) + 1) = 4. Queue = {F, G}. STEP 7. Schedule F; DelayF = (max(4, 2) + 1) = 6. Queue = {G}. STEP 8. Schedule G; DelayG = (max(4, 1) + 2) = 6. Queue = {H}. STEP 9. Schedule H; DelayH = (max(6, 5) + 3) = 9. Queue = {}. The algorithm terminates. The worst-case delays at the output of each component are shown in Fig. 49.8. The critical path, defined as the path between an input and an output with the maximum delay, can now easily be found by successively tracing back, beginning from the primary output with the latest transition time, and walking back along the arriving fan-in of the current gate, until a primary input is reached. In the example, the critical path from the input to the output is B-E-G-H. In the case of CMOS circuits, the rise and fall delay transitions are calculated separately. For inverting CMOS gates, the latest arriving input rise (fall) transition triggers a fall (rise) transition at the output. This can easily be incorporated into the PERT method described above, by maintaining two numbers, tr and tf , for each gate, corresponding to the worst-case rise (high transition) and fall (low transition) delays from a primary input. To obtain the value of tf at an output, the largest value of tr at an input node is added to the worst-case fall transition time of the component; the computation of tr is analogous. For noninverting gates, tr and tf are obtained by adding the rise (fall) transition time to the worst-case input rise (fall) transition time.

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Since each gate delay is a posynomial, the circuit delay found by the PERT technique is a sum of gate delays, the circuit delay is also a posynomial function of the transistor sizes. In general, the path delay can be written as n

∑ i , j =1

aij

xi + xj

n

∑x +K bi

i=1

(49.32)

i

The Area Model The exact area of a circuit cannot easily be represented as a function of transistor sizes. This is unfortunate, since a closed functional form facilitates the application of optimization techniques. As an approximation, the following formula is used by many transistor-sizing algorithms, to estimate the active circuit area. n

Area =

∑x

i

(49.33)

i=1

where xi is the size of the i th transistor and n is the number of transistors in the circuit. In other words, the area is approximated as the sum of the sizes of transistors in the circuit, which, from the definition Eq. (49.8), is clearly a posynomial function of the xi’s.

The Sensitivity-Based TILOS Algorithm Steps in the Algorithm The algorithm that was implemented in TILOS was the first to recognize the fact that the area and delay can be represented as posynomial functions of the transistor sizes. The algorithm proceeds as follows: An initial solution is assumed where all transistors are at the minimum allowable size. In each iteration, a static timing analysis is performed on the circuit, as explained earlier, to determine the critical path for the circuit. Let N be the primary output node on the critical path. The algorithm then walks backward along the critical path, starting from N. Whenever an output node of a gate, Gatei , is visited, TILOS examines the largest resistive path between VDD (ground) and the output node if Gatei’s tr (tf ) causes the timing failure at N. This includes: • The critical transistor, i.e., the transistor whose gate terminal is on the critical path. In Fig. 49.7, X2 is the critical transistor. • The supporting transistors, i.e., transistors along the largest resistive path from the critical transistor to the power supply (VDD or ground). In Fig. 49.7, X1 is a supporting transistor. • The blocking transistors, i.e., transistors along the highest resistance path from the critical tran­ sistor to the logic gate output. In Figure 49.7, X3 is a blocking transistor. TILOS finds the sensitivity, which is the reduction in circuit delay per increment of transistor size, for each critical, blocking, and supporting transistor. (The procedure of sensitivity computation is treated in greater detail shortly.) The size of the transistor with the greatest sensitivity is increased by multiplying it by a constant, BUMPSIZE, a user-settable parameter that defaults to 1.5. The preceding process is repeated until all constraints are met, implying that a solution is found, or the minimum delay state has been passed, and any increase in transistor sizes would make it slower instead of faster, in which case TILOS cannot find a solution. Note that, because in each iteration exactly one transistor size is changed, the timing analysis method can employ incremental simulation techniques to update delay information from the previous iteration. This substantially reduces the amount of time spent in critical path detection.

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R

C

“1”

FIGURE 49.9 Sensitivity calculations in TILOS.

Sensitivity Computation Figure 49.9 illustrates a configuration in which the critical path extends back along the gate of the upper transistor, which is the critical transistor. The sensitivity for this transistor is calculated as follows: set all transistor sizes, except x, to the size of the critical transistor. R is the total resistance of an RC chain driving the gate and C is the total capacitance of an RC chain being driven by the configuration. The total delay, D(x), of the critical path is D( x ) = K + RCu x +

RuC x

(49.34)

where Ru and Cu are the resistance and capacitance of a unit-sized transistor, K is a constant that depends on the resistance of the bottom transistor, the capacitance in the driving RC chain and the resistance in the driven RC chain. The sensitivity, D′(x), is then D′( x ) = RCu −

RuC x2

(49.35)

The sensitivities of supporting transistors and blocking transistors can similarly be calculated. Note that increasing the size of a transistor with negative sensitivity only means that the delay along the current critical path can be reduced by changing the size of this transistor, and does not necessarily mean that the circuit delay can be reduced; the circuit delay is the maximum of all path delays in the circuit, and a change in the size of this transistor could increase the delay along some other path, making a new path critical. This is the rationale behind increasing the size of the most sensitive transistor by only a small factor. From an optimization viewpoint, the procedure of bumping up the size of the most sensitive transistor could be looked upon in the following way. Let the ith transistor (out of n transistors) be the one with the maximum sensitivity. Define ei ∈ Rn as (ei)j = 0 is i ≠ j and (ei)j = 1 if i = j. In each iteration, the TILOS optimization procedure works in the n-dimensional space of the transistor sizes, chooses ei as the search direction, and attempts to find the solution to the problem by taking a small step along the direction.

Transistor Sizing Using the Method of Feasible Directions Shyu et al. [12] proposed a two-stage optimization approach to solve the transistor sizing problem. The delay estimation algorithm is identical to that used in TILOS. The algorithm can be summarized in the following pseudo-code: Use TILOS to size the entire circuit;

While (TRUE) {

Select G1, …, Gk, the k most critical paths,

and X = {xi}, the set of design parameters

Solve the optimization problem

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minimize

∑

such that

Gi ( X ) ≤ T ∀i = 1, …, k

and

xi ∈X

xi

x i ≥ minsize ∀ x i ∈ X

If all constraints are satisfied, exit }

In the first stage, the TILOS heuristic is used to generate an initial solution. The heuristic finds a solution that satisfies the constraints, and only the sized-up transistors are used as design parameters. Although TILOS is not guaranteed to find an optimal solution, it can serve as an initial guess solution for an iterative technique. In the second stage of the optimization process, the problem is converted into a mathematical opti­ mization problem, and is solved by a Method of Feasible Directions (MFD) algorithm described in Section 49.2 using the feasible solution generated in the first stage as an initial guess. To reduce the computation, a sequence of problems with a smaller number of design parameters is solved. At first, the transistors on the worst-delay paths (usually more than one) are selected as design parameters. If, with the selected transistors, the optimizer fails to meet the delay constraints, and some new paths become the worst-delay paths, the algorithm augments the design parameters with the tran­ sistors on those paths, and restarts the process. However, while this procedure reduces the run time of the algorithm, one faces the risk of finding a suboptimal solution since only a subset is the design parameters is used in each step. The MFD optimization method proceeds by finding a search direction d, a vector in the n-dimensional space of the design parameters, based on the gradients of the cost function and some of the constraint functions. Once the search direction has been computed, a step along this direction is taken, so that the decrease in the cost and constraint functions is large enough. The computation stops when the length of this step is sufficiently small. This algorithm has the feature that once the feasible region (the set of transistor sizes where all delay constraints are satisfied) is entered, all subsequent improvements will remain feasible, and the algorithm can be terminated at any time with a feasible solution. Practical Implementation Aspects The Generalized Gradient For convergence, the MFD requires that the objective and constraint functions be continuously differentiable. However, since the circuit delay is defined as the maximum of all path delays, the delay constraint functions are usually not differentiable. To illustrate that the maximum of two continuously differentiable functions, g1(x) and g2(x), need not be differentiable, consider the example in Fig. 49.10. The maximum function, shown by the bold lines, is nondifferentiable at x0. g1(x)

g2(x)

x0

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FIGURE 49.10 Nondifferentiability of the max function.

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To cope with the nondifferentiability of the constraint functions, a modification of the MFD is used, which employs the concept of the generalized gradient. The idea is to use a convex combination of the gradients of the active, or nearly active constraints near a discontinuity. Scaling It is important to scale the gradients of the cost and path delay functions since the use of their unscaled values may produce poor descent search directions due to the large difference in magnitude of the gradients of the constraint and objective functions. When a gradient has a magnitude that is much smaller than other gradients, it dominates the search direction. In such a case, the descent direction is unjustly biased away from the other constraints and/or the cost function.

Lagrangian Multiplier Approaches As can be seen from the approaches studied so far, the problem of transistor sizing can be formulated as a constrained nonlinear programming problem. Hence, the method of Lagrangian multipliers, described in Section 49.2 is applicable. Early approaches that used Lagrangian multipliers rely on the user to provide critical path information, which may be impractical since critical paths are liable to change as sizing progresses. An alternative solution to transistor size optimization using Lagrangian multipliers was presented by Marple and El Gamal [13]. This technique uses a different area model and employs the idea of introducing intermediate variables to reduce the number of delay constraints from an exponential number to a number that is linear in the circuit size. This technique begins with a prespecified layout, and performs the optimization using an area model for that layout. While such an approach has the disadvantage that it may not result in the minimal area over all layouts, it still maintains the feature that the area and delay constraints are posynomials. Apart from the delay constraints, there also exist some area constraints, modeled by constraint graphs that are commonly used in layout compaction. These constraints maintain the minimum spacing between objects in the final layout, as specified by design rules. The delay of the circuit is modeled by a delay graph, D(V, E) where V is the set of nodes (gates) in D, and E is the set of arcs (connections among gates) in D. This is the same graph on which the PERT analysis is to be carried out. Let mi represent the worst-case delay at the output of gate i, from the primary inputs. Then, for each gate, the delay constraint is expressed as mi + d j ≤ m j

(49.36)

where gate i∈fan-in(gate j), and dj is the delay of gate j. Thus, the number of delay constraints is reduced from a number that could, in the worst case, be exponential in V, to one that is linear in E using V additional variables.

Two-Step Optimization Since the number of variables in the transistor-sizing problem, which equals the number of transistors in a combinational segment, is typically too large for most optimization algorithms to handle efficiently, many algorithms choose a simpler route by performing the optimization in two steps. Examples of algorithms that use this idea to solve the transistor-sizing problem are iCOACH, MOSIZ, and CATS. In the first step in MOSIZ, each gate is mapped onto an equivalent macromodeling primitive, such as an inverter. The transistor-sizing problem on this simplified circuit is then solved. Note that the number of variables is substantially reduced when each gate is replaced by a simple primitive, with fewer tran­ sistors. The delay of each equivalent inverter, with the transistor sizes obtained previously, is taken as the timing budget for the gate represented by that inverter, and the gate is optimized under the timing budget. iCOACH uses macromodels for timing analysis of the circuit, and has the capability of handling dynamic circuits. The optimizer employs a heuristic to estimate an improvement factor for each gate, which is related to the sensitivity of the gate. The improvement factor depends on the fan-in count, fanout count, and the worst-case resistive path to the relevant supply rail. The improvement factor is then © 2003 by CRC Press LLC

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used to allocate a timing budget to each gate. In the second step, for each gate, a smaller transistor-sizing problem is solved, in which the area-delay product of the gate is minimized, subject to its delay being within it timing budget. The number of variables for each such problem equals the number of transistors within the gate, which is typically a small number. The optimization method used here is Rosenbrock’s rotating coordinate scheme [5]. The two steps are repeated iteratively until the solution converges. While this technique has the obvious advantage of reducing the number of design parameters to be optimized, it suffers from the disadvantage that the solution may be nonoptimal. This stems from the simplifications introduced by the timing budget allocation; the timing budget allocated to each gate may not be the same as the delay of the gate for the optimal solution.

The Convex Programming-Based Approach The chief shortcoming of most of the approaches above is that the simplifying assumptions that are made to make the optimization problem more tractable may lead to a suboptimal solution. The algorithm in iCONTRAST solves the underlying optimization problem exactly. The objective of the algorithm is to solve the transistor-sizing problem in Eq. (49.28), where both the area and the delay are posynomial functions of the vector x of transistor sizes. The procedure described below may easily be extended to solve the formulations in Eqs. (49.29) and (49.30) as well; however, these formulations are not as useful to the designer. The variable transformation, (xi) = (e zi) maps the problem in (49.28) to minimize

Area( z ) =

n

∑e

zi

i =1

subject to

(49.37)

D( z ) ≤ Tspec

The delay of a circuit is defined to be the maximum of the delays of all paths in the circuit. Hence, it can be formulated as the maximum of posynomial functions of x. This is mapped by the above transformation onto a function D(z) that is a maximum of convex functions; a maximum of convex functions is also a convex function. The area function is also a posynomial in x, and is transformed into a convex function by the same mapping. Therefore, the optimization problem defined in (49.28) is mapped to a convex programming problem, i.e., a problem of minimizing a convex function over a convex constraint set. Due to the unimodel property of convex functions over convex sets, any local minimum of (49.28) is also a global minimum. Vaidya’s convex programming method described in Section 49.2 is then used to find the unique global minimum of the optimization problem. Gradient Calculations In an iteration of Vaidya’s convex programming algorithm, when the center zc of a polytope lies within the feasible region S, the gradient of the area function is required to generate the new hyperplane passing through the center. The gradient of the area function (Eq. (49.37)) is given by

[

∇Area(z ) = e z1 , e z2 , …, e zn

]

(49.38)

In the case when the center zc lies outside the feasible region S, the gradient of the critical path delay function Dcritpath (zc) is required to generate the new hyperplane that is to be added. Note that transistors in the circuit can contribute to the kth component of the gradient of the delay function in either of two ways: 1. If the kth transistor is a critical, supporting, or blocking transistor (as defined in Section 49.3) 2. If the kth transistor is a capacitive load for some critical transistor Transistors that satisfy neither of these requirements make no contribution to the gradient of the delay function. © 2003 by CRC Press LLC

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Concluding Remarks The list of algorithms presented above is among the prominent ones used for transistor sizing. For more information, the reader is referred to [6] and sources such as the International Conference on ComputerAided Design, the Design Automation Conference, and the IEEE Transactions on Computer-Aided Design. The TILOS algorithm is found to be fast and give near-optimal solutions under loose timing con­ straints. As the timing constraints become tight, the heuristic becomes less optimal, and more rigorous methods must be used. The MFD algorithm, which was compared directly with TILOS, was found to give small (up to 5%) improvements over TILOS. The convex programming-based algorithm, iCONTRAST, solves the underlying convex programming problem exactly, and finds the optimal solution. However, the run times of iCONTRAST are not as small as those of TILOS. No comparative data for other algorithms described herein have been presented in the literature. The reader must be cautioned here that the actual optimization problem in transistor sizing is not exactly a posynomial programming problem. The use of Elmore delay models (which are accurate within about 20%) to approximate the circuit delay, and the use of approximate area models allows the problem to be formulated as a convex program, and hence although one may solve this optimization problem exactly, one still has to live with the inaccuracies of the modeling functions. In practice, in most cases, this is not a serious problem.

49.4 The Design Centering Problem Problem Description While manufacturing a circuit, it is inevitable that process variations will cause design parameters, such as component values, to waver from their nominal values. As a result, the manufactured circuit may no longer meet some behavioral specifications, such as requirements on the delay, gain and bandwidth, that is has been designed to satisfy. The procedure of design centering attempts to select the nominal values of design parameters so as to ensure that the behavior of the circuit remains within specifications, with the greatest probability. In other words, the aim of design centering is to ensure that the manufacturing yield is maximized. The values of n design parameters may be ordered as an n-tuple that represents a point in Rn. A point is feasible if the corresponding values for the design parameters satisfy the behavioral specifications on the circuit. The feasible region (or the region of acceptability), Rf ⊂ Rn is defined as the set of all design points for which the circuit satisfies all behavioral specifications. The random variations in the values of the design parameters are modeled by a probability density function, Φ(z): Rn → [0, 1], with a mean corresponding to the nominal value of the design parameters. The yield of the circuit, Y, as a function of the means, x, is given by Y( x ) =

∫ Φ (z )dz x

(49.39)

Rf

The design center is the point x at which the yield, Y(x), is maximized. There have traditionally been two approaches to solving this problem: one based on geometrical methods, and another based on statistical sampling. In addition, several methods that hybridize these approaches also exist. We will now provide an exposition of geometrical approaches to the optimization problem of design centering, and leave the discussion of other techniques of Chapter 50. A common assumption made by geometrical design centering algorithms is that Rf is a convex bounded body. Geometrical algorithms recognize that the evaluation of the integral (49.39) is computationally difficult, and generally proceed as follows: the feasible region in the space of design parameters, i.e., the region where the behavioral specifications are satisfied, is approximated by a known geometrical body, such is polytope or an ellipsoid. The center of this body is then approximated, and is taken to be the design center.

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The Simplicial Approximation Method Outline of the Method The simplicial approximation method is a method for approximating a feasible region by a polytope and finding its center. This method proceed in the following steps: 1. Determine a set of m ≥ n + 1 points on the boundary of Rf . 2. Find the convex hull (see Section 49.2) of these points and use this polyhedron as the initial approximation to Rf. In the two-dimensional example in Fig. 49.11(a), the points 1, 2, and 3 are chosen in Step (1), and their convex hull is the triangle with the vertices 1, 2, and 3. Set k = 0. 3. Inscribe the largest n -dimensional hypersphere in this approximating polyhedron and take its center as the first estimate of the design center. This process involves the solution of a linear program. In Fig. 49.11(a), this is the hypersphere C 0. 4. Find the midpoint of the largest face of the polyhedron, i.e., the face in which the largest (n – 1)­ dimensional hypersphere can be inscribed. In Fig. 49.11(a), the largest face is 2-3, the face in which the large (n – 1)-dimensional hypersphere can be inscribed. 5. Find a new boundary point on Rf by searching along the outward normal of the largest face found in Step (4) extending from the midpoint of this face. This is carried out by performing a line search. In Fig. 49.11(a), point 4 is thus identified. 6. Inflate the polyhedron by forming the convex hull of all previous points, plus the new point generated in Step (5). This corresponds to the quadrilateral 1, 2, 3, 4 in Fig. 49.11(a). 7. Find the center of the largest hypersphere inscribed in the new polyhedron found in step (6). This involves the solution of a linear program. Set k = k + 1, and go to Step (4). In Fig. 49.11(a), this is the circle C 1. Further iterations are shown in Fig. 49.11(b). The process is terminated when the sequences of radii of the inscribed hypersphere converges. Inscribing the Largest Hypersphere in a Polytope Given a polytope specified by Eq. (49.3), if the ai’s are chosen to be unit vectors, then the distance of a point x from each hyperplane of the polytope is given r = aTi x – bi . The center x and radius r of the largest hypersphere that can be inscribed within the polytope  are then given by the solution of the following linear program: minimize r (49.40)

subject to aiT x − r ≥ bi

4

2

4

6

2 c3 c0

c1

c0

1

c1

c2

c4

1 3

5

3 7

FIGURE 49.11 The simplicial approximation method.

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Cut aTx = b

New ellipsoid

Current ellipsoid

Feasible Region

FIGURE 49.12 The ellipsoidal method.

Since the number of unknowns of this linear program is typically less than the number of constraints, it is more desirable to solve its dual [1]. A similar technique can be used to inscribe the largest hypersphere in a face of the polytope. This method has also been generalized for the inscription of maximal norm bodies, to handle joint probability density functions with (nearly) convex level contours. Elongated Feasible Regions If the design centering procedure outlined earlier is applied to a rectangular feasible region, the best possible result may not be obtained by inscribing a hypersphere. For elongated feasible regions, it is more appropriate to determine the design center by inscribing an ellipsoid rather than a hypersphere. Simplicial approximation handles this problem by scaling the axes so that the lower and upper bounds for each parameter differ by the same magnitude and one may inscribe the largest ellipsoid by inscribing the largest hypersphere in a transformed polytope. This procedure succeeds in factoring in reasonably the fact that feasible regions may be elongated; however, it considers only a limited set of ellipsoids, which have their axes aligned with the coordinate axis, as candidates for inscription within the polytope.

The Ellipsoidal Method This method is based on principles similar to those used by the Shor-Khachiyan ellipsoidal algorithm for linear programming. This algorithm attempts to approximate the feasible region by an ellipsoid, and takes the center of the approximating ellipsoid as the design center. It proceeds by generating a sequence of ellipsoids, each smaller than the last, until the procedure converges. Similar to other methods, this procedure assumes that an initial feasible point is provided by the designer. The steps involved in the procedure are as follows (see also Fig. 49.12): 1. Begin with an ellipsoid, E0, that is large enough to contain the desired solution. Set j = 0. 2. From the center of the current ellipsoid, choose a search direction and perform a binary search to identify a boundary point along that direction. One convenient set of search directions is the parameter direction, searching along the ith, i = 1, 2, …, n in a cycle, and repeating the cycle, © 2003 by CRC Press LLC

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provided the current ellipsoid center is feasible. If not, a linear search is conducted along a line from the current center to the given feasible point. 3. A supporting hyperplane [1] at the boundary point can be used to generate a smaller ellipsoid, Ej+1, that is guaranteed to contain the feasible region Rf , if Rf is convex. The equation of Ej+1 is provided by an update procedure. 4. Increment j, and go to Step (1) unless the convergence criterion is met. The convergence criterion is triggered when the volume is reduced by less a given factor, ∈. Upon convergence, the center of the ellipsoid is taken to be the design center.

Convexity-Based Approaches Introduction Here, the feasible region is first approximated by a polytope in the first phase. Next, two geometrical approaches to find the design center are proposed. In the first, the properties of polytopes are utilized to inscribe the largest ellipsoid within the approximating polytope. The second method proceeds by formulating the design centering problem as a convex programming problem, assuming that the varia­ tions in the design parameters are modeled by Gaussian probability distributions and use Vaidya’s convex programming algorithm described in Section 49.2 to find the solution. Feasible Region Approximation The feasible region, Rf ⊂ Rn, is approximately by a polytope given by Eq. (49.3) in this step. The algorithm begins with an initial feasible point, z 0 ∈R f . An n-dimensional box, namely, {z ∈Rn  zmin ≤ zi ≤ zmax}, containing Rf is chosen as the initial polytope 0. In each iteration, n orthogonal search directions, d1, d2, … dn are chosen (possible search directions include the n coordinate direction). A binary search is conducted from z0 to identify a boundary point zbi of Rf , for each direction di . If zbi is relatively deep in the interior of , then the tangent plane to Rf at zbi is added to the set of constraining hyperplanes in Eq. (49.3). A similar procedure is carried out along the direction –di . Once all of the hyperplanes have been generated, the approximate center of the new polytope is calculated. Then z0 is reset to be this center, and the preceding process is repeated. Therefore, unlike the simplicial approximation which tries to expand the polytope outward, this method starts with a large polytope and attempts to add constraints to shrink it inward, The result of polytope approximation on an ellipsoidal feasible region is illustrated in Fig. 49.13. Algorithm I: Inscribing the Largest Hessian Ellipsoid For a polytope given by Eq. (49.3), the log-barrier function is defined as F (z ) = −

m

∑ log (a z − b ) e

T i

(49.41)

i

i=1

The Hessian ellipsoid centered at a point x in the polytope , is defined as the ellipsoid E(x, (x), 1) (see Eq. (49.2)), where (xc) is the Hessian [1] of the log-barrier function above, and is given by ( z ) = ∇ 2 F ( z ) =

m

a i a Ti

∑ (a z − b ) i=1

T i

2

(49.42)

i

This is known to be a good approximation to the polytope locally around x. Hence, the goal is to find the largest ellipsoid in the class E(x, (x), r) that can inscribed in the polytope, and its center xc. The point xc will be taken to be the computed design center. An iterative process is used to find this ellipsoid. In each iteration, the Hessian at the current point xk is calculated, and the largest ellipsoid E(x, (xk ), r) is inscribed in the polytope. The inscription of this ellipsoid is © 2003 by CRC Press LLC

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5 4.8 4.6 4.4 4.2 4 3.8 3.6 3.4 3.2 3 3

3.2

3.4

3.6

3.8

4

4.2

4.4

4.6

4.8

5

FIGURE 49.13 Polytope approximation for the convexity-based methods.

equivalent to inscribing a hypersphere in a transformed polytope. The process of inscribing a hypersphere in a polytope is explained in this section. Algorithm II: The Convex Programming Approach When the probability density functions that represent variations in the design parameters are Gaussian in nature, the design centering problem can be posed as a convex programming problem. The joint Gaussian probability density function of n independent random variables z = (z1, …, zn), with means x = (x1, …, xn) and variance σ = (σ1, …, σn) is given by Φ x (z ) =

 i=n (z − x )2   – i 2i  exp 2σ i   i=0 (2π)n 2 σ1σ 2 …σn  

∑

1

(49.43)

This is known to be a log-concave function of x and z. Also, note that the arbitrary covariance matrices can be handled, since a symmetric matrix may be converted into a diagonal form by a simple linear (orthogonal) transformation. The design centering problem is now formulated as maximize Y( x ) = such that

∫



Φ x (z )dz

(49.44)

x ∈

where  is the polytope approximation to the feasible region Rf . It is a known fact that the integral of log-concave function over convex region is also a log-concave function. Thus, the yield function Y(x) is log-concave, and the above problem reduces to a problem of maximizing a log-concave function over a convex set. Hence, this can be transformed into a convex programming problem. The convex program­ ming algorithm in Section 49.2 is then applied to solve the optimization problem.

Concluding Remarks The preceding list of algorithms is by no means exhaustive, but provides a general flavor for how optimization methods are used in geometrical design centering. The reader is referred to [7–10] and to © 2003 by CRC Press LLC

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1323

Chapter 50 for further information about statistical design. In conclusion, it is appropriate to list a few drawbacks associated with geometrical methods: Limitations of the Approximating Bodies. In the case of ellipsoidal approximation, certain convex bodies cannot be approximated accurately, because of ellipsoid is symmetrical about any hyperplane passing through its center, and is inherently incapable of producing a good approximation to a body that has a less symmetric structure. A polytope can provide a better approximation to a convex body than an ellipsoidal since any convex body can be thought of as a polytope with an infinite number of faces. However, unlike the ellipsoidal case, calculating the exact center of a polytope is computationally difficult and one must resort to approximations. Statistical Effects Are Ignored. Methods such as simplicial approximation, ellipsoidal approximation and Algorithm I of the convexity-based methods essentially approximate the feasible region by means of an ellipsoid, and take the center of that ellipsoid to be the design center, regardless of the probability distributions that define variations in the design parameters. However, the design center could be highly dependent on the exact probability distributions of the variables, and would change according to these distributions. Nonconvexities. Real feasible regions are seldom convex. While in many cases, they are “nearly convex,” there are documented cases where the feasible region is not very well-behaved. In a large number of cases of good designs, since the joint probability density function of the statistical variables decays quite rapidly from the design center, a convex approximation does not adversely affect the result. However, if the normal design has a very poor yield, a convex approximation will prove to be inadequate. The Curse of Dimensionality. Geometrical methods suffer from the so-called “curse of dimensionality,” whereby the computational complexity of the algorithm increases greatly with the number of variables. However, as noted in [11], for circuit books within a die, performance variations in digital MOS circuits depend only on four independent statistical variables. Moreover, for this class of circuits, the circuit performance can be modeled with reasonable accuracy by linear functions. For such circuits, the deter­ ministic (i.e., nonstatistical) algorithm [11] is of manageable complexity.

References [1] D. G. Luenberger, Linear and Nonlinear Programming, 2nd ed., Reading MA: Addison-Wesley, 1984. [2] R. K. Brayton, G.D. Hachtel, and A. L. Sangiovanni-Vincentelli, “A survey of optimization tech­ niques for integrated-circuit design,” Proc. IEEE, vol 69, pp. 1334–1362, Oct. 1981. [3] S. S. Sapatnekar, V. B. Rao, P. M. Vaidya, and S. M. Kang, “An exact solution to the transistor sizing problem for CMOS circuits using convex optimization,” IEEE Trans. on Computer-Aided Design, vol. 12, pp. 1621–1634, Nov. 1993. [4] J. Rubenstein, P. Penfield, and M. A. Horowitz, “Signal delay in RC tree networks,” IEEE Trans. on Computer-Aided Design, vol. CAD-2, pp. 202–211, July 1983. [5] H. H. Rosenbrock, “An automatic method for finding the greatest or least value of a function,” Computer Journal, vol. 3, pp 175–184, Oct. 1960. [6] S. S. Sapatnekar and S. M. Kang, Design Automation for Timing-Driven Layout Synthesis. Boston, MA: Kluwer Academic Publishers, 1993. [7] S. W. Director, P. Feldmann, and K. Krishna, “Statistical integrated circuit design,” IEEE Journal of Solid-State Circuits, vol. 28, pp. 193–202, March 1993. [8] M. D. Meehan and J. Purviance, Yield and Reliability in Microwave Circuit and System Design, Boston, MA: Artech House, 1993. [9] S. W. Director, W. Maly, and A. J. Strojwas, VLSI Design of Manufacturing: Yield Enhancement, Boston, MA: Kluwer Academic Publishers, 1990. © 2003 by CRC Press LLC

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[10] R. Spence and R. S. Soin, Tolerance Design of Integrated Circuits, Reading MA: Addison-Wesley, 1988. [11] D. E. Hocevar, P. F. Cox, and P. Yang “Parametric yield optimization for MOS circuit blocks,” IEEE Trans. on Computer-Aided Design, vol. 7, pp. 645–658, June 1988. [12] J. M. Shyu, A. Sangiovanni-Vincentelli, J. P. Fishburn and A. E. Dunlop, “Optimization-Based Transistor Sizing,” IEEE J. Solid-State Circuits, vol. 23, pp. 400–409, April 1988. [13] D. Marple and A. El Gamal,“Optimal Selection of Transistor Sizes in Digital VLSI Circuits,” Stanford Conference on VLSI, pp. 151–172, 1987.

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50 Statistical Design Optimization 50.1 Introduction 50.2 Problems and Methodologies of Statistical Circuit Design 50.3 Underlying Concepts and Techniques Circuit Variables, Parameters, and Performances • Statistical Modeling of Circuit (Simulator) Variables • Acceptability Regions • Methods of Acceptability Region Approximation • Manufacturing (Parametric) Yield

50.4 Statistical Methods of Yield Optimization

Maciej A. Styblinski Texas A&M University

Large-Sample vs. Small-Sample Methods • Methods Using Standard Deterministic Optimization Algorithms • LargeSample Heuristic Methods for Discrete Circuits • LargeSample, Derivative-Based Methods for Discrete Circuits • A Large-Sample, Derivative-Based Method for Integrated Circuits • Small-Sample Stochastic Approximation-Based Methods • Small-Sample Stochastic Approximation Methods for Integrated Circuits • Case Study: Process Optimization for Manufacturing Yield Enhancement • Generalized Formulation of Yield, Variability, and Taguchi Circuit Optimization Problems

50.5 Conclusion

50.1 Introduction Manufacturing process variations and environmental effects (such as temperature) result in the variations of the values of circuit elements and parameters. Statistical methods of circuit design optimization take those variations into account and apply statistical (or statistical/deterministic) optimization techniques to obtain an “optimal” design. Statistical design optimization belongs to a general area of statistical circuit design.

50.2 Problems and Methodologies of Statistical Circuit Design A broad class of problems exists in this area: statistical analysis involves studying the effects of element variations on circuit performance. It applies statistical techniques, such as Monte Carlo simulation [34] and the variance propagation method [39], to estimate variability of performances. Design centering attempts to find a center of the acceptability region [12] such that manufacturing yield is maximized. Direct methods of yield optimization use yield as the objective function and utilize various statistical (or mixed statistical/deterministic) algorithms to find the yield maximum in the space of designable

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circuit/process parameters. Design centering and tolerance assignment (used mostly for discrete circuits) attempt to find the design center, with simultaneous optimal assignment of circuit element tolerances, minimizing some suitable cost function and providing 100% yield (worst-case design) [4,6]. To solve this problem, mostly deterministic algorithms of nonlinear programming are used. Worst-case design is often too pessimistic and too conservative, leading to substantial overdesign. This fact motivates the use of statistical techniques, which provide a much more realistic estimation of the actual performance variations and lead to superior designs. Stringent requirements of the contemporary very large scale integration (VLSI) design prompted a renewed interest in the practical application of these techniques. The most significant philosophy introduced recently in this area is statistical Design for Quality (DFQ). It was stimulated by the practical appeal of the DFQ methodologies introduced by Taguchi [30], oriented toward “on-target” design with performance variability minimization. In what follows, mostly the techniques of manufacturing yield optimization and their design for quality generalization are discussed.

50.3 Underlying Concepts and Techniques Circuit Variables, Parameters, and Performances Designable Parameters Designable parameters, represented by the n-dimensional vector1 x = (x1, …, xn), are used by circuit designers as “decision” variables during circuit design and optimization. Typical examples are nominal values of passive elements, nominal MOS transistor mask dimensions, process control parameters, etc. Random Variables The t-dimensional vector of random variables (or “noise” parameters in Taguchi’s terminology [30]) is denoted as θ = (θ1, …, θt ). It represents statistical R, L, C element variations, disturbances or variations of manufacturing process parameters, variations of device model parameters such as tox (oxide thickness), VTH (threshold voltage), and environmental effects such as temperature, supply voltage, etc. Usually, θ represents principal random variables, selected to be statistically independent and such that all other random parameters can be related to them through some statistical models. Probability function (p.d.f.) of θ parameters will be denoted as fθ (θ). Circuit (Simulator) Variables These variables represent parameters and variables used in circuit, process, or system simulators such as SPICE. They are represented as the c-dimensional vector e = (e1, …, ec). Specific examples of e variables are: R, L, C elements, gate widths Wj and lengths Lj of MOS transistors, device model parameters, or, if a process simulator is used, process-related control, and physical and random parameters available to the user. The e vector contains only those variables that are directly related to the x and θ vectors.2 This relationship is, in general, expressed as e = e ( x ,θ)

(50.1)

The p.d.f. of θ is transformed into fe(e) the p.d.f. of e. This p.d.f. can be singular, i.e., defined in a certain subspace of the e-space (see examples below). Moreover, it can be very complicated, with highly nonlinear statistical dependencies between different parameters, so it is very difficult to represent it directly as a p.d.f. of e. In the majority of cases, the analytic form of fe (e) is not known. For that reason, techniques of statistical modeling are used (see the next section).

1 2

Vectors are denoted by lower case letters subscripts or superscripts. This means that, e.g., some SPICE parameters will always be fixed.

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±5% ±1%

p.d.f.

−3σ εR −10%

RO +3σ εR +10%

R

FIGURE 50.1 A typical probability density function (p.d.f.) of a discrete resistor before and after “binning.”

Circuit Performances The vector of circuit performance function (or simply performances) is defined as the m-dimensional vector y = ( y1, …, ym ). Its elements can be gain, bandwidth, slew rate, signal delay, and circuit response for a single frequency or time, etc. Each of the performances yj is a function of the vector of circuit elements e: yj = yj (e) = yj (e(x,θ)). These transformations are most often not directly known in analytical form and a circuit simulator (such as SPICE) must be used to find the values of yj’s corresponding to the given values of x and θ. The overall simulator time required for the determination of all the performances y can be substantial for large circuits. This is the major limiting factor for the practical application of statistical circuit design techniques. To circumvent this problem, new statistical macromodeling techniques are being introduced [31] (see example in last subsection of 50.4).

Statistical Modeling of Circuit (Simulator) Variables Statistical modeling is the process of finding a suitable transformation e = e(x,θ), such that given the distribution of θ, the distribution of e can be generated. The transformation e = e(x,θ) can be described by closed form analytical formulas or by a computer algorithm. For discrete active RLC circuits (e.g., such as a common emitter amplifier), vector e is composed of two parts: the first part contains the actual values of statistically perturbed RLC elements: i.e., ei = xi + θi for those elements. In this formula, θ represents absolute element spreads and its expected (average) value, E{θ} = 0 and xi is the nominal value of ei, often selected as the expected value of ei. This implies that the variance of ei , var{ei } = var{θi }; E{ei } = xi and the distribution of ei is the same as that of θi , with the expected value shifted by xi . Alternatively, if θi represents relative element spreads, ei = xi (1 + θi ), where E{θi} = 0. Therefore, E{ei} = xi; var {ei } = xi2 var{θi }, i.e., the standard deviations σei and σθi are related: σei = xi σθi , or σei /E{ei } = σei /xi = σθi . This means that with fixed σθi , the relative standard deviation of ei is constant, as it is often the case in practice, where standard deviations of RLC elements are described in percents of the element nominal values. Both forms of ei indicate that each ei is directly associated with its corresponding θi and xi , and that there is one-to-one mapping between ei and θi . These dependencies are important, since many of the yield optimization algorithms were developed assuming that ei = xi + θi . A typical p.d.f. for discrete elements is shown in Fig. 50.1, before “binning” into different categories (the whole curve) and after binning into ±1%, ±5%, and ±10% resistors (the shaded and white areas: e.g., the ±10% resistors will have the distribution characterized by the external shaded areas, with a ±5% “hole” in the middle). Usually, passive discrete elements are statistically independent3 as shown in Fig. 50.2. The cross-section shown is often called a level set, a norm body [12], or a tolerance body. It is defined as a set of element values for which the element p.d.f. is larger than a prescribed value. This value is selected such that the probability of the element values falling into the tolerance body is equal to e.g., 95%, (i.e., the tolerance body represents 95% of the entire element population). Alternatively, 3 But, for instance, if R (R ) is a loss resistance of an inductor L (capacitor C) then L and R (C and R ) are L C L C correlated.

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R2 Ro2 εR1

εR1

Rε-Approx. to the tolerance region

εR2 εR2 R1

Ro1

FIGURE 50.2 A level set (cross section) of a p.d.f. function for two discrete resistors after manufacturing.

R2 Mismatch

Tn Line of perfect tracking R1

(a)

BJT’s h21e = β (b)

FIGURE 50.3 Dependencies between passive IC elements and between device model parameters: (a) linear, between two resistors R1 and R2; (b) nonlinear, between the base transit time Tn and the current gain h21e = β for bipolar junction transistors.

the tolerance body can be represented as a (hyper-) box shown in the figure, with the sides equal to 2εi (2εRi in the figure), called the tolerance region and denoted by Rε. Figure 50.2 also shown that the dependence ei = xi + θi is equivalent in this case to Ri = RNOM, i + ∆Ri , where xi = RNOM,i ; θ = ∆Ri ). The second part of e is composed of the parameters representing active device (e.g., BJT, MOS) model parameters. They are usually strongly correlated within each device model (same applies to IC’s), but typically, no correlations occur between device model parameters of different devices. Each of the device model parameters ed is related through a specific model ed = ed (x , θ) to the vector θ parameters,4 representing principal random variables, which are themselves often some device model parameters (such as oxide thickness tox of MOS transistors), and/or are some dummy random variables. For example, in the BJT empirical statistical model introduced in [3], the base transient time Tn is modeled as follows:  b  ed = ed ( x d , θ1 , θ 2 ) = Tn (β, X r 5 ) =  a +  (1 + cX r 5 ) β 

(50.2)

i.e., it is the function of the current gain θ1 = β (the principal random variable, affecting the majority of the BJT model parameters) and θ2 = Xr5 (a dummy random variable, uniformly distributed in the interval [–1, 1] independent of β and having no physical meaning); a, b, c are empirically selected constants [see Fig. 50.3 (b)]. In the discrete circuit case, each designable parameter xi has a random variable θi added to it (i.e., x and θ in the same space in which the p.d.f. fe(e) = fθ(x + θ) is defined. For integrated circuits, the passive elements (R’s, C’s), active dimensions (such as W’s and L’s for MOS transistors), and other transistor model parameters are strongly correlated [see Fig. 50.3(a)]. Because of this, the distribution of θ parameters is limited to a certain subspace of the entire e-space, i.e., fe (e(x,0)) is singular, and the formula ei = xi + θi does not hold. As an example, consider a subset of all e parameters representing the gate lengths x1 = L1, x2 = L2 (designable parameters) of two MOS transistors T1, T2 and an independent designable parameter x3 ≡ Ibias , representing the transistor bias current. Assume also (as is frequently the case) that θ ≡ ∆L, the technological gate length reduction (a common random parameter) 4 Observe that these models are parametrized by x: e.g., the MOS transistor model parameters e will also depend i on the device length L and width W.

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e2 = L2 − ∆L

(e1, e2) subspace

x2 = L2

x3 = Ibias e3 = Ibias x1 = L1

e1 = L1 − ∆L

FIGURE 50.4 Singular distribution fe (e1, e2, e3) in 3-dimensional e-space, represented by the thick line in the (e1, e1)subspace (plane). This is due to the perfect matching of ∆L ≡ ∆L1 ≡ ∆L2 values.

changes the same way for T1 and T2, i.e., there is ideal matching of ∆L ≡ ∆L1 = ∆L2 ,5 i.e., e1 ≡ x1 + θ ≡ L1 – ∆L, e2 ≡ x2 + θ ≡ L2 – ∆L, e3 ≡ x3 ≡ Ibias. The only random variable in this model is ∆L, as shown in Fig. 50.4. The p.d.f. fe (e) is in this case defined only in the one-dimensional subspace of the e-space (i.e., all the realization of the vector e are located on the thick line in Fig. 50.4). The major consequence of this difference is that, in general, many yield optimization algorithms developed for discrete circuits (i.e., using the explicit assumption that (ei = ei + θi), cannot be used for IC design. Statistical modeling for IC’s is concerned with representing global variations and parameter mismatches6 occurring between different devices on the same chip. In the last example, mismatch can be modeled by two additional independent local mismatch variables εL1, εL2, representing small random local deviations of ∆L1 and ∆L2 from the ideal value ∆L, i.e., e1 ≡ x1 + θ + εi ≡ L1 – ∆L – εL1, e2 ≡ x2 + θ + εi ≡ L2 – ∆L – εL2 . With this model, ∆L represents a global or common factor, affecting both channel lengths, and εL1, εL2, represented specific (local) variations. The model just presented is a simple (simple, one-factor) case of the Factor Analysis (FA) [20] model of correlations between e1 and e2. In [8], FA analysis, together with Principal Component Analysis (PCA)7 and nonlinear regression were used for the determination of linear and nonlinear statistical models for CMOS transistor parameters. The following common factors F1, …, F8 were identified: tox (oxide thickness common to n- and p-type transistors) NSUB , NSUB,p (n- and p-type substrate doping), ∆Ln , ∆Lp (length reduction), ∆Wn , ∆Wp (width reduction — for narrow transistors only), and XJp (p-type junction depth). These variables were causing about 96% of the total variability of all parameters. All the other CMOS transistor model parameters were related to the F1, …, F8 factors through quadratic [or linear in simplified models] regression formulas. The resulting models were able to represent — with a high level of accuracy — the strong nonlinear statistical dependencies existing between some model parameters. The major theoretical and empirical findings in mismatch modeling are the device area (or length) and distance dependencies of the mismatch level (see [23], where references to other authors can be found). For example, the variance of the difference e1 – e2 between two MOS transistor model parameters e1, e2 is modeled as [3, 9] 5

Such a model is commonly used for digital IC’s [9], since it is of sufficient accuracy for digital applications. Element mismatches are very important for analog IC’s. 7Principal component analysis involving coordinate rotation and lead to uncorrelated principal components.

6

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var (e1 − e 2 ) =

ap 2W1L1

+

ap 2W2 L2

+ s p2d122

(50.3)

where W1, L1, W2, and L2 are widths and lengths of the two transistors, d12 is the distance between the transistor centers, and ap , sp , are empirical coefficients adjusted individually for each model parameter. Using this model together with PCA, and introducing other concepts, two quite sophisticated linear statistical models in the form ei = e(xi , θ, Wi , Li , d) were proposed in [23]. They include the transistor separation distance information, collected into the vector d in two different forms. The models, constructed from on-chip measured data, were used for practical yield optimization. θ parameters were divided into two groups: a group of correlated random variables responsible for the common part of each parameter variance and correlations between model parameters of each individual transistor, and the second group of local (mismatched related) random variables, responsible for mismatches between different transistors. Additional dependencies, related to transistor spacing and device area related coefficients, maintain proper mismatch dependencies.

Acceptability Regions The acceptability region Ay is defined as a region in the space of performance parameters y (y-space), for which all inequality and equality constraints imposed on y are fulfilled. In the majority of cases, Ay is a hyperbox, i.e., all the constraints are of the form: SjL ≤ yj ≤ S Lj ; j = 1, …, m, where SjL, SUj are the (designer defined) lower and upper bounds imposed on yj , called also designer’s specifications. More complicated specifications, involving some relations between yi parameters, or SjL, SUj bounds can also be defined. For the simplest case of the y-space box-constraints, the acceptability region A in the e-space is defined as such a set of e vectors in the c-dimensional space, for which all inequalities SjL ≤ yj (e) ≤ SUj , j = 1, …, m, are fulfilled. Illustration of this definition is shown in Fig. 50.5. It can be interpreted as the mapping of the acceptability region Ay from the y-space into the e-space. Acceptability regions A can be very complicated: they can be non-convex and can contain internal infeasible regions (or “holes”), as shown in Fig. 50.6 for a simple active RC filter [25]. For discrete circuits, A is normally represented in the e-space, due to the simple relationship ei = xi + θi (or ei = xi (1 + θi)), between ei , xi , and θi . For integrated circuits, e is related to x and θ through the statistical model, x and θ are in different spaces (or subspaces), the dimension of θ is lower than the dimension e, and the p.d.f. fe (e) is singular and usually unknown in analytic form. For these reasons, it is more convenient to represent A in the joint (x, θ)-space, as shown in Fig. 50.7. For a fixed x, A can be defined in the θ-space and labeled as Aθ(x), since it is parametrized by the actual values of x, as shown in Fig. 50.7. The shape and location of Aθ(x) change with x, as shown. For a fixed x, Aθ(x) is defined as such a region in the t-dimensional θ space, for which all the inequalities SjL ≤ yj (e(x, θ)) ≤ SjU; j = 1, …, m, are fulfilled. In order to recognize if a given point e(x, θ) in the circuit parameter space belongs to A [or Aθ(x)], an indicator function φ(·) is introduced e2unacceptable SU(ω)

e2

e2

e1unacceptable e1

SL(ω)

y(ω, e1)

A

y(ω, e2) ω

e1

FIGURE 50.5 Illustration of the mapping of the SL (ω), SU (ω) constraints imposed on y(ω, e) into the e-space of circuit parameters. © 2003 by CRC Press LLC

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C2 = 0.1

(a)

+ V1

A = 50,000 + −

R1 = 10 R2 = 10 C1 = 0.1

−

(b)

+ V2

Rb = 1.98

Ra = 1

−

20 log |f| 50

M

SU(ω)

40 30 C

L

20

N

K

10

B

D O

A

SL(ω)

ω1 .4 (c)

ω2 ω3 ω4

.6

.8

1

E

] ]

ω rd s

R1

R1 10.5

ω5

1.2 1.4 1.6

10.78

C

C B

M

K B

K

M

C 9.74

C R2 10.29

9.54

8.32 .1174

R1

R1 10.4

C1

.08474

D

10.37

C

K

K M

M

B K C

9.78 .09694

C2

.1019

9.71

C B

.9758

R2 1.03

FIGURE 50.6 (a) A Sallen–Key active filter; (b) the lower and upper bounds imposed in the filter frequency response; (c) two-dimensional cross sections of the acceptability region A. Capital letters in (b) and (c) indicate the correspondence of constraints to the boundaries of A.

1  φ e ( x , θ) =  0 

(

)

if e ( x , θ) belongs to A (a successful, or “pass” point) otherwise (a “fall” point)

(50.4)

A complementary indicator function φ F (e (x , θ)) = φ(e (x , θ)) −1 is equal to 1 if e(x, θ) does not belong to A and 0 otherwise. Both indicator functions will be used in what follows.

Methods of Acceptability Region Approximation Except for some simple cases, the acceptability region A in the e (or the joint (x, θ))-space is unknown and it is impossible to fully define it. For yield optimization and other statistical design tasks and implicit or explicit knowledge of A and/or its boundary is required. If only the points belonging to A are stored, this can be considered a point-based “approximation” to A. Some of the point-based methods are Monte © 2003 by CRC Press LLC

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θ2

θ1

A(X3)

A

A(X1) A(X2) X1

X2

X3

X

θ1

Hyperplane θ2 (a)

(b)

FIGURE 50.7 Acceptability region for integrate circuits: (a) in the joint (x, θ)-space; (b) in the θ-space, parametrized by different values of x. The hyperplanes shown represent t-dimensional subspaces of θ parameters.

Carlo-based design centering, centers of gravity method, point-based simplicial approximation and yield evaluation (see below), “parametric sampling-based” yield optimization [36], yield optimization with “reusable” points [39], and others. The acceptability segment-based method of the A-region approximation was called in [27] a onedimensional orthogonal search (ODOS) technique leading to several yield optimization methods [25, 46]. Its basic principle is shown in Fig. 50.8(b), where line segments passing through the points ei randomly sampled in the e-space and parallel to the coordinate axes, are used for the approximation of A. ODOS is very efficient for large linear circuits, since the intersections with A can be directly found from analytical formulas. The two-dimensional cross-sections of A, shown in Fig. 50.6 were obtained using this approach. The surface integral-based yield and yield gradient estimation and optimization method proposed in [13] also use the segment approximation to the boundary of A. A variant of this method is segment approximation in one direction, as shown in Fig. 50.8(c). This method was then extended to plane and hyperplane approximation to A in [42] [Fig. 50.8(d)]. In another approach, called “radial exploration of space” in [54], the segments approximating A are in radial directions, as shown in Fig. 50.8(e). The techniques just described rely on the fact that “segment” yields (calculated in the e subspace) can be, for some special cases [27, 54], calculated more efficiently than using a standard Monte Carlo method. This leads to higher efficiency and accuracy of yield estimation, in comparison to the point-based yield estimation. The simplicial approximation proposed in [10] (described in more detail in Section 49.4), is based on approximating the boundary of A in the e-space, by a polyhedron, i.e., by the union of those partitions of a set of c-dimensional hyperplanes which lie inside of the boundary of A or on it. The boundary of A-region is assumed to be convex [see Fig. 50.8(f)(g)]. The approximating polyhedron is a convex hull of points. Simplicial approximation is obtained by locating points on the boundary of A, by a systematic expansion of the polyhedron. The search for next vertex is always performed in the direction passing through the center of the largest face of the polyhedron already existing. In the MC-oriented “point˜ to A are based” version of the method [11] [see Fig. 50.8(a)], subsequent simplicial approximations A i not based on the points located on the boundary of A (which is computationally expensive) but on the points ei belonging to A already generated during the MC simulation; after each new point is generated, ˜ i−1, (where A ˜ i−1 is the latest simplicial approximation to A); if yes, the sampled it is checked if ei belongs to A ˜ i−1 and point is considered successful without performing the circuit analysis; if ei does not belong to A the circuit analysis reveals that ei belongs to A, the polyhedron is expanded to include this point. Several versions of this general approach, leading to the substantial reduction of the computational effort of yield estimation, are described in the original article. © 2003 by CRC Press LLC

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e2

e2

ei

A

A

e1

e1 (a)

(b) e3

e3

A e1

e1

(c)

x11

(d) e2

x21

Plane

e2

e2

x31

e2 A

X2

X0 A  e1

e1

X1

(e)

(f)

e3

e2

Cutting plane

Tolerance Region

A

e1 (g)

e2

(h)

e1

FIGURE 50.8 Various methods of acceptability region approximation: (a) “Point-based” simplicial approximation to the A-region. (b) Segment approximation to A in all directions along ei axes. (c) Segment approximation to A in one direction. (d) (Hyper)-plane approximation A. (e) Segment approximation to A in radial directions. (f) Simplicial approximation to A in 2 dimensions. (g) Simplicial approximation to A in 3 dimensions. (h) Cutting-plane approximation to A. Note: All A-regions are shown in e-space, for the discrete case, i.e., for e = x + θ.

The method of “cuts” proposed in [5], creates a “cutting-plane” approximation to A in the corners of the tolerance region Rε assumed to be a hypercube, as shown in Fig. 50.8(h). The method was combined with discretization of the p.d.f. fe (e) and multidimensional quadratic approximation to circuit constraints, leading to simplified yield and yield derivative formulas and yield optimization for arbitrary statistical distributors[1].

Manufacturing (Parametric) Yield Manufacturing yield is defined as the percentage of the total number of products manufactured that fulfill both functional and parametric performance requirements.8 Functional circuit performance is the circuit ability to perform desired functions. Catastrophic (or “hard”) circuit failures (such as shorts or open circuit faults caused, e.g., by particular wafer contamination) will completely eliminate some of 8For more detailed yield definitions involving different types of yield, e.g., design yield, wafer yield, probe yield, processing yield, etc., see [12].

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the circuit functions, thus decreasing the part of the overall yield called functional yield. Parametric circuit performance is a measure of circuit quality and is represented by measurable performance functions such as gain, delay, bandwidth, etc., constituting the y-parameter vector. The part of yield related to parametric circuit performance is called parametric yield and is the only type of yield considered in what follows. The actual manufacturing yield is smaller than the parametric yield, since it is equal to the product of the functional or parametric yield [12]. In general, parametric yield is used during circuit electrical design, while functional yield is used during circuit layout design.9 Both are used to predict and optimize yield during circuit design. Parametric yield, therefore, is equal to the percentage of circuits that fulfill all parametric requirements, i.e., it is equal to the probability that e belongs to the acceptability region A. So, it can be calculated as the integral of the p.d.f. of e, fe (e) over A, for a given vector of designable parameters x. Since e = e(x , θ) is a function of x, then e, fe (e) = fe (e, x) (e.g., E{e} and var{e} can be both functions of x). Therefore,10 Y ( x ) = P{e ∈ A} =

∫ f (e, x)de = ∫ A

e

Rc

{ }

φ(e ) fe (e, x )de = E e φ(e )

(50.5)

where P{·} denotes probability, φ(e)is the indicator function (50.4), and Ee{·} is expectation with respect to the random variable e. The above formula is useful if fe (e, x) is a nonsingular p.d.f., which is usually the case for discrete circuits, for which ei = xi + θi , (or ei = xi (1 + θi )). In a general case, however, (e.g., for integrated circuits) the p.d.f. fe (e, x) is not known, since it has to be obtained from a complicated transformation e = e (x, θ), given the p.d.f. fθ(θ) of θ. Therefore, it is more convenient to integrate directly in the θ-space. Since parametric yield is also the probability that θ belongs to Aθ(x) (the acceptability region in the θ-space for any fixed x), yield becomes

{

} ∫

Y ( x ) = P θ ∈ Aθ ( x ) = =

Aθ ( x )

fθ (θ) dθ

∫ φ(e(x, θ)) f (θ)dθ = E {φ(e(x, θ))} θ

Rt

(50.6)

θ

Formula (50.6) is general, and is valid for both discrete and integrated circuits. An unbiased estimator of E θ {ρ(e(x, θ))} ≡ E θ {ρ(θ)} (for fixed x), is the arithmetic mean, based on N points θi, sample in θ-space with the p.d.f. fθ (θ), for which the function φ(θi) is calculated (this involves circuit analyses). Thus, the yield estimator Yˆ is expressed as 1 Yˆ = N

N

∑ φ(θ ) = N i

Ns

(50.7)

i =1

where NS is the number of successful trials, i.e., the number of circuits for which θ ∈ Aθ (x) (all circuit constraints are fulfilled). Integral (50.6) is normally calculated using Monte Carlo (MC) simulations [34] and (7). The MC method is also used to determine statistical parameters of the p.d.f. f y ( y) of y = y(x , θ) . In order to sample the θ parameters with p.d.f. fθ(θ), special numerical procedures, called random number generators, are used. The basic MC algorithm is as follows 1. Set i = 0, NS = 0 (i is the current index of a sampled point and NS is the total number of successful trials). 2. Substitute i = i + 1, generate the i-th realization of θ: θ i = (θ1i , K, θti ), with the p.d.f. fθ (θ). 9

Layout design (i.e., transistor spacing, location, size) has also influence on parameter variations and mismatch, as discussed in Section 50.3. 10Multiple integration performed below is over the acceptability region A, or over the entire c-dimensional space Rc of real numbers. ∈ means “belongs to.”

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3. Calculate the i-th realization of y i = ( y1i ,…, y mi ) = y (x , θ i ), with the aid of an appropriate circuit analysis program, and store the results. 4. Check if all circuit constraints are fulfilled, i.e., if S L ≤ y i ≤ SU ; if yes, set NS = NS + 1. 5. If i ≠ N, go to (2); otherwise: Find the yield estimator Yˆ = N S / N . If needed, find also some statistical characteristics of y-parameters (e.g., create histograms of y, find statistical moments of y, etc.). To generate θi’s with the p.d.f. fθ(θ), the uniformly distributed random numbers are generated first and then transformed to fθ(θ). The most typical random number generator (r.n.g.), generating a sequence of pseudo-random, uniformly distributed integers θk in the interval [0, M) (M is an integer), is a multiplicative r.n.g., using the formula [34]: θ k+1 = cθ k (mod M) where c is an integer constant and θk (mod M) denotes a remainder from dividing θk by M. The initial value θ0 of θk is called the “seed” of the r.n.g., and, together with c, should usually be chosen very carefully, to provide good quality of the random sequence generated. Several other r.n.g.’s are used in practice [34]. The rk numbers in the [0, 1) interval are obtained from rk = θk /M. Distributions other than uniform are obtained through different transformations of the uniformly distributed random numbers, such as the inverse of the cumulative distribution function [34]. To generate correlated normal variables θ = (θ1 , K, θ n ), with a given covariance matrix Kθ, the transformation θ = CZ is used, where Z = (z1 , z 2 , K, z n ) is the vector of independent normal variables with E {z i } = 0, var{zi} = 1, i = 1, …, n, and C is a matrix obtained from the so-called Cholesky decomposition of the covariance matrix Kθ such that Kθ = CCt where t denotes transposition. C is usually lower or upper triangular and can be easily constructed from a given matrix Kθ [34]. The yield estimator Yˆ is a random variable, since performing different, independent MC simulations, one can expect different values of Yˆ = Ns/N. As a measure of Yˆ variations, variance or standard deviation ˆ is equal to σ ˜ = Y (1 − Y )/ N , i.e., of Yˆ can be used. It can be shown [7] that the standard deviation of Y, Y ˆ it is proportional to 1 / N . Hence, to decrease the error of Y 10 times, the number of samples has to be increased 100 times. This is a major drawback of the MC method. However, the accuracy of the MC method (measured by σYˆ) is independent of the dimensionality of the θ-space, which is usually a drawback of other methods of yield estimation. One of the methods of variance reduction of the Yˆ estimator is importance sampling [7, 34, 39]. Assume that instead of sampling θ with the p.d.f. f θ (θ), some other p.d.f. g θ (θ) is used. Then,

Y=

fθ (θ)

fθ (θ) 



∫ φ(e(θ)) g (θ) g (θ) dθ ≡ E φ(e(θ)) g (θ)  R′

θ

θ

(50.8)

θ

where g θ (θ) ≠ 0 if φ(θ) = 1. Yield Y can now be estimated as 1 Y˜ = N

( ) ∑ ( ( )) g (θ ) N

φ e θi

i =1

f θ θi

i

(50.9)

θ

˜ = E{[φ(θ)/g (θ) – Y]2}/N. sampling N points θi with the p.d.f. gθ(θ). The variance of this estimator is var {Y} θ If it is possible to choose g θ (θ) such that it mimics (or is similar to) φ(θ) fθ (θ) / Y , the variability of ˆ This can be accomplished if some approx[φ(θ) fθ(θ)/gθ(θ) – Y] is reduced, and thus the variance of Y. imation to φ(θ), i.e., to the acceptability region A is known. Some possibilities of using importance sampling techniques were studied, e.g., in [16]. One of such methods, called parametric sampling was used in [36], and other variants of important sampling were used in [2, 40] for yield optimization. There are several other methods of variance reduction, such as the method of control variates, correlated sampling, stratified sampling, antithetic variates, and others [7, 34, 39]. Some of them have been used for statistical circuit design [7, 39].

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(a)

(b)

e2

e2

X2

X2,opt

A

A

e1

e1 X1

X1,opt

FIGURE 50.9 Interpretation of yield maximization for discrete circuits: (a) initial (low) yield; (b) optimized yield.

50.4 Statistical Methods of Yield Optimization The objective of the yield optimization is to find a vector of designable parameters x = xopt , such that Y(xopt) is maximized. This is illustrated in Fig. 50.9 for the case of discrete circuits where e1 = x1 + θ1, e2 = x2 + θ2.11 Case (a) corresponds to low initial yield proportional to the weighted (by the p.d.f. fe(e)) area (hypervolume, in general), represented by the dark shaded part of the tolerance body shown. Case (b) corresponds to optimized yield, obtained by shifting the nominal point (x1,x2) to the vicinity of the geometric center of the acceptability region A. Because of this geometric property, approximate yield maximization can often be accomplished using methods called deterministic or geometrical design centering. They solve the yield maximization problem indirectly (since yield is not the objective function optimized), using a geometrical concept of maximizing the distance from xopt to the boundary of A. The best known method of this class [10, 12] inscribes the largest hypersphere (or other norm-body) into the simplicial approximation to the boundary of A, shown in Fig. 50.8(g). This approach is described in more detail in Chapter 49.4, together with other geometrical design centering methods. A class of methods known as “performance-space oriented design centering methods” is also available. These methods attempt to maximize the scaled distances of the performances yj from the lower SUj and/or upper SUj specifications, leading to approximate design centering. Some of these methods are also used for variability minimization and performance tuning, which are the most important tenets of design for quality [30], to be briefly discussed later in this section. The major feature of statistical yield optimization methods, referred to as statistical design centering, is statistical sampling in either θ-space only or in both θ and x-spaces. Sampling can be also combined with some geometrical approximation to the A-region, such as the segment, or radial-segment approximation. In dealing with various statistical methods of yield optimization, the type of the transformation e = e(x , θ) from the θ-space to the circuit-parameter space e, has to be considered. The early, mostly heuristic yield optimization methods were based on the simple additive model ei = x i + θ i , valid for discrete circuits. Because of that, the majority of these methods cannot be used for IC circuit or manufacturing process optimization, where θ and x in different spaces, or subspaces, and the distribution of θ is defined over some subspace of the e-space, i.e., it is singular. The type of the statistical yield optimization algorithm to be used in practice strongly depends on the type of the circuit to be considered and the information available, namely: whether the transformation e = e (x , θ) is a simple one: e i = x i + θ i (or e i = x i (1 + θ i )) (for discrete circuits) or general: e = e(x , θ) (for IC’s); whether the values of γ j (x , θ) for given x and θ only or also the derivatives of yj with respect to xk and/or θs are available from the circuit simulator; whether some approximation y˜ (x, θ) to y(x, θ) is available — either with respect to (w.r.t.) θ only (for a fixed x), or w.r.t. both x and θ; whether the 11Alternatively, the model e = x (1 + θ ) can be used, in which case the size of the tolerance body (see Section 50.3) i i i will increase proportionally to xi .

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analytical form of fθ(θ) is known and fθ(θ) is differentiable w.r.t. θ, or only samples θi of θ are given (obtained from a numerical algorithm or from measurements), so, analytical forms of fθ(θ) and its derivatives w.r.t. θ are not known. Different combinations of the cases listed above require different optimization algorithms. The more general a given algorithm is, the largest number of cases it is able to cover, but simultaneously it can be less efficient than specialized algorithms covering only selected cases. An ideal algorithm would be the one that is least restrictive and could use the minimum necessary information, i.e., it could handle the most difficult case characterized by: the general transformation e = e(x, θ), with the values of y = y(x, θ) only available (generated from a circuit simulator) but without derivatives, no approximation to y(x, θ) available, and unknown analytic form of fθ(θ) (only the samples of θ given). Moreover, under these circumstances such an algorithm should be reasonably efficient even for large problems, and with the presence of some additional information, should become more efficient. The selected yield optimization algorithms discussed below fulfill the criteria of the algorithm “optimality” to a quite different level of satisfaction. It has to be stressed that due to different assumptions made during the development of different algorithms and the statistical nature of the results, an entirely fair evaluation of the actual algorithm efficiency is very difficult, and is limited to some specific cases only. Therefore, in what follows, no algorithm comparison is attempted.

Large-Sample vs. Small-Sample Methods Yield optimization is concerned with the maximization of the regression function Y (x) = E θ {φ(x , θ)} with respect to (w.r.t.) x [see Eq. (50.6)]. In solving general problems of this type, φ(·) is replaced by an arbitrary function w(·). Large-sample methods of optimizing E θ {w(x , θ)} calculate the expectation (average) of w (and/or its gradient) w.r.t. θ for each x0, x1, x2, … from a large number of θi samples. Therefore, the averages used in a specific optimization procedure are relatively accurate, following to take relatively large steps x k+1 – x k. On the other hand, small-sample methods use just a few (very often just one) samples of w(x,θi) for any given point x, and make relatively small steps in the x-space, but they utilize also a special averaging procedure, which calculates the average of w or its gradient over a certain number of steps. So, in this case, the averaging in θ-space and progression in the x-space are combined, while in the large-sample methods they are separated. Both techniques have proven convergence under certain (different) conditions. The majority of yield optimization methods belong to the large-sample category (but some can be modified to use a small number of samples per iteration). A class of small-sample yield optimization methods was proposed in [50] and is based on the well-known techniques of stochastic approximation [34], to be discussed later in this section.

Methods Using Standard Deterministic Optimization Algorithms The most natural method of yield optimization would be to estimate the yields Y(x0), Y(x1), … from a large number of samples (as described in the previous section) for each x0, x1, … of the sequence {xk } generated by a standard, nonderivative deterministic search algorithm, such as the simplex method of Nelder and Mead, Powell, or other algorithms discussed in [14]. This is very appealing, since most of the conditions for algorithm’s “optimality” are fulfilled: it would work for any e = e(x , θ) and only the values of y = y(x , θ) and the samples of θ would be required. However, if no approximation to y = y(x, θ) was available, the method would require tens of thousands of circuit analyses, which would be prohibitively expensive. Moreover, if the number of samples per iteration was reduced to increase efficiency, the optimizer would be receiving a highly noise-corrupted information leading to poor algorithm convergence or divergence, since standard optimization algorithms work poorly with noisy data (special algorithms, able to work under uncertainly — such as stochastic approximation algorithms — have to be used). ˆ k, θ) are available separately for each x k, a large number of If some approximating functions yˆ = y(x MC analyses can be cheaply performed, reducing the statistical error. In practice, such an approach is most often too expensive, due to the high cost of obtaining the approximating formulas, if the number © 2003 by CRC Press LLC

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of important θ parameters is large. The approximating functions yˆj(x,θ) for each yj can be also created in the joint (x , θ) space [56, 61]. In [45], an efficient new approximating methodology was created, highly accurate for a relatively large range of the xi values. However, also in this case the dimension of the joint space (x , θ) cannot be too large, since the cost of obtaining the approximating functions yˆj(x,θ) for becomes itself prohibitively high. Because of these difficulties, several dedicated yield optimization methods have been developed, for which the use of function approximation is not required. Some of these methods are described in what follows.

Large-Sample Heuristic Methods for Discrete Circuits These methods have been developed mostly for discrete circuits, for which ei = xi + θi . Only y i = y(x + θi) function values are required, for the sample θi obtained in an arbitrary way. Approximation in the espace can be constructed to increase efficiency, but for discrete circuits the number of θ parameters can be large (proportional to the number of active devices, since no correlations between different devices exist), so the use of approximation is most often not practical. The most typical representative of this class is the centers of gravity method [39]. The method is based on a simple observation that if x S is the – center of gravity of “pass” points (as shown in Fig. 50.10), defined as xS = (x1A + x2A + L + XANA)/NA, i where NA is the number of points xA falling into the A-region, then a step from x to x S will improve yield. In [37], also the center of gravity of the “fail” points x F = (x1F + x F2 + L + x FN F ) / N F was defined, and the direction of yield increase taken as going from x F through x A, as shown in Fig. 50.11. Moving in this direction with the step-size equal to µ(x S − x F ), where µ ≈ 0.2 − 2 (often taken as µ =1) leads to a sequence

e2 A  XS X2

XiA

X XiF

e1

X1

FIGURE 50.10 Interpretation of the original centers of gravity method.

e2 A “pass” “fail” Direction of yield increase X

“Center of gravity” of “fail” points

move

“Center of gravity” of “pass” points

FIGURE 50.11 Interpretation of the modified centers of gravity method. © 2003 by CRC Press LLC

e1

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–

of optimization steps, which is stopped if  xS – xF  is less than a predefined small constant. This is based on the property (proved for a class of p.d.f.’s in [43] that, under some conditions, at the yield maximum – – – – xS – xF = 0 (and xS = xF = xˆ where xˆ is the point of the yield maximum). It was also shown in [43] that for the normal p.d.f. fθ(θ) with zero correlations and all standard deviations σθi = σθ , i = 1, K, t, equal, the “centers-of-gravity” direction coincides with the yield gradient direction. However, with correlations and σθi’s not equal, the two directions can be quite different. Various schemes, aimed at the reduction of the total required number of analyses were developed based on the concepts of “re-usable” points [39]. In [18, 19] the original centers of gravity method was significantly improved, introducing a concept of “Gaussian adaptation” of the covariance matrix of the sampled points of θi, such that they (temporarily) adopt to the shape of the acceptability region, leading to higher (optimal) efficiently of the algorithm. The method was successfully used on large industrial design examples, involving as many as 130 designable parameters, not only for yield optimization, but also for standard function minimization. The methods of “radial exploration of space” [54] [see Fig. 50.8(e)] and one-dimensional orthogonal searches (ODOS) [26, 27] [see Fig. 50.8(b), (c)] discussed in Section 50.3 in the context of Acceptability Region approximation, have also been developed into yield optimization methods: in the “radial exploration” case the asymmetry vectors were introduced, generating a direction of yield increase, and in the ODOS case using a Gauss–Seidel optimization method. Both techniques were especially efficient for linear circuits due to a high efficiency of performing circuit analyses in radial and orthogonal directions.

Large-Sample, Derivative-Based Methods for Discrete Circuits For discrete circuits, the relation ei = x i + θ i holds for a part of the entire e vector, so, xi and θi are in the same space. Moreover, the p.d.f. fθ(θ) is most often known. Let x denote the vector of expectations x ≡ E θ {e(x , θ)}, and fe(e, x) is the p.d.f. fθ(θ) transformed to the e-space (i.e., of the same shape as fθ(θ), but shifted by x). Then, from (50.5), differentiating w.r.t. xi , one obtains ∂Y ( x ) = ∂x i

∫

R

n

φ(e )

 ∂fe (e, x ) fe (e, x ) ∂ ln fe (e, x )  de = E e φ(e )  ∂xi fe (e, x ) ∂x i  

(50.10)

where the equivalence (∂fe (e, x) / fe (e, x)) / ∂x i ≡ ∂ ln fe (e, x) / ∂x i was used. Therefore, yield derivatives w.r.t. xi can be calculated as the average of the expression in the braces of Eq. (50.10), calculated from the same θi samples as those used for yield estimation, provided that the p.d.f. fe (e, x) is differentiable w.r.t x (e.g., the normal or log-normal p.d.f.’s are differentiable, but the uniform p.d.f is not). Notice that instead of sampling with the p.d.f. fe (e, x), some other (better) p.d.f ge (e, x) can be used as in the importance sampling yield estimation [see Eq. (50.8)]. Then, ∂Y ( x ) = Ee ∂x i

 ∂fe (e, x )  fe (e, x )    φ(e ) ∂x i  g e (e, x )   

(50.11)

where sampling is performed with the p.d.f. g e (e, x) ≠ 0. This technique was used in [2, 36, 51] (to be discussed next). Consider the multivariate normal p.d.f., with the positive definite covariance matrix K fe (e ) =

1

( 2π )

t / 2 det K

t  1  exp − (e − x ) K −1 (e − x ) 2  

(50.12)

where e − x ≡ θ (discrete circuits), and det K is the determinant of K. Then, it can be shown that the yield gradient ∇ x y(x) is expressed by

{

}

∇x Y ( x ) = E φ(e )K −1 (e − x ) = Y ( x )K −1 ( x s − x ) © 2003 by CRC Press LLC

(50.13)

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e2 A θ1 X2

θ3 θ4 [∇x Y(X)]pass θ5 θ6

θ2

e1 X1

FIGURE 50.12 Interpretation of the yield gradient formula for normal p.d.f., with no correlations and σθ1 = σθ2 = 1. For the “pass” points (black dots) [∇x Y(x)]pass ≈ (θ3 + θ4 + θ5 + θ6)/4; for the “fail” points (white dots) [∇x Y(x)]fail (–θ1 – θ2)/2. The two estimators can be combined together (equal weighting assumed): ∇xY(x) = –θ1 – θ2 + θ3 + θ4 + θ5 + θ6)/6. It is clearly seen that the two yield gradient estimators coincide with the center-of-gravity of the “pass” and “fail” points, respectively.

where x S is the center of gravity of “pass” points. If yield Y(x) is a continuously differentiable function of x, then the necessary condition for the yield maximum is ∇ x y(xˆ ) = 0, which combined with Eq. (50.13) means that the stationery point xˆ for the yield function (the yield maximum if Y(x) is also concave) is xˆ = x S , the center of gravity of the pass points. This result justifies (under the assumptions stated previously) the centers of gravity method of yield optimization (since its objective is to make xˆ = x S ≡ x F). For K = diag{σe21 ,K, σe2t }, i.e., with zero correlations, the yield gradient w.r.t. x is expressed as  θ θ  ∇x Y ( x ) = E e φ(e ) 21 , K, 2t σ θt  σ θ1 

  

t

   

(50.14)

where σθi ≡ σei was used instead of σei . It can be readily shown that for all σθi = L = σθt = σθ equal, the yield gradient direction coincides with the center-of-gravity direction [43] (Fig. 50.12). Since all higher-order derivatives of the normal p.d.f. exist, all higher order yield derivatives can also be estimated from the same sampled points θi, as those used for yield estimation. The yield gradient can ⋅ = φ() ⋅ −1 indicator function in all the also be calculated from the “fail” points simply using the φ F () expressions above. Then, the two resulting estimators can be combined as one joint average, as it was done in the x–s , x–F -based centers of gravity method. Actually, there exists an optimal weighted combination of the two estimators for any given problem, resulting in the minimum variability of the gradient, but it is difficult to precisely determine in practice. A general rule is that at the beginning of optimization, when x is far away from xˆ (the optimal point), the yield gradient estimator based on the “pass” points should be more heavily weighted; the opposite is true at the end of optimization, when the “fail” points carry more precise gradient information. An interpretation of the yield gradient formula (50.14) is shown in Fig. 50.12, for the case where σθ1 = σθ2 = 1. In the majority of practical applications of large-sample derivative methods, it was assumed that fe(e) was normal. A typical iteration step is made in the gradient direction

( )

x k +1 = x k + α k ∇ xY x k

(50.15)

where αk is most often selected empirically, since yield maximization along the gradient direction is too expensive, unless some approximating functions yˆ = yˆ (x + θ) are used (normally, this is not the case for the class of methods discussed). Since the number of points θi sampled for each xk, is large, the main difference between various published algorithms is how to most efficiently use the information already

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et−1 (subspace) A

Rε

e(1) n−1 xt−1 e(k) t−1

Y−i

Y+i εi

εi ei xi

FIGURE 50.13 Yield and yield derivative estimation for uniform distribution. Y + and Y – denote symbolically the (k) “yields” calculated on the t – 1 dimensional faces of the tolerance hypercube Rε. The et–1 points are sampled in the t – 1 dimensional subspaces of et–1 parameters, with the uniform p.d.f. fe t–1 (et–1).

available. The three methods to be discussed introduced almost at the same time [2, 36, 51]), utilize for that purpose some form of importance sampling, discussed in Section 50.3. In [36], a “parametric sampling” technique was proposed, in which the θi points were sampled with the p.d.f. g e (e, x) in a broader range than for the original p.d.f. (i.e., all the σθi’s were artificially increased). All points sampled were stored in a database, and the gradient-direction steps made according to (50.15). The importance sampling-based gradient formula (50.11) was used in subsequent iterations within the currently available database. Then, a new set of points was generated and the whole process repeated. The methods developed in [51] and [2] were also based on the importance sampling concept, but instead of using the gradient steps as in (50.15), the yield gradient and Hessian12 matrices were calculated and updated within a given database. Then, a more efficient Newton’s direction was taken in [51] or a specially derived and efficient “yield prediction formula” used in [2]. In order to deal with the singularity or nonpositive definiteness of the Hessian matrix (which is quite possible due to the randomness of data and the behavior of Y(x) itself), suitable Hessian corrections were implemented using different kinds of the Hessian matrix decomposition (Cholesky-type in [51] and eigenvalue decomposition in [2]). As it was the case for the heuristic methods, the methods just discussed are relatively intensive to the dimensionality of x and θ spaces. For the uniform p.d.f., centered at e = x (see Fig. 50.13) and defined within a hyperbox xi – εi ≤ ei ≤ xi + ε, i = 1, …, t, where εi are element tolerances (see Fig. 50.2), the yield gradient formula (50.10) cannot be used, since the uniform p.d.f. is nondifferentiable w.r.t. xi. It can be shown [26, 42, 43] that yield can be calculated by sampling in the t – 1 dimensional subspace of the e-space, represented by et–1 ≡ (e1, …, ei–1, ei+1, …, et) and analytical integration in the one-dimensional subspace ei as shown in Fig. 50.13. Using this approach, it can be further proved [43] that the yield derivatives w.r.t. xi are expressed by ∂Y ( x ) 1 Y + − Yi − = 2ε i i ∂x i

(

)

(50.16)

where Yi+ , Yi − are “yields” calculated on the faces of the t – 1 tolerance hyperbox Rε, corresponding to x i + ε i and x i − ε i , respectively. Calculation of these “yields” is very expensive, so in [43]13 different algorithms improving efficiency were proposed. In [53], an approximate method using efficient 3-level

12 13

Matrix of second derivatives. In [43], general formulas for gradient calculation for truncated p.d.f.’s were derived.

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θt−1 (subspace) θ(1) i

θ(3) i

θ(2) i

θ(4) i

sampled point θi A(x)

FIGURE 50.14 Interpretation of “local yield” calculation along a parallel.

orthogonal array (OA) sampling on the faces of Rε was proposed, in which (due to specific properties of OA’s) the same sample points were utilized on different faces (actually one-third of all sampled points were available for a single face). This has lead to substantial computational savings and faster convergence.

A Large-Sample, Derivative-Based Method for Integrated Circuits In this case, which is typical of IC yield optimization, yield gradient calculations cannot be performed in the e-space, as was the case for discrete circuits. In general, yield gradient could be calculated by differentiating the φ(e(x , θ)) ≡ φ(x , θ) term in the θ–space-based yield formula (50.6), derived for the general case, where the general transformation e = e (x , θ) is used. Differentiation of φ(x , θ) is, however, not possible in the traditional sense, since φ(x , θ) is a nondifferentiable unit step function determined over the acceptability region A. One possible solution was proposed in [15]. In what follows, a related, but more general method proposed in [13] is discussed. It was first shown in [13] that yield can be evaluated as a surface-integral rather than the volumeintegral (as it is normally done using the MC method). To understand this, observe that yield can be evaluated by sampling in the t – 1 subspace of the t-dimensional θ-subspace, as shown in Fig. 50.14, evaluating “local yields” along the lines parallel to the θi axis, and averaging all the local yields.14 Each “local yield” can be evaluated using the values of the cumulative (conditional) distribution function15 along each parallel, at the points of its intersection with the boundary of the acceptability region A. This process is equivalent to calculating the surface integral over the value of the cumulative density function calculated (with appropriate signs) on the boundary of the acceptability region. The next step in [13] was to differentiate the “surface-integral” based yield formula w.r.t. xi , leading to the following yield gradient formula   ∇Y ( x ) = Eθt −1   

∑ ( )

fθi θ(i k ) ⋅

k

   ∂y a ( x , θ) ∂θi (k )  x ,θt −1 ,θi  ∇ x y a ( x , θ)

(50.17)

Where summation is over all intersection points θ(i k) of the parallel shown in Fig. 50.14 with the boundary of Aθ (x); ya is that specific performance function y j (x , θ) which, out of all the other performances, actually determines the boundary of the acceptability region at the θ(i k) intersection point.16 The gradient ∇x ya(x, θ), and the derivative ∂y a (x , θ) / ∂θ i have to be calculated for every fixed sampled point (x , θt −1), at 14Identical technique was used in the previous section [42, 42] to derive the yield derivative formula (50.16) (see Fig. 50.13). 15If θ ’s are independent, it is the marginal p.d.f. of θ , as it was assumed in [13]. i i 16At this point, a specific equation y (x, θ , 1(k)) = S (where S ≡ S L or S ≡ S U or are lower and upper bounds a t–1 i a a z a a on ya, respectively) must be solved to find θi(k).

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each intersecting point θ(i k ) shown in Fig. 50.14. Observe that the derivative calculations in (50.17) can (and often will have to) be performed in two steps: since y a (x , θ) = y a (e (x , θ)), so, ∂y a /∂x p = Σ s(∂ya /∂es)(∂es /∂xp), and ∂ya /∂θi = Σ s(∂ya/∂es)(∂es/∂θi), where the derivatives appearing in the first parentheses of both formulas are calculated using a circuit simulator and those in the second parentheses from a given statistical model e = e(x , θ). In the practical implementation presented in [13], random points θr are sampled in the θ space, in the same way as shown in Fig. 50.8(b) but replacing e by θ, then searches for the intersections θ(i k ) are performed in all axis directions, the formula in the braces of Eq. (50.17) is calculated for each intersection, and averaged out over all outcomes. Searches along the parallel lines in all directions are performed to increase the accuracy of the yield gradient estimator. Observe that this technique requires tens of thousands of circuit analyses to iteratively find the intersection points θ(i k ) , plus additional analyses (if needed) for the calculation of the gradient and the derivatives in (50.17). This problem has been circumvented in [13] by constructing approximating functions yˆ = yˆ (x , θ) w.r.t. θ for each x, together with approximating functions for all the derivatives.17 Due to a high level of statistical accuracy obtained in evaluating both yield and its gradients, an efficient, gradient-based deterministic optimization algorithm, based on sequential quadratic programming was used, requiring a small number of iterations (from 5 to 11 for the examples discussed in [13]). The gradient ∇x ya(x, θ) was either directly obtained from circuit simulator, or (if not available) using (improved) finite difference estimators. The method showed to be quit efficient for a moderate size of the θ-space (10-12 parameters). The resulting yield optimization method is independent of the form of e = e(x, θ) the derivatives of yj w.r.t. to both xk and θs are required and the analytical form of fθ(θ) and its cumulative function distribution must be known. The method cannot practically work without constructing the approximating functions y˜ = y(x , θ) (approximating function in the joint space (x , θ) could also be used, if available).

Small-Sample Stochastic Approximation-Based Methods Standard methods of nonlinear programming perform poorly in solving problems with statistical errors in calculating the objective functions (i.e., yield) and its derivatives.18 One of the methods dedicated to the solution of such problems is the stochastic approximation (SA) approach [33] developed for solving the regression equations, and then adopted to the unconstrained and constrained optimization by several authors. These methods are aimed to the unconstrained and (maximum) of a function corrupted by noise (a regression function). The SA methods were first applied to yield optimization and statistical design centering in [49, 50]. The theory of SA methods is well established, so its application to yield optimization offers the theoretical background missing e.g., in the heuristic methods of Section 50.3. As compared to the large-sample methods, the SA algorithms to be discussed use a few (or just one) randomly sampled points per iteration, which is compensated for by a large number of iterations exhibiting a trend toward the solution. The method tends to bring large initial improvements with a small number of circuit analyses, efficiently utilizing the high content of the deterministic information present at the beginning of optimization. In 1951, in their pioneering work, Robins and Monro [33] proposed a scheme for finding a root of a regression function, which they named the stochastic approximation procedure. The problem was to find a zero of a function, whose “noise corrupted” values could be observed only, namely G(x) = g(x) + θ(x) where g(x) (unknown) function of x, θ is a random variable, such that E{θ} = 0 and var{θ} ≤ L < ∞. Therefore, a zero of the regression function g(x) ≡ E{G(x)} = 0 was to be found. The SA algorithm proposed in [33] works as follows: given a point x (k), set the next point as x (k+1) = x (k) – ak G(x (k)). The sequence of {x (k)} points converges to the solution xˆ under some conditions (one of them is, for instance, 17

Low-degree polynomials were used with very few terms, generated from a stepwise regression algorithm. This was the reason a high level of accuracy was required while calculating both yield and its derivatives using the method described in the previous section (and consistency between the yield and gradient estimators), otherwise, the deterministic optimization algorithm would often diverge, as observed in [13]. 18

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e2 dk−1 (previous search direction) ρk 0 is the step length coefficient selected such that the sequence: {τ k } → 0 , and For the Σ∞k=0 τk = ∞, Σ∞k=0 τk2 < ∞ (e.g., the harmonic series {1, 1-2 , 1-3, …} fulfills these conditions). convergence with probability one, it is also required that the conditional expectation E{ξkx1, x2, …, x k } = ∇Y(xk). The algorithm (50.18) is similar to the steepest ascent algorithms of nonlinear programming, so, it will be slowly convergent for ill-conditioned problems. A faster algorithm was introduced in [35] and used for yield optimization in [49, 50]. It is based on the following iterations: x k +1 = x k + τ kd k d k = (1 − ρk )d k −1 + ρk ξk ,

(50.19) 0 ≤ ρk ≤ 1

(50.20)

where ξk is a (one- or more-point) estimator of ∇ xY (x k ) and {τ k } → 0, {ρk } → 0 are nonnegative coefficients. d (k) is a convex combination of the previous (old) direction d k–1 and the new gradient estimate ξk , so the algorithm is an analog of a more efficient, conjugate gradient method. Formula (2) provide gradient averaging. The ρk coefficient controls the “memory” or “inertia” of the search direction d k, as shown in Fig. 50.15. If ρk is small, the “inertia” of the algorithm is large, i.e., the algorithm tends to follow the previous gradient directions. For convergence with probability one, the same conditions must hold as those for (50.18). The coefficients τk and ρk automatically determined based on some heuristic statistical algorithms proposed in [35]. Several other enhancements were used to speed up the convergence of the algorithm, especially in its much refined version proposed in [35]. For solving the optimization problems, the oneor two-point yield gradient estimator is found from (50.10) in general, and from (50.13) or (50.14) for the normal p.d.f. Example 1 A simple two-dimensional case is considered in order to illustrate the algorithm properties. The acceptability region (for a voltage divider) [49] is defined in the two-dimensional space (e1 , e 2 ) by the inequalities: © 2003 by CRC Press LLC

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1.4 5

1

7 4

1.3 10

1.2 12 15 16

18

20

1.1

127

30

1.0 36

43

26

40

0.9 0.9

1.0

1.1

0.45 ≤

1.2

e2 ≤ 0.55 e1 + e 2

FIGURE 50.16 A typical trajectory of the stochastic approximation algorithm (Example 1).

0 ≤ e1 ≤ 1.2

0 ≤ e 2 ≤ 1.3

(50.21)

where ei = x i + θ i and the p.d.f. of θi is normal with E {θ1} = E {θ 2 } = 0, and cov {θ1 , θ 2 } = 0 (no correlations). A typical algorithm trajectory is shown in Fig. 50.16. The one-sample yield gradient formula (50.14) was used. The initial yield was low (7.4%). Very few (25–30) iterations (equal to the number of circuit analyses) were required to bring the minimal point close to the final solution. This is due to the fact that at the beginning of optimization, there is a high contents of deterministic gradient information available even from a few sampled points, so the algorithm progress is fast. Close to the solution, however, the yield gradient estimator is very noisy, and the algorithm has to filter out the directional information out of noise, which takes the majority of the remaining iterations. After the total of 168 circuit analyses, the yield increases to 85.6%. Other starting points resulted in a similar algorithm behavior. It is also observed that the yield optimum is “flat” in the diagonal direction, reflected in random nominal point movement in this direction (iterations 30 through 43). Example 2 Parametric yield for the Sallen–Key active filter of Fig. 50.6(a) (often used in practice as a test circuit) with the specifications on its frequency response shown in Fig. 50.6(b) was optimized (recall that the shape of the acceptability region for this case was very complicated, containing internal non-feasible regions (“holes”)). All R, C variables were assumed designable. The relative standard deviations were assumed equal to 1% for each element, the p.d.f. was normal with 0.7 correlation coefficient between the like elements (R’s or C’s) and zero correlations between different elements. The initial yield was 6.61%. Using the SA algorithm as in the previous example, 50 iterations (equal to the number of circuit analyses) brought yield to 46.2%; the next 50 iterations to 60%, while the remaining 132 iterations increased yield to only 60.4% (again the initial convergence was very fast). The algorithm compared favorably with the Hessian matrix-based, large-sample method discussed previously [51], which required about 400 circuit © 2003 by CRC Press LLC

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analyses to obtain the same yield level, and whose initial convergence was also much slower. It has to be stressed, however, that the results obtained are statistical in nature and it is difficult to draw strong general conclusions. One observation (confirmed also by other authors) is that the SA-type algorithms provide, in general, fast initial convergence into the neighborhood of the optimal solution, as it was shown in the examples just investigated.

Small-Sample Stochastic Approximation Methods for Integrated Circuits The methods of yield gradient estimation for discrete circuits cannot be used for IC’s because of the form of the e = e(x , θ) transformation, as discussed at the beginning of Section 50.4. Previously in this section, a complicated algorithm was described for gradient estimation and yield optimization in such situations. In this section, a simple method based on random perturbations in x-space, proposed in [47, 48], is described. It is useful in its own merit, but especially in those cases, where the conditions for the application of the yield gradient formula (50.17) are hard to meet, namely: the cost of constructing the approximating functions yˆ = yˆ (x , θ) for fixed x is high and calculating the gradient of y w.r.t. x is also expensive (which is the case, e.g., if the number of important x and θ parameters is large), and the analytical form of fθ(θ) is not available (as it is required in (50.17)). The method applications go beyond yield optimization: a general problem is to find a minimum of a general regression function f (x) = E θ {w(x , θ)}, using the SA method, in the case where the gradient estimator of f (x) is not directly available. Several methods have been proposed to estimate the gradient indirectly, all based on adding some extra perturbations to x parameters. Depending on their nature, size, and the way the perturbations are changed during the optimization process, different interpretations result, and different problems can be solved. In the simplest case, some extra deterministic perturbations (usually double-sided) are added individually to each xk (one-at-a-time), while random sampling is performed in the θ-space, and the estimator of the derivative of f (x) w.r.t. xk is estimated from the difference formula ξˆ k = ∂f (x)/∂xk = (1/N) ΣNi=1 {[w(x + ak ek , θ1i ) – w(x – a ke k, θ i2)]/(2a k)}, where ak > 0 is the size of the perturbation step and ek is the unit vector along the ek coordinates axis. Usually, θ1i ≡ θ12 to reduce the variance of the estimator. Normally, N = 1. Other approaches use random direction derivative estimation by sampling points randomly on: a unit sphere of radius a [34], randomly at the vertices of a hypercube in the x-space [38], or at the points generated by orthogonal arrays [53], commonly used in the design of experiments. Yet another approach, dealing with nondifferentiable p.d.f.’s was proposed in [55]. In what follows, the random perturbation approach resulting in convolution function smoothing is described for a more general case, where a global rather than a local minimum of f(x) is to be found. The multi-extremal regression function f(x) defined previously, can be considered a superposition of an uni-extremal function (i.e., having just one minimum) and other multi-extremal functions that add some deterministic “noise” to the uni-extremal function (which itself has also some “statistical noise” — due to θ — superimposed on it). The objective of convolution smoothing can be visualized as “filtering out” but types of noise and performing minimization on the “smoothed” uni-extremal function (or on a family of these functions), in order to reach the global minimum. Since the minimum of the smoothed uni-extremal function does not, in general, coincide with the global function minimum, a sequence of minimization runs is required with the amount of smoothing eventually reduced to zero in the neighborhood of the global minimum. The smoothing process is performed by averaging f(x) over some region ˆ of the n-dimensional parameter space x using a proper weighting (or smoothing) function h(x), defined below. Let the n-dimensional vector η denote a vector of random perturbations; it is added to x to create the convolution function [34] f˜ ( x , β) =

∫ hˆ(η, β) f (x − η)dη

Rn

=

∫

Rn

© 2003 by CRC Press LLC

{

}

hˆ( x − η, β) f ( η)dη = E η f ( x − η)

(50.22)

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100.

100.

50. 2.

50.

3.

5.

1.6

4.

0.

0.

3.

1. 2. 0.6

−50.

−50.

1.

(a) β = 0.

−100. -5.00

-2.50

0.00

2.50

5.00

(b)

β = 0.001

−100. -5.00

-2.50

0.00

2.50

5.00

FIGURE 50.17 Smoothed functional f(x, β) for different β’s using: (a) Gaussian kernel; (b) uniform kernel.

where fˆ(x, β) is the smoothed approximation to the original multi-extremal function f(x), and the kernel ˆ β) is the p.d.f. used to sample η. Note that f (x, β) can be interpreted as an averaged version function h(η, ˆ i.e., the degree of f(x) smoothing ˆ β). Parameter β controls the dispersion of h, of f (x) weighted by h(η, (e.g., β can control the standard deviations of η1…ηn). Eη {f (x – η)} is the expectation with respect to the random variable η. Therefore, an unbiased estimator fˆ(x, β) of fˆ(x, β) is the average: fˆ(x, β) = (1/N) ˆ ˆ – β). The kernel function h(η, β) should have ΣNi–1 f (x – ηi), where η is sampled with the p.d.f. h(η certain properties discussed in [34], fulfilled by several p.d.f.’s, e.g., the Gaussian and uniform. For the function f (x) = x 4 – 16x2 + 5x, which has two distinct minima, smoothed functionals, obtained using (50.22), are plotted in Fig. 50.17 for different values of β → 0, for: (a) Gaussian and (b) uniform kernels. ~ f (x, β) if β is sufficiently large. If β → 0, As seen, smoothing is able to eliminate the local minima of ~ then f (x, β) → f(x). The objective now is to solve the following optimization problem: minimize the smoothed ~ ˆ where xˆ is the global minimum of the original function f (x). functional f (x, β) with β → 0 as x → x, ~ ˆ The modified optimization problem can be written as: minimize f (x, β) w.r.t. x, with β → 0 as x → x. Differentiating (50.22) and using variable substitution, the gradient formula is obtained ∇x f˜ ( x , β) =

∫ ∇ hˆ(η, β) f (x − η)dη = β ∫ ∇ h(η) f (x − βη)dη, 1

η

η

Rn

(50.23)

Rn

ˆ ⋅ is as defined previously, and h(y) is a normalized version of h(y) where hˆ () (obtained if β = 1). For ˜ normalized multinormal p.d.f. with zero correlations, the gradient of f (x, β) is ∇x f˜ ( x , β) =

−1 β

−1

∫ η f (x − βη)h(η)dη = β E {η f (x − βη)} η

Rn

(50.24)

−1 = E ηw ( x − βη, θ) β η,θ

{

}

where sampling is performed in x-space with the p.d.f. h(η), and in θ-space with the p.d.f. fθ(θ); Eη,θ denotes expectation w.r.t. both η and θ, and it was taken into account for f(x) is a noise corrupted version of w(x, θ) i.e., f(x) = Eθ{w(x, θ)}. The unbiased single-sided gradient estimator is therefore ˆ f˜ ( x , β) = −1 1 ∇ x β N

© 2003 by CRC Press LLC

N

∑ η w(x − βη , θ ) i

i =1

i

i

(50.25)

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In practice, a double-sided estimator [34] of smaller variance is used ˆ f˜ ( x , β) = 1 1 ∇ x 2β N

N

∑ η [w (x + βη , θ )]. i

i

i 2

(50.26)

i =1

Normally, N = 1 for best overall efficiency. Statistical properties of these two estimators (such as their variability) were studied in [52]. To reduce variability, the same θ1i = θ i2 are usually used in Eq. (50.26) for positive and negative βηi perturbations. For yield optimization, w(·) is simply replaced by the indicator function φ(·). For multi-extremal problems, β values should be originally relatively large and then systematically reduced to some small number rather than to zero. For single-extremal problems (this might be the case for yield optimization) it is often sufficient to perform just a single optimization with a relatively small value of β, as it was done in the examples to follow.

Case Study: Process Optimization for Manufacturing Yield Enhancement The object of the work presented in [48] was to investigate how to modify the MOS control process parameters together with a simultaneous adjustment of transistor widths and lengths to maximize parametric yield.19 To make it possible, both process/device simulator(s) (such as FABRICS, SUPREM, PISCES, etc.) and a circuit simulator must be used. In what follows FABRICS [12, 22, 24] is used as a process/device simulator. IC technological process parameters are statistical in nature, but variations of some of the parameters (e.g., times of operations, implant doses, etc.) might have small relative variations, and some parameters are common to several transistors on the chip. Because of that, the transformation e = e (x, θ) (where θ are now process related random variables), is such that standard methods of yield optimization developed for discrete circuits cannot be used. Let Z1 = z1 + ξ1 be the process control parameters (doses, times, temperatures), where ξ1 are random parameter variations, and z1 are deterministic designable parameters. Let Z2 = z2 + ξ2 be the designable layout dimensions, where z2 are designable and ξ2 are random variations (common to several transistors on a chip). P = p + ψ are process physical parameters (random, nondesignable) such as diffusivities, impurity concentrations, etc. (as above, p is the nominal value and ψ is random). All random perturbations are collected into the vector of random parameters θ, called also the vector of process disturbances: θ = (ξ1, ξ2, ψ). The vector of designable parameters x = (z1 , z 2 ) is composed of the process z1 and layout z2 designable parameters. Therefore, x and θ are in different spaces (sub-spaces). There are also other difficulties: the analytical form of the p.d.f. of θ is most often not known, since θ parameters are hierarchically generated from a numerical procedure [12], the derivatives of the performances y w.r.t. x and θ are not known from FABRICS and can only be estimated by finite differences, and the θ and x spaces are very large (see below). So, creating approximation and/or finding derivatives using finite differences is expensive. Because of these difficulties, the smoothed-functional approach discussed in this section will be used, as shown in the following example. Example 1 The objective is to maximize parametric yield for the NMOS NAND gate shown in Fig. 50.18 [48], by automated adjustment of process and layout parameters. Specifications are: V0 = Vout(t = 0) ≤ 0.7 V, Vout(t1 = 50 ns) > 6.14 V, circuit area ≤ 2500 µm2. There are 45 designable parameters: all 39 technological process parameters, 6 transistor dimensions, and about 40 noise parameters, so it is a large problem suitable for the use of the SA-based random perturbation method described above. The initial yield was Y = 20%. After the first optimization using the method of random perturbations with 2% relative perturbations of each of the designable parameters involving the total of 110 FABRICS/SPICE analyses, yield increased to 100% and the nominal area decreased to 2138 µm2. Then, specs were tightened 19

This might be important, e.g., for the process refinement and IC cell redesign.

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M1

VDD = 6.5V

+ VGG = 14.5V −

M2

1kΩ

M3

+

CL

+

+ 6V 0V

1kΩ

Vin

5pF

Vout −

−

FIGURE 50.18 NMOS NAND gate of Example 1.

(c)

[V] 6 Vin

(b)

5 (A) (d)

(a)

4 (B) Vout

3

2

V0

1 (A),(B)

V0 0 0

10

20

30 TIME (ns)

40

50

60

FIGURE 50.19 Nominal transient responses for Example 1: (a) Initial. (b) After first optimization. (c) After tightening the specs and second optimization.

to Vout (t2 = 28 ns) > 6.14 V with the same constraints on V0 and area, causing yield to drop to 10.1%. After 60 FABRICS/SPICE analyses, using the perturbation method, yield increased to: Y = 92%, and area = 2188 µm2. These much-improved results produced the nominal circuit responses shown in Fig. 50.19. Several technological process parameters were changed during optimization in the range between 0.1 to 17%: times of oxidation, annealing, drive-in, partial pressure of oxygen, and others, while the transistor dimensions changed in the range between 0.8% to 6.3%. The cost of obtaining these results was quite reasonable: the total of 170 FABRICS/SPICE analyses, despite the large number of optimized and noise parameters. Other examples are discussed in [48]. © 2003 by CRC Press LLC

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Generalized Formulation of Yield, Variability, and Taguchi Circuit Optimization Problems Parametric yield is not the only criterion that should be considered during statistical circuit design. Equally, and often more important is minimization of performance variability caused by various manufacturing and environmental disturbances. Variability minimization has been an important issue in circuit design for many years [17] (see [17] for earlier reference). It leads (indirectly) to parametric yield improvement. Circuits characterized by low performance variability are regarded as high quality products. Most recently, variability minimization has been re-introduced into practical industrial design due to the work of Taguchi [30]. He has successfully popularized the notion of “Off-Line Quality Control” through an intensive practical implementation of his strategy of designing products with low performance variability, tuned to the “target” values STj of the performance functions yj . In what follows, a generalized approach proposed in [44] is discussed, in which a broad range of various problems, including yield optimization and Taguchi’s variability minimization as special cases can be solved, using the SA approach and the general gradient formulas developed previously in this section. It is convenient to introduce the M dimensional vector g(e) of scaled constraints, composed of the vectors g L (e), and g U (e), defined as g kL (e ) =

SkT − y k (e ) , k = 1, K, M L SkT − SkL

(50.27)

g tU (e ) =

yt (e ) − StT , t = 1, K, MU StU − StT

(50.28)

where e = e(x, θ), M = ML + MU ≤ 2 m (note that in general M ≤ 2 m, since some of the lower or upper specs might not be defined). These constraints are linear functions of yi (·); they have important properties: g L = g U = 0 if y = ST , g L = 1 if y = SL, and gU = 1 if y = SU. For S L < y < SU and y ≠ ST , either gL or gU is greater than zero, but never both. For any “good” design, we would like to make each of the normalized constraints introduced previously equal to zero, which might not be possible due to various existing design trade-offs. Therefore, this is a typical example of a multi-objective optimization problem. The proposed scaling helps to compare various trade-off situations. The Taguchi “on-target” design with variability minimization is formulated as follows (for a single performance function y(e))

{

[(

)

]

2 minimize MTAG ( x ) = E θ  y e( x , θ) − ST   

{ } [

= var y ( x ) + y ( x ) − S

T

]

2

(50.29)   

where y (x) is the mean (average) value of y (w.r.t θ), and MTAG , is called the “loss” function (in actual implementations Taguchi uses related but different performance statistics). Generalization of (50.29) to several objectives can be done in many different ways. One possible approach is to introduce u(e) = maxs=1,…,M (gs(e)} and define the generalized loss function (GLF) as

[(

)] 

MGLF ( x ) = E θ  u e( x , θ) 

© 2003 by CRC Press LLC

2

(50.30)

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This generalization is meaningful, since u(e) = max s =1,K, M {g s (e)} is a scalar, and for the proposed scaling either u(·) > 0, or it is equal to zero if all the performances assume their target values SiT . Since (50.27) and (50.28) are less or equal to 1 any time SiL ≤ y i (e) ≤ SUi , then e = e(x, θ) belongs to A (the acceptability region in the e-space), if u(e) < 1. Let us use the complementary indicator function φ F (u(e)) = 1, if u(e) ≥ 1, i.e., e ∉ A (or θ ∉Aθ (x)) (failure) and equal to zero otherwise. Maximization of the parametric yield Y(x) is equivalent to the minimization of the probability of failures F(x) = 1–Y(x), which can be forulmated as the following minimization process, w.r.t. x

{

{

}

minimize F ( x ) = P θ ∉ Aθ ( x ) =

∫

(

(50.31)

)]}

[ (

)

φ F u( x , θ) fθ (θ)dθ = E θ φ F u( x , θ) t

R

The scalar “step” function φF (·) (where the argument is also scalar function u(e) = max1, K, M {g s (e)}), can now be generalized into a scalar weight function w(·), in the same spirit as in the Zadeh fuzzy set theory [62, 63]. For further generalization, the original p.d.f. fθ (θ) used in (50.31) is parametrized, multiplying θ by the smoothing parameters β to control the dispersion of e, which leads to the following optimization problem, utilizing a generalized measure M w (x , β)

{

))}}

{ ((

minimize M w ( x , β) = E θ w u e( x , βθ)

(50.32)

where u(e(x,βθ)) = maxs=1,…,M {gs (e(x,βθ))}. If 0 ≤ w(·) ≤ 1, Mw(·) corresponds to the probability measure of fuzzy event introduced by Zadeh [63]. The choice of w(·) and b leads to different optimization problems and different algorithms for yield/variability optimization. The standard yield optimization problem results if w(α) = φ F (α) and β = 1 [Eq. (50.31)] [Fig. 50.20(a)]. Yield can be also approximately optimized indirectly, using a “smoothed” (e.g., sigmoidal) membership function w(α) [Fig. 50.20(e)]. For variability minimization, we have a whole family of possible approaches: (1) The generalized Taguchi approach with w(α) = α2 [see (50.30)] and β = 1 [see Fig. 50.20(c)]. (2) If w(α) = α and β = 1 is kept constant, we obtain a statistical mini-max problem, since the expected value of the max function is used; this formulation will also lead to performance variability reduction. (3) If w(α) is piecewise constant [Fig. 50.20(d)], the approach is equivalent to the income index maximization with separate quality classes, introduced in [28], and successfully used there for the increase of the percentage of circuits belonging to the best classes {i.e., those characterized by small values of u(e)); this approach also reduces variability of circuit performance functions. For all the cases, optimization is performed using the w(α)

1

1

pass 0

fail α

1

1 fail

w(α)

α

11

(e)

1

α

1

α

w(α) α

fail 1

FIGURE 50.20 Various cases of the weight function w(α).

© 2003 by CRC Press LLC

α

fail

(c)

pass

pass 1 (d)

pass

fail

1

w(α) = α2

(b)

w(α)

0

1

pass

(a) 1

w(α)

α

αi (f)

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vc1

vc1

vc2

vc2

vc1 vc2 vc1 vi

c

vc2

vc1

vc1

vc2

vc2

− + vc2 vc1

c

vo

c

−

−

+

+

vc2

vc2

vc1

vc1

c

vc2 vc1

vc2

vc2

vc1

vc1

FIGURE 50.21 The MOSFET-C bandpass filter optimized in Example 1.

proposed SA approach. The smoothed functional gradient formulas (50.25) or (50.26) have to be used, in general, since the “discrete-circuit” type gradient formulas are valid only for a limited number of situations. Example 1 Performance Variability Minimization for a MOSFET-C Filter The objective of this example [31] was to reduce performance variability and to tune to target values the performances of the MOSFET-C filter in Fig. 50.21. The MOSFETS are used in groups composed of four transistors implementing equivalent resistors with improved linearity. Design specifications are f0, the center frequency, with the SL, ST, SU values specified as {45, 50, 55} kHz; H0, the voltage gain at f0, with the specs {15, 20, 25} dB; and Q, the pole quality factor, with the specs {8, 10, 12}. The Taguchi-like “ontarget” design and tuning was performed by minimizing the generalized measure (50.32) with w(x) = x2, using the SA approach with convolution smoothing, since the designable and random parameters are in different (sub)spaces. The circuit has the total number of 90 transistors so its direct optimization using transistor-level simulation would be too costly. Therefore, in [31] the operational amplifiers (opamps) shown in Fig. 50.21 were modeled by a statistical macromodel, representing the most relevant op-amp characteristics: DC gain A0, output resistance R0, and the -20 dB/dec frequency roll-off. Transistor model parameters were characterized by a statistical model developed in [8], based on 6 common factors (see Section 50.3): tox (oxide thickness), ∆Ln, ∆Lp (length reduction), NSUB,n, NSUB,p (substrate doping) and xjp (junction depth). All other transistor model parameters were calculated from the 6 common factors using second-order regression formulas developed in [8]. The major difficulty was to create statistical models of the op-amp macromodel parameters A0, R0, and f3 dB as the functions of the 6 common factors listed previously. A special extraction procedure (similar in principle to the model of factor analysis [20]) was developed and the relevant models created. Perfect matching between the transistor model parameter of the 22 transistors of each of the op-amps was assumed for simplicity20 (correlational dependencies 20

A more sophisticated model, taking the mismatches into account, was later proposed in [32].

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between individual parameters for individual transistors were maintained using the statistical mode of [8], described earlier). Moreover, perfect matching between the three macromodels (for the 3 op-amps) was also assumed. Mismatches between the threshold voltages and Kp (gain) coefficients of all the transistors in Fig. 50.21 were taken into account, introducing 48 additional noise parameters. So, including the 6 global noise parameters discussed previously, the overall number of θ parameters was 54. Moreover, it was found that even if a large number of noise parameters had small individual effect, their total contributions was significant, so, no meaningful reduction of the dimension of the θ-space was justified. Because of that, it was diffcult to use approximating models in the θ-space, and even more difficult in the joint (x , θ) space of 7 + 54 = 61 parameters. Therefore, no approximation was used. The Monte Carlo studies showed that the proposed statistical macromodel provided quite reasonably statistical accuracy for f0 (less than 1% errors for both the mean and the standard deviation), and less than 9.5% errors for both, H0 and Q. The macromodel-based analysis was about 30 times faster than using the full device-level SPICE analysis. Twenty-five designable parameters were selected, including transistor channel length of the “resistor-simulating transistors,” 4 capacitors, and one of the gate voltages. Due to the designable parameter tracking for transistor quadruples, the actual vector of optimized parameters was reduced to 7: x = (VGs , C1, C2, L2, L3, L4, L5), where VG2 denotes the gate voltage, and Ci , Lj are capacitor and channel length values, respectively. The original yield was 43.5% and relative standard deviations for H0, f0 and Q, were to 3.98%, 7.24%, and 22.06%, respectively, and all nominal values were close to their target values. After SA optimization with convolution smoothing involving 5% perturbations for each of the x parameters, and the total of about 240 circuit analyses, yield increased to 85.0%, and H0, f0, and Q relative standard deviations were reduced to 3.87%, 6.35%, and 13.91%, respectively. Therefore, the largest variability reduction (for Q) was about 37%, with simultaneous significant yield increase. The preceding example demonstrates a typical approach that has to be taken in the case of large analog circuits: the circuit has to be (hierarchically) macromodeled first21 and suitable statistical macromodels have to be created, including mismatch modeling.

50.5 Conclusion Several different techniques of statistical yield optimization were presented. Other approaches to yield estimation and optimization can be found, e.g., in [21] (process optimization), and in [15, 57, 59, 60, 61]. It was also shown that yield, variability minimization, Toguchi design, and other approaches can be generalized into one methodology called design for quality22 (DFQ). DFQ is a quickly growing area [30], where the major objective is not to maximize the parametric yield as the only design criterion (yield is often only vaguely defined), but to minimize the performance variability around the designer specified target performance values. This has been a subject of research for many years using a sensitivity-based approach, and most recently, using the Taguchi methodology, based on some of the techniques of Design of Experiements rather than on the use of sensitivities. To increase the efficiency of the (mostly manual) Taguchi techniques [30], some automated methods started to appear, such as the generalized methodology described previously, or the automated approach based on capability indices Cp /Cpk (used extensively in process quality control) proposed in [41]. Statistical design optimization is still an active research area, but several mature techniques have been already developed and practically applied to sophisticated industrial IC design. This is of great importance to the overall manufacturing cost reduction, circuit quality improvement, and shortening of the overall IC design cycle.

21 22

Behavioral models can also be used. Other approaches to yield generalization/Design for Quality were presented in [13, 28, 58].

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References [1] H. L. Abdel-Malek and J. W. Bandler, Yield optimization for arbitrary statistical discributions: part I — theory, IEEE Trans. Circuit Syst., CAS-27(4), pp. 245–253, April 1980. [2] K. J. Antreich and R. K Koblitz, Design centering by yield prediction, IEEE Trans. Circuits Systems, CAS-29, pp. 88–95, Feb. 1982. [3] P. Balaban and J. J. Golembeski, Statistical analysis for practical circuit design, IEEE Trans. on Circuits and Systems, CAS-22(2), pp. 100–108, Feb. 1975. [4] J. W. Bandler, Optimization of design tolerance using nonlinear programming, J. Optimization Theory and Applications, vol. 14, p. 99, 1974; also in Proc. Princeton Conf. Information Science and Systems, p. 655, Princeton, NJ, Feb. 1972. [5] J. W. Bandler and H. L. Abdel-Malek, Optical centering, tolerancing and yield determination via updated approximations and cuts, IEEE Trans. Circuits and Systems, CAS-25, pp. 853–871, 1978. [6] J. W. Bandler, P. C. Liu, and H. Tromp, A nonlinear programming approach to optimal design centering, tolerancing and tuning, IEEE Trans. CAS, CAS-23, p. 155, March 1976. [7] P. W. Becker and F. Jensen, Design of Systems and Circuits for Maximum Reliability or Maximum Production Yield, New York: McGraw-Hill 1977. [8] J. Chen and M. A. Styblinski, A systematic approach of statistical modeling and its application to CMOS circuits, in Proc. IEEE Int’l. Symposium on Circuits and Systems ’93, pp. 1805–1808, Chicago, May 1993. [9] P. Cox, P. Yang, S. S. Mahant-Shetti, and P. Chatterjee, Statistical modeling for efficient parametric yield estimation of MOS VLSI circuits, IEEE Trans. on Electron Devices, ED-32, pp. 471–478, Feb. 1985. [10] S. W. Director and G. D. Hatchel, The simplicial approximation to design centering, IEEE Trans. Circuits Syst., CAS-24(7), pp. 363–372, July 1977. [11] S. W. Director and G. D. Hatchel, A point basis for statistical design, in IEEE Proc., New York, 1978. ISCAS-78. [12] S. W. Director, W. Maly, and A. J. Strojwas, VLSI Design for Manufacturing: Yield Enhancement, Boston: Kluwer Academic Publishers, 1990. [13] P. Feldman and S. W. Director, Integrated circuit quality optimization using surface integrals, IEEE Trans. on CAD, 12(12), pp. 1868–1879, Dec. 1993. [14] P. H. Gill, W. Murray, and M. H. Wright, Practical Optimizations, San Diego: Academic Press, 1981. [15] D. E. Hocevar, P. F. Cox, and P. Yang, Parametric yield optimization for MOS circuit blocks, IEEE Trans. on Computer-Aided Design, 7(6), pp. 645–658, June 1988. [16] D. E. Hocevar, M. R. Lightner, and T. N. Trick, A study of variance reduction techniques of estimating circuit yields, IEEE Trans. on Computer-Aided Design CAD-2(3), pp. 180–192, July 1983. [17] A. Ilumoka, N. Maratos, and R. Spence, Variability reduction: statistically based algorithms for reduction of performance variability of electrical circuits, IEEE Proc., vol. 129, pt. G(4), pp. 169–180, Aug. 1982. [18] G. Kjellstrom and L. Taxen, Stochastic optimization in system design, IEEE Trans. Circuits Systems, CAS-28, pp. 702–715, July 1981. [19] G. Kjellstrom, L. Taxen, and P. O. Lindberg, Discrete optimization of digital filter using Gaussian adaptation and quadratic function minimization, IEEE Trans. on Circuits and Systems, CAS-34(10), pp. 1238–1242, Oct. 1987. [20] D. N. Lawley and A. E. Maxwell, Factor Analysis as a Statistical Method, New York: Elsevier, 1971. [21] K. K. Low and S. W. Director, An efficient methodology for building macromodels of IC fabrication processes, IEEE Trans. on Computer-Aided Design, 8(12), pp. 1299–1313, Dec. 1989. [22] W. Maly and A. J. Strojwas, Statistical simulation of IC manufacturing process, IEEE Trans. on CAD, CAD-1, July 1982. [23] C. Michael and M. Ismail, Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits, Boston: Kluwer Academic Publishers, 1993. © 2003 by CRC Press LLC

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[24] S. R. Nassif, A. J. Strojwas, and S. W. Director, FABRICS II. IEEE Trans. on CAD, CAD-3, pp. 40–46, Jan. 1984. [25] J. Ogrodzki, L. Opalski, and M. A. Styblinksi, Acceptability regions for a class of linear networks, in Proc. IEEE Int. Symp. on Circuits and Systems, Houston, TX, May 1980. [26] J. Ogrodzki and M. A. Styblinski, Optimal tolerancing, centering and yield optimization by OneDimensional Orthogonal Search (ODOS) technique, in Proc. Eur. Conf. Circ. Theory and Design (ECCTD), vol. 2, pp. 480–485, Warsaw, Poland, Sept. 1980. [27] L. Opalski, M. A. Styblinski, and J. Ogrodzki, An orthogonal search approximation to acceptability regions and its application to tolerance problems, in Proc. Conf. SPACECAD, Bologna, Italy, Sept. 1979. [28] L. J. Opalski and M. A. Styblinski, Generalization of yield optimization problem: Maximum income approach, IEEE Trans. on Comp. Aided Design of ICAS, CAD-5(2), pp. 346–360, April 1986. [29] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, Matching properties of MOS transistors, IEEE J. of Solid State Circuits, 24, pp. 1334–1362, Oct. 1989. [30] M. S. Phadke, Quality Engineering Using Robust Design, Englewood Cliff, NJ: Prentice Hall, 1989. [31] M. Qu and M. A. Styblinski, Hierarchical approach to statistical performance improvement of CMOS analog circuits, in SRC TECHCON ’93, Atlanta, GA, Sept. 1993. [32] M. Qu and M. A. Styblinski, Statistical characterization and modeling of analog functional blocks, in Proc. IEEE Int. Symp. on Circuits and Systems, London, May–June 1994. [33] H. Robins and S. Monro, A stochastic approximation method, Annal. Math. Stat., 22, pp. 400–407, 1951. [34] R. Y. Rubinstein, Simulation and the Monte Carlo Method, New York: John Wiley & Sons, 1981. [35] A. Ruszczynski and W. Syski, Stochastic approximation algorithm with gradient averaging for constrained problems, IEEE Trans. Automatic Control, AC-28, pp. 1097–1105, Dec. 1983. [36] K. Singhal and J. F. Pinel, Statistical design centering and tolerancing using parametric sampling, IEEE Trans. Circuits Syst., CAS-28, pp. 692–702, July 1981. [37] R. S. Soin and R. Spence, Statistical exploration approach to design centering, in Proc. Inst. Elect. Eng., vol. 127, part G, pp. 260–263, 1980. [38] J. C. Spall, Multivariate stochastic approximation using a simultaneous perturbation gradient approximation, IEEE Trans. on Automatic Control, 37(3), 1992. [39] R. Spence and R. S. Soin, Tolerance Design of Electronic Circuits, Electronic Systems Engineering Series, Reading, MA, Addison-Wesley, 1988. [40] W. Strasz and M. A. Styblinski, A second derivative Monte Carlo optimization of the production yield, in Proc. European Conf. Circuit Theory and Design, vol. 2, pp. 121–131, Warsaw, Poland, Sept. 1980. [41] M. A. Styblinski and S. A. Aftab, IC variability minimization using a new Cp and Cpk based variability/performance measure, in Proc. IEEE Int. Symp. on Circuits and Systems, London, May–June 1994. [42] M. A. Styblinski, Estimation of yield and its derivatives by Monte Carlo sampling and numerical integration in orthogonal subspaces, in Proc. Eur. Conf. Circ. Theory and Design (ECCTD), vol. 2, pp. 474–479, Warsaw, Poland, Sept. 1980. [43] M. A. Styblinski, Problems of yield gradient estimation for truncated probability density functions, IEEE Trans. on Comp. Aided Design of ICAS, CAD-5(1), pp. 30–38, Jan. 1986 (special issue on statistical design of VLSI circuits). [44] M. A. Styblinski, Generalized formulation of yield, variability, minimax and Taguchi circuit optimization problems, Microelectron Reliab., 34(1), 31–37, 1994. [45] M. A. Styblinski and S. A. Aftab, Combination of interpolation and self organizing approximation techniques — a new approach to circuit performance modeling, IEEE Trans. on Computer-Aided Design, 12(11), pp. 1775–1785, Nov. 1993. [46] M. A. Styblinski, J. Ogrodzki, L. Opalski, and W. Strasz, New methods of yield estimation and optimization and their application to practical problems (invited paper), in Proc. Int. Symp. on Circuits and Systems, Chicago, IL, 1981. © 2003 by CRC Press LLC

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[47] M. A. Styblinski and L. J. Opalski, A random perturbation method for IC yield optimization with deterministic process parameters, in Proc. IEEE Int. Symp. on Circuits and Systems, pp. 977–980, Montreal, May 7–10, 1984. [48] M. A. Styblinski and L. J. Opalski, Algorithms and software tools for IC yield optimization based on fundamental fabrication parameters, IEEE Trans. on Comp. Aided Design of ICAS, CAD-5(1), pp. 79–89, Jan. 1986 (special issue on statistical design of VLSI circuits). [49] M. A. Styblinski and A. Ruszczynski, Stochastic approximation approach to production yield optimizaion, in Proc. 25th Midwest Symp. on Circuits and Systems, Houghton, MI, Aug. 30–31, 1982. [50] M. A. Styblinski and A. Ruszczynski, Stochastic approximation approach to statistical circuit design, Electron, Lett., 19(8), 300–302, April 14, 1983. [51] M. A. Styblinski and W. Strasz, A second derivative Monte Carlo optimization of the production yield, in Proc. ECCTD ’80, vol. 2, pp. 121–131, Warsaw, Sept. 1980. [52] M. A. Styblinski and T.-S. Tang, Experiments in nonconvex optimization: stochastic approximation with function smoothing and simulated annealing, Neural Networks J., 3(4), 1990. [53] M. A. Styblinski and J. C. Zhang, Orthogonal array approach to gradient based yield optimization, in Proc. Int. Symp. on Circuits and Systems, pp. 424–427, New Orleans, LA, May 1990. [54] K. S. Tahim and R. Spence, A radial exploration algorithm for the statistical analysis of linear circuits, IEEE Trans. on CAS, CAS-27(5), pp. 421–425, May 1980. [55] T.-S. Tang and M. A. Styblinski, Yield optimization for non-differentiable density functions using convolution techniques, IEEE Trans. on CAD of IC and Systems, 7(10), pp. 1053–1067, 1988. [56] W. J. Welch, T.-K.Yu, S. M. Kang, and J. Sacks, Computer experiments for quality control by parameter design, J. of Quality Technol., 22(1), pp. 15–22, Jan. 1990. [57] P. Yang, D. E. Hocevar, P. F. Cox, C. Machala, and P. K. Chatterjee, An integrated and efficient approach for MOS VLSI statistical circuit design, IEEE Trans. CAD of VLSI Circ. Syst., CAD-5, pp. 5–14, Jan, 1986. [58] D. L. Young, J. Teplik, H. D. Weed, N. T. Tracht, and A. R. Alvarez, Application of statistical design and response surface methods to computer-aided VLSI device design II: desirability functions and Taguchi methods, IEEE Trans. on Computer-Aided Design, 10(1), pp. 103–115, Jan. 1991. [59] T.-K. Yu, S. M. Kang, I. N. Hajj, and T. N. Trick, Statistical performance modeling and parametric yield estimation of MOS VLSI, IEEE Trans. CAD of VLSI Circ. Syst., CAD-6(6), pp. 1013–1022, Nov. 1987. [60] T. K. Yu, S. M. Kang, I. N. Hajj, and T. N. Trick, iEDISON: an interactive statistical design tool for MOS VLSI circuits, in IEEE Int. Conf. on Computer-Aided Design, ICCAD-88, pp. 20–23, Santa Clara, CA, Nov. 7–10, 1988. [61] T. K. Yu, S. M. Kang, J. Sacks, and W. J. Welch, Parametric yield optimization of MOS integrated circuits by statistical modeling of circuit performances, Technical Rep. 27, Dept. of Statistics, University of Illinois, Champaign, IL, July 1989. [62] L. A. Zadeh, Fuzzy sets, Inform. Control, 8, pp. 338–353, 1965. [63] L. A. Zadeh, Probability measures of fuzzy events, J. Math. Anal. Appl., 23, pp. 421–427, 1968.

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51 Physical Design Automation1 51.1 51.2 51.3 51.4 51.5

Introduction Very Large Scale Integration Design Cycle Physical Design Cycle Design Styles Partitioning Classification of Partitioning Algorithms • The Kernighan-Lin Partitioning Algorithm

51.6 51.7

Other Partitioning Algorithms Placement Classification of Placement Algorithms • Simulated Annealing Placement Algorithm • Other Placement Algorithms

51.8 Routing 51.9 Classification of Global Routing Algorithms 51.10 Classification of Detailed Routing Algorithms Lee’s Algorithm for Global Routing • Greedy Channel Router for Detailed Routing • Other Routing Algorithms

51.11 Compaction

Naveed Sherwani Intel Corporation

Classification of Compaction Algorithms • ShadowPropagation Algorithm for Compaction • Other Compaction Algorithms

51.12 Summary

51.1 Introduction In the last three decades integrated circuit (IC) fabrication technology has evolved from integration of a few transistors in small scale integration (SSI) to integration of several million transistors in very large scale integration (VLSI). This phenomenal progress has been made possible by automating the process of design and fabrication of VLSI chips. Integrated circuits consist of a number of electronic components, built by layering several different materials in a well-defined fashion on a silicon base called a wafer. The designer of an IC transforms a circuit description into a geometric description, which is known as a layout. A layout consists of a set of planar geometric shapes in several layers. The layout is then checked to ensure that it meets all the design requirements. The result is a set of design files in a particular unambiguous representation, known as an intermediate form, that describes the layout. The design files are then converted into pattern 1

The material presented in this chapter was adapted from the author’s book Algorithms for VLSI Physical Design Automation, Boston: Kluwer Academic Publishers, 1993, with editorial changes for clarity and continuity. Copyright permission has been obtained from Kluwer Academic Publishers.

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generator files, which are used to produce patterns called masks by an optical pattern generator. During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. The component formation requires very exacting details about geometric patterns and separation between them. The process of converting the specifications of an electrical circuit into a layout is called the physical design. It is an extremely tedious and error-prone process because of the tight tolerance requirements and the minuteness of the individual components. Currently, the smallest geometric feature of a compo­ nent can be as small as 0.35 µm (1 µm = 1.0 × 10−6 m). However, it is expected that the feature size can be reduced to 0.1 µm within 5 years. This small feature size allows fabrication of as many as 4.5 million transistors on a 25 × 25 mm maximum size chip. Due to the large number of components and the exacting details required by the fabrication process, the physical design is not practical without the help of computers. As a result, almost all phases of physical design extensively use computer-aided design (CAD) tools and many phases have already been partially or fully automated. This automation of the physical design process has increased the level of integration, reduced the turnaround time, and enhanced chip performance. VLSI physical design automation is essentially the study of algorithms related to the physical design process. The objective is to study optimal arrangements of devices on a plane (or in a three-dimensional space) and efficient interconnection schemes between these devices to obtain the desired functionality. Because space on a wafer is very expensive real estate, algorithms must use the space very efficiently to lower costs and improve yield. In addition, the arrangement of devices plays a key role in determining the performance of a chip. Algorithms for physical design must also ensure that all the rules required by the fabrication are observed and that the layout is within the tolerance limits of the fabrication process. Finally, algorithms must be efficient and should be able to handle very large designs. Efficient algorithms not only lead to fast turnaround time, but also permit designers to iteratively improve the layouts. With the reduction in the smallest feature size and increase in the clock frequency, the effect of electrical parameters on physical design will play a more dominant role in the design and development of new algorithms. In this section, we present an overview of the fundamental concepts of VLSI physical design automa­ tion. Different design styles are discussed in Section 51.4. Section 51.2 discusses the design cycle of a VLSI circuit. In Section 51.3 different steps of the physical design cycle are discussed. The rest of the sections discuss each step of the physical design cycle.

51.2 Very Large Scale Integration Design Cycle Starting with a formal specification, the VLSI design cycle follows a series of steps and eventually produces a packaged chip. A flow chart representing a typical design cycle is shown in Fig. 51.1. 1. System Specification: The specifications of the system to be designed are exactly specified here. This necessitates creating a high-level representation of the system. The factors to be considered in this process include performance, functionality, and the physical dimensions. The choice of fabrication technology and design techniques are also considered. The end results are specifications for the size, speed, power, and functionality of the VLSI system to be designed. 2. Functional Design: In this step, behavioral aspects of the system are considered. The outcome is usually a timing diagram or other relationships between subunits. This information is used to improve the overall design process and to reduce the complexity of the subsequent phases. 3. Logic Design: In this step, the functional design is converted into a logical design, typically represented by boolean expressions. These expressions are minimized to achieve the smallest logic design which conforms to the functional design. This logic design of the system is simulated and tested to verify its correctness. 4. Circuit Design: Here, the boolean expressions are converted into a circuit representation by taking into consideration the speed and power requirements of the original design. The electrical behavior

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System Specification

Functional Design

Logic Design

X = (AB*CD)+(A+D)+(A(B+C)) Y = (A(B+C)+AC+D+A(BC+D))

Circuit Design

Physical Design

Fabrication

Packaging

FIGURE 51.1 Design process steps.

of the various components are also considered in this phase. The circuit design is usually expressed in a detailed circuit diagram. 5. Physical Design: In this step, the circuit representation of each component is converted into a geometric representation. This representation is in fact a set of geometric patterns which perform the intended logic function of the corresponding component. Connections between different © 2003 by CRC Press LLC

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components are also expressed as geometric patterns. As stated earlier, this geometric representa­ tion of a circuit is called a layout. The exact details of the layout also depend on design rules, which are guidelines based on the limitations of the fabrication process and the electrical properties of the fabrication materials. Physical design is a very complex process; therefore, it is usually broken down into various substeps in order to handle the complexity of the problem. In fact, physical design is arguably the most time-consuming step in the VLSI design cycle. 6. Design Verification: In this step, the layout is verified to ensure that the layout meets the system specifications and the fabrication requirements. Design verification consists of design rule checking and circuit extraction. Design rule checking (DRC) is a process which verifies that all geometric patterns meet the design rules imposed by the fabrication process. After checking the layout for design rule violations and removing them, the functionality of the layout is verified by circuit extraction. This is a reverse engineering process and generates the circuit representation from the layout. This reverse engineered circuit representation can then be compared to the original circuit representation to verify the correctness of the layout. 7. Fabrication: After verification, the layout is ready for fabrication. The fabrication process consists of several steps: preparation of wafer, deposition, and diffusion of various materials on the wafer according to the layout description. A typical wafer is 10 cm in diameter and can be used to produce between 12 and 30 chips. Before the chip is mass produced, a prototype is made and tested. 8. Packaging, Testing and Debugging: In this step, the chip is bricated and diced in a fabrication facility. Each chip is then packaged and tested to ensure that it meets all the design specifications and that it functions properly. Chips used in printed circuit boards (PCBs) are packaged in a dualin-line package (DIP) or pin grid array (PGA). Chips which are to be used in a multi-chip module (MCM) are not packaged because MCMs use bare or naked chips. The VLSI design cycle is iterative in nature, both within a step and between steps. The representation is iteratively improved to meet system specifications. For example, a layout is iteratively improved so that it meets the timing specifications of the system. Another example may be detection of design rule violations during design verification. If such violations are detected, the physical design step needs to be repeated to correct the error. The objective of VLSI CAD tools is to minimize the number of iterations and thus reduce the time-to-market.

51.3 Physical Design Cycle Physical design cycle converts a circuit diagram into a layout. This is accomplished in several steps such as partitioning, floorplanning, placement, routing, and compaction, as shown in Fig. 51.2. 1. Partitioning: The complex task of chip layout is divided into several smaller tasks. A chip may contain several million transistors. Layout of the entire circuit cannot be handled due to the limitation of memory space as well as computation power available. Therefore, it is normally partitioned by grouping the components into blocks (subcircuits/modules). The actual partition­ ing process considers many factors such as size of the blocks, number of blocks, and number of interconnections between the blocks. The output of partitioning is a set of blocks along with the interconnections required between blocks. The set of interconnections required is referred to as a netlist. Figure 51.2(a) shows that the input circuit has been partitioned into three blocks. In large circuits the partitioning process is hierarchical and at the topmost level a chip may have between 5 and 25 blocks. Each module is then partitioned recursively into smaller blocks. 2. Placement: In this step, good layout alternatives are selected for each block, as well as the entire chip. The area of each block can be calculated after partitioning and is based approximately on the number and the type of components in that block. The actual rectangular shape of the block, which is determined by the aspect ratio may, however, be varied within a prespecified range. Floorplanning is a critical step, as it sets up the groundwork for a good layout. However, it is

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Circuit Design Physical Design

cutline 2

(a)

Partitioning

(b)

Floorplanning & Placement

(c)

Routing

(d)

Compaction

cutline 1

Fabrication

FIGURE 51.2 Physical design cycle.

computationally quite hard. Very often the task of floorplan layout is done by a design engineer, rather than by a CAD tool. This is sometimes necessary as the major components of an IC are often intended for specific locations on the chip. The placement process determines the exact positions of the blocks on the chip, so as to find a minimum area arrangement for the blocks that allows completion of interconnections between the blocks. Placement is typically done in two phases. In the first phase an initial placement is created. In the second phase the initial placement is evaluated and iterative improvements are made until the layout has minimum area and conforms to design specifications. Figure 51.2(b) shows that three blocks have been placed. It should be noted that some space between the blocks is intentionally left empty to allow interconnections between blocks. Placement may lead to unroutable design, i.e., routing may not be possible in the space provided. Thus, another iteration of placement is necessary. To limit the number of iterations of the placement algorithm, an estimate of the required routing space is used during the placement phase. A good routing and circuit performance heavily depend on a good placement algorithm. © 2003 by CRC Press LLC

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This is due to the fact that once the position of each block is fixed, very little can be done to improve the routing and the overall circuit performance. 3. Routing: In this step, the objective is to complete the interconnections between blocks according to the specified netlist. First, the space not occupied by the blocks (called the routing space) is partitioned into rectangular regions called channels and switchboxes. The goal of a router is to complete all circuit connections using the shortest possible wire length and using only the channels and switchboxes. This is usually done in two phases, referred to as the global routing and detailed routing phases. In global routing, connections are completed between the proper blocks of the circuit disregarding the exact geometric details of each wire and pin. For each wire, the global router finds a list of channels which are to be used as a passageway for that wire. In other words, global routing specifies the “loose route” of a wire through different regions in the routing space. Global routing is followed by detailed routing, which completes point-to-point connections between pins on the blocks. Loose routing is converted into exact routing by specifying geometric information such as width of wires and their layer assignments. Detailed routing includes channel routing and switchbox routing. Routing is a very well-studied problem and several hundred articles have been published about all its aspects. Because almost all problems in routing are computa­ tionally hard, the researchers have focused on heuristic algorithms. As a result, experimental evaluation has become an integral part of all algorithms and several benchmarks have been standardized. Due to the nature of the routing algorithms, complete routing of all the connections cannot be guaranteed in many cases. As a result, a technique called rip-up and reroute is used, which basically removes troublesome connections and reroutes them in a different order. The routing phase of Fig. 51.2(c) shows that all the interconnections between three blocks have been routed. 4. Compaction: In this step, the layout is compressed in all directions such that the total area is reduced. By making the chip smaller, wire lengths are reduced, which in turn reduces the signal delay between components of the circuit. At the same time, a smaller area may imply more chips can be produced on a wafer, which in turn reduces the cost of manufacturing. However, the expense of computing time mandates the extensive compaction is used only when large quantities of ICs are produced. Compaction must ensure that no rules regarding the design and fabrication process are violated during the process. The final diagram in Fig. 51.2(d) shows the compacted layout. Physical design, like VLSI design, is iterative in nature, and many steps such as global routing and channel routing are repeated several times to obtain a better layout. In addition, the quality of results obtained in a step depends on the quality of solutions obtained in earlier steps. For example, a poor quality placement cannot be “cured” by high quality routing. As a result, earlier steps have more influence on the overall quality of the solution. In this sense partitioning, floorplanning, and placement problems play a more important role in determining the area and chip performance, as compared to routing and compaction. Because placement may produce an “unroutable” layout, the chip might need to be replaced or repartitioned before another routing is attempted. In general, the whole design cycle may be repeated several times to accomplish the design objectives. The complexity of each step varies depending on the design constraints as well as the design style used.

51.4 Design Styles Even after decomposing physical design into several conceptually easier steps, it has been shown that each step is computationally very hard. Market requirements demand a quick time-to-market and high yield. As a result, restricted models and design styles are used in order to reduce the complexity of physical design. This practice began in the late 1960s and led to the development of several restricted design styles [8]. The most general form of layout is called the full-custom design style, in which the circuit is partitioned into a collection of subcircuits according to some criteria such as functionality of each subcircuit. In this © 2003 by CRC Press LLC

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Pad

Metal 1

Via

Metal 2

Data path PLA

I/O

ROM/RAM

Random logic A/D converter

FIGURE 51.3 Full-custom structure.

design style, each subcircuit is called a functional block or simply a block. The full-custom design style allows functional blocks to be of any size. Figure 51.3 shows an example of very simple circuit with few blocks. Internal routing in each block is not shown for the sake of clarity. Blocks can be placed at any location on the chip surface without restriction. In other words, this style is characterized by the absence of any constraints on the physical design process. This design style allows for very compact designs. However, the process of automating a full-custom design style has a much higher complexity than other restricted models. For this reason, it is used only when final design must have a minimum area and designing time is less of a factor. The automation process for a full-custom layout is still a topic of intensive research. Some phases of physical design of a full-custom chip may be done manually to optimize the layout. Layout compaction is a very important aspect in full-custom. The rectangular solid boxes around the boundary of the circuit are called I-O pads. Pads are used to complete interconnections between chips or interconnections between chip and the board. The space not occupied by blocks is used for routing of interconnecting wires. Initially all the blocks are placed within the chip area, with the objective of minimizing the total area. However, enough space must be left between the blocks to complete the routing. Usually several metal layers are used for routing interconnections. Currently, two metal layers are common for routing and the three-metal layer process is gaining acceptance, as the fabrication costs become more feasible. The routing area needed between the blocks becomes increasingly smaller as more routing layers are used. This is because some routing is done on top of the transistors in the additional metal layers. If all the routing can be done on top of the transistors, the total chip area is determined by the area of the transistors. In a hierarchical design of circuit each block in full-custom design may be very complex and may consist of several subblocks, which in turn may be designed using the full-custom design style or other design styles. It is easy to see that because any block is allowed to be placed anywhere on the chip, the problem of optimizing area and interconnection of wires becomes difficult. Full-custom design is very © 2003 by CRC Press LLC

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time consuming; thus, the method is inappropriate for very large circuits, unless performance is of utmost importance. Full-custom is usually used for the layout of microprocessors. A more restricted design style is called the standard cell design style. The design process in standard cell design style is simpler than a full-custom design style. Standard cell methodology considers the layout to consist of rectangular cells of the same height. Initially, a circuit is partitioned into several smaller blocks, each of which is equivalent to some predefined subcircuit (cell). The functionality and the electrical characteristics of each predefined cell are tested, analyzed, and specified. A collection of these cells is called a cell library, usually consisting of 200 to 400 cells. Terminals on cells may be located either on the boundary or in the center of the cells. Cells are placed in rows and the space between two rows is called a channel. These channels are used to perform interconnections between cells. If two cells to be interconnected lie in the same row or in adjacent rows, then the channel between the rows is used for interconnection. However, if two cells to be connected lie in two nonadjacent rows, then their intercon­ nection wire passes through the empty space between any two cells, or feedthrough. Standard cell design is well suited for moderate-size circuits and medium production volumes. Physical design using standard cells is simpler as compared to full-custom and efficient using modern design tools. The standard cell design style is also widely used to implement the “random logic” of the fullcustom design, as shown in Fig. 51.3, While standard cell designs are developed more quickly, a substantial initial investment is needed in the development of the cell library, which may consist of several hundred cells. Each cell in the cell library is “handcrafted” and requires a highly skilled design engineer. Each type of cell must be created with several transistor sizes. Each cell must then be tested by simulation and its performance must be characterized. A standard cell design usually takes more area than a full-custom or a hand-crafted design. However, as more metal layers become available for routing, the difference in area between the two design styles will gradually be reduced. The gate array design style is a simplified version of the standard cell design style. Unlike the cells in standard cell designs, all the cells in gate array are identical. The entire wafer is prefabricated with an array of identical gates or cells. These cells are separated by both vertical and horizontal spaces called vertical and horizontal channels. The circuit design is modified such that it can be partitioned into a number of identical blocks. Each block must be logically equivalent to a cell on the gate array. The name “gate array” signifies the fact that each cell may simply be a gate, such as a three-input NAND gate. Each block in the design is mapped or placed onto a prefabricated cell on the wafer during the partition­ ing/placement phase, which is reduced to a block-to-cell assignment problem. The number of partitioned blocks must be less than or equal to that of the total number of cells on the wafer. Once the circuit is partitioned into identical blocks, the task is to make the interconnections between the prefabricated cells on the wafer using horizontal and vertical channels to form the actual circuit. The uncommitted gate array is taken into the fabrication facility and routing layers are fabricated on top of the wafer. The completed wafer is also called a customized wafer. This simplicity of gate array design is gained at the cost of rigidity imposed upon the circuit both by the technology and the prefabricated wafers. The advantage of gate arrays is that the steps involved for creating any prefabricated wafer are the same, and only the last few steps in the fabrication process actually depend on the application for which the design will be used. Hence, gate arrays are cheaper and easier to produce than full-custom or standard cell. Similar to standard cell design, gate array is also a nonhierarchical structure. The gate array architecture is the most restricted form of layout. This also means it is the simplest for algorithms to work with. For example, the task of routing in gate array is to determine if a given placement is routable. The routability problem is conceptually simpler as compared to the routing problem in standard cell and full-custom design styles. The choice of design style for a particular circuit depends on many factors such as functionality of the chip, time-to-market, and the volume of chips to be manufactured. Full-custom is typically reserved for high-performance, high-volume chips, while standard cells are used for moderate performance, where the cost of full-custom cannot be justified. Gate arrays are typically used for low-performance, low-cost applications. A design style may be applicable to the entire chip or a block of the chip.

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Irrespective of the choice of the design style, all steps of the physical design cycle need to be carried out. However, the complexity, the effectiveness, and the algorithms used differ considerably depending on the design style. The following sections discuss algorithms for different phases of the physical design cycle.

51.5 Partitioning As stated earlier, the basic purpose of partitioning is to simplify the overall design process. The circuit is decomposed into several subcircuits to make the design process manageable. This section considers the partitioning phase of the physical design cycle, study constraints, and objective functions for this problem and presents efficient algorithms. Given a circuit, the partitioning problem is to decompose it into several subcircuits subject to con­ straints while optimizing a given objective function. The constraints for the partitioning problem include area constraints and terminal constraints. Area constraints are user specified for design optimization and terminal count depends on the area and aspect ratio of the block. In particular, the terminal count for a partition is given by the ratio of the perimeter of the partition to the terminal pitch. The minimum spacing between two adjacent terminals is called terminal pitch and is determined by the design rules. The objective functions for a partitioning problem include the minimization of the number of nets that cross the partition boundaries, and the minimization of the maximum number of times a path crosses the partition boundaries. The constraints and the objective functions used in the partitioning problem vary depending upon the partitioning level and the design style used. The actual objective function and constraints chosen for the partitioning problem may also depend on the specific problem. The number of nets that connect a partition to other partitions cannot be greater than the terminal count of the partition. In addition, the number of nets cut by partitioning should be minimized to simplify the routing task. The minimization of the number of nets cut by partitioning is one of the most important objectives in partitioning. A disadvantage of the partitioning process is that it may degrade the performance of the final design. During partitioning, critical components should be assigned to the same partition. If such an assignment is not possible, then appropriate timing constraints must be generated to keep the two critical components close together. Usually, several components, forming a critical path, determine the chip performance. If each component is assigned to a different partition, the critical path may be too long. Minimizing the length of critical paths improves system performance. After a chip has been partitioned, each of the subcircuits must be placed on a fixed plane and the nets between all the partitions must be interconnected. The placement of the subcircuits is done by the placement algorithms and the nets are routed by using routing algorithms.

Classification of Partitioning Algorithms The partitioning algorithms also may be classified based on the nature of the algorithms, of which two types exist: deterministic algorithms and probabilistic algorithms. Deterministic algorithms produce repeatable or deterministic solutions. For example, an algorithm which make use of deterministic func­ tions will always generate the same solution for a given problem. On the other hand, the probabilistic algorithms are capable for producing a different solution for the same problem each time they are used, as they make use of some random functions. The partitioning algorithms also may be classified on the basis of the process used for partitioning. Thus, we have group migration algorithms, simulated annealing and evolution-based algorithms, and other partitioning algorithms. The group migration algorithms [9, 17] start with some partitions, usually generated randomly, and then move components between partitions to improve the partitioning. The group migration algorithms are quite efficient. However, the number of partitions must be specified, which is usually not known

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when the partitioning process starts. In addition, the partitioning of an entire system is a multilevel operation, and the evaluation of the partitions obtained by the partitioning depends on the final inte­ gration of partitions at all levels, from the basic subcircuits to the whole system. An algorithm used to find a minimum cut at one level may sacrifice the quality of cuts for the following levels. The group migration method is a deterministic method that is often trapped at a local optimum and cannot proceed further. The simulated annealing/evolution algorithms [3, 10, 18, 26] carry out the partitioning process by using a cost function, which classifies any feasible solution, and a set of moves, which allows movement from solution to solution. Unlike deterministic algorithms, these algorithms accept moves which may adversely affect the solution. The algorithm starts with a random solution and as it progresses, the proportion of adverse moves decreases. These degenerate moves act as a safeguard against entrapment in local minima. These algorithms are computationally intensive as compared to group migration and other methods. Among all the partitioning algorithms, the group migration and simulated annealing/evolution has been the most successful heuristics for partitioning problems. The group migration and simulated annealing/evolution methods are most widely used, and extensive research has been carried out in these two types of algorithms.

The Kernighan-Lin Partitioning Algorithm The Kernighan-Lin (K-L) algorithm is a bisectioning algorithm. It starts by initially partitioning the graph G = (V, E) into two subsets of equal size. Vertex pairs are exchanged across the bisection if the exchange improves the cutsize. The preceding procedure is carried out iteratively until no further improvement can be achieved. The basic idea of the K-L algorithm is illustrated with the help of an example before presenting the algorithm formally. Consider the example given in Fig. 51.4(a). The initial partitions are A = {1, 2, 3, 4} B = {5, 6, 7, 8} Notice that the initial cutsize is 9. The next step of the K-L algorithm is to choose a pair of vertices whose exchange results in the largest decrease of the cutsize or results in the smallest increase, if no decrease is possible. The decrease of the cutsize is computed using gain values D(i) of vertices vi . The gain of a vertex vi is defined as D(i ) = inedge(i ) − outedge(i )

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TABLE 51.1

Log of the Vertex Exchanges

i

Vertex Pair

g(i)

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— (3, 5) (4, 6) (1, 7) (2, 8)

— 3 5 −6 −2

— 3 8 2 0

9 6 1 7 9

where inedge(i) is the number of edges of vertex i that do not cross the bisection boundary and outedge(i) is the number of edges that cross the boundary. The amount by which the cutsize decreases, if vertex vi changes over to the other partition, is represented by D(i). If vi and vj are exchanged, the decrease of the cutsize is D(i) + D(j). In the example given in Fig. 51.4, a suitable vertex pair is (3, 5), which decreases the cutsize by 3. A tentative exchange of this pair is made. These two vertices are then locked. This lock on the vertices prohibits them from taking part in any further tentative exchanges. The preceding procedure is applied to the new partitions, which gives a second vertex pair of (4, 6). This procedure is continued until all the vertices are locked. During this process, a log of all tentative exchanges and the resulting cutsizes is stored. Table 51.1 shows the log of vertex exchanges for the given example. Note that the partial sum of cutsize decrease g(i) over the exchanges of first i vertex pairs is given in the table; e.g., g(1) = 3 and g(2) = 8. The value of k for which g(k) gives the maximum value of all g(i) is determined from the table. In this example k = 2 and g(2) = 8 is the maximum partial sum. The first k pairs of vertices are actually exchanged. In the example the first two vertex pairs (3, 5) and (4, 6) are actually exchanged, resulting in the bisection shown in Fig. 51.4(b). This completes an iteration and a new iteration starts. However, if no decrease of cutsize is possible during an iteration, the algorithm stops. Figure 51.5 presents the formal description of the K-L algorithm.

Algorithm KL Begin INITIALIZE(); while (IMPROVE (table) = TRUE) do (* if an improvement has been made during last iteration, the process is carried out again.*) while (UNLOCK(A) = TRUE) do (* if there exists any unlocked vertex in A, more tentative exchanges are carried out.*) for (each a ∈ A) do if (a = unlocked) then for (each b ∈ B) do if (b = unlocked) then if (Dmax < D(a) + D(b)) then Dmax = D(a) + D(b); amax = a; bmax = b; TENT-EXCHGE(amax, bmax); LOCK(amax, bmax); LOG(table); Dmax = −∞; ACTUAL-EXCHGE(table); End;

FIGURE 51.5 Algorithm K-L.

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The procedure INITIALIZE finds initial bisections, and initializes the parameters in the algorithm. The procedure IMPROVE tests if any improvement has been made during the last iteration, while the procedure UNLOCK checks if any vertex is unlocked. Each vertex has a state of either locked or unlocked. Only those vertices whose status is unlocked are candidates for the next tentative exchanges. The procedure TENT­ EXCHGE tentatively exchanges a pair of vertices. The procedure LOCK locks the vertex pair, while the procedure LOG stores the log table. The procedure ACTUAL-EXCHGE determines the maximum partial sum of g(i), selects the vertex pairs to be exchanged, and fulfills the actual exchange of these vertex pairs. The time complexity of the K-L algorithm is O(n3). The K-L algorithm is, however, quite robust. It can accommodate additional constraints, such as a group of vertices requiring to be in a specified partition. This feature is very important in layout because some blocks of the circuit are to be kept together due to the functionality. For example, it is important to keep all components of an adder together. However, the K-L algorithm has several disadvantages. For example, the algorithm is not applicable for hypergraphs, it cannot handle arbitrarily weighted graphs and the partition sizes must be specified before partitioning. Finally, the complexity of the algorithm is considered too high even for moderate-size problems.

51.6 Other Partitioning Algorithms In order to overcome the disadvantages of the K-L algorithm, several extensions of the K-L algorithm such as the Fiduccia–Mattheyses algorithm, the Goldberg and Burstein algorithm, the component rep­ lication algorithm, and the ratio cut algorithm were developed. In the class of probabilistic and iterative algorithms simulated annealing and evolution-based algorithms have been developed for partitioning. For details on these partitioning algorithms, refer to Chapter 4 of [29].

51.7 Placement The placement phase follows the partitioning phase of the physical design cycle. After the circuit has been partitioned, the area occupied by each block (subcircuit) can be calculated and the number of terminals (pins) required by each block is known. Partitioning also generates the netlist which specifies the connections between the blocks. The layout is completed by arranging the blocks on the layout surface and interconnecting their pins according to the netlist. The arrangements of blocks is done in the placement phase, while interconnection is completed in the routing phase. In the placement phase, blocks are assigned a specific shape and are positioned on a layout surface in such a fashion that no two blocks overlap and enough space is left on the layout surface to complete the interconnections between the blocks. The blocks are positioned so as to minimize the total area of the layout. In addition, the locations of pins on each block are also determined. The input to the placement phase is a set of blocks, the number of terminals for each block, and the netlist. If the layout of the circuit within a block has been completed, then the dimensions of the block are also known. The blocks for which the dimensions are known are called fixed blocks and the blocks for which dimensions are yet to be determined are called flexible blocks. Thus, during the placement phase, we need to determine an appropriate shape for each block (if shape is not known), the location of each block on the layout surface, and determine the locations of pins on the boundary of the blocks. The problem of assigning locations to the fixed blocks on a layout surface is called the placement problem. If some or all of the blocks are flexible, the problem is called the floorplanning problem. Hence, the placement problem is a restricted version of the floorplanning problem. The terminology is slightly confusing as floorplanning problems are placement problems as well, but these terminologies have been widely used and accepted. It is desirable that the pin locations are identified at the same time the block locations are fixed. However, due to the complexity of the placement problem, the problem of identifying the pin locations for the blocks is solved after the locations of all the blocks are known. This process of identifying pin locations is called pin assignment.

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The placement phase is crucial in the overall physical design cycle because an ill-placed layout cannot be improved by high-quality routing. In other words, the overall quality of the layout in terms of area and performance is mainly determined in the placement phase.

Classification of Placement Algorithms The placement algorithms can be classified on the basis of the input to the algorithms, the nature of output generated by the algorithms, and the process used by the algorithms. Depending on the input, the placement algorithms can be classified into two major groups: construc­ tive placement and iterative improvement methods. The input to the constructive placement algorithms consists a set of blocks along with the netlist. The algorithm finds the locations of blocks. On the other hand, iterative improvement algorithms start with an initial placement. These algorithms modify the initial placement in search of a better placement. These algorithms are typically used in an iterative manner until no improvement is possible. The nature of output produced by an algorithm is another way of classifying the placement algorithms. Some algorithms generates the same solution when presented with the same problem, i.e., the solution produced is repeatable. These algorithms are called deterministic placement algorithms. Algorithms that function on the basis of fixed connectivity rules (or formulas) or determine the placement by solving simultaneous equations are deterministic and always produce the same result for a particular placement problem. Some algorithms, on the other hand, work by randomly examining configurations and may produce a different result each time they are presented with the same problem. Such algorithms, are called probabilistic placement algorithms. The classification based on the process used by the placement algorithms is perhaps the best way of classifying these algorithms. Two important classes of algorithms come under this classification: simulationbased algorithms and partitioning-based algorithms. Simulation-based algorithms simulate some natural phenomenon while partitioning-based algorithms use partitioning for generating the placement. The algorithms which use clustering and other approaches are classified under “other” placement algorithms.

Simulated Annealing Placement Algorithm Simulated annealing is one of the most well-developed methods available [2, 10–12, 16, 19, 23, 25–28]. The simulated annealing technique has been successfully used in many phases of VLSI physical design, e.g., circuit partitioning. A detailed description of the application of this method to partitioning may be found in Chapter 4 of [29]. Simulated annealing is used in placement as an iterative improvement algorithm. Given a placement configuration, a change to that configuration is made by moving a com­ ponent or interchanging locations of two components. In the case of the simple pairwise interchange algorithm, it is possible that an achieved configuration has a cost higher than that of the optimum, but no interchange can cause a further cost reduction. In such a situation, the algorithm is trapped at a local optimum, and cannot proceed further. Actually, this happens quite often when this algorithm is used in real-life examples. Simulated annealing avoids getting stuck at a local optimum by occasionally accepting moves that result in a cost increase. In simulated annealing, all moves that result in a decrease in cost are accepted. Moves that result in an increase in cost are accepted with a probability that decreases over the iterations. The analogy to the actual annealing process is heightened with the use of a parameter called temperature T. This parameter controls the probability of accepting moves that result in an increased cost. Additional moves are accepted at higher values of temperature than at lower values. The acceptance probability can be given by e ∆C/T, where ∆C is the increase in cost. The algorithm starts with a very high value of temperature, which gradually decreases so that moves that increase cost have a lower probability of being accepted. Finally, the temperature reduces to a very low value which causes only moves that reduce cost to be accepted. In this way the algorithm converges to an optimal or near-optimal configuration.

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Algorithm Simulated-Annealing

Begin temp = INIT-TEMP; place = INIT-PLACEMENT; while (temp > FINAL-TEMP) do while (inner_loop_criterion = FALSE) do new_place = PERTURB (place); ∆C = COST(new_place) - COST (place); if (∆C < 0) then place = new_place; else if (RANDOM(0,1) > e ∆c T ) then place = new_place; temp = SCHEDULE(temp); End;

FIGURE 51.6 The simulated annealing algorithm.

In each stage, the configuration is shuffled randomly to obtain a new configuration. This random shuffling could be achieved by displacing a block to a random location, an interchange of two blocks, or any other move that can change the wire length. After the shuffle, the change in cost is evaluated. If a decrease in cost occurs, the configuration is accepted; otherwise, the new configuration is accepted with a probability that depends on the temperature. The temperature is then lowered using some function which, for example, could be exponential in nature. The process is stopped when the temperature has dropped to a certain level. The outline of the simulated annealing algorithm is shown in Fig. 51.6. The parameters and functions used in a simulated annealing algorithm determine the quality of the placement produced. These parameters and functions include the cooling schedule consisting of initial temperature (init_temp), final temperature (final_temp), and the function used for changing the tem­ perature (SCHEDULE), inner_loop_criterion, which is the number of trials at each temperature, the process used for shuffling a configuration (PERTURB), acceptance probability (F), and the cost function (COST). A good choice of these parameters and functions can result in a good placement in a relatively short time.

Other Placement Algorithms Several other algorithms which simulate naturally occurring processes have been developed for routing. The simulated evolution algorithm is analogous to the natural process of mutation of species as they evolve to better adapt to their environment. The force directed placement explores the similarity between the placement problem and the classical mechanics problem of a system of bodies attached to springs. The partitioning-based placement techniques include Breuer’s algorithm and the terminal propagation algorithm. Several other algorithms, such as the cluster growth algorithm, the quadratic assignment algorithm, the resistive network optimization algorithm, and the Branch and Bound algorithm, also exist. For more details on these algorithms, refer to Chapter 5 of [29].

51.8 Routing The exact locations of circuit blocks and pins are determined in the placement phase. A netlist is also generated which specifies the required interconnections. Space not occupied by the blocks can be viewed as a collection of regions. These regions are used for routing and are called routing regions. The process of finding the geometric layouts of all the nets is called routing. Each routing region has a capacity, which is the maximum number of nets that can pass through that region. The capacity of a region is a function © 2003 by CRC Press LLC

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Channel C Terminals

Block Switchbox

FIGURE 51.7 Layout of circuit blocks and pins after placement.

(a)

(b)

FIGURE 51.8 (a) Global routing. (b) Detailed routing.

of the design rules and dimensions of the routing regions and wires. Nets must be routed within the routing regions and must not violate the capacity of any routing region. In addition, nets must not short circuit; that is, nets must not intersect each other. The objective of routing is dependent on the nature of the chip. For general purpose chips, it is sufficient to minimize the total wire length. For highperformance chips, total wire length may not be a major concern. Instead, we may want to minimize the longest wire to minimize the delay in the wire and therefore maximize its performance. Usually routing involves special treatment of such nets as clock nets, power, and ground nets. In fact, these nets are routed separately by special routers. Channels and switchboxes are the two types of routing regions. A switchbox is a rectangular area bounded on all sides. A channel is a rectangular area bounded on two opposite sides by the blocks. The capacity of a channel is a function of the number of layers (l), height (h) of the channel, wire width (w), and wire separation (s); i.e., Capacity = (l × h)/(w + s). For example, if for channel C (Fig. 51.7), l = 2, h = 18λ, w = 3λ, s = 3λ, then the capacity is (2 × 18)/(3 + 3) = 6. A VLSI chip may contain several million transistors. As a result, tens of thousands of nets must be routed to complete the layout. In addition, several hundred routes are possible for each net. This makes the routing problem computationally hard. In fact, even when the routing problem is restricted to channels, it cannot be solved in polynomial time; i.e., the channel routing problem is NP-complete [30]. Therefore, routing traditionally is divided into two phases. The first phase is called global routing and generates a “loose” route for each net. In fact, it assigns a list of routing regions to each net without specifying the actual geometric layout of wires. The second phase, which is called detailed routing, finds the actual geometric layout of each net within the assigned routing regions (see Fig. 51.8(b)). Unlike global routing, which considers the entire layout, a detailed router considers just one region at a time. The exact layout is produced for each wire segment assigned to a region, and vias are inserted to complete the layout. Detailed routing includes channel routing and switchbox routing. Another approach to routing is called area routing, which is a single-phase routing technique. However, this technique is computa­ tionally infeasible for general VLSI circuits and is typically used for specialized problems. © 2003 by CRC Press LLC

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51.9 Classification of Global Routing Algorithms Two approaches solve the global routing problem: the sequential and the concurrent: 1. Sequential Approach: As the name suggests, nets are routed one by one. However, once a net has been routed it may block other nets which are yet to be routed. As a result, this approach is very sensitive to the order in which the nets are considered for routing. Usually, the nets are sequenced according to their criticality, perimeter of the bounding rectangle, and the number of terminals. The criticality of a net is determined by the importance of the net. 2. Concurrent Approach: This approach avoids the ordering problem by considering routing of all the nets simultaneously. The concurrent approach is computationally hard and no efficient poly­ nomial algorithms are know, even for two-terminal nets. As a result, integer programming methods have been suggested. The corresponding integer program is usually too large to be employed efficiently. Hence, hierarchical methods that work from the top down are employed to partition the problem into smaller subproblems, which can be solved by integer programming.

51.10 Classification of Detailed Routing Algorithms Many ways are possible for classifying the detailed routing algorithms. The algorithms could be classified on the basis of the routing models used. Some routing algorithms use grid-based models, while some other algorithms use the gridless model. The gridless model is more practical as all the wires in a design do not have the same width. Another possible classification scheme could be to classify the algorithms based on the strategy they use. Thus, we could have greedy routers or hierarchical routers to name two. We classify the algorithms based on the number of layers used for routing. Single-layer routing problems frequently appear as subproblems in other routing problems which deal with more than one layer. Twolayer routing problems have been thoroughly investigated because until recently, due to limitations of the fabrications process, only two metal layers were allowed for routing. A third metal layer is now allowed, thanks to improvements in the fabrication process, but it is expensive compared to the twolayer metal process. Several multilayer routing algorithms also were developed recently, which can be used for routing MCMs, which have up to 32 layers.

Lee’s Algorithm for Global Routing This algorithm, which was developed by Lee in 1961[20], is the most widely used algorithm for finding a path between any two vertices on a planar rectangular grid. The key to the popularity of Lee’s maze router is its simplicity and its guarantee of finding on optimal solution, if one exists. The exploration phase of Lee’s algorithm is an improved version of the breadth-first search. The search can be visualized as a wave propagating from the source. The source is labeled ‘0’ and the wavefront propagates to all the unblocked vertices adjacent to the source. Every unblocked vertex adjacent to the source is marked with a label ‘1’. Then, every unblocked vertex adjacent to vertices with a label ‘1’ is marked with a label ‘2’, and so on. This process continues until the target vertex is reached or no further expansion of the wave can be carried out. An example of the algorithm is shown in Fig. 51.9. Due to the breadth-first nature of the search, Lee’s maze router is guaranteed to find a path between the source and the target, if one exists. In addition, it is guaranteed to be the shortest path between the vertices. The input to Lee’s algorithm is an array B, the source, s, and target, t, vertex. B[v] denotes if a vertex v is blocked or unblocked. The algorithm uses an array, L, where L[v] denotes the distance from the source to the vertex v. This array will be used in the procedure RETRACE that retraces the vertices to form a path, P, which is the output of Lee’s algorithm. Two linked lists, plist (propagation list) and nlist (neighbor list), are used to keep track of the vertices on the wavefront and their neighbor vertices, respectively. These two lists are always retrieved from tail to head. We also assume that the neighbors of a vertex are visited in counterclockwise order, that is, top, left, bottom, and then right.

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FIGURE 51.9 A net routed by Lee’s algorithm.

Algorithm Lee-Router (B, s, t, P)

Input: B, s, t Output: P

Begin plist = s; nlist = φ; temp = 1; path_exists = FALSE; while plist ≠ φ do for each vertex vi in plist do for each vertex vj neighboring vi do if B[vj] = UNBLOCKED then L[vj] = temp; INSERT (vj, nlist); if vj = t then path_exists = TRUE; exit while; temp = temp + 1; plist = nlist; nlist = φ; if path_exists = TRUE then RETRACE (L, P); else path does not exist; End;

FIGURE 51.10 Algorithm LEE-ROUTER.

The formal description of Lee’s algorithm appears in Fig. 51.10. The time and space complexity of Lee’s algorithm is O (h × w) for a grid of dimension h × w. Lee’s routing algorithm requires a large amount of storage space and its performance degrades rapidly when the size of the grid increases. Numerous attempts have been made to modify the algorithm to improve its performance and reduce its memory requirements. © 2003 by CRC Press LLC

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Lee’s algorithm requires up to k + 1 bits per vertex, where k bits are used to label the vertex during the exploration phase and an additional bit is needed to indicate whether the vertex is blocked. For an h × w grid, k = log2 (h × w). Aker [1] noticed that in the retrace phase of Lee’s algorithm, only two types of neighbors of a vertex need to be distinguished; vertices toward the target and vertices toward the source. This information can be coded in a single bit for each vertex. The vertices in wavefront, L, are always adjacent to the vertices in wavefront L − 1 and L + 1. Thus, during wave propagation, instead of using a sequence 1, 2, 3 …, the wavefronts are labeled by a sequence such as 0, 0, 1, 1, 0, 0, …. The predecessor of any wavefront is labeled differently from its successor. Thus, each scanned vertex is either labeled ‘0’ or ‘1’. Besides these two states, additional states (‘block’ and ‘unblocked’) are needed for each vertex. These four states of each vertex can be represented by using exactly two bits, regardless of the problem size. Compared with Acker’s scheme, Lee’s algorithm requires at least 12 bits per vertex for a grid size of 2000 × 2000. It is important to note that Acker’s coding scheme only reduces the memory requirement per vertex. It inherits the search space of Lee’s original routing algorithm, which is O(h × w) in the worst case.

Greedy Channel Router for Detailed Routing Assigning the complete trunk of a net or a two-terminal net segment of a multiterminal net severely restricts LEA and dogleg routers. Optimal channel routing can be obtained if for each column it can be guaranteed that only one horizontal track per net exists. Based on this observation, one approach to reduce channel height could be to route nets column by column trying to join split horizontal tracks (if any) that belong to the same net as much as possible. Based on the preceding observation and approach, Rivest and Fiduccia [24] developed the greedy channel router. This makes fewer assumptions than LEA and dogleg routers. The algorithm starts from the leftmost column and places all the net segments of a column before proceeding to the next right column. In each column the router assigns net segments to tracks in a greedy manner. However, unlike the dogleg router, the greedy router allows the doglegs in any column of the channel, not necessarily where the terminal of the doglegged net occurs. Given a channel routing problem with m columns, the algorithm uses several steps while routing a column. In the first step the algorithm connects any terminal to the trunk segment of the corresponding net. This connection is completed by using the first empty track, or the track that already contains the net. In other words, minimum vertical segment is used to connect a trunk to a terminal. For example, net 1 in Fig. 51.11(a) in column 3 is connected to the same net. The second step attempts to collapse any split nets (horizontal segments of the same net present on two different tracks) using a vertical segment as shown in Fig. 51.11(b). A split net will occur when two a terminals of the same net are located on different sides of the channel and cannot be connected immediately because of existing vertical constraints. This step also brings a terminal connection to the correct track if it has stopped on an earlier track. If two sets of split nets overlap, the second step will only be able to collapse one of them. In the third step, the algorithm tries to reduce the range or the distance between two tracks of the same net. This direction is accomplished by using a dogleg, as shown in Fig. 51.12 (a) and (b). The fourth step attempts to move the nets closer to the boundary which contains the next terminal of that net. If the 1

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FIGURE 51.11 (a) A split net. (b) The collapsed split net. © 2003 by CRC Press LLC

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FIGURE 51.12 (a) Reducing the distance between split nets. (b) The result.

Algorithm Greedy-Channel-Router (N) Input: N Begin d = DENSITY (N); (* calculate the lower bound of channel density *) insert d tracks to channel; for i = 1 to m do T1 = GET-EMPTY-TRACK; if T1 = 0 then ADD-TRACK(T1); ADD-TRACK(T2); else T2 = GET-EMPTY-TRACK; if T2 = 0 then ADD-TRACK(T2); CONNECT(Ti,T1); CONNECT(Bi,T2); join split nets as much as possible; bring split nets closer by jogging; bring nets closer to either top or bottom boundary; while split nets exists do increase number of column by 1; join split nets as much as possible; End;

FIGURE 51.13 Algorithm GREEDY-CHANNEL-ROUTER.

next terminal of a net being considered is on the top (bottom) boundary of the channel, then the algorithm tries to move the net to the upper (lower) track. In case no track is available, the algorithm adds extra tracks and the terminal is connected to this new track. After all five steps have been completed, the trunks of each net are extended to the next column and the steps are repeated. A detailed description of the greedy channel routing algorithm is in Fig. 51.13. The greedy router sometimes gives solutions which contain an excessive number of vias and doglegs. It does, however, have the capability of providing a solution even in the presence of cyclic vertical constraints. The greedy router is more flexible in the placement of doglegs due to fewer assumptions about the topology of the connections. An example routed by the greedy channel router is shown in Fig. 51.14.

Other Routing Algorithms Soukup proposed an algorithm that basically cuts down the search time of Lee’s algorithm by exploring in the direction toward the target, without changing the direction until it reaches the target or an obstacle. © 2003 by CRC Press LLC

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0

3

0

4

5

5 0

5

0

4

0

3

4

1

0

FIGURE 51.14 Channel routed using a greedy router.

An alternative approach to improve upon the speed was suggested by Hadlock. One class of algorithm is called the line-probe algorithms. The basic idea of the line-probe algorithms is to reduce the memory requirement by using line segments instead of grid notes in the search. Several algorithms based on Steiner trees have been developed. The main advantage of these algorithms is that they can be used for routing multiterminal nets. For further details on these global routing algorithms, refer to Chapter 6 of [29]. Extensive research has been carried out in the area of detailed routing and several algorithms exist for channel and switchbox routing. There are LEA-based algorithms which use a reserved layer model and do not allow any vertical constraints or doglegs. The YACR2 algorithm can handle vertical constraint violations. The net merge channel router works for two-layer channel routing problems and it exploits the graph theoretic structure of channel routing problems. Glitter is an algorithm for gridless channel routing and can handle nets of varying widths. The hierarchical channel router divides the channel routing problem into smaller problems, each of which is solved in order to generate the complete routing for the nets in the channel. Several algorithms such as the extended net merge channel routing algorithm, HVH routing from the HV solution, and the hybrid HVH-VHV channel routing algorithm exist for the three-layer channel routing problem. For further details on these detailed routing algorithms, refer to Chapter 7 of [29].

51.11 Compaction After completion of detailed routing, the layout is functionally complete. At this stage, the layout is ready to be used to fabricate a chip. However, due to nonoptimality of placement and routing algorithms, some vacant space is present in the layout. In order to minimize the cost, improve performance, and yield, layouts are reduced in size by removing the vacant space without altering the functionality of the layout. This operation of layout area minimization is called layout compaction. The compaction problem is simplified by using symbols to represent primitive circuit features, such as transistors and wires. The representation of layout using symbols is called a symbolic layout. Special languages [4, 21, 22] and special graphic editors [13, 14] are available to describe symbolic layouts. To produce the actual masks, the symbolic layouts are translated into actual geometric features. Although a feature can have any geometric shape, in practice only rectangular shapes are considered. The goal of compaction is to minimize the total layout area without violating any design rules. The area can be minimized in three ways: 1. By reducing the space between features: This can be performed by bringing the features as close to each other as possible. However, the spacing design rules must be met while moving features closer to each other. 2. By reducing the size of each feature: The size rule must be met while resizing the features. 3. By reshaping the features: Electrical characteristics must be preserved while reshaping the feature.

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Compaction is a very complex phase in the physical design cycle. It requires understanding many details of the fabrication process such as the design rules. Compaction is critical for full-custom layouts, especially for high-performance designs.

Classification of Compaction Algorithms Compaction algorithms can be classified in two ways. The first classification scheme is based on the direction of movements of the components (features): one-dimensional (1-D) and two-dimensional (2-D). In 1-D compaction components are moved only in x- or the y-direction. As a result, either the x- or the y-coordinate of the components is changed due to the compaction. If the compaction is done along the x-direction, then it is called x-compaction. Similarly, if the compaction is done along the y-direction, then it is called y-compaction. In 2-D compaction the components can be moved in both the x- and y-directions simultaneously. As a result, in 2-D compaction both x- and y-coordinates of the components are changed at the same time in order to minimize the layout area. The second approach to classify the compaction algorithms is based on the technique for computing the minimum distance between features. In this approach, we have two methods: constraint graph-based compaction and virtual grid-based compaction. In the constraint graph method, the connections and separations rules are described using linear inequalities which can be modeled using a weighted directed graph (constraint graph). This constraint graph is used to compute the new positions for the components. On the other hand, the virtual grid method assumes the layout is to be drawn on a grid. Each component is considered attached to a grid line. The compaction operation compresses the grid along with all components placed on it, keeping the grid lines straight along the way. The minimum distance between two adjacent grid lines depends on the components on these grid lines. The advantage of the virtual grid method is that the algorithms are simple and can be easily implemented. However, the virtual grid method does not produce compact layouts as does the constraint graph method. In addition, compaction algorithms can be classified on the basis of the hierarchy of the circuit. If compaction is applied to different levels of the layout, it is called hierarchical compaction. Any of the above-mentioned methods can be extended to hierarchical compaction. A variety of hierarchical com­ paction algorithms have been proposed for both constraint graph and virtual grid methods. Some compaction algorithms actually “flatten the layout” by removing all hierarchy and then perform com­ paction. In this case it may not be possible to reconstruct the hierarchy, which may be undesirable.

Shadow-Propagation Algorithm for Compaction A widely used and one of the best known techniques for generating a constraint graph is the shadowpropagation used in the CABBAGE system [15]. The “shadow” of a feature is propagated along the direction of compaction. The shadow is caused by shining an imaginary light from behind the feature under consideration (see Fig. 51.15). Usually the shadow of the feature is extended on both sides of the features in order to account for diagonal constraints. This leads to greater than minimal Euclidean spacings because an enlarged rectangle is used to account for corner interactions. (See shadow of feature in Fig. 51.15.)

B

G

A

E

C

H

D

F

FIGURE 51.15 Example of shadow propagation.

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Algorithm Shadow-Propagation (Comp_list, component) Input: Comp_list, component Begin INITIALIZE-SCANLINE (component); I = φ; while ( (LENGTH-SCANLINE(I ) < (top − bottom)) and (Comp_list ≠ φ)) curr_comp = GET-NXT-COMP (Comp_list); Ii = LEFT-EDGE (curr_comp); if (IN-RANGE (Ii, top, bottom)) I′ = UNION (Ii, I ); if(I′ ≠ I ) ADD-CONSTRAINT (component, curr_comp); I = UNION(Ii, I ); End;

FIGURE 51.16 Shadow-propagation algorithm.

When the shadow is obstructed by another feature, an edge is added to the graph between the vertices corresponding to the propagating feature and the obstructing feature. The obstructed part of the shadow is then removed from the front and no longer propagated. The process is continued until all of the shadow has been obstructed. This process is repeated for each feature in the layout. The algorithm SHADOW­ PROPAGATION, given in Fig. 51.16, presents an overview of the algorithm for x-compaction of a single feature from left to right. The SHADOW-PROPAGATION routine accepts the list of components (Comp_list), which is sorted on the x-coordinates of the left corner of the components and the component (component) for which the constraints are to be generated. The procedure, INITIALIZE-SCANLINE, computes the total length of the interval in which the shadow is to be generated. This length includes the design rule separation distance. The y-coordinate of the top and the bottom of this interval are stored in the global variables, top and bottom, respectively. The procedure, GET-NXT-COMP, returns the next component (curr_comp) from Comp_list. This component is then removed from the list. Procedure LEFT-EDGE returns the vertical interval of component, curr_comp. If this interval is within the top and bottom then curr_comp may have a constraint with component. This check is performed by the procedure IN-RANGE. If the interval for curr_component lies within top and bottom and if this interval is not already contained within one of the intervals in the interval set, , then the component lies in the shadow of component, and hence a constraint must be generated. Each interval represents the edge at which the shadow is blocked by a component. The constraint is added to the constraint graph by the procedure ADD-CONSTRAINT. The procedure UNION inserts the interval corresponding to curr_comp in the interval set at the appropriate position. This process is carried out until the interval set completely covers the interval from top to bottom or no more components are in Comp_list. Figure 51.17(a) shows the layout of components. The constraint for component A with other components is being generated. Figure 51.17(b) shows the intervals in the interval set as the shadow is propagated. From Fig. 51.17(b) it is clear that the constraints will be generated between components A and components B, C, and D in that order. As component F lies outside the interval defined by top and bottom it is not considered for constraint generation. The interval generated by component E lies within one of the intervals in the interval set. Hence, no constraint is generated between components A and E.

Other Compaction Algorithms Several algorithms such as constraint graph-based compaction algorithms, scanline algorithm, and gridbased compaction algorithms exist for the 1-D compaction problem. An algorithm based on a simulation © 2003 by CRC Press LLC

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F

Top

Top B

B B

A

D

E

C

C 1 2 Bottom

Bottom (a)

B

B

D

D,E

C

C

3

4

(b)

FIGURE 51.17 Interval generation for shadow propagation.

of the zone-refining process also was developed. This compactor is considered a 1½-D compactor, as the key idea is to provide enough lateral movements to blocks during compaction to resolve interferences. For further details on these algorithms, refer to Chapter 10 of [29].

51.12 Summary The sheer size of the VLSI circuit, the complexity of the overall design process, the desired performance of the circuit, and the cost of designing a chip dictate that the whole design process must be automated. Also, the design process must be divided into different stages because of the complexity of the entire process. Physical design is one of the steps in the VLSI design cycle. In this step each component of a circuit is converted into a set of geometric patterns which achieves the functionality of the component. The physical design step can be divided further into several substeps. All the substeps of the physical design step are interrelated. Efficient and effective algorithms are required to solve different problems in each of the substeps. Despite significant research efforts in this field, the CAD tools still lag behind the technological advances in fabrication. This calls for the development of efficient algorithms for physical design automation.

References [1] S. B. Aker, “A Modification of Lee’s Path Connection Algorithm,” IEEE Trans. Comput., pp. 97, 98, Feb. 1967. [2] P. Bannerjee and M. Jones, “A Parallel Simulated Annealing Algorithm for Stardard Cell Placement on A Hypercube Computer,” Proc. IEEE Int. Conf. Comput. Design, p. 34, 1986. [3] A. Chatterjee and R. Hartley, “A New Simultaneous Circuit Partitioning and Chip Placement Approach Based on Simulated Annealing,” Proc. Design Autom. Conf., pp. 36–39, 1990. [4] P. A. Eichenberger, Fast Symbolic Layout Translation for Custom VLSI Integrated Circuits, Ph.D. thesis, Stanford University, Stanford, CA, 1986. [5] A. El Gamal et al., “An Architecture for Electrically Configurable Gate Arrays,” IEEE JSSC, 24(2), pp. 394–398, April 1989. [6] H. Hseih, et al., “A 9000-Gate User-Programmable Gate Array,” Proc. 1988 CICC, pp. 15.3.1–15.3.7, May 1988. [7] S. C. Wong et al., “A 5000-Gate CMOS EPLD with Multiple Logic and Interconnect Arrays,” Proc. 1989 CICC, pp. 5.8.1–5.8.4, May 1989. [8] M. Feuer, “VLSI Design Automation: An Introduction,” Proc. IEEE, 71(1), pp. 1–9, Jan. 1983. © 2003 by CRC Press LLC

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[9] C. M. Fiduccia and R. M. Mattheyses, “A Linear-Time Heuristics for Improving Network Parti­ tions,” Proc. 19th Design Autom. Conf., pp. 175–181, 1982. [10] J. Greene and K. Supowit, “Simulated Annealing without Rejected Moves,” Proc. Int. Conf. Comput. Design, pp. 658–663, Oct. 1984. [11] L. K. Grover, “Standard Cell Placement Using Simulated Sintering,” Proc. 24th Design Autom. Conf., pp. 56–59, 1987. [12] B. Hajek, “Cooling Schedules for Optimal Annealing,” Oper. Res., pp. 311–329, May 1988. [13] D. D. Hill, “ICON: A Toll for Design at Schematic, Virtual-Grid and Layout Levels,” IEEE Design Test, 1(4), pp. 53–61, 1984. [14] M. Y. Hsueh, “Symbolic Layout and Compaction of Integrated Circuits,” Technical Report UCB/ERL M79/80, Electronics Research Laboratory, University of California, Berkeley, 1979. [15] M. Y. Hsueh and D. O. Pederson, Computer-Aided Layout of LSI Circuit Building-Blocks, Ph.D. thesis, University of California, Berkeley, Dec. 1979. [16] M. D. Huang, F. Romeo, and A. Sangiovanni-Vincentelli, “An Efficient General Cooling Schedule for Simulated Annealing,” Proc. IEEE Int. Conf. CAD, pp. 381–384, 1986. [17] W. Kernighan and S. Lin, “An Efficient Heuristic Procedure for Partitioning Graphs,” Bell Syst. Tech. J., 49, pp. 291–307, 1970. [18] S. Kirkpatrick, G. D. Gellat, and M. P. Vecchi, “Optimization by Simulated Annealing,” Science, 220, pp. 671–680, May 1983. [19] J. Lam and J. Delosme, “Performance of a New Annealing Schedule,” Proc. 25th Design Autom. Conf., pp. 306–311, 1988. [20] C. Y. Lee, “An Algorithm for Path Connections and Its Applications,” IRE Trans. Electr. Comput., 1961. [21] T. M. Lin and C. A Mead, “Signal Delay in General RC Networks,” IEEE Trans. CAD, CAD-3, No. 4, pp. 331–349, Oct. 1984. [22] J. M. Da Mata, “Allenda: A Procedural Language for the Hierarchical Specification of VLSI Layout,” Proc. 22nd Design Autom. Conf., pp. 183–189, 1985. [23] T. Ohtsuke, Partitioning, Assignment and Placement, Amsterdam: North-Holland, 1986. [24] R. Rivest and C. Fiduccia, “A Greedy Channel Router,” Proc. 19th ACM/IEEE Design Autom. Conf., pp. 418–424, 1982. [25] F. Romeo and A. Sangiovanni-Vincentelli, “Convergence and Finite Time Behavior of Simulated Annealing,” Proc. 24th Conf. Decision Control, pp. 761–767, 1985. [26] F. Romeo, A.S. Vincentelli, and C. Sechen, “Research on Simulated Annealing at Berkeley,” Proc. IEEE Int. Conf. Comput. Design, pp. 652–657, 1984. [27] C. Sechen and K. W. Lee, “An Improved Simulated Annealing Algorithm for Row-Based Placement,” Proc. IEEE Int.Conf. CAD, pp. 478–481, 1987. [28] C. Sechen and A. Sagiovanni-Vincentelli, “The Timber Wolf Placement and Routing Package,” IEEE J. Solid-State Circ., SC-20, pp. 510–522, 1985. [29] N. Sherwani, Algorithms for VLSI Physical Design Automation, Boston: Kluwer Academic Publishers, 1993. [30] T. G. Szymanski, “Dogleg Channel Routing is NP-Complete,” IEEE Trans. CAD, CAD-4, pp. 31–41, Jan. 1985.

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52 Design Automation Technology 52.1 Introduction 52.2 Design Entry 52.3 Conceptual Design Design Planning • Decision Assistance • Exploring Alternative Designs • Applications

52.4 Synthesis 52.5 Verification Timing Analysis • Simulation • Emulation

52.6 Test Fault Modeling • Fault Testing

Allen M. Dewey* Duke University

52.7 Frameworks 52.8 Summary

52.1 Introduction The field of design automation technology, also commonly called computer-aided design (CAD) or computer-aided engineering (CAE), involves developing computer programs to conduct portions of product design and manufacturing on behalf of the designer. Competitive pressures to produce in less time and use fewer resources, new generations of products having improved function and performance are motivating the growing importance of design automation. The increasing complexities of microelec­ tronic technology, shown in Fig. 52.1, illustrate the importance of relegating portions of product devel­ opment to computer automation [1, 3]. Advances in microelectronic technology enable over 1 million devices to be manufactured on an integrated circuit substrate smaller in size than a postage stamp, yet the ability to exploit this capability remains a challenge. Manual design techniques are unable to keep pace with product design cycle demands and are being replaced by automated design techniques [2, 4]. Figure 52.2 summarizes the historical development of design automation technology and computer programs. Design automation programs are also called applications or tools. Design automation efforts started in the early 1960s as academic research projects and captive industrial programs, focusing on individual tools for physical and logical design. Later developments extended logic simulation to more detailed circuit and device simulation and more abstract functional simulation. Starting in the mid to the late 1970s, new areas of test and synthesis emerged and commercial design automation products appeared. Today, the electronic design automation industry is an international business with a well-established and expanding technical base [5]. The electronic design automation technology base will be examined by presenting an overview of the following topical areas:

*Allen M. Dewey passed away before the publication of this edition.

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Devices Per Integrated Circuit

Clocking Frequency

16M

100 MHz VLSI

1M

16 MHz

LSI

8 MHz

64K

MSI

4 MHz

4K

1 MHz

SSI 256 16 1960

1970

1990

1980

SSI - Small Scale Integration LSI - Large Scale Integration

MSI - Medium Scale Integration VLSI - Very Large Scale Integration

FIGURE 52.1 Complexity of microelectronic technology.

1960 Layout Design Automation

1970 Circuit & Device Simulation

Logic Simulation

Test

1980 Logic Synthesis Timing Analysis

IC Technology

Bipolar L ≅ 10 µ

NMOS L≅5µ

CMOS L≅2µ

Methodology

Standard Parts

Gate Array

Standard Cell

1990 High-Level Synthesis Functional Simulation BiCMOS LC

5+4+2 = 11 B−>C−>F

1

C 4

F 2

A 1

B−>D

B−>C−>G

D 3

G 1 J 2

B 5 5

I 1

E 1

H 4

B−>E 5+1 = 6

B−>C−>H 5+4+4 = 13

5+4+2+1 = 12

B−>C−>F−>I

Primary

Outputs

5+4+4+1 = 14

B−>C−>H−>J

Stages

FIGURE 52.19 Block-oriented static timing analysis.

devices “B” and “C” of 9 [39]. When the devices associated with the last stage, i.e., the devices driving the primary outputs, are processed, the accumulated worst-case delays record the longest delay from primary inputs to primary outputs, also called the critical paths. The critical path for each primary output is highlighted in Fig. 52.19. Path-oriented timing analysis generates primary input to primary output propagation delays by tra­ versing all possible signal paths one at a time. Thus, finding the critical path via path oriented timing analysis is equivalent to finding the longest path through a directed acyclic graph, where devices are graph vertices and interconnections are graph edges [41]. A limitation of static timing analysis concerns detecting false violations or false paths. False violations are signal timing conditions that may occur due to the static structure of the design, but do not occur due to the dynamic nature of the design’s response to actual input stimuli. To account for realistic variances in component timing due to manufacturing tolerances, aging, or environmental effects, timing analysis often provides stochastic or statistical checking capabilities. Sta­ tistical timing analysis uses random number generators based on empirically observed probabilistic distributions to determine component timing behavior. Thus, statistical timing analysis describes design performance and the likelihood of the design performance.

Simulation Simulation exercises a design over a period of time by applying a series of input stimuli and generating the associated output responses. The general event-driven, or schedule-driven, stimulation algorithm is diagrammed in Fig. 52.20. An event is a change in signal value. Simulation starts by initializing the design; initial values are assigned to all signals. Initial values include starting values and pending values which constitute future events. Simulation time is advanced to the next pending event(s), signals are updated and sensitized models are evaluated. Sensitized models refer to models having outputs dependent on the updated signals [35,40]. The process of evaluating the sensitized model yields new, potentially different values for signals, i.e., a new set of pending events. These new events are added to the list of pending events, time is advanced to the next pending event(s), and the simulation algorithm repeats. Each pass through the loop of evaluating sensitized models at a particular time step is called a simulation cycle (see © 2003 by CRC Press LLC

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Initialize Design

Advance Time to Next Event

Stop

No

More Events?

Update Pending Events

Yes Update Signals

Generate New Signal Values

Evaluate All Sensitized Models

FIGURE 52.20 General event-driven simulation algorithm.

Fig. 52.20). Simulation ends when the design yields no further activity, i.e., no more pending events exist to process. Logic simulation is a computational intensive task for large, complex designs. Prior to committing to manufacturing, processor designers often simulate bringing up or “booting” the operating system. Such simulation tasks require sizable simulation computational resources. As an example, consider simulating 1s of a 200-K gate, 20-MHz processor design. Assuming that on average only 10% of the total 200-K gates are active or sensitized on each processor clock cycle, Eq. (52.6) shows that simulating 1s of actual processor time equates to 400 billion events. 400 B events = (20 M clock cycles) (200 K gates) (10% activity )  50 instructions  50 M instruction 140 h = ( 400 B events)       event s

(52.6)

Assuming that on average a simulation program executes 50 computer instructions per event on a computer capable of processing 50 million instructions per second, Eq. (52.6) also shows that processing 400 billion events requires 140 h or just short of 6 days. This simple example demonstrates the sizable computational properties of simulation. Figure 52.21 shows how simulation computation scales with design complexity. To address the growing computational demands of simulation, several simulation acceleration tech­ niques have been introduced. Schedule- or event-driven simulation (explained previously) can be accel­ erated by removing layers of interpretation and running simulation as a native executable image; such an approach is called complied, scheduled-driven simulation. Schedule-driven simulation can be accel­ erated also by using more efficient event management schemes. In a conventional, central event man­ agement scheme all events are logged into a time-ordered list. As simulation time advances, pending events become actual events and the corresponding sensitized devices are executed to compute the response events. One the other hand, in a dataflow event management scheme events are “self-empow­ ered”, active agents that flow through networks and trigger device evaluations without registering with a central time-order list and dispatcher [37]. Instead of evaluating a device in a stimulus-response manner, cycle-driven simulation avoids the over­ head of event queue processing by evaluating all devices at regular intervals of time. Cycle-driven simulation is efficient when a design exhibits a high degree of concurrency, i.e., a large percentage of the devices are active per simulation cycle. Based on the staging of devices, the devices are ranked-ordered to determine the order in which they are evaluated at each time step to ensure the correct causal behavior yielding the proper ordering of events. For functional verification, logic devices are often assigned zero-delay and

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100K

System Simulation Time (sec)

10K 1K 100 10 1 0.1 Integrated Circuit

Integrated Circuit Set

System Hardware

System Hardware/ Software

FIGURE 52.21 Simulation requirements.

memory devices are assigned unit-delay. Thus, any number of stages of logic devices may execute between system clock periods. Another simulation acceleration technique is message-driven simulation, also called parallel or dis­ tributed simulation. Device execution is divided among several processors, and the device simulations communicate event activity via messages. Messages are communicated using a conservative or an opti­ mistic strategy. Optimistic message passing strategies, such as time warp and lazy cancellation, make assumptions about future event activity to advance local device simulation. If the assumptions are correct, the processors operate more independently and better exploit parallel computation. However, if the assumptions are incorrect, then local device simulations may be forced to “roll back” to synchronize local device simulations [34, 36]. Schedule-driven, cycle-driven, and message-driven simulation are software-based simulation acceler­ ation techniques. Simulation also can be accelerated by relegating certain simulation activities to dedicated hardware. For example, hardware modelers can be attached to simulators to accelerate the activity of device evaluation. As the name implies, hardware modeling uses actual hardware devices instead of software models to obtain stimulus-response information. In a typical scenario, the hardware modeler receives input stimuli from the software simulator. The hardware modeler then exercises the device and sends the output response back to the software simulator. Using actual hardware devices reduces the expense of generating and maintaining software models and provides an environment to support appli­ cation software development. However, the hardware device must exist, which means hardware modeling has limited use in the initial stages of design in which hardware implementations are not available. Also, it is sometimes difficult for a slave hardware modeler to preserve accurate real-time device operating response characteristics within a master non-real-time software simulation environment. For example, some hardware devices may not be able to retain state information between invocations, so the hardware modeler must save the history of previous inputs and reapply them to bring the hardware device to the correct state in order to apply a new input. Another technique for addressing the growing computational demands of simulation is via simulation engines. A simulation engine can be viewed as an extension of the simulation acceleration techniques of hardware modeling. With a hardware modeler, the simulation algorithm executes in software, and component evaluation executes in dedicated hardware. With a simulation engine, the simulation algo­ rithm and component evaluation execute in dedicated hardware. Simulation engines are typically two to three orders of magnitude faster than software simulation [43].

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Emulation Emulation, also called computer-aided prototyping, verifies a design by realizing the design in “prepro­ duction” hardware and exercising the hardware. The term preproduction hardware means nonoptimized hardware providing the correct functional behavior, but not necessarily the correct performance. That is, emulation hardware may be slower, require more area, or dissipate more power than production hardware. Presently, preproduction hardware commonly involves some form of programmable logic devices, typically field-programmable gate arrays. Programmable logic devices provide generic combina­ tional and sequential digital system logic that can be programmed to realize a wide variety of designs [44]. Emulation begins by partitioning the design; each design segment is realized by a programmable logic device. The design segments are then interconnected to realize a preproduction implementation and exercised with a series of input test vectors. Emulation offers the advantage of providing prototype hardware early in the design cycle to check for errors or inconsistencies in initial functional specifications. Problems can be isolated and design modi­ fications can be accommodated easily by reprogramming the logic devices. Emulation can support functional verification at a computational rate much greater than conventional simulation. However, emulation does not generally support performance verification because, as explained previously, proto­ type hardware typically does not operate at production clock rates.

52.6 Test Figure 52.22 shows that the test task generally follows the verification task. Although the verification and test tasks both seek to check for correct function and performance, verification focuses on a model of the design before manufacturing, whereas test focuses on the actual hardware after manufacturing. Thus, the primary objective of test is to detect a faulty device by applying input test stimuli and observing expected results [47, 53].

Design Entry

Conceptual Design

Synthesis

Test

FIGURE 52.22 Design process.

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Verification

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$5M $3.5M

Tester Costs

$3M $1.5M $500K $200K 1974

1979

1983

1986

1990

1992

FIGURE 52.23 Integrated circuit tester equipment cost.

TABLE 52.2

Fault Coverage and Defect Rate Defect Rate

Microelectronic Fabrication Process 2 µm

90% Yield 1.5 µm

50% Yield 1 µ m

10% Yield

70% Fault Coverage

90% Fault Coverage

99% Fault Coverage

3%

1%

0.1%

19%

7%

0.7%

50%

21%

2%

The test task is difficult because designs are growing in complexity; more components provide more opportunity for manufacturing defects. Test is also challenged by new microelectronic fabrication pro­ cesses having new failure modes which again provides more opportunity for manufacturing defects. New microelectronic fabrication processes also offer higher levels of integration with fewer access points to probe internal electrical nodes. To illustrate the growing demands of test, Table 52.2 shows the general proportional relationship between manufacturing defects and required fault coverage, i.e., quality of testing. Figure 52.23 shows the escalating costs of testing equipment. Testing involves three general testing techniques or strategies: functional, parametric, and fault. Func­ tional testing checks that the hardware device realizes the correct I-O digital system behavior. Parametric testing checks that the hardware device realizes the correct performance specifications, such as speed or power dissipation, and electrical specifications, such as voltage polarities and current sinking/sourcing limitation. Finally, fault testing checks for manufacturing defects or “faults”.

Fault Modeling A fault is a manufacturing or aging defect that causes a device to operative incorrectly or to fail. A sample listing of common integrated circuit physical faults is given next: • • • •

Wiring faults Dielectric faults Threshold faults Soft faults

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Wiring faults are unwanted opens and shorts. Two wires or networks that should be electrically connected but are not constitute an open. Two wires or networks that should not be electrically connected but are constitute a short. Wiring faults can be caused by manufacturing defects such as metallization or etching problems, or aging defects, such as corrosion or electromigration. Dielectric faults are electrical isolation defects that can be caused by masking defects, material impurities or imperfections, and electrostatic discharge. Threshold faults occur when the turn-on and turn-off voltage potentials of electrical devices exceed allowed ranges. The faulty devices cannot be properly operated, which results in component failure. Soft faults occur when radiation exposure temporarily changes electrical charge distributions. Such changes can alter circuit voltage potentials, which can, in turn, change logical values, also called “dropping bits”. Radiation effects are called “soft” faults because the hardware is not permanently damaged [54]. To simplify the task of fault testing, the physical faults described above are translated into logical faults. Typically, a single logical fault covers several physical faults. A popular logical fault model is the single stuck line fault model. The single stuck line fault model considers faults where any single signal line or wire is permanently set to a logic 0, “stuck-at-0”, or a logic 1, “stuck-at-1”. These signal or interconnect faults are assumed to be time invariant. Building on the single stuck line fault model, the multiple stuck line fault model considers multiple signal wire stuck-at-0/stuck-at-1 faults. The multiple stuck line fault model is more expressive and can cover more physical faults than the single stuck line model. However, fault testing for the multiple stuck line fault model is more difficult because of the exponential growth in the possible combinations of multiple signal faults. Stuck fault models do not address all physical faults because not all physical faults result in signal lines permanently set to low or high voltages, i.e., stuck-at-0 or stuck-at-1 logic faults. Thus, other fault models have been developed to address specific failure mechanisms. For example, the bridging fault model addresses electrical shorts that cause unwanted coupling or spurious feedback loops. As another example, the pattern-sensitive fault model addresses wiring and dielectric faults that yield unwanted interference between physically adjacent signals. Pattern-sensitive faults are generally most prevalent in high-density memories incorporating low signal:noise ratios and can be difficult to detect because they are often datapattern and data-rate dependent. In other words, the part fails only under certain combinations of input stimuli and only under certain operating conditions.

Fault Testing Having identified and categorized the physical faults that may cause device malfunction or failure and determined how the physical faults relate to logical faults, the next task is to develop tests to detect these faults. When the tests are generated by a computer program, this activity is called automatic test program generation. Examples of fault testing techniques are listed next: • • • • • •

Stuck-at techniques Scan techniques Signature techniques Ad hoc techniques Coding techniques Electrical monitoring techniques

The following paragraphs review these testing strategies. Basic stuck-at techniques generate input stimuli for fault testing combinational digital systems. Three of the most popular stuck-at fault testing techniques are the D algorithm, the path oriented decision making (Podem) algorithm, and the fan algorithm. These algorithms first identify a circuit fault (e.g., stuck-at-0 or stuck-at-1) and then try to generate an input stimulus that detects the fault and makes the fault visible as an output. Detecting a fault is often called fault sensitization and making a fault visible

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A B

Stuck-at-0 Fault

Z

C D

FIGURE 52.24 Combinational logic stuck-at fault testing.

Operation Mode

Combinational Logic

Combinational Logic

Registers

Test Mode

Combinational Logic

Combinational Logic

Registers

FIGURE 52.25 Scan-based design-for-testability.

is often called fault propagation. To illustrate this process, consider the simple combinational design in Fig. 52.24 [46, 49, 50]. The design is defective because a manufacturing defect has caused the output of the and gate to be permanently tied to ground, i.e., stuck-at-0, using a positive logic convention. To sensitize the fault, the inputs A and B should both be set to 1, which should force the and gate output to a 1 for a good circuit. To propagate the fault, the inputs C and D should both be set to 0, which will force the xor gate output to 1, again for a good circuit. Thus, if A = 1, B = 1, C = 0, and D = 0 in Fig. 52.24, then a good circuit would yield a 1, but the defective circuit yields a 0 which detects the stuck-at-0 fault at the and gate output. Sequential automatic test program generation is a more difficult task than combinational automatic test program generation because exercising or sensitizing a particular circuit path to detect the presence of a possible manufacturing fault may require a sequence of input test vectors. One technique for testing sequential digital systems is called scan fault testing. Scan fault testing is called a design-for-testability technique because it modifies or constrains the design in a manner that facilitates fault testing. Scan techniques impose a logic design discipline that all state registers be connected in one or more chains to form “scan rings”, as shown in Fig. 52.25 [48]. During normal device operation, the scan rings are disabled and the registers serve as conventional memory (state) storage elements. During test operation, the scan rings are enabled and stimulus test vectors are shifted into the memory elements to set the state of the digital system. The digital system is exercised for one clock cycle and then the results are shifted out of the scan ring to record the response.

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Test Mode

Combinational Logic

Combinational Logic

Registers

FIGURE 52.26 Partial scan-based design-for-testability.

Integrated Circuit

Integrated Circuit

Core Logic

Core Logic

Printed Circuit Board

FIGURE 52.27 Boundary scan.

The principal advantage of scan design-for-testability is that the scan ring decouples stages of combi­ national logic, thereby transforming a sequential design into effectively a combinational design and correspondingly a difficult sequential test task into a simpler combinational test task. However, fault tests must still be generated for the combinational logic, and shifting in stimuli and shifting out response requires time. Also, scan paths require additional hardware resources that can impose a performance (speed) penalty. To address these limitations, “partial” scan techniques have been developed that offer a compromise between testability and performance. Instead of connecting every register into scan chains, Fig. 52.26 shows that a partial scan selectively connects a subset of registers into scan chains. Registers in critical performance circuit paths are typically excluded and registers providing control and observa­ baility to portions of the design are typically included. Similar to full scan test operation, stimulus test vectors are shifted into the memory elements to set the state of the digital system. Then, a partial scan test exercises the digital system for multiple clock cycles (two clock cycles for the partial scan shown in Fig. 52.26), and then the results are shifted out of the scan ring to record the response. A variation of partial scan design-for-testability, called boundary scan, has been defined for testing integrated circuits on printed circuit boards. Printed circuit board manufacturing developments, such as fine-lead components, surface mount assembly, and multichip modules, yield high-density boards with fewer access points to probe individual pins. Such printed circuit boards are difficult to test. As the name implies, boundary scan imposes a design discipline on printed circuit board components, typically integrated circuits, such that the I-O pins on the integrated circuits can be connected into scan chains. Figure 52.27 shows that each integrated circuit configured for boundary scan contains scan registers between the I-O pins and the core logic to enable the printed circuit board test bus to control and observe the behavior of individual integrated circuits [51].

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Another design-for-testability technique is signature analysis, also called built-in-self-test. Signature testing techniques use additional logic, typically linear feedback shift registers, to automatically generate pseudorandom test vectors. The output responses are compressed into a single vector and compared to a known good vector. If the output response vector does not exactly match the known good vector, then the design is considered faulty. Matching the output response vector and a known good vector does not guarantee correct hardware; however, if enough pseudorandom test vectors are exercised, then the chances are acceptably small of obtaining a false positive result. Signature analysis is often used to test memories [45]. Ad hoc testing techniques selectively insert test hardware and access points into a design to improve observability and controllability. Typical candidates for additional access points include storage elements (set and reset controls), major system communication buses, and feedback loops. Ad hoc testing tech­ niques, also called behavioral testing techniques, can avoid the performance penalty of more structured, logical fault testing techniques, such as scan testing, and more closely mimics the actions of an expert test engineer. However, the number of access points is often restricted by integrated circuit or printed circuit board I-O pin limitations. Coding test techniques encode signal information so that errors can be detected and possibly corrected. Although often implemented in software, coding techniques can also be implemented in hardware. For example, a simple coding technique called parity checking is often implemented in hardware. Parity checking adds an extra bit to multibit data. The parity bit is set such that the total number of logic 1’s in the multibit data and parity bit is either an even number (even parity) or an odd number (odd parity). An error has occurred if an even parity encoded signal contains an odd number of logic 1’s or an odd parity encoded signal contains an even number of logic 1’s. Coding techniques are used extensively to detect and correct transmission errors on system buses and networks, storage errors in system memory, and computational errors in processors [52]. Finally, the electrical monitoring testing technique, also called current/voltage testing, relies on the simple observation that an out-of-range current or voltage often indicates a defective or bad part. Possibly a short or open is present, causing a particular I-O signal to have the wrong voltage or current. Current testing (Iddq testing) is particularly useful for digital systems using CMOS integrated circuit technology. Normally, CMOS circuits yield very low static or quiescent currents. However, physical faults, such as gate oxide defects, can increase static current by several orders of magnitude. Such a substantial change in static current is straightforward to detect. The principle advantages of current testing are that the tests are simple and the fault models address detailed transistor-level defects. However, current testing requires that enough time be allotted between input stimuli to allow the circuit to reach a static state, which slows down testing and causes problems with circuits that cannot be tested at scaled clock rates.

52.7 Frameworks The previous sections discussed various types of design automation programs ranging from initial design entry tasks to final manufacturing test tasks. As the number and sophistication of design automation programs increases, the systems aspects of how the tools should be integrated with each other and underlying computing platforms become increasingly important. The first commercial design automation system product offerings in the 1970s consisted primarily of design automation programs and an asso­ ciated computing platform “bundled” together in turnkey systems. These initial product offerings offered little flexibility to “mix-and-match” design automation programs and computing products from different source to take advantage of state-of-the-art capabilities and construct a design automation system tailored to particular end-user requirements. In response to these limitations, vendor offerings in the 1980s started to address open systems. Vendors “unbundled” software and hardware and introduced interoperability mechanisms to enable a design automation program to execute on different vendor systems. The interop­ erability mechanisms are collectively called frameworks [56]. Frameworks support design automation systems potentially involving many users, application pro­ grams, and host computing environments or platforms. Frameworks manage the complexities of a © 2003 by CRC Press LLC

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Framework

Computing

Platform

  

 

User Interface Services

Application Program

Application Program

Application Program

Application Program Services

Design Data Services

Operating System

Hardware Resources

FIGURE 52.28 Framework architecture.

complete design methodology by coordinating and conducting the logistics of design automation pro­ grams and design data. Supporting the entire design cycle, also called concurrent engineering, improves productivity by globally optimizing the utilization of resources and the minimization of design errors and associated costs. A general definition of a framework is given next: A CAD framework is a software infrastructure that provides a common operating environment for CAD tools. A framework should enable users to launch and manage tools; create, organize, and manage data; graphically view the entire design process; and perform design management tasks such as configuration and version management. Among the key elements of a CAD framework are platformindependent graphics and user interfaces, inter-tool communications, and design data and process management services. (CAD Framework Initiative, CFI)1 Figure 52.28 illustrates that a framework is essentially a domain-specific (i.e., electronic systems) layer of operating system software that facilitates “plug-compatible” design automation programs. Framework services are specific to electronic systems design and are mapped into the more generic services provided by general purpose computing platforms [55]. User interface services provide a common and consistent “look-and-feel” to application programs. User interface services include support for consistent information display styles using menus and/or windows. These services also include support for consistent command styles using programming function keys and/or mouse buttons. Application program services provide support for program interactive/batch invocation and normal/abnormal termination. Application services also provide support for programto-program communication and process management. Process management implements a design meth­ odology that defines application-to-application and application-to-data dependencies. Process manage­ ment describes a general sequencing of design automation programs and provisions for iterations. In other words, process management ensures a designer is working with the right tool at the right time with the right data. 1CAD Framework Initiative is a consortium of companies established to define and promote industry standards for design automation system interoperability.

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Object-Oriented

Application Program Complexity Relational

Network

Application Data Complexity

FIGURE 52.29 Data management technology.

Product P1 Component C1

Object

Component C2 Inheritance

Component C1

Component C2

SubComponent S1

SubComponent S1

Subcomponent S2

Subcomponent S2

FIGURE 52.30 Object-oriented modeling.

Finally, a framework provides design data services to support access, storage, configuration, and integrity operations. Figure 52.29 shows relationships among relational, network, and object-oriented data management schemes. Due to the comparatively large size of design data and the length of design operations, framework data services are evolving toward object-oriented paradigms [57–59]. Object-oriented paradigms match data structures and operations with design automation objects and tasks, respectively. Figure 52.30 shows that hardware devices, components, and products become natural choices for software “objects”. The hierarchical relationships between hardware units become natural choices for software “inherit­ ance”. Finally, design automation tasks and subtask that operate on hardware units, such as display or simulate, become natural choices for software “methods”.

52.8 Summary Design automation technology offers the potential of serving as a powerful fulcrum in leveraging the skills of a designer against the growing demands of electronic system design and manufacturing. Design automation programs help to relieve the designer of the burden of tedious, repetitive tasks that can be labor intensive and error prone.

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Design automation technology can be broken down into several topical areas, such as design entry, conceptual design, synthesis, verification, testing, and frameworks. Each topical area has developed an extensive body of knowledge and experience. Design entry defines a desire specification. Conceptual design refines the specification into a design plan. Synthesis refines the design plan into an implementation. Verification checks that the implemen­ tation faithfully realizes the desired specification. Testing checks that the manufactured part performs functionally and parametrically correctly. Finally, frameworks enable individual design automation pro­ grams to operate collectively and cohesively within a larger computing system environment.

References [1] D. Barbe, Ed. Very Large Scale Integration (VLSI) — Fundamentals and Applications, New York: Springer-Verlag, 1980. [2] T. Dillinger, VLSI Engineering, Englewood Cliffs, NJ: Prentice-Hall, 1988. [3] E. Hollis, Design of VLSI Gate Array Integrated Circuits, Englewood Cliffs, NJ: Prentice Hall, 1987. [4] S. Sapiro, Handbook of Design Automation, Englewood Cliffs, NJ: Prentice Hall, 1986. [5] S. Trimberger, An Introduction to CAD for VLSI, San Jose, CA: Domancloud Publishers, 1990. [6] G. Birtwistle and P. Subrahmanyan, VLSI Specification, Verification, and Synthesis, Boston: Kluwer Academic, 1988. [7] A. Dewey. “VHSIC Hardware Description Language Development Program,” Proc. Design Autom. Conf., June 1983. [8] A. Dewey, “VHDL: Towards a Unified View of Design,” IEEE Design Test Comput., June 1992. [9] J. Douglas-Young, Complete Guide to Reading Schematic Diagrams, Englewood Cliffs, NJ: Prentice Hall, 1988. [10] C. Liu, Elements of Discrete Mathematics, New York: McGraw-Hill, 1985. [11] M. Pechet, Ed., Handbook of Electrical Package Design, New York: Marcel Dekker, 1991. [12] J. Peterson, Petri Net Theory and Modeling of Systems, Englewood Cliffs, NJ: Prentice Hall, 1981. [13] B. Spinks, Introduction to Integrated Circuit Layout, Englewood Cliffs, NJ: Prentice Hall, 1985. [14] N. Bose, Digital Filters: Theory and Applications, New York: North-Holland, 1985. [15] X. Chen and M. Bushnell, “A Module Area Estimator For VLSI Layout,” Proc. Design Autom. Conf., June 1988. [16] A. Dewey, Principles of VLSI Systems Planning: A Framework for Conceptual Design, Boston: Kluwer Academic, 1990. [17] W. Donath, “Wiring Space Estimation for Rectangular Gate Arrays,” Proc. Int. Conf. VLSI, 1981. [18] W. Heller, “Wirability — Designing Wiring Space for Chips and Chip Packages,” IEEE Design Test Comput., Aug. 1984. [19] C. Leiserson, Area-Efficient VLSI Computation, Ph.D. dissertation, Pittsburgh,” Carnegie Mellon University, 1981. [20] A. Oppenheim and R. Schafer, Digital Signal Processing, Englewood Cliffs, NJ: Prentice Hall, 1975. [21] L. Rabiner, O. Hermann, and D. Chan, “Practical Design Rules for Optimum Finite Impulse Response Low-Pass Digital Filters,” Bell Syst. Tech. J., July-Aug. 1973. [22] E. Sacerdoti, “Planning in a Hierarchy of Abstraction Spaces,” Artif. Intell., Sept. 1974. [23] M. Stefik, “Planning with Constraints,” Artif. Intell., Feb. 1980. [24] C. Thompson, “Area-Time Complexity for VLSI,” Proc. Caltech Conf. VLSI, Jan. 1979. [25] L. Valiant, “Universality Considerations in VLSI Circuits,” IEEE Trans. Comput., Feb. 1981. [26] R. Ayres, VLSI: Silicon Compilation and the Art of Automatic Microchip Design, Englewood Cliffs, NJ: Prentice Hall, 1983. [27] R. Brayton et al., Logic Minimization Algorithms for VLSI Synthesis, Boston: Kluwer Academic, 1992. [28] R. Camposano and W. Wolfe, High-Level VLSI Synthesis, Boston: Kluwer Academic, 1991. [29] D. Gajski, Ed., Silicon Compilation, Reading, MA: Addison-Wesley, 1988.

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[30] D. Gajski et al., High-Level Synthesis — Introduction to Chip and System Design, Boston: Kluwer Academic, 1992. [31] P. Paulin and J. Knight, “Force-Directed Scheduling for the Behavioral Synthesis of ASIC’s,” IEEE Design Test Comput., Oct. 1989. [32] B. Preas, M. Lorenzetti, and B. Ackland, Eds., Physical Design Automation of VLSI Systems, New York: Benjamin Cummings, 1988. [33] T. Sasao, Ed., Logic Synthesis and Optimization, Boston: Kluwer Academic, 1993. [34] R. Bryant, “Simulation on Distributed Systems,” Proc. Int. Conf. Distributed Systems, 1979. [35] J. Butler, Ed., “Multiple-Valued Logic in VLSI Design, New York: IEEE Computer Society Press, 1991. [36] K. Chandy and J. Misra, “Asynchronous Distributed Simulation Via a Sequence of Parallel Com­ putations,” Commun. ACM, April 1981. [37] W. Hahn and K. Fischer, “High Performance Computing for Digital Design Simulation,” VLSI85, Amsterdam: Elsevier, 1985. [38] R. McHaney, Computer Simulation: A Practical Perspective, New York: Academic Press, 1991. [39] T. McWilliams and L. Widdoes,“SCALD — Structured Computer Aided Logic Design,” Proc. Design Autom. Conf., June 1978. [40] U. Pooch, Discrete Event Simulation: A Practical Approach, Boca Raton, FL: CRC Press, 1993. [41] T. Sasiki, et al., “Hierarchical Design and Verification for Large Digital Systems,” Proc Design Autom. Conf., June 1978. [42] J. Sifakis, Ed., Automatic Verification Methods for Finite State Systems, New York: Springer-Verlag, 1990. [43] S. Takasaki, F. Hirose, and A. Yamada, “Logic Simulation Engines in Japan,” IEEE Design Test Comput., Oct. 1989. [44] S. Walters, “Computer-Aided Prototyping For ASIC-Based Synthesis,” IEEE Design Test Comput., June 1991. [45] V. Agrawal, C. Kime, and S. Saluja, “A Tutorial on Built-In Self Test,” IEEE Design Test Comput., June 1993. [46] M. Breuer and A. Friedman, Diagnosis and Reliable Design of Digital Systems, New York: Computer Science Press, 1976. [47] A. Buckroyd, Computer Integrated Testing, New York: John Wiley & Sons, 1989. [48] E. Eichelberger and T. Williams, “A Logic Design Structure for LSI Testability,” Proc. Design Autom. Conf., June 1977. [49] H. Fujiwara and T. Shimono, “On the Acceleration of Test Generation Algorithms,” IEEE Trans. Comput., Dec. 1983. [50] P. Goel,“An Implicit Enumeration Algorithm to Generalize Tests for Combinational Logic Circuits,” IEEE Trans. Comput., March 1981. [51] K. Parker, “The Impact of Boundary Scan on Board Test,” IEEE Design Test Comput., Aug. 1989. [52] W. Peterson and E. Weldon, Error-Correcting Codes, Cambridge, MA: MIT Press, 1972. [53] M. Weyerer and G. Goldemund, Testability of Electronic Circuits, Englewood Cliffs, NJ: Prentice Hall, 1992. [54] G. Zobrist, VLSI Fault Modeling and Testing Technologies, New York: Ablex Publishing, 1993. [55] T. Barnes, Electronic CAD Frameworks, Boston: Kluwer Academic, 1992. [56] D. Bedworth, M. Henderson, and P. Wolfe, Computer-Integrated Design and Manufacturing, New York: McGraw-Hill, 1991. [57] R. Gupta and E. Horowitz, Eds., Object-Oriented Databases with Applications to CASE Networks, and VLSI CAD, Englewood Cliffs, NJ: Prentice Hall 1990. [58] W. Kim, Object-Oriented Concepts, Databases, and Applications, Reading, MA: Addison-Wesley, 1989. [59] E. Nahouranii and F. Petry, Eds., Object-Oriented Databases, Los Alamitos, CA: IEEE Computer Society Press, 1991.

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53 Computer-Aided Analysis 53.1 Circuit Simulation Using SPICE and SUPREM

J. Gregory Rollins Technology Modeling Associates, Inc.

Peter Bendix LSI Logic

Introduction • DC (Steady-State) Analysis • AC Analysis • Transient Analysis • Process and Device Simulation • Process Simulation • Device Simulation • Appendix

53.2 Parameter Extraction for Analog Circuit Simulation Introduction • MOS DC Models • BSIM Extraction Strategy in Detail • Bipolar DC Model • MOS and Bipolar Capacitance Models • Bipolar High-Frequency Model • Miscellaneous Topics

53.1 Circuit Simulation Using SPICE and SUPREM J. Gregory Rollins Introduction Computer-aided simulation is a powerful aid during the design or analysis of electronic circuits and semiconductor devices. The first part of this chapter focuses on analog circuit simulation. The second part covers simulations of semiconductor processing and devices. While the main emphasis is on analog circuits, the same simulation techniques may, of course, be applied to digital circuits (which are, after all, composed of analog circuits). The main limitation will be the size of these circuits because the techniques presented here provide a very detailed analysis of the circuit in question and, therefore, would be too costly in terms of computer resources to analyze a large digital system. The most widely known and used circuit simulation program is SPICE (Simulation Program with Integrated Circuit Emphasis). This program was first written at the University of California at Berkeley by Laurence Nagel in 1975. Research in the area of circuit simulation is California at many universities and industrial sites. Commercial versions of SPICE or related programs are available on a wide variety of computing platforms, from small personal computers to large mainframes. A list of some commercial simulator vendors can be found in the Appendix. It is possible to simulative virtually any type of circuit using a program like SPICE. The programs have built-in elements for resistors, capacitors, inductors, dependent and independent voltage and current sources, diodes, MOSFETs, JFETs, BJTs, transmission lines, transformers, and even transformers with saturating cores in some versions. Found in commercial versions are libraries of standard components which have all necessary parameters prefitted to typical specifications. These libraries include items such as discrete transistors, op amps, phase-locked loops, voltage regulators, logic integrated circuits (ICs) and saturating transformer cores. Computer-aided circuit simulation is now considered an essential step in the design of integrated circuits, because without simulation the number of “trial runs” necessary to produce a working IC would greatly increase the cost of the IC. Simulation provides other advantages, however:

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• The ability to measure “inaccessible” voltages and currents. Because a mathematical model is used all voltages and currents are available. No loading problems are associated with placing a voltmeter or oscilloscope in the middle of the circuit, with measuring difficult one-shot wave forms, or probing a microscopic die. • Mathematically ideal elements are available. Creating an ideal voltage or current source is trivial with a simulator, but impossible in the laboratory. In addition, all component values are exact and no parasitic elements exist. • It is easy to change the values of components or the configuration of the circuit. Unsoldering leads or redesigning IC masks are unnecessary. Unfortunately, computer-aided simulation has its own problems: • Real circuits are distributed systems, not the “lumped elements models” which are assumed by simulators. Real circuits, therefore, have resistive, capacitive, and inductive parasitic elements present besides the intended components. In high-speed circuits these parasitic elements are often the dominant performance-limiting elements in the circuit, and must be painstakingly modeled. • Suitable predefined numerical modes have not yet been developed for certain types of devices or electrical phenomena. The software user may be required, therefore, to create his or her own models which are available in the simulator. (An example is the solid-state thyristor which may be created from a NPN and PNP bipolar transistor.) • The numerical methods used may place constraints on the form of the model equations used. The following sections consider the three primary simulation modes: DC, AC, and transient analysis. In each section an overview is given of the numerical techniques used. Some examples are then given, followed by a brief discussion of common pitfalls.

DC (Steady-State) Analysis DC analysis calculates the state of a circuit with fixed (non-time varying) inputs after an infinite period of time. DC analysis is useful to determine the operating point (Q-point) of a circuit, power consumption, regulation and output voltage of power supplies, transfer functions, noise margin and fanout in logic gates, and many other types of analysis. In addition, DC analysis is used to find the starting point for AC and transient analysis. To perform the analysis the simulator performs the following steps: 1. All capacitors are removed from the circuit (replaced with opens). 2. All inductors are replaced with shorts. 3. Modified nodal analysis is used to construct the nonlinear circuit equations. This results in one equation for each circuit node plus one equation for each voltage source. Modified nodal analysis is used rather than standard nodal analysis because an ideal voltage source or inductance cannot be represented using normal nodal analysis. To represent the voltage sources, loop equations (one for each voltage source or inductor), are included as well as the standard node equations. The node voltages and voltage source currents, then, represent the quantities which are solved for. These form a vector x. The circuit equations can also be represented as a vector F(x) = 0. 4. Because the equations are nonlinear, Newton’s method (or a variant thereof) is used to solve the equations. Newton’s method is given by the following equations: J=

∂F ∂x xi

( )

xi+1 = xi − J −1 ⋅ F xi

Here, if xi is an estimate of the solution, xi + 1 is a better estimate. The equations are used iteratively, and hopefully the vector x converges to the correct solution. The square matrix J of partial © 2003 by CRC Press LLC

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derivatives is called the Jacobian of the system. Most of the work in calculating the solution is involved in calculating J and its inverse J –1. It may take as many a 100 iterations for the process to converge to a solution. Parameters control this process in most simulation programs (see the .OPTIONS statement in SPICE). For example, the maximum number of iterations allowed and error limits which must be satisfied before the process is considered to be converged, but normally the default limits are appropriate. Example 53.1. Simulation Voltage Regulator: We shall now consider simulation of the type 723 voltage regulator IC, shown in Fig. 53.1. We wish to simulate the IC and calculate the sensitivity of the output IV characteristic and verify that the output current follows a “fold-back” type characteristic under overload conditions. The IC itself contains a voltage reference source and operational amplifier. Simple models for these elements are used here rather than representing them in their full form, using transistors to illustrate model development. The use of simplified models can also greatly reduce the simulation effort. (For example, the simple op amp used here requires only eight nodes and ten components, yet realizes many advanced features.) Note in Fig. 53.1 that the numbers next to the wires represent the circuit nodes. These numbers are used to describe the circuit to the simulator. In most SPICE-type simulators the nodes are represented by numbers, with the ground node being node zero. Referring to Fig. 53.2, the 723 regulator and its internal op amp are represented by subcircuits. Each subcircuit has its own set of nodes and components. Subcircuits are useful for encapsulating sections of a circuit or when a certain section needs to be used repeatedly (see the next section). The following properties are modeled in the op amp: 1. 2. 3. 4. 5. 6.

Common mode gain Differential mode gain Input impedance Output impedance Dominant pole Output voltage clipping

The input terminals of the op amp connect to a “T” resistance network, which sets the common and differential mode input resistance. Therefore, the common mode resistance is RCM + RDIF = 1.1E6 and the differential mode resistance is RDIF1 + RDIF2 = 2.0E5.

1

IC-723 R7 270

3

10 9

1

GDIF

1 + −

OPAMP

D1

2

E1

6

00k VIN Rdif2 + − 00k Rdif1 4

8 1E6 Rcm

.01F 1 01 R1

GCM D2

7

5

7 Q1

Q2 4

2 6

8

Q4

4

Q3

R1

1000 R4

5

2.2k

5 3k R3

11

R2 110

R6 510

© 2003 by CRC Press LLC

2 .075 R4 6 R5 510

8

FIGURE 53.1 Regulator circuit to be used for DC analysis, created using PSPICE.

VPP

+ −

VOUT

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The Circuits and Filters Handbook, Second Edition

Regulator circuit. *Complete circuit* *Load source* vout 6 0 *Power input* vpp 1 0 11 x1 1 0 4 5 6 7 8 9 10 ic723 *Series Pass transistors* q3 1 4 11 mq3 q4 1 11 2 mq4 r1 4 11 2.2k r2 5 2 110 r3 5 0 3k r4 2 6 0.075 r5 6 8 510 r6 8 0 510 r7 9 10 270 *Control cards* .op .model mq3 npn(is = 1e−9 bf = 30 + br = 5 ikf = 50m) model mq4 npn(is = 1e-6 bf = 30 + br = 5 ikf = 10) .dc vout 1 5.5 .01 .plot dc i(vout) .probe

.subckt ic723 1 2 4 5 6 7 8 9 10 *Type 723 voltage regulator* x1 1 2 10 8 7 opamp *Internal voltage reference* vr 9 2 2.5 q1 3 7 4 mm q2 7 5 6 mm .model mm npn (is = 1e−12 bf = 100) + br = 5 .ends ic723 *Ideal opamp with limiting .subckt opamp 1 2 3 4 5 * vcc vee +in −in out rdif1 3 8 le5 rdif2 4 8 le5 rcm 8 0 le6 *Common mode gain* gcm 6 0 8 0 le−1 *Differential mode gain* gdif 6 0 4 3 100 r1 6 0 1

*Single pole response*

c1 6 0 .01

d1 6 1 ideal

d2 2 6 ideal

e1 7 0 6 0 1

rout 5 7 le3 .model ideal d (is = le−6 n = .01) .ends opamp

FIGURE 53.2 SPICE input listing of regulator circuit shown in Fig. 53.1.

Dependent current sources are used to create the main gain elements. Because these sources force current into a 1 – Ω resistor, the voltage gain is Gm∗R at low frequency. In the differential mode, this gives (GDIF*R1 = 100). In the common mode, this gives (GCM∗R1∗(RCM/(RDIF1 + RCM = 0.0909). The two diodes D1 and D2 implement clipping by preventing the voltage at node 6 from exceeding VCC or going below VEE. The diodes are made “ideal” by reducing the ideality factor n. Note that the diode current is Id = Is[exp(Vd /(nVt)) – 1], where Vt is the thermal voltage (0.026 V). Thus, reducing n makes the diode turn on at a lower voltage. A single pole is created by placing a capacitor (C1) in parallel with resistor R1. The pole frequency is therefore given by 1.0/2 ∗ π ∗ R1 ∗ C1). Finally, the output is driven by the voltage-controlled voltage source E1 (which has a voltage gain of unity), through the output resistor R4. The output resistance of the op amp is therefore equal to R4. To observe the output voltage as a function of resistance, the regulator is loaded with a voltage source (VOUT) and the voltage source is swept from 0.05 to 6.0 V. A plot of output voltage vs. resistance can then be obtained by plotting VOUT vs. VOUT/I(VOUT) (using PROBE in this case; see Fig. 53.3). Note that for this circuit, even though a current source would seem a more natural choice, a voltage source must be used as a load rather than a current source because the output characteristic curve is multivalued in current. If a current source were used it would not be possible to easily simulate the entire curve. Of course, many other interesting quantities can be plotted; for example, the power dissipated in the pass transistor can be approximated by plotting IC(Q3)*VC(Q3). Several restrictions exist as to what constitutes a valid circuit, and in most cases the simulators will complain if the restrictions are violated: 1. All nodes must have a DC path to ground. 2. Voltage sources must not be connected in a loop.

© 2003 by CRC Press LLC

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1

20

2 120W Power

10

80W Vout

Iout 0

−10

40W

>>

0W 100m 1

300m i (vout) vout

1.0 3.0 2 ic(q4)*vc(q4) vout/i (vout)

10

FIGURE 53.3 Output characteristics of regulator circuit using PSPICE.

3. Current sources may not be connected in series. 4. Each node must be connected to at least two elements. For these simulations, PSPICE was used running on an IBM PC. The simulation took < 1 min of CPU time. Pitfalls. Many SPICE users forget that the first line in the input file is used as the title. Therefore, if the first line of the file is a circuit component, the component name will be used as the title and the component will not be included in the circuit. Convergence problems are sometimes experience if “difficult” bias conditions are created. An example of such a condition is if a diode is placed in the circuit backwards, resulting in a large forward bias voltage, SPICE will have trouble resolving the current. Another difficult case is if a current source were used instead of a voltage to bias the output in the previous example. If the user then tried to increase the output current above 10 A, SPICE would not be able to converge because the regulator will not allow such a large current.

AC Analysis AC analysis uses phasor analysis to calculate the frequency response of a circuit. The analysis is useful for calculating the gain, 3 dB frequency input and output impedance, and noise of a circuit as a function of frequency, bias conditions, temperature, etc. Numerical Method 1. A DC solution is performed to calculate the Q-point for the circuit. 2. A linearized circuit is constructed at the Q point. To do this, all nonlinear elements are replaced by their linearized equivalents. For example, a nonlinear current source I = aV12 + bV23 would be replaced by a linear voltage controlled current source I = V1(2aV1q ) + V2 (3bV22q ) .

3. All inductors and capacitors are replaced by complex impedances, and conductances evaluated at the frequency of interest. 4. Nodal analysis is now used to reduce the circuit to a linear algebraic complex matrix. The AC node voltages may now be found by applying an excitation vector (which represents the indepen­ dent voltage and current sources) and using Gaussian elimination (with complex arithmetic) to calculate the node voltages. AC analysis does have limitations and the following types of nonlinear or large signal problems cannot be modeled: 1. Distortion due to nonlinearities such as clipping, etc. 2. Slew rate-limiting effects © 2003 by CRC Press LLC

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3. Analog mixers 4. Oscillators Noise analysis is performed by including noise sources in the models. Typical noise sources include thermal noise in resistors In2 = 4kT∆ f/R, and shot In2 = 2qId ∆f, and flicker noise in semiconductor devices. Here, T is temperature in Kelvins, k is Boltzmann’s constant, and ∆f is the bandwidth of the circuit. These noise sources are inserted as independent current sources, In j( f) into the AC model. The resulting current due to the noise source is then calculated at a user-specified summation node(s) by multiplying by the gain function between the noise source and the summation node Ajs ( f). This procedure is repeated for each noise source, and then the contributions at the reference node are root mean squared (RMS) summed to give the total noise at the reference node. The equivalent input noise is then easily calculated from the transfer function between the circuit input and the reference node Ais ( f). The equation describing the input noise is therefore: Ii =

1

Ais ( f )

∑ [ A js ( f ) In j ( f )]

2

j

Example 53.2. Cascode Amplifier with Macro Models: Here, we find the gain, bandwidth, input imped­ ance, and output noise of a cascode amplifier. The circuit for the amplifier is shown in Fig. 53.5. The circuit is assumed to be fabricated in a monolithic IC process, so it will be necessary to consider some of the parasitics of the IC process. A cross-section of a typical IC bipolar transistor is shown in Fig. 53.4 along with some of the parasitic elements. These parasitic elements are easily included in the amplifier by creating a “macro model” for each transistor. The macro model is then implemented in SPICE form using subcircuits. The PSPICE circuit simulator allows the user to define parameters which are passed into the subcircuits. This capability is very useful in this case because the resistor model will vary, depending on the value of the resistor. It if is assumed for a certain resistor type that the width w (measured perpendicular to current flow) of the resistor is fixed, e.g., to the minimum line width of the process, then the resistance must be proportional to the length (l) of the resistor (R ∝ l/w). The parasitic capacitance of the resistor, on the other hand, is proportional to the junction area of the resistor, and therefore to the value of the resistance as well (C ∝ lw ∝ R). Using parameterized subcircuits these relations are easily implemented, and one subcircuit can be used to represent many different resistors (see Fig. 53.6). Here, we represent the capacitance using 2 diodes one at each end of the resistor. This was done because the resistor junction capacitance is voltage dependent. The input to the circuit is a voltage source (VIN), applied differentially to the amplifier. The output will be taken differentially across the collectors of the two upper transistors at nodes 2 and 3. The input impedance of the amplifier can be calculated as VIN/I(VIN) or because VIN = 1.0 just as 1/I(VIN). These quantities are shown plotted using PROBE in Fig. 53.7. It can be seen that the gain of the amplifier falls

C

B

E RE RBE

RB DBC RC

RCE

DSU RSU

FIGURE 53.4 BJT cross-section with macro model elements. © 2003 by CRC Press LLC

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1

SU 100 VSU + −

1000 X1

X3

2

X4 5 X6 11

8.3k X10 1.7k X11

VCC

3

3.7k R22 VIN

+ −

6

X5

7 + −

3300 X7 6700 X8

4 6.3k R21

1000 X2

6.3k R31

8 3.7k R32

10 X9 X12 9 50

FIGURE 53.5 Cascode amplifier for AC analysis, created using PSPICE.

Cascode amp with macro models. *P type substrate is node 100 vcc 1 0 10 vsu 100 0 0 vin 7 8 ac 1 x1 1 2 100 icr PARAMS: val = 1k x2 1 3 100 icr PARAMS: val = 1k x3 2 6 4 100 tran x4 3 6 5 100 tran x5 4 7 11 100 tran x6 5 8 11 100 tran *cascode base bias divider* x7 1 6 100 icr PARAMS: val = 3.3k x8 6 0 100 icr PARAMS: val = 6.7k *input bias dividers* r21 1 7 6.3k r22 7 0 3.7k r31 1 8 6.3k r32 8 0 3.7k *Current Source* x9 11 10 9 100 tran x10 9 0 100 icr PARAMS: val = 100 x11 9 0 100 icr PARAMS: val = 100 x12 1 10 100 icr PARAMS: val = 8.3k x13 10 0 100 icr PARAMS: val = 1.7k .op .noise v(2,3) vin 8 .ac dec 8 le6 le10 .probe

.subckt tran 1 2 3 4 PARAMS: val = 1

q1 5 2 3 mq{val}

rc 1 5 20/{val}

dbc 2 5 mdbc {val}

dsc 4 5 mdcs {val}

.model mq npn (is = le−15 bf = 100 br = 5

+ vaf = 30 var = 10 ikf = 5e−3 ikr = le−4

+ re = 5 rb = 100 rc = 50 cje = .1p cjc = .05p

+ tf = 100p tr = 1n)

.model mdbc d (is = 1e−16 cjo = .05p)

.model mdcs d (is = 1e−16 cjo = .01p)

+ rs = 1000)

.ends tran

.subckt icr 1 2 3 PARAMS: val = 1000

rr 1 2 {val}

d1 3 1 md {val/1000}

d2 3 1 md {val/1000}

.model md d (is = le−16 cjo = 10f rs = ik)

.ends icr

FIGURE 53.6 SPICE input listing for cascode amplifier of Fig. 53.5.

off at high frequency as expected. The input impedance also drops because parasitic capacitances shunt the input. It is also requested in Fig. 53.6 that noise analysis be performed at every 20th frequency point. A portion of the noise printout is shown in Fig. 53.8. It can be seen that the simulator calculates the noise contributions of each component in the circuit at the specified frequencies and displays them. The total © 2003 by CRC Press LLC

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1

1.0K

2

30V

Gain

20V

0.5K

Zin 10V

0

>> 0V 1.0MHz 1

10MHz 1/IM (VIN)

2

100MHz VM (2, 3) Frequency

1.0GHz

10GHz

FIGURE 53.7 Gain and input impedance of cascode amplifier.

TEMPERATURE = 27.000 DEG C

**** NOISE ANALYSIS FREQUENCY = 1.000E+09 HZ

**** DIODE SQUARED NOISE VOLTAGES (SQ V/HZ)

RS ID FN TOTAL

x1.d1 0.000E+00 0.000E+00 0.000E+00 0.000E+00

x1.d2 0.000E+00 0.000E+00 0.000E+00 0.000E+00

x2.d1 0.000E+00 0.000E+00 0.000E+00 0.000E+00

x2.d2 0.000E+00 0.000E+00 0.000E+00 0.000E+00

x3.dsc 6.098E−21 2.746E−24 0.000E+00 6.1000E−21

x4.dsc 6.098E−21 2.746E−24 0.000E+00 6.100E−21

**** TRANSISTOR SQUARED NOISE VOLTAGES (SQ V/HZ)

RB RC RE IB IC FN TOTAL

x3.q1 1.519E−19 3.185E−20 8.056E−21 2.190E−18 8.543E−17 0.000E+00 8.782E−17

x4.q1 1.519E−19 3.185E−20 8.056E−21 2.190E−18 8.543E−17 0.000E+00 8.782E−17

x5.q1 1.522E−16 7.277E−20 7.418E−18 3.390E−18 1.611E−16 0.000E+00 3.242E−16

****TOTAL OUTPUT NOISE VOLTAGE TRANSFER FUNCTION VALUE:

V(2,3)/vin EQUIVALENT INPUT NOISE AT vin

x6.q1 1.522E−16 7.277E−20 7.418E−18 3.390E−18 1.611E−16 0.000E+00 3.242E−19

x7.q1

0.000E+00

0.000E+00

0.000E+00

0.000E+00

0.000E+00

0.000E+00

0.000E+00

= 8.554E−16 SQ V/HZ

= 2.925E−08 V/RT HZ

= 9.582E+00

= 3.052E−09 V/RT HZ

FIGURE 53.8 Noise analysis results for cascode amplifier.

noise at the specified summing node (differentially across nodes 2 and 3) in this case is also calculated as well as the equivalent noise referenced back to the input. This example took < 1 min on an IBM PC. Pitfalls. Many novice users will forget that AC analysis is a linear analysis. They will, for example, apply a 1-V signal to an amplifier with 5-V power supplies and a gain of 1000 and be surprised when SPICE © 2003 by CRC Press LLC

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Computer-Aided Analysis

tells them that the output voltage is 1000 V. Of course, the voltage generated in a simple amplifier must be less than the power supply voltage, but to examine such clipping effects, transient analysis must be used. Likewise, selection of a proper Q point is important. If the amplifier is biased in a saturated portion of its response and AC analysis is performed, the gain reported will be much smaller than the actual large signal gain.

Transient Analysis Transient analysis is the most powerful analysis capability of a simulator because the transient response is so hard to calculate analytically. Transient analysis can be used for many types of analysis, such as switching speed, distortion, basic operation of certain circuits like switching power supplies. Transient analysis is also the most CPU intensive and can require 100 or 1000 times the CPU time as a DC or AC analysis. Numerical Method In a transient analysis time is discretized into intervals called time steps. Typically, the time steps are of unequal length, with the smallest steps being taken during portions of the analysis when the circuit voltages and currents are changing most rapidly. The capacitors and inductors in the circuit are then replaced by voltage and current sources based on the following procedure. The current in a capacitor is given by Ic = CdVc /dt. The time derivative can be approximated by a difference equation. I ck + I ck−1 = 2C

Vck − Vck−1 t k − t k −1

In this equation, the superscript k represents the number of the time step. Here, k is the time step we are presently solving for and (k – 1) is the previous time step. This equation can be solved to give the capacitor current at the present time step. I ck = Vck (2C ∆t ) − Vck−1 (2C ∆t ) − I ck−1 Here ∆t = t k – t k–1, or the length of the time step. As time steps are advanced, Vck−1 → Vck ; Ick-1 → I ck . Note that the second two terms on the right hand side of the above equation are dependent only on the capacitor voltage and current from the previous time step, and are therefore fixed constants as far as the present step is concerned. The first term is effectively a conductance (g = 2C/∆t) multiplied by the capacitor voltage, and the second two terms could be represented by an independent current source. The entire transient model for the capacitor therefore consists of a conductance in parallel with two current sources (the numerical values of these are, of course, different at each time step). Once the capacitors and inductors have been replaced as indicated, the normal method of DC analysis is used. One complete DC analysis must be performed for each time point. This is the reason that transient analysis is so CPU intensive. The method outlined here is the trapezoidal time integration method and is used as the default in SPICE. Example 53.3. Phase-Locked Loop Circuit: Figure 53.9 shows the phase-locked loop circuit. The first analysis considers only the analog multiplier portion (also called a phase detector). The second analysis demonstrates the operation of the entire PLL. For the first analyses we wish to show that the analog multiplier does indeed multiply its input voltages. To do this, sinusoidal signals of 0.5 V amplitude are applied to the inputs, one at 2 MHz, the second at 3 MHz. The analysis is performed in the time domain and a Fourier analysis is used to analyze the output. Because the circuit functions as a multiplier, the output should be

[

]

Vout = AVa sin(2e6πt ) Vb sin(3e6πt ) = AVaVb cos(1e 6πt ) − cos(5e 6πt ) © 2003 by CRC Press LLC

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M1

MULTIPLIER

M12 9

M13

1 Vcc + 6 −

VCO

M10

2 8 M3

M2

M4

M5 6

3

M6 11

M7

5

12

4 10 M8

7

M10

7

M9

D2 D4

D1 M1

8 M3

3 M4

100K Rfil 33 R2 70k 70k R1 22 7 03n Cfil

8

1

3

M2

D3 8

2 M5

M11 2 7

10 M8

Istart

6 C1 8

5P 7P Cpad 1 .5P Cpad 2

M9

M7

M6

M11 VCO

FIGURE 53.9 Phase-locked loop circuit for transient analysis, created with PSPICE.

Analog Multiplier Circuit. Vcc 1 0 10.0 Rbias 1 2 800k x1 1 9 3 4 5 6 2 10 mult rdum 9 0 1meg rin1 4 7 10k vbias 7 0 2 vin 3 4 sin(0.5 2meg 0 0) rin2 5 8 10k vbias2 8 0 5.0 vin2 5 6 sin(0.5 3meg 0 0) .tran 5n 3u 0 5n .four 1meg 20 v(10) .op .probe .options defl = 4u defas = 200p defad = 200p

.subckt mult 1 2 3 4 5 * Pwr Iout In1 In2 Pin1 Pin2 Ibias Vout *load resistor* m1 1 1 8 0 nmos w = 30u 1 = 4u *Upper diff pairs* m2 9 5 11 0 nmos w = 60u 1= 4u m3 8 6 11 0 nmos w = 60u 1= 4u m4 8 5 12 0 nmos w = 60u 1= 4u m5 9 6 12 0 nmos w = 60u 1= 4u *Lower diff pairs* m6 11 3 10 0 nmos w = 60u 1= 4u m7 12 4 10 0 nmos w = 60u 1= 4u *Drive Current Mirror* m8 7 7 0 0 nmos w = 60u 1= 4u m9 5 7 0 0 nmos w =60u 1= 4u m10 10 7 0 0 nmos w = 60u 1= 4u m11 6 7 0 0 nmos w =60u 1= 4u *Output current Mirror* m12 9 9 1 1 pmos w = 60u 1= 4u m13 2 9 1 1 pmos w = 60u 1= 4u

6

7

8

.model nmos nmos (level = 2 tox = 5e−8 + nsub = 2e 15 tpg = 1 vto = .9 uo = 450

+ ucrit = 8e4 uexp = .15 cgso = 5.2e−10

+ cgdo = 5.2e−10)

.model pmos pmos (level = 2 tox = 5e−8

+ nsub = 2e 15 tpg = −1 vto = −.9 uo = 200

+ ucrit = 8e4 uexp = .15 cgso = 5.2e−10

+ cgdo = 5.2e−10)

.ends mult

FIGURE 53.10 SPICE input file for analog multiplier portion of PLL.

The 1 and 5 MHz components are of primary interest. Feedthrough of the original signal will also occur, which will give 2 and 3 MHz components in the output. Other forms of nonlinear distortion will give components at higher frequencies. The SPICE input deck is shown in Fig. 53.10. The output of the Fourier analysis is shown in Fig. 53.11. It can be seen that the components at 1 and .5 MHz dominate and are a factor of 3 larger than the next largest component. The phase of the 1 and 5 MHz component is also offset by approximately 90° from the input (at 0°), as expected. © 2003 by CRC Press LLC

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FOURIER COMPONENTS OF TRANSIENT RESPONSE V(10) DC COMPONENT = 8.125452E+00 NO 1 2 3 4 5 6 7 8 9

FREQ HZ 1.000E+06 2.000E+06 3.000E+06 4.000E+06 5.000E+06 6.000E+06 7.000E+06 8.000E+06 9.000E+06

FOURIER COMP. 9.230E−02 6.462E−03 3.207E−02 1.097E−02 8.229E−02 1.550E−02 3.695E−02 7.943E−03 1.962E−02

NORMALIZED COMP. 1.000E+00 7.002E−02 3.474E−01 1.189E−01 8.916E−01 1.680E−01 4.004E−01 8.606E−02 2.126E−01

PHASE NORMALIZED (DEG) PHASE (DEG) 8.973E+01 0.000E+00 −1.339E+01 −1.031E+02 6.515E+01 −2.458E+01 −1.604E+02 −2.501E+02 −1.074E+02 −1.971E+02 −1.683E+02 −2.580E+02 7.984E+01 −9.886E+00 1.302E+02 4.044E+00 −1.149E+02 −2.046E+02

FIGURE 53.11 Results of transient and Fourier analyses of analog multiplier. Phase locked loop circuit. Vcc 1 0 10.0 Rbias 1 2 800k rin 1 4 5 100k vbias 5 0 2 Rfil 6 7 100k Cfil 6 0 .03n x1 1 6 3 4 18 19 2 10 mult r1 8 18 70k r2 9 19 70k vsens 7 17 0 x2 1 8 9 17 vco vin 3 4 sffm(0 1 600k 2 60k) .tran .05u 60u .probe .options acct defl = 4u defas = 200p + defad = 200p .subckt vco 1 22 33 10

* Pwr out1 out2 Ict1 * P current mirror m1 2 8 1 1 pmos w = 10u 1 = 4u m2 8 8 1 1 pmos w = 10u 1 = 4u m3 3 8 1 1 pmos w = 10u 1 = 4u

*Oscillator m4 3 2 7 0 nmos w = 10u 1 = 4u m5 2 3 6 0 nmos w = 10u 1 = 4u *N current mirror m6 6 10 0 0 nmos w = 20u 1 = 4u m7 8 10 0 0 nmos w = 4u 1 = 4u m8 10 10 0 0 nmos w = 20u 1 = 4u m9 7 10 0 0 nmos w = 20u 1 = 4u *source follower buffers m10 13 33 0 nmos w = 80u 1 = 4u m11 1 2 22 0 nmos w = 80u 1 = 4u *Frequency setting capacitor* c1 6 7 7pf cpad6 6 0.5pf cpad7 7 0.5pf

*Diode swing limiters* d1 1 5 md d2 1 4 md d3 5 2 md d4 4 3 md *Pulse to start VCO* istart 6 0 pulse (0 400u. 1us.01us +.01us .3us 100)

FIGURE 53.12 SPICE input listing for phase-locked loop circuit.

Simulation of the entire PLL will now be performed. The SPICE input deck is own in Fig. 53.12. The phase detector and voltage-controlled oscillator are modeled in separate subcircuits. The phase detector, or multiplier, subcircuit is the same as that of Fig. 53.10 and is omitted from Fig. 53.12 for brevity. Examine the VCO subcircuit and note the PULSE-type current source ISTART connected across the capacitor. The source gives a current pulse 0.3E-6 s wide at the start of the simulation to start the VCO running. To start a transient simulation SPICE first computes a DC operating point (to find the initial voltages Vck−1 on the capacitors). As this DC point is a valid, although not necessarily stable, solution, an oscillator will remain at this point indefinitely unless some perturbation is applied to start the oscillations. Remember, this is an ideal mathematical model and no noise sources or asymmetries exist that would start a real oscillator — it must be done manually. The capacitor C1 would have to be placed off-chip, and bond pad capacitance (CPAD1 and CPAD2) have been included at the capacitor nodes. Including the pad capacitances is very important if a small capacitor C1 is used for high-frequency operation. © 2003 by CRC Press LLC

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1.3v

1.2v Loop Filter Output

1.1v v(17)

3.0v

Oscillator Output

0v

Input Signal

−3.0v 0s

10us v(3, 4)−1.2

20us

v(8, 9)+1.2

30us

40us

50us

60us

Time

FIGURE 53.13 Transient analysis results of PLL circuit, created using PSPICE.

In this example, the PLL is to be used as a FM detector circuit and the FM signal is applied to the input using a single frequency FM voltage source. The carrier frequency is 600 kHz and the modulation frequency is 60 kHz. Figure 53.13 shows the input voltage and the output voltage of the PLL at the VCO output and at the phase detector output. It can be seen that after a brief starting transient, the PLL locks onto the input signal and that the phase detector output has a strong 60-kHz component. This example took 251 s on a Sun SPARC-2 workstation (3046 time steps, with an average of 5 Newton iterations per time step). Pitfalls. Occasionally, SPICE will fail and give the message “Timestep too small in transient analysis”, which means that the process of Newton iterations at certain time steps could not be made to converge. One of the most common causes of this is the specification of a capacitor with a value that is much too large, for example, specifying a 1-F capacitor instead of a 1pF capacitor (an easy mistake to make by not adding the “p” in the value specification). Unfortunately, we usually have no way to tell which capacitor is at fault from the type of failure generated other than to manually search the input deck. Other transient failures are caused by MOSFET models. Some models contain discontinuous capaci­ tances (with respect to voltage) and others do not conserve charge. These models can vary from version to version so it is best check the user’s guide.

Process and Device Simulation Process and device simulation are the steps that precede analog circuit simulation in the overall simulation flow (see Fig. 53.14). The simulators are also different in that they are not measurement driven as are analog circuit simulators. The input to a process simulator is the sequence of process steps performed (times, temperatures, gas concentrations) as well as the mask dimensions. The output from the process simulator is a detailed description of the solid-state device (doping profiles, oxide thickness, junction depths, etc.). This input to the device simulator is the detailed description generated by the process © 2003 by CRC Press LLC

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Computer-Aided Analysis

Process Flow

Process Simulation

Device Simulation

Masks

Parameter Extraction

Circuit Simulation

Netlist Extraction

Logic Simulation

FIGURE 53.14 Data flow for complete process-device-circuit modeling.

simulator (or via measurement). The output of the device simulator is the electrical characteristics of the device (IV curves, capacitances, switching transient curves). Process and device simulation are becoming increasingly important and widely used during the integrated circuit design process. A number of reasons exist for this: • As device dimensions shrink, second-order effects can become dominant. Modeling of these effects is difficult using analytical models. • Computers have greatly improved, allowing time-consuming calculations to be performed in a reasonable amount of time. • Simulation allows access to impossible to measure physical characteristics. • Analytic models are not available for certain devices, for example, thyristors, heterojunction devices, and IGBTS. • Analytic models have not been developed for certain physical phenomena, for example, single event upset, hot electron aging effects, latchup, and snap-back. • Simulation runs can be used to replace split lot runs. As the cost of fabricate test devices increases, this advantage becomes more important. • Simulation can be used to help device, process, and circuit designers understand how their devices and process work. Clearly, process and device simulation is a topic which can be been the topic of entire texts. The following sections attempt to provide an introduction to this type of simulation, give several examples showing what the simulations can accomplish, and provide references to additional sources of information.

Process Simulation Integrated circuit processing involves a number of steps which are designed to deposit (deposition, ion implantation), remove (etching), redistribute (diffusion), or transform (oxidation) the material of which the IC is made. Most process simulation work has been in the areas of diffusion, oxidation, and ion implantation; however, programs are available that can simulate the exposure and development of photo­ resist, the associated optical systems, as well as gas and liquid phase deposition and etch. A number of programs are available (either from universities or commercial vendors) which can model silicon processing. The best known program is SUPREM-IV, which was developed at Stanford University (Stanford, CA). SUPREM-IV is capable of simulating oxidation, diffusion, and ion implantation, and has simple models for deposition and etch. In the following section a very brief discussion of the governing equations used in SUPREM will be given along with the results of an example simulation showing the power of the simulator. Diffusion The main equation governing the movement of electrically charged impurities (acceptors in this case) in the crystal is the diffusion equation: DqCa  ∂C  = ∇ ⋅  D∇C − E  ∂t kT  © 2003 by CRC Press LLC

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Here, C is the concentration (#/cm3) of impurities, Ca is the number of electrically active impurities (#/cm3), q is the electron charge, k is Boltzmann’s constant, T is temperature in degrees Kelvin, D is the diffusion constant, and E is the built-in electric field. The built-in electric field E in (V/cm) can be found from: E=−

kT 1 ∇n q n

In this equation, n is the electron concentration (#/cm3), which in turn can be calculated from the number of electrically active impurities (Ca). The diffusion constant (D) is dependent on many factors. In silicon the following expression is commonly used: 2   n  n n D = FIV  Dx + D+ i + D− + D=     n ni  ni   

The four D components represent the different possible charges states for the impurity: (x) neutral, (+) positive, (–) negative, (=) doubly negatively charged. ni is the intrinsic carrier concentration, which depends only on temperature. Each D component is in turn given by an expression of the type  B D = A exp −   kT  Here, A and B are experimentally determined constants, different for each type of impurity (x, +, –, =). B is the activation energy for the process. This expression derives from the Maxwellian distribution of particle energies and will be seen many times in process simulation. It is easily seen that the diffusion process is strongly influenced by temperature. The term FIV is an enhancement factor which is dependent on the concentration of interstitials and vacancies within the crystal lattice (an interstitial is an extra silicon atom which is not located on a regular lattice site; a vacancy is a missing silicon atom which results in an empty lattice site) FIV ∝ CI + CV. The concentration of vacancies, CV, and interstitials, CI, are in turn determined by their own diffusion equation: ∂C v = +∇ ⋅ DV ⋅ ∇CV − R + G ∂t In this equation, DV is another diffusion constant of the form A exp(–B/kT). R and G represent the recombination and generation of vacancies and interstitials. Note that an interstitial and a vacancy may recombine and in the process destroy each other, or an interstitial and a vacancy pair may be simulta­ neously generated by knocking a silicon atom off its lattice site. Recombination can occur anywhere in the device via a bulk recombination process R = A(CVCl)exp(–b/kT). Generation occurs where there is damage to the crystal structure, in particular at interfaces where oxide is being grown or in regions where ion implantation has occurred, as the high-energy ions can knock silicon atoms off their lattice sites. Oxidation Oxidation is a process whereby silicon reacts with oxygen (or with water) to form new silicon dioxide. Conservation of the oxidant requires the following equation: dy F = dt N Here, F is the flux of oxidant (#/cm2/s), N is the number of oxidant atoms required to make up a cubic centimeter of oxide, and dy/dt is the velocity with which the Si-SiO2, interface moves into the silicon. In © 2003 by CRC Press LLC

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general, the greater the concentration of oxidant (C0), the faster the growth of the oxide and the greater the flux of oxidant needed at the Si-SiO2, interface. Thus, F = ksC0. The flux of oxidant into the oxide from the gaseous environment is given by: F = h ( HPox − C0 ) Here, H is a constant, P is the partial pressure of oxygen in the gas, and C0 is the concentration of oxidant in the oxide at the surface and h is of the form A exp(–B/kT). Finally, the moment of the oxidant within the already existing oxide is governed by diffusion: F = D0∇ C When all these equations are combined, it is found that (in the one-dimensional case) oxides grow linearly dy/dt ∝ t when the oxide is thin and the oxidant can move easily through the existing oxide. As the oxide grows thicker dy/dt ∝ t because the movement of the oxidant through the existing oxide becomes the rate-limiting step. Modeling two-dimensional oxidation is a challenging task. The newly created oxide must “flow” away from the interface where it is being generated. This flow of oxide is similar to the flow of a very thick or viscous liquid and can be modeled by a creeping flow equation: ∇ 2V ∝ ∇P ∇⋅V = 0 V is the velocity at which the oxide is moving and P is the hydrostatic pressure. The second equation results from the incompressibility of the oxide. The varying pressure P within the oxide leads to mechan­ ical stress, and the oxidant diffusion constant D0 and the oxide growth rate constant ks are both dependent on this stress. The oxidant flow and the oxide flow are therefore coupled because the oxide flow depends on the rate at which oxide is generated at the interface and the rate at which the new oxide is generated depends on the availability of oxidant, which is controlled by the mechanical stress. Ion Implantation Ion implantation is normally modeled in one of two ways. The first involves tables of moments of the final distribution of the ions that are typically generated by experiment. These tables are dependent on the energy and the type of ion being implanted. The second method involves Monte-Carlo simulation of the implantation process. In Monte-Carlo simulation, the trajectories of individual ions are followed as they interact with (bounce off) the silicon atoms in the lattice. The trajectories of the ions, and the recoiling Si atoms (which can strike more Si atoms) are followed until all come to rest within the lattice. Typically several thousand trajectories are simulated (each will be different due to the random probabil­ ities used in the Monte-Carlo method) to build up the final distribution of implanted ions. Monte-Carlo has advantages in that the damage to the lattice can be calculated during the implant process. This damage creates interstitials and vacancies that affect impurity diffusion, as was seen earlier. Monte-Carlo can also model channeling, which is a process whereby the trajectories of the ions align with the crystal planes, resulting in greater penetration of the ion than in a simple amorphous target. Monte-Carlo has the disadvantage of being CPU intensive. Process simulation is always done in the transient mode using time steps as was done with transient circuit simulation. Because partial differential equations are involved, rather than ordinary differential equations, spatial discretization is needed as well. To numerically solve the problem, the differential equations are discretized on a grid. Either rectangular or triangular grids in one, two, or three dimensions are commonly used. This discretization process results in the conversion of the partial differential equations into a set of nonlinear algebraic equations. The nonlinear equations are then solved using a Newton method in a way very similar to the method used for the circuit equations in SPICE. Example 53.4. NMOS Transistor: In this example, the process steps used to fabricate a typical NMOS transistor will be simulated using SUPREM-4. These steps are: © 2003 by CRC Press LLC

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Polysilicon

Oxide

Aluminum

2.00

Distance (microne) −2.00 0.00

Silicon

−4.00

−2.00

0.00 Distance (microne)

2.00

4.00

FIGURE 53.15 Complete NMOS transistor cross section generated by process simulation, created with TMA SUPREM-4.

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.

Grow initial oxide (30 min at 1000 K). Deposit nitride layer (a nitride layer will prevent oxidation of the underlying silicon). Etch holes in nitride layer. Implant P+ channel stop (boron dose = 5e12, energy = 50 keV). Grow the field oxide (180 min at 1000 K wet O2). Remove all nitride. Perform P channel implant (boron dose = 1e11, energy = 40 keV). Deposit and etch polysilicon for gate. Oxidize the polysilicon (30 min at 1000 K, dry O2). Implant the light doped drain (arsenic dose = 5e13 energy = 50 keV). Deposit sidewall space oxide. Implant source and drain (arsenic, dose = 1e15, energy = 200 keV). Deposit oxide layer and etch contact holes. Deposit and etch metal.

The top 4 µm of the completed structure, as generated by SUPREM-4, is shown in Fig. 53.15. The actual simulation structure used is 200 µm deep to allow correct modeling of the diffusion of the vacancies and interstitials. The gate is at the center of the device. Notice how the edges of the gate have lifted up due to the diffusion of oxidant under the edges of the polysilicon (the polysilicon, as deposited in step 8, is flat). The dashed contours show the concentration of dopants in both the oxide and silicon layers. The short dashes indicate N-type material, while the longer dashes indicate P-type material. This entire simulation requires about 30 min on a Sun SPARC-2 workstation.

Device Simulation Device simulation uses a different approach from that of conventional lumped circuit models to deter­ mine the electrical device characteristics. Whereas with analytic or empirical models all characteristics are determined by fitting a set of adjustable parameters to measured data, device simulators determine the electrical behavior by numerically solving the underlying set of differential equations. The first of these equations is the Poisson equation, which describes the electrostatic potential within the device.

(

∇ ⋅ ε ⋅ ∇Ψ = q N a− − N d+ − p + n − Q f © 2003 by CRC Press LLC

)

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Nd and Na are the concentration of donors and acceptors, i.e., the N- and P-type dopants. Qf is the concentration of fixed charge due, for example, to traps or interface charge. The electron and hole concentrations are given by n and p, respectively, and Ψ is the electrostatic potential. A set of continuity equations describes the conservation of electrons and holes:  ∂n  1 =  ∇ ⋅ J n − R + G ∂t  q   ∂p  1 =  − ∇ ⋅ J p − R + G ∂t  q  In these equations, R and G describe the recombination and generation rates for the electrons and holes. The recombination process is influenced by factors such as the number of electrons and holes present as well as the doping and temperature. The generation rate is also dependent upon the carrier concentrations, but is most strongly influenced by the electric field, with increasing electric fields giving larger generation rates. Because this generation process is included, device simulators are capable of modeling the breakdown of devices at high voltage. Jn and Jp are the electron and hole current densities (in amperes per square centimeter). These current densities are given by another set of equations:   kT J n = qµ −n∇Ψ + n ∇n q   kT   J p = qµ − p∇Ψ − p ∇p q   In this equation, k is Boltzmann’s constant, µ is the carrier mobility, which is actually a complex function of the doping, n, p, electric field, temperature, and other factors. In silicon the electron mobility will range between 50 and 1000 and the hole mobility will normally be a factor of 2 smaller. In other semiconductors such as gallium arsenide the electron mobility can be as high as 5000. Tn and Tp are the electron and hole mean temperatures, which describe the average carrier energy. In many models these default to the device temperature (300 K). In the first term the current is proportional to the electric field (∇ Ψ), and this term represents the drift of carriers with the electric field. In the second term the current is proportional to the gradient of the carrier concentration (∇n), so this term represents the diffusion of carriers from regions of high concentration to those of low concentration. The model is therefore called the drift-diffusion model. In devices in which self-heating effects are important, a lattice heat equation can also be solved to give the internal device temperature: σ(T )

∂T = H + ∇ ⋅ λ(T ) ⋅ ∇T ∂t

(

)

H = − J n + J p ⋅ ∇Ψ + H R where H is the heat generation term, which includes resistive (Joule) heating as well as recombination heating, Hu . The terms σ(T), λ(T) represent the specific heat and the thermal conductivity of the material (both temperature dependent). Inclusion of the heat equation is essential in many power device problems. As with process simulation partial differential equations are involved, therefore, a spatial discretization is required. As with circuit simulation problems, various types of analysis are available: • Steady-state (DC), used to calculate characteristic curves of MOSFETs, BJTs diodes, etc. • AC analysis, used to calculate capacitances, Y-parameters, small signal gains, and S-parameters • Transient analysis, used for calculation of switching and large signal behavior, and special types of analysis such as radiation effects © 2003 by CRC Press LLC

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2.00

Vgs = 3

1.00

Id (Ampa/Micron)*10t−4

3.00

The Circuits and Filters Handbook, Second Edition

Vgs = 2

0.00

Vgs = 1

0.0

2.0

4.0

6.0 Vds (Volts)

8.0

10.0

12.0

FIGURE 53.16 Id vs. Vds curves generated by device simulation, created with TMA MEDICI.

Example 53.5. NMOS IV Curves: The structure generated in the previous SUPREM-IV simulation is now passed into the device simulator and bias voltages are applied to the gate and drain. Models were included which account for Auger and Shockley Reed Hall recombination, doping and electric fielddependent mobility, and impact ionization. The set of drain characteristics obtained is shown in Fig. 53.16. Observe how the curves bend upward at high Vds as the device breaks down. The Vgs = 1 curve has a negative slope at Id = 1.5e-4A as the device enters snap-back. It is possible to model this type of behavior because impact ionization is included in the model. Figure 53.17 shows the internal behavior of the device with Vgs = 3 V and Id = 3e-4A. The filled contours indicate impact ionization, with the highest rate being near the edge of the drain right beneath the gate. This is to be expected because this is the region in which the electric field is largest due to the drain depletion region. The dark lines indicate current flow from the source to the drain. Some current also flows from the drain to the substrate. This substrate current consists of holes generated by the impact ionization. The triangular grid used in the simulation can be seen in the source, drain, and gate electrodes. A similar grid was used in the oxide and silicon regions.

Appendix Circuit Analysis Software SPICE2, SPICE3: University of California, Berkeley PSPICE: MicroSim Corporation, Irvine, CA (used in this chapter) HSPICE: Meta Software, Campbell, CA IsSPICE: Intusoft, San Pedro, CA SPECTRE: Cadence Design Systems, San Jose, CA SABRE: Analogy, Beaverton, OR

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3.00

2.00

Distance (Microns) 1.00 0.00

−1.00

−2.00

Computer-Aided Analysis

−4.00

−2.00

0.00 Distance (Microns)

2.00

4.00

FIGURE 53.17 Internal behavior of MOSFET under bias, created with TMA MEDICI.

Process and Device Simulators SUPREM-4, PISCES: Stanford University, Palo Alto, CA MINIMOS: Technical University, Vienna, Austria SUPREM-4, MEDICI, DAVINCI: Technology Modeling Associates, Palo Alto, CA (used in this chapter) SEMICAD: Dawn Technologies, Sunnyvale, CA

References [1] P. Antognetti and G. Massobrio, Semiconductor Device Modeling with SPICE, New York: McGrawHill, 1988. [2] P. W. Tuinenga, SPICE, A Guide to Circuit Simulation and Analysis Using PSPICE, Englewood Cliffs, NJ: Prentice Hall, 1988. [3] J. A. Connelly and P. Choi, Macromodeling with SPICE, Englewood Cliffs, NJ: Prentice Hall, 1992. [4] S. Selberherr, Analysis and Simulation of Semiconductor Devices, Berlin: Springer-Verlag, 1984. [5] R. Dutton and Z. Yu, Technology CAD, Computer Simulation of IC Process and Devices, Boston: Kluwer Academic, 1993.

53.2 Parameter Extraction For Analog Circuit Simulation Peter Bendix Introduction Definition of Device Modeling We use various terms such as device characterization, parameter extraction, optimization, and model fitting to address an important engineering task. In all of these, we start with a mathematical model that

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describes the transistor behavior. The model has a number of parameters that are varied or adjusted to match the IV (current-voltage) characteristics of a particular transistor or set of transistors. The act of determining the appropriate set of model parameters is what we call device modeling. We then use the model with the particular set of parameters that represent our transistors in a circuit simulator such as SPICE1 to simulate how circuits with our kinds of transistors will behave. Usually, the models are supplied by the circuit simulator we chose. Occasionally, we may want to modify these models or construct our own models. In this case we need access to the circuit simulator model subroutines as well as the program that performs the device characterization. Most people believe the preceding description covers device modeling. However, we feel this is a very narrow definition. One can obtain much more information by characterizing a semiconductor process than just providing models for circuit simulation. If the characterization is done correctly, it can provide detailed information about the fabrication process. This type of information is useful for process archi­ tects as an aid in developing future processes. In addition, the wealth of information from the parameters obtained can be used by process and product engineers to monitor wafers routinely. This provides much more information than what is usually obtained by doing a few crude electrical tests for process moni­ toring. Finally, circuit designers can use device characterization as a means of optimizing a circuit for maximum performance. Therefore, instead of just being a tool used by specialized device physicists, device characterization is a tool for process architects, process and product engineers, and circuit design­ ers. It is a tool that can and should be used by most people concerned with semiconductor manufacture and design. Steps Involved in Device Characterization Device characterization begins with a test chip. Without the proper test chip structures, proper device modeling cannot be done from measured data. A good test chip for MOS technology would include transistors of varying geometries, gate oxide capacitance structures, junction diode capacitance structures, and overlap capacitance structures. This would be a minimal test chip. Additional structures might include ring oscillators and other circuits for checking the AC performance of the models obtained. It is very important that the transistors be well designed and their geometries be chosen appropriate for the technology as well as the desired device model. For bipolar technology modeling, the layout of structures used to get S-parameter measurements is very critical. Although a complete test chip description is beyond the scope of this book, be aware that even perfect device models cannot correct for a poor test chip. Next, we need data that represent the behavior of a transistor or set of transistors of different sizes. These data can come from direct measurement or they can be produced by a device simulator such as PISCES.2 Typically, one does voltage sweeps on various nodes of the transistor and measures the output current at some or all of these nodes. For example, in an MOS transistor, one might sweep the gate voltage and measure the resulting drain current, holding the drain and bulk voltages fixed. The equiment used to do DC device characterization measurements is usually a DC parametric tester. This equipment usually has a set of SMUs (source/measure units) that can force voltage and measure current, or force current and measure voltage. The measuring equipment can be manually run or controlled by a computer. In either case the measured data must be put onto a hard disk. For oxide capacitors, junction diodes, and overlap capacitors, a capacitance or inductance, capacitance, resistance (LCR) meter is used to do the measurements. For junction capacitance models, a junction diode (source to bulk, for example) has a reverse bias sweep done and the capacitance is measured at each bias point. For oxide and overlap capacitances, only a single capacitance measurement at one bias voltage is required.

1

SPICE is a circuit simulation program from the Department of Electrical Engineering and Computer Science at the University of California at Berkeley. 2PISCES is a process simulation program from the Department of Electrical Engineering at Stanford University, Stanford, CA. © 2003 by CRC Press LLC

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DC Parametric Tester

PC/Unix Workstation

RS232 to IEEE-488 Interface

Capacitance Meter Wafer Prober Switching Matrix

Network Analyzer

FIGURE 53.18 Tyical hardware measuring equipment for device characterization.

In a more automated environment, switching matrices, semiautomated probers, and temperaturecontrolled chucks are added. The same equipment is used for bipolar devices. In addition, network analyzers are often used for S-parameter characterization to obtain the related AC transit time parameters of bipolar transistors. A typical collection of measuring equipment might look like Fig. 53.18. It is also possible to use a device simulator like PISCES, or a combination of a process simulator like SUPREM-IV3 coupled to a device simulator, to provide the simulated results. The process recipe steps are fed into SUPREM-IV, which produces a device structure and associated profiles of all dopants; this information is then fed into the device simulator along with a description of voltage sweeps to be applied to various device electrodes. The output of the device simulator is a set of IV characteristics which closely represent what would have been measured on a real device. The benefits of using simulation over measurement are that no expensive measurement equipment or fabricated wafers are necessary. This can be very helpful when trying to predict the device characteristics of a new fabrication process before any wafers have been produced. Once the measured (or simulated) data are available, parameter extraction software is used to find the best set of model parameter values to fit the data. This can be done by extraction, optimization, or a combination of the two. Extraction is simpler and quicker, but not as accurate as optimization. In extraction simplifying assumptions are made about the model equations and parameter values are extracted using slope and intercept techiques, for example. In optimization general least-squares curve fitting routines are employed to vary a set or subset of parameters to fit the measured data. Extraction and optimization are covered in more detail in the following sections. Least-Squares Curve Fitting (Analytical) We begin this section by showing how to do least-squares curve fitting by analytical solutions, using a simple example to illustrate the method. We then discuss least-squares curve fitting using numerical solutions in the next section. We can only find analytical solutions to simple problems. The more complex ones must rely on numerical techniques. Assume a collection of measured data, m1, …, mn . For simplicity, let these measured data values be functions of a single variable, v, which was varied from v1 through vn , measuring each mi data point at each variable value vi , i running from 1 to n. For example, the mi data points might be drain current of an MOS transistor, and the vi might be the corresponding values of gate voltage. Assume that we have a

3SUPREM-IV is a process simulation program from the Department of Electrical Engineering at Stanford Uni­ versity, Stanford, CA.

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model for calculating simulated values of the measured data points, and let these simulated values be denoted by s1, …, sn . We define the least-squares, root mean square (RMS) error as

Errorrms

   =   

1/ 2

2 weight i (si − mi )   i=1 n  2 {weightimi }  i=1 

n

∑{

}

(53.1)

∑

where a weighting term is icluded for each data point. The goal is to have the simulated data match the measured data as closely as possible, which means we want to minimize the RMS error. Actually, what we have called RMS error is really the relative RMS error, but the two terms are used synonymously. There is another way of expressing the error, called the absolute RMS error, defined as follows:

Errorrms

   =   

n

∑ {weight (s − m )} i

i

i

i=1 n

∑ {weight m i

1/ 2

2

min

}

2

i=1

      

(53.2)

where we have used the term mmin in the denominator to represent some minimum value of the measured data. The absolute RMS error is usually used when the measured values approach zero to avoid problems with small or zero denominators in (53.1). For everything that follows, we consider only the relative RMS error. The best result is obtained by combining the relative RMS formula with the absolute RMS formula by taking the maximum of the denominator from (53.1) or (53.2). We have a simple expression for calculating the simulated data points, si, in terms of the input variable, v, and a number of model parameters, p1, …, pm . That is, si = f (v i , p1 , K, pm )

(53.3)

where f is some function. Minimizing the RMS error function is equivalent to minimizing its square. Also, we can ignore the term in the denominator of (53.1) as concerns minimizing, because it is a normalization term, In this spirit, we can define a new error term, 2 Error = (Errorrms )  

n



∑ {weight m }  2

i

i

(53.4)

i=1

and claim that minimizing Error is equivalent to minimizing Errorrms. To minimize Error, we set all partial derivatives of it with respect to each model parameter equal to zero; that is, write ∂(Error ) =0 ∂p j

for j = 1, …, m

(53.5)

Then, solve the preceding equations for the value of pj . Least-Squares Curve Fitting. Analytic Example: Write a simple expression for the drain current of an MOS transistor in the linear region in terms of a single variable, the gate voltage, Vgs , and also in terms of two model parameters, β and Vth ;

(

)

I ds = β Vgs − Vth Vds © 2003 by CRC Press LLC

(53.6)

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We denote the measured drain current by Imeas . In terms of our previous notation, we have the following substitutions: s → Ids v → Vgs p1 → β p2 → Vth We have two conditions to satify for minimizing the error: ∂(Error ) =0 ∂β

(53.7)

∂(Error ) =0 ∂Vth

(53.8)

Equations (53.7) and (53.8) imply, respectively,

∑[β(V n

gsi

](

)

)

− Vth Vds − I measi Vgsi − Vth = 0

i=1

∑[β(V n

gsi

)

− Vth Vds − I measi

i=1

]=0

(53.9)

(53.10)

Solving (53.9) and (53.10) is straightforward but tedious. The result is Vth =

[Term Term − Term Term ] [ Term − Term Term ] 1

2

n

3

1

[

2

4

(53.11)

4

 1  nTerm1 − Term 2Term 4 β=  nTerm 3 − Term 22  Vds 

[

]

]

(53.12)

where n is the number of data points that i is summed over, and n

Term1 =

∑V

I

(53.13)

∑V

(53.14)

gsi measi

i=1

n

Term 2 =

gsi

i=1

n

Term 3 =

∑V

2 gsi

(53.15)

i=1

and n

Term 4 =

∑I i=1

© 2003 by CRC Press LLC

measi

(53.16)

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Thus, analytical solutions can become quite messy, even for the simplest model expressions. In fact, it is usually not possible to solve the system of equations analytically for more complicated models. Then, we must rely on numerical solutions. One further word of caution is required. One may try comparing analytical solutions to those obtained by numerical techniques. They almost always will not match. The reason is that the weighting functions used to calculate Errorrms are different for the two cases. In order to compare the two techniques, one must know the exact algorithm that the numerical least-squares curve fitting routine is using and be able to match the weighting functions. Often weighting is implicit in the numerical least-squares curve fitting algorithm that is not explicitly obvious. Least-Squares Curve Fitting (Numerical) For almost all practical applications we are forced to do least-squares curve fitting numerically, because the analytic solutions as previously discussed are not obtainable in closed form. What we are calling leastsquares curve fitting is more generally known as nonlinear optimization. Many fine references on this topic are available. We highlight only the main features here, and paraphrase parts of [2] in what follows. Basically, we want to solve the optimization problem whose goal is to minimize the function F(x) where F is some arbitrary function of the vector x. If extra conditions exist on the components of x, we are then solving a constrained, nonlinear optimization problem. When using least-squares fitting for model parameter optimization, we usually constrain the range of the fitting parameters. This type of constraint is a very simple one and is a special case of what is called nonlinear constrained optimization. This or the unconstrained approach are the types normally used for model parameter optimization. For simplicity, let F be a function of a single variable, x, instead of the vector, x. We state without proof that a necessary condition for a minimum of F(x) to exist is that F′ =

∂F =0 ∂x

(53.17)

This means we solve the minimization problem if we can solve for the zeroes of F′. This is exactly what we did when we went through the least-squares analytical method. One numerical approach to solving for the zeroes of a function, f, is Newton’s method. This is an iterative method in which we write x k+1 = x k −

f (xk )

f ′( x k )

(53.18)

Steepest Descents Method. Next consider the more general case in which F is now a function of many variables, x; i.e., F is mulltivariate. We want to consider numerical techniques for finding the minimum of F by iteration. We also would like to take iteration steps that decrease the value of F at each step. This imposes what is called a descent condition: F ( x k+1 ) < F ( x k )

(53.19)

where k is the iteration number. Solving the minimization problem amounts to choosing a search direction for the vector x such that at each iteration F decreases until some convergence criterion is satisfied with xk as the solution. Let us write F as a Taylor series expanded around the point x, with p a vector of unit length and h a scalar 1 F ( x + hp) = F ( x ) + hg T ( x )p + h 2 pT G( x )p + K 2

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(53.20)

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where in (53.20), g(x) is the gradient (first derivative in the p direction) of F(x) and G(x) is the curvature (second derivative in the p direction) of F(x). The upper case T means matrix transpose. We want to choose a direction and step length for the next iteration in which x k+1 = x k + hk p k

(53.21)

where in (53.21), p is a unit vector in the search direction and h is the step size. In the method of steepest descents we set p k = −g ( x k )

(53.22)

That is, the method of steepest descents chooses the search direction to be opposite the first derivative in the direction xk . Newton’s Method. The method of steepest descents is a first derivative method. Newton’s method is a second derivative method (this is not to be confused with the simple Newton’s method discussed previously). Referring to (53.20), the Newton direction of search is defined to be the vector p, which satisfies G ( x k )p k = − g ( x k )

(53.23)

Finding pk from the preceding equation involves calculating second derivatives to compute G. Gauss–Newton Method. We want to modify Newton’s method so that second derivative calculations are avoided. To do this, consider the so-called least-squares problem in which F can be written as F (x ) =

∑[ f (x)]

2

i

(53.24)

In this special case, we can write g (x ) = J T (x ) f (x )

(53.25)

G ( x ) = J T ( x ) J ( x ) + Q( x )

(53.26)

where J is the Jacobian of f and Q( x ) =

∑ f (x)G (x) i

i

(53.27)

where Gi is the so-called Hessian of f. Substituting (53.25) and (53.26) into (53.23) gives

[ J (x ) J (x ) + Q ] p T

k

k

k

k

= − J T (x k ) f (x k )

(53.28)

If we throw away the Q term, (53.28) becomes

[ J (x )J (x )]p T

k

k

k

= − J T (x k ) f (x k )

(53.29)

a condition for finding the search direction, pk , which does not involve second derivatives. Solving (53.29) is tantamount to solving the linear least-squares problem of minimizing

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[

]

F (x) = ∑ ji (xk ) pk + fi (xk )

2

(53.30)

When the search direction, pk, is found from (53.29), we call this the Gauss–Newton method. Levenberg-Marquardt Algorithm. Both the method of steepest descents and the Gauss–Newton method have advantages and disadvantages. Briefly stated, the method of steepest descents will move toward the correct solution very quickly, but due to the large steps it takes, it can jump past the solution and not converge. The Gauss–Newton method, however, moves more slowly toward the correct solution, but because it tends to take smaller steps, it will converge better as its approaches the solution. The Levenberg–Marquardt algorithm was designed to combine the benefits of both the steepest descents and Gauss–Newton methods. The Levenberg–Marquardt search direction is found by solving

[ J (x ) J (x ) + λ I ] p T

k

k

k

k

= − J T (x k ) f (x k )

(53.31)

where λk is a nonnegative scalar and I is the identity matrix. Note that (53.31) becomes (53.29) when λk is zero, so that the Levenberg–Marquardt search direction becomes the Gauss–Newton in this case; as λk → ∞, pk becomes parallel to –J T(xk ) f(xk ), which is just –g(xk ), the direction of steepest descents. Generally speaking, in the Levenberg–Marquardt algorithm the value of λk is varied continuously, starting with a value near the steepest descents direction (large λk ) and moving toward smaller values of λk as the solution is approached. Extraction (as Opposed to Optimization) The terms “extraction” and “optimization” are, unfortunately, used interchangeably in the semiconductor industry; however, strictly speaking, they are not the same. By optimization, we mean using generalized least-squares curve fitting methods such as the Levenberg–Marquardt algorithm to find a set of model parameters. By extraction, we mean any technique that does not use general least-squares fitting methods. This is a somewhat loose interpretation of the term extraction, but perhaps the following discussion will justify it. Suppose we have measured the drain current of an MOS transistor in the linear region at zero backbias (the bulk node bias) and we want to find the threshold voltage by extraction (as opposed to optimization). We could plot the drain current vs. gate voltage, draw a tangent line at the point where the slope of Ids is a maximum, and find the Vgs axis intercept of this tangent line. This would give us a crude value of the threshold voltage, Vth (neglecting terms such as Vds /2). This would be a graphic extraction technique; it would not involve using least-squares optimization. We could also apply the preceding graphic technique in an equivalent algorithmic way, without drawing any graphs. Let us write a linear region equation for the drain current −α V −V I ds = β Vgs − Vth Vds 1 + Ke ( gs th )   

(

)

(53.32)

In (53.32), the exponential term is the subthreshold contribution to the drain current; it becomes negligible for Vgs  Vth . To find the value of Vgs where the maximum slope occurs, we set the derivative of Ids with respect to Vgs equal to zero and solve for Vgs. The solution is 1 + K  Vgs (maximum slope) = Vth +    2αK 

(53.33)

where in obtaining (53.33) we used the approximation −α V −V e ( gs th ) ≅ 1 − α Vgs − Vth

(

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)

(53.34)

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If we rewrite (53.33) for Vth in terms of Vgs (maximum slope) we have 1 + K  Vth = Vgs (maximum slope) −    2αK 

(53.35)

Therefore, the approach is to use a measurement search routine that seeks the maximum slope, ∆Ids /∆Vgs , where the ∆ is calculated as numerical derivatives, and having found Vgs (maximum slope) through measurement, use (53.35) to calculate Vth from Vgs (maximum slope). We could continue by including the effects of mobility degradation, modifying (53.32) to  β I ds =  1 + θ Vgs − Vth 

(

  Vgs − Vth Vds 1 + Ke −α (Vgs −Vth )     

)(

)

(53.36)

where we have now included the effects of mobility degradation with the θ term. The extraction analysis can be done again by including this term, with a somewhat different solution obtained using suitable approximations. The main point is that we write the equations we want and then solve them by whatever approximations we choose, as long as these approximations allow us to get the extracted results in closed form. This is parameter extraction. Extraction vs. Optimization Extraction has the advantage of being much faster than optimization, but it is not always as accurate. It is also much harder to supply extraction routines for models that are being developed. Each time you make a change in the model, you must make suitable changes in the corresponding extraction routine. For optimization, however, no changes are necessary other than the change in the model itself, because least-squares curve fitting routines are completely general. Also, if anything goes wrong in the extraction algorithm (and no access to the source code is available), almost nothing can be done to correct the problem. With optimization, one can always change the range of data, weighting, upper and lower bounds, etc. A least-squares curve fitting program can be steered toward a correct solution. Novices at device characterization find least-squares curve fitting somewhat frustrating because a certain amount of user intervention and intuition is necessary to obtain the correct results. These beginners prefer extraction methods because they do not have to do anything. However, after being burned by extraction routines that do not work, a more experienced user will usually prefer the flexibility, control, and accuracy that optimization provides. Commercial software is available that provides both extraction and optimization together. The idea here is to first use extraction techniques to make reasonable initial guesses and then use these results as a starting point for optimization, because optimization can give very poor results if poor initial guesses for the parameters are used. Nothing is wrong with using extraction techniques to provide initial guesses for optimization, but for an experienced user this is rarely necessary, assuming that the least-squares curve fitting routine is robust (converges well) and the experienced user has some knowledge of the process under characterization. Software that relies heavily on extraction may do so because of the nonrobustness of its optimizer. These comments apply when an experienced user is doing optimization locally, not globally. For global optimization (a technique we do not recommend), the previous comparisons between extraction and optimization are not valid. The following section contains more detail about local vs. global optimization. Strategies: General Discussion The most naive way of using an optimization would be to take all the measured data for all devices, put them into one big file, and fit to all these data with all model parameters simultaneously. Even for a very high quality, robust optimization program the chances of this method converging are slight. Even if the program does converge, it is almost certain that the values of the parameters will be very unphysical. © 2003 by CRC Press LLC

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This kind of approach is an extreme case of global optimization. We call any optimization technique that tries to fit with parameters to data outside their region of applicability a global approach. That is, if we try to fit to saturation region data with linear region parameters such as threshold voltage, mobility, etc., we are using a global approach. In general, we advise avoiding global approaches, although in the strategies described later, sometimes the rules are bent a little. Our recommended approach is to fit subsets of relevant parameters to corresponding subsets of relevant data in a way that makes physical sense. For example, in the MOS level 3 model, VT0 is defined as the threshold voltage of a long, wide transistor at zero back-bias. It does not make sense to use this parameter to fit to a short channel transistor, or to fit at nonzero back-bias values, or to fit to anywhere outside the linear region. In addition, subsets of parameters should be obtained in the proper order so that those obtained at a later step do not affect those obtained at earlier steps. That is, we would not obtain saturation region parameters before we have obtained linear region parameters because the values of the linear region parameters would influence the saturation region fits; we should have to go back and reoptimize on the saturation region parameters after obtaining the linear region parameters. Finally, never use optimization to obtain a parameter value when the parameter can be measured directly. For example, the MOS oxide thickness, TOX, is a model parameter, but we would never use optimization to find it. Always measure its value directly on a large oxide capacitor provided on the test chip. The recommended procedure for proper device characterization follows: 1. Have all the appropriate structures necessary on your test chip. Without this, the job cannot be performed properly. 2. Always measure whatever parameters are directly measurable. Never use optimization for these. 3. Fit the subset of parameters to corresponding subsets of data, and do so in physically meaningful ways. 4. Fit the parameters in the proper order so that those obtained later do not affect those obtained previously. If this is not possible, iteration may be necessary. Naturally, a good strategy cannot be mounted if one is not intimately familiar with the model used. There is no substitute for learning as much about the model as possible. Without this knowledge, one must rely on strategies provided by software vendors, and these vary widely in quality. Finally, no one can provide a completely general strategy applicable to all models and all process technologies. At some point the strategy must be tailored to suit the available technology and circuit performance requirements. This not only requires familiarity with the available device models, but also information from the circuit designers and process architects.

MOS DC Models Available MOS Models A number of MOS models have been provided over time with the original circuit simulation program, SPICE. In addition, some commercially available circuit simulation programs have introduced their own proprietary models, most notably HSPICE.4 This section concentrates on the standard MOS models provided by UC Berkeley’s SPICE, not only because they have become the standard models used by all circuit simulation programs, but also because the proprietary models provided by commercial vendors are not well documented and no source code is available for these models to investigate them thoroughly. MOS Levels 1, 2, and 3. Originally, SPICE came with three MOS models known as level 1, level 2, and level 3. The level 1 MOS model is a very crude first-order model that is rarely used. The level 2 and level 3 MOS models are extensions of the level 1 model and have been used extensively in the past and present [11]. These two models contain about 15 DC parameters each and are usually considered useful for digital circuit simulation down to 1 µm channel length technologies. They can fit the drain current 4

HSPICE is a commercially available, SPICE-like circuit simulation from Meta Software, Campbell, CA.

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for wide transistors of varying length with reasonable accuracy (about 5% RMS error), but have very little advanced fitting capability for analog application. They have only one parameter for fitting the subthreshold region, and no parameters for fitting the derivative of drain current with respect to drain voltage, Gds (usually considered critical for analog applications). They also have no ability to vary the mobility degradation with back-bias, so the fits to Ids in the saturation region at back-bias are not very good. Finally, these models do not interpolate well over device geometry; e.g., if a fit is made to a widelong device and a wide-short device, and then one observes how the models track for lengths between these two extremes, they usually do not perform well. For narrow devices, they can be quite poor as well. Level 3 has very little practical advantage over level 2, although the level 2 model is proclaimed to be more physically based, whereas the level 3 model is called semiempirical. If only one can be used, perhaps levels 3 is slightly better because it runs somewhat faster and does not have quite such an annoying kink in the transition region from linear to saturation as does level 2. Berkeley Short-Channel Igfet Model (BSIM). To overcome the many shortcomings of level 2 and levels, the BSIM and BSIM2 models were introduced. The most fundamental difference between these and the level 2 and 3 models is that BSIM and BSIM2 use a different approach to incorporating the geometry dependence [3, 6]. In level 2 and 3, the geometry dependence is built directly into the model equations. In BSIM and BSIM2, each parameter (except for a very few) is written as a sum of three terms Parameter = Par0 +

ParL ParW + Weff L eff

(53.37)

where Par0 is the zero-order term, ParL accounts for the length dependence of the parameter, ParW accounts for the width dependence, and Leff and Weff are the effective channel width and length, respec­ tively. This approach has a large influence on the device characterization strategy, as discussed later. Because of this tripling of the number of parameters and for other reasons as well, the BSIM model has about 54 DC parameters and the BSIM2 model has over 100. The original goal of the BSIM model was to fit better than the level 2 and 3 models for submicron channel lengths, over a wider range of geometries, in the subthreshold region, and for nonzero backbias. Without question, BSIM can fit individual devices better than level 2 and level 3. It also fits the subthreshold region better and it fits better for nonzero back-biases. However, its greatest shortcoming is its inability to fit over a large geometry variation. This occurs because (53.37) is a truncated Taylor series in 1/Leff and 1/Weff terms, and in order to fit better over varying geometries, higher power terms in 1/Leff and 1/Weff are needed. In addition, no provision was put into the BSIM model for fitting Gds , so its usefulness for analog applications is questionable. Many of the BSIM model parameters are unphysical, so it is very hard to understand the significance of these model parameters. This has profound implications for generating skew models (fast and slow models to represent the process corners) and for incorporating temperature dependence. Another flaw of the BSIM model is its wild behavior for certain values of the model parameters. If model parameters are not specified for level 2 or 3, they will default to values that will at least force the model to behave well. For BSIM, not specifying certain model parameters, setting them to zero, or various combinations of values can cause the model to become very ill-behaved. BSIM2. The BSIM2 model was developed to address the shortcomings of the BSIM model. This was basically an extension of the BSIM model, removing certain parameters that had very little effect, fixing fundamental problems such as currents varying the wrong way as a function of certain parameters, adding more unphysical fitting parameters, and adding parameters to allow fitting Gds. BSIM2 does fit better than BSIM, but with more than twice as many parameters as BSIM, it should. However, it does not address the crucial problem of fitting large geometry variations. Its major strengths over BSIM are fitting the subthreshold region better, and fitting Gds better. Most of the other shortcomings of BSIM are also present in BSIM2, and the large number of parameters in BSIM2 makes it a real chore to use in device characterization. © 2003 by CRC Press LLC

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BSIM3. Realizing the shortcomings of BSIM2, UC Berkeley recently introduced the BSIM3 model. This is an unfortunate choice of name because it implies BSIM3 is related to BSIM and BSIM2. In reality, BSIM3 is an entirely new model that in some sense is related more to level 2 and 3 than BSIM or BSIM2. The BSIM3 model abandons the length and width dependence approach of BSIM and BSIM2, preferring to go back to incorporating the geometry dependence directly into the model equations, as do level 2 and 3. In addition, BSIM3 is a more physically based model, with about 30 fitting parameters (the model has many more parameters, but the majority of these can be left untouched for fitting), making it more manageable, and it has abundant parameters for fitting Gds , making it a strong candidate for analog applications. It is an evolving model, so perhaps it is unfair to criticize it at this early stage. Its greatest shortcoming is, again, the inability to fit well over a wide range of geometries. It is hoped that future modifications will address this problem. In all fairness, however, it is a large order to ask a model to be physically based, have not too many parameters, be well behaved for all default values of the parameters, fit well over temperature, fit Gds, fit over a wide range of geometries, and still fit individual geometries as well as a model with over 100 parameters, such as BSIM2. Some of these features were compromised in developing BSIM3. Proprietary Models. A number of other models are available from commercial circuit simulator vendors, the literature, etc. Some circuit simulators also offer the ability to add a researcher’s own models. In general, we caution against using proprietary models, especially those which are supplied without source code and complete documentation. Without an intimate knowledge of the model equations, it is very difficult to develop a good device characterization strategy. Also, incorporating such models into device characterization software is almost impossible. To circumvent this problem, many characterization pro­ grams have the ability to call the entire circuit simulator as a subroutine in order to exercise the proprietary model subroutines. This can slow program execution by a factor of 20 or more, seriously impacting the time required to characterize a technology. Also, if proprietary models are used without source code, the circuit simulator results can never be checked against another circuit simulator. Therefore, we want to stress the importance of using standard models. If these do not meet the individual requirements, the next best approach is to incorporate a proprietary model whose source code one has access to. This requires being able to add the individual model not only to circuit simulators, but also to device characterization programs; it can become a very large task. MOS Level 3 Extraction Strategy in Detail The strategy discussed here is one that we consider to be a good one, in the spirit of our earlier comments. Note, however, that this is not the only possible strategy for the level 3 model. The idea here is to illustrate basic concepts so that this strategy can be refined to meet particular individual requirements. In order to do a DC characterization, the minimum requirement is one each of the wide-long, wideshort, and narrow-long devices. We list the steps of the procedure and then discuss them in more detail. STEP 1. Fit the wide-long device in the linear region at zero back-bias, at Vgs values above the subthreshold region, with parameters VT0 (threshold voltage), U0 (mobility), and THETA (mobility degradation with Vgs). STEP 2. Fit the wide-short device in the linear region at zero back-bias, at Vgs values above the subthresh­ old region, with parameters VT0, LD (length encroachment), and THETA. When finished with this step, replace VT0 and THETA with the values from step 1, but keep the value of LD. STEP 3. Fit the narrow-long device in the linear region at zero back-bias, at Vgs values above the subthreshold region, with parameters VT0, DW (width encroachment), and THETA. When finished with this step, replace VT0 and THETA with the values from step 1, but keep the value of DW.

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1441

STEP 4. Fit the wide-short device in the linear region at zero back-bias, at Vgs values above the subthresh­ old region, with parameters RS and RD (source and drain series resistance). STEP 5. Fit the wide-long device in the linear region at all back-biases, at Vgs values above the subthreshold region, with parameter NSUB (channel doping affects long channel variation of threshold voltage back-bias). STEP 6. Fit the wide-short device in the linear region at all back-biases, at Vgs values above the subthresh­ old region, with parameter XJ (erroneously called the junction depth; affects short-channel variation of threshold voltage with back-bias). STEP 7. Fit the narrow-long device in the linear region at zero back-bias, at Vgs values above the subthreshold region, with parameter DELTA (narrow channel correction to threshold voltage). STEP 8. Fit the wide-short device in the saturation region at zero back-bias (or all back-biases) with parameters VMAX (velocity saturation), KAPPA (saturation region slope fitting parameter), and ETA (Vds dependence of threshold voltage). STEP 9. Fit the wide-short device in the subthreshold region at whatever back-bias and drain voltage is appropriate (usually zero back-bias and low Vds) with parameter NFS (subthreshold slope fitting param­ eter). One may need to fit with VT0 also and then VT0 is replaced after this step with the value of VT0 obtained from step 1. This completes the DC characterization steps for the MOS level 3 model. One would then go on to do the junction and overlap capacitance terms (discussed later). Note that this model has no parameters for fitting over temperature, although temperature dependence is built into the model that the user cannot control. In Step 1, VT0, U0, and THETA are defined in the model for a wide-long device at zero back-bias. They are zero-order fundamental parameters without any short or narrow channel corrections. We therefore fit them to a wide-long device. It is absolutely necessary that such a device be on the test chip. Without it, one cannot obtain these parameters properly. The subthreshold region must be avoided also because these parameters do not control the model behavior in subthreshold. In Step 2, we use LD to fit the slope of the linear region curve, holding U0 fixed from step 1. We also fit with VT0 and THETA because without them the fitting will not work. However, we want only the value of LD that fits the slope, so we throw away VT0 and THETA, replacing them with the values from step 1. Step 3 is the same as step 2, except that we are getting the width encroachment instead of the length. In Step 1, the value of THETA that fits the high Vgs portion of the wide-long device linear region curve was found. Because the channel length of a long transistor is very large, the source and drain series resistances have almost no effect here, but for a short-channel device, the series resistance will also affect the high Vgs portion of the linear region curve. Therefore, in step 4 we fix THETA from step 1 and use RS and RD to fit the wide-short device in the linear region, high Vgs portion of the curve. In Step 5, we fit with NSUB to get the variation of threshold voltage with back-bias. We will get better results if we restrict ourselves to lower values of Vgs (but still above subthreshold) because no mobility degradation adjustment exists with back-bias, and therefore the fit may not be very good at higher Vgs values for the nonzero back bias z-curves. Step 6 is just like step 5, except we are fitting the short-channel device. Some people think that the value of XJ should be the true junction depth. This is not true. The parameter XJ is loosely related to the junction depth, but XJ is really the short-channel correction to NSUB. Do not be surprised if XJ is not equal to the true junction depth. Step 7 uses DELTA to make the narrow channel correction to the threshold voltage. This step is quite straightforward.

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0.00

2.00

Ids (Amps)*10−4 4.00

6.00

8.00

W/L = 40um/1.2um Vbs = 0, −2.5, −5 Volts Vds = 0.1 Volts Tox = 250 A

0.00

1.00

2.00

3.00

4.00

5.00

Vgs (Volts)

FIGURE 53.19 Typical MOS level 3 linear region measured and simulated plots at various Vbs values for a wideshort device.

Step 8 is the only step that fits in the saturation region. The use of parameters VMAX and KAPPA is obvious, but one may question using ETA to fit in the saturation region. The parameter ETA adjusts the threshold voltage with respect to Vds , and as such one could argue that ETA should be used to fit measurements of Ids sweeping Vgs and stepping Vds to high values. In doing so, one will corrupt the fit in the saturation region, and usually we want to fit the saturation region better at the expense of the linear region. Step 9 uses NFS to fit the slope of the log(Ids) vs. Vgs curve. Often, the value of VT0 obtained from step 1 will prevent one from obtaining a good fit in the subthreshold region. If this happens, try fitting with VT0 and NFS, but replacing the final value of VT0 with that from step 1 at the end, keeping only NFS from this final step. The preceding steps illustrate the concepts of fitting relevant subsets of parameters to relevant subsets of data to obtain physical values of the parameters, as well as fitting parameters in the proper order so that those obtained in the later steps will affect those obtained in earlier steps minimally. Please refer to Figs. 53.19 and 53.20 for how the resulting fits typically appear (all graphs showing levels fits are provided by the device modeling software package Aurora, from Technology Modeling Associates, Inc., Palo Alto, CA). An experienced person may notice that we have neglected some parameters. For example, we did not use parameters KP and GAMMA. This means KP will be calculated from U0, and GAMMA will be calculated from NSUB. In a sense U0 and NSUB are more fundamental parameters than KP and GAMMA. For example, KP depends on U0 and TOX; GAMMA depends on NSUB and TOX. If one is trying to obtain skew models, it is much more advantageous to analyze statistical distributions of parameters that depend on a single effect than those that depend on multiple effects. KP will depend on mobility and oxide thickness; U0 is therefore a more fundamental parameter. We also did not obtain parameter PHI, so it will be calculated from NSUB. The level 3 model is very insensitive to PHI, so using it for curve fitting is pointless. This illustrates the importance of being very familiar with the model equations. The kind of judgments described here cannot be made without such knowledge. © 2003 by CRC Press LLC

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0.60 0.00

0.20

0.40

Ids (Amps) *10−2

0.80

1.00

Computer-Aided Analysis

0.00

1.00

2.00

3.00

4.00

5.00

Vds (Volts)

FIGURE 53.20 Typical MOS level 3 saturation region measured and simulated plots at various Vgs and Vbs values for a wide-short device.

cov

c cs c2p

L W

FIGURE 53.21 Mask layers showing dimensions that should be identical for all MOS devices of the same width.

Test Chip Warnings. The following hints will greatly assist in properly performing device characterization. 1. Include a wide-long device; without this, the results will not be physically correct. 2. All MOS transistors with the same width should be drawn with their sources and drains identical. No difference should be seen in the number of source/drain contacts, contact spacing, source/drain contact overlap, poly gate to contact spacing, etc. In Fig. 53.21, c is the contact size, cs is the contact space, cov is the contact overlap of diffusion, and c2p is the contact to poly spacing. All these dimensions should be identical for devices of different L but identical W. If not, extracting the series resistance will become more difficult. 3. Draw devices in pairs. That is, if the wide-long device is W/L = 20/20, make the wide-short device the same width as the wide-long device; e.g., make the short device 20/1, not 19/1. If the narrow­ © 2003 by CRC Press LLC

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long device is 2/20, make the narrow-short device of the same width; i.e., make it 2/1, not 3/1, and similarly for the lengths. (Make the wide-short and the narrow-short devices have the same length.) 4. Draw structures for measuring the junction capacitances and overlap capacitances. These are discussed later in the section on capacitance models.

BSIM Extraction Strategy in Detail All MOS model strategies have basic features in common; namely, fit the linear region at zero back-bias to get the basic zero-order parameters, fit the linear region at nonzero back-bias, fit the saturation region at zero back-bias, fit the saturation region at nonzero back-bias, and then fit the subthreshold region. It is possible to extend the type of strategy we covered for level 3 to the BSIM model, but that is not the way BSIM was intended to be used. The triplet sets of parameters for incorporating geometry dependence into the BSIM model, (53.37), allow an alternate strategy. We obtain sets of parameters without geometry dependence by fitting to individual devices without using the ParL and ParW terms. We do this for each device size individually. This produces sets of parameters relevant to each individual device. So, for device number 1 of width W(1) and length L(1) we would have a value for the parameter VFB which we will call VFB(1); for device number n of width W(n) and length L(n) we will have VFB(n). To get the Par0, ParL and ParW terms, we fit to the parameters themselves, rather than the measured data. That is, to get VFB0, VFBL , and VFBW , we fit to the “data points” VFB(1),…,VFB(n) with parameters VFB0, VFBL , and VFBW using (53.37), where Leff and Weff are different for each index, 1 through n. Note that as L and W become very large, the parameters must approach Par0. This suggests that we use the parameter values for the wide-long device as the Par0 terms and only fit the other geometry sizes to get the ParW and ParL terms. For example, if we have obtained VFB(1) for our first device which is our wide-long device, we would set VFB0 = VFB(1), and then fit to VFB(2),…,VFB(n) with parameters VFBL and VFBW , and similarly for all the other triplets of parameters. In order to use a general leastsquares optimization program in this way the software must be capable of specifying parameters as targets, as well as measured data points. We now list a basic strategy for the BSIM model: STEP 1. Fit the wide-long device in the linear region at zero back-bias, at Vgs values above the subthreshold region, with parameters VFB (flatband voltage), MUZ (mobility), and U0 (mobility degradation), with DL (length encroachment) and DW (width encroachment) set to zero. STEP 2. Fit the wide-short device in the linear region at zero back-bias, at Vgs values above the subthresh­ old region, with parameters VFB, U0, and DL. STEP 3. Fit the narrow-long device in the linear region at zero back-bias, at Vgs values above the subthreshold region, with parameters VFB, U0, and DW. STEP 4. Refit the wide-long device in the linear region at zero back-bias, at Vgs values above the subthreshold region, with parameters VFB, MUZ, and U0, now that DL and DW are known. STEP 5. Fit the wide-short device in the linear region at zero back-bias, at Vgs values above the subthresh­ old region, with parameters VFB, RS, and RD. When finished, replace the value of VFB with the value found in step 4. STEP 6. Fit the wide-long device in the linear region at all back-biases, at Vgs values above the subthreshold region, with parameters K1 (first-order body effect), K2 (second-order body effect), U0, and X2U0 (Vbs dependence of U0). © 2003 by CRC Press LLC

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STEP 7. Fit the wide-long device in the saturation region at zero back-bias with parameters U0, ETA (Vds dependence of threshold voltage), MUS (mobility in saturation), U1 (Vds dependence of mobility), and X3MS (Vds dependence cf MUS). STEP 8. Fit the wide-long device in the saturation region at all back-biases with parameter X2MS (Vbs dependence of MUS). STEP 9. Fit the wide-long device in the subthreshold region at zero back-bias and low Vds value with parameter N0; then fit the subthreshold region nonzero back-bias low Vds data with parameter NB; and finally fit the subthreshold region data at higher Vds values with parameter ND. Or, fit all the subthreshold data simultaneously with parameters N0, NB, and ND. Repeat steps 6 through 10 for all the other geometries, with the result of sets of geometry-independent parameters for each different size device. Then follow the procedure described previously for obtaining the geometry-dependent terms Par0, ParL , and ParW . In the preceding strategy, we have omitted various parameters either because they have minimal effect or because they have the wrong effect and were modified in the BSIM2 model. Because of the higher complexity of the BSIM model over the level 3 model, many more strategies are possible than the one just listed. One may be able to find variations of the above strategy that suit the individual technology better. Whatever modifications are made, the general spirit of the above strategy probably will remain. Some prefer to use a more global approach with BSIM, fitting to measured data with ParL and ParW terms directly. Although this is certainly possible, it is definitely not a recommended approach. It represents the worst form of blind curve fitting, with no regard for physical correctness or understanding. The BSIM model was originally developed with the idea of obtaining the model parameters via extraction as opposed to optimization. In fact, UC Berkeley provides software for obtaining BSIM parameters using extraction algorithms, with no optimization at all. As stated previously, this has the advantage of being relatively fast and easy. Unfortunately, it does not always work. One of the major drawbacks of the BSIM model is that certain values of the parameters can cause the model to produce negative values of Gds in saturation. This is highly undesirable, not only from a modeling standpoint, but also because of the convergence problems it can cause in circuit simulators. If an extraction strategy is used that does not guarantee non-negative Gds, very little can be done to fix the problem when Gds becomes negative. Of course, the extraction algorithms can be modified, but this is difficult and time consuming. With optimization strategies, one can weight the fitting for Gds more heavily and thus force the model to produce non-negative Gds. We, therefore, do not favor extraction strategies for BSIM, or anything else. As with most things in life, minimal effort provides minimal rewards. BSIM2 Extraction Strategy We do not cover the BSIM2 strategy in complete detail because it is very similar to the BSIM strategy, except more parameters are involved. The major difference in the two models is the inclusion of extra terms in BSIM2 for fitting Gds (refer to Fig. 53.22, which shows how badly BSIM typically fits 1/Gds vs. Vds). Basically, the BSIM2 strategy follows the BSIM strategy for the extraction of parameters not related to Gds. Once these have been obtained, the last part of the strategy includes steps for fitting to Gds with parameters that account for channel length modulation and hot electron effects. The way this proceeds in BSIM2 is to fit Ids first, and then parameters MU2, MU3, and MU4 are used to fit to 1/Gds vs. Vds curves for families of Vds and Vbs. This can be a very time consuming and frustrating experience, because fitting to 1/Gds is quite difficult. Also, the equations describing how Gds is modeled with MU2, MU3, and MU4 are very unphysical and the interplay between the parameters makes fitting awkward. The reader is referred to Fig. 53.23, which shows how BSIM2 typically fits 1/Gds vs. Vds. BSIM2 is certainly better than BSIM, but it has its own problems fitting 1/Gds. BSIM3 Comments The BSIM3 model is very new and will undoubtedly change in the future [5]. We will not list a BSIM3 strategy here, but focus instead on the features of the model that make it appealing for analog modeling. © 2003 by CRC Press LLC

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W/L = 40um/1.2um Vbs = 0 Volts Vgs = 2, 3, 4, 5 Volts Tox = 250 A

0.75 0.50

0.25

1/gd (Mhos)*10−4

1.00

1.25

The Circuits and Filters Handbook, Second Edition

1.00

2.00

3.00

4.00

Vds (Volts)

W/L = 40um/1.2um Vbs = 0 Volts Vgs = 2, 3, 4, 5 Volts Tox = 250 A

0.75 0.50 0.25

1/gd (Mhos)*10−4

1.00

1.25

FIGURE 53.22 Typical BSIM 1/Gd vs. Vds measured and simulated plots at various Vgs values for a wide-short device.

1.00

2.00

3.00

4.00

Vds (Volts)

FIGURE 53.23 Typical BSIM2 1/Gd vs. Vds measured and simulated plots at various Vgs values for a wide-short device.

© 2003 by CRC Press LLC

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W/L = 40um/1.2um Vbs = 0 Volts Vgs = 2, 3, 4, 5 Volts Tox = 250 A

0.60 0.00

0.20

0.40

Ids (Amps)*10−2

0.80

1.00

1.20

Computer-Aided Analysis

0.00

1.00

2.00

3.00

4.00

5.00

Vds (Volts)

FIGURE 53.24 Typical BSIM3 saturation region measured and simulated plots at various Vgs values for a wide-short device.

BSIM3 has terms for fitting Gds that relate to channel length modulation, drain-induced barrier lowering, and hot electron effects. They are incorporated completely differently from the Gds fitting parameters of BSIM2. In BSIM3, these parameters enter through a generalized Early voltage relation, with the drain current in saturation written as  (V − Vd sat )  I ds = I d sat 1 + ds  VA  

(53.38)

where V* is a generalized Early voltage made up of three terms as 1 1 1 1 = + + VA VACLM VADIBL VAHCE

(53.39)

with the terms in (53.39) representing generalized Early voltages for channel length modulation (CLM), drain-induced barrier lowering (DIBL), and hot carrier effects (HCE). This formulation is more physically appealing than the one used in BSIM2, making it easier to fit 1/Gds vs. Vds. curves with BSIM2. Figures 53.24 and 53.25 show how BSIM3 typically fits Ids vs. Vds and 1/Gds vs. Vds. Most of the model parameters for BSIM3 have physical significance so they are obtained in the spirit of the parameters for the level 2 and 3 models. The incorporation of temperature dependence is also easier in BSIM3 because the parameters are more physical. All this, coupled with the fact that about 30 parameters exists for BSIM3 as compared to over 100 for BSIM2, makes BSIM3 a logical choice for analog design. However, BSIM3 is evolving, and shortcomings to the model may still exist that may be corrected in later revisions.

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W/L = 40um/1.2um Vbs = 0 Volts Vgs = 2, 3, 4, 5 Volts Tox = 250 A

0.50

1/gd (Mhos)*104 1.00

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1.00

2.00

3.00

4.00

Vds (Volts)

FIGURE 53.25 Typical BSIM3 1/Gd vs. Vds measured and simulated plots at various Vgs values for a wide-short device.

Which MOS Model to Use? Many MOS models are available in circuit simulators, and the novice is bewildered as to which model is appropriate. No single answer exists, but some questions must be asked before making a choice: 1. 2. 3. 4. 5. 6. 7. 8. 9.

What kind of technology am I characterizing? How accurate a model do I need? Do I want to understand the technology? How important are the skew model files (fast and slow parameter files)? How experienced am I? Do I have the expertise to handle a more complicated model? How much time can I spend doing device characterization? Do I need to use this model in more than one circuit simulator? Is the subthreshold region important? Is fitting Gds important?

Let us approach each question with regard to the models available. If the technology is not submicron, perhaps a simpler model such as level 3 is capable of doing everything needed. If the technology is deep submicron, then use a more complicated model such as BSIM, BSIM2, or BSIM3. If high accuracy is required, then the best choice is BSIM3, mainly because it is more physical than all the other models and is capable of fitting better. For a good physical understanding of the process being characterized, BSIM and BSIM2 are not good choices. These are the least physically based of all the models. The level 2 and 3 models have good physical interpretation for most of the parameters, although they are relatively simple models. BSIM3 is also more physically based, with many more parameters than level 2 or 3, so it is probably the best choice. If meaningful skew models need to be generated, then BSIM and BSIM2 are very difficult to use, again, because of their unphysical parameter sets. Usually, the simplest physically based model is the best for skew model generation. A more complicated physically based model such as BSIM3 may also be difficult to use for skew model generation.

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If the user is inexperienced, none of the BSIM models should be used until the user’s expertise improves. Our device is to practice using simpler models before tackling the harder ones. If time is critical, the simpler models will definitely be much faster for use in characterization. The more complicated models require more measurements over wider ranges of voltages as well as wider ranges of geometries. This, coupled with the larger number of parameters, means they will take some time with which to work. The BSIM2 model will take longer than all the rest, especially if the Gds fitting parameters are to be used. The characterization results may need to be used in more than one circuit simulator. For example, if a foundry must supply models to various customers, they may be using different circuit simulators. In this case, proprietary models applicable to a single circuit simulator should not be used. Also, circuit designers may want to check the circuit simulation results on more than one circuit simulator. It is better to use standard Berkeley models (level 2, level 3, BSIM, BSIM2, and BSIM3) in such cases. If the subthreshold region is important, then level 2 or level 3 cannot be used, and probably not even BSIM. BSIM2 or BSIM3 must be used instead. These two models have enough parameters for fitting the subthreshold region. If fitting Gds is important, BSIM2 and BSIM3 are, again, the only choices. None of the other models have enough parameters for fitting Gds. Finally, if a very unusual technology is to be characterized, none of the standard models may be appropriate. In this case commercially available specialized models or the user’s own models must be used. This will be a large task, so the goals must justify the effort.

Bipolar DC Model The standard bipolar model used by all circuit simulators is the Gummel–Poon model, often called the BJT (bipolar junction transistor) model [4]. Most circuit simulator vendors have added various extra parameters to this model, which we will not discuss, but they all have the basic parameters introduced by the original UC Berkeley SPICE model. We now list a basic strategy for the BJT model: STEP 1. Fit a Gummel plot (log(IC) and log(IB) vs. VBE) for the IC curve in the straight line portion of the curve (low to middle VBE values) with parameters IS and NF. Note that it is best if the Gummel plots are done with VCB = 0. STEP 2. Fit plots of IC vs. VCE, stepping IB, in the high VCE region of the curves with parameters VAF, BF, and IKF. STEP 3. Fit plots of IC vs. VCE, stepping IB, in the low VCE region of the curves with parameter RC. STEP 4. Fit a Gummel plot for the IB curve for VBE values in the mid- to high-range with parameter BF. STEP 5. Fit a Gummel plot for the IB curve for low VBE values with parameters ISE and NE. STEP 6. Try to obtain parameter RE by direct measurement or by simulation using a device simulator such as PISCES. It is also best if RB can be obtained as a function of current by measurement on special structures, or by simulation. One may also obtain RB by S-parameter measurements (discussed later). Failing this, RB may be obtained by fitting to the Gummel plot for the IB curve for VBE values in the mid- to high-range with parameters RB, RBM, and IRB. This is a difficult step to perform with an optimization program. STEP 7. Fit a Gummel plot for the IC curve for high VBE values with parameter IKF.

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STEP 8. At this point, all the DC parameters have been obtained for the device in the forward direction. Next, obtain the reverse direction data by interchanging the emitter and collector to get the reverse Gummel and IC vs. VCE data. Repeat Step 2 on the reverse data to get VAR, BR, IKR.

Repeat Step 4 on the reverse data to get BR.

Repeat Step 5 on the reverse data to get ISC, NC.

Repeat Step 7 on the reverse data to get IKR.

Fitting the reverse direction parameters is very frustrating because the BJT model is very poor in the reverse direction. After seeing how poor the fits can be, one may decide to obtain only a few of the reverse parameters.

MOS and Bipolar Capacitance Models MOS Junction Capacitance Model The MOS junction capacitance model accounts for bottom wall (area component) and side wall (periph­ ery component) effects. The total junction capacitance is written as a sum of the two terms CJ(total) =

[

A(CJ)

]

1 + (VR PB)

MJ

+

[

P(CJSW )

]

1 + (VR PB)

MJSW

(53.40)

where A is the area and P is the periphery of the junction diode capacitor, and VR is the reverse bias (a positive number) across the device. The parameters of this model are CJ, CJSW, PB, MJ, and MJSW. It is very easy to find parameter values for this model. Typically, one designs special large junction diodes on the test chip, large enough so that the capacitances being measured are many tens of picofarads. This means the diodes have typical dimensions of hundreds of microns. Two junction diodes are needed — one with a large area:periphery ratio, and another with a small area:periphery ratio. This is usually done by drawing a rectangular device for the large area:periphery ratio, and a multifingered device for the small area:periphery ratio (see Fig. 53.26). The strategy for this model consists of a single step, fitting to all the data simultaneously with all the parameters. Sometimes it is helpful to fix PB to some nominal value such as 0.7 or 0.8, rather than optimize on PB, because the model is not very sensitive to PB.

diffusion

well contacts

FIGURE 53.26 Mask layers showing the periphery multifingered junction diode structure. © 2003 by CRC Press LLC

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BJT Junction Capacitance Model The BJT model is identical to the MOS, except it uses only the bottom wall (area term), not the side wall. Three sets of BJT junction diodes need to be characterized: emitter-base, collector-base, and col­ lector-substrate. Each of these has three model parameters to fit. For example, for the emitter-base junction diode, the parameters are CJE, VJE, and MJE (CJE corresponds to CJ, VJE to PB, and MJE to MJ of the MOS model). Similarly, for the collector-base junction diode, we have CJC, VJC, and MJC. Finally, for the collector-substrate junction diode, we have CJS, VJS, and MJS. These parameters are all fit in a single strategy step on the relevant data. Again, it is best if large test structures can be drawn rather than the values measured directly on transistor, because the transistor junction diodes have such small areas that the measurements are prone to accuracy problems. MOS Overlap Capacitance Model In addition to the junction capacitance model, the MOS models include terms for the overlap or Miller capacitance. This represents the capacitance associated with the poly gate overlap over the source and drain regions. As for the junction diodes, special test chip structures are necessary for obtaining the overlap capacitance terms CGS0, CGD0, and CGB0. These structures usually consist of large, multifin­ gered devices that look just like the junction capacitance periphery diodes, except that where the junction diodes are diffusion over well structures, the overlap capacitors are poly over diffusion.

Bipolar High-Frequency Model The SPICE BJT model has five parameters for describing the high-frequency behavior of bipolar devices. These are parameters TF, XTF, ITF, VTF, and PTF, all of which are associated with the base transit time, or equivalently, the cutoff frequency. Parameter TF is the forward transit time, XTF and ITF modify TF as a function of VBE (or IC), and VTF modifies TF as function of VBE (or IC), and VTF modifies TF as a function of VCB. Parameter PTF represents the excess phase at the cutoff frequency. The expression used by SPICE for the transit time is 2   IF   [ VBC {(1.44)( VTF)}] τ f = TF 1 + XTF  e  IF + ITF   

(53.41)

where IF = IS e { 

(q ) (Vbe )} {( NF )(k )(T )}

− 1 

(53.42)

SPICE uses the transit time to calculate the diffusion capacitance of the emitter-base junction in forward bias. Obtaining the bipolar high frequency parameters is very complicated, time-consuming, and difficult. It also requires very expensive measuring equipment, including a network analyzer for measuring S-parameters, and a quality high-frequency wafer prober with high-frequency probes. Having measured the S-parameters, after suitable data manipulation and optimization it is possible to find the highfrequency SPICE parameters. It is beyond the scope of this book to cover high-frequency bipolar theory completely. We will, however, list the basic steps involved in obtaining the high frequency bipolar transit time parameters: STEP 1. Measure the S-parameters over an appropriate frequency range to go beyond the cutoff frequency, fT . Do these measurements over a large range of IC values and stepping over families of VCB values as well. Be sure to include VCB = 0 in these data. Be sure that the network analyzer being used is well calibrated. These measurements can be done in either common emitter or common collector mode. Each has advantages and disadvantages. © 2003 by CRC Press LLC

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Probe

FIGURE 53.27 Typical bipolar transistor test chip layout for measuring S-parameters with high-frequency probes. This shows the common emitter configuration.

STEP 2. De-embed the S-parameter measurements by measurements dummy pad structures that dupli­ cate the layout of the bipolar transistors, including pads and interconnect, but with no devices. The deembedding procedure subtracts the effects of the pads and interconnects from the actual devices. This step is very important if reliable data are desired [10]. STEP 3. Calculate the current gain, β from the S-parameter data. From plots of β vs. frequency, find the cutoff frequency, fT . Also calculate parameter PTF directly from these data. STEP 4. Calculate τf from fT by removing the effect of RE, RC, and the junction capacitances. This produces tables of τf vs. IC, or equivalently, τf vs. VBE, over families of VCB. STEP 5. Optimize on τf vs. VBE data over families of VCB with parameters TF, XTF, ITF, and VTF. Note that many of the preceding steps are done automatically by some commercial device modeling programs. It is very important to have well-designed and appropriate test structures for measuring S-parameters. The pad layout and spacing is very critical because of the special size and shape of the high-frequency probes (see Fig. 53.27). The test chip structures must be layed out separately for common emitter and common collector modes if measurements are necessary for both these modes. It is also possible to use the S-parameter measurements to obtain the base resistance as a function of collector current. From this information one can optimize to obtain parameters RB, RBM, and IRB. However, the base resistance obtained from S-parameters is not a true DC base resistance, and the model is expecting DC values of base resistance.

Miscellaneous Topics Skew Parameter Files This chapter discusses obtaining model parameters for a single wafer, usually one that has been chosen to represent a typical wafer for the technology being characterized. The parameter values obtained from this wafer correspond to a typical case. Circuit designers also want to simulate circuits with parameter values representing the extremes of process variation, the so-called fast and slow corners, or skew parameter files. These represent the best and worst case of the process variation over time. Skew parameter values are obtained usually by tracking a few key parameters, measuring many wafers over a long period of time. The standard deviation of these key parameters is found and added to or subtracted from the typical parameter values to obtain the skew models. This method is extremely crude and will not normally produce a realistic skew model. It will almost always overestimate the process spread, because the various model parameters are not independent — they are correlated. Obtaining realistic skew parameter values, taking into account all the subtle correlations between parameters, is more difficult. In fact, skew model generation is often more an art than a science. Many attempts have been made to utilize techniques from a branch of statistics called multivariate analysis [1]. In this approach, principal component or factor analysis is used to find parameters that are linear combinations of the original parameters. Only the first few of these new parameters will be kept; the others will be discarded because they have less significance. This new set will have fewer parameters than © 2003 by CRC Press LLC

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the original set and therefore will be more manageable in terms of finding their skews. The user sometimes must make many choices in the way the common factors are utilized, resulting in different users obtaining different results. Unfortunately, a great deal of physical intuition is often required to use this approach effectively. To date, we have only seen it applied to the simpler MOS models such as level 3. It is not known if this is a viable approach for a much more complicated model such as BSIM2 [7]. Macro Modeling Sometimes, a device is designed and manufactured that cannot be modeled by a single transistor model. In such cases, one may try to simulate the behavior of a single device by using many basic device elements together, representing the final device. For example, a single real bipolar device might be modeled using a combination of several ideal bipolar devices, diodes, resistors, and capacitors. This would be a macro model representing the real bipolar device. Macro modeling usually uses least-squares optimization techniques. One chooses model parameter values to represent the ideal devices in the technology, and then optimizes on geometry size, capacitance size, resistance size, etc., to obtain the final macro model. This is similar to the optimization techniques used to find model parameters for a standard model, but in this case we are calling on an entire circuit simulator rather than a model subroutine to provide the output characteristics of our macro model. Obviously, macro modeling can be very computation intensive. A complex macro model can take a very long time to optimize. Also, it may be impractical to use a macro model for every real device in the circuit. For example, if the circuit in question has 100,000 real transistors and each of these is being represented by a macro model with 10 components, the number of circuit nodes introduced by the macro model (>10 × 10,000) might be prohibitive in terms of simulation time. Nevertheless, for critical com­ ponents, macro modeling can provide tremendous insight. Modeling in a TCAD Environment Programs that do optimization are part of a larger set of software that is sometimes called TCAD (technology computer-aided design). Typically, TCAD encompasses software for process simulation (doping distributions), device simulation (electrical characteristics), device modeling, and circuit simu­ lation. Other elements of TCAD can include lithography simulation, interconnect modeling (capacitance, resistance, and inductance), etc. In the past, each of the software components of TCAD were used as stand-alone programs, with very little communication between the components. The trend now is to incorporate all these pieces into a complete enviroment that allows them to communicate with each other seamlessly, efficiently, and graphically, so that the user is not burdened with keeping track of file names, data, etc. In such a system, one can easily set up split lots and simulate from process steps up through circuit simulation. One will also be able to close the loop, feeding circuit simulation results back to the process steps and run optimization on an entire process to obtain optimal circuit performance characteristics (see Fig. 53.28). The future of device modeling will surely be pushed in this direction. Device modeling tools will be used not only separately, but within a total TCAD environment, intimately connected with process, device, interconnect, and circuit simulation tools. Process Simulator

Device Simulator

Optimizer

Circuit Simulator

Circuit Netlist

FIGURE 53.28 Block diagram of a TCAD system. © 2003 by CRC Press LLC

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References [1] W. R. Dillon and M. Goldstein, Multivariate Analysis Methods and Applications, New York: John Wiley & Sons, 1984. [2] P. E. Gill, W. Murray, and M. Wright, Practical Optimization, Orlando, FL: Academic Press, 1981. [3] J. S. Duster, J.-C. Jeng, P. K. Ko, and C. Hu, “User’s Guide for BSIM2 Parameter Extraction Program and The SPICE3 with BSIM Implementation,” Electronic Research Laboratory, Berkeley: University of California, 1988. [4] I. Getreu, Modeling the Bipolar Transistor, Beaverton, OR: Tektronix, 1976. [5] J.-H. Huang, Z. H. Liu, M.-C. Jeng, P. K. Ko, and C. Hu, BSIM3 Manual,” Berkeley: University of California, 1993. [6] M.-C. Jeng, P. M. Lee, M. M. Kuo, P. K. Ko, and C. Hu, “Theory, Algorithms, and User’s Guide for BSIM and SCALP,” Version 2.0, Electronic Research Laboratory, Berkeley: University of Cali­ fornia, 1987. [7] J. A. Power, A. Mathewson, and W. A. Lane, “An Approach for Relating Model Parameter Variabil­ ities to Process Fluctuations,” Proc. IEEE Int. Conf. Microelectronic Test Struct., vol. 6, Mar, 1993. [8] W. H. Press, B. P. Flannery, S. A. Teukolsky, and W. T. Vetterling, Numerical Recipes in C, Cambridge, U.K.: Cambridge University Press, 1988. [9] B. J. Sheu, D. L. Scharfetter, P. K. Ko, and M.-C. Jeng, “BSIM: Berkeley Short-Channel IGFET Model for MOS Transistors,” IEEE J. Solid-State Circuits, vol. SC-22, no. 4, Aug. 1987. [10] P. J. van Wijnen, On the Characterization and Optimization of High-Speed Silicon Bipolar Transistors, Beaverton, OR: Cascade Microtech, Inc., 1991. [11] A. Vladimirescu and S. Liu, “The Simulation of MOS Integrated Circuits Using SPICE2,” memo­ randum no. UCB/ERL M80/7, Berkeley: University of California, 1980. Other recommended publications which are useful in device characterization are L. W. Nagel. “SPICE2: A Computer Program to Simulate Semiconductor Circuits,” memorandum no. ERL-M520, Berkeley: University of California, 1975. G. Massobrio and P. Antognetti, Semiconductor Device Modeling with SPICE, New York: McGraw-Hill, 1993.

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54 Analog Circuit Simulation 54.1 54.2 54.3 54.4 54.5 54.6 54.7

Introduction Purpose of Simulation Netlists Formulation of the Circuit Equations Modified Nodal Analysis Active Device Models Types of Analysis DC (Steady-State) Analysis • AC Analysis • Transient Analysis

J. Gregory Rollins Technical Modeling Associates, Inc.

54.8 Verilog-A 54.9 Fast Simulation Methods 54.10 Commercially Available Simulators

54.1 Introduction Analog circuit simulation usually means simulation analog circuits or very detailed simulation of digital circuits. The most widely known and used circuit simulation program is SPICE (simulation program with integrated circuit emphasis) of which it is estimated that there are over 100,000 copies in use. SPICE was first written at the University of California at Berkeley in 1975, and was based on the combined work of many reasearchers over a number of years. Research in the area of circuit simulation continues at many universities and industrial sites. Commercial versions of SPICE or related programs are available on a wide variety of computing platforms, from small personal computers to large mainframes. A list of some commercial simulator vendors can be found in the Appendix. The focus of this chapter is the simulators and the theory behind them. Examples are also given to illustrate their use.

54.2 Purpose of Simulation Computer-aided simulation is a powerful aid during the design or analysis of VLSI circuits. Here, the main emphasis will be on analog circuits; however, the same simulation techniques may be applied to digital circuits, which are, after are, composed of analog circuits. The main limitation will be the size of these circuits because the techniques presented here provide a very detailed analysis of the circuit in question and, therefore, would be too costly in terms of computer resources to analyze a large digital system. However, some of the techniques used to analyze digital systems (like iterated timing analysis or relaxation methods) are closely related to the methods used in SPICE. It is possible to simulate almost any type of circuit SPICE. The programs have built-in elements for resistors, capacitors, inductors, dependent and independent voltage and current sources, diodes, MOSFETs, JFETs, BJTs, transmission lines, and transformers. Commercial versions have libraries of

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standard components, which have all necessary parameters prefitted to typical specifications. These libraries include items such as discrete transistors, op-amps, phase-locked loops, voltage regulators, logic integrated circuits, and saturating transformer cores. Versions are also available that allow the inclusion of digital models (mixed mode simulation) or behavioral models that allow the easy modeling of math­ ematical equations and relations. Computer-aided circuit simulation is now considered an essential step in the design of modern integrated circuits. Without simulation, the number of “trial runs” necessary to produce a working IC would greatly increase the cost of the IC and the critical time to market. Simulation provides other advantages, including: • The ability to measure “inaccessible” voltages and currents that are buried inside a tiny chip or inside a single transistor. • No loading problems are associated with placing a voltmeter or oscilloscope in the middle of the circuit, measuring difficult one-shot waveforms or probing a microscopic die. • Mathematically ideal elements are available. Creating an ideal voltage or current source is trivial with a simulator, but impossible in the laboratory. In addition, all component values are exact and no parasitic elements exist. • It is easy to change the values of components or the configuration of the circuit. Unfortunately, computer-aided simulation has it own set of problems, including: • Real circuits are distributed systems, not the “lumped element models” which are assumed by simulators. Real circuits, therefore, have resistive, capacitive, and inductive parasitic elements present in addition to the intended components. In high-speed circuits, these parasitic elements can be the dominant performance-limiting elements in the circuit, and they must be painstakingly modeled. • Suitable predefined numerical models have not yet been developed for certain types of devices or electrical phenomena. The software user may be required, therefore, to create his or her own models out of other models that are available in the simulator. (An example is the solid-state thyristor, which may be created from an npn and pnp bipolar transistor). • The numerical methods used may place constraints on the form of the model equations used. In addition, convergence difficulties can arise, making the simulators difficult to use. • There are small errors associated with the solution of the equations and other errors in fitting the non-linear models to the trsnsistors that make up the circuit.

54.3 Netlists Before simulating, a circuit must be coded into a netlist. Figure 54.1 shows the circuit for a simple differential pair. Circuit nodes are formed wherever two or more elements meet. This particular circuit has seven nodes, which are numbered zero to six. The ground or datum node is traditionally numbered as zero. The circuit elements (or branches) connect the nodes. The netlist provides a description of the topography of a circuit and is simply a list of the branches (or elements) that make up the circuit. Typically, the elements may be entered in any order and each has a unique name, a list of nodes, and either a value or model identifier. For the differential amplifier of Fig. 54.1, the netlist is shown in Fig. 54.2. The first line gives the title of the circuit (and is required in many simulators). The next three lines define the three voltage sources. The letter V at the beginning tells SPICE that this is a voltage source element. The list of nodes (two in this case) is next followed by the value in volts. The syntax for the resistor is similar to that of the voltage source; the starting letter R in the names of the resistors tells SPICE that these are resistors. SPICE also understands that the abbreviation “k” after a value means 1000. For the two transistors Q1 and Q2, the starting letter Q indicates a bipolar transistor. Q1 and Q2 each © 2003 by CRC Press LLC

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1 + 1k

R2

V3

1k

R3

5V

−

3

6 Q1

+

2V

0 5

4 Q2 2

V1 −

R1

+ 2V

1k

V2 − 0

0

0

FIGURE 54.1 Circuit for differential pair.

Differential pair circuit V1 4 0 2V V2 5 0 2V V3 1 0 5V R1 2 0 1k R2 3 1 1K R3 6 1 1K Q1 3 4 2 m2n2222 Q2 6 5 2 mq2n2222 .model m2n2222 NPN IS = 1e-12 BF = 100 BR = 5 TF = 100pS

FIGURE 54.2 Netlist for differential pair.

have three nodes and in SPICE, the convention for their ordering is collector, base, emitter. So, for Q1, the collector is connected to node 3, the base to node 4, and the emitter to node 2. The final entry “m2n2222” is a reference to the model for the bipolar transistor (note that both Q1 and Q2 reference the same model). The “.model” statement at the end of the listing defines this model. The model type is npn (for an npn bipolar junction transistor), and a list of “parameter = value” entries follow. These entries define the numerical values of constants in the mathematical models which are used for the bipolar transistor. (Models will be discussed later in more detail.) Most commercial circuit simulation packages come with “schematic capture” software that allows the user to draw the circuit by placing and connecting the elements with the mouse

54.4 Formulation of the Circuit Equations In SPICE, the circuits are represented by a system of ordinary differential equations. These equations are then solved using several different numerical techniques. The equations are constructed using Kirchhoff ’s voltage and current laws (KVL and KCL). The first system of equations pertains to the currents flowing into each node. One equation is written for each node in the circuit (except for the ground node), so the following equation is really a system of N equations for the N nodes in the circuit. The subscript i denotes the node index. ∂Q i ( V ) - + Wi ( t ) 0 = F i ( V ) = G i ( V ) + ---------------∂t

(54.1)

V is an N-dimensional vector that represents the voltages at the nodes. Q is another vector which represents the electrical charge (in Coulombs) at each node. The term W represents any independent

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R1

C1

gmV1

R2

I1

0

0

0

Vx 2

1

+

R1

FIGURE 54.3 Example circuit for nodal analysis.

L1

3

− R2

0

0

R3

0

0

FIGURE 54.4 Circuit for modified nodal analysis.

current sources that may be attached to the nodes and has units of amperes. The function G(V) represents the currents that flow into the nodes as a result of the voltages V. If the equations are formulated properly, a system of N equations in N unknowns results. For example, for the circuit of Fig. 54.3 which has two nodes, we need to write two equations. At Node 1: d ( C1 V1 ) 0 = (V 1 – V 2 ) ⁄ R 1 + ------------------- + I1 dt

(54.2)

We can identify G(V) as (V1 – V2)/R, the term Q(V) is C1V1 and W(t) is simply I1. Likewise at Node 2: 0 = (V 2 – V 1 ) ⁄ R 1 + V 2 ⁄ R 2 + gmV 1

(54.3)

In this example, G and Q are simple linear terms; however, in general, they can be non-linear functions of the voltage vector V.

54.5 Modified Nodal Analysis Normal nodal analysis that uses only KCL, cannot be used to represent ideal voltage sources or inductors. This is so because the branch current in these elements cannot be expressed as a function of the branch voltage. To resolve this problem, KVL is used to write a loop equation around each inductor or voltage source. Consider Fig. 54.4 for an example of this procedure. The unknowns to be solved for are the voltage V1 at Node 1, V2 the voltage at Node 2, V3 the voltage at Node 3, the current flowing through voltage source V1 which we shall call Ix and the current flowing in the inductor L1 which we shall call I1 The system of equations is: 0 = V1 ⁄ R1 + Ix 0 = V2 ⁄ R2 – Iz + Il 0 = V3 ⁄ R3 – Il 0 = V1 – Vx + V2 d ( L1 I1 ) - – V3 0 = V 2 + ---------------dt © 2003 by CRC Press LLC

(54.4)

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The use of modified nodal analysis does have the disadvantage of requiring that an additional equation be included for each inductor or voltage source, but has the advantage that ideal voltage sources can be used. The total number of equations to be solved is therefore the number of nodes plus the number of voltages sources and inductors.

54.6 Active Device Models VLSI circuits contain active devices like transistors or diodes, which act as amplifiers. These devices are normally described by a complicated set of non-linear equations. We shall consider a simple model for the bipolar transistor — the Ebers–Moll model. This model is one of the first developed, and while it is too simple for practical application, it is useful for discussion. A schematic of the Ebers–Moll model is shown in Fig. 54.5. The model contains three non-linear voltage-dependent current sources Ic , Ibf , and Ibr and two non-linear capacitances Cbe and Cbc . The current flowing in the three current sources are given by the following equations: I c = I s ( exp(V be ⁄ V t )) – exp(V ce ⁄ V t )

(54.5)

I I bf = ----s ( exp(V be ⁄ V t ) – 1) Bf

(54.6)

I I br = ----s-( exp(V bc ⁄ V t ) – 1) Br

(54.7)

The voltages Vbe and Vbc are the voltages between base and emitter and the base and collector, respec­ tively. Is , Bf and Br are three user-defined parameters that govern the DC operation of the BJT. Vt is the “thermal voltage” or kT/q, which has the numerical value of approximately 0.26 volts at room temper­ ature. Observe that in the normal forward active mode, where Vbe > 0 and Vce < 0, Ibr and the second term in Ic vanish and the current gain of the BJT, which is defined as Ic /Ib becomes numerically equal to Bf . Likewise, in the reverse mode where Vce > 0 and Vbe < 0, the reverse gain (Ie /Ib) is equal to Br . The two capacitances in Fig. 54.5 contribute charge to the emitter, base, and collector, and this charge is given by the following equations: V be

Q be = τ f I s ( expV be ⁄ V t – 1) + C je

∫ (1 – V ⁄ Vje )

–m e

(54.8)

0

V bc

Q bc = τ r I s ( exp V bc ⁄ V t – 1) + C jc

∫ (1 – V ⁄ Vjc )

–m c

(54.9)

0

IBR −

+

B

CBE C

IBF

+ −

+ CBE

IC

−

E

© 2003 by CRC Press LLC

FIGURE 54.5 The Ebers–Moll model for the bipolar transistor.

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Qbe contributes positive charge to the base and negative charge to the emitter. Qbc contributes positive charge to the base and negative charge to the collector. The first term in each charge expression is due to charge injected into the base from the emitter for Qbe and from the collector into the base for Qbc. Observe that the exponential terms in the charge terms are identical to the term in Ic . This is so because the injected charge is proportional to the current flowing into the transistor. The terms τf and τr are the forward and reverse transit times, respectively, and correspond to the amount of time it takes the electrons (or holes) to cross the base. The second term in the charge expression (the term with the integral) corresponds to the charge in the depletion region of the base–emitter junction for Qbe and in the base–collector junction for Qbc . Recall that the depletion width in a pn junction is a function of the applied voltage. The terms Vje and Vjc are the “built-in” potentials with units of volts for the base–emitter and base–collector junctions. The terms mc and me are the grading coefficients for the two junctions and are related to how rapidly the material changes from n-type to p-type across the junction. This “simple” model has eleven constants Is, Bf , Br , Cje , Cjc , Me , Mc , Vje , Vjc , Tf , and Tr that must be specified by the user. Typically, these constants would be extracted from measured I-V and C-V data taken from real transistors using a fitting or optimization procedure (typically a non-linear least-squares fitting method is needed). The Ebers–Moll model has a number of shortcomings that are addressed in newer models like Gummel–Poon, Mextram, and VBIC. The Gummel–Poon model has over 40 param­ eters that must be adjusted to get a good fit to data in all regions of operation. Models for MOS devices are even more complicated than the bipolar models. Modeling the MOSFET is more difficult than the bipolar transistor because it is often necessary to use a different equation for each of the four regions of operation (off, subthreshold, linear, saturation) and the drain current and capacitance are functions of three voltages (Vds, Vbs, and Vgs) rather than just two (Vbe and Vce) as in the case of the BJT. If a Newton–Raphson solver is to be used, the I-V characteristics and capacitances must be continuous and it is best if their first derivatives are continuous as well. Furthermore, MOS models contain the width (W) and length (L) of the MOSFET channel as parameters; and for the best utility the model should remain accurate for many values of W and L. This property is referred to as “scalability.” Over the years, literally hundreds of different MOS models have been developed. However, for modern VLSI devices, only three or four are commonly used today. These are the SPICE Level-3 MOS model, the HSPICE Level-28 model (which is a proprietary model developed by Meta Software), the public domain BSIM3 model develeped at UC Berkeley, and MOS9 developed at Phillips. These models are supported by many of the “silicon foundries,” that is, parameters for the models are provided to chip designers by the foundries. BSIM3 has been observed to provide a good fit to measured data and its I-V curves to be smooth and continuous (thereby resulting in good simulator convergence). The main drawback of BSIM3 is that it has over 100 parameters which are related in intricate ways, making extraction of the parameter set a difficult process. A process known as “binning” is used to provide greater accuracy. When binning is used, a different set of model parameters is used for each range of the channel length and width (L and W). An example of this is shown in Fig. 54.6. For a given type of MOSFET, 12 complete sets of model parameters are extracted and each is valid for a given range. For example, in Fig. 54.6, the set represented by the number “11” would only be valid for channel lengths between 0.8 and 2.0 microns and for channel widths between 0.5 and 0.8 microns. Thus, for a typical BSIM3 model with about 60 parameters, 12 × 60 = 720 parameters would need to be extracted in all and this just for one type of device. Many commercial simulators contain other types of models besides the traditional R, L, C, MOS, and BJT devices. Some simulators contain “behavioral” models which are useful for systems design or inte­ gration tasks; examples of these are integrators, multipliers, summation, and LaPlace operator blocks. Some simulators are provided with libraries of prefitted models for commercially available operational amplifiers, logic chips, and discrete devices. Some programs allow “mixed-mode” simulation, which is a combination of logic simulation (which normally allows only a few discrete voltage states) and analog circuit simulation.

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10 1

2

3

4

5

6

7

8

9

10

11

12

2.0

W

0.8

0.5 0.3

0.5

0.8 2.0 Length (L)

10

FIGURE 54.6 Binning of MOS parameters.

54.7 Types of Analysis For analog circuits, three methods of analysis are commonly used: DC, AC, and transient analysis. DC analysis is used to examine the steady-state operation of a circuit; that is, what the circuit voltages and currents would be if all inputs were held constant for an infinite time. AC analysis (or sinusoidal steady state) examines circuit performance in the frequency domain using phasor analysis. Transient analysis is performed in the time domain and is the most powerful and computationally intensive of the three. For special applications, other methods of analysis are available such as the Harminic–Balance method, which is useful for detailed analysis of nonlinear effects in circuits excited by purely perodic signals (like mixers and RF amplifiers).

DC (Steady-State) Analysis DC analysis calculates the steady-state response of a circuit (with all inductors shorted and capacitors removed). DC analysis is used to determine the operating point (Q-point) of a circuit, power consump­ tion, regulation and output voltage of power supplies, transfer functions, noise margin and fanout in logic gates, and many other types of analysis. In addition, a DC solution must be calculated to find the starting point for AC and transient analysis. To calculate the DC solution, we need to solve Kirchhoff ’s equations formulated earlier. Unfortunately, since the circuit elements will be non-linear in most cases, a system of transcendental equations will normally result and it is impossible to solve this system analytically. The method that has met with the most success is Newton’s method or one of its derivatives. Newton’s Method Newton’s method is actually quite simple. We need is to solve the system of equations F(X) = 0 for X, where both F and X are vectors of dimension N. (F is the system of equations from modified nodal analysis, and X is the vector of voltages and current that we are solving for.) Newton’s method states that given an initial guess for X i, we can obtain a better guess X i + 1 from the equation: X

i+1

i

i

–1

i

= X – [ J ( X ) ] F ( X )

(54.10)

Note that all terms on the right side of the equation are functions only of the vector X i. The term J(X) is a N × N square matrix of partial derivatives of F, called the Jacobian. Each term in J is given by: ∂F i ( X ) J i, j = --------------- ∂X j

© 2003 by CRC Press LLC

(54.11)

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Stead state anaiysis of differential pair. V1 4 0 2V V2 5 0 2V V3 1 0 5V R1 2 0 1k R2 3 1 1K R3 6 1 1K Q1 3 4 2 m2n2222 Q2 6 5 2 m2n2222 .model m2n2222 NPN IS = 1e-12 BF = 100 BR = 5 TF = 100pS .dc V1 1.0 3.0 0.01

FIGURE 54.7 Input file for DC sweep of V1.

We assemble the Jacobian matrix for the circuit at the same time that we assemble the circuit equations. Analytic derivatives are used in most simulators. The –1 in Eq. (54.10) indicates that we need to invert the Jacobian matrix before multiplying by the vector F. Of course, we do not need to actually invert J to solve the problem; we only need to solve the linear problem F = YJ for the vector Y and then calculate X i + 1 = X i – Y. A direct method such as the LU decomposition is usually employed to solve the linear system. For the small circuit of Fig. 54.3, analyzed in steady state (without the capacitor), the Jacobian entries are: J 1, 1 = 1 ⁄ R 1

J 1, 2 = –1 ⁄ R 1

J 2, 1 = 1 ⁄ R 1 + gm

J 2, 2 = 1 ⁄ R 1 + 1 ⁄ R 2

(54.12)

For a passive circuit (i.e., a circuit without gain), the Jacobian will be symmetric and for any row, the diagonal entry will be greater than the sum of all the other entries. Newton’s method converges quadratically, provided that the initial guess X i is sufficiently close to the true solution. Quadratically implies that if the distance between X i and the true solution is d, then the distance between X i + 1 and the true solution will be d 2. Of course, we are assuming that d is small to start with. Still, programs like SPICE may require 50 or more iterations to achieve convergence. The reason for this is that, often times, the initial guess is poor and quadratic convergence is not obtained until the last few iterations. There are additional complications like the fact that the model equations can become invalid for certain voltages. For example, the BJT model will “explode” if a junction is forward-biased by more than 1 V or so since : exp(1/Vt) = 5e16. Special limiting or damping methods must be used to keep the voltages and currents to within reasonable limits. Example Simulation Most circuit simulators allow the user to ramp one or more voltage sources and plot the voltage at any node or the current in certain branches. Returning to the differential pair of Fig. 54.1, we can perform a DC analysis by simply adding a .DC statement (see Fig. 54.7). A plot of the differential output voltage (between the two collectors) and the voltage at the two emitters is shown in Fig. 54.8. Observe that the output voltage is zero when the differential pair is “balanced” with 2.0 V on both inputs. The output saturates at both high and low values for V1, illustrating the nonlinear nature of the analysis. This simulation was run using the PSPICE package from MicroSim Corporation. The simulation run is a few seconds on a 486 type PC.

AC Analysis AC analysis is performed in the frequency domain under the assumption that all signals are represented as a DC component Vdc plus a small sinusoidal component Vac . V = V dc + V ac exp(jωt) © 2003 by CRC Press LLC

(54.13)

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6.0V

Output

Emitters 1.0V 0V

2.0V V (6)

4.0V

V (2)

FIGURE 54.8 Output from DC analysis.

Here, j = – 1 , ω is the radial frequency (2πf ), and Vac is a complex number. Expanding (1) about the DC bias point Vdc (also referred to as the Q point), we obtain: ∂G ( V dc ) ∂  ∂Q ( V dc ) 2 -------------------- V + αV ac Λ F ( V ) = F ( V dc ) + W dc + W ac + -------------------V ac + ∂V dc ∂t  ∂V dc  ac

(54.14)

The series has an infinite number of terms; however, we assume that if Vac is sufficiently small, all terms above first order can be neglected. The first two terms on the right-hand side are the DC solution and, when taken together, yield zero. The third term Wac is the vector of independent AC current sources which drive the circuit. The partial derivative in the fourth term is the Jacobian element, and the derivative of Q in parentheses is the capacitance at the node. When we substitute the exponential into Eq. (54.14), each term will have an exponential term that can be canceled. The result of all these simplifications is the familiar result: 0 = W ac + JV ac + jωCV ac

(54.15)

This equation contains only linear terms which are equal to the partial derivatives of the original problem evaluated at the Q point. Therefore, before we can solve the AC problem, we must calculate the DC bias point. Rearranging terms slightly, we obtain: –1

V ac = – ( J + jωC) W ac

(54.16)

The solution at a given frequency can be obtained from a single matrix inversion. The matrix, however, is complex but normally the complex terms share a sparsity pattern similar to the real terms. It is normally possible (in FORTRAN and C++) to create a suitable linear solver by taking the linear solver which is used to calculate the DC solution and substituting “complex” variables for “real” variables. Since there is no non-linear iteration, there are no convergence problems and AC analysis is straightforward and fool-proof. The same type of analysis can be applied to the equations for modified nodal analysis. The unknowns will of course be currents and the driving sources voltage sources. –1

I ac = – ( J + jωL) E ac

(54.17)

The only things that must be remembered with AC analysis are: 1. The AC solution is sensitive to the Q point, so if an amplifier is biased near its saturated DC output level, the AC gain will be smaller than if the amplifier were biased near the center of its range. 2. This is a linear analysis and therefore “clipping” and slew rate effects are not modeled. For example, if a 1-V AC signal is applied to the input of a small signal amplifier with a gain of 100 and a power © 2003 by CRC Press LLC

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supply voltage of 5 V, AC analysis will predict an output voltage of 100 V. This is of course impossible since the output voltage cannot exceed the power supply voltage of 5 V. If you want to include these effects, use transient analysis. AC Analysis Example In the following example, we will analyze the differential pair using AC analysis to determine its frequency response. To perform this analysis in SPICE, we need only specify which sources are the AC driving sources (by adding the magnitude of the AC signal at the end) and specify the frequency range on the .AC statement (see Fig. 54.9). SPICE lets the user specify the range as linear or “decade,” indicating that we desire a logarithmic frequency scale. The first number is the number of frequency points per decade. The second number is the starting frequency, and the third number is the ending frequency. Figure 54.10 shows the results of the analysis. The gain begins to roll off at about 30 MHz due to the parasitic capacitances within the transistor models. The input impedance (which is plotted in kΩ) begins to roll off at a much lower frequency. The reduction in input impedance is due to the increasing current that flows in the base-emitter capacitance as the current increases. SPICE does not have a method of calculating input impedance, so we have calculated it as Z = Vin /I(Vin), where Vin = 1.0, using the post­ processing capability of PSPICE. This analysis took about 2 seconds on a 486 type PC. Noise Analysis Noise is a problem primarily in circuits that are designed for the amplification of small signals like the RF and IF amplifiers of a receiver. Noise is the result of random fluctuations in the currents which flow in the circuit and is generated in every circuit element. In circuit simulation, noise analysis, is an extension of AC analysis. During noise analysis, it is assumed that every circuit element contributes some small noise component either as a voltage Vn in series with the element or as a current In across the element. Since the noise sources are small in comparison to the DC signal levels, AC small signal analysis is an applicable analysis method. AC analysis of differential pair. V1 4 0 2V AC 1 V2 5 0 2V V3 1 0 5V R1 2 0 1k R2 3 1 1K R3 6 1 1K Q1 3 4 2 m2n2222 Q2 6 5 2 m2n2222 .model m2n2222 NPN IS = 1e-12 BF = 100 BR = 5 TF = 100pS .AC DEC 10 1e3 1e9

FIGURE 54.9 Input file for AC analysis.

15 Gain

Input Impedence

0 1.0KHz V (6)

1.0MHz .001/I (v1) Frequency

© 2003 by CRC Press LLC

1.0GHz

FIGURE 54.10 Gain and input impedance calculated by AC analysis.

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20nV Output Noise

Input Noise 0V 1.0KHz V(INOISE)

1.0MHz

1.0GHz

V(ONOISE) Frequency

FIGURE 54.11 Noise referenced to output and input.

Different models have been developed for the noise sources. In a resistor, thermal noise is the most important component. Thermal noise is due to the random motion of the electrons: 4kT∆f 2 I n = --------------R

(54.18)

where T is the temperature, k is Boltzman’s constant, and ∆f is the bandwidth of the circuit. In a semiconductor diode, shot noise is important. Shot noise is related to the probability that an electron will surmount the semiconductor barrier energy and be transported across the junction: 2

I n = 2qI d ∆f

(54.19)

Other types of noise occur in diodes and transistors; examples are flicker and popcorn noise. Noise sources, in general, are frequency dependent. Noise signals will be amplified or attenuated as they pass through different circuits. Normally, noise is referenced to some output point called the “summing node.” This would normally be the output of the amplifier where we would actually measure the noise. We can call the gain between the summing node and the current flowing in an element j in the circuit Aj (f ). Here, f is the analysis frequency since the gain will normally be frequency dependent. Noise signals are random and uncorrelated to each other so their magnitudes must be root-mean­ squared summed rather than simply summed. Summing all noise sources in a circuit yields: In ( f ) =

∑j Aj ( f ) Ij ( f ) 2

2

(54.20)

It is also common to reference noise back to the amplifier input and this is easily calculated by dividing the preceding expression by the amplifier gain. Specifying noise analysis in SPICE is simple. All the user needs to do is add a statement specifying the summing node and the input source. Spice then calculates the noise at each as a function of frequency .noise v([6]) V1

(54.21)

See Fig. 54.11 for example output. Many circuit simulators will also list the noise contributions of each element as part of the output. This is particularly helpful in locating the source of noise problems.

Transient Analysis Transient analysis is the most powerful analysis capability because the transient response of a circuit is so difficult to calculate analytically. Transient analysis can be used for many types of analysis, such as © 2003 by CRC Press LLC

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switching speed, distortion, and checking the operation of circuits such as logic gates, oscillators, phaselocked loops, or switching power supplies. Transient analysis is also the most CPU intensive and can require 100 or 1000 times the CPU time of DC or AC analysis. Numerical Method In transient analysis, time is discretized into intervals called time steps. Typically, the time steps are of unequal length, with the smallest steps being taken during intervals where the circuit voltages and currents are changing most rapidly. The following procedure is used to discretize the time-dependent terms in Eq. (54.1). Time derivatives are replaced by difference operators, the simplest of which is the forward difference operator: Q ( tk + 1 ) – Q ( tk ) dQ ( t k ) ---------------- = ------------------------------------dt h

(54.22)

where h is the time step given by h = tk + 1 – tk . We can easily solve for the charge Q(tk + 1) at the next time point: Q ( t k + 1 ) = Q ( t k ) – h ( G i ( V ( t k )) + W i ( t k ))

(54.23)

using only values from past time points. This means that it would be possible to solve the system simply by plugging in the updated values for V each time. This can be done without any matrix assembly or inversion and is very nice. (Note for simple linear capacitors, V = Q/C at each node, so it is easy to get V back from Q.) However, this approach is undesirable for circuit simulation for two reasons. (1) The charge Q, which is a “state variable” of the system, is not a convenient choice since some nodes may not have capacitors (or inductors) attached, in which case they will not have Q values. (2) It turns out that forward (or explicit) time discretization methods like this one are unstable for “stiff ” systems, and most circuit problems result in “stiff systems.” The term “stiff system” refers to a system that has greatly varying time constants. To overcome the stiffness problem, we must use implicit time discretization methods which, in essence, means that the G and W terms in the above equations must be evaluated at tk + 1. Since G is non-linear, we will need to use Newton’s method once again. The most popular implicit method is the trapezoidal method. The trapezoidal method has the advan­ tage of only requiring information from one past time point and, furthermore, has the smallest error of any method requiring one past time point. The trapezoidal method states that if I is the current in a capacitor, then: Q ( V ( t k + 1 )) – Q ( V ( t k ) ) dQ - – I ( tk ) I ( t k + 1 ) = ------- = 2 ------------------------------------------------------h dt

(54.24)

Therefore, we need only substitute the above equation into Eq. (54.1) to solve the transient problem. Observe that we are solving for the voltages V(tk + 1), and all terms involving tk are constant and will not be included in the Jacobian matrix. An equivalent electrical model for the capacitor is shown in Fig. 54.12. Therefore, the solution of the transient problem is in effect a series of DC solutions where the values of some of the elements depend on voltages from the previous time points. dt/(2+C)

+

+

−

−

Ic1

2+C+Vc1/dt

FIGURE 54.12 Electrical model for a capacitor; the two current sources are independent sources. The prime (′) indicates values from a preceding time point. © 2003 by CRC Press LLC

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3.0V

−2.0V 0s

20ns V(6,3)

40ns

60ns

V(4,5)

Time

FIGURE 54.13 Transient response V(6,3) of differential amplifier to sinusoidal input at V(4,5).

All modern circuit simulators feature automatic time step control. This feature selects small time steps during intervals where changes are occurring rapidly and large time steps in intervals where there is little change. The most commonly used method of time step selection is based on the local truncation error (LTE) for each time step. For the trapezoidal rule, the LTE is given by: 3

3

h dx - ξ) ε = ----- -------( 12 dt 3

(54.25)

and represents the maximum error introduced by the trapezoidal method at each time step. If the error (ε) is larger than some preset value, the step size is reduced. If the error is smaller, then the step size is increased. In addition, most simulators select time points so that they coincide with the edges of pulsetype waveforms. Transient Analysis Examples As a simple example, we return to the differential pair and apply a sine wave differentially to the input. The amplitude (2 V p-p) is selected to drive the amplifier into saturation. In addition, we make the frequency (50 MHz) high enough to see phase shift effects. The output signal is therefore clipped due to the non-linearities and shifted in phase due to the capacitive elements in the transistor models (see Fig. 54.13). The first cycle shows extra distortion since it takes time for the “zero-state” response to die out. This simulation, using PSPICE, runs in about one second on a 486 type computer.

54.8 Verilog-A Verilog-A is a new language designed for simulation of analog circuits at various levels. Mathematical equations can be entered directly as well as normal SPICE-type circuit elements. Groups of equations and elements can be combined into reusable “modules” that are similar to subcir­ cuits. Special functions are also provided for converting analog signals into digital equivalents, and vice versa. Systems-type elements such as LaPlace operators, integrators, and differentators are also provided. This makes it possible to perform new types of modeling that were not possible in simulators like SPICE: • Equations can be used to construct new models for electrical devices (for example, the Ebers-Moll model described earlier could be easily implemented). • Behavioral models for complex circuits like op-amps, comparitors, phase detectors, etc. can be constructed. These models can capture the key behavior of a circuit and yet be simulated in a small fraction of the time it takes to simulate at the circuit level. • Special interface elements make it possible to connect an analog block to a digital simulator, making mixed-mode simulation possible.Verilog-A is related to and compatible with the popular Verilog-D modeling language for digital circuits. © 2003 by CRC Press LLC

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Vref

Vdif Phase Detector

Vref

Vcnt Loop Filter

VCO

OUT

Vdiv Divider

FIGURE 54.14 Block diagram of phase-locked loop.

As an example, consider a phase-locked loop circuit which is designed as an 50X frequency multiplier. A block diagram for the PLL is shown in Fig. 54.14 and the Verilog-A input listing is shown in Figs. 54.15 and 54.16. Simulation of this system at the circuit level is very time consuming due to the extreme difference in frequencies. The phase detector operates at a low frequency of 1.0 MHz, while the VCO operates at close to 50 MHz. However, we need to simulate enough complete cycles at the phase detector output to verify that the circuit correctly locks onto the reference signal. The circuit is broken up into five blocks or modules: The “top module,” VCO, divider, phase detector, and loop filter. The VCO has a simple linear dependence of frequency on the VCO input voltage and produces a sinusoidal output voltage. The VCO frequency is calculated by the simple expression freq = center + gain * (Vin – Vmin). Center and gain are parameters which can be passed in when the VCO is created within the top module by the special syntax “#(.gain(2e7),.center(3e7)” in the top module. If the parameters are not specified when the module is created, then the default values specified within the module are used instead. The special V() operator is used to obtain the voltage at a node (in this case V(in) and V(Vdd)). The sinusoidal output is created using the SIN and IDT operators. SIN calculates the sin of its argument. Idt calculates the integral of its argument with respect to time. The amplitude of the output is taken from the Vdd input, thus making it easy to integrate the VCO block with others. Given that Vdd = 5 volts, gain = 2e7 Hz/V center = 3e7 Hz, and in = 1.8, the final expression for the VCO output is: V out = 2.5 + 2.5 sin( 3e7 + 2e7 ∫ 2π ( V in – 1.8)dt)

(54.26)

The phase detector functions as a charge pump which drives current into or out of the loop filter, depending on the phase difference between its two inputs. The @cross(V1,dir) function becomes true whenever signal V1 crosses zero in the direction specified by dir. This either increments or decrements the variable STATE. The “transition” function is used to convert the STATE signal, which is essentially digital and changes abruptly, into a smoothly changing analog signal which can be applied to the rest of the circuit. The “ 0, the enhancement-loaded common souce inverter functions as a linear signal processor. This obser­ vation confirms an original contention that I/O linearity in MOSFET technology circuits requires that all pertinent MOSFETs be biased in the saturation regime of their static volt–ampere characteristic curves. b) Since the circuit at hand operates linearly for Vo ≥ (Vi – Vhnd ) > 0, a small-signal voltage gain, say Av , can be meaningfully defined. Returning to the output voltage expression, this gain is seen to be Av =

dV0 = − λ dl dVi

where the negative algebraic sign suggests phase inversion between the small-signal input voltage and its corresponding small-signal output response. A laudable attribute of the common source inverter is that its voltage gain depends on only the ratio of gate geometries, which is accurately controlled during processing. c) The voltage range, Vo ≥ (Vi – Vhnd ) > 0, required for I/O linearity translates to an input voltages requirement of Vhnd < Vi ≤ Vhnd +

Vmax 1 + λ dl

and a corresponding output voltage range of Vmax > Vo ≥

Vmax 1 + λ dl

The last result suggests that the optimum output bias voltage, say VoQ, in the sense of maximum output signal swing commensurate with linear circuit operation is 1  λ dl  VoQ =  V 2  1 + λ dl  max Using the previously derived output voltage expression, this disclosure corresponds to an input bias, ViQ given by © 2003 by CRC Press LLC

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Monolithic Device Models

ViQ = Vhnd +

1 2 λ dl

 2 + λ dl    Vmax  1 + λ dl 

4) While the load transistor is always saturated, the driver MD slips into its ohmic regime for Vo < (Vi – Vhnd ) where V  W   I dd = K n  d  Vo  Vi − Vhnd − o   L   2 Since Idd ≡ Idl , where Idl is given in step 1 above, the output voltage is now prescribed by 2 V  W  W   K n  d  Vo  Vi − Vhnd − o  = K n  l  (Vmax − Vo )  L  L   2

which produces the quadratic relationship 2 =0 (1 + λ dl )Vo2 − 2[Vmax + λ dl (Vi − Vhnd )]Vo + Vmax

An approximate solution for the resultantly small output voltage Vo is Vo ≈

Vmax   V − Vhnd   21 + λ dl  i   Vmax   

Unlike the linear output response corresponding to saturation of MD, the present result shows that the output voltage decreases nonlinearly with increasing input voltage Vi . 5) When used as a logical inverter, the logic “1” or “high” level for the circuit in Fig. 55.18 is Vmax, as defined in step 1. It follows that when the input voltage is Vmax, the logic “0” or “low” voltage Vmin is established at the output port. From the output result derived in the preceding step, Vmin ≈

Vmax   V − Vhnd   2 1 + λ dl  max   Vmax   

The proper operation of a digital inverter requires that if a logic high input, Vi = Vmax, produces a logic low output, Vo = Vmin, the identical logic low input, Vi = Vmin, must result in an output response whose value mirrors the defined logic high; that is Vo = Vmax. Since an output voltage that is numerically equal to Vmax is established only if zero current flows through the load transistor, and thus through the driver transistor as well, design care must be exercised to ensure that the logic “0” voltage Vmin is smaller than the threshold voltage Vhnd of the driver. Using the preceding relationship, Vmin < Vhnd implies the requirement Vmax −1 2V λ dl > hnd V 1 − hnd Vmax that is, the subject inverter must be capable of sufficient gain. Figure 55.19 summarizes the foregoing disclosures by sketching Vo as a function of Vi . © 2003 by CRC Press LLC

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Output Voltage, Vo Vmax

Slo pe = in Ga l √λ d =−

VoQ Q-Point For Linear Operation

Vmax 1 + √λdl

Vhnd +

Vmax 1 + √λdl

Vmin Vmin

Vhnd

ViQ

Vmax Input Voltage, Vi

FIGURE 55.19 Static transfer characteristic of an N-channel enhancement-loaded common source inverter.

Engineering Description of Device Operation A circuit analysis based on the model defined by (55.60) is useful only to the extent that a first–order estimate of MOSFET circuit performance is required. A more accurate estimate of circuit responses demands the use of more sophisticated MOSFET models. Before discussing these refinements, it is instructive to articulate several engineering and physical concepts that underlie the simplified device representation. To the foregoing end, consider an N-channel enhancement-mode MOSFET operated under the usual case of nonpositive bulk–source biasing Vbs , a small drain–source voltage Vds , and a gate–source voltages Vgs , that is allowed to vary from zero to a voltage that is larger than the gate–source threshold potential Vhn. Figure 55.20 shows the simplified cross section of the device, together with the depletion layers corresponding to the indicated biasing. For the case of Vds = Vbs = 0, depletion layers are formed around all bulk–source and bulk–rain junctions. These depletion layers are the zero bias transition regions that establish device equilibrium. For equally doped source and drain diffusions, the depletion layers are uniformly thick, and because the bulk is much more lightly doped than is either the drain or the source diffusion, most of the depletion layer thickness extends into the bulk. If Vbs is made negative, the reverse biasing across the bulk–source and bulk–drain junctions increases, and the depletion layer thickness increases uniformly. If Vds is also increased, the depletion region about the drain becomes thicker than the depletion layer about the source, since the net reverse bias at the bulk–drain junction perimeter is Vds – Vbs , while at the bulk–source junction, the reverse bias is only –Vbs . The Depletion Condition. If the gate–source voltage Vgs , is allowed to increase to a positive value that is smaller than the gate–source threshold potential, and if the bulk–source voltage Vbs , is at most 0 V, no drain current, Id , can flow even if the drain–source voltage, Vds , is large. In order to understand this fact, it is fruitful to paint a qualitative electrostatic picture corresponding to the biasing, Vbs < 0, Vds > 0, and 0 < Vgs < Vhn . This biasing circumstance defines the so-called depletion condition in an N-channel enhancement mode MOSFET. The immediate effect of Vgs > 0 is to establish a vertical electric field the gate metal (or polysilicon), through the oxide layer, and toward the silicon, as shown by the directed lines in the diagram of Fig. 55.20 Electric field lines must terminate on negative charges. Since the only substantive source of such charges © 2003 by CRC Press LLC

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1505

Monolithic Device Models

S

−

Vgs

− +

Vds

G

+

D

SiO2

Id

DEPLETION LAYER, Vds > 0

N+ DRAIN

N+ SOURCE

− − − − − − − − − − − − −

DEPLETION LAYER, Vds = 0

P-TYPE SUBSTRATE (BULK) −

Vbs

+

B

FIGURE 55.20 Cross section of an N-channel enhancement–mode MOSFET showing depletion layers for zero and positive drain–source voltages Vds . The applied bulk source voltage Vbs is presumed to be negative or zero, and the voltage Vgs applied from gate to source is positive. The encircled negative signs symbolize immobile ionized acceptor atoms. The vertical arrows in the oxide layer represent the electric field induced by applied gate–source potential. The diagram is not drawn to scale.

in an N-channel enhancement–mode MOSFET is ionized acceptor impurities in the bulk, the electric field corresponding to positive Vgs induces a depletion region beneath the gate in the MOSFET channel between source and drain. Equivalently, the electrostatic force associated with positive Vgs drives the free holes originally present in the interfacial channel region deeper into the bulk, thereby leaving only immobile ionized impurity atoms (depicted as encircled negative signs in the figure) in the channel beneath the gate. The resultant channel depletion layer, or surface depletion layer, complements the depletion layers already established around the perimeters of the source and drain diffusions. The bulk side boundaries of these transition layers are illustrated in Fig. 55.20 for the cases of Vds = 0 and Vds > 0. The reason underlying zero drain current response to even relatively large drain–source voltages is now apparent. In particular, appreciable drain current is realized only if a correspondingly large electron concentration is transported from the source to the drain. Only two paths are conceivable for this charge transport. One is through the channel depletion region, and the other is through the substrate bulk lying beneath the surface depletion layer. But no free electrons are present in the surface depletion region. Furthermore, no free electrons can be injected from the source to the bulk, thence into the drain, because the junction perimeters of both the source and drain regions are reverse biased in the depletion mode of operation. Hence, Id is essentially zero in the depletion mode of operation. The Inversion Condition. If the thin interfacial channel region described in the preceding subsection were to contain a large concentration of free electrons, in addition to immobile acceptor ions, a drain current would flow in response to the application of positive drain–source voltage. Positive Vds serves to attract channel electrons in the direction of source to drain, thereby effecting a drain current path from drain, through the channel, to the source. The transport of electrons through the channel in response to a lateral electric field set up in the direction of drain to source by the application of positive Vds is, in fact, the principle mechanism for current flow in an N-channel MOSFET. The problem now is to understand how an appreciable electron concentration is induced in the interfacial channel that is heavily populated by ionized bulk impurities. Boltzmann statistics and the mass action law provide the answer to the foregoing query. The electric field at the surface of the MOSFET produces a potential, say Vy , at the interface of oxide and silicon. If © 2003 by CRC Press LLC

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an allowance is made for a potential drop, say Vox, from the interface of gate metal (or polysilicon) and gate oxide to the interface of gate oxide and silicon surface, this induced interfacial potential subscribes to the Kirchhoff ’s voltage law (KVL) relationship Vgs = Vox + Vy

(55.61)

For analytical expedience, the electrical effects of work function differences [3] between gate lead and gate metal (or polysilicon) and between gate metal (or polysilicon) and gate silicon dioxide are presumed to have been incorporated into the voltage Vox . The aforementioned interfacial potential Vy , defines the free-electron concentration is the interfacial channel region in accordance with n = noe

Vy /V

T

=

N iB2 Vy /VT e po

(55.62)

where VT is the Boltzmann voltage, NiB is the intrinsic carrier concentration in the substrate bulk po , the equilibrium concentration of holes in the bulk, is very nearly equal to the average bulk impurity con­ centraton NA, and no =

N iB2 N iB2 ≈ po NA

(55.63)

represents the equilibrium concentration of free electrons in the bulk. Equation (55.62) establishes the mechanism for achieving large-free-electron concentrations in the interfacial channel region. It shown that n rises dramatically with the potential Vy . Suppose that Vy is allowed to increase to a voltage that forces n to equal the intrinsic carrier concentration, NiB . This particular value of Vy is symbolized as VF and is termed the Fermi potential of the substrate bulk. From (55.62) and (55.63) N  VF = VT ln A   N iB 

(55.64)

which is typically of the order of 300 mV. It is crucial to understand that at an interfacial potential of VF , the channel immediately beneath the oxide–silicon interface is intrinsic; that is, it is neither P-type, as it was prior to the application of the Fermi potential at the interface, nor is it N-type, which is mandated for significant drain currents. Further increases in Vy , which are realized by increasing the gate–source voltage Vgs , result in corresponding increases in electron concentration. When Vy is slightly greater than VF , the interfacial channel is said to experience weak inversion in the sense that there are now more electrons than there are holes in the interfacial channel region. There is a practical limit to the magnitude of Vy . This limit is the interfacial potential corresponding to n = NA, since only one hole can be relinquished by, and hence only one electron can be attracted to, each bulk impurity atom. From (55.62) and (55.63), n = NA implies Vy = 2VF . This value of interfacial potential is essentially constant, and when it is achieved, the N-channel enhancement mode MOSFET is said to be in strong inversion. Although drain currents can be observed for interfacial potentials in the weak inversion range, VF < Vy < 2VF , the condition for substantial current flow, in the sense of that predicted by the simplified static model of 55.60), is generally taken to be strong inversion; that is Vy = 2VF . The gate–source voltage Vgs corresponding to the strong inversion requirement is the threshold voltage Vhn . By (55.61) Vhn = Vox + 2VF

(55.65)

However, Vgs > Vhn ensures strong inversion, and hence a substantive supply of free–channel electrons, at only the source end of the channel. In order for strong inversion to prevail throughout the entire © 2003 by CRC Press LLC

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Monolithic Device Models

G

(a)

D

P-TYPE SUBSTRATE

N+ IN RA D

SO N+ U RC E

S

L G D

P-TYPE SUBSTRATE

N+ IN RA D

SO N+ U RC E

S

(b) Metal or Polysilicon Silicon Dioxide

Inversion Layer Depletion

FIGURE 55.21 Simplified cross sections of an N-channel enhancement-mode MOSFET. The substrate contact is now shown, and it is assumed that the bulk–source voltage Vbs is zero. (a) The case of Vgs > Vhn and Vds = 0. (b) The case of Vgs > Vhn and 0 < Vds < Vdss .

source to drain channel, it is also necessary that the gate–drain voltage Vgd exceed the threshold potential Vhn . Since Vgd = Vgs − V ds

(55.66)

Vds < Vgs − Vhn ≡ V dss

(55.67)

Vgd > Vhn implies

Thus, the biasing constraints Vgs > Vhn and Vds < Vdss, which ensure MOSFET operation in the ohmic regime of its static characteristic curves, are equivalent to establishing the criteria for strong inversion of the entire interfacial channel region. Figure 55.21 depicts the channel inversion situation for Vds = 0 and for 0 < Vds < Vdss, with the bulk–source voltage Vbs taken as zero in both cases. For Vds = 0, the diagram in Fig. 55.21 (a) shows that the depletion layers around the perimeters of the source, drain, and inverted channel are uniformly thick, as is the channel inversion layer itself. This uniformity reflects identical reverse biases imposed across both the bulk–source and bulk–drain junctions as a result of zero drain–source voltage. The uniformly thick inverted channel volume can be perceived as a resistive semiconductor bar, for which the resistance is Rds , as defined by (55.55). From a physical perspective, it also derives from Rds =

ρc L Aeff

(55.68)

where ρc is the average resistivity of the inverted channel, and Aeff is the effective cross–sectional area pierced by electrons in transit from the N+ source region to the N+ drain region. This area is the thickness of the inverted channel multiplied by W, the depth of the channel, measured in a direction that is perpendicular to the face of the page in Fig. 55.21(a). Since the free–channel charge concentration, n, is predominantly electrons, the resistivity in (55.68) is ρc ≈

© 2003 by CRC Press LLC

1 qµ nn

(55.69)

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with µn representing the mobility of channel electrons. The Ohm’s law relationship Id = Vds /Rds therefore suggests that the ohmic regime drain current, Id , is proportional to the electron mobility, µn, as well as to the geometrical factor, (W/L). The latter contention reinforces the previously discussed direct depen­ dence of drain current on the gate aspect ratio. The situation corresponding to Vds > 0 is depicted in Figure 55.21(b). The thickness of the depletion layer about the perimeter of the bulk–drain junction is now larger than the depletion layer thickness about the bulk–drain junction. This enhanced layer thickness stems from a reverse bias about the bulk–drain junction that is larger than that across the bulk–source junction by an amount Vds . Addition­ ally, the inversion layer nearer the drain end of the channel is thinner than it is near the source end because the gate–drain voltage supporting inversion at the drain site is smaller by the same amount, Vds, than is the gate–source voltage that induces an inversion layer near the source. This nonuniform inversion layer suggests that the resistance Rds associated with the resistive inversion region is no longer independent of the drain–source voltage. It follows that the resultant drain current Id = Vds /Rds , is dependent on Vds as is borne out by the second of the static characteristic equations in (55.60). There is yet another important aspect of positive Vds . In general, the current flowing through a semiconductor volume is the superposition of drift and diffusion components. When the free-carrier concentration that supports current flow has no charge gradient in the plane of charge transport, the current is exclusively a drift component proportional to the electric field established in the charge transport plane. Such a situation prevails for small Vds , which is to say the drain current arising from the application of small drain–source voltages is approximately proportional to the lateral field established in the direction of drain to source by positive Vds . Further increases in the drain–source voltage incur a more pronounced gradient to the inversion layer charge. Accordingly, the diffusion component of net drain current progressively increases with increasing Vds . Despite inceases in this diffusion current com­ ponent, the simplified static volt–ampere relationships of (55.60) account for only drift current effects in the interfacial channel of a MOSFET. Pinchoff and Saturation. As discussed in the preceding section, the thickness of the inversion layer narrows narrows nearer the drain site for increasing values of the drain–source voltage Vds . If Vds is increased to a value that equals the drain saturation voltage Vdss , the inversion layer thickness vanishes at the drain end of the channel since the interfacial potential at the end becomes zero. Figure 55.22(a) depicts this so-called channel pinchoff condition. Since the inversion layer thickness is zero at the drain end of the channel when Vds = Vdss , the differential resistance there is infinitely larger, which corroborates the channel resistance conclusions drawn earlier in conjunction with (55.55). If Vds is increased beyond Vdss , the second equation in (55.60) is impertinent to the volt–ampere characteristics of an N-channel enhancement mode MOSFET because the channel inversion region no longer embraces the entire metallurgical channel length L, as depicted in Fig. 55.22(b). Stated in other terms, the gradient of the channel charge profile increases for Vds > Vdss to such an extent that drift is no longer the predominant charge transport mechanism supporting the flow of drain current. The dimin­ ished channel length contention can be argued as follows. The application of a drain–source voltage Vds establishes a lateral electric field directed through the channel region from the drain to the source. This electric field induces a channel voltage, say Vx, with respect to the source at any position x within the length of the channel. If Vdss is the value of drain–source voltage that precisely establishes the inversion charge profile depicted in Fig. 55.22(a), Vds > Vdss suggests that the total electron charge embodied by this profile must be contained in a cross–sectional channel area whose length, say L′ is smaller than L. In particular, if Vds is written as Vds = Vdss + ∆Vds

(55.70)

Vdss is the potential dropped over the length, L′, of the channel, while ∆Vds is the voltage dropped over the channel segment ∆L, as indicated in Fig. 55.22(b). © 2003 by CRC Press LLC

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Monolithic Device Models

G S

N+ IN RA D

SO N+ U RC E

D

P-TYPE SUBSTRATE

(a) L G S

N+ IN RA D

SO N+ U RC E

D

−

Vdss

+ − ∆Vds

+

∆L

L′

P-TYPE SUBSTRATE

(b)

Metal or Polysilicon Silicon Dioxide

Inversion Layer Depletion

FIGURE 55.22 Simplified cross sections of an N-channel enhancement–mode MOSFET. The substrate contact is not shown, and it is assumed that the bulk–source voltage Vbs is zero. (a) The case of Vgs > Vhn and Vds ≡ Vdss. (b) The case of Vgs > Vhn and Vds = Vdss +∆Vds .

Note that the channel region of length ∆L comprises a depletion layer whose intrinsic electric field is a function of the difference voltage, ∆Vds . Intuitively, a drain current dependence on ∆L, and hence on ∆Vds , can be suspected since the large lateral electric field associated with large ∆L (and thus, large Vds ) encourages the transport of inversion layer electrons into the drain region. This intuitively deduced dependence of Id on ∆L is ignored in the third equation of (55.60) for the static model of an N-channel enhancement-mode MOSFET. Refinements to the Simple MOSFET Model Several refinements to the simple static model of a MOSFET are typically invoked in either manual or computer-aided analyses of MOS technology circuits. Among these are channel length modulation corrections to the drain saturation current, incorporation of threshold voltage dependence on bulk–source bias, incorporation of series lead resistances, and inclusion of charge storage phenomena in the carrier transport mechanism that underlies MOSFET operation. These refinements are discussed below with respect to only N-channel devices. With appropriate symbolic changes, they apply equally well to P-channel MOSFETs. Channel Length Modulation. As discussed carlier, the effective channel length of a MOSFET decreases by an amount ∆L when the transistor operates in the saturated regime of its static characteristic curves. Recall from (55.59) that the drain current flowing in an N-channel MOSFET is Idss when the drain–source voltage Vds is Vdss . Since Idss is inversely proportional to the channel length L, the drain current Id for Vds > Vdss must be larger than Idss by a factor of [L/(L – ∆L)]; that is,

Id V

ds ≥Vdss

© 2003 by CRC Press LLC

(

Kn  W    V − Vhn 2  L  gs  L  = I dss  = ∆L  L − ∆L  1− L

)

2

(55.71)

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In this semiquantitative relationship, the factor ∆L/L relates empirically to the drain–source voltage as ∆L = L

1 Vλ 1+ Vds − Vdss

(55.72)

so that in the saturated domain,

Id V

ds ≥Vdss

=

2 Kn  W  V − Vdss    Vgs − Vhn 1 − ds Vλ  2  L 

(

)

(55.73)

In this expression, Vλ termed the channel length modulation voltage, is of the order of tens of volts. Instead of the zero slope in the saturated common drain static volt–ampere characteristics that is indicated in Fig. 55.17, the effect of a finite channel length modulation voltage is to incur a nonzero slope Idss /Vκ in each of these curves. Example 2. In the circuit of Fig. 55.23, all transistors have a transconductance coefficient of 200 µmho/V. Transistor M2 has a threshold voltage of 2.3 V, a channel length modulation voltage of 25 V, and a gate aspect ratio that is five times larger than that of transistor M1. In turn, M1 is characterized by a threshold voltage of 2.0 V, and a channel length modulation voltage of 20 V. Transistor M3 has a gate aspect ratio of 10, a gate–source threshold voltage of 1.8 V, and a channel length modulation voltage of 45 V. If the power line voltage, VDD , is 5.2 V, calculate the current, Id3, flowing in the drain of transistor M3 for VCC = 5.2 V and VCC = 10.4 V. Solution. 1) Both transistors M1 and M2 operate in their saturation regions since the gate and drain terminals of each of these devices are electrically tied together. Moreover, since the substrates of all transistors are grounded and no negative voltages are applied to the circuit, the currents conducted by transistors M1 and M2 are identical. Accordingly, from (55.74) 2 K n  W2  Vds2 − Vdss2   Vgs2 − Vhn2 1 +   2  L  Vλ 2  

(

=

)

2 K n  W1  Vsd1 − Vdss1    Vgs1 − V hn1 1 + 2  L Vλ1  

(

)

VDD

M2

Id3 M3

VCC

M1

Vk

FIGURE 55.23 Schematic diagram of an enhancement-mode N-channel MOSFET constant current sink.

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In this expression, the gate–source voltage of M2, Vgs2, is (VDD – Vk) ≡ Vds2, the drain–source voltage of transistor M2, and Vgs1, the gate–source voltage of transistor M1, which is also the drain–source voltage of M1, is the voltage Vk, indicated in the schematic diagram. Moreover, from (55.67), the drain–source saturation voltage Vdss2, of M2 is (Vgs2 – Vhn2) ≡ (VDD – Vk – Vhn2), while the drain–source saturation voltage Vdss1 of transistor M1 is (Vgs1 – Vhn1) ≡ (Vk – Vhn1). Using these observations and introducting a parameter h such that Vhn1 Vλ1 h=  W2 L  Vhn2   W L  1 + V   1  λ2  1+

the foregoing current relationship yields Vk =

VDD Vhn2 − hVhn1 − h +1 h +1

For the stipulated device parameters and circuit variables, Vk is 2.62 V. Note that the M1–M2 subcircuit functions as a voltage divider that serves to transform the power line voltage VDD into a voltage Vk that is suitable for biasing the current sinking transistor M3. 2) For transistor M3 in Fig. 55.23, the gate–source voltage is Vk , the drain–source voltage is VCC , and the drain–source saturation voltage is Vk – Vhn3 . Since VCC > (Vk – Vhn3), at even the smallest value of VCC of interest, M3 is always saturated. Thus, Id 3 =

2 K n  W3  VCC − Vk + Vhn3    (Vk − Vhn3 ) 1 +  2  L  V λ3  

For VCC = 5.2 V, Id3 is 740.0 µA, while VCC = 10.4 delivers Id3 = 817.9 µA. It follows that the effect of a finite channel length modulation voltage in transistor M3 is to increase the drain current flowing in this device by 10.5% when VCC doubles its original 5.2 V value. Substrate Bulk Effect on Threshold Voltage. In an N-channel enhancement mode MOSFET, the gate–source threshold voltage Vhn, is not a constant, as inferred by (55.65). Instead, Vhn is modulated by the applied bulk–source voltage, Vbs . This threshold modulation, which is commonly called bulk or body effect, can be understood qualitatively by studying the effect of a strong reverse bias applied from the substrate to the source. In particular, a large negative value of Vbs serves to deplete the bottom part of the substrate in the immediate neighborhood of the bulk contact. As a result, free electrons in this neighborhood are displaced toward the oxide-semiconductor interface. Since interfacial depletion pre­ cedes the channel inversion caused by a gate–source bias that is at least as large as the threshold potential, these displaced free electrons must be pushed back down into the body of the substrate before channel inversion can occur. The threshold voltage expression given by (55.65) accounts for only equilibrium (zero net reverse bias across the boundary separating the inversion layer from the substrate) concentra­ tions of free substrate electrons. Thus, the actual threshold voltage must be that given by (55.65) plus a correction to allow for the additional energy required to displace substrate electrons that are no longer in equilibrium because of nonzero Vbs . This correction is minimal for lightly doped substrates. Substrate bias–induced threshold voltage modulation is also minimized by thin oxides. Thin oxide layers promote strong vertical field intensities for even small gate–source biases, thereby expediting interfacial channel depletion.

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A suitable expression for the corrected threshold voltage, say Vhnc , is Vhnc = Vhn + 2Vθ (2VF − 2VT − Vbs )

(55.74)

where VF is defined by (55.64). With La =

ε sVT qN A

(55.75)

representing the Debye length of electrons in a substrate having an average impurity concentration of NA, the parameter Vθ, which is known as the body effect voltage, is Vθ =

(qN A La / Cox ) VT

2

=

qN A ∈s Cox2

(55.76)

In (55.75) and (55.76), εs is the dielectric constant of silicon [1.053 pF/cm], while Cox is the density of gate oxide capacitance given by (55.52). In (55.74), the effect of a bulk–source reverse bias Vbs < 0 is to increase the effective threshold voltage Vhnc. The amount of such increase depends on the value of the body effect voltage Vθ . Confirming earlier contentions, the amount of requisite threshold correction is small if Vθ is small, which requires small substrate concentration and/or large Cox (corresponding to small oxide thickness Tox ). Equation (55.74) is easily modified to embrace P-channel transistors by replacing Vhnc by Vhpc , the corrected source to gate threshold voltage of a P-channel enhancement mode MOSFET. Additional changes entail replacing Vhn by Vhp , substituting Vsb , the source to substrate bias, for Vbs, and finally, replacing NA in (55.75) and (55.76) by ND , the average donor concentration in the N-type substrate of a P-channel device. It is often convenient to express the effective threshold voltage of an enhancement mode MOSFET in terms of the zero bias threshold voltage; that is, the threshold voltage prevailing with zero bias applied between bulk and source. From (55.74), the zero bias threshold voltage, say Vhno , is Vhno = Vhn + 2 Vθ (VF − VT )

(55.77)

  Vbs Vhnc = Vhno + 2 Vθ (VF − VT )  1 − −1 2(VF − VT )   

(55.78)

It follows that

Ohmic Resistances. Although ohmic resistances generally exert negligible effects on the volt–ampere characteristics of MOSFETs, they nonetheless materialize in the bulk, drain, and source regions. The topological significance of these parasitic resistances is abstracted by the symbolic schematic diagram of the N-channel enhancement-mode MOSFET shown in Fig. 55.24. The resistance of the heavily doped drain region is rdd , and its source region counterpart is rss . Both of these resistances are of the order of a few ohms. Unfortunately, they are difficult to calculate satisfac­ torily because their respective net values incorporate the contact resistances formed at the surface of the drain and source. Moreover, they are spreading resistances, since the currents in the drain and source do not flow in one direction. The resistance, rbb , is a spreading resistance associated with the bulk substrate. Because of the relatively light impurity concentration in the bulk, rbb is considerably larger than either rdd or rss . Under static conditions, however, the voltage dropped across rbb is about the same as, or even less than, the voltages dropped across the internal drain and source resistances, since the substrate–source © 2003 by CRC Press LLC

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D Id rdd rbd

DBD D′ I′d

rbb

G

B′

B

S′ rbs

DBS rss S

FIGURE 55.24 Schematic diagram of an N-channel enhancement–mode MOSFET with internal ohmic resistances and bulk–drain and bulk–source diodes explicitly delineated. For P-channel devices, the diode connections are reversed, as are the indicated reference directions of the currents, Id and I d′ .

and substrate–drain junctions are reverse biased. These junctions are represented respectively by the diodes, DBS and DBD, which have their own internal ohmic resistances, rbs and rbd , respectively. The immediate effect of incorporating regional ohmic resistances into the MOSFET model is to separate internal drain, source, and bulk nodes from the externally accessible drain, source, and bulk terminals. Thus, the drain–source (Vds), gate–source (Vgs), bulk–source (Vbs), bulk–drain (Vbd), and gate–drain (Vgd) voltages exploited previously in all modeling relationships and discussions must now be interpreted as the voltages appearing from internal drain (D′) to internal source (S′), gate to internal source, internal bulk (B′) to internal source, internal bulk to internal drain, and gate to internal drain terminals, respectively. Likewise, the drain current, Id, in all preceding modeling expressions must be viewed as the channel current I d′ in Fig. 55.24. Note that the channel current differs from the measurable drain current by an amount that equals the small reverse bias current that flows through the drain–bulk PN junction diode. MOSFET Capacitances. The frequency response of MOS analog circuits and the switching speed of MOS digital circuits are limited by the time required to charge and discharge capacitances that appear between internal device nodes, from interconnecting metallization to the circuit ground plane, and between interconnecting electrical lines. Figure 55.25 illustrates the topological interconnection of intrinsic device capacitances. The capacitors, Cbd and Cbs, represent transition capacitances associated with the PN bulk–source and bulk–drain junctions. Both of these elements have the voltage function form, C=

C0   V 1 −   V j − 2VT 

m

(55.79)

where m is the grading coefficient, C0 is the zero-bias value of the transition capacitance, and Vj is built-in potential of the pertinent junction. When computing C0, care must be taken to include the areas of the drain and source diffusion sidewalls, as well as the areas of the bottoms of these diffused or implanted regions. © 2003 by CRC Press LLC

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D Cold

Id

rdd Cgd

DBD

rbd

I′d G

Cbd rbb

DBS

B rbs

Cgs rss Cbs

Cgb

Cols

S

FIGURE 55.25 Schematic diagram of an N-channel enhancement-mode MOSFET with internal ohmic resistances, bulk–drain and bulk–source diodes, and internal device capacitances explicitly delineated. The diodes DBD and DBS appear as ideal elements in the senses of zero internal capacitances and resistances. For P-channel devices, the diode connections are reversed, as are the indicated reference directions of the currents Id and I′d .

The capacitors, Cold and Cols , are overlap capacitances between the gate and drain and the gate and source, respectively. These capacitances are zero when the subject MOSFET is fabricated in self–aligning gate technology. To first order, the sum of gate–bulk (Cgb), gate–drain (Cgd), and gate–source (Cgs) capacitances is the net effective capacitance of the gate oxide layer; that is, WLC ox = C gb + C gd + C gs

(55.80)

The partitioning of WLCox into three component capacitances entails a complex calculation. Such par­ titioning must ensure consistency between capacitive charging currents and the charge storage and transport implications of the static volt–ampere relationships of the MOSFET mode [4]–[6]. For manual analysis purposes, the following approximate relationships have proven to be effective. 1. For linear small-signal operation in the ohmic region of the static MOSFET characteristic curves [7], C gs =

WLC ox 2

 VdsQ  1 + 3V   dssQ 

(55.81)

Cg =

WLC ox  VdsQ  1− 2  VdssQ 

(55.82)

and

In these two expressions, VdsQ and VdssQ , respectively, symbolize the quiescent values of interal drain–source voltage and drain saturation voltage. Equation (55.80) through (55.82) imply © 2003 by CRC Press LLC

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Monolithic Device Models

 V  C gb = WLC ox  dsQ   3VdssQ 

(55.83)

2. For linear small-signal operation in the saturation region of the static MOSFET characteristic curves [8] C gs =

2WLC ox 3

C gd ≈ 0

(55.84) (55.85)

and C gb =

WLC 0x 3

(55.86)

Note that despite Cgd ≈ 0, the net effective gate–drain capacitance is not zero; rather, it is Cold , the gate–drain overlap capacitance. Other High-Order Effects. At risk of oversimplification, most of the deviations between the observed electrical behavior of MOSFETs and the response predicted by either the simplified model or any of its embellished versions result from processing and manufacturing attempts aimed toward improving the electrical performance of these devices. For example, a continuing design issue is increased switching speed. In MOSFETs, the most commonly invoked mechanism for improved response speed is reduction in channel length. But there are several serious drawbacks to a progressively decreased channel length, most of which stem from the commensurate increase in the strength of the lateral electric field induced by drain–source bias. One drawback of large channel fields is the possible saturation of the nominal velocity at which majority carriers (electrons in N-channel devices) are transported from the source to the drain [9]. In particular, at low field strengths, the carrier velocity increases almost linearly with the strength of the electric field in which the carrier is immersed. The relevant proportionality constant between carrier velocity and small electric field strengths is, in fact, the carrier mobility. But at high fields, this carrier velocity approaches a constant (known as the saturated limited velocity), thereby actually limiting the ability of a MOSFET to respond quickly to applied excitation. Moreover, carrier velocity saturation decreases the transconductance coefficient and increases the thermal sensitivity of static drain current [10]. A second ramification of the high electric fields associated with short channel lengths is the production of hot carriers [11]. Hot carriers differ from the routine majority carriers that populate the channel in that they absorb an amount of energy from the high lateral channel field that is large enough for them to overcome the potential barrier at the silicon dioxide–silicon interface and thus be injected into the gate oxide layer. This injection alters the voltage drop across the gate oxide and hence, the threshold voltage. The resultant threshold shift causes device turn on voltage perturbations that are especially troublesome in logic cells that are operated in noisy environments or in logic cells for which the logic swing (different between the logical “1” and logical “0” voltages) is small. The trapping of injected charge in the oxide layer also degrades the operational reliability of a MOSFET through a phenomenon known as oxide wearout [12], and it increases the vulnerability of the device to electromagnetic and nuclear radiation [13]. Yet another effect of high channel fields is impact ionization, or avalanche multiplication, in the highfield drain end of the channel [14]. The secondary carrier emission associated with this phenomenon can, like hot carrier production, lead to oxide charging. It can also induce substrate currents, thereby signif­ icantly modifying the static and dynamic behavior predicted by the simplified model and its first-order refinements [15]. © 2003 by CRC Press LLC

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A more insidious problem materializes when impact ionization occurs in the bulk. Secondary carriers emitted in the bulk can diffuse large distances owing to the relatively light doping concentration of the substrate. These diffusing carriers can perturb the electrical operation of proximate devices on the same chip, thereby limiting the packing densities of junction isolated circuits [16]. Yet another substrate problem is punchthrough, wherein the depletion layers about the source and drain regions coalesce in the channel [17]. Punchthrough is an extreme condition that results from careless application of excessive drain–source voltage. Finally, thin gate oxides are desirable from the viewpoint that they diminish the sensitivity of threshold voltage to bulk–source voltage. But the strong vertical electric fields encouraged by thin oxides also decrease the lateral, source to drain, mobility of free channel charges [18], since such fields tend to repel carriers toward the substrate bulk. As a result, the effective mobility of channel charges, which is known as surface mobility, can be markedly diminished from the concentration-dependent mobility experienced by current carriers under equilibrium conditions. This decrease in carrier mobility degrades the speed of MOSFET response, as well as reducing the static drain current predicted by the simplified model. Small-Signal Equivalent Circuit The development of the small-signal MOSFET model parallels the small-signal modeling of any nonlinear element. In particular, the nonlinear volt–ampere branch relationships of a MOSFET are expanded into a Taylor series about the quiescent operating point, and only the linear terms of these expansions are retained. For the model depicted in Fig. 55.25, the only nonlinearity, assuming that the bulk–drain and bulk–source diodes are reverse biased, is the internal drain current I d′ , which is a function of the internal gate–source, internal drain–source, and internal bulk–source voltages Vgs , Vds , and Vbs , respectively. Thus, I′d ≈ I′dQ +

+

∂I d′ ∂Vgs

(V

gs

Q

∂I′d V − VbsQ ∂Vbs Q bs

(

)

− VgsQ +

∂I d′ V − VdsQ ∂Vds Q ds

(

) (55.87)

)

If the signal components of drain current, gate–source voltage, drain–source voltage, and bulk–source voltage are denoted by i′da = I′d − I′dQ v ga = Vgs − VgsQ

(55.88)

v da = Vgs − VdsQ v ba = Vbs − VbsQ ida ′ = g mf v ga + g mbv ba +

v da ro

(55.89)

Assuming, as is usually the case for linear signal processing applications, that the MOSFET is biased in its saturated domain, (55.73), (55.78), (55.87), and (55.89) yield a forward transconductance gmf of

g mf

© 2003 by CRC Press LLC

∂I′ = d ∂Vgs ∆

Q

  3  Vλ + VdsQ −  2  VdssQ W  = 2K n   I dQ ×   L  V V +V −V dsQ dssQ  λ λ 

(

)

     

(55.90)

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where IdQ, VdsQ, and VdssQ are the quiescent values of the drain current, drain–source voltage, and drain saturation voltage, respectively. Observe that while the small-signal forward transconductance of a bipolar junction transistor increases linearly with the quiescent collector current, the small-signal forward transconductance of a MOSFET increases with only the square root of the quiescent drain current. Observe further that gmf rises with the square root of gate aspect geometry and that for a large channel length modulation voltage Vλ,

g mf

W  ≈ 2K n   I dQ  L

Vλ →∞

(59.91)

The equations used to arrive at (55.90) produce a bulk transconductance gmb of ∆

g mb =

∂I ′d q = λ b g mf ∂Vbs

(55.92)

Vθ 2 2(VF − VT ) − VbsQ

(55.93)

where λb =

Note that the threshold modulation factor λb and hence the small-signal bulk transconductance, is small if Vθ , which is a measure of the influence exerted on the threshold voltage by bulk-source biasing, is small. Finally, the small-signal channel resistance ro derives from 1 ∆ ∂I d′ = ro ∂Vds

= Q

I dQ Vλ + VdsQ − VdssQ

(55.94)

Equation (55.94) shows that the drain–source channel resistance is infinitely large for an infinitely large channel length modulation voltage Vλ. Equation (55.89) and Fig. 55.25 give rise to the small-signal equivalent circuit of Fig. 55.26. In this model, the intrinsic drain–bulk and source–bulk diodes are replaced by open circuits on the assumption that the bulk–drain and bulk–source junctions are back biased. The resultant equivalent circuit is appli­ cable to N-channel, as well as to P-channel enhancement-mode MOSFETs. Example 3. The MOSFET inverter of Fig. 55.27(a) is biased at its input port by a voltage VGG and design care is exercised to ensure that the driver transistor MD operates in its saturated regime. Specifically, if VoQ symbolizes the quiescent component of the net output voltage Vo , VoQ > (VGG – Vhnd), where Vhnd is the threshold voltage of the driver. The driver transistor has a gate aspect ratio of (WD /L), while the gate aspect ratio of the load device ML is WL /L; otherwise, the two transistors in the circuit are identical. Derive expressions for the small-signal, low-frequency voltage gain Av = Vos /Vs of the circuit, and the small-signal driving point output resistance Rout , faced by the capacitance CL. Additionally, give an expression for the 3-dB bandwidth, B3dB, of the circuit, assuming that capacitance CL is the dominant energy storage element in the neighborhood of the circuit 3-dB bandwidth. Solution. 1) The first step toward solving this problem is to recognize that at low signal frequencies, the load transistor ML functions as a two terminal linear resistance, say RLeff , as is suggested by the AC schematic diagram in Fig. 55.27(b). This resistance is the ratio Vx /Ix in the load transistor AC

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Cold D rdd Cgb

i′da

gmf vga

Cgs

gmb vba

Cbd

rbd

Cbs

rbs

ro

G vga

+

vba

− −

+ rbb

rss

Cols

S

B

FIGURE 55.26 Small-signal, high-frequency equivalent circuit for N-channel and P-channel enhancement-mode MOSFETs. All indicated capacitances are evaluated at the quiescent operating point of the subject MOSFET.

VDD

ML

RLeff Vo

MD +

Vos

MD CL

CL

Vs

+

− +

Vs −

VGG − (a)

(b)

FIGURE 55.27 (a) A capacitively loaded N-channel enhancement-mode common source inverter. (b) AC schematic diagram of the circuit in (a). The battery voltages, VGG and VDD , are replaced by short circuits (or by their internal impedances, which are presumed to be zero here), the load transistor ML is replaced by an effective load resistance RLeff , and the net output voltage Vo , is represented by its small-signal component Vos .

schematic diagram drawn in Fig. 55.28(a), for which the low-frequency small-signal equivalent circuit is the structure depicted in Fig. 55.28(b). An inspection of the latter diagram reveals v ga = v ba = −Vx + rssl I x and

[

Vx = (rssl + rddl )I x + rol I x + g mflv ga + g mblv ba © 2003 by CRC Press LLC

]

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Monolithic Device Models

rddl ML +

Vx

gmfl vga Ix

gmbl vba

rol − vba

+ vga −

+

− rssl

rbbl

+ Vx

Ix −

FIGURE 55.28 (a) AC schematic diagram of the load transistor in the amplifier of Fig. 55.27(a). (b) Small-signal, low-frequency equivalent model of the circuit in (a). The subscript “l,” appended to the symbology for the conven­ tional small-signal parameters of a MOSFET, signifies that the subject parameter corresponds to the load transistor.

Combining these two relationships and recalling (55.92), the effective resistance RLeff presented to the drain of the driver transistor MD by the load transistor ML is ∆

RLeff =

Vx rddl + rol = rssl + Ix 1 + (1 + λ bl ) g mflrol

where λbl is the threshold modulation factor of the load transistor. Since the source and drain ohmic resistances, rssl and rddl , respectively, are very small and since the drain–source channel resistance, rol , is typically at least in the mid-tens of thousands of ohms, RLeff can be approximated as RLeff ≈

1

(1 + λ bl )g mfl

2) With the load transistor modeled as a two terminal load resistance, the AC schematic diagram of the inverting amplifier in Fig. 55.27(a) becomes the structure in Fig. 55.27(b), for which the smallsignal model in the diagram is drawn in Fig. 55.29(a). Noting in the latter diagram that  r  v ga = Vs +  ssl  Vos  RLeff  and  r  v ba =  ssl  Vos  RLeff  a straightforward low-frequency circuit analysis produces a small-signal voltage gain Av of Av =

© 2003 by CRC Press LLC

V os =− Vs

g mfd RLeff R +r +r 1 + (1 + λ bd ) g mfdrssd + Leff ddd ssd rod

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R′

Rout Vos RLeff

rddd

gmfd vga

gmbd vba

CL

rod

− vba +

+ vga − +

Vs

rssd

rbbd

rddd

Vx

− (a) +

gmfd vga

R′

Ix −

rod

gmbd vba

+ vga −

− vba + rssd

rbbd

(b)

FIGURE 55.29 (a) Small-signal equivalent circuit of the amplifier represented by the AC schematic diagram in Fig. 55.27(b). (b) Small-signal model for calculating the resistance R′ presented to the output port of the amplifier in Fig. 55.27(a) by the driver transistor.

Observe a 180° phase inversion, as expected, between the source excitation and resultant output voltage response. Note further that for a large drain–source channel resistance, rod , and small ohmic resistance, rddd and rssd , in the drain and source leads, respectively, the voltage gain relation­ ship collapses to the simple expression Av ≈ −g mfd RLeff 3) It is instructive to substitute the simplified expression for the effective load resistance into the foregoing approximate gain equation. The result is Av ≈ −

g mfd

(1 + λ bl )g mfl

The approximate gain relationship exploits the assumption of infinitely large drain-source channel resistance, and hence infinitely large channel length modulation voltage. Thus, (55.91) can be used for the transconductances that appear in the preceding gain equation. But since the load and driver © 2003 by CRC Press LLC

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Monolithic Device Models

transistors conduct the same quiescent drain current and since the two transistors are identical except for differing gate aspect ratios,  1  Wd L Av ≈ −    1 + λ bl  W1 L The last result agrees well with the results of the voltage gain analysis performed in conjunction with Example 1. In that example, an analogous inverter was addressed analytically by applying a simple MOSFET model that inherently ignores both channel length and threshold modulation phenomena. In fact, the present result agrees exactly with the relevant results of Example 1 if in the present case, threshold modulation is ignored to constrain λbl to zero. 4) Since the load capacitance, CL, in the inverting amplifer of Fig. 55.27(a) is assumed to be the dominant energy storage element at signal frequencies lying in the immediate neighborhood of the circuit 3-dB bandwidth, CL is the only capacitive element that appears in the corresponding small-signal model of Fig. 55.29(a). With only one capacitance embedded in a low-pass network, the 3-dB bandwidth (in units of radians per second) is simply the inverse of the time constant established by the capacitance. Thus, B3dB =

1 1 = RoutC L R′ RLeff C L

(

)

where Rout is the driving point resistance facing CL, and R′ in Fig. 55.29(a) is the resistance seen to the left of the effective load resistance RLeff. The resistance R′ is the Vx /Ix ratio in the model of Fig. 55.29(b), which can be shown to be

[

]

R′ = rddd + rssd + 1 + (1 + λ bl ) g mfdrssd rod Clearly, the resistance R′ is larger than the relatively large drain–source channel resistance, rod . It follows that R′ is significantly larger than RLeff , whence the approximate 3-dB bandwidth is B3 dB ≈

(1 + λ bl )g mfl 1 ≈ RLeffC L CL

Complementary MOS (CMOS) Complementary MOS, or CMOS, is an actively loaded enhancement-driven MOSFET network. Its topol­ ogy, which is depicted in Fig. 55.30, consists of an N-Channel enhancement mode MOSFET (MN) whose drain terminal is connected to the drain terminal of a P-channel enhancement mode MOSFET (MP). Because the gate terminals of both the N-channel and the P-channel devices are indicated as electrically tied together, the response of a CMOS cell coalesces the response afforded by an N-channel amplifier driving a P-channel enhancement load with the response delivered by a P-channel amplifier driving an N-channel enhancement load. Many of the advantages of CMOS technology in digital logic applications are made transparent by an analysis of the static transfer characteristic of the CMOS cell. Static Transfer Characteristic The P-channel transistor MP in Fig. 55.30 is saturated when its source–drain voltage Vsdp = (VDD − Vo ) is at least as large as its source–gate voltage Vsgp = (VDD + Vi ), less one source–gate threshold voltage, say Vhp . Thus, MP is saturated for output voltages that satisfy Vo ≤ Vi = Vhp © 2003 by CRC Press LLC

(55.95)

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VDD MP

Idp Vi

Vo Idn

MN

FIGURE 55.30 The circuit schematic diagram of a simple CMOS cell.

Analogous reasoning leads to Vo ≥ Vi − Vhn

(55.96)

as the saturation requirement for the N-channel device, MN. Consider first the case of Vi < Vhn, which corresponds to cutoff of transistor MN, or Idn = 0 in Fig. 55.30. Since Vi is small, (55.95) is not satisfied, and transistor MP operates in its ohmic regime. Using the simplified model for the static volt–ampere characteristics of an enhancement mode P-channel MOSFET, it follows that W  (V − V0 )   I dp = K p  p  (VDD − V0 ) (VDD − Vi ) − Vhp − DD  2 L    p

(55.97a)

where Kp is the transconductance coefficient of MP (Wp /Lp) is the gate aspect ratio of MP. Since Idp = Idn = 0, Vo = VDD for all Vi < Vhn . As diagrammed in the static transfer characteristic of Fig. 55.31, the logic “1” level is the full power supply voltage VDD . This logic result contrasts with that of the enhance­ ment-loaded enhancement-driven inverter, for which the logic “1” level is one load threshold voltage below the power line voltage. For output voltages in the neighborhood of VDD , (55.95) is violated, while (55.96) is satisfied; that is, MP remains in its ohmic regime, but MN is saturated. Accordingly, with Kn and (Wn /Ln) denoting the transconductance coefficient and gate aspect ratio, respectively, of the N-channel MOSFET, respectively, Idp = Idn implies W   (V − Vo )  I dp = K p  p  (VDD − Vo )(VDD − Vi ) − Vhp − DD 2  Lp   

(55.97b)

2  K  W  =  n   n  (Vi − Vhn ) = I dn  2   Ln 

If Vic is the input voltage at which Vo falls from VDD to the level Vi + Vhp = Vic + Vhp , the last result delivers Vic =

© 2003 by CRC Press LLC

VDD − Vhp + ηnp Vhn 1 + ηnp

(55.98)

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Monolithic Device Models

Output Voltage, Vo VDD (Vic + Vhp)

Unity Slope

(Vic − Vhn) Vmin Vhp

Vmin

Vic Vhn

VDD Input Voltage, Vi

FIGURE 55.31 Approximate static forward transfer characteristic of the CMOS cell in Fig. 55.30.

where  K  W / L  η np =  n  n n   K p  Wp / L p 

(55.99)

Thus, for Vi < Vic , MP operates in its ohmic regime, MN is in saturation, and the static transfer characteristic is derived implicity from (55.97b). When the output voltage Vo simultaneously satisfies (55.95) and (55.96) both MP and MN are saturated. It follows that since Idp = Idn ,  K p   Wp   K n   Wn  2 2  2  L  (VDD − Vi − Vhp ) =  2   L  (Vi − Vhn)   p   n

(55.100)

which is independent of Vo . Moreover, this relationship is satisfied for Vi = Vic . Thus, for (Vi – Vhn) < Vo < (Vi + Vhp ), Vi ≡ Vic , implying, as shown in Fig. 55.31, an infinitely large incremental slope in the static transfer characteristic at Vi = Vic . In practice, the magnitude of this slope is large, but not infinitely large, owing to channel length modulation and body effects. For Vi > Vi c , which corresponds to Vo < (Vi − Vhn), transistor MN operates in its ohmic regime, while transistor MP is saturated. The resultant static characteristic derives from  K p   Wp  Vo   K n   Wn   2  2  L  (VDD − Vi − Vhp ) =  2   L  Vo  Vi − Vhn − 2    p   n

(55.101)

If Vmin denotes the logic “0” output voltage corresponding to a logic “1” input voltage of Vi = VDD (55.101) produces © 2003 by CRC Press LLC

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Vmin = (VDD − Vhn) 1 −

1  Vhp  ηnp  VDD − Vhn 

2

(55.102)

which can be approximated as Vmin ≈

1 2ηnp

 Vhp2     VDD − Vhn 

(55.103)

Since Vmin must be smaller than Vhn in order to ensure that a logic “1” output results from an application of a logic “0” input, (55.103) shows that ηnp >

Vhp2

(55.104)

2Vhn(VDD − Vhn)

is a design requirement in logic applications of CMOS. Small-Signal Analysis Although the foregoing static analysis suggests that abrupt switching between logic states takes place at an input voltage of Vic, the slope of the transfer characteristics when both transistors are saturated is finite in an actual CMOS cell. The slope, which represents the small-signal voltage gain of the circuit, is best estimated by performing a small signal analysis. To this end, let the input voltage Vi in Fig. 55.30 be the superposition of an input Q-point voltage, say ViQ , and an applied small-signal voltage, say Vs . The resultant output voltage Vo is a Q-point component VoQ , and a small-signal voltage Vos , where the ratio Vos /Vs is the small-signal voltage gain Av . The low-frequency small-signal model for evaluating Av for the CMOS cell in Fig. 55.30 is offered in Fig. 55.32. In this equivalent circuit, which is derived from the model given in Fig. 55.26 Vsn = Vsp = Vs

(55.105)

+ + va

−

− gmfpva

+

vb

rssp

rbbp

gmbpvb rop

Vsp −

rddp Vos rddn

− ron

Vsn +

+ vc

−

gmfnvc

gmbnvd −

vd

rssn

rbbn

+

FIGURE 55.32 Small-signal, low-frequency equivalent circuit of the CMOS cell in Fig. 55.30. © 2003 by CRC Press LLC

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Monolithic Device Models

+ −

+ va −

gmfpva

vb

rssp

rbbp

gmbpvb rop

RLp Ix −

rddp

Vx + (a) Vos RLp

rddn

ron

+

+ vc −

Vsn

gmfnvc

gmbnvd −

vd

rssn

rbbn

+

−

(b)

FIGURE 55.33 (a) Small-signal, low-frequency equivalent circuit used to evaluate the effective resistance RLp that loads the drain of the N-channel transistor MN in the CMOS amplifier of Fig. 55.30. (b) Equivalent circuit for evaluating the voltage gain due solely to the N-channel transistor in the CMOS cell.

The partitioning of the input signal voltage into two identical components Vsn and Vsp reflects the simultaneous application of the input signal Vs to the gates of both the N-channel and the P-channel transistors. Since the small-signal equivalent circuit is linear, this voltage decomposition allows superpo­ sition theory to be applied in the evaluation of the voltage gain. In particular, Vos = AvnVsn + AvpVsp = (Avn + Avp )Vs

(55.106)

where Avn is the circuit voltage gain due solely to the application of Vsn to the N-channel transistor. Similarly, Avp is the voltage gain attributed exclusively to the application of Vsp to the gate of the P-channel device. The N-channel transistor gain, Avn, can be computed by setting the signal source, Vsp , to zero. With Vsp = 0, the P-channel transistor acts as an effective load on the drain terminal of the N-channel transistor. The effective resistance of this P-channel load, say RLP , derives from an analysis of the circuit given in Fig. 55.33. In this model, Va = Vb = − I x rssp

(55.107)

whence RLP = © 2003 by CRC Press LLC

Vx = rddp + rssp +[1 + (1 + λ bp )g mfprssp ]rop Ix

(55.108)

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Given RLP as the effective resistance terminating the drain of the N-channel transistor, the voltage gain,

Avn, follows from a consideration of the equivalent circuit provided in Fig. 55.33(b). It can be shown that

Avn = −

g mfnRLP R +r +r 1 + (1 + λ bn )g mfnrssn + LP ddn ssn ron

(55.109)

The gain, Avp , attributed to the P-channel transistor can be found by repeating the foregoing calculations for the case of Vsn = 0. In this case, the N-channel transistor loads the drain of the P-channel device by a resistance, say RLn . By symmetry, RLn is given by (55.108) with the subscript “p,” replaced by the subscript, “n,” to connote N-channel device parameters. Similarly, Avp is derived from (55.109), with the subscript “n” supplanted by subscript “p.” The result is Avp = −

g mfp RLn R +r +r 1 + (1 + λ bp )g mfprssp + Ln ddp ssp rop

(55.110)

where RLn = rddn + rssn + [1 + (1 + λ bn )g mfnrssn]ron

(55.111)

The substitution of (55.109) and (55.110) into (55.106) leads directly to an expression for the desired smallsignal voltage gain. This gain is the slope of the static transfer characteristics curve at a quiescent operating point that constrains the operation of both transistors in the CMOS cell to their saturated regimes. The CMOS cell voltage gain expression can be simplified by assuming that the internal series drain and source resistances are negligible and the channel length modulation voltages are large in both the P-channel and the N-channel transistors. Accordingly, RLn ≈ ron ≈

Vλn I dQ

and

(55.112) RLp ≈ rop ≈

Vλp I dQ

where IdQ is the quiescent drain current flowing through both transistors and Vλn and Vλp represent the channel length modulation voltages of the N-channel and P-channel transistors, respectively. Thus, Av =

(

)(

Vos ≈ − g mfn + g mfp ron rop Vs

)

(55.113)

and using (55.112),

(

) 

  1 + K p Wp L p K n (Wn Ln ) 2K n (Wn / Ln )   Av = − 1 1 I dQ  +  Vλn Vλp  

     

(55.114)

Interestingly, (55.114) shows that the voltage gain magnitude is inversely proportional to the square root of the quiescent drain current flowing on both devices of the CMOS cell. © 2003 by CRC Press LLC

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Monolithic Device Models

Cross Section of Monolithic CMOS In principle, the CMOS cell shown in Fig. 55.30 can be realized by interconnecting an individual N-channel (NMOS) enhancement-mode MOSFET and an individual P-channel (PMOS) enhancementmode transistor. But both MOSFETs can be fabricated monolithically on the same chip, thereby explaining why a CMOS cell is often referred to as CMOS “device.” The simplified cross section of a monolithic CMOS transistor is shown in Fig. 55.34. The left-hand side of this structure comprises the N-channel component of the CMOS cell. This half structure consists of gate oxide, surface metallization for the source, drain, gate, and bulk electrical contacts for the NMOS transistor, and a P-type substrate into which a P+ and two N+ regions are diffused or implanted. The two N+ diffusions form the source and drain regions of the NMOS transistor, while the P+ diffusion establishes a low resistance contact to the substrate bulk. The right-hand side of the structure is the PMOS transistor. It has a lightly doped N-type well that is diffused into the P-type bulk. Into this N-type region, which forms the substrate of the PMOS transistor, two P+ regions are diffused for the PMOS source and drain. An N+ diffusion or implant into the lightly doped N-type region ensures a low resistance electrical contact to the PMOS bulk. The ability to synthesize CMOS as a monolithic interconnection of its NMOS and PMOS components is advantageous from both fabrication and circuit design perspectives. However, potentially serious problems plague the resultant structure [19]. The source of most of these problems is the unavoidable appearance of bipolar transistors and semiconductor resistors beneath the surface of the CMOS cell. To crude first order, these bulk parasitic elements are formed topologically as shown in Fig. 55.35. The emitter of the PNP bipolar junction transistor in this diagram is the P+ drain/source diffusion of the P-channel MOSFET, its base is the N-type PMOS well, and its collector is the P-type tub that serves as the substrate for the NMOS device. The NPN transistor has an emitter which is the N+ drain/source diffusion of the NMOS transistor, its base is the P-type tub, and its collector is formed of the N-type well that is used as the PMOS substrate. The electrical equivalent of the circuit topology abstracted in Fig. 55.35 is the schematic offered in Fig. 55.36. Under most operational circumstances, the surface current, Id, flowing through the CMOS device is significantly larger than the bulk current, Ibulk, flowing through the bulk parasitic elements. One way of ensuring Id  Ibulk is to preclude the bipolar devices from turning on, which requires that resistors

SN BN

GN

DN

DP

SP

BP

GP

N+

N+

PMOS

N+

NMOS

P+

P-TYPE

P+

METAL

N-TYPE

INSULATOR SP PMOS GP

BP DP DN

GN

BN NMOS SN

FIGURE 55.34 Simplified cross section of a monolithic CMOS transistor. © 2003 by CRC Press LLC

SiO2

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Vi + VDD −

Vo SN BN

GN

DN

DP

SP BP

GP

NMOS

PMOS

QN QP

Rn

Rp

P-TYPE

METAL

INSULATOR

SiO2

P+

N+

N

FIGURE 55.35 Simplified topological representation of parasitic bulk transistors and resistors in the cross section of monolithic CMOS. Also shown is the biasing and the I/O terminals for normal inverter operation of the CMOS cell.

VDD PMOS

Rn

Id Vi

Vo

QP Icn

NMOS

Icp

QN

DESIRED

CMOS CELL

Ip

PARASITIC BULK ELEMENTS

Ibulk

In

Rp

Id + Ibulk

FIGURE 55.36 Equivalent circuit of electrical cross section depicted in Fig. 55.35.

Rn and Rp be so small as to disallow the development of an appreciable forward bias across the emitterbase junctions of either BJT. Small Rn and Rp require large doping concentrations in the P-type substrate and in the N-type well, respectively. Unfortunately, these large substrate concentrations have the unde­ sirable effect of increasing the threshold voltages of, and exacerbating the body effect in, both MOS transistors. © 2003 by CRC Press LLC

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Short of achieving an ideal goal of Rn = Rp = 0, there is no practical way of precluding turn on of both the parasitic bipolar devices, because the bipolar subcircuit on the right-hand side of Fig. 55.36 is a positive feedback network. The instability mechanism can be illustrated qualitatively as follows. Assume that both of the parasitic bipolar units conduct slightly. Let the collector current of transistor QN be Icn and that of QP be Icp . The collector current, Icn , produces a base current, Icn /βn , in the base of QN, where βn is the static forward current transfer ratio, or static beta of QN. Similarly, the base current flowing in transistor QP is Icp /βp , with βp symbolizing the static beta of QP. The resultant current, In , flowing in the resistance, Rn , is I n = I cn −

I cp

(55.115)

βp

Likewise, Rp conducts a current Ip of I p = I cp −

I cn βn

(55.116)

Let the original collector current Icn increase be a small amount, say ∆Icn . This perturbation is arguably the result of a change in circuit operating temperature, impacting electromagnetic radiation, or a spurious signal that superimposes with the power line voltage VDD . Then, In can be expected to change by an amount ∆In such that ∆I n = ∆I cn −

∆I cp βp

>0

(55.117)

The current change ∆Icp in the QP collector current is positive, since positive ∆In increases the forward bias across the emitter–base junction of transistor QP. But an increase, ∆Icp , in the QP collector current, Icp , results in a change, say ∆Ip , in the current flowing through the resistance Rp . If, in addition to satisfying (55.117), ∆I p = ∆I cp −

∆I cn >0 βn

(55.118)

a further increase in the collector current of QN materializes, owing to the fact that an enhanced current through Rp increases the forward bias across the emitter–base junction of the NPN transistor, QN. This additional increase, which superimposes with the originally incurred increase in the collector current of QN, propagates through the bulk bipolar subcircuit in a fashion that is similar to the foregoing scenario. It therefore causes further increases in the QN (and in the QP) collector current. The process described previously continues until both bipolar transistors saturate, which is the socalled latchup condition. Since saturated bipolar transistors develop only small voltages across their collector–emitter terminals, the latchup condition in monolithic CMOS is tantamount to a very low resistance path between the power supply line and circuit ground. The resultantly large power supply current, most of which is the saturation current supplied to the bulk parasitic elements, causes significant self heating of the bulk. Aside from the fact that this self heating supports still further increases in bulk bipolar collector currents, it can damage the semiconductor bulk, thereby leading to catastrophic failure of the entire CMOS structure. It is important to note that two conditions must be satisfied if latchup is to occur. These two conditions, which are defined by (55.117) and (55.118), can be combined into the single latchup condition, βnβ p > 1 © 2003 by CRC Press LLC

(55.119)

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Recalling that the beta of bipolar devices is inversely proportional to base width, the likelihood of latchup can be minimized by designing the CMOS cell so that its N-type substrate well is sufficiently wide and/or its P-type substrate is also wide. Unfortunately, these width guidelines do not complement ongoing demands to downsize integrated devices. This observation explains why latchup is an especially perplexing problem in many state of the art VLSI architectures that feature minimal geometry devices. Another way to reduce bipolar beta is to increase base region doping. This increased doping decreases the resistances Rn and Rp , but only at the expense of increasing NMOS and PMOS threshold voltages and increasing the MOSFET threshold voltage dependence on bulk–source biasing. The foregoing difficulties with respect to minimizing the risk of CMOS latchup compel creative engineering solutions to the latchup problem. One of these solutions involves selective light doping of the P+ and/or N+ drain/source regions with gold or other inert impurities. Such doping has the effect of reducing the minority carrier diffusion lengths to which bipolar transistor betas are dependent. Another solution places a lightly doped trench of semiconductor material around the PMOS transistor. This guard ring inserts a large resistance in series with the collectors of both transistors QN and QP in the bulk parasitic subcircuit. The resultantly high net collector resistances inhibit collector current increases, thereby reducing the chance of latchup. In some applications, the guard ring is an oxide trench that serves to open circuit the collectors of QN and QP.

Depletion-Mode MOSFET As is the case with enhancement-mode transistors, there are two types of depletion mode MOSFETs: the N-channel device and the P-channel transistor. Figure 55.37(a) displays the cross section of the N-channel depletion mode MOSFET, and Fig. 55.37(b) is the corresponding circuit schematic symbol. The P-channel counterparts to the N-channel depletion-mode transistor are offered in Fig. 55.38. A comparison of these two figures to the device cross sections offered in Figs. 55.15(a) and 55.16(a) reveals that the cross sections of depletion-mode MOSFETs differ from those of enhancement-mode transistors only in that depletionmode transistors have a semiconductor impurity layer diffused or implanted in the source to drain spacing S

G

D

Tox

Silicon Dioxide

N+

Drain

N+

Source

N-Channel L

P-TYPE SUBSTRATE (BULK) B

(a) − Vgd + G

+ Vgs −

(b)

+

Id

D

Ib

Ig

Is

B + Vbs −

Vds −

S

FIGURE 55.37 (a) Simplified cross section of an N-channel depletion-mode MOSFET. The diagram is not drawn to scale. (b) Electrical schematic symbol of an N-channel depletion-mode MOSFET.

© 2003 by CRC Press LLC

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S

G

D

Tox

Silicon Dioxide

P+

Drain

P+

Source

P-Channel L

N-TYPE SUBSTRATE (BULK) B

(a) +

G

Vdg − − Vsg +

−

Id Ig

Ib

Is

D

B − Vsb

Vsd

+

+ S

(b)

FIGURE 55.38 (a) Simplified cross section of a P-channel depletion-mode MOSFET. The diagram is not drawn to scale. (b) Electrical schematic symbol of a P-channel depletion-mode MOSFET.

immediately beneath the gate oxide. This thin channel region has an impurity concentration that is greater than the substrate dopant concentration and is typically of the order of 1016 atoms/cm3. Static Volt–Ampere Curves The cross section of the N-channel depletion mode MOSFET differs from that of the N-channel enhance­ ment mode MOSFET by a thin N-type layer, which is diffused or implanted in the source–drain channel of the depletion mode device. An understanding of the electrical effect of this channel is facilitated by recalling that in N-channel enhancement mode transistors, a concentration of free electrons must be induced in the source–drain channel in order for a drain current to flow. The vehicle for inducing such a channel of free electrons is the gate–source voltage, Vgs . In particular, Vgs must exceed the gate–source threshold voltage, Vhnc , to allow an enhancement MOSFET to operate in either the ohmic or saturated regimes of its static characteristic curves. Thus, Vhnc is the minimum gate–source voltage commensurate with establishing the supply of free-channel region electrons whose source to drain transport comprises the transistor drain current. Moreover, the amount by which Vgs exceeds Vhnc determines the amount of drain current that flows for given Vds . This means that for fixed Vds , the dran current is controlled by Vgs or, more correctly, by the excess voltage Vgs – Vhnc . In contrast, the diffused or implanted N-type channel renders a copious supply of free electrons available in the source–drain channel of an N-channel depletion mode MOSFET. Consequently, this device does not require elevation of the gate-source voltage to a threshold level. In fact, the free electrons made available by ionized N-type impurity atoms in the diffused or implanted channel allows for the flow of drain current in response to positive drain-source voltage for Vgs = 0 and even for Vgs < 0. This contention can be understood by studying the N-channel depletion-mode device cross section of Fig. 55.39, which is drawn to illustrate the electrical effects of nonpositive gate-source voltage Vgs < 0, positive drain-source voltage Vds > 0, and negative bulk–source voltage Vbs < 0. The effect Vbs < 0 is a depletion layer about the bulk–source, bulk–drain, and bulk–channel PN junctions. Since the source and drain regions are much more heavily doped than is the P-type substrate, most of the bulk–source and bulk–drain depletion layers extend into the substrate. On the other hand, the fact that the channel dopant © 2003 by CRC Press LLC

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−

S −

Vgs

+

Vds

+

D

G

Id

N+ DRAIN

N+ SOURCE

SiO22

P-SUBSTRATE −

BULK DEPLETION

Vbs

+

SURFACE DEPLETION

B

FREE ELECTRONS

METAL

FIGURE 55.39 Cross section of an N-channel depletion mode transistor. The indicated depletion layers correspond to Vds > 0, Vgs < 0, and Vbs < 0. The diagram is not drawn to scale.

concentration is only slightly larger than that of the substrate means that the bulk-channel depletion layer extends significantly into the channel region. The net bulk-channel depletion layer is thicker at the source end of the channel than at the drain end, because the reverse bulk-channel bias at the drain end is (Vds – Vbs), while at the source end, it is only –Vbs . A depletion layer is also formed beneath the oxide-surface interface, since negative gate-source voltage serves to repel free-channel electrons away from the interface and deeper into the channel. This interfacial depletion region is thicker at the drain site, where the net interface-channel reverse bias is the gate-drain voltage, Vgd = (Vgs – Vds), than at the source end, where the interface-channel reverse bias is only the gate-source voltage, Vgs . As a result, free-channel electrons are confined to the trapezoidal region shown as the darkened area in Fig. 55.39. These free electrons are available for source to drain transport, and thus, they give rise to a drain current, Id , in respect to an applied positive drain-source bias, Vds . Several points in regard to the cross section picture of the depletion layers formed in an N-channel depletion-mode transistor warrant attention. First, an interface-channel depletion layer is established at the source end of the N-type channel even if Vgs ≡ 0 because of metal-oxide contact potential, stray charges trapped in the gate oxide region, and interfacial oxide-surface imperfections. This zero-bias depletion layer, which corresponds to a zero-bias interfacial potential at the source end of the channel, is analogous to the zero-bias transition layer and corresponding built-in potential that prevail across the PN junction of a conventional semiconductor diode. Second, the available volume of free-channel electrons is controllable by the gate-source bias. A decreasing (more negative) Vgs produces a surface depletion region that extends deeper into the substrate. This extended depletion layer reduces the channel

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cross section area through which available free electrons are transported, thereby increasing the effective channel resistance and decreasing the drain current that flows as a result of applied drain–source bias. On the other hand, an increased (more positive) Vgs narrows the depth of the surface–channel depletion layer, which increases the drain current, Id , for a given value of drain–source bias, Vds . Thus, just as an increasing Vgs increases the drain current flowing for fixed Vds in NMOS, the drain current that flows in an N-channel depletion-mode MOSFET (DNMOS) biased at a fixed positive drain–source voltage is a monotonically increasing function of gate–source bias. A third important point is that the bulk–source bias, Vbs , like the gate–source bias, Vgs , modulates the drain current. An increasingly negative Vbs makes the bulk–channel depletion layer protrude further into the channel, thereby diminishing the cross section channel area pierced by transported free electrons and thus, the drain current that flows for a given Vds . Accordingly, a body effect induced by substrate reverse bias, not unlike the body effect in enhancement-mode transistors, materializes in depletion-mode devices. A fourth point is that for the depletion condition illustrated in Fig. 55.39, the free electrons available for transport in the source–drain channel are isolated from the oxide-semiconductor interface by the surface depletion region induced by Vgs < 0. These electrons are not as affected by the vertical electric fields arising from gate–source bias as are those free electrons that prevail in enhancement mode devices. Thus, even if the doping concentration in the N-type channel of a DNMOS device is identical to the P-type substrate doping concentration in an NMOS transistor, the average mobility of free electrons in a depletion-mode MOSFET is larger than that of free electrons in an enhancement-mode unit. Since the transit time, which is the average time required for the transport of electrons from the source to the drain, is inversely related to electron mobility, the electrical responses of DNMOS circuits are potentially faster than those of comparable NMOS circuits. For given Vds and Vbs , it is clear that there exists a negative value of gate–drain voltage, say Vgd = (–Vpnc ), such that the surface depletion layer coalesces with the channel side of the bulk-channel depletion layer at the drain end of the N-type channel. This condition, which is diagrammed in Fig. 55.40(a), is referred to as channel pinchoff and corresponds to a gate–source voltage of Vgs = Vgs + Vds = −Vpnc + Vdss

(55.120)

where Vpnc , a positive number, is termed the channel pinchoff voltage. The parameter Vds is the drain saturation voltage; it is the particular drain–source voltage commensurate with channel pinchoff at the drain site. For Vgd < (–Vpnc ), which corresponds to Vds > (Vgs + Vpnc) ≡ Vdss, the point of channel pinchoff moves closer to the source end of the channel, as indicated in Fig. 55.40(b). Channel length modulation is therefore observed in an N-channel depletion mode transistor, just as it is in enhancement-mode technology. A first-order static model of the drain current increase arising from channel length modu­ lation is identical to the model invoked for channel length modulation in NMOS. This is to say that the effect of channel length modulation is given by (55.73), subject to replacing Vhn by (–Vpmc ) and interpreting Vdss as (Vgs + Vpnc). Progressive increases in Vds above Vdss move the channel pinchoff point closer to the source end of the channel. When the gate–source bias Vgs decreases to (–Vpnc ), the pinchoff point is at the source, and the entire channel is said to be pinched off. Under this operating condition, no drain current can flow, since the entire source to drain channel is depleted of free electrons. It follows that a necessary condition for nonzero drain current, Id, in DNMOS technology is Vgs > (–Vpnc ), which suggests viewing (–Vpnc ) as an effective threshold voltage for DNMOS. To first order, the dependence of pinchoff voltage Vpnc on the bulk–source bias is the threshold voltage function given by (55.78), provided Vhno in (55.78) is replaced by Vpno , the pinchoff voltage of zero bulk–source bias. Moreover, the substrate Debye length implicit to the variable Vθ is taken to be the average Debye length in the N-type channel of DNMOS. The static volt–ampere characteristic of an N-channel depletion-mode MOSFET derives approximately from the static equations for enhancement-mode transistors [20]. In particular,

© 2003 by CRC Press LLC

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−

S Vgs

−

+

Vds

+

D

G

Id

N+ DRAIN

N+ SOURCE

SiO2

Vbs

−

+

B (a) −

S Vgs

−

+

Vds

+

D

G

Id

N+ DRAIN

N+ SOURCE

SiO2

−

Vbs

+

B (b)

FIGURE 55.40 Cross section of N-channel depletion-mode MOSFET. The diagram is not drawn to scale. (a) Pinchoff at drain end of channel, Vgd = –Vpnc . (b) Operation beyond pinchoff, Vgd ≤ –Vpnc .

0,  W   V  K n   Vds  Vgs + Vpnc − ds  , 2    L   Id =  2 Vds − Vdss   Kn  W  ,  2  L  Vgs + Vpnc 1 + V   λ  

(

)

Vgs ≤ −Vpnc Vgs > −Vpnc and

(

Vds < Vgs + Vpnc Vgs > −Vpnc and

(

Vds ≥ Vgs + Vpnc

)

(55.121)

)

where Id is taken as a current flowing into the drain terminal of an N-channel transistor. Because of internal drain, source, and substrate resistances, Vgs , Vds , and Vbs (on which Vpnc is dependent), respectively, are internal gate–source, internal drain-source, and internal bulk–source voltages, respectively. For Pchannel depletion-mode MOSFETs, (55.121) remains applicable provided Id is interpreted as a current flowing out of the drain terminal, Vgs is replaced by the source–gate voltage Vsg , Vds is supplanted by the source–drain voltage Vsd , and Vbs is replaced by the bulk–source voltage Vsb . The commentary offered earlier in regard to second-order effects in enhancement-mode technology apply to depletion-mode technology as well.

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VDD

Idl

ML

Vo Idd + Vi

MD

−

FIGURE 55.41 Schematic diagram of an enhancement-driven, deple­ tion-loaded N-channel MOSFET inverter.

Depletion-Loaded Inverter Depletion-mode transistors, like enhancement-mode MOSFETs, can be used as load devices in inverters designed for either digital or analog signal-processing applications. The simplified schematic diagram of a typical enhancement-driven depletion-loaded inverter is given in Fig. 55.41. As the following analyses confirm, the inverter offers a logic swing capability that extends to the power supply voltage, VDD . In linear signal processors, the inverter in Fig. 55.41 also delivers a small-signal voltage gain that is larger than the gain afforded by an enhancement-driven enhancement-loaded inverter. Static Transfer Analysis. The static transfer characteristic of the depletion loaded, enhancement driver inverter is depicted in Fig. 55.42. Its derivation commences with the observation that the gate–source voltage of ML is zero. Accordingly, ML in the circuit of Fig. 55.41 is saturated if (VDD – Vo) > Vpnl , where Vo is the indicated output voltage and Vpnl is the pinchoff voltage of ML. (For simplicity, body effect, as well as channel length modulation, series internal device resistances, and other second-order effects are ignored.) With ML saturated, the simplified static model of a MOSFET gives for its drain current Idl I dl =

K nl  Wl  2 V , 2  Ll  pnl

for

(

Vo ≤ VDD − Vpnl

)

(55.122)

where Knl is the transconductance coefficient and (Wl /Ll ) is the gate aspect ratio of ML. On the other hand, Vo > (VDD – Vpnl ) constrains ML to its ohmic regime, where I dl =

K nl  Wl  V − Vo   VDD − Vo )Vpnl − DD (    2  Ll  2  

(

for Vo > VDD − Vpnl

)

(55.123)

If the input voltage Vi is smaller than the threshold voltage Vhnd of the driver transistor MD, Idd in Fig. 55.41 is zero. Moreover, since the circuit operates as an inverter, Vo is large when Vi is small. Thus, Vi < Vhnd forces ML to conduct in its ohmic regime where (55.123) is applicable. Since Idl is identical to Idd , Vo = VDD , for Vi < Vhnd

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(55.124)

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Output Voltage, Vo

ML OHMIC; MD OFF ML OHMIC; MD SAT.

VDD VDD − Vpnl

Un ity

Slo pe

MD SAT.; MD SAT.

MD SAT.; ML OHMIC Vpnl √λdl Vmin Vmin

Vhnd VA

VDD Input Voltage, Vi

FIGURE 55.42 Static transfer characteristic of an enhancement-driven, depletion-loaded, common-source MOSFET inverter. The characteristic exploits the simplified MOSFET model equations.

Within the context of simplified MOSFET modeling, the logical “one” voltage of the depletion-loaded enhancement-driven inverter is seen to be the power supply voltage, VDD . Recall that in the enhancementloaded enhancement-driven inverter considered earlier, the logical “one” voltage is one load threshold voltage below the supply voltage. As Vi rises above the threshold voltage, Vhnd , the driver begins to conduct a drain current, Idd . If Vi is such that Vo , which is the drain–source voltage developed across MD, is larger than (Vi – Vhn), MD is saturated, whence I dd =

2 K nd  Wd  (V − Vhnd ) 2  Ld  i

for Vo ≥ Vi − Vhnd

(55.125)

with Knd denoting the transconductance coefficient of the driver, and Wd /Ld its gate aspect ratio. As long as Vo , in addition to exceeding Vi – Vhnd , remains above VDD – Vpnl , ML continues operating in its ohmic domain. Since Idd = Idl , (55.123) and (55.125) provide

(VDD − Vo )Vpnl − VDD2− Vo  = λ2dl (Vi − Vhnd ) 



(

for Vo ≥ (Vi − Vhnd ) and Vo > VDD − Vpnl

)

2

(55.126)

where ∆

λ dl =

K nd  Wd Ld  K nl  Wl Ll 

(55.127)

Equation (55.126) implicitly defines the static forward transfer characteristic for the indicated range of output voltages. The subject relationship shows that Vo reduces to VDD – Vpnl when Vi rises to a value, say VA, give by © 2003 by CRC Press LLC

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Monolithic Device Models

VA = Vhnd +

Vpnl

(55.128)

λ dl

When Vo falls below VDD – Vpnl , ML becomes saturated. But as long as Vo remains above Vi – Vhnd , MD remains saturated. The pertinent transfer characteristic derives from equating (55.122) and (55.125), so that 2 Vpnl = λ dl (Vi − Vhnd )

2

(

for Vo > (Vi − Vhnd ) and Vo ≤ VDD − Vpnl

)

(55.129)

This relationship is independent of the output voltage Vo and additionally, it is satisfied for only one value of the input voltage; namely, Vi = VA, as defined by (55.128). It follows that the circuit at hand, biased at Vi = VA, delivers a theoretically infinitely large magnitude of small-signal gain, subject to the assumption that channel length and threshold voltage modulation phenomena can be ignored. When Vo falls below Vi – Vhnd , the load transistor remains saturated, while the driver enters its saturation regime. Under this condition, the pertinent device volt–ampere equations deliver a static transfer char­ acteristic that derives from the solution of the quadratic expression, 2 λ dlVo2 − 2λ dl (Vi − Vhnd )Vo + Vpnl = 0

(55.130)

The logical “0” output, say Vmin, corresponding to a logical “1” input of Vi = VDD can be determined by applying the quadratic formula to this relationship. To first order, Vmin =

2 Vpnl

2λ dl (VDD − Vhnd )

(55.131)

Because a logical “0” input must produce a logical “1” output, and recalling that the logical “1” output of VDD is produced whenever Vi < Vhnd , (55.131) implies the design requirement, VDD > Vhnd +

2 Vpnl

2λ dlVhnd

(55.132)

Small-Signal Analysis. Recall that the static volt–ampere equations of a depletion-mode MOSFET differ from those of its enhancement-mode counterpart only in that the threshold voltage Vhnc of the enhance­ ment-mode transistor is replaced by (–Vpnc), where Vpnc symbolizes the pinchoff voltage, corrected for body effect, of the depletion-mode device. It follows that the topology of the low-frequency model for a depletion-mode MOSFET is identical to that of the enhancement-mode transistor. Indeed, the highfrequency model depicted in Fig. 55.26 remains applicable to depletion-mode units, provided Vhnc is replaced by (–Vpnc) in (55.90) – (55.94), which analytically define the small-signal model parameters gmf , gmb , and ro . The discussion in regard to capacitances and various high-order effects submitted in the section on refinements to the simple MOSFET model remain generally applicable as well. Example 4. The input voltage, Vi , in the enhancement-driven depletion-loaded MOSFET inverter of Fig. 55.41 is of the form Vi = (ViQ + Vs), where ViQ is a constant voltage that biases both transistors in their saturated domains. The voltage Vs is a small amplitude, low-frequency sinusoidal signal. Derive a general expression for the low-frequency small-signal voltage gain Av = Vos /Vs , and compare the results to those obtained earlier in conjunction with the enhancement-driven enhancement-loaded MOSFET inverter. Do not ignore the electrical effects of internal series resistances, bulk-induced threshold and pinchoff voltage modulation, and channel length modulation. © 2003 by CRC Press LLC

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Solution. 1) The schematic diagram in Fig. 55.41) indicates that, at low frequencies, transistor ML imposes a resistive load on the drain of the driver transistor, MD. This contention follows from the obser­ vations that VDD is grounded for small-signal considerations and that the only signal exciting transistor ML is applied simultaneously to its gate and source terminals by the drain of MD. Thus, for small input signals, ML behaves as a two terminal linear resistor of resistance, say RLeff . Accordingly, the pertinent small-signal equivalent circuit is identical to the equivalent circuit shown in Fig. 55.29, save for the fact that no load capacitor is currently considered. From the results of Example 3, the voltage gain is of the form Av =

Vos =− Vs

g mfd R

Leff

1 + (1 + λ bd ) g mfdrssd +

RLeff + rddd + rssd rod

The only remaining task is the determination of an expression for the resistance Rleff . 2) The equivalent circuit pertinent to finding RLeff is offered in Fig. 55.43, in which the drain, to which VDD is applied in the original circuit schematic diagram, is grounded, and the gate is connected directly to the source. Let a signal current, Ix , be applied as indicated from ground to the source–gate terminal. The desired resistance, which is the ratio of the indicated voltage, Vx , to the applied current, Ix , is

RLeff =

(rssl + rddl ) + [1 + (1 + λ bl )g mflrssl ]rol 1 + λ bl g mflrol

3) Several important aspects of the foregoing analysis warrant attention. a. If all model parameters in both the gain and the effective resistance expressions are evaluated for MOSFET operation in the saturated regime, the voltage gain obtained is the slope at Vi = VA of the static transfer characteristic curve plotted in Fig. 55.42. Although the voltage gain is not infinitely large, as is implied by the aforementioned transfer characteristic, its magnitude

rddd

+ vga −−

gmfd vga

rod

gmbd vba

− vba + rssd

+ Vx

Ix

rbbd

RLeff

−

FIGURE 55.43 Equivalent circuit used to determine the effective load resistance RLeff presented to the enhancementmode driver by the depletion-mode load in the inverter of Fig. 55.41.

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Monolithic Device Models

approaches infinity if rol → ∞ and if λbl → 0. But rol → ∞ implies negligible channel length modulation, while λbl → 0 corresponds to the neglect of threshold body phenomena. These simplifying approximations are implicit to the plot of Fig. 55.42. b. If the internal series resistances are very small, and if the channel length modulation resistance is very large in both the load and driver transistors, RLeff ≈

1 λ bl g mfl

and Av ≈ −g mfa˙˙ RLeff The resultant voltage gain collapses to A v ≈ −

g mfd λ bl g mfl

c. A comparison of the approximate gain expression found above to the corresponding gain approximation for the enhancement-loaded inverter considered in Example 3 indicates that the gain afforded by the depletion-loaded inverter is slightly larger. In particular, if Ave and Avd , respectively, denote the approximate voltage gains of the enhancement-driven enhancementloaded inverter and the enhancement-driven depletion-loaded inverter,  1 + λ bl  Avd ≈   Ave  λ bl  Note once again that a tacit neglect of body effect yields infinitely large voltage gain magnitude in the depletion-loaded inverter.

References [1] D. A. Hodges, P. R. Gray, and R. W. Brodersen, “Potential of MOS technologies for analog integrated circuits,” IEEE J. Solid-State Circuits, vol. SC-13, pp. 285–294, June 1978. [2] D. A. Hodges and H. G. Jackson, Analysis and Design of Digital Integrated Circuits, New York: McGraw-Hill, 1983, pp. 49–52. [3] A. B. Glaser and G. E. Subak-Sharpe, Integrated Circuit Engineering: Design, Fabrication, and Applications, Reading, MA: Addison-Wesley, 1977, pp. 91–94. [4] D. E. Ward and R. W. Dutton, “A charge-oriented model for MOS transistor capacitances,” IEEE J. Solid-State Circuits, vol. SC-13, pp. 703–708, Oct. 1978. [5] S.-Y. Oh, D. E. Ward, and R. W. Dutton, “Transient analysis of MOS transistors,” IEEE J. SolidState Circuits, vol. SC-15, pp. 636–643, Aug. 1980. [6] B. J. Sheu, D. L. Scharfetter, C. Hu, and D. O. Pederson, “A compact IGFET charge model,” IEEE Trans. Circuits Syst., vol. CAS-31, pp. 745–748, Aug. 1984. [7] J. E. Meyer, “MOS models and circuit simulation,” RCA Review, vol. 32, pp. 42–63, Mar. 1971. [8] S. Liu and L. W. Nagel, “Small-signal MOSFET models for analog circuit design,” IEEE J. SolidState Circuits, vol. SC-17, pp. 983–998, Aug. 1982. [9] F. N. Tronfimenkoff, “Field-dependent mobility analysis of the field-effect transistor,” Proc. IEEE, vol. 53, pp. 1765–1766, Nov. 1965. [10] M. H. White, F. Van de Wiele, and J. P. Lambot, “High-accuracy MOS models for computer-aided design,” IEEE Trans. Electron Devices, vol. ED-27, pp. 899–906, May 1980. © 2003 by CRC Press LLC

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[11] P. E. Cottrell, R. R. Troutman, and T. H. Ning, “Hot electron emission in N-channel IGFET’s,” IEEE Trans. Electron Devices, vol. ED-26, pp. 520–523, April 1979. [12] K.-L. Chen et al., “Reliability effects on MOS transistors due to hot carrier injection,” IEEE Trans. Electron Devices, vol. ED-32, pp. 386–393, Feb. 1985. [13] T. H. Ning, C. M. Osborn, and H. N. Yu, “Effect of electron trapping on IGFET characteristics,” J. Electron. Mater., vol. 6, p. 65, 1977. [14] P. K. Chatterjee, “VLSI dynamic NMOS design constraints due to drain induced primary and secondary impact ionization,” IEDM Tech. Digest, p. 14, 1979. [15] T. Tsuchiya and S. Nakajima, “Emission mechanism and bias-dependent emission efficiency of photons induced by drain avalanche in Si MOSFET,” IEEE Trans. Electron Devices, vol. ED-32, pp. 405–412, Feb. 1985. [16] J. R. Brews et al., “Generalized Guide for MOSFET Miniaturization,” IEEE Electron Dev. Lett., vol. EDL-1, p. 2, 1980. [17] C.-Y. Wu, W.-Z. Hsiao, and H.-H. Chen, “A simple punchthrough voltage model for short-channel MOSFETs with single channel implantation in VLSI,” IEEE Trans. Electron Devices, vol. ED-32, pp. 1704–1707, Sep. 1985. [18] C. G. Sodini, P. K. Ko, and J. L. Moll, “The effect of high fields on MOS devices and circuit performance, IEEE Trans. Electron Devices, vol. ED-31, pp. 1386–1393, Oct. 1984. [19] R. R. Troutman, Latchup in CMOS Technology: The Problem and Its Cure, Boston: Kluwer Academic, 1986. [20] M.-W. Chiang, J. Choma, Jr., and C. Kao, “A simulation method to completely model the various transistor I-V operational modes of long channel depletion MOSFETs,” IEEE Trans. ComputerAided Design, vol. CAD-4, pp. 322–328, July 1985.

55.3 JFET Technology Transistors Stephen I. Long Both the MOSFET and the junction FET or JFET are used in analog IC design, usually in conjunction with bipolar transistors. In this section, the mechanisms responsible for the operation of the JFET will be described, models presented, and fabrication technologies discussed. Performance of integrated and discrete silicon JFETs are compared with each other and with compound semiconductor FET devices.

Introduction The JFET consists of a conductive channel with source and drain contacts whose conductance is controlled by a gate electrode. The channel can be fabricated in either conductivity type, n or p, and both normally on (depletion-mode-type devices) and normally off (enhancement-mode-type) devices are possible. The circuit symbols typically used for JFETs are shown in Fig. 55.44 along with the bias polarities of active region operation for these four device possibilities. For analog circuit applications, the depletion mode is almost exclusively utilized because it provides a larger range of input voltage and therefore greater dynamic range. In silicon, both p- and n-channel JFETs are used, but when compound semiconductor materials such as GaAs or InGaAs are used to build the FET, n-channel devices are used almost exclusively. When fabricated with silicon, the JFET is used in analog IC processes for its high input impedance, limited by the depletion capacitance and leakage current of a reverse-based pn junction. When the JFETs are used at the input stage, an op-amp with low input bias current, at least at room temperature, can be built. Fortunately, a p-channel JFET can be fabricated with a standard bipolar process with few additional process steps. This enables inexpensive BiFET processes to be employed for such applications. Unfortu­ nately, the simple process modifications required for integrating JFETs and BJTs are not consistent with the requirements for high-performance devices. Short gate lengths and high channel doping levels are generally not possible. So the transconductance per channel width and the gain–bandwidth product of © 2003 by CRC Press LLC

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Monolithic Device Models

VDS

n-channel depletion

n-channel enhancement

p-channel enhancement

p-channel depletion

VGS

FIGURE 55.44 The circuit symbols typically used for JFETs are shown with the bias polarities for active region operation.

JFETs integrated with a traditional analog BJT process are not very good. The short-circuit current gain–bandwidth product (fT) is about 50 MHz for an integrated p-channel JFET. The MOSFETs in a BiCMOS process are much better devices, however a BiCMOS process does not often include both NPN and PNP BJTs needed for high-performance analog circuits. Discrete silicon JFET’s are available with much better performance because they can be fabricated with a process optimized for the JFET. Typical applications are for low-noise amplifiers up to the VHF/UHF range. Noise figures less than 0.1 dB can be obtained at low frequencies with high source impedances and 2 dB at high frequencies at the noise matching input condition with high-performance discrete silicon JFETs. The low input gate current IG, which can be in the picoamp range, causes the shot noise (proportional to 1 G ) component to be very low. The input equivalent noise current of the JFET is mainly due to input referred channel (Johnson) noise. This property gives very low noise performance when presented with a high source impedance. In this case, the JFET is often superior to a BJT for noise. For low source impedances, the BJT is generally better. Compound semiconductor materials such as GaAs and InGaAs are used to fabricate JFET-like devices called MESFETs (metal-semiconductor FET) and HEMTs (high electron mobility transistor). The reason for using these materials is superior performance at high frequencies. These devices are unequaled for gain — bandwidth, ultralow noise, and power amplification at frequencies above 10 GHz and up to 200 GHz. Integrated analog microwave circuits are fabricated with these devices and are commercially available for use in low noise receiver and power amplifier applications. Some representative results will be summarized in the section on GaAs MESFET and HEMT technologies.

JFET Static I–V Characteristics The JFET differs in structure and in the details of its operation from the MOSFET discussed in the previous section. Figure 55.45 shows an idealized cross section of a JFET. The channel consists of a doped region, which can be either p or n type, with source and drain contacts at each end. The channel is generally isolated from its surrounding substrate material by a reverse biased pn junction. The depletion regions are bounded in Fig. 55.45 by dashed lines and are unshaded. The thin, doped channel region forms a resistor of width W into the page and height d. A gate electrode is located at the center of the channel, defined by a semiconductor region of opposite conductivity type of length L. An n-channel structure is shown here for purposes of illustration. The p-type gate constricts the channel, both through the depth of the diffusion or implant used to produce the gate and through the depletion layer formed at the p–n junction. The height of the channel can be varied by biasing the gate relative to the source © 2003 by CRC Press LLC

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L S

G

D p n d p

FIGURE 55.45 Idealized cross section of a JFET. The depletion regions are bounded with dashed lines and are unshaded.

(VGS). A reverse bias increases the depletion layer thickness, reducing the channel height and the drain current. If VGS is large enough that the channel is completely depleted, the drain current will become very small. This condition corresponds to the cutoff and subthreshold current regions of operation, and the VGS required to cutoff the channel is called VP , the pinchoff voltage. VP corresponds to the threshold voltage that was defined for the MOSFET. Similarly, a forward bias between gate and channel can be used to increase drain current, up to the point where the gate junction begins to conduct. Most JFETs are designed to be depletion mode (normally on); drain current can flow when VGS = 0 and they are normally operated with a reverse-biased gate junction. It is also possible, however, to fabricate enhancementmode JFETs by use of a thinner or more lightly doped channel. The pinchoff voltage is a sensitive function of the doping and thickness of the channel region. It can be found through Poisson’s equation if the channel doping profile N(x) is known. For a nonuniform profile, VP = VBI −

q ε

d

∫0 xN (x )dx

(55.133)

For uniform doping, N(x) = ND and the familiar result in (55.134) shows that the pinchoff voltage depends on the square of the thickness. This result shows that very precise control of profile depth is needed if good matching and reproductibility of pinchoff voltage is to be obtained [11]. VP = VBI −

qN Dd 2 2ε

(55.134)

JFET Operating Regions The static current–voltage characteristics of the JFET can be categorized by the five regions of operation shown in Fig. 55.46 for an n-channel device. The mechanisms that produce these regions can be quali­ tatively understood by referring to the channel cross sections in Fig. 55.47. In these figures, the doped channel region is shaded, and the depletion region is white. First, consider the JFET in Fig. 55.47(a) with small VDS (VGS – VP). This condition corresponds to the ohmic region (sometimes called linear or triode region) where current and voltage are linearly related. At small drain voltages, the depletion layer height is nearly uniform, the electric fields in the channel are too small to saturate the carrier velocity, and thus the channel behaves like a linear resistor. The resistance can be varied by changing VGS. The channel height is reduced by increasing the reverse bias on the gate leading to an increased resistance. As VDS increases, the depletion layer thickness grows down the length of the channel, as shown in Fig. 55.47(b). This occurs because the drain current causes a voltage increase along the channel as it flows through the channel resistance. Since the depletion layer thickness is governed by the gate-to-channel voltage (VGC), there is an increasing reverse bias that leads to constriction of the channel at the drain end of the gate. Ideally, when VDS = VGS – VP , then VGC = VP , and the channel height will approach zero (pinchoff). The constricted channel will cause the drain current to saturate as shown. Further increases © 2003 by CRC Press LLC

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Monolithic Device Models

ID

VGS > VT

ohmic region

pinchoff region

subthreshold region

VDS

VDsat inverse

region

VGS = VT

cutoff

FIGURE 55.46 The static current–voltage characteristic of the JFET can be categorized by five regions of operation. An n-channel device is shown in this illustration with grounded source.

in VDS do not cause the drain current to increase since the channel has already constricted to a minimum height and the additional potential is accommodated by lateral extension of the depletion region at the drain end of the gate. This region of operation is generally described as the pinchoff region (rather than the saturation region in order to avoid confusion with BJT saturation). The height of the channel is not actually zero but is limited by the mobile channel charge, which travels at saturated drift velocity in this high field region. If VGS < 0, then the initial channel height at the source is reduced, ID is less, and the pinchoff region occurs at a smaller drain voltage VDS = VGS – VP . The saturation of drain current can also occur at smaller VDS if the gate length is very small. In this case, the electric field in the channel is large, and the carrier velocity will saturate before the channel can reach pinchoff. Velocity saturation will also limit drain current. The subthreshold region of operation, shown in Fig. 55.47(c) is defined when small drain currents continue to flow even though VGS ≤ VP . While technically this gate bias should produce cutoff, some small fraction of the electrons from the source region will have sufficient energy to overcome the potential barrier caused by the gate depletion region and will drift into the drain region and produce a current. Since the energy distribution is exponential with potential, the current flow in this region varies expo­ nentially with VGS . The inverse region occurs when the polarity of the drain bias is reversed. This region is of little interest for the JFET since gate-to-drain conduction of the gate diode limits the operation to the linear region only. Channel Length Modulation Effect A close look at the I–V characteristic in the pinchoff region shows that the incremental conductivity or slope of this region is not equal to zero. There is some finite slope that is not expected from the simple velocity saturation or pinchoff models. Channel length modulation is one explanation for this increase; the position under the gate where pinchoff or velocity-saturation first occurs moves toward the source as VDS increases. This is due to the expansion of the drain side depletion region at large VDS . Figure 55.48 illustrates this point. Here, a channel cross section is shown for VDS = VGS – VP in Fig. 55.48(a) and for VDS  VGS – VP in Fig. 55.48(b). While pinchoff always occurs when the gate-to-channel voltage is VP , the higher drain voltage causes the location of this point (L) to move closer to the source end of the channel (L′). Since the electric field in this region E is roughly proportional to (VGS – VP)/L where L is now a function of VDS and VGS , then the current must increase as the channel length decreases due to increasing carrier velocity (v = µE). If the channel length is short, velocity saturation may cause the drain current to saturate. In this case, the velocity saturation point moves closer to the source as drain voltage © 2003 by CRC Press LLC

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−+

VDS 0

−+ S

VGS

G

D

VGS = 0

(a)

VGS < 0 VGS = VP VDS VDS = VGS − VP −+

VGS > 0

ID

−+ S

VGS

VGS = 0 G

D VGS < 0

(b)

VGS = VP VDS VDS = VGS − VP −+ −+ S

VGS < VP

log ID G

VDS > |VP|

D

VDS = 0

(c)

VGS

VP

FIGURE 55.47 (a) Ohmic region with small VDS(VGS – VP). (b) When VDS = VGS – VP , the channel height will become narrow at the drain end of the gate. The device enters pinchoff. The constricted channel will cause the drain current to saturate as shown. (c) Cutoff and subthreshold current regions occur when the depletion region extends through the channel.

(a)

(b)

L

L′

FIGURE 55.48 A channel cross section is shown for VDS = VGS – VP in (a) and for VDS  VGS – VP in (b). While pinchoff always occurs when the gate-to-channel voltage is VP , the higher drain voltage causes the location of this point (L) to move closer to the source end of the channel (L′). © 2003 by CRC Press LLC

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Monolithic Device Models

ID0.5 VDS > VGS − VP compensation of temperature drift

low T high T

FIGURE 55.49 Effect of temperature on the drain current in the pinchoff region.

VGS

is increased. Since the length has decreased, less gate-to-channel voltage is needed to produce the critical field for velocity saturation. Less voltage implies a wider channel opening, hence more current. Temperature Effects Two mechanisms influence the drain current of the JFET when temperature is changed [4], [12]. First, the pinchoff voltage becomes more negative (for n-channel) with increase in temperature, therefore requiring lower VGS to cut off the channel or to enter the pinchoff region. Therefore, when the device is operating in the pinchoff region, and VGS – VP is small, the drain current will increase with temperature. This effect is caused by the decrease in the built-in voltage of the gate-to-channel junction with increasing temperature. Second, the carrier mobility and saturated drift velocity decreases with temperature. This causes a reduction in drain current that is in opposition to the first effect. This effect dominates for large VGS – VP . Therefore, there is a VGS value for which the drain current is exactly compensated by the two effects. This is illustrated qualitatively in Fig. 55.49. The gate current is also affected by temperature, as it is the reverse current of a pn junction. The current increases roughly by a factor of 2 for each 10°C increase in temperature. At high temperatures, the input current of a JFET input stage may become comparable to that of a well-designed BJT input stage of an op-amp, thus losing some of the benefit of the mixed BJT–JFET circuit design.

JFET Models Most applications of the JFET in Analog ICs employ the pinchoff region of operation. It is this region, that provides power gain and buffer (source follower) capability for the device, so the models for the JFET presented next will concentrate on this region. It will also be assumed that the gate–source junction will not be biased into forward conduction. Although forward conduction is simple to model using the ideal diode equation within the FET equivalent circuit models, this bias condition is not useful for the principal analog circuit applications of the JFET and will also be avoided in the discussion that follows. Large-Signal Model: Drain Current Equations Equations modeling the large signal JFET ID – VGS characteristic can be derived for the two extreme cases of FET operation in the pinchoff region. A gradually decreasing channel height and mobility limited drift velocity in the channel are appropriate assumptions for very long gate length FETs. A fixed channel height at pinchoff with velocity saturation limited drift velocity are more suitable for short gate lengths. The square-law transfer characteristic [2] given by (55.135) provides a good 2

 V  I D = I DSS 1 − GS  (1 + λVDS ) VP  

(55.135)

approximation to measured device characteristics in the case of long gate length (>5 µm) or very low electrical fields in the channel (VGS – VP)/L < Esat. In both cases, the channel height varies slowly and the © 2003 by CRC Press LLC

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ID

−1/λ

VDS

FIGURE 55.50 The channel length modulation parameter λ is defined by the extrapolation of the drain current in saturation to ID = 0.

velocity remains proportional to mobility. Esat is the critical field for saturation of drift velocity, about 3.5 kV/cm for GaAs and 20 kV/cm for Si. IDSS is defined as the drain current in the pinchoff region when VGS = 0. The first two terms of the equation are useful for approximate calculation of dc biasing. The third term models the finite drain conductance caused by the channel length modulation effect. The parameter λ in this term is derived from the intercept of the drain current when extrapolated back to zero as shown in Fig. 55.50. Equation (55.135) is also used to represent the pinchoff region in the SPICE JFET model. It is parameterized in a slightly different form as shown below in (55.136).

(

I D = β VGS, i − VT 0

) (1 + λV 2

DS

)

(55.136)

These equations are the same if VT0 = VP , and β=

I DSS VP2

VGS, i = VGS − I D RS

(55.137)

VDS, i = VDS − I D RS − I D RD The pinchoff region is defined for VDS, i ≥ VGS,i – VT0 as is usual for the gradual channel approximation. RS and RD are the parasitic source and drain resistances associated with the contacts and the part of the channel that is outside of the gate junction. These resistances will reduce the internal device voltages below the applied terminal voltages as shown in (55.137). For shorter gate length devices, improved models have been proposed and implemented in SPICE3 and some of the many commercial SPICE products, often in the MESFET model. The Raytheon or Statz model [10] is frequently used for this purpose. This model modifies the drain current dependence on VGS by adding a velocity saturation model parameter b in the denominator as shown in (55.138).

(

) (1 + λV ) ) 

 β V −V 2 GS , i T0 I D =  1 + b VGS, i − VT 0 

(

DS , i

(55.138)

This added term allows the drain current to be nearly square law in VGS for small VGS – VT0, but it becomes almost linear when VGS is large, effectively emulating the rapid rise in transconductance followed by saturation that is typical in short channel devices. Although the specific behavior of the drain current is sensitive to the vertical doping profile in the channel [15], (55.138) is flexible enough to accommodate most short channel device characteristics with uniform or nonuniform channel doping. Another feature of short gate length FET’s that this model predicts adequately is a saturation of ID at VDS, i < VGS, i – VT0. © 2003 by CRC Press LLC

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Monolithic Device Models

10 1.3

1/L

8

1.6 2

gm (mS)

6

measurement

4 5 2

20

10

0 0.0

0.2

0.4

0.6

0.8

1/L (µm−1)

FIGURE 55.51 Plot of transconductance vs. 1/L. The gate length L is varied over the range of 1.3 to 20 µm (lengths shown next to data points). 1/L scaling is observed for gate lengths greater than 5 µm.

This early transition into the pinchoff region is also a consequence of velocity saturation and is widely observed. Width and Length Scaling Classical FET theory suggests that the drain current should scale linearly with channel width W and inversely with gate length L. In practice, this applies adequately for JFETs with long gate lengths (L ≥ 5 µm) and wide channels (W ≥ 5 µm) but breaks down below these approximate dimensions. In the case of the width, the drain current of a narrow channel JFET will be larger than expected by a linear scaling due to the lateral diffusion that occurs during implantation or diffusion. The channel may be wider than the mask dimension by possibly 0.5 µm for this reason. If the process design rules allow use of very narrow channels, experimental data should be used to determine the effective channel width. Scaling of drain current with gate length is less straightforward. For very short gate lengths, at the limit of velocity saturation, no increase in drain current is predicted by (55.139) unless the channel depth d is also scaled. An increase in channel doping is required to reduce d. Since channel doping in a given process is constant, the drain current will scale less sensitively than 1/L if gate lengths below 5 µm are used. This effect is illustrated in Fig. 55.51 for a GaAs MESFET, a type of JFET to be described in the section on JFET technologies, where the transconductance is plotted against 1/L. The gate length L is varied over the range of 1.3–20 µm (lengths shown next to data points). 1/L scaling is observed for gate lengths greater than 5 µm. β =

εv satW d

(55.139)

In practice, data measured on devices covering a range of L is needed in order to predict length scaling accurately. Note that the SPICE2 or SPICE3 JFET and MESFET models do not attempt to scale device parameters for gate length, so the length scaling must be accomplished manually through use of parameter sets optimized for each length. Device Capacitances There will be capacitances associated with the pn junctions comprising the JFET. Figure 55.45 shows that are junctions between the gate and channel and between the channel and substrate. In addition, for some silicon JFET devices as discussed in the section on JFET technologies, there will also be a junction between the gate and substrate. Each of these capacitances are voltage dependent and should be considered in a device model if it is to be accurate at high frequencies. The gate-to-channel capacitance is split into two components, a gate-to-source capacitance Cgs and a gate-to-drain capacitance Cgd . The VGS and VGD dependence of these capacitances is often approximated by the depletion capacitance of a pn junction; eqs. (55.140) and (55.141) are typically used to predict variation of capacitance in the indicated bias range. For VGS < VP the capacitance rapidly drops to a small © 2003 by CRC Press LLC

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value limited by parasitic capacitances and is insensitive to either VGS or VDS . VBI is the apparent builtin voltage of the junction. In some models, the parameter m is made adjustable to accommodate nonuniform doping profile effects. Typically, m = 0.5 is used to represent a uniformly doped channel. C gso

C gs =

(1 − VGS

(55.140)

VBI )

m

C gdo

C gd =

(1 − VGD

(55.141)

VBI )

m

While this model is severely in error in the linear region [6], if operation of the device is limited to the pinchoff region it can provide an adequate prediction. For the GaAs MESFET, Cgd will be of the order of 15 percnt of the total gate capacitance; Cgs about 85 percent. For the SI JFET, Cgd is about 25 percent; Cgs is about 75 percent. This formulation is found in both the SPICE JFET and MESFET models; however, the MESFET model implementation [10] includes the pinchoff effects and is considerably more accurate in the linear region. The parasitic gate-to-substrate capacitance Cgss found certain Si JFET technologies can also be modeled by functions like (55.140) or (55.141). However, it is not included explicitly as part of the SPICE JFET model. If it is necessary, the diode model can be used to simulate Cgss by connecting an external diode from gate-to-substrate. Small-Signal Model The small-signal model for the JFET in the pinchoff region is shown in Fig. 55.52. The voltage-dependent current source models the transconductance gm as a constant that can be derived from the drain current equations above from gm =

∂I D ∂VGS

(55.142)

The square-law current model (55.135) predicts a linearly increasing gm with VGS gm = −

2I DSS  VGS  1− VP  VP 

(55.143)

whereas a model that includes some velocity saturation effects such as (55.138) would predict a saturation in gm .

���

�

��

+

����

���

���

�� ���

−

���

�� � FIGURE 55.52 The small-signal model for the JFET in the pinchoff region. © 2003 by CRC Press LLC

�

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1549

Monolithic Device Models

The small-signal output resistance r0 models the channel length modulation effect. This is also derived from the drain current equations through r0−1 =

∂I D ∂VDS

(55.144)

1 I Dλ

(55.145)

For both models, r0 is determined by r0 =

The small-signal values of the nonlinear, voltage dependent Cgs , Cgd , and Cgss are also shown in Fig. 55.52. Parasitic source and drain resistances RS and RD can also be included, as shown. If they are not included in the small-signal model, the effect of these parasitics can sometimes be produced in the intrinsic FET model by reducing the intrinsic gm of the device. The short-circuit current gain–bandwidth product fT defined in (55.146) is a high-frequency figure of merit for transistors. It is inversely proportional to the transit time τ of the channel charge, and it is increased by reducing the gate length. Reduced L also reduces the gate capacitance and increases transcon­ ductance. The FET channel material also affects fT as higher drift velocity leads to higher gm . fT =

(

gm

2π C gss + C gs + C gd

)

=

1 τ

(55.146)

SPICE Model Parameter Summary In Tables 55.3 and 55.4, a brief summary of the basic set of parameters used in all SPICE JFET and MESFET models is provided. These parameters were defined in the section on the large-signal model. Note that some SPICE versions will include other parameters designed to improve the accuracy or versatility of the model. These parameters scale directly or inversely in channel width W for most implementations. If the gate length is changed, generally a new set of parameters extracted for the new gate length will be required. The parameters β, Cgso , Cgdo , and IS scale directly with W and RS , RD inversely. Other parameters are not affected by width to the first order.

JFET Technologies The IC fabrication technology used to make JFETs depends primarily on the material. Discrete Si JFETs are available that provide fT above 500 MHz and very low input rms noise currents through optimizing the channel design and minimizing parasitic capacitances, resistances, and gate diode leakage currents. However, a silicon IC process is rarely designed to optimize the performance of the JFET; rather, the JFET is made to accommodate an existing bipolar process with as few modifications as possible [2]. Then, the extra circuit design flexibility and performance benefits of a relatively inexpensive mixed FET/BJT process (often called BiFET) can be obtained with small incremental cost. On the other hand, gallium arsenide IC processes exist only for the improved performance that is possible with these devices. Thus, the process technology is carefully designed to optimize device performance for bandwidth, noise, or power and to minimize the parasitic capacitances and inductances associated with passive components [9]. Silicon JFET Technologies In principle, it would be possible to build p-channel Si JFETs in a standard analog BJT process without additional mask steps if the base diffusion has suitable doping and thickness to give a useful pinchoff voltage when overlaid with the emitter diffusion. Unfortunately, this is usually not the case, since the emitter diffusion is too shallow, and the pinchoff voltage resulting from this approach would be too high (positive © 2003 by CRC Press LLC

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TABLE 55.3 Summary of SPICE JFET Model Parameters and Typical Values for a p-Channel Ion-Implanted Si JFET with W/L = 25 [2] Parameter Pinchoff voltage (VP) Transconductance coefficient (β) Channel length modulation (λ) Zero-bias GS junction capacitance (Cgso) Zero-bias GD junction capacitance (Cgdo) Zero-bias GB junction capacitance (Cgss) Junction grading coefficient (GS and GD) Junction grading coefficient (GB) Gate junction built-in voltage (VBI) Gate junction saturation current (IS)

Units

Typical Value

Volts Amps/Volt2 Volt–1 Farad Farad Farad — — Volt Amp

1.0 3.0e-4 –0.01 2e-12 2e-12 4e-12 0.33 0.5 0.5 1e-10

TABLE 55.4 Summary of SPICE MESFET Model Parameters and Typical Values for a 1 µm Gate Length GaAs MESFET Normalized to a 1 µm Channel Width [6] Parameter Pinchoff voltage (VP) Transconductance coefficient (β) Doping tail extending parameter (b) Channel length modulation (λ) Saturation voltage parameter (α) Source resistance (RS) Drain resistance (RD) Zero-bias GS junction capacitance (Cgso) Zero-bias GD junction capacitance (Cgdo) Gate junction built-in voltage (VBI) Gate junction saturation current (IS)

G

p base diffusion and JFET channel S

p substrate

n+ subcollector diffusion

Units

Typical Value

Volts Amps/Volt2 Volt–1 Volt–1 Volt–1 Ohm Ohm Farad Farad Volt Amp

–1.0 1.0e-4 0.3 0.05 2.5 900 900 1.2e-15 2.8e-15 0.8 5e-16

n+ gate diffusions D

n collector diffusion & lower gate

FIGURE 55.53 Cross section of a double diffused silicon JFET (not to scale).

in the case of the p-channel device). Therefore, the channel of the JFET must be made thinner either through the use of an additional diffusion or by providing the channel and gate with ion implantations. The double diffused JFET process was the earliest approach to be used, since the channel depth could be reduced through the use of only one additional diffusion step. A cross-sectional view is shown in Fig. 55.53. Here, the depth of the gate diffusion is extended by an extra predeposition and drive-in diffusion step carried out prior to the emitter diffusion steps. Therefore, a narrower base region is obtained allowing the pinchoff voltage of the JFET to be independent of the requirements of the BJT. While this © 2003 by CRC Press LLC

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Monolithic Device Models

������ ������� ������� � ���� ���������

�

�+ ������� ���������

� ���� �������

�

�

� ��������� ��������� � ����� ����

� ���������

FIGURE 55.54 Cross section of an ion implanted silicon JFET (not to scale).

simple process modification is inexpensive to implement, the absolute control and matching of pinchoff voltage is not accurate enough for low input offset voltage in JFET differential amplifier pairs. In addition, the forced compatibility with the BJT process requires use of the collector layer under the channel. This forms a lower gate electrode that is by necessity less heavily doped than the channel. Therefore, the depletion region at this interface extends primarily into the gate, and the lower gate is rather ineffective in contributing to the total transconductance of the JFET. It does add the parasitic capacitance Cgss to the device at the collector to substrate junction, limiting frequency response. Finally, due to the relatively high base doping level, the drain breakdown voltage is low. Because of the performance compromises inherent in this approach, it has been largely superceded by the ion implantation method. Figure 55.54 illustrates the cross section of an ion-implanted JFET. In order to gain better control of the pinchoff voltage and transconductance, both the channel and the gate are formed by ion implantation. This allows use of a channel that is more lightly doped than the base diffusion enabling the collector “gate” layer to more effectively contribute to the transconductance of the device. In addition, the predeposition of channel and gate charge is much more repeatable with ion implantation, so device matching and reproducibility of pinchoff voltage is greatly improved. The fT will be improved by the larger gm per unit width and the slightly reduced gate capacitances, and the drain breakdown voltage will be increased as is often needed for an analog IC process. However, low channel doping is not a good recipe for a high-frequency transistor with short gate length, so the fT of these devices is still only 50 MHz or so. GaAs MESFET and HEMT Technologies High-performance GaAs MESFET devices are constructed with a metal-semiconductor junction gate instead of a diffused or implanted pn junction gate. The metal gate forms a Schottky barrier diode directly on an n-type channel as shown in Fig. 55.55 and allows the channel height to be varied in the same manner as the JFET. No gate dielectric or diffusion is necessary. The channel is formed either by ion implantation of an n-type dopant into a high resistivity (semiinsulating) GaAs substrate or a lightly

Ohmic contact metal

Schottky barrier Gate S

G

n channel implant D

Semi-insulating GaAs substrate n+ source/drain implant

FIGURE 55.55 Cross section of a GaAs MESFET (not to scale). © 2003 by CRC Press LLC

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Drift Velocity (×106 cm/s)

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The Circuits and Filters Handbook, Second Edition

3 InGaAs GaAs Si

2

1

0 0

10 Electric Field (kV/cm)

20

FIGURE 55.56 Electron velocity vs. electric field for InGaAs (53% In) [5], GaAs [8], and Si [3].

p-type substrate or by growth of the channel region with molecular beam epitaxy. These MESFETs are used as the primary active device in analog microwave and mm-wave monolithic integrated circuits (sometimes called MMICs). Since analog MESFET circuits are used for low noise, wide bandwidth, or high power amplification up to 50 GHz, gate lengths are often quite small; 0.25 µm is not unusual. The high performance of these devices comes through a combination of factors. First, the mobility and saturated drift velocity of n-GaAs are five times and two times larger than n-Si, respectively. In addition, the peak drift velocity is reached at much lower electric field for GaAs [8] as illustrated in Fig. 55.56. The parasitic substrate capacitance is quite small due to the high resistivity provided by semiinsulating GaAs. These factors lead to a much higher fT (20–50 GHz) and lower parasitic resistances (fmax) at lower operating voltages for the GaAs MESFET than the Si JFET. These are desirable qualities for high performance microwave circuits, and the high electron velocity at low bias voltage can lead to reduced power as well. Also, patterning submicrometer gate lengths with metal or silicide gate materials is relatively straightfor­ ward, and gate resistance can be reduced through plating thick gate stripes with mushroom cross sections. Passive interconnections can have low losses through the use of plated air bridge interconnections suspended over the surface of the MMIC, and plated-through substrate vias can be fabricated when needed to reduce parasitic inductances. MESFET MMICs are available commercially from several sources. Custom MMIC design and fabri­ cation can also be supported by several GaAs IC foundries. Further reduction in noise figure and increase in bandwidth has been demonstrated by the use of heterojunction MESFETs, sometimes called HEMT’s (high electron mobility transistors) or P-HEMTs (pseudomorphic HEMTs). This device achieves its improved performance mainly through the high mobility, undoped InGaAs channel material. The electron velocity versus electric field of In0.53Ga0.47 As is compared with GaAs and Si in Fig. 55.56, where it can be seen that higher drift velocity is obtained in In0.53Ga0.47 As [5] than either GaAs [8] or Si [3]. The higher the In concentration in the InGaAs, the higher the mobility and velocity and the lower the noise. InGaAs cannot be lattice matched to GaAs substrates, but about 20 percent In can be tolerated if the InGaAs channel is very thin. In this case, the mismatch is accommodated by elastic strain rather than by the formation of lattice defects. This strained condition is called pseudomorphic: a forced lattice match due to elastic strain. When grown on InP semiinsulating substrates, much higher In concentration can be used in the channel (53%) under latticematched conditions, and even more In is possible when pseudomorphic growth conditions are used. In addition, the channel layer is confined between higher bandgap regions (InAlAs) as illustrated in Fig. 55.57. The confinement provided by these energy barriers provides large channel electron sheet concentrations, also improving gm . Finally, the gate barrier heterojunction also enables good Schottky gate characteristics to be obtained even though the channel material itself has a low bandgap and would otherwise provide a poor barrier height if the metal were in direct contact. Excellent performance of HEMT or P-HEMT devices and MMICs at microwave and millimeter wave frequencies has been reported. Table 55.5 summarizes some representative results. © 2003 by CRC Press LLC

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Monolithic Device Models

G S

D

InGaAs contact InAIAs barrier Si planar doping InAIAs spacer InGaAs (undoped) channel InAIAs (undoped) Superlattice buffer S.I. InP substrate

FIGURE 55.57 Cross section of a heterostructure FET (not to scale).

TABLE 55.5

Summary of Performance of HEMT and P-HEMT Devices and MMICs.

Device Technology InP P-HEMT (Discrete MIC) (three-stage MMIC) InP HEMT (Distributed amplifier) GaAs P-HEMT (two-stage MMIC)

Frequency (GHz)

NF (dB)

G (dB)

Reference

95 141 94 5–100

1.3 7.3 3.5

8.2

[1]

21 5.5

[13] [7]

112–115

5.5

10

[14]

Note: G refers to the power gain associated with the frequency, noise, or wide band condition cited.

References [1] P. D. Chow, K. Tan et al., “W-band and D-band low noise amplifiers using 0.1 micron pseudomor­ phic InAlAs/InGaAs/InP HEMT’s,” IEEE MTT Symp., Albuquerque, NM, 1992. [2] P. R. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits, New York: Wiley, 1993. [3] C. Jacobini, C. Canali et al., “A review of some charge transport properties of silicon,” Solid-State Electron, vol. 20, pp. 77, 1977. [4] S. J. Lee and C. P. Lee, “Temperature effect on low threshold voltage ion-implanted GaAs MESFET’s,” Electron. Lett., vol. 17, no. 20, pp. 760–761, 1981. [5] M. A. Littlejohn, K. W. Kim et al., “High-field transport in InGaAs and related heterostructures,” in Properites of Lattice-Matched and Strained Indium Gallium Arsenide. London: Inspec, IEE, 1993, pp. 107–116. [6] S. I. Long and S. E. Butner, Gallium Arsenide Digital Integrated Circuit Design. New York: McGrawHill, 1990. [7] R. Majidi-Ahy, C. Nishimoto et al., “5-100 Ghz InP coplanar waveguide MMIC distributed ampli­ fier,” IEEE Trans. Microwave Theory Tech., vol. 38, pp. 1986–1991, Dec. 1990. [8] F. Pozela and A. Reklaitis, “Electron transport properties in GaAs at high electric fields,” Solid-State Electron, vol. 23, pp. 927–933, 1980. [9] R. A. Pucel, “Design considerations for monolithic microwave circuits,” IEEE Trans. Microwave Theory Tech., vol. 29, pp. 513–534, June 1981. [10] H. Statz, P. Newman et al., “GaAs FET device and circuit simulation in SPICE,” IEEE Trans. Electron, vol. 34, pp. 160–169, Feb. 1987. [11] S. M. Sze, Physics of Semiconductor Devices, New York: Wiley Interscience, 1981. [12] G. W. Taylor, H. M. Darley et al., “A Device Model for an Ion-Implanted MESFET.” IEEE Trans. Electron, vol. ED-26, pp. 172–179, 1979. © 2003 by CRC Press LLC

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[13] H. Wang, T. Ton et al., “An ultralow noise W-band monolithic three-stage amplifier using 0.1 µm pseudomorphic InGaAs/GaAs HEMT technology,” IEEE MTT Symp., Albuquerque, NM, 1992. [14] H. Wang, T. Ton et al., “A D-band monolithic low noise amplifier,” IEEE GaAs IC Symp., Miami Beach, FL, 1992. [15] R. E. Williams and D. W. Shaw, “Graded channel FET’s: Improved linearity and noise figure,” IEEE Trans. Electron, vol. 25, pp. 600–605, June 1978.

55.4 Passive Components Nhat M. Nguyen Resistors Resistors available in monolithic form are classified in general as semiconductor resitors and thin-film resistors. Semiconductor structures include diffused, pinched, epitaxial, and ion-implanted resistors. Commonly used thin-film resistors include tantalum, nickel–chromium (Ni–Cr), cermet (Cr–SiO), and tin oxide (SnO2). Diffused, pinched, and epitaxial resistors can be fabricated along with other circuit elements without any additional processing steps. Ion-implanted and thin-film resistors require additional processing steps for monolithic integration but offer lower temperature coefficient, smaller absolute value variation, and superior high-frequency performance. Resistor Calculation. The simplified structure of a uniformly doped resistor of length L, width W, and thickness T is shown in Fig. 55.58. The resistance is R=

1 L L  ρ L =  = R▫ σ WT  T  W W

(55.147)

where σ and ρ are conductivity and resistivity of the sample, respectively, and R▫ is referred to as the sheet resistance. From the theory of semiconductor physics, the conductivity of a semiconductor sample is

(

σ = q µ nn + µ p p

)

(55.148)

where q is the electron charge (1.6 × 10–19 Coulomb), µn (cm2/V · s) is the electron mobility, µp (cm2/V · s) is the hole mobility, n (cm–3) is the electron concentration, p (cm–3) is the hole concentration, and σ (Ω/cm)–1 is the electrical conductivity. For an n-type doped sample with a concentration ND (cm–3) of donor impurity atoms, the electron concentration n is approximately equal to ND . Given the mass-action law np = ni2, the conductivity of an n-type doped sample is approximated by  n2  σ = q µ nN D + µ p i  ≈ qµ nN D ND  

(55.149)

where ni (cm–3) is the intrinsic concentration. For a p-type doped sample, the conductivity is  n2  σ = q  µ n i + µ p N A  ≈ qµ p N A  NA 

(55.150)

where NA (cm–3) is the concentration of p-type donor impurity atoms. The sheet resistance of an n-type uniformly doped resistor is thus

© 2003 by CRC Press LLC

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Monolithic Device Models

L

T

W

N(x) Net impurity profile

x T

FIGURE 55.58 Simplified structure of a uniformly doped resistor.

  1 R▫ =   µ q N T  n D 

(55.151)

For an n-type nonuniformly doped resistor as shown in Fig. 55.59, where n-type impurity atoms are introduced into the p-type region by means of a high-temperature diffusion process, the sheet resistance [7] is  R▫ =  

∫

xj 0

 qµ nN D ( x )dx  

−1

(55.152)

where xj is the distance from the surface to the edge of the junction depletion layer. Measured values of electron mobility and hole mobility in silicon material as a function of impurity concentration are shown in Fig. 55.60 [4]. The resistivity ρ (Ω-cm) of n-type and p-type silicon as a function of impurity concentration is shown in Fig. 55.61 [12]. The sheet resistance depends also on temperature since both electron mobility and hole mobility vary with temperature [17]. This effect is accounted for by utilizing a temperature coefficient quantity that measures the sheet resistance variation as a function of temperature. A mathematical model of the temperature effect is

© 2003 by CRC Press LLC

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n-Type Doped Region, ND(x) p-Type Region

L

W

ND(x)

Net impurity profile

x dx

FIGURE 55.59 Simplified structure of an n-type nonuniformly doped resistor.

[

R▫ (T ) = R▫ (To ) (T − To )TC

]

(55.153)

where To is the room temperature and TC is the temperature coefficient. Diffused Resistors In MOS (metal-oxide-semiconductor) technology, the diffused layer forming the source and drain of the MOS transistors can be used to form a diffused resistor. In silicon bipolar technology, the available diffused layers are base diffusion, emitter diffusion, active base region, and epitaxial layer. Base Diffused Resistors. The structure of a typical base diffused resistor is shown in Fig. 55.62, where the substrate material is assumed of p-type silicon material. The diffused resistor is formed by using the p-type base diffusion of the npn transistors. The resistor contacts are formed by etching selected windows of the SiO2 passivation layer and depositing thin films of conductive metallic material. The isolation region can be formed with either a p-type doped junction or a trench filled with SiO2 dielectric material. © 2003 by CRC Press LLC

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Electron and Hole Mobility 1400 1300 1200 1100 1000 900

Electrons

800 700 600 Holes

500 400 300 200 100 0 1e+13

1e+14

1e+15

1e+16

1e+17

1e+18

1e+19

1e+20

Impurity Concentration

FIGURE 55.60 Electron and hole mobility vs. impurity concentration in silicon.

The pn junction formed by the p-type resistor and the n-type epitaxial (epi) layer must be reverse biased in order to eliminate the undesired dc current path through the pn junction. The impedance associated with a forward-biased pn junction is low and thus would also cause signficant ac signal loss. To ensure this reverse bias constraint the epi region must be connected to a potential that is more positive than either end of the resistor contacts. Connecting the epi region to a relatively higher potential also eliminates the conductive action due to the parasitic pnp transistor formed by the p-type resistor, the n-type epi region, and the p-type substrate. When the base diffused resistor is fabricated along with other circuit elements to form an integrated circuit, the epitaxial contact is normally connected to the most positive supply of the circuit. The resistance of a diffused resistor is given by (55.147), where the diffused sheet resistance is between 100 and 200 Ω/▫. Due to the lateral diffusion of impurity atoms, the effective cross-sectional area of the resistor is larger than the width determined by photomasking. This lateral or side diffusion effect can be accounted for by replacing the resistor width W by an effective width Weff, where Weff ≥ W. The resistance from the two resistor contacts must also be accounted for, especially for small values of L/W [3]. Basediffused resistors have a typical temperature coefficient between +1500 and +2000 ppm/°C. The maximum allowable voltage for the base-diffused resistor of Fig. 55.62 is limited by the breakdown voltage between the p-type base diffusion and the n-type epi. This voltage equals the breakdown voltage BVCBO of the collector-base junction of the npn transistor and typically causes an avalanche breakdown © 2003 by CRC Press LLC

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Resistivity

100 5 2 10 5 2 1

p-type

5

n-type

2 0.1 5 2 0.01 5 2 0.001 1e+14

1e+15

1e+16

1e+17

1e+18

1e+19

1e+20

Impurity Concentration

FIGURE 55.61 Resistivity of p-type and n-type silicon vs. impurity concentration.

mechanism across the base–epi junction. As the applied voltage approaches the breakdown voltage, a large leakage current flows from the epi region to the base region and can cause excessive heat dissipation. For analog integrated circuit applications where good matching tolerance between adjacent resistors is required, the resistor width should be made as large as possible. Base-diffused resistors with 50-µm resistor widths can achieve a matching tolerance of ± 0.2 percent. The minimum resistor width is limited by photolithographic consideration with typical values between 3 and 5 µm. Also, in order to avoid the self-heating problem of the resistor it is important to ensure a minimum resistor width for a given dc current level, with a typical value of about 3 µm for every 1 mA of current. With respect to high-frequency performance, the reverse-biased pn junction between the p-type base diffusion and the n-type epi contributes a distributed depletion capacitance which in turn causes an impedance roll-off at 20 dB/decade. This capacitance depends on the voltage applied across the junction and the junction impurity-atom dopings. For most applications the electrical lumped model as shown in Fig. 55.62 is adequate for characterizing this capacitive effect where the effective pn junction area is divided equally between the two diodes. Figure 55.63 shows a normalized impedance response as a function of the RC distributed stage. The frequency at which impedance value is reduced by 3 dB is given by

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Monolithic Device Models

Base Diffusion

Buried Layer

Isolation Emitter Diffusion

SiO2

Resistor Contact

Resistor Contact

p Diffusion

Epitaxial Contact n+

n Epitaxial n+

Buried Layer p Substrate

R

A/2

A/2

Epi Contact

FIGURE 55.62 p-type base-diffused resistor.

f −3 dB

 1   2π     1   2π  =   1   2π     1   2π 

2.0 RC 2.32 RC

N = 1 (Circuit model of Fig. 55.62) N =2 (55.154)

2.42 RC

N =3

2.48 RC

N=4

Emitter Diffused Resistors. Emitter-diffused resistors are formed by using the heavily doped n+ emitter diffusion layer of the npn transistors. Due to the high doping concentration, the sheet resistance can be as low as 2 to 10 Ω/▫ with a typical absolute value tolerance of ± 20 percent. Figure 55.64 shows an emitter-diffused resistor structure where an n+ diffusion layer is formed directly on top of the n-type epitaxial region and the ohmic contacts are composed of conductive metal thin films. Since the resistor body and the epi layer are both n-type doped, they are electrically connected in

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R/N

Z(jw)

C/(N+1)

First Stage

R/N

R/N

C/(N+1)

C/(N+1)

Epi Contact

Nth Stage

Second Stage

C/(N+1)

Z(dB)

0.0

−1.0

N=1 N=2

−2.0

N=3 N=4

−3.0

−4.0

−5.0

−6.0

−7.0

−8.0

−9.0

−10.0 0.0

1.0

2.0

3.0

4.0

5.0

6.0

Freq

FIGURE 55.63 Normalized frequency response of a diffused resistor for N = 1, 2, 3, 4. The epi contact and one end of the resistor are grounded.

parallel but the epi layer is of much higher resistivity due to its lower concentration doping, and thus the effective sheet resistance of the resistor structure is determined solely by the n+ diffusion layer. The pn junction formed between the p-type substrate and the n-type epi region must always be reverse biased, which is accomplished by connecting the substrate to a most negative potential. Because of the common n-type epi layer, each resistor structure of Fig. 55.64 requires a separate isolation region. Figure 55.65 shows another emitter diffused resistor structure where the n+ diffusion layer is situated within a p-type diffused well. Several such resistors can be fabricated in the same p-type well or in the same isolation region because the resistors are all electrically isolated. The p-type well and the n+ diffusion region form a pn junction that must always be reverse biased for electrical isolation. In order to eliminate the conductive action due to the parasitic npn transistor formed by the n-type resistor body, the p-type © 2003 by CRC Press LLC

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Monolithic Device Models

n+ Diffusion

Isolation

SiO2

Resistor Contact

n+ Diffusion

Resistor Contact

n Epitaxial p Substrate

R

Substrate

FIGURE 55.64 n-type emitter-diffused resistor I.

well, and the n-type epi, the junction potential across the well contact and the epi contact must be either short-circuited or reverse biased. The maximum voltage that can be applied across the emitter-diffused resistor of Fig. 55.65 is limited by the breakdown voltage between the n+ diffusion and the p-type well. This voltage equals the breakdown voltage BVEBO of the emitter–base junction of the npn transistor, with typical values between 6 and 8 V. Pinched Resistors The active base region for the npn transistor can be used to construct pinched resistors with typical sheet resistance range from 2 to 10 KΩ/▫. These high values can be achieved due to a thin cross-sectional area through which the resistor current traverses. The structure of a p-type base-pinched resistor is shown in Fig. 55.66, where the p-type resistor body is “pinched” between the n+ diffusion layer and the n-type epitaxial layer. The n+ diffusion layer overlaps the p-type diffusion layer and is therefore electrically connected to the n-type epi. In many aspects the base-pinched resistor behaves like a p-channel JFET, in which the active base region functions as the p channel, the two resistor contacts assume the drain and source, and the n+ diffusion and the epi constitute the n-type gate. When the pn junction formed between the active base and the surrounding n+ diffusion and n epi is subject to a reverse bias potential, the carrier-free depletion region increases and extends into the active base region, effectively reducing the resistor cross section and consequently increasing the sheet resistance. Since the carrier-free depletion region varies with reverse bias potential, the pinched resistance is voltage controlled and is nonlinear. Absolute values for the base-pinched resistors can vary as much as ±50 percent due to large process variation in the fabrication of the active base region. The maximum voltage that can be applied across the base-pinched resistor of Fig. 55.66 is restricted by the breakdown voltage between the n+ diffusion layer and the p-type base diffusion. The breakdown voltage has a typical value around 6 V. © 2003 by CRC Press LLC

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Base Diffusion

Isolation

n+ Diffusion

p Diffusion Resistor Contact

Resistor n+ Diffusion Contact

p Well Contact

Epitaxial Contact

SiO2

n+ n Epitaxial p Substrate

R

p-Well Contact

FIGURE 55.65 n-type emitter-diffused resistor II.

Epitaxial Resistors Large values of sheet resistance can be obtained either by reducing the effective cross-sectional area of the resistor structure or by using a low doping concentration that forms the resistor body. The first technique is used to realize the pinched resistor while the second is used to realize the epitaxial resistor. Figure 55.67 shows an epitaxial resistor structure where the resistor is formed with a lightly doped epitaxial layer. For an epi thickness of 10 µm and a doping concentration of 1015 donor atoms/cm3, this structure achieves a resistivity of 5 Ω-cm and an effective sheet resistance of 5 KΩ/▫. The temperature coefficient of the epitaxial resistor is relatively high with typical values around +3000 ppm/°C. This large temperature variation is a direct consequence of the hole and electron mobilities undergoing more drastic variations against temperature at particularly low doping concentrations [13]. The maximum voltage that can be applied across the epitaxial resistor is significantly higher than that for the pinched resistor. This voltage is set by the breakdown voltage between the n-type epi and the p-type substrate which varies inversely with the doping concentration of this pn junction. Epitaxial Pinched Resistors. By putting a p-type diffusion plate on top of the epitaxial resistor of Fig. 55.67, even larger sheet resistance value can be obtained. The p-type diffusion plate overlaps the epi region and is electrically connected to the substrate through the p-type isolation. The epi layer is thus pinched between the p-type diffusion plate and the p-type substrate. When the n-type epi and the surrounding p-type regions is subject to a reverse bias potential, the junction depletion width extends into the epi region and effectively reduces the cross-sectional area. Typical sheet resistance values are between 4 and 5 KΩ/▫. The epitaxial-pinched resistor behaves like an n-channel JFET, in which the effective channel width is controlled by the substrate voltage. © 2003 by CRC Press LLC

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Monolithic Device Models

Base Diffusion

Buried Layer

Isolation n+ Diffusion

SiO2

p Diffusion Pinched Region Resistor Resistor n+ Diffusion Contact Contact

Epitaxial Contact n+

n Epitaxial n+ Buried Layer p Substrate

R

p-channel JFET Epi Contact

Epi Contact

FIGURE 55.66 p-type base-pinched resistor.

Ion-Implanted Resistors Ion implantation is an alternative technique beside diffusion for inserting impurity atoms into a silicon wafer [17]. Commonly used impurities for implantation are the p-type boron atoms. The desired impurity atoms are first ionized and then accelerated to a high energy by an electric field. When a beam of these high-energy ions is directed at the wafer, the ions penetrate into exposed regions of the wafer surface. The penetration depth depends on the velocity at contact and is typically between 0.1 and 0.8 µm. The exposed regions of the wafer surface are defined by selectively etching a thick thermally grown SiO2 layer that covers the wafer and functions as a barrier against the implanted ions. Unique characteristics of the ion-implantation technique include a precise control of the impurity concentration, uniformly implanted layers of impurity atoms, and no lateral diffusion. The structure of a p-type ion-implanted resistor is shown in Fig. 55.68, where the p-type diffused regions at the contacts are used to achieve good ohmic contacts to the implanted resistor. The pn junction formed between the p-type implanted region and the n-type epitaxial layer must be reverse biased for electrical isolation. By connecting the epi region to a potential relatively more positive than the substrate potential, the conductive action due to the parasitic pnp transistor formed by the p-type implanted, the n-type epi, and the p-type substrate is also eliminated. Ion-implanted resistors exhibit relatively tight absolute value tolerance and excellent match­ ing. Absolute value tolerance down to ±3 percent and matching tolerance of ±2 percent are typical performance. Table 55.6 provides a summary of the typical characteristics for the diffused, pinched, epitaxial, and ion-implanted resistors. © 2003 by CRC Press LLC

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n+ Diffusion

n+ Diffusion

Optional p Diffusion Plate

p-type Isolation

SiO2

Resistor Contact

Resistor Contact

Optional p Diffusion

n+

n+ n Epitaxial p Substrate

R R

Substrate

Substrate Substrate (a) Epitaxial Resistor

(b) Epitaxial-Pinched Resistor

FIGURE 55.67 n-type epitaxial and epitaxial-pinched resistors.

Thin-Film Resistors Compared with diffused resistors, thin-film resistors offer advantages of a lower temperature coefficient, a smaller absolute value variation, and an excellent high-frequency characteristic. Commonly used resistive thin films are tantalum, nickel–chromium (Ni–Cr), cermet (Cr–SiO), and tin oxide (SnO2). A typical thin-film resistor structure is shown in Fig. 55.69, where a thin-film resistive layer is deposited on top of a thermally grown SiO2 layer and a thin-film conductive metal layer is used to form the resistor contacts. The oxide layer functions as an insulating layer for the reistor. Various CVD (chemical vapor deposition) techniques can be used to form the thin films [8]. The oxide passivation layer deposited on top of the resistive film and the conductive film protects the device surface from contamination. The electrical lumped model as shown in Fig. 55.69 is adequate to characterize the high-frequency perfor­ mance of the resistor. The parallel-plate capacitance formed between the thin-film resistive and the substrate is divided equally between the two capacitors. Table 55.7 provides a summary of the charac­ teristics for some commonly used thin-film resistors.

© 2003 by CRC Press LLC

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Monolithic Device Models

SiO2

Resistor Contact

Epitaxial Contact

Resistor Contact

p Implanted Region

n+ p Diffused

n Epitaxial

p Diffused

p Substrate

R

Epi Contact

FIGURE 55.68 p-type ion-implanted resistor. TABLE 55.6

Typical Properties of Semiconductor Resistors

Resistor Type

Sheet ρ(Ω/▫)

Absolute Tolerance (%)

Matching Tolerance (%)

Temperature Coefficient (ppm/°C)

Base diffused

100–200

±20

Emitter diffused Base pinched Epitaxial Epitaxial pinched Ion implanted

2–10 2–10 K 2–5 K 4–10 K 100–1000

±20 ±50 ±30 ±50 ±3

±2 (5 µm wide) ±0.2 (50 µm wide) ±2 ±10 ±5 ±7 ±2 (5 µm wide) ±0.15 (50 µm wide)

+1500 to +2000 — +600 +2500 +3000 +3000 Controllable to ±100

Source: P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits. New York: Wiley, 1984, p. 119.

Capacitors Monolithic capacitors are widely used in analog and digital integrated circuits for functions such as circuit stability, bandwidth enhancement, ac signal coupling, impedance matching, and charge storage cells. Capacitor structures available in monolithic form include pn junction, MOS, and polysilicon capacitors. pn junctions under reverse-biased conditions exhibit a nonlinear voltage-dependent capacitance. MOS and polysilicon capacitors, on the other hand, closely resemble the linear parallel-plate capacitor structure as shown in Fig. 55.70. If the insulator thickness T of the parallel-plate structure is small compared with the plate width W and length L, the electric field between the plates is uniform (fringing field neglected). Under this condition the capacitance can be calculated by C=

κε 0 WL T

(55.155)

where κ is the relative dielectric constant of the insulating material and ε0 is the permittivity constant in vacuum (8.854 × 10–14 F/cm).

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Oxide Passivation Layer Metal Contact

Metal Contact

Thin-Film Resistive Layer

SiO2 p Substrate

R

Substrate

FIGURE 55.69 Thin-film resistor.

TABLE 55.7

Typical Characteristic of Thin-Film Resistors

Resistor Type

Sheet ρ (Ω/▫)

Absolute Tolerance (%)

Matching Tolerance (%)

Temperature Coefficient (ppm/°C)

Ni–Cr Ta SnO2 Cr–SiO

40–400 10–1000 80–4000 30–2500

±5 ±5 ±8 ±10

±1 ±1 ±2 ±2

±100 ±100 0–1500 ±50–±150

Source: A. B. Grebene, Bipolar and MOS Analog Integrated Circuit Design. New York: Wiley, 1984, p. 155.

Top Plate

Insulating Layer

L

Bottom Plate

T

W

FIGURE 55.70 Structure of a parallel-plate capacitor. © 2003 by CRC Press LLC

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Monolithic Device Models

(a)

−

VR

+

Depletion Region p (NA cm−3)

n (ND cm−3)

Wd

(b)

−

+

VR

Charge Density

Q+ = (qNDxn) A −xp

(c)

x

xn

−

Q = −(qNAxp) A

Electric Field

−xp

(d)

xn

x

FIGURE 55.71 Abrupt p–n junction: (a) p–n junction symbol; (b) depletion region; (c) charge density within the depletion region; (d) electric field.

Junction Capacitors The structure of an abrupt pn junction is shown in Fig. 55.71, where the doping is assumed uniform throughout the region on both sides. The acceptor impurity concentration of the p region is NA atoms/cm3 and the donor impurity concentration of the n region is ND atoms/cm3. When the two regions are brought in contact, mobile holes from the p region diffuse across the junction to the n region and mobile electrons diffuse from the n to the p region. This diffusion process creates a depletion region that is essentially free of mobile carriers (depletion approximation) and contains only fixed acceptor and donor ions. Ionized acceptor atoms are negatively charged and ionized donor atoms are positively charged. In equilibrium the diffusion process is balanced out by a drift process that arises from a built-in voltage ψo across the junction. This voltage is positive from the n region relative to the p region and is given by [17] ψo = © 2003 by CRC Press LLC

kT N AN D ln q ni2

(55.156)

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where k is the Boltzmann constant (1.38 × 10–23 V · Coulomb/K), T is the temperature in Kelvin (K), q is the electron charge (1.60 × 10–19 C), and ni (cm–3) is the intrinsic carrier concentration in a pure semiconductor sample. For silicon at 300 K, ni ≈ 1.5 × 1010 cm–3. When the pn junction is subject to an applied reverse bias voltage VR, the drift process is augmented by the external electric field and more mobile electrons and holes are pulled away from the junction. Because of this effect, the depletion width Wd and consequently the charge Q on each side of the junction vary with the applied voltage. A junction capacitor can thus be defined to correlate this charge–voltage relationship. The Poisson’s equation relating the junction voltage φ(x) to the electric field ξ(x) and the total charge Q is d 2φ(x) dξ(x) q =− = − (p − n + ND − NA) 2 dx dx εS  qN A  ε ≈ S qN D –  ε S

(55.157)

−x p < x < 0 0 < x < xn

where εS (11.8ε0 = 1.04 × 10–12 F/cm) is the permittivity of the silicon material. The first intergral of (55.157) yields the electric field as  − ξ(x) =  − 

(

)

qN A x + xp εS qN D (xn + x ) εS

−x p < x < 0 (55.158) 0 < x < xn

The electric field is shown in Fig. 55.71, where the maximum field strength occurs at the junction edge. This value is given by ξ max =

qN A qN D xp = x εS εS n

The partial depletion width xp on the p region and the partial depletion width xn on the n region can then be related to the depletion width Wd as x p + x n = Wd xp =

ND W NA + ND d

xn =

NA W NA + ND d

Taking the second integral of (55.157) yields the junction voltage  qN  x 2 x2  p A  + xpx +   2 2  ε φ(x) =  S  2  qN D  x n x p + x x − x  n  ε  2 2   S

−x p < x < 0 (55.159) 0 < x < xn

where the voltage at xp is arbitrarily assigned to be zero. The total voltage ψ0 + VR can be expressed as © 2003 by CRC Press LLC

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Monolithic Device Models

ψ o + VR = φ( x n ) =

qN D  N D  2 1+ x 2ε S  N A  n

Finally, the depletion width Wd and the total charge Q in terms of the total voltage across the junction can be derived to be 12

 2ε  1 1  Wd =  S (ψ o + VR ) +   N A N D    q

(55.160)

12

(

Q = A qN A x p

)

−1   1 1   + = A(qN D x n ) = A 2qε S (ψ o + VR )    NA ND    

The junction capacitance is thus 12

−1  qε  1  1 1   dQ + Cj = = A S    dVR  2  ψ o + VR   N A N D    

=

(55.161)

C jo  VR  1 + ψ   o

12

where A is the effective cross-sectional junction area and Cjo is the value of Cj for VR = 0. If the doping concentration in one side of the pn junction is much higher than that in the other, the depletion width and the junction capacitance can be simplified to 12

  2ε Wd =  S (ψ o + VR )   qN L

(55.162)

12

 ε qN  1   C j = A S L    2  ψ o + VR  

(55.163)

where NL is the concentration of the lightly doped side. Figure 55.72 displays the junction capacitance per unit area as a function of the total voltage ψo + VR and the concentration on the lightly doped side of the junction [3]. In silicon bipolar technology the base–emitter, the base–collector, and the collector–substrate junctions under reverse bias are often utilized for realizing a junction capacitance. The collector–substrate junction has only a limited use since it can only function as a shunt capacitor due to the substrate being connected to an ac ground. Base–Collector Junction Capacitor. A typical base–collector capacitor structure is shown in Fig. 55.73 together with an equivalent lumped circuit model. A heavily doped n+ buried layer is used to minimize the series resistance RC . For the base–collector junction to operate in reverse bias, the n-type collector must be connected to a voltage relatively higher than the voltage at the p-type base. The junction breakdown voltage is determined by BVCBO of the npn transistor, which has a typical value between 25 and 50 V. © 2003 by CRC Press LLC

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Capacitance per Unit Area (pF/µm2) 10−2 1019

1018

10−3

Breakdown region

1017 Impurity concentration 1016

10−4

1015

1014

10−5

10−6 1

2

4

6

8

10

20

40

60

80 100

Total Voltage (V)

FIGURE 55.72 Junction capacitance as a function of the total voltage and the concentration on the lightly doped side.

Base–Emitter Junction Capacitor. Figure 55.74 shows a typical base–emitter capacitor structure where the parasitic junctions DBC and DSC must always be in reverse bias. The base–emitter junction achieves the highest capacitance per unit area among the base–collector, base–emitter, and collector–substrate junctions due to the relatively higher doping concentrations in the base and emitter regions. For the base–emitter junction to operate in reverse bias, the n-type emitter must be connected to a voltage relatively higher than the voltage at the p-type base. The breakdown voltage of the base–emitter junction is relatively low, determined by the BVEBO of the npn transistor, which has a typical value of about 6 V. MOS Capacitors MOS (metal-oxide-semiconductor) capacitors are preferable and commonly used in integrated circuits since they are linear and not confined to a reverse-biased operating condition as in the junction capacitors. The structure of a MOS capacitor is shown in Fig. 55.75, where by means of a local oxidation process a thin oxide layer is thermally grown on top of a heavily doped n+ diffusion layer. The oxide layer has a typical thickness between 500 and 1500 Å (Å = 10–10 m = 10–4 µm) and functions as the insulating layer of the parallel-plate capacitor. The top plate is formed by overlapping the thin oxide area with a deposited layer of conductive metal. The bottom-plate diffusion layer is heavily doped for two reasons: to minimize the bottom-plate resistance and to minimize the depletion width at the oxide-semiconductor interface when the capacitor operates in the depletion and inversion modes [17]. By keeping the depletion width © 2003 by CRC Press LLC

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Monolithic Device Models

SiO2

Base Contact

p Diffusion

Collector Contact n+

n Epitaxial n+ Buried Layer p Substrate

Base

RB

RC

DBC

Collector

DSC

Substrate

FIGURE 55.73 Base–collector junction capacitor.

SiO2

Emitter Contact

Base Contact

n+ Diffusion

Epitaxial Contact n+

p Base n Epitaxial n+ Buried Layer p Substrate

Base

RB

DBE

DBC

RC

Emitter

Epi Contact

DSC

Substrate

FIGURE 55.74 Base–emitter junction capacitor.

small, the effective capacitance is dominated by the parallel-plate oxide capacitance. The MOS capacitance is thus given by C=

κ ox ε 0 A T

(55.164)

where κox is the relative dielectric constant of SiO2 (2.7 to 4.2), ε0 is the permittivity constant, T is the oxide thickness, and A is the area defined by the thin oxide layer. © 2003 by CRC Press LLC

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Top Plate

Bottom Plate

Edge of Thin Oxide Edge of n+ Diffusion Isolation

SiO2

Capacitor Contact

Thin Oxide n+ Diffusion

Bottom-Plate Contact

n Epitaxial p Substrate

R Bottom-Plate Contact

C

Substrate

FIGURE 55.75 MOS capacitor.

In practice, a thin layer of silicon nitride (Si3 N4) is often deposited on the thin oxide layer and is used to minimize the charges inadvertently introduced in the oxide layer during oxidation and subsequent processing steps. These oxide charges are trapped within the oxide and can cause detrimental effect to the capacitor characteristic [17]. The silicon nitride assimilates an additional insulating layer and effec­ tively creates an additional capacitor in series with the oxide capacitor. The capacitance for such a structure can be determined by an application of Gauss’s law. It is given by C=

εo A  Tni   Tox  κ  +κ   ni   ox 

(55.165)

where Tni and Tox are the thickness of the silicon nitride and oxide layers, respectively, and κni (2.7 to 4.2) and κni (3.5 to 9) are the relative dielectric constant of oxide and silicon nitride, respectively. In the equivalent circuit model of Fig. 55.75, the parasitic junction between the p-type substrate and the n-type bottom plate must always be reverse biased. The bottom-plate contact must be connected to a voltage relatively higher than the substrate voltage. Polysilicon Capacitors Polysilicon capacitors are conveniently available in MOSFET technology, where the gate of the MOSFET transistor is made of polysilicon material. Polysilicon capacitors also assimilate the parallel-plate capacitor. © 2003 by CRC Press LLC

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Capacitor Contact

Polysilicon

Thin Oxide

Polysilicon Contact

SiO2 p Substrate

R Poly Contact C COX

Substrate

FIGURE 55.76 Polysilicon capacitor.

Figure 55.76 shows a typical structure of a polysilicon capacitor, where a thin oxide is deposited on top of a polysilicon layer and serves as an insulating layer between the top-plate metal layer and the bottomplate polysilicon layer. The polysilicon region is isolated from the substrate by a thick oxide layer that forms a parasitic parallel-plate capacitance between the polysilicon layer and the substrate. This parasitic capacitance must be accounted for in the equivalent circuit model. The capacitance of the polysilicon capacitor is determined by either (55.164) or (55.165) depending on whether a thin silicon nitride is used in conjunction with the thin oxide.

Inductors Planar inductors have been implemented using a variety of substrates such as standard PC boards, ceramic and sapphire hybrids, monolithic GaAs [24], and more recently monolithic silicon [18]. In the early development of silicon technology, planar inductors were investigated [26], but the prevailing lithographic limitations and relatively large inductance requirements (for low-frequency applications) resulted in excessive silicon area and poor performance. Reflected losses from the conductive silicon substrate were a major contribution to low inductor Q. Recent advances in silicon IC processing technology have achieved fabrication of metal width and metal spacing in the low micrometer range and thus allow many more inductor turns per unit area. Also, modern oxide-isolated processes with multilayer metal options allow thick oxides to help isolate the inductor from the silicon substrate. Practical applications of monolithic inductors in low-noise amplifiers, impedance matching amplifiers, filters and microwave oscillators in silicon technologies have been successfully demonstrated [19], [20]. Monolithic inductors are especially useful in high-frequency applications where inductors of a few nanoHenrys of inductance are sufficient. Inductor structures in monolithic form include strip, loop, and spiral inductors. Rectangular and circular spiral inductors are by far the most commonly used structures. Rectangular Spiral Inductors The structure of a rectangular spiral inductor is shown in Fig. 55.77, where the spiral loops are formed with the top metal layer M2 and the connector bridge is formed with the bottom metal layer M1. Using the top metal layer to form the spiral loops has the advantage of minimizing the parasitic metal-to­ substrate capacitance. The metal width is denoted by W and the metal spacing is denoted by S. The total inductance is given by © 2003 by CRC Press LLC

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M2

W

Via

M1

S

SiO2

M1

M2

n+ Tub Contact

SiO2 n+ Buried Layer p Substrate

FIGURE 55.77 Rectangular spiral inductor. 4N −1 4N

4N

LT =

∑ L (i) + 2 ⋅ ∑ ∑ LM (ij) S

i=1

(55.166)

i=1 j =i +1

where N is the number of turns, Ls(i) is the self inductance of the rectangular metal segment i and LM (ij) is the mutual inductance between metal segments i and j. The self-inductance is due to the magnetic flux surrounding each metal segment. The mutual inductance is due to the magnetic flux coupling around every two parallel metal segments and has a positive value if the currents applied to the metal conductors flow in the same direction and a negative value otherwise. Perpendicular metal segments have negligible mutual inductance. The self-inductance and mutual inductance for straight rectangular conductors can be determined by the geometric mean distance method [10], in which the conductors are replaced by equivalent straight filaments whose basic inductive characteristics are well known. Self-Inductance. The self-inductance for the rectangular conductor of Fig. 55.78 depends on the con­ ductor length L, the conductor width W, and the conductor thickness T. The static self-inductance is given by [9], [10].   2L   AMD  µ r   LS = 2L ln  − 1.25 +   +   ζ (nH)  L   4     GMD  © 2003 by CRC Press LLC

(55.167)

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I (a)

L

T

W

I1 (b)

I2 S

L

T

W D

FIGURE 55.78 Calculation of (a) self-inductance and (b) mutual inductance for parallel rectangular conductors.

where µr is the relative permeability constant of the conductor, GMD is the geometric mean distance, AMD is the arithmetic mean distance, and ζ is a frequency-dependent parameter that equals 1 for direct and low-frequency alternating currents and approaches 0 for very high-frequency alternating currents. The AMD and GMD for the rectangular conductor of Fig. 55.78 are W +T  AMD =    3  0.22313 ⋅ (W + T ) T → 0   GMD = 0.22360 ⋅ (W + T ) T = W 2  0.223525 ⋅ (W + T ) T → W

(55.168)

The rectangular dimensions L, W, and T are normalized to the centimeter in the preceding expressions. Mutual Inductance. The mutual inductance for the two parallel rectangular conductors of Fig. 55.78 depends on the conductor length L, the conductor width W, and the conductor thickness T, and the distance D separating the conductor centers. The static mutual inductance is [10] © 2003 by CRC Press LLC

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LM = 2Lα(nH)

(55.169)

where 12 12    L  2     GMD  2  L  GMD    α = ln     +  + 1 +     − 1 +   GMD    GMD      L    L       

and GMD = exp( ln D − β)

(55.170)

−8  1  D  −2 1  D  −4 1  D  −6 1  D    +   +   +   60  W  168  W  360  W  12  W   −10  1  D β= +   +L 660  W    0.1137 for D = W  

The GMD closed-form expression (55.170) is valid for rectangular conductors with small thickness-to­ width ratios T/W. As the thickness T approaches the width W, the GMD approaches the distance D and the GMD is no longer represented by the above closed-form expression. Figure 55.79 shows plots of the self inductance and the mutual inductance as expressed in (55.167) and (55.169), respectively. The conductor dimensions are given in µm (µm = 10–4 cm). For the inductor structure of Fig. 55.77 it is important to emphasize that since the spiral loops are of nonmagnetic metal material, the total inductance depends only on the geometry of the conductors and not on the current strength. At high-frequencies, especially those above the self-resonant frequency of the inductor, the skin effect due to current crowding toward the surface and the propagation delay as the current traverses the spiral must be fully accounted for [16], [22]. The ground-plane effect due to the inductor image must also be considered regardless of the operation frequency. An equivalent lumped model for the rectangular spiral inductor of Fig. 55.77 is shown in Fig. 55.80. This model consists of the total inductance LT, the accumulated metal resistance RS , the coupling capac­ itance CCP between metal segments due to the electric fields in both the oxide region and the air region, the parasitic capacitances CIN and COUT from the metal layers to the buried layer [2], [11], [15], and the buried-layer resistance Rp . Since the spiral structure of Fig. 55.77 is not symmetrical, the parasitic capac­ itors CIN and COUT are not the same, though the difference is relatively small. The self-resonant frequency can be approximated using the circuit model of Fig. 55.80 with one side of the inductor being grounded. For simplicity, let CIN = COUT ≡ CP and neglect the relatively small coupling capacitor CCP , the self-resonant frequency is given by 1/ 2

fR =

1 2π

   2 C  1 − RS  P    LT   1   C   LT C P 1 − RP2  P    LT   

(55.171)

Transformer Structures. Transformers are often used in high-performance analog integrated circuits that require conversions between single-ended signals and differential signals. In monolithic technology, transformers can be fabricated using the basic structure of the rectangular spiral inductor. Figure 55.81 shows a planar interdigitated spiral transformer that requires only two metal layers M1 and M2. The

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Ls (nH) 0.60 0.55 W+T = 5 W+T = 10 W+T = 15

0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05

Length 100

200

300

400

500

(a) Lm (nH) 0.44 0.40 D=5 D = 10 D = 15

0.36 0.32 0.28 0.24 0.20 0.16 0.12 0.08 0.04

Length 100

200

300

400

500

(b)

FIGURE 55.79 (a) Self-inductance as a function of width, thickness and length for rectangular conductors. (b) Mutual inductance as a function of distance and length for rectangular conductors (W = 5, T = 0).

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CCP

LT

RS

COUT

CIN

RP

RP

Tub Contact

FIGURE 55.80 Electrical model for the spiral inductor.

Primary Coil (M2)

Port 4

Secondary Coil (M2)

Port 1

Via

M1

Via

Port 3

Port 2

FIGURE 55.81 Rectangular spiral transformer I.

structure of Fig. 55.82, on the other hand, requires three layers of metal for which the top metal layer M3 is used for the upper spiral, the middle metal layer M2 is used for the lower spiral, and the bottom metal layer M1 is used for the two connector bridges. This structure can achieve a higher inductance per unit than that of Fig. 55.81 due to a stronger magnetic coupling between the upper spiral and the lower spiral through a relatively thin oxide layer separating metal layers M2 and M3. An equivalent lumped

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Monolithic Device Models

M3

M1

Via

Port 2

Port 1

Port 4

Port 3

Via M2

FIGURE 55.82 Rectangular spiral transformer II.

Port 3

Port 1

k

Tub Contact

Tub Contact

CC

Secondary Coil

Primary Coil

Port 2

FIGURE 55.83 Electrical model for the spiral transformer.

© 2003 by CRC Press LLC

Port 4

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W S

M2

M1 Via

SiO2

M1

n+ Tub Contact

M2

SiO2 n+ Buried Layer p Substrate

FIGURE 55.84 Concentric circular spiral inductor.

model is shown in Fig. 55.83. In addition to all the circuit elements of the two individual spiral inductors, there are also a magnetic coupling factor k and a coupling capacitance CC between the primary and secondary coils. Circular Spiral Inductors The structure of a concentric circular spiral inductor is shown in Fig. 55.84 where the circular loops share the same center point. The top metal layer M2 is used for the circular conductors and the bottom metal layer M1 is used for the connector bridge. The metal width is denoted by W and the spacing between two adjacent loops is denoted by S. The total inductance is given by N

LT =

∑ i=1

LS (i ) + 2 ⋅

N –1

N

∑∑ L

M

(ij )



(55.172)

i=1 j =i +1

where N is the number of circular turns, LS(i) is the self-inductance of the circular conductor i and LM (ij) is the mutual inductance between conductors i and j. Self-Inductance. Consider the single circular conductor of Fig. 55.85(a) that has a radius R and a width W. A current I applied to this conductor produces a magnetic flux encircled by the loop and another magnetic flux inside the conductor itself. The inductance associated with the former and the latter magnetic flux component is referred to as the external self-inductance and the internal self-inductance, respectively. The external self-inductance characterizing the change in the encircled magnetic flux to the change in current is [25].   k 2  LS = µ( 2R − δ)1 −  K (k ) − E (k ) (nH ) 2   © 2003 by CRC Press LLC

(55.173)

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W = 2δ

(a) R

M

3

4

2

1

T (b) W

W

S

Ro Ri

(c)

FIGURE 55.85 Calculation of self-inductance and mutual inductance for circular conductors. (a) External selfinductance; (b) internal self-inductance; (c) mutual inductance.

where k2 =

4R( R − δ)

(2R − δ)2

(55.174)

and µ is the permeability of the conductor (equals 4π nH/cm for nonmagnetic conductors), and δ is one-half the conductor width W. K(k) and E(k) are the complete elliptic integrals of the first and second kind, respectively, and are given by

© 2003 by CRC Press LLC

K (k ) =

∫

π 2

E (k ) =

∫

π 2

0

0

dφ 1 − k 2 sin 2 φ 1 − k 2 sin 2 φ dφ

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The internal self-inductance is determined based on the concept of magnetic field energy. As shown in Fig. 55.85(b), the flat circular conductor is first approximated by an M number of round circular con­ ductors [14] that are electrically in parallel and each conductor has a diameter equal to the thickness T of the flat conductor. The internal self-inductance of each round conductor is then determined as [25]. L=

µ (nH cm) 8π

The internal self-inductance of the flat conductor thus equals the parallel combination of these M components LS ≈

µ   4 

M

∑[ i=1

–1   R − δ + T (i − 0.5)  

]

–1

(nH)

(55.175)

where R – δ + T(i – 0.5) is the effective radius from the center of the loop to the center of the round conductor i. The typical contribution from the internal self-inductance of (55.175) is less than 5% the contribution from the external self-inductance of (55.173). Mutual Inductance. The mutual inductance of the two circular loops of Fig. 55.85(c) depends on the inner radius Ri and the outer radius Ro . For any two adjacent loops of the circular spiral inductor, the outer radius is related to the inner radius by the simple relation Ro = Ri + (W + S). The mutual inductance is determined based on the Neumann’s line integral given as follows: LM =

µ 4π

∫∫

C C

dl1 ⋅ dl 2 D

where dl1 · dl2 represents the dot product of the differential lengths and D is the distance separating the differential l1 vector and l2 vector. The static mutual inductance [25] is   2  2 LM = µ Ri Ro  − k K (k ) − E (k ) (nH)   k k  

(55.176)

where k2 =

4Ri Ro

(Ri + Ro )

2

(55.177)

Fig. 55.86 shows plots of the external self-inductance and the mutual inductance as expressed in (55.173) and (55.176), respectively. The conductor dimensions are given in µm. As in the rectangular spiral inductor, the ground-plane effect and the retardation effect of the circular spiral inductor must be fully accounted for. The circuit model of Fig. 55.80 can be used to characterize the electrical behavior of the circular inductor. A comparison between the rectangular spiral of Fig. 55.77 and the circular spiral of Fig. 55.84 is shown in Fig. 55.87, where the total inductance LT is plotted against the turn number N. Both inductors have the same innermost dimension, the same conductor width, space, and thickness. The dimensions are given in µm, and the ground-plane effect and the retardation effect are not considered. For a given turn number, the rectangular spiral yields a higher inductance per semiconductor area than the circular spiral. Figure 55.88 shows a plot of the inductor Q vs. the total inductance of the same spiral inductors under consideration. Due to a higher inductance per length ratio, the Q of the circular inductor is higher than that of the rectangular inductor, about 10 percent for high inductance values.

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Ls (nH)

0.45 W=5 W = 10 W = 15

0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0

Radius R 20

40

60

80

100

(a) Lm (nH) 0.32 Ro = Ri+10 Ro = Ri+20 Ro = Ri+30

0.28

0.24 0.20

0.16 0.12

0.08

0.04 Ri 20

40

60

80

100

(b)

FIGURE 55.86 (a) External self-inductance as a function of radius and width for circular conductors. (b) Mutual inductance as a function of radii Ri and Ro for circular conductors.

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Lt (nH) 22.0 20.0 Rectangular Spiral 18.0

Circular Spiral

16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 Turn 2.0

4.0

6.0

8.0

10.0

FIGURE 55.87 Total static inductance vs. turn number for the rectangular and circular inductors. The groundplane effect is neglected. Innermost center dimension is 88 by 88, W = 6, S = 3, T = 1.2.

References [1] I. Bahl and P. Bhartia, Microwave Solid State Circuit Design, New York: Wiley, 1988. [2] T. G. Bryant and J. A. Weiss, “Parameters of microstrip transmission lines and of coupled pairs of microstrip lines,” IEEE Trans. Microwave Theory Tech., vol. MTT-16, pp. 1021–1027, 1968. [3] H. R. Camenzind, Electronic Integrated Systems Design, New York: Van Nostrand Reinhold, 1972. [4] E. M. Conwell, “Properties of silicon and germanium,” Proc. IRE, vol. 46, pp. 1281–1300, 1958. [5] R. Garg and I. J. Bahl, “Characteristics of coupled microstrip lines,” IEEE Trans, Microwave Theory Tech., vol. MTT-27, pp. 700–705, 1979. [6] F. R. Gleason, “Thin-film microelectronic inductors,” in Proc. Nat. Electron. Conf., 1964, pp. 197–198. [7] P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 2nd ed., New York: Wiley, 1984. [8] A. B. Grebene, Bipolar and MOS Analog Integrated Circuit Design, New York: Wiley, 1984. [9] H. M. Greenhouse, “Design of planar rectangular microelectronic inductor,” IEEE Trans. Parts, Hybrids, Packaging, vol. PHP-10, pp. 101–109, 1974. [10] F. W. Grover, Inductance Calculations, New York: Van Nostrand, 1946. [11] E. Hammerstad and O. Jensen, “Accurate models for microstrip computer-aided design,” IEEE MTT-S Dig., pp. 407–409, 1980. [12] J. C. Irwin, “Resistivity of bulk silicon and of diffused layers in silicon,” Bell Syst. Tech. J., vol. 41, pp. 387–410, 1962.

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Inductor Q @ 1 GHz 5.0 4.6 4.2 3.8 3.4 3.0

Rectangular Spiral Circular Spiral

2.6 2.2 1.8 1.4 1.0

Lt (nH) 0.0

5.0

10.0

15.0

20.0

FIGURE 55.88 Inductor Q vs. total inductance for the rectangular and circular inductors. Metal sheet resistance is 25 mΩ/▫. Innermost dimension is 88, W = 6, S = 3, T = 1.2.

[13] C. Jacoboni, C. Canali, G. Ottaviani, and A. A. Quaranta, “A review of some charge transport properties of silicon,” Solid State Electron., vol. 20, 1977. [14] R. L. Kemke and G. A. Burdick, “Spiral inductors for hybrid and microwave applications,” in Proc. Electron. Components Conf., 1974, pp. 152–161. [15] M. Kirschning and R. H. Jansen, “Accurate wide-range design equations for the frequency-depen­ dent characteristics of parallel-coupling microstrip lines,” IEEE Trans. Microwave Theory Tech., vol. MTT-32, pp. 83–90, 1984. [16] D. Krafcsik and D. Dawson, “A close-form expression for representing the distributed nature of the spiral inductor,” IEEE MTT-S Dig., pp. 87–92, 1986. [17] R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits, 2nd ed., New York: Wiley, 1986. [18] N. M. Nguyen and R. G. Meyer, “Si IC-compatible inductors and LC passive filters,” IEEE J. SolidState Circuits, vol. 25, pp. 1028–1031, 1990. [19] N. M. Nguyen and R. G. Meyer, “A Si bipolar monolithic RF bandpass amplifier,” IEEE J. SolidState Circuits, vol. 27, pp. 123–127, 1992. [20] N. M. Nguyen and R. G. Meyer, “A 1.8-GHz monolithic LC voltage-controlled oscillator,” IEEE J. Solid-State Circuits, vol. 27, pp. 444–450, 1992. [21] N. M. Nguyen and R. G. Meyer, “Start-up and frequency stability in high-frequency oscillators,” IEEE J. Solid-State Circuits, vol. 27. pp. 810–820, 1992. [22] M. Parisot, Y. Archambault, D. Pavlidis, and J. Magarshack, “Highly accurate design of spiral inductors for MMIC’s with small size and high cut-off frequency characteristics,” IEEE MTT-S Digest, pp. 106–110, 1984.

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[23] E. Pettenpaul, H. Kapusta, A. Weisgerber, H. Mampe, J. Luginsland, and I. Wolff, “CAD models of lumped elements on GaAs up to 18 GHz,” IEEE Trans. Microwave Theory Tech., vol. 36, pp. 294–304, 1988. [24] R. A. Pucel, “Design considerations for monolithic microwave circuits,” IEEE Trans. Microwave Theory Tech., vol. MTT-29, 513–534, 1981. [25] S. Ramon, J. R. Whinnery, and T. V. Duzer, Fields and Waves in Communication Electronics, 2nd ed., New York: Wiley, 1984. [26] R. M. Warner, Jr., and J. N. Fordemwalt, Integrated Circuits, New York: McGraw-Hill, 1965.

55.5 Chip Parasitics in Analog Integrated Circuits Martin A. Brooke The parasitic elements in electronic devices and interconnect limit the performance of all integrated circuits. No amount of improvement in device performance or circuit design can completely eliminate these effects. Thus, as circuit speeds increase, unaccounted for interconnect parasitics become a more and more common cause of analog integrated circuit design failure. Hence, the causes, characterization, and modeling of significant interconnect parasitics are essential knowledge for good analog integrated circuit design [1]–[4].

Interconnect Parasitics The parasitics due to the wiring used to connect devices together on chip produce a host of problems. Unanticipated feedback through parasitic capacitances can cause unwanted oscillation. Mismatch due to differences in interconnect resistance contribute to unwanted offset voltages. For very-high-speed inte­ grated circuits, the inductance of interconnects is both a useful tool and a potential cause of yield problems. Even the interactions between interconnect lines are both important and very difficult to model. So too are the distributed interactions of resistance, capacitance, and (in high-speed circuits) inductance that produce transmission line effects. Parasitic Capacitance Distributed capacitance of integrated circuit lines is perhaps the most important of all integrated circuit parasitics. It can lower the bandwidth of amplifiers, alter the frequency response of filters, and cause oscillations. Physics. Every piece of integrated circuit interconnect has capacitance to the substrate. In the case of silicon circuitry, the substrate is conductive and connected to an ac ground, thus there is a capacitance to ground from every circuit node due to the interconnect. Figure 55.89 illustrates this substrate capac­ itance interconnect parasitic. The capacitance value will depend on the total area of the interconnect, and on the length of edge associated with the interconnect. This edge effect is due to the nonuniformity interconnect edge

edge

FIGURE 55.89 Substrate capacitance. The electric field distorts at the edges, making the capacitance larger there than elsewhere. © 2003 by CRC Press LLC

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interconnect level 2 edge

edge

interconnect level 1

FIGURE 55.90 Overlap capacitance. The bottom interconnect level will have edges into and out of the page with distorted electric field similar to that shown for the top level of interconnect.

interconnect

interconnect

edge

edge

Substrate

FIGURE 55.91 Parallel line capacitance. Only the solid field lines actually produce line-to-line capacitance, the dashed lines form substrate capacitance.

of the electric field at the interconnect edges. The nonuniformity of the electric field at edges is such that the capacitance value is larger for a given area of interconnect near the edge than elsewhere. In addition to the substrate capacitance, all adjacent pieces of an interconnect will have capacitance between them. This capacitance is classified into two forms, overlap capacitance, and parallel line capac­ itance (also known as proximity capacitance). Overlap capacitance occurs when two pieces of interconnect cross each other, while parallel line capacitance occurs when two interconnect traces run close to each other for some distance. When two lines cross each other, the properties of the overlapping region will determine that size of the overlap capacitance. The electric field through a cross section of two overlapping lines is illustrated in Fig. 55.90. The electric field becomes nonuniform near the edges of the overlapping region, producing an edge-dependent capacitance term. The capacitance per unit area at the edge is always greater than elsewhere and, if the overlapping regions are small, the edge capacitance effect can be significant. The size of parallel line capacitance depends on the distance for which the two lines run side by side and on the separation of the lines. Since parallel line capacitance occurs only at the edges of an inter­ connect, the electric field that produces it is very nonuniform. This particular nonuniformity, as illus­ trated in Fig. 55.91, makes the capacitance much smaller for a given area of interconnect than either overlap or substrate capacitance. Thus, two lines must run parallel for some distance for this capacitance to be important. The nonuniformity of the electric field makes the dependence of the capacitance on line separation highly nonlinear, as a result the capacitance value decreases much more rapidly with separation than it would if it depended linearly on the line separation. Modeling. In the absence of significant interconnect resistance effects, all of the parasitic capacitances can be modeled with enough accuracy for most analog circuit design applications by dissecting the interconnect into pieces with similar capacitance characteristics and adding up the capacitance of each piece to obtain a single capacitance term. For example, the dissected view of a piece of interconnect with substrate capacitance is shown in Fig. 55.92. The interconnect has been dissected into squares that fall into three classes: two types of edges, and one center type. The capacitance to the substrate for each of © 2003 by CRC Press LLC

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Edge

Corner Edge

Corner No Edge

FIGURE 55.92 Determining substrate capacitance. The capacitance of each square in the dissected interconnect segment is summed.

these squares in parallel and thus the total capacitance of the interconnect segment is simply the sum of the capacitance of each square. If the substrate capacitance contribution of each square has been previ­ ously measured or calculated, the calculation of the total interconnect segment substrate capacitance involves summing each type of squares capacitance multiplied by the number of squares of that type in the segment. The accuracy of this modeling technique depends solely on the accuracy of the models used for each type of square. For example, in Fig. 55.92, the accuracy could be improved by adding one more type of edge square to those that are modeled. One of these squares has been shaded differently in the figure and is called the corner edge square. For the nonedge pieces of the interconnect the capacitance is approximately a parallel-plate capacitance and can be computed from (55.178). C=

A ⋅ εr ⋅ ε0 t

(55.178)

In (55.178), A is the area of the square or piece of interconnect, t is the thickness of the insulation layer beneath the interconnect, εr is the relative dielectric constant of the insulation material, and ε0 is the dielectric constant of free space. For silicon integrated circuits insulated with silicon dioxide the param­ eters are given in Table 55.8. The capacitance of edge interconnect pieces will always be larger than nonedge pieces. The amount by which the edge capacitance increases will depend on the ratio of the size of the piece of interconnect and the thickness of the insulation layer beneath the interconnect. If the interconnect width is significantly larger than the thickness of the insulation then edge effects are probably small and can be ignored. However, when thin lines are used in integrated circuits the edge effects are usually significant. The factor by which the edge capacitance can increase over the parallel-plate approximation can easily be as high as 1.5 for thin lines. TABLE 55.8 Parameters for Calculation of Substrate Capacitance in Silicon Integrated Circuits Insulated with Silicon Dioxide

© 2003 by CRC Press LLC

Parameter

Value

εr ε0 t

3.9 8.854 · 10–12 F/m 1–5 · 10–6 m

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FIGURE 55.93 Determining parallel line capacitance. The differently shaded pairs of squares are different types and will each have a different capacitance between them.

The modeling of overlap capacitance is handled in the same fashion as substrate capacitance. The region where interconnect lines overlap is dissected into edges and nonedges and the value of capacitance for each type of square summed up to give a total capacitance between the two circuit nodes associated with each piece of interconnect that overlaps. The area of overlap between the two layers of interconnect can be used as A in (55.178), while that separation between the layers can be used as t. The strong distortion of the electric fields will increase the actual value above this idealized computed value by a factor that depends on the thickness of the lines. This factor can be as high as 2 for thin lines. Parallel line capacitance can also be handled in a manner similar to that used for substrate and overlap capacitance. However, we must now locate pairs of edge squares, one from each of the adjacent inter­ connect lines. In Fig. 55.93, one possible pairing of the squares from adjacent pieces of interconnect is shown. The capacitance for each type of pair of squares is added together, weighted by the number of pairs of each type to get a single capacitance that connects the circuit nodes associated with each interconnect line. The effect on the capacitance of the spacing between pairs must be either measured or computed for each possible spacing, and type of pair of squares. One approach to this is to use a table of measured or computed capacitances and separation distances. The measured parallel line capacitance between silicon integrated circuit lines for a variety of separations is presented in Fig. 55.94. From the figure, we see that the capacitance value decreases exponentially with line separation. Thus an exponential fit to measured or simulated data is good choice for computing the capacitance [7], [8]. Parallel Line Capacitance in fF 600 500 400

Measured Data

300

Exponential Fit

200 100 0 0

2

4 6 Line separation in microns

8

10

FIGURE 55.94 Parallel line capacitance measured from a silicon integrated circuit. The diamonds are an exponental fit to the data [using (55.179)]. The fit is excellent at short separations when the capacitance is largest.

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Equation (55.179) can be used to predict the parallel line capacitance C for each type of pair of edge squares. L is the length of the edge of the squares, and the parameters Cc and Sd are computed or fit to measured coupling capacitance data like that in Fig. 55.94. − sS C = Cc ⋅ L ⋅ e ( d )

(55.179)

Effects on Circuits. The effects that parasitic capacitances are likely to produce in circuits range from parametric variations, such as reduced bandwidth, to catastrophic failures, such as amplifier oscillation. Each type of parasitic capacitance produces a characteristic set of problems. Being aware of these typical problems will ease diagnosis of actual, or potential, parasitic capacitance problems. Substrate capacitance usually causes lower than expected bandwidth in amplifiers and lowering of the poles in filters. The capacitance is always to ac ground and thus increases device and circuit capacitances to ground. Thus, circuit nodes that have a dominant effect on amplifier bandwidth, or filter poles, should be designed to have as little substrate capacitance as possible. Another, more subtle, parametric variation that can be caused by substrate capacitance is frequency-dependent mismatch. For example, if the parasitic capacitance to ground is different between the two inputs of a differential amplifier, then, for fast transient signals, the amplifier will appear unbalanced. This could limit the accuracy high-speed comparators, and is sometimes difficult to diagnose since the error only occurs at high speeds. Overlap and parallel line capacitance can cause unwanted ac connections to be added to a circuit. These connections will produce crosstalk effects and can result in unstable amplifiers. The output interconnect and input interconnect of high-gain or high-frequency amplifiers must thus be kept far apart at all times. Care must be taken to watch for series capacitances of this type. For example, if the output and input interconnect of an amplifier both cross the power supply interconnect, unwanted feedback can result if the power supply line is not well ac grounded. This is a very common cause of integrated circuit amplifier oscillation. Because of the potential for crosstalk between parallel or crossing lines, great care should also be taken to keep weak (high-impedance) signal lines away from strong (low­ impedance) signal lines. Parasitic Resistance For analog integrated circuit designers, the second most important interconnect parasitic is resistance. This unexpected resistance can cause both parametric problems, such as increased offset voltages, and catastrophic problems such as amplifier oscillation (for example, poorly sized power supply lines can cause resistive positive feedback paths in high gain amplifiers called “ground loops”). To make matters worse, the resistivity of integrated circuit interconnect has been steadily increasing as the line widths of circuits have decreased. Physics. Except for superconductors, all conductors have resistance. A length of interconnect used in an integrated circuit is no exception. The resistance of a straight section of interconnect is easily found by obtaining the resistance per square for the particular interconnect layer concerned, and then adding up the resistance of each of the series of squares that makes up the section. This procedure is illustrated in Fig. 55.95. For more complicated interconnect shapes the problem of determining the resistance between two points in the interconnect is also more complex. The simplest approach is to cut the interconnect up into rectangles and assume each rectangle has a resistance equal to the resistance per square of the interconnect material times the number of full and partial squares that will fit along the direction of current flow in the rectangle [5]. This scheme works whenever the direction of current flow is clear; however, for corners and intersections of interconnect the current flow is in fact quite complex. Figure 55.96 shows the kind of current flow that can occur in an interconnect section with complex geometry. Modeling. To account for the effects of complex current flows the resistance of complex interconnect geometries must be determined by measurement or simulation. One simple empirical approach is to cut © 2003 by CRC Press LLC

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ow

nt fl

tion

c dire

rre f cu

o

FIGURE 55.95 Determining the resistance of a length of interconnect. Each square has the same resistance regardless of size.

FIGURE 55.96 Current flow in a complex interconnect geometry.

FIGURE 55.97 The process of breaking a complex geometry into subgeometries, constructing the equivalent con­ nected resistance, and forming a single resistance for an interconnect section. In this example, only two subgeometries are used: a corner subgeometry and a basic rectangular subgeometry.

out sections of resistive material in the same shape as the interconnect shape to be modeled, and then measure the resistance. The resistance for other materials can be found by multiplying by the ratio of the respective resistances per square of the two materials. Once the resistance has been found for a particular geometry it can be used for any linear scaling of that geometry. For most types of integrated circuit interconnect all complex geometries can be broken up into relatively few important subgeometries. If tables of the resistance of these subgeometries for various dimensions and connection patterns are obtained, the resistance of quite complex shapes can be accurately calculated by connecting the resistance of each subgeometry together and calculating the resistance of the connected resistances. This calculation can usually be performed quickly by replacing series and parallel connected resistor pairs with their equivalents. The process of breaking a complex geometry into subgeometries, constructing the equivalent connected resistance, and forming a single resistance for an interconnect section is illustrated in Fig. 55.97. © 2003 by CRC Press LLC

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Effects on Circuits. The resistance of interconnect can have both parametric and catastrophic effects on circuit performance. Even small differences in the resistance on either input side of a differential amplifier can lead to increased offset voltage. Thus, when designing differential circuits care must be taken to make the interconnect identical on both input sides, as this ensures that the same resistance is present in both circuits. The resistance of power supply interconnect can lead to both parametric errors in the voltages supplied and catastrophic failure due to oscillation. If power supply voltages are assumed to be identical in two parts of a circuit and, due to interconnect resistance, there is a voltage drop from one point to the next, designs that rely on the voltages being the same may fail. In high-gain and feedback circuits the resistance of the ground and power supply lines may become an unintentional positive feedback resistance which could lead to oscillation. Thus output and input stages for high-gain amplifiers will usually require separate ground and power supply interconnects. This ensures that no parasitic resistance is in a feedback path. When using resistors provided in an integrated circuit process, the extra resistance provided by the interconnect may cause inaccuracies in resistor values. This would be most critical for small resistance values. The only solution in this case is to accurately compute the interconnect resistance. Since most resistance layers provided in analog integrated circuit processes are just a form of high resistivity inter­ connect, the methods described here for accurately computing the resistance of interconnect are also useful for predicting the resistance of resistors to be fabricated. Parasitic Inductance In high-speed integrated circuits the inductance of long lines of interconnect becomes significant. In integrated circuit technologies that have an insulating substrate, such as gallium arsenide (GaAs) and silicon on insulator (SOI), reasonably high-performance inductive devices can be made from intercon­ nect. In technologies with conductive substrates, resistive losses in the substrate restrict the application of interconnect inductance. High-frequency circuits are often tuned using interconnect inductance and capacitance (LC) to form a narrow bandpass filter or tank circuit, and LC transmission lines, or stubs, made from interconnect are useful for impedance matching. There is much similarity between this use of parasitic inductance and the design of microstripline-printed circuit boards. The major difference being that inductance does not become significant in integrated circuit interconnect until frequencies in the gigahertz are reached. In order to make a good interconnect inductance, there are two requirements. First, there must not be any resistive material within range of the magnetic field of the inductance. If this occurs then induced currents flowing in the resistive material will make the inductor have high series resistance (low Q factor). This would make narrow bandwidth bandpass filters difficult to make using the inductance, and make transmission lines made from the interconnect lossy. The solution is to have an insulating substrate, or to remove the substrate from beneath the inductor. The second requirement for large inductance is to form a coil or other device to concentrate the magnetic field lines. Within the confines of current integrated circuit manufacturing, spiral inductors, like that illustrated in Fig. 55.98 are the most common method used to obtain useful inductances. Transmission Line Behavior Two types of transmission line behavior are important in integrated circuits, RC transmission lines and LC/RLC transmission lines. For gigahertz operation inductive transmission lines are important. These can be lossy RLC transmission lines if a conductive substrate such as silicon is used, or nearly lossless LC transmission lines if an insulating substrate such as gallium arsenide is used. The design of inductive transmission lines is very similar to designing microstripline-printed circuit boards. At lower frequencies of 10 to 1000 MHz resistive capacitive (RC) transmission lines are important for long low resistivity interconnect lines or short high resistivity lines. RC transmission lines are of concern to analog circuit designers working in silicon integrated circuits. When used correctly, an interconnect can behave as though it were purely capacitive in nature. However, © 2003 by CRC Press LLC

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FIGURE 55.98 Spiral inductance used in insulated substrate integrated circuits for gigahertz frequency operation.

when a higher resistivity interconnect layer, such as polysilicon or diffusion is used, the distributed resistance and capacitance can start to produce transmission line effects at relatively short distances. Similarly, for very long signal distribution lines or power supply lines, if they are not correctly sized, transmission line behavior ensues. Physics. One method for modeling distributed transmission line interconnect effects is lumped equivalent modeling [6]. This method is useful for obtaining approximate models of complex geometries quickly, and is the basis of accurate numerical finite element simulation techniques. For analog circuit designers the conversion of interconnect layout sections into lumped equivalent models also provides an intuitive tool to understanding distributed transmission line interconnect behavior. To be able to model a length of interconnect as a lumped RC equivalent, the error between the impedance of the interconnect when correctly treated as a transmission line, and when replaced with the lumped equivalent, must be kept low. If this error is e, then it can be shown that the maximum length of interconnect that can be modeled as a simple RC T or Π network is given in (55.180). In the equation, R is the resistance per square of the particular type of interconnect used, C is the capacitance per unit area, and ω is the frequency of operation in radians per second. D≤

3⋅e ω ⋅ R ⋅C

This length can be quite short. Consider the case of a polysilicon interconnect line in a 1.2 µm CMOS process that has a resistance per square of 40 Ω a capacitance per unit are of 0.1 fF/µm2. For an error e of 10 percent the maximum line length of minimum width line that can be treated as a lumped T or Π network for various frequencies is given in Table 55.9. Longer interconnect lines than this must be cut up into lengths less than or equal to the length given by (55.180).

(55.180) TABLE 55.9 The Maximum Length of Minimum Width Polysilicon Line That Can Be Modeled with a Single Lumped RC T or Π Network and Remain 10 percent Accurate Frequency (MHz)

Length (micrometers)

10 100 1000

1262 399 126

Modeling. The accurate modeling of distributed transmission line effects in integrated circuits is best performed with lumped equivalent circuits. These circuits can be accurately extracted by dissecting the interconnect geometry into lengths that are, at most, as long as the length given by (55.180). These lengths are then modeled by either a T or Π lumped equivalent RC network. The extraction of the resistance and capacitance for these short interconnect sections can now follow the same procedures as were © 2003 by CRC Press LLC

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D

D

FIGURE 55.99 The extraction of an accurate RC transmission line model for resistive interconnect. The maximum allowable length D is computed from (55.180).

described in the previous sections on parasitic interconnect resistance and capacitance. The resulting RC network is then an accurate transmission line model of the interconnect. Fig. 55.99 shows an example of this process. Effects on Circuits. Several parametric and catastrophic problems can arise due to unmodeled transmis­ sion line behavior. Signal propagation delays in transmission lines are longer than predicted by a single lumped capacitance and resistance model of interconnect. Thus, ignoring the effects of transmission lines can result in slower circuits than expected. If the design of resistors for feedback networks results in long lengths of the resistive interconnect used to make the resistors, these resistors may in fact be RC trans­ mission lines. The extra delay produced by the transmission line may well cause oscillation of the feedback loops using these resistors. The need for decoupling capacitors in digital and analog circuit power supplies is due to the RC transmission line behavior of the power supply interconnect. Correct modeling of the RC properties of the power distribution interconnect is needed to see whether fast power supply current surges will cause serious changes in the supply voltage or not. Nonlinear Interconnect Parasitics A number of types of interconnect can have nonlinear parasitics. These nonlinear effects are a challenge to model accurately because the effect can change with the operating conditions of the circuit. A con­ servative approach is to model the effects as constant at the worst likely value they can attain. This is adequate for predicting parameters, like circuit bandwidth, that need only exceed a specification value. If the specifications call for accurate prediction of parasitics then large nonlinear parasitics are generally undesirable and should be avoided. © 2003 by CRC Press LLC

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Diffusion Interconnect Depletion Region

(a) Silicon Substrate

Diffusion Interconnect Depletion Region

(b) Silicon Substrate

FIGURE 55.100 Diffusion interconnect has a voltage-dependent capacitance produced by the depletion region between the interconnect and the substrate. At low voltage difference between the interconnect and substrate (a), the capacitance is large. However, the capacitance decreases for larger voltage differences (b).

Most nonlinear interconnect parasitics are associated with depletion or inversion of the semiconductor substrate. A diffusion interconnect is insulated from conducting substrates such as silicon by a reversed biased diode. This diode’s depletion region width varies with the interconnect voltage and results in a voltage-dependent capacitance to the substrate. For example, the diffusion interconnect in Fig. 55.100 has voltage dependent capacitance to the substrate due to a depletion region. The capacitance value depends on the depletion region thickness, which depends on the voltage difference between the inter­ connect and the substrate.   V  C = C0 ⋅ 1 −  s    φB  

M

(55.181)

The typical equation for depletion capacitance is given in (55.181). In this equation VS is the voltage from the interconnect to the substrate, φB is the built-in potential of the semiconductor junction, M is the grading coefficient of the junction, while C0 is the zero-bias capacitance of the junction. Since the capacitance is less than C0 for reverse bias and the junction would not insulate for forward bias, we can assume that the capacitance is always less than C0 and use C0 as a conservative estimate of C. Because of the uncertainty in the exact structure of most semiconductor junctions φB and M are usually fit to measured capacitance versus voltage (CV) data. Another common nonlinear parasitic occurs when metal interconnect placed over a conducting semi­ conductor substrate creates inversions at the semiconductor surface. This inversion layer increases the substrate capacitance of the interconnect and is voltage dependent. To prevent this most silicon-integrated circuit manufacturers place an inversion-preventing implant on the surface of the substrate. The depletion between the substrate and n-type or p-type wells diffused into the substrate also creates a voltagedependent capacitance. Thus use of the well as a high resistivity interconnect for making high value resistors will require consideration of a nonlinear capacitance to the substrate.

Pad and Packaging Parasitics All signals and supply voltages that exit an integrated circuit must travel across the packaging intercon­ nections. Just like the on-chip interconnect, the packaging interconnect has parasitic resistance, capaci­ tance, and inductance. However, some of the packaging materials are significantly different in properties © 2003 by CRC Press LLC

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package Interconnect pads

wire bond

FIGURE 55.101 A packaged integrated circuit. The main sites of parasitics are the pad, bond, and package inter­ connect.

and dimension to those used in the integrated circuit, thus there are major differences in the importance of the various types of parasitics. Fig. 55.101 is a typical packaged integrated circuit. The chief components of the packaging are the pads on the chip, the wire or bump bond used to connect the pad to the package, and then the package interconnect. The pads used to attach wire bonds or bump bonds to integrated circuits are often the largest features on an integrated circuit. The typical pad is 100 µm on a side and has a capacitance of 100 fF. In addition, protection diodes are often used on pads that will add a small nonlinear component to the pad capaci­ tance. The wire bonds that attach the pads to the package are typically very low resistivity and have negligible capacitance. Their major contribution to package parasitics is inductance. Typically, the package inter­ connect inductance is greater than the wire bond inductance; however, when wire bonds are used to connect two integrated circuits directly together, then the wire bond inductance is significant. Often, the dominant component of package parasitics comes from the packaging interconnect itself. Depending on the package, there is inductance, capacitance to ground, and parallel line capacitance produced by this interconnect. Carefully made high-frequency packages do not exhibit much parallel line capacitance (at the expense of much capacitance to ground due to shielding), but in low-frequency packages with many connections this can become a problem. Typical inductance and capacitance values for a high-speed package capable of output bandwidths around 5 GHz are incorporated into a circuit model for the package parasitics in Fig. 55.102. When

vs

vpad

RS

IC = 0V Cpad 0.1pF

Vs {RS} DC = 0V AC = 1V

+ −

0 0

L1 package 0.2nH

vpackage

IC = 0A

IC = 0V Cpackage 1.0pF

R2 1T 0

L2 package 0.2nH

vout

IC = 0A

IC = 0V RL

{RL}

CL

10pF

0 0

PARAMETERS RS 10 RL 50

0

FIGURE 55.102 The circuit model of a high-frequency package output and associated parasitics. Cpad is the pad capacitance. L1package, Cpackage, R2, and L2package model the package interconnect. RS is the source resistance of the circuit. RL and CL are the external load. © 2003 by CRC Press LLC

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6.0 RL = 10MEG CL + 10pF 4.0 + 3dB 2.0

0 1.0 Ohms −2.0

0.1 Ohms 1000 Ohms − 3dB

100 Ohms

10 Ohms

−4.0

−6.0 10MHz

30MHz

100MHz 300MHz Vdb(vout) 3 −3 Frequency

1.0GHz

3.0GHz

10GHz

FIGURE 55.103 The PSPICETM ac simulation of circuit in Fig. 55.102 when the load resistance RL is 10 MΩ. This shows how the package inductance causes peaking for sufficiently low output resistance. In this case, peaking occurs for RS below 4 Ω and at about 2 GHz.

6.0

4.0

RL = 50 Ohms = 10pF + 3dB Total Attenuation

2.0

0

−2.0

1.0 Ohms 0.1 Ohms 10 Ohms

− 3dB Total Attenuation 100 Ohms

−4.0 1000 Ohms −6.0 10MHz

30MHz

100MHz 300MHz Vdb(vout) 3 −3 Frequency

1.0GHz

3.0GHz

10GHz

FIGURE 55.104 The PSPICE™ ac simulation of circuit in Fig. 55.102 when the load is 50 Ω. The package inductance still causes peaking for RS below 4 Ω.

simulated with a variety of circuit source resistances (RS) this circuit reaches maximum bandwidth without peaking when the output resistance is 4 Ω. At lower output resistance, Fig. 55.103 shows that considerable peaking in the output frequency response occurs. © 2003 by CRC Press LLC

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FIGURE 55.105 Test structures for measuring parallel line capacitance.

Parasitic Measurement The major concern when measuring parasitics is to extract the individual parasitic values independently from measured data. This is normally achieved by exaggerating the effect that causes each individual parasitic in a special test structure, and then reproducing the structure with two or more different dimensions that will affect only the parasitic of interest. In this fashion, the effects of the other parasitics are minimized and can be subtracted from the desired parasitic in each measurement. CP =

C1 − C 2 L1 − L2

(55.182)

For example, to measure parallel line capacitance, the test structures in Fig. 55.105 would be fabricated. These structures vary only in the length of the parallel lines. This means that if other parasitic capacitance ends up between the two signal lines used to measure the parasitic, then it will be a constant capacitance that can be subtracted from both measurements. The parallel line capacitance will vary in proportion to the variation of length between the two test structures. Thus the parallel line capacitance per unit length can be found from (55.182). In this equation CP is the parallel line capacitance per unit length, C1 and C2 are the capacitances measured from each test structure, and L1 and L2 are the length of the two parallel interconnect segments.

References [1] D. L. Carter and D. F. Guise, “ Effects of interconnections on submicron chip performance,” VLSI DESIGN, pp. 63–68, 1984. [2] H. B. Lunden, “Detailed extraction of distributed networks and parasitics in IC designs,” in Proc. Euro. Conf. Circuit Theory, Design, 1989, 84–88. [3] R. A. Sainati and T. J. Moravec, “Estimating high speed circuit interconnect performance,” IEEE Trans. Circuits Syst., vol. 36, pp. 533–541, April 1989. [4] D. S. Gao, A. T. Yang, and S. M. Kang, “Modeling and simulation of interconnection delays and crosstalks in high-speed integrated circuits,” IEEE Trans, Circuits Syst., vol. 37, pp. 1–8, Jan. 1990. [5] M. Horowitz and R. W. Dutton, “Resistance extraction from mask layout data,” IEEE Trans. Computer-Aided Design Integrat. Circuits Syst. vol. 7, pp. 1029–1037, Oct. 1988. [6] R. J. Antinone and G. W. Brown, “The modeling of resistive interconnections for integrated circuits,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 200–203, April 1983. [7] A. E. Ruehli and P. A. Brennan, “ Capacitance models for integrated circuit, metalization wires,” IEEE J. Solid-State Circuits, vol. SC-10, pp. 530–536, Dec. 1975. [8] S. Mori, I. Suwa, and J. Wilmore, “Hierarchical capacitance extraction in an IC artwork verification system,” in Proc. IEEE Int. Conf. Computer-Aided Design, 1984, pp. 266–268.

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57 High-Performance Analog Circuits Chris Toumazou Imperial College of Science, Technology, and Medicine

Alison Payne Imperial College of Science, Technology, and Medicine

John Lidgey Oxford Brookes University

B. M. Wilamowski University of Idaho

57.1 Broadband Bipolar Networks Introduction • Miller’s Theorem • Bipolar Transistor Modeling at High Frequencies • Single-Gain Stages • Neutralization of Cµ • Negative Feedback • RF Bipolar Transistor Layout • Bipolar Current-Mode Broadband Circuits • Broadband Amplifier Stability • Conclusions • Appendices

57.2 Bipolar Noise Thermal Noise • Shot Noise • Flicker — 1/f Noise • Other Types of Noise • Noise Characterization

57.1 Broadband Bipolar Networks Chris Toumazou, Alison Payne, and John Lidgey Introduction Numerous textbooks have presented excellent treatments of the design and analysis of broadband bipolar amplifiers. This chapter is concerned with techniques for integrated circuit amplifiers, and is written mainly as a tutorial aimed at the practicing engineer. For broadband polar design it is first important to identify the key difference between lumped and distributed design techniques. Basically when the signal wavelengths are close to the dimensions of the integrated circuit, then characteristic impedances become significant, lines become lossy, and we essen­ tially need to consider the circuit in terms of transmission lines. At lower frequencies where the signal wavelength is much larger than the dimensions of the circuit, the design can be considered in terms of lumped components, allowing some of the more classical low-frequency analog circuit techniques to be applied. At intermediate frequencies we enter the realms of hybrid lumped/distributed design. Many RF designs fall into this category, although every day we see new technologies and circuit techniques devel­ oped that increase the frequency range for which lumped approaches are possible. In broadband appli­ cations, ICs are generally designed without the use of special microwave components, so broadband techniques are very similar to those employed at lower frequencies. However, several factors still have to be considered in RF design: all circuit parasitics must be identified and included to ensure accurate simulation; feedback can generally only be applied locally as phase shifts per stage are significant; the cascading of several local feedback stages is difficult since ac coupling is often impractical; the NPN bipolar transistor is the main device used in silicon, since it has potentially a higher ft than PNP bipolar or MOSFET devices; active PNP loads are generally avoided due to their poor frequency and noise performance and so resistive loads are used instead.

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Cf

Rth −A Vin Vo = −AVin

Vs

Rth Vin Vs

Cf(1+A)

FIGURE 57.1 Example of the Miller effect.

The frequency performance of an RF or broadband circuit will depend on the frequency capability of the devices used, and no amount of good design can compensate for transistors with an inadequate range. As a rule, designs are kept as simple as possible, since at high frequencies all components have associated parasitics.

Miller’s Theorem It is important to describe at the outset a very useful approximation that will assist in simplifying the high-frequency analysis of some of the amplifiers to be described. The technique is known as Miller’s theorem and will be briefly discussed here. A capacitor linking input to output in an inverting amplifier results in an input referred shunt capacitance that is multiplied by the voltage gain of the stage, as shown in Fig. 57.1. This increased input capacitance is known as the Miller capacitance. It is straightforward to show that the input admittance looking into the inverting input of the amplifier is approximately Yin = jωCf (1 + A). The derivation assumes the inherent poles within the amplifier are at a sufficiently high frequency so that the frequency response of the circuit is dominated by the input of the amplifier. If this is not the case then Miller’s approximation should be used with caution as will be discussed later. From the preceding model, it is apparent that the Thévenin input signal sources sees an enlarged capacitance to ground. Miller’s approximation is often a useful way of simplifying circuit analysis by assuming that the input dominant frequency is given by the simple low-pass RC filter in Fig. 57.1. However, the effect is probably one of the most detrimental in broadband amplifier design, affecting both frequency performance and/or stability.

Bipolar Transistor Modeling at High Frequencies In this section, we consider the high-frequency small-signal performance of the bipolar transistor. The section assumes the reader has some knowledge of typical device parameters, and has some familiarity with the technology. For small-signal analysis, the simplified hybrid-π model shown in Fig. 57.2 is used, where rb rc rπ ro

= base series resistance = collector series resistance = dynamic base–emitter resistance = dynamic collector–emitter resistance

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rb

rc

Cµ

c

b Cπ

ro

Vπ rπ

Ccs

gmVπ

e

FIGURE 57.2 Hybrid π model of BJT.

rb c

b Cbe rπ

ro

gmVπ

Cce

e

FIGURE 57.3 Simplified Miller-approximated hybrid π model of BJT.

rb

sCµ(Vπ−Vce)

b Cπ

c ro

Vπ gmVπ

rπ e

FIGURE 57.4 Simplified high-frequency model.

Cπ = base–emitter junction capacitance Cµ = collector–base junction capacitance Ccs = collector–substrate capacitance gm = small-signal transconductance At low frequencies, the Miller approximation allows the hybrid-π model to be simplified to the circuit shown in Fig. 57.3, where the net input capacitance now becomes Cbe = Cπ + Cµ (1 – Av), the net output capacitance becomes Cce = Cµ(1 – 1/Av), where Av is the voltage gain given by Av = (Vce/Vbe) ≈ – gmR1 where R1 is the collector load resistance. rC and Ccs have been neglected. Thus, Cbe ≈ Cπ + gmR1Cµ and Cce ≈ Cµ. The output capacitance Cce is often neglected from the small-signal model. The approximation Av = – gmR1 assumes that rπ  rb, and that the load is purely resistive. At high frequencies, however, we cannot neglect the gain roll-off due to Cπ and Cµ, and even at frequencies as low as 5 percent of ft the Miller approximation can introduce significant errors. A simplified hybrid-π model that takes the high-frequency gain roll-off into account is shown in Fig. 57.4. Cµ is now replace by an equivalent current source sCµ (Vπ – Vce). A further modification is to split the current source between the input and output circuits as shown in Fig. 57.5. Finally, the input and output component terms can be rearranged leading to the modified equivalent circuit shown in Fig. 57.6, which is now suitable for broadband design. From Fig. 57.6, the transconduc­ tance (gm – sCµ) shows the direct transmission of the input signal through Cµ. The input circuit current © 2003 by CRC Press LLC

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rb c

b ro

Vπ rπ

Cπ

sCµ(Vπ−Vce) e

gmVπ

sCµ(Vπ−Vce)

FIGURE 57.5 Split current sources.

rb b

c

sCµVce Cbe

Cµ

Vπ

ro

rπ (gm−sCµ)Vπ e

FIGURE 57.6 Modified equivalent circuit.

R1 Vin

Rs

Vout

FIGURE 57.7 Common-emitter amplifier.

source (sCµVce) shows the feedback from the output to the input via Cµ. Depending on the phase shift between Vce and Vbe , this feedback can cause high-frequency oscillation. At lower frequencies, sCµ  gm and Vce /Vπ ≈ –gmR1, which is identical to the Miller approximation. The model of Fig. 57.6 is the most accurate for broadband amplifier design, particularly at high frequencies.

Single-Gain Stages Consider now the high-frequency analysis of single-gain stages. Common-Emitter (CE) Stage Figure 57.7 shows a common-emitter amplifier with load R1 and source Rs. External biasing components are excluded from the circuit. First analysis using the Miller approximation yields the small-signal high-frequency model shown in Fig. 57.8, where Rs′

Vout

Vin

Cbe R1′

Vπ

Cµ rπ

gmVπ

FIGURE 57.8 High-frequency model of the common emitter. © 2003 by CRC Press LLC

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( )

R1′ = R1 r0 , Rs′ = Rs + rb and Cbe = C π + g m R1′ Cµ  Vπ  rπ   1 =   Vin  rπ + Rs′   1 + s rπ Rs′ Cbe 

(

(57.1)

)

−g m R1′ Vout = ,

Vπ 1 + sCµ R 1′ and thus   g m R1′ rπ  Vout 1  = −  Vin  rπ + Rs′   1 + sCµ R1′ 1 + s rπ Rs′ Cbe 

)( (

(

) )

   

(57.2)

This approximate analysis shows: • • • • •

“Ideal” voltage gain = –gm R1 Input attenuation caused by Rs′ in series with rπ Input circuit pole p1 at s = 1/Cbe(rπ  R′s ) ≈ 1/Cbe R′s Output attenuation caused by r0 in parallel with R1 Output circuit pole p2 at s = 1/CµR′1

The input circuit pole is generally dominant, and thus the output pole p2 can often be neglected. With a large load capacitance C1, p2 ≈ 1/C1R′1 , and the gain and phase margin will be reduced. However, under these conditions the Miller approximation will no longer be valid, since the gain roll-off due to the load capacitance is neglected. If we now consider analysis using the broadband hybrid-π model of Fig. 57.6, then the equivalent model of the common emitter now becomes that shown in Fig. 57.9, where Cbe = C π + Cµ , Rs′ = Rs + rb

and

R1′ = R1 r0

From the model it can be shown that

(

)

Vout − g m − sCµ R1′ = Vπ 1 + sCµ R1′

(V

in

(57.3)

− Vπ ) Rs′ + sCµVout = Vπ rπ + sCbeVπ

(57.4)

and

(

(

Vinrπ + VoutsCµrπ Rs′ = Vπ (rπ + Rs′ ) 1 + sCbe rπ Rs′

Rs′

Vout sCµVce

Vin

Cbe

Cµ R1′

Vπ rπ (gm-sCµ)Vπ

FIGURE 57.9 Equivalent circuit model of the common emitter. © 2003 by CRC Press LLC

))

(57.5)

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Rearranging these equations yields  g m R1′ rπ 

Vout = − 

Vin  rπ + Rs′    1 − sCµ g m ×    (1 + sC R ) 1 + sC R + sC g R R − s 2C 2 R R  be s ′ µ 1′ µ m 1′ s′ µ s′ 1′  

(

(57.6)

)

This analysis shows that there is a right-hand-plane (RHP) zero at s = 1/(Cµre), which is not predicted by the Miller approximation. Assuming Rπ  RS′ and Cπ  Cµ, the denominator can be written as

( (

)

)

1 + s Rs′ C π + Cµ g m R1′ + Cµ R1′ + s 2CµC π R1′ Rs′

(57.7)

which can be described by the second-order characteristic equation 1 + s(1 p1 +1 p2 ) + s 2 p1 p2

(57.8)

By comparing coefficients in (57.7) and (57.8) the sum of the poles is the same as that obtained in (57.2) using the Miller approximation, but the pole product p1 p2 is greater. This means that the poles are farther apart than predicted by the Miller approximation. In general, the Miller approximation should be reserved for analysis at frequencies of operation well below ft , and for situations where the capacitive loading is not significant. The equivalent circuit of Fig. 57.9 therefore gives a more accurate result for high-frequency analysis. For a full understanding of RF behavior, computer simulation of the circuit including all parasitics is essential. Since the CE stage provides high current and voltage gain, oscillation may well occur. Therefore, care must be taken during layout to minimized parasitic coupling between the input and output. The emitter should be at ground potential for ac signals, and any lead inductance from the emitter to ground will generate phase-shifted negative feedback to the base, which can result in instability. Common-Collector (CC) Stage The common collector or emitter follower shown in Fig. 57.10 is a useful circuit configuration since it generally serves to isolate a high gain stage from a load. The high-frequency performance of this stage must be good enough so as not to degrade the frequency performance or stability of the complete amplifier. An equivalent high-frequency small-signal model of the common collector is shown in Fig. 57.11. The following set of equations can be derived from Fig. 57.11:

(Vin − Vb )

Rs′ = Vπ rπ + sCbeVπ + sCµVout ,

Vb = Vout + Vπ

(57.9)

and

(

)

Vπ rπ + sCbeVπ + sCµVout + g m − sCµ Vπ − sCµVout − Vout R1′ = 0

Vin

Rs Vout R1

FIGURE 57.10 Common-collector amplifier. © 2003 by CRC Press LLC

(57.10)

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Vin

Rs′

Vb sCµVce Cbe

Cµ R1′

Vπ rπ (gm-sCµ)Vπ

Vout

FIGURE 57.11 Equivalent circuit of the common collector.

Rearranging these equations yields R1′ (1 + g mrπ + sC πrπ ) Vout = Vin ( R + r ) 1 + s R r C + R 1 + sC R (1 + g r + sC r ) s′ π s′ π be µ s′ m π π π 1′

( (

) )

(

)

(57.11)

The preceding expression can be simplified by assuming Rπ  RS′ , gmrπ  1, Cπ  Cµ to,  1 + sC π g m Vout  rπ   =   Vin  rπ + Rs′   1 + sCµ Rs′ (1 + sC π g m ) + (1 + sC π Rs′ ) g m R1′ 

(

)

(57.12)

This final transfer function indicates the presence of a left-half-plane (LHP) zero at s = (gm /Cπ) = ωt . The denominator can be rewritten as approximately

(1 + 1 g mR1′ ) + s(Cµ Rs′ + Cπ

)

g m + Cbe Rs′ g m R1′ + s 2CµC π Rs′ g m

(57.13)

which simplifies to

(

(

)

)

1 + s C πre + Cµ Rs′ + Cµ + C π re Rs′ R1′ + s 2CµC π Rs′ R1′

(57.14)

Assuming a second-order characteristic form of 1 + s(1/p1 + 1/p2) + s2/p1 p2, if p1  p2, the above reduces to 1 + s/p1 + s2/p1 p2. If (RS ′/R1 ′)  1, then p1 ≈ 1/(Cπ re), and this dominant pole will be approximately canceled by the zero. The frequency response will then be limited by the nondominant pole p2 ≈ 1/CµRs ′. The frequency response of a circuit containing several stages is thus rarely limited by the CC stage, due to this dominant pole-zero cancellation. For this analysis to be valid, RS ′  R1′ . As Rs ′ increases the poles will move closer together, and the pole-zero cancellation will degrade. In practice, the CC stage is often used as a buffer, and is thus driven from a high source resistance into a low value load resistance. A very important parameter of the common-collector stage is output impedance. It is generally assumed that the output impedance of a common collector is low, also that there is good isolation between a load and the amplifying stage, and that any amount of current can be supplied to the load. Furthermore, it is assumed that capacitive loads will not degrade the frequency performance since the load will be driven by an almost short circuit. While this may be the case at low frequencies, it is a different story at high frequencies. Consider the following high-frequency analysis. We first assume that the small-signal model shown in Fig. 57.12 is valid. From the Fig. 57.12, the output impedance can be approximated as Z + Rs′ Vout = π I out 1 + g m Z π

© 2003 by CRC Press LLC

(57.15)

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Rs

Rs gmVπ

Zπ

Iout

FIGURE 57.12 Equivalent circuit of the CC output stage.

Vout

Vout

Iout

R1 R2 L

Zout

FIGURE 57.13 Equivalent high-frequency model of CC output stage.

where Zπ = (rπ  Cbe) and Rs′ = Rs + rb. At very low frequencies (ω → 0): Rout =

rπ + Rs′ ≈ 1 g m + Rs′ g mrπ ≈ re + Rs′ β 1 + g mrπ

(57.16)

1 sCbe + Rs′ ≈ Rs′ 1 + g m sCbe

(57.17)

At very high frequencies (ω → ∞): Rout =

If re > Rs ′, then the output impedance decreases with frequency, that is, Zout is capacitive. If Rs ′ > re , then Zout increases with frequency, and so Zout appears inductive. It is usual for an emitter follower to be driven from a high source resistance, thus the output impedance appears to be inductive and can be modeled as shown in Fig. 57.13, where R1 = re + Rs′ β,

R2 = Rs′ ,

L = Rs′ ωt

The inductive behavior of the CC stage output impedance must be considered in broadband design since any capacitive loading on this stage could result in peaking or instability. The transform from base resistance to emitter inductance arises because of the 90° phase shift between base and emitter currents at high frequencies, due principally to Cπ . This transform property can be used to advantage to simulate an on-chip inductor by driving a CC stage from a high source resistance. Similarly, by loading the emitter with an inductor we can increase the effective base series resistance Rs ′ without degrading the noise performance of the circuit. A capacitive load will also be transformed by 90° between the base and emitter; for example, a capacitive loading on the base can look like a negative resistance at the emitter. Common-Base (CB) Stage The common-base amplifier shown in Fig. 57.14 offers the highest frequency performance of all the single-stage amplifiers. When connected as a unity gain current buffer, the CB stage operates up to the ft of the transistor. Using the simplified hybrid π model of Fig. 57.3, it follows that I out β ≈ I in β +1

© 2003 by CRC Press LLC

where

β=

βo 1 + s ωo

(57.18)

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Iout

Iin

FIGURE 57.14 Common-base configuration.

Vin

Rs

Ve

R1 Vout

Zπ

Vπ

(gm-sCµ)Vπ Vout

rb

R1

Rs Vin

FIGURE 57.15 CB stage as a voltage amplifier.

I out ao ≈ where ao = βo (βo +1) and ωt = βoω o I in 1 + s ωt

(57.19)

The CB stage thus provides wideband unity current gain. Note that the input impedance of the CB stage is the same as the output impedance of the CC stage, and thus can appear inductive if the base series resistance is large. In many situations, the CB stage is connected as a voltage amplifier, an example of this being the current-feedback amplifier, which will be discussed in a later section. Consider the following highfrequency analysis of the CB stage being employed as a voltage gain amplifier. Figure 57.15 shows the circuit together with a simplified small-signal model. From the equivalent model the gain of the circuit can be approximated as  1 − sCµ g m Vout kR1  =  Vin Rs  1 + s(C π g m )(kRs′ Rs ) 

(57.20)

where Rs′ = Rs + rb , and k ≈

Rs Rs +1 g m

If RS  1/gm , then k ≈ 1 and so  1 − sCµ g m Vout R  = 1 Vin Rs  1 + s(C π g m )(1 + rb Rs ) 

(57.21)

Thus, it can be seen that the circuit has a right-hand-plane zero at s = 1/(re Cµ), since re = 1/gm and a pole at 1/Cπ re (1 + rb /Rs ) = ωt /(1 + rb /Rs). Note that in the case of a current source drive (RS  rb), the pole is at the ωt of the transistor. However, this does assume that the output is driven into a short circuit. Note also the excellent isolation between the input and output circuits, since there is no direct path through Cµ and so no Miller effect. © 2003 by CRC Press LLC

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Neutralization of C Many circuit techniques have been developed to compensate for the Miler effect in amplifiers and hence extend the frequency range of operation. The common-emitter stage provides the highest potential power gain, but the bandwidth of this configuration is limited since the amplified output voltage effectively appears across the collector–base junction capacitance resulting in the Miller capacitance multiplication effect. This bandwidth limiting due to Cµ can be overcome by using a two-transistor amplifying stage such as the CE–CB cascode stage or the CC–CE cascade. Consider now a brief qualitative description of each in turn. The circuit diagram of the CE–CB cascode is shown in Fig. 57.16. The CE transistor Q1 provides high current gain of approximately β and a voltage gain of Av1 ≈ –gm1 R1 = –gm1 re2, which in magnitude will be close to unity. Therefore, the Miller multiplication of Cµ is minimized, and the bandwidth of Q1 is maximized. The CB transistor Q2 provides a voltage gain Av2 ≈ R1/re2. The total voltage gain of the circuit can be approximated as Av ≈ –gm1 R1, which is equal to that of a single CE stage. The total frequency response is given by the cascaded response of both stages. Since both transistors exhibit wideband operation, then the dominant poles of each stage may be close in frequency. As a result, the total phase shift through the cascode configuration is likely to be greater than that obtained with a single device, and care should be taken when applying negative feedback around the pair. Consider now the CC–CE stage of Fig. 57.17. In this case voltage gain is provided by the CE stage transistor Q2 and is Av2 ≈ –gm2 R1. This transistor is being driven from the low output impedance of Q1 and so the input pole frequency of this device (≈1/Cbe2 Rs2) is maximized. The CC stage transistor Q1 is effectively a buffer that isolates Cµ of Q2 from the source resistance Rs. The low-frequency voltage gain of this circuit is reduced when compared with a single-stage configuration because the input signal effectively appears across two base-emitter junctions. The two-transistor configurations help to maintain a wideband frequency response by isolating the input and output circuits. In integrated circuit design, another method of neutralizing the effect of Cµ is possible when differential gain stages are used. For example, Fig. 57.18 shows a section of a differential input amplifier. If the inputs are driven differentially, then the collector voltages Vc1 and Vc2 will be 180° out of phase. The neutralization capacitors

R1 Vout Vbias

Vin

Q2

Rs Q1

FIGURE 57.16 CE–CB cascode.

Vin

Rs

R1

Q1

Vout Q2 Ibias

FIGURE 57.17 CC–CE stage.

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Vc1 +Vin/2

Vc2

Q1

−Vin/2

Q2

Cn

Cn Cn = Cµ

Vc1 +Vin/2

Q1

FIGURE 57.18 Differential gain stage.

Vc2 Q2

−Vin/2

FIGURE 57.19 Implementation of neutralization capacitors.

Cn thus inject a current into the base of each transistor that is equal and opposite to that caused by the intrinsic capacitance Cµ. Consequently, the neutralization capacitors should be equal to Cµ in order to provide good signal cancellation, and so they may be implemented form the junction capacitance of two dummy transistors with identical geometries to Q1 and Q2 as shown in Fig. 57.19.

Negative Feedback Negative feedback is often employed around high gain stages to improve the frequency response. In effect, the gain is reduced in exchange for a wider, flatter bandwidth. The transfer function of a closed-loop system can be written H (s ) =

A(s ) 1 + A(s )B(s )

(57.22)

where A(s) is the open-loop gain and B(s) is the feedback fraction. If the open-loop gain A(s) is large, then H(s) ≈ 1/B(s). In RF design, compound or cascaded stages can produce excessive phase shifts that result in instability when negative feedback is applied. To overcome this problem, it is generally accepted to apply local negative feedback around a single stage only. However, the open-loop gain of a single stage is usually too low for the approximation H(s) = 1/B(s) to hold.

RF Bipolar Transistor Layout When laying out RF transistors, the aim is to • Minimize Cµ and Cπ . • Minimize base width to reduce the forward transit time tƒ and thus maximize ƒt . • Minimize series resistance rb and rc . To minimize junction capacitance, the junction area must be reduced; however, this will tend to increase the series resistance. Transistors are generally operated at fairly high currents to maximize ƒt . However, if the emitter gets too crowded, then the effective value of β will be reduced. The requirements given above are generally best met by using a stripe geometry of the type shown in Fig. 57.20.

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n+ deep collector

base contacts

emitter

FIGURE 57.20 Stripe geometry.

B

E

FIGURE 57.21 Transistor layout with interleaving fingers.

The stripe geometry maximizes the emitter area-to-periphery ratio, which reduces emitter crowding while minimizing the junction capacitance. The length of the emitter is determined by current-handling requirements. The base series resistance is reduced by having two base contacts and junction depths are minimized to reduce capacitance. The buried layer, or deep collector, reduces the collector series resis­ tance. High-power transistors are produced by paralleling a number of transistors with interleaving “fingers,” as shown in Fig. 57.21. This preserves the frequency response of the stripe geometry while increasing the total current-handling capability.

Bipolar Current-Mode Broadband Circuits Recently there has been strong interest in applying so-called current-mode techniques to electronic circuit design. Considering the signal operating parameter as a current and driving into low impedance nodes has allowed the development of a wealth of circuits with broadband properties. Many of the following circuit and system concepts date back several years; it is progress in integrated circuit technology that has given a renewed impetus to “practical” current-mode techniques. The NPN bipolar transistor, for example, is used predominantly in analog IC design because electron mobility is greater than hole mobility in silicon. This means that monolithic structures are typically built on P-type substrates, because vertical NPN transistors are then relatively easy to construct and to isolate from each other by reverse biasing the substrate. Fabricating a complementary PNP device on a P-type substrate is less readily accomplished. An N-type substrate must be created locally and the PNP device placed in this region. Early bipolar processes created PNP devices as lateral transistors and engineers dealt with their inherently poor, low-frequency charac­ teristics by keeping the PNP transistors out of the signal path whenever possible. However, high-speed analog signal processing demands symmetrical silicon processes with fully com­ plementary BJTs. Newer, advanced processes have dielectrically isolated transistors rather than reversedbiased PN junction isolation. These processes are able to create separate transistors, each situated in a local semiconductor region. Then, both PNP and NPN devices are vertical and their performance characteristics are much more closely matched. Dielectric isolation processes have revolutionized high-speed analog circuit design and have been key in making high-performance current-conveyor and current-feedback op-amp architectures practical. In © 2003 by CRC Press LLC

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the following sections, we will briefly review the development of the current-conveyor and currentfeedback op-amp. The Current Conveyor The current conveyor is a versatile broadband analog amplifier that is intended to be used with other circuit components to implement many analog signal-processing functions. It is an analog circuit building block in much the same way as a voltage op-amp, but it presents an alternative method of implementing analog systems that traditionally have been based on voltage op-amps. This alternative approach leads to new methods of implementing analog transfer functions, and in many cases the conveyor-based implementation offers improved performance when compared to the voltage op-amp-based implemen­ tation in terms of accuracy, bandwidth, and convenience. Circuits based on voltage op-amp are generally easy to design since the behavior of a voltage op-amp can be approximated by a few simple design rules. This is also true for current conveyors, and once the appropriate design rules are understood, the application engineer is able to design conveyor-based circuits just as easily. The first-generation current conveyor or CCI was proposed by Smith and Sedra in 1968 [1] and the more versatile second-generation current conveyor, or CCII, was introduced by the same two authors in 1970 [2], as an extension of the CCI. The CCII, is without doubt the more valuable and adaptable building block of the two, and we will concentrate mostly on this device. Figure 57.22(a) shows the voltage–current describing matrix for the CCII, while Fig. 57.22(b) shows the schematic normally used for the CCII with the power supply connections omitted. The voltage at the low-impedance input node X follows that at the high-impedance input node Y, while the input current at node X is mirrored or “conveyed” to the high-impedance output node Z. The ± sign indicates the polarity of the output current with respect to the input current; by convention, a positive sign indicates that both the input and output currents simultaneously flow into or out of the device, thus Fig. 57.22(b) illustrates a CCII +. For the first-generation conveyor, or CCI, the input current at node X was reflected to input Y, that s, the two inputs had equal currents. In the case of the secondgeneration conveyor input, Y draws no current, and this second generation, or CCII formulation, has proved to be much more adaptable and versatile than its first-generation predecessor. Because of the combined voltage and current following properties, CCII’s may be used to synthesize a number of analog circuit functions that are not so easily or accurately realizable using voltage op-amps. Some of these application areas are shown in Fig. 57.23. As current-conveyors become more readily available and circuits designers become more familiar with the versatility of this device it is certain that further ingenious uses will be devised. The Ideal Transistor and the Current-Conveyor. So far a transistor-level realization of the CCII has not been discussed. The current-vlotage transfer relationship for the CCII+ is given by VX = VY , IY = 0 and I Z = I X

(57.23)

These equations show that a simple voltage-following action exists between input node Y and output node X, and that there is a simple current-following action between input node X and output node Z. Also, these characteristic equations tell us that the impedance relationship for the ideal current conveyor are Z INY = ∞, Z X = 0 and ZOUTZ = ∞ IY VX IZ

=

0 1 0

0 0 0 0 ±1 0 (a)

VY IX VZ

(57.24)

Y CCII +

VY

X

Z

IX

IZ (b)

FIGURE 57.22 The CCII current conveyor. (a) I–V describing matrix. (b) Schematic. © 2003 by CRC Press LLC

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CCCS

Instrumentation Amps

Differentiation VCCS

Integration Amplifiers

Ideal transistor

Analog Computation Summation

CurrentConveyors Current-Feedback Opamps

Oscillators

Impedance Conversion

Filters

Inductance Synthesis

FDNR Synthesis

FIGURE 57.23 Current-conveyor applications.

IZ VY

Y X

IX

Z IZ = −β/[β+1]IX since β>>1 ∴ IZ ≈ −IX

VX VY [1 + (1/gmRX)] since gmRX>>1 ∴ VX ≈ VY

VX =

FIGURE 57.24 Single BJT CCII–.

Figure 57.24 shows a schematic representation of a CCII — built with a single BJT and on reflection it is clear that the current conveyor is effectively an ideal transistor, with infinite β and infinite gm. Driving into the base of a BJT gives almost unity voltage gain from input base to output emitter, with high input impedance and low output impedance, and driving into the emitter of a BJT gives almost unity current gain from emitter input to collector output, with low input impedance and high output impedance. Drawing the comparison further, the high-input-impedance Y node corresponds to the base (or gate) of a transistor, the low-input-impedance X node corresponds to the emitter (or source) of a transistor, and the high-output-impedance Z node corresponds to the collector (or drain) of a transistor. Clearly, one transistor cannot function alone as a complete current conveyor since an unbiased single transistor at best can only handle unipolar signals and the high-accuracy unity voltage and unity current gain required for a high-performance current conveyor cannot be obtained. However, the generic rela­ tionship between the current conveyor and an ideal transistor is valid, and it provides valuable insight into the development and operation of monolithic current conveyors described in the next section.

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Supply-Current Sensing. Many of the current-conveyor theories and applications have been tested out in practice using “breadboard” conveyor circuits, due to the lack of availability of a commercial device. Some researchers have built current conveyors from matched transistor arrays, but the most common way of implementing a fairly high-performance current conveyor has been based on the use of supplycurrent sensing on a voltage op-amp [3], [4], as shown in Fig. 57.25. The high-resistance op-amp input provides the current-conveyor Y node, while the action of negative feedback provides the low-resistance X node. Current-mirrors in the op-amp supply leads copy the current at node X to node Z. Using this type of architecture, several interesting features soon became apparent. Consider the two examples shown in Fig. 57.26. In Fig. 57.26(b), Rs represents the output resistance of the current source. The open-loop gain of an op-amp can generally be written Vout A o = Vin 1 + j( f fo )

(57.25)

where Ao is the open-loop dc gain magnitude and ƒo is the open-loop –3 dB bandwidth. Since Ao  1, the transfer function of the voltage follower of Fig. 57.26(a) can be written as Vout 1

≈ 1 + j ( f GB) Vin

(57.26)

where GB = Ao ƒo. From (57.26), the –3 dB bandwidth of the closed-loop voltage follower is equal to the open-loop gain-bandwidth product or GB of the op-amp. If the op-amp is configured instead to give a closed-loop voltage gain K, it is well known that the closed-loop bandwidth correspondingly reduces by the factor K. The transfer function for the current-follower circuit of Fig. 57.26(b), as shown in [4], is given by 1 + j ( f GB) I out ≈ λ 1 + j ( f kGB) I in

Y

+

X

−

(57.27)

Z

FIGURE 57.25 Supply-current sensing on a voltage op-amp.

Vin

+ −

+ Vout

−

Iin Rs

FIGURE 57.26 (a) Voltage follower. (b) Current follower.

© 2003 by CRC Press LLC

Iout

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where λ is the current transfer ratio of the current mirrors and k = (Rs + ro /Ao)/(Rs + ro), and ro represents the output resistance of the op-amp. Since Ao  Rs  ro, then K ≈ 1, and the pole and zero in (57.27) almost cancel. The current-follower circuit thus operates well above the gain–bandwidth product GB of the op-amp, and the –3-dB frequency of this circuit will be determined by higher frequency parasitic poles within the current mirrors. This “extra” bandwidth is achieved because the op-amp is being used with input and output nodes held at virtual ground. The above example is generic in the development of many of the circuits that follow. It demonstrates that reconfiguring a circuit topology to operate with current signals can often result in a superior frequency performance. First-Generation Current Conveyors. Smith and Sedra’s original paper presenting the first-generation CCI current conveyor showed a transistor-level implementation based on discrete devices, shown in Fig. 57.27. Assuming that transistors Q3–Q5 and resistors R1–R3 are matched, then to first order the currents through these matched components will be equal. Transistors Q1 and Q2 are thus forced to have equal currents, and equal Vbes. Input nodes X and Y therefore track each other in both voltage and current. In practice there will be slight differences in the collector currents in the different transistors, due to the finite β of the devices. These differences can be reduced, for example, by using more elaborate current mirrors. The polarity of the output current at node Z can be inverted easily by using an additional mirror stage, and the entire circuit can also be inverted by replacing NPN transistors with PNPs, and vice versa. Connecting two complementary current conveyors, as shown in Fig. 57.28 results in a class AB circuit Y

X Q2

Z

Q1

Q4

Q3

R1

Q5

R2

R3 VSS

FIGURE 57.27 First-generation current conveyor (CCI).

VCC

Q3

Q4 X

Y Q2

Z

Q1

VSS

© 2003 by CRC Press LLC

FIGURE 57.28 Class AB current conveyor.

0912 S1-S8 Frame55.book Page 1715 Thursday, October 10, 2002 10:48 PM

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1715

VCC Q10

Q9

Q11

Q12

Q7

Q8

Q5

Q6

Z

Q4 Q3

Q13 Q1

Y

Q2

X

FIGURE 57.29 Simplified PA630 current conveyor (CCI).

capable of bipolar operation. Note that in practice this circuit may require additional components to guarantee start-up. An integrated current conveyor based on the architecture shown in Fig. 57.27 is commercially available as the PA630 [5], and the basic topology of this device is shown in Fig. 57.29. An NPN Wilson mirror (Q1–Q3) and a PNP Wilson mirror (Q4–Q6) are used to provide the current and voltage following properties between inputs X and Y, similar to the circuit of Fig. 57.27. Taking a second output from the PNP current mirror to provide the Z output would destroy the base-current compensation scheme of the Wilson mirror. Therefore, a second NPN Wilson mirror (Q7–Q9) is used to perform a current-splitting action and so the combined emitter current of Q7 and Q8 is divided in two, with one half being shunted via Q9 to the supply rail, and the other half driving an output PNP Wilson mirror (Q10–Q12). This results in an output current at node Z that to first order is virtually equal to that at the X and Y inputs. Q13 is included to ensure that the device always starts up when turned on. The complete architecture of the PA630 CCI also includes frequency compensation to ensure stability, and modified output current mirrors that use the “wasted” collector current of Q9 to effectively double the output resistance at node Z. A full description of the architecture and operation of this device can be found in [6]. The current-conveyor architecture shown in Fig. 57.29 includes both NPN and PNP transistors in the signal path, and thus the bandwidth and current-handling capability of this device will be poor if only lateral PNPs are available. The development of complementary bipolar processes, with vertical PNP as well as NPN transistors, has made possible the implementation of high-performance integrated circuit current conveyors. Second-Generation Current Conveyors. A second-generation current conveyor (CCII) can also be simply implemented on a complementary bipolar process, by replacing the diode at the CCI Y input with a © 2003 by CRC Press LLC

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VCC

IB1 CM1 Q2 VCC

Y

Q4

Q1

Z

X

IB IX

CM1

Q2

Q3 Y

IB2

Q1 Z

X

VSS

CM2

VSS

a

b

FIGURE 57.30 (a) Class A CCII. (b) Class AB CCII.

transistor, and taking the input from the high resistance base terminal, as shown in Fig. 57.30(a). This can be extended to a class AB version, as shown in Fig. 57.30(b). Referring to Fig. 57.30(b), transistors Q1–Q4 act as a voltage buffer that transfers the voltage at node Y to node X. The current source and sink (IB1 = IB2 = IB) provide the quiescent bias current for these input transistors. Any input current (Ix ) at node X is split between Q2 and Q3, and is copied by current mirrors CM1 and CM2 to the output node Z. This CCII architecture forms the basis of the commercially available CCII01 current conveyor [7]. As we shall see later, it is also used as the basic input stage of the current-feedback op-amp, which has emerged as a high-speed alternative to the more conventional voltage op-amp [8]. The simple CCII architecture of Fig. 57.30(b) will clearly exhibit a quiescent voltage offset between nodes X and Y due to the mismatch between the Vbe s of the NPN and PNP transistors Q1/Q2 and Q3/Q4, since VY − VX = VBE ( p) − VBE (n)

(

= VT 1n I sp I sn

(57.28)

)

where Isp and Isn are the reverse saturation currents of the PNP and NPN transistors, respectively, and VT is the thermal voltage. This process-dependent voltage offset can be reduced by including additional matching diodes in the input stage, as shown in Fig. 57.31. Referring to this diagram, VY − VX = VBE (Q1 ) + VD2 − VBE (Q2 ) − VD1

[

][

VY − VX = VBE (Q1 ) − VD1 − VBE (Q2 ) − VD2

]

(57.29)

Inclusion of these diodes clearly reduces the quiescent input voltage offset, provided that D1 is matched to Q1, D2 is matched to Q2, etc. However, the addition of diodes D1 and D2 has several disadvantages. First, the input voltage dynamic range of the circuit will be reduced by the forward voltage across the additional diode. Second, the small-signal input resistance seen looking into node X will be double that for the basic architecture given in Fig. 57.30(b). This nonzero input resistance at node X (Rx) will compromise the performance of the current conveyor, especially in applications where a nonzero input voltage is applied at node Y. The effect of the small-signal input resistance Rx is to produce a signaldependent voltage offset Vd between nodes X and Y, where Va˙ = Rx I x © 2003 by CRC Press LLC

(57.30)

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VCC IB1 Q2 VCC

D2 D1

Q4

Y

X

Q1

Z

D4 VSS

D3

Q3 IB2 VSS

FIGURE 57.31 CCII with input matching diodes.

Since the value of Rx is determined by the small-signal resistance (re2 + rd2) in parallel with (re3 + rd3), its value could be reduced by increasing the value of the quiescent bias current IB . However, an increase in bias current will lead to an increase in the total power consumption, as well as a possible increase in offsets, and so is certainly not an ideal solution. Further techniques for CCII implementation are discussed in [14]. The previous conveyor is typical of commercial conveyor architectures [7], which are generally built on a high-speed dielectric isolation (fully complementary) bipolar process. Such devices feature an equivalent slew rate of some 2000 V/µs and a bandwidth of around 100 MHz. Until high-performance current conveyors are widely available, these devices will continue to be used in research laboratories rather than in the applications arena. Process technologies and design techniques have now advanced to the stage where the implementation of an integrated current conveyor is both desirable and viable, and a whole host of applications are waiting for its arrival. Current-Feedback Operations Amplifier In this section, the design and development of a high-gain wide-bandwidth transimpedance or currentfeedback operational amplifier is considered. The design of conventional operational amplifiers has remained relatively unchanged since the introduction of the commercial operational amplifier in 1965. Recently, a new amplifier architecture, called a current-feedback operational amplifier, has been intro­ duced. This amplifier architecture is basically a transimpedance amplifier, or a current-controlled voltage source, while the classical voltage-feedback operational amplifier is a voltage-controlled voltage source. The current-feedback operational amplifier has two major advantages, compared to its voltage-feed­ back counterpart. First, the closed-loop bandwidth of the current-feedback amplifier is larger than that of classical voltage-feedback design for comparable open-loop voltage gain. Second, the current-feedback operational amplifier is able to provide a constant closed-loop bandwidth for closed-loop voltage gains up to about 10. A further advantage of the current-feedback architecture is an almost unlimited slew rate due to the class-AB input drive, which does not limit the amount of current available to charge up the compensation capacitor as is the case in the conventional voltage-feedback op-amp. This high-speed performance of the current-feedback operational amplifier is extremely useful for analog signal processing applications within video and telecommunication systems. The generic relationship between the CCII+ and the current-feedback op-amp is extremely close and several of the features offered by the CCII are also present in the current-feedback op-amp. The basic © 2003 by CRC Press LLC

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+

Y

Z

−

X

CCII+

ZT +1

VOUT

IIN

FIGURE 57.32 Current-feedback op-amp structure.

structure of the current-feedback op-amp is essentially that of a CCII+ with the Z node connected directly to an output voltage follower, as shown in Fig. 57.32. Any current flowing into the low impedance inverting input is conveyed to the gain node (ZT), and the resulting voltage is buffered to the output. ZT is thus the open-loop transimpedance gain of the current-feedback op-amp, which in practice is equal to the parallel combination of the CCII+ output impedance, the voltage buffer input impedance and any additional compensation capacitance at the gain node. Generally, in current-feedback op-amps, the gain node is not connected to an external pin, and so the Z node of the CCII+ cannot be accessed. Current-Feedback Op-Amp Architecture. In the following sections we review the basic theory and design of the current-feedback op-amp and will identify the important features and mechanisms that result in broadband performance. We will begin by reviewing the voltage-feedback op-amp and comparing it with the current-feedback op-amp in order to see the differences clearly. A schematic of the classical voltage-feedback op-amp comprising a long-tail pair input stage is shown in Fig. 57.33(a), which contrasts a typical current-feedback architecture, which is shown in Fig. 57.33(b). In both circuits, current mirrors are represented by two interlocking circles with an arrow denoting the input side of the mirror. The current-feedback op-amp of Fig. 57.33(b) shows that the noniverting input is a high-impedance input that is buffered to a low-impedance inverting terminal via a class AB complementary commoncollector stage (Q1, Q2, D1, D2). Note that this classical input buffer architecture is used here for simplicity. In practice a higher performance topology such as that described in Fig. 57.31 would more likely be employed. The noninverting input is a voltage input; this voltage is then buffered to the inverting lowimpedance current input to which feedback is applied. In contrast, both the noninverting and inverting input of the voltage-feedback op-amp are high-impedance voltage inputs at the bases of transistors Q1 and Q2. In both architectures, the collector currents of Q1 and Q2 are transferred by the current mirror to a high-impedance node represented by resistance RZ and capacitance CZ. This voltage is then transferred to the output by voltage buffers that have a voltage gain Avb , providing the necessary low output impedance for current driving. In the case of the current-feedback op-amp, the output buffer is usually the same topology as the input buffer stage shown in the Fig. 57.33(b), but with slightly higher output current bias levels and larger output devices to provide an adequate output drive capability. Ideally, the bias current ICQ1 and ICQ2 will be canceled at the gain node giving zero offset current. Differential-Mode Operation of the Current-Feedback Op-Amp. A schematic diagram of the currentfeedback op-amp with a differential input voltage applied at the noninverting and inverting input is shown in Fig. 57.34. The positive input voltage is applied to the base of transistor Q1 (NPN) via D1, and the negative input voltage is applied to the emitter of Q1, causing the VBE of Q1 to increase and the VBE of Q2 to reduce. IC1 will therefore increase by an amount ∆I and so IC2 will decrease by the same amount –∆I. A net current of 2∆I is therefore sourced out of the high-impedance node (Z) giving rise to a positive voltage (2∆IZ). This voltage is then buffered to the output.

© 2003 by CRC Press LLC

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+VCC

CM1

IOUT

Gain-node Avb RZ

IC1 +

CZ

Output

buffer

IC2

Q1

Q2

−

IBIAS −VCC (a) +VCC IBIAS IC1

CM1

Q1 D1

−

+

IOUT

D2

Gain-node RZ

buffer

Output

CZ

Q2 IBIAS

IC2

CM2

−VCC (b)

FIGURE 57.33 (a) Simplified classic voltage-feedback op-amp architecture. (b) Typical current-feedback op-amp architecture.

With negative feedback applied around the current-feedback op-amp, the low-impedance inverting input will sense the current “feedback” from the output via the feedback network. This feedback current flowing into the inverting input is given by iin− = IC 2 − IC1

(57.31)

The difference between the collector current IC1 and IC2, iin– , will thus be driven into gain node Z, giving rise to the output voltage Vout = Ziin−

(57.32)

It is clear that the output voltage is dependent on the current that flows into the inverting input, hence the amplifier has a high open-loop transimpedance gain Z.

© 2003 by CRC Press LLC

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+Vcc IBIAS IC1

CM1

Q1 D1 + +vin 2

− −vin 2

D2 Q2 IC2

IBIAS

Gain-node (Z) buffer

iout = 2(∆I)

vout

Z

CM2

−Vcc

FIGURE 57.34 Current-feedback op-amp with differential input voltage applied.

+Vcc IBIAS IC1

CM1

Q1 D1 vin +

iout

−

Gain-node

vout

buffer

D2

RZ

R2

CZ

Q2 IBIAS

IC2

iin­

CM2

R1

−Vcc

FIGURE 57.35 Noninverting current-feedback op-amp.

Closed-Loop Noninverting Operation of the Current-Feedback Op-Amp. A schematic diagram of the current-feedback op-amp connected with negative feedback as a noninverting amplifier is shown in Fig. 57.35. For a positive input voltage vin, the output voltage vout will swing in the positive direction and the inverting input current iin– will flow out: iin− =

v in− (v out − v in− ) − R1 R2

(57.33)

The input stage is simply a voltage follower and so ideally, vin+ = vin– = vin . Because vout = Ziin– , then substituting for vin– and iin– in (57.33) yields v out v in (v out − v in ) = − Z R1 R2

© 2003 by CRC Press LLC

(57.34)

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High-Performance Analog Circuits

rearranging for vout /vin 1  1 1 1 v out  +  = v in  +   R1 R2   R2 Z 

(57.35)

  v out  R2   1  = 1+   R  v in  R1  1+ 2   Z 

(57.36)

This result shows that the closed-loop noninverting gain of the current-feedback op-amp is similar to that of a classical voltage-feedback op-amp. From (57.36), the open-loop transimpedance gain Z must be as large as possible to give good closed-loop gain accuracy. Since vout/Z represents the error current iin– then maximizing the Z term will minimize the inverting error current. Note that at this stage it is only the R2 term in the denominator of the second term in (57.36) that sets the bandwidth of the amplifier; the gain-setting resistor R1 has no effect on the closed-loop bandwidth. Closed-Loop Inverting Operation of Current-Feedback Op-Amp. A current-feedback op-amp connected as an inverting amplifier is shown in Fig. 57.36. The low-impedance inverting input samples the input current and drives the output until the voltage at its terminal is at a virtual ground because of negative feedback. Ideally the closed-loop gain is given by ACL = −

R2 R1

(57.37)

From Fig. 57.36, application of Kirchhoff ’s current law to the current i1, iin– , and i2 gives iin− + i2 = i1 iin− −

v out v = in R2 R1 +Vcc

IBIAS CM1 Q1 D1

iout

−

+

Gain-node buffer

D2

RZ

CZ

Q2 CM2 IBIAS −Vcc vin

R1

i1

iin­

i2

FIGURE 57.36 Inverting current-feedback op-amp amplifier.

© 2003 by CRC Press LLC

R2

vout

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because vout/Z = –iin– , then −

v out v out v − = in Z R2 R1

which can be rearranged as   v out R2  1  =− R  v in R1  1+ 2   Z 

(57.38)

Again, the high-Z term is required to provide good closed-loop gain accuracy. More Detailed Analysis of the Current-Feedback Op-Amp. A simplified macromodel of the currentfeedback architecture configured as a noninverting amplifier is shown in Fig. 57.37. The input stage is represented by a semi-ideal voltage buffer to the inverting input. The output resistance of the input stage buffer Rinv is included since it has a significant effect on the bandwidth of the amplifier, as will be shown later. The current that flows out from the inverting terminal i3 is transferred to the gain node, which is represented by RZ and CZ , via a current mirror that has a current gain K. The voltage at the gain node is transferred to the output in the usual way by a voltage buffer, with voltage gain Avb . The net transfer function is given by

v out = v in

1+

R2 R1

(57.39)

   R   Rinv 1 + 2  + R2  R1    1 + jωC Z   Avb K    

Hence, the pole frequency is also given by f −3dB =

Avb K

(57.40)

   R  2πC Z Rinv 1 + 2  + R2  R1    

(A full derivation of this transfer function is given in Appendix A.)

vin

+

K

X1 i3

buffer

R1

i3 i1 v1

v2 RZ

Rinv

−

Ki3

Avb CZ

buffer

R2 i2

FIGURE 57.37 Inverting amplifier with current-feedback op-amp macromodel.

© 2003 by CRC Press LLC

vout

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High-Performance Analog Circuits

+

vin

Avb

gm −

R1

RZ

CZ

vout

buffer

R2 −

FIGURE 57.38 Noninverting amplifier with voltage-feedback op-amp macromodel.

To compare this result to the classical voltage-mode op-amp architecture, a simplified schematic diagram of the voltage-feedback op-amp configured as a noninverting amplifier is shown in Fig. 57.38. Again from a full analysis, given in Appendix B, the transfer function obtained is

v out = v in

R2 R1 RzC Z  1 + jω  g A R 1 + m vb Z   R2   1 + R  1  1+

     

(57.41)

The pole frequency is given by g m Avb RZ  R2  1 + R   1 2πRZ C Z

1+ f −3dB =

(57.42)

Pole Frequency Comparison. If one compares the closed-loop pole frequency Eqs. (57.40) and (57.42) for the current-feedback and voltage-feedback op-amp, respectively, it is clear that the bandwidth of the voltage-feedback op-amp is dependent on the closed-loop gain (1 + R2/R1) resulting in the well-known constant gain-bandwidth product fMAX = (Av)CL fT . This means that an increase in the closed-loop gain results in a decrease in the bandwidth by the same factor as illustrated in Fig. 57.39. In contrast, the pole frequency of the current-feedback op-amp is directly dependent on R2 and can be set almost indepen­ dently of the closed-loop gain. Thus, the closed-loop bandwidth is almost independent of closed-loop gain as shown in Fig. 57.40, assuming that Rinv is close to zero. Intuitively, this is the case since the feedback error current that is set by the feedback resistor R2 is the current available to charge up the compensation capacitor. However, if one considers (57.40) in some detail it can be seen that for high closed-loop gains and a nonzero Rinv , then the Rinv term starts to dictate and so the bandwidth will become more dependent on the closed-loop gain. Slow Rate of the Current-Feedback Op-Amp. As mentioned earlier, one other advantage of the currentfeedback op-amp over the classical voltage-feedback op-amp is the high slew rate performance. For the classical long-tail, or emitter-coupled pair input stage shown in Fig. 57.41, the maximum current available to charge up the compensation capacitor CZ at the gain node is IBIAS, and this occurs when Q1 or Q2 is driven fully on. The resulting transconductance plot shown in Fig. 57.42 limits the slew rate of the amplifier.

© 2003 by CRC Press LLC

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40

Voltage gain (dB)

30 20 10 0 −10 −20 Frequency (Hz)

FIGURE 57.39 Frequency response of voltage-feedback op-amp amplifier for various closed-loop gains.

40

Voltage gain (dB)

30

20 10 0 −10 −20 Frequency (Hz)

FIGURE 57.40 Frequency response of current-feedback op-amp amplifier for various closed-loop gains. +VCC

CM1

iout Gain-node RZ

+

Q1

vin

CZ

Q2

IBIAS

− −VCC

FIGURE 57.41 Long-tail pair input stage.

In contrast, the slew rate of the current-feedback op-amp is virtually infinite, as can be seen from the input stage schematic shown in Fig. 57.43. Referring to Fig. 57.43, a change in the input voltage ∆Vin at V(+) will be copied by the input buffer to V(–). When connected as noninverting amplifier, the current

© 2003 by CRC Press LLC

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High-Performance Analog Circuits

Output Current

+IBIAS

0

−IBIAS −0.3

−0.2

−0.1

0.0

0.1

0.2

0.3

Input voltage (V)

FIGURE 57.42 Long-tail pair input transconductance. +VCC IBIAS CM1 Q1 D1

iout Gain-node

+

RZ

D2

vin

CZ

Q2

−

CM2 IBIAS −VCC

FIGURE 57.43 Current-feedback op-amp input stage.

through R1 will change by ∆Vin/R1, while the current through R2 will change by ∆Vin/R2, since the output voltage at this point remains stationary. The total change in current through R1 and R2 must be supplied by the internal input buffer, and will be ∆I(–) = ∆Vin((R2 + R1)/(R2 · R1)). This large input error current causes a rapid change in the output voltage, until Vout is again at the value required to balance the circuit once more, and reduce I(–) to zero. The larger the input voltage slew rate, the larger the change in input error current, and thus the faster the output voltage slew rate. Current-feedback op-amps theoretically have no slew-rate limit. A typical current-feedback op-amp will exhibit a slew rate of between 500 and 2000 V/µS. An analysis of this input stage (see Appendix C) shows that the transconductance follows a sinh(x) type function, as shown in Fig. 57.44. In theory, this characteristic provides nearly unlimited slew-rate capability [9]. However, in practice a maximum slew rate will be limited by the maximum current drive into the gain node, which depends on the power dissipation of the circuit, the ability of power supply to deliver sufficient current, and the current-handling capability of the current mirrors. Wideband and High-Gain Current-Feedback Op-Amp. Previously, we have shown that the bandwidth of the current-feedback op-amp is almost independent of the closed-loop gain setting. Therefore, the closedloop gain-bandwidth GB increases linearly with the closed-loop gain. However, the bandwidth of the practical current-feedback op-amp starts decreasing with high gain as a result of the finite inverting-input

© 2003 by CRC Press LLC

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1726

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The Circuits and Filters Handbook, Second Edition

0

0

FIGURE 57.44 Input-stage transconductance of the current-feedback op-amp.

impedance [10], as shown by (57.40). This is because for high gain, Rinv(1 + R2/R1) > R2, and so the Rinv(1 + R2/R1) term dominates the expression for closed-loop bandwidth, resulting in a direct conflict between gain and bandwidth. At low gains when R2 > Rinv(1 + R2/R1), the closed-loop pole frequency is determined only by the compensation capacitor and the feedback resistor R2. Thus, the absolute value of the feedback resistor R2 is important, unlike the case of the voltage-feedback op-amp. Usually, the manufacturer species a minimum value of R2 that will maximize bandwidth but still ensure stability. Note that because of the inherent architecture a very high bandwidth can be achieved with the current-feedback design for a given value of R2. In practice, for gains higher than about 10, the Rinv(1 + R2/R1) term in (57.40) becomes dominant and the amplifier moves toward constant gain–bandwidth product behavior. The GB can be increased by reducing R2 [11] but this will compromise stability and/or bandwidth, or alternatively, CZ can be reduced. The latter option is limited since the minimum value of CZ is determined by the device parameters and layout parasitics. Two possible ways of improving the high-gain constant bandwidth capability of the current-feedback op-amp can be seen by inspection of (57.40). Either the K factor, which represents current gain in the current mirrors at the Z-node can be increased from unity to increase the bandwidth as it rolls off with high gain, or the inverting input impedance of the amplifier should be reduced toward zero. In the following section we consider the design of a suitable broadband variable-gain current-mirror circuit with a possible application being to improving the maximum bandwidth capability of currentfeedback op-amps. Basic Current Mirror. A typical current-feedback op-amp circuit is shown in Fig. 57.45. It includes a complementary common-collector input stage (Q1–Q4) and a similar output buffer (Q5–Q8), with linking cascode current mirrors setting the Z-node impedance (Q12–Q14, Q9–Q11). The cascoded mirror provides unity current gain. Any attempt to increase the current gain via emitter degeneration usually results in much poorer current-mirror bandwidth. Consider now the development of a suitable broadband, variable gain current mirror. A schematic diagram of a simple Widlar current mirror and its small-signal equivalent circuit are shown in Figs. 57.46 and 57.47, respectively. For simplicity, we will assume that the impedance of the diode-connected transistor Q1 is resistive and equal to RD . The dc transfer function of the mirror is derived in Appendix D and is given by I out β = I in β + 2 and the –3-dB bandwidth is given by © 2003 by CRC Press LLC

(57.43)

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High-Performance Analog Circuits

+VCC IBIAS

R

IBIAS

R

Q13

Q12

Q7 (5X)

VBIAS Q3

Q14

Cinv

INPUT

R

CZ

OUTPUT

Q5 (2X)

Q1 VBIAS Q4

Q6 (2X)

Q2 RL R

Q11

R2 Q9

Q10

Q8 (5X)

R1 R

IBIAS

R

IBIAS

−VCC

FIGURE 57.45 Transistor-level schematic of a typical current-feedback op-amp. x = unit transistor area.

Iin

Q1

RE1

Iout

Q2

RE2

FIGURE 57.46 Simple Widlar current mirror with emitter degeneration.

f −3dB =

1  r (r + RD )  2πC π  π2 bb2   rπ + rbb2 + RD 

(57.44)

In order to increase the current gain it is usual to insert an emitter-degeneration resistor RE1 in the emitter of Q1. The dc transfer function, derived in the Appendix E, is then © 2003 by CRC Press LLC

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Iin

Iout rbb2

RD1

rπ2

RE1

Cπ2

gm 2

RE2

FIGURE 57.47 Small-signal equivalent circuit of Fig. 57.46 current mirror.

I in RE1 = VT ln

I out I in

(57.45)

and the ac small-signal current gain is given by iout = ( RE1 + RD1 ) g m2 iin

(57.46)

where RD1 =

I in KT q

(57.47)

The –3-dB bandwidth now becomes f −3dB =

1  rπ2 (rbb2 + RD1 + RE1 )  2πC π2    rπ2 + rbb2 + RD1 + RE1 

(57.48)

It can be seen that increasing RE1 to increase the gain results in a reduction in the mirror bandwidth. The method of increasing the area of Q2 to increase the current gain is not advantageous because the capacitance Cπ2 increases simultaneously, and so again, the bandwidth performance is compromised. We can conclude that this approach, though apparently well founded, is flawed in practice. Improved Broadband Current Mirror. A current mirror with current gain is shown in Fig. 57.48 and the small-signal equivalent circuit is shown in Fig. 57.49. In this current mirror Q1 and Q2 are connected as diodes in series with RE1. Q3 is connected as a voltage buffer with the bias current source IEQ3 . Q4 is the output transistor with degeneration resistor RE4 for current gain setting. The basic idea is to introduce the common collector Q3 to buffer the output from the input and hence isolate gain setting resistor RE 4 from the bandwidth determining capacitance of the input. The dc transfer function is given by I in RE1 − I out RE 4 + VT 1n

I in2 =0 ICQ3 I out

(57.49)

and the ac small-signal current gain is given by iout (R + RD1 + RD2 )g m4 = E1 iin 1 + g m4 RE 4 © 2003 by CRC Press LLC

(57.50)

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Iin

Iout

VCC

Q2

Q3

Q1

Q4 RE1

RE4

IBIAS

FIGURE 57.48 Improved current mirror with current gain.

Iout

Iin rbb3 RD2

rπ3

gm3,vrπ3

Cπ3

rbb4 rπ4

RD1

RE1

Cπ4

IEQ3

gm4,vrπ4

RE4

FIGURE 57.49 Equivalent circuit of improved current mirror with current gain.

and the –3-dB bandwidth now becomes f −3dB =

1  rπ4 Rx  2πC π4    rπ4 + Rx 

(57.51)

where Rx = rbb 4 +

rπ3 + rbb3 + RD1 + RD2 + RE1 β3

(57.52)

It can be seen clearly that the dominant pole (57.51) of the current mirror with current gain is now only slightly decreased when we increase the current gain by increasing RE1. However, the nondominant pole at the input node is increased, and this will marginally effect the resultant overall stability performance if employed in a current-feedback op-amp. This current mirror with current gain has been employed successfully in current-feedback op-amp design for increased gain-bandwidth capability [12]. © 2003 by CRC Press LLC

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Phase Linearity. The internal signal path in a current-feedback op-amp is very linear due largely to the symmetrical architecture. Consequently, these devices have a very linear phase response. Furthermore, all the frequency components of a signal are delayed by the same amount when passing through the amplifier, and so the waveform is reproduced accurately at the output. Current-feedback op-amps typi­ cally exhibit differential phase error of around ±1° at frequencies of approximately half the bandwidth. Choosing the Value of R2. From (57.40), we can see that for a fixed value of Cz , a smaller feedback resistor R2 will give a higher closed-loop bandwidth. It might be expected that the maximum bandwidth would be obtained with the minimum feedback resistance; that is, with R2 = 0. In practice, current-feedback op-amps are generally unstable when their feedback resistance is reduced below a particular value. The reason for this is that the dominant closed-loop pole at frequency of f ≈1/2πCz R2 must be significantly lower than any nondominant parasitic pole frequency within the op-amp, so that a reasonable gain and phase margin is maintained. If the value of R2 is reduced, then this dominant pole will move upward in frequency toward the parasitic poles, reducing the gain and phase margin, and eventually leading to instability. Obviously, the “correct” value for R2 will depend on the internal value of Cz and the location of any parasitic poles within the device. These are the sort of parameters that are known to the manu­ facturer, but are generally not listed in a data sheet. Therefore, the manufacturer of a particular device will generally recommend a value of R2 that guarantees stability, while maintaining a reasonably wide bandwidth. Reducing R2 below this recommended or optimum value will tend to lead to peaking and instability, while increasing R2 above the optimum value will reduce the closed-loop bandwidth. If band limiting is required, then a larger value of R2 than the optimum can be chosen to limit the bandwidth as required. Since a current-feedback op-amp requires a minimum value of R2 to guarantee stability, these devices cannot be used with purely capacitive feedback because the reactance of a capacitor reduces at high frequencies. This means that the conventional voltage op-amp integrator cannot be implemented using a current-feedback op-amp. Practical Considerations for Broadband Designs. 1. Ground Planes. The purpose of a ground plane is to provide a low impedance path for currents flowing to ground, since any series impedance in the ground connections will mean that not all ground nodes are at the same potential. In addition, the inductance of a printed circuit track is approximately inversely proportional to the track width, and so the use of thin tracks can result in inductive ground loops, leading to ringing or even oscillations. The use of an unbroken ground plane on one side of the circuit board can minimize the likelihood of inductive loops within the circuit. However, any particularly sensitive ground-connected nodes in the circuit should be grounded as physically close together as is possible. 2. Bypass Capacitors. Power supply lines often have significant parasitic inductance and resistance. Large transient load currents can therefore result in voltage spikes on the power supply lines, which can couple onto the signal path within the device. Bypass capacitors are therefore used to lower the impedance of the power supply lines at the point of load, and thus short out the effect of the supply line parasitics. The type of bypass capacitor to use is determined by the application and frequency range of interest. High-speed op-amps work best when their power supply pins are decoupled with radio-frequency-quality capacitors. Manufacturers often recommend using a composite large-small parallel bypass capacitor with something like a 4.7-uF tantalum capacitor on all supply pins, with a parallel 100-nF ceramic to ensure good capacitive integrity at higher frequencies, where the tantalum becomes inductive. However, a note of caution here: This large-small double capacitor technique relies on the large capacitor having sufficiently high ESR so that at resonance the two capacitors do not create a highQ parallel filter. In surface-mount designs a single bypass capacitor may well be better than two due to the inherent high-Q of surface-mount capacitors.

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All bypass capacitor connections should be minimized, since track lengths will simply-add more series inductance and resistance to the bypass path. The capacitor should be positioned right next to the power supply pin, with the other lead connected directly to the ground plane. 3. Sensitive Nodes. Certain nodes within a high-frequency circuit are often sensitive to parasitic com­ ponents. A current-feedback op-amp, for example, is particularly sensitive to parasitic capacitance at the inverting input, since any capacitance at this point combines with the effective resistance at that node to form a second nondominant pole in the feedback loop. The net result of this additional pole is a reduced phase margin, leading to peaking and even instability. Clearly, great care must be taken during layout to reduce track lengths, etc., at this node. In addition, the stray capacitance to ground at V(–) can be reduced by putting a void area in the ground plane at this point. If the op­ amp is used as an inverting amplifier, then the potential of the inverting input is held at virtual ground, and any parasitic capacitance will have less effect. Consequently, the current-feedback op­ amp is more stable when used in the inverting rather than the noninverting configuration. 4. Unwanted Oscillations. Following the preceding guidelines should ensure that your circuit is well behaved. If oscillations still occur, a likely source is unintentional positive feedback due to poor layout. Output signal paths and other tracks should be kept well away from the amplifier inputs to minimize signal coupling back into the amplifier. Input track lengths should also be kept as short as possible for this same reason.

Broadband Amplifier Stability Operational amplifiers are generally designed with additional on-chip frequency compensation capaci­ tance in place. This is doe to present the applications engineer with an op-amp that is simple to use in negative feedback, with minimal chance of unstable operation. In theory, all will be well, but for three main reasons, op-amps become unstable in the real world of analog electronic circuit design. This section outlines the three main causes for unstable operation of broadband amplifiers and shows practical ways of avoiding these pitfalls. Op-Amp Internal Compensation Strategy Before dealing with specific stability problems in broadband amplifiers and how to solve them, we will look briefly at the internal frequency compensation strategy used in op-amp design. Generally, op-amps can be classified into two groups, those with two high-voltage gain stages and those with only one stage. The two-stage design provides high open-loop gain but relatively low bandwidth, while the higher speed signal-stage amplifier provides lower open-loop gain but much higher usable bandwidth. Insight into the internal op-amp architecture and the type of compensation used will give the designer valuable information on how to tame the unstable op-amp. Review of the Classical Feedback System Analyzing the classical feedback system in Fig. 57.50 gives the well-known expression for the closed-loop gain, Ac : Ac = A [1 + B ⋅ A]

VIN

+

VOUT A − B

FIGURE 57.50 Classical feedback system.

© 2003 by CRC Press LLC

(57.53)

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where A is the open-loop gain of the amplifier and B the feedback fraction. T = B · A is referred to as the loop-gain, and the behavior of T over frequency is a key parameter in feedback system design. Clearly, if T  1 or A  Ac , then the closed-loop gain is virtually independent of the open-loop gain A, thus Ac ≈ B −1

(57.54)

This is the most important and desirable feature of negative feedback systems. However, the system will not necessarily be stable since, at higher frequencies, phase lag in the open-loop gain A may cause the feedback to become positive. Stability Criteria Though negative feedback is desirable, it results in potential instability when the feedback becomes positive. The loop-gain T is the best parameter to test whether an amplifier is potentially unstable. The phase margin ΦM is a common feature of merit used to indicate how far the amplifier is from becoming an oscillator:

(

)

Φ M = 180° + Φ BA = 1

(57.55)

When ΦM = 0°, the phase of the loop gain, T = B · A is exactly –180° for B · A = 1. The closed-loop gain Ac will become infinite and we have got an oscillator! Clearly, what is required is that ΦM > 0 and generally the target is to make ΦM ≥ 45° for reasonably stable performance. However, excessive ΦM is undesirable if settling time is an important parameter in a particular application. An op-amp is a general purpose part and so the IC designer strives to produce a maximally versatile amplifier by ensuring that even with 100 percent feedback, the amplifier circuit will not become unstable. This is done by maintaining a ΦM > 0 for 100 percent feedback, that is, when B = 1. If the feedback network B is taken to be purely resistive, then any additional phase lag in the loop gain must come from the open-loop amplifier A. Tailoring the phase response of A so that the phase lag is less than 180° up to the point at which A < 1 or 0 dB, ensures that the amplifier is “unconditionally stable”; that is, with any amount of resistive feedback, stable operation is “guaranteed.” Most open-loop op-amps, whether single-stage or two-stage, will exhibit a two-pole response. The separation of these two poles whether at low frequency or high frequency will have a major effect on the stability of the system and it is the op-amp designer’s objective to locate these open-loop poles to best advantage to achieve maximum bandwidth, consistent with versatile and stable performance. Two-Stage Op-Amp Architecture A schematic of the standard two-stage op-amp topology is shown in Fig. 57.51. The input differential pair T1/T2 provides high gain, as does the second gain stage of T3/T4 Darlington pair common emitter. (high impedance node) +V T4

T3

(high impedance node)

X (+) T1

T2

INPUT

Cp

+ x1 −

Y

(−) Io

Io −V

FIGURE 57.51 Architecture of the standard two-stage op-amp.

© 2003 by CRC Press LLC

Vo

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High-Performance Analog Circuits

A high-voltage gain is achieved with this structure, so that output stage is usually a unity voltage gain common-collector output buffer to provide a useful load current drive capability. The amplifier structure in Fig. 57.51 has two internal high-impedance nodes, node X and node Y. These high impedance nodes are responsible for introducing two dominant poles into the frequency response and their relative location is critical in determining the stability of the amplifier. Each pole contributes a low-pass filter function to the open-loop gain expression of the form

[1 + jf f ]

−1

(57.56)

P

Each pole introduces 45° of phase lag at the pole frequency fP and an additional 45° at f ≈ 10 · fP . With a two-pole amplifier the open-loop gain A is given by

[

][

A = A0 1 + jf f P1 1 + jf f P 2

]

(57.57)

where A0 is the dc open-loop gain and fP1 and fP2 are the two-pole frequencies. A typical plot of A versus f is shown in Fig. 57.52(a). At low frequencies, where f  fP1 the gain is flat, and at fP1 the gain begins to fall at a rate increasing to –20 dB/decade. The roll-off steepens again at fP2 to a final gradient of –40 dB/decade. It is generally the case that fP1  fP2 as shown in Fig. 57.52(a). Turning our attention to the phase plot in Fig. 57.52(a), at f = fP1 the output lags the input by 45°, and as the frequency rises toward fP2 the phase

AdB 85dB

uncompensated compensated

0

freq fp1

fp1′

fp2′

fp2

Phase 180

Two-Stage Op-Amp

uncompensated

90

compensated

0

freq fp1

fp1′

fp2′

fp2

(a) AdB 65dB

freq fp1

fp2

Phase Single-Stage Op-Amp

180 90 0 fp1

fp2

freq

(b)

FIGURE 57.52 Pole frequency and phase response for (a) two-stage op-amp and (b) single-stage op-amp.

© 2003 by CRC Press LLC

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106 30° 45° 60°

105

104

1000

100

10

1 1

10

100

1000

1°104

1°105

N

FIGURE 57.53 Low-frequency gain A0 vs. N ( = fP2 /fP1) for a two-pole amplifier.

lag increases through 135° at fP2 to 180° at f ≈ 10 · fp2. To ensure unconditionally stable performance, the second pole must be sufficiently far from the first so that the phase margin is large enough. Figure 57.53 shows curves of the dc value of open-loop gain A0 versus the ratio N of the pole frequencies (N = fP2/fP1) for different values of phase margin. For a given value of A0 = 1000 or +60 dB, the ratio of the pole frequencies must be N ≈ 700 to obtain a phase margin of 45°. Miller Compensation and Pole Separation Without any added compensation capacitance the two open-loop poles of the op-amp are invariably too close to make the amplifier unconditionally stable. The most common compensation method is to add a capacitor between the base and collector of the Darlington pair, shown as Cp in Fig. 57.51. This is known as Miller compensation because this strategy makes use of the Miller capacitance multiplication effect discussed earlier. The net result is that the two poles now become significantly far apart, with fP1 reducing and fP2 increasing, and so the phase margin can be increased to make the op-amp unconditionally stable. However, the penalty of this method is poorer bandwidth and also lower slew rate because of the large capacitance needed, which in practice may be 20 pF or more. Single-Stage Op-Amp Compensation Figure 57.54 shows a typical simplified circuit schematic of a single-stage op-amp. The input is a differ­ ential emitter-coupled pair followed by a folded cascode transistor and an output complementary com­ mon-collector buffer. The key difference between this architecture and the two-stage design shown earlier is that X is a low-impedance node, and so the only high-impedance node in the circuit is node Y. Interestingly, the higher frequency nondominant pole of the two-stage amplifier has now become the dominant frequency pole of the single-stage design, as indicated by the second set of curves in Fig. 57.52(b), which leads to several advantages: 1. The frequency performance off the amplifier is extended. This frequency extension does not lead to a deterioration in phase margin, but simply means that the phase margin problem is shifted up in the frequency domain. 2. Capacitance at the high-impedance Y node reduces bandwidth, but now improves phase margin. © 2003 by CRC Press LLC

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High-Performance Analog Circuits

+V Io

(low impedance node)

X (−) INPUT

VBIAS

T3

(high impedance node)

T1

T2

+ x1 −

Y (+) Io

Vo

Io −V

FIGURE 57.54 Architecture of single-stage op-amp.

3. A single value of a few pF’s of grounded capacitor at Y will now act as a satisfactory compensation capacitor, unlike the large Miller capacitor required in the two-stage design. 4. The slewing capability of this single-stage structure is very good as a result of the much smaller compensation capacitor. 5. Clearly, it is much more straightforward to develop a stable amplifier for high-frequency applica­ tions if it has essentially only one voltage gain stage and so high-frequency op-amp designers generally opt for a single gain stage architecture. Grounded Capacitor Compensation Typical AOL vs. f responses of two single-stage op-amps are shown in Fig. 57.55, indicating one highfrequency pole and its proximity to the nondominant pole. The curves are taken from data for (a) a 2-GHz gain–bandwidth product voltage-feedback op-amp and (b) a 150-MHz current-feedback op-amp. In both cases the phase characteristics demonstrate the expected 45° lag at the pole frequency, and the slow roll-off in phase at high frequency due to the presence of the very-high-frequency poles. Both single-stage and two-stage op-amps can be approximated by the two-pole macromodel shown in Fig. 57.56. Transconductance GM and output resistance R0 represent the gain per stage of GM · R0. The difference between the two-stage and single-stage op-amp models is that R01 of the single-stage is of the order of [GM]–1 and the dominant compensation capacitor is C2. CP in the case of the single stage will simply be a feedback parasitic capacitor, while in the case of a two-stage it will be the dominant Miller compensating capacitor. This simple model is an excellent first-cut tool for determining pole locations, and the value of compensation capacitor for a desired bandwidth and stability. 180

90

0

PHASE

−90

40

−180

20

−270

0

TRANSIMPEDANCE (V/mA)

60

10000

PHASE (°)

OPEN LOOP GAIN (dB)

GAIN

PHASE 1000 GAIN

− +

vin

vout 100

v ROL = vout in

140 100

100 60

PHASE (°)

80

10 20 1

−10 10k

100k

1M

10M

FREQUENCY (Hz)

(a)

−360 100M 500M

−20 10k

100k

1M

10M

100M

FREQUENCY (Hz)

(b)

FIGURE 57.55 Single-pole op-amps; open-loop gain and phase frequency characteristics. (a) Voltage feedback. (b) Current feedback.

© 2003 by CRC Press LLC

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Cp

VX GM1VIN

R01

C1

VY GM2VIN

R02

C2

FIGURE 57.56 Partial equivalent circuit of two-pole op-amp.

High-Frequency Performance Although the bandwidth in a single-stage design is significantly extended, circuit parasitics become more important. We are confronted with the problem of potential instability, since at higher frequencies the “working environment” of the op-amp becomes very parasitic sensitive; in other words, now op-amp­ embedded parasitics cannot be neglected. An op-amp in closed-loop can be considered at three levels, as shown schematically in Fig. 57.57. The inner triangle is the ideal op-amp, internally compensated by the op-amp designer for stable operation using the circuit techniques outlined earlier. High-frequency amplifiers are sensitive to parasitics of the surrounding circuit. The key parasitics within the outer triangle include power supply lead inductance, stray capacitance between power supply pins, and input to ground capacitance. The effect of these parasitics is to destabilize the amplifier, and so the designer is confronted with the task of reestablishing stable operation. The approach needed to achieve this parallels the work of the op-amp designer. The parasitics almost always introduce additional extrinsic nondominant poles, which need to be compen­ sated. The task of compensation cannot be attempted without considering the outer or third level, which +V

CSTRAY L1 +

VIN

−

+

VO

IDEAL AMP

−

CL L2

CSTRAY

CSTRAY

−V

Z2 Z1

FIGURE 57.57 Real feedback amplifier.

© 2003 by CRC Press LLC

RL

0912 S1-S8 Frame55.book Page 1737 Thursday, October 10, 2002 10:48 PM

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includes the closed-loop gain defining components together with the load impedance. Again, stray reactance associated with these components will modify the loop gain, and so to guarantee stable operation of the closed-loop amplifier it is necessary to compensate the complete circuit. Power Supply Impedance In this section, we consider the ways in which the impedance of the power supply can affect the frequency response of the amplifier. First, some important rules: 1. There is no such thing as an ideal zero-impedance power supply. 2. Real power supplies have series R-L impedance and at high frequencies the inductance matters most. 3. Power supply inductance causes “bounce” on the power supply voltage, generating unwanted feedback via parasitic capacitive links to the inputs. Power supply “bounce” increases with increas­ ing load current. 4. Supply decoupling capacitors act as “short term local batteries” to maintain power supply integrity, and it is important that they are placed as close as possible to the power supply pins of the op-amp. Large electrolytic capacitors are fine at low frequencies but are inductive at high frequencies. Figure 57.58 shows commonly used decoupling circuitry. Small-sized tantalum electrolytics are preferred, while a parallel ceramic capacitor with low series inductance takes over the decoupling role at high frequencies. The added series R prevents the inductance of the electrolytic resonating with the ceramic capacitor. The waveforms in Fig. 57.59 illustrate the benefits of good decoupling. Effects of Resistive and Capacitive Loads The load presented to an amplifier is likely to have both resistive and capacitive components, as illustrated previously in Fig. 57.57. Increasing the load current causes power supply ripple, so good power supply decoupling is vital. +V R CTAN −

CCER

+ CTAN

R CCER

−V

(a)

FIGURE 57.58 Supply decoupling circuitry. Note: CCER = ceramic capacitor and CTAN = tantalum.

CL = 20 pF

CL = 20 pF

CL = 50 pF

CL = 50 pF (b)

FIGURE 57.59 High-speed voltage buffer: (a) with and (b) without supply decoupling.

© 2003 by CRC Press LLC

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Voltage Gain (dB)

20

VS = ± 15V 15 T = 25° C C 10 RL = 500 Ω 5 VO < 100 m

CL = 500 pF

0 −5

CL = 4000 pF

−10 −15

CL = 1000 pF

−20 −25 −30

CL = 100 pF 1

CL = 50 pF

10 Frequency (MHz)

100

200

FIGURE 57.60 Load capacitance causes gain peaking.

A closed-loop amplifier with voltage-sampled negative feedback results in a very-low output imped­ ance, so it is natural to think that the effects of any load would be shunted out by this low impedance. In reality, the load has an important effect on the amplifier and must not be overlooked. Resistive loads, for example, cause two main effects. First, as a voltage divider with the open-loop output resistance of the op-amp r0, the open-loop gain is reduced. This effect is small unless the load resistance approaches r0. Second, the load current is routed to the output pin via the supply pins, and as the load current increases, the supply pin voltage is modulated. This effect is more important, since the integrity of the power supply will be degraded. Again, good supply decoupling is essential to minimize this effect. Capacitive load current is proportional to the derivative of output voltage, and the maximum capacitive output current demand occurs when dVOUT/dt is a maximum. Though not directly a stability issue, the designer must remember that a capacitive load demands high output current at high frequencies and at high amplitude, that is I MAX = C L ⋅ 2πf MAX ⋅VOUTPEAK

(57.58)

Figure 57.60 illustrates the effect of load capacitance on the loop gain. C1 together with the equivalent output resistance of the op-amp, adds an additional pole into the loop gain of the form

[

VF VOUT = B = 1 1 + jf f L

]

where

f L = 1 2πr0 ⋅C L

(57.59)

The load resistance has a minor influence on the loop gain compared to the effects of load capacitance by slightly reducing the value of dc open-loop gain by factor K, where K = RL/[r0 + RL ], as described above. Since the effective output resistance reduces to r0′ = r0 /RL , then fL changes to fL′ = 1/2πr0′ CL. Neutralizing the Phase Lag To compensate for high-frequency phase lag, the simplest technique is to add a series resistance R between the output of the op-amp and the load connection point, as shown in Fig. 57.61. The series resistor adds a zero into the VF /VOUT equation, which changes to

[

VF VOUT = K ⋅ 1 + jf f Z

] [1 + jf f ] P

(57.60)

where K = [R + RL]/[r0 + R + RL], fP = 1/[2π(r0 + R)/RL · CL] and fZ = 1/[2πRL//R · CL] = fP · [1 + r0/R], so clearly; fP < fZ . © 2003 by CRC Press LLC

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High-Performance Analog Circuits

R2 − +

R

VOUT

CL

RL

FIGURE 57.61 Load capacitance neutralization.

The phase lag introduced by the pole is compensated by the phase lead of the zero at higher frequencies. The maximum phase lag is limited if the zero is close to the pole, almost eliminating the effects of the load capacitor. Maximum phase lag in VF /VOUT occurs at f = fM , where fM is given by

[

fM = fP ⋅ fZ

]

1/ 2

= f P ⋅(1 + r0 R)1/ 2

(57.61)

and at fM the phase lag Φ = Φ′ is given by

[

[

]

Φ′ = 90° − 2⋅ tan −1 f M f P = 90° − 2⋅ tan −1 (1 + r0 R) Φ′ ≈ −19.5° for R = r0

1/ 2

] (57.62)

Φ′ ≈ −8.2°

for R = 2⋅r0

Φ′ ≈ −6.4°

for R = 3⋅r0

These values show that the added lag Φ′ is not excessive as long as R > r0. The disadvantage with this method is that the series resistor is in direct line with the output current, increasing the output resistance of the amplifier and limiting the output current drive capability. The output impedance also goes inductive at high frequencies. An alternative way of solving the problem of capacitive load is to view the closed-loop output resistance of the op-amp as being inductive, since the closed-loop output impedance of the op-amp is essentially the open-loop output resistance divided by the loop gain. As the loop gain falls with frequency, the output impedance rises, and thus appears inductive. Adding a load capacitor generates a resonant circuit. The solution is to “spoil” the Q of the resonator, therefore minimizing the added phase lag of CL. Adding a so-called series R–C “snubber,” as in Fig. 57.62, effects a cure. The resistor R is ac coupled by the capacitor at high frequencies and spoils the Q. Effectively, CL resonates with the inductive output impedance, and at this frequency leaves the R–C snubber as a “new” load. The equivalent circuit is therefore close to the previous compensation method shown in Fig. 57.61, but with the added advantage that now the load current is not carried by the series resistance. To select the snubber component values, make R = 1/2πf0C, where f0 is the resonant frequency, which can simply be determined experimentally from the amplifier without the snubber in place. The value of the series capacitance is a compromise: too big and it will increase the effective load capacitance. Choosing C = CL works reasonably well in practice. Amplifier CL R SNUBBER

C

FIGURE 57.62 Snubber cures capacitive load peaking. © 2003 by CRC Press LLC

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10 Cin− = 6pF

GAIN (dB)

0 −10

Cin− = 0 Cin− = 2 pF Cin− = 4 pF

−20 −30 100k

1.0M

10M

100M

1.0G

FREQUENCY (Hz)

FIGURE 57.63 Stray input capacitance causes gain peaking.

Inverting Input Capacitance to Ground With most broadband bipolar op-amps, parasitic capacitance to ground adds an additional pole (and hence phase lag) into the feedback path, which threatens stability. Stray capacitance C1 at the inverting input pin (shown previously in Fig. 57.57) modifies B and adds phase lag in the loop-gain T, compro­ mising stability. Solving for B with C1 taken into account will clarify the problem. It is simple to show that

[

B = VF VOUT = Z1 Z1 + Z 2

]

(57.63)

where Z1 = R1/[1 + jωR1C1] and Z2 = R2. Substituting, we get

[

B = K 1 + jf fC

]

(57.64)

where K = R1 [R1 + R2] and fC = 1/[2πC1R1/R2]. The additional pole at f = fC will now give the circuit a very undesirable three-pole loop gain, which could cause significant gain peaking, as shown in Fig. 57.63. fC could be made high by choosing relatively low values of R1//R2 but the additional pole can be eliminated by adding a feedback capacitor C2 across resistor R2 to give pole-zero cancellation.

[

Z1 = R1 1 + jωR1C1

]

[

and Z 2 = R2 1 + jωR2C 2

]

(57.65)

If R1 C1 = R2C2, then B = Z1/[Z1+Z2] = R1/[R1 + R2], making B frequency independent. The design equation for C2 is then C 2 = C1 ⋅ R1 R2

(57.66)

If the open-loop phase margin ΦM needs to be increased for the desired value of closed-loop gain, and the inverting capacitance C1 has its inevitable high-frequency influence, then the optimum solution for C2 would be to locate the zero on the second pole of the loop-gain response following the procedure given above.

Conclusions This chapter hopefully serves to illustrate some of the modern techniques the practicing engineer will encounter when designing broadband bipolar amplifiers. It focuses mainly upon key generic building blocks and methodologies for broadband design. Many circuits and design techniques have not been covered, but analysis techniques described should serve as a foundation for the analysis of other broadband designs. Furthermore, comprehensive analytical treatment of many alternative broadband bipolar circuits can be found in the texts [6] and [13]–[15]. © 2003 by CRC Press LLC

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Appendices A: Transfer Function and Bandwidth Characteristic of Current-Feedback Operational Amplifier vin

+

i3

buffer

v2

Ki3

K

X1

Avb CZ

RZ

Rinv

− R1

i3 i1 v1

vout

buffer

R2 i2

−i1 + i2 + i3 = 0 v1 R1

(57.68)

v out − v1 R2

(57.69)

v in − v1 Rinv

(57.70)

Ki3 RZ 1 + jωRZ C Z

(57.71)

i1 = i2 =

i3 = v2 =

(57.67)

v out = Avbv 2



(57.72)

Substituting (57.68)–(57.70) into (57.67) yields −

v1 v −v v −v + out 1 + in 1 = 0 R1 R2 Rinv

Rearranging for v1 gives v in R2 + v out Rinv v1 = R R 1+ 2 + 2 R1 Rinv From (57.71) and (57.72), it is clearly seen that v out =

Avb Ki3 RZ 1 + jωRZ C Z

Substituting for i1 and i2 from (57.68) and (57.69) into (57.67) gives 1 1 v i3 = v1  +  − out  R1 R2  R2 © 2003 by CRC Press LLC

(57.73)

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Substitute for v1:  v in R2  R + v out i3 =  inv 1 + R2 + R2  R1 Rinv 

 1 1 v   +  − out   R1 R2  R2  

Substitute for i3 from (57.73):

v out (1 + jωRZ C Z ) Avb KRZ

 v in R2 + v out   Rinv = R R  1 + 2 + 2  R R   inv 1

    1 1  v out   +  −    R1 R2  R2    

rearranging

v out

v out = v in

  1 v in R2  1 1 1 +  +       (1 + jωRZ C Z ) −  R1 R2  + 1  = Rinv  R1 R2   A KR  R2 R2  R2   R2 R2  vb Z   1 + R + R  1 + R + R       1 inv 1 inv   1+

R2 R1

 R  R R  R  Rinv 1 + 2 + 2  (1 + jωRZ C Z ) Rinv 1 + 2 + 2  R1 Rinv  R1 Rinv  1   1 − Rinv  +  + Avb KRZ R2  R1 R2 

v out = v in

1+

R2 R1

   R   R  Rinv 1 + 2  + R2  Rinv 1 + 2  + R2  jωRZ C Z R1  R1      +1 + Avb KRZ Avb KRZ

Factorize the denominator

v out = v in    R   Rinv 1 + 2  + R2  R1   1 +    Avb KRZ    

© 2003 by CRC Press LLC

1+

R2 R1

     R    Rinv 1 + 2  + R2  jωRZ C Z  R1       1 +  Avb KRZ    R2    + + 1 R R  inv  2   R  1   1 +   Avb KRZ

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R 1+ 2 v out R1 = v in     R   R  Rinv 1 + 2  + R2  Rinv 1 + 2  + R2    R1  R1    1 +  1 + jωC  Z   Avb KRZ  R     Rinv 1 + 2  + R2  R1      A K +  vb  RZ 

       

If we assume that RZ is very large, then  R  Rinv 1 + 2  + R2 R1   ≈0 RZ and the transfer function becomes

v out = v in

1+

R2 R1

   R   Rinv 1 + 2  + R2  R1    1 + jωC Z   A K vb  

The pole frequency is given by f −3 dB =

Avb K    R  2πC Z Rinv 1 + 2  + R2  R1    

The gain–bandwidth product is given by  R  Avb K 1 + 2   R1  GBW =    R  2πC Z Rinv 1 + 2  + R2  R1     B: Transfer Function and Bandwidth Characteristic of Voltage-Feedback Operational Amplifier +

vin

R1

RZ

R2 −

© 2003 by CRC Press LLC

Avb

gm −

CZ

buffer

vout

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The Circuits and Filters Handbook, Second Edition

  g m RZ Avb R1 v out =  v in − R + R2v out  1 + jωRZ C Z    R1 g m Avb RZ g A R v out 1 +  = v in m vb Z + + R R 1 j R C 1 jωRZ C Z ω +  Z Z ) 2 )(  ( 1 v out = v in

g m Avb RZ 1 + jωRZ C Z R1 g m Avb RZ 1+ (R1 + R2 )(1 + jωRZCZ )

Multiply the numerator and denominator by (1 + jωRZ CZ)/gm Avb RZ v out 1 = 1 ω j R C R1 + v in Z Z + (R1 + R2 ) g m Avb RZ v out v in

R2 R1 = 1 + jωRZ C Z   R2   1 +  +1   g m Avb RZ   R1  1+

v out = v in

1+

R2 R1

 R  R2 jωRZ C Z 1 + 2  R1  R1  + +1 g m Avb RZ g m Avb RZ 1+

get 1 + [1 + (R2/R1)/gm Avb RZ ] out of the denominator

v out = v in

1+

R2 R1

  R  jωRZ C Z 1 + 2   R1  R    1 + 2    R1 g m Avb RZ 1 +  1 + R  g m Avb RZ   1+ 2   R1   1+  g A m vb RZ 

        

multiply the denominator bracket by gm Avb Rz /[1 + (R2/R1)]

v out = v in  R  1+ 2   R1 1 +   g m Avb RZ     

© 2003 by CRC Press LLC

1+

R2 R1

  R   jωRZ C Z 1 + 2    R1    1 +   R   g m Avb RZ + 1 + 2   R1    

(57.74)

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High-Performance Analog Circuits

R 1+ 2 v out R1 = R2  v in  1+  R1   jωRZ C Z 1 +  1 +  g m Avb RZ   1 + g m Avb RZ    R2    1 + R    1 

     

assuming that gm Avb RZ is much larger than 1 + R2/R1, then

v out = v in

R2 R1  RZ C Z 1 + jω  g A R 1 + m vb Z  R2    1 + R  1  1+

     

The pole frequency is given by g m Avb RZ  R2  1 + R   1 2πRZ C Z

1+ f −3dB = The gain–bandwidth product is given by

 R2   g m Avb RZ  1 + R  1 +   R2    1  1 +   R1   GBW = 2πRZ C Z C: Transconductance of the Current-Feedback Op-Amp Input Stage +Vcc IBIAS IC1

CM1

Q1 D1 + +vin 2

D2 Q2 IBIAS

IC2

− −vin 2

Gain-node buffer

iout

Z

CM2

−Vcc

© 2003 by CRC Press LLC

vout

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The Circuits and Filters Handbook, Second Edition

v in = v1 − v 2 iout = ICI − IC 2 vBE1 vT

IC1 = I S1e IC 2 = I S 2e

vBE 2 vT

VBE1 = VDQ1 + v in VBE 2 = v in − VDQ2  VDQ1 vin   V +v  T T 

IC1 = I S1e 

 VDQ1 vin   V −v  T T 

IC 2 = I S 2e 

vin vT IC1 = ICQ CQ1e

IC 2 = ICQ2e

v − in vT

Assuming matched transistors then, ICQ1 = ICQ2 = ICQ

iout

 +  vin  −  vin   v v = IC1 − IC 2 = ICQ e  T  − e  T      

[

]

iout = y = e x − e −x = 2 sinh(x) ICQ where x = + vin /VT . D: Transfer Function of Widlar Current Mirror IOUT

IIN β1 IE1 β1 + 1 Q1

IE1 β1 + 1

IE2 β2 + 1

IE2

IE1

I IN = I E1 + I IN =

© 2003 by CRC Press LLC

Q2

I E2 β 2 +1

I E1 (β 2 +1) + I E2 β 2 +1

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High-Performance Analog Circuits

I OUT = β 2 I B2 I OUT =

β 2 I E2 β 2 +1

I OUT (β 2 I E 2 )(β 2 +1) = I IN (β 2 +1) I E1(β 2 +1) + I E2

[

]

I OUT β 2 I E2 = I IN I E1 (β 2 +1) + I E2 I OUT 1 = I IN I E1 (β 2 +1) I E2β 2

+

1 β2

For

I E1 = IE2

 β +1  I S1  1  e  β1 

vBE1 VT

 β +1  I S 2  2  e  β2 

vBE 2 vT

Then, as VBE1 = VBE2,

I E1 IE2

 β +1  I S1  1   β1  =  β +1  IS 2  2   β2 

I OUT 1 = I IN I S1 (β1 +1) I S 2β1

+

1 β2

Assume β1 = β2 = β, IS1 = IS2. Then I OUT β

= I IN β + 2

E: Transfer Function of Widlar Current Mirror with Emitter Degeneration Resistors

IIN

Q1

RE1

© 2003 by CRC Press LLC

IOUT

Q2

RE2

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The Circuits and Filters Handbook, Second Edition

Assuming that β  1, then VBE1 + I IN R1 = VBE 2 + I out R2 I out =

I IN R1 (V BE1 − VBE 2 ) + R2 R2

I OUT R1 (VBE1 − VBE 2 ) = + I IN R2 I IN R2

I OUT R1 = + I IN R2

 I I  VT ln IN S 2   I S1 I OUT  I IN R2

I OUT I IN

 I ∆VBE  V T  ln IN + I VT  R  OUT = 1 + R2 I IN R2

I OUT I IN

 I  V T  ln IN  R  I OUT  ∆VBE + = 1 + R2 I IN R2 I IN R2

Assuming that the term VT[ln(IIN/IOUT)]/IINR2 is small compared with the other terms, then I OUT R1 ∆VBE = + I IN R2 I IN R2

References [1] K. C. Smith and A. S. Sedra, “The current conveyor — A new circuit building block,” Proc. IEEE, vol. 56, pp. 1368–1369, Aug. 1968. [2] A. Sedra and K. C. Smith, “A Second Generation Current-Conveyor and its Applications,” IEEE Trans. Circuit Theory, vol. CT-17, pp. 132–134, 1970. [3] B. Wilson, “High performance current conveyor implementation,” Electron. Lett., vol. 20, no. 24, pp. 990–991, 1984. [4] C. Toumazou, F. J. Lidgey, and C. Makris, “Extending voltage-mode op-amps to current-mode performance,” Proc. IEE: Pt. G, vol. 137, no. 2, pp. 116–130, 1990. [5] PA630 Data Sheet, Photronics Co., Ottawa, P.Q., Canada. [6] C. Toumazou, F. J. Lidgey, and D. Haigh, Eds., Analogue IC Design — The Current-Mode Approach, Exeter, England: Peter Peregrinus, 1990. [7] CCII01 Data Sheet, LTP Electronics, Headington, Oxford, England. [8] D. F. Bowers, “A precision dual current-feedback operational amplifier,” in Proc. IEEE Bipolar Circuits Technol. Meet., 1988, pp. 68–70. [9] D. F. Bowers, “Applying current feedback to voltage amplifier,” in Analogue IC Design: The CurrentMode Approach, edited by C. Toumazou, F. J. Lidgey, and D. G. Haigh, Eds. Exeter, England: Peter Peregrinus, 1990, ch. 16, pp. 569–595. [10] I. A Koullias, “A wideband low-offset current-feedback op amp design,” in Proc. IEEE 1989 Bipolar Circuits Technol. Meet., Minneapolis, MN, Sep. 18–19, 1989, pp. 120–123. [11] A. Payne and C. Toumazou, “High frequency self-compensation of current feedback devices,” in Proc. IEEE ISCAS, San Diego, California, May 10–13, 1992, pp. 1376–1379. [12] T. Vanisri and C. Toumazou, “Wideband and high gain current-feedback op-amp,” Electron. Lett., vol. 28, no. 18, pp. 1705–1707, Aug. 27, 1992. © 2003 by CRC Press LLC

0912 S1-S8 Frame55.book Page 1749 Thursday, October 10, 2002 10:48 PM

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[13] A. Grebene, Bipolar and MOS Analog Integrated Circuit Design, New York: Wiley, 1984. [14] C. Toumazou, Ed., Circuits and Systems Tutorials, New York: IEEE ISCAS, 1994. [15] High Performance Analog Integrated Circuits. Élantec Data Book, 1994.

57.2 Bipolar Noise B. M. Wilamowski Bipolar transistors and other electronic devices generate internal electrical noise. This limits the device operation at a small-signal range. There are a few different sources of noise, such as thermal noise, shot noise, flicker noise or 1/f noise, burst noise or “popcorn noise,” and avalanche noise [1], [6].

Thermal Noise Thermal noise is created by random motion of charge carriers due to the thermal excitation [1]. This noise is sometimes known as the Johnson noise. The thermal motion of carriers creates a fluctuating voltage on the terminals of each resistive element. The average value of this voltage is zero, but the power on its terminals is not zero. The internal noise voltage source or current source is described by Nyquist equation v n2 = 4kTR∆f

in2 =

4kT∆f R

(57.75)

where k is the Boltzmann constant, T is absolute temperature, and 4kT is equal to 1.66 × 10–20 V· C at room temperature. The thermal noise is proportional to the frequency bandwidth ∆f. It can be represented by the voltage source in series with resistor R, or by the current source in parallel to the resistor R. The maximum noise power can be delivered to the load when RL = R. In this case, maximum noise power in the load is kT∆f. The noise power density dPn/df = kT, and it is independent of frequency. Thus, the thermal noise is the white noise. The rms noise voltage and the rms noise current are proportional to the square root of the frequency bandwidth ∆f. The thermal noise is associated with every physical resistor in the circuit. In a bipolar transistor, the thermal noise is generated mainly by series base, emitter, and collector resistances.

Shot Noise Shot noise is associated with the carrier injection through the pn junction. In each forward biased junction, there is a potential barrier that can be overcome by the carriers with higher thermal energy. This is a random process and the noise current is given by in2 = 2qI∆f

(57.76)

where q is the electron charge and I is the forward junction current. The shot noise depends on the thermal energy of carriers near the potential barrier. Similar to the thermal noise, the shot noise has constant and frequency-independent noise power density. It is also the white type of noise. Shot noise is usually considered as a current source connected in parallel to the small-signal junction resistance.

Flicker — 1/f Noise Flicker noise in bipolar transistors is associated mainly with generation-recombination centers [2]–[4]. Free carries are randomly trapped and released by these centers. This is a relatively slow process and it cannot be seen at high frequencies. The flicker noise is always associated with a current and is approxi­ mated by © 2003 by CRC Press LLC

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in2 = K F I AF

∆f f

(57.77)

where KF is the flicker-noise coefficient and AF is the flicker-noise exponent. Both KF and AF are device dependent. With modern technology, the number of trapping centers can be significantly lowered, thus the effect of flicker noise is meaningfully reduced. The 1/f nature of the flicker noise is such that sometimes this noise component is considered to be responsible for the long term device parameter fluctuation.

Other Types of Noise The burst or “popcorn” noise is another type of noise at low frequencies [3], [4]. This noise is not fully understood, but it seems that it is related to the heavy-metal ion contamination. The burst noise looks, on an oscilloscope, like a square wave with the constant magnitude, but with random pulse widths. It has significant effect at low frequencies. In audio amplifiers, the burst noise sounds as random shoots, which are similar to the sound associated with making popcorn. Obviously, bipolar transistors with large burst noise must not be used in audio amplifiers and in other analog circuitry. The burst noise is often approximated by in2 = K B

iDAB  f  1+    fB 

2

∆f

(57.78)

where KB , AB , and fB are experimentally chosen parameters, which usually vary from one device to another. Furthermore, a few different sources of the burst noise can exist in a single transistor. In such a case, each noise source should be modeled by a separate Eq. (57.78) with different parameters (usually different corner frequency fB). The avalanche noise is another noise component, which can be found in bipolar transistors. For large reverse voltages on the collector junction, the collector current can be multiplied by the avalanche phe­ nomenon. Carriers in the collector-base junctions gain energies in high electrical field, then losing this energy during collision with the crystal lattice. If the energy gained between collisions is large enough, then during collision another pair of carriers (electron and hole) can be generated. This way, the collector current can be multiplied. This is a random process and obviously the noise source is associated with the avalanche carrier generation. The magnitude of the avalanche noise is usually much larger than any other noise component. Fortunately, the avalanche noise exists only in the pn junction biased with a voltage close to the breakdown voltage. The avalanche phenomenon is often used to build the noise sources [5].

Noise Characterization Many different methods are used in literature for noise characterization. Sometimes the noise is charac­ terized by an equivalent noise resistance, sometimes by an equivalent noise temperature, sometimes by an equivalent rms noise voltage or current or sometimes by a noise figure. Equivalent Noise Voltage and Current The equivalent noise voltage or current is the most commonly used method for modeling the noise in semiconductor devices. The equivalent diagram of the bipolar transistor, including various noise com­ ponents, is shown in Fig. 57.64. The noise components are given by i B2 =

4kT∆f rB

i c2 = 2qI C ∆f

© 2003 by CRC Press LLC

i 2E =

4kT∆f rE

iC2 =

4kT∆f rC

(57.79)

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High-Performance Analog Circuits

C  iC 2



iB 2

rC CCS

CBC 

rB

B

rπ

ib 2



ic 2

gm v1

CBE

ro

S



iE 2

rE E

FIGURE 57.64 Equivalent diagram of the bipolar transistor, which includes noise sources.

i b2 = 2qI B ∆f + K F

I BA F ∆f + K B f

I BAB  f  1+    fB 

2

∆f

Thermal noise is associated with physical resistors only, such as base, emitter, and collector series resis­ tances. The small-signal equivalent resistances, such as rπ and r0, do not exhibit thermal noise. The shot noise is associated with both collector and base currents. It was found experimentally that the flicker and the burst noise are associated with base current. The typical noise characteristic of a bipolar transistor is shown in Fig. 57.65. The corner frequency of the flicker noise can vary from 100 Hz to 1 MHz. Equivalent Noise Resistance and Noise Temperature The noise property of a two-port element can be described by a noise current source connected in parallel to the output terminals, as Fig. 57.66(a) shows. Knowing that noise current can be expressed as the shot noise of the dc device current [(57.76)], the two-port noise can be expressed by means of an equivalent dc noise current I eq =

in2 2q∆f

(57.80)



log

ib 2 ∆f

2 qIB KF

IBAF f

fF

FIGURE 57.65 Bipolar noise as a function of frequency. © 2003 by CRC Press LLC

log(f)

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RS + − vs

RS noiseless two-port



in 2

RL

RN

+ − vs

(a)

noiseless two-port

RL

(b)

FIGURE 57.66 Noise characterization for two-ports: (a) using the noise source at the output, (b) using noise resistance RN at the input.

Another way to model the two-port noise in the two-port is to use the thermal noise at the input. This can be done using an additional “noisy” resistor connected to the input, as Fig. 57.66(b) shows: Rn =

2 v n1 v2 = 2 n2 4kT∆f Av 4kT∆f

(57.81)

where Av is the voltage gain of the two-part, and vn21 and vn22 are equivalent noise voltage sources at the input and the output, respectively. The equivalent noise resistance is not a very convenient way to represent the noise property of the two-port. This additional resistance Rn must not be on the circuit diagram for small-signal analysis. To overcome this difficulty the concept of the equivalent noise tem­ perature was introduced. This is a temperature increment of the source resistance required to obtain the same noise magnitude at the output if this source resistance is the only noise source. The noise temper­ ature can be calculated from the simple formula Tn =

Rn 290 K Rs

(57.82)

where Rn and Rs are shown in Fig. 57.66(b). It is customary to use 290 K as the reference room temperature for the noise temperature calculations. Noise Figure The noise figure is the ratio of the output noise of the actual two-port to the output noise of the ideal noiseless two-port when the resistance of the signal source Rs is the noise source.   total output noise F = 10 log    output noise due to the source resistance

(57.83)

The noise figure F is related to the noise resistance and the noise temperature in the following way:  R  T   F = 10 log 1 + n  = 10 log 1 + n   290 K Rs  

(57.84)

The noise figure F is the most common method of noise characterization.

References [1] A. Van der Ziel, Noise, Englewood Cliffs, NJ: Prentice Hall, 1954. [2] J. L. Plumb and E. R. Chenette, “Flicker noise in transistors,” IEEE Trans. Electron Devices, vol. ED­ 10, pp. 304–308, Sep. 1963. [3] R. C. Jaeger and A. J. Broderson, “Low-frequency noise sources in bipolar junction transistors,” IEEE Trans. Electron Devices, Vol. ED-17, pp. 128–134, Feb. 1970. © 2003 by CRC Press LLC

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[4] R. G. Meyer, L. Nagel, and S. K. Lui “Computer simulation of 1/f noise performance of electronic circuits,” IEEE J. Solid-State Circuits, vol. SC-8, pp. 237–240, June 1973. [5] R. H. Haitz, “Controlled noise generation with avalanche diodes,” IEEE Trans. Electron Devices, vol. ED-12, pp. 198–207, April 1965. [6] P. R. Gray and R. G. Mayer, Analysis and Design of Analog Integrated Circuits, 3rd ed., New York: Wiley, 1993.

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58 RF Communication Circuits 58.1 Introduction 58.2 Technology Active Devices • Passive Devices

58.3 The Receiver Receiver Topologies • Full Integration • The DownConverter • The LNA

58.4 The Synthesizer Synthesizer Topology • The Oscillator • The Prescaler • Fully Integrated Synthesizer

Michael Steyaert Marc Borremans Johan Janssens Bram De Muer

58.5 The Transmitter

Katholieke Universiteit Leuven, ESAT-MICAS

58.6 Toward Fully Integrated Transceivers 58.7 Conclusion

Down-Conversion vs. Up-Conversion • CMOS Mixer Topologies

58.1 Introduction A few years ago, the world of wireless communications and its applications started to grow rapidly. The main cause for this event was the introduction of digital coding and digital signal processing in wireless communications. This digital revolution is driven by the development of high-performance, low-cost, CMOS technologies that allow for the integration of an enormous amount of digital functions on a single die. This allows, in turn, for the use of sophisticated modulation schemes, complex demodulation algorithms, and high-quality error detection and correction systems, resulting in high-performance lossless commu­ nication channels. Today, the digital revolution and the high growth of the wireless market also bring many changes to the analog transceiver front-ends. The front-ends are the interface between the antenna and the digital modem of the wireless transceiver. They have to detect very weak signals (µV) which come in at a very high frequency (1 to 2 GHz) and, at the same time, they have to transmit at the same high-frequency high power levels (up to 2 W). This requires high-performance analog circuits, like filters, amplifiers, and mixers which translate the frequency bands between the antenna and the A/D-conversion and digital signal processing. Low cost and a low power consumption are the driving forces and they make the analog front-ends the bottleneck for future RF design. Both low cost and low power are closely linked to the trend toward full integration. An even further level of integration renders significant space, cost, and power reductions. Many different techniques to obtain a higher degree of integration for receivers, transmitters, and synthesizers have been presented over the past years.1-3 This chapter introduces and analyzes some advantages and disadvantages and their fundamental limitations.

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Parallel to the trend to further integration, there is the trend to the integration of RF circuitry in CMOS technologies. The mainstream use for CMOS technologies is the integration of digital circuitry. The use of these CMOS technologies for high-performance analog circuits yields, however, many benefits. The technology is, of course — if used without any special adaptations toward analog design — cheap. This is especially true if one wants to achieve the ultimate goal of full integration: the complete transceiver system on a single chip, with both the analog front-end and the digital demodulator implemented on the same die. This can only be achieved in either a CMOS or a BiCMOS process. BiCMOS has better devices for analog design, but its cost will be higher, not only due to the higher cost per area, but also due to the larger area that will be needed for the digital part. Plain CMOS has the extra advantage that the performance gap between devices in BiCMOS and nMOS devices in deep sub-micron CMOS, and even nMOS devices in the same BiCMOS process, is becoming smaller and smaller due to the much higher investments in the development of CMOS than bipolar. The fT’s of the nMOS devices are getting close to the fT’s of npn devices. Although some research had been done in the past on the design of RF in CMOS technologies,4 it is only in the few years that real attention has been given to its possibilities.5,6 Today several research groups at universities and in industry are researching this topic.2,3,7,9 As bipolar devices are inherently better than CMOS devices, RF CMOS is by some seen as a possibility for only low-performance systems, with reduced specification (like ISM),8,10 or that the CMOS processes need adaptations, like substrate etching under inductors.7 Others feel, however, that the benefits of RF CMOS can be much bigger and that it will be possible to use plain deep sub-micron CMOS for the full integration of transceivers for high-performance applications, like GSM, DECT, and DCS 1800.2,3 First, this chapter analyzes some trends, limitations, and problems in technologies for high-frequency design. Second, the down-converter topologies and imple­ mentation problems are addressed. Third, the design and trends toward fully integrated low-phase noise PLL circuits are discussed. Finally, the design of fully integrated up-converters is studied.

58.2 Technology Active Devices Due to the never-ending progress in technology and the requirement to achieve a higher degree of integration for DSP circuits, sub-micron technologies are nowadays considered standard CMOS tech­ nologies. The trend is even toward deep sub-micron technologies (e.g., transistor lengths of 0.1 µm. Using the square law relationship for MOS transistors to calculate the ft of a MOS device no longer holds, due to the high electrical fields. Using a more accurate model, which includes the mobility degradation due to the high electrical fields, results in

ft =

=

gm 2π C gs µ 2π 2 3L2

(V

)   µ  1 + 2 q +  (V  v L  gs

−Vt

max

(58.1)

gs

 −Vt  

)

Hence, by going to deep sub-micron technologies, the square law benefit in L for speed improvement drastically reduces due to the second term in the denominator of Eq. (58.1). Even for very deep sub­ micron technologies, the small signal parameter gm has no square law relationship anymore:

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RF Communication Circuits

FIGURE 58.1

Comparison of ft and fmax.

gm =

(

µCoxW Vgs −Vt

)

   µ  L1 + 2 θ + Vgs −Vt   vmax L    

(

)

(58.2)

with transistor lengths smaller than approximately

L
ωB , the positive pulses appear at QB while QA = 0. If ωA = ωB, then the PFD generates pulses at either QAor QB with a width equal to the phase difference between the two inputs. The outputs QAand QB are usually called the “up” and “down” signals, respectively. If the input signal fails, which usually happens at the NRZ data recovery applications during missing or extra transmissions, the output of the PFD would stick on the high state (or low state). This condition may cause the VCO to oscillate fast or slow abruptly, which results in noise jitter or even losing lock. This problem can be remedied by additional control logic circuits to make the PFD output toggle back and forth between the two logic levels with 50% duty cycle,18 the loop is interpreted as zero phase error. The “rotational FD” described by Messerschmitt can also solve this issue.9 The output of a PFD can be converted to a dc control voltage by driving a three-state charge-pump, as described in Section 59.2. © 2003 by CRC Press LLC

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FIGURE 59.19 Waveforms of the signals for the JK-flipflop phase detector: (a) waveforms at zero phase error, (b) waveforms at positive phase error

59.4 PLL Applications Clock and Data Recovery In data transmission systems such as optical communications, telecommunications, disk drive systems, and local networks, data is transmitted on baseband or passband. In most of these applications, only data signals are transmitted by the transmitter; clock signals are not transmitted in order to save hardware cost. Therefore, the receiver should have some scheme to extract the clock information from the received data stream and regenerate transmitted data using the recovery clock. This scheme is called timing recovery or clock recovery. To recover the data correctly, the receiver must generate a synchronous clock from the input data stream, and the recovered clock must synchronize with the bit rate (the baud of data). The PLL can be used to recover the clock from the data stream, but some special design considerations must be addressed. For example, because of the random nature of data, the choice of phase-frequency detectors is restricted. In particular, a three-state PD is not proper; because of missing data transitions, the PD will interpret the VCO frequency to be higher than the data frequency, and the PD output stays on “down” state to make the PLL lose lock, as shown in Fig. 59.21. Thus, the choice of phase-frequency detector for random binary data requires a careful examination of their responses when some transitions are absent. One useful method is the rotational frequency detector described in Reference 9. The random data also causes the PLL to introduce undesired phase variation in the recovered clock; this is called timing jitter and is an important issue of the clock recovery.

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(a)

(b) FIGURE 59.20

(a) PFD diagram and (b) input and output waveforms of PFD.

FIGURE 59.21

Response of a three-state PD to random data.

Data Format Binary data is usually transmitted in a NRZ (Non-Return-to-Zero) format, as shown in Fig. 59.22(a), because of the consideration of bandwidth efficiency. In NRZ format, each bit has a duration of TB (bit period). The signal does not go to zero between adjacent pulses representing 1’s. It can be shown23 in 1 that the corresponding spectrum has no line component at ƒB = ----TB ; most of the spectrum of this signal fB lines below --- . The term “non-return-to-zero” distinguishes from another data type called “return-to­ 2 zero” (RZ), as shown in Fig. 59.22(b), in which the signal goes to zero between consecutive bits. Therefore,

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1806

FIGURE 59.22

The Circuits and Filters Handbook, Second Edition

(a) NRZ data and (b) RZ data.

the spectrum of RZ data has a frequency component at ƒB . For a given bit rate, RZ data needs wider transmitting bandwidth; therefore, NRZ data is preferable when channel or circuits bandwidth is a concern. Due to the lack of a spectral component at the bit rate of NRZ format, a clock recovery circuit may lock to spurious signals or fail to lock at all. Thus, a non-linear process at NRZ data is essential to create a frequency component at the baud rate. Data Conversion One way to recover a clock from NRZ data is to convert it to RZ-like data that has a frequency component at bit rate, and then recover clock from data using a PLL. Transition detection is one of the methods to convert NRZ data to RZ-like data. As illustrated in Fig. 59.23(a), the edge detection requires a mechanism to sense both positive and negative data transitions. In Fig. 59.23(b), NRZ data is delayed and compared with itself by an exclusive-OR gate; therefore, the transition edges are detected. In Fig. 59.24, the NRZ data Vi is first differentiated to generate pulses corresponding to each transition. These pulses are made to be all positive by squaring the differentiated signal v·i . The result is the signal V i′ that looks just like RZ data, where pulses are spaced at an interval of TB .

FIGURE 59.23

Edge detection of NRZ data.

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PLL Circuits

FIGURE 59.24

Converting NRZ to RZ-like signal.

Clock Recovery Architecture Based on different PLL topologies, there are several clock recovery approaches. Here, the early-late and the edge-detector based methods are described. Figure 59.25 shows the block diagram of the early-late method. If the input lags the VCO output, Fig. 59.26 shows the waveforms for this case. In Fig. 59.26, the early integrator integrates the input signal for the early-half period of the clock signal and holds it for remainder of the clock signal. On the other hand, the late integrator integrates the input signal for the late-half period of the clock signal and holds it for the next early-half period. The average difference between the absolute values of the late hold and the early hold voltage generated from a low-pass filter gives the control signal to adjust the frequency of the VCO. As mentioned previously, this method is popular for rectangular pulses. However, this method has some drawbacks. Since this method relies on the shape of pulses, a static phase error can be introduced if the pulse shape is not symmetric. In high-speed applications, this approach requires a fast settling integrator that limits the operating speed of the clock recovery circuit and the acquisition time cannot be easily controlled.

FIGURE 59.25

Early-late block diagram.

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1808

FIGURE 59.26

The Circuits and Filters Handbook, Second Edition

Clock waveforms for early-late architecture.

The most widely used technique for clock recovery in high-performance, wide-band data transmission applications is the edge-detection based method. The edge-detection method is used to convert data format such that the PLL can lock the correct band frequency. More details were given in the previous subsection. There are many variations of this method, depending on the exact implementation of each PLL loop component. The “quadricorrelator” introduced by Richman7 and modified by Bellisio24 is a frequency-difference discriminator and has been implemented in a clock recovery architecture. Figure 59.27 is a phase-recovery locked loop using edge-detection method and quadricorrelator to recover timing information from NRZ data.25 As shown in Fig. 59.27, the quadricorrelator follows the edgedetector with a combination of three loops sharing the same VCO. Loop I and II form a frequency-locked loop that contains the quadricorrelator for frequency detection. Loop III is a typical phase-locked loop for phase alignment. The phase- and frequency-locked loops share the same VCO; the interaction between two loops is a very important issue. As described in Reference 25, when ω1 ≈ ω2 , the dc feedback signal produced by loop I and II approaches zero, and loop III dominates the loop performance. A composite frequency- and phase-locked loop is a good method to achieve fast acquisition and a narrow PLL loop

FIGURE 59.27

Quadricorrelator.

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PLL Circuits

bandwidth to minimize the VCO drift. Nevertheless, because the wide band frequency-locked loop can respond to noise and spurious components, it is essential to disable the frequency-locked loop when the frequency error gets into the lock-in range of the PLL to minimize the interaction. More clock recovery architectures are described in References 18, 20, 22, and 26–28.

Frequency Synthesizer A frequency synthesizer generates any of a number of frequencies by locking a VCO to an accurate frequency source such as a crystal oscillator. For example, RF systems usually require a high-frequency local oscillator whose frequency can be changed in small and precise steps. The ability to multiply a reference frequency makes PLLs attractive for synthesizing frequencies. The basic configuration used for frequency synthesis is shown in Fig. 59.28(a). This system is capable of generating an integer multiple frequency of a reference frequency. A quartz crystal is usually used as the reference clock source because of its low jitter characteristic. Due to the limited speed of a CMOS device, it is difficult to generate frequency directly in the range of GHz or more. To generate higher frequencies, prescalers are used; they are implemented with other IC technologies such as ECL. Figure 59.28(b) shows a synthesizer structure using a prescaler V; the output frequency becomes

fout =

NVfi M

(59.46)

Because the scaling factor V is much greater than one, obviously, it is no longer possible to generate any desired integer multiple of the reference frequency. This drawback can be circumvented by using a so-called dual-modulus prescaler, as shown in Fig. 59.29. A dual-modulus prescaler is a divider whose division can be switched from one value to another by a control signal. The following shows that the dual-modulus prescaler makes it possible to generate a number of output frequencies that are spaced only by one reference frequency. The VCO output is divided by V/V+1 dual-modulus prescaler. The

FIGURE 59.28 Frequency-synthesizer block diagrams: (a) basic frequency-synthesizer system; (b) system extends the upper frequency range by using an additional high-speed prescaler.

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1810

FIGURE 59.29

The Circuits and Filters Handbook, Second Edition

The block diagram of dual-modulus frequency synthesizer. 1

1

- and a “swallow counter” --- . The dual-modulus output of the prescaler is fed into a “program counter” --N A prescaler is set to divide by V+1 initially. After “A” pulses out of the prescaler, the swallow counter is full and changes the prescaler modulus to V. After additional “N-A” pulses out of the prescaler, the program counter changes the prescaler modulus back to V+1, restarts the swallow counter, and the cycle is repeated. In this way, the VCO frequency is equal to (V + 1) A + V (N – A) = VN + A times the reference frequency. Note that N must be larger than A. If this is not the case, the program counter would be full earlier than 1 --- , and both counters would be reset. Therefore, the dual-modulus prescaler would never be switched A from V + 1 to V. For example, if V = 64, then A must be in the range of 0 to 63 such that Nmin = 64. The smallest realizable division ratio is

(N ) tot

min

= N min V = 4096

(59.47)

The synthesizer of Fig. 59.29 is able to generate all integer multiples of the reference frequency, starting from Ntot = 4096. For extending the upper frequency range of frequency synthesizers, but still allowing the synthesis of lower frequency, the four-modulus prescaler is a solution.1 Based on the previous discussions, the synthesized frequency is an integer multiple of a reference frequency. In RF applications, the reference frequency is usually larger than the channel spacing for loop dynamic performance considerations, in which the wider loop bandwidth for a given channel spacing allows faster settling time and reduces the phase jitter requirements to be imposed on the VCO. Therefore, a “fractional” scaling factor is needed. Fractional division ratios of any complexity can be realized. For example, a ratio of 3.7 is obtained if a counter is forced to divide by 4 in seven cycles of each group of ten cycles and by 3 in the remaining three cycles. On the average, this counter effectively divides the input frequency by 3.7.

References 1. R. E. Best, Phase-Locked Loops Theory, Design, Applications, McGraw-Hill, New York, 1984. 2. D. G. Troha and J. D. Gallia, Digital phase-locked loop design using S-N54/74LS297, Application Note AN 3216, Texas Instruments Inc., Dallas, TX. 3. W. B. Rosink, All-digital phase-locked loops using the 74HC/HCT297, Philips Components, 1989. 4. F. M. Gardner, Phaselock Techniques, 2nd ed.

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1811

5. S. G. Tzafestas, Walsh Functions in Signal and Systems Analysis and Design, Van Nostrand Reinhold, New York, 1985. 6. F. M. Gardner, Acquisition of phaselock, Conference Record of the International Conference on Communications, vol. I, pp. 10-1–10-5, June 1976. 7. D. Richman, Color carrier reference phase synchronization accuracy in NTSC color television, Proc. IRE, vol. 42, pp. 106–133, Jan. 1954. 8. F. M. Gardner, Properties of frequency difference detector, IEEE Trans. on Communication, vol. COM-33, no. 2, pp. 131–138, Feb. 1985. 9. D. G. Messerschmitt, Frequency detectors for PLL acquisition in timing and carrier recovery, IEEE Trans. on Communication, vol. COM-27, no. 9, pp. 1288–1295, Sep. 1979. 10. R. B. Lee, Timing recovery architecture for high speed data communication system, Masters thesis, 1993. 11. M. Bazes, A novel precision MOS synchronous delay lines, IEEE J. Solid-State Circuits, vol. 20, pp. 1265–1271, Dec. 1985. 12. M. G. Johnson and E. L. Hudson, A variable delay line PLL for CPU-coprocessor synchronization, IEEE J. Solid-State Circuits, vol. 23, pp. 1218–1223, Oct. 1988. 13. B. Kim, T. C. Weigandt, and P. R. Gray, PLL/DLL systems noise analysis for low jitter clock synthesizer design, ISCAS Proc., pp. 31–35, 1994. 14. M. V. Paemel, Analysis of a charge-pump PLL: a new model, IEEE Trans. on Comm., vol. 42, no. 7, pp. 131–138, Feb. 1994. 15. F. M. Gardner, Charge-pump phase-locked loops, IEEE Trans. on Comm., vol. COM-28, pp. 1849–1858, Nov. 1980. 16. F. M. Gardner, Phase accuracy of charge pump PLL’s, IEEE Trans. on Comm., vol. COM-30, pp. 2362–2363, Oct. 1982. 17. T. C. Weigandt, B. Kim, and P. R. Gray, Analysis of timing recovery jitter in CMOS ring oscillator, ISCAS Proc., pp. 27–30, 1994. 18. T. H. Lee and J. F. Bulzacchelli, A 155-MHz clock recovery delay- and phase-locked loop, IEEE J. of Solid-State Circuits, vol. 27, no. 12, pp. 1736–1746, Dec. 1992. 19. M. P. Flyun and S. U. Lidholm, A 1.2 µm CMOS current-controlled oscillator, IEEE J. Solid-State Circuits, vol. 27, no. 7, pp. 982–987, July 1992. 20. S. K. Enam and A. A. Abidi, NMOS IC’s for clock and data regeneration in gigabit-per-second optical-fiber receivers, IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1763–1774, Dec. 1992. 21. M. Horowitz et al., PLL design for a 500MB/s interface, ISSCC Digest Technical Paper, pp. 160–161, Feb. 1993. 22. A. Pottbacker and U. Langmann, An 8GHz silicon bipolar clock-recovery and data-regenerator IC, IEEE J. Solid-State Circuits, vol. 29, no. 12, pp. 1572–1751, Dec. 1994. 23. B. P. Lathi, Modern Digital and Analog Communication System, HRW, Philadelphia, 1989. 24. J. S. Bellisio, A new phase-locked loop timing recovery method for digital regenerators, IEEE Int. Comm. Conf. Rec., vol. 1, pp. 10-17–10-20, June 1976. 25. B. Razavi, A 2.5-Gb/s 15-m W clock recovery circuit, IEEE J. Solid-State Circuits, vol. 31, no. 4, pp. 472–480, April 1996. 26. R. J. Baumert, P. C. Metz, M. E. Pedersen, R. L. Pritchett, and J. A. Young, A monolithic 50-200MHz CMOS clock recovery and retiming circuit, IEEE Custom Integrated Circuits Conf., pp. 14.5.5–14.5.4, 1989. 27. B. Lai and R. C. Walker, A monolithic 622Mb/s clock extraction data retiming circuit, IEEE Inter. Solid-State Circuits Conf., pp. 144–145, 1991. 28. B. Kim, D. M. Helman, and P. R. Gray, A 30MHz hybrid analog/digital clock recovery circuit in 2-µm CMOS, IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1385–1394, Dec. 1990.

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IX

The VLSI Circuits John Choma, Jr. University of Southern California 60 Digital Circuits John P. Uyemura, Bing J. Sheu, Robert C. Chang MOS Logic Circuits • Transmission Gates

61 Digital Systems F. Gail Gray, Wayne D. Grover, Josephine C. Chang, Bing J. Sheu, Roland Priemer, Kung Yao, Flavio Lorenzelli Programmable Logic Devices • Clocking Schemes • MOS Storage Circuits • MicroprocessorBased Design • Systolic Arrays

62 Data Converters Bang-Sup Song, Ramesh Harjani Digital-to-Analog Converters • Analog-to-Digital Converters

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60 Digital Circuits

John P. Uyemura Georgia Institute of Technology

60.1 MOS Logic Circuits Introduction • MOSFET Models for Digital Circuits • The Digital Inverter • nMOS Logic Gates • CMOS Inverter • Static CMOS Logic Gates • Dynamic CMOS Logic Gates

Bing J. Sheu Nassda Corporation

Robert C. Chang

60.2 Transmission Gates Digital Processing • Analog Processing

National Chung Hsing University

60.1 MOS Logic Circuits John P. Uyemura Introduction MOS-based technology has become the default standard for high-density logic designs for several reasons. The most obvious is that MOSFETs can be made with side dimensions of 0. As shown in Fig. 60.1, the primary device voltages are VDS, VGS, and VSB. The value gate-source voltage VGS relative to the threshold voltage VTn determines if drain current ID flows. If VGS, < VTn then ID ≈ 0, establishing the condition of cutoff. Elevating the gate-source voltage to a value VGS, > VTn places the MOSFET into the active region where ID will be nonzero if a drain-source voltage VDS is applied; the value of ID depends on the values of the device voltages. To describe active operation, we introduce the drain-source saturation voltage VDS, sat defined by VDS,sat = VGS − VTn

(60.1)

The threshold voltage is affected by the affected by the source-bulk (body) voltage VSB by VTn = VT 0n + γ  2 φ F + VSB − 2 φ F 

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(60.2)

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Drain ID

+

VSG

Bulk Gate

−

+ VGS

Gate

VDS

Source + − VBS +

−

Bulk

VSB +

−

ID

Source

+ VSD −

Drain

(a)

(b)

FIGURE 60.1 MOSFET symbols. (a) n-channel MOSFET; (b) p-channel MOSFET.

where VT0n is the nFET zero-body-bias threshold voltage, γ is the body bias (or, body effect) coefficient, and φF is the bulk Fermi potential. When VDS ≤ VDS,sat , the MOSFET is nonsaturated with β  2 I D ≈  n  2(VGS − VTn )VDS − VDS  2

[

]

(60.3)

In this equation βn is the device transconductance given by βn = kn′ (W/L), with kn′ the process transcon­ ductance in units of [A/V2], W the channel width, and L the channel length; the width-to-length (W/L) is called the aspect ratio of the transistor. The process transconductance is given by kn′ = µ nCox , where µn is the electron surface mobility and Cox the oxide capacitance per unit area. For an oxide layer with thickness tox , the MOS capacitance per unit area is calculated from Cox =

ε ox t ox

(60.4)

where εox is the oxide permittivity. In the current technologies tox is smaller than about 60 Å. If VDS ≥ VDS sat, the MOSFET is saturated with 2 β  I D ≈  n  (VGS − VTn )  2

(60.5)

This ignores several effects, most notably that of channel-length modulation, but is still a reasonable approximation for estimating basic performance parameters. The structure of the MOSFET gives rise to several parasitic capacitances that tend to dominate the circuit performance. Two types of capacitors are contained in the basic model shown in Fig. 60.2. The contributions CGS and CGD are due to the MOS layering of the gate-oxide-semiconductor, which is the origin of the field effect. The total gate capacitance GG is calculated from CG = Cox WL

(60.6)

Drain CGD

CDB Bulk

CG Gate CSB

CGS Source

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FIGURE 60.2 MOSFET capacitances.

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and the gate-source and gate-drain contributions can be approximated to first order by CGD ≈

CG ≈ CGS 2

(60.7)

Capacitors CDB and CSB are depletion contributions from the reverse-biased pn junction at the drain and source. These are nonlinear, voltage-dependent elements that decrease with increasing reverse voltage. A p-channel MOSFET (pMOS or pFET) is the electrical complement of an n-channel device. An enhancement-mode pFET is defined to have a negative threshold voltage, i.e., VTp < 0. It is common to use device voltage of VSG , VSD , and VBS , as shown in Fig. 60.1 to describe the operation. Cutoff occurs if VSG < VTp , while the device is active if VSG ≥ VTp . The saturation voltage of the pFET is defined by VSD,sat = VSG − VTp

(60.8)

With VSG ≥ VTp  and VSG < VSD, sat, the transistor is nonsaturated with

(

)

β  2  I D ≈  p  2 VSG − VTp VSD − VSD   2

(60.9)

For the pFET, βp is the device transconductance βp = k ′p (W/L); where k ′p = µp Cox is the process transconductance, and (W/L) is the aspect ratio of the device. In complementary metal oxide-semicon­ ductor inverters (CMOS) nFETs and pFETs are used in the same circuit, and it is important to note that k n′ > k ′p due to the fact that the electron mobility is larger than the hole mobility, typically by a factor of 2 to 8. It is often convenient to use the simplified MOSFET symbols shown in Fig. 60.3. The polarity of the transistor (nMOS or pMOS) is made explicit by the absence or presence of the gate inversion “bubble”, as shown. These symbols do not show the bulk electrode explicitly, but it is important to remember that all nFETs have their bulks connected to the lowest voltage in the circuit (usually ground), while all pFET bulks are connected to the highest voltage (usually the power supply VDD). In digital circuit design, it is useful to model MOSFETs as voltage-controlled switches, as shown in Fig. 60.4. The MOSFET switches are controlled by a gate input signal G, which is taken to be a Boolean variable. Employing a positive logic convention, G = 0 corresponds to a low voltage (below VTn), while G = 1 is a high voltage. The operation of the FET switches is straightforward. An input of G = 0 places the nFET into cutoff, corresponding to an OPEN switch; G = 1 implies active operation, and the switch is CLOSED. The pFET has a complementary behavior, with G = 0 giving a CLOSED switch, and G = 1 giving an OPEN switch.

Drain

Gate

Source

Gate

Source (a)

FIGURE 60.3 Simplified MOSFET symbols. (a) nMOSFET; (b) pMOSFET.

© 2003 by CRC Press LLC

Drain (b)

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Rn

Rn

Rn G=0

G

G=1 CLOSED

OPEN

(a)

Rp

Rp

Rp

G=0

G

G=1 CLOSED

OPEN

(b)

FIGURE 60.4 MOSFET switching models. (a) nFET switch model; (b) pFET switch model.

The switch models include parasitic drain-to-source resistance Rn and Rp , which are usually estimated using Rn =

1 kn′ (W L)n (VDD − VTn )

Rp =

1

(60.10)

(

k p′ (W L) p VDD − VTp

)

These equations illustrate the general dependence that the drain-source resistance R is inversely propor­ tional to the aspect ratio (W/L). However, the MOSFET is at best a nonlinear resistor, so that these are only rough estimates. It is important to note the MOSFET parasitic capacitances CGS , CGD , CSB , and CDB must be included in the switching models when performing transient analysis.

The Digital Inverter An ideal digital inverter is shown in Fig. 60.5. In terms of the Boolean variable A, the inverter accepts A – and produces the complement A. Electronic implementation of the inverter requires assigning voltage ranges for Vin and Vout to represent logic 0 and logic 1 states. These are chosen according to the DC voltage transfer characteristics (VTC) of the electronic circuit. A VTC is simply a plot of the output voltage Vout as a function of Vin; a general VTC is shown in Fig. 60.6. VDD

 A

A

+

+ Vin (a)

Cout

−

− (b)

FIGURE 60.5 Basic inverter. (a) Ideal inverter symbol. (b) Electronic parameters. © 2003 by CRC Press LLC

Vout

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Vout VDD VOH Unity Gain Line Vout = Vin VI

VOL 0

VT

VIL

VI

Vin

VIH

VDD

FIGURE 60.6 Inverter voltage transfer characteristics.

Consider first the output voltage Vout. The maximum value of Vout is denoted by VOH , and is called the output high voltage. This is used to represent an ideal logic 1 output voltage. Conversely, the smallest value of Vout is denoted as VOL , and is called the output low voltage. VOL is the output logic 0 voltage. The logic swing of the inverter is then defined by (VOH – VOL). The range of input voltage Vin used to represent logic 0 and logic 1 input states is usually determined by points on the VTC at which the slope has a value of (dVout /dVin) = –1. Logic 0 voltages are those with values between 0 V and VIL, the input low voltage. Similarly, voltages in the range from the input voltage VIH to VOH represent logic 1 input levels. The intersection of the VTC with the unity gain line defined by Vout = Vin gives the inverter threshold voltage VI; this represents the switching point of the circuit. The numerical value of VOH , VOL VIL , VIHt , and VI are determined by the circuit and topology and the characteristics of the devices used in the circuit. The transient characteristics of the gate are defined by two basic transition times. Figure 60.7 shows Vin and Vout , and the most important output switching intervals. The input voltage has been taken as an ideal step-like pulse. In a more realistic situation the input voltage is better approximated by a ramp or an exponential. The idealized pulse is used here because it allows a comparison among various circuits. Vin VOH

VOL t Vout tHL

tLH

VOH

VOL

t tPHL

FIGURE 60.7 Inverter switching times. © 2003 by CRC Press LLC

tPLH

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The most important switching properties of the inverter are the low-to-high time tLH , and the highto-low time tHL as shown in Fig. 60.7. These represent the minimum response times of the inverter. Note that these time intervals are usually defined between the 10 and 90% voltages instead of the full logic swing. The maximum switching frequency is computed from f max =

1 t LH + t HL

(60.11)

The propagation delay tP for the gate is the average time required for a change in the input to be seen at the output. It is computed using the time intervals tPHL and tPLH shown in the diagram from  1 t P =   (t PHL + t PLH )  2

(60.12)

Note that the transition times for this parameter are measured to the 50% voltage.

nMOS Logic Gates Early generations of MOS logic circuits were based on a single type of MOSFET. The Intel 4004, for example, used only pMOS transistors, while subsequent microprocessor chips such as the Intel 8088, the Zilog Z80, and the Motorola 6800 used only n-channel MOSFETs. Although all current MOS-based designs are implemented in CMOS, which employs both nMOS and pMOS devices, it is worthwhile to examine nMOS-only logic circuits. This provides an introduction to the basic characteristics of MOS logic circuits, many of which are used in even the most advanced CMOS techniques. Several types of inverter circuits can be constructed using n-channel MOSFETs. Three configurations are shown in Fig. 60.8. Each circuit uses a switching transistor MD, known as the driver, which is controlled by the input voltage Vin. The VTC is determined by the load device that connects the drain of MD to the power supply VDD . The MD can be viewed as the switched “pull-down” device, while the load serves as the “pull-up” device. In Fig. 60.8(a) a simple linear resistor with a value RL is used as the load. The circuits in part (b) of the figure use an enhancement-mode (defined with VTn > 0) nMOSFET biased into saturation, while (c) has a depletion-mode nMOSFET (where VTn < 0) as an active load. Active loads provide better switching characteristics due to the nonlinearity of the device. In addition, MOSFETs are much smaller than resistors and process variations are not as critical because the circuit characteristics depend on the ratio of driver-to-load dimensions. VDD

VDD

VDD

βL

ML

βL

ML

RL IL ID

IL +

βD

MD

MD +

Vout Vin

ID

−

− (a)

+

ID +

Vout Vin

−

− (b)

+

βD

MD Vout

Vin

IL

+

−

− (c)

FIGURE 60.8 nMOS inverter circuits. (a) Resistor load; (b) saturated enhancement model MOSFET load; (c) depletion mode MOSFET load.

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Although the three nMOS inverter circuits are similar in structure, they have distinct switching properties. Consider the output voltage swing. Circuits (a) and (c) of the figure both have VOH ≈ VDD , but the active load in (b) gives VOH = VDD − VTL

(60.13)

VTL = VT 0n + γ  2φ F + VOH − 2φ F 

(60.14)

with the theshold voltage computed from

This is referred to as a threshold voltage loss, and is due to the fact that the load must have a minimum gate-source voltage of VGSL = VTL to be biased into the active mode. Obviously, VOH < VDD for this circuit. The value of VOL > 0 is determined by a ratio of driver parameters to load parameters. In circuit (a), this ratio is given by RL βD , which is inversely proportional to VOL. This means a small VOL requires that both the load resistance and the driver dimensions are large. In circuits (b) and (c), VOL is set by the driver-to-load ratio βR = (βD /βL) = (W/L)D /(W/L)L; increasing βR decreases VOL. For the depletion MOSFET load circuit in (c), the design equation is given by

βR =

VTL

2

2 2(VDD − VTD )VOL − VOL

(60.15)

A condition of βR > 1 is generally required to achieve a functional inverter, implying that the driver MOSFET is always larger than the load device. Also, note that is not possible to achieve VOL = 0 because this requires an infinite driver-to-load ratio. The transient switching characteristics are obtained by including the output capacitance Cout as shown in Fig. 60.5 at the output. Cout consists of the input gate capacitance seen looking in the MOSFET of the next stage, and also has parasitic contributions from the MOSFETs and interconnects. By using a switch model for the driver, it is seen that the transient characteristics are determined by the time required to charge and discharge Cout. The high-to-low time tHL represents the time it takes to discharge the capacitor through the driver MOSFET with a device transconductance value of βD . A rough estimate is obtained using the RC time constant such that tHL ≈ 2RD Cout, with RD the equivalent resistance. Similarly, the lowto-high time tLH is the time interval needed to charge Cout through the load device. With respect to Fig. 60.8 circuit (c) has the best transient response such that tLH ≈ 2RL Cout , where RL represents the equivalent resistance of the load MOSFET. nMOS circuits in the mid-1980s had inverter transition times on the order of a few nanoseconds. Because the DC design requires that βR = (βD /βL) > 1, and the drainsource resistance of a MOSFET is inversely proportional to β, these circuits exhibit nonsymmetrical switching times with tLH > tHL. The propagation delay times can be estimated using tPHL ≈ RD Cout and tPLH ≈ RL Cout because these are measured relative to the 50% voltage levels. MOS-based logic design allows one to easily construct other logic functions using the inverter circuit as a guide. For example, adding another driver MOSFET in parallel gives the NOR operation, while adding a series connected driver yields the NAND operation; these are shown in Fig. 60.9. Complex logic gates for AOI (AND-OR-INVERT) and OAI (OR-AND-INVERT) canonical logic functions can be constructed using the simple rules • nMOSFETs (or groups) in parallel provide the NOR operation • nMOSFETs (or groups) in series provide the NAND operation Examples are provided in Fig. 60.10. It should be noted that this type of circuit structuring is possible because the drain and source are interchangeable. The main problem that arises in design complex nMOS logic gates is that the circuit requires large driver-to-load ratios to achieve small VOL values. The switching

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VDD

VDD ML

ML

A+B

AB A

A

MA

B MB

MA

B MB

(a)

(b)

FIGURE 60.9 nMOS NOR and NAND gates. (a) Two-input NOR gate; (b) two-input NAND gate.

VDD

VDD

ML

ML

AB + CD

A(B+C+D) A

A

C

B

D

B

(a)

C

D

(b)

FIGURE 60.10 nMOS AOI logic gates.

FET arrays collectively act like a driver network that must be designed to have a large overall effective β-value. Although parallel-connected MOSFETs are not a problem, the pull-down resistance of seriesconnected MOSFETs can be large unless the individual aspect ratios are increased. Satisfying this con­ dition requires additional chip area, decreasing the logic density.

CMOS Inverter A CMOS inverter is shown in Fig. 60.11. This circuit uses a pair of transistors, one nMOS and one pMOS, connected with their gates together. When Vin < VTn , the pFET is active and the nFET is in cutoff. Conversely, when Vin > (VDD –VTn), the nFET is active while the pFET is in cutoff. The two MOSFETs are said to form a complementary pair. The complementary arrangement of the MOSFETs gives the circuit a full rail-to-rail output range, i.e., VOL = 0 V and VOH = VDD . The devices are connected in such a way that terminal voltages satisfy VGSn + VSGp = VDD VDSn + VSDp = VDD

© 2003 by CRC Press LLC

(60.16)

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VSGp − βp

VDD

+

Mp + Mn

βn Vin = VGSn

VDD

+ VSDp −

Rp

+

+

Vin

Vout = VDSn

−

+

Rn Cout −

−

Vout −

(a)

(b)

FIGURE 60.11 CMOS inverter. (a) Circuit; (b) switch model.

Vout

nMOS OFF pMOS ON

VOH = VDD Unity Gain Line Vout = Vin Both nMOS

and

pMOS ON

VI nMOS ON pMOS OFF VOL = 0 0

VTn

VI

(VDD -|VTp|) VDD

Vin

FIGURE 60.12 CMOS VTC.

Note in particular the relationship between the gate-source voltages. Increasing the voltage on one transistor automatically decreases the voltage applied to the other. This provides the VTC with a very sharp transition, as shown in Fig. 60.12. Moreover, the shape of the VTC is almost insensitive to the power supply value VDD , which allows CMOS circuits based on this construction to be used with a range of values. The minimum value of VDD is set by the device the device threshold voltages, and is usually estimated as being about 3 VT . This is based on the input switching voltage Vin, and allows one VT to switch the nFET, one VT to switch the pFET, and one VT for separation. Currently, VT values equal ~0.5 V, so that the minimum VDD is about 1.5 V. Because VT is set in the fabrication, the minimum power supply used in low-voltage designs depends upon the process specifications. The maximum value of the power supply voltage is limited by the reverse breakdown voltages of the drain-bulk junctions. This is typically around 14 to 17 V. Because the structure of the CMOS circuit automatically gives a full-rail output logic swing, the DC design of the gate centers around setting the inverter threshold voltage VI . At this point, both FETs are saturated, and equating currents gives the expression

VI =

© 2003 by CRC Press LLC

(

βn β p VTn + VDD − VTp 1 + βn β p

)

(60.17)

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This equation shows that VI can be set by adjusting the ratio βn /βp . If βn = βp , and VTn ≈ VTp , then VI ≈ (VDD /2). Increasing this ratio decrease the inverter switching voltage. If the nFET and pFET are of equal size, then βn > βp (as k n′ > k p′ ), and V1 < (VDD /2). The transient characteristics are obtained by analyzing the charge and discharge current flow paths through the transistors. By using the switch model in Fig. 60.11(b), the primary time constants are τ n = RnCout =

Cout βn (VDD – VTn )

τ p = RpCout =

Cout

(

β p VDD – VTp

(60.18)

)

Analyzing the transitions with a step input voltage yields  2(V − V )  2(VDD − VTn )   0 t HL = τ n  Tn + ln −1  V0  (VDD − VTn )    t LH

(

) )

(

)

 2 V −V 2V −V  Tp DD Tp 0 = τ p  + ln −1  V0    VDD − VTp   

(

(60.19)

where V0 = 0.1 VDD is the 10% voltage. Noting once again that k n′ > k′p , equal size transistors will give tLH > tHL . To obtain symmetrical switching, the pMOSFET must have an aspect ratio of (W/L)p = (k n′ /k′p ) (W/L)n . This illustrates that while the ratio of β-values sets the DC switching voltage VI, the individual choices for βn and βp determine the transient switching times. In general, fast switching requires large transistors, illustrating the speed vs. area trade-off in CMOS design. The propagation delay time exhibits the same dependence. Another interesting characteristic of the CMOS inverter is the power dissipation. Consider an inverter with stable logic 0 or logic 1 inputs. Because one MOSFET is in cutoff, the DC power supply current IDD is very small, being restricted to leakage levels. The standby DC power dissipation is PDC = IDDVDD ≈ 0, so that static logic circuits do not dissipate much power under static conditions. Appreciable IDD from the power supply to ground flows only during a transition. Dynamic power dissipation, on the other hand, occurs due to the charging and discharging of the output capacitance Cout . The dynamic power dissipation can be estimated by 2 PDynamic = CoutVDD f

(60.20)

where f is the switching frequency of the signal. Qualitatively, this is understood by noting that this is just twice the average stored energy multiplied by the frequency. This illustrates the important result that the power dissipation of a CMOS circuit increases with the switching frequency.

Static CMOS Logic Gates Static logic gates are based on the inverter. The term “static” means that the output voltages (logic levels) are well defined as long as the inputs are stable. The nFET rules discussed for nMOS logic gates still apply to CMOS. However, static logic gates provide an nFET and a pFET for every input. Proper operation requires that rules be developed for the pMOSFET array as follows: • pMOSFETs (or groups) in parallel provide the NAND operation • pMOSFETs (or groups) in series provide the NOR operation

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VDD MpA

VDD

MpB

MpA AB MpB

MnB

B

A+B MnA

A

A

B

MnB

MnA (a)

(b)

FIGURE 60.13 CMOS (a) NAND and (b) NOR gates.

VDD

VDD

B

B

A





A C

B

A

A (B + C)

A⊕B 

A

A

C

B

A



B

(a)

B

(b)

FIGURE 60.14 CMOS AOI logic examples. (a) AOI gate; (b) XOR circuit.

When these rules are compared to the nMOS rules, it is seen that the nFET and pFET arrays are logical duals of one another (i.e., OR goes to AND, and vice versa). An N-input static CMOS logic gate requires 2N transistors. NAND and NOR gates are shown in Fig. 60.13 using the rules; this type of logic is termed series-parallel, for obvious reasons. Examples of complex logic gates are shown in Fig. 60.14. Note in particular the circuit in Fig. 60.14(b). This imple­ ments the XOR function by means of A ⊕ B = AB + AB = AB + AB

(60.21)

Reductions of this type are often performed to work the AOI or OAI equation into a more familiar form. As seen from these examples, the logic function is determined by the placement of the nFETs and pFETs in their respective arrays. Electrically, the design problem centers around choosing the aspect ratios to achieve acceptable switching times. Because a MOSFET has a parasitic drain-source resistance that varies as (1/β), series-connected transistor chains exhibit larger time constants than parallel-connected

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arrangements. Recalling that Rn < Rp shows that for equal size devices, series chains of nFETs are preferable to the same number of series-connected pFETs. Consequently, NAND gates are used more frequently than NOR gates, and AOI logic functions with a small number of OR operations are better. It is also possible to expand to transistor arrays that are not of the series-parallel type, such as a delta configuration, but it is difficult to devise general design guidelines for these circuits. Canonical CMOS static logic design is based on using pairs of nMOS and pMOS transistors. In modern very large scale integration (VLSI) design, the design complexity is limited by the interconnect (as opposed to the number of transistors), so that the need to connect every input to two transistors may result in problems in the chip layout. Pseudo-nMOS circuits provide an alternative to standard CMOS circuits. These logic gates implement logic using nFET arrays; however, the pMOS array is replaced by a single p-channel MOSFET that acts as a load device. Figure 60.15 shows an inverter and an AOI circuit imple­ ment based on pseudo-nMOS structuring. In both circuits, the load pMOSFET is biased active with VSGp = VDD by grounding the gate. Although the circuits are simplified, two main problems arise with this type of circuit. First, the output low voltage VOL is determined by the driver-to-load ratio (βn /βp ) > 1, so that large driver nFETs are required. Second, if the input voltage is high, then the circuit dissipates DC power. Despite these drawbacks, pseudo-nMOS circuits may be useful in certain situations. Transmission gates (TGs) provide another approach to implementing logic functions in CMOS. The properties of transmission gates are discussed in more detail in the next section. However, because they are useful for certain types of logic gates, a short discussion has been included here. A basic TG consists of an nMOSFET and a pMOSFET in parallel, as shown in Fig. 60.16(a); the symbol in (b) represents the VDD VDD βp

βp

Mp Load

A(B + C) + DE +

A

βn

Mn Driver

+ Vin

Mp Load



A

A

D

C

E

Vout − B

−

(b)

(a)

FIGURE 60.15 Pseudo-nMOS logic circuits. (a) Inverter; (b) AOI logic gate.



C



C



C

Rp Mp A

B

B

A

A

B

Mn Rn C C (a)

C (b)

FIGURE 60.16 Transmission Gate. (a) Circuit; (b) symbol; (c) switching model.

© 2003 by CRC Press LLC

(c)

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S D0  S

F

D1 S

FIGURE 60.17 TG-based 2:1 multiplexer.



B

B A

A 

B

A⊕B

B

A⊕B



B

B

(a)

(b)

FIGURE 60.18 TG-based (a) XOR and (b) XNOR logic gates.

composite structure. Transmission gates act like voltage-controlled switches: logically, a condition of C = 0 gives an open switch, while C = 1 gives a closed switch. Transmission gates can pass the full range of voltages (from 0 V to VDD) in either direction; this is not possible with a single device, due to the threshold voltage characteristic discussed earlier in this section. Figure 60.17 illustrates a simple 2: 1 multiplexer (MUX) with two input lines, D0 and D1, and a control bit S. When S = 0, the upper TG is closed, and the output is F = D0. Conversely, S = 1 closes the bottom TG, so F = D1. The operation of this circuit is expressed by F = SD0 + SD1

(60.22)

The circuit can be expanded easily to create larger multiplexers. For example, an 8: 1 requires three select bits, and each of the eight lines will be a switching network using three TGs. Several other TG-based logic functions are popular in CMOS design. Figure 60.18 shows the exclusive-OR (XOR) and exclusiveNOR (XNOR) circuits. The primary drawbacks of TG-based logic circuits are that (1) the TG does not have a connection to the power supply, and acts as a parasitic RC element to the stage that drives it, and (2) the chip layout may become large, complicated, or both. In particular, (1) implies that TG circuits may be slower than equivalent functions designed using basic static CMOS techniques.

Dynamic CMOS Logic Gates Dynamic CMOS logic gates are characterized as having outputs that are valid only for a limited time interval. Although this property inherently makes the circuit design more challenging, dynamic logic circuits can potentially achieve fast switching speeds. In general, dynamic circuits use parasitic capacitors in the MOS circuit to store charge Q. Because Q = CV, the presence or absence of charge corresponds to a logic 1 or logic 0 level, respectively, MOSFETs are used as voltage-controlled switches to “steer” the

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VDD MP

A

MA

Cout

+ Vout − φ

B

MB

C

MC

C1

C2

Precharge

Evaluate

Precharge t

φ

MN

C3

(a)

(b)

FIGURE 60.19 Dynamic CMOS logic gate. (a) Three-input NAND gate; (b) timing intervals.

charge on and off the logic nodes. Several dynamic logic families have appeared in the literature, each having distinct characteristics. We now merely touch on some characteristics of a basic circuit which illustrates the important points. Consider the dynamic logic circuit in Fig. 60.19 for a three-input NAND gate. The transistors labeled MP and MN are controlled by the clock φ(t), and provide synchronization of the data flow. Note the presence of capacitors Cout, C1, C2, and C3. These represent parasitic capacitances due to the transistors and interconnect, and are crucial to the operation. The circuit is controlled by the timing provided by φ(t). When φ = 0, MP is ON and MN is OFF. During this time, Cout is charged to a voltage Vout = VDD , which is called a precharge event. When φ changes to a level φ = 1, MP is driven into cutoff, but MN is biased ON; the operation of the circuit during this time is termed a conditional discharge event. If the inputs are set to (A, B, C) = (1, 1, 1), then all three logic transistors, MA, MB, and MC, are ON, and Cout can discharge through these transistors and MN to a final voltage of Vout = 0 V. If at least one input is a logic 0, then Cout does not have a direct discharge path to ground. Ideally, Vout would stay at VDD . However, charge leakage occurs across the reverse-biased drain-bulk pn junctions in the MOSFETs, eventually leading to a value of Vout 0 V. Typically, the output voltage can be held only for a few milliseconds, thus leading to the name “dynamic circuit”. Another problem that arises in dynamic logic circuits is that of charge sharing. Consider the threeinput NAND gate with inputs of (A, B, C) = (0, X, X) during the precharge, where X is a do not care condition. The total charge transferred to the circuit from the power supply is QT = CoutVDD

(60.23)

Now suppose that the inputs are switched to (A, B, C) = (1, 1, 0) during the evaluation phase. MOSFETs MA and MB are ON, but MC is OFF, blocking the discharge path. Charge sharing occurs because the charge originally stored on Cout is now shared with C1 and C2. After the transients have decayed, the three capacitors are in parallel, Ignoring any threshold drop, they will share the same final voltage Vf such that QT = (Cout + C1 + C 2 )V f

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(60.24)

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Equating the two expressions for charge gives Vf =

Cout V < VDD C out + C1 + C 2 DD



(60.25)

To ensure that the output voltage remains at a logic 1 high voltage, the capacitors must satisfy the relation Cout  C1 + C 2

(60.26)

The capacitance values are proportional to the sizes of the contributing regions, so that the performance is closely tied to the layout of the chip.

References The material in this section is quite general. The references listed below are books in the field of digital MOS integrated circuits that provide further reading on the topics discussed here. [1] L. A. Glasser and D. W. Dobberpuhl, The Design and Analysis of VLSI Circuits, Reading, MA: Addison-Wesley, 1985. [2] H. Haznedar, Digital Microelectronics, Reading, MA: Addison-Wesley, 1991. [3] J. P. Uyemura, Circuit Design for CMOS VLSI, Norwell, MA: Kluwer Academic, 1992. [4] J. P. Uyemura, Fundamentals of MOS Digital Integrated Circuits, Reading MA: Addison-Wesley, 1988.

60.2 Transmission Gates Robert C. Chang and Bing J. Sheu A signal propagates through a transmission gate (TG) in a unique manner. In conventional logic gates, the input signal is applied to the gate terminal of an MOS transistor and the output signal is produced at the drain or the source terminal. In a TG, the input signal propagates between the source and the drain terminals through the transistor channel, while the gate voltage is held at a constant value. The TG is turned off if the voltage applied to the gate terminal is below the threshold voltage. The TG approach can be used in digital data processing to implement special switching functions with high performance as well as a small transistor count [1]. It also can be used in analog signal processing to act as a compact voltage-controlled resistor.

Digital Processing Single Transistor Version A TG can be constructed by a single nMOS or pMOS transistor, as shown in Fig. 60.20. For an nMOS TG to pass a signal Vin to the output terminal, the selection signal S is set to the logic 1 value, i.e., the gate voltage VG is set to a high voltage value VDD . If the input signal is also the VDD value, the output voltage Vout is determined by [2],  t τ  nc Vout (t ) = (VDD − Vthn )  1 + (t τ nc ) 

(60.27)

where Vthn is the threshold voltage of the nMOS transistor with the body effect and τnc is the charging time constant which can be expressed as

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S

VDD

Vin

Vout

Vin

Vout

Cload

Cload S (a)

(b)

FIGURE 60.20 (a) nMOS TG; (b) pMOS TG.

τ nc =

2Cout µ nCOX ( W L )(VDD − Vthn )

(60.28)

Here, µ n is the carrier mobility, COX is the per-unit-area capacitance value, and W/L is the transistor aspect ratio. If time t goes to ∞, then Vout will approach VDD – Vthn , which indicates that a threshold voltage loss occurs in the signal from the input node to the output node. This is due to the fact that VGS must be greater than the threshold voltage to turn on the nMOS transistor. Owing to this voltage reduction, an nMOS TG can only transmit a “weak” logic 1 value. However, a logic 0 can be transmitted by an nMOS TG without penalty. In order to analyze this case, we set Vin = 0 and Vout (t = 0) = VDD – Vthn . The output voltage Vout is determined by  2e − (t τnd )  Vout (t ) = (VDD − Vthn )  − (t τ ) 1 + e nd 

(60.29)

where the discharge time constant can be expressed as τ nd =

Cout µ nCOX ( W L )(VDD − Vthn )

(60.30)

Notice that Vout will approach zero as time goes to infinity. Input-output (I-O) characteristics of an nMOS transmission gate are shown in Fig. 60.21. The schematic diagram of a pMOS TG is shown in Fig. 60.20(b). For a pMOS transmission gate to pass a signal Vin to the output terminal, the selection signal S is set to the logic 0 value. To transmit a logic 0 value with the initial Vout value being VDD, the expression for Vout is given as Vout (t ) = Vthp +

(

VDD − Vthp

)(

1 + VDD − Vthp t / 2τ pd

)

(60.31)

where τpd is the discharging time constant for the pMOS TG. As time goes to infinity, Vout will approach Vthp , so that the pMOS TG can only transmit a “weak” logic 0 value. On the other hand, the pMOS

VDD

|Vthp| 0

© 2003 by CRC Press LLC

Vout Vin

t

FIGURE 60.21 Characteristics of nMOS TG.

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S

Vin

Vout Cload VDD

− S

FIGURE 60.22 Characteristics of pMOS TG.

transmission gate can perfectly transmit a logic 1 value. To analyze this case, we set Vin = VDD and assume the initial Vout Value as Vthp . The expression for Vout is given as  2e − (t τ pc )  Vout (t ) = VDD − VDD − Vthp    1 + e − (t τ pc )   

(

)

(60.32)

where τpc is the charging time constant for the pMOS TG. The output voltage will approach VDD as time goes to ∞. The transfer characteristics of the pMOS transmission gate is shown in Fig. 60.22. Complementary Transistor Version Figure 60.23 is the schematic diagram of a complementary transistor version of the TG which can be constructed by combining the characteristics of nMOS and pMOS TGs. The CMOS TG can transmit both the logic 0 and logic 1 values without any degradation. The voltage transmission properties of the single transistor and CMOS TGs are summarized in Table 60.1. The overall behavior of the CMOS TG can be described as follows. When the selection signal S is low, both the nMOS and pMOS transistors are cut off. The output voltage Vout will remain at a high impedance state. When the selection signal S is high, both the nMOS and pMOS transistors are turned on and the output voltage will be equal to the input voltage. Three regions of operation exist for a CMOS TG. In region 1 Vin < Vthp , then nMOS transistor is in the triode region and the pMOS transistor is in the cutoff region. Because the pMOS transistor is turned off, the total current, Itot , is supplied by the nMOS transistor and Itot decreases as Vin increases. In region 2Vthp  < Vin < VDD – Vthn both the nMOS and pMOS transistors are in the triode region. In this region, the nMOS transistor current decreases and the pMOS transistor current increases as Vin increases. Thus, Itot is approximately a constant value. In region 3 Vin >VDD –Vthn the nMOS transistor is turned off and the pMOS transistor is in the triode region. The plot of the TG on-resistance is shown in Fig. 60.24.

S

Vin

Vout Cload VDD

− S

© 2003 by CRC Press LLC

FIGURE 60.23 CMOS TG.

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TABLE 60.1 Transmission

Gate Characteristics

on-resistance

RP

Vout Vin Type

Vin = 0 (logic 0)

Vin = VDD

(logic 1)

nMOS pMOS CMOS

0 Vthp 0

VDD – Vthn VDD VDD

RN

Mp cutoff

MN cutoff

RTG Vthp C1

C2

VDD - Vthn

Vin

FIGURE 60.24 TG resistances.

Cn

P1

P2

Product term

Pn

FIGURE 60.25 Model for pass transistor logic.

Pass-Transistor Logic Pass-transistor logic is a family of logic which is composed of TG. Methods for deriving pass-transistor logic using nMOS TGs have been reported [3]. Figure 60.25 shows the schematic diagram of the passtransistor logic in which a set of pass signals, P i′s, are applied to the sources of the nMOS transistors and another set of control signals, C i′s, are applied to the gates of the nMOS transistors. The desired logic function F can be expressed as F = C1 · P1 + C2 · P2 + … + Cn · Pn . When C i′s are high, P i′s are transmitted to the output node. P i′s can be logic 0, logic 1, true, or complement of the ith input variable Xi , or the high-impedance state Z. Constructing a Karnaugh map can help one to design the pass-transistor circuit. The pass function rather than the desired output values is put to the corre­ sponding locations in the Karnaugh map. Then any variables that may act as a control variable or a pass variable are grouped. For example, consider the design of a two-input XOR function. The truth table and the modified Karnaugh map of the XOR function are given in Tables 60.2 and 60.3, respectively. By grouping the A – column when B is 0, and the A column when B is 1, the function can be expressed as F = B ⋅A + B⋅A where the B is a control variable and A is a pass variable. © 2003 by CRC Press LLC

(60.33)

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TABLE 60.2 Truth Table of XOR Function

TABLE 60.3

A

B

A_B

Pass Function

0 0 1 1

0 1 0 1

0 1 1 0

A+B – A +B – A+ B – – A +B

Modified Karnaugh Map for XOF Function B 1

0 

A

A

0

B A

A

A

1

B 





B

B



B

VDD

B A

A A⊕B



B

A⊕B

B



A

A



A A⊕B

B (a)

B (b)

(c)

FIGURE 60.26 XOR gates. (a) nMOS version. (b) Complementary version I. (c) Complementary version II.

Figure 60.26(a) and (b) show the schematic diagrams of nMOS and CMOS implementations of the XOR function. When the control variable B is with a logic 0 value, the pass variable A is transmitted to – the output. When the control variable B is with a logic 1 value, the pass variable A is transmitted to the output. Another implementation of the XOR function is shown in Fig. 60.26 (c). It is not permitted to have groupings that transmit both true and false values of the input variable to the output simultaneously. The final expression must contain all the cells in the Karnaugh map. Note that the p-transistor circuit is the dual of the n-transistor circuit. Thus, the p-pass function must be constructed when a complementary version is required. In addition, the pass variable with logic 0 value is transmitted by the nMOS network in a complementary implementation while the pass variable with logic 1 value is transmitted by the pMOS network. The OR function can be constructed by one pMOS transistor and one CMOS TG, as shown in Fig. 60.27. When the input signal A is with the logic 0 value, the CMOS TG is turned on and the input signal B is passed to the output node. On the other hand, if the input signal A is with the logic 1 value, the pMOS TG is turned on and the logic 1 value of input signal A is transmitted to the output node. Because the pMOS TG can propagate a “strong” logic 1 value it is not necessary to use another CMOS TG. © 2003 by CRC Press LLC

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

A

B

A+B

A

FIGURE 60.27 OR gates.

S

X 

S

F

Y

S

FIGURE 60.28 A two-input multiplexer.

CLK M1 Da



Q

M2

CLK M3 M4 Q

FIGURE 60.29 A CMOS D latch.

Transmission gates can be used to construct a multiplexer which selects and transmits one of the inputs to the output. Figure 60.28 is the circuit schematic diagram of a two-input multiplexer, which is composed of CMOS TGs. The output function of the two-input multiplexer is F = X ⋅S +Y ⋅S

(60.34)

If the selection signal S is at a logic 1 value, the input signal X is transmitted to the output. On the other hand, if the selection signal S is at a logic 0 value, the input signal Y is transmitted to the output. Multiplexers are important components in CMOS data manipulation structures and memory elements. A basic D latch can be constructed by two TGs and two invertes, as shown in Fig. 60.29. When the CLK signal is at a logic 0 value, pass transistors M1 and M2 are turned off so that the input signal Da cannot be transmitted to the outputs Q and Q . In addition, pass transistors M3 and M4 are turned on so that a feedback path around the inverter pair is established and the current state of Q is stored. When the CLK signal is at a logic 1 value, M1 and M2 are turned on and M3 and M4 are turned off. Thus, the output signal Q is set to the input signal Da and Q is set to Da . Because the output signal Q will follow the change of input signal Da when the CLK signal is high, this circuit is a positive level-sensitive D latch. A positive edge-trigger register or so-called D flip-flop can be designed by combining one positive levelsensitive D latch and one negative level-sensitive D latch. By cascading D flip-flops, a shift register can be constructed. © 2003 by CRC Press LLC

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M1 M1

M2 M2

M3 C1 Read

word

Write

bit

bit

data_R

data_W

(a)

(b)

FIGURE 60.30 (a) SRAM cell; (b) DRAM cell.

C

VDD VDD

SUM

VDD

B

VDD VDD

CARRY A

FIGURE 60.31 TG adder.

Transmission gates can be used in the design of memory circuits. A typical random access memory (RAM) architecture consists of one row/word decoder, one column/bit decoder, and memory cells. The memory cells used in RAMs can be categorized into static cells and dynamic cells. Memory data/charges are stored on the latches in static cells, while on the capacitors in dynamic cells. The static random access memories (SRAMs) are not forced to include the refresh circuitry and are faster than the dynamic random access memories (DRAMs). However, the size of SRAM cells is much larger than that of DRAM cells. The most commonly used circuit in the design of SRAM cells is the six-transistor circuit shown in Fig. 60.30. Four transistors are used to form two cross-coupled inverters. The other two transistors, M1 and M2, are TGs to control the read/write operation of the memory cell. If the word line is not selected, the data stored on the latch will not change as long as the leakage current is small. If the word line is selected, the transistors M1 and M2 are turned on. Through the bit and bit lines, data can be written into the latch or the stored data can be read out by the sense amplifier. Transmission gates can also be found in the four-transistor DRAM cell circuit, as shown in Fig. 60.30(b). When the Read line is selected, pass transistor M1 is turned on and the data stored on the capacitor C1 are read out. When the Write line is selected, pass transistor M2 is turned on and the data from data_W line are written into the cell. Figure 60.31 is the circuit schematic diagram of a TG adder, which consists of four transmission gates, four inverters, and two XOR gates [4]. The SUM output, which represents A  B  C, is constructed by a multiplexer controlled by A  B and its complement. Notice that when A  B is false, the CARRY output equals A or B. Otherwise, CARRY output takes the value of input signal. C. Although the TG adder has the same number of transistors as the combinational adder, it has the advantage of having © 2003 by CRC Press LLC

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Complementary pass signal 

Complementary control signal

P1

P1



P2

P2

 Pn

Pn

C1  C1 C2 

C2

Cn

NMOS pass-transistor logic network



Cn

CMOS output inverters

FIGURE 60.32 Schematic structure of the basic CPL circuit.

noninverted SUM and CARRY output signals and an equal delay time for the SUM and CARRY output signals. Another form of differential CMOS logic, complementary pass-transistor logic (CPL), has been devel­ oped and utilized on the critical path to achieve very high speed operation [5]. Figure 60.32 is the circuit schematic diagram of the basic CPL structure using an nMOS pass-transistor logic organization. The CPL is constructed by an nMOS pass-transistor logic network, complementary inputs and outputs, and CMOS output inverters. As the nMOS pass transistor will transmit a logic 1 signal with one threshold voltage reduction, the output signals must be amplified by the CMOS inverters which can shift the logic threshold voltage and drive a large capacitive load. One attractive feature of the CPL design is that complementary outputs are generated by the simple four-transistor circuits. Because inverters are not required in CPL circuits, the number of critical-path gate stages can be reduced. Figure 60.33 shows the schematic diagrams of four basic CPL circuit modules: an AND/NAND module, an OR/NOR module, an XOR/XNOR module, and a wired-AND/NAND module [5,6]. By combining these four circuit modules, arbitrary Boolean functions can be constructed. These modules have an identical circuit schematic and are distinguished by different arrangements of input signals. This property of CPL is quite suitable for master-slice design.

A B





B A

A



B

(a)





B A

A





B

B

B

B

B

B

(b)

(c)



A



A A

A

B



B



A

C 

C

(d)

FIGURE 60.33 CPL circuit modules. (a) AND/NAND; (b) OR/NOR; (c) XOR/XNOR; (d) Wire-AND/NAND.

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



B

B



A

C

C



A

A



A

B



A

B

C

A





C

A

SUM

SUM

CARRY

CARRY

FIGURE 60.34 CPL full adder circuit.

B Register

A Register 16

16

Partial Product Generator 256 × 2 Wallace-Tree Adder Array 32 × 2 × 2 Carry Lookahead Adder 32

FIGURE 60.35 Block diagram of the 16 × 16 bit multiplier.

The schematic diagram of a CPL full adder is shown in Fig. 60.34. Both the circuitry to produce the SUM output signal and the circuitry to produce the CARRY output signal are constructed from basic CPL modules. The SUM circuitry consists of two XOR/XNOR modules, while the CARRY circuitry consists of three wired-AND/NAND modules. The CMOS output inverters are fixed “overhead” because they are required whether the circuit has one, two, or many inputs. Thus, designing with a complex Boolean function in a CPL gate is preferred to minimize the delay time and overall device count. Figure 60.35 is the block diagram of a 16 × 16 bit multiplier, which is constructed by using a parallel multiplication architecture. A carry-look-ahead (CLA) adder and a Wallace-tree adder array are used to minimize the critical-path gate stages. The number of transistors in the CPL multiplier is less than that in a full CMOS counterpart [7]. Due to the continued device miniaturization and the recent drive of portable systems, VLSI systems have been pushing toward low-voltage, low-power operation. Various techniques from system level to device level were developed to reduce the operating voltage and the power consumption of the VLSI circuits [8, 9]. The low-power design can be addressed at four levels: algorithm, architecture, logic style, and integration. At the logic design level, capacitive loads are to be reduced and the number of charg­ ing/discharging operations are to be minimized. A CPL is one of the most attractive logic families that can achieve very low power consumption. The input capacitance in CPL is about half that of the CMOS © 2003 by CRC Press LLC

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configuration because pMOS can be eliminated in logic organization. Therefore, CPL can achieve a higher speed and dissipate less power. Experimental results [5] show that for the same delay time of the CMOS full adder operating at 5 V, the CPL adder requires only a 2-V supply. As the supply voltage decreases, the delay time will increase, but the power-delay product will decrease. Hence, it is desirable to operate at the slowest allowable speed to reduce power dissipation. Experimental results indicate that performance of CPL logic style is better than the conventional CMOS logic style from the viewpoint of power consumption.

Analog Processing MOS Operational Amplifier Compensation The frequency stabilization of a basic two-stage CMOS amplifier can be achieved by using a pole-splitting capacitor CC [10]. The pole p1 due to the capacitive loading of the first stage is pushed down to a very low frequency, and the pole p2 due to the capacitance at the output node of the second stage is pushed to a very high frequency. However, a right-half-plane zero is introduced by the feedthrough effect of the compensation capacitor CC. It will degrade the stability of the op amp and make the second stage behavior like a short-circuited configuration at high frequencies. In order to remove the effects of the zero, a source follower can be inserted in the path from the output back through the compensation capacitor. Another approach is to insert a nulling resistance, RZ, in series with the compensation capacitor. If RZ is set to 1/gm2, where gm2 is the transconductance of the second stage, the zero vanishes and the feedthrough effect is cancelled out. A single transistor or complementary version of the TG can be used to implement RZ . Figure 60.36 is the schematic diagram of a basic two-stage op amp supplemented by a feedback branch (M8, CC) for compensation [11]. Capacitance CL is the load capacitance to be driven by the amplifier. The pMOS TG M8 is biased in the triode region and provides the equivalent resistance. Transmission gates can be used to construct the cascode configuration of an op amp. A fully differential folded-cascode op amp is shown in Fig. 60.37 [11]. The output cascode stage consists of TGs M5 to M10. A high output impedance can be achieved by using the split-load arrangement. The bias voltage Vbias1 establishes the bias current I of the input stage, and a bias current I0 in the output transistors M7 to M12. Thus, each transistor of M3 to M6 has a stabilized current I0 + I/2. The source voltages of M5 and M6 are stabilized because they conduct stabilized currents and their gate voltages are fixed at Vbias2. This fixes vDS 3 and vDS 4. Let transistors M3 and M4 have the same W/L ratio and bias them in the triode region by choosing a suitable value for Vbias2. If the ouput common-mode voltage v0, c drops, the resistance VDD M3

M4 M6 M8 Vout

Vin−

M1

Vbias

M2

CC

Vin+

M5 M7

VSS

FIGURE 60.36 CMOS op amp.

© 2003 by CRC Press LLC

CL

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VDD M3

M4

Io + I/2 Vbias2

I/2 Vin−

I/2 M1

M2

Io + I/2

M5

M6

M7 Vbias3

M8

Vin+ Vout+

Vout− Io

I Vbias1

Io

Vbias4 M9

M10

M11

M12

M5

VSS

FIGURE 60.37 A fully differential CMOS op amp with stabilized DC output level.

of M3 and M4 reduces, which increases vGS 5 and vGS 6. Because the current in M5 and M6 remains unchanged, vDS 5 and vDS 6 are forced to decrease. Then, the drain voltages of M5 and M6 increase, which increases vGS 7 and vGS 8. Therefore, vDS 7 and vDS 8 reduce which forces v0+ and v0– to rise. The commonmode voltage v0, c is thus increased. This approach can increase the common-mode rejection ratio (CMRR) of the op amp. The negative feedback scheme tends to keep v0, c at a constant value. It means that the small-signal common-mode output is zero or a very small value. Thus, a high CMRR is achieved. Transimpedance Compensation The optical receiver is an important component of the optical fiber communication system. One of the basic modules in a high performance optical receiver is the low-noise preamplifier. Several approaches are available to design the preamplifier. One approach is to use the transimpedance design which can avoid the equalization and limited dynamic range problems by using negative feedback. Transmission gates can be used to provide the feedback resistance for a transimpedance amplifier. A complete preamplifier circuit schematic is given in Fig. 60.38 [12]. This circuit consists of three gain stages and two TGs. Each gain stage is composed of a pMOS current source achieving a common-source amplification with a folded nMOS load. One TG transistor, M10, functions as a feedback resistor and the other, M11, functions to implement the automatic gain control function. The gate voltage of M10 is derived from another circuit which minimizes the temperature and power supply dependence of the feedback resistance [12]. Transistor M11 is controlled by the automatic gain control voltage [13] and is normally off. If the input current to the preamplifier forces the output voltage out of its linear range, M11 is turned on and begins to shunt current away from the feedback resistor and into the first stage output node. With recent progress in intelligent information processing, artificial neural networks can be used to perform several complex functions in scientific and engineering applications, including classification, pattern recognition, noise removal, optimization, and adaptive control [14]. Design and implementation of VLSI neural networks have become a very important engineering task. The basic structure of an artificial neural network consists of a matrix of synapse cells interconnecting an array of input neurons with an array of output neurons. The inputs, Vi, are multiplied by weight values, Ti , of the synapses. The results of the multiplication are summed and compared to the threshold value θi in the output neurons. Schematic diagrams of a mathematical model of a neuron and its electronic counterpart are shown in © 2003 by CRC Press LLC

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VDD

M3

M12

M6 M9

VOUT M11

VAGC

VBIAS

M4 M5

M1 M2

IIN

M7 M8

M13 GND M10 VFRC

FIGURE 60.38 Circuit schematic of a preamplifier.

T1 V1 T2 V2 f,θ

n V0 = f (∑ TiVi − θ) i=1

Tn Vn (a) VGC RFB

V1 V2

T1 T2

n V0 = A(R∑ TiVi − Vθ) + i=1 A −

− +

Vθ Vn

Tn (b)

FIGURE 60.39 Neuron and synapse operation. (a) Mathematical model. (b) Analog circuit model with adjustable gain.

Fig. 60.39. The circuit in Fig. 60.39(b) uses a gain-controllable amplifier in which the voltage gain is controlled by changing the feedback resistance. The feedback resistor RFB can be constructed by the TG structure so that feedback resistance can be adjusted by the gain-control voltage VGC [15]. Continuous-Time Filters Resistors are important components in the construction of continuous time filters [16]. However, the implementation of resistors by integrator circuit (IC) fabrication technologies was found to be lacking © 2003 by CRC Press LLC

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Digital Circuits

VC1 I1

VC2

Io1

M1

VI1

Vo

VSS I2

M2

I3

M3

VSS

VI2

I4

Vo Io2

M4 VC1

FIGURE 60.40 Double-MOS implementation of a differential AC resistor.

in several areas of performance. The TG can be used to realize active resistance. For example, a doubleMOS differential configuration, shown in Fig. 60.40, is used to implement a differential AC resistor [17]. This circuit consists of four nMOS transmission gates. Not only can it linearize the AC resistor, but it can also eliminate the effects of the bulk-source voltage [18]. To determine the AC resistance, assume that all the transistors are matched and are biased in the triode region. The current I01 and I02 can be expressed as I 01 = I1 + I 3

[

= µ n COX (W / L) (VC1 − V0 − Vthn )(VI1 − V0 ) − (1 / 2) (VI1 − V0 )

[

2

]

+ µ n COX (W / L) (VC 2 − V0 − Vthn )(VI 2 − V0 ) − (1 / 2) (VI 2 − V0 )

(60.35) 2

]

I 02 = I 2 + I 4

[

= µ nCOX ( W L ) (VC 2 − V0 − Vthn ) (VI1 − V0 ) − (1 / 2) (VI1 − V0 )

[

2

]

+ µ nCOX ( W L ) (VC1 − V0 − Vthn )(VI 2 − V0 ) − (1 / 2) (VI 2 − V0 )

(60.36) 2

]

Equation (60.35) and (60.36) can be combined to determine the differential current

[

]

I 01 − I 02 = µ nCOX (W / L) (VC1 − VC 2 )(VI1 − VI 2 )

(60.37)

Thus, rac is given by rac =

VI1 − VI 2 1 = I 01 − I 02 µ nCOX ( W L ) (VC1 − VC 2 )

(60.38)

Because all transistors are required to be biased in the triode region, (60.38) holds when

[

VI1 , VI 2 ≤ min VC1 − Vthn ,VC 2 − Vthn

]

(60.39)

The double-MOSFET differential resistor is really a transresistance, thus, it can be applied only to differential-in, differential-out op amps. © 2003 by CRC Press LLC

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reset

φ1

CI

φ2

φ1 −

Vin CS

+

Req

FIGURE 60.41 Direct digital integrator.

Switched-Capacitor Circuits Switched-capacitor circuits make use of TGs in processing the analog signals [11, 17, 19]. This approach uses switches and capacitors and is in discrete time. If the clock rate is much higher than the signal frequency, an AC resistor can be implemented by combining switches and capacitors. The equivalent resistance is dependent only on the clock rate and the capacitor. The circuit schematic diagram of the direct digital integrator (DDI) is shown in Fig. 60.41. The resistance is realized by two MOS switches and one capacitor. The difference equation can be expressed as v 0,n+1 = v 0,n −

Cs v C I in

(60.40)

After taking the z-transform, the new expression becomes z ⋅ V0 ( z ) = V0 ( z ) –

Cs V (z ) C I in

(60.41)

By rearranging the various terms, the transfer function of the DDI integrator can be expressed as V0 ( z ) C z −1 =− s ⋅ Vin ( z ) C I 1 − z −1

(60.42)

By setting z = e jωT, the frequency response can be determined: V0 C 1 ωT 2 jω ) = − s ⋅ ⋅e − jωT ( Vin C I jωT sin(ωT 2)

2

(60.43)

where T is the period of the clock. In (60.43), the first term corresponds to an ideal integrator, the second term contributes to the magnitude error, and the third term is the phase error. Because the frequency response of the ideal integrator is –[ jωReq CI ]–1, the equivalent resistance value is determined by Req =

T Cs

(60.44)

A ladder network can be constructed by cascading the DDI integrators. In the ladder network all cascaded stages sample the input signal at clock Φ1 and transform the signal at clock Φ2, where Φ1 and Φ2 are nonoverlapping clock signals. This clocking scheme induces the extra half-cycle phase delay. This phase

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φ1

CI

φ2

φ2 − +

CS

Vin+ Vin−

FIGURE 60.42 Bottom-plate differential-input lossless digital integrator. φ1

φ2 CS

CI

Vin+ φ2

φ1

φ2

−

+

+

−

φ1

φ2

φ2

Vo+ Vo−

φ2

Vin− CI

CS φ1

φ2

FIGURE 60.43 Differential bilinear integrator.

error can cause extra peaking in frequency response and generate cyclic response. In order to remove the excess phase, other integrators, such as lossless digital integrators (LDI) or bilinear integrators, can be used. In an LDI ladder network, the odd-number stages sample the input signal at clock Φ1 and transform the signal at clock Φ2, while the even-number stages sample the input signal at clock Φ2 and transform the signal at clock Φ1. Thus, the frequency response of an LDI integrator can be expressed by V0 C 1 ωT 2 jω ) = − S ⋅ ( Vin C I jωT sin(ωT 2)

(60.45)

Figure 60.42 is the circuit schematic diagram of the bottom-plate differential-input LDI. Output of an LDI integrator is more insensitive to parasitic components. Figure 60.43 is the circuit schematic diagram of a differential bilinear integrator. The transfer function of the bilinear integrator is V0+ − V0− CS 1 + z −1 = ⋅ Vin+ − Vin− C I 1 − z −1

(60.46)

As the output of the bilinear integrator does not change during clock Φ1, it can be used to feed another identical integrator. © 2003 by CRC Press LLC

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VH VL RS

Α

Β

id

VS CS

CL

FIGURE 60.44 Circuit for analysis of switch charge injection.

Transmission gates can be used to initialize the switched-capacitor circuits. For example, capacitor CI in Fig. 60.41 is to perform the integration function and to be reset or discharged before operation. An nMOS TG can be put in parallel with the capacitor CI. Before normal operation, the TG is turned on and the capacitor CI is discharged so that the initial capacitor voltage value is reset to zero. The accuracy of switched-capacitor circuits is disturbed by charge injection when the controlling switch turns off [20]. The turn-off of an MOS switch consists of two phases. The gate voltage is higher than the transistor threshold voltage Vth during the first phase. A conduction channel extends from the source to the drain of the transistor. As the gate voltage decreases, mobile carriers exit through both the drain and the source terminals and the channel conduction decreases. During the second phase, the gate voltage is smaller than Vth and the conduction channel no longer exists. The coupling between the gate and the data-holding node is only through the gate-to-diffusion overlap capacitance. The following analysis is focused on the switch charge injection due to the first phase of the switch turn-off. Figure 60.44 is the circuit schematic corresponding to the general case of switch charge injection. Capacitance CL is the lumped capacitance at the data-holding node. Capacitance CS could be the lumped capacitance associated with the amplifier output node, while resistance RS could be the output resistance of an op amp. Let CG represent the total gate capacitance of the switch, including both the channel capacitance and gate-to-drain/gate-to-source overlap capacitances. Kirchhoff ’s current law at node A and node B requires CL

dv L C d(VG − v L ) = − id + G 2 dt dt

(60.47)

and vS dv C d(VG − v s ) + CS S = id + G RS dt 2 dt

(60.48)

where vL and vS are the error voltages at the data-holding node and the signal-source node, respectively. Gate voltage is assumed to decrease linearly with time from the turn-on value VH : VG = VH − αt

(60.49)

where α is the falling rate. When the transistor is biased in the strong inversion region, id = β (VHT − α ⋅t )(v L − v S )

(60.50)

where β = µ COX

W L

(60.51)

and VHT = VH − VS − Vthn

© 2003 by CRC Press LLC

(60.52)

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VH

VH VL

VH VL

VL RS

RS CL VS

VS

∞

VS CS

(a)

CL

(b)

CS

CL

(c)

FIGURE 60.45 Special cases of switch charge injection. (a) No source resistance and capacitance. (b) No source capacitance. (c) Infinitely large source resistance.

Here, Vthn is the transistor effective threshold voltage, including the body effect. For small-geometry transistors, narrow- and short-channel effects should be considered in determining the Vthn value. Under the condition dVG /dt  dVL /dt and dVS /dt, and (60.47) and (60.48) can be simplified to CL

dv L C = −β(VHT − αt )(v L − v S ) − G α dt 2

(60.53)

and vS dv C + CS S = β(VHT − αt )(v L − v S ) + G α RS dt 2

(60.54)

No closed-form solution to this set of equations can be found. Numerical integration can be employed to find final results. Analytical solutions to special cases are given next. Figure 60.45(a) is the circuit schematic diagram of the case, with only a voltage sourced at the signalsource node. Because CS  CL ,vs can be approximated as zero and the governing equation reduces to CL

dv L C = −β(VHT − αt )v L − G α dt 2

(60.55)

When the gate voltage reaches the threshold condition, the error voltage at the data-holding node is vL = −

 παC L  CG   β erf  VHT    2β  2C L   2αC L 

(60.56)

Notice that the value of the error function erf(·) can be found from mathematical tables. Another special case is when the source capacitance is negligibly small, as is shown in Fig. 60.45(b). The governing equations reduce to CL

dv L C = −β (VHT − αt )(v L − v s ) − G α dt 2

(60.57)

vs C = β(VHT − αt )(v L − v S ) + G α Rs 2

(60.58)

and

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When the gate voltage reaches the threshold condition, the error voltage at the data-holding node is

vL = −

 V  αCG exp − HT  ⋅ αC 2C L R  L S

 θ  ⋅exp   C L RS 

∫ [βR (V VHT /α

0

S

HT

1/C LβRs2α

) ]

− αθ + 1

(60.59)

  1  2 − 1 + β R V − αθ  dθ )  S ( HT

If a time constant RS CS is much larger than the switch turn-off time, then the channel charge will be shared between CS and CL, as shown in Fig. 60.45(c). For the case of a symmetrical transistor and CS = CL, half of the channel charge will be deposited to each capacitor. Otherwise the following equations can be used to find the results: CL

dv L C = −β(VHT − αt )(v L − v s ) − G α dt 2

(60.60)

dv S C = β(VHT − αt )(v L − v s ) + G α dt 2

(60.61)

and CS

We can multiply (60.61) by the ratio CL /CS and then subtract the result from (60.60) to obtain C L

d(v L − v S ) dt

 C  αCG  C L  1− = −β(VHT − αt )1 + L  (v L − v S ) − 2  CS   CS 

(60.62)

When the gate voltage reaches the threshold condition, the amount of voltage difference between the data-holding node and the signal-source node becomes

v L − v s = −

 CG (1 − C L / CS )  παC L  2β(1+C L / CS )  2C L 

  β(1+C / C ) L S ⋅ erf  VHT    2αC L  

(60.63)

References [1] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, 2nd ed. Reading, MA: AddisonWesley, 1993. [2] J. P. Uyemura, Fundamentals of MOS Digital Integrated Circuits, Reading, MA: Addison-Wesley, 1988. [3] D. Radhakrishnan, S.R. Whitaker, and G. K. Maki, “Formal design procedures for pass transistor switching circuits,” IEEE J. Solid State Circuits, vol. 20, no. 2, pp. 531–536, April 1985. [4] Y. Suzuki, K. Odagawa, and T. Abe, “Clocked CMOS calculator circuitry,” IEEE J. Solid State Circuits, vol. 8, no. 6, pp. 734–739, Dec. 1973. [5] K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu, “A 3.8-ns CMOS 16 × 16-b multiplier using complementary pass-transistor logic,” IEEE J. Solid State Circuits, vol. 25, no. 2, pp. 388–395, April 1990. [6] T. Kengaku, Y. Shimazu, T. Tokuda, and O. Tomisawa, IECE Jpn., 2–83, 1987. © 2003 by CRC Press LLC

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[7] Y. Oowaki et al., “A 7.4ns CMOS 16 × 16 multiplier,” in ISSCC Dig. Tech. Papers, pp. 52, 53, 1987. [8] A. P. Chandrakasan, S. Sheng, and R.W. Brodersen, “Low-power CMOS digital design,” IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 473–484, April 1992. [9] K. Shimohigashi and K. Seki, “Low-voltage ULSI design,” IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 408–413, April 1993. [10] P. G. Gray and R. G. Meyer, “MOS operational amplifier design — a tutorial overview,” IEEE J. Solid-State Circuits, vol. 17, no. 6, pp. 969–982, Dec. 1982. [11] R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing, New York: John Wiley & Sons, 1986. [12] D. M. Pietruszynski, J. M. Steininger, and E. J. Swanson, “A 50-Mbit/s CMOS monolithic optical receiver,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1426–1433, Dec. 1988. [13] G. Williams, U.S. Patent, 4,574,249, Mar. 4, 1986. [14] P. K. Simpson, “Foundations of neural networks,” in Artificial Neural Networks: Paradigms, Appli­ cations, and Hardware Implementations, E. Sánchez-Sinencia and C. Lau, Eds. New York: IEEE Press, 1992, pp. 3–24. [15] S. M. Gowda, B. J. Sheu, J. Choi, C.-G. Hwang, and J. S. Cable, “Design and characterization of analog VLSI neural network modules,” IEEE J. Solid-State Circuits, vol. 28, no. 3, pp. 301–313, March 1993. [16] M. Ismail, S. V. Smith, and R. G. Beale, “A new MOSFET-C universal filter structure for VLSI,” IEEE J. Solid-State Circuits, vol. 23, no. 2, pp. 183–194, Feb. 1988. [17] R. E. Geiger, P. E. Allen, and N. R. Strader, VLSI Design Techniques for Analog and Digital Circuits, New York: McGraw-Hill, 1990. [18] M. Banu and Y. Tsividis, “Fully integrated active RC filters in MOS technology,” IEEE J. Solid-State Circuits, vol. 18, no. 6, pp. 644–651, Dec. 1983.

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61 Digital Systems

61.1 Programmable Logic Devices

F. Gail Gray Virginia Polytechnic Institute and State University

Wayne D. Grover TR Labs, University of Alberta

Josephine C. Chang Taiwan Semiconductor Manufacturing Co.

Bing J. Sheu Nassda Corporation

Roland Priemer University of Illinois at Chicago

Kung Yao University of California

Flavio Lorenzelli University of California

PLD Device Technologies • PLD Notation • Programmable Logic Array (PLA) • Programmable Read Only Memory (PROM) • Programmable Array Logic (PAL) • Classification of Combinational Logic PLD Devices • Designing with Combinational Logic PAL Devices • Designing with Sequential PAL Devices • Designing with PALs Having Programmable Macro-Cell Outputs • FPGA Technologies • FPGA Architectures • Design Process • VHDL Synthesis Style for FPGAs • Synthesis of State Machines

61.2 Clocking Schemes Introduction • Clocking Principles • Clock Distribution Schemes • Future Directions

61.3 MOS Storage Circuits Dynamic Charge Storage • Shift Register • Dynamic CMOS Logic

61.4 Microprocessor-Based Design Introduction • Features of a Microprocessor-Based System • Memory • Microprocessor Architecture • Design Using a General-Purpose Microprocessor • Interfacing • Design Using a Microcontroller • Design Guidelines

61.5 Systolic Arrays Concurrency, Parallelism, Pipelining, and Systolic Array • Digital Filters • Systolic Word and Bit-Level Designs • Recursive Least-Squares Estimation • Kalman Filtering • Eigenvalue and Singular Value Decompositions

61.1 Programmable Logic Devices F. Gail Gray Traditional programmable logic devices (PLDs) and field programmable gate arrays (FPGAs) allow circuit designers to implement logic circuits with fewer chips relative to standard gate level designs based on primitive gates and flip-flops. As a result, layout and unit production costs are generally reduced. In this chapter, we use the term programmable device to refer to the class of moderately complex single-chip devices, in which the user in the field can program the function of the device. We include such devices as the programmable logic array (PLA), programmable array logic (PAL), programmable read-only memory (PROM), and the field programmable gate array (FPGA). Since most commercial vendors provide software design aids for mapping designs to their specific chips, initial design costs and time to market are low. Another important advantage of programmable device designs is flexibility. Design changes do not require physical changes to the printed circuit board as long as the revised functions still fit onto the same programmable chip. The low cost of design revisions makes programmable chips very

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The Circuits and Filters Handbook, Second Edition

Complexity Ladder of Devices

Device SSI discrete gate chip MSI chip PLDa LSI (PROM)a FPGA MPGA Standard cell Custom chip a

Complexity of a Single Chip

Range of Realizable Functions

Lowest

All functions Narrow Moderate All combinational functions with n inputs Wide Wide Wide All functions

Highest

Initial Design and Cost of Design Change

Unit Product Cost (High Volume)

High High Low Very low

High High Moderate Moderate

High High Low Low

Low High High Very high

Moderate Low Low Very low

Low High High Very high

Time to Market

Field programmable.

attractive for prototype design and low volume production. Designers often move up the design ladder once proven designs move into high volume production. Table 61.1 shows the position of PLDs, PROMs, and FPGAs on the complexity ladder of device types. In the “Range of Realizable Functions” column, we compare the range of realizations for various device types. Discrete gates can implement any function if enough gates are available. MSI chips implement very specialized functions such as shift registers, multiplexers, decoders, etc. The table compares pro­ grammable devices (PLDs, FPGAs, and PROMs) relative to the range of functions that can be imple­ mented on a single chip. A PROM chip with n address inputs can implement any combinational function of n variables. A PLD chip with n inputs can implement only a subset of the combinational functions of n variables. Gate arrays can implement a wide range of both combinational and sequential functions. The programmable devices are characterized by low time to market, low design cost, low cost of modi­ fications, and moderate production costs. Non-field programmable devices such as mask programmable gate arrays (MPGAs), standard cell devices, and full custom devices are characterized by high initial design costs and longer time to market, but have lower volume production costs. Custom chips are preferred for large volume production because of the very low unit production costs. However, initial design costs and the cost of design changes is very high for custom chip design. Also, the design of custom chips requires highly trained personnel and a large investment in equipment. The low design cost, low cost of design changes, and low time to market make PLDs and FPGAs good choices for lower volume production and for prototype development. The primary difference between PLDs and FPGAs arise because of a difference in the ratio of the number of combinational logic gates to the number of flip-flops. PLD devices are better for applications that require complex combinational logic functions that drive a relatively small number of flip flops, such as finite-state machine controllers or purely combinational logic functions. FPGAs are better for devices that require arithmetic operations (adders, multipliers, and arithmetic logic units), or that require a large number of registers and less complex combinational logic functions, such as digital filters.

PLD Device Technologies Companies produce PLD devices in different technologies to meet varying design and market demands. There are two categories of technologies. Process technology refers to the underlying semiconductor structure, which affects device speed, power consumption, device density, and cost. Programming tech­ nology refers to the physics of chip programming and affects ease of programming and the ability to reprogram or to reconfigure chips. Process Technologies The dominant technologies in PLD devices are bipolar and CMOS. Bipolar devices are faster and less expensive to manufacture, but consume more power than CMOS devices. The higher power requirements © 2003 by CRC Press LLC

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of bipolar devices limit the gate density. Typical CMOS devices, therefore, achieve much higher gate densities than bipolar devices. The power consumption of CMOS devices depends on the application because a CMOS device only consumes power when it is switching states. The amount of power consumed increases with the speed of switching. Therefore, the total amount of power consumed depends on the frequency and speed of state changes in the device. Some devices have programmable power standby activation that puts the device in a lower power consumption configuration if no input signal changes for a predefined amount of time. The device then responds to the next input change much slower than normal but switches back to the faster speed configuration and maintains the faster speed as long as input changes continue to occur frequently. When programmed in the standby power mode, power consumption is reduced on the average at the expense of response time of the device. When programmed to operate in the turbo mode, the device stays in the faster configuration at all times. The result is higher power consumption, but faster response time. The mode of operation is selected by the user to match the requirements of an application. To take advantage of the higher densities of CMOS devices and still be compatible with bipolar devices, many CMOS PLAs have special driver circuits at the input and output pins to allow pin compatibility with popular bipolar devices such as the commonly used TTL devices. ECL is a very high-speed technology used in some PLD devices. Although ECL has the highest speed of the popular technologies, the power consumption is very high which severely limits the gate density. Security is another issue that is related to process technology. Many PLDs have a programmable option that prevents reading the program. Since the software provided by most manufacturers allows the user to read the program in the chip in order to verify correct programming, it is extremely easy to copy designs. To prevent illegal copying of patented designs, one simply blows the security fuse, which perma­ nently prevents anyone from reading the program by normal means. However, the program in most bipolar circuits can easily be read by removing the case and examining the programmed fuses under a microscope. CMOS PLDs are much more secure because it is virtually impossible to determine the program by examining the circuit. Programming Technologies The programming technologies used in PLDs are virtually the same as the programming technologies available for ROMs. Programming technologies are divided into two broad categories: mask program­ mable devices and field programmable devices. In mask programmable technologies, identical base chips are produced in mass. The final metallization step is simply omitted. A mask programmable PLD chip is programmed by performing a final metal deposition step that selects the programming options. Clearly, this step must be performed at the manufacturer’s plant. The user makes entries on order forms that specify how the chip is to be pro­ grammed and sends it to the manufacturer. The manufacturer must then prepare one or more production masks prior to making the chip. Mask programmable devices incur a high setup cost to make the first device, but unit production costs are typically less than half of that for field programmable technologies. The usual practice is to use field programmable devices for prototype work and implement only proven designs in mask programmable technologies when a large production volume is required. Many PLD devices are available in both mask programmable and field programmable versions, which make the conversion easy and reliable. The user can program field programmable technologies directly. Specialized equipment is needed. Modern programming devices can actually program both ROM and PLD devices. The programmer is typically controlled by a small computer (PC) and uses files prepared in standard format (JEDEC) by software provided by the manufacturer or written by software vendors. Such software can include elegant features such as a programming language (ABEL, VHDL, Verilog, etc.), truth table input, equation input, or state machine input. Selection of a chip vendor should include careful evaluation of the support software for programming the chip. Field programmable PLD technologies can be classified into three broad categories: fusible link PLDs, ultraviolet erasable PLDs (EPLDs), and electrically erasable PLDs (EEPLDs). Field programmable ROMS © 2003 by CRC Press LLC

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come in analogous forms: fusible link ROMs (PROMs), ultraviolet erasable ROMS (EPROMs), and electrically erasable ROMS (EEPROMs). Fusible link PLDs typically utilize bipolar process technology. The programmer blows selected fuses in the device. Because higher than normal voltages and currents are required to blow the fuses, program­ ming fusible link PLDs can be quite stressful for the device. Overheating is a common problem. However, this technology is quite well developed and the design of programming devices is sufficiently mature so that reliable results can be expected as long as directions are carefully followed. Fusible link technologies provide the convenience of on-site programming, which reduces the time required to develop designs and the time required to make design changes. The trade-off involves at least a twofold increase in per unit cost and a significant reduction in device density relative to mask programmable devices because the fuses take up considerable chip space. A fusible link PLD can be programmed only once because the blown fuses cannot be restored. Ultraviolet erasable PLDs (EPLDs) have a window on the top of the chip. Programming the chip involves storing charges at internal points in the circuit that control switch settings. Shining ultraviolet light through the window on the chip can dissipate the charges. Therefore, EPLDs provide the convenience of reprogramming as a design evolves. On the downside, EPLDs cost at least three times as much per chip as mask programmable PLDs and operate at much slower speeds. Since EPLDs typically utilize CMOS technology, they are slower than fusible link PLDs but require less power. Therefore, EPLDs are often used in development work with the final design being implemented in either fusible link technology (for faster speed) or mask programmable technology (for faster speed and lower density). In spite of the fact that EPLDs cost more than fusible link PLDs, the reprogramming feature eventually results in a lower cost for development than using fusible link PLDs. This technology requires an additional piece of hardware to erase the chips. Electrically erasable PLDs (EEPLDs) provide the convenience of reprogramming without the need to erase the previous program because the chip is programmed by setting the states of flip-flops inside the device. It is, therefore, not necessary to purchase an erasing device. The reprogramming also requires less time to accomplish. Of course, EEPLD chips cost more and have a lower gate density than EPLD chips.

PLD Notation PLDs typically have many logic gates with a large number of inputs. Also, there are often many gates that have the same set of inputs. For example, the PAL22V10 has 132 AND gates, each with the same 44 gate inputs. Obviously, the diagram for such a complex circuit using standard AND gate symbols would be extremely complex and difficult to read. Figure 61.1 is the conventional diagram for an 8-input AND gate. Clearly, a similar diagram for a 44-input AND gate would be very cumbersome. Figure 61.2 is the same 8-input AND gate in PLD

A B C D E F G H

Y FIGURE 61.1 Conventional diagram for an 8-input AND gate.

FIGURE 61.2 PLD notation for an 8-input AND gate. © 2003 by CRC Press LLC

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notation. The 8 parallel wires that actually occur as inputs to the AND gate are represented by a single horizontal line in PLD notation. The actual inputs to the AND gate are drawn perpendicular to the single line. There are usually more signal lines than just the 8 needed for this gate. An X is placed at the intersection of the single line with each of the perpendicular lines that provide actual inputs to the AND gate. Keep in mind that the single horizontal line actually represents 8 parallel wires that are not physically connected to each other. By comparing the internal structures of PLAs, PALs, and PROMs, we will describe the capabilities and limitations of each type of PLD. Since the PAL is currently the most popular PLD device, we will describe design methodology for both combinational and sequential PAL devices. By emphasizing the difference between designing with PALs and designing with standard logic gates, we provide practical insights about PLD design.

Programmable Logic Array (PLA) Figure 61.3 shows that the basic PLA consists of a programmable AND array followed by a programmable OR array. Vertical lines in the AND array represent the input variables (A, B, C, D). Since each input drives many AND gates, an internal buffer provides high current drive signals in both true and comple­ mented format for each input variable. Initially, there is a connection from each input variable and its complement to each AND gate. In this example circuit, each AND gate initially has 8 inputs (A, A, B, B, C, C, D, D). Each AND gate input line contains a fuse or electronic switch. We program the chip by blowing the fuses in lines that we do not need, or by programming the electronic switches. After programming, we remove the Xs from the lines that are disconnected. For example, in the programmed chip of Fig. 61.4, the upper AND gate implements product term (A · C · D). In the OR array of Fig. 61.3, there is an initial connection from each AND gate output to every input on each OR gate. Again, the single vertical line connected on the input side of each OR gate represents all six wires. Each of the input lines to the OR gates also contains a fuse or programmable switch. Figure 61.4 shows that, after programming, output X connects to product terms A · C · D, B · D, and C · D. The number of product lines on a chip limits the range of functions that fit onto the chip. The PLA chip in Fig. 61.3 can implement any three functions (X, Y, Z) of the same four variables (A, B, C, D) as long as the total number of required product terms is less than or equal to six. However, there are 100 different

FIGURE 61.3 Basic architecture for a PLA. © 2003 by CRC Press LLC

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FIGURE 61.4 An example of a programmed PLA.

product terms involving 4 variables. So, practical chips have many more product lines than this contrived example. In order to fit functions onto the chip, designers must be able to simplify multiple output functions using gate sharing whenever possible. Finding a minimal gate implementation of multiple output func­ tions with gate sharing is a very complex task. The goal is to minimize the total number of gates used. The size of gates does not matter. For example, whether an AND gate has four inputs or two inputs is not important. All that changes is the number of fuses that are blown. This differs dramatically from the minimization goals when discrete gates are used. For discrete gate minimization, a four-input gate costs more than a two-input gate. Therefore, the classical minimization programs need to be modified to reflect the different goals for PLA development. Three parameters determine the capacity of a PLA chip. Let n be the number of inputs, p the number of product term lines, and m the number of outputs. Then the PLA chip can implement any m functions of the same n variables that require a total of p or fewer product terms. The device complexity is proportional to (m + n)p.

Programmable Read Only Memory (PROM) The programmable read only memory is the most general of the combinational logic PLD devices described in this section. However, from a structural viewpoint, the PROM is a special case of the PLA in which the AND array is fixed and the OR array is programmable. Figure 61.5 is a conceptual diagram of a PROM. The filled circles in the AND array represent permanent connections. The Xs in the OR array indicate that it is programmable. The number of product lines in a PROM is 2n ; whereas the number of product lines in a typical PLA is much smaller. A PROM has a product line for each combination of input variables. Since any logic function of n variables can be expressed in a canonical sum of minterms © 2003 by CRC Press LLC

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FIGURE 61.5 Conceptual diagram of a PROM.

FIGURE 61.6 An example of a programmed PROM.

form in which each product term is a product of exactly n literals, the PROM can implement any function of its n input variables. To demonstrate the generality of the PROM, Fig. 61.6 shows how the PROM of Fig. 61.5 must be programmed so as to implement the same set of logic functions that are programmed into the PLA of Fig. 61.4. The PROM program follows directly from the truth table for a logic function. The truth table for the logic functions X, Y, and Z appears in Table 61.2. The correspondence between the truth table and the program in the PROM of Fig. 61.6 is straightforward. A logic 1 in the truth table corresponds to an X in the figure and a logic 0 in the table corresponds to the absence of an X. A PROM with n address lines (serving as n input variable lines) and m data lines (serving as m output variable lines) can implement any m functions of the same n variables. Unlike a PLA, a PROM has no © 2003 by CRC Press LLC

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TABLE 61.2 Truth Table for the Logic Functions Implemented in the PROM ABCD

XYZ

ABCD

XYZ

0000 0001 0010 0011 0100 0101 0110 0111

111 000 100 000 111 101 110 111

1000 1001 1010 1011 1100 1101 1110 1111

001 010 101 010 001 111 111 111

restrictions due to a limited number of product lines. The PROM contains an n input, 2n output decoder that generates 2n internal address lines that serve as product lines. Since the decoder grows exponentially in size with n, the cost of a PROM also increases rapidly with n. The justification for a PLA is to reduce the cost of the PROM decoder by providing fewer product terms since many practical functions require significantly fewer than 2n product terms. As a result, some n variable functions will not fit onto a PLA chip with n input variables, whereas any n variable function will fit onto a PROM with n address lines.

Programmable Array Logic (PAL) Programmable array logic (PAL) is the most popular form of PLD today. Lower price, higher gate densities, and ease of programming all tend to make PAL more popular than PLA. On the negative side, the range of functions that can fit onto a chip with the same number of inputs, outputs, and product lines is less for a PAL than for a PLA. Figure 61.7 is the basic architecture of a PAL. The PAL architecture is a special case of the PLA architecture in which the OR array is fixed. The filled circles in the OR array indicate permanent connections. Only the AND array is programmable. Compare this PAL architecture with the PLA archi­ tecture in Fig. 61.3. Since the OR array is not programmable, it is immediately evident that fewer functions will fit onto the PAL. In the PLA, the product terms can be divided among the three outputs in any way desired and product terms that are used in more than one output can share the same product line. In the PAL, each output is limited to a fixed number of product terms. In Fig. 61.7, all outputs are limited

FIGURE 61.7 Basic architecture of a PAL. © 2003 by CRC Press LLC

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FIGURE 61.8 An example of a programmed PAL.

to two product terms. In addition, if two output functions both require the same product term in a PAL, two different product lines must be used. Consider the three functions implemented on the PLA in Fig. 61.4. Since the three functions require a total of nine product terms, they will not fit onto the PAL of Fig. 61.7. However, any function that would fit onto this PAL would obviously fit onto the PLA since the OR array in the PLA can be programmed to be identical to the OR array of the PAL. Figure 61.8 is an example of three functions that fit onto this PAL. Note that we must use two different product lines to provide the same product term (A · C · D) to outputs X and Y. In order to describe the range of applications for a PAL, we must know the number of inputs, n, the number of outputs, m, and the number of product lines that are permanently connected to each output OR gate. The PAL of Fig. 61.7 has four inputs, n = 4, three outputs, m = 3, and has two product lines connected to each OR gate. This PAL is described as a 2-2-2 PAL with four input variables. Many PALs have the same number of product terms permanently connected to each output. In this case, the three parameters n, m, and p completely describe the size of the PAL. For PALs, the parameter p usually represents the number of product terms per output instead of the total number of product terms, as was the case for PLAs. The minimization algorithm for multiple output PALs is significantly less complex than the minimi­ zation algorithm for a PLA because gate sharing is eliminated as a possibility by the fact that the OR array is not programmable. This means that each output function can be minimized independently. Minimizing a single output function is much less complex than minimizing a set of output functions where gate sharing must be considered. Overall, the higher density, less complex minimization algorithms, and lower cost of PALs tend to offset the additional functional capabilities of PLAs.

Classification of Combinational Logic PLD Devices The programmability of the AND and OR array provide a convenient means to classify combinational logic PLD types. The classification of Table 61.3 illustrates comparative features of combinational logic PLD devices. Even though PLAs have the most general structure (i.e., both the AND and OR arrays are © 2003 by CRC Press LLC

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TABLE 61.3

Classification of Combinational PLD Devices

AND Array Fixed Fixed Field programmable Field programmable

OR Array

Device

Typical Number of Product Terms per Output Gate

Mask programmable Field programmable Fixed Field programmable

ROM PROM, EPROM, EEPROM PAL PLA

2n 2n 16 50–150

programmable), the number of functions that fit onto the chips is limited by the number of product terms per output. ROMs and PROMs have fixed AND arrays, but all possible product terms are provided. Therefore, PROMs and ROMs are the most general devices from a functional viewpoint. Applications are only limited by the size and cost of available devices. PALs are the most restricted devices from both the structural and functional viewpoints. Nevertheless, the lower cost relative to PROMS and PLAs, higher gate densities relative to PLAs, and wider variety of available chip types have contributed to a rapid rise in popularity of PAL devices. For this reason, we will concentrate on PAL devices in the rest of this section.

Designing with Combinational Logic PAL Devices Determining if a function will fit onto a PAL device is a complex procedure. To demonstrate the difficulty, we will examine the types of functions that can fit onto a PAL16L8 chip. Figure 61.9 shows that the PAL16L8 chip has 8 output pins and 16 pairs of vertical input lines to the AND array. The “L” in the chip name indicates that the 8 outputs are all active low combinational logic outputs. The most important information not provided by the device name is the number of product terms per output, which is 7 for this device. An additional product term provides an output enable for each output pin, so there are 8 product lines per output pin (a total of 64 product lines). There are 10 primary input pins (pin numbers 1–9 and 11). In terms of our definitions, it would seem that n = 10, m = 8, and p = 7. As we will demonstrate, this simplistic analysis significantly understates the capacity of this chip. A simplistic analysis would say that the PAL16L8 chip could implement any 8 functions of the 10 input variables as long as each function requires no more than 7 product terms. As far as it goes, this statement is correct. However, it significantly understates the capacity of the chip because it does not take into account the fact that 6 of the output pins are internally connected as inputs to the AND array (pins 13–18). This is the source of the additional 6 inputs to the AND array. These internal feedback connections significantly expand the capacity of the chip. Consider the following logic function. X = ABC +BCD + AE +DEF + AC + D + FGH +FGI +BEH + CH + IJ + BEJ + DH It appears that this logic function will not fit onto the PAL16L8 chip because it requires 13 product terms and each output has only 7 product lines. However, if not all chip outputs are needed for the application, we can use one of the feedback lines to fit this function onto the chip. We first partition the function X as follows: X = ABC +BCD + AE +DEF + AC + D + Y Y = FGH +FGI +BEH + CH + IJ + BEJ + DH Since Y has only 7 product terms, we will map function Y to the macro-cell connected to pin 18 and use the feedback line from pin 18 to connect Y to a pair of vertical lines in the AND array. Function Y is now available to all other cells as an input variable. Since function X also has 7 product terms, we will map X to the macro-cell connected to pin 17. One of the product terms in X is the single variable Y. Figure 61.10 shows the final implementation. To obtain the needed product terms for output X, we used two macro-cells in the array. As a result, pin 18 is no longer available as an output. © 2003 by CRC Press LLC

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FIGURE 61.9 Logic diagram of PAL 16L8 chip. (Courtesy of Texas Instruments.)

Two practical matters need to be considered. First, some signals must now pass through the AND array twice as they proceed from an input to an output due to the feedback path. Therefore, the delay of the chip is now twice what it was when the feedback path was not utilized. Second, the buffer inverts the outputs; therefore, we actually obtain X on pin 17. If X is specified to be active low, then the output on pin 17 is exactly what we need. If the output X is specified to be active high, then an inverter is required. Since PALs are available with both active low and active high outputs, a designer should select an appropriate PAL to eliminate the need for inverters. Another feature that adds to the flexibility of the chip is that pins 13–18 can be used either as inputs or as outputs. For example, the enable for the output buffer at pin 15 can be permanently disabled. Since © 2003 by CRC Press LLC

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FIGURE 61.10 Implementation of function with 13 product terms on PAL16L8 chip.

pin 15 is connected directly into the AND array, it is no different from any other input, say pin 2. Of course, by permanently disabling the buffer at pin 15, the OR array connected to the buffer is also disconnected. In order to use pin 15 as an input, we must give up the use of the macro-cell connected to pin 15. However, dual use pins and feedback lines dramatically extend the range of applications for the chip. For example, suppose we need only one output and select pin 19 for that use. Then, pins 13–18 © 2003 by CRC Press LLC

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are available either as inputs or as feedback lines. We can therefore fit a wide range of functions onto the chip with varying numbers of inputs and product terms. Assuming that we need only the one output on pin 19, then we could have up to 16 inputs (pins 1-9, 11, 13-18). We could, of course, use only the 7 product lines in the macro-cell connected to pin 19 to implement our function. We, therefore, conclude that the PAL16L8 chip can implement any single function of 16 variables that requires no more than 7 product terms. If we need more product terms but not as many input variables, then we can connect pin 11 to pin 12. This connects the output on pin 12 back into the AND array the same as any other input variable. The output on pin 19 can pick up the 7 product terms on pin 12 as an input. This takes up one of the product lines for pin 19, but 6 product lines remain. Therefore, the single output on pin 19 can now have up to 13 product terms. However, pin 11 is no longer available as an input. Therefore, we must conclude that the PAL16L8 can implement any single function of 15 variables that requires no more than 13 product terms. If we want to maximize the number of product terms for a single output at pin 19, then we can use pins 13–18 and pin 11 as feedback lines. Each feedback line contributes 7 product terms. The AND array for pin 19 can pick up all 49 product terms by using one product line to pick up each feedback variable. All product lines are now busy. The OR gate at pin 19 then sums all 49 product terms. The only pins that are now available for inputs are 1–9. We therefore conclude that the PAL16L8 can implement any single function of 9 variables that requires 49 or fewer product terms. Clearly, there are many combinations of implementations with a variety of values for the number of inputs, the number of outputs, and the number of product terms per output. Table 61.4 shows the full range of possible implementations. For example, from the tables we note that the PAL16L8 can implement any 3 functions of 10 variables in which the product terms are distributed among the three outputs in any of the following ways: 7-7-37, 7-13-31, 7-19-25, 13-13-25, or 13-19-19. The notation 7-7-37 means that two of the outputs require at most 7 product terms and that the third output requires at most 37 product terms. To accomplish these results, 5 of the output pins must be devoted to feedback lines. Any implementation that uses a feedback line will have a time delay equal to twice that of a single macro-cell. In the “Delay” column of Table 61.4, symbol TA represents the delay that a signal experiences while passing through the AND–OR array one time. In implementations that do not use feedback lines, signals experience a maximum delay of TA. For implementations that use one or more feedback lines, the delay is 2 TA because some input signals propagate through the AND–OR array twice before reaching an output pin. However, none of the implementations in the table require more than twice the normal time delay for a single macro-cell. Although the tables cover broad generalizations for classes of functions that will fit onto the PAL16L8 chip, there are certain special types of more complex functions that will fit. For example, suppose that input variables A, B, C, D, E, F, G, H, and I occupy pins 1–9. Further suppose that we implemented functions S, T, V, W, X, Y, and Z using the macro-cells connected to pins 12, 13, 14, 15, 16, 17, and 18, respectively. Further suppose that we connect pin 12 to pin 11 so that all of these functions are connected to a pair of vertical input lines in the AND array. Thus, all of these functions are now available to the single output P at pin 19. This approach allows many very complex logic functions to fit onto the chip. Example 61.1. Let each of the functions S, T, V, W, X, Y, and Z be a sum of products expression involving the 9 input variables with at most 7 product terms. For example, S might be S = ABCDEFGHI + ABCDEFGHI + BCDEFGHI + FGHI + AHI + DEFGHI + ABCDEFGHI Variables T, V, W, X, Y, and Z could be of similar complexity. Then, output P might be P = ABCDEFGHISTVWXYZ +BCDEFGSTVWXYZ +⋅⋅⋅ where P has at most 7 such product terms.

The delay of this implementation is still twice the delay of one basic macro-cell.

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TABLE 61.4

Range of Implementions of PAL16L8 Chip

m

n

Number of Product Terms per Output

Delay

1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 3 3 3 3 3 3 4 4 4 4 4 5 5 5 6 6 6 7 7 8

16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 15 14 13 12 11 10 14 13 12 11 10 13 12 11 12 11 10 11 10 10

7 13 19 25 31 37 43 49 7-7 7-13 7-19, 13-13 7-25, 13-19 7-31, 13-25, 19-19 7-37, 13-31, 19-25 7-43, 13-37, 19-31, 25-25 7-7-7 7-7-13 7-7-19, 7-13-13 7-7-25, 7-13-19, 13-13-13 7-7-31, 7-13-25, 7-19-19, 13-13-19 7-7-37, 7-13-31, 7-19-25, 13-13-25, 13-19-19 7-7-7-7 7-7-7-13 7-7-7-19, 7-7-13-13 7-7-7-25, 7-7-13-19, 7-13-13-13 7-7-7-31, 7-7-13-25, 7-7-19-19, 7-13-13-19, 13-13-13-13 7-7-7-7-7 7-7-7-7-13 7-7-7-7-19, 7-7-7-13-13 7-7-7-7-7-7 7-7-7-7-7-13 7-7-7-7-7-19, 7-7-7-7-13-13 7-7-7-7-7-7-7 7-7-7-7-7-7-13 7-7-7-7-7-7-7-7

TA 2TA 2TA 2TA 2TA 2TA 2TA 2TA TA 2TA 2TA 2TA 2TA 2TA 2TA TA 2TA 2TA 2TA 2TA 2TA TA 2TA 2TA 2TA 2TA TA 2TA 2TA TA 2TA 2TA TA 2TA TA

Example 61.2. This example illustrates embedded factors. Each equation has at most 7 product terms involving the listed variables. S = f(A - I) = ABCDEFGHI + ABCDEFGHI +⋅⋅⋅ T = f(S, A - I) = ABCDEFGHIS + ABCDEFGHIS +⋅⋅⋅ V = f(S, T, A - I) = CDEFGHIST +BCDHIST +⋅⋅⋅ W = f(S, T, V, A - I) = ABCDEFGHISTV + DEFHISTV +⋅⋅⋅ X = f(S, T, V, W, A - I) = AB CDE CDEFGHISTVW +ETVW +⋅⋅⋅ Y = f(S, T, V, W, X, A - I) = ABCDEFGHISTVWX + DHISTVWX +⋅⋅⋅ Z = f(S, V, T, W, X, Y, A - I) = ABCDEFGHISTVWXY + FHIWXY +⋅⋅⋅ P = f(S, V, T, W, X, Y, Z, A - I) = ABCDEFGHISTVWXYZ +BCDEFGSTVWXYZ V +⋅⋅⋅

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The delay of this implementation is 8 times the delay of a single macro-cell because an input signal change might have to propagate serially through all of the macro-cells on its way to the output at pin 19. These examples demonstrate that very complex functions can fit onto the chip. Determining the optimum way to factor the equations is a very complex issue. Chip manufacturers and third party vendors provide software packages that aid in the fitting process.

Designing with Sequential PAL Devices The concept of registered outputs extends the range of PAL devices to include sequential circuits. Figure 61.11 is the logic diagram for the PAL16R4 chip. Again, this chip has 16 pairs of inputs to the AND array. The R4 part of the designation means that the chip has four outputs connected directly to D type flip-flops, i.e., the outputs are registered. Let us add another parameter, k, to designate the number of flip-flops on the chip. An examination of Fig. 61.11 indicates that the PAL16R4 also has four combi­ national outputs with feedback connections to the AND array. These pins are I/O pins because they can also be used as inputs if the OR output to the pins is permanently disabled. All outputs are active low. The chip has eight input pins. Using our parameter system, the PAL16R4 apparently has n = 8, m = 4, k = 4, p = 7 for combinational pin outputs and p = 8 for registered pin outputs. However, as for the PAL16L8, these numbers significantly understate the capabilities of this chip. Since the four registered outputs are also connected back into the AND array, this chip can implement a sequential circuit with the registered outputs serving as state variables. Therefore, this chip can imple­ ment any 8-input, 4-output, sequential circuit that needs no more than 4 state variables (16 states) and no more than 7 product terms for each output or 8 product terms for each state variable. Separate pins provide an enable for the state variables (pin 11) and a clock for the flip-flops (pin 1). Thus, the state variables are also available at output pins. By an analysis similar to that used in the previous section, we can utilize the feedback lines to significantly expand the types of circuits that will fit onto the PAL16R4 chip. Table 61.5 shows the range of basic possibilities. For example, the table indicates that the PAL16R4 chip can implement any single output, 8-input, sequential circuit that requires no more than four state variables (16 states) and in which the available product terms may be divided among the outputs and state variables in seven different distributions. The notation (7)-(8-8-8-26) means that the single output can have up to 7 product terms, that one state variable can have up to 26 product terms, and that the other three state variables can have up to 8 product terms each.

Designing with PALs Having Programmable Macro-Cell Outputs The PAL16R4 chip has limited application potential because the outputs from pins 14-17 must be registered. Most new chips allow a user to decide whether to have registered or combinational outputs at each pin and also allow the user to select either active high or active low outputs. The PAL22V10 chip (see architecture in Fig. 61.12), demonstrates this additional flexibility. Each of 10 macro-cells contains a normal PAL AND array and an I/O architecture control block. Each PAL AND array provides a differing number of product terms permanently connected as inputs to an OR gate and an additional product term that enables an output buffer. The number of product terms per output is printed near the OR gate symbol (8, 10, 12, 14, 16, 16, 14, 12, 10, 8). Figure 61.13 shows that this chip is similar in form to the PAL chips described earlier in this chapter. There are 22 vertical pairs of input lines to the AND array. Of these pairs, 11 are connected directly to input pins labeled I1 – I11 (pins 2-11, 13). Ten pairs are feedback lines from the architecture control blocks of the 10 macro-cells. Each macrocell is associated with a bi-directional pin (pins 14-23) that can be used either as an input pin, an output pin, or a bi-directional bus pin. If used as a bi-directional bus pin, the designer must control the output enable using a product term from the AND array. The 22nd pair, labeled CLK/I0, is connected to pin 1. If the chip is being used to implement a purely combinational circuit, pin 1 can be used as an additional input variable. If a sequential circuit is being implemented, pin 1 must be used as the clock signal for the flip-flops. © 2003 by CRC Press LLC

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FIGURE 61.11 Logic diagram of PAL16R4 chip.

The architecture control block in each macro-cell provides designer control over the signal that is connected to the bi-directional pin and feedback line associated with that macro-cell. Figure 61.14 shows that the architecture control block contains a D flip-flop, an inverter, two multiplexers with programmable select lines, and an output buffer with an enable. The Output MUX selects either the direct output of the combinational AND array (either active high or active low) or the data value stored in the D flipflop (either active high or active low). If the output enable is active, the buffer steers the signal selected by the Output MUX to the pin. An inactive enable causes the buffer to enter the high impedance state, © 2003 by CRC Press LLC

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TABLE 61.5

Range of Basic Implementations of PAL16R4 Chip

m

n

k

Number of Product Terms per (Combinational Output)–(State Variable)

Delay

1 1 1 1

11 10 9 8

4 4 4 4

TA 2TA 2TA 2TA

2 2 2 3 3 4

10 9 8 9 8 8

4 4 4 4 4 4

(7)-(8-8-8-8) (7)-(8-8-8-14), (13)-(8-8-8-8) (7)-(8-8-8-20), (7)-(8-8-14-14), (13)-(8-8-8-14), (19)-(8-8-8-8) (7)-(8-8-8-26), (7)-(8-8-14-20), (7)-(8-14-14-14), (13)-(8-8-8-20), (13)-(8-8-14-14), (19)-(8-8-8-14),(25)-(8-8-8-8) (7-7)-(8-8-8-8) (7-7)-(8-8-8-14), (7-13)-(8-8-8-8) (7-7)-(8-8-8-20), (7-7)-(8-8-14-14), (7-13)-(8-8-8-14), (7-19)-(8-8-8-8), (13-13)-(8-8-8-8) (7-7-7)-(8-8-8-8) (7-7-7)-(8-8-8-14), (7-7-13)-(8-8-8-8) (7-7-7-7)-(8-8-8-8)

TA 2TA 2TA TA 2TA TA

FIGURE 61.12 Architecture of the PAL22V10 chip. (Courtsey of Advanced Micro Devices, Inc.)

which effectively disconnects the buffer from the pin. The pin can then be an input or can be connected to an external bus. The feedback signal selected by the Feedback MUX is either the pin signal or the data value stored in the flip-flop (low active). Therefore, the feedback line can be used to expand the number of product terms, to provide a state variable for a sequential circuit, to provide an additional input for the chip, or to implement a bi-directional pin. Figures 61.13 and 61.14 show that the common clock input to all flip flops comes directly from pin 1, that a single product term (SP) provides a common synchronous preset for all flip flops and that another single product line (AR) provides a common asynchronous reset for all flip flops. The asynchronous reset occurs when the product line is active independent of clock state. The synchronous preset occurs only on the active edge of the clock when the preset product line is active. The two programmable multiplexers in the architecture control block significantly increase the flexi­ bility of the chip compared to either the PAL16L8 or the PAL16R4. Table 61.6 shows several combinations of switch settings along with typical applications for each setting. The PAL22V10 is much more versatile than either the PAL16L8 or the PAL16R4. Since pins 14-23 can be used as inputs, combinational outputs, or registered outputs, the following inequalities describe the possibilities. If the chip is used to implement a combinational logic function, the constraints are: n ≤ 22,

m ≤ 10

(n + m) ≤ 22 © 2003 by CRC Press LLC

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FIGURE 61.13 Complete circuit diagram for the PAL22V10 chip. (Courtesy of Advanced Micro Devices, Inc.)

For sequential circuits, the constraints are:

n ≤ 21, m ≤ 10, k ≤ 10

(m + k ) ≤ 10, (n + m + k ) ≤ 21

because the clock signal for the flip-flops uses one of the input pins (pin 1).

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FIGURE 61.14 Macro-cell architecture of PAL22V210 chip. (Courtesy of Advanced Micro Devices, Inc.)

TABLE 61.6

Applications for Combinations of Switch Settings for the PAL22V10 Chip

Name

Output Connection

Feedback Connection

Application

INP COCF COIF RORF ROIF

None Combinational Combinational Register Register

Pin Combinational Pin (input) Register Pin (input)

Use pin as input only Combinational output and/or combinational feedback Bi-directional pin implementing a combinational output Typical state machine controller Bi-directional pin with registered output. Bus applications

Table 61.7 shows representative sizes for circuits that will fit onto the PAL22V10 chip.

FPGA Technologies Due to the relatively high complexity of FPGAs, almost all FPGAs use CMOS process technology because of its high density and low power characteristics. Currently, there are two popular FPGA programming technologies, static RAM (SRAM) and anti-fuse. The anti-fuse device gets its name from the fact that its electrical properties are the dual of the electrical properties of a fuse. The anti-fuse is a pair of conducting plates separated by a di-electric insulator, similar to a small capacitor. By contrast, the fuse is a pair of terminals separated by a thin conducting wire. A fuse is programmed by passing a high current through the thin wire causing the wire to heat up and melt, producing an open circuit where a short circuit previously existed. Fusible link technology is used in many PLA and EPROM devices. By contrast, the anti-fuse is programmed by applying a high voltage across the di-electric insulator that permanently breaks down the di-electric insulator, producing a short-circuit where an open-circuit previously existed. Both fusible-link and anti-fuse devices are non-volatile which makes them particularly well-suited for use in extreme environments, such as space and other high radiation environments. Anti-fuse technology also provides higher speed operation than other technologies. SRAM chips are volatile (i.e., they lose their program when power is removed) and have lower density and slower speed than anti-fuse chips. On the positive side, SRAM chips are lower cost, re-programmable © 2003 by CRC Press LLC

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TABLE 61.7

Representative Circuit Sizes That Will Fit onto a PAL22V20 Chip Representative Combinational Logic Circuits

m

n

1 1 1 2 2 3 3 3 5 5 10

21 20 12 20 12 19 12 12 12 17 12

Number of Product Terms per Output 16 31 111 16-16 16-96, 29-83, 40-72, 49-63, 56-56 14-16-16 16-16-81 37-38-38 15-19-23-27-31 12-14-14-16-16 8-10-12-14-16-16-14-12-10-8

Delay TA 2TA 2TA 2TA 2TA TA 2TA 2TA 2TA TA TA

Representative Sequential Circuits m

k

n

Number of Product Terms per (Output)–(State Variable)

1 1 1 1 2 2 2 2 4 4 5 2

3 3 3 3 3 3 3 3 4 4 5 8

17 13 11 11 16 13 11 11 13 11 11 11

(16)-(14-16-16) (25)-(25-25-25) (88)-(8-8-10) (31)-(27-28-28) (16-16)-(12-14-14) (16-16)-(19-23-23) (44-45)-(8-8-10) (23-23)-(23-23-23) (14-14-16-16)-(10-10-12-12) (12-12-29-29)-(8-8-10-10) (12-14-14-16-16)-(8-8-10-10-12) (16-16)-(8-8-10-10-12-12-14-14)

TA 2TA 2TA 2TA TA 2TA 2TA 2TA TA 2TA TA TA

and, therefore, dynamically reconfigurable. In the current marketplace, SRAM chips have captured most of the popular commercial market.

FPGA Architectures Figure 61.15 shows a high-level layout of an FPGA chip. Each chip contains a two-dimensional array of identical configurable logic blocks (CLBs). The FPGA in Fig. 61.15 has 64 CLBs arranged in an 8 × 8 array. The user can program the CLBs to implement specific combinational or sequential logic functions. A programmable interconnect structure is permanently placed in the space between CLBs. The user

FIGURE 61.15 FPGA architecture. (Courtesy of Xilinx.)

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FIGURE 61.16 Programmable FPGA elements. (Courtesy of Xilinx.)

programs switches that make desired connections between his programmed CLBs either by setting SRAM bits or by permanently closing the anti-fuses. Programmable I/O blocks are located around the perimeter of the chip that allows the user to connect signals to pins on the chip. For convenience, in this paragraph we describe FPGA elements using SRAM terminology. Anti-fuse devices have similar components. FPGAs have three basic programmable elements, illustrated in Fig. 61.16. The lookup table (LUT) is a programmable RAM. The LUT shown in Fig. 61.16a is a 16 × 1 RAM. It has four address inputs and one data output. It is programmed by storing either a logic 1 or a logic 0 in each RAM location. The value at a specific location is read out (looked up) by applying the address at the RAM inputs. A programmable interconnect point (PIP) is simply a CMOS pass transistor with a programmable SRAM bit controlling the gate signal. If a connection between the two transistor terminals for the PIP in Fig. 61.16b is desired, a logic 1 is stored in the SRAM control bit. If no connection is desired, a logic 0 is stored in the SRAM control bit. SRAM bits also control the address lines of programmable multiplexers (MUX). The MUX in Fig. 61.16c has two input lines and therefore can be controlled by one SRAM bit. Programming the SRAM control bit to be logic 0 connects the upper MUX input to the MUX output. Programming the SRAM control bit to be logic 1 connects the lower MUX input to the MUX output. To illustrate the principles, consider the minimal CLB shown in Fig. 61.17. This CLB has three input signals (A, B, and C) and one output signal (X). The CLB has one 8 × 1 LUT and one D flip-flop with a reset input (R). It has three 2 × 1 programmable MUXs with SRAM control bits labeled M1, M2, and M3, respectively. The MUX controlled by M3 connects either the LUT output (F) or the bit stored in the flip-flop (Q) to the CLB output (X). If M3 = 0, the D flip-flop is bypassed and the CLB will implement the combinational logic function stored in the LUT. If M3 = 1, the CLB will implement a sequential function. The MUX controlled by SRAM bit M2 selects either the LUT output (F) or the input signal (C) as the reset signal for the flip-flop. The MUX controlled by SRAM bit M1 selects either input signal C or the bit stored in the flip-flop (Q) as the third address input (E) to the LUT. Inputs A and B are permanently connected to two of the LUT address lines.

A D

F B

LUT

M1

FIGURE 61.17 A minimal CLB.

© 2003 by CRC Press LLC

M3 R

CLK

E

C

X

Q

M2

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J D

F K

X

Q 1

LUT

R

CLK

Q

Reset 1

1

FIGURE 61.18 Minimal CLB programmed to be a JK flip-flop. TABLE 61.8 Contents of LUT for Programmed CLB J

K

Q

F

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 0 0 1 1 1 0

To illustrate how the minimal CLB in Fig. 61.17 could be programmed, we will show how to program it to implement a JK flip-flop. M3 will be 1 to select the flip-flop output as the CLB output. M2 will be 1 to select input C as the flip-flop reset signal. M1 will be 1 to select the flip-flop output (Q) as the E input to the LUT. Input A will be designated as the J input and input B will be designated as the K input for the flip-flop. Figure 61.18 shows the programmed CLB with all signal names related to their use in the JK flip-flop. Table 61.8 shows how the LUT must be programmed to implement the function of a JK flip-flop. Figure 61.19 shows an actual CLB in the XC4010XL chip, a small FPGA chip manufactured by Xilinx. This CLB uses the same small set of elements that we used in the minimal CLB. This CLB contains 2 D-flip-flops, 3 LUTs, and 16 programmable MUXs. If the user had to directly program each CLB and each PIP in the interconnect structure, the task would be formidable. However, most chip manufacturers provide software packages that allow the user to specify the device function using a variety of high-level abstractions. In the next section, we will discuss this process in more detail.

Design Process From the previous discussion, it is clear that fitting designs to PLD chips is a complex process. PLD manufacturers and third-party vendors market software packages that help engineers map designs onto chips. Selecting a package appropriate for a particular design environment is a critical decision that will significantly affect the productivity of the design group. There are basically three types of development system packages: user designed packages, vendor designed packages, and universal packages. Since these programs are very complex and require many years of effort to develop, most design groups will lack the time and resources to develop their own. Many vendors provide design aids that are specific to a particular product line. There is a great danger in becoming dependent upon one vendor’s products because new products in this field appear frequently. Clearly, a universal design package that supports a wide variety of product lines is most desirable. A variety of development systems with different features, capabilities, and price is available.

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C1

4

C4

H1

DIN/H2

SR/H0

EC S/R CONTROL

G4 G3 G2

DIN F' G' H'

LOGIC FUNCTION G' OF G1-G4

Bypass YQ D

SD

Q

G1 LOGIC FUNCTION OF H' F',G', AND H'

EC

G' H'

Y

F4 F3 F2

RD

1

DIN F' G' H'

LOGIC FUNCTION F' OF F1-F4

Bypass

S/R CONTROL D

SD

XQ Q

F1 EC

K (CLOCK)

RD

1 H' F'

X Multiplexer Controlled by Configuration Program

X6692

FIGURE 61.19 Actual CLB for the XC4010XL chip. (Courtesy of Xilinx.)

Figure 61.20 shows a flow diagram for the process typically used to design PLAs and FPGAs. Design entry refers to the use of an editor to create a source file that specifies the functional behavior of the device. High-level simulation verifies correct functional behavior of the device. Logic synthesis refers to the process of implementing the design using the primitive elements present on a specific chip, such as gates, flip-flops, registers, etc. Most development systems support prelayout simulation at this level to verify that the design still functions correctly. System partitioning and mapping refers to the process of grouping blocks of primitive elements into sets that map directly into major chip structures, such as CLBs in FPGAs or AND-OR arrays in PLDs. Place and route refers to mapping the structures into specific locations on the chip and making connections between them. The software package then performs a timing analysis on the final design to verify that design timing specifications are met. Finally, the chip is configured by generating an output file that can be read by the chip programmer. Design Entry It is essential for a universal development system to have a variety of design entry modes. Many vendors market the more complex design entry modes as optional features. This section describes some of the more common design entry modes and their value to PLD and FPGA designers. Boolean equations are an important method of design entry. A PLD design system must support Boolean equation entry because the AND-OR arrays on PLD chips directly implement Boolean equations. Almost all PLD designers will use Boolean equation entry extensively. Boolean equation entry is also useful for FPGA designs. Truth table entry allows specification of a combinational logic function by defining the output for each of the 2n input combinations. This form is particularly valuable if don’t care entries exist. Truth table entry is most commonly used for functions with a small number of input variables that are not easily described by Boolean equations. Code converters, decoders, and lookup tables are examples. A good design tool will support truth table entry. Symbolic state machine entry is crucial for PLD and FPGA designers because both PLDs and FPGAs are often used to implement state machine controllers. Current tools have features described as state

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Design Entry

High Level Simulation

Logic Synthesis

Prelayout Simulation

System Partitioning

Mapping

Place and Route

Timing Constraints Met ?

Configure

FIGURE 61.20 Design process.

machine entry that vary dramatically in form and usefulness. Before selecting a tool, the specifics of the state machine entry format should be carefully investigated. The most useful formats allow symbolic representation of states and specification of state transitions using some form of conditional statement such as if_then_else, or case. Relational operators are also useful in this context. The tool should perform automated state assignment and should fit the state variable equations to the target chip. State diagrams using graphics are useful, but not essential. This feature is mainly a convenience, provided that symbolic state machine entry is available. Schematic entry is a widely accepted way to describe logic systems. To be useful, it must be combined with a powerful partitioning and mapping tool that can fit the circuit onto chips. Schematic entry is useful to convert existing gate level designs into PLD or FPGA implementations. Hardware description language (HDL) entry is potentially the most useful of all methods. Popular HDL languages are VHDL, Verilog, and System C. Using these languages, a designer can specify an executable specification of his device. Mature simulators exist for all of these languages that allow functional verification of the high level HDL design. Logic Synthesis Logic synthesis is the process of transforming a given description of a device produced by one of the design entry methods described in the previous section into an equivalent netlist using primitive com­ ponents. For example, the process of transforming a symbolic state machine description or an HDL description into a netlist is an example of logic synthesis. The power of the synthesis algorithms in a development system is perhaps the most important feature of the system. HDL synthesis tools are beginning to be mature enough for use in both PLD and FPGA designs. Very good synthesis tools exist for subsets of the popular HDL languages. Full synthesis tools for all language © 2003 by CRC Press LLC

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constructs are still in the research phase. In the next section, we will illustrate how to synthesize FPGA designs using the VHDL language. Logic minimization is obviously an essential process in a PLD development system because the number of product terms per output gate on PAL chips is limited. Recall that the goal of logic minimization for PLD designs is to reduce the number of product terms, not the size of the product terms. Classical logic minimization algorithms use cost functions that reward reduction of the number of gate inputs. This is important for TTL gate implementations, for example, because an 8-input gate costs about four times as much as a 4-input gate. In PLD designs, the number of gate inputs does not matter. Each product term consumes one product line in the chip. A one-literal product term, such as X, costs exactly the same as a ten-literal product term, such as ABCDEFGHIJ. Therefore, traditional logic minimization programs, such as Espresso, need to be modified for PLD development. If product terms can be shared among different outputs, then multiple output minimization is necessary. However, for most PAL devices, the product terms cannot be shared; therefore, single output minimization algorithms are sufficient. Single output minimization algorithms are much less complex and take much less time to execute than multiple output minimization algorithms. Therefore, systems that do single output minimization result in higher productivity. Therefore, be careful of systems that advertise well-known traditional logic minimization algorithms to market their products, especially if multiple output minimization is stressed. Equation factoring, which is sometimes called multiple level minimization, is essential in order to fit large functions onto PLD chips using multiple cells combined with feedback lines inside the chips. This feature is missing from most vendor PLD development systems. However, in order to provide effective automated PLD synthesis, this operation is absolutely necessary. In most current PLD development systems, the designer must interact with the synthesis program to implement multiple level minimization. Such interaction requires extensive skill from the user of the software package. Simulation of Designs All good development systems include some form of simulation capability. The simulators vary widely in scope, user interface, and general usefulness. Behavioral simulation allows high-level design descriptions to be simulated independent of implemen­ tation. Behavioral simulators verify the input-output behavior of the device. Correct behavioral simula­ tion verifies the correctness of the algorithms prior to mapping the design to specific hardware components. Device simulators verify the function of the design after mapping the design to a specific chip but before actually programming the chip. This is the most common type of simulator in current PLD development systems. A device simulator will construct a software model of the target PLD architecture, map the design to that architecture, and then simulate the behavior of the specific PLD. The better simulators will provide timing information as well as functional information. Mapping Designs to Chips System partitioning, mapping, place and route, and configure functions are usually performed by vendorspecific development software. These software packages usually accept a netlist as input and produce an output file that can be read by the programming tool.

VHDL Synthesis Style for FPGAs Since HDL synthesis is one of the most popular ways to design FPGAs, we will show representative synthesis techniques for VHDL, one of the common HDL languages. The user may use these examples as templates to write code that will synthesize successfully. Registers and Flip-Flops Figure 61.21 shows a VHDL template for a register, AREG, with synchronous reset signal (RESET) and data input, A. In VHDL, entities are called processes. This code defines a process named SynchronousRegProcess. The list of signal names in the parentheses following the word process is called the sensitivity © 2003 by CRC Press LLC

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SynchronousRegProcess: process (CLK) begin -- No other statements here if (CLK'event and CLK='1') then if RESET ='0' then AREG

-- Data_Section

-- Control_Section

when S1 =>

-- Data Section

-- Control Section

when others =>

-- Actions

end case;

end if;

end process;

OUTPUT_PROCESS: process (STATE) begin

case STATE is

when S0 = >

-- Output_Signal_Assignments

when S1 =>

-- Signal Assignments

when others =>

-- Signal Assignments

end case;

end process;

end FSM;

FIGURE 61.31 VHDL template for a state machine.

Synthesis of State Machines Figure 61.31 shows a VHDL template for a state machine. First, the code includes a declaration of a data type called STATE_TYPE. This data type is simply a list of the names of the states. The names should be chosen to reflect the purpose of the state, such as INITIAL, IDLE, TRANSMIT, RECEIVE, etc. Next,

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a signal, STATE, is declared to be of type STATE_TYPE. Signal STATE keeps track of the current state of the state machine. The architecture consists of two processes. Process STATE_PROCESS updates the current state on each positive transition of clock signal CLK. Process OUTPUT_PROCESS updates the state machine outputs whenever there is a change in state. As written, these processes implement a Moore state machine. To design a Mealy state machine, simply add the machine input signals to the OUTPUT_PROCESS sensitivity list. The state machine has a low-active asynchronous RESET signal that initializes the state machine to state S0. A case statement performs data transfer statements and computes the next state based on the current state. For other approaches to using high-level languages to design digital systems, see [8].

References [1] Programmable Logic Data Book, Texas Instruments, Dallas, TX. [2] Programmable Logic, Intel Corporation, Mt. Prospect, IL. [3] C. Alford, Programmable Logic Designer’s Guide, Howard W. Sams & Company, Indianapolis, IN, 1989. [4] H. Katz, Contemporary Logic Design, Benjamin/Cummings Publishing Company, Redwood City, CA, 1994. [5] L. Pappas, Digital Design, West Publishing Company, St. Paul, MN, 1994. [6] D. Pellerin and M. Holley, Practical Design Using Programmable Logic, Prentice Hall, Englewood Cliffs, NJ, 1991. [7] J. F. Wakerly, Digital Design, Principles & Practices, 2nd ed., Prentice Hall, Englewood Cliffs, NJ, 1994. [8] J. R. Armstrong and F. G. Gray, VHDL Design: Representation and Synthesis, 2nd ed., Prentice Hall, Englewood Cliffs, NJ, 2000. [9] V.P. Nelson, H.T. Nagle, B.D. Carroll, and J.D. Irwin, Digital Logic Circuit Analysis and Design, Prentice Hall, Englewood Cliffs, NJ, 1995.

61.2 Clocking Schemes Wayne D. Grover Introduction Advances in VLSI processing technology, particularly CMOS, have resulted in submicron processes with roughly fourfold increases in circuit densities and two- to threefold increases in speed over the preceding 1.2 µm process. Consequently, CMOS applications at speeds near 1 GHz are now feasible. New design challenges must be mastered to realize systems at these speeds. In particular, clocking-related issues of skew, delay, power dissipation, and switching noise are potentially design-limiting factors. For example, at a bus speed of 200 MHz, 1 ns of skew represents 20% of the clock period. Yet to get the most advantage from available process speed we would like to keep skew under 10% of the clock period, thus setting a target of 500 ps of skew for dies that may be as large as 2 cm on a side. In large synchronous designs, the clock net is also typically the largest contributor to on-chip power dissipation and electrical noise generation, particularly “ground bounce”, which reduces noise margin. Ground bounce is a rise in ground potential due to surges of current returning through a nonzero (typically inductive) ground path impedance. A typical CMOS flip flop consumes 12 µW/MHz. At 200 MHz a system with 2 K flip flops will consume 4.8 W for clocking alone. At the board and shelf level, clock distribution networks also can be a source of electromagnetic emissions, and may require considerable delay tuning for optimization of the clock distribution network. In the past, multiphase clocking schemes and dynamic logic structures helped minimize transistor count, but this is now less important than achieving low skew, enhancing routability, controlling clockrelated switching noise, and providing effective CAD tools for clock net synthesis and documentation. © 2003 by CRC Press LLC

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For these reasons, a shift has occurred toward single-phase clocking and fully static logic in all but the largest custom designs today. In addition, phase-feedback control schemes using phase-locked loops (PLLs) are becoming common, as are algorithmic clock-tree synthesis methods. This section focuses on the issues and alternatives for on-chip and multichip clocking, with the primary emphasis on CMOS technology. We first review the fundamental nature and sources of skew and the requirements for the clocking of storage elements. We then outline and compare a number of “open­ loop” clock distribution approaches, such as the single-buffer, clock trunk, clock ring, H-tree, and balanced clock tree approaches. Phase-locked looped synchronization methods and PLL-based clock generation are then outlined. In closing, we look at future technologies and developments for high-speed clocking. The concepts and methods of this section apply to many circuit technologies on- and off-chip. However, we emphasize CMOS because CMOS processes (including bi-CMOS) presently represent the vast majority of digital VLSI designs and are expected to continue to do so. Asynchronous, self-timed, and wavefront array systems are outside the scope of this chapter. These approaches aim to minimize the need for low-skew synchronous clocking. However, truly asynchronous modules tend to require a large overhead in logic for interaction with each other, so that speed, size, and power often suffer relative to synchronous design. Nonetheless, self-timing can be an effective approach for random-access memory and read-only memory (RAM and ROM) cells, to which considerable optimization effort can be invested for reuse in many designs. Self-timed methods should be considered the alternative to fully synchronous design in large, highly modularized systems, particularly where welldefined autonomous modules have relatively infrequent interactions. The main issues in self-timed systems are the possibly high delay required to avoid metastability problems between self-timed modules, and the circuit costs of the synchronization protocol for intermodule communication.

Clocking Principles Most of us accept the clocked nature of digital systems without question, but what, fundamentally, is the reason for clocking? Any digital system can be viewed either as a pipeline or as a finite state machine (FSM) architecture, as outlined in Fig. 61.32. In the pipelined architecture clocked sections are cascaded, each section comprising an asynchronous combinational logic block followed by a latch or storage element that samples and holds the logic state at the clock instant. In the FSM, the only difference is that the next state input and the system outputs are determined by the asynchronous logic block, and the sampled next state value (S) are fed back into the combinational logic. The FSM can therefore be conceptually unfolded and also represented in a pipeline fashion. The fundamental reason for clocking digital systems is seen in this pipelined abstraction of a digital system: it is to bring together and retain coordination among asynchronously evolved intermediate results. With physical delays that are temper­ ature, process, and input dependent in combinational logic, we need to create agreed-upon time instants at which all analog voltages in a system are valid when interpreted as boolean logic states. Clocking deals with delay uncertainty in logic circuit paths by holding up the fast signals and waiting for the slower signals so that both are valid before they are again combined or interact with each other. Without this coordination purely asynchronous logic would develop severe propagation path differences, and be slow in repetitive operations. Ultimately, a valid state would evolve, but all inputs would have to be stable for the entire time required for this evolution. On the other hand, when the overall combinational logic function is appropriately partitioned between clocked storage latches, system speed can approach the limit given by the delay of a single gate because each logic sub-block is reused in each clock period. From this, we obtain several insights: (1) only the storage elements of a digital system need become loads on the clock net (assuming state logic gates); (2) the system cannot be clocked faster than the rate set by the slowest combinational signal path delay between clocked storage elements; (3) any uncertainty in clock timing (skew) is indistinguishable from uncertainty in the settling time of the intervening combinational logic; and (4) for a logic family to work, its storage elements must: (i) at no time be transparent (i.e., simultaneously connect input to output), (ii) have a setup time less than (T – tclk–Q ) where T is the clock period and tclk–Q is the clock-to-Q output delay of the same type of flop, and (iii) have © 2003 by CRC Press LLC

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clock

logic

logic

logic

registers (a) pipelined architecture clock

inputs

outputs

logic

register

next state

(b) finite-state machine atchitecture

FIGURE 61.32 Architecture of digital systems.

a hold time less than their clock-to-output delay. The last points may be better appreciated by considering that the combinational logic block may be null, i.e., a zero-delay wire, such as in a shift-register. An implication of [4(i)] is that two-phase nonoverlapping clocks, or an equivalent sequencing process, is fundamental for the storage elements of a digital system. This may sound unusual to readers who have already designed entire systems with SSI and MSI parts, or in gate-array design systems, without having seen anything but single-phase edge-triggered flip flops, latches, counters, etc. However, at least two clock phases (or clock-enabling phases) are internally required in any clocked storage device. An analogy is of a ship descending in elevation through a lock [27]. During the first clock phase sluice gates “charge” the lock up to the incoming water level and open the input gate to bring a ship in. Throughout this phase, it is essential that the output gate is closed, or water will race destructively right though the lock. Only when the ship is entirely in the lock and the input gate is closed (isolating the input) can the output sluice gates be opened to equalize the water level to that on the outgoing side, allowing the ship to leave (producing a new output). Similarly, in a flip flop or latch the currently stored value, which appears at the output, must be isolated from the input while the input evolves to its next value. Skew and Delay Clock skew is defined must generally as the difference in time between the actual and the desired instant of active clock edge at a given clocked storage element. In the majority of designs in which the desired instant of clocking is the same at all storage elements, skew is the maximum difference in clock waveform timing at different latches. Clock skew is of concern because it ultimately leads to the violation of setup or hold times within latches, or to clock race problems in multiphase clocking. Furthermore, from a design viewpoint, uncertainty in clock timings must be treated as equivalent to actual clock skew. Skew or timing uncertainty are therefore equivalent to an increase in critical path logic delay. In either case, the clock period must be extended to ensure valid logic levels and proper setup/hold requirements relative to the clock time. To illustrate the equivalence of skew (either actual of design timing uncertainty) to a loss of system speed, consider a 200-MHz process used in a design which as 25 % skew, (i.e., actual clock edge dispersion

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or, equivalently, uncertainty in clock timing is 1.25 ns). If a competitor uses the same process at 200 MHz and achieves 5 % skew (0.25 ns), then the latter design has 20 % more of each 5 ns clock cycle for settling combinational logic paths. Alternatively, for the same logic functions, the low-skew system could be clocked at 250 MHz with the same timing margins as the high-skew system. Skew, therefore represents a loss of performance relative to basic process capabilities developed at the great expense. However, skew reduction costs relatively little, and is in the logic designer’s control, not the process developer’s and yet it is directly equivalent to a basic enhancement in process speed. Skew is usually of primary concern on-chip or within any module that is designed on the presumption of a uniform clock phase throughout the module. Clock delay, on the other hand, is the difference between the nominal clock edge time at an internal flip flop and the system clock, or timing reference, external to the chip. While skew is typically managed internal to the die, delay is of concern at the system level to ensure external setup and hold time requirements. Skew and delay may be independent in any given clock distribution scheme. For example, an on-chip clocking tree that yields essentially zero skew may, nonetheless, impart a high clock delay, which will be of importance at the system level. The “early clock” technique and some PLL methods (presented later) can be used to address on-chip clock delay problems. Isochronic or Equipotential Regions The clock distribution problem arises at all scales of system design, from on-chip clock distribution in VLSI and WSI to the synchronization of circuit packs tens of meters apart. These application are unified as a generic problem: synchronous clocking of “electrically large” systems, i.e., systems in which propa­ gation time across the system is significant relative to the clock period. In such systems: D v > k fapp

(61.1)

where D is the characteristic scale or distance of the system, v is the propagation velocity, fapp is the application clock frequency, and k is the skew requirement as a fraction of the clock period. For all locations around a clock entry point at which (61.1) is false, we can consider events to be essentially simultaneous (or, equivalently, the region is a single electrical node), and the clock can be distributed within such regions without delay equalization. The region over which clock can be distributed without any significant skew is also known as an equipotential [27] region, or an isochronic region [1]. In this section, we are concerned only with cases in which (61.1) is true, but it is implicit that the clocked end nodes may be either clocked loads directly or a buffer that feeds a local isochronic region. The diameter (and shape) of an isochronic region on-chips depends on the wire type employed for interconnection. To control skew on chip, we need to consider delay differences due both to wire lengths and to the lumped capacitive efforts of the driven loads. Where the RC time constant of the wiring interconnect τw is much less than the RC combination of the driving source resistance and the lumped capacitance of N clocked loads on the net (τnet = Rs Cgate N = Nτg ), we can consider all points on a net to be isochronic, meaning that the net acts like one electrical node characterized by the total lumped capacitance of gates on the net. Wires on a chip are often modeled as distributed R0C0 sections, where R0 and C0 are the resistance and capacitance per unit length, respectively (see Fig. 61.33). In such cases, the propagation delay for a wire of length l follows the diffusion equation [31] τ w = RoCol 2 2

(61.2)

Therefore, if we consider a net of length l with N standard loads, we can consider the net to be isochronic if τw  Nτg . From (61.2), this implies: l

© 2003 by CRC Press LLC

2NRsCgate R0C0

(61.3)

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B′ C′ D′

B C D

SCHEMATIC A

ROUTING B

A

C D

ISOCHRONIC NET

NON-ISOCHRONIC NET B

C

B

C

A

A D

Ro

EQUIVALENT SCHEMATIC B,C,D, A

Co

D

B A

C D

RESULTS B C A D

B′ C′ D′

A

B C D

B′ C′ D′

FIGURE 61.33 Isochronic and nonisochronic passive wiring nets.

This relationship provides a guideline for the maximum length over which wire delays may be neglected relative to gate-charging delays. Based on typical values for a 1-µm process, τg < 500 ps, isochronic regions for lightly loaded lines (N = 1) are up to 10,000 λ for lines in third layer metal, 5000 and 8000 λ for first and second layer metal, respectively, and 200 λ for polysilicon wires, where λ is the minimum feature size of the process [31]. This illustrates the importance of distributing clock within metal layers to the greatest extent possible. Even a few short polysilicon links may introduce sufficient series resistance to drastically reduce the isochronic region for the given clock line. This also illustrates that if clock is distributed in metal layers, and is always buffered before exceeding the isochronic distance, it will be primarily differences in lumped capacitive loads and not wire length that determine clock signal delays, and hence relative clock skews. Nature of Skew On-Chip The concept of isochronic regions helps us understand the nature of clock skews in VLSI and helps explain why on-chip skews may be greater than those between off-chip points that are physically many more times distant. A key realization is that signals do not propagate at the “speed of light”. If they did, absolute delays across even the largest chips (2 cm edges) would be subnanosecond and the isochronic diameter would easily encompass an entire die at clock speeds up to 200 MHz. Rather, on-chip propa­ gation delay depends much more on the time needed for output drivers to charge the total lumped capacitance associated with all the gate inputs of the driven net. In other words, fanout and driver current abilities have more to do with delay than path lengths. This is especially true when clock distribution is © 2003 by CRC Press LLC

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exclusively via metal layers, as is the norm in a modern design. On the other hand, off-chip, we route signals via impedance-controlled coaxial or microstrip lines, or via optical fiber, and these media typically do exhibit propagation velocities of 0.6 to 0.8 c. Therefore, off-chip, differences in physical propagation distances are the dominant source of skew, while on-chip, it is imbalances in driver loads that are the most common source of skew. In on-chip cases in which wire diffusion delays and lumped capacitive effects are both significant, a difference in line length can also result in skew due to a different total wiring capacitance. In addition, equal length lines that go through different metallization layers or through polysilicon links will have different delays due to different levels of capacitive coupling to Vss and different series resistances, especially in the case of polysilicon links. Accordingly, an important principal to simplify clock net design is to aim for buffering levels and fanouts that yield isochronic conditions for the passive wiring nets between buffered points on the clock net. This simplifies skew control in clock net design because attention then only need be paid to balancing loads on each buffer and to matching the number of buffers in each clock path. The alternative, in which passive wiring nets are not isochronic, requires detailed delay modeling of each wire path, taking into account the actual routing, the R0C0 of the wire type, the temperature, and the exact position of each lumped load on the wiring path. The important concept, however, is that by the choice of metal layers, line widths, and/or loadings, one can establish formally defined isochronic conditions on some or all portions of a complete clock net, which, in its entirety, is far too large to be isochronic. When fully isochronic subregions (such as a wide clock trunk) can be established, or even when a defined region is not isochronic but has delay that is simply and reliably predicted from position (such as on a clock ring), the remaining clock net layout and skew control problem is simplified, design risk is lowered, and pre-and postlayout simulations are more consistent because final routing of clock paths from these reference regions is shortened and overall uncertainty reduced. We shall see and use this principle in analyzing the popular clock distribution schemes that follow. The skew that intrinsically arises from differences in RC time constants of either lines or gate loads is aggravated by threshold variations in buffers and clocked loads due to minute differences in electronic parameters and lithographic variation in line widths and lengths at different devices. Time-constant and threshold effects interact to give a worst-case skew, which is the difference between the time at which the voltage response of line with the slowest time constant, τmax, crosses the threshold of the logic element with the highest threshold, VTmax , until switching of the device with the lowest threshold driven by the line with fastest RC time constant. Taking the difference of the earliest and latest switching times we have [32]:  V  δ = τ min ln 1 − T min  − τ VDD  

max

 V  ln 1 − T min  VDD  

(61.4)

Equation (61.4) implies that a clock system design in which buffered electrical segments of the clock net have 10% variation in τ about τnom, and 10% variation of VT about VDD /2, will have an estimated skew of at least 17% of τnom. Single-Phase Clocking Clocks ultimately always drive a storage register or latch of some type. The form of clock signal(s) required in a system therefore depends on the type of latch or flip flop element used and on properties of the combinational logic circuits used. True single-phase clocking is the most complex clocking principles with which to design systems, and has traditionally not been used, although recent work has assessed some truly single phase logic families [2]. The reason for caution with single-phase clocking is that invalid states may be passed to the output in two ways, as shown in Fig. 61.34(a) if the combinational logic (CL) delay is less than Th (i.e., too fast) or (b) the CL delay is greater than TC – tcharge (i.e., too slow). In other words, a two-sided (min and max) constraint on logic path delay exists for single phase clocking [27]. This means that although attractive to minimize total interconnect, buffer counts, and interphase skew © 2003 by CRC Press LLC

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Combinational logic

Inputs Cin Present state

Outputs

Next state

Ron Clock

Clock TH TC Outputs / Next state

tcharge

TCL Tcharge < TH < TCLmax

TCLmin

< Tc - tcharge

FIGURE 61.34 In single-phase clocking the combinational logic, path must be neither too slow nor too fast.

is avoided, truly single-phase clocking involves a greater design risk and timing analysis complexity. Because of this, the most common overall clocking scheme is single-phase clock distribution with local generation of a two-phase clock. Two-Phase Clocking With two nonoverlapping clock phases, we can eliminate one of the risks of single-phase clocking, that of a logic path being too fast. On the first phase the input is made transparent and allowed to affect the CL, charging the inputs through Ron Cin in time tcharge . During this time, the CL outputs are isolated from the input latch. On the second phase, the new CL output values are stored by the second phase latch while the input latch is opaque, isolating inputs from the new values until the next phase one clock time. A nonoverlapping period between phases ensures that at no time does direct transparency occur from input to output. With two-phase nonoverlapping clocks, as shown in Fig. 61.35(a), we need to ensure only that the maximum delay in the CL is less than TC – tcharge – T3 – tpreset. It is essential that the nonoverlapping interval, T2, be greater than zero, but T3 can be arbitrarily short. When present, however, T3 acts as an extra timing margin against skew. It is obviously desirable to make T2 as small as possible, but we can do so only when distributing twophase clock directly if the interphase skew is less than T2. In the worst case, the interphase skew may be twice the skew of each of the two clock phase nets individually. Skew, therefore, necessitates at least a 1:1 derating in speed for two-phase clocking in addition to the basic loss of clock cycle time for logic settling, to ensure correct operation of storage devices. If skews in the two clock phase nets are uncorrelated, however, the extra penalty could be as high as 2: 1. Every nanosecond of skew in the clock net for each phase then not only reduces the basic critical path logic timing margin by 1 ns, but also adds 2 ns to the T2 requirement. Therefore, in high-performance systems we have quite an incentive to distribute a single clock phase throughout the design and accept the extra logic required to generate two-phase clocks locally at each device (or small group of similar devices) that requires them. © 2003 by CRC Press LLC

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Inputs

Present state

(a)

Outputs

Combinational logic

Cin

Next state

Ron ϕ1

ϕ2

Clock

Tϕ1 Outputs/Next state

tcharge < Tϕ1

Tϕ2

T2 > o

T3

T2

TCLmax

Tc

TCL

< Tc - tcharge - T3 - tpreset

tpreset

tcharge φ2E

(b) φ

Cboot φ1

φ2

φ2

Vref φ 1 φ1

M1 M2

FIGURE 61.35 (a) With nonoverlapping two-phase clocks, no lower limit exists on the combinational logic delay. (b) Generator for two-phase nonoverlapping clock and buffer circuit to ensure nonoverlap period. Source: (b) [Glasser and Dobberpuhl, 1985], p. 349.

Two-Phase Clock Generator Circuit The canonical form of circuit to generate the local two-phase nonoverlapping clocks from a single phase clock is shown in Fig. 61.35(b). The feedback of ϕ2 into NOR 1 ensures that ϕ2 must be low before ϕ1 can go high after the single-phase ϕin input has gone low, and vice versa. A special clock buffer circuit is shown in Fig. 61.35(b), which helps ensure that a period of nonoverlap exists in the presence of the threshold variations in the driven loads [12]. It does this by using transistor M1 to clamp the ϕ2 output low until far into the fall of ϕ1. ϕ2 is held low until ϕ1 has fallen below (Vref – Vthresh ) to finally cut off M1. Vref might be set at 2 V in a 5-V process, thereby ensuring that ϕ1 is well below the logic threshold of all clocked loads before ϕ2 begins to rise, while at the same time minimizing but guaranteeing the existence of a nonoverlap period, which is lost processing time. Multiple-Phase Overlapping Clocks Generating and/or distributing nonoverlapping clocks with a minimal T2 can be quite difficult in large systems. An alternative is to define three or more primary functional logic steps and use a similar number © 2003 by CRC Press LLC

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φ1

TO φ1 φ2 φ3

B

TS

φ2

A TP C φ3

FIGURE 61.36 Principle of multiphase clocking. Outputs are isolated from inputs by other stages of nonactive logic even though any two active clock waveforms may overlap. Source: [Glasser and Dobberpuhl], 1985, p. 352.

of overlapping clock phases. In this case, the multiple stages of clocking removes the need for the guaranteed nonoverlap period in two-phase clocking. Let us consider three-phase overlapping clocking. The principles generalize to any higher number of phases. In three-phase clocking, the middle phase can be thought of as providing the nonoverlap time, which ensures time isolation between input and output activation for the module enabled on each clock phase. In fact, each phase plays a similar isolating role with respect to operations performed on its adjacent phases. Figure 61.36 illustrates the concept. The number of phases and the role for each phase typically reflects some natural cycle or step sequence of the basic system being designed; for example: bus input, add to accumulator, bus output. In WSI systems, in which uncertainty in clock delays, circuit speeds, and interconnect impedances may be high [10], overlapping clock logic can give high tolerance to clock skew, and is compatible with self-timing in selected subcircuits. Three-phase overlapping clocking has a distinct advantage: no hazard exists unless all three clock phases overlap in time. In the presence of severe clock skew, this can be a major advantage. Although called overlapping clocks, the circuits still function if successive phases do not actually overlap, although speed is sacrificed if overlap is lost. Overlapping Clock Phase Generator Figure 61.37 illustrates a circuit for generating three-phase overlapping clocks. Phase overlap is ensured because it is the onset of each phase that kills its predecessor. A Johnston counter comprised of three static D-flip flops generates the phase-enabling signals which sequence the actual generator stage, which is comprised of the three cross-coupled NOR gates. A deliberately limited positive-going drive ability of the enable input ensures that the Johnston counter exercises underlying rate and sequence control, while the output waveforms are determined by the interactions between the actual clock phase signals. While the enable inputs to each NOR are logically sufficient to drive the output high when the other input is low, they are arranged not to be able to drive the NOR output low on their own when the enable signal returns high. The output of phase i therefore stays high after its own enable signal has disappeared (gone high) until the phase i + 1 output is also high in response to the low-going phase i + 1 enable. Figure 61.37 shows this logic and a NORing clock buffer circuit in which the phase i + 1 signal is necessary to assist in returning the phase i output to zero. Clocking Latches A latch is a storage element which is level sensitive to the clock waveform. The latch output conforms to the input that is present while the clock waveform is at its active level for that latch, and then continues to hold that value when the clock level falls below the active level. Latches have setup and hold time requirements analogous to those in the flip flops that follow. Circuit designs for high and low active latches are given in [31]. By combining latches of opposite active polarity, with logic between the stages, there can be two logic operations per clock period. In this type of operation, however, skew adds to the needed clock period as usual, but in addition any imbalance in the clock duty cycle requires a further © 2003 by CRC Press LLC

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− φ1E

φ1

φ2

− φ2E

−φ 3E

− φ2E

φ2

φ3

φ1

Enable signals

φ3 (a)

(b) φ C

C D

Q

D

C Q

D

Q

−φ 3E − φ2E − φ 1E

(c)

FIGURE 61.37 Three-phase clock generator logic and buffer design to ensure overlap. Source: [Glasser and Dob­ berpuhl], 1985, (a) p. 348, (b), (c) p. 354.

margin because the minimum duty cycle half-width must remain greater than the worst-case logic delay. The clock edges also must be kept sharp enough that transparency never occurs between two successive latches working on opposite clock phases simultaneously, or that some minimum logic delay always exists between latches that exceeds the possible overlap time. The DEC ALPHA microprocessor was an example of a two-phase latch machine in which both phases drive latches that are active in the respective phases permitting logic evaluation twice per cycle. This is one case in which to control the very high transistor count, two-phase clock is distributed globally rather than generated at each module. The entire clock net on each phase is driven from a single large buffer placed at the center of the die where a PLL is also fabricated to advance the on-chip clocking phase relative to external bus timing, thereby compensating for buffer delay. Two principles for maintaining 50 % clock duty cycle in a latch machine are (1) whenever generating or phase-locking to a system clock, do so at twice the rate needed, then (frequency) divide by two. This results in 50/50 clock waveform, regardless of the original clock source waveform. (2) When repeatedly buffering clock in a chain, or when distributing clock through a hierarchy of clock buffers, use inverting clock buffers at each stage. Inverting the clock at every buffering stage inherently counteracts the effects of different rise and fall times in buffers. Otherwise, these can accumulate to extend or shorten the ON period of the clock waveform. For example, if a noninverting buffer has greater fall time than rise time, a clock path transiting several of these buffers will develop a broadened ON period. This effect is selfcompensating in a chain of inverting buffers. Clocking Flip Flops Flip flops are more complex storage circuits than latches, but have no dependency on clock duty cycle because they are sensitive only during an active edge of the clock waveform. A rising edge D-flip flop (for instance) updates its output to match its D input on the rising edge of the clock waveform. The Q output retains the updated value thereafter, regardless of further changes in the input or clock waveform (with the exception of another rising clock transition). A latch is a more fundamental circuit element than the D-flip flop in that edge-triggered behavior is attained only by implementing two latches and © 2003 by CRC Press LLC

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L1 (MASTER)

L2 (SLAVE)

− Q

D

Q CLK I2

I1

(a) tlogic

Q1

D1

CL

Q2

D2

tsetup CLK

tflip-flop

CLK′ tskew

CLK CLK′ tsetup

thold

D1 tflip-flop Q1

tlogic tsetup

D2 tskew tcycle (b)

FIGURE 61.38 (a) Two-phase latch structure of a typical CMOS positive edge-triggered D flip flop. (b) Setup, hold, and delay times for a D-flip showing how skew is equivalent to a shorter clock period and threatens setup time margin. Source: [Bakoglu 1990], p. 345.

generating a pair of two-phase nonoverlapping clock pulses internally, in response to the active clock transition at the edge-triggered input. For instance, Fig. 61.38 shows a typical D-flip flop in which inverters I1 and I2 generate the internal two-phase clock signals for level-sensitive latches L1 and L2. In specialized applications, it may be advan­ tageous to design a custom module within which multiphase clocks are distributed directly, without incurring greatly increased skew problems. For example, an error-correcting codec ASIC prototype for 45 Mb/s digital communications includes a 2613 stage tapped delay line comprised of seven-gate single-phase

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1889

D-flip flop modules. The use of single-phase clock flip flops in this context is relatively expensive, but appropriate for fast validation of the system design. For cost- and power-reduced production in volume, a more detailed latch-based design using directly distributed two-phase nonoverlapping clocks may be worthwhile. In general, while it is most common to conduct system design based on the single-phase clocking model, two-phase or multiphase clocking may be advantageous within specialized substructures. Although edge triggered, a minimum clock pulse width is still typically required to deliver enough switching energy on the clock line. For correct operation (specifically, to avoid uncertain outputs due to metastability) of an edge-triggered flip flop, data must be stable at the input(s) for a minimum setup time before the clock edge, and the data must remain stable at the input for the hold time, after the clock edge. The time until the D-flip flop output is valid after the clock edge occurs is the clock-to-Q delay. For hazard-free transfer of data from one stage to another with D-flip flops, without assuming a minimum logic delay constraint between stages, the clock-to-Q delay must exceed the hold time. Typical values for a range of D-flip flop types in a 1.5-µm CMOS process are tsetup = 0.8 to 1.5 ns, thold = 0.2 to 0.4 ns, and tclk-Q = 1.3 to 3.5 ns for Q output fanouts of 1 to 16, respectively. With the extra input logic delays in a JK flip flop, many JK flip flop cell implementations exhibit thold = 0.0 ns. By comparing magnitudes of typical setup and hold time requirements, it is apparent that skew is more likely to cause a setup time violation on critical delay logic paths than it is to result in a hold time violation. Role of Clocks in Dynamic Logic Clock signals are also used to implement a variety of logic gate functions in a dynamic circuit style, i.e., based on short-term charge storage, not static logic. This typically involves precharging on one phase and logic evaluation steered by the inputs on the second phase. The “Domino” logic approach combines a dynamic NMOS gate with a static CMOS buffer [8]. In “NORA” (no-race), logic dynamic logic blocks are combined with clocked CMOS latch stages. A variety of other dynamic logic circuits, using up to four clock signals to structure the precharge and to evaluate timing, are covered by [12] and [31]. In all of these gate level circuit implementations, the clocking-related issues are ultimately manifestations of the basic principles already seen for two-phase clocking; i.e., of never simultaneously enabling a direct path from input (or precharge source) to output. These logic styles were developed to reduce transistor counts. However, modern designers will most often be faced with a greater challenge in managing systemlevel problems of skew in a single clock phase distributed to static register than the challenge of reducing transistor count. Synchronizers and Metastability Many systems need to sample external inputs which may be timed independently of the synchronous system clock, such as switch-based control inputs, keyboard states, or external process states in a realtime controller. The external state needs to be synchronized with the system time base for processing. Metastability leading to synchronizer failure is a fundamental possibility that can never be entirely eliminated. Figure 61.39 is a basic synchronizer circuit. Our concern is that it is possible for the synchronizer output to take an arbitrarily long time to settle to one or the other valid logic states if the input signal voltage is sampled in the intermediate voltage range, i.e., ViL < Vin (t) < ViH . In this range, it is possible to find the input voltage at a value that leaves the cross-coupled latches internal to a flip flop in an intermediate state, with insufficient positive feedback to snap the output to either high or low valid states. System noise or quantum fluctuation will ultimately perturb such a precarious balance point and the output runs to one direction or the other, but it can take an arbitrarily long time for the synchronizer to reach a valid output state. As shown in Fig. 61.39(b), some flip flop outputs may also tend to rise at least halfway toward the positive output level before deciding the input was really a zero. This glitch may trigger edge-sensitive circuits following the synchronizer. Fortunately, the probability of an indeterminate latch output falls exponentially with the time T after sampling the possibility indeterminate input:

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SYNCHRONIZER ASYNCHRONOUS INPUT

DQ

SYNCHRONIZED SIGNAL

CLK

CLK

D

METASTABLE STATE

Q POSSIBLE OUTPUTS SEES A “1” ASYNCHRONOUS INPUT

SYNCHRONIZER

DQ

DQ

CLK

CLK

METASTABLE

DQ SEES A “0”

CLK

(a)

Data Clock

1V Q output

2 ns/div (b)

FIGURE 61.39 (a) Metastability in a synchronizer circuit. Source: [Bakoglu 1990], p. 357. (b) Experimental illus­ tration of metastability in 74F/74 (TTL) D-flip flop showing output rise before indeterminate final response (10-s point accumulation). Source: [Johnson and Graham, 1993]. p. 130.

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P(t > T ) = fclk fin ∆e −T

τsw

(61.5)

where fclk is the synchronous sampling frequency, fin in the frequency of external transitions to be synchronized, ∆ is the time taken for the input voltage in transition to cross from ViL to ViH (or vice versa), and τsw is the time constant characterizing the bandwidth of the latch device. Having recognized the strict possibility of a metastable logic state resulting from synchronizer input, the designer can address the issue in several practical ways: 1. Use a high gain fast comparator to minimize ∆ by minimizing the voltage range ViL to ViH . 2. Ensure or specify fast transition in external sensors or other devices to be sampled, if design control extends to them. 3. If there is no real-time penalty from an additional clock period of input response delay, the synchronizing latch should be followed by one or two more identical synchronizer latch stages, thereby increasing T in (61.5) to reduce the chance of a metastable state being presented to internal circuitry to an acceptably low probability. The effect of input metastability on the system also should be analyzed for its impact. If it is extremely crucial to avoid a metastability hazard, then phase-locking the external system to the system clock may be considered, or if the system and external timebases are free running but well characterized (for example, in terms of a static frequency offset or known phase modulation), then the anticipated times of synchro­ nization hazard may be calculated and avoided or otherwise resolved. As a practical matter, the way in which design software handles metastability should be considered. Potentially metastable conditions should be flagged as a warning to the user, but not necessarily treated as a violation prohibited by the design environment. Some applications, particularly in VLSI for tele­ communications, need design support for plesiochronous (near-synchronous), phase-modulated, or jittered signal environments. This implies test vector support to represent clocks interacting through logic at slightly different long-term or instantaneous free-running frequencies with design and simulation rules that permit the metastable conditions inherent as such clocks walk relative to one another. Circuit simulations must be allowed to continue with a random value resulting from the simulated “synchronizer failure” to be useful in such applications. Controlled Introduction of Skew Skew is not necessarily all bad. In fact, from the viewpoint of the system power supply, and power- and grounded-related noise current surges, it is undesirable to have all logic transitions occurring exactly simultaneously. In a CMOS IC with 20 K register stages at 0.1 pF load each and a 1-ns clock rise time, 10 A of peak current can be drawn by the clock net. This can present a serious L dI/dt problem through power and ground pins and can even lead to electromigration problems for the metallic clock lines. Chip clocking strategies should take this into account early in the design by seeking ways to deliberately stagger or slightly disperse the timing of some modules with respect to others. Also, the system clock waveform may not necessarily need the fastest possible rise time. Consistent with avoiding slow-clock problems, and controlling threshold-related skew in buffers, the clock edge should not be made faster than this as an end in itself. Excessively fast clock edges clock edges only aggravate power and ground noise problems as well as ringing and potentially causing electromagnetic radiation problems in the chip-to-chip inter­ connect. These principles motivate the widely used 10 K ECL logic family, which is based on the muchfaster 100 K series with explicit measures to slow down the rise and fall times of the basic 100 K logic gates. When considering random skew, it may or may not be beneficial to pursue skew reduction below a certain level in the design. In the case of a microprocessor or a design in which the fastest possible IC speed is always useful skew reduction does mean a performance improvement. In some other applications, however, the clock speed is set by the application. For instance, a VLSI circuit for a telecommunications multiplexer may be required to operate at a standard line rate of 45 MHz. In this case there may be no

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premium for a design that can perform the same functions at a higher speed. A working design with skew of 5 to 7 ns (out of a 22-ns clock period) may then be more desirable than a functionally equivalent design with 0.5 ns skew because dI/dT effects are eased by distributing the total switching current over time in the former. This principle may be important in practice as automated clock synthesis tools become more widely used and effective at achieving low skew, possibly creating unnecessary system level noise and EMI emission problems. Future clock-related CAD tools should possibly aim to disperse clock timing at various loads while satisfying a target worst-case skew, rather than absolutely minimizing skew. Strictly speaking, skew can also be beneficial when allowed to build up in a controlled way in certain regular logic structures. For instance, by propagating clock in the opposite direction to data in a shift register, one enhances the effective setup time of the data transfer from register to register. In general, however, it is not feasible or advisable to try to design every clock path with a desired (non-simultaneous) clocking time at each register, taking into account the individual logic paths of signals leading each clocked latch input. Especially when designing larger systems mediated by CAD tools for placement, routing, and delay estimation, the most practical and low-risk approach is to consider any deviations from a common nominal clock time as undesired skew. Indeed, for any one latch, timing margin may be enhanced by the actual skew that arises, but with thousands of logic paths, it is impossible to analyze the relative data and clock timing for each latch. Only one instance in which the skew works against the assumed timing margin is enough to fail a design. Therefore, the “customized skew” approach is recom­ mended only for small and very high speed specialized circuit design. Clock Signal Manipulation As a matter of design discipline, some commercial ASIC and cell-based layout systems may prohibit a designer from directly gating or manipulating a clock signal. Any needed clock qualification is done through defined enable or reset inputs on register structures. As in software development, in which structured design disciplines have been developed, gating the clock may be riskier than its apparent efficiency warrants. In addition, clock gating within random logic designs can interfere with test pattern generation. The risk also exists of creating clock glitches or even logical lockups when clocked logic functions decode conditions that gap its own clock. On the other hand, in high performance and in large system-level designs, clock gating for power down and clock tuning may be unavoidable. Wagner [30] discusses clock pulse-width manipulation, defining four canonical subcircuits that can be used to “chop”, “shrink”, or “stretch” the clock waveform for either delay tuning or duty cycle main­ tenance. The effect of these circuits on the positive pulse portion of a clock waveform is shown in Fig. 61.40, where AND gates have delay da, OR gates have delay d0, inverters have delay di and the delay elements have delay D. Aside from a single gate delay, the chopper and stretchers leave the rising edge unaltered and tune the trailing edge. These can be used to maintain a balanced clock duty cycle or to tune the nonoverlap period in two-phase clocking. The shrinker delays the rising edge of the clock as might be helpful to specifically delay clocking a latch or a flip flop that is known to follow a particularly long logic path delay. This is not generally a preferred design approach, especially when manufacturing repeatability and temperature dependence of delay elements are considered. By clock gating, we mean selectively removing or masking active phases or edges from the clock signal at one or more latches. One valid reason to gate the clock in CMOS is to reduce power consumption. Many circuit designs possess large modules or subsystems which it makes sense to stop cycling in certain application states. Gating the clock off is therefore the simplest form of power management, because CMOS has negligible power dissipation in a static state. However, even for this simple use of clock gating, the main issue is avoiding glitches when gating the clock. Before gating any clock, the designer should see if gating can be avoided with an alternate design style. For example, if it is desired to hold the data on one register for a number of cycles while other registers on the same clock proceed, a preferred approach is to use a 2:1 mux at the register input. Rather than gate the clock, the mux is steered to select the register’s own output for those cycles in which gating would have occurred. Ultimately, if it is appropriate to gate out one or more clock pulses, a recommended way of doing so in rising edge active logic is to OR out the undesired clock edges, decoding the clock © 2003 by CRC Press LLC

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clock in Element A

1

clock in Element B

1

&

clock out

+

clock out

clock in Element C

&

clock out

clock in Element D

+

clock out

(a) elements positive pulse Input Clock W

0 CHOP (Element A)

D+di da W−D

SHRINK (Element C) STRETCH (Element D)

time

D+da W+D da

(b) effect on a positive pulse

FIGURE 61.40 Standard circuits for chopping, stretching, and shrinking a clock waveform to adjust duty cycle or timing margins. (Source: Adapted from [30], p. 15.)

gapping conditions on the same clock polarity as the one being qualified (see Fig. 61.41). A natural tendency seems to be to AND out the gapped clock edge and/or to decode the gapping condition on CLK , but these approaches are more apt to generate clock line glitch than the OR-based approach. In the AND approach the gating line returns high at the same time as the falling edge after the last-gapped active edge. In the case of minimum delay through the gapping logic the risk is that both AND inputs are momentarily above threshold. Minimizing Delay Relative to an External Clock In a large system skew can build up between clock and data at the system level, even if the clock is skewfree everywhere within the ICs because data paths through ICs can build up delay relative to the system clock. For instance, if an ECL or TTL system clock line is distributed to a large CMOS IC, then the system clock must be level shifted and a large clock buffer may be required in each IC to drive its internal clock net. The delay through the on-chip clock interface and buffer can mean that even if the chip timing is internally skew-free, the on-chip clock is significantly delayed relative to the external system timing. Short of using the phase-lock methods described later, a simple technique to minimize this form of systemlevel skew is either to retime chip outputs with a separate copy of the system clock that has not gone

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A

B C

CLK

A

C

B Gapping logic

FIGURE 61.41 OR-ing out a clock edge when clock gating is essential.

central clock buffer (or clock tree) “early clock”

system clock

outputs

IC

chip internal timing

inputs

FIGURE 61.42 The “early clock” technique for reducing chip delay relative to external system timing.

through the internal clock buffer, or, if electrically compatible, to use the external system clock to directly retime the output signals from each IC (Fig. 61.42). This is called the early clock concept. Note that this assumes an adequate timing margin exists in the final stage of internal logic to permit the relatively early sampling of logic states.

Clock Distribution Schemes Single-Driver Configurations Often a single on-chip clock buffer is the simplest and best approach to clock distribution. A single adequately sized clock buffer is typically located at the perimeter to drive the entire clock net of the chip, as shown in Fig. 61.43. This approach can also perform well in large systems if the clock is distributed in a low R0C0 routing layer, such as third-layer metal. The main advantage regarding skew is that no matter how the single-clock driver delays or otherwise responds to the external clock input, the output waveform is electrically common to all loads. No intervening buffers and no separate passive net segments © 2003 by CRC Press LLC

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CLK

VSS (a) VDD

CLK

VSS (b) VDD

FIGURE 61.43 Single clock buffer placed in the I–O perimeter with dedicated power, ground pins (a) branching from a medial point on die (current density on line to medial point may be high), (b) branching immediately (skew may be high).

develop skew. Moreover, if the global clock net comprises an electrically isochronic region (NCgate  l 2 RCwire ) in which clock loads are reasonably uniformly distributed, the clock net voltage rises virtually simultaneously at all points on the charging clock net, resulting in extremely low skew. Often this leads to lower skew than in a buffered clock fanout tree. There is also only one global clock wiring net, simplifying documentation. On the other hand, skew can be larger and more routing dependent with a single buffer (than with some following schemes) when clock routing lengths vary significantly and wiring capacitance and resistance are significant. In such cases an isochronic net is not an accurate model, and performance depends on the way clocked loads are distributed on arms branching from the medial clock node. It is possible for neighboring flip flops to be connected to the central driver via quite different path lengths, making prelayout simulation relatively uncertain and requiring considerable postlayout tuning. Another caution is that even if no actual skew is present because a single waveform is common to all loads, the rise time of the clock waveform may show considerable loading effects, so that threshold-dependent skew arises in the clocked loads. Finally, the potential for conducted switching noise problems is high with the single-buffer configuration because the entire clock net capacitance is charged in typically under 1 ns. Power supply decoupling and ground bound problems and even current density (electromigration limits) considerations may need to be given special attention if using this configuration. It is usually recom­ mended that the single clock buffer be physically adjacent to the clock input pin, and the clock pin should be flanked by dedicated power and ground pins that feed only the clock driver. This principle, which applies in general to clock input buffers in all clocking schemes, keeps the clock switching noise out of the core power and ground bus lines. Also, the delay through a large clock buffer may be considerable, so a lightly loaded “early clock” can be picked off from the buffer input and used to retime chip output registers, or a PLL may advance the phase to the internal clock buffer so as to align internal and external timing regardless of the buffer delay. © 2003 by CRC Press LLC

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An interesting central clock buffer design, which also has attributes of the clock trunk scheme which follows is reported in [9]. Here, the area for central clock driver fabrication is a strip across the center along one axis of the die. External clock is fed from one pin on the same axis as the buffer, and internal clock lines radiate systematically away from the central linear distributed buffer. Data flow is also highly structured and arranged to progress away from the central driver strip, further minimizing clock-to-data skew. Four-Quadrant Clocking Approaches In the quadrant-oriented approach, we may use up to four clock pads and four smaller clock drivers placed at the centers of the die edge, preferably also with dedicated power and ground from flanking pins. There may be one, two, or four external clock pins. Figure 61.44(a) shows a quadrant scheme tested in [24]. In Fig. 61.44(b), a single-pin quadrant-oriented scheme in 1-µm, two-layer metal CMOS achieved 0.6 ns skew among 400 registers. A four-pin quadrant approach was successfully used in [29] to develop a 90-MHz CMOS CPU. If more than one pin is used for clocking, pin count goes up but absolute delay through the clock buffers can be reduced. The maximum wiring RC delay on the internal clock net and the peak current and L dI/dt effects through any one pin and bonding wire inductance may all be reduced in this case. Total loads on each of the four internal clock nets should be well balanced and/or the drivers sized for the actual number of loads in each quadrant. In many cases, reduction of each clocked area to one fourth of the die area can result in isochronic regions for which no further design attention other than total load balancing is required for clock routing within each region. The quadrant approach can also reduce the clock routing problem when the clock shares only two metallization layers available for all signal routing. Two other considerations apply to the quadrant schemes: (1) external tracking to multiple clock pins should be laid out with delay balancing in mind; (2) skew should be particularly considered on data paths which must cross from quadrant to quadrant, bridging timing across clock subnetworks. Symmetric and Generalized Clock Buffer Trees A symmetric or regular clock buffer tree [Fig. 61.45(a)] has equal fanouts from buffers at the same level, equivalent (or isochronic) passive interconnect paths at each stage, identical buffer types at each level, and equal groups of loads at each leaf of the tree. This ideal can be approximated if loads are regularly distributed and layout and routing can be controlled to ensure equal interconnect delays from each buffer to its subtending buffers. The remaining skew will primarily be due to threshold variation in buffers and terminal loads. A more general view of the clock buffer tree that arises with irregular layouts and routing is that the buffer tree has unequal interconnect delays and differing numbers of loads at each buffer. Figure 61.45 (b) illustrates the electrical model of such a clock tree. (R and C values are all different.) The basic approach to skew control in such a generalized buffer tree is to size each buffer specifically for the individual loads it drives and the delay of the interconnect path to its input from the preceding level buffer. In practice, this means that generalized clock buffer trees may be the most handcrafted (and/or custom-tuned) of all designs, especially in a large system-level clock tree that extends down from a master clock source through multiple shelves, backplanes, connectors, circuit packs, and individual ICs. The system-level hierarchical clock tree design for the VAX 8800 is a good example described by Samaras [25]. Here, a two-phase clock was distributed to 20 large circuit packs over a 21-in. backplane with a global skew of 7.5 ns, for operation at about 50 MHz (37 % skew). Some basic methods and principles are, however, identifiable for designing generalized buffer trees so that it is not all just careful tuning and handcrafting: 1. Inverting buffers at each level will preserve clock duty cycle better than a tree of noninverting buffers. 2. Total delay (root to leaves) of the clock net is theoretically minimized when driving primarily capacitive loads, by a fanout ratio e = 2.718 … at each level of the tree [23]. In practice, this implies a fanout ratio of about n = 3, with appropriately sized buffers, if delay is to be minimized. However, n = 3 can lead to relatively deep trees of many buffers in which skew can build-up from threshold and time-constant variations as in (61.4). © 2003 by CRC Press LLC

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(a)

(b)

LOCAL NETS

LOCAL BUFFERS

LOCAL BUFFERS

LOCAL NETS

QUADRANT NETS

CLOCK PAD

INTERCONNECT SPLITTER

PAD DRIVER LOCAL LOCAL BUFFERS NETS

LOCAL BUFFERS

LOCAL NETS

QUADRANT NETS

FIGURE 61.44 Quadrant-oriented clock distribution schemes: (a) 4 pins, 2 parallel buffers per quadrant. Source: [Nigam and Keezer, 1993], (b) Single-pin quadrant scheme with 2 buffer levels. Source: [Boon et al., 1989].

3. If identical buffers are used within each level, then the design aim is to make sure that the load of further buffers and/or interconnect RC load is delay-equivalent for each buffer. Dummy loads may be required to balance out portions of the clock tree whose total fanout is not needed. At the end-nodes of the tree equal numbers of standard loads should be grouped together on each leaf node, within a locally isochronic region. © 2003 by CRC Press LLC

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Clock source

Every path traverses exactly three gates (a) FF

R1

C

FF

C

C1 A

R0

B

FF FF

R2 D

FF

D

A

C2

C0

FF FF FF

R3 FF FF

E

FF

C3

FF FF

C E

FF FF

(b)

FIGURE 61.45 (a) Idealized symmetric buffer clock tree. Source: [Johnson and Graham, 1993], p. 348. (b) Gener­ alized clock buffer tree where interconnects and loads are not identical.

4. If the tree is deep, the skew among members of one local clock group at the bottom of the tree may be considerably smaller than the skew than the skew between groups of clocked loads at different end-nodes of the tree. If the inter- and intragroup skews are separately characterized, however, logic path delays can be designed to take advantage of the low intragroup skew and to allow greater timing margin on intergroup paths [25]. 5. The choice of clock buffer type for use in any clock tree should take into account the effects of power supply sensitivity. For example, the bootstrapped clock buffer of Fig. 61.46(a) can provide a very sharp rise time, although with relatively high delay through the buffer. Sharp rise times minimize skew due to switching threshold variations in the following buffers or clocked loads. The output switching time of the bootstrapped clock buffer is, however, relatively sensitive to supply voltage. On the other hand, the phase correcting buffer of Fig. 61.46(b) is very tolerant to supply variations, but is not as fast in its output rise time. This leads to a mixed buffer strategy in which the bootstrapped buffer is used in the relatively small population of buffers in the first few stages of a clock tree. Here, special attention can be paid to ensuring well-equalized power voltages. The phase-correcting buffer is more appropriate in later stages, nearer the more numerous individual loads, among which on-chip or wafer supply levels may exhibit more IR voltage drop variation. © 2003 by CRC Press LLC

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���

����

��� �����

���

���

����

FIGURE 61.46 (a) Bootstrapped clock buffer for use in first level of a clock tree; (b) phase-correcting clock buffer for use deeper in clock tree. Source: [Fried 1986].

Algorithms for the generalized clock tree design problem are also emerging. The algorithm in [28] can generate a buffer design based on custom transistor sizing to drive each heterogeneous load, all with the same nominal delay. A still more general optimization approach is under development by Cirit [5]. The sizes of all buffers in the tree are jointly optimized with respect to unequal interconnect RC totals and unequal loads that each drives, as in Fig. 61.45(b). Thus, the minimum total tree delay is found for which all paths from root to leaf of the tree also have equal delay. The procedure is intended to be iterated along with placement and routing alternatives until a set of feasible buffer sizes and acceptable total delay is found. Clock Trunk Schemes The clock trunk concept is gaining popularity and is now supported within several CAD systems for CMOS processes with two or more metallization layers. Three variants of clock trunk structures are shown in Fig. 61.47. An input clock signal is buffered (its input pad is at the center of one side of the chip edge) and is routed either to the midpoint, or one or both ends of the internal clock “trunk”. The trunk itself is a metal line specially widened for low resistance, thereby making delay and the R0[Cload + C0] rise time particularly small on the trunk portion of the overall clock net. As long as the lumped capacitive loads (Cload ) dominate the trunk’s C0, the time constant of the trunk drops as it is widened. C0 can be kept particularly low by forming the trunk in third-layer metal. The idea is to size and drive the clock trunk so that an isochronic region is created down the middle of the die, reducing all remaining clock path distances to not more than half the die diameter and setting up a situation in which the final distribution of clock from the isochronic trunk to the loads is in line with one routing axis. This means

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First Layer Metal Main Trunk

Second Layer Metal

Tributary

Vd Vs

One Standard Load Wires of Equal Length

Vd Pa Vss

Clock Driver to be Placed in the Center of the Clocked Load Distribution Vd Vs Required

Die

Clock Input Die

Clock Input (b)

(a)

Vd Vss

I/O

Main_Buffer

Sub_Buffer

I/O

I/O

Vd Vss

Die

Clock Input

Wire of Equal Length (c)

I/O Cells

(d)

FIGURE 61.47 The clock trunk concept: (a) single-ended unbuffered clock trunk, (b) double-ended unbuffered, (c) buffered clock trunk, (d) clock trunk with shorted branch buffer outputs. Sources: (a)–(c): [LSI Logic 1992]. (d): [Saigo et al., 1990].

that branch routing from the trunk to loads can be exclusively contained within one metal layer and travel in a shortest direct line from trunk to load. This is highly desirable for processes in which all horizontal and vertical routing are dedicated to one metal layer or the other. Overall layout and routing is simplified and clock paths are predictable and uniform in routing and wiring type. If, however, the total fanout is very small, the wide metal trunk may add more to trunk capacitance than it decreases R0 in the R0[Cload + C0] product for the trunk. This is undesirable because for an isochronic trunk, we want C on the trunk to be dominated by its loads, not by the distributed capacitance of the trunk. In practice, © 2003 by CRC Press LLC

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therefore, the trunk scheme is typically recommended for fanouts of over 50. Below this, a single buffer scheme is recommended. By designing with the following principles for single-ended, double-ended, and buffered clock trunks, clock nets of up to 2000 fanouts can achieve < 1.5 ns skew in 1.0- or 0.7-µm CMOS gate array technology [21]. When the clock fanout is between 50 and 500 unit loads, a single-ended trunk scheme, as shown in Fig. 61.47(a) provides a good trade-off among skew, area, and delay. A single clock driver input buffer is used to drive the trunk line, which is typically realized by six first-layer metal lines in parallel with metal filled in. Clock trunk sizing for a given fanout must set a minimum width to take current density limits into account, given that all of the clock net current flows through the trunk if the tributaries are not buffered. Tributaries of nominally constant fanout branch out in second-layer metal. To the extent possible, macro-cells and hard-coded mega-cells should be laid out with the clock trunk in mind, ideally permitting the clock trunk to be located in the middle of the logic to which it fans out. The tributary branches may or may not be buffered with their own clock drivers, depending on the total number of loads to be driven. Buffering primarily has the effect of reducing overall delay, rise time, and total current density in the trunk, by allowing a smaller trunk driver. Form a purely skew-oriented view, however, it is better not to have the secondary drivers as long as the trunk is isochronic and the size and delay of the main driver is acceptable. When using local buffering, it is important that the branch loads on all tributaries be balanced, more so than when using an unbuffered trunk. Local buffering is, therefore, primarily a way of distributing the total buffering load so that no one buffer needs to be extremely large. For layout software simplicity, the main trunk may be constrained to use vertical (or horizontal) routing channels only. The main trunk (or each of possibly several main trunks) should be placed as close as possible to the centroid of area of all the loads which it drives. Layout or floorplanning software for commercial ASIC design can typically assist the designer in clock trunk placement by visualizing the spatial distribution of clock loads. When a design has between 500 and 2000 clock fanouts, a double-ended clock trunk, as in Fig. 61.47(b) or (c) is recommended. The double-ended clock drivers are internal buffers which use the I/O slots of two pins that will not be used externally thereafter. Both single-ended and double-ended clock trunk schemes use only one external clock input pin, with adjacent pins providing an AC ground and switching noise isolation by powering the drivers with dedicated Vss and Vdd pins for the clock buffers. In general, clock input pins should always be surrounded by nondriven pins to minimize the possibility of cross talk coupling into the clock waveform. Clock pins also should be chosen so that minimal internal routing is required between the predriver associated with the input pad and the clock trunk drivers. As a clock trunk design is laid out, the spike current draw from Vss due to simultaneous switching of large fanouts on the clock net should be assessed and considered in determining how many Vss pins are needed in a particular design. In the double-ended trunk scheme, some care must be taken to ensure that an equal-length path can be routed from the midpoint of the trunk, where the clock input branches to the trunk drivers at both ends of the clock trunk, and that a direct routing from the side of the die to the branch point at the center of the die is feasible. Particularly when preconfigured macro-cell function have been placed, the metallization layer needed to bring the clock predriver into the middle of the die may be blocked. This leads to the recommendation that the clock input pin be placed on the side of the die that is in line with the clock trunk [see Fig. 61.47(c)]. The line to the branch point and the two branch lines can then use the same metallization layer as the clock trunk and can be automatically provided for as part of the routing channel width reserved by the clock trunk layout software. The two double-ended arrangements will have a basic skew given by the (nontrunk) R0C0 delay across one half of the chip’s dimension (typically under 300 ps), plus skew due to any imbalance in buffer loads and thresholds. An advantage of the buffered clock trunk is that the capacitive load of the clock tree is distributed somewhat in both time and position across multiple buffer stages, reducing the current spikes occurring during a clock edge and their impact on ground bounce and injected power supply noise. On the other hand, a total of three or four buffer stages associated with this structure (for low skew in large © 2003 by CRC Press LLC

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TABLE 61.10 Fanouts of Clock Trunk Schemes in 1-µm CMOS Gate

Arrays (Maximum Number of Clock Loads Driven with 2000 >1500 >1200

Source: Clock Scheme for One Micron Technologies, Rev. 1.1, LSI Logic Appli­ cation Note, LSI Logic Corp., Aug. 1992.

applications) may cause high delay between the clock edge used to latch incoming and outgoing data on chip and the external system clock. Clock net fanouts achievable using the clock trunk scheme in commercial gate arrays are summarized in Table 61.10. In even larger dies with famous of over 3K flip flops, multiple symmetrically driven double-ended clock trunks can be established to control the maximum distance of any point from a clock trunk. For example, with two trunks placed one fourth of the die width in from the sides, no load is over one fourth the die diameter from a trunk, and the loading of branch buffers is half that required with one trunk. Branch lines from different trunks should not be connected together where they meet in the middle of the die. These points are far enough away in terms of delay from their common driving points that joining them could cause power-wasting buffer output fights. In a further variant on the buffered clock trunk, buffers have their ouputs ganged (i.e., shorted) by an additional vertical metal line parallel to the trunk, close to the buffer outputs. The effect of shorting the branch buffers is to equalize the propagation delay through the trunk and distribute the capacitance per buffer more uniformly. This has been found to reduce skew considerably if the branch buffers were not equally loaded and also reduced skew (although less so) in the balanced buffer case [26]. Clock Ring Configuration The clock ring approach shown in Fig. 61.48 combines aspects of the clock trunk, quadrant, and the single large buffer approaches to achieve a combination of moderately low skew, and moderately low delay without the possibly high routing-dependent skew of the pure single-buffer scheme. The ring approach also simplifies overall clock and signal routing conflicts in a two-layer metal process. The external clock is buffered at entry with a moderate- to large-scale buffer, which drives a clock ring that follows the die perimeter. The ring is not a widened trunk because typically less than 50 other buffers IC

clock buffer system clock

FIGURE 61.48 The clock ring concept. © 2003 by CRC Press LLC

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are driven off the ring, not the entire clock net. Therefore, with relatively low Cload on the ring, it is not widened. The extra capacitance of a widened ring would be relatively high (on a square die, the total ring length will be four times the length of a corresponding central trunk) and only increase skew and delay. The ring drives secondary buffers sized to drive balanced groups of flip flops in the core of the chip. The aim of the ring on a large die is not to create a wholly isochronic perimeter, although this could be approached by driving the ring at multiple symmetric locations. Rather, the ring establishes a relatively low-skew reference perimeter from which any interior clock load can be reached either by a purely vertical path or purely horizontal path (i.e., in a direct line of a single metal layer) no longer than one half the die size. The worst-case routing distance from the ring is the same as in the clock trunk scheme, but two thirds of all locations are within half that distance in the ring, whereas only one-half of all uniformly distributed loads are within half of the maximum distance of a central trunk. In practice, with good load balance on the secondary drivers, clock skew of 0.8 to 1.0 ns has been obtained in a designs of up to 30K gates. If the secondary drivers are well balanced, skew in this architecture will depend primarily on the R0C0 delay from the ring driving point to its far side, around the periphery, typically 0.8 ns for a die of 350 to 400 mil. Relatively low chip delay is obtained by using the clock signal on the ring as an “early clock” with which to time I/O latches. The ring is electrically closed as this helps distribute the subbuffer capacitance and equalize delays, especially if driven at two opposing points. H-Trees The H-Tree is an area-efficient regular structure most suited to clock distribution in systems in which the synchronized modules are identical in size and placed in regular array. Figure 61.49 illustrates a 256-module H-tree tested on a 4-in. wafer by Keezer and Jain [17]. The scheme balances the R0C0 delay through the clock network by geometric symmetry so that the delay is nominally constant from the root to any leaf node. Loads are clocked only at leaf nodes of the tree. The minimum feature size of the process can be assumed to set the line width of the H-tree at its leaf nodes and each preceding level has progressively wider lines to maintain constant current density and to minimize impedance mismatch effects (at wafer scale and above) when no branching buffers exist. The H-tree is driven by a buffer at its root and may or may not have additional buffers at branching points. ASIC manufacturers have been able to achieve skew below 500 ps at fanouts of > 5000 with experimental H-tree layouts in third-layer metal [22]. (VLSI Cells)

Transmission Lines 4.0 inch

Buffer

Primary Clock Input

FIGURE 61.49 The H-tree concept illustrated in the form of a 256-cell passive H-tree for Wafer-scale integration. Source: [Keezer and Jain, 1992].

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The H-tree approach is most practical only if an entire layer in a multilayer PCB or a third or fourth metallization layer in CMOS can be dedicated for H-tree clock distribution. Otherwise, the H-tree may encounter (or cause) a large number of routing blockages or require poly links which will disrupt the H-tree performance. In addition, many VLSI designs include memory cells or other hardcoded cells that are incompatible with the ideal symmetry of the H-tree. However, if a suitable layer is available for H-tree layout, it may be applied to random-logic designs by considering each leaf of the node as a clock supply point for all clocked loads within an isochronic region around each leaf node. The whole die is then tiled with overlapping isochronic regions, each fed from out of the plane by a leaf of the overlying H-tree. Each leaf of the H-tree might also use a variably sized buffer to drive the particular number of clocked loads of the random logic layout that fall in its particular leaf node zone. Kung and Gal-Ezer [18] have given an expression for the time constant of an H-tree, which charac­ terizes the total delay from root node to leaf: 2  τ H = 1.43 N 3  3 −  R0C0  N

(61.6)

where an N × N array of leaf nodes is drives. Absolute delay rises as N 3 for large N. This in itself does not limit the clocking speed because, at least theoretically, more than one clock pulse could be propagating toward the leaf nodes within the H-tree. As a practical matter, however, the delay of the H-tree expressed in (61.6) is essentially a rise time effect on the clock waveform. A slow rising edge out of the H-tree can lead to significant skew due to threshold variations in the leaf node buffers. These considerations apply to the on-chip context in which the H-tree clock network is dominated by RC diffusion delay effects. Equation (61.6) also describes an unbuffered H-tree. By placing buffers at selected levels of the overall tree, total propagation delay through the tree will increase, but the bandwidth of the tree may be preserved by effectively reducing N to the portions of the overall tree between buffers, in (61.6). In contrast to the rapid bandwidth fall-off on-chip, at the multi-chip module level of system integration an H-tree may be designed from an impedance-controlled transmission line standpoint to obtain very high clock band­ width. In experiments of this type, Bakoglu [3] has achieved 30 ps of skew at 2 GHz with a 16 leaf H-tree covering a 15 × 15 cm wafer area. In an H-tree the total clock path length doubles each time one moves up two levels from the leaf nodes toward the root. Based on this, Kugelmass and Steiglitz [19] have shown that given σb and σw as the standard deviation of buffer delay (if present) and wire delay, respectively, the total delay of an H-tree considering buffers and wires has variance:

(

)

σ 2 = σ b2 log 2 (N ) = σ 2w 2 N −1

(61.7)

and that the average case skew between any two leaf nodes is bounded by: E [skew ] = σ w 4

(N − 1) ln(N ))

(61.8)

where N is large and wire length effects dominate. Average case (or expected) skew is the maximum difference between clock times, averaged over many design trials, not the average clock time difference in any one design. Kugelmass and Steiglitz [19] also give results for the probability that a sample value of the skew exceeds the mean skew by a given factor in either an H-tree or a binary tree, based on assumptions that all wire length and buffer delay variables are independent and identically distributed: 2    2 a  P skew > E [skew ] + a ≤ 1 +  48 ( ln N ) π 2     E [skew ]    

(

© 2003 by CRC Press LLC

)

−1

(61.9)

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TABLE 61.11 Comparative Performance of Clock Distribution Networks (8 × 8 Array of Loads Clocked at 31 MHz and Constant Total Power, 650 mW) Scheme

Delay (ns)

Skew (ns)

Rise/Fall Time (ns)

3-level symmetric buffer tree Single buffer H-tree Clock trunk with branch buffers Clock trunk with ganged branch buffers 4-pin-quadrant scheme, 2 buffers per quadrant

7 15 13 14.2 4.3

3 ~0.0 4 2 1.3

12.5 38 14.2 16 9

Source: N. Nigam and D. C. Keezer, “A Comparative Study of Clock Distribution Approaches for WSI,” Proc. IEEE 1993 Int. Conf. WSI, pp. 243–251.

where a is the amount of time by which the mean skew is exceeded. These expressions may be used to estimate skew-limited production yield at a given target clock speed. Delay, Skew, and Rise Time Comparison The five clock distribution schemes described thus far were studied in a unified, experimental way by Nigam and Keezer [24] using HSPICE simulations. They compared each scheme on a 5-in. wafer holding an 8 × 8 grid of modules to be clocked. Each module presented at a total load of 2 pF and the interconnect R and C values were taken for a typical 2-µm double-metal CMOS process. Clock distribution lines were 10 µm wide for the buffer tree and the H-tree, except for its trunk, which was 40 µm. The clock trunk schemes used a 20-µm trunk width. All interconnect was modeled as distributed RC, with transmission line delay effects included. The results are tabulated in Table 61.11 and give an excellent overview of the relative characteristics of each method. The H-tree has essentially no skew, but has the highest delay and slowest clock edge, which can translate into skew due to threshold variations in the loads. The clock trunk has good skew and moderate delay. The best overall performance is achieved by the four-quadrant scheme, essentially by virtue of reducing the clocking area to one fourth of the overall size of the other clock networks. Balanced Binary Trees A balanced binary tree (BBT) is an unbuffered clock distribution tree in which each branch node has exactly two subtending nodes, and the delay from the root to all leaf nodes is made constant by placing branch points at the “balance point” of the two subtending trees from any node. Balanced binary trees are not simply clock buffer trees with fanouts of two. The significance of the BBT is that constant delay is achieved through multiple levels, without any buffers, and the BBT can be constructed by a fairly simple algorithm. Passive BBTs also may be used in practice to implement delay-equalized fanout net­ works between the active buffer levels of a larger buffered clock tree. The BBT concept should not be confused with the buffered clock tree concept in general, however. The key is that the generalized buffer clock tree does not have path delay equivalence if its buffers are removed, whereas the BBT has this property. The basic ideas and methods of generalized balanced tree synthesis are explained in [6]. The clock tree that results has two branches at every node. Clocked loads appear only at the leaves of the tree. The line lengths at each level can be different than those at other levels of the tree, and the two line segments that are children of any node also can be of unequal lengths. The key, however, is that at each branch the total distance from the branch point to any subtending leaf via one outgoing path is equal to that in the other outgoing direction. Figure 61.50 illustrates the basic procedure for BBT synthesis. The process works from the bottom up, by considering all leaf node positions, i.e., clock entry points for modules or isochronic local regions. Leaf nodes are subjected to a generalized matching or pairing process in which each node is paired with the other node closest to it in the Manhattan street length sense within the available routing channels. A first-level branch point is then defined at the midpoint on each line joining the paired leaf nodes. A © 2003 by CRC Press LLC

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FIGURE 61.50 BBT synthesis in an 8-terminal net. Solid dots are roots of subtrees in the previous level; hollow dots are roots of new subtrees computed at the current level. Source: Cong et al., 1991].

similar pairing of the first-level branch points then defines a new set of line segments, each of which has two leaf nodes symmetrically balanced at its ends. Second-level branch are then defined at the RC balance point on each line joining first-level branch points, and so on. Each iteration consists of finding the minimum path length matching of pairs of branch points from the previous iteration and defining the next set of branch points at the time-constant balance points on the line between just-matched, lowerlevel branch points. Assuming leaf nodes present equal loads, the first-level branch points are the midpoints of the pair-matching line segments. After that, the balance point for level i is the point on the line segment joining matched level (i – 1) branch points at which the total RC wiring time constants (simply total length if all wires and layers are identical) to the leaf nodes in the right and left directions are equal. This is repeated until only two branch points remain to be matched. A line is routed between them and driven by the clock signal at the final balance point, which defines the root of the BBT. Clock trees developed in this way are in one sense highly structured and symmetric in that the total delay from root to any leaf is nominally constant, like the H-tree. Unlike the H-tree, however, the actual layout is irregular, allowing the BBT to accommodate the actual placement of cells and modules and to cope with the limited and irregular routing channels available in designs that do not use a completely regular layout. Skew in BBTs has been considered theoretically and experimentally. Kugelmass and Steiglitz [19] showed that in a BBT with independent variations in the delay at each stage of the tree, with σ02 variance, the expected skew is fairly tightly bounded by: E [skew ] ≤

4σ 0 ln N 2 ln 2

(61.10)

where N is the number of leaf nodes of the tree. Using the previous expressions we can compare the H-tree to a BBT. The comparison shows that when the regular structure of an H-tree is feasible, it is of relative merit for large fanouts because the expected skew grows more slowly (O(N1/4(In N)1/2)) than the BBT tree in which expected skew grows as O(ln N). For comparison, assuming 10,000 leaf nodes and the same σw per unit wiring length, the expected skew of the H-tree is about one half that expected of the BBT. This outcome is primarily because the BBT must be deeper (have more levels) than the H-tree for the same fanout. © 2003 by CRC Press LLC

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Experimentally, Cong et al. [6] produced a large sample trials of 16- and 32-node BBT clock trees, synthesized on a 1000 × 1000 grid. It was shows that the BBT resulted in less than 2% of the skew from a corresponding minimum spanning tree (MST) for clock distribution to the same loads, even though the BBT had 24 to 77% more total routing length than the MST. The MST benchmark characterizes the skew that would typically result if the clock was routed as an ordinary signal net, with no special concern about skew. An example of balanced clock tree synthesis supported by a gate array provider is [22], in combination with a three-level clock buffer tree hierarchy. Skew of < 500 ps is achieved in 0.5 µm designs of up to 13,440 clocked loads. By using appropriately sized buffers and wire width at each level of the balanced tree, clock rise time is typically 0.8 to 0.9 ns at the terminal nodes. The clock tree compiler is invoked after floorplanning. The compiler takes into account the resistance and capacitance of different wire types, the length and width of wires, and the input capacitance of clock pins and buffers. Up to three active buffering levels can be used, with fanouts of up to 64, 14, and 15, respectively, from buffers at each level. The fanout subnet driven by each buffer is laid out as a (passive) BBT, so that the leaves of one balanced tree are the buffers that act as the roots of further passive binary balanced subtrees driven by the next buffering level. At the lowest level, local buffers each drive up to 15 loads via a final four-stage passive BBT. Clocking Schemes Involving Phase-Locked Loops A PLL is a negative-feedback control system in which the phase (and, implicitly, frequency) of a voltagecontrolled oscillator (VCO) or phase shifter is brought into alignment, or to a predefined static phase offset, with respect to the phase of a periodic reference signal. The application of PLLs is most often to control skew and clock delay problems primarily at the multichip and interboard levels of system design. Figure 61.51(a) shows how a PLL can be used to lock the on-chip clock phase at a selected point onchip, to an external phase reference. Figure 61.51(b) shows the mid-trunk phase on a single-ended clock trunk being made to match the external phase reference. Here, the feedback line from the middle of the trunk to the PLL input is assumed to have negligible delay in itself because it is a metal line with only one standard load. Similarly, in the double-ended clock trunk scheme, the sense line can be connected one fourth of the way along the clock trunk. This will lock the internal system clock to the reference timing at two points on the clock trunk, as shown in Fig. 61.51(c), reducing overall skew to one fourth of that in the single-ended clock trunk scheme. The phase-sense line needs to be connected to the clock trunk at only one point because, by symmetry, the corresponding point from the other driver is similarly phase locked. In general, when the phase-sense line has negligible delay, the clock phase at the sense point is driven into lock with the reference phase. Thus, in generating clock signals we can null out the delays of large buffers or drivers in the output circuits as well as their process and temperature-dependent variations, and, in general, coordinate clock and data phases at the inputs to another chip at any remote point by bringing the phase-sense line back from the actual point where the phase-controlled relationship is desired. In this way even the delay of an off-chip driver can be cancelled out by including it within the PLL feedback loop. If delay in the phase-sensing feedback path is not negligible, then its effect is to advance the phase at the desired control point. The feedback delay can be compensated by a matching delay in the forward path from the VCO to the phase-sensing point, or at the PLL input. An inverter in the feedback signal path is also a convenient way to cause a 180º phase shift between referenced and VCO without requiring any loop delay. With the addition of frequency divider (divide by N) in the feedback path, as in Fig. 61.51(d), the VCO operates at N times the frequency of the reference clock input. For N = 2n frequency multiplication, the feedback divider can be a simple ripple counter of n toggle flip flop stages. For other multipliers, a synchronous counter is usually used. The delay-matching element at the PLL phase detector input compensates for delay from the feedback path divider. On-chip frequency multiplication can ease a number of system-level design problems. The overall system clock rate need not be equal to that of the fastest chip in the system. Transmission line effects across the relatively long distances of PCBs or © 2003 by CRC Press LLC

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clock chip

clock pad

PLL

clock route

dclk output pad dclk + dpad (a) Internal clock driver SYSTEM CLOCK

×

PLL

Clock Trunk

vco output (b) Internal clock driver

Delay matching SYSTEM CLOCK

D

×

PLL

Clock Trunk

vco output ÷N (c)

SYSTEM CLOCK

VREF

CKOUT PLL

×

CKIN × Feedback Clock

(d)

FIGURE 61.51 PLLs for skew and delay control: (a) canceling internal and clock net delay, (b) halving the skew in a single-ended clock trunk, (c) reducing double-ended clock trunk skew to one-fourth of the single-ended trunk, (d) one-chip frequency multiplication. Sources (a): [Weste and Eshraghian, 1993], p. 335, (b)–(d): LSI Logic Corp., Phase-Locked Loop Application Note, Nov. 1991.

backplanes can be reduced by operating at a lower clock frequency outside of the system ICs. The lower frequency of system reference distribution may also reduce power, and usually assists in meeting radiated emission specifications for electronic equipment. Because a PLL regenerates the clock in each IC, a considerable amount of clock edge slew rate control can be used on the external system clock, further © 2003 by CRC Press LLC

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easing EMI and power supply switching noise problems. The difficulty of retaining clock waveform integrity getting on-and off-chip at high frequencies through inductive packaging and bonding leads is also eased for the same reason. PLLs for CMOS A block diagram of a PLL is shown in Fig. 61.52(a). The VCO exhibits a positive monotonic frequency of oscillation in response to a control voltage, characterized by the slope of its frequency vs. voltage curve. The loop filter, H(f ), is of a general low-pass characteristic, often of an all-poles design to avoid any jitter peaking (or AC gain) in the closed loop transfer function of the PLL. The loop filter must provide a DC coupled path between the phase detector and VCO. The phase (and/or frequency) detector compares the VCO output phase to the input reference phase and generates an output signal that is either of a DC nature or has a DC component that is proportional to the phase difference between the reference and feedback signal. The phase detector is characterized by the rate of change in the DC component of its output vs. phase input difference in volts/radian. A phase detector that is commonly used because of its all-digital nature and suitability for CMOS integration is Gardner’s phase-frequency detector (PFD) [11] with charge pump outputs. The PFD produces an output that goes toward VDD or VSS in the presence of a negative or positive frequency offset, respectively, thereby slewing the VCO toward the lock frequency. Once in frequency lock, the PFD produces pump up/pump down signals that vary in proportion to the time difference between reference and feedback clock edges at the PFD input. These pulse-width modulated signals drive a charge pump with a tristate buffer arrangement to either hold, bleed off, or supply charge to a capacitive storage element (i.e., the loop filter), thereby adjusting (and filtering) the voltage on the VCO control node to minimize the phase difference at the phase detector inputs. Ön

U Phase Detector

D

Charge Pump

Filter

VCO

n

× fin

reference clock (fin) (a)

P1

P2

Pn

fvco

control voltage

N1

N2

Nn

odd number of stages (b)

tin

tout

= tin + ∆t

control voltage

FIGURE 61.52 CMOS PLL circuits: (a) basic PLL block diagram, (b) CMOS VCO based on current starved inverters, (c) VCDL. Source: [Weste and Eshraghian, 1993], p. 336.

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For CMOS clocking system applications, the VCO is usually a form of a stable multivibrator in which the switching speed dependence of a CMOS inverter on its n-transistor pulldown current is exploited, as shown in Fig. 61.52(b). The VCO control voltage regulates the current flow in, and hence the speed of, each inverter stage through the extra n-transistor stage added to each inverter. Any odd number of such stages connected in a loop will oscillate, but now the relaxation period is voltage controlled. Weste and Eshragian [31] describe a 13-stage “current-starved inverter” VCO based on this approach. A related VCO design is based on varying the load capacitance seen by each inverter (in a chain of inverters) by applying the VCO control voltage to an n-MOSFET in series with the gate of another transistor configured as a capacitive load [16]. An on-chip RC loop filter can also be constructed from a CMOS transmission gate biased as a resistor and MOS gates used as capacitors (source and drain both connected to VSS) [31]. If frequency multiplication is desired, a PLL with a true VCO is required. Otherwise, many PLL applications can use a voltage-controlled delay line (VCDL) in conjunction with a “raw-clock” input signal, as in Fig. 61.52(c). All the phase-lock feedback principles are the same, except we phase-shift the raw-clock input as required, rather than controlling the VCO oscillation phase. This eliminates the risk of the PLL ever failing to lock-in and may be simpler to fabricate. On the other hand, system design must take into account a more limited range of phase-shifting ability (a full half-cycle of phase control range may require a lot of delay stages) and to make sure initial delays are nominally centered within the positive-only delay control range of the VCDL. Another more subtle point is that while a VCO introduces a perfect integrator (1/s term) in the PLL closed loop response, a VCDL does not. A VCDL, therefore, should not be simply substituted for a VCO without revisiting the closed loop response characteristics for noise bandwidth and possible jitter peaking. Special power, grounding, and testing considerations apply when a PLL is used. A PLL is basically a linear circuit, so noise is especially important. Particularly when a frequency multiplying PLL is used, the VCO power supply should be well decoupled from system noise, and the input phase reference should be highly stable, as the PLL output clock will have N times the reference’s phase noise. Noise voltages coupled into the analog PFD output and LPF signal path are similarly converted into phase noise that is N times worse than in a × 1 PLL. Leadless on-chip decoupling capacitors are recommended as are dedicated power and ground pins for the PLL. The R and C components for the loop filter are often offchip. In this case it is important that they are connected (depending on the H(s) configuration) to the same analog ground reference as the VCO and PFD. The VCO output, or a divided down version of it, should be brought to an external pin for lock-in validation and as an aid in possible global system clock tuning. For testability, several other separate pins are typically required for independent access to input and output of the PFD, LPF, and VCO each. An on-chip PLL can require up to six or more pinouts. Anceau’s PLL Scheme Anceau [1] developed a PLL-based approach for large systems in which modules are well-defined, relatively independent, and could be entirely self-timed if not for the need to avoid metastability in communication with other modules. Anceau recognized two natural system scales which are isochronic below different maximum frequencies. One is a global region encompassing the entire system, with a clock period determined by propagation distance delays, or, on-chip, by RC diffusion delays. The isoch­ ronic rate for this scale defines a slower clock rate for a system-wide communication bus. The second type of clocking region is smaller local regions which can run at full speed and are characterized by critical logic path delays and lumped capacitive loads within modules, not distance-dependent delays. Each smaller region will be free to operate in an almost self-timed mode. The clocking style within each module (e.g., logic type and number of clock phases) can be as appropriate for the individual modules. Skew at the highest clock speeds in the system need be considered only within each module, except that timing must be controlled when reading the common data bus to avoid metastability. This is done by reference to the active edge of the slower-rate communications clock (comm_clk), formed by dividing down the master module clock frequency. The rising edge of comm_clk strobes the enabled driver data onto the bus. All other nondriving modules in the comm_clk cycle read the bus on an internal clock edge that is kept away in time form this transition in comm_clk, for © 2003 by CRC Press LLC

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BROADCASTED MODULE CLOCK

CLOCK GENERATOR

PLL DIVIDER

PLL

PLL

1/

FUNCTIONAL MODULES

N

COMMUNICATION INTERFACES COMMUNICATION CLOCK

COMMUNICATION BUS

COMMUNICATION MECHANISM (a)

(i) comm

clock

(ii) bus

data

(iii) module

clock

read bus

(iv) read enable pulse

(must

precede read)

metastability margin maintained by phase locking (iii) to (i) (b)

FIGURE 61.53 Anceau’s scheme for metastability avoidance: (a) system architecture, (b) interface timing (Source: Adapted from [1].)

metastability avoidance. Figure 61.53 illustrates the overall scheme. A PLL phase locks the module clock at a predefined angle relative to the comm_clk, thus keeping the raw module clock away from the transition times in the lower rate communication clock. The read timing is then safe because it is always preceded by the comm_clk transition on which new date were strobed to the bus. A monostable triggered by the comm_clk edge can be used inside each module as a delay generator to prohibit any bus read in the metastable region. This way, as long as modules write to the bus only on the comm_clk edge, other modules that read the bus will never do so at a moment when the bus data are still in transition. Grover’s Interval-Halving PLL Scheme A novel PLL-based approach to clock distribution in “electrically” large systems can synchronize all clocks in a large system on a single clock line [13, 14]. In this scheme any number of nonisochronic points arbitrarily located on a single- or double-conductor reference line independently derive clock that is in absolute phase-lock to a common system-wide reference time. The central principle is that the time between appearances of an isolated pulse traveling down and back on a reference line is the same regardless of the point of observation, as shown in Fig. 61.54(a). This figure plots the trajectory in space-time of an isolated pulse that travels from a site at one end of a line and is returned at the end of the line to its © 2003 by CRC Press LLC

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SITE A

SITE K

SITE X

INJECTOR TRANSMISSION LINE SPACE

X=D

X SPACE-TIME TRAJECTORY OF PROJECTED REFERENCE PULSE

t1 TIME

tA 1/ tA 2

VIEW AT SITE A

tK

TIME

1/ tK 2

VIEW AT SITE K VIEW AT SITE X

tX

TIME TIME

1/ tX 2

(a) VCC VCC

R1

FF1

A

J Q K CLK

TG1 VCO

ref. line

TG2

PHASE-ALIGNED CLOCK TO APPLICATIONS

C1

R2 Q ~ +N Q (b) IHPLL

clock

forward S

A

Injector

Q

IHPLL

clock

R

return (c)

(d)

FIGURE 61.54 Grover’s interval-having clock distribution scheme: (a) interval-having reference-time principle, (b) IHPLL circuit for single-line skew-compensated clock distribution, (c) phase detector for 2-line operation, (d) driving two lines rather than one looped line. Source (a) (b): [Grover, 1994].

origin (where it is electrically terminated). Figure 61.54(a) is drawn for the most general case of physically separate go and return conductors, looped at the right-hand end (x = D), but the space-time trajectory of the isolated pulse is identical if the line is a single conductor open-circuited at the end and driven by an impedance-matched source. Equivalently, a tristate buffer can terminate and regenerate the returning pulse at the end of the line for on-chip use. In either case, it is evident that the instant in time that is halfway between the outgoing and returning pulse edges is the same for all points of observation on the line, regardless of the propagation velocity of the line, i.e., © 2003 by CRC Press LLC

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t1 [ x ] + t 2 [ x ] = t1[ D] = t 2 [ D] ≡ t ref 2

(61.11)

where t1[x], t2 [x], are the times when the travelling pulse edge passes position x in Fig. 61.54(a), and t[D] is the time the reference pulse edge reaches (and departs) the reflection point. This time, called tref , is the midpoint between the two pluses as seen at every point of observation on the line. This principle is adapted for single-line, skew-compensated clock distribution by periodic injection of a reference pulse onto a single conductor, reflection of this pulse at the end of the reference line, and generation of a local clock at all stations, such clock being phase-locked to the interval mid-time by a special interval-halving PLL (IHPLL) circuit, as outlined in Fig. 61.54(b). The phase detector in the IHPLL is considerably simpler than the conventional PFD used in many CMOS PLL designs. This method can be adapted easily to a two-line operation, in which a full duty cycle waveform, rather than a narrow pulse, can be used to drive the looped reference line path. The reference line can be looped at one end and driven at the other, or split into two terminated lines, routed together as a pair, and driven together as shown in Fig. 61.54(c). In the latter case, all modules lock to the reference edge arrival at mid-path, rather than at its end. In either of the two-conductor configurations, an edge-triggered, set-reset flip flop function [Fig. 61.54(d)] is the required phase detector. The two-conductor IHPLL approach avoids the need for an end-reflection or a tristate returning line driver, but requires layout of the reference line so that distances from the end are the same on both directions of the path at every tapping point. This is not hard to achieve on-chip, as the two halves of the looped path could be laid out identically. At the system level, however, the single-line variant has the advantage that uncontrolled cable and tracking lengths can be used without concern about delay equivalence in the return path, and an absolute minimum of cabling, connectors, and tracking is required for clock distribution. The interconnect is the same as that for a system in which clock is directly wired to all modules with a single line. However, this would normally be possible only if the whole system were one isochronic region. Grover [13] reports experimental skew under 1 ns over 30 m on a coaxial cable which has an uncompensated delay of 147 ns. It was also shown that in the presence of the effects of the transmission line on the traveling reference pulse, the linear component of switching time error on the traveling reference pulse contributes no skew to the resultant clock phase. A phase-shifter variant of this scheme uses a separate line to distribute raw-clock, which is then adaptively phase shifted at each point into the low-skew global phase by a voltage-controlled delay under the same feedback control sensing arrange­ ment. Two-line operation, phase shifter, and other variations are described further in [14]. With this scheme, hierarchical clock distribution networks with delay-controlled cabling, delay-tuning, and numerous temperature- and load-dependent intermediate buffers may be replaced by one conductor with arbitrary routing. Both EMI and conducted noise are reduced by buffer driver elimination and because of the reduced average power of the reference pulse compared to the full clock signal. It may also be possible to add new clock-deriving taps in service, offering a growth path that is not limited by a predesigned clock–tree fanout limit. In many applications hybrids of reduced-depth clock trees, fanning out from skew-compensated roots on a single-line clock system of this type, may give the best combination of techniques. Anceau’s and Grover’s schemes are similar in that a reference line is distributed to all modules and a PLL generates a local clock at each module. However, in the Anceau scheme modules do not run phase synchronously, Actual skew between modules remains arbitrarily high at the module clock frequency because the comm_clk line is set slow enough to be isochronic over the whole system. Actual delay in comm_clk, which is significant at the higher module rate, is not compensated at modules. Each module derives only enough information to coordinate its bus accesses with other modules, at the slower comm_clk frequency. In Grover’s scheme, however, truly synchronous full-speed global clocking of all modules is achieved by returning the signal on the reference line (by reflection or looping) and exploiting the interval-halving time-reference principle and IH-PLL to cancel global skew. Gate-to-gate interaction

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on any clock cycle is feasible between modules in this case, as opposed to interaction only through the metastable-avoidance bus interface protocol. Clock Tuning in Large Systems In large systems, clock tuning at the chip, circuit pack, shelf, and rack levels of physical equipment may be required for the highest performance. Circuits to permit clock tuning can be a tapped delay-line circuit with a programmable selector, or (on a circuits card) a printed-in set of loops to be shunted out as needed by a suitcase jack, or a voltage-controlled varactor clock delay buffer. All of these are described in [15]. In general, to aid in the tuning process, one pin on each IC should be devoted to give external observability of the worst-case (if known) clock phase form inside the IC. This way the tuning process can compensate for the delays through I/O pads and clock buffers in large ICs. Tuning begins by designing cable lengths, tracking, and connectors so that clock paths have nominally equivalent delays. The active tuning process then measures and adjusts relative delay starting from the master clock source to predefined levels of tuning points (TPs) electrically farther from the master clock source, denoted by TP0. The delay measurement and adjustment repeats through lower level tuning points until the clock on in every IC is tuned. In going from the first to successive tuning points, it is preferable to refer delay measurements directly back to TP0 each time. This may, however, be physically unmanageable, in which case delay tuning to level TPn can be relative to TPn-1 although overall error relative to TP0 will be higher in the relative tuning scheme. For systems that must grow in service, operational (i.e., in-service) signals should be the basis of the delay measurement, not requiring off-line signals or patterns. One convenient way of indirectly measuring delay between points that are not easily accessed simul­ taneously for oscilloscope measurements is to make an oscillator out of the signal path to be measured. If the number of inversions in the path between TPs is odd, then a multiplexer can be switched to loop the tuning point signal at TPn back to the TPn – 1 driving point. A frequency counter can then measure the oscillation frequency, providing data to support automatic clock delay adjustments at the subordinate tuning point. One mainframe computer used an automatic tuning scheme in which a clock phase-shifter chip produced multiple, slightly time-shifted copies of the clock on each system PCB. Individually selected delayed clock instances were then supplied to each IC on the board through a programmable crosspoint matrix IC. Each clock-receiving IC also provided several internal clock observation outputs to support delay measurements down to the gate level. After automatically measuring the delays of the observable internal clocks in up to 30 ICs per board, the on-board clock selection matrix was programmed, giving each IC its best clock phase for overall system timing margins and minimal skew [30].

Future Directions Current-Steered Logic One way of reducing power supply noise injection from clocking is with current-steered logic. Experi­ ments on differential current mode flip flops in CMOS predict very short setup times (300 to 500 ps). Such devices would be very quiet electrically and much less susceptible to varying load effects on delay than on conventional CMOS. On the other hand, such devices might be about twice as large as conven­ tional CMOS flip flops and require more power. Using the bi-CMOS ability to integrate ECL type structures with CMOS may, however, be part of the solution for clocking very high speed medium-scale integrated devices. Reduced Voltage Swing Another potential method for reducing clocked load power consumption is to reduce voltage swings. Some experiments indicate a significant reduction in clock-related power and ground noise, but skew and delay objectives are more difficult to meet as the devices slow down in response to lower switching voltage swings.

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Mixed Technology Here, clock speed increases are envisaged by using current mode logic circuits selectively to implement critical timing paths in otherwise all-CMOS systems. New power reductions may also be obtained with ECL-based, high-speed, serial-multiplexed interfaces to replace wide buses which have many parallel CMOS drivers. Q Elimination Most logic families provide flip flops with both Q and Q outputs as standard cells. An approach that could potentially have clock-related switching current and power is to eliminate the Q output buffer and develop corresponding logic synthesis tools to utilize inverted inputs and other logic means to assemble logic function without the Q outputs form flops. In one experiment of which the author is aware, Q buffers were removed, halving overall flip flop power consumption, at the cost of only a 5% degradation in clock-to-Q delay. Dedicated Layer for Clock Distribution A number of workers are advocating or are already using dedicated third-layer metal for clock distribution. This affects process cost, but the advantages can be significant in high-performance applications. Thirdlayer metal is lower than other layers in resistance and capacitance. By moving the clock net, which is the largest single net in many designs, out of the other layers, routability of all other signals is improved and floorplanning simplified. Moreover, the clock tree can avoid uncertain delays due to unpredictable routing or due to polysilicon links in series when routing in fewer shared signal layers. In addition, noise due to clocking can be more easily isolated in the third-layer metal approach. Optoelectronic Clock Distribution Optical clock distribution takes advantage of the three-dimensional nature of imaging optics to remove all but the last-stage buffering levels of the clock distribution tree from the plane of the circuit, thereby eliminating multiple stages of buffering and metallization for clock routing. Figure 61.55 is an overview of the basic idea proposed by Clymer and Goodman [7]. The optical clock signal is generated off-chip and drives a laser diode at the top of the figure. The optical beam is expanded onto a transmission

OPTICAL SOURCE

HOLOGRAM

IC CHIP SURFACE

FIGURE 61.55 Clymer and Goodman’s concept for wafer-scale optical clock distribution. Source: [Clymer and Goodman, 1986].

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hologram, which focuses the light intensity onto predefined locations where optical detectors are fabri­ cated into the wafer or die. The optical signal is detected, amplified, and used to drive a local clock generator-buffer which supplies a local isochronous regions. The optical path length differences are not equalized in this scheme because the optical path velocity is so high as to make the all optical path delays negligible as compared with the diffusion and lumped capacitive delays that determine the clock rare of the electronic system. When sources, detector, and packaging for this type of approach are developed, the potential exists for very low skew — high-speed clock distribution, with greater on-chip densities by eliminating most clock routing. One of the main challenges is in attaining uniform response times from the optical detector-amplifier combination (which tend to be sensitive to feature size variations) and the development of sources in the optical wavelength range for photodetectors that can be fabricated within the conventional CMOS circuit environment. Reconfigurable Clock Nets In WSI systems, where a single short in very large clock net may disable an entire wafer-level system, Fried [10] advocates methods of restructuring a clock net to enhance yield, primarily through the addition of a controllable tristate output stage to clock buffers within the clock distribution network. This way failed portions of the clock net can be isolated, or, with redundant interconnect and buffers, they may clocked by an alternate path. In particular, tristate buffers may be programmed on or off to select clock for each module from redundant connections to the central clock net, or to simply isolate failed clock net subregions from the drivers of unfailed portions.

References [1] F. Anceau, “A Synchronous Approach for Clocking VLSI Systems,” IEEE J. Solid-State Circuits, vol. SC-17, no. 1, pp. 51–56, Feb. 1982. [2] M. Afghahi and C. Svensson, “A Unified Single-Phase Clocking Scheme for VLSI Systems,” IEEE J. Solid-State Circuits, vol. 25, no. 1, pp. 225–233, Feb. 1990. [3] H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990, chap. 8. [4] S. Boon, S. Butler, R. Byrne, B. Setering, M. Casalanda, and A. Scherf, “High Performance Clock Distribution for CMOS ASICS,” Proc. IEEE 1989 Custom Integrated Circuits Conf., pp. 15.4.1–15.4.5, 1989. [5] M. A. Cirit, “Clock Skew Elimination in CMOS VLSI,” Proc. IEEE Int. Symp. Circuits Systems, 1990, pp. 861–864. [6] J. Cong, A. Kahng, and G. Robins, “On Clock Routing for General Cell Layouts,” Proc. 4th IEEE Int. ASIC Conf., pp. 14.5.1–14.5.4, Sep. 1991. [7] B. D. Clymer and J. W. Goodman, “Optical Clock Distribution to Silicon Chips,” Opt. Engin., vol. 25, no. 10, pp. 1103–1108, Oct. 1986. [8] R. H. Cramback, C. M. Lee, and H. S. Law, “High-Speed Compact Circuits with CMOS,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 614–619, June 1982. [9] D. Dobberpuhl et al., “A 200 MHz 64-b CMOS microprocessor,” IEEE JSSC, vol. 27, no. 11, pp. 1555–1567, Nov. 1992. [10] J. Fried, “Power and Clock Distribution for WSI Systems,” in Proc. IFIP Workshop on Wafer Scale Integration, G. Saucier and J. Trilhe, Eds. Amsterdam: North-Holland, 1986, pp. 127–141. [11] F. M. Gardner, “Charge-Pump Phase-Locked Loops,” IEEE Trans. Commun., vol. COM-28, pp. 1849-1858, Nov. 1980. [12] L. A. Glasser and D. W. Dobberpuhl, The Design and Analysis of VLSI Circuits. Reading, MA: Addison-Wesley, 1985, chap. 6. [13] W. D. Grover, “A New Method for Clock Distribution,” IEEE Trans. Circuits & Systems Part I, Feb. 1994, vol. 41, no. 2, pp. 149–160.

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[14] W. D. Grover, Method and Apparatus for Clock Distribution and Distributed Clock Synchronization, United States Patent #5,361,277, Issued Nov. 1, 1994. [15] M. W. Johnson and M. Graham, High-Speed Digital Design: A Handbook of Black Magic. Englewood Cliffs, NJ: Prentice Hall, 1993, chap. 11. [16] M. G. Johnson and E. L. Hudson, “A Variable Delay Line PLL of CPU-Coprocessor Synchroniza­ tion,” IEEE J. Solid-State Circuits, vol. 23, no, 5, pp. 1218–1223, Oct. 1998. [17] D. C. Keezer and V. K. Jain, “Design and Evaluation of Wafer Scale Clock Distribution.” IEEE Int. Conf. WSI, 1992, pp. 168–175. [18] S.-Y. Kung and R.J. Gal-Ezer, “Synchronous vs. Asynchronous Computation in Very Large Scale Integrated (VLSI) Array processors, Proc. SPIE, vol. 341, pp. 53–64, 1982. [19] S. D. Kugelmass and K. Steiglitz, “An Upper Bound on Expected Clock Skew in Synchronous Systems,” IEEE Trans. Comput., vol, 39, no. 12, pp. 1475–1477, Dec. 1990. [20] LSI Logic Corp., Phase-Locked Loop Application Note, LSI Logic Application Note, Nov. 1991. [21] LSI Logic Corp., Clock Scheme for One Micron Technologies, Rev. 1.1, LSI Logic Application Note, Aug. 1992. [22] LSI Logic Corp, Clock Distribution Schemes for 300K Technologies, Rel. 2.0, LSI Logic Application Note, May 1993. [23] A. M. Moshen and C. A. Mead, “Delay-Time Optimization for Driving and Sensing of Signals on High-Capacitance Paths of VLSI Systems,” IEEE Trans. Electron Devices, ED-26, pp. 540–548, 1979. [24] N. Nigam and D. C. Keezer, “A Comparative Study of Clock Distribution Approaches for WSI,” Proc. IEEE 1993 Int. Conf. WSI, pp. 243–251, 1993. [25] W. A. Samaras, “The CPU Clock System in the VAX 8800 Family,” Digital Tech. J., no. 4, pp. 34–40, Feb. 1987. [26] T. Saigo, S. Watanabe, Y. Ichikawa, S. Takayama, T. Umetsu, K. Mima, T. Yamamoto, J. Santos, and J. Buurma, “Clock Skew Reduction Approach for Standard Cell,” Proc. IEEE 1990 Custom Integrated Circuits Conf., pp. 16.4.1–16.4.4, 1990. [27] C. L. Seitz, “System Timing,” in Introduction to VLSI Systems, C. Mead and L. Conway, Eds. Reading, MA: Addition-Wesley, 1980, chap. 7. [28] J. Shyu, A. Sangiovanni-Vincentelli, J. Fishburn, and A. Dunlop, “Optimization-Based Transistor Sizing,” IEEE J. Solid-State Circuits, vol. 23, no. 2, pp. 400–409, April 1988. [29] D. Tanksalvala et al., “A 90 MHz RISC CPU Designed for Sustained Performance,” IEEE Solid-State Circuits Conf., pp. 52–53, Feb. 1990. [30] K. D. Wagner, A Survey of Clock Distribution Techniques in High Speed Computer Systems, Report CRC 86-20. Stanford, CA: Stanford University Center for Reliable Computing, Dec. 1986. [31] N. Weste and K. Eshragian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd ed. Reading, MA: Addison-Wesley, 1993, pp. 317–335 (clocking strategies), pp. 334–336 (PLL methods), pp. 685–689. [32] D. F. Wann and M. A. Franklin, “Asynchronous and Clocked Control Structures for VLSI Based Interconnection Networks,” IEEE Trans. Comput., vol. C-32, No. 3, pp. 284–293, March 1983.

61.3 MOS Storage Circuits Josephine C. Chang and Bing J. Sheu In a large digital system, a sequence of operations must be performed for a particular function. The results of each operation depend on the results of previous operations. Therefore, the outputs of a logic circuit block typically depend not only on present input signals, but also on the history of the inputs. A combinational logic circuit becomes more useful if it is combined with memory elements. To construct a sequential system, the most common and straightforward way is to employ a central clock to synchronize the sequence of operations.

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Instead of using memory elements in a sequential system, we can used dynamic logic circuits to store temporary data. With the building blocks of inverters and transmission gates, the MOS transistors can be used as dynamic storage components to store data temporarily on the device capacitances. Dynamic storage is widely used in MOS technologies because of the simplicity of the required circuitry. Because a memory element such as a static circuit latch occupies a large area and consumes power, elimination of latches has a positive effect on circuit density and power consumption. However, the disadvantages of dynamic logic gates include high transient power disturbances and less noise margins in some applications [1]. Dynamic logic circuits design is based on the synchronized movement of charge through the MOS circuit. A typical capacitance value associated with a logic gate is on the order of a few femtofarads, with means the amount of charge Q = CV dynamically stored on the capacitance is on the order of femto­ coulombs. Therefore, perturbations from ideal behavior can become critical to the operation of a circuit.

Dynamic Charge Storage The MOS technologies have two attractive feature that lead to an efficient way to store data momentarily. These two features are the extremely high input impedance of MOS transistor and the ability of a MOS transistor to function as a nearly ideal electrical switch. In order to store the charge on a capacitive node, the node must be isolated from both the power supply and ground. Various types of storage nodes can be realized in CMOS technologies. For example, charge can be stored at a node between sources (or drains) of two MOS transistors such as nMOS–nMOS, pMOS–nMOS, and nMOS–pMOS [2]; or the source (or the drain) terminal of one MOS transistor connected to the gate terminal of a second MOS transistor. Because the stored charge will leak away over time, this circuit is termed dynamic storage circuit. Figure 61.56 shows the schematic diagrams of three combinations of source-drain connection. The distinction among the three connection types comes from the difference in voltage transmission levels for nMOS and pMOS gates. Dynamic charge storage requires clocking the data at a sufficiently high rate so that the charge on the various nodes does not lead away significantly. Typically, this requires a minimum refresh rate of 500 Hz to 1 kHz, corresponding to a charge storage time of about to 2 ms.

+ Vx −

C

+ Vx −

C

(a)

(b)

+ Vx −

C

(c)

FIGURE 61.56 MOSFET source-drain connection storage nodes. (a) nMOS-nAMOS; (b) pMOS-pMOS; (c) nMOS­ pMOS.

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nMOS–nMOS An nMOS transistor is perfect for transmitting logic 0 signals, but imperfect for transmitting logic 1 signals due to the threshold voltage loss through the transistor. The voltage level of Vx which can be stored on the capacitor C is therefore limited by

(

)

0 ≤ Vx ≤ VDD − Vth, n = Vmax

(61.12)

where Vth, n = Vth0, n + γ n

(

2φ Fn + Vmax − 2φ Fn

)

(61.13)

Charge storage on an nMOS–nMOS node is affected by the leakage paths through the p-type bulk to the ground. This affects the long-term storage of a logic 1 value. pMOS–pMOS A pMOS–pMOS node is the complement storage component of an nMOS-nMOS node. The voltage level of Vx is limited by Vmin = Vth, p ≤ Vx ≤ VDD

(61.14)

Vth, p = Vth0, p + γ p  2φ Fp + (VDD − Vmin ) − 2φ Fp   

(61.15)

where

Because both p-channel MOS transistors have n-type bulks which are connected to VDD, this type of storage node receives leakage current from the power supply. The logic 1 values can be held indefinitely, but the logic 0 values can only exist for a limited period of time. nMOS–pMOS A complementary nMOS–pMOS storage node can benefit from both nMOS and pMOS in transmitting logic 0 and logic 1, respectively. The voltage level which is stored on the capacitance is in the range of 0 ≤ Vx ≤ VDD

(61.16)

If the maximum input value of VDD is transmitted through the pMOS transistor and the minimum input value of 0 V is transmitted through the nMOS transistor. On the other hand, if the case is reversed, the maximum input value is entered through the nMOS transistor and the minimum input value is entered through the pMOS transistor, then the voltage range is reduced to Vth, p ≤ Vx ≤ VDD − Vth, n

(61.17)

This type of operation should be avoided because it greatly reduces the noise margins. In a standard nMOS–pMOS storage node both leakage paths to the power supply and ground exist. The ability to retain logic 0 and logic 1 values depends on which leakage path dominates. Source-Gate Connection This type of storage node is the connecting point between the source terminal of a pass transistor and a gate terminal of another MOS transistor [3]. Electrical charge can be temporarily stored on or removed

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from the gate terminal of the second transistor. When the gate terminal of the pass transistor is at a logic low value, the pass transistor is turned off, and the charge on the gate terminal is isolated. This charge determines the stored logic value. If the stored charge is perfectly isolated, the logic value would be stored indefinitely. In a practical situation, the isolation is less than perfect, primarily because of leakage through the reverse-biased diode operation between the source diffusion region of the pass transistor and the substrate. In addition, leakage also can occur through the pass transistor. With the continuous advances in VLSI technologies, subthreshold leakage through the channel of the pass transistor becomes more important due to scale-down in device sizes. Leakage currents alter the node voltage, which may lead to a logic error. Two major problems arise in maintaining the integrity of a stored logic state. First is the parasitic conduction paths in the transistors that lead to charge leakage. Leakage currents alter the node voltage, which may cause a logic error. The second problem is charge sharing, which occurs when two isolated storage nodes become connected by a switching event and must equalize their voltages by redistributing charge. Charge sharing may result in a logic error, or may block logic propagation entirely. Charge Sharing Beside charge leakage, a problem called charge sharing may also damage the integrity of a stored logic state. Charge sharing occurs when a dynamic charge-storage node is used to drive another isolated node in a switching network [4]. Typically, when two capacitors with different voltages are connected by a pass transistors, as shown on Fig. 61.57, charge sharing may occur. When the pass transistor is turned on, the voltages on the capacitors equilibrate to some intermediate value. In Fig. 61.57, capacitors C1 and C2 are in parallel when the transmission gate is conducting. This forces the voltages across C1 and C2 to be equal. If the two capacitors are charged to different initial voltages, charge sharing will occur when the transmission gate turns on. Let the initial voltage charge on C1 be V1 and Q1, and the initial voltage and charge on C2 be V2 and Q2. The initial charge balance equation is Q1 + Q2 = C1V1 + C 2V2

(61.18)

After the transmission gate turns on, the final charges on C1 and C2 become Q 1′ and Q 2′ , respectively, and both capacitors are charged to the same value V ′. The final charge balance equation is Q1′ + Q2′ = (C1 + C 2 )V ′

(61.19)

By applying the charge-conservation principle, we can obtain C1V1 + C 2V2 C1 + C 2

(61.20)

C1 (C V + C2V2 ) C1 + C 2 1 1

(61.21)

V′ = and Q1′ =

− S V1

V2 C2

C1 S

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FIGURE 61.57 Charge-sharing-prone structure.

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A precharged circuit might work incorrectly due to charge-sharing errors, which could occur inside the pulldown network or at the output circuit. To control a precharged circuit, a gated clock can be present only at the input of the bottom transistor, while all other inputs to the gates of transistors in series in the pulldown chain must have a stable signal over the same clock phase to prevent chargesharing problems. A sneak path is created when two pass transistors in series are both turned on at the same time and one is connected to VDD while the other is connected to the ground. Charge can leak through this sneak path.

Shift Register A frequent use of dynamic storage circuits is the shift register. Shift registers are most often used to provide temporary storage of digital signals. The shift register storage can be used as a simple way to delay the arrival of a signal for a specific number of clock cycles. Shift register storage is also frequently used as the temporary memory for a sequential logic circuit. In general, shift registers provide dense, limited access memory for many applications in digital integrated circuits. Simple Shift Register Figure 61.58 is the schematic diagram of a multistage MOS shift register, with each stage composed of a pass transistor and an inverter [5]. The nonoverlapping clock waveforms Φ1 and Φ2 are used. Assume that a logic signal is placed at the input of the first shift register stage while the Φ1 clock is low and the transmission gate of the first stage is turned off. Next, when the Φ1 clock goes high, if the signal at the input to the first stage is held constant, it will be propagated to the input of the inverter in the first stage. After a short delay, the output of the first inverter will provide the inverted logic signal to the input of the second shift register stage. At this time, the Φ2 clock is low and the transmission gate in the second stage will not pass this signal. When the clock values change so that Φ2 becomes high, the transmission gate of the second stage will propagate the output signal of the first stage to the second inverter, and then the output of the second stage is produced. This signal will be stopped by the transmission gate of the third stage because Φ1 is low while Φ2 is high. This sequence continues through the shift register chain as the clock signals alternate, causing the input signal to propagate through the shift register stages. The data are stored on the capacitances associated with the gate terminals of the inverter. The transmission − φ1

− φ2

− φ1

− φ2

φ1

φ2

φ1

φ2

(a)

φ1

φ2 (b)

FIGURE 61.58 (a) A four-stage MOS register. (b) Nonoverlapping waveforms of φ1and φ2. © 2003 by CRC Press LLC

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gate acts as the switch that lets charge flow into and out of the capacitors when they are turned on. The charge is trapped at the capacitor when the transmission gate is turned off. Each time the Φ1 clock changes to a high value, the shift register input signal will propagate to the gate of the first inverter and the output signal of the first stage will be produced. A sequence of alternating Φ1 and Φ2 clock signals will cause an input signal to propagate through the whole structure at the rate of two stages of the shift register for each complete cycle of the clock signals. After N clock cycles, a logic input value will have shifted through 2N stages of the shift register chain. When a two-phase clock is used to control a shift register, it is important that the two clock phases do not overlap. If both phases of the clock were high simultaneously, a data value could propagate through multiple stages during the clock overlap time. This would cause erroneous operation of the shift register. Parallel Shift Register Several copies of the multistage shift registers can be combined in parallel with the same clock lines to form a parallel shift register to transmit a group of signals in lock-step fashion. Such a parallel shift of 8, 16, or 32 data bits is often used in microprocessor circuits. The basic structure of this set of shift registers demonstrates two principles which are important for the efficient geometrical layout of digital circuits. The data for the shift register flow from left to right while the control signals (Φ1 and Φ2 clocks) flow from top to bottom. Such an orthogonal structure of data paths and control signals within a circuit module is widely used to provide a regular organization of logic circuits within a VLSI chip. Physical layout of the shift register stages can be mirrored with respect to the ground and VDD lines. This mirroring technique allows shared power and ground connections and reduces required circuit layout area. It is important to minimize the size of the basic shift register stage because this stage is repeated many times in a large shift register. Clocked Barrel Shifter A barrel shifter is a wraparound shifter that forms a very useful switch array [6]. The basic layout is shown in Fig. 61.59. The inputs are labeled Ii ; the shift controls Φ2· SHi, and the outputs Oi . The input lines O3

φ2. SH3

O2

φ2. SH2

O1

φ2. SH1

O0

φ2. SH0

φ1

I0

I1

FIGURE 61.59 A four-bit clocked barrel shifter.

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I2

I3

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run horizontally while the output lines run vertically. The operation of the first shift register stage is the same as explained earlier. In the second stage for four output signals from the four inverters in the first stage can be shifted without changing the order, or each signal can move up one, two, or three locations.

Dynamic CMOS Logic The dynamic CMOS logic design consists of dynamic circuits based on precharging the output node to a particular level when the clock is at the logic 0 level. During the precharge phase, the inputs to the circuits change. When the clock is at the logic 1 value, the output of the logic gate may be pulled to a complementary value, depending on the input conditions. The choice of using static or dynamic logic is dependent on many criteria. When low-power performance is desired, it appears that dynamic logic has some inherent advantages in a number of areas including reduced switching activity due to hazards, elimination of short-circuit dissipation, and reduced parasitic node capacitances. Static logic circuits have advantages on charge sharing and precharge operation. Static circuits design can exhibit spurious transitions due to races. These spurious transitions dissipate extra power over that required to perform the computation. The number of these extra transitions is a function of input patterns, internal state assignment in the logic design, delay skew, and logic depth. Although it is possible with careful logic design to eliminate these transitions, dynamic logic intrinsically does not have this problem because any node can undergo at most one power-consuming transition per clock cycle [7]. Short-circuit currents are found in static CMOS circuits. However, by sizing transistors for equal rise and fall times, the short-circuit component of the total power dissipated can be kept to N, we have y1 = a1x1 + a2 x 2 + a3 x 3 y2 = y3 =

a1x 2 + a2 x 3 + a3 x 4 a1x 3 + a2 x 4 + a3 x 5

M Here, we show two of many possible systolic arrays that can implement the above correlation operations. Design B1 in Fig. 61.100(a) uses three identical PEs to perform the accumulation (multiply and add) operation. Here, the weights ai are preloaded to the cells and stay throughout the computation. Partial results yi move systolically from cell to cell. Starting at the third iteration, y1, y2, …, are outputted from the rightmost cell at the rate of one output per iteration. For each iteration, a xi is broadcast to all the cells, and a yi , initialized to zero, enters the leftmost cell. The broadcasted data xi is marked with an arrow ↓ in Table 61.12. Indeed, by comparison we see y1, y2, and y3, outputted at iteration T = 3, 4, and 5, agree with those given from the correlation equations. In design B2, shown in Fig.61.100(b), each input xi is again broadcasted to each cell, each yi stays at each cell to accumulate terms, while the weights ai circulate around the cells in the array. A tag bit is associated with a1 to reset the contents of the accumulator, while a tag bit is associated with a3 to output the contents of the accumulator after the first two iterations. Data movements in design B2 are shown in Table 61.13. Note that resets occur at cell 1 at iteration 1, cell 2 at iteration 2, cell 3 at iteration 3, cell

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x3

x2

x1

y3

y2

y1

x3

x1 a1

yout a2

a1

a3

y1

a3

xin yin

x2

y2

a2

y3

xin a

yout

ain yin + a • xin

y

aout

ain

aout

yout

y + ain • xin

yout

y

FIGURE 61.100 (a) Systolic array design B1 for correlation; (b) systolic array B2 for correlation.

TABLE 61.12 Data Movement in Design B1 Iteration

Cell 1

T=1

x1 a1

T=2

x 2 a1

↓

a1a1 + x 2 a2

T=3

x3 a1

↓

x 2a1 + x3 a2

T=4

x 4 a1

↓

x3a1 + x 4 a2

T=5

x 5 a1

↓

x 4a1 + x 5 a2

↓

Cell 2

Cell 3

↓

↓

x1 a2

x1 a3 ↓

x1a2 + x 2 a3

↓

↓

x1a1 + x 2a2 + x3 a3 → y1

↓

x 2a1 + x3a2 + x 4 a3 → y2

↓

x3a1 + x 4a2 + x 5 a3 → y3

↓

↓

↓

TABLE 61.13 Data Movement in Design B2 Iteration

Cell 1

Cell 2

↓

Cell 3

↓

T=1

0 + a1 x1

T=2

a1 x1 + a2 x 2

T=3

a1x1 + a2 x 2 + a3 x3 → y1

T=4

0 + a1 x 4

T=5

a1 x 4 + a2 x 5

↓

a3 x1

a2 x1 ↓

↓

↓

0 + a1 x 2 ↓

↓

a2 x1 + a3 x 2 ↓

↓

a1 x 2 + a2 x3

0 + a1 x3 ↓

a1 x 2 + a2 x3 + a3 x 4 → y2 ↓

↓

0 + a1 x 5

↓

a1 x3 + a2 x 4 ↓

a1 x3 + a2 x 4 + a3 x 5 → y3

4 at iteration 4, etc. Similarly, output y1 occurs from cell 1 at iteration 3, y2 from cell 2 at iteration 4, y3 from cell 3 at iteration 5, etc. Systolic Array Design Techniques Systolic array designs, as shown above for the correlation case, can be obtained by ad hoc approaches. More formal procedures for the systematic design of systolic arrays have been proposed by Moldovan [7], Quinton [9], Kung [5], Rao [10], Darte and Delosme [1] and others. All those more formal procedures are collectively referred to as dependence graph mapping techniques for systolic array design. In this approach, an algorithm must be formulated in the single assignment algorithm form. Each variable has a unique value during the evaluation of the algorithm. Those variables with multiple values can be converted to single values by vectorizing the variables through the introduction of new indices. © 2003 by CRC Press LLC

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As an example, consider the matrix multiplication of C = AB, where A = [aik] is N1 × N3, B = [bkj] is N3 × N2, and C = [cij] is N1 × N2. A conventional formulation of this algorithm contains the expression, cij = cij + aik bkj for i = 1 to N1, j = 1 to N2, and k = 1 to N3. We note, cij has multiple values for k = 1, …, N3. We can modify it to have single values by replacing it by the variable cijk. The previous equation for cij then becomes cijk = cij(k–1) + aik bkj, cij0 = 0, cijN3 , i = 1, …, N1, j = 1, …, N2, k = 1, …, N3. All algorithm variables are assumed to be indexed variables with V variable names, denoted by the generic names of Vm , 1 ≤ m ≤ V. In the above matrix–matrix multiplication problem V = 3, and we can take X1, = c, X2 = a, and X3 = b. For each variable name, the domain of the index vectors is a subset in an S-dimensional space. This subset is called the algorithm’s index space and S is its dimension. For most iterative signal processing problems, time is usually one of the index space coordinates. For the preceding matrix–multiplication problem, we need to propagate aik across the j variables as well as bkj over the i variables in order to perform the basic multiplication operation. These and aik and bkj are propagating variables because they involve no computations, but need to be made available at various stages of the computation. In the matrix–matrix problem, clearly S = 3 and the index space is S0 = {(i, j, k): 1 ≤ i ≤ N1, 1≤ j ≤ N2, 1 ≤ k ≤ N3,}. Furthermore, the initializations of the new variables are given by a(i, 0, k) = aik , b(0, j, k) = bjk, c(i, j, 0) = 0, c(i, j, N3) = cij , and the algorithm is finally given by a(i, j, k) = a(i, j, – 1, k), b(i, j, k) = a(i –1, j, k), c(i, j, k) = c(i, j, k – 1) + a(i, j, j)b(i, j, k), for (i, j, k) ∈ S0. In general, a point (or node) in the index space is called an index point. Thus, Xm(I) is the variable Xm defined at the index point I. A dependence graph mapping is a representation of a single assignment algorithm, where the dependencies among the variables are represented by directed arcs among the nodes. A basic property of the class of algorithms of interest is that of shift-invariance. An algorithm is shift-invariant if the dependence graph is regular. That is, X(I) depends on Y(J), then X(I + K) depends on Y(J + K) for all I, J, and K in the index space. Three well-known shift-invariance algorithms include: 1. Uniform recurrence equations (URE): X1(I) = F1(X1(I – D1), …, XV (I – DV)), Xi(I) = Xi(I – Di ), 2 ≤ i ≤ V. Computation occurs only in F1(·) and propagations in all the other variables, Clearly, the final form of the above matrix–matrix multiplication algorithm is a URE algorithm with V = 3, F1(·) = c(i, j, k), with X1(·) = c(·), X2(·) = a(·), X3(·) = b(·), I = (i, i, k), D1 = [0, 0, 1]T, D2 = [0, 1, 0]T, and D3 = [1, 0, 0]T. 2. Generalized uniform recurrence equations (GURE): Xm(I) = Fm(Xm1 (I – Dm1), …, Xmk(m) (I – Dmk(m))), 1 ≤ m ≤ V, where m1, …, mk(m), belongs to {1, …, m}. In GURE we can have computations in all V functions of Fm (·). The number of independent variables mk(m) depends on each m. The shift index dependence, I – Dmi , is fixed for each Xmi .

3. Regular iterative algorithm (RIA): Xm(I) = Fm(Xm1 (I – Dm1, m), …, Xmk(m) (I – Dmk(m)m)), 1 ≤ m ≤ V. Here, the shift index dependency, I – Dmi ,m , is not fixed but is a function of mi and m. Each processor of the systolic array is assumed to have all the necessary computational modules to compute Fm (.). For URE, we need only one such module, but for GURE and RIA, we need V modules. The time required for the computation of Fm(·) is denoted by τm , and the minimum time between such computations is denoted by hm. In most cases, we can set τm and hm to unity. The design of a processor array to perform the algorithm requires spatial and temporal assignments. Each Xm (I) must be assigned to a processor at each integral time slot. The processor allocation function, A(I) assigns all variables with the index I to the processors in the array. The scheduling function, Sm(I), assigns the start of the computation for the variable Xm(I). The simplest form of scheduling and processor allocations are based on the projection of the high multidimensional dependence graph onto the lower dimensional processor array. Variables represented by nodes in the dependence graph are mapped to processors which perform the computations. The directed arcs of the dependence graphs are transformed to physical communica­ tion links in the processor array. The essence of the allocation function A(·) is thus to return for every index value I ∈ S0 a vector which indicates the processor in charge of the computation represented by a point in a lower dimensional space. Analogously, the scheduling function Sm(·) provides the relative start of the execution for the computation © 2003 by CRC Press LLC

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indexed by I. These two functions cannot be chosen independently because two computations assigned to the same processor cannot be scheduled for the same time (compatibility constraint). Additional details on this constraint are given later. While in principle A(·) and Sm(·) can be any function, we shall consider only affine functions, in the sense that A(I) = , ATI, Sm(I) = λTi + γm , where A is a suitable matrix, λ a vector, and γm an integral constant. The dependence graph of an algorithm can be interpreted as a lattice embedded in a multidimensional integral space (i.e., a proper bounded subset of Zs, where Z is the set of relative integers), enclosed in a convex polyhedron. We assume the lattice to be “dense” in the sense that all the integral points in it correspond to actual computations. The whole procedure of mapping an algorithm onto a systolic-type processor consists of two conceptually different but interdependent operations of using a space transfor­ mation and a time transformation. The former actually projects the dependence graph onto a lower dimensional structure which then can be mapped one-to-one onto the physical array, while the latter gives the start of the execution of each computation. For simplicity, consider the projection of the S-dimensional space onto an (S – 1) dimensional processor space. The more general problem of projecting the dependence graph onto an (S – p)­ dimensional space (p ≥ 1) can be expressed using a similar but more involved notation and is omitted here. Instead of considering allocation functions, we refer to the projection vector u, which is orthogonal to the processor space onto which we project. Assume that we have chosen both the projection and the scheduling vectors (u and λ, respectively). For normalization purposes, they are chosen to be coprime vectors, such that the greatest common divisor of their components is 1, and their first nonzero element is positive. Two sets of constraints must be satisfied by u and λ. Assume nodes I and J are located along a direction parallel to the projection vector u such that J = I + α u, α ∈ Z. Then, the computations associated with the two nodes will be projected onto the same processor. Consequently, compatibility constraint requires that they be performed at different times. Analytically, this is equivalent to  λT u λ maxm = 1, …, V hm, which for hm = 1 simplifies to λT u > 0. Thus, for this case λ and u cannot be perpendicular. Furthermore, the ∆ λT u represents the number of time slots between successive calculations scheduled on the quantity c = same processor. 1/c is sometimes called the efficiency of the processors because the larger the c, the more time the processors can idle. One common approach is to select the projection vector and the scheduling vector so as to achieve the highest efficiency, with c being as close to 1 as possible. Consider the case in which the variable Xm(I) depends on Xn (I – Dnm ). The precedence constraint implies the calculation of Xn (I – Dnm ) must be scheduled so as to be completed before the start of the calculation of Xm (I). Analytically, the precedence constraint is equivalent to λTDnm + γm – γn ≥ τn = 1, for all 1 ≤ m ≤ v and for all dependences Dnm. If the γ constants are chosen to be all equal, the precedence constraint becomes λTDnm ≥ 1∀m = 1, … , V. Assume the precedence and compatability constraints are satisfied and λ and u are coprime vectors. Then it is possible to extend both vectors to two unimodular matrices. A matrix with integral entries is called unimodular when its determinant is equal to ± 1. This implies that they admit integral inverses. The unimodular extension of coprime vectors is not unique. We will choose U and Λ to be the unimodular extended matrices that have u and λ, respectively, as their first columns. It is possible to show that the columns of any S-dimensional unimodular matrix can constitute a basis for the space ZS. Moreover, if we denote σ1 , ..., σs to be the columns of Σ = U –T, then we have σ1Tu = 1 and σ1Tu =0 for all i = 2, …, S. Therefore, {σ2, …, σs} will be a basis of the processor space of the resulting logic array. Similarly, the first column of T (the inverse of ΛT) t1, represents the direction in which time increases by one step; i.e., it is the vector defining the hyperplane of the points computed at the same time. The other columns of T (denoted by t2, …, ts) are a basis of such a hyperplane. If we denote by Σ + = [σ2, …, σs] the matrix basis of the processor space, the allocation function and the scheduling function have the form A(I) = Σ T+ I, Sm(I) = λTI + γm, m = 1, …, V. With these elements we can have the complete description of the final array. The processors are labeled by A(I) = Σ T+ I as I ranges over the index space. The dependences Dnm are mapped onto communication links Σ T+ D nm and the delay registers on such links must be in number equal to λTDnm + γm – γn – τn = λTDnm –1. © 2003 by CRC Press LLC

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j

yi

y1 y2 y3 y4

ak a3

a2

a1

a2 a1 i x1 x2 x3

0

x1

0

x2

0 (a)

x3 (b)

FIGURE 61.101 (a) Two-dimensional dependence graph; (b) one-dimensional dependence graph.

Reconsider the systolic correlation problem using the weights {a1, …, ak} and the data {x1, …, xn}, as discussed earlier. Recall the correlation is given by yi = a1 xi + a2xi+1 + … + ak xi+k–1, 1 ≤ i ≤ n + 1 – k. A recurrence equation formulation of this equation is given by y(i, j) = y(i, j – 1) + w(i, j)x(i, j), y(i, 0) = 0, yi = y(i, k); w(i, j) = w(i – 1, j), w(1, j) = aj; and x(i, j) = x(i+1, j – 1), x(i, 0) = xi–1, all with 1 ≤ i ≤ n + 1 – k, 1 ≤ j ≤ k. A dependence graphical representation of these equations is shown in Fig. 61.101(a). A URE reformulation of the recurrence equations yields X1(I) = y(i, j) = F1(X1(I – D1), X2(U – D2), X3(I – D3)), X2(I) = w(i, j) = X2(I – D2), X3(I) = x(i, j) = X3(I – D3), with the index point I = [i, j]T and displacement vectors D1 = [0, 1]T, D2 = [1, 0]T, and D3 = [–1, 1]T. In particular, consider the URE representation of the B1 design based on the choice of u = [1, 0]T, Σ + = [0, 1]T, λ = [1, 1]T, γm = 0, m = 1, 2, and 3, and τn = hn = 1, n = 1, 2, and 3. Then, the two-dimensional graph of Fig. 61.101(a) is projected onto the one-dimensional graph of Fig. 61.101(b). Specifically, for any index I = [i, j]T, the processor allocation function yields A(I) = Σ T+ I = j, i ≤ j ≤ k, which is a valid projection from two-dimensions to one. On the other hand, the index point for each input data x1 (with variable name of X3) is given by I = [i, l – i + 1]T, l = 1, …, n. Then the scheduling function S3(I) is given by S3(I) = λTI = [1, 1] [i, l – i + 1]T = i + l – i + 1 = l + 1, l = 1, …, n. This indicates each x1 for the previously given I must be available at all the processors at time l + 1. Thus, there is no propagation and this means all the x1 must be broadcasted to all the processors. However, the simplistic definition of a systolic design does not allow broadcasting. Indeed, the precedence constraint is not satisfied with D3. That is, λTD3 = [1,1][– 1, 1]T = 0 ≥/ τn = 1. Of course, other choices of λ and u generate other forms of systolic array architecture for correlation. For more complicated signal processing tasks such as QR decomposition, recursive leastsquares estimation, singular value decomposition, Kalman filtering, etc., the design of efficient systolic array architectures are generally difficult. The dependence graph mapping technique provides a systematic approach to such designs by providing the proper selections of these λ and u vectors.

Digital Filters The application of digital filtering has spread tremendously in recent years to numerous fields, such as signal processing, digital communications, image processing, and radar processing. It is well known that the sampling rate, which is closely related to the system clock, must be higher than the Nyquist frequency of the signals of interest. It follows that in order to perform real-time filtering operations when high frequency signals are involved, high-speed computing hardware is necessary. Pipelining techniques have been widely used to increase the throughput of synchronous hardware implementations of a transfer function of a particular algorithm. Most algorithms can be described in a number of different ways, and each of these descriptions can be mapped onto a set of different concurrent architectures. Different descriptions may lead to realizations with entirely different properties, and can have a dramatic impact on the ultimate performance of the hardware implementation. Pipelining can also be used for other than throughput increase. For a fixed sample rate, a pipelined circuit is characterized by a lower power consumption. This is due to the fact that in a pipelined system capacitances can be © 2003 by CRC Press LLC

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charged and discharged with a lower power supply. Because the dissipated power depends quadratically on the voltage supply, the power consumption can be reduced accordingly. An increase in the speed of the algorithm also can be achieved by using parallelism. By replicating a portion of the hardware architecture, similar or identical operations can be performed by two or more concurrent circuits, and an intelligent use of this hardware redundancy can result in a net throughput increase, at the expense of area. Note that VLSI technologies favor the design in which individual sections of the layout are replicated numerous times. A regular and modular design can be achieved at relatively low costs. For a fixed sample rate, parallelism can be exploited for a low power design due to the reduced speed requirements on each separate portion of the circuit. Much work has been done in the field of systolic synthesis of finite and infinite impulse response (FIR/IIR) filters, as can be seen from the literature references. In the following subsection, we consider possible strategies that can be used to increase the throughput of the concurrent architectures of the FIR and IIR filters. Finite Impulse Response Filters Finite impulse response (FIR) filters have been largely employed because of certain desirable properties. In particular, they are always stable, and causal FIR filters can posses linear phase. A large number of algorithms have been devised for the efficient implementation of FIR filters, which minimize the number of multipliers, the round-off noise, or the coefficient sensitivity. The generic expression that relates the output y(n) at time n to the inputs x(n-i) at times (n-i) i = 0,1, …, q is given by y (n) =

q

∑ a x(n − i) i

i=0

q are the FIR filter coefficients. Here, we consider only issues of pipelining and parallelism. where the {ai}i=0 The pipeline rate, or throughput, of implemented nonrecursive algorithms such as FIR filters can be increased without changing the overall transfer function of the algorithms by means of a relatively simple modification of the internal structure of the algorithm. In particular, one set of latches and storage buffers can be inserted across any feed-forward cutset of the data flow graph. Figure 61.102(b), illustrates the

x(n)

D

a0

D a1

a2

y(n)

(a)

x(n)

D

a0

D a1

D

a2 D

D feed-forward cutset

(b)

y(n − 1)

FIGURE 61.102 A three-tap FIR filter. (a) With no pipelining, the throughput is limited by the rate of one multi­ plication and two additions. (b) With pipelined circuit, the throughput is increased to the rate of one multiplication or two additions.

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x(2k + 1) x(2k) D D

x(2k − 2) x(2k − 1)

a0

a1

a2

y(2k)

a0

a1

a2

y(2k + 1)

FIGURE 61.103 Three-tap FIR filter whose hardware has been duplicated to achieve double throughput rate.

increase of throughout achieved by pipelining in a second-order three-tap FIR filter. The sample rate of the circuit of Fig. 61.102(a) is limited by the throughput of one multiplication and two additions. After placing the latches at the locations shown in Fig. 61.102(b), the throughput can be increased to the rate of one multiplication or two additions. Pipelining can be used to increase the sample rate in all the cases in which no feedback loops are present. The drawbacks of pipelining are an increased latency and a larger number of latches and buffers. Parallelism can be used to increase the speed of an FIR filter. Consider Fig. 61.103, in which the threetap FIR filter of Fig. 61.102 was duplicated. Because at each time instant two input samples are processed and two samples are output, the effective throughput rate is exactly doubled. As can be seen from Fig. 61.103. parallelism leads to speed increase at a considerable hardware cost. For many practical implementations, parallelism and pipelining can be used concomitantly, when either method alone would be insufficient or limited by technology such as I–O, clock rate, etc. Infinite Impulse Response Filters These are recursive filters in the sense that their output is function of current inputs as well as past outputs. The general I–O relationship is expressed by y (n) =

p

∑

ai y (n − j ) +

q

∑ b x (n − i) i

(61.22)

i =o

j=1

q are the coefficients where the {aj} pj =1 are the coefficients associated to the recursive part, and the {bi}i=0 associated to the nonrecursive portion of the filter. The associated transfer function is written as the following z-transform

q

H (z ) =

∑b z i =o p

1−

∑a z j

j=1

© 2003 by CRC Press LLC

−i

i

z− j

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For stability reasons, it is required that all the poles (i.e., the zeroes of the denominator of H(z)) be inside the unit circle in the z-plane. Consider a circuit in which L loops are present each with latency τk , k = 1, …, L. The number of latches present in each loop is equal to vk , k = 1, …, L. Then the throughput period cannot be shorter than τ  Tmax ≡ max  k  k = l, …, L v  k The pipeline can be increased by increasing the number of latches internal to the feedback loops. The computational latency associated with the internal feedback prevents one from introducing pipeline simply by inserting latches on feedforward cutsets. In fact, inserting latches in the loop would change the overall transfer function. This difficulty can be overcome by recasting the algorithm into an equivalent formulation from an I–O point of view. The transformations applied to the algorithm, prior to the mapping, have the purpose of creating additional concurrency, thereby increasing the achievable through­ put rate. Without ever changing the algorithm’s transfer function, additional delays are introduced inside the recursive loop. These delays are subsequently used for pipelining. In the sequel, we briefly describe two types of look-ahead techniques that generate the desired algorithmic transformations, namely the clustered and the scattered look-ahead techniques proposed by Loomis and Sinha [18] and Parhi and Messerschmitt [19], respectively. Look-ahead techniques are based on successive iterations of the basic recursion, in order to generate the desired level of concurrency. The implementation is then based on the iterated version of the algorithm. Clustered Look-Ahead: In a pth order recursive system, the output at time n is a function of the past output samples y(n-1), y(n – 2), …, y(n – p). In the clustered look-ahead technique, the recursion is iterated m times so that the current output is a function of the cluster of p consecutive samples y(n – m), y(n – m – 1), …, y(n – m – p). The original order-p recursive filter is emulated by a (p + m)th filter, where m canceling poles and zeroes have been added. In this way the m delays generated inside the feedback loop can be used to pipeline by m stages. By iterating 61.22 m times, we can derive the following I–O relationship y (n) =

p−1

 p   akrj +m−k  y (n − j − m) + k = j +1   

∑∑ j=1

m−1

q

∑ ∑ b x(n − k − j) k

j=0 k=0

P akri–k, i > 0, where the coefficients {ri} can be precomputed off-line, and are such are such that ri = Σk=1 r0 = 1, and ri = 0, i = –(p – 1), …, –1. This implementation requires (p + m) multiplications for the nonrecursive part, and p for the recursive part, for a total of (2 p + m), which grows linearly with m. The transfer function is equal to m−1

q

∑∑ b z

−k− j

k

H (z ) =

j=0 k=0

p−1

1−

 p   akrj +m−k  z − j −m k = j +1   

∑∑ j=1

The clustered look-ahead technique does not guarantee that the resulting filter is stable because it may introduce poles outside the unit circle. Consider the following simple example with a stable transfer function: H (z ) = © 2003 by CRC Press LLC

1 1 − 1.3z + 0.35z −2 −1

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with poles at z = 0.7 and z = 0.5. The two-stage equivalent filter can be obtained by introducing the canceling pole-zero pair at z = –1.3, as follows: H (z ) =

1 + 1.3z −1 1 + 0.9 z −1 = −2 −3 1 −1.3z −1 + 0.35z −2 1 +1.3z −1 1 − 1.34 z + 0.455z

(

)(

)

Because a pole is found at z = –1.3, this transfer function is clearly unstable. Scattered Look-Ahead: In the scattered look-ahead technique, the current output sample y(n), is expressed in terms of the (scattered) p past outputs y(n – m), y(n – 2m), …, y(n – mp). The original order-p filter is now emulated by an order-mp filter. For each pole of the original filter, (m – 1) canceling pole-zero pairs are introduced at the same distance from the origin as the original pole. Thus, stability is always assured. The price we must pay is higher complexity, on the order of mp. To best describe the technique, it is convenient to write the transfer function H(z) as a ratio of polynomials, i.e., H(z) = N(z)/D(z). The transformation can be written as follows:

H (z ) =

N (z ) = D( z )

∏ D(ze ( ) ) ∏ D(ze ( ) )

N (z )

m–1

j 2πk m

k=1 m–1

j 2πk m

k=0

Note that the transformed denominator is now a function of z–m. Consider the example of the previous section. For the scattered look-ahead technique, it is necessary to introduce pole-zero pairs at z = 0.7 e ± j (2π/3) and z = 0.5 e ± j (2π/3). The transformed denominator equals 1 – 0.125z–3. The complexity of the nonrecursive part of the transformed filter is (pm + 1) multiplications, while the recursive part requires p multiplications, for a total of (pm + p +1) pipelined multiplications. Although the complexity is still linear in m, it is much higher than in the clustered look-ahead technique for a large value of p. Parhi and Messerschmitt [19] presented a technique to reduce the complexity of the nonrecursive portion down to O(p log2 m), applicable when m is a power of 2. This technique can be described as follows. Assume that the original recursive portion of the given IIR filter is given by 1

H (z ) =

p

1−

∑ a( ) z 1 j

−j

j=1

An equivalent two-stage implementation of the same filter can be obtained by multiplying numerator and denominator by the polynomial (1 – ΣPj=1 (–1)j aj(1)z –j ), which is given by p

1− H (z ) =

∑ (−1) a( )z j

1 j

−j

j=1

p

1−

∑ a( ) z 2

−j

j

j=1

(2) p j=1 j

where the set of coefficient {a } is obtained from the original set {aj(1)} pj=1 by algebraic manipulation. By repeating this process log2 m times one can obtain an m-stage pipelined implementation, equivalent to the original filter. In this way the hardware complexity only grows logarithmically with the number of pipelining stages. © 2003 by CRC Press LLC

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z−1

Input Output

Head Con­ nection

Module

z−1

z−1

Module 2

1

Module

End

L

Con­ nection

FIGURE 61.104 A general structure of bidirectional IIR filters.

Input

0 MUX 1

PE 1

PE 2

PE m

PE m+1

Output

Control

FIGURE 61.105 The overlapped subfilter scheme for IIR filtering.

Bidirectional Systolic Arrays for Infinite Impulse Response Filtering: Lei and Yao [16] showed that many IIR filter structures can be considered as special cases of a general class of systolizable filters, as shown in Fig. 61.104. These filters can be pipelined by rescaling the time so that z′ = z1/2, , and by applying a cutset transformation. This time rescaling causes the hardware factorization to reduce to merely 50%, which is quite inefficient. Lei and Yao [17] later proposed two techniques to improve the efficiency of these bidirectional IIR filters. In the first method (“overlapped subfilter scheme”), one makes use of the possibility to factor the numerator and the denominator of the given transfer function. For instance, if H (z ) =

N (z ) N a (z ) N b (z ) = ⋅ D( z ) Da ( z ) Db ( z ) 123 123 Ha ( z )

Hb ( z )

where a + b = p, a – b = 0, 1, or 2, and p is the number of modules of the original transfer function. Then the two subfilters, Ha(z) and Hb(z), can be realized on the same systolic array of a + 1 modules, as in Fig. 61.105. A multiplexer at the input of the array chooses the incoming data at even time instants, and the data from the output of the first module at odd time instants. The modules alternately perform operations associated to Ha(z) and Hb(z) in such away as to interleave the operations and have an overall 100% efficiency. In the second technique (“systolic ring scheme”) the number of modules is about half of the order of the original transfer function. The modules of the new structure are arranged as a systolic ring, as in Fig. 61.106. For example, a five-module ring can be used to implement a ten-module IIR filter: module i performs the operations associated to modules i and (5 + i) of the original array, for i = 1, …, 5. Note that in the original structure every other module is idle. The resulting ring is therefore 100% efficient.

Systolic Word and Bit-Level Designs Previous discussions on systolic array designs have taken place at the word level. This is to say that the smallest data or control item exchanged between pairs of processors is constituted by a word representable by B bits. Each processor in a word-level system has the capability of performing word-level operations. Some may be as complex as floating point multiplications or others as simple as square root operations, © 2003 by CRC Press LLC

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Input

0 MUX 1

PE 1

PE (n−1)/2

PE 2

Output PE (n+1)/2

Control

PE n

PE n−1

PE (n+3)/2

FIGURE 61.106 The systolic ring scheme for IIR filtering.

etc. The systolic array approach can be applied at various different levels beyond the word level, according to what is sometimes referred to as granularity of the algorithm description. Systolic arrays and associated dependence graphs can, in fact, be defined at high levels of description, in which each individual processor can, in principle, be a whole mainframe computer or even a separate parallel processor array. The communication between processors thus takes the form of complex protocols and entire data sequences. According to the same principle, the algorithm description can also be done at the lowest level of operation, namely, at the bit level, at which each processor is a simple latched logic gate, capable of performing a logic binary operation. The exchanged data and control also take the form of binary digits. The different approaches due to the different granularity of description have different merits and can be advantageously used in various circumstances or at different steps of the design. These considerations bring to one possible design strategy, namely, the hierarchical systolic design. In this approach the complete systolic design is broken down to a sequence of hierarchical steps, each of which define the algorithm at different levels of granularity. At first, the higher level of description is adopted, the relative dependence graph is drawn, and, after suitable projection and scheduling, a highlevel systolic architecture is defined. Subsequently, each high-level processor is described in terms of finer scale operations. Dependence graph and systolic architecture corresponding to these operations are produced and embedded in the higher level structure previously obtained. The process can continue down to the desired level of granularity. The simplest form of hierarchical design implies two steps. The first step involves the design of the word-level architecture. Second, the operations performed by each work-level processor are described at bit level. The corresponding bit-level arrays are then nested into the word-level array, after ensuring that data flows at both levels are fully compatible. The hierarchical approach has the merits of reducing the complexity of each step of the design. The dependence graphs involved usually have reduced dimensionality (thus, are more manageable), and the procedure is essentially recursive. The drawback of a hierarchical design is that it implicitly introduces somewhat arbitrary boundaries between operations, thereby reducing the set of resulting architectures. An approach that leaves all options open is to consider the algorithm at bit level from the outset. This approach has led to new insights and novel architectures. The price to pay is that the designer must deal with dependence graphs of higher dimensionality. As an example, the dependence graph of the inner –1 ai bi is two dimensional. If the same inner product is written product between two N-vectors, c = ΣNi=0 N –1 B–1 at bit level, i.e., ck = Σ i =0 Σ j=0 ai, j bi, k – j + carries, k = 0, …, B – 1, then it produces a three-dimensional dependence graph. Examples of the two design procedures applied to the convolution problem are considered below. First, consider the factors that can make bit-level design advantageous: • Regularity. Most bit-level arrays are highly regular. Only relatively simple cells need be designed and tested. The communication pattern is simple and regular. Neighbor-to-neighbor connections allow high packing density and low transmission delays. © 2003 by CRC Press LLC

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• High pipeline rate. Because the individual cells have reduced computation time (on the order of the propagation delay through a few gates), the overall throughput can be made very high. • Inexpensive fault tolerance. The use of bypass circuitry can be made without wasting too much of the silicon area. It must be borne in mind that bit level arrays realistically cannot be operated in wavefront array mode because the interprocessor hand-shaking protocols would be too expensive as compared to the data exchange. A good clock signal distribution is therefore needed to synchronize the array operations. In systolic arrays, unlike synchronous architectures of a different sort, only the incremental clock skew must be minimized by suitably designing the clock signal distribution lines. This problem may become par­ ticularly delicate in bit-level arrays, where the number of processors involved is very high. Bit-Level Design of a Serial Convolver Bit-level systolic design was first proposed by McCanny and McWhirter [29]. Subsequently, they and others have applied this technique to various algorithms. As a simple example, consider the bit-level design of a serial convolver. The word-level output of an N point convolver can be written as –1 –1 ai xk– i , k = 0, 1, …, where {ai}Ni=0 is a given set of coefficients and xi, i = 0,1, …, is a sequence yk = ΣNi =0 of input data. Coefficients and data values are assumed to be B-bit words. The word-level dependence graph is shown in Fig. 61.107, together with one possible systolic realization. In this case, the coefficients are permanently stored in each individual cell. Input and output values are propagated in opposite directions. In each processing element, the corresponding coefficient is multiplied by the incoming data value. This product is added to the partial output value and the accumulated result is propagated forward. Each cell performs the simple multiply and add operation expressed by yk,i+1 ← yk,i + ai xk–i , yk = yk,N . According to the hierarchical approach, one must now proceed to determine the dependence graph corresponding to the bit-level description of the multiply-and-add operation. The complete dependence graph can be subsequently obtained by embedding the finer scale graph into the higher level graph. If both ai and xi are B-bit binary numbers, then the jth bit of yki , can be computed according to yk,i,j = yk,i,j + si,k,j , si,k,j ≡ ΣBl=–10 ai,l x k–i, j–l + carries, where ai , l and xi,l , l = 0, …, B – 1, represent the lth bit of ai and xi . The dependence graph corresponding to this operation is given in Fig. 61.108, where subscripts only

x1 0 x0

x1

x2

x3

x0

a0 a1 a2 a3

a0 y0 a1 y1

a2

y2

y3

a3 y4

y5

y6

y0 0 y1

FIGURE 61.107 World-level dependence graph of an N point convolution operation with one possible systolic realization.

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x0

x1

x2

a0 s0

s3

s1

s4

s2

s5

a1 a2

FIGURE 61.108 Bit-level dependence graph corresponding to the mul­ tiply-and-add operation.

x0

x1 y0

x2 y1

x3 y2

y3

a0 y4

a1

y5

a2

y6

a3

FIGURE 61.109 Bit-level dependence graph for convolution obtained by embedding the bit-level graph into the word-level graph.

indicate the bit position, and B = 3. Note that this graph is quite similar to the graph corresponding to a convolver, apart from the carry bits, which are taken care of by the insertion of an additional row of cells. The combined dependence graph, obtained from the word dependence graph of Fig. 61.107, in which each cell is replaced by the bit-level dependence graph of Fig. 61.108, is given in Fig. 61.109. The data flows are fully compatible at both word and bit levels. At this point, a full two-dimensional bit-level systolic array can be obtained from the final dependence graph by simply replacing each node with latched full adder cells. Different linear systolic implementations can be obtained by projecting the combined dependence graph along various directions. One possibility is again to keep the coefficients residents in individual cells, and have input data bits and accumulated results propagate in opposite directions. The schematic representation of the systolic array with these features is drawn in Fig. 61.109. Judgment about the merits of different projections involves desired data movement, I–O considerations, throughput rate, latency time, efficiency factor (ratio of idle time to busy time per cell), etc. As discussed previously, the convolution operation can be described at bit level from the very begin­ ning. In this case the expression for the jth bit of the kth output can be expressed as follows: © 2003 by CRC Press LLC

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a00

x00

x01

a01

x02

a02

x1 a1

x2 a2

x02

x01

x12

x11

x10

x21

x20

x00

x30 x3

a3

FIGURE 61.110 General three-dimensional bit-level dependence graph for convolution. N −1 B−1

yk, j =

∑∑ a x

i ,l k−i , j −1

i=0

+ carries

(61.23)

l=0

By using this expression as a starting point, one is capable of generating a number of feasible systolic realizations potentially much larger than what is attainable from the two-step hierarchical approach. The reason for this can be simply understood by nothing that in this formulation no arbitrary precedence relationship is imposed between the two summations on i and l, whereas earlier we required that the summation on l would always precede the summation on i. The result is a fairly complicated threedimensional dependence graph of size N × B × number of inputs, as shown in Fig. 61.110. Observe that the bottom level of the dependence graph corresponds to the summation over l in (61.23). In the same figure a schematic two-dimensional bit-level systolic realization of the algorithm is given, in which the coefficient bits are held in place. Projections along different directions have different characteristics and may be considered preferable in different situations. The choice ultimately must be made according to given design constraints or to efficiency requirements. The concept of bit-level design, as considered here, can be applied to a large variety of algorithms. Indeed, it has generated a number of architectures, including FIR/IIR filters, arrays for inner product computation, median filtering, image processing, eigenvalue problems, Viterbi decoding, etc.

Recursive Least-Squares Estimation Least-Squares Estimation The least-squares (LS) technique constitutes one of the most basic components of all modern signal processing algorithms dealing with linear algebraic and optimization of deterministic and random signals and systems. Specifically, some of the most computationally intensive parts of modern spectral analysis, © 2003 by CRC Press LLC

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Digital Systems

1971

beam formation, direction finding, adaptive array, image restoration, robotics, data compression, param­ eter estimation, and Kalman filtering all depend crucially on LS processing. Regardless of specific application, an LS estimation problem can be formulated as Ax ≈ y, where the m × n data matrix A and the m × 1 data vector y are known, and we seek the n × 1 desired solution x. In certain signal processing problems, rows of A are composed of sequential blocks of lengths n taken from a one-dimensional sequence of observed data. In other n-sensor multichannel estimation problems, each column of A denotes the sequential outputs of a given sensor. In all cases, the desired solution x provides the weights on the linear combinations of the columns of A to optimally approximate the observed vector y in the LS sense. When m = n and A is nonsingular, then an exact solution for x exists. The Gaussian elimination method provides an efficient approach for determining this exact solution. However, for most signal processing problems, such as when there are more observations than sensors, and thus m > n, then no exact solution exists. The optimum LS solution xˆ is defined by A xˆ – y = minx Ax – y. The classical approach in LS solution is given by xˆ = A+y, where A+ is the pseudo-inverse of A defined by A+ = (AT A)–1 AT. The classical LS approach is not desirable from the complexity, finite precision sensitivity, and processing architecture points of views. This is due to the need for a matrix inversion, the increase of numercial instability from “squaring of the condition number” in performing the ATA operation, and the block nature of the operation in preventing a systolic update processing and architecture for real-time applications. The QR decomposition (QRD) approach provides a numerically stable technique for LS solution that avoids the objections associated with the classical approach. Consider a real-valued m × n matrix A with m ≥ n and all the columns are linearly independent (i.e., rank A = n). Then, from the QRD, we can find – – a m × m orthogonal matrix Q such that QA = R. The m × n matrix R = [RT, 0T]T is such that R is an n × n upper triangular matrix (with nonzero diagonal elements) and 0 is an all-zero (m − n) × n matrix. This upper triangularity of R is used crucially in the following LS solution problem. Because the l2 norm of any vector is invariant with respect to an orthogonal transformation, an – application of the QRD to the LS problem yields Ax – y2 = Q(Ax – y)2 =  Rx – f 2, where f is a m × 1 matrix given by f = Qy = [uT, vT]T. Denote e = Ax – y as the residual of the LS problem. Then, the previous LS problem is equivalent to e2 = Ax – y2 = [Rx, 0x]T – [uT – vT]T2 = Rx – u2 + v2. Because R is a nonsingular upper triangular square matrix, the back substitution procedure of the Gaussian elimination method can be used to solve for the exact solution xˆ of Rxˆ = u. Finally, the LS problem reduces to minx – Ax – y2 = Axˆ – y2 =  Rxˆ – f 2 = Rxˆ – u2, + v2 = v2. For the LS problem, any QRD technique such as the Gram-Schmidt method, the modified-Gram–Schmidt (MGS) method, the Givens transformation, and the Householder transformation is equally valid for finding the matrix R and the vector v. For a systolic implementation, the Givens transformation yields the simplest architecture, but the MGS and Householder transformation techniques are also possible with slight advantages under certain finite precision conditions. Recursive Least-Squares Estimation The complexity involved in the computation of the optimum residual eˆ and the optimum LS solution vector xˆ can become arbitrarily large as the number of samples in the column vectors of A and y increases. In practice, we must limit m to some finite number greater than the number of columns n. Two general approaches in addressing this problem are available. In the sliding window approach, we periodically incorporate the latest observed set of data (i.e., updating) and possibly remove an older set of data (i.e., downdating). In the forgetting factor approach, a fixed scaling constant with a magnitude between 0 and 1 is multiplied against the R matrix and thus exponentially forget older data. In either approach, we find the optimum LS solution weight vector xˆ in a recursive least-squares manner. As the statistics of the signal change over each window, these xˆ vectors change adaptively with time. This observation motivates the development of a recursive least-squares solution implemented via the QRD approach. For simplicity, we consider only the updating aspects of the sliding window recursive least-squares problem. Let m denote the present time of the sliding window of size m. Consider the m × n matrix A(m), the m × 1 column vector y(m), the n × 1 solution weight column vector x(m), and the m × 1 residual column © 2003 by CRC Press LLC

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vector e(m) expressed in terms of their values at time m − 1 as A(m) = [α(1), …, α(m)]T = [A(m – 1)T, α(m)]T, y(m) = [y1, …, ym]T [y(m – 1)T, yTm]T, x(m) = [x1(m), …, xn(m)]T, and e(m) A(m) × (m) – y(m) = [e1(m), …, en(m)T. By applying the orthogonal matrix Q(m) = [Q1(m)T, Q2(m)T]T of the QRD of the m × n matrix A(m), we obtain Q(m) A(m) = [R(m)T, 0T]T = R0(m) and Q(m)y(m) = [Q1(m)T, Q2(m)T]T y(m) = [u(m)T, v(m)T]T. The square of the l2 norm of the residual e is then given by ∈(m) = e(m)2 = A(m)x(m) – y(m)2 = Q(m)(A(m)x(m) – y(m))2 = R(m)x(m) – u(m)2 + v(m)2. The residual is minimized by using the back substitution method to find the optimum LS solution xˆ(m) satisfying R(m)xˆ (m) = u(m) = [u1(m),…,un(m)]T. It is clear that the optimum residual eˆ(m) is available after the optimum LS solution xˆ(m) is available as seen from eˆ(m) = A(m) xˆ(m) – y(m). It is interesting to note that it is not necessary to first obtain xˆ(m) explicitly and then solve for eˆ(m) as shown earlier. It is possible to use a property of the orthogonal matrix Q(m) in the QRD of A and the vector y(m), to obtain eˆ(m) explicitly. Specifically, note eˆ(m) = A(m) xˆ (m) – y(m) = Q1 (m)T R(m) xˆ (m) – y(m) = [Q1(m)T Q1(m) – Im]y(m) = –Q2(m)T Q2(m)y(m) = –Q2(m)Tv(m). This property is used explicitly in the following systolic solution of the last component of the optimum residual. Recursive QR Decomposition Consider the recursive solution of the QRD. First, assume the decomposition at step m–1 has been completed as given by Q(m – 1)A(m – 1) = [R(m – 1)T, 0T]T by using a (m – 1) × (m – 1) orthogonal matrix. Next, define a new m × m orthogonal transformation T(m) = [Q(m) – 1), 0; 0,1]. By applying T(m) on the new m × n data A(m), which consists of the previously available A(m – 1) and the newly available row vector α(m)T we have Q(m − 1) T (m) A(m) =   0

0  1

 A(m −1) Q(m −1) A(m − 1)  =  T  α(m)T    α(m)    

R(m −1)   =  0  = R1 (m)    α(m)T    While R(m–1) is an n × n upper triangular matrix, R1(m)does not have the same form as the desired R0(m) = [R(m)T,0T]T where R(m) is upper triangular. Givens Orthogonal Transformation Next, we want to transform R1(m) to the correct R0(m) form by an orthogonal transformation G(m). While any orthogonal transformation is possible, we will use the Givens transformation approach due to its simplistic systolic array implementation. Specifically, denote G(m) = Gn(m)Gn–1(m) … G1(m), where G(m) as well as each Gi(m), i = 1, … n, are all m × m orthogonal matrices. Define 1 1 1    Gi (m) = i 0   m 0 

i 0 1 c i (m) −si (m)

m 0   (m), si  1  c i (m)

i = 1, …, n

as a m × m identity matrix, except that the (i, i) and (m, m) elements are specified as ci(m) = cos θi(m), where θi(m) represents the rotation angle at the ith iteration, the (i, m) element as si(m) = sin θi(m), and the (m, i) element as –Si(m). By cascading all the Gi(m), G(m) can be reexpressed as © 2003 by CRC Press LLC

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Digital Systems

 k(m)  G(m) =  0  h T (m) 

d(m)  0   γ (m)

0 I m−n−1 0

where k(m) is n × n, d(m) and h(m) are n × 1, and γ(m) is 1 × 1. In general k(m), d(m), and h(m) are n ci(m) and will be quite involved functions of ci (m) and si (m), but γ(m) is given simply as γ(m) = Π i=1 used in the evaluation of the optimum residual. Use G(m) to obtain G(m)T(m)A(m) = G(m)R1(m). In order to show the desired property of the n orthogonal transformation operations of G(m), first consider c1 (m)    G1 (m)R1 (m) =     s m  1( ) x  0  =  0   0

s1 (m)        c1 (m)

1 1 1

x

L

x

L L

0

L

x

L

x  0    0  x 

x

L

x

L L

0

L

x

L

x  x  x  x  x 

x  x  x  x  x 

In the preceding expression, an x denotes some nonzero valued element. The purpose of G1(m) operating on R1(m) is to obtain a zero at the (m, 1) position without changing the (m – 2) × n submatrix from the second to the (m – 1)st rows of the r.h.s. of the expression. In general, at the ith iteration, we have x     Gi (m)    0  0 

x . . . x  x   x . . . x    x    =   M   0 . . . 0  0   0 0 x x x  0 i −1

x . . . x  x . . . x  x   M  0 . . . 0  0 0 0 x x  i

The preceding zeroing operation can be explained by noting that the Givens matrix Gi(m) operates as a (m – 2) × (m – 2) identity matrix on all the rows on the right of it except the ith and the mth rows. The crucial operations at the ith iteration on these two rows can be represented as c  −s

s  c 

0  0

L

0

ri

ri+1

L

L

0

ai

ai+1

L

i © 2003 by CRC Press LLC

rn   an 

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The Circuits and Filters Handbook, Second Edition

0   = 0

L

0

riT

ri +1

T

L

L

0

0 i

aiT+1

L

rnT   anT 

For simplicity of notation, we suppress the dependencies of i and m on c and s. Specifically, we want to force aiT = 0 as given by 0 = aiT = –sri + cai . In conjunction with c2 + s2 = 1, this requires c2 = ri2/(ai2 + ri2) from the individual and s2 = ai2/(ai2/ri2). Then riT = cri + sai = ( a 2i + r i2 ), c = ri /riT, and s = ai /riT .This shows – results of G1(m), G2(m), …, Gn(m), the overall results yield Q(m) A(m) = G(m) R(m) = [R(m)T, 0T]T = R0(m), with Q(m) = G(m)T(m). Recursive Optimal Residual and LS Solutions Consider the recursive solution of the last component of the optimum residual eˆ(m) = [eˆ1(m), …, eˆm(m)]T = –Q2(m)T v(m) = –Q2(m)T [v1(m), …, vm(m)T]. Because Q2(m) = [Q2(m – 1), 0; h(m)T Q1(m – 1), γ(m)], then eˆ(m) = [eˆ1(m), …, eˆm(m)]T = Q2(m) = –[QT2 (m – 1), QT1 (m – 1)h(m); 0, γ(m)] [v1(m), …, vm(m)]. n ˆ Thus, the last component of the optimum residual is given by e(m) = –γ(m)vm(m) = –Π i =1 ci(m)vm(m),

which depends on all the products of the cosine parameters ci(m) in the Givens QR transformation, and vm(m) is just the last component of v(m), which is the result of Q(m) operating on y(m). As considered earlier, the LS solution xˆ satisfies the triangular system of equations. After the QR operation on the extended matrix [A(m), Y(m)], all the rij , j ≥ i = 1, …, n and ui , i = 1, …, n are available. Thus, {xˆ1, …, xˆn} can be obtained by using the back substitution method of xˆi = (ui – Σ nj– i+1rij xˆj /rij ), i = n, n – 1, …, 1. Specifically, if n = 1, then xˆ1 = u1/r11. If n = 2, then xˆ2 = u2/r22 and xˆ1 = u1 – r12 xˆ2/r11 = u1/r11 – u2 r12 /r11r22 . If n = 3, then xˆ3 = u3 /r33, xˆ2 = u2 – r23 x3 /r22 = u2 /r22 – r23 u3 /r22 r23 , and xˆ1 = u1 – r12 xˆ2 – r13 xˆ3 /r11 = u1/r11 – r12 u2 /r11 r22 + u3[–r13 /r11 r33 + r12 r23 /r11 r22 r33 ]. Systolic Array Implementation for QR Decomposition and LS solution The recursive QRD considered above can be implemented on a two-dimensional triangular systolic array based on the usage of four kinds of processing cells. Figure 61.111(a) shows the boundary cell for the generation of the sine and cosine parameters, s and c, needed in the Givens rotations. Figure 61.111(b) shows the internal cell for the proper updating of the QRD transformations. Figure 61.111(c) shows the single output cell needed in the generation of the last component of the optimal residual eˆm(m) as well ˆ as the optimal LS solution x(m). Figure 61.111(d) shows the delay cell which performs a unit time delay for proper time skewing in the systolic processing of the data. Figure 61.112 shows a triangular systolic array capable of performing the recursive QRD for the optimal recursive residual estimation and the recursive least-squares solution by utilizing the basic processing cells in Fig. 61.111. In particular, the associated LS problem uses an augmented matrix [A,y] consisting of the m × n observed data matrix A and the m × 1 observed vector y. The number or processing cells in the triangular array consists of n boundary cells, n(n + 1)/2 internal cells, one output cell, and n delay cells. The input to the array in Fig. 61.112 uses the augmented matrix a11 a12 L a1n y1    a21 a22 L a2n y 2   [ A, Y ] =   M   a a  m1 m2 L a y mn m   skewed in a manner such that each successive column from left to right is delayed by a unit time as given by

© 2003 by CRC Press LLC

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Digital Systems

σ

a

a

r

(c,s)

(c,s)

r

σo Init.cond. : r = 0; σ = −1 Input a = 0: C = 1; s = 0, σo = σ; r = 0. Input a ≠ 0: r′ = (a2 + r2) .5; c = r/r′; s = a/r′; r = r′ ; σ = coσ.

(c,s)

a′ Init.cond. : r = 0. r′ = cr + sa; a′ = −sr + ca; r = r′

(a)

(b)

a

σ

σ

D

Out

σ0 a0 a0 = σa

σ0 = σ

(c)

(d)

FIGURE 61.111 (a) Boundary cell; (b) internal cell; (c) output cell; (d) delay cell.

 a11   a 21   a31     a  n1 a  ( n+1)1     am1     0   0

0

L

0

a12

0

L

0

a 22

a13

L

0

M a ( n−1) 2

a1n

a n2

a 2n M

a (m−1) 2

a (m− n+1) n M amn 0

0  k =1  0  2  0  3   M  0  n  y1  n +1  M   ym− n  m  M   ym−1  m + n −1  ym  m + n

We see that at time k, input data consists of the kth row of the matrix, and moves down with increasing time. However, in Fig. 61.112, purely for drawing purpose in relation to the position of the array, the relevant rows of data are drawn as moving up with increasing k. Consider some of the iterative operations of the QRD for the augmented matrix [A, y] for the systolic array in Fig. 61.112. At time k = 1, a11 enters BC 1 and results in c = 0, s = 1, and r11 = a11 . All other cells are inactive. At k = 2, a21 enters BC 1, with the results c = a11 (a 112 + a 212 ) , s = a21 (a 112 + a 212 ) , r11 = 2 2 a 11 + a 21 . This r11 corresponds to that of riT, while the preceding c and s correspond to the c and s in the

© 2003 by CRC Press LLC

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The Circuits and Filters Handbook, Second Edition

a51

a42

a33

y2

5

a41

a32

a23

y1

4

a31

a22

a13

0

3

a21

a12

0

0

2

a11

0

0

0

k=1

σ (c,s)

BC 1 r11

(c,s)

1 IC 2 r12

1 IC 3 r13

(c,s)

1 IC 4 u1

I=1

2 IC 3 r23

(c,s)

2 IC 4 u2

I=2

3 IC 4 u3

I=3

σ D1 σ

BC 2 r22

(c,s)

σ D2 σ

BC 3 r33

(c,s)

σ D3 σ

Out

I=4

aout J=1

3

J=2

J=

J=4

FIGURE 61.112 Triangular systolic array implementation of an n = 3, QRD-recursive, least-squares solver.

Givens transformation. Indeed, the new aiT is zero and does not need to be saved in the array. Still, at k = 2, a12 enters 1 IC 2 and outputs aT = 0 and r12 = a12 . At k = 3, a13 enters BC 1, and the Givens rotation operation continues where the new ri is given by the previously processed riT and ai is now given by a13. Meanwhile, a22 enters at 1 IC 2. It outputs aT = –a21a12/ (a 112 + a 212 ) + –a22a21/ (a 112 + a 212 ) , which corre­ sponds to that of a iT+1, and r 12 = a11a12/ ( a 112 + a 212 ) + –a21a22/ ( a 112 + a 212 ) , which corresponds to that of r iT+1. In general, the top (i.e., I = 1) row of the processing cells performs Givens rotation by using the first row to operate on the second, third, …, mth rows (each row with n + 1 elements), such that the {21,31, …, m1} locations in the augmented matrix are all zeroed. The next row (I = 2) of cells uses the second row to operate on the third, …, mth rows (each row with n elements), such that locations at {32, 42, …, m2} are zeroed. Finally, at row I = n, by using the nth row to operate on the (n + 1)st, …, mth rows, elements at locations {(n + 1)n, (n + 2)n, …, mn} are zeroed. We also note that the desired cosine values in γ(m) are being accumulated by c along the diagonal of the array. Delay cells {D1, D2, …, Dn) are used to provide the proper timing along the diagonal. The cell BC 1 (at I = J = 1) terminates in the QR operation at time k = m, while the cell at I = 1 and J = 2 terminates at k = m + 1. In general, the processing cell at location (I, J) terminates at k = I + J + m – 2. In particular, the last operation in the QRD on the augmented matrix is performed by the cell at I = n and J = n + 1 at time k = 2n + m – 1. Then, the last component of the optimum residual em(m) exits the output cell at time k = 2n + m. After the completion of the QRD obtains the upper triangular system of equation, we can “freeze” the rIJ values in the array to solve for the optimum LS solution xˆ by the back substitution method. Specifically,

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1977

we can append [In, 0], where In is a n × n identity matrix and 0 is an n × 1 vector of all zeroes, to the bottom of the augmented matrix [A, y]. Of course, this matrix is skewed as before when used as input to the array. In particular, immediately after the completion of the QR operation at BC 1, we can input the unit value at time k = m + 1. This is stage 1 of the back substitution method. Due to skewing, a unit value appears at the I = 1 and J = 2 cell at stage 3. Finally, at stage (2n – 1), which is time k = m + 2n – 1, the last unit value appears at the I = n and J = 1 cell. For our example of n = 3, this happens at stage 5. The desired LS solution xˆ1 appears at stage (2n + 1) (ie., stage 7 for n = 3), which is time k = 2n + m + 1, while the last solution xˆn appears at stage 3n (i.e., stage 9 for n = 3), which is time k = 3n + m. The values of {xˆ1, xˆ 2, xˆ 3} at the output of the systolic array are identical to those given by the back substitution method solution of the LS problem.

Kalman Filtering Kalman filtering (KF) was developed in the late 1950s as a natural extension of the classical Wiener filtering. It has profound influence on the theoretical and practical aspects of estimation and filtering. It is used almost universally for tracking and guidance of aircraft, satellites, GPS, and missiles as well as many system estimation and identification problems. KF is not one unique method, but is a generic name for a class of state estimators based on noisy measurements. KF can be implemented as a specific algorithm on a general-purpose mainframe/mini/microcomputer operating in a batch mode, or it can be implemented on dedicated system using either DSP, ASIC, or custom VLSI processors in a real-time operating mode. Classically, an analog or a digital filter is often viewed in the frequency domain having some low-pass, bandpass, high-pass, etc. properties. A KF is different from the classical filter in that it may have multiple inputs and multiple outputs with possibly nonstationary and time-varying characteristics performing optimum states estimation based on the unbiased minimum variance estimation criterion. In the following discussions, we first introduce the basic concepts of KF, followed by various algorithmic variations of KF. Each version has different algorithmic and hardware complexity and implementational implications. Because there are myriad of KF variations, we then consider two simple systolic versions of KF. Basic Kalman Filtering The KF model consists of a discrete-time linear dynamical system equation and a measurement equation. A linear discrete-time dynamical system with n × 1 state vector x(k + 1), at time k + 1, is given by x(k + 1) = A(k)x(k) + B(k)u(k) + w(k), where x(k) is the n × 1 state vector at time k, A(k) is an n × n system coefficient matrix, B(k) is an n × p control matrix, u(k) is a p × 1 deterministic vector, which for some problems may be zero for all k, and w(k) is an n × 1 zero-mean system noise vector with a covariance matrix W(k). The input to the KF is the m × 1 measurement (also called observation) vector y(k), modeled by y(k) = C(k)x(k) + v(k), where C(k) is an m × n measurement coefficient matrix, and v(k) is a m × 1 zero-mean measurement noise vector with an m × m positive-definite covariance matrix V(k). The requirement of the positive-definite condition on V(k) is to guarantee the Cholesky (square root) fac­ torization of V(k) for certain KF algorithms. In general, we will have m ≤ n (i.e., the measurement vector dimension is less than or equal to that of the state vector dimension). It is also assumed that w(k) is uncorrelated to v(k). That is, E{w(i)v(j)T} = 0. We also assume each noise sequence is white in the sense E{w(i)w(j)T} = E{v(i)v(j)T} = 0, for all i ≠ j. The KF provides a recursive linear estimation of x(k) under the minimum variance criterion based on the observation of the measurement y(k). Let xˆ (k) denote the optimum filter state estimate of x(k) given measurements up to and including y(k), while x + (k) denotes the optimum predicted state estimate of x(k) given measurement up to and including y(k – 1). Then the n × n optimum estimation error covariance matrix is given by P(k) = E{(x(k) – xˆ (k))(x(k) – xˆ (k))T}, while the minimum estimation error variance is given by J(k) = Trace {P(k) = E{(x(k) – xˆ (k))T (x(k) – xˆ (k))}. The n × n optimum prediction error covariance matrix is given by P+(k) = E{x(k) – x+(k))(x(k) – x+(k))T}.

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The original KF recursively updates the optimum error covariance and the optimum state estimate vector by using two sets of update equations. Thus, it is often called the covariance KF. The time update equations for k = 1, 2, …, are given by x+(k) = A(k – 1)xˆ (k – 1) + B(k – 1)u(k – 1) and P+(k) = A(k – 1) P(k – 1)AT (k – 1) + W(k – 1). The n × n Kalman gain matrix K(k) is given by K(k) = P+(k)CT(k)[C(k)P+(k)CT(k) + V(k)]–1. The measurement update equations are given by xˆ (k) = x+(k) + K(k)(y(k) – C(k)x+(k)) and P(k) = P+(k) – K(k)P+(k). The first equation shows the update relationship of xˆ (k) to the predicted state estimate x+(k), for x(k) based on {L, y(k – 2), y(k – 2), y(k – 1)}, when the latest observed value y(k) is available. The second equation shows the update relationship between P(k) and P+(k). Both equations depend on the K(k), which depends on the measurement coefficient matrix C(k)and the statistical property of the measurement noise, covariance matrix V(k). Furthermore, K(k) involves an m × m matrix inversion. Other Forms of Kalman Filtering The basic KF algorithm considered above is called the covariance form of KF because the algorithm propagates the prediction and estimation error covariance matrices P+ (k) and P(k). Many versions of the KF are possible, characterized partially by the nature of the propagation of these matrices. Ideally, under infinite precision computations, no difference in results is observed among different versions of the KF. However, the computational complexity and the systolic implementation of different versions of the KF are certainly different. Under finite precision computations, especially for small numbers of bits under fixed point arithmetics, the differences among different versions can be significant. In the following discussions we may omit the deterministic control vector u(k) because it is usually not needed in many problems. In the following chol (.) qr(.), and triu (.) stand for Cholesky factor, QR decomposition, and triangular factor, respectively. 1. Information Filter. The inverse of the estimation error covariance matrix P(k) is called the information matrix and is denoted by PI(k). A KF can be obtained by propagating the information matrix and other relevant terms. Specifically, the information filter algorithm is given by time updates for k = 1, 2, …, of L(k) = A–T(k – 1)PI(k – 1)A–1(k – 1) × [W–1(k – 1) + A–T(k – 1)PI(k – 1) A–T(k – 1)]–1, d+(k) = (I – L(k)A–T(k – 1)PI(k – 1)A–1(k – 1). The measurements updates are given by d(k) = d+(k) + CT(k)V–1(k)y(k)PI(k) = PI+(k) + CT(k)V–1(k)C(k). 2. Square-Root Covariance Filter (SRCF). In this form of the KF, we propagate the square root of P(k). In this manner, we need to use a lower dynamic range in the computations and obtain a more stable solution under finite precision computations. We assume all three relevant covariance matrices are positive-definite and have the factorized form of P(k) = ST(k)S(k), W(k) = S WT (k)SW(k), V(k) = ST(k)Sv(k). In particular, S(k) = chol(P(k)), SW (k) = chol(W(k)), SV(k) = chol(V(k)), are the upper triangular Cholesky factorizations of P(k), W(k), and V(k), respectively. The time updates for k = 1, 2, …, are given by x+(k) = A(k – 1) xˆ (k – 1), U(k) = triu(qr([S(k – 1)AT(k – 1); SW(k – 1)])), P+s(k) = U(k)(1:n; 1:n). The measurement updates are given by P+(k) = P+Ts (k)P+s(k),/,K(k) = P+(k)C+(k)[C(k)P+(k)C+(k)+V(k)]–1, xˆ (k) + K(k)(y(k) – C(k)x+(k)),Z(k) = triu(qr([Sv (k), 0mn ; P+s(k)C+(k), P+s(k)])) and S(k) = Z(k)(m + 1: m + n, m + 1: m + n). 3. Square-Root Information Filter (SRIF). In the SRIF form of the KF, we propagate the square root of the information matrix. Just as in the SRCF approach, as compared to the conventional cova­ riance form of the KF, the SRIF approach, as compared to the SRIF approach, needs to use a lower dynamic range in the computations and obtain a more stable solution under finite precision computations. First, we denote SI(k) = (chol (P(k)))–1, SIW (k) = (chol(W(k)))–1, and SIV (k) = (chol(V(k)))–1. The time updates for k = 1, 2,…, are given by U(k) = triu(qr([SIW(k – 1), 0n×n, 0n×1 ; SI(k – 1)A–1(k – 1), SI(k – 1)A–1(k – 1), b(k – 1)])), P+S (K) = U(k)(n + 1:2n, n + 1:2n) and b+(k) = U(k)(n + 1: 2n, 2n + 1). The measurement updates are given by Z(k) = triu(qr([P+S (k),b+(k); SIV (k)C(k), SIV (k)y(k)]))SI(k) = Z(k)(1:n, 1:n), and b(k) = Z(k)(1: n, n + 1). At any iteration, xˆ (k) and P(k) are related to b(k) and SI(k) by xˆ(k) = SI(k)b(k) and P(k) = (SIT(k)SI(k))–1.

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Systolic Matrix Implementation of the KF Predictor The covariance KF for the optimum state estimate xˆ(k) includes the KF predictor x+(k) In particular, if we are only interested in x+(k) a relatively simple algorithm for k = 1, 2, …, is given by K(k) = P+(k)C T(k)[C(k)P+(k)C T(k) + V(k)]–1, x+(k + 1) = A(k) x+(k) + A(k) K(k) [y(k) – C(k)x+ (k)] and P+(k + 1) = A(k) P+(k)AT(k) – A(k)K(k)C(k)P+(k)AT(k) + W(k). To start this KF prediction algorithm, we use xˆ(0) and P(0) to obtain x+(1) = A(0)xˆ(0) and P+(1) = A(0)P(0)AT(0) + W(0). The above operations involve matrix inverse; matrix-matrix and matrix-vector multiplications; and matrix and vector additions. Fortunately, the matrix inversion of α = C(k)P+(k)C T(k) + V(k) can be approximated by the iteration of β(i + 1) = β(i)[2I – αβ(i), i = 1, …, I. Here, β(i) is the ith iteration estimate of the inverse of the matrix α. While the preceding equation is not valid for arbitrary α and β(i), for KF applications, we can use I = 4 because a good initial estimate β(1) of the desired inverse is available from the previous step in the KF. Clearly, with the use of the above equation for the matrix inversion, all the operations needed in the KF predictor can be implemented on an orthogonal array using systolic matrix operations of the form D = B × A + C, as shown in Fig. 61.113. cmn

c2n

c1n

cm2

c22 cm1

bn1

0

0

0

0

c12

0

b21

b32

c21

c11

b11

b22

a11

b12

a12

a21

b2n

a22

b1n

a1m aout cin

cout

b

cout

b ain + cin

aout

ain

an1

~ a 11

a2m

~ a 12

~ a 21

ain

bnn

~ a 22

~ a in

an2

anm

~ a n1 ~ a 2n

~ a n2

~ a nn

FIGURE 61.113 Systolic matrix multiplication and addition of B × A + C. © 2003 by CRC Press LLC

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TABLE 61.14 Systolic Matrix Operations of a KF Predictor Step 1 2 3 4 5 6 7 8 9 10 11 12 13

B P+(k) P+(k) C(k) α β(i) P+(k) CT(k) A(k) A(k) –C(k) A(k)K)(k) A(k)K(k) n–3 A(k) – A(k)K(k)C(k)

A T

C T

D

Time

C (k) AT(k) P+(k) CT(k) –β(i) 2I – αβ(i) β K(k) x+(k) x+(k) –C(k) y(k) – C(k)x+(k)

0 0 V(k) 2I 0 0 0 0 y(k) A(k) A(k)x+(k)

P+(k) C (k) P+(k) AT(k) C(k)P+(k) CT(k) + V(k) = α 2I – αβ(i) β(i + 1) K(k) A(k)K(k) A(k)x+(k) y(k) – C(k)x+(k) A(k) – A(k)K(k)C(k) x+(k + 1)

n+m n 2m 2Im 2Im n+m n+m 1 m+1 2n 1

P+(k) AT(k)

W(k)

P+(k)

2n

The recursive algorithm of the KF predictor is decomposed as a sequence of matrix multiplications, as shown in Table 61.14. In step 1 the n × n matrix P+(k) and the m × n matrix C T(k) are denoted as B and A, respectively. The rows of B (starting from the n, n – 1, …,1 row) are skewed and inputted to the n x n array starting at time 1. By time n (as shown in Fig. 61.113), all the elements of the first column of B (i.e., bn1, …, b11) are in the first column of the array. At time n + 1, …, 2n – 1, elements of the second to nth columns of B are inputted to the array and remain there until the completion of the BA matrix multiplication. At time n + 1, a11 enters (1,1) cell and starts the BA process. At time n + m, a1m enters the (1,1) cell. Of course, additional times are needed for other elements in the second to the nth rows of A to enter the array. Further processing and propagation times are needed before all the elements of D = BA = P+(k)C T(k) are outputted. However, in step 2, because B remains as P+(k), we do not need to input it again, but only append A(k) (denote as A˜ in Fig. 61.113) in the usual skewed manner after the previous A = C T(k). Thus, at time n + m + 1, a˜11 enters the (1, 1) cell. By time n + m + n, a˜1n enters the (1, 1) cell. Thus, step 1 takes n + m time units, while step 2 takes only n time units. In step 3 m time units are needed to load C(k) and m time units are needed to input P+(k)C T(k), resulting in 2m time units. Steps 4 and 5 perform one iteration of the inverse approximation. In general, I = 4 iterations is adequate, and 16m time units are needed. Thus far, all the matrices and vectors are fed continuously into the array with no delay. However, in order to initiate step 13, the (n, 1) component of (A(k) – A(k)K(k)C(k) is needed, but not available. Thus, at the end of step 11, an additional (n – 3) time units of delay must be provided to access this component. From Table 61.14, a total of 9n + 22m time units is needed to perform one complete KF prediction iteration. Systolic KF Based on the Faddeev Algorithm A form of KF based on mixed prediction error covariance P+(k) and information matrix PI (k) = P –1(k) ˆ – 1) + updates can be obtained from the covariance KF algorithm. For k = 1, 2, …, we have x+(k) = A(k – 1)x(k B(k – 1), P+(k) = A(k – 1)PI –1(k – 1)AT(k – 1) + W(k – 1), PI(k) = P+–1(k) + C T(k)V –1(k)C(k)K(k) = ˆ PI –1(k)C T(k)V –1(k) and xˆ (k) = x+(k) + K(k)(y(k) – C(k)x+(k)). The algorithm starts with the given x(0) and P(0), as usual. Because this algorithm requires the repeated use of matrix inversions for (PI(k – 1)), (P+(k))–1, (V(k))–1 as well as P(k) = (PI(k)) –1, the following Faddeev algorithm is suited for this approach. Consider an n x n matrix A, an n x m matrix B, a p x n matrix C, and a p x m matrix D arranged in the form of a compound matrix [A B; –C D]. Consider a p x n matrix W multiplying [A B] and added to [–C D], resulting in [A B;–C + WAD + WB]. Assume W is chosen such that –C + WA = 0, or W = CA–1. Then, we set D + WB = D + CA–1B. In particular, by picking {A, B, C, D} appropriately, the basic matrix operations needed above can be obtained using the Faddeev algorithm. Some examples are given by

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A

I

−I

0

I

B

−C

0

I

B

−C

D

A

B

−I

0

⇒ D + W B = A −1

⇒ D + W B = CB

⇒ D +W B = D +C B

⇒ D + W B = A −1B

A modified form of the previous Faddeev algorithm first triangularizes A with an orthogonal trans­ formation Q, which is more desirable from the finite precision point of view. Then, the nullification of the lower left portion can be performed easily using the Gaussian elimination procedure. Specifically, applying a QRD, Q[A B] = [R QB]. Then, applying the appropriate W yields R   −C + W Q A

 R  =   0 D + W Q B QB

  D + C A −1B QB

(61.24)

The preceding mixed prediction error covariance and information matrix KF algorithm can be refor­ mulated as a sequence of Faddeev algorithm operations, as given in Table 61.15. The times needed to perform steps 2, 3, 4, and 6 are clearly just the sum of the lengths of the two matrices in the corresponding steps. Step 1 requires only n times unit to input the second row of matrices because xˆ (k − 1) is already located in the array from the previous iteration (step 8 output) and one time unit to output x+(k). Due to the form of [–I 0] in step 4, C(k) of step 5 can be inputted before the completion of P+−1(k) in step 4. Thus, only n time units are needed in step 5. Similarly, x+(k) of step 7 can be inputted in step 6. Thus, we need TABLE 61.15 Faddeev Algorithm Solution to KF Step

© 2003 by CRC Press LLC

Compound Matrix

D + WB

Time

1

I − A(k −1)

xˆ (k − 1) B(k – 1)u(k –1)

x + (k)

n+1

2

P –1(k – 1) −A(k – 1)

A T (k – 1) W (k – 1)

P+ (k)

2n

3

V (k – 1) −C T (k)

I 0

C T (k)V −1(k – 1)

m+n

4

P+ (k) −I

p+−1(k)

2n

5

I −C T (k)V –1(k)

P −1(k)

n

6

P −1(k) −I

K(k)

2n

7

I C (k)

y(k) − C(k)x + (k)

m+1

8

I −K (k)

xˆ (k)

m+1

I 0 C (k) P+–1(k)

C T (k + 1)V −1(k) 0 x + (k) y(k) y(k)−C (k)x + (k) x + (k)

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only m + 1 time units to input [C(k) y(k)] and complete its operations. In step 8 only m + 1 time units are needed as in step 1. Thus, a total of 9n + 3m + 3 time units are needed for the Faddeev algorithm approach to the KF. Other Forms of Systolic KF and Conclusions While the operations of a KF can be expressed in many ways, only some of these algorithms are suited for systolic array implementations. For a KF problem with a state vector of dimension n and a measure­ ment vector of dimension m, we have shown the systolic matrix-matrix multiplication implementation of the predictor form of the KF needs 9n + 22m time steps for each iteration. A form of KF based on mixed update of prediction error covariance and information matrices is developed based on the Faddeev algorithm using matrix-matrix systolic array implementation. It has a total of 9n + 3m + 3 time steps per iteration. A modified form of the SRIF algorithm can be implemented as a systolic array consisting of an upper rectangular array of n(n + 1)/2 internal cells, and a lower n-dimensional triangular array of n boundary cells, and (n – 1)2/2 internal cells, plus a row of n internal cells, and (n – 1) delay cells. It has a total of n-boundary cells, ((n – 1)2 + 2n2 + 2n)/2 internal cells, and (n – 1) delay cells. Its throughput rate is 3n time steps per iteration. A modified form of the SRCF algorithm utilizing the Faddeev algorithm results in a modified SRCF form of a KF consisting of a trapezodial section, a linear section, and a triangular section systolic array. The total of these three sections needs (n + m) boundary cells, n linear cells, and ((m – 1)2 + 2nm + (n – 1)2)/2 internal cells. Its throughput rate is 3n + m + 1 time steps per iteration. The operations of both of these systolic KF are quite involved and detailed discussions are omitted here. In practice, in order to compare different systolic KFs, one needs to concern oneself not only with the hardware complexity and the throughput rate, but other factors involving the number of bits needed finite precision computations, data movement in the array, and I–O requirements as well.

Eigenvalue and Singular Value Decompositions Results from linear algebra and matrix analysis have led to many powerful techniques for the solution of wide range of practical engineering and signal processing problems. Although known for many years, these mathematical tools have been considered too computationally demanding to be of any practical use, especially when the speed of calculation is an issue. Due to the lack of computational power, engineers had to content themselves with suboptimal methodologies of simpler implementation. Only recently, due to the advent of parallel/systolic computing algorithms, architectures, and technologies, have engi­ neers employed these more sophisticated mathematical techniques. Among these techniques are the socalled eigenvalue decomposition (EVD) and the singular value decomposition (SVD). As an application of these methods, we consider the important problem of spatial filtering. Motivation–Spatial Filtering Problem Consider a linear array consisting of L sensors uniformly spaced with an adjacent distance d. A number M, M < L, of narrowband signals of center frequency f0, impinging on the array. These signals arrive from M different spatial direction angles θ1, …, θM , relative to some reference direction. Each sensor is provided with a variable weight. The weighted sensor outputs are then collected and summed. The goal is to compute the set of weights to enhance the estimation of the desired signals arriving from directions θ1, …, θM. In one class of beamformation problems, one sensor (sometimes referred to as main sensor) receives the desired signal perturbed by interference and noise. The remaining L – 1 sensors (auxiliary sensors) are mounted and aimed in such a way as to collect only the (uncorrelated) interference and noise components. In this scenario the main sensor gain is to be kept at a fixed value, while the auxiliary weights are adjusted in such a way as to cancel out as much perturbation as possible. Obviously, the only difference of this latter cast is that one of the weights (the one corresponding to the main sensor) is kept at a constant value of unity. Let the output of the ith sensor, i = 1, …, L, at discrete time n = 0, 1, …, be given by

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Digital Systems

{[

]

j 2 πf n x i (n) =  x i (n) + v i (n) e ( 0 )

}

x i (n) = ai (n)

M

∑ S (n)e k

j 2π ( i−1)d sinθk λ

k=1

where ai (n) is the antenna gain at time n, Sk is the complex amplitude of the kth signal, inclusive of the initial phase, and λ is the signal wavelength. The vectors xi(n) and vi(n) are analytic signal representations. The noise vi(n) is assumed to be uncorrelated white and Gaussian, of power σN2 . In order to avoid the ill effects of spatial aliasing, let us also assume that d ≤ λ/2. The outputs of the sensor array for times n = 0, 1, …, N, can be collected in matrix form as follows: X = S = A +V { { { { N ×L

N ×M

M ×L

N ×L

The matrix A is referred to as the steering matrix. In the case in which ai (n) = 1 for all i, the matrix A is Vandermonde and full rank, and its kth row can be expressed as A(θ) = (1, e j2πdsin θ/λ, …, e j2π(L–I)dsin θk /λ). The data correlation matrix, RX = E{XH X}, where E(·) is the ensemble average operator, is equal to RX = AHRs A + σN2 I, Rs = E{SH S}. We note: 1. The matrix Rs has rank M by definition as does the matrix AH Rs A. 2. The rows of A are in the range space of RX . 3. The value σN2 is an eigenvalue of RX with multiplicity L – M, given the det (RX – σN2 I) = 0, and the rank of AH Rs A is M. The eigenvalue decomposition of RX can therefore be written as RX = VS ΛSVSH + σ 2NVNVNH, where VS is L × M, VN is L x (L – M), VSHVS = I and VNHVN = 1, and VSHVN = 0. Moreover, we have that AVN = 0. Let A(θ) be a generic steering vector, defined as A(θ) ≡ (1, e j2πdsin θ/λ, …, e j2π(L–I)dsin θ/λ). Then, the function (θ) = 1/A(θ)VN  2 has M poles at the angles θ = θk k = 1, …, M. Alternatively, any linear combination, w, of the columns of VN is such that E{|| Xw ||2 } = minz E{|| Xz ||2 } = σN. In other words, the signals impinging from angular directions θ1, …, θM are totally canceled out in the system output. The desired weighting vector for our spatial filtering problem can consequently be expressed as w = VN p, p = [p1, …, pL–M]T , for any nonzero vector p. From the above discussion, we see that the solution to the original spatial filtering problem can be obtained from the eigenvalue decomposition of the correlation matrix RX = E{X HX}. In practice the sample correlation matrix Rˆ X is used instead, where the ensemble average is replaced by a suitable temporal average. The computation of the covariance matrix implies the computation of the matrix product X H X. Some small elements in X are then squared and the magnitude of the resulting element can become comparable or smaller than the machine precision. Rounding errors can often impair and severely degrade the computed solution. In these cases it is better to calculate the desired quantities (correlation eigenvalues and eigenvectors) directly from the data matrix X using the SVD technique as considered next. Eigenvalue Decomposition of a Symmetric Matrix Consider an L × L real symmetric matrix A = AT. In the previous spatial filtering example, A = RX . Let i i  I i−1    G(i, j , θ) =     j 

© 2003 by CRC Press LLC

j

c

s I j −i −1

−s

c

        I L − j 

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be an orthogonal Givens rotation matrix, where c = cos θ and s = sin θ. Pre- or postmultiplication of A by G leaves A unchanged, except for rows (columns) i and j, which are replaced by a linear combination of old rows (columns) i and j. A Jacobi rotation is obtained by simultaneous pre- and postmultiplication of a matrix by a Givens rotation matrix, as given by G(i, j, θ)T AG(i, j, θ), where θ is usually chosen in order to zero out the (i, j) and (j, i) entries of A. The matrix A can be driven toward diagonal form by iteratively applying Jacobi rotations, as given by A0 ← A, Ak+1 ← GkT AGk, where Gk is a Givens rotation matrix. A sweep is obtained by applying L(L – 1)/2 Jacobi rotations, each nullifying a different pair of off-diagonal elements, according to a prespecified order. Given the matrix Ak = (a(pqk )) at the kth iteration, and a pair of indices (i, j), the value of tan θ can be obtained from the following equations: u=

a(jjk ) − aii(k ) 2aij(k )

tan θ =

sign(u) u + 1 + u2

(61.25)

It is possible to demonstrate that each Jacobi rotation reduces the matrix off-norm. The matrix Ak indeed tends to diagonal form and for all practical purposes it reaches it after  (log L) sweeps. The matrix V of eigenvectors is obtained by applying the same rotations to a matrix initialized to the identity, as follows: V0 ← I, Vk+1 ← VkGk . A two-dimensional systolic array implementation of the previ­ ous algorithm is shown in Fig. 61.114, for the case L = 8. At the beginning of iteration k, processor Pij contains elements  a(k ) 2i−1, 2 j −1   a(k )  2i , 2 j –1

a2(ki−) 1, 2 j   a2(ki ,)2 j 

i, j = 1, 2, …, L 2 ,

The diagonal processors compute the rotation parameters and apply the rotation to the four entries they store. Subsequently, they propagate the rotation parameters horizontally and vertically to their neighbors, which, upon receiving them, apply the corresponding rotation to their stored entries. After the rotation is applied, each processor swaps its entries with its four neighbors along the diagonal connections. The correct data movement at the edges of the array is also shown in Fig. 61.114. A correct scheduling of operations requires that each processor be idle for two out of three time steps, which translates into an efficiency of 33%. Each sweep takes 3 (L – 1) time steps, and the number of sweeps can be chosen on the order of log L.

P11

P12

P13

P14

P22

P22

P23

P24

P31

P32

P33

P34

P41

P42

P43

P44

FIGURE 61.114 Systolic array for an EVD of a symmetric matrix based on Jacobi rotations.

© 2003 by CRC Press LLC

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1985

Digital Systems

Singular Value Decomposition of a Rectangular Matrix via the Hestenes Algorithm Consider an N × L real matrix A, N ≥ L. Its SVD can be written as follows: T A =U { { ∑ { {V

N ×L

N ×L L×L L×L

where U and V have orthonormal columns. The matrix ∑ = diag(σ1 , ...., σ L ) is the diagonal matrix of singular values, where σ1 ≥ σ2 ≥ … ≥ σL ≥ 0. Consider the following recursion A0 ← A, Ak+1 ← AkGk , where the Givens rotations are chosen not to zero out entries of Ak , but to orthogonalize pairs of its columns. A sweep is now defined as a sequence of Givens rotations that orthogonalize all  L2 pairs of columns exactly once. Observe the similarity with the algorithm described previously for the calculation of eigenvalues and eigenvectors. If G(i, j, θ) is the Givens rotation which orthogonalizes columns i and j of A, then G(i, j, θ)T MG(i, j, θ) is the Jacobi rotation that zeroes out the entries (i, j) and (j, i) of M = AT A. A sweep (as defined here) of rotations applied to the rectangular matrix A corresponds exactly to a sweep (as defined earlier) of rotations applied to the symmetric matrix M. At any time step, the original matrix A can be expressed as follows: k

A = AkVkT Vk =

∏G

k

i=1

where Vk has orthonormal columns for any k (by definition of Givens rotations). After a number of sweeps (on the order of log L) the matrix Ak approaches a matrix, W, of orthogonal columns, Ak → W, Vk → V. If σi is the norm of the ith column of W, i = 1, …, L, then we have W = U diag (σ1, …, σL), A = U ΣV T. This SVD approach based on the Hestenes algorithm can be realized on a Brent-Luk [58] linear systolic array, as shown in Fig. 61.115, for the case L = 8. Each processor stores a pair of columns; in particular, the procedure starts by storing columns 2 k – 1 and 2k in processor Pk. Each processor computes the rotation parameters which orthogonalize the pair of columns. Let x and z be the two stored columns. Let ξ and ζ be their norms, and η be their inner product. Then the value of tan θ from u=

ζ−ξ 2η

tan θ =

sign(u) | u | + 1 + u2

After applying the computed rotation, each processor swaps its pair of columns with the two neighboring processors along the connections shown in Fig. 61.115. The column indices stored in each processor at the different steps of a single sweep are given in Table 61.16. Note that all the  L2 pairs of indices are generated by using the Brent–Luk scheme. The stopping criteria can be set in advance. A possible criterion is by inspecting the magnitude of the rotating angles. When they are all in absolute value below a given threshold, then the algorithm can stop. More commonly, a predetermined number of sweeps is chosen ahead of time. Observation shows that a number of sweeps on the order of log L is sufficient for convergence.

P1 P2

P3 P4

P5 P6

P7 P8

FIGURE 61.115 Linear systolic array for SVD of a rectangular matrix based on the Hestenes algorithm.

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TABLE 61.16 Movement of Matrix

Columns during One Sweep (L = 8)

P1

P2

P3

P4

(1, 2) (1, 4) (1, 6) (1, 8) (1, 7) (1, 5) (1, 3) (1, 2)

(3, 4) (2, 6) (4, 8) (6, 7) (8, 5) (7, 3) (5, 2) (3, 4)

(5, 6) (3, 8) (2, 7) (4, 5) (6, 3) (8, 2) (7, 4) (5, 6)

(7, 8) (5, 7) (3, 5) (2, 3) (4, 2) (6, 4) (8, 6) (7, 8)

Singular Value Decomposition of a Rectangular Nonsymmetric Matrix via the Jacobi Algorithm The SVD algorithm described in the previous section has the drawback of a somewhat complicated updating procedure. In many signal processing applications, continuous updating of the matrix decom­ position as new samples are appended to the data matrix is required. Such problems occur in spectral analysis, direction-of-arrival estimation, beam forming, etc. An efficient updating procedure for the SVD of rectangular matrices of growing row size is given by the algorithm described in this section, based on the succession of two basic operations: a QR updating step, followed by a rediagonalization operation. This algorithm is otherwise known as a version of the Kogbetliantz algorithm for triangular matrices. Given the m × L data matrix at time m, Am = [a1, …, am]T, where ai , i = 1, …, m are the rows of Am , one defines the exponentially weighted matrix Bm (β) Am , where Bm (β) is the diagonal forgetting matrix Bm (β) ≡ diag (βm–1, βm–2, …, β, 1), and 0 < β ≤ 1 is the forgetting factor. The updating problem is to determine the SVD of the updated weighted matrix Bm+1 (β) Am+1 , given the SVD at time m, Bm (β) Am = U m ∑ m Vm Often only the singular values and right singular vectors are of interest. This is fortunate because the left singular matrix grows in size as time increases, while the sizes of Σm and Vm remain unchanged. The algorithm can be summarized as follows. Given the matrices Vm and Σm and the new data sample xm+1,  β ∑m  ∑ ′m ←   Vm′ ← Vm ,  x m+1 Vm  the QR updating step  ∑′m    ← Qm+1 ∑′m  0  the rediagonalization using permuted Jacobi rotations for k = 1, …, 1,

for i = 1, …, n – 1, j = i + 1,

∏ G(i, j, θ) ∑′ G(i, j, φ) ∏ , V ′ ← V ′ G(i, j, φ) ∏ . ∑ ′m ←

T

m

ij

T

m

end © 2003 by CRC Press LLC

m

ij

ij

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Digital Systems

1987

end

∑m+1 ← ∑′m ,

Vm+1 ← Vm′ .

In the preceding algorithm, the parameter l determines both the number of computations between subsequent updates and the estimation accuracy at the end of each update step. When l is chosen equal to the problem order L, then one complete sweep is performed. In practice, the l parameter can be chosen as high as ~10L (usually for block computations or slow updates) and as small as 1 (for very high updating rates, with understandable degradation of estimation accuracy). The matrices Σm and Σ m′ are upper triangular at all times. This is ensured by the application of the permuted left and right Givens rotations in the rediagonalization step. After the application of any Jacobi rotation, the rotated rows and columns are subsequently permuted. This expedient not only preserves the upper triangularity of the Σ-matrices, but also makes it possible for the rotations to be generated on the diagonal and propagated along physically adjacent pairs of rows and columns. All these features make this algorithm a very attractive candidate for a systolic implementation. A schematic diagram of the systolic array proposed by Moonen et al. [63] is shown in Fig. 61.116, where the triangular array stores the matrices square array Σm and Σ m′ , for all m, and the square array stores the V-matrix. The input incoming data samples, xm+1, are input into the V-array, where the vector­ by-matrix multiplication xm+1 Vm is performed. The output is subse­ triangular quently fed into the triangular array. As it propagates through the array, array the QR updating step is carried on: left rotations are generated in the diagonal elements of the array and propagated through the corresponding rows of the Σ-matrix. One does not need to wait for the completion of the QR step to start performing the Jacobi rotations associated with the FIGURE 61.116 Two-dimen­ diagonalization step. It is known that the two operations (QR update and sional systolic array for updat­ diagonalization) can be interleaved without compromising the final ing the Jacobi SVD algorithm result. The parameters relative to the left rotations are, as before, propa- for a nonsymmetric matrix. gated along the rows of the triangular matrix, while the right rotation parameters move along the columns of Σm , and are passed on to the V-array. Due to the continual modification of the matrix Vm caused by these right rotations, and because of the use of finite precision arithmetic, the computed right singular matrix may deviate from orthogonality. It is also known that in a realistic environment the norm of Vm VmT – I grows linearly with m. Reorthogonalization procedures must therefore be included in the overall scheme. A complicated reorthogonalization procedure based on left rotations, which interleaves with the other operations, was described in Moonen et al. [63]. An improved reorthogonalization algorithm was proposed by Vanpoucke and Moonen [66], where the matrix Vm is stored in parametrized form, thereby guaranteeing orthogonality at all times. The resulting trian­ gular array and its modes of operation were also described.

References [1] A. Darte and J. M. Delosme, “Partitioning for Array Processors,” Tech. Rep. LIP-IMAG 90-23, Laboratoire de l’Informatique du Parallélisme, Ecole Supérieure de Lyon, Oct. 1990. [2] H. T. Kung and C. E. Leiserson, “Systolic Arrays (for VLSI),” in Introduction to VLSI Systems, C. A. Meads and L. A. Conway, Eds. Reading, MA: Addison-Wesley, 1980, chap. 8.3. [3] H. T. Kung, “Why systolic architecture?” Computer, vol. 15, pp. 37–46, 1982. [4] S. Y. Kung, K. S. Arun, R. J. Gal-Elzer, and D. V. B. Rao, “Wavefront Array Processor: Language, Architecture, and Applications,” IEEE Trans. Comput., vol. 31, pp. 1054–1066, 1982. [5] S. Y. Kung, VLSI Array Processing Englewood Cliffs, NJ: Prentice Hall, 1988. [6] F. Lorenzelli, “Systolic Mapping with Partitioning and Computationally Intensive Algorithms for Signal Processing,” Ph.D. thesis, University of California, Los Angeles, 1993. © 2003 by CRC Press LLC

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[7] D. I. Moldovan, “On the Analysis and Synthesis of VSLI Algorithms,” IEEE Trans. on Comput., vol. 31, pp. 1121–1126, 1982. [8] M. Newman, Integral Matrices, New York: Academic Press, 1972. [9] P. Quinton, “The Systematic Design of Systolic Arrays,” IRISA Tech. Report 193, April 1983. [10] S. Rao,“Regular Iterative Algorithms and Their Implementations on Processor Arrays,” Ph.D. thesis, Stanford, CA: Stanford University, 1985. [11] E. Angelidis and J. E. Diamessis, “A Novel Method for Designing FIR Filters with Nonuniform Frequency Samples,” IEEE Trans. Signal Process., vol 42, pp. 259–267, 1994. [12] S. Chanekar, S. Tantaratana, and L.E. Franks, “Multiplier-Free IIR Filter Realization Using Periodically Time-Variable State-Space Structures, I and II,” IEEE Trans, Signal Process., vol. 42, pp. 1008–1027, 1994. [13] L. A. Ferrari and P. V Sankar, “Minimum Complexity FIR Filters and Sparse Systolic Arrays,” IEEE Trans. Comput., vol 37, pp. 760–764, 1988. [14] A. Jayadeva, “A New Systolic Design for Digital IIR Filters,” IEEE Trans. Circuits Syst., vol. 37, pp. 653–654, 1990. [15] S. C. Knowles, J. G. McWhirter, R. F. Woods, and J. V. McCanny, “Bit-Level Systolic Architectures for High Performance IIR Filtering,” J. VLSI and Signal Process., vol. 1, pp. 9–24, 1989. [16] S. M. Lei and K. Yao, “A Class of Systolizable IIR Digital Filters and Its Design for Proper Scaling and Minimum Output Roundoff Noise,” IEEE Trans. Circuits Syst., vol. 37, pp. 1217–1230, 1990. [17] S. M. Lei and K. Yao, “Efficient Systolic Array Implementation of IIR Digital Filtering,” IEEE Trans. Circuits Syst., vol. 39, pp. 581–584, 1992. [18] H. H Loomis Jr. and B. Sinha, “High-Speed Recursive Digital Filter,” Circuits, Syst. Singal Process., vol. 3, pp. 267–294, 1984. [19] K. K. Parhi and D. G. Messerschmitt, “Pipeline Interleaving and Parallelism in Recursive Digital Filters. I. Pipelining Using Scattered Look-Ahead and Decomposition,” IEEE Trans. Acoust. Speech Signal Process, vol. 37, pp. 1099–1117, 1989. [20] N. R. Shanbhag and K. K. Parhi, Pipelined Adaptive Digital Filters, Boston: Kluwer Academic, 1994. [21] R. F. Woods and J. V. McCanny, “Design of High Performance IIR Digital Filter Chip,” IEEE Proc. E, Comput. Digital Tech., vol. 139, pp. 195–202, 1992. [22] C. W. Wu and J.-C. Wang. “Testable Design of Bit-Level Systolic Block FIR Filters,” Proc. IEEE Int. Symp. Circuits Syst., pp. 1129–1132, 1992. [23] R. Wyrzykowski and S. Ovramenko,“Flexible Systolic Architecture for VLSI FIR Filters,” IEEE Proc. E, Comput. Digital Tech., vol. 139, pp. 170–172, 1992. [24] L. W. Chang and J. H. Lin, “A Bit-Level Systolic Array for Median Filter,” IEEE Trans. Signal Process., vol. 40, pp. 2079–2083, 1992. [25] J. M. Delosme, “Bit-Level Systolic Array for Real Symmetric and Hermitian Eigenvalue problems,” J. VLSI Signal Process., vol. 4, pp. 69–88, 1992. [26] R. A. Evans, J. V. McCanny, J. G. McWhirter, A. Wood, and K. W. Wood, “A CMOS Implementation of a Systolic Multibit Convolver Chip,” Proc. VLSI, pp. 227–235, 1983. [27] G. Fettweis and H. Meyr, “High-Rate Viterbi Processor: A Systolic Array Solution,” IEEE J. Sel. Topics Commun., vol. 8, pp. 1520–1534, 1990. [28] S. C. Knowles, J. G. McWhirter, R. F. Woods, and J. V. McCanny, “Bit-Level Systolic Architectures for High Performance IIR filtering,” J. VLSI Signal Process., vol. 1, pp. 9–24, 1989. [29] J. V. McCanny and J. G. McWhirter, “On the Implementation of Signal Processing Function Using One Bit Systolic Arrays,” Elect. Lett., Vol. 18, pp. 241–243, 1982. [30] J. V. McCanny, J. G. McWhirter, and S. Y. Kung, “The Use of Data Dependence Graphs in the Design of Bit-Level Systolic Arrays,” IEEE Trans. Acoust., Speech Process., vol. 38, pp. 787–793, 1990. [31] J. V. McCanny, R. F. Woods, and M. Yan, “Systolic Arrays for High-Performance Digital Signal Processing,” in Digital Signal Processing: Principles, Device, and Applications, N. B. Jones and J. D. M. Watson, Eds, New York: Peter Peregrinus, 1990, pp. 276–302. [32] C. L. Wang, “An Efficient and Flexible Bit-Level Systolic Array for Inner Product Computation,” J. Chin. Inst. Eng., vol. 41, pp. 567–576, 1991. © 2003 by CRC Press LLC

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[33] C. W. Wu, “Bit-Level Pipelined 2-D Digital Filters Image Processing,” IEEE Trans. Circuits Syst. Video Technol., vol. 1, pp. 22–34, 1991. [34] M. G. Bellanger and P. A. Regalia, “The FLS-QR Algorithm for Adaptive Filtering: The Case of Multi-Channel Signal,” Signal Process, vol. 22, pp. 115–126, 1991. [35] J. M. Cioffi, “The Fast Adaptive ROTOR’S RLS Algorithm,” IEEE Trans. Acoust. Speech Signal Process., vol. 38, pp. 631–653, 1990. [36] W. M. Gentleman and H.T. Kung, Matrix Triangularization by Systolic Arrays,” Proc. SPIE, RealTime Signal Process, vol. 298, pp. 298–303, 1981. [37] S. Haykin, Adaptive Filter Theory, 2nd ed. Englewood Cliffs, NJ: Prentice Hall, 1991. [38] F. Ling and J. G. Proakis, “A Recursive Modified Gram-Schmidt Algorithm with Applications to Least-Squares Estimation and Adaptive Filtering,” IEEE Trans. Acoust. Speech Signal Process, vol. 34, pp. 829–836, 1986. [39] K. J. R. Liu, S. F. Hsieh, K. Yao, and C. T. Chiu, “Dynamic Range, Stability, and Fault Tolerant Capability of Finite-Precision RLS Systolic Array Based on Givens Rotations,” IEEE Trans. Circuits Systems, June, pp. 625–636, 1991. [40] K. J. R. Liu, S. F. Hsieh, and K. Yao, “Systolic Block Householder Transformation for RLS Alogrithm with Two-Level Pipelined Implementation,” IEEE Trans. Signal Process., vol. 40, pp. 946–958, 1992. [41] J. G. McWhirter, “Recursive Least-Squares Minimization Using a Systolic Array,” Proc. SPIE, RealTime Signal Process. VI, vol. 431, pp. 105–112, 1983. [42] J. G. McWhirter, “Algorithm Engineering in Adaptive Signal Processing,” IEEE Proc. F, vol. 139, pp. 226–232, 1992. [43] B. Yang and J. F. Böhme, “Rotation-Based RLS Algorithms: Unified Derivations, Numerical Prop­ erties, and Parallel Implementations,” IEEE Trans. Acoust. Speech Signal Process., vol. 40, pp. 1151–1167, 1992. [44] M. J. Chen and K. Yao, “On Realization of Least-Squares Estimation and Kalman Filtering by Systolic Arrays,” in Systolic Arrays, W. Moore, A. McCabe, and R. Urquhart, Eds. Bristol, U.K.: Adam Hilger, 1986, pp. 161–170. [45] F. Gaston, G. Irwin, and J. McWhirter, “Systolic Square Root Covariance Kalman Filtering,” J. VLSI Signal Process., pp. 37–49. 1990. [46] J. H. Graham and T. F. Kadela, “Parallel Algorithm Architectures for Optimal State Estimation,” IEEE Trans. Comput., vol. 34, pp. 1061–1068, 1985. [47] R. E. Kalman, “A New Approach to Linear Filtering and Prediction Problems,” J. Basic Eng., vol. 82, pp. 35–45, 1960. [48] P. G. Kaminiski, “Discrete Square Root Filtering: A Survey of Current Techniques,” IEEE Trans. Autom. Control, vol. 16, pp. 727–735, 1971. [49] S. Y. Kung and J. N. Hwang, “Systolic Array Design for Kalman Filtering,” IEEE Trans. Signal Process., vol. 39, pp. 171–182, 1991. [50] R. A. Lincoln and K. Yao, “Efficient Systolic Kalman Filtering Design by Dependence Graph Mapping,” in VLSI Signal Processing III, R. W. Brodersen and H. S. Moscovitz, Eds. New York: IEEE Press, 1988, pp. 396–407. [51] J. G. Nash and S. Hansen, “Modified Faddeev Algorithm for Matrix Manipulation,” Proc. SPIE, vol. 495, pp. 39–46, 1984. [52] C. C. Paige and M. A. Saunders, “Least Squares Estimation of Discrete Linear Dynamic Systems Using Orthogonal Transformation,” SIAM J. Numer. Anal., vol. 14, pp. 180–193, 1977. [53] G. M. Papadourakis and F. J. Taylor, “Implementation of Kalman Filters Using Systolic Arrays,” Proc. Int. Conf. Acoust., Speech and Signal Process., pp. 783–786, 1987. [54] P. Rao and M. A. Bayoumi, “An Algorithm Specific VLSI Parallel Architecture for Kalman Filter,” in VLSI Signal Processing IV, H. S. Moscovitz, K. Yao, and R. Jain, Eds. New York: IEEE Press, 1991, pp. 264–273. [55] T.Y. Sung and Y. H. Hu, “Parallel Implementation of the Kalman Filter,” IEEE Trans. Aero. Electr. Syst., vol. 23, pp. 215–224, 1987. © 2003 by CRC Press LLC

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[56] H. Yeh, “Systolic Implementation of Kalman Filters,” IEEE Trans. Acoust., Speech, and Signal Process., pp. 1514–1517, 1988. [57] E. Biglieri and K. Yao, “Some Properties of Singular Value Decomposition and Their Application to Signal Processing,” Signal Process., vol. 18, pp. 277–289, 1989. [58] R. Brent and F. T. Luk, “The Solution of Singular-Value and Symmetric Eigenvalue Problems on Multiprocessor Arrays,” SIAM J. Sci. Stat. Comput., vol. 6, pp. 69–84, 1985. [59] G. H. Golub and C. F. Van Loan, Matrix Computations, 2nd ed., Baltimore: Johns Hopkins Uni­ versity Press, 1989. [60] S. Haykin, Adaptive Filter Theory, 2nd ed. Englewood Cliffs, NJ: Prentice Hall, 1991. [61] M. R. Hestenes, “Inversion of Matrices by Biorthogonalization and Related Results,” J. Soc. Ind. Appl. Math., vol. 6, pp. 51–90, 1958. [62] F. T. Luk, “A Triangular Processor Array for Computing Singular Values,” Linear Algebra Appl., vol. 77, pp. 259–273, 1986. [63] M. Moonen, P. Van Dooren, and J. Vandewalle, “A Systolic Array for SVD Updating,” SIAM J. Matrix Anal. Appl., vol. 14, pp. 353–371, 1993. [64] R. O. Schmidt,“A Signal Subspace Approach to Multiple Emitter Location and Spectral Estimation,” Ph.D thesis, Stanford, CA: Stanford University, 1981. [65] G. W. Stewart, “A Jacobi-Like Algorithm for Computing the Schur Decomposition of a Nonher­ mitian Matrix,” SIAM J. Sci. Stat. Comput., vol. 6, pp. 853–864, 1985. [66] F. Vanpoucke and M. Moonen, “Numerically Stable Jacobi Array for Parallel Subspace Tracking,” Proc. SPIE, vol. 2296, 1994. [67] F. D. Van Veen and K. M. Buckley, “Beamforming: A Versatile Approach to Spatial Filtering,” IEEE ASSP Mag., vol. 5, pp. 4–24, 1988.

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62 Data Converters

62.1 Digital-to-Analog Converters

Bang-Sup Song University of California, San Diego

Ramesh Harjani University of Minnesota

Introduction • Basic Converter Design Issues • Converter Architectures • Techniques for High-Resolution Digital-toAnalog Converters • Sources of Conversion Errors • LowSpurious DAC Design Examples

62.2 Analog-to-Digital Converters Introduction • Nyquist Rate Converters • Oversampled Converters

62.1 Digital-to-Analog Converters Bang-Sup Song Introduction Digital-to-analog converters (DACs), referred to as decoders in communications terms, are devices by which digital processors communicate with the analog world. Although DACs are used as key elements in analog-to-digital converters (ADCs), they find numerous applications as stand-alone devices from CRT display systems and voice/music synthesizers to automatic test systems, waveform generators, dig­ itally controlled attenuators, process control actuators, and digital transmitters in modern digital com­ munications systems. The basic function of the DAC is the conversion of input digital numbers into analog waveforms. An N-bit DAC provides a discrete analog output level, either voltage or current, for every level of 2N digital words, {Di ; i = 0, 1,2, …, 2N – 1}, that is applied to the input. Therefore, an ideal voltage DAC generates 2N discrete analog output voltages for digital inputs varying from 000…00 to 111…11 as illustrated in Fig. 62.1 for the four-bit example. The output has a one-to-one correspondence with the input b b b  b Vout ( Di ) = Vref  N + N2−1 + L + N2−1 + N1   2 2 2 2 

(62.1)

where Vref is a reference voltage setting the output range of the DAC and bN bN–1,…,b1 is the binary representation of the input digital word Di. In the unipolar case, as shown, the reference point is 0 when the digital input D0 is 000…00, but in bipolar or differential DACs, the reference point is the midpoint of the full scale when the digital input is 100…00, and the range is defined from –Vref /2 to Vref /2. Although purely current-output DACs are possible, voltage-output DACs are common in most applications. Signal-to-Noise Ratio and Dynamic Range The resolution is a term used to describe a minimum voltage or current that a DAC can resolve. The fundamental limit of a DAC is the quantization noise due to the finite resolution of the DAC. IF the input digital word is N bits long, the minimum step that a DAC can resolve is Vref /2N. If output voltages

© 2003 by CRC Press LLC

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ANALOG OUTPUT

Vref

Vref

2

0 0000

1000

1111

DIGITAL INPUT

FIGURE 62.1 Transfer characteristics of a unipolar DAC.

are reproduced with this minimum step of uncertainty, an ideal DAC should have a maximum signalto-noise ratio (SNR) of 3 SNR = 22N ≈ 6N + 1.8(dB) 2

(62.2)

where SNR is defined as the power ratio of the maximum signal to the inband uncorrelated noise. For example, an ideal 16-bit DAC has an SNR of about 97.8 dB. The spectrum of the quantization noise is evenly distributed up to the Nyquist bandwidth (half the sampling frequency). Therefore, this inband quantization noise decreases by 3 dB when the oversampling ratio is doubled. This implies that when oversampled, the SNR within the signal band can be made lower than the quantization noise limited by (62.2). The resolution of a DAC is usually characterized in terms of SNR, but the SNR accounts only for the uncorrelated noise. The real noise performance is better represented by TSNR, which is the ratio of the signal power to the total inband noise, including harmonic distortion. Also, a slightly different term is often used in place of the SNR. The useful signal range or dynamic range is defined as the power ratio of the maximum signal to the minimum signal. The minimum signal is defined as the smallest input, for which the TSNR is 0 dB, while the maximum signal is the full-scale input. Therefore, the SNR of nonideal DACs can be lower than the ideal dynamic range because the noise floor can be higher with a large signal present. In practice, DACs are limited not only by the quantization noise, but also by nonideal factors such as noises from circuit components, power supply coupling, noisy substrate, timing jitter, insufficient settling, and nonlinearity.

Basic Converter Design Issues The performance of a DAC can be specified in terms of its linearity, monotonicity, and conversion speed. In most conventional DACs, except for the oversampling DACs the linearity and monotonicity are limited by how accurately the reference voltage/current is divided using passive/active components. Linearity Differential Nonlinearity. The output range of an N–bit DAC is equally divided into 2N small units, as shown in Fig. 62.1, and one least significant bit (LSB) change in the input digital word makes the analog © 2003 by CRC Press LLC

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Data Converters

output voltage change by Vref /2N. The differential nonlinearity (DNL) is a measure of the deviation of the actual DAC output voltage step from this ideal voltage step for 1 LSB. The DNL is defined as DNL =

Vout ( Di+1 ) − Vout ( Di ) − Vref 2N Vref 2N

, for i = 0,1,K, 2N − 2 (LSB)

(62.3)

and the largest positive and negative numbers are usually quoted to specify the static performance of a DAC. Integral Nonlinearity. The overall linearity of a DAC can be specified in terms of the integral nonlinearity (INL), which is a measure of deviation of the actual DAC output voltage from the ideal straight line drawn between two endpoints, 0 and Vref . Because the ideal output is i × Vref /2N for any digital input Di , the INL is defined as INL =

Vout ( Di ) − i × Vref 2N Vref 2N

, for i = 0,1,K, 2N −1 (LSB)

(62.4)

and the largest positive and negative numbers are usually quoted to specify the static performance of a DAC. However, several definitions of INL may result depending on how two endpoints are defined. In some DAC architectures the two endpoints are not exactly 0 and Vref . The nonideal reference point causes an offset error, while the nonideal full-scale range gives rise to a gain error. In most DAC applications, these offset and gain errors resulting from the nonideal endpoints do not matter, and the integral linearity can be better defined in a relative measure using a straight line linearity concept rather than the end point linearity in the absolute measure. The straight line can be defined as two endpoints of the actual DAC output voltages or as a theoretical straight line adjusted to best fit the actual DAC output characteristics. The former definition is sometimes called endpoint linearity, while the latter is called best straight line linearity. Monotonicity The DAC output should increase over its full range as the digital input word to the DAC increases. That is, the negative DNL should be < – 1 LSB for a DAC to be monotonic. Monotonicity is critical in most applications, in particular, in digital control applications. The source of nonmonotonicity is an inaccuracy in binary weighting of a DAC. For example, the most significant bit (MSB) has a weight of one half of the full range. If the MSB weight is smaller than the ideal value, the analog output change can be smaller than the ideal step Vref /2N when the input digital word changes from 0111…11 to 1000…00 at the midpoint of the DAC range. If this decrease in the output is > 1 LSB, the DAC becomes nonmonotonic. The similar nonmonotonicity can take place when switching the second or lower MSB bits in binaryweighted multi-bit DACs. Monotonicity is inherently guaranteed if an N–bit DAC is made of 2N elements for thermometer decoding. However, it is impractical to implement high-resolution DACs using 2N elements because the number of elements grows exponentially as N increases. Therefore, to guarantee monotonicity in practical applications, DACs have been implemented using either a segmented DAC or an integrator-type DAC. Oversampling interpolative DACs also achieve monotonicity using a pulse-density modulated bitstream converted into analog voltages by a lossy integrator or by a low-pass filter. Segmented Digital-to-Analog Converters. Applying a two-step conversion concept, a DAC can be made in two levels using coarse and fine DACs. The fine DAC divides one coarse MSB segment into fine LSBs. If one fixed MSB segment is subdivided to generate LSBs, matching among MSB segments creates a nonmonotonicity problem. However, if the next MSB segment is subdivided instead of the fixed segment, the segmented DAC can maintain monotonicity regardless of the MSB matching. This is called nextsegment approach. Unless the next segment approach is used to make a segmented DAC with a total M + N bits, the MSB DAC should have a resolution of M + N bits for monotonicity, while the LSB DAC © 2003 by CRC Press LLC

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1994

The Circuits and Filters Handbook, Second Edition

I out I dump Current Divider N bits M bits I ref 2M

I ref 2M

Segments of Output

I ref 2M

Next Segment

I ref 2M

I ref 2M

Segments Dumped

FIGURE 62.2 Segmented DAC for monotonicity.

requires an N–bit resolution. Using the next-segment approach, an MSB DAC made of 2M identical elements guarantees monotonicity, although INL is still limited by the MSB matching. To implement a segmented DAC using two resistor-string DACs, voltage buffers are needed to drive the LSB DAC without loading the MSB DAC. Although the resistor-string MSB DAC is monotonic, overall monotonicity is not guaranteed due to the offsets of the voltage buffers. The use of a capacitorarray LSB DAC eliminates a need for voltage buffers. The most widely used segmented DAC is a current­ ratioed DAC, whose MSB DAC is made of identical elements for the next-segment approach, but the LSB DAC is a current divider. A binary-weighted current divider can be used as an LSB DAC, as shown in Fig. 62.2. For monotonicity, the MSB M–bits are selected by a thermometer code, but one of the MSB current sources corresponding to the next segment of the thermometer code is divided by a current divider for fine LSBs. Integrator-Type Digital-to-Analog Converters. As mentioned, monotonicity is guaranteed only in a thermometer-coded DAC. The thermometer coding of a DAC output can be implemented either by repeating identical DAC elements many times or by repeatedly using the same element. The former requires more hardware, but the latter more time. In the continuous time integrator-type DAC the integrator output is a linear ramp and the time to stop integrating can be controlled by the digital codes. Therefore, monotonicity can be maintained. Similarly, the discrete time integrator can integrate a constant amount of charge repeatedly and the number of integrations can be controlled by the digital codes. The integration approach can give high accuracy, but its disadvantage is its slow speed limiting its applications. Although it is different in concept, oversampling interpolative DACs modulate the digital code in to a bitstream, and its pulse density represents the DAC output. Due to the incremental nature of the pulse density modulation, oversampling DACs are monotonic. A DAC for the pulse-density modulated bitstream is a lossy integrator. The integrator integrates a constant charge if the pulse is high, while it subtracts the same charge if the pulse is low. In principle, it is equivalent to the discrete time integrator DAC, but the output is represented by the average charge on the integrator. Conversion Speed The output of a DAC is a sampled-and-held step waveform held constant during a word clock period. Any deviation from the ideal step waveform causes an error in the DAC output. Highspeed DACs usually have a current output, but even current-output DACs are either terminated with a 50 to 75 Ω lowimpedance load or buffered by a wideband transresistance amplifier. Therefore, the speed of a DAC is limited either by the RC time constant of the output node or by the bandwidth of the output buffer amplifier. Figure 62.3 illustrates two step responses of a DAC when it settles with a time constant of τ © 2003 by CRC Press LLC

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1995

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FIGURE 62.3 Errors in step response: (a) settling, and (b) slewing.

and when it slews with a slew rate of S, respectively. The transient errors given by the shaded areas of Fig. 62.3 are hτ and h2/2S, respectively. This implies that a single time-constant settling of the former case only generates a linear error in the output, which does not effect the DAC linearity, but the slewlimited settling of the buffer generates a nonlinear error. Even in the single-time constant case (the former), the code-dependant time constant in settling can introduce a nonlinearity error because the settling error is a function of the time constant τ. This is true for a resistor-string DAC, which exhibits a code-dependent settling time because the output resistance of the DAC depends on the digital input. The slew rate limit of the buffer is a significant source of nonlinearity since the error is proportional to the square of the signal, as shown in Fig. 62.3(b). The height and the width of the error term change with the input. The worst-case harmonic distortion (HD) when generating a sinusoidal signal with a magnitude V0 with a limited slew rate of S is [1]. ωTc 2 × V0 , k = 1, 3, 5, 7, . . . HDk = 8 2 πk k − 4 STc sin 2

(

)

(62.5)

where Tc is the clock period. For a given distortion level, the minimum slew rate is given. Any exponential system with a bandwidth of ωo gives rise to signals with the maximum slew rate of 2ω0V0. Therefore, by making 2ω0V0 > Smin, no slew rate is limited and the DAC system will exhibit no distortion.

Converter Architectures Many circuit techniques are used to implement DACs, but a few popular techniques used widely today are of the parallel type, in which all bits change simultaneously upon applying an input code word. Serial DACs, on the other hand, produce an analog output only after receiving all digital input data in a sequential form. When DACs are used as stand-alone devices, their output transient behavior limited by glitch, slew rate, word clock jitter, settling, etc. are of paramount importance, but are used as subblocks of ADCs, digital-to-analog converters need only to settle within a given time interval. In stand-alone DAC applications, the digital input word made of N bits should be synchronously applied to the DAC with a precise timing accuracy. Thus, the input data latches are used to hold the digital input during the conversion. The output analog sample-and-hold, usually called deglitcher, is often used for the better transient performance of a DAC. The three most popular architectures in integrated circuits are DACs using a resistor string, ratioed current sources, and a capacitor array. The current-ratioed DAC finds the greatest application as a stand-alone DAC, while the resistor-string and capacitor-array DACs are used mainly as ADC subblocks. Resistor-String Digital-to-Analog Converters The simplest voltage divider is a resistor string. Reference levels can be generated by connecting 2N identical resistors in series between Vref and 0. Switches to connect the divided reference voltages to the © 2003 by CRC Press LLC

0912 ch62(1992-2017) frame55 Page 1996 Tuesday, October 29, 2002 1:59 PM

1996

The Circuits and Filters Handbook, Second Edition

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FIGURE 62.4 Resistor-string DAC: (a) with 1-out-of-2N decoder, and (b) with a binary tree decoder. TABLE 62.1

Resistor in IC Processes

Resistor Type

Sheet R (Ω/sq.)

Tolerance (%)

10–20 µm Matching (%)

T.C. (ppm/°C)

Diffusion Ion implantation Thin film Undoped poly

100–200 500–1k 1k 100–500

±20 ±5 ±5 ±20

±0.2–0.5 ±0.1 ±0.1 ±0.2

1500 200 10–100 1500

output can be either a 1-out-of-2N decoder or a binary tree decoder as shown in Fig. 62.4 for the 3-bit example. Because it requires a good switch, the stand-alone resistor-string DAC is easier to implement using CMOS. However, the lack of switches does not limit the application of the resistor string as a voltage reference divider subblock for ADCs in other process technologies. Resistor strings are used widely as reference dividers, an integral part of the flash ADC. All resistorstring DACs are inherently monotonic and exhibit good differential linearity. However, they suffer from a poor integral linearity and also have the drawback that the output resistance depends on the digital input code. This causes a code-dependent settling time when charging the capacitive load of the output bus. The code-dependent settling time has no effect on the reference divider performance as an ADC subblock, but the performance is severely degraded as a stand-alone DAC. This nonuniform settling time problem can be alleviated by adding low-resistance parallel resistors and by compensating the MOS switch overdrive voltages. In bipolar technology, the most common resistors are thin-film resistors made of tantalum, Ni-Cr, or Cr-SiO, which exhibit very low voltage and temperature coefficients. In CMOS either diffusion or undoped poly resistors are common. Four of the most frequently used resistors are listed in Table 62.1. Conventional trimming or adjustment techniques are impractical to be applied to all 2N resistor elements. The following four methods are often used to improve the integral linearity of resistor-string DACs. Layout Techniques. The use of large geometry devices and/or careful layout is effective in improving the matching marginally. Large geometry devices reduce the random edge effect, and the layout using a common centroid or geometric averaging can reduce the process gradient effect. However, typical match­ ing of resistors in integrated circuits is still limited to an 8- to 10-bit level due to the mobility and resistor © 2003 by CRC Press LLC

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Data Converters

Vref

R Ideal Tap Voltages

R

Vref

External

Trim

Resistors

R R

R

R

R

R

R

R

R

R

R

R

R

R

(a)

(b)

FIGURE 62.5 INL improvements: (a) by external voltage sources, and (b) by parallel resistors.

thickness variations. Differential resistor DACs with large feature sizes are reported to exhibit a higher matching accuracy of an 11- to 12-bit level. Off-Chip Adjustment. It is possible to set tap points of a resistor-string to specified voltages by connecting external voltage sources to them, as shown in Fig. 62.5(a) for the 3-bit example. Simply put, the more taps adjusted, the better the integral linearity obtained. An additional benefit of this method is the reduced RC time constant due to the voltage sources at the taps. Instead of using voltage sources, the required voltages can be obtained using parallel trimming, resistors, as shown in Fig. 62.5(b). However, in addition to external components for trimming, fine adjustments and precision measurement instruments are needed to ensure that voltage levels are correct. Furthermore, due to mismatch in the temperature coefficients between the external components and the on-chip components, retrimming is often required when temperature changes. Postprocess Trimming. The most widely used methods are laser trimming [2], Zener zapping [3], and other electrical trimming using PROM. The trimming method is the same as the parallel resistor trimming shown in Fig. 62.5(b) except for the fact that external trimming resistors are now integrated on the chip. While being trimmed, the resistor string is biased with a constant current. Individual segments are trimmed to have the same voltage drop. However, during normal conversion, the current source is replaced by a reference voltage source. The focused laser beam for trimming has a finite diameter, and the resistor to be trimmed occupies a large chip area. Both the laser trimming and the Zener zapping processes are irreversible. The long-term stability of trimmed resistors is a major concern, although the electrical and the PROM trimming (if PROM is replaced by EPROM) can be repeated. All trimming methods in this category are time consuming and require precision instruments. On-Chip Buffers. The voltage at intermediate taps of the resistor string can be controlled by another resistor string through on-chip unity-gain buffers. This is actually an improved version of the off-chip method. The controlling resistors can be either laser trimmed or electronically controlled by switches. Laser-trimmed controlling resistors have the same problems mentioned earlier. The trimming network © 2003 by CRC Press LLC

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1998

The Circuits and Filters Handbook, Second Edition

can be implemented to electronically control resistor values. In either case buffers with a high open-loop gain, a low output resistance, a large current driving capability, and a wide bandwidth for accurate and fast settling are required. Current-Ratioed Digital-to-Analog Converters The most popular stand-alone DACs in use today are current-ratioed DACs, of which the two types are a weighted-current DAC and an R-2R DAC. Binary-Weighted Current Digital-to-Analog Converters. The weighted current DACs shown in Fig. 62.6 are made of an array of switched binary-weighted current sources and the current summing network. In bipolar technology binary weighting is achieved by ratioed transistors and emitter resistors with binaryrelated values of R, R/2, R/4, and so on, while in MOS technology, only ratioed transistors are used. One example is a video random access memory DAC in CMOS, which is made of simple PMOS differential pairs with binary-weighted tail currents. Digital-to-analog converters relying on active device matching can achieve an 8-bit level performance with a 0.2 to 0.5% matching accuracy using a 10 to 20 µm device feature size while degeneration with thin-film resistors gives a 10-bit level performance. The current sources are switched on or off by means of switching diodes or emitter-coupled differential pairs (source­ coupled pairs in CMOS), as shown in Fig. 62.6. The output current summing is done by a wideband transresistance amplifier, but in high-speed DACs, the output current is used directly to drive a resistor load for a maximum speed but with a limited output swing. The weighted current design has the ��

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0912 ch62(1992-2017) frame55 Page 1999 Tuesday, October 29, 2002 1:59 PM

1999

Data Converters

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FIGURE 62.7 R-2R ladder DAC.

advantage of simplicity and high speed, but it is difficult to implement a high-resolution DAC because a wide range of emitter resistors and transistor sizes is used and very large resistors cause problems with both temperature stability and speed. R-2R Ladder Digital-to-Analog Converters. This large resistor ratio problem is alleviated by using a resistor divider known as an R-2R ladder, as shown in Fig. 62.7. The R-2R network consists of series resistors of value R and shunt resistors of value 2R. The top of each shunt resistor 2R has a single-pole double-throw electronic switch which connects the resistor either to ground or to the output current summing node. The operation of the R-2R ladder network is based on the binary division of current as it flows down the ladder. At any junction of series resistor R, the resistance looking to the right side is 2R. Therefore, the input resistance at any junction is R, and the current splits into two equal parts at the junction because it sees equal resistances in either direction. The result is binary-weighted currents flowing into each shunt resistor in the ladder. The digitally controlled switches direct the current to either ground or to the summing node. The advantage of the R-2R ladder method is that only two values of resistors are used, greatly simplifying the task of matching or trimming and temperature tracking. In addition, for high-speed applications relatively low resistor values can be used. Excellent results can be obtained using laser-trimmed thin-film resistor networks. Because the output of the R-2R DAC is the product of the reference voltage and the digital input word, the R-2R ladder DAC is often called a multiplying DAC (MDAC). Both the weighted-current DAC and the R-2R DAC can be used as a current divider to make a subDAC. To make a segmented DAC for monotonicity based on the next-segment approach, as discussed earlier, the MSB should be made of thermometer-coded equal currents. Once the MSB is selected, the next segment should be divided further into LSBs as shown in Fig. 62.2. Integral nonlinearity can be improved by dynamically matching or by self-calibrating the MSB current sources as discussed later. Capacitor-Array Digital-to-Analog Converter. Capacitors made of double-poly or poly-diffusion in MOS technology are considered one of the most accurate passive components comparable to thin-film resistors in bipolar process, both in the matching accuracy and voltage and temperature coefficients [4]. The only disadvantage in the capacitor-array DAC implementation is the use of a dynamic charge redistribution principle. A switched-capacitor counterpart of the resistor-string DAC is a parallel capac­ itor array of 2N unit capacitors (C) with a common top plate. The capacitor-array DAC is not appropriate for stand-alone applications without a feedback amplifier virtually grounding the top plate and an output sample-and-hold or deglitcher. The operation of the capacitor-array DAC in Fig. 62.8 is based on the thermometer-coded DAC principle, and has a distinct advantage of monotonicity if the system is imple­ mented properly. However, due to the complexity of handling the thermometer-coded capacitor array, © 2003 by CRC Press LLC

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The Circuits and Filters Handbook, Second Edition

2N C Total 2N C − C

C

C

+

C

Vout

Thermometer - coded N bits

Vref

FIGURE 62.8 Thermometer-coded capacitor-array DAC.

2N C Total 2N C − 2N−1 C

4C

2C

C

C

+

Vout

Vref

FIGURE 62.9 Binary-weighted capacitor-array DAC.

a binary-weighted capacitor array is often used, as shown in Fig. 62.9, by grouping unit capacitors in binary ratio values. A common centroid layout of the capacitor array is known to give a 10-bit level matching for this application when the unit capacitor size is over 12 µm × 12 µm. The matching accuracy of the capacitor in MOS technology depends on the geometry sizes of the capacitor width and length and the dielectric thickness. As a stand-alone DAC, the top plate of the DAC is precharged either to the offset of the feedback amplifier or to the ground. One smallest capacitor is not necessary for this application. However, as a subblock of an ADC, the total capacitor should be 2NC, as drawn in Fig. 62.9, and the top plate of the array is usually connected to the input nodes of comparators or high-gain operational amplifiers, depend­ ing on the ADC architectures. As a result, the top plate has a parasitic capacitance, but its effect on the DAC performance is negligible. The capacitor-array DAC requires two-phase nonoverlapping clocks for proper operation. Initially, all capacitors should be charged to ground. After initialization, depending on the digital input, the bottom plates are connected either to Vref or to ground. Consider the case in which the top plate is floating without the feedback amplifier. If the charge at the top plate finishes its redistri­ bution the top plate voltage neglecting the top plate parasitic effect becomes N

Vo =

∑2 V i

i=1

© 2003 by CRC Press LLC

bk

ref

(62.6)

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Data Converters

where bN bN–1, …, b2 b1 is the input binary word. For example, switching the MSB capacitor bottom to Vref changes the output voltage by 2N −1C N

∑

Vref =

Ci

Vref 2

(62.7)

i=1

where the capacitor Ci , for the ith bit is nominally scaled to 2i –1C. Therefore, the nonlinearity at the midpoint of the full range is limited by the ratio mismatch of the half sum of the capacitor array to the total sum of the array. Similarly, the nonlinearity at one fourth of the range is limited by the ratio of one fourth of the capacitor array to the total array, and so on. One important application of the capacitor-array DAC is as a reference DAC for ADCs. As in the case of the R-2R MDAC, the capacitor-array DAC can be used as an MDAC to amplify residue voltages for multistep ADCs. As shown in Fig. 62.9, if the input is sampled on the bottom plates of capacitors instead of the ground, the voltage amplified is the amplified input voltage minus the DAC output. By varying the feedback capacitor size, the MDAC can be used as an interstage residue amplifier in multistep pipelined ADCs. For example, if the feedback capacitor is C and the digital input is the coarse N-bit decision of the sampled analog voltage, the amplifier output is a residue voltage amplified by 2N for the subsequent LSB conversion. R + C or C + R Combination Digital-to-Analog Converters Both resistor-string and capacitor-array DACs need 2N unit elements for N-bits, and the number grows exponentially. Splitting arrays into two, one for MSBs and the other for the LSBs, requires a buffer amplifier to interface between two arrays. Although a floating capacitor connects two capacitors arrays, the parasitic capacitance of the floating node is not well controlled. A more logical combination for highresolution DAC is between resistor and capacitor DACs. This combination does not require any coupling capacitors or interface buffer amplifiers. In the R + C combination, the MSB is set by the resistor string, and next segment of the resistor-string DAC supplies the reference voltage of the LSB capacitor DAC, as shown in Fig. 62.10. When the top plate is initialized, all capacitor bottom plates are connected to the lower voltage of the next segment of the resistor-string DAC. During the next clock phase, the bottom plates of capacitors are selectively connected to the higher voltage of the segment if the digital bit is ONE, but stays switched to the lower voltage if MSB DAC Vref

LSB DAC

R

R

2

M

2

N−1

R RÕs

C

4C

2C

C

bN

b3

b2

b1

R

R

Thermometer -coded M MSBÕs

FIGURE 62.10 R + C combination DAC.

© 2003 by CRC Press LLC

N LSBÕs

2

C

N

C

− +

Vout

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2002

The Circuits and Filters Handbook, Second Edition

MSB DAC

2

M−1

C

bM

4C b3

2C b2

C

2

N

C

−

C

+

Vref

b1

Vout

R

R Vref N

2 RÕs M MSBÕs R

Thermometer

LSB DAC

R

-coded N LSBÕs

FIGURE 62.11 C + R combination DAC.

ZERO. This segmented DAC approach gives an inherent monotonicity as far as the LSB DAC is monotonic within its resolution. Although INL is poor, the fully differential implementation of this architecture benefits from the lack of the even-order nonlinearity, thereby achieving improved INL. On the other hand, in the C + R combination shown in Fig. 62.11, the operation of the capacitor DAC is the same. The MSB side reference voltage is fixed, but the reference voltage of the smallest capacitor is supplied by the LSB resistor-string DAC. This approach exhibits nonmonotonicity due to the capacitor DAC match­ ing. Both combination DACs are seldom used as stand-alone DACs due to their limited speed, but are used frequently as subblocks of high-resolution ADCs.

Techniques for High-Resolution Digital-to-Analog Converters Most DACs are made of passive or active components such as resistors, capacitors, or current sources, and their linearity relies on the matching accuracy of those components. Among frequently used DAC components, diffused resistors and transistors are in general known to exhibit an 8-bit level matching while thin-film resistors and capacitors are matched to a 10-bit level. Trimming or electronic calibration is needed in order to obtain a higher linearity than what is achievable with bare component matching. The traditional solutions to this have been the wafer-level trimming methods such as laser trimming and Zener zapping. Although many other promising trimming or matching techniques such as polysilicon fuse trimming, electrical trimming techniques using PROM, and large device matching by geometrical averaging have been proposed, conventional factory-set trimming or matching techniques give no flex­ ibility of retrimming. How successfully these techniques can be applied to large-volume production of high-resolution DACs and how the factory-trimmed components will perform over the long term are still in question. The future trend is toward more sophisticated and intelligent electronic solutions that overcome and complement some of the limitations of conventional trimming techniques. The methods recently devel­ oped are dynamic circuit techniques [5] for component matching, switched-capacitor integration [6], electronic calibration [7] of a DAC nonlinearity, and oversampling interpolation techniques [8] which trade speed with resolution. In particular, the oversampling interpolative DACs are used widely in stand­ alone applications such as digital audio playback systems or digital communications due to their inherent monotonicity.

© 2003 by CRC Press LLC

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Data Converters

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Dynamic Matching Techniques In general, a dynamic element matching to improve the accuracy of the binary ratio is a time-averaging process. For simplicity, consider a simple voltage or current divide-by-two element, as shown in Fig. 62.12. Due to mismatches in the ratio of resistors, transistors, and capacitors, the divided voltage or current is not exactly Vref /2 or Iref /2, but their sum is Vref or Iref . The dynamic matching concept is to multiplex these two outputs with complementary errors of ∆ and –∆ so that the errors ∆ and –∆ can be averaged out over time while the average value of Vref /2 or Iref /2 remains. It is in effect equivalent to the suppressed carrier balanced modulation of the error component ∆. The high-frequency energy can be filtered out using a post low-pass filter. This technique relies on the accurate timing of the duty cycle. Any duty cycle error or timing jitter results in inaccurate matching. The residual matching inaccuracy becomes a secondorder error proportional to the product of the original mismatch and the timing error. The application of dynamic element matching to the binary-weighted current DAC is a straightforward switching of two complementary currents. Its application to the binary voltage divider using two identical resistors or capacitors requires exchanging of resistors or capacitors. This can be achieved easily by reversing the polarity of the reference voltage for the divide-by-two case. However, in the general case of N element matching the current division is inherently simpler in implementation than the voltage division. In general, to match the N independent elements, a switching network with N inputs and N outputs is required. The function of the switching network is to connect any input out of N inputs to one output with an average duty cycle of 1/N. The simplest one is a barrel shifter rotating the I-O connections in a predetermined manner [5]. This barrel shifter generates a low-frequency modulated error when N becomes larger because the same pattern repeats every N clocks. A more sophisticated randomizer with the same average duty can distribute the mismatch error over the wider frequency range. The latter technique finds applications as a multi-bit DAC in the multibit noise-shaping sigma-delta data converter, whose linearity relies on the multi-bit DAC. Voltage or Current Sampling. The voltage or current sampling concept is an electronic alternative to direct mechanical trimming. To sample voltage or current using a voltage or current sampler is equivalent to trimming individual voltage or current sources. The voltage sampler is usually called a sample-and­ hold (S/H) circuit, while the current sampler is called a current copier. The voltage is usually sampled on the input capacitor of a buffer amplifier and the current is usually sampled on the input capacitor of a transconductance amplifier such as an MOS transistor gate. Therefore, both voltage and current sampling techniques are ultimately limited by their sampling accuracy.

© 2003 by CRC Press LLC

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2004

The Circuits and Filters Handbook, Second Edition

2NC − 1

2

+

Vout

Iref

C

Vref

1

2

1

VOUT

1

2N

2 2N

2

Vref 2N TIME (a)

(b)

FIGURE 62.13 Voltage and current sampling concepts: (a) integrator, and (b) current copier.

The idea behind the voltage or current sampling DAC is to use one voltage or current element repeatedly. One example of the voltage sampling DAC is a discrete-time integrator-type DAC with many S/H amplifiers for sampling output voltages. The integrator integrates a constant charge repeatedly, and its output is sampled on a new S/H amplifier every time the integrator finishes an integration as shown in Fig. 62.13(a). This is equivalent to generating equally spaced reference voltages by stacking identical unit voltages [6]. The fundamental problem associated with this sampling voltage DAC approach is the accumulation of the sampling error and noise in generating larger voltages. Similarly, the current sampling DAC can sample a constant current on current sources made of MOS transistors, as shown in Fig. 62.13(b) [7]. Because one reference current is copied on other identical current samplers, the matching accuracy can be maintained as far as the sampling errors are kept constant. It is not practical to make a highresolution DAC using voltage or current sampling alone. Therefore, this approach is limited to generating MSB DACs for the segmented DAC or for the subranging ADCs. Electronic Calibration Techniques Electronic calibration is a general term to describe various circuit techniques, which usually predistort the DAC transfer characteristic so that the DAC linearity can be improved. One such technique is a straightforward code mapping, and the other is a self-calibration. The code-mapping calibration is a very limited technique only for the factory because it requires a precision measurement setup and a large digital memory. The self-calibration is to incorporate all the calibration mechanisms and hardware on the DAC as a built-in function so that users can recalibrate whenever calibrations are needed. The selfcalibration is based on an assumption that the segmented DAC linearity is limited by the MSB DAC so that only errors of MSBs may be measured, stored in memory, and recalled during normal operation. There are two ways of measuring the MSB errors. In one method individual-bit nonlinearities, usually appearing as component mismatch errors, are measured digitally [9], and a total error, which is called a code error, is computed from individual-bit errors depending on the output code during normal conversion. On the other hand, the other method measures and stores digital code errors directly and eliminates the digital code-error computation during normal operation [10]. The former requires less digital memory during normal conversion while the latter requires fewer digital computations. © 2003 by CRC Press LLC

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Data Converters

Digital Ramp

DAC

Σ Ideal Level

Up/Down Counter

Calibration DAC

Memory Address

FIGURE 62.14 Code mapping with a calibration DAC.

Direct Code Mapping. The simplified code mapping of a DAC can be done with a calibration DAC, digital memory, and a precision instrument to measure the DAC output, as shown in Fig. 62.14. The idea is to measure the DAC error using a calibration DAC so that the DAC output corrected by the calibration DAC can produce an ideal DAC output. The input code of the calibration DAC is stored as a code error in digital memory addressed by the DAC input code. This code error is recalled to predistort the DAC output during normal operation. This technique needs a 2N memory with a word length corresponding to the number of bits of the calibration DAC. This method can correct any kinds of DAC nonlinearities as long as the calibration DAC has an output range wide enough to cover the whole range of nonlinearity. However, the same method can be implemented without the use of a calibration DAC if the main DAC is monotonic with extra bits of resolution. In this case, the calibration is a simple code mapping, selecting correct input digital codes for correct DAC output voltages among redundant input digital codes. Self-Calibration for Individual Capacitor Errors. The idea of measuring the individual bit errors using a calibration DAC is to quantize the difference ∆ in the divide-by-two elements in Figure 62.12 because the ideal divide ration is 1/2. For example, the MSB should be half of the whole range of a DAC, the second MSB is half of the MSB, and so on. Unless buffer amplifiers are used, the ideal calibration DACs for R and C DACs are C and R DACs, respectively. The ratio error measurement cycle of two-bit C DAC is illustrated in Fig. 62.15. Errors can be quantized using a successive approximation method, but the up/down converter is shown here for simplicity. Initially, the top plate is charged to the comparator offset and the bottom plates of C1 and C2 sample 0 and Vref . At the same time, the bottom plate of CC samples

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FIGURE 62.15 Capacitor ratio error measurement cycles: (a) initialization, and (b) error quantization.

© 2003 by CRC Press LLC

0912 ch62(1992-2017) frame55 Page 2006 Tuesday, October 29, 2002 1:59 PM

2006

The Circuits and Filters Handbook, Second Edition

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FIGURE 62.16 Current difference measurement cycles: (a) initialization, and (b) error quantization.

Vref /2 and the up/down counter is reset to make Vcal = 0. In the next clock period the charge is redistributed by swapping 0 and Vref on the bottom plates of C1 and C2. Then the top plate residual error Vx will be from the charge conservation Vx =

C1 C2 ∆C V − V = V C1 + C 2 + CC ref C1 + C 2 + CC ref 2C + CC ref

(62.8)

If Vcal = 0, C1 = C + ∆C/2, and C2 = C – ∆C/2. This top plate residual voltage can be nulled out by changing the calibration DAC voltage Vcal. The measured calibration voltage is approximately Vcal = −

∆C V CC ref

(62.9)

As the actual error Vx is half of the measured value when the Vref is applied to C1, the actual calibration DAC voltage to be subtracted during normal operation becomes Vcal /2. Similarly, the multi-bit calibration can start from the MSB measurement and move down to the LSB side [9]. The extension of this calibration technique to current DACs is straightforward. For example, two identical unipolar currents, I1 and I2, can be compared using a voltage comparator and a calibration DAC, as shown in Fig. 62.16. After I1 is switched in, the calibration DAC finds an equilibrium as a null. Then the difference can be measured by interchanging I1 and I2 and finding a new equilibrium. Therefore, the current difference error is obtained as I cal = I 2 − I1

(62.10)

During normal operation, half of this value should be added to the DAC output using the same calibration DAC every time the current I1 is switched to the DAC output. Similarly, the same amount is subtracted if I2 is switched to the output. Code-Error Calibration. The code-error calibration is based on the simple fact that the thermometercoded MSBs of a DAC are made of segments of equal magnitude [10]. Any nonuniform segment will contribute to the overall nonlinearity of a DAC. The segment error between two adjacent input codes is measured by comparing the segment with the ideal segment. Starting from the reference point, 0 or Vref /2, the same procedure is repeat until all the segment errors are measured. Therefore, the current © 2003 by CRC Press LLC

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2007

Data Converters

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− �

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− �

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FIGURE 62.17 Code-error measurement cycle: (a) initialization, and (b) error quantization.

code error, Error(j), is obtained by adding the current segment error to the accumulated sum of all the previous segment errors: Error( j ) =

j

∑ Seg(k)

(62.11)

k=1

where Seg(k) is the kth segment error from the reference point. These measured code errors are stored in memory addressed by digital codes so that they can be subtracted from uncalibrated raw digital outputs during normal conversion. The segment error measurement of a current-ratioed DAC thermometer-coded MSBs is similar to the current difference measurement in Fig. 62.16. The only difference in measurement is the use of the reference segment current in place of one of the two currents to be compared. That is, each MSB current source is compared to the reference segment. For the capacitive DAC, the kth segment error can be measured in two cycles. After the output of the DAC is initialized to have a negative ideal segment voltage with the input digital code corresponding to k – 1, the input code is increased by 1 as shown in Fig. 62.17. Applying digital codes to the capacitor-array DAC means connecting the bottom plates to either Vref or ground depending on the corresponding digital bits. Then the kth segment error is generated at the output and can be measured digitally using subsequent ADC stages or using a calibration DAC as shown in Fig. 62.15. Digital Truncation Errors. All calibration methods need extra bits of resolution in the error measure­ ments because digital truncation errors are accumulated during code-error computations. For example, if the truncation errors are random, the additions of n digital numbers will increase the standard deviation of the added number by n½. This accumulated truncation error affects both DNL and INL of the converter self-calibrated using measured errors of individual bits. On the other hand, if calibrated using measured segment errors, the DNL of the converter is always guaranteed to be within ± 1-2 LSB of a target resolution because all segment errors are measured with one extra bit of resolution, but the INL will still be affected by the digital truncation because code errors are obtained by accumulating segment errors. The effect of the digital truncation errors due to n repeated digital additions on the INL can be modeled using © 2003 by CRC Press LLC

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Digital In

The Circuits and Filters Handbook, Second Edition

M

Interpolation Filter, k↑

fs k

M

N

Truncation Loop

DAC

Analog Out

LPF

fs

fs

(Usually, N = 1)

FIGURE 62.18 Interpolative oversampling DAC.

α Q(z) X(z)

+

Σ

H(z)

Y(z)

−

FIGURE 62.19 Delta-sigma modulation as a digital truncator.

uncorrelated and independent random variables, and the standard deviation of INL is calculated in LSB units as σ INL =

(n − i)(i − 1) (LSB) 12(n −1)

for i = 1, 2, . . ., n

(62.12)

For example, when n = 16, the maximum standard deviation of the INL at the midpoint is about 0.56 LSB. Interpolative Oversampling Techniques Ordinary DACs generate a discrete output level for every digital word applied to their input, and it is difficult to generate a large number of distinct output levels for long words. The oversampling interpo­ lative DAC achieves fine resolution by covering the signal range with a few widely spaced levels and interpolating values between them. By rapidly oscillating between coarse output levels, the average output corresponding to the applied digital code can be generated with reduced noise in the signal band [8]. The general architecture of the interpolative oversampling DAC is shown in Fig. 62.18. A digital filter interpolates sample values of the input signal in order to raise the word rate to a frequency well above the Nyquist rate. The core of the technique is a digital truncator to truncate the input words to shorter output words. These shorter words are then converted into analog form at the high sample rate so that the truncation noise in the signal band may be satisfactorily low. The sampling rate upconversion for this is usually done in stages using two upsampling digital filters. The first filter, usually a two to four times oversampling FIR, is to shape the signal band for sampling rate upconversion and to equalize the passband droop resulting from the second SINC filter for higher-rate oversampling. A noise-shaping sigma-delta-sigma modulator can be built in digital form to make a digital truncator as shown in Fig. 62.19. Using a linearized model, the z-domain transfer function of the modulator is Y (z ) =

αH ( z ) 1 X (z ) + Q( z ) 1 + αH ( z ) 1 + αH ( z )

(62.13)

where Q(z) is the quantization noise and α is the quantizer gain. The loop filter H(z) can be chosen so that the quantization noise may be high-pass filtered while the input signal is low-pass filtered. For the first-order modulator, the loop filtered is just an integrator with a transfer function of

© 2003 by CRC Press LLC

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Data Converters

X(z)

+

Σ −

z−1 1−z−1

+

Q(z)

z−1 1−z−1

Σ −

Y(z)

α 2

FIGURE 62.20 Second-order one-bit modulator.

H (z ) =

z −1 1 − z −1

(62.14)

while for the second-order modulator, the transfer function is H (z ) =

(

z −1 2 − z −1

(1 − z ) −1

2

)

(62.15)

However, the standard second-order modulator is implemented, as shown in Fig.62.20, using a double integration loop. In general, first-order designs tend to produce correlated idling patterns. Second-order designs are vastly superior to first-order designs both in terms of the required oversampling ratio to achieve a particular signal-to-noise ratio as well as in the improved randomness of the idling patterns. However, even the second-order loop is not entirely free of correlated fixed patterns in the presence of small DC inputs. The second-order loop needs dithering to reduce fixed pattern noises, but loops of a higher order than third do not exhibit fixed pattern noises. Stability. The quantizer gain α plays an important role in keeping the modulator stable. Considering α, the transfer function of the second-order loop shown in Fig. 62.20 becomes Y (z ) =

(

)

αz −2 X ( z ) + 1 − z −1 Q( z ) 2

1 − 2(1 − α )z −1 + (1 − α )z −2

(62.16)

The root locus of the transfer function in the z-domain is shown in Fig. 62.21. As shown, the secondorder loop becomes unstable for α > 4/3 because one pole moves out of the unit circle. This in turn implies that the signal at the input of the quantizer becomes too large. Most delta-sigma modulators become unstable if the signal to the quantizer exceeds a certain limit. Higher-order modulators tend to be overloaded easily at higher quantizer gain than first-or second-order modulators. Therefore, for the stability reason, the integrator outputs of the loop filter are clamped so that the signal at the input of the quantizer is limited for linear operation. Digital truncators of a higher order than second are feasible in digital circuits because signal levels can be easily detected and controlled. The straightforward third order or higher loop using multiple loops is unstable, but higher order modulators can be built using either the cascaded MASH [11] or the single-bit higher order [12] architecture. Dynamic Range. In general, for the Nth order loop, the noise falls by 6N + 3 dB for every doubling of the sampling rate, providing N + 0.5 extra bits of resolution. Because the advantage of oversampling begins to appear when the oversampling ratio is > 2, a practically achievable dynamic range by oversam­ pling is approximately

© 2003 by CRC Press LLC

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2010

The Circuits and Filters Handbook, Second Edition

z - Plane 1 α= 1 2 α= 4 3

α=1

α= 4 3

−1

α=0 1

α> 4 3

−1

FIGURE 62.21 Root locus of the second-order loop transfer function.

DR > (6N + 3) ( log 2 M −1) dB

(62.17)

where M is the oversampling ratio. For example, a second-order loop with 256 times oversampling can give a dynamic range of > 105 dB, but the same dynamic range can be obtained using a third-order loop with only 64 times oversampling. The dynamic range is not a limit in the digital modulator. In practice, the dynamic range is limited in the rear-end analog DAC and postfilter. One-Bit or Multi-Bit DAC. The rear end of the interpolative oversampling DAC is an analog DAC. Because the processing in the interpolation filter and truncator is digital instead of analog, achieving precision is easy. Therefore, the oversampling DAC owes its performance to the rear-end analog part because the conversion of the truncated digital words into analog form takes place in the rear-end DAC. The one-bit quantizer can be easily overloaded and needs clamping to be stable, while multi-bit quantizers are more stable due to their small quantization errors. However, the multi-bit system is limited by the accuracy of the multi-bit DAC. Although the analog techniques such as dynamic matching or selfcalibration can improve the performance of the multi-bit DAC, the one-bit DAC is simpler to implement and its performance is not limited by component matching. It is true that a continuous time filter can convert the one-bit digital bitsteam into an analog waveform, but it is difficult to construct an ideal undistorted digital waveform without clock jitter. However, if the bitstream is converted into a charge packet, a high linearity is guaranteed due to the uniformity of the charge packets. A typical differential one-bit switched-capacitor DAC with one-pole roll-off can be built as shown in Fig. 62.22 using two-phase nonoverlapping clocks 1 and 2. There are many advantages in a fully differ­ ential implementation. The dynamic range increases by 3 dB because the signal is doubled (6 dB) but the noise gains by 3 dB. It also rejects most noisy coupling through power supplies or through the substrate as a common-mode signal. Furthermore, the linearity is improved because the even-order nonlinearity components of the capacitors and the op amp are canceled. In the implementation of Fig. 62.22, a resistor as a loss element can be replaced by a capacitor switched in and out at fc as illustrated. The bandwidths of these filters in both cases are set by 1/RCI and fcCR /CI , respectively, Also, the filter DC gains are defined by Rfc CS and CS /CR , respectively. The digital bitstream is converted into a charge packet by sampling the reference voltage on the bottom plates of the sampling capacitors (CS). If the digital bit is ZERO, –Vref is sampled during the clock phase 1 and the charge on CS is dumped on the lossy integrator during 2. On the other hand, if the digital bit is ONE, Vref is sampled instead. To reduce the input-dependent switch-feedthrough component, the switches connected to the top plates should be © 2003 by CRC Press LLC

0912 ch62(1992-2017) frame55 Page 2011 Tuesday, October 29, 2002 1:59 PM

2011

Data Converters

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FIGURE 62.22 Switched-capacitor one-bit DAC/filter.

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FIGURE 62.23 Alternative one-bit DAC sampling constant Vref .

turned off slightly earlier than the bottom plate switches using 1p and 2p. Alternatively, a slightly different one-bit DAC is possible by sampling a constant reference voltage by inverting the polarity of the inte­ gration depending on the digital bit as shown in Fig. 62.23. The op amp for this application should have a high DC gain and a fast slew rate. The op amp DC gain requirement is a little alleviated considering the linear open-loop transfer characteristic of most op amps within a limited swing range. As discussed earlier, the slew-limited settling generates an error proportional to the square of the magnitude. Therefore, a nonslewing op amp such as a class AB input op amp performs better for this application. The op amp starts to slew when a larger voltage than its linear input range is applied. When the charge packet of the sampled reference voltage is dumped onto the input summing node, it causes a voltage step on the summing node. The bypass capacitor CB between two summing nodes helps to reduce this voltage step to prevent the op amp from slewing. The large the CB , the smaller the voltage step. However, a too-large CB will narrowband the feedback amplifier, and the settling will take longer as a result. Postfiltering Requirement. Although the one-pole roll-off will substantially attenuate high-frequency components around fc, the one-bit DAC should be followed by a continuous time postfilter so that the charge packets can be smoothed out. Unlike the delta-sigma modulator which filters out the out-of­ band-shaped noise using digital filters, the demodulator output noise can be filtered only by analog filters. © 2003 by CRC Press LLC

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The Circuits and Filters Handbook, Second Edition

Because the shaped noise is out-of-band, it does not affect the inband performance directly, but the large out-of-band high-frequency noise tends to generate inband intermodulation components and limit the dynamic range of the system. Therefore, the shaped high-frequency noise needs to be filtered with a lowpass filter one order higher than the order of the modulator. It is challenging to meet this postfiltering requirement with analog filtering techniques. Analog filters for this application are often implemented in continuous time using a cascade of Sallen–Key filters made of emitter follower unity-gain buffers, but both switched-capacitor and continuous time filtering techniques have improved significantly to be applied to this application. The other possibility is the hybrid implementation of an FIR filter using digital delays and an analog current swimming network. Because the output is a bitstream, current sources weighted using coefficients of an FIR filter are switched to the current summer depending on the digital bit to make a low-pass FIR filter.

Sources of Conversion Errors Glitch The basic function of the DAC is the conversion of digital numbers into analog waveforms. A distortionfree DAC creates instantaneously an output voltage that is proportional to the input digital number. In reality, DACs cannot achieve this impossible goal. If the input digital number changes from one value to a different one, the DAC output voltage always reaches a new value sometime later. For DACs, the shape of the transient response is a function governed in large part by two mechanisms, glitch and slew rate limit. The ideal transient response of a DAC to a step is a single-time constant exponential function, which only generates an error growing linearly with the input signal, as explained in Fig. 62.3. Any other transient responses give rise to errors that have no bearing on the input signal. The glitch impulse is described in terms of a picovolts times seconds or equivalent unit. Glitches are caused by small time differences between some current sources turning off and others turning on. Take, for example, the major code transition at half scale from 011 … 11 to 100 … 00. Here, the MSB current source turns on while all other current sources turn off. The small difference in switching times results in a narrow half-scale glitch, as shown in Fig. 62.24. Such a glitch, for example, can produce distorted characters in CRT display applications. To alleviate both glitch and slew-rate problems related to transients, a DAC is followed by a S/H amplifier, usually called a deglitcher. The deglitcher stays in the hold mode while the DAC changes its output value. After the switching transients have settled, the deglitcher is changed to the sampling mode. By making the hold time suitably long, the output of the deglitcher can be made independent of the DAC transient response. Thus, the distortion during transients can be circumvented by using a fast S/H amplifier. However, the slew rate of the deglitcher is on the same order as that of the DAC, and the transient distortion will still be present, now as an artifact of the deglitcher.

ANALOG OUTPUT

Vref Early MSB Switching

Late MSB Switching

0 TIME 011111

100000

FIGURE 62.24 Glitch impulse at a major carry. © 2003 by CRC Press LLC

Vref 2N

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2013

Digital In

LATCH

Data Converters

DAC

Analog Out

Word Clock Jittered Word Clock

Analog Out

Timing Error

FIGURE 62.25 Word clock jitter effect.

Timing Error-Word Clock Jitter Although a DAC is ideally linear, it needs precise timing to correctly reproduce an analog output signal. If the samples do not generate an analog waveform with the identical timing with which they were taken, distortion will result, as explained in Fig. 62.25. Jitter can be loosely defined as timing errors in analogto-digital and digital-to-analog conversion. When the analog voltage is reconstructed using a DAC with timing variations in the word clock, the sample amplitudes, the ONEs and ZEROs are correct, but they come out at the wrong time. Because the right amplitude at the wrong time is the wrong amplitude, a timing jitter in the word clock produces an amplitude variation in the DAC output, causing the waveform to change shape. This in turn introduces either spurious components related to the jitter frequency or raises the noise floor of a DAC, unless the jitter is periodic. If the jitter has a Gaussian distribution with a root mean square jitter of ∆t, the worst-case SNR resulting from this random word clock jitter is SNR = −20 × log

2πf∆t M1 2

(62.18)

where f is the signal frequency and M is the oversampling ratio. The oversampling ratio M is defined as M=

fc 2 fn

(62.19)

where fc is the word clock frequency and fn is the noise bandwidth. The timing jitter error is more critical in reproducing high-frequency components. In other words, to make an N-bit DAC, an upper limit for the tolerable word clock jitter is ∆t
1 the effect of the nonlinearities in the second stage will have a much lower effect than those resulting from the first stage. Nonlinearities in the DAC can be reduced substantially by utilizing reference feedforward compensation [15]. Here, the reference for the second stage changes dynamically and is obtained by amplifying the first-stage digital-to-analog subconverter segment voltage that corresponds to the most © 2003 by CRC Press LLC

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Data Converters

Digital Output (V)

4 Output with error correction

3

2 Output without error correction 1 Ideal converter code center 0 0

1

2

Analog Input (V) 3

4

FIGURE 62.46 Digital-error correction simulation results.

current digital output code of the first-stage analog-to-digital subconverter. Figure 62.46 presents the simulation results for the 4-bit two-stage pipelined converter with and without digital error correction. For purposes of clarity the second-stage subconverter is made ideal. In a real converter some nonlinearity would still exist, but would be limited to that introduced by the last stage. Traditionally, even though the resolution of the first subconverter is only 2 bits, it needs to be linear to the overall converter resolution. Digital-error correction can reduce the linearity requirements such that it is commensurate with its resolution. N-Clock Converters Both the successive approximation and algorithmic analog-to-digital topologies require N clock cycles to perform an N-bit conversion. They both perform 1 bit of conversion per clock cycle. The successive approximation converter is a subclass of the subranging converter, in which during each clock cycle only 1 bit of resolution is generated. The algorithmic converter is a variation of the pipelined converter, in which the pipeline is folded back into a loop. Both topologies essentially perform a binary search to generate the digital value. However, in the case of the successive approximation converter the binary search is performed on the reference voltage, while in the case of the algorithmic converter the search is performed on the input signal. Successive Approximation Converters. A block diagram for the successive approximation converter is shown in Fig. 62.47. Because the conversion requires N-clock cycles a S/H version of the input signal is provided to the negative input of the comparator. The comparator controls the digital logic circuit that performs the binary search. This logic circuit is called the successive approximation register (SAR). The output of the SAR is used to drive the DAC that is connected to the positive input of the comparator. During the first clock period, the input is compared with the MSB, i.e., the MSB is temporarily raised high. If the output of the comparator remains high, then the input lies somewhere between 0 and Vref /2, Vin

S/H

− Control +

Successive Approximation Register

D/A converter

N-bit output

FIGURE 62.47 Successive approximation converter block diagram. © 2003 by CRC Press LLC

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The Circuits and Filters Handbook, Second Edition

Vref

0 Vin 72% of Vref

1 1 1

0

1

2

3

4

Clock Period

FIGURE 62.48 Binary search process for successive approximation.

S0 Vx C 2

C S1

+

S2

C 4 S3

C 8 S4

C 8

−

S5

Vin Vref

S6

FIGURE 62.49 Charge-distribution implementation of the successive approximation architecture.

and the MSB is reset to 0. However, if the comparator output is low, then the input signal is somewhere between Vref /2 and Vref , and the MSB is set high. During the next clock period the MSB-1 bit is evaluated in the same manner. This procedure is repeated such that at the end of N clock periods all N bits have been resolved. Figure 62.48 is the binary search procedure for a 4-bit converter and shows the comparator output sequence that corresponds to an input equal to 72% of Vref . The successive approximation converter is one of the most popular topologies in both MOS and bipolar technologies. In MOS technologies the charge-redistribution implementation [9] of the successive approximation methodology is the most commonly used. The circuit diagram of a 4-bit charge redistri­ bution converter is shown in Fig. 62.49. In this circuit, the binary weighted capacitors {C, C/2, …, C/8} and the switches {S1, S2, …, S5} form the 4-bit scaling DAC. For each conversion the circuit operates as a sequence of three phases. During the first phase (sample) switch S0 is closed and all the other switches {S1, S2, …, S6} are connected such that the input voltage Vin is sampled onto all the capacitors. During the next phase (hold) S0 is open and the bottom plates of all the capacitors are connected to ground; i.e., switches {S1, S2, …, S5} are switched to ground. The voltage, Vx , at the top plate of the capacitors at this

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Data Converters

time is equal to –Vin and the total charge in all the capacitors is equal to –2CVin. The final phase (redistribution) begins by testing the input voltage against the MSB. This is accomplished by keeping the switches {S1, S2, …, S5} connected to ground and switching S1 and S6 such that the bottom plate of the largest capacitor is connected to Vref . The voltage at the top plate of the capacitor is equal to Vx =

Vref − Vin 2

(62.22)

If Vx > 0 then the comparator output goes high, signifying that Vin < (Vref /2) and switch S1 is switched back to ground. If the comparator output is low, then Vin > (Vref /2) and the switch S1 is left connected to Vref and the MSB is set high. In a similar fashion the next bit, MSB-1, is evaluated. This procedure is continued until all N bits have resolved. After the conversion process the voltage at the top plate is such that V V V   V Vx = −Vin + b3 ref + b2 ref2 + b1 ref3 + b0 ref0  1 2 2 2   2

(62.23a)

−1LSB < Vx < 0

(62.23b)

where bi is {0, 1} depending upon if biti was set to 0 or 1. One of the advantages of the charge-redistribution topology is that the parasitic capacitance from the switches has little effect on the accuracy. Additionally, the clock feedthrough from switch S0 only causes an offset and the clock feedthrough from switches {S1, S2, …, S5} is input signal independent because they are always connected to either ground or Vref . However, any mismatch in the binary ratios of the capacitors in the array causes nonlinearity, which limits the accuracy to 10 or 12 bits. Self-Calibration Successive Approximation Converters. Fortunately, self-calibrating [7] techniques have been introduced that correct for errors in the binary ratios of the capacitors. Figure 62.50 is the block diagram for a successive approximation-based self-calibrating ADC. The circuit consists of an N-bit binary weighted capacitor array main DAC, an M-bit resistor string sub-DAC, and a calibration DAC. Digital logic is used to control the circuit during calibration and also to store the error voltages. Main DAC

+ To SAR C1−A

−

Sub-DAC

Successive Approximation Register (SAR)

Data Output

FIGURE 62.50 Self-calibration charge redistribution converter.

A d d e r

Register

S1−B

Vref

© 2003 by CRC Press LLC

Ccal

Data Register

SN−1

C1−B

Calibration DAC

SN

CN−1

Control Logic

CN

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Let each weighted capacitor Ci have a normalized error in its ratio (1 + εi ) from its ideal value: Ci = 2i−1C (1 + ε i )

(62.24)

Each capacitor contributes an error voltage at the top plate which is equal to Vei =

Vref i−1 2 ε i i = 1B, 2, ..., N 2N

(62.25)

Therefore, the total linearity error is equal to N

Verror =

∑V b

(62.26)

εi i

i =1B

where bi is the logic value of the ith bit. The calibration cycle begins by measuring the error contribution from the largest capacitor and progressing to the smallest. The error from the MSB capacitor is evaluated by closing S0 and setting switches {S1, S2, …, S5} such that all the capacitors except CMSB are charged to Vref . Next, the switch S0 is opened and switches {S1, S2, …, S5} are switched to connect the bottom plates to ground. Under ideal conditions, i.e., CMSB = 2N–1C, the voltage at the top plate is equal to zero. It should be noted that the total capacitance is equal to 2C. However, because CMSB = 2N–1C(1 + εMSB), the top plate voltage Vx = (Vref /2)εMSB, such that Vx MSB = 2VεMSB. Therefore, the error voltage at the top plate is a direct measure of the corresponding error in the capacitor ratio. A successive approximation search using the sub-DAC is used to measure these voltages. The relationship between the measured residual voltage and the error voltage is equal to Vεi =

N  1  Vεi  Vxi − 2  j =i +1 

∑

(62.27)

which corresponds to the equivalent error terms on the digital side. These digital correction terms are stored and subsequently added or subtracted during the normal operation cycle. Self-calibration improves the resolution of successive approximation converters to approximately 15 or 16 bits. Algorithmic Converters. As stated earlier, the algorithmic ADC is formed by modifying a pipelined converter. Here, the pipeline has been closed to form a loop. All N-bits are evaluated by a single stage, therefore implying that a N-bit conversion requires N clock cycles. A block diagram for the algorithmic converter is shown in Fig. 62.51 [6] and consists of a S/H, a 2× amplifier, a comparator, and a reference subtraction circuit. The circuit operates as follows. The input is first sampled and held by setting S1 to Vin. This signal is then multiplied by 2 (by the 2× amplifier). The result of this multiplication, V0, is compared to Vref. If VoN > Vref then the most significant bit, bN, is set to 1 or it is set to 0. If bN is equal to 1, then S2 is connected to Vref such that VbN is equal to VbN = 2V0N − bNVref bN = {0, 1}

(62.28)

This voltage is then sample-and-held and used to evaluate the MSB-1 bit. This procedure continues until all N-bits are resolved. The general expression for V0 is equal to

[

]

V0i = 2V0i−1 − biVref z −1

(62.29)

where bi is the comparator output for the ith evaluation and z –1 implies a delay of one clock period. © 2003 by CRC Press LLC

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Data Converters

Vin

Vo S/H

+

2X

−

S1 Vref + Vb

Σ

Vref

− S2

FIGURE 62.51 Algorithmic ADC block diagram.

V1

V3 Vref

V4

Vin

V5

C2 − +

C1

Vx

−

A1 C6

+

A3

Vo

C3

C5 − Vy

A2

+

C4

V2

FIGURE 62.52 Example circuit implementation of the algorithmic converter.

A circuit implementation for this ADC topology is shown in Fig. 62.52 [10]. This circuit uses three amplifiers, five ratio-matched capacitors (C1 to C5), an arbitrary valued capacitor, C6, and a comparator. Two implifiers and the capacitors (C1 to C5) form the recirculating register and the gain of two amplifiers. The amplifier A3 and capacitor C6 form an offset compensated comparator. The switches controlled by V3, V4, and V5 load the input or selectively subtract the reference voltage. The conversion is started by setting V1, V2, and V3 high. This forces Vx and VY to 0 and loads Vin into C1. Then, V1 is set low and V5 is set high. Therefore, the charge Vin ∗ C1 is transferred from C1 to C2. C1 is made to be equal to C2, therefore, Vx = Vin (C3 is also charged to Vx). Because V1 has been set low the comparator output goes high if Vin > 0, or else it remains low. This determines the MSB. The MSB-1 is determined by setting V2 low and setting V1 high. This forces the charge from C3 to transfer to C4 (V4 = Vx ; C5 is also charged to © 2003 by CRC Press LLC

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φ4

φ1 + φ3

C1

Vin

φ4

−

Vo

+

φ2

φ1 + φ3 φ2

C2

φ4

FIGURE 62.53 Ratio-independent multiply-by-two circuit.

+ − Vramp

Start/Stop

Counter Vin

Vramp

Vin

Ramp Generator

Clock

Tin

Time

FIGURE 62.54 Single-slope integrating converter.

V4). During the same period C1 is connected to ground if MSB = 1, or it is connected to Vref . Next, V2 is set low and V1 is set high, while C1 is switched from ground to Vref for Vref to ground. This transfers a charge equivalent to C1 ± Vref from C1 to C2 and transfers the charge in C5, C5 ∗ Vy , to C2. The capacitor C5 is made to be twice as large as C2, therefore, the voltage at Vx is equal to 2 ∗ Vin ± Vref . This process is repeated and the comparator determines bit MSB-1. This circuit has been shown to provide up to 10 bits of resolution at a maximum conversion rate of 200 kHz. The maximum resolution of the algorithmic converter is limited by the ratio matching of the capacitors, clock feedthrough, capacitor voltage coefficient, parasitic capacitance, and offset voltages. The previous topology solves the problem of parasitic capacitances and amplifier offset voltage, however, its maximum resolution is limited by the ratio matching of the capacitors that are used to realize the gain of two amplifiers. This problem is partially resolved by using a ratio-independent multiply-by-two algorithm [6] to increase the maximum resolution to the 12-bit level. The ratio-independent multiply-by-two algorithm is easily explained by the circuit shown in Fig. 62.53. During φ1, capacitor C1 is charged to Vin. This charge is then transferred onto C2 during φ2. The charge on C2 is equal to Vin ∗ C1. During φ3 C2 is disconnected from the feedback path and Vin is once again sampled onto C1. During φ4 the charge in C2 is added to C1. The total charge in C1 is now equal to C1 Vin + C1 Vin = 2C1Vin and is completely independent of the value of C2. Therefore, the voltage at the output at φ4 is equal to 2Vin. The only constraint is that the input voltage be held steady, i.e., S/H during φ1 and φ3.

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I S2 closed + C

S1

S4 closed

S3 closed

Vref

− Vin

−Vbias S2 Time

0 S3 Vin

-Vbias

S1 T1

S1

S1 T2

T3

S4 Vref

FIGURE 62.55 Single-slope integrating converter with calibration cycle.

2N-Clock Converters The basic principle of the integrating converter can be explained with the help of Fig. 62.54. A comparator compares the input signal with the output of a ramp voltage generator. The ramp voltage generator is zeroed after each measurement. The output of this comparator is used to gate the clock to an interval counter. The counter output corresponding to the ramp time Tin provides an accurate measure of the input voltage. The input voltage Vin is equal to Tin ∗ U, where U is the ramp rate. Because the absolute values of components are not well controlled and also because of the large offset voltages associated with MOS amplifiers and comparators, a calibration or a reference cycle is usually added to calculate the ramp rate and the offset voltage. A simple circuit for a single-slope integrating converter that includes the calibration cycle is shown in Fig. 62.55 [4]. The ramp voltage is generated using a constant current source to charge a capacitor. The ramp voltage, t Vramp , is equal to ∫0 (I/c)dt, which is equal to (I∆t)/c for a constant current I. The ramp voltage is compared against the analog ground voltages, Vin and Vref , respectively. The addition of the third calibration cycle eliminates any offset errors. The final resolution is dependent only on the linearity of the ramp generator, i.e., the linearity of the current source. In the single-slope approach just described, the calibration is done in digital. However, the complete calibration can be performed in analog as well, as in the dual-slope approach. Further improvements include a charge balancing technique [4] that uses an oscillating inte­ gration process to keep the voltage across the capacitor closer to zero, thereby reducing the linearity constraints on the ramp generator. The primary advantage of the integrating converter is the small number of precision analog components that are required to generate extremely high resolution. However, the primary disadvantage is the conversion time required. It takes 2N clock cycles to generate a N-bit conversion.

Oversampled Converters Oversampling converters have the advantage over Nyquist rate converters in that they do not require very tight tolerances from the analog components and also because they simplify the design of the antialias filter. Examples of oversampling converters include the noise-shaping architecture and the interpo­ lative architecture. Our discussion centers around noise-shaping converters. If the analog input signal Vin has a frequency spectrum from 0 to f0 then 2f0 is defined as the Nyquist rate. Oversampling converters sample the input at a rate larger than the Nyquist frequency. If fs is the

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sampling rate, then (fs)/(2f0) = OSR is called the oversampling ratio. Oversampling converters use “signal averaging” along with a low-resolution converter to provide extremely high resolution. This technique can best be understood by considering the following example in Fig. 62.56. Let the input be exactly in the middle of Vn and Vn+1 and let it be sampled a number of times. If, in addition to the input signal, we add some random noise, then for a large number of samples the output would fall on Vn 50% of the time and on Vn+1 the other 50% of the time. If the signal was a littler closer to Vn+1, then the percentage of times the output falls on Vn+1 would increase. Using this averaging technique we can get a better estimate of the input signal. However, in simple oversampling the resolution only increases by n , where n is the number of samples of Vin that are averaged. Therefore, to increase the resolution of the converter by one additional bit we are required to increase the number of samples by 4 x. Noise-shaping converters use feedback to generate the necessary noise and additionally perform frequency shaping of the noise spectrum to reduce the amount of oversampling necessary. This can be illustrated with the help of Fig. 62.57. The output from H1 is quantized by an N-bit ADC. This digitial value is then converted to an analog value by the N-bit DAC. This value is subtracted from the input and the result is sent to H1. Here, we assume an N-bit converter for simplicity, however, for the special case in which N = 1 the noise-shaping converter is called a sigma-delta converter. The quantization process approximates an analog value by a finite-resolution digital value. This step introduces a quanti­ zation error, Qn. Further, if we assume that the quantization error is not correlated to the input, the system can now be modeled as a linear system, as shown in Fig. 62.58. Here, we note that the error Vn+1

Vin

+

A/D

Resolution of converter

Vin

Vo

Vn Qn

Noise

FIGURE 62.56 Higher resolution provided by oversampling. +

Vin

−

Σ

H1

A/D

Vo

D/A

FIGURE 62.57 Noise-shaping oversampling converters.

Qn Vin

+

Σ

H1

−

FIGURE 62.58 Linear system model of noise-shaping converter.

© 2003 by CRC Press LLC

+

Vo

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Data Converters

z−1

+

FIGURE 62.59 Forward path delay integrator.

+

z−1

FIGURE 62.60 Feedback path delay integrator.

Qn Vin

+ −

Σ

x1

x2

z−1

+

+

Vo

FIGURE 62.61 First-order noise-shaping converter.

introduced by the analog-to-digital process is modeled by Qn . The output voltage for this system can now be written as V0 =

Qn

+

Vin H1

[1 + H ] [1 + H ] 1

(62.30)

1

Data converters are sampled data systems, and as such are easier to analyse in the Z-domain. For most sigma-delta converters H1 has the characteristics of a low-pass filter and is usually implemented as a switched-capacitor integrator. MOS switched-capacitor integrators can be implemented with either a delay in the forward signal path or a delay in the feedback path, and can be modeled in the Z-domain by Figs. 62.59 and 62.60, respectively. We use the first integrator architecture because it simplifies some of the algebra. For a first-order sigma-delta converter H1 is realized as a simple switched-capacitor integrator, i.e., H1 = (z –1)/(1 – z –1). Therefore, Fig. 62.58 can now be drawn as Fig. 62.61. Replacing H1 by (z –1)/(1 – z –1) in (62.30) we can write the transfer function for the first-order sigma-delta converter as

(

V0 = Vin z −1 + Qn 1 − z −1

)

(62.31)

As can be seen from (62.31) the output is a delayed version of the input plus the quantization noise multiplied by the factor (1 – z –1). This function has a high-pass characteristic, as shown in Fig. 62.62. We note here that the quantization noise is substantially reduced at lower frequencies and increases slightly at higher frequencies. In this figure, f0 is the input signal bandwidth and fs /2 = π corresponds to the Nyquist rate of the oversampling converter. For simplicity the quantization noise is usually assumed to be white1 with a spectral density equal to erms 2 ⁄ f s . Therefore, the magnitude of the output noise spectrum can be written as 1Quantization noise is clearly not uncorrelated or white for the first-order sigma-delta modulator, but becomes increasingly so for the higher-order systems.

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2

fs/2 0

0

fo

radian

N ( f ) = e rms

FIGURE 62.62 Magnitude response of the function (1 – z –1).

π

 πf  2 2 1 − z −1 = 2erms sin   fs fs  fs 

(62.32)

Further, if f0  fs we can approximate the root mean square noise in the signal band, (0 < f < f0), by

N f0 ≈ erms

π  2 f0  3  fs 

32

(62.33)

As the oversampling ratio increases the quantization noise in the signal band decreases; i.e., for a doubling of the oversampling ratio the quantization noise drops by 20 log(2)3/2 ≈ 9 dB. Therefore, for each doubling of the oversampling ratio we effectively increase the resolution of the oversampling converter by an additional 1.5 bits. The previous analysis was based on the assumption that the quantization noise was not correlated to the input and uniformly distributed across the Nyquist band. We now reexamine these assumptions. The assumption that the quantization noise is not correlated with the input only holds for extremely busy input signals. This is particularly not true for the first-order modulator assumed in the analysis above, such that for extremely low frequency or DC inputs the first-order modulator generates pattern noise (also called tones), as shown in Fig. 62.63. The peaks of the pattern noise occur at input voltages that are integer divisors of the quantization step. It is possible to provide a conceptual explanation for this occurrence. For example, for an input that is an integer divisor of the quantization level the digital output of the quantizer repeats itself at an extremely low frequency. This low-frequency repetition causes noise power to be introduced into the signal band. The quantization noise for second- and higher-order models is significantly more uncorrelated and is usually assumed to be white. The quantization error has a value that is limited to ±(1/2) LSB of the quantizer (the ADC in Fig. 62.47). If we assume that the quantization noise is white and uniformly distributed over the quantization level, then the average noise quantization is equal to

∫

1 + LSB 2

1 − LSB 2

x 2dx =

LSB 2 = Pn 12

(62.34)

Because the quantization noise is sampled at the clock frequency fs, the entire noise power is aliased back into the overall converter Nyquist ban [0 – (fs /2)]. Therefore, the spectral density of the quantization noise is equal to

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Data Converters

−50 −55

Noise Power (dB)

−60 −65 −70 −75 −80 −85 −90 −95 −100

−0.5

−1

0.5

0

1

INPUT LEVEL

FIGURE 62.63 Pattern noise for a first-order sigma-delta modulator for DC inputs.

Pn =

LSB 2 = 12

∫

fs 2

0

ne ( f ) δf = ne ( f )

ne ( f ) = Pn

2

2

fs 2

(62.35a)

2 fs

(62.35b)

The SNR for an ADC is defined as 10 log(Ps /Pn ), where Ps is the signal power. The signal power is highly waveform dependent. For example, the Ps for a full-scale sine wave input, (A/2) sin (ωT), which is applied to an N-bit quantizer, can be written in terms of the quantization level as

[(

) ]

2N −1 LSB A2 = 8 8

2

(62.36)

Therefore,

(

) 

12 2N −1  Ps  SNR = 10 log   = 10 log   8  Pn  

2

 

(62.37)

Higher-Order Modulators In Fig. 62.61, we replaced H1 for Fig. 62.58 with a first-order integrator. Clearly, H1 can be replaced by other higher-order functions that have a low-pass characteristic.2 For example, in Fig. 62.64 we show a second-order modulator. This modulator uses one forward delay integrator and one feedback delay integrator to avoid stability problems. The output voltage for this figure can be written as

2Actually, it is not necessary that they have low-pass characteristics. Bandpass characteristics may be preferred if the input signal is to be bandlimited.

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Qn Vin

+ −

Σ

+

+

+

z−1

+

Vo

z−1

FIGURE 62.64 Second-order modulator block diagram.

4 2nd order

1st order

0 0

FIGURE 62.65 Noise shaping due to the second-order modulator in Fig. 62.62.

π

(

V0 = Vin z −1 + Qn 1 − z −1

)

2

(62.38)

Note that the quantization noise is shaped by the second-order difference equation. This serves to further reduce the quantization noise at low frequencies. However, a further increase in the noise occurs at higher frequencies. A comparison of the noise shaping offered by the first and second-order modulators is shown in Fig. 62.65. Once again, assuming that fo  fs we can write an expression for the root mean square noise in the signal band for the second-order modulator as

N f0 ≈ erms

π 2  2 f0    5  fs 

52

(62.39)

The noise power in the signal bandwidth falls by 15 dB for every doubling of the oversampling ratio. One of the added advantages of the second-order modulator over the first-order modulator is that quantization noise has been shown to be less correlated to the input, therefore, less pattern noise. From our analysis so far, it would seem that increasing the order of the filter would reduce the necessary oversampling ratio for a given resolution. This is true, however, the simple Candy-style modulator (shown in Figs. 62.61 and 62.64) with orders >2 results in stability problems. This is because for higher-order modulators the later integrator stages are easily overloaded and saturated. This in turn increases the noise in the signal band. However, higher-order modulators can be realized by using a cascade of lower order modulators in the MASH architecture [8]. In the cascaded MASH technique, both the digital output and the output of the integrator of each lower-order modulator is passed on to the next module. A secondorder MASH architecture using two cascaded first-order sections is shown in Fig. 62.66. It can be shown that the output is equal to

(

Y = z −2 X − Qn2 1 − z −1

© 2003 by CRC Press LLC

)

2

(62.40)

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Data Converters

Qn1 X

+ −−

+

C1

+

z−1

−

Σ

Y

+

+ −

^ X

z−1

+

Σ

Σ

z−1

+

+

+

C2

−

z−1

Qn2

Σ

Differentiator

FIGURE 62.66 MASH architecture for a second-order modulator.

B3 B2 B1 Vin

+

+ Σ

Integrator 1

Integrator 2

−

Integrator 3 A2

A3 +

Σ +

1 Bit A/D

Vo

A1 1 Bit A/D

FIGURE 62.67 Finite pole-zero loop filter higher-order modulator.

Once again, we note that the quantization noise is multiplied by the second-order difference equation. The sign in front of the noise term is not important. However, for complete cancellation of the quanti­ zation noise from the first integrator the gain of the first loop needs to be identical to the gain of the second loop. Therefore, the amplifier gain and capacitor matching become extremely important. It has been shown that a 1% matching and an op amp gain of 80 dB are sufficient for 16 bits of accuracy [8]. An alternate methodology to stabilize higher-order oversampled coders is the use of finite poles and zeroes for the loop filter [16], H1 in Fig. 62.57. Up until now, all the loop filters have been integrators with poles at DC and zeroes at extremely high frequencies. The loop filter can be realized using additional feedback and feedforward paths as shown in Fig. 62.67. A third-order modulator is shown in this figure. Having finite poles and zeroes serves two purposes: (1) the nonzero poles function to reduce the in-band noise by flattering the quantization noise transfer function at low frequencies, (2) the finite zeroes function to reduce the magnitude of the quantization noise at high frequencies. By reducing the magnitude of the quantization noise at high frequencies, even higher-order modulators can be made stable. Additionally, these modulators have been shown to be devoid of pattern noise artifacts. Multi-Bit Quantizers The primary reason for using single-bit or two-level quantizers is their inherent perfect linearity. Because only two levels can exist, a straight line can always be drawn between these two levels. On the other hand

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ADNL

Qn +

Vin

−

Σ

+

z−1

+

+

Vo

+ DANL

FIGURE 62.68 Model for nonlinearity associated with multi-bit quantizers.

Vin

+ −

Σ

Loop Filter

N-Bit A/D

RAM

Vo

N-Bit D/A

FIGURE 62.69 Digital error correction for multi-bit quantizers.

number of advantages are found in using multi-bit quantizers in oversampling converters. The quanti­ zation noise generated in the multi-bit-based based noise-shaping converter is significantly more “white” and uncorrelated with the input signal, thereby reducing the probability of pattern noise. Additionally, the quantization noise power goes down exponentially as the number of bits in the quantizer increases. However, the primary problem associated with multilevel quantizers is the nonlinearity errors present with the DAC in the modulator loop. This problem can be illustrated with the help of Fig. 62.68. In Fig. 62.68, the error resulting from the nonlinearity in the multi-bit ADC is included as ADNL and the error resulting from the nonlinearity in the multi-bit DAC is included as DANL. The output voltage is given by (62.43). Here, note that the analog-to-digital nonlinearity is suppressed by the loop filter, while the digital-to-analog nonlinearity is only subjected to a unit delay. Therefore, any digital-to-analog nonlinearity directly appears in the output. A number of methods have been applied to reduce the effects of nonlinearity associated with multi-bit quantizers. The two most promising methods that have emerged are digital error correction [18] and dynamic element matching [17,19].

(

)

(

V0 = Vin z −1 − DA NL z −1 + Qn 1 − z −1 + AD NL 1 − z −1

)

(62.41)

A block diagram for digital error correction for multi-bit quantizer-based noise-shaping converters is shown in Fig. 62.69. The random access memory (RAM) and the multi-bit DAC have the same input signal. Because of the high gain in the loop at low frequencies the output of the DAC is almost identical to the input voltage, Vin. Now, if the digital RAM is programmed to generate the exact digital equivalent of the digital-to-analog output for any digital input, then the RAM output and the digital-to-analog output will be identical to each other. Because the output of the DAC is almost identical to the input voltage, the output voltage will also be the exact digital equivalent of the analog input. The RAM can be programmed by reconfiguring the modulator stages and feeding the system with a multi-bit digital ramp [18]. In the dynamic element matching approach, the various analog elements that are used to generate the different analog voltage levels are dynamically swapped around. The various elements can be swapped randomly [17] or in a periodic fashion [19]. The use of random permutations translates the nonlinearity of the DAC into random noise that is distributed throughtout the oversampling converter Nyquist range. This method virtually eliminates errors due to nonlinearity, but unfortunately it also increases the noise level in the signal band. In a variation of this basic technique, the various analog elements are swapped © 2003 by CRC Press LLC

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C2

φ1

φ1 C1 Vin

1 φ2

4 2

3

φ2

− +

Vo

A

FIGURE 62.70 Example circuit implementation for a switched-capacitor integrator.

in a periodic fashion such that the nonlinearity in the DAC is translated into noise at higher frequencies. Individual level averaging further eliminates the possibility of pattern noise within the signal band [19]. Technology Constraints One of the primary reasons for using sigma-delta converters is that they do not require good matching among the analog components. Therefore, for the two-level sigma-delta converter the nonidealities are introduced primarily by the integrator loop. To aid in the analysis of the various technology constraints we shall consider a particular implementation of an integrator (Fig. 62.70). The ideal transfer function for this circuit is given by –1/(1 – z –1). To realize this ideal transfer function the circuit relies on the virtual ground generated at the negative input of the integrator to accomplish complete charge transfer during each clock period. However, limited amplifier gain does not generate a perfect virtual ground, thereby not accomplishing the complete transfer of charge during each clock period. The effect of the limited gain is similar to a leaky integrator and the transfer function for the leaky integrator can be written as H (z ) =

−1 1 − αz −1

(62.42a)

where α=

1 1 ≈ 2 1 C  1 − 1 + 1  1 − A A  C2 

(62.42b)

The net effect of finite gain is to increase the modulation noise in the signal band as illustrated by Fig. 62.71 for the first-order modulator. In this figure, the X-axis is plotted from 0 to 1 rather than the 10 Signal Transfer Function

Amplitude (dB)

0 −10 −20 −30 −40

30dB Noise Transfer Function 40dB 50dB 90dB

−50 10−3

10−2 10−1 Normalised Frequency (radians)

FIGURE 62.71 Effect of finite amplifier gain on noise transfer function using a linear model.

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100

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70 60 SNR (dB)

50

Infinite Gain

40 30 20 10 Finite Gain

0 −10 −60

−50

−40

−30 −20 INPUT LEVEL (dB)

−10

0

FIGURE 62.72 Effect of finite amplifier gain using difference equation simulations.

complete Nyquist band to emphasize the signal band. The noise transfer function has been plotted for a number of amplifier gains. When compared to Fig. 62.62, note the increase in the noise level in the signal band. The effect of finite gain is felt throughout the input signal magnitude range as shown in Fig. 62.72. The graph for Fig. 62.71 was generated using the linearized model for the modulator presented in (62.21) and the graph in Fig. 62.72 was generated using the difference equation method. The difference equation method does not make any assumptions about linearity nor does it assume that the input is uncorrelated with the quatizantion noise, however, it requires considerably more simulation time. Because of oversampling the bandwidth requirements for the op amps in the integrators are usually large. Unfortunately, it is extremely difficult to realize extremely high gain and extremely high bandwidth amplifiers in MOS. One solution that attempts to mitigate the finite gain effect is to estimate the amount of incomplete charge transfer and compensate for it [5]. Circuit noise provides additional limitations to the maximum resolution realizable by an oversampled converter. The primary noise sources are the thermal noise generated by the switches in the integrator, amplifier noise, charge injection, and clock feedthrough from the switches. Because of sampling, the thermal noise associated with the finite on resistance of the switches is aliased back into the Nyquist band of the oversampling converter. The total noise aliased into the baseband for large bandwidth amplifiers is equal to kT/C for each switch pair, where k is the Boltzmann constant, T is the temperature in degrees Kelvin, and C is the value of the sampling capacitor in the integrator. For the parasitic insensitive integrator in Fig. 62.70, the total noise from this source is equal to 2kT/C. This noise is evenly spread across the Nyquist band, but only the fraction 2f0 /fs of this noise appears in the signal band. The rest is filtered out by the digital LPF. Using this constraint, for a full-scale sine wave input the minimum sampling capacitance is given by Cmin = 16 · kT · SNRdesired

(62.43)

The inband portion of the amplifier noise is also added to the output signal. In general, only the noise of the first amplifier is important for higher-order converters. For MOS amplifiers the flicker noise component is significantly more important as it tends to dominate in the signal band. When necessary, correlated double sampling techniques [5] can be used to reduce the effect of this noise source. Correlated double sampling, or autozeroing as it is sometimes called, has the added benefit that it eliminates any amplifier offset voltages. It is usually important to remove this offset voltage only for data acquisition applications. Because tight component matching is not required of the analog components, sigma-delta converters are particularly well suited for mixed-signal applications. However, having digital circuits on the sample chip increases the switching noise that is injected into the substrate and into the power supply lines. Any portion of this noise that lies in the signal band is added to the input signal. Therefore, fully differential integrator topologies should be used for high-resolution converters. Substrate and supply noise are

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Data Converters

φ1

C2

φ′1

φ1

C1 Vin

M1 φ2

M4 M2 M3

φ2

− +

A

Vo

φ′1 φ2

From D/A Path

FIGURE 62.73 Proper clock phase to eliminate signal-dependent clock feedthrough.

common-mode signals and are reduced by the common-mode rejection ratio of the amplifier when using fully differential circuits. In addition to the amplifier and the switching noise the charge injection from switches also sets a limit on the maximum resolution attainable component. Charge injection from switches has a signal-depen­ dent component and a signal-independent component. The effect of the signal-independent component is to introduce an additional offset error that can easily be calibrated out, if necessary. However, the signal-dependent component, particularly from the input sampling transistor (transistor M1 in Fig. 62.73), cannot be distinguished from input signal. This signal-dependent component is highly nonlinear and can be reduced substantially by using proper clock phasing. Signal-dependent charge injection from transistors M1 and M2 in Fig. 62.73 can be canceled to first order by delaying the turn off of φ′1 slightly [6]. A number of topologies for the digital low-pass filters have been tried. However, it has been shown that simple finite impulse response (sinc) filters are probably the optimal choice. It has been shown that the number of stages of sinc filtering necessary is equal to the modulator order plus 1 [2]. Noise-shaping converters have the ability to provide extremely high resolution. However, care must be used when using simple linear assumptions. Clearly, for the first-order modulator the white noise assumption breaks down. Additionally, it has been shown that the simple linear model overestimates the realizable SNR. For example, the linearized model overestimates the attainable SNR by as much as 14 dB for the secondorder modulator.

Acknowledgment The author acknowledges the help of his students in completing this manuscript, particularly Feng Wang.

References [1] W. C. Black, “High-Speed CMOS A/D Conversion Techniques,” Ph.D. thesis, Berkeley: University of California, 1980. [2] J. C. Candy and G. C. Temes, Oversampling Methods for A/D and D/A Conversion. New York: IEEE Press, 1992. [3] M. J. Demler, High-Speed Analog-to-Digital Conversion, New York: Academic Press, 1991. [4] P. R. Gray and D. A. Hodges, “All-MOS Analog-Digital Conversion Techniques,” IEEE Trans. Circuits Syst., vol. CAS-25(7), pp. 482–489, 1978. [5] P. J. Hurst and R. A. Levinson, “Delta-Sigma A/Ds with Reduced Sensitivity to Op Amp Noise and Gain,” IEEE Int. Symp. Circuits Syst., pp. 254–257, 1989. [6] P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, “A Ratio-Independent Algorithmic Analog-toDigital Conversion Technique,” IEEE J. Solid-State Circuits, vol. SC-19(6), pp. 828–836, 1984. [7] H. S. Lee, D. A. Hodges, and P. R. Gray, “A Self-Calibrating 15 Bit CMOS A/D Converter,” IEEE J. Solid-State Circuits, vol. SC-19(6), pp. 813–819, 1983.

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[8] Y. M. Matsuya, K. Uchimura, and A. Iwata, “A 16-Bit Oversampling A-to-D Conversion Technology using Triple Integration Noise Shaping,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 921–929, 1987. [9] J. L. McCreary and P. R. Gray, “All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques. I,” IEEE J. Solid-State Circuits, vol. SC-10, pp. 371–379, 1975. [10] R. H. McCharles, V. A. Saletore, W. C. Black, and D. A. Hodges, “An Algorithmic Analog-to-Digital Converter,” IEEE Int. Solid-State Circuits Conf., 1977. [11] S. Masuda, Y. Kitamura, S. Ohya, and M. Kikuchi, “A CMOS Pipelined Algorithmic A/D Converter,” IEEE Custom Integrated Circuits Conf., pp. 559–562, 1984. [12] G. C. Temes, F. J. Wang, and K. Watanabe, “Novel Pipeline Data Converters,” IEEE Int. Symp. Circuits Systems, pp. 1943–1946, 1988. [13] R. Unbehauen and A. Cichocki, MOS Switched-Capacitor and Continuous-Time Integrated Circuits and Systems. New York: Springer-Verlag, 1989. [14] S. H. Lewis, Video-Rate Analog-to-Digital Conversion Using Pipelined Architectures. Ph.D. thesis, Berkeley: University of California, 1987. [15] S. Sutarja and P. R. Gray, “A Pipelined 13-Bit, 250-ks/s, 5-V Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. SC-23, pp. 1316–1323, 1988. [16] K. Chao, S. Nadeem, W. Lee, and C. Sodini, “A Higher-Order Topology for Interpolative Modulators for Oversampling A/D Converters,” IEEE Trans. Circuits Syst., pp. 309–318, March 1990. [17] R. Carley, “A Noise-Shaping Coder Topology for 15+ Bit Converters,” IEEE J. Solid-State Circuits, pp. 267–273, April 1989. [18] R. Walden et al., “Architectures for Higher-Order Multibit Sigma-Delta Modulators,” IEEE Int. Symp. Circuits Syst., pp. 895–898, 1990. [19] B. Leung and S. Sutarja, “Multibit Sigma-Delta A/D Converter Incorporating a Novel Class of Dynamic Element Matching Techniques,” IEEE Trans. Circuits Syst., vol. CAS-39(1), pp. 35–51, 1992.

Further Information Max Hauser provides an extremely good overview of oversampling converters in “Principles of Oversampling A/D Conversion,” J. Audio Eng. Soc., vol. 39(1/2), pp. 3–26, 1991. Sources for further reading about Nyquist rate converters include D. J. Dooley, Data Conversion Integrated Circuits. New York: IEEE Press, 1980, and R. J. van der Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters, Boston: Kluwer Academic, 1994. IEEE Journal of Solid-State Circuits, particularly the December issues, and the IEEE Transactions on Circuits and Systems are good sources for more recent research on data converters.

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Design Automation1 Allen M. Dewey Duke University 63 Internet-Based Micro-Electronic Design Automation (IMEDA) Framework Moon Jung Chung, Heechul Kim Introduction • Functional Requirements of Framework • IMEDA System • Formal Representation of Design Process • Execution Environment of the Framework • Implementation • Conclusion

64 System-Level Design Alice C. Parker, Yosef Gavriel, Suhrid A. Wadekar Introduction • System Specification • System Partitioning • Scheduling and Allocating Tasks to Processing Modules • Allocating and Scheduling Storage Modules • Selecting Implementation and Packaging Styles for System Modules • The Interconnection Strategy • Word Length Determination • Predicting System Characteristics • A Survey of Research in System Design

65 Synthesis at the Register Transfer Level and the Behavioral Level J. Bhasker Introduction • The Two HDLs • The Three Different Domains of Synthesis • RTL Synthesis • Modeling a Three-State Gate • An Example • Behavioral Synthesis • Conclusion

66 Embedded Computing Systems and Hardware/Software Co-Design Wayne Wolf Introduction • Uses of Microprocessors • Embedded System Architectures • Hardware/Software Co-Design

67 Design Automation Technology Roadmap Don Cottrell Introduction • Design Automation — Historical Perspective • The Future • Summary

68 Performance Modeling and Analysis in VHDL James H. Aylor, Robert H. Klenke Introduction • The ADEPT Design Environment • A Simple Example of an ADEPT Performance Model • Mixed-Level Modeling • Conclusions

1

This section is dedicated to the memory of Allen M. Dewey.

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63 Internet-Based Micro-Electronic Design Automation (IMEDA) Framework 63.1 Introduction 63.2 Functional Requirements of Framework The Building Blocks of Process • Functional Requirements of Workflow Management • Process Specficiation • Execution Environment • Literature Surveys

63.3 IMEDA System 63.4 Formal Representation of Design Process Process Flow Graph • Process Grammars

63.5 Execution Environment of the Framework

Moon Jung Chung Michigan State University

Heechul Kim Hankuk University of Foreign Studies

The Cockpit Program • Manager Programs • Execution Example • Scheduling

63.6 Implementation The System Cockpit • External Tools • Communications Model • User Interface

63.7 Conclusion

63.1 Introduction As the complexity of VLSI systems continues to increase, the micro-electronic industry must possess an ability to reconfigure design and manufacturing resources and integrate design activities so that it can quickly adapt to the market changes and new technology. Gaining this ability imposes a twofold challenge: (1) to coordinate design activities that are geographically separated and (2) to represent an immense amount of knowledge from various disciplines in a unified format. The Internet can provide the catalyst by abridging many design activities with the resources around the world not only to exchange information but also to communicate ideas and methodologies. In this chapter, we present a collaborative engineering framework that coordinates distributed design activities through the Internet. Engineers can represent, exchange, and access the design knowledge and carry out design activities. The crux of the framework is the formal representation of process flow using the process grammar, which provides the theoretical foundation for representation, abstraction, manip­ ulation, and execution of design processes. The abstraction of process representation provides mecha­ nisms to represent hierarchical decomposition and alternative methods, which enable designers to manipulate the process flow diagram and select the best method. In the framework, the process information is layered into separate specification and execution levels so that designers can capture processes and

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execute them dynamically. As the framework is being executed, a designer would be informed of the current status such as updating and tracing design changes and be able to handle exceptions. The framework can improve design productivity by accessing, reusing, and revising the previous process for a similar design. The cockpit of our framework interfaces with engineers to perform design tasks and to negotiate design tradeoff. The framework has the capability to launch whiteboards that enable the engineers in a distributed environment to view the common process flows and data and to concurrently execute dynamic activities such as process refinement, selection of alternative process, and design reviews. The proposed framework has a provision for various browsers where the tasks and data used in one activity can be organized and retrieved later for other activities. One of the predominant challenges for microelectronic design is to handle the increased complexity of VLSI systems. At the turn of the century, it is expected that there will be 100 million transistors in a single chip with 0.1 micron features, which will require an even shorter design time (Spiller, 1997). This increase of chip complexity has given impetus to trends such as system on a chip, embedded system, and hardware/software co-design. To cope with this challenge, industry uses custom-off-the-shelf (COTS) components, relies on design reuse, and practices outsourcing design. In addition, design is highly modularized and carried out by many specialized teams in a geographically distributed environment. Multi-facets of design and manufacturing, such as manufacturability and low power, should be considered at the early stage of design. It is a major challenge to coordinate these design activities (Fairbairn, 1994). The difficulties are caused by due to the interdependencies among the activities, the delay in obtaining distant information, the inability to respond quickly to errors and changes, and general lack of commu­ nications. At the same time, the industry must contend with decreased expenditures on manufacturing facilities while maintaining rapid responses to market and technology changes. To meet this challenge, the U.S. government has launched several programs. The Rapid Prototyping of Application Specific Signal Processor (RASSP) Program was initiated by the Department of Defense to bring about the timely design and manufacturing of signal processors. One of the main goals of the RASSP program was to provide an effective design environment to achieve a four-time improvement in the development cycle of digital systems (Chung, 1996). DARPA also initiated a program to develop and demonstrate key software elements for Integrated Product and Process Development (IPPD) and agile manufacturing applications. One of the foci of the earlier program was the development of infrastructure for distributed design and manufacturing. Recently, the program is continued to Rapid Design Explo­ ration & Optimization (RaDEO) to support research, development, and demonstration of enabling technologies, tools, and infrastructure for the next generation of design environments for complex electro-mechanical systems. The design environment of RaDEO is planned to provide cognitive support to engineers by vastly improving their ability to explore, generate, track, store, and analyze design alternatives (Lyons, 1997). The new information technologies, such as the Internet and mobile computing, are changing the way we communicate and conduct business. More and more design centers use PCs, and link them on the Internet/intranet. The web-based communication allows people to collaborate across space and time, between humans, humans and computers, and computers in a shared virtual world (Berners-Lee, 1994). This emerging technology holds the key to enhance design and manufacturing activities. The Internet can be used as the medium of a virtual environment where concepts and methodologies can be discussed, accessed, and improved by the participating engineers. Through the medium, resources and activities can be reorganized, reconfigured, and integrated by the participating organizations. This new paradigm certainly impacts the traditional means for designing and manufacturing a complex product. Using Java, programs can be implemented in a platform-independent way so that they can be executed in any machine with a Web browser. Common Object Request Broker Architecture (CORBA) (Yang and Duddy, 1996) provides distributed services for tools to communicate through the Internet (Vogel). Designers may be able to execute remote tools through the Internet and see the visualization of design data (Erkes, 1996; Chan, 1998; Chung and Kwong, 1998). Even though the potential impact of this technology will be great on computer aided design, Electronic Design Automation (EDA) industry has been slow in adapting this new technology (Spiller and Newton, © 2003 by CRC Press LLC

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1997). Until recently, EDA frameworks used to be a collection of point tools. These complete suites of tools are integrated tightly by the framework using their proprietary technology. These frameworks have been suitable enough to carry out a routine task where the process of design is fixed. However, new tools appear constantly. To mix and match various tools outside of a particular framework is very difficult. Moreover, tools, expertise, and materials for design and manufacturing of a single system are dispersed geographically. Now, we have reached the stage where a single tool or framework is not sufficient enough to handle the increasing complexity of a chip and emerging new technology. A new framework is necessary which is open and scalable. It must support collaborative design activities so that designers can add new tools to the framework, and interface them with other CAD systems. There are two key functions of the framework: (1) managing the process and (2) maintaining the relationship among many design repre­ sentations. For design data management, refer to (Katz, 1987). In this chapter, we focus on the process management aspect. To cope with the complex process of VLSI system design, we need a higher level of viewing of a complete process, i.e., the abstraction of process by hiding all details that need not to be considered for the purpose at hand. As pointed out in National Institute of Standards and Technology reports (Schlenoff et al., 1996; Knutilla et al., 1998), a “unified process specification language” should have the following major requirements: abstraction, alternative task, complex groups of tasks, and complex sequences. In this chapter we first review the functional requirements of the process management in VLSI system design. We then present the Internet-based Micro-Electronic Design Automation (IMEDA) System. IMEDA is a Web-based collaborative engineering framework where engineers can represent, exchange, and access design knowledge and perform the design activities through the Internet. The crux of the framework is a formal representation of process flow using process grammar. Similar to the language grammar, production rules of the process grammar map tasks into admissible process flows (Baldwin, 1995a). The production rules allow a complex activity to be represented more concisely with a small number of high-level tasks. The process grammar provides the theoretical foundation for representation, abstraction, manipulation, and execution of design and manufacturing processes. It facilitates the com­ munication at an appropriate level of complexity. The abstraction mechanism provides a natural way of browsing the process repository and facilitates process reuse and improvement. The strong theoretical foundation of our approach allows users to analyze and predict the behavior of a particular process. The cockpit of our framework interfaces with engineers to perform design tasks and to negotiate design tradeoff. The framework guides the designer in selecting tools and design methodologies, and it generates process configurations that provide optimal solutions with a given set of constraints. The just-in-time binding and the location transparency of tools maximize the utilization of company resources. The framework is equipped with whiteboards so that engineers in a distributed environment can view the common process flows and data and concurrently execute dynamic activities such as process refinement, selection of alternative processes, and design reviews. With the grammar, the framework gracefully handles exceptions and alternative productions. A layered approach is used to separate the specification of design process and execution parameters. One of the main advantages of this separation is freeing designers from the over-specification and graceful exception handling. The framework, implemented using Java, is open and extensible. New process, tools, and user-defined process knowledge and constraints can be added easily.

63.2 Functional Requirements of Framework Design methodology is defined as a collection of principles and procedures employed in the design of engineering systems. Baldwin and Chung (Baldwin, 1995a) define design methodology management as selecting and executing methodologies so that the input specifications are transformed into desired output specifications. Kleinfeldt (1994), states that “design methodology management provides for the definition, presentation, execution, and control of design methodology in a flexible, configured way.” Given a methodology, we can select a process or processes for that particular methodology. Each design activity, whether big or small, can be treated as a task. A complex design task is hierar­ chically decomposed into simpler subtasks, and each subtask in turn may be further decomposed. Each © 2003 by CRC Press LLC

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task can be considered as a transformation from input specification to output specification. The term workflow is used to represent the details of a process including its structure in terms of all the required tasks and their interdependencies. Some process may be ill-structured, and capturing it as a workflow may not be easy. Exceptions, conditional executions, and human involvement during the process make it difficult to model the process as a workflow. There can be many different tools or alternative processes to accomplish a task. Thus, a design process requires design decisions such as selecting tools and processes as well as selecting appropriate design parameters. At a very high level of design, the input specifications and constraints are very general and may even be ill-structured. As we continue to decompose and perform the tasks based on design decisions, the output specifications are refined and the constraints on each task become more restrictive. When the output of a task does not meet certain requirements or constraints, a new process, tools, or parameters must be selected. Therefore, the design process is typically iterative and based on previous design experience. Design process is also a collaborative process, involving many different engineering activities and requiring the coordination among engineers, their activities, and the design results. Until recently, it was the designer’s responsibility to determine which tools to use and in what order to use them. However, managing the design process itself has become difficult, since each tool has its own capabilities and limitations. Moreover, new tools are developed and new processes are introduced continually. The situation is further aggravated because of incompatible assumptions and data formats between tools. To manage the process, we need a framework to monitor the process, carry out design tasks, support cooperative teamwork, and maintain the relationship among many design representations (Chiueh and Katz, 1990; Katz et al., 1987). The framework must support concurrent engineering activities by integrating various CAD tools and process and component libraries into a seamless environment. Figure 63.1 shows the RASSP enterprise system architecture (Welsh et al., 1995). It integrates tools, tool frameworks, and data management functions into an enterprise environment. The key functionality of the RASSP system is managing the RASSP design methodology by “process automation”, that is, control­ ling CAD program execution through workflow.

FIGURE 63.1

RASSP enterprise system architecture.

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The Building Blocks of Process The lowest level of a building block of a design process is a tool. A tool is an unbreakable unit of a CAD program. It usually performs a specific task by transforming given input specifications into output specifications. A task is defined as design activities that include information about what tools to use and how to use them. It can be decomposed into smaller subtasks. The simplest form of the task, called an atomic task, is the one that cannot be decomposed into subtasks. In essence, an atomic task is defined as an encapsulated tool. A task is called logical if it is not atomic. A workflow of a logical task describes the details of how the task is decomposed into subtasks, and the data and control dependencies such as the relationship between design data used in the subtasks. For a given task, there can be several workflows, each of which denotes a possible way of accomplishing the task. A methodology is a collection of workflow supported together with information on which workflow should be selected in a particular instance.

Functional Requirements of Workflow Management To be effective, a framework must integrate many design automation tools and allow the designer to specify acceptable methodologies and tools together with information such as when and how they may be used. Such a framework must not only guide the designer in selecting tools and design methodologies, but also aid the designer in constructing a workflow that is suitable to complete the design under given constraints. The constructed workflow should guarantee that required steps are not skipped; built-in design checks are incorporated into the workflow. The framework must also keep the relationships between various design representations, maintain the consistency between designs and support cooper­ ative teamwork, and allow the designer to interact with the system to adjust design parameters or to modify the previous design process. The framework must be extendible to accommodate rapidly changing technologies and emerging new tools. Such a framework can facilitate developing new hardware systems as well as redesigning a system from a previous design. During a design process, a particular methodology or workflow selected by a designer must be based on available tools, resources (computing and human), and design data. For example, a company may impose a rule that if input is a VHDL behavioral description, then designers should use Model Technol­ ogy’s VHDL simulator, but if the input is Verlig, they must use ViewLogic simulator. Or, if a component uses Xilinx, then all other components must also use Xilinx. Methodology must be driven by local expertise and individual preference, which in turn, are based on the designer’s experience. The process management should not constrain the designer. Instead, it must free designers from routine tasks, and guide the execution of workflow. User interaction and a designer’s freedom are especially important when exceptions are encountered during the execution of flows, or when designers are going to modify the workflow locally. The system must support such activities through “controlled interactions” with designers. Process management can be divided into two parts: • A formal specification of supported methodologies and tools that must show the tasks and data involved in a workflow and their relationships. • An execution environment that helps designers to construct workflow and execute them.

Process Specification Methodology management must provide facilities to specify design processes. Specification of processes involves tasks and their structures (i.e., workflow). The task involved and the flow of process, that is the way the process can be accomplished in terms of its subtasks, must be defined. Processes must be encapsulated and presented to designers in a usable way. Designers want an environment to guide them in building a workflow and to help them execute it during the design process. Designers must be able to browse related processes, and compare, analyze, and modify them.

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Tasks Designers should be able to define the tasks that can be logical or atomic, organize the defined tasks, and retrieve them. Task abstraction refers to using and viewing a task for specific purposes and ignoring the irrelevant aspects of the task. In general, object-oriented approaches are used for this purpose. Abstraction of the task may be accomplished by defining tasks in terms of “the operations the task is performing” without detailing the operations themselves. Abstraction of tasks allows users to clearly see the behavior of them and use them without knowing the details of their internal implementations. Using the gener­ alization–specialization hierarchy (Chung, 1990), similar tasks can be grouped together. In the hierarchy, a node in the lower level inherits its attributes from its predecessors. By inheriting the behavior of a task, the program can be shared, and by inheriting the representation of a task (in terms of its flow), the structure (workflow) can be shared. The Process Handbook (Malone, in press) embodies concepts of specialization and decomposition to represent processes. There are various approaches associated with binding a specific tool to an atomic task. A tool can be bound to a task statically at the compile time, or dynamically at the run time based on available resources and constraints. When a new tool is installed, designers should be able to modify the existing bindings. The simplest approach is to modify the source code or write a script file and recompile the system. The ideal case is plug and play, meaning that CAD vendors address the need of tool interoperability, e.g., the Tool Encapsulation Specification (TES) proposed by CFI (CFI, 1995). Workflow To define a workflow, we must specify the tasks involved in the workflow, data, and their relationship. A set of workflows defined by methodology developers enforces the user to follow the flows imposed by the company or group. Flows may also serve to guide users in developing their own flows. Designers would retrieve the cataloged flows, modify them, and use them for their own purposes based on the guidelines imposed by the developer. It is necessary to generate legal flows. A blackboard approach was used in (Lander et al., 1995) to generate a particular flow suitable for a given task. In Nelsis (Bosch, 1991), branches of a flow are explicitly represented using “or” nodes and “merge” nodes. A task can be accomplished in various ways. It is necessary to represent alternative methodologies for the task succinctly so that designers can access alternative methodologies and select the best one based on what-if analysis. IDEF3.X (IDEF) is used to graphically model workflow in RASSP environment. Figure 63.2 shows an example of workflow using IDEF3.X. A node denotes a task. It has inputs, outputs, mechanism, and conditions. IDEF definition that has been around for 20 years mainly to capture flat modeling such as a shop floor process. IDEF specification, however, requires complete information such as control mecha­ nisms and scheduling at the specification time, making the captured process difficult to understand. In IDEF, “or” nodes are used to represent the alternative paths. It does not have an explicit mechanism to represent alternative workflow. IDEF is ideal only for documenting the current practice and not suitable for executing iterative process which is determined during the execution of the process. Perhaps, the most important aspect missing from most process management systems is the abstraction mechanism (Schlenoff et al., 1996).

Execution Environment The execution environment provides dynamic execution of tasks and tools and binds data to tools, either manually or automatically. Few frameworks separate the execution environment from the specification of design process. A task can be executed in several modes (Kleinfeldth et al., 1994): manual mode, manual execution of flow, automatic flow execution, and automatic flow generation. In manual flow execution, the environment executes a task in the context of a flow. In an automatic flow execution environment, tasks are executed based on the order specified on the flow graph. In automatic flow generation, the framework generates workflow dynamically and executes them without the guidance of designers. Many frameworks use blackboard- or knowledge-based approaches to generate workflow. However, it is important for designers to be able to analyze the workflow created and share it with others. © 2003 by CRC Press LLC

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FIGURE 63.2

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Workflow example using IDEF definition.

That is, repeatability and predictability are important factors if frameworks support dynamic creation of workflow. Each task may be associated with pre- and post-conditions. Before a task is executed, the pre-condition of the task is evaluated. If the condition is not satisfied, the framework either waits until the condition is met, or aborts the task and selects another alternative. After the task is executed, its post-condition is evaluated to determine if the result meets the exit criteria. If the evaluation is unsatisfactory, another alternative should be tried. When a task is complex involving many subtasks and each subtask in turn has many alternatives, generating a workflow for the task that would successfully accomplish the task is not easy. If the first try of an alternative is not successful, another alternative should be tried. In some cases, backtrack occurs which nullifies all the executions of previous workflow.

Literature Surveys Many systems have been proposed to generate design process (Knapp and Parker, 1991) and manage workflow (Dellen et al., 1997; Lavana et al., 1997; Schurmann and Altmeyer, 1997; Sutton and Director, 1998). Many of them use the web technology to coordinate various activities in business (Andreoli et al., 1998), manufacturing (Berners-Lee et al., 1994; Cutkosy et al., 1996; Erkes et al., 1996), and micro­ electronic design (Rastogi et al., 1993; Chan et al., 1998). WELD (Chan et al., 1998) is a network infrastructure for a distributed design system that offers users the ability to create a customizable and adaptable virtual design system that can couple tools, libraries, design, and validation services. It provides support not only for designing but also for manufacturing, consulting, component acquisition, and product distribution, encompassing the developments of companies, universities, and individuals throughout the world. Lavana et al. (1997) proposed an Internet-based collaborative design. They use Petri nets as a modeling tool for describing and executing workflow. User teams, at different sites, control the workflow execution by selection of its path. Minerva II (Sutton and Director, 1998) is a software tool that provides design process management capabilities serving multiple designers working with multiple CAD frameworks. The proposed system generates design plan and realizes unified design process man­ agement across multiple CAD frameworks and potentially across multiple design disciplines. ExPro © 2003 by CRC Press LLC

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(Rastogi et al., 1993) is an expert-system-based process management system for the semiconductor design process. Several systems can automatically determine what tools to execute. OASIS (OASIS, 1992) uses Unix makefile style to describe a set of rules for controlling individual design steps. The Design Planning Engine of the ADAM system (Knapp and Parker, 1986; Knapp and Parker, 1991) produces a plan graph using a forward chaining approach. Acceptable methodologies are specified by listing pre-conditions and post-conditions for each tool in a lisp-like language. Estimation programs are used to guide the chaining. Ulysses (Bushnell and Director, 1986) and Cadweld (Daniell and Director, 1991) are blackboard systems used to control design processes. A knowledge source, which encapsulates each tool, views the information on the blackboard and determines when the tool would be appropriate. The task management is inte­ grated into the CAD framework and Task Model is interpreted by a blackboard architecture instead of a fixed inference mechanism. Minerva (Jacome and Director, 1992) and the OCT task manager (Chiueh and Katz, 1990) use hierarchical strategies for planning the design process. Hierarchical planning strat­ egies take advantage of knowledge about how to perform abstract tasks which involve several subtasks. To represent design process and workflow, many languages and schema have been proposed. NELSIS (Bosch et al., 1991) framework is based on a central, object-oriented database and on a flow management. It uses a dataflow graph as Flow Model and provides the hierarchical definition and execution of design flow. PLAYOUT (Schurmann and Altmeyer, 1997) framework is based on separate Task and Flow Models which are highly interrelated among themselves and the Product Model. In (Barthelmann, 1996), graph grammar is proposed in defining the task of software process management. Westfechtel (1996) proposed “process-net” to generate the process flow dynamically. However, in many of these systems, the relation­ ship between task and data is not explicitly represented. Therefore, representing the case in which a task generates more than one datum and each of them goes to a different task is not easy. In (Schurmann, 1997), Task Model (describing the I/O behavior of design tools) is used as a link between the Product Model and the Flow Model. The proposed system integrates data and process management to provide traceability. Many systems use IDEF to represent a process (Chung et al., 1996; IDEF; Stavas). IDEF specification, however, requires complete information such as control mechanisms and scheduling at the specification time, making the captured process difficult to understand. Although there are many other systems that address the problem of managing process, most proposed system use either a rule-based approach or a hard-coded process flow. They frequently require source code modification for any change in process. Moreover, they do not have mathematical formalism. Without the formalism, it is difficult to handle the iterative nature of the engineering process and to simulate the causal effects of any changes in parameters and resources. Consequently, coordinating the dynamic nature of processes is not well supported in most systems. It is difficult to analyze the rationale how an output is generated and where a failure has occurred. They also lack a systematic way of generating all permissible process flows at any level of abstraction while providing means to hide the details of the flow when they are not needed. Most systems have the tendency to over-specify the flow information, requiring complete details of a process flow before executing the process. In most real situations, the complete flow information may not be known after the process has been executed: they are limited in their ability to address the underlying problem of process flexibility. They are rather rigid and not centered on users, and do not handle exceptions gracefully. Thus, the major functions for the collaborative framework such as adding new tools and sharing and improving the process flow cannot be realized. Most of them are weak in at least one of the following criteria suggested by NIST (Schlenoff et al., 1996): process abstraction, alternative tasks, complex groups of tasks, and complex sequences.

63.3 IMEDA System The internet-based micro-electronic design automation (IMEDA) System is a general management frame­ work for performing various tasks in design and manufacturing of complex micro-electronic systems. It provides a means to integrate many specialized tools such as CAD and analysis packages, and allows the designer to specify acceptable methodologies and tools together with information such as when and how © 2003 by CRC Press LLC

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they may be used. IMEDA is a collaborative engineering framework that coordinates design activities distributed geographically. The framework facilitates the flow of multimedia data sets representing design process, production, and management information among the organizational units of a virtual enterprise. IMEDA uses process grammar (Baldwin and Chung, 1995) to represent the dynamic behavior of the design and manufacturing process. In a sense, IMEDA is similar to agent-based approach such as Redux (Petrie, 1996). Redux, however, does not provide process abstraction mechanism or facility to display the process flow explicitly. The major functionality of the framework includes: • Formal representation of the design process using the process grammar that captures a complex sequence of activities of micro-electronic design. • Execution environment that selects a process, elaborates the process, invokes tools, pre- and postevaluates the productions if the results meet the criterion, and notifies designers. • User interface that allows designers to interact with the framework, guides the design process, and edits the process and productions. • Tool integration and communication mechanism using Internet Socket and HTTP. • Access control that provides a mechanism to secure the activity and notification and approval that provide the mechanisms to disperse design changes to, and responses from, subscribers IMEDA is a distributed framework. design knowledge, including process information, manager pro­ grams, etc., are maintained in a distributed fashion by local servers. The following Fig. 63.3 illustrates how IMEDA links tools and sites for distributed design activities. The main components of IMEDA are • System Cockpit: It controls all interactions between the user and the system and between the system components. The cockpit will be implemented as a Java applet and may be executable on any platform for which a Java enabled browser is available. It keeps track of the current design status and informs the user of possible actions. It allows users to collaboratively create and edit process flows, production libraries, and design data. • Manager Programs: These encapsulate design knowledge. Using pre-evaluation functions, man­ agers estimate the possibility of success for each alternative. They invoke tools and call postevaluation functions to determine if a tool’s output meets the specified requirements. The interface servers allow cockpits and other Java-coded programs to view and manipulate production, task

FIGURE 63.3

The architecture of IMEDA.

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and design data libraries. Manager programs must be maintained by tool integrators to reflect site-specific information such as company design practices and different ways of installing tools. • Browsers: The task browser organizes the tasks in a generalization-specialization (GS) hierarchy and contains all the productions available for each task. The data-specification browser organizes the data-specifications in a GS hierarchy and contains all the children. • External Tools. These programs are the objects invoked by the framework during design activities. Each atomic task in a process flow is bound to an external tool. External tools are written typically by the domain experts. • Site Proxy Server: Any physical site that will host external tools must have a site proxy server running. These servers provide an interface between the cockpit and the external tools. The site server receives requests from system cockpits, and invokes the appropriate tool. Following the tool completion, the site server notifies the requesting cockpit, returning results, etc. • CGI Servers and Java Servlets: The system cockpit may also access modules and services provided by CGI servers or the more recently introduced Java servlets. Currently, the system integrates modules of this type as direct components of the system (as opposed to external tools that may vary with the flow). • Database Servers: Access to component data is a very important function. Using an API called JBDC, the framework can directly access virtually any commercially available database server remotely. • Whiteboard: The shared cockpit, or “whiteboard” is a communication medium to share infor­ mation among users in a distributed environment. It allows designers to interact with the system and guides the design process collaboratively. Designers will be able to examine design results and current process flows, post messages, and carry out design activities both concurrently and col­ laboratively. Three types of whiteboards are the process board, the chat board, and the freeform drawing board. Their functionality includes: (i) process board to the common process flow graph indicating the current task being executed and the intermediate results arrived at before the current task; (ii) drawing board to load visual design data, and to design and simulate process; and (iii) chat board to allow participants to communicate with each other via text-based dialog box. IMEDA uses a methodology specification based on a process flow graphs and process grammars (Baldwin and Chung, 1995). Process grammars are the means for transforming high-level process flow graphs into progressively more detailed graphs by applying a set of substitution rules, called productions, to nodes that represent logical tasks. It provides not only the process aspect of design activities but also a mechanism to coordinate them. The formalism in process grammar facilitates abstraction mechanisms to represent hierarchical decomposition and alternative methods, which enable designers to manipulate the process flow diagram and select the best method. The formalism provides the theoretical foundations for the development of IMEDA. IMEDA contains the database of admissible flows, called process specifications. With the initial task, constraints, and execution environment parameters, including personal profile, IMEDA guides designers in constructing process flow graphs in a top-down manner by applying productions. It also provides designers with the ability to discover process configurations that provide optimal solutions. It maintains consistency among designs and allows the designer to interact with the system and adjust design parameters, or modify the previous design process. As the framework is being executed, a designer can be informed of the current status of design such as updating and tracing design changes and be able to handling exception. Real-world processes are typically very complex by their very nature; IMEDA provides designers the ability to analyze, organize, and optimize processes in a way never before possible. More importantly, the framework can improve design productivity by accessing, reusing, and revising the previous process for a similar design. The unique features of our framework include: Process Abstraction/Modeling — Process grammars provide abstraction mechanism for modeling admissible process flows. The abstraction mechanism allows a complex activity to be represented © 2003 by CRC Press LLC

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more concisely with a small number of higher-level tasks, providing a natural way of browsing the process repository. The strong theoretical foundation of our approach allows users to analyze and predict the behavior of a particular process. With the grammar, the process flow gracefully handles exceptions and alternative productions. When a task has alternative productions, back­ tracking occurs to select other productions. Separation of Process Specification and Execution Environment — Execution environment infor­ mation such as complex control parameters and constraints is hidden from the process specifica­ tion. The information of these two layers is merely linked together to show the current task being executed on a process flow. The represented process flow can be executed in both automatic and manual modes. In the automatic mode, the framework executes all possible combinations to find a solution. In the manual mode, users can explore design space. Communication and Collaboration — To promote real-time collaboration among participants, the framework is equipped with the whiteboard, a communication medium to share information. Users can browse related processes, compare them with other processes, analyze, and simulate them. Locally managed process flows and productions can be integrated by the framework in the central server. The framework manages the production rules governing the higher level tasks, while lower level tasks and their productions are managed by local servers. This permits the framework to be effective in orchestrating a large-scale activity. Efficient Search of Design Process and Solution — IMEDA is able to select the best process and generate a process plan, or select a production dynamically and create a process flow. The process grammar easily captures design alternatives. The execution environment selects and executes the best one. If the selected process does not meet the requirement, then the framework backtracks and selects another alternative. This backtrack occurs recursively until a solution is found. If you allow a designer to select the best solution among many feasible ones, the framework may generate many multiple versions of the solution. Process Simulation — The quality of a product depends on the tools (maturity, speed, and special strength of the tool), process (or workflow selected), and design data (selected from the reuse library). Our framework predicts the quality of results (product) and assesses the risk and reli­ ability. This information can be used to select the best process/work flow suitable for a project. Parallel Execution of Several Processes and Multiple Versions — To reduce the design time and risk, it is necessary to execute independent tasks in parallel whenever they are available. Sometimes, it is necessary to investigate several alternatives simultaneously to reduce the design time and risk. Or the designer may want to execute multiple versions with different design parameters. The key issue in this case is scheduling the tasks to optimize the resource requirements. Life Cycle Support of Process Management — The process can be regarded as a product. A process (such as airplane designing or shipbuilding) may last many years. During this time, it may be necessary for the process itself to be modified because of new tools and technologies. Life cycle support includes updating the process dynamically, and testing/validating the design process, version history and configuration management of the design process. Tests and validations of the design processes, the simulation of processes, and impact analysis are necessary tools.

63.4 Formal Representation of Design Process1 IMEDA uses a methodology specification based on a process flow graphs and process grammars (Baldwin and Chung, 1995). The grammar is an extension of graph grammar originally proposed by Ehrig (1979) and has been applied to interconnection network (Derk and DeBrunner, 1998) and software engineering (Heiman et al., 1997).

1Materials in this section are excerpted from R. Baldwin and M.J. Chung, IEEE Computers, pp. 54–63, Feb. 1995. With permission.

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Process Flow Graph A process flow graph depicts tasks, data, and the relationships among them, describing the sequence of tasks for an activity. Three basic symbols are used to represent a process flow graph. Oval nodes represent logical tasks, two-concentric oval nodes represent Atomic Tasks, rectangular nodes represent data spec­ ifications and diamond nodes represent selectors. A task that can be decomposed into subtasks is called logical. Logical task nodes represent abstract tasks that could be done with several different tools or tool combinations. A task that cannot be decomposed is atomic. An atomic task node, commonly called a tool invocation, represents a run of an application program. A selector is a task node that selects data or parameter. Data specifications are design data, where the output specification produced by a task can be consumed by another task as an input specification. Each data specification node, identified by a rectangle, is labeled with a data specification type. Using the graphical elements of the flow graph, engineers can create a process flow in a top-down fashion. These elements can be combined into a process flow graph using directed arcs. The result is a bipartite acyclic directed graph that identifies clearly the task and data flow relationships among the tasks in a design activity. The set of edges indicates those data specifications used and produced by each task. Each specification must have at most one incoming edge. Data specifications with no incoming edges are inputs of the design exercise. T(G), S(G), and E(G) are the sets of task nodes, specification nodes, and edges of graph G, respectively. Figure 63.4 shows a process flow graph that describes a possible rapid

FIGURE 63.4 A sample process flow graph in which a state diagram is transformed into a field-programmable gate array configuration file.

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FIGURE 63.5 Graph production from a design process grammar. Two simulation alternatives based on input format are portrayed in (a); two partition alternatives representing different processes for an abstract task are protrayed in (b).

prototyping design process, in which a state diagram is transformed into a field-programmable gate array (FPGA) configuration file. The various specification types form a class hierarchy where each child is a specialization of the parent. There may be several incompatible children. For example, VHDL and Verilog descriptions are both children of simulation models. We utilize these specification types to avoid data format incompatibilities between tools (see Fig. 63.5a). Process flow graphs can describe design processes to varying levels of detail. A graph containing many logical nodes abstractly describes what should be done without describ­ ing how it should be done (i.e., specifying which tools to use). Conversely, a graph in which all task nodes are atomic completely describes a methodology. In our prototype, we use the following definitions: In(N) is the set of input nodes of node N: In(N) = { M | (M,N) ∈ E}. Out(N) is the set of output nodes of node N: OUT(N) = { M | (N,M) ∈ E}. I(G) is the set of input specifications of graph G: { N ∈ S(G) | In(N) = ∅ } .

Process Grammars The designer specifies the overall objectives with the initial graph that lists available input specifications, desired output specifications, and the logical tasks to be performed. By means of process grammars, logical task nodes are replaced by the flows of detailed subtasks and intermediate specifications. The output specification nodes are also replaced by nodes that may have a child specification type. The productions in a graph grammar permit the replacement of one subgraph by another. A produc­ tion in a design process grammar can be expressed formally as a tuple P = (GLHS, GRHS,σin, σout), where GLHS and GRHS are process flow graphs for the left side and the right side of the production, respectively, such that (i) GLHS has one logical task node representing the task to be replaced, (ii) σin is a mapping from the input specifications I(GLHS) to I(GRHS), indicating the relationship between two input specifications

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(each input specification of I(GRHS) is a subtype of I(GLHS)), and (iii) σout is a mapping from the output specifications of GLHS to output specifications of GRHS indicating the correspondence between them. (each output specification must be mapped to a specification with the same type or a subtype). Figure 63.5 illustrates productions for two tasks, simulate and FPGA partitioning. The mappings are indi­ cated by the numbers beside the specification nodes. Alternative productions may be necessary to handle different input specification types (as in Fig. 63.5a), or because they represent different processes- sepa­ rated by the word “or’’ — for performing the abstract task (as in Fig. 63.5b). Let A be the logical task node in GLHS, and A′ be a logical task node in the original process flow graph G such that A has the same task label as A′. The production rule P can be applied to A′, which means that A′ can be replaced with GRHS only if each input and output specifications of A′ matches to input and output specifications of GLHS, respectively. If there are several production rules with the same left side flow graph, it implies that there are alternative production rules for the logical task. Formally, the production matches A′ if: (i) A′ has the same task label as A. (ii) There is a mapping ρin, from In(A) to In(A′), indicating how the inputs should be mapped. For all nodes N ∈ In(A), ρin(N) should have the same type as N or a subtype. (iii) There is a mapping, ρout, from Out(A′) to Out(A), indicating how the outputs should be mapped. For all nodes N∈Out(A′), ρout(N) should have the same type as N or a subtype. The mappings are used to determine how edges that connected the replaced subgraph to the remainder should be redirected to nodes in the new subgraph. Once a match is found in graph G, the production is applied as follows: (i) Insert GRHS –I(GRHS) into G. The inputs of the replaced tasks are not replaced. (ii) For every N in I(GRHS) and edge (N,M) in GRHS, add edge (ρin(σin (N)),M) to G. That is to connect the inputs of A′ to the new task nodes that will use them. (iii) For every N in Out(A′) and edge (N,M) in G, replace edge (N,M) with edge (σout(ρout(N)),M). That is to connect the new output nodes to the tasks that will use them. (iv) Remove A′ and Out(A′) from G, along with all edges incident on them. Figure 63.6 illustrates a derivation in which the FPGA partitioning task is planned, using a production from Fig. 63.5b. The process grammar provides mechanism of specifying alternative methods for a logical task. A highlevel flow graph can then be decomposed into detailed flow graphs by applying production rules to a logical task. A production rule is a substitution that permits the replacement of a logical task node with a flow graph that represents a possible way of performing the task. The concept of applying productions to logical tasks is somewhat analogous to the idea of productions in traditional (i.e., non-graph) gram­ mars. In this sense, logical tasks correspond to logical symbols in grammar, and atomic tasks correspond to terminal symbols.

63.5 Execution Environment of the Framework Figure 63.7 illustrates the architecture of our proposed system, which applies the theory developed in the previous section. Decisions to select or invoke tools are split between the designers and a set of manager programs, where manager programs are making the routine decisions and the designers make decisions that requires higher-level thinking. A program called Cockpit coordinates the interaction among manager programs and the designers. Tool sets and methodology preferences will differ among sites and over time. Therefore, our assumption is that each unit designates a person (or group) to act as system integrator, who writes and maintains the tool-dependent code in the system. We provide the toolindependent code and template to simplify the task of writing tool-dependent code.

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FIGURE 63.6 A sample graph dertivation. Nodes in the outlined region, left, are replaced with nodes in the outlined region, right, according to production partition 1 in Fig. 63.5.

FIGURE 63.7

The proposed system based on Cockpit.

The Cockpit Program The designer interacts with Cockpit, a program which keeps track of the current process flow graph and informs the designer of possible actions such as productions that could be applied or tasks that could be executed. Cockpit contains no task-specific knowledge; its information about the design process comes

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entirely from a file of graph productions. When new tools are acquired or new design processes are developed, the system integrator modifies this file by adding, deleting, and editing productions. To assist the designer in choosing an appropriate action, Cockpit interacts with several manager programs that encapsulate design knowledge. Two types of manager programs are used: task managers and production managers. Task managers invoke tools and determine which productions to execute for logical task nodes. Production managers provide ratings for the productions and schedule the execution of tasks on the right-hand side of the production. Managers communicate with each other using messages issued by Cockpit. Our prototype system operates as follows. Cockpit reads the initial process flow graph from an input file generated by using a text editor. Cockpit then iteratively identifies when productions can be applied to logical task nodes and requests that the production managers assign the ratings to indicate how appropriate the productions are for those tasks. The process flow graph and the ratings of possible production appli­ cations are displayed for the designer, who directs Cockpit through a graphical user interface to apply a production or execute a task at any time. When asked to execute a task, Cockpit sends a message to a task manager. For an atomic task node, the task manager simply invokes the corresponding tool. For a logical task, the task manager must choose one or more productions, as identified by a Cockpit. The Cockpit applies the production and requests the production manager to execute the new expanded process.

Manager Programs Manager programs must be maintained by system integrators to reflect site-specific information, such as company design practices and tool installation methods. Typically, a manager program has its own thread. A Cockpit may have several manager programs, and therefore multi-threads. We define a com­ munication protocol between Cockpit and manager programs and provide templates for manager pro­ grams. The manager programs provide five operations: pre-evaluation, tool invocation, logical task execution, production execution, and query handling. Each operation described next corresponds to a C++ or Java function in the templates, which system integrators can customize as needed. Pre-evaluation: Production managers assign ratings to help designers and task managers select the most appropriate productions. The rating indicates the likelihood of success from applying this production. The strategies used by the system integrator provide most of the code to handle the rating. In some cases, it may be sufficient to assign ratings statically, based on the success of past productions. These static ratings can be adjusted downward when the production has already been tried unsuccessfully on this task node (which could be determined using the query mechanism). Alternatively, the ratings may be an arbitrarily complex function of parameters obtained through the query mechanism or by examining the input files. Sophisticated manager programs may continuously gather and analyze process metrics that indicate those conditions leading to success, adjust adjusting ratings accordingly. Tool Invocation: Atomic task mangers must invoke the corresponding software tool when requested by Cockpit, then determine whether the tool completed successfully. In many cases, information may be predetermined and entered in a standard template, which uses the tool’s result status to determine success. In other cases, the manager must determine tool parameters using task-specific knowledge or determine success by checking task-specific constraints. Either situation would require further customization of the manager program. Logical Task Execution: Logical task managers for logical tasks must select productions to execute the logical task. Cockpit informs the task manager of available productions and their ratings. The task manager can either direct Cockpit to apply and execute one or more productions, or it can decide that none of the productions is worthwhile and report failure. The task manager can also request that the productions be reevaluated when new information has been generated that might influence the ratings, such as a production’s failure. If a production succeeds, the task manager checks any constraints; if they are satisfied, it reports success.

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Production Execution: Production managers execute each task on the right-hand side of the produc­ tion at the appropriate time and possibly check constraints. If one of the tasks fails or a constraint is violated, backtracking can occur. The production manager can use task-specific knowledge to determine which tasks to repeat. If the production manager cannot handle the failure itself, it reports the failure to Cockpit, and the managers of higher level tasks and productions attempt to handle it. Query Handling: Both production and task managers participate in the query mechanism. A produc­ tion manager can send queries to its parent (the task manager for the logical task being performed) or to one of its children (a task manager of a subtask). Similarly, a task manager can send a query to its parent production manager or to one of its children (a production manager of the production it executed). The manager templates define C functions, which take string arguments, for sending these queries. System integrators call these functions but do not need to modify them. The manager templates also contain functions which are modified by system integrators for responding to queries. Common queries can be handled by template code; for example, a production manager can frequently ask its parent whether the production has already been attempted for that task and whether it succeeded. The manager template handles any unrecognized query from a child manager by forwarding it to the parent manager. Code must be added to handle queries for task-specific information such as the estimated circuit area or latency.

Execution Example Now we describe a synthesis scenario that illustrates our prototype architecture in use. In this scenario, the objective is to design a controller from a state diagram, which will ultimately be done