Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips

SYSTEMATIC DESIGN OF CMOS SWITCHED-CURRENT BANDPASS SIGMA-DELTA MODULATORS FOR DIGITAL COMMUNICATION CHIPS This page ...

Author: Jose De La Rosa | Bele Perez-Verdu

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SYSTEMATIC DESIGN OF CMOS SWITCHED-CURRENT BANDPASS SIGMA-DELTA MODULATORS FOR DIGITAL COMMUNICATION CHIPS

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Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips by

José M. de la Rosa University of Seville, Spain

Belén Pérez-Verdú University of Seville, Spain

and

Angel Rodríguez-Vázquez University of Seville, Spain

KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

eBook ISBN: Print ISBN:

0-306-48194-4 0-7923-7678-1

©2004 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print ©2002 Kluwer Academic Publishers Dordrecht All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's eBookstore at:

http://kluweronline.com http://ebooks.kluweronline.com

A Visi y al que viene de camino A Alberto y Aitana A nuestros padres


Contents

List of Figures

xiii

List of Tables

xxiv

Preface

xxv

Acknowledgments

xxvii

Prologue

xxix

Chapter 1: Bandpass Sigma-Delta A/D Converters – Fundamentals and State-of-the-Art 1.1 Introduction 1.2 Analog-to-digital interfaces for digital radio receivers 1.3 Analog-to-Digital Conversion: Fundamentals 1.3.1 Sampling 1.3.2 Quantization

1.4 Oversampling

6 8

Analog-to-Digital Converters

1.4.1 Basic architecture of a modulator 1.4.2 Figures of merit 1.4.2.1 Signal-to-noise ratio 1.4.2.2 Dynamic range and effective resolution 1.4.3 First-order lowpass modulator 1.4.4 Lowpass modulator architectures 1.4.5 Second-order lowpass Modulator 1.4.6 High-order lowpass modulators 1.4.7 Multi-bit lowpass modulators

1.5 Bandpass

1 2 5

11 13 13 13 14 16 17 18 22

23

modulators

1.5.1 Quantization noise shaping of bandpass 1.5.2 Signal passband location

1.6 Synthesis of bandpass

10

modulators

modulator architectures

1.6.1 The Lowpass-to-bandpass transformation method 1.6.1.1 Pattern noise of second-order bandpass 1.6.2 Other lowpass-to-bandpass transformations

modulators

25 28

30 30 33 35

viii

36

1.6.3 Optimized synthesis of 1.6.4 Quadrature bandpass modulators 1.6.5 N-path bandpass modulators 1.6.6 Continuous-time bandpass modulators

1.7 Decimation for bandpass 1.8 State-of-the-art bandpass

37 41 43

46 48

ADCs ADCs

Chapter 2: Switched-Current Building Blocks for

Modulators

2.1 Introduction 2.2 Principle of Operation: The Current Memory Cell 2.3 SI Integrators 2.3.1 Review of discrete-time integrators 2.3.2 SI delay elements 2.3.3 SI non-inverting integrators 2.3.4 SI inverting integrators 2.3.5 Generalized SI integrators

2.4 SI Differentiators 2.4.1 Discrete-time differentiators 2.4.2 Inverting SI differentiators 2.4.3 Non-inverting SI differentiators 2.4.4 Bilinear SI differentiators

2.5 SI Resonators 2.5.1 Biquad filter background 2.5.2 Discrete-time resonators 2.5.2.1 Resonator structures based on differentiators and integrators 2.5.2.2 Delay element based resonators 2.5.3 SI Resonators 2.5.3.1 SI LDI loop resonators 2.5.3.2 SI FE loop resonators 2.5.3.3 SI delay loop resonators

2.6 SI quantizers 2.7 Current Mode 1-bit D/A Converters

55 57 61 61 62 64 69 73

74 74 75 77 78

80 80 83 84 88 89 90 94 98

100 103

Chapter 3: Mechanisms of Error in Switched-Current Circuits 3.1 Introduction 3.2 Finite output-input conductance ratio error 3.2.1 Linear analysis 3.2.2 Non-linear analysis 3.2.3 Effect of the finite steering switch-on resistance 3.2.4 Circuit strategies to reduce the finite output-input conductance ratio error

107 108 109 112 116 121

ix

3.3 Charge injection error

127

3.3.1 Analysis and modelling of the charge injection error 3.3.2 Impact of the charge injection error on the performance of the memory cell 3.3.3 Circuit strategies to reduce the charge injection error 3.3.3.1 Dummy switch compensation technique 3.3.3.2 Circuit replication technique 3.3.3.3 Zero-voltage technique 3.3.3.4 Algorithmic technique – the 3.3.3.5 Fully-differential circuits

memory cell

3.4 Settling error

128 132 135 136 137 140 140 143

146

3.4.1 Linear analysis of a simple memory cell 147 3.4.2 Linear analysis of enhanced cells 150 3.4.3 Non-linear settling error 153 3.4.4 Stationary input signals 154 3.4.5 Non-stationary input signals 158 3.4.5.1 Phase delay and uncertainty of the sampled current caused by non-stationary input signals 163 3.4.5.2 Harmonic distortion due to non-stationary input signals 165

3.5 Mismatch error 3.5.1 Effect of mismatch error on the gain stage of second-generation memory cells 3.5.2 Effect of mismatch error on fully-differential second-generation memory cells

3.6 Electrical noise 3.6.1 Noise analysis of a memory cell 3.6.1.1 Noise of the cell on the sampling phase 3.6.1.2 Noise of the cell on the hold phase 3.6.1.3 Equivalent noise bandwidth

3.7 Maximum signal range – Class AB memory cells 3.8 Other mechanisms of error 3.8.1 Junction leakage current error 3.8.2 Current glitches 3.8.3 Effect of clock signal: clock jitter and uncertainty on the sampling instant 3.8.3.1 Clock jitter 3.8.3.2 Uncertainty on the sampling instant

3.9 Design considerations for SI memory cells

169 170 174

177 179 181 183 184

187 189 190 191 192 192 193

195

Chapter 4: Non-Ideal Performance of Switched-Current Bandpass Modulators 4.1 Introduction 4.2 Ideal noise shaping in fourth-order bandpass modulators 4.3 Impact of linear errors on the performance of SI integrators

203 204 208

4.3.1 Effect of

on the transfer function of LD integrators

209

4.3.2 Effect of


211

x

4.3.3 Effect of

211


4.4 Impact of linear errors on the performance of SI resonators

212 212 214

4.4.1 Effect of memory cell errors 4.4.2 Effect of resonator loop gain errors

219 4.5 Non-ideal quantization noise shaping in fourth-order 4.6 Cumulative influence of SI errors on the quantization noise shaping 225 227 230 231

4.6.1 Effect of cumulative errors on the performance of the memory cell 4.6.2 LD Integrator considering cumulative errors 4.6.3 Noise shaping degradation with cumulative errors

235

4.7 Harmonic distortion due to non-linear SI errors

236 4.7.1 Harmonic distortion due to static non-linear errors 4.7.1.1 Simple model for the memory cell in the presence of static non-linear errors 236 238 4.7.1.2 Harmonic distortion in fully-differential SI integrators 4.7.1.3 Harmonic distortion in fully-differential SI resonators 242 247 4.7.1.4 Harmonic distortion in SI fourth-order bandpass modulators 249 4.7.2 Harmonic distortion due to the settling error 4.7.2.1 Harmonic distortion in fully-differential SI integrators due to settling error 251 4.7.2.2 Harmonic distortion in SI resonators due to the settling error 254 4.7.2.3 Harmonic distortion in SI fourth-order due to the settling error 258 260 4.7.3 Harmonic distortion caused by the sampling-and-hold process 263 4.7.4 Harmonic distortion due to resonator loop gain errors 4.7.4.1 Harmonic distortion in fully-differential integrators due to non-linear scaling errors 264

4.7.4.2 Harmonic distortion in 4th-order

due to non-linear scaling errors 265

4.8 SNR degradation due to non-linear SI errors 4.9 Thermal noise in bandpass modulators

268 271 272 273 275

4.9.1 Noise analysis of SI integrators 4.9.2 Input-equivalent thermal noise of a fourth-order 4.9.3 In-band thermal noise power for simple memory-cell based

Chapter 5: Behavioral Simulation of Switched-Current

Modulators

5.1 Introduction 5.2 Simulation of SI circuits

279 282

5.2.1 An overview of existing SI simulation tools 5.2.2 Behavioural simulation of SI circuits

282 285

5.3 Behavioural modeling of SI integrators

287

5.3.1 Modeling of SI integrators 5.3.1.1 Calculation of the stationary drain current 5.3.1.2 Transient response 5.3.1.3 Calculation of the charge injection error 5.3.1.4 Thermal noise 5.3.1.5 Calculation of the memorized drain current for both memory cells

288 290 293 298 301 302

xi

5.3.1.6 Calculation of the output current 5.3.2 Behavioural modeling of the first memory cell in the modulator chain 5.3.3 Behavioural modeling of SI resonators

5.4 Behavioural Modeling of 1-bit Quantizers and D/A Converters 5.4.1 Current Comparators 5.4.2 1-bit D/A converters

304 306 307

308 309 311

5.5 SDSI: A MATLAB based behavioural simulator for SI

modulators 312

5.5.1 Description of the tool 5.5.2 Implementing SI behavioural models in SIMULINK 5.5.3 Graphical User Interface of SDSI

312 314 320

5.6 SDSI Application:Effect of Sl errors on single-loopLP and BP 5.6.1 Modulator topologies and models 5.6.2 Performance degradation due to SI errors

modulators 324 325 326

Chapter 6: Practical IC Implementations 6.1 Introduction 6.2 Bandpass modulators for AM digital radio receivers 6.3 Switched-current implementation 6.3.1 Memory cell 6.3.1.1 Design considerations 6.3.1.2 Memory cell performance 6.3.2 SI Integrator 6.3.3 SI Resonator 6.3.4 1-bit Quantizer 6.3.5 1-bit D/A Converter 6.3.6 Complete schematic of the modulators

343 343 346 353 358 361 364 365

6.4 A high frequency current mode buffer

365

6.4.1 Illustrating the Speed Degradation in SI Interfaces 6.4.2 Circuit Description

366 368

6.5 Practical design issues

369

6.5.1 Clock phase generator circuit 6.5.2 Layout considerations

370 372

6.6 Experimental results 6.6.1 Measurement set-up 6.6.1.1 Mixed-signal printed circuit board 6.6.1.2 Instrumentation and test set-up 6.6.2 Measured results 6.6.2.1 Current mode buffer 6.6.2.2 SI resonator 6.6.2.3 SI fourth-order bandpass modulator 6.6.2.4 SI second-order bandpass modulator 6.6.3 Comparison to the predictive results of the SI bandpass

337 339 343

376

modulators

377 378 381 383 383 384 392 395 399

xii

6.7 Illustrating by measurements the performance degradation with SI errors 403

References

413

Appendix A: Distortion analysis of SI memory cells with nonstationary input signals using Volterra series

431

Appendix B: Effect of mismatch error on the performance of a memory cell with non-unity gain

439

Index

445

List of Figures

1.1 1.2 1.3 1.4 1.5 1.6 1.7

1.8

1.9 1.10 1.11 1.12 1.13 1.14 1.15 1.16 1.17

1.18 1.19 1.20 1.21 1.22 1.23 1.24 1.25 1.26

Analog RF superheterodyne receiver 2 Ideal digital RF receiver. 3 Digital RF receivers. a) Superheterodyne. b) Direct conversion. c) IF conversion. 4 Operation of an ADC. a) Basic scheme. b) Signal processing. 6 Application range of several ADC architectures in the resolution–speed plane. 7 Anti-aliasing filtering of: a) Nyquist-rate converters. b) Oversampling converters. 8 Ideal quantization process. a) Ideal transfer characteristic. b) Quantization error. c) Probability density function of additive, white quantization noise. d) Linear model of an ideal quantizer. 9 Block diagram of an oversampling ADC. 10 11 a) Basic structure of a modulator. b) Quantization noise filtering. Block diagram of a first-order 1-bit lowpass modulator. 15 Pattern noise for a first-order lowpass modulator with M = 64 . 16 Block diagram of the single-loop 2nd-order lowpass modulator. 17 Block diagram of a Lth-order single-loop lowpass modulator. 18 Interpolative (Lee-Sodini) Lth-order lowpass modulator . 20 Conceptual block diagram of a cascade 20 Fourth-order , 2-2 cascade modulator. 21 Digitizing a signal in a digital superheterodyne RF receiver using: a) Two lowpass 24 ADCs. b) One bandpass ADC. 25 Conceptual block diagram of a (a)Ideal output spectrum of a 4th-order (b) SNR vs. M . 27 Choice of the signal passband location. a) Trade-off among antialiasing filter requirements and high values of b) Trade-off among image-rejection filter requirements 29 and low values of to the derived by applying Block diagram of the of Fig. 1.13. 30 Zero location of for: 31 a) 2th-order derived from the obtained by using of Fig. 1.10. b) 4th-order derived from the of Fig. 1.12. c) 8th-order 4-4 derived from the of Fig. 1.16. 32 Pattern noise for a 2nd-order bandpass modulator with M = 64 . 33 An example of a 4th – order obtained using the directly method [Jant93]. a) Modulator architecture. b) Pole/zero location of and c) vs. frequency. 37 and RF radio receiver schemes using a) Typical. b) Using quadrature mixer. c)

xiv

38 Using quadrature 39 1.27 Conceptual block diagram of a quadrature th and quantization noise zero location for a quadrature 4 -order 39 1.28 1.29 Realization of complex filters. a) Conceptual block diagram. b) Complex filter with a 40 single pole. 41 1.30 N – path filter structure. 42 1.31 Conceptual diagram of a 2-path fourth-order 1.32 High-pass filter implementation. a) Using an integrator in a feedback loop. b) Us43 ing chopping. (a) Conceptual block diagram. (b) Open loop 1.33 Basic architecture of a 44 block diagram. 47 b) 1.34 Decimation process. a) 48 1.35 Efficient decimator for for the modulators in 1.36 Power consumption divided by resolution as a function of 50 Table 1.3. 52 for lowpass modulators. 1.37 FOM vs. 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9

2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19

Principle of operation of switched-current circuits. a) Basic circuit. b) Sampling 57 phase. c) Hold phase. First-Generation current memory cell. a) Output current provided on clock phase b) Output current provided on all clock phases. c) Clock phase diagram. d) 58 Transient response. 60 Second-generation current memory cell. Synthesis of an inverting FE SC integrator. a) Original CT integrator. b) SC resistor. 61 c) Resulting SC integrator. Delay blocks. a) Full clock period delay cell. b) A 4/3 clock period delay cell. c) Delay 63 line. d) N-path equivalent block diagram of the delay line. 65 Z-domain block diagram of a non-inverting integrator. SI Non-inverting lossless integrators. a) Two-clock phase delay cell with feedback. b) Simplified structure for (a). c) Three-clock phase structure. d) N-clock phase structure. 66 68 Non-inverting damped integrator. SI Inverting lossless integrators. a) Two-clock phase structure which implements the 70 SC LD integrator transfer function. b) Three-clock phase structure. 72 Inverting damped integrator. 73 Generalized integrator. 74 Bilinear SI integrator. a) Lossless. b) Damped. SI inverting differentiator. a) Z-domain block diagram. b) SI realization. 75 77 SI non-inverting differentiator. a) Z-domain block diagram. b) SI realization. 79 Bilinear SI differentiator. a) Z-domain diagram. b) SI realization. 84 Ideal response of a resonator. a) Bode diagram. b) Transient response. LDI-loop resonator. a) Block diagram. b) Movement of poles with errors. 85 Impulsive response of an LDI-loop resonator. a) Bode diagram. b) Impulsive response. 86 86 FE-loop resonator. a) Block diagram. b) Movement of its poles with errors.

xv

2.20 Impulsive response of the FE-loop resonator. a) Bode diagram. b) Impulsive response. 87 2.21 Resonator based on a differentiator and an integrator. a) Block diagram. b) Movement of its poles with errors. 88 2.22 Delay element based resonator structures. a) Two-delay loop. b) Programmable resonant frequency structure with double delay. c) Programmable resonant frequency structure with no delay. 89 2.23 Conceptual realization of an SI LDI-loop resonator. 90 2.24 N-phase inverting integrator-based resonator. a) Block diagram. b) 3-phase implementation. 91 2.25 Sensitivity of (a) and (b) to SI gain errors in the LDI-loop resonator. 93 2.26 Simulation of a 2-phase SI LDI-loop Resonator. a) Effect of on the output spectrum of the resonator. b) Effect of 94 2.27 SI FE-loop resonators. a) 2-phase integrator-based structure. b) 3-phase integratorbased structure. 95 2.28 Sensitivity of Q and in FE-loop resonators. 97 2.29 Simulation of a 2-phase SI FE-loop Resonator. a) Effect of b) Effect of 97 2.30 SI delay-loop resonators. a)Blockdiagram. b)2-phase memory cell delay-loop resonator. 98 2.31 Ideal operation of current comparators. a) Ideal behaviour. b) Basic architecture. 100 2.32 Basic structure of a capacitive CT current comparator. a) Single-ended. b) Fully-differential. 101 2.33 Current Comparator with non-linear negative feedback. 102 2.34 DT current comparator with positive feedback based on a regenerative latch. 103 104 2.35 1-bit current mode DACs used in SI 3.1

3.2

3.3 3.4

3.5 3.6 3.7

Linear model for the memory cell with finite output-input conductance error. a) Simple second-generation memory cell. b) Small signal equivalent circuit. c) Simplified 108 equivalent circuit including goQ . Transmission error caused by the finite output-input conductance ratio. a) Connection of two memory cells in series. b) Small signal equivalent circuit during clock phase 110 c) Small-signal equivalent circuit during clock phase Variation of both the output and the input conductances of the memory transistor over 113 a signal period (HSPICE). a) b) c) Harmonic distortion due to the non-linear output-input conductance ratio error. a) vs. memory transistor length and vs. the modulation index. b) 117 for Transmission error caused by the steering switch-on resistance. a) Connection of two memory cells. b) Equivalent circuit for linear switch-on resistance. c) Equivalent cir118 cuit for non-linear switch-on resistance. Circuit strategies to reduce a) Simple cascode memory cell. b) Source follower 122 cascode memory cell. c) Regulated cascode memory cell. Circuit strategies for increasing a) Folded-cascode memory cell. b) Regulated folded-cascode memory cell. c) Opamp active memory cell. d) Grounded-gate active 125 memory cell. e) Grounded-gate regulated cascode memory cell

xvi

3.8 3.9

3.10 3.11 3.12 3.13

3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.23 3.24 3.25 3.26 3.27 3.28 3.29

The charge injection error mechanism. a) Simple memory cell. b) Regions of operation of c) Turn-off transient of 127 Simulation (HSPICE) of the charge injection error. a) Voltage error, b) Current error, 131 Transmissionerror caused by in the connection of N memory cells in series. Propagation of the output offset current. 134 Circuit strategies to reduce based on dummy compensation technique. a) Dummy switch. b) Tunable feedthrough cancellation. 136 Cancellation of using dummy transistors. (HSPICE, level-47 MOS models were used). 137 Circuit strategies to reduce based on circuit replication. a) Cancellation of the signal-independent part [Yang90b].b) Cancellation of the signal-dependent part [Song93]. c) Cancellation of both the signal-independent and the signal-dependent parts [Jons93]. d) Combination of circuit replication and double-sampling [Min98]. 138 Memory cell using the zero-voltage technique [Nair94]. 140 Circuit strategies to reduce based on the algorithmic technique. a) Algorithmic memory cell [Toum90b].b) Two-step Memory Cell [Hugh93c]. c) Improved two-step memory cell [Helf98b]. d) n-step memory cell [Helf98b]. 141 Simulation (HSPICE) of a current error in an memory cell for different values of 143 Conceptual fully-differential SI memory cell. 144 Simulation (HSPICE) of the charge injection error in a fully-differential memory cell. 144 a) Without dummy switch. b) With dummy switch. Linear model of the incomplete settling error for a simple memory cell. a) Memory cell. b) Small-signal equivalent circuit during the sampling phase. 147 Step response of the regulated folded cascode memory cell. 152 Montecarlo simulation of the step response of the regulated folded cascode memory and cell. Nominal conditions: and 10% standard deviation from nominal values. 153 Non-linear model of the incomplete settling error for a fully-differential memory cell. a) Memory cell. b) Equivalent circuit during the sampling phase. 154 Approximation of 157 Comparison with the previous models and HSPICE. 158 Transient evolution of the drain current for an input sinusoidal signal of amplitude and and frequency 159 Conceptual model of a memory cell with continuous-time input signals. a) Block dia162 gram. b) Linear equivalent circuit. Phase delay and uncertainty of the sampled current caused by an non-stationary (sinusoidal) input signal of Effect of the sampling frequency. a) HSPICE. b) Theory. 163 Phase delay and “Jitter” caused by a non-stationary (sinusoidal) input signal. Effect of the input frequency 164 b) a) Phase delay and uncertainty of the sampled current caused by sampled-and-held sinusoidal input signals (HSPICE). 165

xvii

3.30 Comparison between the harmonic distortion caused by a non-stationary input signal and a stationary input signal. a) Output spectrum for b) as a function of (HSPICE). 166 3.31 Comparison of the numerical simulation of (3.143) with HSPICE. 167 3.32 Comparison of the theoretical model with simulation. a) vs. b) vs. 168 3.33 Second-generation memory cell with output gain stage. a) Single-ended. b) Fully-differential. 171 3.34 Fully-differential memory cell. 174 3.35 Effect of mismatch error on fully-differential second-generation memory cells. 176 3.36 vs. for different values of 177 3.37 Noise model in a MOS transistor. a) Current noise. b) Voltage noise. 177 3.38 Noise analysis of a memory cell. a) Noise sources of the cell. b) Equivalent circuit on the sampling phase. c) Equivalent circuit on the hold phase. 179 3.39 Equivalent noise bandwidth, a) Concept. b) No aliasing occurs, Aliasing occurs, 185 3.40 PSD of the equivalent noise power. Comparison with HSPICE. 187 3.41 Basic class AB memory cell. 188 3.42 Parasitic pn junctions of a memory cell. a) Different leakage current sources associated to the memory cell. b) Equivalent circuit at the gate node. 190 3.43 Strategies to reduce current glitches. a) Four clock phase diagram. b) Connection to a dummy voltage during the phase when the output is not connected to another cell. 192 3.44 Uncertainty on the sampling instant. 193 for main SI errors. 3.45 Comparison of 196 198 3.46 FOM vs. 3.47 Harmonic distortion and thermal noise as a function of the bias current for different voltage supplies. a) 199 b) a) For 200 3.48 SNDR vs. vs. b)

4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

4.9

Architecture of the fourth-order a) Original second-order, 1-bit ) Resulting bandpass modulator. 205 DR vs. M for a fourth-order bandpass modulator. 206 Architecture of the bandpass modulator under study. 207 Histogram of the resonator outputs in the 4th-order 208 (a) Conceptual realization of a LD integrator including output and input conductances. (b) Small signal equivalent circuit on clock phase of period c) Small signal equivalent circuit on clock phase of period 209 212 Conceptual SI realization of an LDI-loop resonator. Error on the resonant frequency as a function of the settling error. 214 Conceptual realization of an LD integrator including resonator loop gain errors due to finite output conductances. b) Small-signal equivalent circuit on clock phase c) 215 Small-signal equivalent circuit on clock phase Conceptual schematic of the LDI-loop resonator including non-ideal output stages.

217

xviii

Comparison between the effect of settling and scaling errors. a) Effect on the ratio of the poles. b) Effect on the frequency of the poles. 218 4.11 Influence of SI errors on the quantization noise shaping. Effect of: a) b) c) 221 d) 4.12 Comparison of theory and simulation. Effect of a) 4.10

223 4.13 224 4.14 DR vs. Error. 225 4.15 SNR degradation predicted by (a) Eq. (4.36). (b) Eq. (4.37). 226 4.16 Cumulative Error. a) Memory acquiring an input current. b) Equivalent circuit during 228 clock phase c) Equivalent circuit on clock phase 4.17 Total error of the memorized drain current. 229 4.18 LD Integrator with cumulative errors. a) Schematic. b) Small signal equivalent circuit 230 on clock phase 1. c) Small-signal equivalent circuit on clock phase 2. 4.19 SNR degradation vs. for an input signal of -6dB amplitude. a) M = 128, M = 256. b) SNR vs. M for different values of and 233 4.20 Error bound vs. DR loss for different values of M. 234 4.21 Notch Frequency Degradation with SI Errors. 235 4.22 Fully-Differential LD SI integrator. 238 4.23 at the output of the integrator as a function of for different values of the input signal frequency. 241 4.24 Third-order harmonic distortion in fully-differential LD SI integrators due to non-lin4.25 4.26 4.27 4.28 4.29 4.30 4.31 4.32

4.33

4.34 4.35

vs. ear 242 LDI-Loop Resonator. 242 referred to the resonator output as a function of for several values of the in 244 put frequency and amplitude Fully-differential regulated folded-cascode memory cell. 245 245 Non-linear input impedance in regulated folded-cascode memory cells. Harmonic distortion at the output of an SI resonator caused by the non-linear input im246 pedance of regulated folded-cascode memory cells. Block diagram of a fourth-order 247 as a function of due to static errors in fourth-order for difa) terent values of b) Output spectra for 250 at the output of a fourth-order due to the non-linear input impedance of vs. regulated folded-cascode memory cells. a) b) Output spectrum cor(Amplitude of each input responding to and tone: 251 Effect of the non-linear settling on the harmonic distortion of a fully-differential LD integrator. a) as a function of for different values of as a b) function of for different values of 255 Harmonic distortion at the output of an LDI-loop resonator caused by the non-linear settling error. 258 as a function of for different values of and an input signal consisting on two input tones at a) and Output spectra for

xix

4.36 4.37 4.38 4.39 4.40 4.41 4.42

4.43

4.44 4.45 4.46 4.47 4.48 4.49 4.50 4.51 5.1 5.2 5.3 5.4 5.5

5.6 5.7 5.8 5.9

different values of 259 as a function of for different values of and an input signal consisting on two input tones at and 260 Z-Domain block diagram of the fourth-order for the calculation of the amplitude of the input of the first memory cell. 261 Harmonic distortion at the output of the modulator caused by the sampling-and-hold process. 262 Comparison of the harmonic distortion caused by the incomplete settling error and the sampling-and-hold process 263 Fully-Differential LD SI integrator with gain 264 Third-order harmonic distortion at the output of the integrator as a function of for different values of the input signal frequency 265 Third-order harmonic distortion (simulation) at the output of a fourth-order as a function of for different values of the DAC reference current 266 Third-order intermodulation distortion at the output of a fourth order due to non-linear gain errors on the output stages of the integrators. a) Effect of both integrators. b) Isolate effect of each integrator (Amplitude of each input tone equal to 267 Quantization noise increase due to SI non-linear errors. 268 (a) Equivalent block diagram of the fourth-order with non-linear errors. (b) Histogram of and for –6dB input level . (c) Histogram of and for –30dB input level . 270 for a fourth-order SNR vs. for several input signal levels. 271 Noise analysis of an FE integrator. 272 Equivalent block diagram of the 4th-order bandpass modulator with thermal noise contributions. 274 Equivalent circuit to calculate the input noise of 4th-order 274 Trade-off between harmonic distortion and dynamic-range. 277 SNDR vs. 277 The SI integrator as a basic block. 286 SI Fully-differential regulated-folded cascode LD integrator. 288 Simulated (HSPICE) step response of the SI integrator of Fig. 5.2. 289 Equivalent circuit for the integrator of Fig. 5.2 on clock phase using a linear midabstraction level model. 291 Non-linear input conductance modelled with a high abstraction level. a) simulated in HSPICE. b) Transmission error resulting from the connection of two memory cells in series for different values of 292 Flow graph to estimate the steady-state of 294 Equivalent circuit for the calculation of the transient response. 295 Equivalent circuit for the transient response of the memory cell in the linear case. a) 296 Complete circuit. b) Half circuit. Non-linear step response of the differential memory transistor gate-source voltage. 299

xx

5.10 Complete model for the calculation of the drain current. 303 5.11 Mid-abstraction level modeling of the output stage. a) Integrator in the clock phase in which it delivers its output. b) Equivalent circuit. 305 5.12 Transient evolution of the drain current for an input sinusoidal signal of amplitude and frequency 307 5.13 Impulsive response of an SI resonator. a) Effect of output-input conductance ratio error. b) Cumulative effect of conductance ratio and settling error. 309 5.14 Transfer function of a current comparator. a) Ideal. b) Non-Ideal including deterministic hysteresis. c) Non-Ideal including random hysteresis. 310 311 5.15 Comparator model flow graph. 312 5.16 Model of the 1-bit D/A converter. 313 5.17 Structure of the simulator. 314 5.18 “Step-by-step” diagram to create a new SI model in SDSI. 315 5.19 Fully-differential regulated folded-cascode memory cell. 5.20 Example of C MEX-file S-function corresponding to a fully-differential regulated folded-cascode memory cell. 316 5.21 C file containing the models for the fully-differential regulated folded-cascode memory cell errors. 318 5.22 C file containing the model for the transient behaviour in case of memory cells with continuous-time input signals. 319 5.23 SDSI model of the fully-differential regulated folded-cascode memory cell of Fig. 5.19. 320 321 5.24 SDSI mam window. 321 5.25 Setting global parameters and simulation options. 5.26 Building the circuit topology. a) Creating a new SIMULINK window. b) Incorporating a building block from available libraries into the circuit. 322 323 5.27 Spectrum analysis Window modulators. b) Bandpass modulators. a) Lowpass 5.28 Analysis of output data in modulators. 324 5.29 Z-domain block diagram of the modulators under study. a) Second-order lowpass modulator. b) Fourth-order bandpass modulator. 325 5.30 SDSI block diagram for the modulators of Fig. 5.29. a) Second-order lowpass modulator. b) Fourth-order bandpass modulator. 325 5.31 Effect of non-linear gain errors on the output spectrum of a) Second-order b) c) Fourth-order as a function of 327 5.32 Effect of mismatch gain errors on the of Fig. 5.30. a) Impact on the resonator output spectrum. b) SNR vs. relative Input Amplitude. 328 5.33 Effect of linear Modulator outout spectra for several values of a) Second-order b) Fourth-order c) Half-scale SNR as a function of (Output stages for the integrators are ideal) 329 5.34 Effect of linear Modulator output spectra for several values of a) Second-order b) Fourth-order c) Half-scale SNR as a function of 330 5.35 Effect of non-linear Modulator output spectra for different values of a) Lowpass. b) Bandpass. c) d) Intermodulation distortion caused by the increase of vs. e) Caused by the increase of 332

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5.36 SNR as a function of the comparator hysteresis for the modulators of Fig. 5.30. . 333 5.37 Notch frequency degradation with SI errors. a) Output spectra for different values of and b) Output spectra for different values of the sampling frequenand for c) Notch frequency error against (settling error negligible). d) Notch frequency error against for 334 5.38 Effect of cumulative errors on the SNDR of a fourth-order bandpass modulator. All errors equal to 0.5%. 335 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9

6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19

6.20 6.21 6.22 6.23 6.24 6.25 6.26 6.27

Dynamic range of a second-order 339 Dynamic range of a fourth-order 341 Architecture of the a) Bandpass. b) Original lowpass. 341 Architecture of the a) Bandpass. b) Original lowpass. 342 Ideal output spectra of: a) b) 343 Circuit strategies to reduce a) Regulated-cascode. b) Regulated folded-cascode. 344 memory cell. 344 Schematic of the memory cell. 346 Characterization of in HSPICE. a) Differential input voltage as a function of the input signal amplitude. b) Output conductance as a function of the memory transistor 348 drain current. Charge injection error of the memory cell (HSPICE). a) Differential voltage error in 350 the gate. b) Differential current error. Characterization of the settling error. a) Transient response of the memory cell. b) 351 Settling error as a function of the sampling frequency. 352 Harmonic distortion due to non-stationary input signals. 354 Schematic of the integrator input stage. 357 Schematic of the integrator including the output stage. 358 Transient response of the integrator. 358 Complete schematic of the resonator. Simulated (HSPICE) impulsive response of the resonator at different clock frequen360 cies, a) 1MHz. b) 10MHz. 362 1-bit quantizer. a) Schematic. b) Clock phase waveforms. Impact of mismatch errors on the quantizer performance. a) Transient evolution of both the input current and the output voltage of the comparator. b) Input/Output trans364 fer characteristics. 365 Schematic of the 1-bit D/A converter Schematic of the modulators in this chapter. a) Second-order bandpass modulator. 366 b) Fourth-order bandpass modulator. a) Conceptual 2nd generation SI memory cell. b) front-end SI memory cell. c) Front367 end of an SI circuit. 368 Schematic of the current mode buffer. 370 Clock phase diagram for second-generation SI circuits. 371 Connection of two memory cells in series. 371 Clock phase generator schematic. Clock phase transitions obtained by layout-extracted simulation of the clock phase

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generator circuit. 372 374 6.28 Layout recommendations for mixed-signal chips. modulator. 375 6.29 Layout of the fourth-order SI bandpass modulator. a) Microphotograph of 6.30 Chip containing the SI fourth-order bandpass the chip. b) Package diagram. 376 6.31 Test chip containing: a current mode buffer, an SI LDI-loop resonator and an SI a) Microphotograph of the chip. b) Package diagram. 377 modulator. a) Photo6.32 PCB for the characterization of the SI fourth-order bandpass graph. b) Schematic. 379 380 6.33 PCB for the test chip. a) Photograph. b) Schematic. 6.34 Test Set-up. a) For SI bandpass modulators. b) For SI blocks (current mode buffer 382 and SI resonator). 383 6.35 Input/Output Transfer Characteristics. 384 6.36 Experimental Bode Plot of the current buffer. 385 6.37 Conceptual schematic of the testing setup for the SI resonator. 6.38 Measured impulsive responses of the resonator when clocked at different frequencies c) 386 in the AM range. a) b) 387 6.39 Measured impulsive response of the resonator when clocked at 6.40 Measured impulsive response of the resonator for an input amplitude of 388 a) c) Zoom in of (a). b) b) 389 6.41 Measured errors in the resonator transfer function: a) Comparison between worst-case speed condition HSPICE simulations 6.42 390 and experimental results. 391 6.43 Movement of the poles with for different values of 391 6.44 Resonant frequency as a function of 6.45 Measured modulator output spectra for a sinusoidal signal or –6dB input level and commercial AM IF input frequencies. a) 488kHz input frequency (2MHz sampling 392 frequency). b) 1.63MHz input frequency 393 6.46 Measured intermodulation distortion. 6.47 Measured SNR vs. input level for a sinusoidal input signal with AM IF frequency. a) SNR vs. input level for different sampling frequencies and M=128. b) SNR vs. relative amplitude for different sampling frequencies and Bw = 10kHz. 394 6.48 Measured modulator output spectra above AM Frequencies. a) 10MHz sampling frequency and input sinusoidal signal of –6dB @2.44MHz. b) 16MHz sampling frequency and input sinusoidal signal of –6dB @3.8MHz 395 6.49 Measured modulator output spectra above AM Frequencies. Input frequency at a) 10MHz sampling frequency and input sinusoidal signal of –6dB @7.56MHz. b) 14.28MHz sampling frequency and input sinusoidal signal of –6dB @ 10.87MHz. 395 6.50 Measured modulator output spectra for a sinusoidal signal of -6dB input level and commercial AM input frequencies. a) 500kHz input frequency (2MHz sampling fre396 quency). b) 1.67MHz input frequency for an input tone 6.51 Measured modulator output spectra when clocked at of and different relative amplitudes: a) –16.3dB ,b) –13.8dB , c) –11.3dB , d) –8.7dB . 397

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6.52 Idle tones for an input tone at as a function of 398 6.53 Measured SNDR vs. input level for different AM frequencies when the input signal frequency is 398 6.54 Measured modulator output spectra for a sinusoidal signal of -6dB input level and commercial AM input frequencies. a) 491kHz input frequency (2MHz sampling frequency). b) 1.63MHz input frequency 399 6.55 Measured modulator output spectra for an input tone at and different input levels (a) –14.8dB , (b) –9.7dB and (c) –4.8dB 400 6.56 Measured SNDR vs. input level for different AM frequencies for an input signal frequency at 400 6.57 Measured and theoretical Half-Scale SNR vs. obtained in a 50kHz band centered at 401 6.58 Half-Scale SNR vs. M for and an input tone of –6dB@ 976kHz and –6dB @981kHz for the and the respectively. 402 6.59 Half-Scale SNR against the oversampling ratio for in the second-order Comparison between measurements and theory. 402 6.60 Performance degradation caused by non-linear input impedance. Output spectra for different values of a) Measured. b) Simulated (nominal conditions). c) Simulated (worst-case speed vs. nominal conditions). 404 a) Measured. b) Simulated. 405 6.61 SNDR vs. input level for different values of 6.62 Intermodulation distortion due to the non-linear input impedance. a) Measured output Measurements vs. simulations. spectra for different values of 406 407 6.63 Notch frequency position as a function of a) Output spectra for different values of 6.64 Performance degradation with b) 408 Notch frequency shift, 6.65 Harmonic distortion caused by the non-linear sampling-and-hold. Output spectra for different sampling frequencies. a) Measured results for the AM bandwidth. Results 409 beyond AM (10MHz). b) Measured. c) Simulated. A.1 B.1

SI simple memory cell. a) Schematic. b) Equivalent circuit. c) Equivalent circuit dur434 d) Equivalent circuit during the hold phase ing the sampling phase 439 Second-generation memory cell with output stage of gain

List of Tables

1.2 1.3 1.4

Relationships between analog and digital coefficients for the modulator of Fig. 1.16 21 46 Equivalent CT and DT loop filter transfer function for a 2nd – order 49 Summary of bandpass modulators published up to now 52 Summary of SI lowpass modulators published up to now

2.1 2.2

Classification of SC integrators Classification of SC Differentiators

3.1 3.2

for different types of memory cells Summary of non-ideal performance of fully-diff. SI memory cells

183 195

4.1 4.2 4.3 4.4 4.5 4.6

Degradation of the memory cell transfer function due to main SI errors Resonator transfer function degradation with memory cell errors Resonator transfer function degradation with SI errors Quantization Noise Shaping Degradation Quantization Noise Power Degradation forsome errors in the memory cell and

208 213 219 220 222 237

6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8

Transistor sizes for the memory cell 347 Small-signal transconductance and drain-source conductance of the memory cell 349 352 Changes on the nominal capacitance of MOST capacitors Simulated performance (HSPICE) of the memory cell 354 Sizes of the integrator 355 Simulated performance (HSPICE) of the integrator 356 Performance Summary of the Current-Mode Buffer 369 Measured performance of the modulator 394

1.1

62 75

Preface

As in modern IC circuits, high precision analogue circuits occupy just a small portion of the total chip area. The technology trend is driven by digital requirements with well established MOS technology, the realisation of analogue sampled data circuits has become possible and these circuits have widely been employed in many application specific integrated circuits (ASIC). Attempts to develop analogue sampled-data circuits which are compatible with standard digital CMOS process technology has led to switched currents. From the early implementation of switched currents for filter designs and the successful implementation of numerous high frequency, high order filters, attention has more recently been applied to the application of switched currents to oversampling data converters. The sigma delta converter is a technique where analogue accuracy in the amplitude domain is transferred to the time domain. The marriage between switched currents using polysilicon digital CMOS and the sigma delta modulator using digital circuit techniques has provided a powerful, high performance, systematic design tool for bandpass sigma-delta modulators for digital communication chips. This book provides an excellent treatment of the design and application of switched currents to bandpass sigma delta modulators. The book is structured to give the reader a very comprehensive review of both the details and mechanisms resulting in transmission errors in switched-current cells and how these errors manifest themselves in bandpass sigma-delta modulators. Special emphasis is also placed on the computer-aided-design (CAD) infrastructure, in particular, the much desired area of behavioural simulation. This is a significant contribution to the field, and for the first time will enable both designers and researchers to simulate realistic, high order sigma-delta converters in reasonably short times in addition to the important design feedback provided by the simulator. The depth of analysis, particularly with the error mechanisms in the first three chapters, as far as I am aware, has not been handled with such rigour and details elsewhere. To pull the work together the authors have concluded the book with two practical high performance demonstrator chips, based on switched-current bandpass sigma-delta modulators for AM radio. Again, both details of layout and measurement techniques as well as performance optimization are presented. The results of the chips serve to demonstrate the powerful design

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capability offered by the proposed simulator and realistic performance expected with state-of-art bandpass sigma modulators. With the trend for complex systems on a chip and the requirement for single chip mixed analogue and digital processors then this book is ideally suited for both the practising digital and analogue circuit design engineer as well as the researcher requiring theoretical insight into the mechanisms and trade-offs of sampled-data analogue systems in a digital CMOS processing environment.

Christofer Toumazou November 2001

Acknowledgments

We would like to express our gratitude to Professors Luis Hernández (Univ. Carlos III, Madrid), José Luis Huertas (IMSE-CNM, Seville), Andreas Kaiser (ISENIEMN, Lille), Fernando Medeiro (IMSE-CNM, Seville) and Chris Toumazou (Imperial College, London) for the review of this text. Specially, we wish to thank Prof. Medeiro for his valuable inputs on sigma-delta design issues, from system-level to measurements. This work has been partially supported by the EU ESPRIT Program in the framework of the Project #29261 (MIXMODEST), and by the Spanish CICYT under contracts TIC 1FD1997-1611 and TIC 2001-0929.


Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips

Prologue During the 80s and the 90s we have witnessed a pervasive trend towards replacing analog-based solutions by digital-based ones. Year by year the border between the analog and the digital has shifted to become closer and closer to the very analog signal interfaces. This trend has been parallel to the exponential increase of the capabilities of digital VLSI circuits, fueled by the evolution of microelectronic technologies towards deep submicron. Particularly in the area of telecommunications, electronic systems are mostly digital; basically only the analog circuits strictly needed to interface the front- and back-end analog signals remain. Today, many electronic communication systems are realized by connecting different chips on a PCB. For the analog interface circuitry designers basically rely on what is available in the different semiconductor catalogues. In future, however, the trend is towards integrating the analog circuitry on the same silicon substrate in which the digital core circuitry is realized. Thus, new generations of on-chip mixedsignal communication systems are coming into the picture. Together with reduced price, size and power consumption, these systems feature greater functionality through the closer interaction between the analog and the digital. For instance, the digital implementation of some functions such as channel selection and the demodulation of the signals coming from the antenna in a wireless transceiver, facilitates the programmability of these functions, thus allowing their adaptability to a great number of communication systems [Abid95]. Basic tasks realized at the interfaces of mixed-signal chips include data conversion, signal conditioning, amplification, driving, etc. This book deals with data conversion; specifically with analog-to-digital (A/D) conversion. There are many different techniques and architectures available for the A/D conversion task [Plass94] [Raza95] [Gust00]. The direct approach consists of sampling the input sig-

xxx


nal at the minimum rate for given bandwidth, the Nyquist rate, and then mapping these samples onto corresponding quantized digital representations by employing an analog circuit to generate code thresholds, and an array of analog comparators. This direct quantization provides the fastest operation for given technology; however, the granularity of the quantization, and hence the error produced in the process of quantization, can only be reduced by enhancing the analog circuitry, a process which is inherently limited by the random fluctuations of the underlying technological parameters. This problem can be partially overcome by resorting to the use of averaging, either spatial averaging, or temporal averaging. The converters addressed in this book belong to the second class; i.e., they employ temporal averaging to reduce the errors caused by quantization without enhancing the analog circuitry employed for the quantization itself. The price is that the input signal must be slow enough to allow for “redundant” samples to be taken. This book deals with the so-called Sigma-Delta or Delta-Sigma, converters [Nors97]. These converters are basically composed of two parts; namely, a mixedsignal modulator [Inos62] and a digital filter. The former is composed in turn of a low-resolution (i.e. low-precision) analog quantizer and filters. The operation of converters is simple to describe, although very difficult to analyze. On the one hand, samples are taken at a higher rate than the one dictated by the Nyquist frequency – input signal is oversampled. On the other hand, these samples are quantized with a large error by using a rude analog quantizer. A large portion of this error is then placed at the frequency band comprised between the Nyquist frequency and the actual sampling frequency through the combined action of oversampling and modulator filtering. Finally, this out-of-band error is removed by digital filtering. Hence, the outcome is that the in-band error is equal to what would might have been obtained through direct quantization with a quantizer of a much larger accuracy than the one implemented within the modulator section. This possibility of trading analog accuracy by signal processing and speed makes modulators very well suited for the implementation of analog interfaces in mixed-signal ICs intended for low- and medium-frequency signal bandwidths. Initially, efforts were focused on signals of the lowpass type. Current developments are trying to push these lowpass modulators into the telecom band [Mede99a]; for instance, for their application at the new generations of xDSL modems. Also, during the 90s these converters have found extensive usage in applications dealing with bandpass signals [Schr89]. This book focuses on the so-called bandpass A/D converters. These converters employ oversampling and filtering to achieve high-resolution in the conversion of

Prologue

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narrow-band signals (signal bandwidth much smaller than the carrier frequency) with low-accuracy analog quantizers. One of their main advantages as compared to other architectures comes from the fact that they do not need to digitize the whole Nyquist band; instead they digitize just the signal band, thereby requiring much less power consumption to obtain a similar dynamic range. To the best of our knowledge, the first bandpass IC prototype was reported by Jantzi in 1992 [Jant92]. Since then, many other ICs have been reported for quite diverse wireless communication applications. Namely: telemetry [Norm96]; digital AM/FM radio receivers [Jant93] [Sing95] [Enge99] [Loui99]; cellular phones with diverse commercial standards such as GSM [Shoa97], DECT [Taba99], etc. Among all these prototypes, those using Continuous-Time (CT) circuits achieve the highest speeds, and have been mainly implemented in bipolar or BiCMOS technologies [Shoa97] [Gao98]. In this book we consider Discrete-Time (DT) circuit techniques because they may be better suited for CMOS technologies. Most of the reported CMOS bandpass converters employ Switched-Capacitor (SC) circuits [Jant93] [Song95] [Hair96] [Ong97] [Jant97] [Baza98] [Chua98] [Taba99] [Toni99] [Baza99], and have been implemented in technologies that offer analog options. These options, for instance, the availability of thin-oxide thermal capacitors (poly-insulator-poly or metal-insulator-metal) or the availability of highresistivity layers, increase the production costs as compared to standard, digital CMOS technologies. To avoid such a price overhead, analog front-ends, in particular bandpass modulators, should be implemented by using only the primitives available in such standard technologies. In the case of SC circuits, it involves using either thick-oxide, multi-metal capacitor structures [Ong97], or thin-oxide Metal-InsulatorSemiconductor structures. On the one hand, the former structures have very poor matching properties. Among other reasons, this is due to imprecise polishing of the inter-metal oxide, which leads to large variations in the oxide thickness and permittivity [Lei98]. On the other hand, MOS capacitors [Baza95] [Yosh99], although they have good matching, exhibit a great inherent nonlinearity due to the fact that the bottom layer is a semiconductor. An alternative way to avoid the necessity of analog technology options is to use SwItched-current (SI) circuit techniques [Hugh89] [Toum93]. SI circuits do not require linear capacitors, although they require good matching. Hence, they can use MOS capacitors. Fortunately, the nonlinearity of these capacitors plays only a secondary role. SI circuits employ the MOS transistor as the basic primitive for the operations of

xxxii


delay and signal scaling. Because of the capacitive nature of the MOS gate, it is possible to store a voltage in it during a sampling phase, and to take the associated current during a later hold phase. In addition, it is easy to transmit and to scale these retained currents using only MOS transistors, which guarantees a total compatibility with CMOS technologies. But, in addition, the SI technique offers other advantages. On the one hand, as the signal is transmitted by currents, instead of by voltages as in the SC case, the dynamic range is not limited by the supply voltages. This fact makes the SI technique especially appropriate for low supply voltages. On the other hand, as operational amplifiers are not required for its implementation (as in the case of SC), high speeds can be achieved with a low power consumption [Hugh96]. During the last years, SI circuits have been used in different applications ranging from filtering [Fiez91] [Zele94] [Hugh96] to A/D conversion [Tan97] [Jons00]. Particularly, several lowpass SI ICs have been reported [Craw92] [Brac94] [Vann94] [Nedv95] [Lind95] [Lind96] [Azer96] [Moen97] [Tan97] [Jorg98]. For all these circuits, performances were worse than those obtained by their SC counterparts. Among other reasons, this was due to the fact that the error mechanisms of SI circuits were not so well understood and analyzed as those of SC circuits. Consequently, SI design equations were not as accurate as SC equations. Also, the lack of specific synthesis and verification tools dedicated to SI circuits rendered their design much less efficient than in the case of SC [Mede99b]. This book aims at contributing to the solution of these problems through the systematic and thorough analysis of the error mechanisms in SI circuits, and their influence on modulators, specially those of the bandpass type. On the one hand, this analysis provides simplified expressions that relate the error mechanisms to the electrical design parameters. These equations are of inestimable aid to support the design process both at the basic block level and at the modulator level. On the other hand, the detailed study of non-idealities needed to obtain these simplified expressions supports the development of precise behavioural models for fast and accurate timedomain simulations. The effectiveness of the studies described in this book has been demonstrated experimentally through two ICs fabricated in a standard CMOS technology. These ICs, which use second- and fourth-order architectures, have been designed to fulfill the specifications of the front-end of a digital AM radio receiver. The fourthorder modulator features 10.5-bit effective resolution in the AM commercial band with a power consumption of 60mW. The second-order modulator achieves 8-bit resolution, with 42mW power consumption. As will be shown in Chapter 1, the results featured by these modulators are competitive with current state-of-the-art SC

References

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modulators realized in technologies with analog options. It hence serves to demonstrate that the SI technique is a viable alternative for the implementation of bandpass A/D converters using CMOS digital technologies provided that a careful design is made. The content of this book is organized as follows. In Chapter 1 the basic principles of oversampling A/D converters are introduced, paying special attention to bandpass modulators. Most of the reported architectures are analyzed, considering that the quantization error is the only source of error. In addition, the current state-of-the-art of this type of converters is reviewed, and a comparative study is done considering the different circuit techniques and technologies used. Chapter 2 describes SI circuits used in modulators from an ideal point of view, giving special attention to the SI resonators – fundamental building blocks of bandpass modulators. The effect of error mechanisms on SI cells is analyzed in depth in Chapter 3. In this chapter, a detailed description of all SI errors is given, and their effects on the operation of SI memory cells are analyzed, placing special emphasis on nonlinear dynamic behaviours. A new model is presented for the associated errors which can be extended to SI integrators and resonators. The degradation of these blocks caused by SI errors and their impact on the performance of bandpass modulators are studied in Chapter 4, obtaining closed-form expressions for the in-band quantization noise power and the harmonic distortion as a function of the electrical parameters of the SI cells. This detailed study supports the development of behavioral models – described in Chapter 5 – which constitute the basis for the implementation of a tool which allows for time-domain simulation of arbitrary SI modulator topologies. This tool has been implemented in the MATLAB/SIMULINK environment [Math91], taking advantage of the friendly and interoperative interface capabilities and powerful signal processing that this well-known program offers. Finally, Chapter 6 describes the design, implementation and experimental results of the designed ICs as well as of their basic blocks.

References [Abid95] [Azer96]

[Baza95]

A.A. Abidi: “Low-Power Radio-Frequency ICs for Portable Communications”, Proc. of the IEEE, Vol.83, pp. 544-569, April 1995. C. Azeredo Leme, J.B. Silva and J.E. Franca: “A Full 12-BIT Switched-Current Modulator with self-calibration”, Proceedings of the 22nd European SolidStated Circuits Conference, ESSCIRC’96, pp. 336-339, September 1996. S. Bazarjani, W. M. Snelgrove: “A 4th Order SC BandPass Modulator designed on a digital CMOS Process”, Proc. 1995 Midwest, August 1995.

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[Baza98]

[Baza99]

[Brac94]

[Craw92]

[Chua98]

[Enge99]

[Fiez91] [Gao98]

[Gust00] [Hair96] [Hugh89]

[Hugh96]

[Inos62]

[Jant92]

[Jant93]

S. Bazarjani, W.M. Snelgrove: “A 160MHz Fourth-Order Double-Sampled SC Bandpass Sigma-Delta Modulator”, IEEE Trans. Circuits and Systems-II, Vol. 45, pp. 547-555, May 1998. S. Bazarjani, S. Younis, J. Goldblatt, D. Butterfield, G. McAllister, S. Ciccarelli: “An 85MHz IF Bandpass Sigma-Delta Modulator for CDMA Receivers”, Proceedings of the 25th European Solid-Stated Circuits Conference, ESSCIRC’99, pp. 266-269, September 1999. M.Bracey and W. Redman-White: “A Switched-Current Converter for Direct Photodiode Interfacing”, Proc. 1994 IEEE Int. Symp. Circuits and Systems, pp. 287-290, May 1994. P.J. Crawley and G.W. Roberts: “Switched-Current Sigma-Delta Modulation for A/D Conversion”, Proc. 1992 IEEE Int. Symp. Circuits and Systems, pp. 13201323, May 1992. S. Chuang, H. Liu, X. Yu, T.L. Sculley, R. H. Bamberger: “Design and Implementation of Bandpass Delta-Sigma Modulators Using Half-Delay Integrators”, IEEE Trans. Circuits and Systems-II, Vol. 45, pp. 535-546, May 1998. J. van Engelen, R. van de Plasshe, E. Stikvoort, A. Venes: “A Sixth-Order Continuous-Time Bandpass Sigma-Delta Modulator For Digital Radio IF”, IEEE Journal of Solid-State Circuits, Vol. 34, pp. 1753-1764, December 1999. T.S. Fiez, G. Liang, and D.J. Allstot: “Switched-Current Circuit Design Issues”, IEEE J. Solid-State Circuits, Vol. 26, pp. 192-202, March 1991. W. Gao, W. Martin Snelgrove: “A 950 MHz IF Second-Order Integrated LC Bandpass Delta-Sigma Modulator”, IEEE Journal of Solid-State Circuits, Vol. 33, pp. 723-732, May 1998. M. Gustavsson, J.J. Wikner, N. Tan: “CMOS Data Converters for Communications”, Kluwer, 2000. A. Hairapetian: “An 81-MHz IF Receiver in CMOS”, IEEE Journal of SolidState Circuits, pp. 1981-1986, December 1996. J.B. Hughes, Nell C. Bird, and Ian C. Macbeth: “Switched-Current - A New Technique For Analog Sampled-Data Signal Processing”, Proc. 1989 IEEE Int. Symp. Circuits and System, pp. 1584-1587, May 1989. J.B. Hughes, K.W. Moulding, J. Richardson, J. Bennet, W. Redman-White, Mark Bracey and R. Singh Soin: “Automated Design of Switched-Current Filters”, IEEE J. Solid-State Circuits, Vol. 31, pp. 898-907, July 1996. H. Inose, Y. Yasuda and J. Murakami: “A Telemetering System by Code Modulation- D-S Modulation”, IRE Transactions on Space Electronics and Telemetry, Vol. 8, pp. 204-209, September, 1962. S.A. Jantzi, W.Martin Snelgrove, and P. F. Ferguson: “A 4th-Order BandPass Sigma-Delta Modulator”, Proc. of 1992 IEEE Custom Integrated Circuit Conference, pp. 16.5.1-4, May 1992. S.A. Jantzi, M. Snelgrove and P.F. Ferguson: “A fourth-order Bandpass sigmadelta Modulator”, IEEE J. Solid-State Circuits, Vol. 28, pp. 282-291, March 1993.

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[Jant97]

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S.A. Jantzi, K. W. Martin, and A. S. Sedra: “Quadrature Bandpass Modulation for Digital Radio”, IEEE J. Solid-State Circuits, Vol. 32, pp. 1935-1949, December 1997. [Jons00] B.E. Jonsson: “Switched-Current Signal Processing and A/D Conversion Circuits - Design and Implementation”, Kluwer Academic Publishers 2000. [Jorg98] I. H.H. Jorgensen and G. Bogason: “Optimization and Design of a Low Power Switched-Current for Voice Band Applications”, Int J. of Analog Integrated Circuits and Signal Processing, Vol. 17, pp. 221-247, November 1998. [Lei98] T. F. Lei, J.Y. Cheng, S. Y. Shiau, T. S. Chao and C. S, Lai: “Characterization of Polysilicon Oxides Thermally Grown and Deposited on the Polished Polysilicon Films”, IEEE Trans. on Electron Devices, Vol. 45, pp- 912-917, April 1998. [Lind95] S. Lindfors and K. Halonen: “A Current Mode Modulator Based on the Error Compensation Technique”, Proc. of the 1995 European Conference on Circuit Theory and Design, pp. 517-520, 1995. [Lind96] S. Lindfors and K. Halonen: “A High Speed Switched-Current Delta-Sigma Modulator”, Proceedings of the 22nd European Solid-Stated Circuits Conference, ESSCIRC’96, pp. 216-219, September 1996. [Loui99] L. Louis, J. Abcarius, and G. W. Roberts: “An Eighth-Order Bandpass Modulator for A/D Conversion in Digital Radio”, IEEE Journal of Solid-State Circuits, pp. 423-431, April 1999. [Math91] The MathWorks Inc.: “MATLAB: User’s Guide”, 1991. [Mede99a] F. Medeiro, B. Pérez-Verdú and A. Rodríguez-Vázquez: “A 13-bit, 2.2-MS/s, 55-mW Multibit Cascade Modulator in CMOS Single-Poly Technology”, IEEE Journal of Solid-State Circuits, pp. 748-760, June 1999. [Mede99b] F. Medeiro, B. Pérez-Verdú and A. Rodríguez-Vázquez: “Top-down Design of High-Performance Sigma-Delta Modulators”, Kluwer Academic Publishers, 1999. [Moen97] N. Moeneclaey and A. Kaiser: “Design Techniques for High-Resolution Current-Mode Sigma-Delta Modulators”, IEEE Journal of Solid-State Circuits, pp. 953-958, July 1997. [Nedv95] J. Nedved, J. Vanneuville, D. Gevaert and J. Sevenhans: “A Transistor-Only Switched Current Sigma-Delta A/D Converter for a CMOS Speech CODEC”, IEEE Journal of Solid-State Circuits, Vol. 30, pp. 819-822, July 1995. [Norm96] O.Norman: “A BandPass Delta-Sigma Modulator For Ultrasound Imaging at 160MHz Clock Rate”, IEEE Journal of Solid-State Circuits, pp. 2036-2041, Dec. 1996. [Nors97] S.R. Norsworthy, R. Schreier, G.C. Temes: “Delta-Sigma Converters. Theory, Design and Simulation”, New York, IEEE Press, 1997. Modulator for Digital [Ong97] A.K. Ong and B.A. Wooley: “A Two-Path Bandpass IF Extraction at 20MHz”, IEEE Journal of Solid-State Circuit, Vol. 32, pp. 1920-1933, December 1997. [Plass94] R. van de Plassche: “Integrated Analog-to-Digital and Digital-to-Analog Con-

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verters”, Kluwer Academic Publishers, 1994. B. Razavi: “Principles of Data Conversion System Design”, IEEE Press, 1995. W. Sansen: “Challenges in Analog IC Design in Submicron CMOS Technologies”, Proc. IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design,

R. Schreier and M. Snelgrove: “Bandpass Sigma-Delta Modulation”, Electronics Letters, Vol. 25,pp. 1560-1561, November 1989. [Shoa97] O. Shoaei and W. M. Snelgrove: “Design and Implementation of a Tunable 40MHz-70MHz Gm-C Bandpass Modulator”, IEEE Trans. on Circuits and Systems-II, Vol. 44, pp. 521-530, July 1997. [Sing95] F.W. Singor and W. M. Snelgrove: “Switched-Capacitor Bandpass Delta-Sigma A/D Modulation at 10.7 MHz”, IEEE J. Solid-State Circuits, pp. 184-192, March 1995. [Song95] B.S. Song: “A Fourth-Order Bandpass Delta-Sigma Modulator with Reduced Number of Op Amps”, IEEE Journal of Solid-Stated Circuits, Vol. 25, pp. 1309-1315, December 1995. [Taba99] A. Tabatabaei, B. Wooley: “A Wideband Bandpass Sigma-Delta Modulator for Wireless Applications”, IEEE Int. Symp. on VLSI Circuits, pp. 91-92, 1999. N.Tan: “Switched-Current Design and Implementation of Oversampling A/D [Tan97] Converters”, Kluwer Academic Publishers 1997. [Toni99] D. Tonietto, P. Cusinato, F. Stefani, A. Baschirotto: “A 3.3V CMOS 10.7MHz 6th-order bandpass Modulator with 78dB Dynamic Range”, Proceedings of the 25th European Solid-Stated Circuits Conference, ESSCIRC’99, pp. 78-81, September 1999. [Toum93] C.Toumazou, J.B.Hughes, and N.C. Battersby,(Editors): “Switched-Currents: An Analogue Technique for digital technology”, London: Peter Peregrinus Ltd., 1993. [Vann94] J. Vanneuville, J. Nedved, D. Gevaert, J. Sevenhans and I. Adamcik: “A Transistor Only Sigma-Delta A/D Converter For a CMOS Speech Codec”, Proc. of ESSCIRC’94, Sept. 1994. [Zele94] R.H. Zele and D. J. Allstot: “Low-Voltage Fully Differential Switched-Current Filters”, IEEE J. Solid-State Circuits, Vol. 29, pp. 203-209, March 1994. [Yosh99] H. Yoshizawa, Y. Huang, P.F. Ferguson, and G.C. Temes: “MOSFET-Only Switched-Capacitor Circuits in Digital CMOS Technology”, IEEE J. SolidState Circuits, Vol. 34, pp. 734-747, June 1999. [Schr89]

Bandpass Sigma-Delta A/D Converters: Fundamentals and State-of-the-Art

1

Chapter 1 Bandpass Sigma-Delta A/D Converters Fundamentals and State-of-the-Art 1.1 Introduction The current explosion of interest in the realization of mixed-signal systems on chip using VLSI technologies has motivated the use of oversampling Sigma-Delta Analog-to-Digital Converters (ADCs) to implement the front-end of such systems. This type of ADCs, composed of a low-resolution quantizer embedded in a feedback loop, uses oversampling (a sampling frequency much larger than the Nyquist frequency) to reduce the quantization noise and modulation [Inos62] to push this noise out of the signal band. The combined use of redundant temporal data (oversampling) and filtering modulation) results in high-resolution, robust ADCs, which have lower sensitivity to circuitry imperfections and are more suitable than traditional Nyquist-rate ADCs for the implementation of Analog-to-Digital (A/D) interfaces in a standard CMOS technology. The efficiency of ADCs has been demonstrated in a large number of ADC Integrated Circuits (ICs) for digitizing lowpass signals with diverse bandwidths and applications [Nors97][Mede99]. Recently, the principle of modulation has been extended to bandpass signals, leading to a new type of ADCs, named BandPass ADC [Schr89], which are especially suited to convert bandpass signals with a narrow bandwidth. This has an obvious application at the front-end of modern wireless communication systems such as mobile phones, digital radio receivers, etc. have much in common with their lowpass counterparts – whose basic properties and limitations have been described elsewhere [Nors97][Mede99]. However, there are some issues which are peculiar to This chapter is devoted to the description of these issues. In Section 1.2, digital radio receivers are described, pointing out the need for an ADC at the IF location. Section 1.3 and Section 1.4 give an overview of ADCs. Section 1.5, Section 1.6 and Section 1.7

2


explain the basic concepts and architectural issues of 1.8 summarizes the performance of state-of-the-art

, Finally, Section

1.2 Analog-to-digital interfaces for digital radio receivers A Radio Frequency (RF) receiver is a system that extracts a desired low-power signal (typically ) in the presence of other noisy and higher power ((30 – 60)dB ) interfering signals of the RF electromagnetic spectrum. The performance of an RF receiver is characterized by two figures [Vizm95][Raza98]: sensitivity and selectivity. The former measures the ability to detect signals in the absence of any interference other than noise, while the latter characterizes the capacity of the receiver to discriminate between the desired signal and large adjacent-channel interferers. Fig. 1.1 shows the block diagram of an analog superheterodyne RF receiver composed of three fundamental parts [Hayk94]: (a) The RF section, where after filtering and amplifying, the incoming RF signal is translated to a fixed Intermediate Frequency (IF) through the combination of a mixer and a Local Oscillator (LO) (of adjustable frequency). As the sensitivity of the superheterodyne RF receiver is primarily dominated by the noise of this stage, a Low-Noise Amplifier (LNA) is normally used (see Fig. 1.1) to reduce the noise contributions of subsequent stages in the receiver. (b) The IF section, where the IF signal is filtered, amplified and downconverted to baseband. The selectivity of the receiver is mainly determined by the channel select filtering performed at this stage. This is because in practice it is easier to achieve high-Q bandpass filters centred at IF (typically in the MHz range) than at RF (in the GHz range). (c) The demodulation section, which retrieves the information from the modulated carrier (demodulation process).


3

In recent years, the market of digital RF communication portable devices (mobile phones, digital AM/FM radio receivers, wireless LANs,...) is rapidly expanding with the development of new services and applications (paging, facsimile, short messaging functions, etc.). On the one hand, the variety of new applications and devices has led to the proliferation of a large number of communication standards with different modulation schemes, carrier frequencies, channel bandwidths, dynamic range requirements, etc. On the other hand, consumers demand low-cost, low-power, and small form devices that satisfy those communication requirements. This market demand together with the continuous scaling of CMOS technologies make it possible to integrate an RF receiver onto a single chip with two main objectives. On the one hand, increasing integration will reduce the receiver cost and the power dissipation. On the other hand, aggressive utilization of VLSI technology enables the combined integration of an ADC along with the front-end stages of the receiver. In this manner, the back-end signal processing (channel-selection and demodulation) can be shifted from the analog into the digital domain. This offers two main advantages. First, to take full advantage of the smaller geometries by reducing the die size, it is desirable to perform most RF receiver functions using digital circuits, which, unlike the analog circuits, scale with technology. Second, Digital Signal Processing (DSP) simplify the implementation of programmable filters, thus allowing the adaptability of the RF receiver to multiple communication standards in different countries [Abid95a]. Fig. 1.2 shows the ideal block diagram of a digital RF receiver [Feld98]. In this approach, the RF signal is directly digitized by the ADC. Hence, the channel selection and demodulation process is performed in the digital domain. Unfortunately, the receiver of Fig. 1.2 is unrealizable because it would require realizing the A/D conversion of a signal at 900MHz-2.5GHz (depending on the carrier frequency) with an accuracy of 14-18bit. Hence, a more realistic digital radio receiver would contain an Analog Signal Processing (ASP) section including signal conditioning, i.e: frequency translation, amplification and filtering.

4


The implementation of these analog functions can be realized in different manners resulting in several RF receiver architectures. Fig. 1.3 shows the most significant ones [Raza98]. Fig. 1.3 (a) is a digital superheterodyne receiver, where the signal is first down-translated to IF and then to baseband where it is digitized and demodulated. This is the more conventional architecture. However, it is not appropriate for fully-integrated RF receivers because high-frequency high-Q bandpass filters (in both the RF and the IF sections) are required. Fig. 1.3(b) shows the block diagram of a direct conversion receiver. In this architecture, the RF signal is mixed-down directly to baseband where is digitized. This approach is more suited to integration than the superheterodyne because it eliminates the IF section. Hence, only off-chip RF filters are required. However, non-idealities of the mixer (offset and flicker noise) can severely degrade the performance of this type of receiver.


Many of the problems arising in the mentioned architectures can be eliminated using the IF conversion receiver, shown in Fig. 1.3(c). In this architecture the incoming signal at the antenna is first mixed-down to IF where it is digitized. Hence an ADC capable of digitizing IF bandpass signals, often called bandpass ADC, is required. In all the architectures shown in Fig. 1.3, the ADC is one of the most critical blocks for several reasons. On the one hand, the sensitivity of the digital receiver depends on the accuracy with which the signal is digitized. On the other hand, in some architectures such as the one shown in Fig. 1.3(c), part of the signal channel selection is performed by the ADC itself. The rest of the chapter is devoted to describing the fundamental principles and architectures of ADCs, with special emphasis on those based on modulators [Schr89]. This type of converters has been demonstrated to be the optimum solution for digitizing IF signals in a large number of ICs as will be seen in Section 1.8.

1.3 Analog-to-Digital Conversion: Fundamentals As alluded to in the previous section, the ADC is a critical block in digital RF radio receivers. This section explains its basic operation as well as its inherent errors. An ADC is a system that transforms signals which are continuous in time and amplitude (analog signals) into discrete-time signals which are quantized in amplitude (digital signals). Fig. 1.4(a) shows the basic scheme of an ADC that includes the following components: an anti-aliasing filter, a Sampling-and-Hold (S/H) circuit, a quantizer and a coder. The operation of these blocks is illustrated in Fig. 1.4(b). First, the analog input signal, passes through the anti-aliasing filter, removing the spectral components above one half of the sampling frequency, of the subsequent S/H. Otherwise, from the Nyquist sampling theorem [Oppe89], high frequency components of would be folded or aliased into the signal bandwidth, thus corrupting the signal information. The resulting band-limited signal, is sampled at a rate of by the S/H circuit, thus yielding the discrete-time signal, Following the S/H, the quantizer maps the continuous range of amplitudes of into a discrete set of levels. Finally, the coder assigns an unique binary number to each level providing the output digital data,

5

6


As illustrated in Fig. 1.4(b) the fundamental processes involved in an ADC are: sampling and quantization. Both of them make a continuous-to-discrete conversion of the analog signal, the former in time and the latter in amplitude. These two transformations present inherent errors that limit the performance of an ADC, even assuming ideal components. 1.3.1 Sampling ADCs can be classified depending on the value of the ratio between the sampling frequency, and the Nyquist-rate, – represented by the parameter According to the Nyquist theorem, M must be larger than unity in order to avoid the loss of signal information during the sampling process. Based on this criterion, those ADCs with M = 1 are called Nyquist–rate converters. Otherwise, if the ADC is known as an Oversampling converter and M stands for the oversampling ratio. There are many architectures for Nyquist-rate ADCs, each of which embodies

Bandpass Sigma–Delta A/D Converters: Fundamentals and State-of-the-Art

7

various trade-offs among resolution†1 , speed †2, power consumption and active area requirements. Regarding the resolution vs. speed trade-off, Nyquist-rate ADCs can be divided into three main categories [John97]: low-to-medium speed, from dc to ~l00Hz, and high resolution, 20–22bit (dc–100Hz@20–22bit); medium speed and medium resolution (100Hz–10MHz@12–20bit); and high speed and low-tomedium resolution (10MHz–1GHz@6–12bit). A thorough review of many architectures – beyond the scope of this work – can be found in [John97] [Plass94] [Raza95]. As an illustration, Fig. 1.5 represents the specifications required for main applications in the resolution–speed plane. For the sake of clarity, the figure is divided into the three mentioned regions, showing the maximum resolution achievable at each conversion speed. This limit – due to the thermal noise – can be approximated by a negative slope straight line in the resolution–speed plane [Nish93], and goes higher resolution at a rate of 2dB/year (that is, 0.33bit/year) [Swan95]. The application range of each ADC architecture (both Nyquist and Oversampling) is pointed out in Fig. 1.5. Observe that the so-called oversampling ADCs cover a wide region, becoming very popular during the last decade

†1. The resolution of an ADC is given by the full-scale dynamic range in effective number of bit. †2. The speed of an ADC refers to the maximum signal frequency that can be processed with no degradation of the resolution.

8


[Cand92][Nors97][Mede99]. These types of ADCs can solve some of the problems encountered in Nyquist-rate converters, mainly the need for high-selectivity analog filters, and large sensitivity to circuitry imperfections and noisy environments. In fact, oversampling converters relax the requirements placed on the analog circuitry at the expense of more complex digital circuitry [Cand92]. This is advantageous when the ADC is implemented in modern standard submicron VLSI technologies, where complicated high speed digital circuitry is more easily realized in less area, but the realization of high accuracy analog circuitry is complicated. Another advantage of oversampling converters is that they simplify the requirements placed on the anti-aliasing filter. This is illustrated in Fig. 1.6. Note that the anti-aliasing filter for a Nyquist converter must have a sharp transition band, thus introducing phase distortion in signal components located near the cut-off frequency.

1.3.2 Quantization A quantizer is a system that maps a continuous range of amplitudes into a finite set of discrete amplitudes or levels. Contrary to the sampling process, the quantization of a discrete-time signal is a non-reversible operation. Fig. 1.7(a) shows the transfer characteristic of an ideal quantizer. This can be represented mathematically by a non-linear function as follows [Cand92],


where

denotes the slope of the line intersecting the code steps or quantizer gain; stands for the quantization error. This error is a non-linear function of the input signal, as shown in Fig. 1.7(b). Note that, if is confined to the interval , the quantization error is bounded by the interval with being the quantization step, defined as the separation between consecutive levels in the quantizer. For an N-bit quantizer, with being the full-scale range of the quantizer (see Fig. 1.7(a)). For inputs outside of that interval, the absolute value of the quantization error grows monotonously. This situation is known as overloading of the quantizer.

If varies randomly from sample to sample in the interval and the number of levels of the quantizer is large, it can be shown [Benn48] that the quantization error distributes uniformly in the range with the rectangular probability density, shown in Fig. 1.7(c), having a constant Power Spectral Density (PSD). Because of that, the quantization error is modelled as an additive white noise source, as shown in Fig. 1.7(d), usually called quantization noise. As the total quantization noise power, is uniformly distributed in the range its PSD equals

9

10


and the in-band noise power, calculated as,

decreases with M at a rate of 3dB/octave. This property is exploited by oversampling converters by using large values of M. Strictly speaking, the white noise approximation is not valid for single-bit quantizers or comparators (very interesting in practice due to their simplicity). However, experience shows that the results obtained with this model are also applicable to the mentioned quantizers [Cand92]. This will be discussed below.

1.4 Oversampling

Analog-to-Digital Converters

By embedding the quantizer in a feedback loop, it is possible to reduce the inband quantization noise power of an ADC significantly beyond what can be achieved by simply using oversampling. This is the basic principle of converters, introduced by Inose et al. in 1962 [Inos62]. Oversampling ADCs operate with redundant temporal data, obtained using oversampling with low-resolution quantizers (one-bit quantizers in many cases), and apply signal processing techniques (averaging in the simplest case) to combine these temporal data, thus increasing the effective resolution. Fig. 1.8 shows the block diagram of an oversampling ADC which includes three basic components: an anti-aliasing filtering, a modulator and a dig-


11

ital decimator. The signal is oversampled and quantized in the modulator. This block also filters the quantization error, by shaping its PSD in such a way that most of its power lies outside of the signal band, where the error is eliminated by digital filtering. This fact has resulted in the qualifier noise-shaping, which is also used to name the The modulator output – coded into a reduced number of bits – is passed through the decimator, where, after filtering all the components out of the signal band, data are decimated to reduce down to The result is the signal coded in a large number of bit and clocked at Among the converter blocks, the modulator is the hardest to design since oversampling simplifies the anti-aliasing filter requirements and the decimator is a pure digital block whose design can be highly structured and automated [Nors97].

1.4.1 Basic architecture of a

modulator

Fig. 1.9(a) shows the basic scheme of a modulator. Its output, is substrated from its input, which has been sampled at a rate much larger than the Nyquist rate. The result is filtered by and passed through a quantizer, which usually has a reduced number of levels. If the gain of is high in the interval of the frequency of interest, and low outside of it, the quantization error is attenuated in said band due to the feedback loop.

†3. Early used discrete-time filters in their implementations. This is why we adopt them for our discussion. Nowadays, continuous-time filters are also implemented as we will see in Section 1.6.6.

12


Assuming that the quantization error can be modelled as an additive, white noise source, the quantizer can be replaced by the linear model shown in Fig. 1.7(d). In such a case, the modulator in Fig. 1.9(a) can be viewed as a two-input, and oneoutput, , system, which in the Z-domain can be represented by

where and are the Z-transform of the input signal and quantization noise, respectively; and are the respective transfer functions of the input signal and quantization noise. The exact form of both functions will depend on the architecture of the modulator. Analysing the block diagram of Fig. 1.9(a), yields

In view of (1.4), we can impose the following conditions to get operative modulators:

with

being a constant. If around dc, the modulator is called a lowpass modulator Otherwise, if in a narrow passband centered at a given frequency (usually called notch frequency and represented by ), the modulator is called a bandpass modulator [Gail89] [Schr89]. Fig. 1.9(b) illustrates the filtering functions performed for both types of modulators. From (1.2) and (1.4), the PSD of the shaped quantization noise is

and the shaped quantization noise in-band power is calculated as follows:


13

1.4.2 Figures of merit At this point, it is convenient to define the figures of merit commonly used to characterize the oversampling converters. 1.4.2.1 Signal-to-Noise Ratio (SNR, S / N ) This is the ratio between the output power at the frequency of a sinusoidal input and the in-band noise power. It is usually given in decibels:

where A is the input amplitude of the sinusoide. Note that the SNR monotonously increases with A. However, beyond a certain input amplitude, the quantizer input lies outside of the interval which produces the overloading of the latter and consequently a sharp drop is observed in the SNR curve. The value of the SNR at said input amplitude – the maximum value of SNR – is often called the SNR-peak. As will be shown in Chapter 4, besides quantization noise, there are other contributions to the in-band noise power due to non-idealities of the circuitry. To take into account all these errors, the Signal-to-(Noise plus Distortion) Ratio (SNDR or TSNR) is normally used. 1.4.2.2 Dynamic Range (DR) and effective resolution (B) The dynamic range is defined as the ratio between the output power of the frequency of a sinusoidal input with amplitude and the output power when the input is a sinusoide of the same frequency, but of a small amplitude, so it cannot be

14


distinguished from noise, that is, with SNR = 0dB. Ideally, the full-scale range of the modulator input is approximately given by that of the quantizer, and hence,

On the other hand, the dynamic range of an ideal B-bit Nyquist ADC can be calculated from (1.3) and (1.10), yielding

Manipulating this expression yields the effective number of bits or effective resolution of an ADC as a function of its DR, expressed in dB, DR(dB),

In general, the above expression is used to express the effective resolution of a in terms of DR(dB) if the performance of the modulator is limited by either quantization noise or by circuitry errors. 1.4.3 First-order (lowpass) For an

modulator

from (1.5) and (1.6),

must satisfy the following condition

The simplest block that implements such a transfer function is an integrator, in which,

Substituting the filter

in Fig. 1.9(a) with a discrete-time integrator, and


15

replacing the N-bit quantizer with a comparator (1-bit quantizer) results in the modulator of Fig. 1.10. One may view the “delta” and “sigma” as referring to the analog operations in the system loop: subtraction of the fed back output signal and integration of the differences. Assuming a linear model for the comparator, and that Fig. 1.10 yields the following modulator output:

Note that called a first-order is given by:

is of first order; so the modulator of Fig. 1.10 is From (1.8) and (1.11), the DR of a first-order

The main disadvantage of first-order is that a high oversampling ratio is needed to achieve high resolution. Note that each doubling of M in (1.16) DR increases in 9dB, only 6dB more than for a simple quantizer. As an example, using a first-order should be necessary to obtain a 16-bit effective resolution over a 10kHz signal bandwidth, meaning M = 1500. Another limitation of first-order is the high correlation between the input signal and the quantization error. Because of this correlation, the output spectrum of the modulator can contain discrete tones (often named idle tones) that are not predicted by the white noise model [Cand92]. However, the expressions derived for and DR are approximately valid when the input signal varies over time [Benn48]. Nevertheless, as shown in literature [Cand81], for static inputs, the output of a first-order tries to equal on average the input signal level with repetitive patterns. Thus, for dc inputs in the range the in-band quantization error power sharply changes with the input, as shown in Fig. 1.11 [Cand92]. A possible solution to this problem is to include, usually at the quantizer input, some non-

16


periodic signals, as pseudo-random noise. With this technique (called dithering [Nors97]) it is possible to partially decorrelate the quantization error and the input, at the expense of larger complexity of the design. This is still a matter of discussion. In fact, other authors [Hein93][Schr94] propose the use of chaos†4 to eliminate the idle tones caused by the correlation between the input signal and the quantization error. 1.4.4 Lowpass


In order to enhance the performance of the first-order a large number of architectures have been reported up to now following two different, non-exclusive strategies: a) Increasing the order, L, of which leads to an increase of the order of resulting in a more effective cancellation of the quantization noise in the signal band. b) Augmenting the number of bits, N, of the quantizer; thus, PSD of the quantization noise is reduced.

and hence the

Describing all possible architectures goes beyond the scope of this work and a detailed study of them can be found in many papers and books [Nors97][Mede99]. For completeness, a short summary of the most significant architectures is given in the following sections. †4. Chaotic modulators are those which are made of unstable in-loop filters [Schr94].


1.4.4.1 Second-order lowpass

17

Modulator

If the quantizer in a first-order is itself replaced by a first-order the resulting architecture is the so-called single-loop second-order shown in Fig. 1.12 [Cand92]. Making to guarantee the stability of the loop†5 and the Z-domain transform of the modulator output is:

where it has been assumed that the quantization error is an additive, white noise source. For this modulator, From (1.8) the in-band shaped quantization noise power yields:

where has been assumed. Thus, doubling M results in a 15dB decrease in the in-band noise power, instead of the 9dB obtained with a first-order As a numerical example, a sampling frequency of 3MHz is necessary to achieve 16-bit effective resolution over a 10kHz signal band. In addition to increasing the order of the noise shaping, the use of two integrators also contributes to decorrelate the input signal and the quantization error. In fact, the presence of idle tones in the signal band decreases as the modulator order increases [Cand92].

†5. According to [Cand85], the stability of 2nd – order long as the input signal remains in the range

is guaranteed if

as

18


1.4.4.2 High-order lowpass

modulators

The second-order suppresses the quantization noise more effectively in the signal band than the first-order In general, as the order of the loop filter increases, the in-band quantization noise power decreases and the out-of-band noise power increases more than commensurately. The simplest way of implementing an L-order consists of including L integrators before the quantizer [Ritc77]. -order single loop The resulting architecture, shown in Fig. 1.13, is called The Z-domain modulator output is given by:

For the modulator of Fig. 1.13, quantization noise power is given by:

in which the in-band

In case of N – bit quantizers,

In general, doubling M results in a reduction of 3(2L + 1)dB in and (1.10) the SNR and the DR are respectively:

. From (1.9)


19

A drawback of with is their tendency to instability. A modulator is considered stable if, for bounded inputs and whatever integrator initial conditions, the internal state variables (integrator outputs) remain also bounded over time [Op’T93]. Some attempts have been reported to mathematically determine the stability conditions of [Good95], resulting in extremely complex expressions. In fact, when L > 2, it is not always possible to precisely determine a stability condition. With the help of behavioural simulations, in [Op’T93] it has been shown that stable operation is only obtained for inputs confined to a given interval, with proper selection of the scaling coefficients, which depends on the modulator architecture and on the integrator initial conditions. In addition to the architecture of Fig. 1.13, there are other possibilities for obtaining high-order noise-shaping filtering [Ribn91][Adam97]. The easiest way is to synthesize an differentiator. Nevertheless, the value of such a function at a frequency near to half the sampling frequency quickly increases with L, providing modulators with a clear tendency to be instable. To solve this problem, Lee and Sodini [Lee87a] proposed an architecture that makes it possible to generate with multiples poles and zeroes along the signal band and a much smaller gain out of that band. The Lee-Sodini architecture, also called interpolative, is shown in Fig. 1.14. Assuming a linear model for the quantizer,

If all coefficients are zero, has all zeros located at DC. A drawback of interpolative modulators is the increased complexity of the analog circuitry. Regarding stability, Lee claimed that if is less than 2, then the modulator is stable. This assertion is known as Lee’s rule. Unfortunately is not completely reliable and designers must rely on time-consuming simulations to confirm the sta-

20


bility of their designs [Lee87b]. An alternative to interpolative modulators are the cascade architectures (also named multi-stage or MASH) [Chou89][Long88][Mats87][Rebe90] whose generic block diagram is shown in Fig. 1.15. Their functioning is based on the cascade connection of low-order modulators, whose stability is guaranteed by design. The quantization noise generated in one stage is then re-modulated by the next one, and later cancelled in the digital domain. As a result, one obtains the modulator input plus the quantization noise of the last stage, attenuated by a shaping function of order equal to the number of integrators in the cascade. As an illustration, Fig. 1.16 shows a fourth-order architecture consisting of a cascade of two second-order (cascade 2-2). If scaling coefficients meet the relations of Table 1.1, the Z-domain output is:


21

where represents the Z-transform of the second-stage quantization noise. The scaling coefficients can be optimized in order to minimize the quantization noise power and signal levels [Mede98], giving:

One of the main drawbacks of cascade modulators is that they exhibit greater sensitivity to certain non-ideal aspects of the circuitry. Multi-bit quantization can be used to compensate the corresponding loss of resolution, as detailed in the next section.

22


1.4.4.3 Multi-bit lowpass

modulators

A multi-bit quantizer can be embedded in the feedback loop in order to improve the dynamic range of the modulator for a given oversampling ratio, or to reduce the oversampling ratio for a given DR [Paul87][Carl97]. As stated in (1.23), a minimum of 6dB reduction in quantization noise is obtained per extra bit of the internal quantizer. Besides, the use of multi-bit quantization improves the stability of high-order loops because it is easier to anticipate the saturation of the quantizer. Another advantage of multi-bit quantizers is that their actual behaviour approximates better to a linear model than 1-bit quantizers. The most significant drawback of multi-bit is that their linearity is limited by that of the Digital-to-Analog Converter (DAC) needed in the feedback path [Adam91][Plass79]. Non-linear DACs introduce harmonic distortion directly at the input to the modulator, thus degrading its operation [Nors97]. To overcome this problem, different techniques exist that reduce the sensitivity of the to the errors associated to the multi-bit quantization. These techniques can be classified as follows: Element trimming techniques, which use laser trimming and calibration to improve the matching of the unity devices used in the DAC. This technique is expensive because of the additional steps required during the fabrication process. Digital correction techniques, based on the cancellation in the digital domain of the errors induced during the in-loop DAC conversion [Cata89] [Sarh93] [Yang92]. Dynamic element matching techniques. The mismatching in the DAC converter elements (responsible for non-linearity) is corrected through a dynamic selection of these elements. The selection algorithms permit, in the simplest case, conversion of the harmonic distortion provoked by the nonlinearity into white noise. In more elaborated applications, the spectral power density of this error can be shaped so that most of its power lies outside the signal band [Chen95][Bair96][Nys96]. Techniques based on dual-quantization architectures. These techniques employ single-bit and multi-bit quantization at different points of the modu-


23

lator topology. Their operation is based on the cancellation, in the digital domain, of the quantization noise associated with the coarsest quantization. In single-loop architectures, the single-bit quantizer output is fed back only to the first integrators of the loop, while the feedback to the integrators further in the loop employ a multi-bit DAC. This last technique has been employed in combination with cascade architectures to obtain high-resolution @high-speed The basic idea is to use a multi-bit quantizer only at the last stage of the cascade, keeping the others single-bit. Thus, the DAC non-linearity error of the last stage is attenuated by a shaping function, provided by the cancellation logic, and filtered out by the digital decimator. Several cascade multi-bit have been reported intended for telecom applications, particularly for cable modem digital subscriber loop (xDSL) [Bran91] [Mede99b]. They are capable of digitizing wideband (above 1MHz) signals with more than 12-bit effective resolution. However, the continuous grown of the digital wireless communication market is demanding high-resolution ADCs capable of digitizing narrow band IF signals. In such an application, the use of becomes more appropriate, as described in the next section.

1.5 Bandpass

modulators

Digitization of a signal in digital superheterodyne RF receivers can be basically accomplished using the methods represented in Fig. 1.17. The first one, shown in Fig. 1.17(a) uses an analog quadrature mixer [Pede94] to multiply the IF signal by two carriers that are 90° out of phase. As a result, the signal is separated into its lowpass In-phase (I) and Quadrature (Q) components which are digitized by means of two lowpass ADCs. The other method, shown in Fig. 1.17(b), changes the order of the ADC and the mixer and uses only one bandpass ADC. Thus, the signal is first translated to the digital domain and then mixed to the baseband. This is advantageous for several reasons. On the one hand, the I and Q components of the signal are separated in the digital domain rather than in the analog domain as occurs in Fig. 1.17(a). Hence, the problems associated with the analog mixer – mismatch between I and Q signal paths, low-frequency noise and dc offset – are avoided [Nors97]. Another advantage of the scheme shown in Fig. 1.17(b) is that it allows channel-

24


select filtering, gain control and demodulation to be handled in the digital domain [Jant93][Sing95]. This results in robust RF receivers with a high degree of programmability, thus allowing a single software-controlled RF receiver to be employed for multi-standard receivers [Tao99c], being suitable for use in widely varying propagation environments [Ong98]. Digitization of an IF signal can be accomplished either with a wideband Nyquistrate ADC or a ADC. The use of the latter is the optimum solution for digitizing these signals for several reasons. On the one hand, it is problematic to design high-precision Nyquist-rate converters in modern standard CMOS technologies, optimized for digital circuits, but deficiently modelled for analog interfaces which require precise components. On the other hand, as the bandwidth of IF signals is typically much smaller than the carrier frequency, reducing the quantization noise in the entire Nyquist band becomes superfluous. Instead of that, by using ADCs the quantization noise power is reduced only in a narrowband around the IF location (see Fig. 1.9(b)), thus taking advantage of the higher oversampling ratio †6 and hence yielding a high DR.


25

As mentioned in Section 1.4.1, extend the noise-shaping concept from the conventional – in which the quantization noise is suppressed around dc – to a more general case where the quantization noise is reduced in a narrow passband centred at an IF location [Gail89][Schr89]. Thus, the design and analysis of share much in common with . In fact, many advantages inherent to the architectures of the latter are preserved in the former [Nors97]. This section is devoted to describing the fundamentals of focusing on the aspects of modulator design which are specific to this class of modulators: basic architecture, band location, noise shaping and synthesis of

1.5.1 Quantization noise shaping of bandpass

modulators

As stated in the previous section, a is a particular class of that places the zeroes of in a narrow band around an IF location, usually named notch frequency, Fig. 1.18 shows the conceptual block diagram of a It is composed of a BandPass Filter (BPF), an N-bit quantizer and a DAC connected in a loop. The BPF can be synthesized by cascading two or more second-order biquadratic filters or resonators, which must have a sharp transfer function and well-defined resonance at These resonators may be implemented as a Discrete-Time (DT) filter using either Switched-Capacitor (SC) [Sing95] or switched-current (SI) [Patt94] techniques or they may be implemented as a Continuous-Time (CT) filter using, [Shoa97] or LC filters [Gao98]. Let us consider that the BPF is a 2Lth -order filter composed of a cascade of L resonators with a DT†7 transfer function given by:

†6.In the case of bandpass signals, the oversampling ratio is defined as [Vaug91] , where is the signal bandwidth, is the centre frequency and represents the largest integer not exceeding

26


where and are the conjugate-complex poles of . Assuming that the quantization error can be modelled as an additive, white noise source, the Z-transform of the modulator output in Fig. 1.18 is:

where

and

derived from (1.5), yield:

Note that has L zeroes at and In most practical cases, and are placed in the unit circle, i.e, , with being the sampling period. In some ICs the value of can be either digitally [Corm97] or continuously [Shoa97] programmable, thus allowing to be changed without changing This is especially useful in radio applications, where the use of a tunable eliminates the necessity of a channel-selection function in the RF section. Assuming that satisfied and that

is synthesized in such a way that the condition in (1.6) is

yields: †7. A similar discussion can be held for This class of modulators are internally DT systems since there is a sampler before the quantizer. In fact, equivalent DT and CT forward-path loop filters are related by the impulse-invariant transformation [Shoa94], as will be discussed in Section 1.6.6.


27

From (1.2) and (1.4), the PSD of the shaped quantization noise is:

and the shaped quantization noise in-band power is calculated as follows:

where

has been assumed. An important conclusion is that, although the of Fig. 1.18 is a 2Lth-order modulator, the quantization noise is suppressed with an Lth-order bandstop transfer function. In other words, the quantization noise shaping of a 2Lth-order is equal to that of an Lth-order As an illustration, Fig. 1.19(a) plots the simulated output spectrum of the modulator in Fig. 1.18for L = 2, N= l, and The input was a sinusoidal signal of a frequency close to and an amplitude equal to with being the output level of the DAC. As Fig. 1.19(a) shows, the output spectrum of the modulator can be seen as the sum of two components: the input signal spectrum (a vertical line) and the quantization noise spectrum. The form of the shaped quantization noise is like a valley with its minimum value at

28


The SNR and the DR for the modulator of Fig. 1.18, derived from (1.9) and (1.10), are respectively:

Note that for a -order the quantization noise increases at a rate of “only” 15dB/octave, which is equivalent to a -order filtering. This is shown in Fig. 1.19(b) by plotting SNR vs. M, computed from the spectrum in Fig. 1.19(a).

1.5.2 Signal passband location In theory, the passband of a can be placed at any frequency from dc to Thus, for a given input signal centre frequency, (the IF location in a RF receiver) and bandwidth, the choice of the ratio is a trade-off among sampling frequency (directly related to the speed of the whole system), anti-aliasing filter requirements, and oversampling ratio [Nors97]. As illustrated in Fig. 1.20(a), the transition band, of the antialiasing filter becomes sharper as approaches Thus, the maximum value of to avoid aliasing is [Ong98]:

From the above condition it follows that the lower the higher However, the use of low complicates the problem of suppressing image-band signals when the RF signal is mixed down to an IF location. This is illustrated in Fig. 1.20(b), where the incoming RF signal is centered at An image-rejection filtering must be performed preceding the mixer to avoid image-band signals centered at to corrupt the desired signal [Lee98]. In order to cope with both image-rejection and antialiasing filter requirements, must be located at an intermediate location in the Nyquist band. An optimum solution to this problem is to place at one-quarter of the sampling frequency. This


29

notch frequency location, in addition to relaxing the mentioned filter specifications, offers several advantages. First, the forward path loop (analog) filter realization can be relatively simplified. Secondly, it simplifies the synthesis of bandpass architectures, which can be easily derived from low-pass prototypes with a simple variable transformation (for instance which will be described in the next section. Last but not least, the design of the digital mixing to baseband (see Fig. 1.17(b)) is obviously simplified because the digital cosine and sine signals are equal to the data series (1, 0, –1,0, ...) and (0, 1, 0, –1, ...), respectively. In addition to the mentioned advantages, making also offers the possibility of centering the IF signal at as demonstrated in [Loui99] – the spectrum is symmetrical with respect to This is a consequence of frequency aliasing resulting from the inherent sampling process at the input of the modulator. This approach offers several advantages. On the one hand, while the anti-aliasing filter requirements are the same with the signal placed at the image-rejection filter specifications are relaxed. On the other hand, making allows for either the clock rate to be reduced to one-third (easing decimation and power requirements) or processing signals to be three times higher in frequency. The only drawback is that the oversampling ratio is also reduced by a factor of three. For example, in the case of a fourthorder modulador, this means a loss of 3.7bit in the effective resolution.

30


1.6 Synthesis of bandpass


The basic structure of a is analogous to that of an except for the forward path loop filter, which is of the bandpass type for the former and of the lowpass type for the latter. Thus, the operation of both types of modulators is based on the same strategy to attenuate the quantization noise. Hence, although most of the design art developed for can be used to develop there are some aspects of the modulator design which are peculiar to This fact has motivated the development of several methods for synthesizing architectures. This section summarizes the most important methods reported in literature.

1.6.1 The lowpass-to-bandpass transformation method: As shown in Section 1.5.1, an -order and a -order present identical figures of merit: SNR and DR. Consequently, a simple way to synthesize any architecture is to apply a Lowpass-to-Bandpass (LP-to-BP) transformation to an that meets a given specification. The LP-to-BP transformation most extensively used in is †8:

Applying the above transformation to the order of Fig. 1.13, the -order of the Fig. 1.21 is obtained. The Z-transform of the modulator output, derived from (1.38) and (1.19), is:

†8. Approximately 70% of the

ICs use this variable transformation to obtain their architecture.


31

where

Comparing (1.19) and (1.39), it can be seen how the zeroes of the mapped from dc (in the original (in the resulting corresponds to as illustrated in Fig. 1.22.

are This

Note that, as a consequence of the transformation in (1.38), the integrators of the original become resonators in the resulting which have the transfer function in (1.27) with and The shaped quantization noise power, of the modulator in Fig. 1.21, can be obtained by substituting in (1.33), yielding an identical expression to that shown in (1.21). In an analogous way, the SNR and the DR are identical to that obtained in (1.22) and (1.23), respectively. In general, any -order, N–bit can be obtained by applying the transformation in (1.38) to an -order, N-bit As an illustration, Fig. 1.23 shows several obtained by using that transformation. Fig. 1.23(a) shows a -order , Fig. 1.23(b) is a -order, and Fig. 1.23(c) is an -order 4-4 cascade obtained from the modulator in Fig. 1.16.

32


The transformation in (1.38) preserves all features of the original modulator: SNR, DR, etc.... In addition to these characteristics, (1.38) keeps the stability properties of the original lowpass modulators. In fact, the resulting will be stable if and only if the original is stable. As for the lowpass case, the use of cascade guarantee the stability for high-order modulators (L > 2).


1.6.1.1 Pattern noise of second-order bandpass

33

modulators

The non-linear behaviour of the quantization error is also translated from to This phenomenon is much more significant as the number of internal levels of the quantizer and/or the order of the modulator decreases, the worst case corresponding to a 1-bit first-order as discussed in Section 1.4.3. In the bandpass case, a 1-bit second-order presents a noise pattern similar to that of its lowpass counterpart. To demonstrate this, the modulator of Fig. 1.23(a) was simulated for a single-tone input signal with a frequency equal to The signal amplitude was varied in the range Fig. 1.24 shows the quantization error in-band power as a function of the input signal amplitude for M = 64, showing a behaviour similar to that shown in Fig. 1.11. This behaviour cannot be explained by the linear model (dashed line in Fig. 1.24) and hence, a non-linear analysis is required. Gray [Gray90] solved the non-linear difference equations of a 1storder That analysis demonstrated that for dc inputs, the quantization error spectrum is discrete, with idle tones appearing at

where is the amplitude of amplitude of these tones is:

and

represents the fractional part of a. The

34


The above results can be extended to the bandpass case by simply applying the frequency translation to (1.42). This shows that the quantization error nd spectrum of a 2 -order with a sinusoidal signal placed at will contain pairs of idle tones at

which agrees with the experimental observations detailed in Chapter 6. Note that, up to now, the input tone has been assumed to be placed at which corresponds to the minimum quantization noise power, and hence maximum DR. However, as will be detailed in Chapter 4, circuit parasitics will cause to shift from Hence, the signal should be centered at in order to obtain the maximum resolution. Placing a single tone at a frequency different from in a is equivalent to applying a sinusoidal signal of low frequency in a As demonstrated in [Gray90], the output spectrum of a with a sinusoidal input signal of frequency, is discrete, having tones at

The above result can be extended to the bandpass case, by applying the frequency translation to (1.45). This shows that the output spectrum of a -order will contain idle tones at

Bandpass Sigmn-Delta A/D Converters: Fundamentals and State-of-the-Art

35

where

Note that, two families of tones appear at both sides of which can corrupt the signal information. Measurements in Chapter 6 confirm the above results.

1.6.2 Other lowpass-to-bandpass transformations The Z-domain transformation, places the zeroes of at This relaxes the image-rejection and anti-aliasing filtering requirements as shown in Section 1.5.2. However, centering the signal passband at that location offers some disadvantages. On the one hand, in the presence of non-linear errors in the analog circuitry of the modulator, any inter-modulation distortion products resulting from the mixing of tones located at with input signal will fall inside the passband, thus corrupting the signal information. This will be treated in more detail in Chapter 4. On the other hand, for a given input IF, the demands for the sampling rate of the modulator are more restrictive than placing the signal passband center frequency between and [Loui99]. The reasons above motivate us to generalize the LP-to-BP transformation in order to locate the zeroes of at any arbitrary frequency. Intuitively, one possibility may be extending (1.38) to the following transformation [Zhan91]:

Because of the above transformation, the transforms into:

of an original

-order

whose zeroes are placed at with Therefore, the transformation in (1.47) allows us to place the zeroes of the bandpass at any even submultiple of the sampling frequency. However, this transformation offers

36


several disadvantages as compared to that in (1.38). On the one hand, the order of the resulting is increased unnecessarily for On the other hand, in general, the transformation in (1.48) does not preserve the stability properties of the original [Nors97]. Constantinides reported a more general LP-to-BP transformation for filters which preserve all the properties of the original filter [Cons70]. Constantinides’ LPto-BP transformation applied to is [Ong98]:

Note that, for the above transformation is reduced to that shown in (1.38). Applying Constantinides’ transformation to an -order, N-bit the following results:

1.6.3 Optimized synthesis of A more flexible approach for designing consists in directly synthesizing the forward path loop filter. This allows us to place the poles and zeroes of both and optimally in order to fulfil a given specification [Jant94]. From this perspective, the modulator design problem is essentially reduced to that of filter optimization. Therefore, once suitable and are generated, an architecture that implements these transfer functions is synthesized. The resulting architectures are usually of the interpolative type like that shown Fig. 1.14. This type of architecture offers the possibility of designing in such a way that it performs a bandpass filter, thus eliminating the necessity of an antialiasing filter prior to the modulator. However, as occurs with other interpolative structures, complicated analog circuitry is required, thus being more sensitive to the precision of the components. For illustration purposes, Fig. 1.25(a) shows a -order composed of a cascade of resonators, designed using this method [Jant93]. Fig. 1.25(b) shows the


pole/zero location of and placed around In this case an anti-aliasing filter (see Fig. 1.25(c)). 1.6.4 Quadrature bandpass

37

Observe that the zeroes of are realizes a bandpass function which acts as

modulators

As stated in Section 1.2, IF-conversion based digital radio receivers, the in-coming signal at the antenna, is first mixed down into an IF location where it is digitized and subsequently demodulated. Fig. 1.26(a) shows a typical block diagram of a digital receiver that employs a multiplier as a mixer. The multiplication in the time domain between the LO and the antenna signal is equivalent to a convolution in the frequency domain. Because of this convolution, spectral components at the image frequency (of the signal) are mixed down into the same IF as the desired signal is, thus corrupting the information. This can be avoided if an image-reject filter is used as illustrated in Fig. 1.20(b). However, for low-IF frequencies, narrow-band high-Q bandpass filters are required, meaning an increase of the power consumption and forcing us to use off-chip circuitry. Image-rejection or quadrature mixers [Lee98] overcome this problem by mixing with both a cosine and a sine signal that performs a rejection of the image compo-

38


nents†9. An obvious consequence of the quadrature mixing is that the IF signal is separated into two components: I and Q. Hence, two are required as illustrated in Fig. 1.26(b), which means doubling the required hardware – two compared to only one used in Fig. 1.26(a). This fact motivates finding new strategies that solve the problem of the A/D conversion of both I and Q signals. Fig. 1.26(c) shows a scheme that uses a complex, or quadrature, version of a called quadrature [Jant97b]. This type of which uses complex quantization noise filtering, employees only one ADC to perform directly the conversion of both I and Q mixer outputs. Fig. 1.27 shows a conceptual block diagram of a quadrature The main difference with respect to conventional is the complex bandpass filter embedded in the loop. Thus, the modulator output consists of a pair of high-speed bit streams, one of them representing the real output and the other one the imaginary †9. This cancellation effect is only obtained in the ideal case. In practice, a mismatch between both paths of the quadrature mixer will cause undesired image signals to appear at the IF band [Jant97b].


39

output. When combined, these two outputs form a complex digital signal which represents the complex input signal (I and Q components coming from the mixer in an RF radio receiver) and the shaped quantization noise. The performed by quadrature has complex value coefficients and hence, it is not constrained to performing complex-conjugate zeroes or to having a symmetric response respect to dc. This allows the -order to place L zeroes at without having any zero at Therefore, the zeroes of may be a rotated version of those of an -order To illustrate this, let us consider a complex -order with This function, displayed in Fig. 1.28, presents 4 zeroes at The complex filter in a quadrature can be realized either using DT (SC or SI) or circuitry. In practice, this filter is constructed from several cross-coupled real filters, as illustrated in Fig. 1.29(a). The complex output signal is:

40


where

Observe that there is an analogy between complex filters and fully-differential filters in the sense of that both architectures double the number of elements required to implement a given circuit. As an illustration, Fig. 1.29(b) shows an efficient realization of a complex first-order filter with a single pole at whose transfer function is given by [Jant97b]:

Note that two cross-coupled integrators are required to perform this filter. In the case of quadrature 2L integrators will be required to implement an – order modulator. However, they can place L zeroes at the notch frequency instead of L/2 as occurs with conventional This is especially advantageous for application in digital RF receivers. For instance, assume that we use – order to implement the RF receivers in Fig. 1.26(b). Thus, we will need eight integrators to place two zeroes at the notch frequency. On the other hand,


using a quadrature we will also need eight integrators, but a shaping function will be performed on the quantization noise.

41

-order noise

Despite the mentioned advantages of quadrature in practical cases, there is an important limitation of this type of modulators due to mismatching between real and imaginary channels. Mismatch in the quadrature mixer or the will create an image signal. As a consequence, modulator input signals presented in the image band will appear in the signal band, thus corrupting the information [Jant97b]. To reduce this effect, quadrature must be designed to place some of the zeroes at the image bandwidth [Jant96]. However, this reduces the order of the quantization noise filtering performed by the quadrature modulator – one of its main advantages with respect to conventional

1.6.5 N-path bandpass

modulators

Centering the notch frequency at has multiple advantages as already mentioned. However, in practical applications, the dynamic range of the modulators becomes increasingly constrained by circuit non-idealities at high sampling rates – needed to digitize signals at IF locations. To overcome this problem, some authors propose the use of N-path filter structures to implement the resonator transfer function [Ong98], Fig. 1.30 shows the block diagram of a generalized N-path filter structure [Greg86]. If the paths in the N-path filter are assumed to be perfectly matched, it can be shown [Greg86] that the Z-domain transfer function of the structure in Fig. 1.30 is:

42


where is the transfer function of each identical path filter, stands for the variable of a single path. Hence, while is a single delay with respect to the sampling rate of a single path, represents a single delay with respect to the effective output rate of the N-path filter. Using the N-path design technique, the resonator transfer function can be separated into N interleaved paths, in the following way,

Note that in this resonator structure, the constituent high-pass filters are clocked at 1/N the overall resonator output rate, so the demand for the circuit bandwidth is relaxed by a factor of N. As an illustration, Fig. 1.31 shows a 2-path -order [Ong97b]. The original architecture is partitioned into two interleaved paths, with the resonators replaced by high-pass filters. Fig. 1.32 shows two alternative implementations of a high-pass filter [Taba99]. Fig. 1.32(a) consists of an integrator in a feedback loop. Fig. 1.32(b) achieves an equivalent transfer function by chopping the input and output of the integrator at . The latter is less sensitive to the integrator noise than


43

the former (because of the feedback). However, it needs to implement two analog mixers. Nevertheless, the number of mixers can be reduced by combining the mixer at the output of the first resonator with that at the input of the second resonator. In conclusion, the use of N-path filters permits an increase of the effective sampling frequency of bandpass modulators, thus relaxing the bandwidth specifications for their building blocks. However, in practical applications, these types of architectures are very sensitive to gain and phase mismatches between the signal transfer function in the different paths. This manifests itself as mirror image signals which appear in the signal bandwidth and corrupt the transmitted information [Ong97b].

1.6.6 Continuous-time bandpass

modulators

The architectures described in earlier sections assumed that the loop filter is of the DT type. In recent years, the increased demand for high-speed has motivated the development of CT loop filter based genetically known as continuous-time [Ragh97] [Shoa97] [Gao98] [Enge99] [Tao99c][Maur00]. This approach offers several advantages. On the one hand, CT filters are much faster than their DT counterparts. On the other hand, it can be shown that provide an implicit anti-aliasing filter for out-of-band signals at no cost [Shoa97]. In contrast, are more sensitive to clock jitter than DTThis is because the internal clock that controls the comparison instant, also controls the rising and falling edges of the DAC output. Hence, clock jitter

44


errors are directly added to the input signal [Tao99b]. Another important limitation of is the excess loop delay contributed by each building block in the modulator loop, which can severely degrade the quantization noise transfer function [Shoa95]. The architecture of any arbitrary can be generated by applying a DT-to-CT transformation to an original that meets the required specifications. Therefore, much of the knowledge available for can be utilized for synthesizing architectures. There are different ways of realizing such a DT-to-CT transformation depending on the shape of the DAC impulsive response [Shoa94]. The differences among them will originate several architecture issues, specific of , which will be briefly reviewed in this section. A more detailed analysis – beyond the scope of this work – can be found in several works related to this subject [Shoa97][Gao98]. The block diagram of a conceptual is shown in Fig. 1.33. This modulator is internally a DT circuit since there is an S/H circuit inside the loop, just at the quantizer input. This fact makes the overall loop from the output of the quantizer back to its input have a Z-domain transfer function as illustrated in Fig. 1.33(b). The equivalent DT loop filter transfer function is [Shoa97]:


45

where

is the transfer function of the DAC, which in the time domain can be expressed as:

Since has a pulse waveform, the expression in (1.56) is known as the pulse invariant transformation. The parameters pl and p2 determine the DAC pulse type, which can be: Nonreturn-to-Zero and Return-to-Zero and and Half-delay Return-to-Zero (HRZ, and The pulse invariant transformation allows us to obtain an equivalent relation between DT- and Thus, the synthesis process of a starts from a DT loop filter that satisfies the required specifications and then it is transformed into an equivalent CT filter using (1.56). As an illustration, Table 1.2 shows the equivalent Z – domain loop filter transfer functions (obtained for NZ, RZ and HRZ DAC impulsive responses) of a -order [Gao98]. Note that none of the Z-domain transfer functions in Table 1.2 is equal to:

which is the transfer function derived from applying the LP-to-BP transformation – order convenient for the reasons mentioned in Section 1.6.1. To obtain the loop filter in (1.59), the authors in [Shoa95] proposed a multi-feedback loop which combines different types of DAC transfer functions.

46


1.7 Decimation for bandpass

ADCs

The decimator filter is the last stage of a ADC as illustrated in Fig. 1.8. The modulator output is an N-bit stream (with N typically less than 4) with a sample rate much higher than the Nyquist-rate. This digital data stream codifies the input signal plus the shaped quantization noise. The decimator realizes two operations on the modulator output: filtering the out-of-band quantization noise and reducing the sampling rate to the Nyquist rate [Nors97]. Fig. 1.34 illustrates the decimation process for an (Fig. 1.34(a)) and a (Fig. 1.34(b)). In both cases, the operations are the same. The modulator output, y, is first filtered by a signal band filter (of the lowpass type for and of the bandpass type for with a digital cut-off frequency of The purpose of this filter is to remove all out-of-band signal components in order to avoid aliasing in the subsequent sampling rate compressor stage. Thus, the band-limited signal resulting from the filtering, w, is downsampled by discarding M – 1 out of every M samples to produce the decimated signal, at the Nyquist rate. Note that the scheme of Fig. 1.34(b) requires a high-Q narrow-band BPF with a high passband center frequency. This yields an increase of cost, in terms of power consumption and silicon area, as compared to the lowpass case. This problem can be avoided by using the scheme shown in Fig. 1.35, composed of a complex mixer and a complex lowpass filter [Schr90]. The modulator output is mixed down to baseband


47

through the multiplication of This scheme can be notably simplified if because the multiplying signal is a sum of two periodic data series containing 0's and ±1's as illustrated in Fig. 1.35. As the inputs to the lowpass filters are zeros in alternate clock cycles, the two lowpass filters can be simplified by only one multiplexed in time.

48


1.8 State-of-the-art bandpass

ADCs

Although the idea of translating the zeroes of from dc to any given IF location was originally presented by Schreier and Snelgrove in 1989 [Schr89], it was not until 1992 that Jantzi, Snelgrove and Ferguson published the first monolithic [Jant92]. Since then, there have been a large number of ICs implemented in several technologies (CMOS, BiCMOS, Bipolar), with diverse circuit techniques: DT (both SC and SI); or CT circuits using different supply voltages. Table 1.3 shows a summary of the ADC ICs published to this day. For each of them, the most significant figures are shown, namely: DR, SNR, the power consumption, the characteristics of the fabrication process and the modulator architecture. For the latter, the synthesis method employed is also given. Note that most modulators use a single-loop architecture, obtained by applying the LP-to-BP transformation, which, as stated in Section 1.6.1, makes

The modulators in Table 1.3 cover multiple applications in digital wireless communications, ranging from telemetering [Norm96b] to digital radio receivers


49

50


[Jant93] [Sing95] [Hair96] [Enge99] [Loui99] and modern cellular phones [Long93][Song95] covering commercial standards such as GSM [Shoa97] and DECT [Taba99]. Depending on the application, there are different specifications for DR, and Hence, it is difficult to state a measure of comparison among all reported modulators. The authors in [Good96] proposed a Figure-Of-Merit (FOM) for comparative evaluation of data converter integrated circuits. The original formula of the FOM can be adapted to as follows [Mede99],

The above formula (expressed in picojoules), which represents the energy needed per conversion, is not suited to compare because it does not include However, this data constitutes one of the most important design specifications. Thus, in order to compare different performances, in Fig. 1.36, the modulators in


51

Table 1.3 are placed in the power consumption–speed plane. Note that, for similar values of the power consumption per resolution CT modulators achieve higher values of than DT modulators. However, the best trade-off among power consumption, resolution and is obtained by SC modulators, in particular those reported in [Hair96][Taba99]. Table 1.3 shows that different technologies were employed by ICs. Observe that most are integrated in a BiCMOS technology, while CMOS is the technology employed by the majority of However, to the best of our knowledge, only two of the latter were integrated in a standard CMOS process [Ong97b][Toni99]. This is due to the fact that SC circuits are very sensitive to capacitor linearity. Most linear capacitor structures are formed by two poly layers, not available in standard processes. This fact has motivated the exploration of other analog techniques compatible with standard, digital VLSI technologies. This is the case of SI circuits [Toum90c], which during the last few years have been used for different analog functions, including filtering [Hugh96] and A/D conversion [Tan97][Jons00]. Particularly, a large number of SI have been reported, as summarized in Table 1.4. The SI technique is based on the principle that, by storing the gate voltage of an MOS transistor, the current flowing through it can be memorized. In addition to its obvious compatibility with a standard process (poly-poly capacitors are not needed), the SI technique offers other advantages. On the one hand, as signal carriers are currents instead of voltages, the signal range is not limited by supply voltages. This fact makes SI a suitable technique for low-voltage supplies. On the other hand, as operational amplifiers are not needed, fast operation can be achieved with low power consumption [Hugh96]. In the case of the mentioned advantages have not been demonstrated in practice. To illustrate this, Fig. 1.37 compares the FOM of both SI and reported up today. Note that the performance obtained by SI circuits is worse than that obtained by SC circuits. Observe that, while most SC modulators feature an FOM below about 10pJ, practically all SI modulators obtain an FOM above 100pJ. Such a lower performance is due to several reasons. First, since the SI technique is a relative “young” technique, its associated errors have not been properly analyzed nor modelled as well as their influence on the performance of the modulators. Secondly, the larger influence of SI non-idealities, as compared to the SC ones, force the use of circuit strategies with the penalty of increasing the power consumption and the active area. Finally, the lack of CAD methodology for SI circuits, hin-

52



53

ders the automation of the synthesis tasks in the design process, as well as their verification through behaviour simulation. The work in this book aims at solving these problems by means of a systematic analysis of mechanisms of errors in SI circuits as well as their influence on the performance of For this purpose, architecture and circuit methodologies are presented to design using SI circuits. The models and techniques described here are demonstrated through two CMOS prototypes intended for AM digital radio receivers. One of them uses a single-loop -order architecture, and digitizes AM signals with 10.5-bit effective resolution and 60mW power consumption from a 5V supply voltage (10.5-bit@60mW@5V). The other one is a order architecture featuring 8-bit@42mW@5V in the commercial AM band. For comparison purposes both modulators are placed in Fig. 1.36. It can be seen that performance comparison between SI- and is better than in the lowpass case (see Fig. 1.37). In fact, the -order SI appears below the best fitting straight line of the thus demonstrating that SI is a viable alternative to the traditional SC technique for implementing

54


SUMMARY In this chapter, basic concepts and architectures of bandpass A/D converters have been described. These types of converters have been shown suitable for realizing the analog-digital interface at the front-end of modern wireless communication systems, especially digital RF receivers. The first part of the chapter described the fundamentals of A/D converters, mainly those related to modulators. In the second part, those aspects which are relevant for have been detailed. Different ways of synthesizing the noise transfer function have been summarized, pointing out their advantages and drawbacks. Special emphasis has been made on the lowpass-to-bandpass transformation, , which is the synthesis method most used by reported This transformation keeps most properties of the original One of these properties is the correlation between the quantization error and the input signal, which manifests itself as idle tones at the output spectrum of the modulator. Although the chapter centers on the modulator block, the decimator has also been briefly described. Among other ways of performing the decimation, the one that uses digital mixing and lowpass decimation has shown to be the most efficient one in terms of area and power consumption. To finish the chapter, a compilation of reported state-of-the-art bandpass modulator ICs has been made. They have been grouped according to the circuit technique employed, and compared regarding the power consumed, effective resolution and maximum speed operation. Although best performance is obtained by SC modulators, only two of them have been fabricated in a standard CMOS technology. An alternative is using SI circuits. This technique does not need poly-poly capacitors for its implementation, thus being compatible with standard CMOS technology. However, SI obtain worse performance than their SC counterparts. This is a consequence of the lack of detailed analysis of SI non-idealities as well as their influence on the modulator performance. The analysis, modelling and design methodologies that will be presented in this book, have made possible the design of two SI which, as described in this chapter, obtain a good comparison with the state-of-the-art thus demonstrating that SI is an interesting alternative to SI for implementing analog-digital interfaces in standard VLSI technologies.

Switched-Current Building Blocks for

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55

Chapter 2 Switched-Current Building Blocks for 2.1

Modulators

Introduction

Traditionally, Analog-to-Digital Converters (ADCs) used Switched-Capacitor (SC) circuits to realize their building blocks [Cand92][Nors97]. This analog sample-data technique is based on the idea that a periodically switched capacitor can emulate a resistor. Linear and accurate time-constants are obtained using a quite simple circuitry, much less intricate than that required for analog Continuous-Time (CT) techniques [Umbe89][Greg86][John97]. This is a positive consequence of its synchronous operation, another being the use of the precharging time slots for error correction. SC circuits are also easily decomposable into loosely coupled modules, and hence relatively simple to design and amenable for automatic synthesis [Mede99]. In the last decades, there has been an emergence of Digital Signal Processing (DSP) techniques, which have absorbed most functions realized by SC. The digital approach offered many advantages over SC: flexibility, programmability,.... [Gray87b]. However, most signal processing systems must interact with the external world thus requiring data converters and analogue interfaces. The requirements for realizing both a DSP core and the associated analogue peripheral circuitry in a single chip has led to the appearance of the so-called mixedmode signal chips. However, the use of digital CMOS technologies for the realization of these chips has resulted in degraded SC performance for several reasons. On the one hand, double polysilicon structures, which had been traditionally used by SC circuits to form high-quality linear floating capacitors, are not available in standard digital technologies. To overcome this problem some alternative capacitor structures have been proposed: One alternative is the use of inter-metal capacitors. These structures present two main problems. First, their capacitance density is much smaller than that of poly-poly capacitors. This can be partially solved by using multi-layer

56


sandwiched capacitors, that make use of several metal layers, available in modern VLSI technologies. Second, metal-metal capacitors present worse matching properties than double-poly capacitors. This is due to the fact that the polishing process of the inter-metal oxide (dielectric) is not as precise as that of the inter-poly dielectric and hence, the thickness and permittivity variations of the former are larger than that of the latter. Another alternative structure consists of using MOS capacitors [Baza95] [Yosh99], which have large capacitance per unit area, and good matching properties. However, as a consequence of their hard non-linearity, they cannot be used in SC circuits unless cancellation circuit strategies are incorporated, leading in most cases to impractical realizations. Another limiting factor that degrades the performance of SC circuits implemented in standard VLSI technologies is the continuous reduction of supply voltages, prompted by the continuous scaling-down process. This fact, which is advantageous for digital circuitry, makes the design of SC circuits difficult, which are forced to use clock boosting strategies for switches and to increase the power consumption in order to obtain high-speed and high dynamic range opamps with low voltage operation. In this scenario, the use of current-domain sampled data technique, also named switched-current (SI) [Toum93], instead of voltages results advantageous for several reasons. On the one hand, SI circuits utilize the gate oxide capacitance of the MOS transistor to store the signal charge and so they do not need the second layer of poly required for SC circuits. On the other hand, as the signal carriers are currents, the supply voltage does not limit the signal range as much as in SC circuits. Therefore, SI circuits are more suitable than SC for low-voltage operation. The above considerations make the SI technique very well suited for designing mixed-signal chips in standard technologies with low supplies voltages. In particular, it has successfully been demonstrated in the field of lowpass modulators through several ICs [Craw92a] [Brac94a] [Nedv95] [Tan96] [Moen97] [Jons98b]. The work of this book explores the use of SI circuits in the design of bandpass modulators As a starting point, this chapter describes all basic operations realized by SI circuits, especially those required for Different building blocks that perform those operations are analyzed from the ideal point of view, and compared attending to their sensitivity to scaling coefficients.


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57

2.2 Principle of Operation: The Current Memory Cell The basic principle of SI circuits is illustrated in Fig. 2.1. When switch S (controlled by is closed (see Fig. 2.1(b)), the gate node is connected to the input voltage Assuming that the transistor M is operating in the saturation region, and neglecting second-order effects, the drain-source current, will be a function of the gate-source voltage, . When the switch S opens (see Fig. 2.1(c)) the gate node remains isolated thus allowing to memorize the charge stored on the gate oxide capacitance, This keeps the drain-source current at (Fig. 2.1(c)). The first attempt to exploit this principle was made in 1972 [Mats72]. However, it was not until 1989 that it was revived independently by a number of researchers [Hugh89][Groe89][Nair89][Vall89][Wegm89a]. The most elementary SI circuit is the so-called current memory cell. The first memory cell implemented was based on a simple current mirror. Some authors referred to this circuit as the first-generation memory cell [Hugh89]. Fig. 2.2(a) shows the basic schematic of such a cell. It has two different modes of operation: the sampling and the hold operation.

58


On clock phase (sampling phase) of period the switch is closed, and the memory cell operates as a current mirror. The sum of the input current and the bias current flows through the drain of M1 giving †1

During this clock phase, M2 is only connected to the bias current source

†1.

is written as

in order to simplify the notation.


and therefore, the output current,

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59

as Fig. 2.2(d) illustrates.

On clock phase of clock period the switch is open, and the switch is closed. The transistor gate capacitance of stores the charge corresponding to the voltage at time on the sampling phase. Thus, the drain current of is held at the value corresponding to that of yielding

and the output current is

Taking the Z-transform in (2.4) gives

It can be derived from the above expression that the output current is a memorized copy of the input current. This is achieved thanks to the charge contained in the gate capacitance of Note that the output current is not available during phase Fig. 2.2(b) shows the schematic of a first generation current memory cell whose output current is available during the entire time. This cell is sometimes called trackand-hold. On clock phase (track phase), the output current tracks the input and during the clock phase (hold phase) the output current is held at the value stored in the previous phase. The transient response of the memory cells shown in Fig. 2.2(a) and (b) is illustrated in Fig. 2.2(d). The first generation memory cell is not very appropriate for critical filter realizations, due to sensitivity problems [Daub90]. Circuits based on this cell suffered inevitable errors resulting from mismatch between the memory transistors and These errors will be explained and analyzed in the next chapter as well as their effects on the performance of the memory cell. The introduction of the current copier [Daub90] enabled this imperfection to be overcome and the so-called second-generation switched-current memory cell was developed [Hugh90b]. Fig. 2.3 shows the schematic of this circuit. Note that it can realize the operation of a current memory using a single transistor, M, operating as follows. On clock phase of clock period switches and are

60

Systematic Designof CMOS Switched-CurrentBandpass Sigma-Delta Modulators for DigitalCommunicationChips

closed thus allowing the current

to flow in the drain of M, giving

On phase of clock period , switches and is sustained. With now closed, the output current,

are open and the value of

is forced to flow through the output. It is important to note that the operation of the memory cell in Fig. 2.3 is degraded in practice as a consequence of several mechanisms of error, namely: finite output conductance, charge injection error, incomplete settling error... The control of these errors can be made either through sizing or by using circuit strategies that will result in more advanced memory cell topologies. This will be discussed and analyzed in detail in the next chapter. Here, we are interested in how to synthesize building blocks for modulators based on SI memory cells. For the sake of simplicity, we will base the work on the basic second-generation memory cell of Fig. 2.3. However, the synthesis process described here can be extended to the case of more advanced memory cells.


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2.3 SI Integrators As explained in Chapter 1, the integrator is the most fundamental analog building block in As will be shown in this section, an SI integrator can be realized through the connection of several SI memory cells. The way in which this connection is realized will allow us to obtain a large family of integrators with different transfer functions. As a starting point for our discussion, DT voltage mode integrators will be briefly reviewed. 2.3.1 Review of discrete-time integrators Traditionally, Discrete-Time (DT) integrators have been implemented through the use of SC circuits. A large number of SC integrator structures have been derived from the original CT integrators – realized through resistors, capacitors and opamps – by means of the substitution of the original resistor with an equivalent SC circuit [Greg86][Umbe89]. Fig. 2.4 illustrates this process for an inverting integrator. The original CT integrator is shown in Fig. 2.4(a). Replacing the resistor R with the SC circuit shown in Fig. 2.4(b) results in the SC integrator of Fig. 2.4(c). Observe that the resulting Z-domain transfer function can be directly obtained by applying the Forward-Euler (FE) transformation†2 to the original CT integrator, and making For that reason, the resulting SC integrator is called an inverting FE integrator.

†2. The Forward-Euler transformation is defined as:

62


In the more general case, there will be many different structures of SC integrators depending either on the type of SC resistor used or the configuration of the original integrator (either inverting or non-inverting). Table 2.1 shows a classification of the different types of SC integrators and their corresponding transfer functions which are found in literature. Details on how they have been derived is beyond the scope of this work and a complete review on them can be found in a number of books and tutorial papers [Greg86] [Umbe89] [Lake94][John97]. The aim of this section is to demonstrate – through the description of different SI integrator topologies – that SI circuits are able to realize all transfer functions shown in Table 2.1. As a starting point we will describe different ways to implement delay elements, which are the basic building blocks for SI integrators. 2.3.2 SI delay elements The use of delay blocks is required for the realization of all transfer functions shown in Table 2.1. An SI circuit capable of performing a full clock period delay can be achieved by simply cascading two memory cells as Fig. 2.5(a) shows. From (2.7) it is easy to show that:


Modulators

63

64


Combining the above equations and taking the Z-transform, the transfer function of a full clock period delay results in:

Note that the duration of this delay can be controlled by simply changing the timing diagram of the clock phases. For instance, let us consider the delay cell shown in Fig. 2.5(b). Using an analysis similar to that shown in the previous section, the following expressions can be derived:

giving the following transfer function for the delay element:

A delay line which delays the input N clock periods could be generated by cascading pN memory cells, with p being the number of phases in which the clock period is divided. This way of implementing delay lines is not very appropriate in practice because the transmission error (associated to each memory cell) is increased by a power of pN. A better approach to implement a delay of is illustrated in Fig. 2.5(c). The circuit consists of N + 1 memory cells connected in parallel using the clock phase diagram inset Fig. 2.5(c). Each cell delivers its output signal current immediately before its next input and N periods after its previous output phase [Toum93]. Note that the circuit in Fig. 2.5(c) can be represented by the N-path block diagram of Fig. 2.5(d), whose transfer function is [Greg86]:

2.3.3

SI non-inverting integrators

Non inverting integrators (with unity gain) are governed by the following finitedifference equation:


Modulators

65

which can be represented by the Z-domain block diagram shown in Fig. 2.6. This behaviour can be easily reproduced using SI circuits by substituting the delay elements in the block diagram of Fig. 2.6 with the corresponding SI delay blocks. Let us consider the SI non-inverting lossless integrator shown in Fig. 2.7(a). Two memory cells are connected in series to form a delay cell and the output current is fed back to the input summing node. This circuit can be simplified by inspection to that shown in Fig. 2.7(b) because the switches and in the integrator loop – controlled by phases and –are in parallel and may be replaced by a short circuit [Toum93]. The operation of this circuit is as follows. On phase of clock period , transistor is diode-connected and its drain source current can be written as:

and the output current,

On phase

is

of clock period

the drain current of transistor

is

From Eqs. (2.14), (2.15), (2.16) and taking Z-transform, it can be shown that the transfer function of the integrator is:

66


which corresponds to the transfer function of a non-inverting FE integrator, shown in Table 2.1. Another alternative SI circuit which implements the behaviour in (2.13) is the integrator of Fig. 2.7(c). Note that, except for the clock phase diagram, Fig. 2.7(a) is of the same topology as that in Fig. 2.7(c). However for the latter, switches and cannot be eliminated.


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67

Following the same procedure as before, it can be shown that the Z-domain transfer function of the integrator in Fig. 2.7(c) is:

Note that the delay caused by the above integrator is (2/3) of the clock period. This fact allows the realization of many topologies based on non-inverting integrators [Gora94]. However, as the clock period is divided in three phases instead of two, the involved signals have to reach the stationary state in a shorter time. In general, assuming that the clock period is divided into N phases, and that the clock phase intervals are of the same duration, the function of a non-inverting SI integrator realized using two memory cells as illustrated in Fig. 2.7(d) can be written as

where is the clock phase in which the output current is taken. For instance, the transfer function of a non-inverting LD integrator (see Table 2.1) can be obtained using the integrator structure shown in Fig. 2.7(d) for N = 4 and k = 3. Substituting in (2.19), it can be shown that the transfer function for a lossless non-inverting integrator implemented as Fig. 2.7(d) is given by:

Consider now the non-inverting integrator shown in Fig. 2.8. It contains an extra feedback stage made up of transistors and the bias current source, both of them weighted through a current mirror which also inverts the signal. On clock phase of period transistor is diode-connected and its drain source current is:

68



On phase

is

of clock period

the drain current of transistor

is

Taking the Z-transform from Eqs. (2.21), (2.22), (2.23), it can be shown that the transfer function of this integrator is:

Note that if the weighted output, is fed back during instead of during the transfer function of the integrator in Fig. 2.8 will be given by:

In the more general case of N -phase integrators, a similar transfer function to (2.24) can be found by including a feedback stage like that of Fig. 2.8 into the integrator shown in Fig. 2.7(d), yielding:


Modulators

69

The performance of this integrator for physical frequencies, is given by

The above expression can be simplified for the CT case by making

It is seen from the above expression that, except for the excess phase lag term, the above transfer function corresponds to a damped CT non-inverting integrator with a transfer function given by

which has a dc gain equal to

and a pole frequency at

2.3.4 SI inverting integrators A DT inverting integrator (with unity gain) can be described by the following finite-difference equation:

In the case of the behaviour described by the above equation can be achieved using SI circuits as shown in Fig. 2.9(a). On phase of clock period , transistor is diode-connected and its drain source current can be written as

70


On phase

of clock period


, the drain current of transistor

is

is given by

From Eqs. (2.31), (2.32), (2.33) and taking the Z-transform, we obtain:

which coincides with the transfer function of the DT LD inverting integrator shown in Table 2.1.


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71

Note that the transfer function of a DT BE inverting integrator of Table 2.1 could be obtained using the circuit shown in Fig. 2.9(a) by taking the output current during clock phase instead of This circumstance is possible from the ideal point of view. However, in practical cases, the transient response of the gate capacitance of should be completed much faster than the duration of clock phase If it does not happen, the current sunk through the output will contain an error due to the incomplete settling. For this reason, the SI BE inverting integrator is not a good choice for the implementation of practical SI circuits. As for the non-inverting integrator, a large number of inverting integrator transfer functions can be generated by simply dividing the clock period into many phases. For instance, the integrator shown in Fig. 2.9(b)[Gora94] yields the following transfer function:

if the output current is supplied during clock phase vided during clock phase the transfer function is:

while if this current is pro-

The transfer functions in (2.35) and (2.36) can be generalized to the case of N -phase inverting integrators, yielding:

where it has been assumed that the output current is provided during clock phase with As in the case of non-inverting integrators, damped configurations can be obtained using inverting integrators as illustrated in Fig. 2.10. Note that the integrator in this figure is similar to the integrator in Fig. 2.9(a) except for the extra feedback stage made up of transistors the bias current source, and the scaling stage

72


It can be shown that this circuit exhibits the following transfer function:

As for lossless integrators, the above transfer function can be extended to a more general case of N-phase memory cells. In this case, the transfer function will be given by:

and the performance for physical frequencies is given by:

As for inverting integrators, it can be shown that the above transfer function corresponds to:

which corresponds with the transfer function of a CT inverting integrator with dc gain


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73

2.3.5 Generalized SI Integrators The integrator topologies described in earlier sections can be extended to multiple inputs in a straightforward manner. Consider, for instance, the integrator structure of Fig. 2.11 which is known as a generalized integrator [Toum93]. It is made from the superposition of non-inverting, inverting and amplifying inputs giving the following transfer function †3 :

The generalized integrator is a frequently used building block for even-order state-variable filters. Apart from the FE and LD stages described above, bilinear SI integrators, which are based on the bilinear transformation can be realized as Fig. 2.12(a) shows [Toum93]. It consists of a linear combination of non-inverting and inverting lossless integrators. It can be shown that the Z-domain transfer function is given by:

Note that, if the output current is fed back on the sampling phase

as shown in

†3.This structure operates correctly from an ideal viewpoint. In practice, (2.42) will be degraded as a consequence of incomplete settling. This error will be analyzed in more detail in Chapter 3.

74


Fig. 2.12(b), a bilinear damped SI integrator can be obtained with a transfer function of the form:

2.4 SI Differentiators Although most SI modulators reported in literature are made up of filters based on integrators, some are realized by using SI differentiator based filters [Tan94a]. The design of such filters may be interesting for several reasons. On the one hand, the use of differentiators avoids the low-frequency instability problems associated with integrator based ladder circuits. On the other hand, some resonator structures – used in bandpass modulators – consist of a combination of differentiator and integrator based circuits, as will be discussed in the next section. As in the case of integrators, a good starting point for the description of SI differentiators can be found in the SC technique.

2.4.1 Discrete-time differentiators A large number of SC differentiators have been reported [Umbe89] and used for the design of many filter topologies [Yu89]. As in the case of integrators, SC differentiators were derived from original CT differentiators by replacing the resistors in the latter with equivalent SC circuits. The resulting SC differentiators can be classi-


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75

fied according to the transformation that relates their transfer function with that of the original CT differentiator. This is shown in Table 2.2. All transfer functions shown in this table can be realized using SI circuits as will be demonstrated in this section.

2.4.2 Inverting SI differentiators As with the integrators, SI differentiator modules can be realized through the interconnection of delay units. The equivalent Z-domain block for a BE inverting differentiator is shown in Fig. 2.13(a). The finite differences equation describing this

76


block diagram, given by

can be implemented using SI circuits as shown in Fig. 2.13(b)[Toum93]. The operation of this circuit is as follows. During phase of clock period current memory is diode-connected and its drain current is


On clock phase

is

of period

, the drain current of transistor

is given by

From eqs. (2.46), (2.47) and (2.48) and after taking the Z-transform, the following transfer function for the inverting differentiator is

The above transfer function can be expressed in the frequency domain by substituting in (2.49), yielding:

Assuming

the above transfer function can be written as


Modulators

77

which is equivalent to a continuous time inverting differentiator transfer function except for the excess phase lag term,

2.4.3 Non-inverting SI differentiators The following finite-difference equation

characterizes the behaviour of a non-inverting DT differentiator. The equivalent Z-domain block diagram is shown in Fig. 2.14(a). It is composed of an inverting differentiator, the output of which is inverted and fed back to the input summing node. The total loop therefore has positive feedback which makes the module unstable. It may only be used in conjunction with other circuits which render it stable by applying negative feedback [Toum93]. This can be achieved, for instance, in a biquad arrangement as we will see in the following section. Note that the Z-transform of (2.52) corresponds to a non-inverting FE differentiator of Table 2.2. Fig. 2.14(b) shows the corresponding implementation using single-ended SI memory cells. Observe that some extra current mirrors are required to realize the signal inversion. Fully-differential circuitry avoids the use of such current

78


mirrors by simply crossing-over signal pairs.†4 Following the same procedure as in the earlier section, it can be shown that the transfer function of the circuit in Fig, 2.14(b) is:

The exact performance for physical frequencies is given by:

For

yields,

which is equivalent to a CT non-inverting differentiator transfer function except for the excess phase lag term

2.4.4 Bilinear SI Differentiators The SI differentiators described in the above sections provide transfer functions which differ from their CT counterparts in an extra half-period delay. This causes a phase shift error equal to A more exact realization of an SI differentiator in the frequency domain can be obtained by using the bilinear transformation, whose transfer function is shown in Table 2.2. Fig. 2.15(a) shows the block diagram of a bilinear differentiator. It can be realized by using SI circuits as illustrated in Fig. 2.15(b). This structure is similar to the †4. This differentiator operates correctly from an ideal point of view. However, in practice an error occurs as a consequence of the incomplete settling because the output current is fed back in the clock phase in which is acquiring the input current.


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79

non-inverting differentiator except that an additional inverted input current is added to the output summing node. It can be shown that the transfer function of this circuit is:

and the frequency response is:

which for

can be approximated by

which is equivalent to a CT non-inverting differentiator. Note that the inverting bilinear SI differentiator can be obtained by simply taking

80


the output current in Fig. 2.15(b). In this case, the transfer function from the noninverting input signal to will be given by:

This differentiator structure, which has been already included in chopper stabilized SI lowpass modulators [Tan97], can be used in combination with a noninverting FE integrator to form a resonator structure which presents a low sensitivity of the resonant frequency to the scaling gain errors. This will be discussed in more detail in the next section.

2.5 SI Resonators Resonators are second-order filter sections (also called biquads) which realize a bandpass transfer function. As stated in Chapter 1, resonators play the same role in as integrators in For this reason, the synthesis and design of this block is crucial in order to get a good performance of the This section explores all possible topologies of resonators which use SI circuits (integrators, differentiators and delay cells). As in the case of integrators and differentiators, the most appropriate SI resonator structures can be obtained by emulating the well-known CT resonators. Therefore, as a starting point, the basic properties of biquads will be reviewed and fundamental design parameters used in the design process will be defined. 2.5.1 Biquad filter background

Biquad filters are more flexible and universal than first-order filters since they can realize all types of filtering functions: lowpass, highpass, bandpass, bandstop and allpass. A DT biquad can be described in the Z-domain by a transfer function of the form [Umbe89]


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81

Substituting in (2.60), and assuming that the frequencies which are of interest are much lower than , it can be shown that the continuous-time biquadratic transfer function corresponding to (2.60) can be expressed, after some manipulations, as [Umbe89]

where Q is the pole quality factor, and is the resonant angular frequency. It is interesting to note that Q describes the selectivity of the biquad. Thus, if Q is high, the magnitude of the transfer function will have a sharp peak near Specifically, let us assume that the transfer function has two conjugatecomplex poles at then, it can be shown that they are related to the parameters and Q as

By analogy with the continuous-time case, for any pair of conjugate-complex poles in the Z-domain we can represent the denominator of (2.60) in canonic form as

It can be easily derived that the roots of the above equation (the poles of (2.60)) can be expressed as being

The above relationships provide considerable simplification in the analysis and design of biquads. However, more exact formulae can be obtained by applying the bilinear s-z transformation to (2.60). After some algebraic manipulation and identifying (2.64), it can be shown that

82


On the other hand, the DT resonant angular frequency, denoted by derived giving

can be

If the biquad is composed of SC circuits, the scaling coefficients of (2.60), i.e, and are realized by capacitor ratios. Otherwise, if the biquad is made up of SI circuits, and are physically implemented through current mirrors by weighting the aspect ratio between the input and the output currents. Let be a parameter which represents the capacitor ratio (in an SC realization) or the transistor aspect ratio (in an SI realization). The sensitivity of Q with respect to represented by is a critical parameter which is often used as a measure for different filter configurations. It can be derived from (2.65) that

On the other hand, in bandpass applications, such as it is also important to control the position of the signal bandwidth central frequency. This is determined by the location of the resonant frequency of the biquads in the filter. Hence, the control of is a hard specification for the designer. For this reason, it will be very important to know the sensitivity of with respect to This parameter can be derived from (2.66)


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83

The transfer function of (2.61) is quite general, and in fact, different filter functions (lowpass, highpass, bandstop and bandpass) can be derived by appropiately selecting the numerator coefficients [Umbe89]. In this work we are interested only in a particular type of biquads, often called resonators, which realize a bandpass filter function, given by:

Depending on the transformation used, different Z-domain resonator transfer functions can be derived whose denominator can be expressed in the form of (2.63). In the following, we will refer to resonators as DT resonators which can be described by the following transfer function:

where 2.5.2 Discrete-time resonators As stated in Chapter 1, most of the reported bandpass modulator architectures have been obtained from corresponding lowpass prototypes by applying a transformation [Nors97]. As a consequence of this transformation, the zeroes of the noise transfer function change from dc to a quarter of the sampling frequency. The integrators which form the loop filter in the original modulator become resonators which are described by the following transfer function:

where by substituting phase of being

The performance of for physical frequencies is obtained in (2.71). Fig. 2.16(a) depicts the magnitude and for in a narrow bandwidth around the resonant frequency, As can be seen in this figure, the resonator performs an infinite gain at Fig. 2.16 (b) plots the impulsive response for an input sig-

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nal of amplitude A. Observe that the resonator impulsive response is equivalent to a CT oscillator (dashed line) sampled at

2.5.2.1 Resonator structures based on differentiators and integrators There are many filter structures which implement the transfer function in (2.71) [Sing95]. Assuming an ideal realization of the resonator, all these structures would provide identical behaviour. However, in the presence of errors, the scaling coefficients which are used to build the mentioned structures deviated from their nominal values due to either capacitor ratio errors – for SC circuits – or to transistor size ratio errors – in the case of SI circuits. This causes different resonator structures to behave differently. The most important effect is that the position of the filter poles is affected in different ways by the errors. In some structures the filter poles move around the unity circle in the Z-plane. This results in the resonant frequency not being properly placed. In other structures the effect of errors will move the resonator poles off the unit circle (in the Z-plane), causing unstable behaviour. If the poles move inside the unit circle, then the Q factor will be reduced, thus reducing the gain of the filtering at the resonant frequency. Fig. 2.17(a) shows a resonator structure made up of LD Integrators (LDI). This topology, often called LDI-loop resonator [Sing95], has a transfer function of the form:


which for the nominal values of the scaling coefficients results in the transfer function of (2.71) with

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and

As was mentioned in the previous section, Q and are crucial parameters which define the selectivity and the resonant frequency of the resonator. For the res†5 onator in Fig. 2.17, nominally, and . In practical cases, the errors associated to the scaling coefficients in Fig. 2.17(a) will shift the resonant However, Q will remain at its frequency to nominal value. This is illustrated in Fig. 2.17(b) by plotting the movement of the resIt can be seen how the onator poles in the Z-plane for changes in and poles move around the unity circle thus guaranteeing that this structure will be stable. Fig. 2.18 illustrates the behaviour of this resonator in practical cases. Fig. 2.18(a) plots the frequency response for several values of , with As can be seen from this figure, the resonant frequency is shifted but the resonator gain – which depends on Q – remains at the same value. Fig. 2.18(b) shows the impulsive response for an input signal of amplitude A . Observe that the output amplitude oscillates but is not attenuated in time. Fig. 2.19(a) shows another resonator structure which realizes the transfer function in (2.71), with It is made up of two non-inverting FE integrators. The first integrator has to be damped with a feedback scaling gain, named

†5. Infinite Q is reached if LDIs are considered ideal. However, in the presence of errors, a finite Q is obtained.

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The transfer function of this resonator is:

For

the

nominal values of the scaling coefficients: and yields giving the same values of and Q as with the LDI-loop resonator. However, the main drawback of the circuit in Fig. 2.19(a) is that errors in scaling coefficients can move poles outside the unit circle as illustrated in Fig. 2.19(b). Note that only the errors in will force poles to move around the unity circle thus causing to shift from its nominal position.


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As illustrated in Fig. 2.19(b), the FE resonator behaves as a LDI-loop resonator under changes on However its behaviour changes with respect to Fig. 2.20(a) depicts the influence of (for and ) on the frequency response for the FE-loop structure. It can be seen that the gain at the resonant frequency is degraded but the resonant frequency remains at its nominal value, . This degradation is illustrated in Fig. 2.20(b) by plotting the impulsive response of the FE-loop for different values of This behaviour is very attractive for radio receiver applications in which the position of the signal band is a hard constraint. However, the loss of gain will directly act on the resolution of a as will be explained in Chapter 4. Note that the FE-loop resonator becomes unstable if . Although this fact appears to be a drawback as compared to LDI-loop resonators, some authors propose to design filters with a small instability with the objective of reducing idle tones in modulators [Schr94]. This is still a matter of discussion. In fact, the authors in [Sing95] reported similar experimental results from two second-order one of them based on LDI-loop resonators and the other one using FEloop resonators. The resonator in Fig. 2.19 can be also realized using a differentiator with the transfer function in (2.59) as illustrated in Fig. 2.21(a), whose transfer function is:

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which for the nominal values: transfer function in (2.71) with

and

results in the

As Fig. 2.21(b) illustrates, the resonator in Fig. 2.21(a) presents similar degradation to the resonator of Fig. 2.19(a) under errors on the scaling coefficients, the only difference being the nominal value of

2.5.2.2 Delay element based resonators Up to now, the resonator structures which have been studied were based on integrators as building blocks. Consider now other implementations made up of delay elements as shown in Fig. 2.22. Fig. 2.22(a) shows one made of two delay elements in a loop, often called a two-delay loop resonator [Long93]. It has the transfer function in (2.71) with Nominally, this structure has its poles in the same position as both the LDI and FE-loop structures. In a practical SI realization, this resonator will result more sensitive than the others to the loop gain errors, as will be shown in the following section. Most of the reported SC resonators have their poles placed at This is a consequence of the transformation. Other attractive choices for the resonator transfer function are shown in Fig. 2.22(b) and (c). Their transfer functions are:


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respectively. Making the scaling coefficient these resonators will have their conjugate poles on the unit circle at radial angles of [Corm97]. In practical realizations of this resonator, the scaling coefficient can be digitally programmed, thus allowing the designer to control the resonant frequency without changing the sampling frequency.

2.5.3 SI Resonators As stated in the introduction of this chapter, the growing interest in in the last years has motivated the development of many different topologies for SI building blocks such as integrators and differentiators. However, very little has been done in the field of [Patt94]. As a consequence, there has not been so much interest in the design of SI resonators – the basic building block of The objective of this section is to describe different ways of realizing these blocks with SI circuits. As was explained in the previous section, the resonator block can be realized through the interconnection of smaller subblocks as delay units and integrators using different alternative structures. For this purpose, different SI implementations of the resonators presented in Section 2.5.2 will be described from the ideal point of view. A comparison among them will be shown based on the analysis of the sensitivity to scaling coefficients.

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2.5.3.1 SI LDI-loop resonators The LDI-loop resonator is represented by the block diagram of Fig. 2.17(a). This structure can be realized using SI circuits by connecting in a single loop two LD SI integrators as shown in Fig. 2.23. Applying the expressions derived in Section 2.3 for such integrators, it can be shown that the finite-difference equations which govern the resonator behaviour are:

where and are the output currents of the first and the second integrators, respectively. Rearranging the above equations and taking the Z-transform, the transfer function for the resonator in Fig. 2.23 results equal to (2.72). Note that an additional current mirror (not shown in Fig. 2.23) is required to implement the inversion of the nominal value of the scaling feedback coefficient This can be simplified with fully-differential circuits by crossing their outputs as will be shown in Chapter 3. The resonator architecture in Fig. 2.17 can be extended to a more general case by replacing the LDIs in Fig. 2.23 with N-phase inverting (or non-inverting) integrators as shown in Fig. 2.24(a). Note that the transfer function in (2.71) is achieved using this structure for any value of a. In the more general case of an N-phase integratorbased resonator, the following finite-difference equations can be found for the


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description of the behaviour of such structure:

For instance, Fig. 2.24(b) shows an SI realization of the structure in Fig. 2.24(a) which is made up of 3-phase inverting integrators. The finite-difference equations that govern the behaviour of this resonator are:

which, after taking the Z-transform, results in the transfer function in (2.72). Note that, if the output current , is provided during clock phase instead of the fol-

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lowing transfer function for the resonator can be derived:

As was mentioned in the previous section, the analysis of the sensitivity of Q and to the errors in the scaling coefficients is often used as a measure to compare different structures of resonator. For this purpose, let us assume that the memory cells in the structure of Fig. 2.23 and Fig. 2.24 have a gain error†6 so that they deviate from their ideal behaviour as

where and are the input and the output current of the memory cell respectively, and is the gain error due to the presence of non-idealities in the SI memory cell. From (2.80) the following finite-difference equation for the LDI results:

The transfer function for the N-phase LDI-loop resonator can be obtained by substituting (2.81) in (2.77). After taking the Z-transform, we obtain:

where and

is the error associated to the scaling coefficient, defined as:

From (2.65) and (2.66) the expressions for Q and

can be derived, yielding:

†6. This gain error may be caused by any non-ideality presented in the memory cell as will be shown in the next chapter.


and their sensitivity to and that we obtain:

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can be obtained from (2.67) and (2.68). Assuming

It is clear that the sensitivity of Q with respect to is much lower than that to as illustrated in Fig. 2.25(a). This is an important conclusion because, in practical cases, current mirrors are more subject to gain errors such as mismatch than memory cell errors. This means that the maximum gain of the resonator (at the resonant frequency) will not be significantly degraded in this structure in the presence of errors in the scaling coefficients. However, memory cells must be carefully designed in order to avoid that their errors do not degrade the resonator gain. However, the resonant frequency is less sensible to than to as Fig. 2.25(b) illustrates. This will be a critical issue in the design of SI bandpass modulators based on LDI-loop resonators.

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All these conclusions have been validated by simulation using a time-domain behavioural simulator for SI circuits†7. As an illustration, Fig. 2.26 shows a timedomain simulation of the 2-phase SI LDI-loop resonator of Fig. 2.23 in the presence of gain errors and Note that memory cell errors cause a degradation of the Qfactor of the poles, which manifests itself as gain loss in the output spectrum of the resonator, as illustrated in Fig. 2.26(a). On the other hand, the effect of is only to shift the resonant frequency as shown in Fig. 2.26(b).

2.5.3.2 SI FE-loop resonators The resonator architecture of Fig. 2.19, based on FE integrators, can be realized through SI circuits as Fig. 2.27 (a) shows. It consists of two FE SI integrators connected in a loop†8. One of these integrators is a lossless non-inverting structure like that shown in Fig. 2.7(b) and the other one is a damped non-inverting structure like that shown in Fig. 2.8. The difference equations which describe the behaviour of this resonator are:

†7. Details related to this simulator and the behavioural models for SI memory cells will be discussed in Chapter 5. †8. As stated in the previous section, this resonator structure can also be realized by combining noninverting differentiators and integrators in a single loop. This can be implemented using the SI differentiator shown in Fig. 2.15(b), by taking only the non-inverting input current as demonstrated in (2.59). However, as the performance of both resonator structures (Fig. 2.19(a) and Fig. 2.21(a)) is similar, we will center on the SI implementation of Fig. 2.19(a) as a case study.


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After the Z-transform, we obtain:

This type of resonator can also be constructed by using N-phase FE SI integrators. Such structures, in addition to realizing the transfer function in (2.71), allow the designer to control the block delay Fig. 2.27(b) shows one which uses 3-phase FE SI integrators. For this resonator the finite difference equations are:

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After taking the Z-transform of (2.89), it is easy to show that the transfer function for this resonator structure is:

and in the case of an N-phase integrator-based FE-loop resonator,

Following the same procedure as in the previous section, Q and giving:

and the sensitivity of these parameters to (2.68). Assuming that yields:

and

can be derived,

can be obtained from (2.67) and

Note that, contrary to LDI-loop resonators, from the above expressions it can be derived that the Q factor has the same sensitivity to both and However, Q is more sensitive to than in the case of LDI-loop resonators as illustrated by comparing Fig. 2.25(a) and Fig. 2.28(a).


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In respect of the resonant frequency, the FE resonator is less sensitive to memory cell errors than the LDI-loop structure. Note that, if does not depend on memory cells errors. On the other hand, the sensitivity of to scaling errors is of the same order as that of LDI-loop structures as illustrated by comparing Fig. 2.25(b) and Fig. 2.28(b). These results have been validated by behavioural simulation of the resonator in Fig. 2.27(a). This is illustrated in Fig. 2.29 by showing the output spectrum of the resonator in the presence of memory cell and scaling errors. Observe that the effect of memory cell errors is similar to the LDI resonator. However, the FE resonator is more severely degraded in the presence of scaling errors as is demonstrated by comparing the output spectra of Fig. 2.26(b) and Fig. 2.29(b).

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2.5.3.3 SI delay-loop resonators The last SI resonator structure presented in this chapter is shown in a conceptual level in Fig. 2.30(a). For the nominal value of the feedback scaling coefficient , the transfer function of this structure is:

As this structure is composed of delay blocks, it can be easily realized through SI circuits using the N-phase delay elements described in Section 2.3.2. As was discussed in that section, the use of 2N memory cells to realize a delay of implies a transmission error equal to with being the gain error of each memory cell. In order to avoid this, delay lines based on parallel connected memory cells were proposed. However, in practical cases, the use of such circuits forces to reduce the circuit time constants considerably since memory cells must memorize their inputs in a shorter time. For this reason, the SI realizations presented in this section for the resonator in Fig. 2.30(a) are based on delay elements realized through series-connected memory cells. As an example, Fig. 2.30(b) shows a 2-phase SI implementation of the resonator structure in Fig. 2.30(a), with a transfer function given by (2.96) with


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In the presence of scaling errors in the memory cells and in the feedback scaling coefficient the transfer function in (2.96) is degraded as:

Following the same procedure as in the previous sections, Q and derived,

can be

and their sensitivities to memory cell and current mirror errors are

Note that the resonant frequency is neither sensitive to nor to In respect of the Q factor, the resonator of Fig. 2.30 presents a similar sensitivity to as the integrator-based resonators. However, the sensitivity of Q with respect to is much larger than that of the LDI resonator. Summarizing, the LDI-loop resonators result advantageous as compared to the other structures because they present the lowest sensitivity of Q with respect to scal ing gain errors. This will result in more efficient filtering in practical applications such as

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2.6 SI quantizers As was described in Chapter 1, a modulator is composed of a filter and a quantizer connected in a loop. In the case of this filter is based on integrators while in the case of it is based on resonators. The SI circuits used to build these blocks were described and classified in the previous sections. This section deals with the SI implementation of the other fundamental block in modulators: the quantizer. All SI modulators reported in literature employed a 1-bit quantizer. In most cases current mode comparators were used to realize this block. In this section we will review the existing structures for such circuits. A current mode comparator is a circuit that detects the sign of the difference between two currents and codifies the outcome of the detection through a digital signal [Rodr98]. Fig. 2.31(a) illustrates this operation. In this figure, represent levels that guarantee correct logic interpretation of the output signal. Current comparators are composed of an input resistor which acts as a sensing device followed by a voltage comparator as Fig. 2.31(b) illustrates. If the dominant part of this sensing device is resistive, they are called resistive current comparators. On the other hand, if the dominant part is capacitive, they are called capacitive current comparators.


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Capacitive-input are faster than resistive-input architectures for applications involving small input currents. For this reason, most current comparators employed in the SI modulators are capacitive current comparators. Fig. 2.32(a) shows the basic structure of this class of comparators [Sala90]. Its operation is as follows. The input current charges or discharges the input parasitic capacitance and forces the input voltage to change. For positive values of the voltage at the inverter input node rises until it hits the upper voltage rail causing the inverter output voltage to go low. For negative values of the current is pulled to ground and the inverter output goes to . Note that in the comparator in Fig. 2.32(a), both the input current and the output voltage are single-ended signals. Fig. 2.32(b) shows the fully differential version of this circuit. Its behaviour is the same as that shown in Fig. 2.32(a) except that the input current is the differential current The differential voltage at the comparator inputs changes according to the direction of the current flows and the output is produced according to the differential input voltage. Both current comparators have been successfully used in SI [Brac94a][Tan96].

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Capacitive and resistive current comparators are complementary structures. The first present faster response times than the latter for small input currents. However, for large input currents resistive-input architectures can be faster than capacitive architectures. This has led to the combination of the advantages of these two basic architectures, namely: large sensitivity and reduced amplification time for low-current levels, and reduced input voltage excursion for large-current levels [Rodr98]. One such structure is shown in Fig. 2.33 [Domi92]. It consists of a capacitive current comparator like that in Fig. 2.32(a), with nonlinear feedback. The operation of this circuit is as follows. When the input current flows into the quantizer, all the current must be sunk by making its gate-source voltage less than the value of its threshold voltage. When the input current flows from the quantizer, all the current must be provided by making its gate-source voltage larger than its threshold voltage. Therefore, the gates of and experience a large potential change when the input current changes direction. Due to the low input impedance, the potential change at the input is small. Transistors and act as a voltage amplifier. This comparator has been implemented in different SI modulators [Tan96]. Another criterion for classifying comparators refers to their operation in the time domain. CT comparators operate in asynchronous manner. On the other hand, DT comparators operate in synchronization with a clock signal. Up to now all comparator structures described here were CT comparators. In practice, when these blocks are employed in SI modulators, they must be followed by a flip-flop (RS or D type) in order to keep the output voltage constant during the phase in which it is reconverted to the analog part of the modulator. The last structure of current comparator, used in SI is shown in Fig. 2.34. It is made up of a regenerative latch [Brac94b] and an RS flip-flop. The


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regenerative latch operates as follows. Since the input switches are PMOS, currents are sampled in the complementary phase developing a small voltage difference through the NMOS switch. When the NMOS switch opens, the current which flows through it cuts off abruptly, and the latch impedance changes from positive to negative (due to the positive feedback). Consequently, depending on the sign of the small difference of stored voltage, the latch output nodes (R and S in Fig. 2.34) will go to the positive or negative rail. A fast comparison is thus obtained with low input current levels.

2.7 Current Mode 1-bit D/A Converters The last building block that will be considered in this chapter is the current-mode Digital-to-Analog Converter (DAC). In an SI modulator, this block is used to convert the digital output back into an analog current signal to be applied as an input to the modulator. As in the case of quantizers, only 1-bit DACs have been used by SI reported in literature. Thus, we will center on this type of DACs. A current mode 1-bit DAC can be implemented by means of a current source controlled by the current mode quantizer output. Fig. 2.35(a) shows one structure commonly used in SI [Craw92a]. If the input voltage †9 is high, the switch transistor turns off and the output current, is equal to with †9. The output voltage of the 1-bit quantizer in the modulator.

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being a scaling coefficient. On the other hand, when the input voltage is low, turns on, resulting in the output current equalling Fig. 2.35(b) shows one variant of the DAC in Fig. 2.35(a) [Brac94a]. As in the earlier structure, the output current is determined by the sign of the quantizer output. However, an additional control signal determines whether the DAC operation is unipolar or bipolar. Finally, the last structure we will describe, used by SI designers, is shown in Fig. 2.35(c) [Tan96]. The differential output current changes the flow direction according to the input voltage sign. In practice, the type of current source is chosen in order to resemble the structure of the memory cell employed in the modulator.


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SUMMARY

This chapter described a family of building blocks for the realization of modulators using SI circuits. The principle of operation of the SI technique, the current memory cell, was explained as well as its application for realizing delay elements. Starting from this cell, three main groups of circuits were described: integrators, differentiators and resonators. All transfer functions performed by SC circuits were demonstrated with SI blocks through the combination of memory cells and using different clock phase diagrams. The main contribution of the chapter dealt with SI resonators. These circuits constitute the fundamental building blocks of SI bandpass modulators. For that reason, different topologies have been presented, some of them consisting of the connection of integrators in a loop, while others are based on delay elements. A comparative study of all of them has been performed based on the sensitivity to errors in their scaling coefficients. The purpose of this study is to determine, in a first approach, which is the most appropriate resonator architecture for SI bandpass modulators. A more detailed description of the mechanisms responsible for SI errors will be given in Chapter 3 and their influence on the performance of bandpass modulators will be detailed in Chapter 4. To finish the chapter, the more usual quantizers and DACs implemented in SI modulator ICs have been reviewed.


Mechanisms of Error in Switched-Current Circuits

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3

Mechanisms of Error in Switched-Current Circuits 3.1

Introduction

In the previous chapter switched-current (SI) building blocks for modulators have been described from an ideal viewpoint. In practice, the behaviour of these blocks deviates from the ideal performance as a consequence of MOS transistor imperfections. Although the main non-idealities which degrade the performance of SI circuits have been identified and described in literature [Toum93][Tan97], very little has still been done in the analysis and modelling of these errors as well as their influence on the performance of building blocks. This is one of the main causes for which state-of-the-art SI [Tan97][Moen97] achieve lower performances than their Switched-Capacitor (SC) counterparts [Mede99]. For the above-mentioned reasons, the analysis of basic block SI non-idealities is treated in this chapter with two well-differentiated objectives: on the one hand, the obtainment of behavioural models that support a fast and precise time-domain simulation; on the other hand, the attainment of approximate equations which, in closedform, express the effect of each non-ideality on the performance of the cell, as a function of itself and other design variables. Those equations will provide the quantitative knowledge on the cell parameters for each SI error. This will allow the designer to control the non-idealities either through the choice of MOS transistor sizes and bias current (sizing) or by means of proper circuit techniques. Special emphasis will be put on signal-dependent errors since they have been demonstrated as one of the main performance limitations in practical circuits such as filtering [Fiez90][Toum93][Hugh96] and Analog-to-Digital Converters (ADC’s) [Moen97][Tan97]. Thus, we will analyse harmonic distortion caused by non-linearities in both single-ended and fully-differential memory cells. Simple closed-form equations will be derived and validated by electrical simulation using HSPICE [Meta88]. In particular, we will describe a new model for the non-linear settling error, which, being simpler than the previously reported, will allow us to extend the analysis to the modulator level.

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The study presented here will be based on second-generation memory cells. As stated in Chapter 2, these memory cells are the most extensively used for the design of SI circuits, particularly in the field of

3.2 Finite output-input conductance ratio error Simple second-generation memory cells like those shown in Fig. 3.1(a) behave as either the input or the output stage of a current mirror depending on the clock phase in which they are operating. During the sampling phase, the drain of the memory transistor is connected to its gate and the input current flows through it. On the hold phase, the connection between the drain and the gate of the memory transistor is split and the cell delivers its output through the load. As a consequence of this dual operation, the drain of the memory transistor will be at different voltages on both clock phases†1. This voltage variation is translated into an error on the memorized drain current basically through two mechanisms [Daub88]. The first is caused by the channel length modulation effect of both the memory transistor and the bias current

†1. In second-generation memory cells the drain node of the memory transistor is the input node of the memory cell during the sampling phase and the output node during the hold phase. In first-generation memory cells the output current is delivered to the output through a current mirror. In such a case, the error is due to the difference between the memory transistor drain voltage and the current mirror out put drain voltage.


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source transistor. The second one is due to the charge which flows through the draingate overlap capacitance into the gate capacitance, thus causing an error on the gate voltage and consequently on the memorized drain current. These two mechanisms of error can be modelled as a finite output conductance connected in parallel with the memory transistor [Daub88][Hugh89]. Thus, when a memory cell is in its hold phase and it delivers its output to another cell (in sampling phase), the drain current memorized by the latter will contain an error caused by the parallel connection of its finite input conductance and the output conductance of the former. This error – often represented through the parameter – is referred to as the finite output-input conductance ratio error [Toum93]. This section is devoted to the analysis of this non-ideality as well as the different circuit strategies to reduce it. 3.2.1 Linear analysis Let us consider the simple second-generation memory cell shown in Fig. 3.1(a). Assuming that the memory switches are ideal and that the amplitude of the input signal, is small as compared to the bias current source the memory cell can be modelled by its small signal equivalent circuit, shown in Fig. 3.1(b). In this circuit, is the gate-source capacitance of the memory transistor M; is the drain-gate overlap capacitance; is the small-signal transconductance of the memory transistor (evaluated at the operating point), given by

and and are respectively the drain-source conductances of the memory transistor and the bias source transistor at the operating point, given by [Tsiv96]:

where and are respectively the channel length modulation parameter for the memory transistor and the bias source transistor, The circuit in Fig. 3.1(b) includes both mechanisms responsible for the error in the memory transistor drain current due to the variation of the drain-source voltage

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between both clock phases. Observe that this circuit can be simplified into that shown in Fig. 3.1(c) where represents the equivalent output conductance of the memory cell given by

Expression (3.3) contains both the static and the dynamic parts of the output conductance. Observe that, while the static one is always present, the dynamic one appears only during the transitions between both clock phases. Let us consider now the connection of two memory cells in series shown in Fig. 3.2(a). For the following analysis it will be assumed that both memory cells are modelled by the equivalent circuit shown in Fig. 3.1(c) and that they reach the stationary state before the end of their sampling phase and thus, can be considered negligible. During clock phase of period memory cell 1 is on the sampling phase and memory cell 2 is on the hold phase. The equivalent circuit is shown in Fig. 3.2(b). Taking into account the above considerations it can be shown that the memory transistor drain current of the memory cell 1 is given by


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During clock phase of period memory cell 1 is on the hold phase and memory cell 2 is on the sampling phase. The equivalent circuit is shown in Fig. 3.2 (c). From this circuit, we obtain that the output current of the memory cell 1 is:

where

and

Substituting (3.6) and (3.7) in (3.5) we obtain

Assuming that

where error.

yields

is defined as the (linear) finite output-input conductance ratio

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Systematic Design of CMOS Switched-Cuirent Bandpass Sigma-Delta Modulators for Digital Communication Chips

3.2.2 Non-linear analysis Provided that small signal conditions apply, expression (3.9) can be used to describe the input-output behaviour of the memory cell under finite output-input conductance ratio error. Unfortunately, practical SI circuits operate at signal amplitudes close to the bias current level in order to maximize the dynamic range. In such cases, the linear model fails to predict the real behaviour of the memory cell. To overcome this problem it will be necessary to employ a large signal model. Let us consider again the memory cell of Fig. 3.1 (a). For the following analysis, it will be assumed that both the memory and the bias transistors can be described by the hand-analysis model of the MOS transistor in the saturation region, i.e,

where and are respectively the drain-source current, the drain-source and the gate-source voltages of the MOS transistor; W and L are respectively the channel width and length; is the carrier mobility in the channel; is the gate oxide capacitance per unit area and is the threshold voltage. The only secondorder effect included is the channel length modulation modelled by [Tsiv87]. From (3.2), (3.3) and (3.10) it can be derived that

where and denotes that is evaluated at the operating point corresponding to the input signal amplitude In practice, that operating point will depend on the input signal amplitude and may change significantly between two periods of the clock signal. To illustrate this non-linear behaviour, we have simulated in HSPICE the memory cell of Fig. 3.1(a) for and when clocked at 1MHz. The input signal was a sinusoidal function of amplitude and frequency Fig. 3.3(a) shows the tran-


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sient evolution of the input current, Fig. 3.3(b) and Fig. 3.3(c) show the evolution of both and , respectively. As a consequence of the operating point variation, their values are modified significantly over the input signal period. Because of its dependence on the input amplitude, the memory cell in Fig. 3.1 (a) behaves as though it had input and output conductances given by [Craw94][Mart99a]

where

and

Let us consider now the connection in series of two memory cells shown in Fig. 3.2(a). During the clock phase of period it can be shown from (3.4),

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(3.13) and (3.14) that the memory transistor drain current of memory cell 1 is given by

where

During the clock phase of period from the equivalent circuit of Fig. 3.2(c) and taking into account the above considerations it can be derived that the output current of memory cell 1 is given by:

and

where From (3.16), (3.17), (3.18) and (3.19) it can be shown that the finite difference equation which describes the operation of the memory cell in the presence of the non-linear output/input conductance ratio error is:


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Note that for and (linear case) the above expression can be simplified into that shown in (3.9). In order to simplify the analysis of (3.20), it will be assumed that the memory cell operates under mild distortion conditions [Will95], i.e, the input signal amplitude is low as compared to the bias current source In such a case, assuming that and performing a Taylor series expansion of (3.20), yields:

has been supposed†2 . In the above expression, for represents the -order non-linear gain error. The most significant coefficients in (3.21) are the second- and the third-order, respectively given by:

where

where represents the overdrive voltage in the operating point. Assuming that the input current is a sinusoidal signal of amplitude the output current will contain harmonics of the input signal frequency The -order harmonic distortion, is defined as the ratio of the output signal amplitude at frequency to the linear output amplitude [Will95]. The Total Harmonic Distortion (THD) is defined as [Will95]:

The most significant harmonic distortion terms are given by:

†2. In the ideal case

and

, respectively

On the other hand, in the regime of mild distortion,

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which are similar to those obtained by the authors in [Mart99a]. Note that, in most practical cases, simplified into:

and hence, the above expressions can be

where To verify the above calculations, a transient simulation of the connection in series of two memory cells was performed using HSPICE. Fig. 3.4(a) represents and as a function of the modulation index In this simulation: and ideal bias current sources of were used (instead of PMOS current sources). In order to illustrate the effect of the finite drain-source conductance, Fig. 3.2(b) compares theoretical with simulated as a function of the memory transistor length, L for W = 5L and A good agreement is obtained between simulation data and the values predicted by (3.25).

3.2.3 Effect of the finite steering switch-on resistance In the previous analysis it was assumed that all switches were ideal. In SI circuits we can differentiate between two types of switches: memory and steering switches. The first ones realize the connection of the input node to the memory transistor gate. They do not carry currents in the steady state, and thus do not contribute to the error


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caused by the finite output-input ratio error. Their main non-ideal effect is that caused by their channel charge injected on the memory transistor gate capacitance during the transition between the sampling phase and the hold phase. This phenomenon will be described in Section 3.3. The second type of switches drive stationary currents in the connection between two memory cells. As they are usually biased in the ohmic region of the MOS transistor, its main non-ideal effect is the finite switchon resistance. This section is devoted to analysing the impact of this error on the performance of SI memory cells. For our analysis, we will consider that the steering switches are NMOS transistors. A similar analysis can be carried out for the case of either PMOS or CMOS switches. Fig. 3.5(a) shows the connection of two memory cells during the clock phase (of period in which the information is transmitted from one cell to another. Note that, during this phase, the steering switches named and are switched off while switch is switched on. As the gate node of is connected to

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the upper supply voltage, this switch is operating in the ohmic region. Assuming that the input signal amplitude is small as compared to the bias current, we can substitute the circuit in Fig. 3.5(a) by its small-signal equivalent circuit. This is shown in Fig. 3.5(b). Note that and have been replaced with open circuits while is modelled by a linear drain-source conductance represented by Solving that circuit for yields:

Assuming that

and

the above expression simplifies into:


where resistance.

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represents the linear error due to the finite steering switch-on

In case that signal amplitudes are large as compared to the bias current, the linear equivalent circuit of Fig. 3.5(b) is not valid. In such a case, the steering switch transistor can be described by the first-order model of the MOS transistor in the ohmic region,

where represents the drain-source current, is the drain-source voltage and is the gate-source voltage of the steering switch transistor. The large-signal switch-on resistance can be derived from (3.30) as

where is the voltage variation around the operating point and stands for the overdrive voltage of The above expression can be expressed as

where stands for the switch-on conductance in the operating point. Taking into account the above considerations, the effect of the non-linear switch-on conductance can be analysed using the equivalent circuit shown in Fig. 3.5(c). To simplify the analysis, we will consider that the remaining transistors can be modelled by their small-signal equivalent circuits. Note that the expression in (3.32) will be different depending on the sign of Thus the source of the steering switch transistor is whether otherwise the source is and hence,

Solving the circuit in Fig. 3.5(c) for

yields the following expression

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which relates

and

where Otherwise, for

results in:

Solving (3.34) and (3.35) for we found that

and performing a Taylor series expansion for

where

Rearranging the above expressions and assuming

it can be shown that:


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Several conclusions can be derived from the above expression. On the one hand, note that the harmonic distortion caused by the non-linear switch-on resistance can be reduced by increasing the switch-on voltage. However, this is not an appropriate technique for low-voltage operation. Instead of that, the switch size, can be made much larger than the memory transistor size, W / L, but this technique increases the intrinsic parasitic capacitances of the switch, thus making the design of the cell difficult or high-speed operation. On the other hand, observe that both harmonic distortion coefficients are proportional to and can thus be reduced by using the same strategies to attenuate this error. Details on these strategies are given in the following section.

3.2.4 Circuit strategies to reduce the finite output-input conductance ratio error The transmission error can be reduced either by increasing the input conductance, or by reducing the output conductance, of the memory cell. In case of a simple memory cell, it can be shown from (3.1) and (3.3) that

where has been assumed for simplicity. Observe that can be reduced either by decreasing or by increasing W / L. However, the lower the bias current source the lower the linear input signal range, and consequently the lower the dynamic range. Besides, as we will see in Section 3.4, the bandwidth of the memory cell will be considerably limited by On the other hand, the use of large size ratio aspects W / L will give large values of the gate-source memory transistor capacitance, thus reducing the memory cell bandwidth as well as an additional †3. For the simple memory cell the input conductance is

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penalty for occupying large silicon area. As a numerical example, for and using typical parameters extracted from a standard CMOS technology: and the expression (3.41) obtains that From the considerations above it seems to be clear that the use of sizing to reduce is not a good solution in practical cases. To overcome this problem, several circuit strategies have been proposed [Toum93] that either increase the input conductance or reduce the output conductance of the memory transistor. Most of them are based on the well-known techniques developed to obtain better performances of current mirrors [Toum90a]. Fig. 3.6 shows different circuit approaches to reduce the output conductance based on the cascoding technique [Abid88]. Fig. 3.6(a) shows a simple cascode


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memory cell. Observe that using this cell, the variation of the drain-source voltage of M is reduced by the voltage gain of the so-called cascode transistor A simple analysis of the small-signal (low-frequency) equivalent circuit of Fig. 3.6(a) during the clock phase obtains that the equivalent output conductance of this cell is given by

where

represents the output-conductance of the simple memory cell and stands for the small-signal voltage gain of This gain is typically about 100 [Toum93], which according to (3.41) and using the same values as in the previous numerical example, allows us to obtain for W / L > 4.2. That is, we can reduce the error by ten times as compared to the simple memory cell using a memory transistor size one hundredth lower. Observe that in the circuit of Fig. 3.6(a), during the clock phase (sampling phase), the drain of is connected to the gate of M, thus making it difficult to keep both transistors in the saturation region. The source follower cascode memory cell of Fig. 3.6(b) [Daub91] copes with this problem by adding a source follower, consisting of transistors and which shifts the drain voltage level of M to keep both M and in saturation. The output conductance of this cell is approximately the same as that of the simple cascode. Although the simple cascode notably diminishes in order to make SI circuits competitive with state-of-the-art switched-capacitor (SC) circuits, an even lower transmission error is required. This can be achieved with the regulated-cascode memory cell shown in Fig. 3.6(c) [Toum90b]. In this cell, the local amplifier formed by transistors and reduces the output conductance of the memory transistor by:

where and cally simple memory cell.

are respectively the voltage gain of and Typigiving a value of 10000 times lower than that of the

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As stated at the beginning of this section, the error can also be reduced by increasing the input conductance of the memory cell. Fig. 3.7 shows several circuit strategies using this method. Thus, Fig. 3.7(a) shows a folded-cascode memory cell [Zele94]. This cell uses the voltage gain of the cascode transistor – which is normally of opposite polarity to the memory transistor – to increase the input conductance by

where stands for the input conductance of the simple memory cell. Note that, as in the case of simple cascode memory cells, the input conductance of the simple memory cell can be increased even more than that obtained with the folded-cascode memory cell by simply adding a loop of two transistors at the input node during the sampling phase. This is achieved with the regulated folded-cascode memory cell shown in Fig. 3.7(b). The analysis of the small signal equivalent circuit of this cell during clock phase reveals that the input conductance is:

Notice that the folded cascode technique allows the same cell to obtain either a very low input impedance or a very high output impedance depending on the node which is used as the input node. For instance, let us assume that the input node of the cell in Fig. 3.7(b) is the drain node of instead of its source. In such a case, the output conductance of the cell (evaluated on clock phase ) is:

In an analogous way, using the source node of as the input node in the cell of Fig. 3.6(c), an input conductance approximately equal to that shown in (3.45) can be obtained. In addition to the cascoding technique, there are other circuit strategies to decrease Most of them are based on the feedback technique [Daub90] to increase


125

126


the input conductance by creating a “virtual earth” at the input node. This principle is used by the so-called opamp active memory cell [Vall89], shown in Fig. 3.7(c). The feedback formed by the opamp on the clock phase increases the input conductance as with A being the gain of the opamp. This memory cell introduces a significant design problem because the opamp makes the memory cell a third-order dynamic system. Thus, the challenge is to design an opamp that remains stable during the sampling phase without significantly reducing the speed of the circuit. This is a difficult problem. Besides, the addition of the opamp notably increases the power consumption of the cell. To cope with the above problem, other memory cells like the grounded-gate active memory cell shown in Fig. 3.7(d) have been reported [Groe89b]. These cells uses a Grounded-Gate voltage Amplifier (GGA) – formed by transistors and – to create a virtual earth at the input node obtaining an input conductance given by

where is the voltage gain of The gain of the GGA can be increased by using a regulated cascoding technique. This is used by the cell in Fig. 3.7(e) [Groe89b] which has an input conductance given by:

The circuit techniques reviewed in this section reduce not only the linear error but also the harmonic distortion caused by the non-linear [Mart99a]. This can be easily derived from (3.27). Note that both and are proportional to the linear output-input conductance ratio error. From a similar analysis to that in Section 3.2.2, it can be shown that both and of an enhanced memory cell are:

where

denotes the gain factor of the amplifier used to reduce


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3.3 Charge injection error As stated previously, SI circuits have two types of switches: steering switches – whose non-ideal behaviour has been analysed in Section 3.2.3 – and memory (or sampling) switches. When the memory switch is closed (sampling mode), the drain of the memory transistor is connected to its gate thus charging the gate-source capacitance to a voltage capable of conducting the input current. When the memory switch is open, the gate of the memory transistor remains isolated and ideally the gatesource voltage is held at the same value as that reached at the end of the sampling phase. In practice, the memory switch is implemented by a MOS transistor. Fig. 3.8(a) shows a memory cell in which the memory switch is implemented by an NMOS transistor, Its gate is connected to the clock phase signal and its drain and source†4 are connected to the drain and gate of the memory transistor, respectively. Clock signal periodically switches between a high voltage, – – normally close or equal to the higher supply voltage – and a low voltage – close or equal to the lower supply voltage. Therefore, switches between the ohmic region for and the cut-off region for Because of the switching, its channel

†4. In Fig. 3.8, we are assuming that and hence, the source of the memory switch corresponds to the gate node of the memory transistor.

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inversion layer is periodically created during the sampling phase destroyed during the hold phase as illustrated in Fig. 3.8(b).

and

During the turn-off transient, the channel mobile charges of flow out of its drain, substrate, and source (Fig. 3.8(c)). Thus, part of this charge is dumped on the memory transistor gate-source capacitance (the source of ). In addition, the fast changing of the gate voltage causes the channel charge to flow through the gate diffusion overlap capacitances into both the source and drain of These two phenomena cause a variation on the memory gate-source voltage, and consequently an error in the memorized drain current. This non-ideal effect is known as a charge injection or clock feedthrough error and is often represented in the SI context by the parameter [Daub90][Toum93]. From its detection, at the early stage of SC circuit development [Staf74][Suar75][Hodg80], there have been many attempts to analyze and model this error [Macq83][Sheu84][Wils85][Shie87][Wegm87] and a large number of circuit strategies have been proposed to attenuate it [Wegm89b][Eich90] [Espe94][Yang90b] [Song93] [Jons93] [Min98] [Nair94] [Mart98a] [Toum90c] [Hugh93c] [Helf98b][Toum91]. This section is devoted to exploring the analysis and modelling of this error and to analyzing its impact on memory cell performance. 3.3.1 Analysis and modelling of the charge injection error The charge injection is a complex physical phenomenon involving the flow of mobile charges in the channel of the memory switch transistor. Thus, a precise study of this mechanism of error requires the solution of the continuity equation that relates the channel carrier density to the current density and the generation and recombination processes. This analysis – which has been numerically solved for the general sample and hold circuit in [Wegm87][Eich90] – lies beyond the objectives of this book. Instead, we will use a more basic model derived from [Wegm87] which in addition to simplifying the analysis, is more appropriate for SI circuits [Toum93][Tan97]. Let us consider again the cell in Fig. 3.8(a). The total channel charge of be approximately described as [Eich90]

where and are the effective width and length of respectively†5; is the gate-source voltage of M and is the threshold voltage of given by

can


In practical cases, [Toum93]

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and the following approximation can be made

Substituting (3.52) in (3.50) results in the channel charge injected in the memory capacitor being

where stands for the fraction of the total channel charge injected into the memory capacitor, typically As stated in the introduction of this section, an additional charge is injected into the memory capacitor through the gate-diffusion overlap capacitance given by

Hence, the total charge injected is the sum of (3.53) and (3.54)

and the error resulting in the memorized gate-source voltage is

where †5. According length overlap.

to

[Tsiv87]

the

effective with

width and

and length are defined as being the lateral channel width and

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The error in the drain current of the memory transistor can be calculated by using the first-order model of the MOS transistor in the saturation region (for ) given in (3.10)

On the other hand,

Substituting the above expression in (3.59) yields:

Thus, the drain current error caused by the clock feedthrough is:

As an illustration, Fig. 3.9 shows an electrical simulation (HSPICE) of the charge injection error for the simple memory cell of Fig. 3.8(a) using an ideal bias current of and a memory transistor of size The following values for the parameter in the model were used: (extrinsic capacitor) and level-47 MOS transistor models which correspond to BSIM3v2 [Meta88]. The simulation was performed by applying an input signal to the cell consisting of a step function and measuring the error on both the gate voltage and the output


131

current during the hold phase. In order to eliminate the output-input conductance ratio error, the cell was connected to a voltage-controlled voltage source whose level was set to the same voltage as that which appeared across the gate-source of the memory transistor. This simulation was repeated for different values of the input step. Fig. 3.9(a) displays as a function for different sizes of and Fig. 3.9(b) represents the current error versus the modulation index. Observe that the error increases with the size of the memory switch. This is well predicted by the theory, thus demonstrating that the simple model described above is sufficient to analyze the charge injection error in SI circuits.

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3.3.2 Impact of the charge injection error on the performance of the memory cell Let us consider the memory cell shown in Fig. 3.8(a). For the following analysis it will be assumed that this cell is ideal except for the charge injection error, i.e, the output conductance will be considered negligible At the end of clock phase of period the memorized drain current is given by

and the memory transistor gate voltage can be expressed as

When turns off, its channel charge causes an error in the gate voltage memorized at the end of clock phase Thus, in the clock phase of period the value of the memory transistor gate voltage will be

The drain-source current and the output currents during the clock phase derived from (3.61) and (3.62), respectively yielding

Substituting (3.56) in (3.67) and performing a Taylor expansion series for yields:

where

can be


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represents the output offset current due to the presence of the charge injection error. The linear gain error is given by

and the terms for represent the non-linear gain errors. The most significant are the second- and the third-order ones given by

Assuming that the input signal is a single tone of amplitude and frequency the output current will contain harmonics. Among them, the most significant are the second- and the third-order ones given by

134


which are similar to those obtained for other authors [Fiez90][Mart99a]. The above expressions can be simplified for practical applications, in which, yielding:

which can be reduced by attenuating the linear error, Comparing the effects of the charge injection on the memory cell performance with those of the finite output conductance given by (3.21), it can be observed that both mechanisms of error cause a linear gain error and harmonic distortion. Note that, in case of the charge injection error, there is an additional effect due to the output offset current. However, this offset decreases when the input signal is copied from one cell to the next one [Toum93]. To demonstrate this, let us consider the connection in series of N cells shown in Fig. 3.10. We will assume for our analysis that these cells are ideal except for the charge injection error and that the non-linear gain errors can be neglected. In such a case we can express the output current of the first memory cell, as


In a similar way, the output of the second memory cell,

135

is

Hence, the output current of the cell N-th can be written as

Taking the Z-transform from (3.78) yields:

On the other hand, we have

Identifying (3.79) and (3.80) we obtain that the transfer function of the memory cell in the presence of the charge injection error can be approximated by

3.3.3 Circuit strategies to reduce the charge injection error The analysis above demonstrates that the charge injection error causes the same degradation in the performance of the memory cell as that due to the finite outputinput conductance ratio error. However, the control and cancellation of the former– either through sizing or by using proper circuit strategies – is more difficult than that of the latter for several causes. On the one hand, the physical mechanisms responsible for are more complex than those for and hence, a more accurate modelling is required. On the other hand, an accurate model for involves more electrical parameters than that for thus making its control through sizing much more difficult. For instance, from (3.56) it seems clear that can be reduced by increasing This, however, results in a reduction of the speed.

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For the above-mentioned reasons, is not completely removed in practice, thus being one of the most limiting factors to achieve high performance SI circuits. To cope with this problem, many compensation techniques have been proposed in literature [Eich90] [Wegm89b] [Espe94] [Yang90b] [Song93] [Jons93] [Min98] [Nair94] [Mart98a][Toum90c][Hugh93c][Helf98b][Toum91]. We can classify them into four main families: dummy switch compensation [Eich90][Wegm87][Espe94]; circuit replication [Yang90b][Song93][Jons93][Min98]; zero-voltage [Nair94] [Mart98a] and algorithmic technique [Toum90c] [Hugh93c] [Helf98b] [Toum91]. 3.3.3.1 Dummy switch compensation technique Fig. 3.11(a) shows a memory cell which uses the dummy switch compensation technique [Eich90][Wegm89b]. This approach adds a half-sized dummy MOS switch, to the simple memory cell. Transistor is usually a minimum-size device, while the real switch transistor is composed of two such devices in parallel. As is controlled by the inverted clock phase, when turns off, turns on, thus collecting the charge injected. Ideally, this technique provides a notable reduction of As an illustration, we simulated (HSPICE), a simple memory cell with dummy switch compensation. The memory switch and the dummy sizes were and W/L = 2/0.8, respectively. A memory transistor of


137

size was used together with an extrinsic gate-source capacitance of 2pF. The remaining parameters are the same as those used for the simulation of Fig. 3.9. As Fig. 3.12 shows, the dummy compensated cell reduces by a factor of two both the signal-independent and the signal-dependent parts of the charge injected as compared to the uncompensated memory cell. In practice, the accuracy of the dummy switch compensation technique critically depends on the timing relationship between the clock phase and the edges, which are difficult to control, and thus complete cancellation is not achievable. The circuit in Fig. 3.11(b) tackles this problem by using an adaptative cancellation of based on the modification of the clock-signal shape [Espe94]. This technique uses the feedthrough-influenced magnitudes as a tuning variable, which can be controlled by a feedback loop (see Fig. 3.11(b)). The operation of this loop is as follows. A reference memory cell with zero input current is used to collect the charge injection error. This error is integrated onto a capacitor, and the voltage at the capacitor used to control – through the tuning variable – the clock signal generator. This technique obtains very good experimental results featuring an error attenuation of 50dB relative to the uncompensated memory cell. However, an additional feedback loop – formed by a reference memory cell and an integrator – is required for each clock phase used by the SI circuit. This may be impractical in SI circuits that use more complicated clock phase schemes.

3.3.3.2 Circuit replication technique Fig. 3.13 shows several memory cells which use the circuit replication technique

138


for cancellation of at the output node†6. Fig. 3.13(a) shows the first memory cell using this approach [Yang90b]. The replica circuit samples the charge injection error. This error is inverted and added to the output signal of the cell. As the replica circuit has no input signal, the net effect is to cancel the signal-independent error, , but not the signal-dependent error. This problem is partially solved by the cell in Fig. 3.13(b) [Song93] by using a cell which has two output branches – formed by transistors and – with different gains and . Assuming that gain is †6. Although the cells shown in this figure are first-generation memory cells, this principle can be applied to second-generation memory cells as well.


139

realized by increasing the channel width, then the channel area, and thus the charge injected onto the gate-source capacitances of and are divided by and respectively. Using this principle, the authors in [Song93] demonstrated that the output current is given by:

Comparing the above expression to that shown in (3.63), it is shown that the cell in Fig. 3.13(b) cancels practically all the charge injection error except for the quadratic term which can be eliminated using fully-differential circuitry. The memory cell in Fig. 3.13(c) eliminates this problem [Jons93]. In this circuit, the output current is the combination of four output branches with different gains. It can be shown that the output current is given by

Thus, the error can be completely cancelled for the following conditions:

However, in practice the cell in Fig. 3.13(c) requires a complicated device matching to obtain accurate current ratios The cell in Fig. 3.13(d) [Min98] simplifies the scheme of the cell in Fig. 3.13(c) by using not only a circuit replication technique, but also double sampling. In the cell of Fig. 3.13(d) the signal-independent error of the NMOS switches can be cancelled at the output by generating the same amount of signal-independent error into the opposite direction of PMOS switches. The signal-dependent error is cancelled by using a replication technique. Hence, the error obtained at the output of this cell is

where and respectively.

are the voltage error caused by PMOS and NMOS switches

140


3.3.3.3 Zero-voltage technique Another efficient circuit strategy for the cancellation of is that used by the cell in Fig. 3.14 [Nair94]. This cell uses the commonly known zero-voltage technique to avoid the signal-dependent charge injection. The operation of this cell can be summarized as follows. During clock phase as a consequence of the feedback formed by the opamp and both the drain and the source of the memory switch transistors remain constant at the value When the switch opens, at the beginning of clock phase the charge injected onto the memory capacitor is largely signal independent. Thus, fully-differential versions [Toum93] of the cell in Fig. 3.14 achieve a large cancellation of as demonstrated in [Mart98a]. An important disadvantage of this technique is that it requires an operational amplifier for its implementation, with the consequent increase of the power dissipation and circuit complexity, contrary to the philosophy of the SI technique.

3.3.3.4 Algorithmic technique – the

memory cell

The technique most extensively used by SI circuits to cancel the charge injection error is based on the algorithmic approach. This circuit strategy consists of sampling the error, inverting it and adding it to the memorized current. The algorithmic nature of this process ensures that the charge injection error is cancelled without the need of matching. Fig. 3.15(a) shows the first memory cell which relies on this principle [Toum90b]. The charge injection error of in clock phase is cancelled with its charge injection error in clock phase The same cancellation occurs in and then again in giving:


141

where represents the error in the -th cell during clock phase This approach has a speed penalty – the sampling time is reduced with the number of clock phases – and a complicated clock phase diagram.

142


A more simple and efficient technique is the so-called proposed in [Hugh93c] which is shown in Fig. 3.15(b). This cell divides the sampling time in two steps. In the first step, during clock phase the input current is memorized with an error by the so-called coarse memory transistor This error is memorized during clock phase with an error Thus the output current is:

Recently, an improved version of the cell in Fig. 3.15(b), shown in Fig. 3.15(c) has been presented [Helf98b]. In this cell the input signal is sampled in parallel by both the coarse and the fine memory transistors, which are NMOS transistors.

the

Observe that the coarse memory has considerably more time to settle than that in It can be shown [Helf98b] that the error obtained at the output of this cell is

where is the current error of an uncompensated memory cell, and and are the transconductances of and respectively. Using a minimum size for the current error at the output of the cell can be reduced by increasing the area of The two-step approach can be generically extended to an -step [Toum91]. As an illustration, Fig. 3.15(d) shows a three-step approach. It can be shown that the error at the output of this cell is

where represents the error at the memory transistor memory cell, the error of the cell is

In general, for an -step

The use of memory cells, especially has been demonstrated in a large number of applications of SI circuits such as filtering [Hugh96] and A/D conversion [Tan97][Moen97]. However, this type of memory cells is not very appropriate for bandpass modulators. This is because the input signal does not remain stationary during the sampling phase since it is located at a quarter of the sampling frequency,


143

and hence causes the fine memory transistor to sample not only the error components from the coarse memory but also the signal change itself. Fig. 3.16 illustrates this by plotting the current error of an memory cell for a sinusoidal input signal of amplitude and different values of when clocked at (stationary state is reached). Observe how the larger the ratio between the input frequency and the sampling frequency, the larger the current error. Also note that the current error varies greatly across the signal period, the largest values being at signal zero-crossing intervals (maximum signal change). This non-linear behaviour will manifest itself as a harmonic distortion at the output signal, which also increases with

3.3.3.5 Fully-differential circuits For the above-mentioned reasons, the circuit strategies described in the previous sections are not suited for SI circuits intended for high–speed applications such as bandpass modulators.

144


Note that the greater part of the charge injection voltage error in Fig. 3.9(a) is due to the offset term, of (3.56). This term can be cancelled by using a fullydifferential memory cell like that shown in Fig. 3.17 at the conceptual level†7 . In this cell, the differential voltage error due to the charge injection can be derived from (3.56):

which is notably reduced as compared to the single-ended case. This is confirmed by electrical simulation with HSPICE. Fig. 3.18(a) shows the voltage error for the fullydifferential memory cell of Fig. 3.17 for different memory switch sizes. Note that the offset term is nulled in Fig. 3.18(a) and that can be notably reduced by using minimum sizes This effect is most significant if a dummy compensation technique is used in combination with fully-differential mem-

†7. An additional Common-Mode Feedback Circuit (CMFB), not shown in this figure, is required. An efficient CMFB circuit will be described in Chapter 6.


145

ory cells as illustrated in Fig. 3.18(b). In addition to reduce the linear error, another consequence of using fully-differential circuits is that even-order harmonics are cancelled. Following a similar analysis to that performed in Section 3.3.2, it can be shown that the output current of the memory cell in Fig. 3.17 under charge injection error can be written as:

where

and

Fully-differential memory cells can be used to cancel, not only to the charge injection error, but also other error mechanisms of SI circuits. For instance, considering that a fully-differential memory cell is ideal except for the finite output-input conductance ratio error, the output current can be derived from (3.21), yielding:

where

Note that of the fully-differential memory cell is the same as that obtained the signal range is twice that of the sinin (3.27) because, although gle-ended memory cell.

146


Summarizing, as demonstrated above for and fully-differential SI memory cells can achieve a higher level of performance than their single-ended counterparts. For that reason, in the rest of this chapter and in the greater part of this book, special emphasis will be placed on this type of memory cells.

3.4 Settling error During the sampling phase the input current which is applied to a memory cell charges (or discharges) the gate-source capacitance of its memory transistor. This transient evolution reaches the steady state when the gate-source voltage is such that the drain current which flows through the memory transistor is equal to the bias current plus the input current. However, if the charging process is not completed during the sampling period, an error voltage is stored into the gate capacitance which causes an error in the memorized drain current. This results in an error in the output current, often referred to as an incomplete settling error. The time required for the charging of the gate-source capacitance is set by the duration of the sampling phase, which is directly related to the period of the clock signal. This fact makes the incomplete settling error one of the major limiting factors in high-speed applications where the increase of the sampling frequency is used to reduce the quantization noise power in the signal band. A similar mechanism of error is found in SC circuits where the incomplete charge transfer constitutes one of the main limiting factors in high-speed ADCs [Mede99]. Besides, as with the SC technique, the electrical parameters responsible for the dynamics of SI circuits are also related to other non-idealities. Hence, circuit techniques employed to reduce the latter may transform the dynamics of the cell. For instance, the use of grounded-gate active memory cells (employed to increase the input conductance) introduces a pair of conjugate complex poles thus resulting in a third-order dynamics system [Hugh93a]. Another problem associated to the incomplete settling error in SI circuits is the strong dependence of the transient response on the input signal amplitude, which results in high levels of harmonic distortion in those circuits intended for high-speed applications. This is a mayor problem in bandpass modulators applied to radio receivers. Several attempts to analyze both the linear and the non-linear settling error in SI


147

circuits have been reported in literature [Toum93] [Craw94] [Hugh93a] [Nain93] [Moen94][Helf98a][Mart98b]. A comparison among them is made in this section. In addition, a new model for the non-linear settling is presented. This model accurately predicts the harmonic distortion of fully-differential memory cells and will allow to extend the analysis of this error to other blocks in the modulator hierarchy as we will see in Chapter 4. 3.4.1 Linear analysis of a simple memory cell Fig. 3.19(a) shows a second-generation simple memory cell. Assuming that the steering switch is ideal and that the sampling switch is modelled through a switch-on resistance, the small signal equivalent circuit during the sampling phase is shown in Fig. 3.19(b). In this figure, is the capacitance resulting from the combination of the drain-source capacitances of both and C is the gate-source capacitance of plus the non-linear extrinsic capacitance, i.e, and represents the sampling switch-on resistance. The overlap parasitic capacitances of has been neglected for the sake of simplicity since their most important effect is the clock feedthrough described in Section 3.3. The circuit in Fig. 3.19(b) is described by the following differential equation:

The transfer function which relates

and

is obtained by performing

148


an S-transform of (3.96), yielding:

which is a second-order lowpass transfer function whose dc gain is poles are located at

and their

where A monotonic (first-order) settling can be achieved by forcing a dominant pole in (3.96). This can be obtained for

For most practical cases the above condition is satisfied. For instance, using typical parameters of a CMOS technology, and assuming a minimum size (2/0.8 for the sampling switch and and , the cell behaves as if it had a singlepole at

Let us suppose that the sampling switch is closed at the instant and that the input signal is kept stationary at the value In such conditions, the transient response of and can be expressed respectively as:

where and


149

stands for the settling error at the instant has been assumed.

with

Let us analyze the effect of the incomplete settling error on the performance of a cell like that shown in Fig. 3.19(a). Assuming that the sampling switch is closed at (see Fig. 3.19 (a)) the transient evolution of and are respectively given by (3.101) and (3.102) with At the beginning of the hold phase, the sampling switch opens and the value of the drain current is given by:

Rearranging the above equation and naming yields:

,

During the hold phase, the drain current is kept constant at the value reached at the end of the sampling phase and the cell delivers the output current, Thus, at the end of hold phase the output current is

and

Hence, the output current that the cell delivers can be determined by substituting (3.105) and (3.106) in (3.104) giving

Taking the Z-transform yields

150


The above transfer function shows that, as a consequence of the incomplete settling, the ideal transfer function of the cell is modified by a gain error as happens to other non-idealities such as the finite output-input conductance ratio error or the charge injection error. Also, a residue of the current memorized in the previous sampling phase is added to the new value of the memorized current. This adds a pole at to the transfer function of the cell. This effect will be very important when the cells are used in a bandpass modulator because it will cause a deviation in the ideal notch frequency as will be discussed in detail in Chapter 4.

3.4.2 Linear analysis of enhanced cells In the previous analysis all transistors of the memory cell were assumed to be ideal except for the incomplete settling error. In practice, as demonstrated in previous sections, the simple memory cell is subject to other non-idealities such as charge injection or finite output-input conductance ratio error. In order to attenuate these errors, several circuit strategies have been described in previous sections. In the case of the charge injection, one of the most efficient techniques is the use of fully-differential circuitry with dummy switches. This does not affect the dynamics of the cell. However, most circuit techniques proposed for reducing the finite output-input conductance ratio error use a feedback loop either to increase the input conductance or to reduce the output conductance. This loop adds parasitic capacitances at the critical nodes of the cell which will obviously modify its dynamics. As an illustration, let us consider the regulated folded-cascode memory cell shown in Fig. 3.7(b) and for the sake of simplicity let us assume ideal bias current sources and switches. Under such conditions, the input feedback loop adds two additional poles and two zeroes to the original first-order system. Using ASAP, an analog symbolic analyser program [Fern92], we have obtained the S-domain transfer function of the cell in the sampling phase

where


151

and

Considering only the effect of the gate-source capacitances and function in (3.109) simplifies into:

where

the transfer

and

In this case, the frequency of the zero and the poles are located at

A monotonic (first-order) settling can be achieved by setting This can be done by ensuring thus reducing the input conductance as well. However, it will result in a high power consumption for high-speed operation. Instead of that, another optimum design criterion for a fast and monotonic settling consists of providing a settling time comparable to that of the first-order response (simple memory cell). The authors in [Flan96] found that this can be achieved for and Fig. 3.20 illustrates this for ns by comparing the optimum monotonic response with both a dominant first-

152


order response

and a dominant second-order response

The simulation in Fig. 3.20 demonstrates that the solution found in [Flan96] provides an optimum monotonic settling comparable with that of a first-order system. However, there are several limitations for the application of this solution in practical cases. On the one hand, it imposes very restrictive conditions to some memory cell design parameters such as and and thereby reduces the number of freedom degrees in the design space in order to reduce other errors such as or which depend on the mentioned parameters. On the other hand, as the operation frequency increases, the time constants should be reduced, and hence, capacitors and should be made as small as possible, thus becoming more sensible to relative variations of their nominal values due to either the fabrication process or the effect of parasitic capacitances of the circuit. As a consequence, large relative variations in the nominal values of the time constants will be obtained, difficult to control in practice, and therefore, resulting in non-monotonic responses. This is illustrated in Fig. 3.21 by showing a Montecarlo simulation of the transient response of a regulated-folded cascode memory cell designed for a monotonic settling in the nominal case. In this simulation, the capacitances of the circuit and were assumed to be random variables with a standard deviation of 10% . It can be observed how, for some cases, a dominantly second-order response is obtained.

†8. In this study it has been assumed that the second and the third poles are complex conjugates and that the zero is well frequency-separated from them, and hence there does not exist a doublet. This is a case of practical interest which occurs normally.


153

3.4.3 Non-linear settling error As stated in the introduction of this section, settling error strongly depends on the input signal amplitude in practical SI circuits. Several efforts have been made in order to analyze the non-linear transient behaviour in simple SI memory cells [Nain93] [Craw94] [Moen94] [Helf98a] [Mart98b]. The major effect of the non-linear settling error on the memory cell is harmonic distortion. The first attempt to analyze this effect was made by the authors in [Craw94]. They proposed an upper bound for the THD generated by both singleended and fully-differential SI memory cells. However, that bound gave much more pessimistic results than both HSPICE simulations and measurements – about 20dB lower than theory. The model proposed by the authors in [Helf98a] accurately predicted HSPICE results. However, the analytical solution that they found is too complicated for extending the model to other SI blocks of a higher hierarchy level such as integrators and resonators. In the first part of this section, we propose an analytical model for the non-linear settling error which agrees with both HSPICE simulations and the model presented in [Helf98a]. However, the model described here is much simpler than that in [Helf98a], thus allowing us to extend this analysis to the modulator level as we will see in Chapter 4.

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In the mentioned works [Craw94][Helf98a], it was assumed that the input signal is constant during the sampling phase, but this assumption does not apply to those cells connected to continuous-time input signals. A possible solution to this problem was found in [Mart98b]. The authors demonstrated that high levels of harmonic distortion can be obtained even for low values of However, the mathematical formulation of the problem in [Mart98b] – based on some simplifications – was intended for the obtainment of the expressions for the harmonic distortion and nothing was said on how the memory cell transfer function is degraded. In the second part of this section, we will analyze the harmonic distortion caused by non-stationary input signals. The results of this analysis demonstrated that both expressions of the harmonic distortion, caused either by non-stationary or stationary input signals, converge in case of high values of It will be shown that a model for the memory cell under these circumstances can be seen as the series connection of a continuous-time non-linear filter, which is responsible for the harmonic distortion of non-stationary input signals, and a discrete-time non-linear filter, which produces the harmonic distortion of stationary-input signals. 3.4.4 Stationary-input signals Fig. 3.22(a) shows a fully-differential version of the memory cell in Fig. 3.19(a). For the analysis that follows, it will be assumed that the condition in (3.99) is satisfied and therefore, the effect of the switch-on resistance can be neglected and the equivalent circuit of Fig. 3.19(b) can be simplified into that shown in Fig. 3.22(b), where and represent the transconductances of and respectively,


155

given by

where Assuming that the input signal is kept stationary during the sampling phase and that the sampling switch gate voltage goes down at the gate-source voltage of and can be calculated by solving the circuit in Fig. 3.22(b) for the initial conditions so that

In a similar manner, the drain-source currents of transistors by

Assuming

where

fully-differential currents, i.e, the above equations can be expressed as:

and

are given

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and At the end of the hold phase, of period will be

the differential output current,

Substituting (3.119) into (3.117) and considering

yields

At this point, in order to evaluate the harmonic distortion caused by the settling error, we need to determine a curve which, with a polynomial form, best fits (3.118) in a given interval. A solution to this problem involves using non-linear regression by applying the method of minimum square error in such a range [Vande84], which normally leads to intractable mathematical expressions. Instead of that, we have combined Taylor series expansion for and numerical fitting for and to obtain the following approximation:

where

of

is

the linear settling and

error, is a fitting parameter.

Fig. 3.23 compares (3.118) with the approximation in (3.121) for different values showing a good agreement. Substituting (3.121) into (3.120), yields:

where


157

Thus the analysis of a fully-differential memory cell with non-linear settling error can be accomplished considering a memory cell with a linear gain error whose input signal is equal to (3.123). Assuming that is a sinusoidal signal of amplitude and frequency the output current will contain harmonics of In fully-differential circuits, the thirdorder harmonic is dominant. In this case, the THD is approximately equal to To obtain from (3.123), we will approximate the output current by its firstorder harmonics, so that

Performing a Fourier series expansion of (3.123) it can be shown that the amplitude of the third-order harmonics is approximately given by

158


and the third-order harmonic distortion of the cell is

where Fig. 3.24 compares the theoretical model with HSPICE referring to the example given in [Craw94] and [Helf98a]. In that example, C = 22.1pF, and In Fig. 3.24, is displayed against Observe that the data obtained with the new model are quite similar to that achieved with the model proposed by the authors in [Helf98a]. However, the expression in (3.126) is much simpler than that reported in [Helf98a] and hence, it is suitable for analyzing the harmonic distortion in other blocks in the modulator hierarchy such as integrators or resonators as we will see in Chapter 4. 3.4.5 Non-stationary input signals In the previous analysis it has been assumed that the input signal remains constant during the sampling phase. This assumption does apply in the following cases: (a) The input signal is supplied by another cell. (b) The memory cell follows an S/H circuit. (c) The ratio between the input signal frequency and the sampling frequency is small (less than one tenth).


159

Let us consider a memory cell connected to a continuous-time sinusoidal signal of amplitude and frequency Fig. 3.25 shows the transient evolution of the drain current. Note that the amplitude variation during a sampling interval is

Thus, the amplitude of the input signal can change up to during the sampling phase. In this case, the error caused by the incomplete settling of the signal cannot be solved by analyzing the transient response of the memory cell to an input step, since, as we will demonstrate here, an additional error appears due to the variation of the input signal during the sampling time. For a better understanding of this phenomenon, we will consider first the linear analysis of a memory cell with a nonstationary input signal. For the sake of simplicity, we will assume a continuous-time sinusoidal signal. In this case, and assuming that the condition in (3.99) is satisfied, equation (3.96) is transformed into:

†9. This is the case of a memory cell connected at the input node of a bandpass

modulator.

160


Solving the above equation for the initial condition

yields:

where

The drain current can be obtained as:

where Following the same steps as in Section 3.4.1, it can be shown that the output current of a memory cell in the presence of a non-stationary sinusoidal input signal is:

and

where Note that for

and

and hence, the expression (3.132) transforms into:


Besides, for stationary input signals, simplifies into that shown in (3.107).

161

and the above equation

An important conclusion derived from (3.132) is that, even for a negligible linear settling error the performance of a memory cell with a continuous-time sinusoidal input signal is degraded as:

which, depending on the ratio between the input signal frequency and the sampling frequency, will deviate more or less from the ideal behaviour of a memory cell. Taking into account that expressed as:

the expression (3.135) can be

which can be rewritten as:

Hence, if the settling error is negligible, the memory cell reaches a sinusoidal stationary state, with a transfer function of the form

Note that the above expression can be seen as the cascade of two transfer functions as illustrated in Fig. 3.26(a): one of the continuous-time (CT) type, whose transfer function is:

162


and the other one of the discrete-time type, which is the transfer function of the memory cell with a sampled-and-held input signal, which, in the more general case (assuming that there are other errors), will be represented by Note that, in the ideal case, The equivalent circuit is shown in Fig. 3.26(b). Observe that the current which flows through the capacitor, C, given by

will cause a transmission error,

whose module

depends on the ratio between the input signal frequency and the time constant of the memory cell,


The

163

above

analysis assumed a negligible settling error, that is, However, and hence, are not null. Therefore, the memory cell is degraded by If we consider that the settling error cannot be nulled, then will be given by (3.108). In this case, the drain current of the memory transistor in Fig. 3.26(b) will evolve in time during the sampling phase according to (3.103) from its previous memorized value to the sinusoidal stationary state input current, but, as a consequence of the settling error, that stationary state will not be reached, and hence, there will be an accumulation of two errors: and The impact of on the memory cell performance has been analyzed in previous sections. In this section we will analyze which are the main effects of and we will compare its influence on the memory cell with that caused by

3.4.5.1 Phase delay and uncertainty of the sampled current caused by non-stationary input signals The presence of a non-stationary input current causes two main effects on the memory cell performance. One of them is an uncertainty of the sampled current and the other one is an extra phase delay between the input signal and the memorized drain current. Both of them depend on the input amplitude variation during the sampling phase, that is, the ratio between the input signal frequency and the sampling frequency. These effects are illustrated in Fig. 3.27. Thus, Fig. 3.27(a) shows the electrical simulation (HSPICE) of a fully-differential current memory cell like that

164


shown in Fig. 3.22(a) with and The differential gate-source voltage is represented as a function of the differential input signal current for three values of with Note that the phase delay increases with the sampling frequency as a consequence of the increment of i.e, This effect is predicted by the theoretical model in (3.129) as Fig. 3.27(b) illustrates. Observe that the ellipses in Fig. 3.27 become wider as increases. This effect appears because is not an exact submultiple of – which is common in practice. Hence, since the number of sampling periods contained in an input period is not an integer, the sampled currents will vary from one input period to the next one. This phenomenon can be modelled as an uncertainty of the sampling instant, or a clock jitter, which will be described at the end of the chapter. Fig. 3.28 illustrates the effect of changing Note that for the curve vs. is wider than that corresponding to thus showing the effect of a non-stationary input signal as compared to a quasi-stationary input signal. In the case of sampled-and-held input signals, the above phenomena appears as the settling error is greatly increased. This is illustrated in Fig. 3.29 for a fully-differential memory cell with and Note that the cell starts to behave as if it had a non-stationary input signal when the settling error is large that is, for (discrete-time approaches to continuous-time), the expression in (3.108) simplifies into:


165

which is identical to that shown in (3.138). 3.4.5.2 Harmonic distortion due to non-stationary input signals Another consequence of non-stationary input signals is the increase of the harmonic distortion as compared to the stationary input signal case. Let us analyze a fully-differential memory cell like that shown in Fig. 3.22(a). Fig. 3.30(a) compares two simulated (HSPICE) output spectra corresponding to both a stationary input signal (provided by an S/H circuit) and a non-stationary input signal. It is clear that the latter presents much more harmonic distortion than the former This is also illustrated in Fig. 3.30(b) by plotting as a function of the input signal frequency in both cases, for and Observe that, in this case, and the linear settling error is negligible. However, the harmonic distortion due to the presence of non-stationary input signals is significantly higher than that using an S/H at the input of the cell [Mart98b]. Let us analyze this circumstance. Replacing with in (3.132), the output current of a fully-differential memory cell can approximated by

166

Systematic Design of CMOS Switched-Currenl Bandpass Sigma-Delta Modulators for Digital Communication Chips

where

is given by (3.118) and

This model has been validated by HSPICE. Fig. 3.31 represents as a funcIt can be seen that both electrical simulation and for different values of tion of the model in (3.143) present a close agreement. To obtain a closed-form expression for the harmonic distortion due to non-stationary signals we have to make two simplifications in (3.143). First, the function in (3.144) is approximated by its second-order Taylor series expansion for yielding


Secondly,

167

is substituted by (3.121).

Making the above simplifications and following the same steps as for the stationary input signal case, it can be shown that the third-order harmonic distortion of the memory cell for non-stationary input signals is given by:

which agrees with the approximation found in [Mart98b]. Although the mathematical background of the above analysis is not rigorous, it helps to get a better understanding of the non-linear behaviour of the cell using a very similar model to the linear case, except for In order to validate our approach we have compared the results obtained with (3.146) to simulation. Fig. 3.32(a) represents as a function of for and and different values of the sampling frequency. Observe that even for small values of the settling error there is a high level of harmonic distortion. This is also observed in Fig. 3.32(b) by displaying as a function of for

† l0. A more rigorous analysis is shown in Appendix A. It uses the Volterra series expansion method [Sche80] and yields results identical to those shown in (3.146), if

168


and different values of the input signal frequencies. Note that, in this figure, theoretical predictions deviate from simulations for low values of i.e, for high values of for which, according to the Volterra series expansion method, the prediction in (3.146) is not valid. Note that the harmonic distortion caused by given by (3.126), approaches that in (3.146), when Hence, taking the limit in (3.126), results in:

which, assuming that the fitting parameter

results in the expression given in (3.146) if is re-defined as

Summarizing, the effects caused by non-stationary input signals are equivalent to those caused by assuming sampled-and-held signals, when that is, when the discrete-time approaches the continuous-time.


169

3.5 Mismatch error Integrated circuits are subject to random variations of their physical quantities. These deviations are caused by the fabrication process and can be classified into two main categories: global and local variations. The former are related to the total variation in the value of a parameter over a wafer. The latter reflects the difference in a quantity of adjacent devices. This will cause random differences between identically designed devices, which is generically known as mismatch error [Shyu82] [Shyu84] [Laks86][Pelg89]. There are basically four mechanisms responsible for mismatch errors in MOS transistors [Shyu84]: edge effects on the channel length and width; variations in the effective channel mobility of the carriers over the channel; fluctuations of the gate oxide thickness and randomly distributed surface-stage charge density over the channel. The first three ones cause a deviation in the nominal value of the large signal transconductance, and because of the two last ones, the threshold voltage deviates from its nominal value as As a consequence of these variations, both parameters and can be modelled as random processes with a mean value, and a standard deviation, respectively [Shyu82]. These deviations in and will cause a random error in the nominal value of the drain current. Considering that MOS transistors are operating in the saturation region and that their DC characteristics can be modelled by (3.10), the nominal value and the relative variance of the drain current are given by [Laks86]†11

where and

stands for the correlation coefficient between the mismatches in and represents the standard deviation of The authors in [Laks86][Pelg89]

† 11 .Though random deviations in the fabrication process also cause a random error on its effect on the drain current error, and hence, on the performance of SI circuits is equal to that of For this reason, and to simplify the analysis, we will assume without loss of generality.

170


demonstrated experimentally that

and that

and

can be modelled as

where and are technology process related constants. From (3.149), (3.150) and (3.151), it can be derived that

where

Mismatch errors constitute one of the limiting factors of first-generation memory cells like those shown in Fig. 2.2(a). Ideally, the drain current of both the input and the output transistors have the same value. However, as a consequence of mismatches in and there will be an error at the output current. Second-generation memory cells eliminate this problem because the same transistor is used to implement both the sink and source currents, and hence, mismatch error does not appear. However, general SI circuits require scaling coefficients which are implemented by current mirrors thus being subject to mismatches. This section is devoted to analyzing the impact of mismatching on the performance of memory cells. Their effects on scaling stages are examined as well as their impact on fullydifferential memory cells.

3.5.1 Effect of mismatch error on the gain stage of second-generation memory cells Fig. 3.33(a) shows a second-generation memory cell with an output stage of gain


equal to To simplify our analysis we will assume for can be found in Appendix B.

171

The complete analysis

Under the conditions above, the drain current of transistors respectively given by

and

are

where

with and being the nominal values of the threshold voltage and the large-signal transconductance.†12 During clock phase

of period

is diode connected and its

† 12. In the following, the following notation will be used for the sake of simplicity:

and

172


drain current is

On clock phase transistor holds the current memorized in the previous phase and the cell delivers its output current, given by:

Substituting (3.155) and (3.156) into (3.157) and (3.158) and solving for can be shown that the output current of the cell can be written as

where

and

has been assumed.

Performing a Taylor series expansion of (3.159),

can be approximated by

where and are the output offset current, the linear gain and the -order non-linear gain error caused by the mismatches,

it


173

Observe that only contributes to the offset and the linear gain error but its effect on the non-linear behaviour is negligible. Assuming that the input signal is a single tone of amplitude and frequency the output current of the memory cell in Fig. 3.33(a) will contain harmonics of the input signal, the more significant being the second-order and the third-order ones, respectively given by:

where From the above analysis, it is easy to show that for the fully-differential memory cell shown in Fig. 3.33(b), even order terms in (3.160) are cancelled and the output current of the cell is given by

Note that both the linear gain error and the third-order gain error are random variables with a zero mean. Their standard deviations can be calculated from (3.162) and (3.164), giving:

174


Mismatch errors cannot be completely cancelled because they are inherent to the fabrication process. However, as demonstrated in (3.152), these errors can be partially attenuated by increasing the transistor size, at the price of reducing the speed of the circuit. An alternative strategy for reducing this degradation can be found in the layout synthesis process. As will be described in more detail in Chapter 6, there are a number of layout strategies to make critical transistors (in a current mirror or a differential pair) as matched as possible [Tsiv96]. 3.5.2 Effect of mismatch error on fully-differential second-generation memory cells Let us consider the fully-differential memory cell shown in Fig. 3.34. For the following analysis it will be assumed that memory transistors are ideal except for mismatch error. Thus, during clock phase of period the drain currents of both transistors and are

where and are those shown in (3.155) and (3.156), respectively. During clock phase of period memory transistors hold their drain currents and the


175

differential output current is

From (3.170), (3.171) and (3.172) yield:

where

Observe that, though the cell is fully-differential, even order powers of the input signal appear as a consequence of mismatched and This is a similar problem to that found in balanced differential pairs, where residual even-order distortion coefficients appear as a consequence of device mismatches [Will95]. This mismatch can be modelled as an input offset signal, which can be compensated by using an additional circuit which extracts that offset from the memory cell, thus annulling its effect. The above results have been validated by HSPICE. Fig. 3.35 represents the current error, as a function of the modulation index for and different values of

176


Simulation was made by performing a dc analysis of the cell in Fig. 3.34 with memory switches open (hold mode). A differential voltage was applied between memory transistor gates and the output current of each branch was collected by a voltage-controlled voltage source. The level of this source was set to the same voltage as that which appears across the gate-source voltage of each branch. As Fig. 3.35 illustrates, the current error is dominated by even-order terms, as confirmed by theory. The harmonic distortion, also dominated by the second-order term, is approximately given by:

which is four times smaller than that caused by mismatch errors in gain stages, given by (3.165). As an illustration, Fig. 3.36 represents values of

and

as a function of

for different

Note that high levels of harmonic distortion

can be obtained for low-voltage operation and

This can be a hard limiting factor in modern standard technolo-

gies, which operate at low-voltage supplies ing the mismatch.

and are not optimized for reduc-


177

3.6 Electrical noise Integrated-circuit devices are subject to small current and voltage fluctuations that are generated within themselves. These fluctuations are signals of random nature which are commonly known as electrical noise [Gray87a]. This term is also often used to describe the interferences on the sensitive analog signals caused by the highspeed switching signals coming from the digital circuitry. This phenomenon, often named switching noise or simply digital noise, can be reduced by the use of proper layout as we will see in Chapter 6. Electrical noise, however, cannot be eliminated and constitutes a lower limit to the accuracy of analog signals. The electrical noise of a MOS transistor can be modelled as shown in Fig. 3.37(a). A noisy current source, is connected in parallel with a noiseless

178


transistor so that the total drain current can be expressed as [Tsiv87]

As is a random signal, its instantaneous value cannot be known. Instead, can be described as a random process of zero mean and a mean-square value, defined in a bandwidth as

where stands for the Power Spectral Density (PSD) of . As we will see below, in SI circuits it is more convenient to use the equivalent input voltage noise model shown in Fig. 3.37(b). A noisy voltage source is connected in series with the gate of a noiseless transistor. Hence, the total gate-source voltage is given by

where is a random process of zero mean and square mean value can be calculated by integrating its PSD, in a bandwidth

Both current and voltage models are related by

which

as

There are basically two physical mechanisms which originate electrical noise in a MOS transistor: thermal noise and nicker noise. Thermal noise is caused by the random thermal motion of carriers in the channel. This noise increases with the temperature but is independent of frequency. For a MOS transistor in the saturation region, the PSD of the thermal noise current is


179

Flicker noise decreases with frequency as which is why this noise is also called noise. The exact mechanisms responsible for this noise are not known. Some authors attribute it to the presence of “traps” at the oxide-silicon interface, which can randomly exchange carriers with the channel and cause random fluctuations in its charge density. Other authors attribute this noise to mobility fluctuations [Tsiv87]. The PSD of the flicker noise current is:

where is a process dependent parameter, and W and L are the width and the length of the transistor respectively. As the thermal and flicker noise are not correlated, the total PSD of the noise current for a MOS transistor is

3.6.1 Noise analysis of a memory cell Fig. 3.38(a) shows a simple second-generation memory cell and its noise sources. For the following analysis, ideal steering switches have been considered and the sampling switch is a NMOS transistor, Note that the noise source associated to the latter only appears during the sampling phase. On the hold phase, as the inver-

180


sion layer of is eliminated, their associated noise sources are nullified. The other noise currents are those associated to the memory transistor, and the bias current source transistor, labelled and respectively. The equivalent noise current at the output of the cell can be derived by determining the equivalent noise voltage at the gate of and multiplying its PSD by where stands for the small-signal transconductance of at the operating point. To do this, the equivalent PSD of each noise source at the gate of is derived by computing the transfer function from said noise source to the gate of Assuming that they are not correlated they can be added to obtain the PSD of However, as the memory cell is a discrete-time circuit, the transfer function from each noise source to the gate of will differ from one clock phase to the other. Hence, the output equivalent noise is found by analyzing the output noise for each clock phase and adding them - assuming they are not correlated - to obtain the total output noise of the cell. In the following analysis it will be assumed that flicker noise sources are removed as a consequence of the so-called autozero effect [Toum93]. To understand this effect, let us analyze the cell of Fig. 3.38(a) assuming that only flicker noise sources are presented. Let be the equivalent output current of the cell. At the end of the sampling phase, of period the drain current of is:

At the end of the hold phase, the output current will be

As

is a low-frequency noise source,

From (3.187) and (3.188) it is obtained that the flicker noise is nearly cancelled by the sampling process. For this reason, only thermal noise will be considered in the following analysis.


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3.6.1.1 Noise of the cell on the sampling phase Fig. 3.38(b) shows the equivalent circuit of the cell during the sampling phase. During this phase, is operating in the ohmic region and is modelled by an onresistance in series with a noise voltage source, whose PSD is

In the circuit of Fig. 3.38(b) stands for the equivalent noise current resulting from the combination of noise currents from and Assuming they are not correlated,

Analyzing the circuit of Fig. 3.38(b), it can be shown that the PSD of the equivalent noise voltage at the gate of is

where Note that in practice, and hence, the contribution of to the output noise of the cell can be neglected and the PSD of the equivalent noise current at the output of the cell is approximately given by:

Observe that stands for the equivalent noise current during a given sampling time interval. In general we will refer to as the equivalent noise current at the output of the cell in any sampling period. That is,

where

is the gating function defined as

182


with being the duration of the sampling phase. The PSD of obtained by applying the Fourier transform of (3.193) giving

where the symbol represents the convolution product operator and the PSD of given by

where

From (3.195) and (3.196) yields

Substituting (3.192) in the above equation gives

Note that in general, for other types of memory cells,

can be

is


183

where Hg(f) represents the transfer function from the equivalent current source to the gate of the memory transistor. As an illustration, Table 3.1 shows for several memory cells described in Section 3.2.4. Observe how the contribution to the noise of the memory cell of cascode transistors is attenuated by the voltage gain of the cascode stage in each case.

3.6.1.2 Noise of the cell on the hold phase Fig. 3.38(c) shows the equivalent circuit of the memory cell on the hold phase. During this clock phase, a sample of the memorized drain current and hence, of the equivalent noise current stored in the previous clock phase is taken. Thus, the expression of the equivalent noise current during any hold phase can be expressed as the convolution product of and the gating function

184


where stands for the duration of the hold phase. Taking the Fourier transform of (3.201) yields

Assuming that and PSD of the cell can be written as

are not correlated, the total output current noise

3.6.1.3 Equivalent noise bandwidth The calculation of can be simplified by using the concept of equivalent noise bandwidth. Let us consider the case in which is a narrow-band noise resulting from the filtering of through a filter as illustrated in Fig. 3.39(a). The total power of is computed as

The equivalent noisebandwidth, is defined as the equivalent bandwidth of the noise, calculated so that it contains the same power of the represented noise but Observe from Fig. 3.39(a) that the total power of with constant spectral density the noise current can be written as


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Thanks to the concept of the particular form of can be obviated in the following calculations. In the case of the memory cell of Fig. 3.38(a), Returning to the expression in (3.203), we can distinguish between two different cases:

In this case, no aliasing occurs as illustrated in Fig. 3.39(b), and the summation in (3.203) is computed only for giving

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In this case the noise components at frequencies above are aliased, thus increasing the noise power in the Nyquist bandwidth. As can be seen in Fig. 3.39(c), is the number of bands that are overlapped in the interval In such a case (3.203) can be written as

an expression which, when

, can be approximated by:

From (3.206) and (3.208) we obtain that the total output current of a memory cell is given by

As an illustration of this, Fig. 3.40 compares HSPICE simulations and theoretical predictions of for a simple memory cell with an ideal switch and and To evaluate the sampled noise of the cell, a transient analysis is necessary. Unfortunately, HSPICE does not include noise sources in the transient analysis. To solve this deficiency, an unsampled (white) noise of PSD equal to was generated externally and included into the HSPICE simulation through the use of the DATA command [Meta88]. The cell was clocked at and the PSD of the gate-source voltage was generated by collecting five points per period (50MHz).


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3.7 Maximum signal range – Class AB memory cells One practical limitation which has not been mentioned in previous sections is that, in second-generation memory cells, the signal current must always be less than the bias current, Consequently, if a large signal swing is required, a large must be supplied, thus increasing the power consumption. This problem can be solved by using a class AB memory cell like that shown in Fig. 3.41 [Batt91]. This cell uses both NMOS in Fig. 3.41) and PMOS in Fig. 3.41) as memory transistors instead of only one of them as in the case of the second-generation (class A) memory cell. As a consequence of the class AB operation, the input current, can be larger than as demonstrated in the following analysis. Let us assume that all transistors in Fig. 3.41 can be modelled by (3.10), with and that PMOS and NMOS transistors are matched, i.e, they have the same values of and In such a case, during the clock phase of period (sampling phase), the following set of equations can be derived:

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Solving the above equations for

where

and

yields:

has been assumed.

During clock phase of period drain currents memorized at the end of

Note that, when current be satisfied [Batt91].

or

transistors and hold their and the output current is given by:

one of the memory transistors takes all the input and the operation of the cell will still


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The errors that limit the performance of the class AB memory cell are basically the same as those affecting the second-generation class A memory cell, which were discussed in previous sections. As a consequence, circuit and sizing strategies used for the latter can be applied to the cell of Fig. 3.41. In the particular case of the charge injection error, a more efficient cancellation can be achieved in the class AB memory cell if complementary memory switches are used, that is, PMOS at the gate of and NMOS at the gate of [Batt93]. However, to obtain a successful cancellation of the error, PMOS and NMOS transistors of the cell have to be matched, which is difficult to achieve in practical circuits. The obvious advantage of the class AB memory cell is that it requires less power to obtain the same signal range as in the class A memory cell. However, the absence of a large bias current in the class AB memory cell results in the transconductance of the memory transistors being more sensitive to input current variations than in the class A cells [Mach94]. As consequence of the strong dependence of the transconductance on the input current, high levels of harmonic distortion are generated in the class AB cells. Besides, mismatches in of NMOS and PMOS current mirrors also contribute to the harmonic distortion – contrary to the case of the class A memory cell [Bruu99]. The above limitations have motivated that, except for a few cases [Nedv95] [Tan96], most SI do not use the class AB memory cell. However, in the last two years different techniques have been proposed to improve the performance of these cells [Wora99][Wora00]. Although the use of these techniques has not still been sufficiently demonstrated in practical circuits, they take the advantages of technology scaling and promise to surpass the performance of the SC technique during the next decade [Hugh00]. Therefore, they should be taken into account in future implementations of SI

3.8 Other mechanisms of error In addition to the basic mechanisms of error described in the previous sections, there are other non-idealities which can degrade the operation of SI circuits. Their impact on the performance of SI building blocks is less than that caused by other errors However, practical circuits can be severely degraded if the mechanisms responsible for them are not properly cancelled. For this purpose, this section will give a short description of said non-idealities as well as some possible ways to eliminate them.

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3.8.1 Junction leakage current error The MOS transistor has parasitic pn junctions formed by the drain or source diffusions and the substrate As the substrate is connected to the most negative supply voltage, these junctions are reversed biased. Fig. 3.42(a) shows a memory cell with their associated parasitic junctions. Among them, the most critical is the one formed by the source of the memory switch transistor, and the substrate. At the end of the sampling phase of clock period opens and the reverse bias or leakage current, , discharges the stored voltage on the gate capacitance, causing a voltage error [Wegm90a][Daub91]. The equivalent circuit is shown in Fig. 3.42(b). Solving this circuit for the initial condition yields:

At the end of hold phase given by

of clock period

with

the gate voltage will be

Thus, an additional voltage error appears due to the leakage current


191

For typical values of leakage currents and practical sampling times, this error can be considered negligible. To illustrate this numerically, for a typical minimum size switch, and for the voltage error caused by the leakage current is , much smaller than, for instance, in typical charge injection errors, which are in the milivolt range (see Fig. 3.9(a)).

3.8.2 Current glitches As stated in Chapter 2, basic SI circuits can be classified into two families: firstgeneration memory cells (or current track-and-hold) and second-generation memory cells (or current mirrors). The former use only memory switches while the latter require two types of switches: memory switches for sampling currents and steering switches for driving them. Non-overlapping clock phases are usually employed to control memory switches in first generation SI circuits as happens with most SC circuits. This does not cause any problem because the cell remains in a static state when all switches are open, thus retaining (ideally) the voltages and currents as they†13 were just before opening. This is not the case of second-generation SI circuits. Let us consider the connection in series of two memory cells shown in Fig. 3.43. If non-overlapping clock phases are used, the output node of these cells is left open-circuited during the nonoverlapping period of the clock. Therefore, the output node (drain node of the memory transistor) will quickly go to the supply voltages. This potential change will introduce an error via the drain-gate overlap capacitance. Also, those voltage variations are coupled onto the output current through the drain-source capacitance, thus generating transient current spikes – also named glitches [Sinn94][Quei94]. To minimize this problem several authors have proposed a four clock phase diagram like that shown in Fig. 3.43(a) [Tan97][Sinn94][Quei94]. The basic idea is to avoid the existence of high impedance output nodes. For this purpose, non-overlapping clock phases are used for memory switches while overlapping phases control the steering switches. Observe that sampling and steering switches corresponding to

† 13. The same happens with the output stage of a second-generation integrator. See Chapter 2.

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the same clock phase are switched on approximately at the same time instant. However, during the switch-off transient, the sampling phase is opened just before the steering switch. This avoids sampling an erroneous value of the input current. Even using a four clock phase scheme, high impedance nodes appear in secondgeneration SI circuits. Let us consider the output stage of the memory cell 2 in Fig. 3.43(b). During clock phase the output is left open-circuited, and hence, this node will change strongly to the limits of voltage supplies. To overcome this problem the output node should be connected to a low-impedance node during this clock phase [Tan97] as illustrated in Fig. 3.43(b). This will be discussed in more detail in Chapter 6. 3.8.3 Effect of clock signal: clock jitter and uncertainty on the sampling instant 3.8.3.1 Clock jitter In practice, the period of the clock signal presents random variations in its nominal value. These variations are due to time uncertainties in which the switch-on transitions occur. This phenomenon – known as clock jitter – has already been studied in SC circuits [Taka91] as well as its impact on the performance of modulators [Mede99][Tao99b]. In SI circuits, clock jitter has two main effects. One is a random error in the stored gate-source voltage which will result in an extra noise added at the output cur-


193

rent of the cell. This error can be estimated as follows. Let us suppose a sinusoidal input current of amplitude and frequency which is sampled at with being the error in the sampling time caused by the clock jitter. The error on the drain current can be written as

Assuming that is a random variable with a Gaussian distribution of standard deviation and zero mean, the power spectral density of (3.216) is given by

with

being the sampling frequency.

3.8.3.2 Uncertainty on the sampling instant Another consequence of clock signal imperfections on SI circuits is a signaldependent error [Jons98a][Mart98b]. Let us consider the simple memory cell of Fig. 3.44. The sampling instant, is given by:

where signal, and

represents the ideal sampling instant , is the fall-time of the clock and are respectively the high and low voltages of the clock signal, is the switch-off voltage, which can be written as:

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Systematic Design of CMOS Switched-Currert Bandpass Sigma-Delta Modulators for Digital Communication Chips

where stands for the gate-source voltage of the memory transistor, M. As depends on the input current, any uncertainty on the sampling instant, will cause a signal-dependent error, thus producing harmonic distortion. Let us define applied, then

as the uncertainty for zero input. If an input current is and the corresponding current error will be given by:

where represents the current error for zero input. Note that, if then Therefore, in fully-differential memory cells, the error caused at each branch will be:

Since

the error can be cancelled to the first order, thus reducing the THD up to levels of –l00dB for as the authors in [Jons98a] demonstrated. These values of THD are much lower than those caused by other SI errors under similar conditions, like, for instance, the errors caused by non-stationary input currents.


195

3.9 Design considerations for SI memory cells In previous sections, different closed-form expressions have been derived for the linear gain error, offset and harmonic distortion caused by SI errors. A summary of the most significant results is shown in Table 3.2. The purpose of those expressions is to provide the necessary knowledge to design SI circuits for a given set of specifications. Hence, depending on these specifications, the performance degradation caused by a given error will be more important than that of the others. The purpose of this section is to compare, by mean of by-hand-analysis expressions, the performance degradation caused by each error and to give some design considerations. Although the discussion presented here is based on the simple memory cell like the one shown in Fig. 3.1 (a), the same analysis can be derived for a more sophisticated cell. However, the simplest version of the cell is preferred so that circuit complications will not detract from fundamental issues.

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Using the expressions shown in Table 3.2, Fig. 3.45 compares the harmonic distortion caused by errors and for and the same value of the linear error. Note that the harmonic distortion caused by dynamic errors is much larger than that caused by static errors. In particular, for linear errors below the harmonic distortion is dominated by the non-linear sampling-and-hold error, The harmonic distortion (and the linear error) caused by dynamic errors will be especially critical in high-speed applications. Thus, in order to increase the bandwidth of the memory cell – given by – either C should be reduced or should be increased. However, the former will cause an increase of the sampled thermal noise, while the latter will produce an increase in the power consumption. This leads us to the classical trade-off among speed, dynamic range and power consumption. In order to analyze this trade-off for the simple memory cell, the following performance vectors are defined: •

where

The minimum speed of the cell, defined as:

has been considered.


197

The power consumption,

where VDD is the power supply voltage. The dynamic range,

and

From (3.190) and (3.208) and assuming shown that

it can be

Combining the above performance vectors, the following Figure-Of-Merit (FOM) can be defined [Nair96]:

where

and

Fig. 3.46 represents FOM as a function of The maximum value of FOM is obtained for

for

and

Once the optimum value of has been obtained from solving the tradeoff among speed, dynamic range and power consumption, the design effort should aim at reducing the harmonic distortion so that it will be below the required dynamic

198


range. Let us consider the following example. Assume that a memory cell is designed to operate at with a Signal-to-(Noise + Distortion) Ratio (SNDR) larger than 60dB . The problem consists of finding the optimum values for and C that achieve these requirements. We will solve this problem numerically. For the sake of simplicity, the charge injection error will be neglected because it is assumed that the value of C ( = 0.5 pF) will be large enough to attenuate this error. Thus, Fig. 3.47(a) represents the harmonic distortion and the thermal noise power as a function of for and . Note that, while thermal noise is below the desired resolution, the harmonic distortion (especially that caused by ) limits the performance unless the power consumption is increased. However, a better performance is obtained by reducing the power supply as illustrated in Fig. 3.47(b) for Note that, although the thermal noise is larger than in Fig. 3.47(a), it agrees with the required resolution (60dB). However, the harmonic distortion is reduced with thus demonstrating that the performance of SI circuits will not be degraded for low-voltage operation. Fig. 3.48(a) illustrates this by representing SNDR vs. for different values of Note that, as the harmonic distortion caused by (which dominates the maximum resolution is obtained for the minimum SNDR) decreases with Observe from Fig. 3.47(b) that in the case that can be considered negligible, for example if the resolution at low values of will be dominated by the harmonic distortion due to This is illustrated in Fig. 3.48(b). In this case, †14. In this case, the harmonic distortion caused by the non-linear settling is well below thermal noise.


199

the maximum value of SNDR is obtained for giving SNDR = 67.5dB. This value can be increased if is reduced by using any of the memory cells described in Section 3.2.4. However, as the memory cell becomes more complex, it becomes more difficult to keep all transistors in the saturation region with low values of This fact imposes a practical limit to the lowest supply voltage used.

200



201

SUMMARY This chapter described the main errors responsible for the non-ideal behaviour of SI circuits, namely: finite output-input conductance ratio error, charge injection error, incomplete settling error, mismatch errors and noise. The physical mechanisms behind all of them are explained and a precise modelling of the memory cell is derived. Based on this modelling, the effect of each error on the performance of both single-ended and fully-differential memory cells is analyzed by considering either linear or non-linear errors. As a result of this analysis, closed-form expressions are found for the linear gain error, offset and harmonic distortion. The knowledge provided by these expressions allow the designer to reduce the errors by properly sizing the cell. Numerical examples, validated by electrical simulations, are given as an illustration. Besides, circuit strategies to reduce SI errors reported up to the present are summarized and compared. All the analyses have been made at the memory cell level and validated by electrical simulation using HSPICE. In the next chapter we will extend this study to other blocks in the modulator hierarchy such as integrators and resonators. This will allow us to evaluate the impact of each SI error on the performance of bandpass modulators.


Non-Ideal Performance of Switched-Current Bandpass

Modulators

203

Chapter 4 Non-Ideal Performance of Switched-Current Bandpass Modulators 4.1

Introduction

As stated in Chapter 1, modulators combine oversampling to reduce the in-band power of the quantization noise, and filtering to shape this noise and push it outside the signal band. Thus, the resolution of Analog-to-Digital Converters (ADCs) can be augmented by means of two mechanisms, namely, the increase of the loop filter order (L) and the oversampling ratio ( M ) . In addition to these two properties, the resolution also increases with the number of bits of the quantizer (N). In practice, several problems arise from enlarging M, L and N. On the one hand, as the signal bandwidth is commonly fixed, the only way to increase M is through the sampling frequency . This makes the bandwidth requirements for the modulator building blocks more demanding. On the other hand, large values of L lead to an unstable behaviour of the modulator because of the accumulation of large signals in the integrators [Arda87]. Finally, large values of N are unfeasible due to the sensitive influence of unavoidable linearity errors associated to the in-loop multi-bit Digital-to-Analog Converters (DACs) [Nors97]. The above reasons render 1-bit second-order (N = 1;L = 2) lowpass a convenient architecture for practical implementation purposes†1. Most bandpass obtain their architecture by applying the Z-domain transformation to an . This maintains the stability properties of the original modulators and enables us to take advantage of the knowledge available on the properties of the original [Nors97]. As a consequence of this transformation, fourth-order – derived from a second-order LP– constitute a †1. Recently, the demand for high frequency applications has motivated the use of cascade architectures based on first- and second-order single-loop stages. These architectures allow us to obtain high resolutions without using large values of M [Mede99].

204


fundamental architecture for as has been demonstrated in a large number of Switched-Capacitor (SC) implementations [Jant93] [Long93] [Song95] [Fran96] [Hair96][Norm96b][Baza97][Corm97][Jant97b][Liu97][Nors97][Ong97b]. The non-ideal performance of these modulators as well as the characterization of their major building block error mechanisms – operational amplifier finite gain, slew-rate, clock jitter, etc... – have been modelled and described, as well as their influence on the modulator performance [Bose88c], thus allowing for an automatic design methodology [Mede99]. This is not the case of switched-current (SI) where very few analysis have been realized only at the memory cell level. This chapter extends the analysis of SI errors from the memory cell level – already discussed in Chapter 3 – to other levels of the modulator hierarchy such as integrators and resonators. The impact of both linear and non-linear SI errors on the performance of is analyzed in a systematic way. As a result of this study, closed-form expressions are found for the quantization noise transfer function deviations, the in-band noise power, and the harmonic distortion. All these results have been validated by time-domain behavioural simulations using the simulator that will be described in Chapter 5. The analysis presented in this chapter will focus on single loop fourth-order . These modulators are easy to understand and simple to design, are capable of providing high resolution together with large tolerance to imperfections and robust stable operation [Nors97]. Nevertheless, this study can be easily extended to other architectures such as multi-stage cascade architectures, based as they are on single loop fourth-order [Hair96].

4.2 Ideal noise shaping in fourth-order bandpass

modulators

Fig. 4.1(a) shows the Z-domain block diagram of a single loop second-order Applying the transformation to this modulator, results in the fourth-order shown in Fig. 4.1(b). Assuming that the quantization error is modelled as white, additive noise [Nors97], the Z-domain output is given by

where and are respectively the Z-transform of the input signal and the additive quantization noise source. The ideal quantization Noise Transfer Function


Modulators

205

is of the bandstop type,

On the other hand, the ideal Signal Transfer Function, type,

By making , where that has two transmission zeroes at quency is actually of the band-stop type.

is of the all-pass

is the sampling frequency, it can be seen , and that the filtering around this fre-

The in-band quantization noise power can be calculated by integrating the output power spectral density within the signal band,

206


where is the Power Spectral Density (PSD) of the quantization noise error, is the quantization step, and is the oversampling ratio. From (4.4), and assuming that the modulator input is a sinewave of amplitude the Signal-to-Noise Ratio (SNR) at the output results in:

The modulator Dynamic Range (DR) is obtained by making above expression.

in the

In this ideal scenario, the resolution increases with M at a rate of about 2.5-bit/octave. This is illustrated in Fig. 4.2 where DR is displayed as a function of M. However, such an ideal feature can only be achieved provided that the scaling coefficients and the resonator transfer functions in Fig. 4.1(b) are realized without errors. Modelling of these errors and circuit optimization are needed to cope with the SNR and DR degradation observed in actual circuits. The block diagram of Fig. 4.1(b) contains two resonators in a single loop. Resonators play the same role in as integrators in Hence, the first step of our analysis is choosing a suitable architecture to realize the resonator transfer function As stated in Chapter 2, there are basically three alternatives: LDI, FE and delay loop resonators. Assuming that all scaling coeffi-


Modulators

207

cients are exact, the mentioned structures are identical. However, as demonstrated in Section 2.5, in practical realizations the scaling coefficients are non-exact due to errors, and hence the poles of experience movements around their nominal positions – different for each structure. The analysis in Section 2.5 revealed that LDI-loop resonators are the only ones which remain stable under changes in their scaling coefficients. For that reason, this has been the resonator structure chosen for our study†2 . Fig. 4.3 shows the Z-domain block diagram of a fourth-order based on LDI-loop resonators. Note that the required feedback loop delay has been realized through two additional delay blocks. The scaling factors can be optimized to obtain similar dynamic range for both resonators, bearing in mind the general recommendations about the scaling of SC [Mede99] and SI circuits [Tan97]. This yields the following nominal values,

which, as confirmed by the histogram of Fig. 4.4, cause both resonators to have similar output signal amplitudes, and hence, their design can be identical. The analysis described in this section assumed that all building blocks of the modulator are ideal. However, as stated in Chapter 3, there are several mechanisms

†2. All the analyses derived in this chapter for LD loop resonators can be extended to FE loop resonators following the same methodology described here.

208


of errors that degrade the ideal operation of SI circuits. In the following sections, we will present a systematic study of the impact of said errors on the performance of fourth-order bandpass modulators. For this purpose, the analysis of SI errors will be extended from the memory cell to other building blocks of a higher level in the modulator hierarchy, such as integrators and resonators. Based on this analysis, close form expressions will be derived for the degradation of and The study presented here will be focused on second-generation memory cells, which as stated in Chapter 3, are the most extensively used in Integrated Circuits (ICs).

4.3 Impact of linear errors on the performance of SI integrators As stated in Chapter 3, the most significant error mechanisms which degrade the performance of second-generation SI circuits are†3: finite output-input conductance ratio error (represented by the parameter ); incomplete settling ; and memoryswitch charge injection . The effect of these errors on the performance of the memory cell has been studied in Chapter 3. Table 4.1 summarizes the linear effect.

†3. Other errors such as mismatch of fully-differential second-generation memory cells will not be considered because in practical cases they can be neglected as compared to the others.


Modulators

209

In the more general case, the original half-delay transfer function is modified into,

where a, b and c are different for each error, as Table 4.1 shows. The deviations from real integrator transfer functions as compared to their ideal counterparts can be hierarchically derived from the non-ideal memory cell transfer functions as we will demonstrate in the next section. Although we will focus on LD integrators, the same procedure can be followed to obtain the non-ideal transfer function of FE integrators [Toum93].

4.3.1 Effect of


Fig. 4.5(a) shows a simple SI realization of an LD integrator. For the following analysis it will be assumed that memory cells are ideal except for the finite outputinput conductance ratio error. Thus, each memory cell has a finite input conductance, represented by the parameter and a finite output conductance,

210


On clock phase of period , memory cell 2 is on the sampling phase and memory cell 1 is on the hold phase. The small-signal equivalent circuit is shown in Fig. 4.5(b). From this circuit it can be shown that the drain current of is†5

During clock phase of period , the small-signal equivalent circuit is shown in Fig. 4.5(c). On this clock period, memory cell 1 is on the sampling phase and memory cell 2 is on the hold phase. The drain current of is given by

and the output current is:

From (4.8), (4.9) and (4.10), it can be shown that the difference equation which governs the operation of the integrator is given by

Assuming that and taking the Z-transform of the above expression, we obtain the transfer function for the LD integrator degraded by

Note that the effect of on the integrator transfer function is analogous to that caused in SC integrators by the finite operational amplifier dc gain [Bose88b], modifying the dc gain and the pole frequency of the integrator.

†4. In case of simple memory cells, †5. We use the notation


4.3.2 Effect of

Modulators

211


For the following analysis, we will assume that the memory cells which form the integrator of Fig. 4.5(a) are ideal except for the charge injection error, . Assuming only the signal-independent part of this error, the drain current of the memory cell 2 on clock phase is:

and on clock phase , the drain current of the memory cell 1 and the output current of the integrator are respectively given by:

From (4.13), (4.14) and (4.15) it can be derived that the transfer function of the LD integrator under charge injection error, for , is:

where has been assumed. Note from (4.12) and (4.16) that and present the same influence on the integrator transfer function. This will cause that both errors degrade the modulator in the same way, as we will see later on.

4.3.3 Effect of


Assuming that memory cells are ideal except for the linear settling error and following the same steps as before, it can be shown that the finite difference expressions which describe the operation of the LD integrator of Fig. 4.5 are:

212


Solving the above expressions for

and taking the Z-transform results in:

Note that modifies the transfer function of the integrator in a different way as compared to and , by adding one pole and one zero. This different effect at the integrator level will be reflected at the modulator level as we will see in Section 4.5.

4.4 Impact of linear errors on the performance of SI resonators 4.4.1 Effect of memory cell errors Fig. 4.6 shows a conceptual SI realization of an LDI-loop resonator. For our analysis we will assume that the integrator output stages are ideal and the integrators which form the resonator are identical. Thus, they are subject to identical memory errors, and hence, the resonator transfer function degraded by memory cell errors – generically represented by – can be calculated from the integrator transfer function in a hierarchically way as


Modulators

213

Where represents the integrator transfer function degraded by error . Table 4.2 shows the expression for with and Both errors and cause the same degradation on transfer function of the resonator by

. If we represent the

it is clear from Table 4.2 that for the mentioned errors results in . This gives a fixed pole angular frequency of a pole ratio corresponding to , hence , thus the resonator remains stable under these errors. On the other hand, the settling error yields and that, although the degradation of is the same as for and quency of the poles is shifted from causing an error given by

and and As

. Note errors, the fre-

214


Fig. 4.7 represents . An error of about 1.3% in the resonator pole frequency is obtained for . It will be shown in next sections that the notch frequency, – the central frequency of the signal band – of is shifted from its nominal position due to the settling error.

4.4.2 Effect of resonator loop gain errors In the previous section, the integrator output stages were assumed ideal. Integrator output stages act as scaling coefficients and in the resonator loop of Fig.4.6(a). In practice, different errors associated to those stages have to be considered, such as mismatching and the finite output resistance. Before studying the effect of these errors on the resonator transfer function, let us consider their influence on the integrator transfer function. Fig. 4.8(a) shows the conceptual schematic of an SI LD integrator with a non-ideal output stage modelled through an output resistance. The steering switches are modelled through an on-resistance in series with an ideal switch. The integrator input-stages are considered ideal except for the finite transconductances, and the memory transistor output conductances, and .Let us assume that one output stage (represented through a current source in parallel with an output resistance) is connected to the mentioned integrator. The small-signal equivalent circuit on clock phase of period Fig. 4.8(b). The drain current of transistor is given by

where

is shown in


Modulators

215

with as the transmission error due to the current division at the output of the integrator. On clock phase

of period

On this phase, the output current,

is given by

216


with From (4.22), (4.23) and (4.24) it can be shown that

Defining input,

as the transmission error due to current division at the

From the above expression it can be seen that the non-ideal output stage has two different effects on the integrator transfer function. The first one is to modify the output gain by the errors and the second one is to change the poles of the integrator by the error The above analysis has been made by considering only one output stage. In general, if the integrator has N input stages, its output current is given by:

where and are the memorized error and the scaling error associated to the n-th input (n-th output stage connected at the input), while is the error associated to the integrator output stage. Now, let us consider the resonator of Fig. 4.9. Using (4.27) and the approximations given above, it is easy to show that the resonator transfer function is given by


Modulators

217

where From (4.28) we can differentiate two different effects of non-ideal output stages on the resonator transfer function. On the one hand, there are deviations in the scaling coefficients included in the resonator architecture of Fig. 4.6

where

and

Due to these errors, the generic resonator coefficients are modified as

This means that the resonator poles remain inside the unity circle for changes in the scaling coefficients but the frequency of these poles is shifted from causing an error given by

218


Mismatch errors in the output current mirrors also contribute to the scaling error, as demonstrated in Section 3.5. Taking into account both the finite output conductance and mismatch errors, the scaling coefficients are modified as

Another effect of non-ideal integrator output stages is represented through the errors and which we will represent generically as and . These errors cause a degradation in the resonator transfer function characterized by

Hence, both the ratio and the frequency of the poles are modified as

Fig. 4.10 compares the effect of non-ideal integrator output stage errors with that of the settling error. Fig. 4.10(a) plots the movement of and Fig. 4.10(b) plots the movement of the pole frequency. It can be seen that the most significant degradation is due to


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Table 4.3 summarizes the influence of SI errors on the resonator transfer function showing all possible cases for generic coefficients and

4.5 Non-ideal quantization-noise shaping in fourth-order In this section we will analyze the impact of linear SI errors on the quantization noise shaping of fourth-order . As stated in the previous sections, we will focus on the architecture of Fig. 4.3. Note that, in addition to the mentioned SI errors, other scaling errors are found at the modulator level. They therefore do not influence the resonator transfer function, and simply affect the resonator and the DAC gains,

We will refer to the corresponding errors associated to these scaling coefficients as

Let us consider that the resonators in the modulator of Fig. 4.3 are degraded by SI errors as Table 4.3 shows. Assuming that the quantization error can be modelled as an additive, white noise, Table 4.4 shows different expressions for the quantiza-

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tion noise transfer function degraded by each SI error represent by

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which we will generically

We can classify the SI errors in three different groups according to the way they degrade the zeroes of .†6 The errors and (denoted by parameter ) only reduce the Q-factor of the zeroes of , thus lowering the band-stop attenuation of the modulator bandpass filtering. This is illustrated in Fig. 4.11(a), where is plotted for different values of

†6. Although from the ideal point ofview, does not have poles, in the presence of SI errors some poles appear. However, this effect is negligible as compared to the degradation of the zeroes for practical error values and considering the frequencies of interest (in the signal band).

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The errors and , represented by parameter , just change the position of the notch frequency, . However, the quantization noise power does not significantly increase, as shown in Fig. 4.11(b). , The errors and , represented by parameters and respectively, degrade the position of the notch frequency and increase the quantization noise power in the signal band. Note that, for similar values of parameters and , the settling error produces larger deviations in than the error. This is illustrated in Fig. 4.11(c) and Fig. 4.1 l(d) respectively.

Finally, it can be seen from Table 4.4 that for a reasonable range – less than 1% – modulator loop gain errors do not cause any effect on the quantization noise shaping. All these results have been validated by time-domain behavioural simulation†7. Thus, Fig. 4.12 compares the theoretical model – solid line – with the simulation showing the degradation of with different errors and demonstrates a good agreement between simulation and theory. The non-ideal shaping of the quantization noise results in an increased noise power , different for each group of errors. Table 4.5 shows the erroneous quanti-

†7. A detailed description of the behavioural models and the simulator will be given in Chapter 5.


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zation noise power increments. They have been obtained from their corresponding by applying (4.4). Table 4.5 provides insight into the significance of the different error sources. For the sake of completeness this has to be complemented with the ranges expected for the error parameters, which depending on the circuit strategy adopted, may vary typically between 0.1% and 1%. Several conclusions are drawn from Table 4.5. For the errors the deviation in the quantization noise power is dominated by the term up to ; beyond this limit the term dominates, thus practically destroying all the benefits of oversampling. This is illustrated in Fig. 4.13(a), which depicts the DR as a function of M for three values of assuming that the remaining errors are zero.


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Correspondingly, for the family of errors called the term dominates up to Fig. 4.13(b) shows DR as a function of M for three values of In the case of errors called , we have to differentiate the effect of the settling error and error. For the settling error, the term dominates up to for the error this term dominates up to . The influence of both errors is illustrated in Fig. 4.13(c) and Fig. 4.13(d) respectively. For similar values of parameters and , the settling error produces larger deviations in the noise transfer function than the rest of errors – illustrated in Fig. 4.14. This makes it necessary to use larger oversampling ratios to achieve similar SNR levels.

4.6 Cumulative influence of SI errors on the quantization noise shaping In the previous section, the isolated influence of SI errors on the quantization noise shaping was analyzed. Expressions for the quantization noise power were found for each family of errors assuming that the others were nullified. However, that model fails to predict the SNR degradation if two or more errors are different from zero. A conservative estimation should consider that all the power increments shown in Table 4.5 are cumulative. In such a case, the total quantization noise power

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is given by

Fig. 4.15 compares the prediction given by (4.36) with behavioural simulations by plotting the half-scale SNR (obtained for ) vs. M for several values of and . It is clear from this figure that (4.36) predicts very pessimistic results as compared to simulations. A less conservative theoretical prediction can be derived from the expressions in Table 4.5 by simply summing the error terms as


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However, as illustrated in Fig. 4.15(b), the above expression offers a very optimistic prediction. The reason of these differences is the starting point of the analysis. In Section 4.3 we analyzed the integrator transfer function assuming that all errors presented in SI circuits except one were nullified. This starting hypothesis is only true in case one error dominates the others. In this section we will study the cumulative influence of SI errors on the performance of basic building blocks. This analysis will be extended to describe the quantization noise shaping degradation in the presence of all errors. 4.6.1 Effect of cumulative errors on the performance of the memory cell Consider the cascaded memory cells shown in Fig. 4.16(a). During clock phase of period , cell 1 is in hold phase while cell 2 is in sampling phase. The small-signal equivalent circuit for such a configuration is shown in Fig. 4.16 (b). The stationary current of the memory transistor in cell 2, , is given by

where

and

represents the finite switch-on conductance.

For the sake of simplicity, we will assume fies into

. Thus (4.38) simpli-

where , with and being the small-signal input and output conductance of cell 2, respectively. Expression (4.39) is also valid for other memory cells by substituting with the corresponding input transconductance. However, it applies only if the memory cell reaches the steady state before the end of the sampling phase. Otherwise, an additional error is generated as a consequence of the incomplete settling of the voltage at the gate of the memory transistor. Using a firstorder approach for the settling (see Fig. 4.16(b)), the following differential equation results:

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Solving from the above equation with condition of the gate-source capacitor yields

where

as the initial

stands for the incomplete settling error and represents the memorized drain current in the previous sampling phase. When the memory switch opens, in the beginning of phase , the charge injected


by the switch transistor in

introduces an additional error term

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, so that

Fig. 4.16(c) shows the equivalent circuit for cell 2 in the hold mode. The memorized drain current is calculated from this circuit. Taking the Z-transform gives:

and

Thus, the transfer function for the memory cell in the presence of errors is given by:

It can be seen from the above equation that the ideal transfer function of the memory cell – a half delay – is modified by a gain error which is the sum of the output/input conductance error, the charge injection error and the settling error. This is illustrated in Fig. 4.17 where the transient evolution of is represented during both clock phases.

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4.6.2 LD Integrator considering cumulative errors Let us consider the LD integrator shown in Fig. 4.18(a). In the following it will be assumed that memory cells which form the integrator are subject to three errors: output/input conductance ratio error, charge injection error and settling error. The output current mirror will be considered ideal. On clock phase of period the small-signal equivalent circuit is that shown in Fig. 4.18(b). The steady state drain current of is given by

with

. Due to the incomplete settling,


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On clock phase of period the small-signal equivalent circuit for the integrator is shown in Fig. 4.18(c). The drain current of is given by

and the output current is

From (4.45)-(4.48) and after taking the Z-transform we obtain:

The isolated effect of each error on the integrator transfer function can be obtained from the above equation by simply nullifying the rest of the errors. From (4.49) it is clear that all error mechanisms contribute as an error gain but the settling error is the only one that changes the poles in a different way as compared to the other errors. 4.6.3 Noise shaping degradation with cumulative errors Let us consider the resonator shown in Fig. 4.9. Using the non-ideal transfer function given in (4.49) for the LD integrators and considering all mentioned errors: and , we obtain the following transfer function for the resonator:

where

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Let us consider the block diagram of Fig. 4.3. Note that the poles of (4.50) correspond to the zeroes of . Substituting (4.50) in the transfer function of the resonator in Fig. 4.3, the erroneous quantization noise transfer function under cumulative errors results in:

We

can

express

the

above and

coefficients

in terms of which yields:

From (4.4) and (4.54) the quantization noise power can be derived. After some simplification it can be shown that

Making all errors equal to an error bound named power is obtained:

, the following quantization noise

where and . This equation allows us to express the quantization noise power degradation in terms of , thus by forcing all SI errors in the modulator to be smaller than , we bound the quantization noise power with (4.58). Fig. 4.19(a) plots the half-scale SNR as a function of , for M = 64, M = 128 and M = 256. Simulation results match the data calculated from (4.58).


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Fig. 4.19(b) plots the half-scale SNR as a function of M for different values of . The term dominates up to , above this value the advantages of oversampling are destroyed. In practical applications, the designer needs to know which is the maximum error, , allowed as a function of the value of DR required. In such a case, it is useful to express in terms of DR loss, and the oversampling ratio M. From (4.5) and (4.58) it can be shown that

Fig. 4.20 plots

for different values of M. It can be seen that the

234


predictions given by the theoretical data agree with the simulations. As a numerical example, let us assume that the required resolution is DR = 96dB (16-bit). Looking at Fig. 4.20, this will be achieved for M = 512 and , which are very restrictive conditions. In the case of AM radio receivers, the required DR = 60dB (10-bit), which leads to a more realistic approach, for M = 128 and . Another consequence of the influence of errors is that the resolution of the modulator does not significantly increase with M, thus destroying the advantages of oversampling. In addition to the quantization noise degradation, in , the control of the notch frequency (represented by the parameter ) is also critical. In practice, this frequency is fixed by the system requirements, so that its position should not be significantly shifted from . We can derive by solving (4.54) for the frequency of the zeroes. Assuming that , the error in , denoted as , is given by:

From (4.60) and taking into account that all the errors in (4.52) are positive, and therefore for all SI . On the other hand, considering that the quantization noise power is minimum at , we can define a maximum error . From (4.60) and assuming all SI errors to be equal to , this condition is satisfied if . For instance, if M = 128, we obtain: Fig. 4.21 illustrates this by plotting three output spectra corresponding to different values of . It is seen that the predictions of (4.60) agree with the simulation data.


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Note from (4.60) that the error in the notch frequency increases with the oversampling ratio. This imposes another trade-off between and M. Hence, if large values of M are required to achieve higher resolution, errors should be attenuated according to (4.60) in order to reduce the notch frequency shift.

4.7 Harmonic distortion due to non-linear SI errors In the previous sections the effect of main SI non-idealities on the noise shaping of has been analyzed. Both their isolate and cumulative influence have been studied. As a result of this analysis, closed-form expressions have been derived for the quantization noise power increments and the notch frequency as a function of the main SI errors. In the mentioned study, all SI error mechanisms have been assumed to be linear, that is, not dependent on the input signal. However signal-dependent errors are responsible for the low performance of most In particular, harmonic distortion caused by them is recognized as one of the most important SI performancelimiting factors [Moen97]. Practically all SI errors are signal-dependent and, hence, cause harmonic distortion as demonstrated in Chapter 3. There, the influence of each SI non-linear error on the harmonic distortion was analyzed and closed-form expressions were derived for the memory cell. This analysis was validated by electrical simulations.

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In this section we will extend that study to bandpass SI modulators. Based on the analysis of fully-differential memory closed-form expressions will be derived for the harmonic distortion coefficients of SI fully-differential integrators, resonators and bandpass modulators. 4.7.1 Harmonic distortion due to static non-linear errors According to the analyses derived in Chapter 3, the output current of a simple memory cell in the presence of SI errors can be generically expressed as

where stands for the offset current at the output, is the linear gain error, the thermal noise contribution and represents the non-linearity.

is

Note that the expression in (4.61) is valid for all SI errors except for the settling error. In such a case, the output current of the cell can be written as:

The output current in the above expression is not only a function of the input current at the sampling instant, but also of the output current at the last sampling instant, This is due to the fact that the value of the gate-source voltage reached at the end of the sampling phase depends not only on the value of the input signal at that instant but also on the initial condition of the capacitor. In this sense, we will refer to the settling as a dynamic error. Otherwise, the remaining SI errors will be referred to as static errors because they only depend on the input signal at the sampling instant. 4.7.1.1 Simple model for the memory cell in the presence of static non-linear errors As mentioned earlier, we will assume that the memory cell reaches the steady state before the end of the sampling phase and, consequently, settling error will not be considered. Also, thermal noise and offset current will not be included in our analysis because they do not contribute to the harmonic distortion. Regarding it can be expressed as a polynomial function of the input current, †8. A similar analysis can be derived for single-ended circuits following the procedure shown in this section.


where

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have different expressions for each error.

Taking into account the above considerations, expression (4.61) can be simplified into:

For illustration purposes, Table 4.6 shows (extracted from Section 3.2 and Section 3.3) when the memory cell is degraded by charge injection, and nonlinear output-input conductance ratio error. All symbols and parameters have the same meaning as in Section 3.2 and Section 3.3. Assuming that the input current of the memory cell is a sinusoidal signal of amplitude the output current will contain harmonics of the input signal frequency The harmonic distortion, is defined as the ratio of the output signal amplitude at frequency to the linear output amplitude. For our analysis, we will assume fully-differential memory cells. Thus, even powers of the input current in (4.64) can be considered negligible. On the other hand, assuming that the thirdorder harmonic is dominant, (4.64) can be simplified into:

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In this case, the Total Harmonic Distortion ( T H D ) is approximately equal to and given by:

4.7.1.2 Harmonic distortion in fully-differential SI integrators Fig. 4.22 shows the schematic of a fully-differential SI LD integrator. It is composed of two cells and an output stage. In the following, it will be assumed that the operation of the memory cells is described by (4.65). Although these memory cells are simple, our analysis can be extended to enhanced memory cells – cascode, regulated-cascode or folded regulated-cascode – by conveniently changing the expressions of and The operation of the integrator is as follows. After clock phase which goes on for the differential drain current of the memory cell 2 is given by:

where cell 1. After clock phase

represents the differential drain current of memory


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Assuming that the output stage (represented in Fig. 4.22 as a simple current mirror) is the output current of the integrator is given by:

From (4.67), (4.68) and (4.69) it can be derived that the output current of the integrator is

where

Assuming that (4.70), we obtain:

and performing a Taylor series expansion of

where

Thus, the analysis of an SI integrator formed by memory cells with static nonlinear errors can be accomplished considering an integrator formed by memory cells with linear gain errors whose input signal is equal to (4.73). The equivalent harmonic distortion at the integrator input can be estimated by analyzing the harmonic content of such an expression. For this purpose, let us assume that the input current is a sinusoidal signal of amplitude and frequency In this case, the output current of the integrator will be a periodic signal, with the amplitude of its fundamental harmonic given approximately by:

†9. The effect of non-ideal output stages will be considered in the next section.

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where is the sampling period. On the other hand, we will suppose that the output of the integrator can be approximated by its first harmonic, so that:

Substituting (4.74) and (4.75) in (4.73) and performing a Fourier series expansion, it can be shown that the third-order harmonic is

The amplitude of the third-order harmonic at the integrator input derived from (4.76) is

The amplitude of the third-order harmonic referred to the integrator output can be obtained by multiplying (4.77) by the module of the integrator transfer function

The third-order harmonic distortion referred to the integrator output is calculated by dividing the above expression by giving

The above expression has been verified by time-domain behavioural simulation


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using the SDSI simulator described in Chapter 5. Fig. 4.23 displays as a function of for several values of by keeping equal to 1%. Observe that the calculated data matches the simulation results very well. The expression in (4.79) has been derived for the general case and, hence, it can be used to predict the harmonic distortion in SI fully-differential integrators due to any static error. As an application, let us assume that the integrator in Fig. 4.22 is ideal except for the charge injection error. The theoretical prediction of the thirdorder harmonic distortion for this integrator can be computed by substituting the corresponding expressions of and (see Table 4.6)†10 in (4.79). †11 Fig. 4.24 plots vs. and compares the theoretical model with time-domain simulations using SDSI. In this example: (common-mode signal), and Note that both the linear and the non-linear gain errors increase with Their effects on the harmonic distortion are well predicted by the model. On the other hand, the influence of the integrator gain is also considered by changing the input signal frequency. Several values of have been applied showing a good agreement with the simulations.

†10. These expressions correspond to a single-ended memory cell. For the case of fully-differential cells, has the same value and †11. and represent the memory switch gate capacitance and memory transistor gate-source capacitance, respectively.

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4.7.1.3 Harmonic distortion in fully-differential SI resonators Fig. 4.25 shows the block diagram of an LDI-loop As was demonstrated in previous sections, this structure is advantageous as compared to the others because it remains stable under changes in the loop coefficients. Let us assume that the integrators which form the resonator in Fig. 4.25 are implemented as shown in Fig. 4.22. In the presence of non-linear static errors, they can be described by (4.72) and, hence, the finite-difference equations which describe the behaviour of the resonator are

†12. In the following, we will use these symbols for SI integrators with non-linear errors.


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where and are respectively the input and the output of the first integrator in the loop (see Fig. 4.25) while and are respectively the input and the output of the resonator. Solving for

in (4.81), substituting it in (4.80) and assuming that results in the following finite-difference equation:

where

Assuming that is a sinusoidal signal of amplitude nal, with the amplitude of its fundamental harmonic being:

will be a periodic sig-

As in the case of the integrator, the output current of the resonator can be approximated by its fundamental harmonic, which can be generically expressed as

where resonator.

and

is the phase delay caused by the

Substituting (4.85) in (4.83), and performing a Fourier series expansion, it can be shown that the third-order harmonic is

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where

and

has been assumed.

From (4.86) it can be derived that the amplitude of the third-order harmonic at the resonator input is

Following the same procedure as in Section 3, the third-order harmonic distortion at the resonator output can be found by multiplying (4.87) by the resonator gain (evaluated at and dividing this result by This gives

where This analysis has been validated by time-domain behavioural simulation as illustrated in Fig. 4.26 for different values of Observe that the data predicted by (4.88) fits the simulation results very well. For this simulation the linear gain error was and the input amplitude


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As in the case of the integrator, the expression above predicts the third-order harmonic distortion of fully-differential SI resonators under non-linear static errors. The expression in (4.88) can be particularized for each SI error by simply substituting by the corresponding expression derived in Chapter 3. As an illustration, let us assume that the resonator in Fig. 4.25 is formed by fully-differential regulated folded-cascode memory cells like the one shown in Fig. 4.27. As was demonstrated in Section 3.4.2, due to the input feedback loop, this cell increases the input conductance as compared to the simple memory cell. There we demonstrated that the current source named (see Fig. 4.27) has to be taken as large as possible in order to obtain an overdamped settling response. However, large values of may force some transistors to leave the saturation region, thus causing a non-linear dependence of the input voltage on the input signal. This behaviour is illustrated in Fig. 4.28 by plotting the differential input voltage as a function of the input current amplitude

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This behaviour can be modelled as

where is the differential drain current of each memory cell. Coefficients and which are a function of were extracted from a dc simulation using HSPICE. It can be shown that where is the output conductance of the memory cell. Thus, the harmonic distortion of the resonator can be calculated by simply substituting (4.90) in (4.88). Fig. 4.29 compares theoretical results with simulations by plotting as a function of for different values of Note that, as a consequence of changing both the linear and the non-linear error, the harmonic distortion does not increase with This is well predicted by the model. Because the resonator open loop gain is too high, a small input amplitude was chosen as compared to the bias current, in order to keep the memory transistors in the saturation region.


4.7.1.4 Harmonic distortion in SI fourth-order bandpass Fig. 4.30 shows the block diagram of a fourth-order resonators like those shown in Fig. 4.25.

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modulators based on LDI-loop

Modeling the quantization error as an additive, white noise source and considering that the integrators are ideal, the Z-domain equations that describe the behaviour of the modulator are:

where tor;

and represent respectively the input and the output of the modulaand are the input and the output of the first integrator; and are the input and the output of the first resonator.

For the analysis of the harmonic distortion, the following considerations have been taken into account: The harmonic distortion referred to the modulator input is equal to the harmonic distortion referred to the modulator output. This is because the gain of is unity. The harmonic distortion referred to the first resonator input is added directly to the input signal. Thus, it is not attenuated in the base band. However, the contribution of the second resonator to the harmonic distortion is attenuated

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by the gain of the first resonator. For this reason, only the first resonator contribution has to be considered for the analysis. The quantization noise has not been considered for the calculations since it does not contribute to the harmonic distortion. From (4.91), the amplitude of the resonator output can be written as

where is the amplitude of the modulator input, Taking into account the effect of the linear gain error on the integrators, it can be shown that the above expression is modified as follows:

Substituting (4.93) in (4.87) and dividing by the third-order harmonic distortion at the modulator output is approximately given by

We can simplify the above expression taking into account several considerations. On the one hand, as can be derived from Table 4.6, can be expressed as On the other hand, as stated in Section 4.2, the optimum dynamic range for the resonators is obtained for Taking into account the above considerations, the expression in (4.94) simplifies into:


where

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is the DAC output current and

In bandpass signal processing, the third-order intermodulation distortion, is more appropriate for measuring distortion than Let us assume that the modulator input consists of two sinusoidal signals of the same amplitude and different frequencies and If the memory cells which form the modulator are degraded by non-linear errors, the modulator output spectrum presents intermodulation harmonics of the input signals. Among them, the most significant one is which is defined as the amplitude of the output at and related to the linear output amplitudes at It can be shown that is related to as [Will95]

The above expression has been validated by time-domain behavioural simulation. Fig. 4.31(a) compares the data predicted by (4.96) with that obtained with the simulations by depicting as a function of for different values of the DAC reference current, and demonstrating a good agreement. The dependence on the input signal amplitude is shown in Fig. 4.31(b) by plotting two output spectra for different values of Note that, in addition to the harmonic distortion, there is also an increase of the in-band noise power as a consequence of the nonlinearity. This phenomenon will be discussed in more detail in Section 4.8. As an illustration, let us consider that the modulator is formed by fully-differential regulated folded-cascode memory cells like those shown in Fig. 4.27. In this case, Fig. 4.32(a) compares simulation results and theoretical data by plotting against for different values of the DAC reference current Fig. 4.32(b) shows the output spectrum of the modulator for and The predicted value for is –53dB, which agrees with the simulated value (–51dB).

4.7.2 Harmonic distortion due to the settling error As stated in Chapter 3, the settling error degrades the memory cell performance in a different way than the remaining memory cell errors ( and ). This different

250


behaviour is basically due to the fact that the incomplete settling error mechanism depends on initial conditions of the gate-source voltage on the sampling phase. This causes a different quantization noise filtering in bandpass modulators for as compared to that due to and As a consequence of its different influence on the memory cell, the impact of the non-linear settling error on the performance of bandpass modulators has to be analyzed in a different way. However, as we will demonstrate here, very similar results to the static case are obtained at the modulator level. Based on the analysis of the fully-differential LD integrator, we will derive a closed form expression for the third-order intermodulation distortion in fourth-order and we will validate these theoretical results by comparing them to time-domain behavioural simulations.


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4.7.2.1 Harmonic distortion in fully-differential SI integrators due to settling error Let us consider the fully-differential integrator of Fig. 4.22. In the following, it will be assumed that the operation of memory cells is described by (3.120), and hence, the differential drain current of each memory cell can be expressed by (3.117). The operation of the integrator is as follows. After clock phase which goes on for the differential drain current of memory cell 2 can be expressed as:

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and where drain current of memory cell 1.

represents the differential

After clock phase

Assuming that the output stage (represented in Fig. 4.22 as a simple current mirror) is ideal, the output current of the integrator is given by

From (4.97), (4.98) and (4.99), and using the approximation given in (3.121), it can be derived that the output current of the integrator is

where

Note that, assuming that simplified into:

the above expression can be

Thus, the analysis of an SI integrator formed by memory cells with non-linear settling error can be accomplished considering an integrator formed by memory cells with linear settling errors whose input signal is equal to (4.102). The equivalent distortion at the integrator input can be estimated by analyzing the harmonic content of such an expression. For this purpose, let us assume that the input current is a sinusoidal signal of amplitude and frequency In this case, the output current of the


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integrator will be a periodic signal, with the amplitude of its fundamental harmonic approximately given by:

where stands for the transfer function of the integrator degraded by the linear settling error and evaluated in On the other hand, we will suppose that the output of the integrator can be approximated by its first harmonic, so that

Substituting (4.103) and (4.104) in (4.101) and performing a Fourier series expansion, it can be shown that the third-order harmonic is

where

The amplitude of the third-order harmonic at the integrator input derived from (4.105) is

For

and

the above expression can be approximated by:

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The amplitude of the third-order harmonic referred to the integrator output can be obtained by multiplying (4.108) by the module of the integrator transfer function,

The third-order harmonic distortion referred to the integrator output is calculated by dividing the above expression by giving

The above expression has been validated by time-domain simulation. Fig. 4.33(a) represents against for The effect of the cell bandwidth on the harmonic distortion of the integrator has been considered by changing The effect of is illusvs. trated in Fig. 4.33(b) by showing for for different values of

4.7.2.2 Harmonic distortion in SI resonators due to the settling error Let us consider the LDI-loop resonator shown in Fig. 4.25. In the following analysis it will be assumed that the integrators which form that resonator are implemented as in Fig. 4.22 and that they are ideal except for the non-linear settling error. From (4.100) and (4.102) it can be shown that the finite-difference equations which govern the behaviour of the resonator are:

where and are respectively the input and the output of the first and the second integrators in the loop, and and represent the corresponding non-linear


terms, respectively given by:

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256


Assuming that solving for in (4.113) and substituting it in (4.112), results in the following difference equation:

where

Substituting (4.114) and (4.115) into (4.117) and assuming

yields:

where

The equivalent harmonic distortion at the resonator input can be obtained by analyzing the harmonic content of the above expression. Hence, assuming that is a sinusoidal input with amplitude and frequency the output of the resonator will be a quasi-sinusoidal signal (except for harmonic distortion), whose amplitude can be approximated by.

Thus, for the following analysis, the output current will be approximated by (4.85). Therefore, solving in (4.113), substituting it in (4.119) and performing a Fourier series expansion, it can be shown that the third-order harmonic signal at the resonator input is approximately given by:

†13.

represents either

or

or


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and where has been assumed. From the above expression, the amplitude of the third-order harmonic at the resonator input can be derived, given by:

The harmonic distortion at the resonator output can be obtained by multiplying the above expression by the resonator gain (evaluated at 3 ) and dividing the result by This yields

where The above analysis has been validated by time-domain behavioural simulation. For this purpose, the resonator in Fig. 4.25 was simulated considering zero output conductances and ideal switches. Hence, the only deviation from ideal behaviour is caused by the settling error. Fig. 4.34 shows the third-order harmonic distortion at the output of the resonator as a function of the linear settling error, for different values of This simulation was done by changing the small-signal transconductance, of the memory transistors when clocked at for and Note that, as also happens with static errors – see Fig. 4.29 – the harmonic distortion does not increase with because the open loop gain of the resonator is also attenuated. Observe that, although simulated behaviour is well predicted by theory, their differences become larger as increases since for the analysis it was assumed that

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4.7.2.3 Harmonic distortion in SI fourth-order

due to the settling error

Let us consider now the fourth-order shown in Fig. 4.30. For the analysis that follows it will be assumed that memory cells which form the modulator are ideal except for the settling error. Assuming that the quantization error is an additive, white noise source, in Section 4.7.1.4 it was derived that the amplitude of the first resonator output relates to the amplitude of the input signal, by the expression (4.92). The third-order harmonic distortion at the modulator output (equal to that at the modulator input) can be obtained by substituting (4.92) into (4.122), assuming that and dividing by This yields:

which, due to the oversampling frequency.

practically does not depend on the input

The third-order intermodulation distortion can be derived from (4.96) and (4.124), giving:

Non-Ideal Performance of Switched-CurrentBandpass

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The above expression has been validated by time-domain simulation. This is demonstrated in Fig. 4.35(a) by representing as a function of for different values of and for and

†14.The simulation was carried out by varying

in such a way that 0.1 %
3%, both expressions converge. However, for practical cases, that is for 130 in the ideal case. However, in the real case, is smaller than that shown in (6.1) as a consequence of the influence of SI errors on the quantization noise shaping. Therefore, following the same procedure as in Section 4.4.3, it can be shown that the is degraded by the non-idealities of SI circuits as:

where

and all error terms have the same significance as that described in Chapter 4. Fig. 6.1 displays the data obtained with (6.2) by making all errors equal to an error bound named It can be seen that even for the AM requirements cannot be achieved for all values of M. The use of a single loop 1-bit fourth-order (L = 2) relaxes the design specifications. According to (1.36) the ideal DR for such an architecture is:

In the presence of SI errors, it can be derived from (1.10) and (4.58) that

Fig. 6.2 represents as a function of M. Observe that in the ideal case the use of a is not necessary as compared to the because is much larger than that required for AM digital radio receivers. However, in practical cases the use of instead of is advan-

Practical IC Implementations

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tageous because it allows us to relax the design requirements. Thus, by forcing all errors to be below , the AM specifications are fulfilled as Fig. 6.2 demonstrates. The above reasons have motivated us to design a IC which copes with AM digital radio requirements. On the other hand, in order to experimentally verify the conclusions given above, a was also implemented. Fig. 6.3(a) shows the z-domain block diagram of the It has been obtained by applying a transformation to the second-order lowpass

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modulator of Fig. 6.3(b). As stated in Chapter 1, such a transformation keeps the stability properties of the latter and allows us to exploit the knowledge available for the lowpass modulator in order to design the bandpass modulator. Observe that the architecture in Fig. 6.3(a) is based on LDI-loop resonators. As was discussed in Chapters 2 and 4, this resonator structure is advantageous as compared to the others (FE-loop and delay-loop) because it remains stable under changes in the scaling coefficients – the reason why we have adopted it for our implementations. On the other hand, the scaling factors of the modulator have been optimized to obtain a similar signal range for both resonators, as it is shown in the histogram of Fig. 4.4, giving:

Fig. 6.4(a) shows the architecture of the As in the case of the fourth-order one, the second-order modulator has also been obtained by applying a to an In this case it was derived from the first-order lowpass architecture shown in Fig. 6.5(b). As was mentioned above, the second-order architecture is implemented for test purposes. For commercial applications, this prototype presents a tonal behaviour in its output spectrum as does the original first-order lowpass modulator. As is well-known, in this class of modulators, both the input signal and the quantization noise are correlated. This results in a non-white quantization noise spectrum. For second-order bandpass modulators the same phenomenon occurs. This is illustrated in Fig. 6.5(a) by displaying the ideal spectrum of the modulator in Fig. 6.4(a). In the case of the quantization noise can be assumed to be white as Fig. 6.5(b) illustrates.


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6.3 Switched-current implementation 6.3.1 Memory cell 6.3.1.1 Design considerations As stated in Chapter 4, the resolution of SI bandpass modulators is mainly limited by memory cell errors: and In addition to these errors, non-linearities in the memory cell and thermal noise also limit the resolution of the modulator. Chapter 3 described the circuit techniques for reducing Among them, there are two structures which have been extensively used in the reported SI ICs. One of them, shown in Fig. 6.6(a), is the regulated-cascode SI memory cell [Toum90b], which reduces the output conductance of the simple cell as shown in (3.43). The other structure is the regulated folded-cascode memory cell [Gold94][Zele94], shown in Fig. 6.6(b), which increases the input conductance of the simple cell as in (3.45). Both topologies employ local feedback either to increase the output resistance or to decrease the input resistance. However, the actual output resistance of the former is constrained by that of the bias source which is connected in parallel to the output resistance enhancement. On the contrary, the bias source of Fig. 6.6(b) can be realized through a simple PMOS transistor, thus increasing the voltage range [Gold94].

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Another main limitation of SI circuits is the charge injection error This nonideality was described in detail in Chapter 3 as well as the circuit strategies reported to reduce it. The most popular one is the memory cell [Hugh93c], shown in Fig. 6.7, which has been successfully used in a large number of applications [Hugh96][Tan97]. However, as was demonstrated in Section 3.3.3.4, this type of memory cell is not well suited for When the fine memory transistor Fig. 6.7) is loaded, the signal is compared to the coarse memory in Fig. 6.7). In the input signal is not stationary since it is located at a quarter of the sampling frequency, thus causing the fine memory to sample not only the error components from the coarse memory, but also the signal change itself. Hence, unless a Sampling-and-Hold (S/H) is placed at the front-end of the modulator, the advantages of the memory cell will be lost. For the reasons mentioned above, we will employ other circuit strategies consisting of the combination of fully-differential circuitry and dummy switches, which, as demonstrated in Fig. 3.18(b), achieves a notably reduction of On the other hand, a regulated folded-cascode topology will be used to reduce


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Because of the local feedback at the input node (see Fig. 6.6(b)), the regulatedfolded cascode memory cell exhibits a third-order dynamics with a single pole at

and a pair of complex conjugate poles whose values depend on the transconductances and on the intrinsic capacitances of transistors (see Fig. 6.6(b)) as:

where

Note that a first-order dynamics can be obtained by increasing For this purpose an extrinsic MOS capacitor connected to the gate of the memory transistor is used to create a dominant pole at

thus controlling the error due to incomplete settling, by properly sizing the memory transistor. In addition, contributes to reduce the common-mode chargeinjection error. Fig. 6.8 shows the entire schematic of the memory cell. It is a fully-differential version of the one shown in Fig. 3.7(b) including the Common Mode FeedBack circuit (CMFB) [Duqu93]. The local feedback stage is formed by transistors the memory transistors are and the current source transistors are The steering switches are PMOS while the memory switches are NMOS with minimum size; the latter include dummy devices which, in combination with fully-differential circuitry, attenuate the charge injection error. Capacitors are realized with NMOS transistors. The top plate of this capacitor is the gate of the transistor. The

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bottom plate is made by connecting the drain, source and substrate terminals.

6.3.1.2 Memory cell performance The memory cell has been designed using the guidelines given in the previous section to attain the specifications required for AM digital receivers and, at the same time, to optimize the trade-off between speed and dynamic range, for the maximum sampling frequency needed to convert signals in the commercial AM bandwidth. For this purpose, the circuit in Fig. 6.8 was automatically sized using FRIDGE, a transistor-level optimizer [Mede95], which uses statistical optimization techniques based on simulated annealing [Laar87] to explore the design space in order to find an optimal cost function. This cost function, which is automatically formulated by the tool on the basis of the objectives given by the designer, is evaluated through electrical simulation of the cell using HSPICE [Meta88]. For the design of the cell in Fig. 6.8, the most significant specifications given to FRIDGE were the following: To keep all transistors in the saturation region over the entire signal range with a saturation margin of 0.1 V, except for the memory transis-


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tors, M1 and M2, for which the margin was 0.5V. To minimize power consumption. To reduce memory cell errors below 0.1% (according to AM requirements). To reject common mode signals with a maximum amplitude of of the differential mode signal range) in the AM bandwidth. To create a dominant pole so that

(50%

in the AM bandwidth.

To reduce the thermal noise in-band power below –60dB in the AM bandwidth. In order to fulfil the above specifications, the design space was explored by the optimizer by performing both dc and ac analyses with HSPICE. As a result, the sizes shown in Table 6.1 were obtained. The resulting bias currents are: and (realized with a NMOS transistor). In order to demonstrate the performance of the cell, SI errors have been extracted from electrical simulations as described below.

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1. Finite output-input conductance ratio error, The finite output-input ratio error is defined as the ratio of two parameters: the input and the output conductances. To characterize said parameters we made two simulations in HSPICE. In the first one, the memory switches of the cell were closed and the steering switches were open. A dc differential input current was applied. Fig. 6.9(a) displays the differential input voltage as a function of the input amplitude. Note that the input resistance, is given by the slope of this curve (in the linear range). This gives Table 6.2 shows the small-signal transconductances and the drain-source conductances for transistors and Substituting those values in (3.45) we obtain which agrees with the simulated data.


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For the characterization of the static output conductance†2, we simulated the memory cell with all switches open. A differential input voltage was applied at the input nodes of the cell. As a consequence of the finite output conductance, a non-zero current flows across the input voltage source. The output conductance is obtained by performing the derivative of that current with respect to the input voltage. This procedure gives us the value of the output conductance at the operating point Repeating that simulation for different values of the memory transistor drain current we can obtain the dependence of the output conductance on the memory transistor drain current. This is displayed in Fig. 6.9(b). From the above simulations we obtain that the finite output-input conductance ratio error (at the operating point) for this memory cell is given by According to (3.27), this gives for a modulation index, which is approximately equal to the simulated value, and is well below the maximum harmonic distortion required for AM digital radio receivers (60dB). 2. Charge injection error, We have characterized the charge injection error in the memory cell by computing (using HSPICE) the difference between the differential gate-source voltage at the end of the sampling phase and that at the beginning of the hold phase. This simulation was repeated for different values of the memory transistor drain current. Fig. 6.10(a) represents this error as a function of the differential gate-source voltage. This voltage error causes an error in the memorized drain current and, hence, in the differential output current. To characterize the latter, we connected the memory cell to a voltage-controlled voltage source whose level was set at the same voltage as that

†2. Strictly speaking, the output conductance is composed of two parts: a static conductance, due to the channel length modulation effect and a dynamic conductance, due to the capacitive coupling between the drain and the gate of the memory transistor. However, in this cell, the dynamic part can be considered negligible as compared to the static part because

350


in the sampling phase. Thus, the finite output-input conductance ratio error was removed. Fig. 6.10(b) plots the current error as a function of the differential input current. In both graphs, the charge injection error can be obtained by computing the slope of the regression line. This results in which according to (3.75) yields for 3. Transient behaviour:

and

Transient behaviour can be characterized by analyzing the step response of the memory cell (on its sampling phase). Fig. 6.11(a) shows the transient response of the memory cell for different input amplitudes showing a first-order dynamics. The settling error can be computed as the difference between the memorized drain current and the corresponding input current corresponding to a given acquisition time†3. Fig. 6.11(b) represents as a function of These data are compared to those predicted by theory†4 showing a good agreement. Observe that, for the sampling frequencies required to convert AM signals – from to – the settling error is negligible (below 0.05%). As discussed in Section 3.4.5.2, for these values of the settling error, the harmonic distortion is only significant if there is not an S/H at the input of the memory cell. In order to evaluate this effect, the memory cell was simulated considering a †3. The acquisition time is defined as the time period in which the memory switch is closed. †4. Theoretical data have been obtained by using the non-linear model for the settling error detailed in Section 5.3.1.2.


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sinusoidal input signal of amplitude and frequency Fig. 6.12 represents vs. in the AM bandwidth. As will be demonstrated experimentally, this value of the harmonic distortion is enough to achieve the requirements for digital AM radio receivers. Concerning the additional capacitors used to improve the settling behaviour (see Fig. 6.8), Table 6.3 shows their worst case values and the associated values of the pole and the pole of the memory cell under process variations. These shifts do not influence the settling behaviour.

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4. Thermal noise Apart from the previous memory cell errors, the ultimate limiting factor in practical realizations of SI modulators is thermal noise. In order to evaluate the thermal dynamic range (represented by the parameter defined as the ratio between the signal power and the thermal noise power, the noise Power Spectral Density (PSD) of the memory cell is calculated as:

where

and

is the fraction of time in which the noise is connected to the output of the


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memory cell (in our case is the sampling-and-hold function; and is the equivalent noise bandwidth, which for the memory cell in Fig. 6.8 is The total thermal noise power lator input bandwidth

is obtained by integrating (6.12) into the modu-

where M represents the oversampling ratio. Thus

In

can be calculated as

our

design,

This gives and which clearly does not limit the performance of the modulator. Finally, the simulated performance of the memory cell is summarized in Table 6.4. This table shows a minimum value of the Common Mode Ratio Rejection (CMRR) of 30dB, which, according to behavioural simulations, does not affect the performance of the modulador.

6.3.2 SI Integrator The integrator is the next block in the modulator design hierarchy. Fig. 6.13 shows the schematic of the input stage. It is based on the memory cell of Fig. 6.8 and formed by two Regulated-Gate Cascode (RGC) groups. The design criteria for this block were the same as those followed for the memory cell. Thus, the sizes of the integrator, shown in Table 6.5, are the same as those used for the memory cell except for those of This is intended to compensate the increase of the Q -factor of the conjugate complex poles, given by

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355

where and are those in (6.9) and (6.10) respectively. Observe that represents the equivalent capacitance at the input node. In the integrator, that capacitance is increased as a consequence of the connection in parallel of two memory cells. This forces Q to rise as compared to that of the memory cell. To compensate this effect, was increased. In addition to the change in the size of transistors those transistors acting as bias current sources, i.e, were resized in order to supply current to two memory transistors instead of one as in the memory cell. These differences in the sizing of the integrator as compared to the memory cell cause both the input and the output conductances to change. Their values are given in Table 6.6 as well as the corresponding value of It is actually the value of which we will employ to analyze the effect of SI errors on the performance of the bandpass modulators reported in this chapter. Concerning the thermal noise, the PSD of the integrator noise is given by:

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where

For this design, From (6.15) we obtain to fulfil the modulator specifications.

and which is large enough

Table 6.6 summarizes the simulated performance of the integrator. In addition to


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the mentioned errors, there are others associated to the integrator output stages. Those stages have been implemented by simple current mirrors. Fig. 6.14 shows the entire schematic of the integrator including the output stage. As we will see in the next section, for the implementation of the resonators three different scaling coefficients are required with gains: 0.5, 1 and 2. The output resistances corresponding to these stages are given in Table 6.6. The ratio between these output resistances and the switch-on resistance, of the current steering switches causes an additional error as was described in Chapters 3 and 4. In this case, current steering switches are realized by means of PMOS transistors of so that which, as can be derived from the data in Table 6.6, bounds the scaling errors as: and which comply with AM radio receiver requirements. As an illustration, Fig. 6.15 shows the transient response of the integrator. The input signal was a sinewave of amplitude and frequency 200kHz. The sampling frequency was 4MHz (in the middle of the AM bandwidth).

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6.3.3 SI Resonator The implementation of the integrator gains requires additional scaling stages realized with simple current mirrors. As stated in the previous section, three different gain stages were realized with gains 0.5, 1 and 2. The required gain inversion is straightforward because of the fully-differential nature of the circuits. Fig. 6.16 shows a complete schematic of the resonator block. It is composed of


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two fully-differential regulated-folded cascode LD integrators, each of them containing a CMFB circuit and the corresponding output stages. Note that the integrator output nodes are connected to a low impedance node, called while the steering switches are opened (not connected to other blocks). Fig. 6.17(a) shows a simulation (HSPICE) of the impulsive response for the resonator of Fig. 6.16. The input signal was a pulse function of amplitude and duration equal to with being the sampling period. Ideally, the resonator output should repeat the values in the ranges periodically, with k being the gain of the resonator. Fig. 6.17(a) displays the transient evolution of this block with gain The sampling frequency was 1MHz – low enough to guarantee the complete settling of the signals during the sampling phase. Thus, the errors presented in that simulation were: output-input conductance ratio error, charge injection and scaling errors. The discrete-time output response (dots in Fig. 6.17(a)) is also displayed in this figure. As a consequence of these non-idealities, the impulsive response deviates from the ideal one as shown in (4.50). Using the System Identification Toolbox from MATLAB [Math91f], we fit the discrete-time output data obtained from HSPICE to the following Z-domain transfer function:

From the fitting we obtain and On the other hand, from (6.19) and (4.50) we have that the theoretical values for these scaling coefficients are

Substituting the values of the errors of Table 6.6 in (6.20) results in: and which agree with those obtained from the simulated data, From (4.60) we obtain that there is an error in the resonant frequency, and hence in the notch frequency, of the modulator of This

360



361

should be taken into account in practice, because the maximum value of SNR is achieved at the real position. For this reason, the input signals should be placed at that frequency, not at a quarter of the sampling frequency – the ideal notch frequency. In order to quantify the effect of the settling error, Fig. 6.17(b) shows the impulsive response of the resonator for a sampling frequency of At this sampling frequency, the settling error is increased from 0.025% (at clock frequency 1MHz) to 0.25%. As a consequence of the incomplete settling, the transient response is severely degraded as compared to that shown in Fig. 6.17(a). In particular, it can be seen that the output amplitude is quickly attenuated. Following the same procedure as before, we obtain and which agrees approximately with the theoretical results obtained from (6.20): On the other hand, due to the increase of and and the notch frequency error increases as well up to

6.3.4 1-bit Quantizer Fig. 6.18(a) shows the block diagram of the 1-bit quantizer, made up of a regenerative latch [Brac94b] and an RS flip-flop which maintains the output value in the phase in which the resonators are fedback, The regenerative latch operates as follows. Since the input switches are PMOS, currents are sampled in the complementary phase developing a small voltage difference through the NMOS switch. When the NMOS switch opens at (see Fig. 6.18(b)), the current which flows through it cuts off abruptly, and the latch impedance changes from positive to negative (due to the positive feedback). Consequently, depending on the sign of the small difference of stored voltage, the latch output nodes (R and S nodes in Fig. 6.18) will go either to the positive or negative rail. A fast comparison is thus obtained with low input current levels. For design purposes we will first consider the balanced case with ideally matched circuit elements. In the sampling phase, a positive impedance is required, so a necessary condition is:

where

is the effective transconductance of the inverter,

is the total output con-

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ductance and

363

is the on-resistance of switch

In our design, we obtain Thus, the condition given in (6.21) is satisfied. Fig. 6.18(b) shows a layout-extracted simulation of the latch phases for As can be seen from these waveforms, this is a very conservative design because the overlapping time between the two clock phases, is approximately a half clock period. Ideally, this latch operates correctly if the NMOS switch opens at the beginning of clock phase thus corresponding to a small value of However, in practical cases, as clock phases are internally generated, the time instants at which they are either falling or rising are subject to multiple perturbations mainly caused by current glitches. In order to prevent these perturbations from corrupting the latch operation, a large value of was chosen in relation with the sampling period. Other important considerations in the design of the latch concern the influence of mismatches among their components. Because of errors in the transconductance, output conductance and load capacitance, the static resolution is limited by

while the dynamic resolution is bounded by

where

is the common mode input current.

As an illustration, let us consider the response of the quantizer to an input signal of triangular shape. Fig. 6.19(a) and (b) show the layout-extracted simulations for the input and the output of the quantizer, respectively. As a consequence of the mismatch errors, the performance of the quantizer is degraded by the hysteresis. This is illustrated in Fig. 6.19(b) by plotting the output voltage against the input current amplitude. A 0.7% hysteresis is observed. This is not problematic because the power

364


of the in-band noise remains virtually unchanged for hysteresis as large as ten percent of the full-scale converter input [Bose88b]. 6.3.5 1-bit D/A Converter Fig. 6.20 shows the schematic of the 1-bit D/A converter used in the modulator, consisting of a current source controlled by the comparator output. The stacked cascode current mirror has been chosen because it resembles the structure of the memory cell. The two output currents, with values , change


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the direction of the flow depending on the sign of the comparator output. PMOS switches are used due to the common-mode input voltage required in the integrators. The guidelines for the design of this circuit were to reduce its output conductance in such a way that the associated output-input conductance ratio error is negligible. The resulting output resistance is for the PMOS current mirror and for the NMOS current mirror. As the steering switch-on resistance of the integrator is the resulting associated scaling errors are and respectively, which are low enough to fulfil the modulator specifications. On the other hand, the offset figure is well below the limit that guarantees correct modulator operation. 6.3.6 Complete schematic of the modulators Fig. 6.21 shows a conceptual schematic of the modulators. Observe in this diagram that the LD integrator blocks have three types of terminals: input terminals, output terminals and a clock terminal. The latter represents the clock phase in which the input signal is sampled.

6.4 A high frequency current mode buffer The speed advantages of the SI circuits detailed in previous sections are only fully realized if the input currents are generated on-chip. Otherwise, the circuit dynamics may become severely degraded due to the parasitic time constants at the

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chip bonding pads. Commonly, designers of HF SI chips give no details about the interface circuitry which can be used to overcome this problem [Brac96]. A few interface circuits reported in literature have single-ended output [Toum94]. In this section we will describe a CMOS current mode buffer which interfaces single-ended off-chip currents into on-chip fully-differential HF SI circuits.

6.4.1 Illustrating the Speed Degradation in SI Interfaces Consider the SI second-generation memory cell of Fig. 6.22(a). We have implic-


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itly assumed that this memory is on-chip and that the capacitance of the driving stage is negligible as compared to the gate-to-source capacitance of the memory transistor During phase (sampling phase) this capacitance is charged with a time constant Assume now that the memory cell is placed at the chip front-end, and we use the simplest possible interface: an off-chip linear resistor, with a resistance much larger than (see Fig. 6.22(b)). Consequently, the time constant changes from to Because the pad equivalent capacitance is typically large as compared to the inner capacitance, the high-frequency behaviour of the memory cell becomes degraded. Similar problems are observed in other enhanced SI memory cells, including those with low input impedance – like the one shown in Fig. 6.8. Consider now Fig. 6.22(c), where a current buffer has been incorporated at the front-end of an SI circuit. The input current is first processed by the buffer and then the resulting current is applied to the SI circuit. From Fig. 6.22(c) the following transfer function is found,

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from where a condition is derived to render the influence of this capacitance negligible,

where is the input signal period. This constitutes a basic specification for the design of the buffer. Other specifications refer to the SNR and the output swing, which must be in compliance with the SI circuit. In the case of the described in this chapter, the maximum input frequency is 1.6MHz (AM), the resolution is 60dB and the output swing is 6.4.2 Circuit Description Fig. 6.23 shows the schematic for the proposed current mode buffer. It has a fully-differential structure, but can be used either with single-ended input or with differential input. If voltage-to-current conversion is needed, it can be implemented using an external resistance connected to any of the two input nodes. This block has three major stages: the input stage the output stage and the Common Mode Feed Back stage (CMFB) As Fig. 6.23 shows, the input stage incorporates a local input feedback to obtain a very low input resistance, given by

This is needed to satisfy (6.26) under the constraint imposed by the value of the


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bonding capacitance – not controllable by the designer. Note that is controlled by changing either the transconductance of transistor or the inverter gain This extra degree of freedom is convenient because as increases, the output thermal noise PSD, given by

increases as well. The output stage scales the input current by a factor of either 0.5 or 1.0 depending on whether the input current is single-ended or differential, respectively. The CMFB stage operates as follows. Assuming a positive (negative) input common mode flowing into the input nodes, then gate voltage increases (decreases) causing drain current to increase (decrease), thus subtracting (adding) the common mode current to the input and output stages. The most important parameter in the design of this stage is, hence, the common mode gain given by

Following the guidelines given above, we have designed this buffer. Table 6.7 shows a summary of the simulated performance (it also includes experimental results which will be discussed later). Note that a high output resistance is not needed because the SI memory cells used are regulated folded-cascode.

6.5 Practical design issues In the earlier sections, the design of basic SI building blocks was described. The-

370


oretical guidelines were given and layout-extracted simulations illustrated their performance. Those blocks have been used for the implementation of the modulators in this chapter. In addition to those theoretical considerations, this section details some practical aspects regarding the physical realization of the On the one hand, a clock phase generator circuit has been designed and implemented inside the chips. This circuit generates all clock phases needed for the correct operation of the modulator blocks. On the other hand, the combination of both analog and digital circuitry on the same chip requires special care in the layout generation process. If not, the switching noise from the digital circuitry (clock phase generator and DAC) may be coupled to the analog nodes via the parasitic capacitance, power supplies, and the own substrate. 6.5.1 Clock phase generator circuit The use of non-overlapping clock phases is mandatory in most SC circuits and first-generation SI circuits. However, in second-generation SI circuits, transient current spikes appear during the non-overlapping time interval. These spikes are due to internal node changes from a low impedance state to one of high impedance during the non-overlapping period of the clock [Sinn94][Quei94]. Several clocking strategies have been published in order to reduce the levels of glitching [Sinn94][Craw94][Tan97]. The basic idea consists of guaranteeing that steering switches are connected to a low impedance node all the time. This can be achieved by using the clock phase diagram shown in Fig. 6.24 [Tan97].


371

Non-overlapping phases and control memory switches and overlapping phases and are used to control current-steering switches. It can be seen from Fig. 6.24 that during the non-overlapping time periods of phases and either' or are switched on. Let us consider the connection of two memory cells in series shown in Fig. 6.25. Note that the input voltages of both cells and are connected to a low impedance node during all clock phases thanks to the use of the clocking diagram shown in Fig. 6.24. Fig. 6.26 shows the schematic of the clock phase generator implemented in our chips. Observe that, in addition to the mentioned clock phases, this circuit generates others required for the circuits included in the modulators. On the one hand, complementary versions for and are required to control the PMOS steering switches. We call these clock phases and respectively. On the other hand, additional clock phases will be needed to control dummy memory switches. We call these phases and

372


As an illustration, Fig. 6.27 shows the transient evolution of all the mentioned clock phases. This figure represents the layout-extracted simulation of the clock generator for a 6.7MHz clock frequency (maximum in the AM bandwidth).

6.5.2 Layout considerations The operation of an electronic circuit may be severely degraded as a consequence of the fabrication process. This fact is extremely important in analog circuits in which technology parameter variations may fully destroy their ideal performance. This degradation can be partially avoided by following some practical recommendations during the layout synthesis process. For this purpose, a large number of layout strategies for analog circuits has been proposed in literature [Tsiv96]. On the other hand, when both analog and digital circuits are integrated on the same chip, the high-speed switching signals provided by the digital circuitry create interferences on the sensitive analog nodes. This interference is often referred to as “switching noise” or simply digital noise [Tsiv96][Lama92]. This noise is mainly coupled to the analog circuitry via the power supplies and the substrate. This is the


373

case of in general, and of in particular. The coupled noise may be disastrous for the analog part of the modulator, unless the designer takes some precautions during the layout phase [Lama92][Tsiv96][Tan97]. For the design of the chips in this work, the following precautions were taken into account, when possible, during the layout process:

1. Separate digital and analog power supplies As mentioned above, power supplies are one of the paths for the switching noise to couple the analog circuitry. To avoid this interference, it is extremely important to separate the analog power supply from the digital one. We used both separate bonding pads and supply lines for the digital and the analog part of the chip respectively. This is illustrated in Fig. 6.28.

2. Partitioning of the circuit It is critical to avoid the proximity of analog and digital circuitry. When that is not possible, it is very important to place well and substrate contacts between the corresponding analog and digital interfaces. Special care must be put on the distribution of the clock signals. The best way to do this is to route them as buses. This is illustrated in Fig. 6.28. The distance between the buses should be larger than the minimum distance required in the given process technology in order to decrease the coupling between the clock signals. Observe that it is critical to prevent the digital signals in general, and the clock buses in particular, from crossing analog signals. This is achieved by using the floorplanning shown in Fig. 6.28.

3. Shielding of sensitive circuits The shielding of the memory transistor gates is recommended in order to avoid the coupling of clock signals through the intrinsic gate capacitance of the memory transistors. For this purpose we placed guard rings surrounding both SI memory cells and integrators. These guard rings were composed of two parts. One part is of the -well type and the other one is of the -well type. The former is placed closer to the circuit it guards than the latter, as Fig. 6.28 shows.

4. Basic analog layout recommendations In addition to the mentioned precautions, we have applied the basic analog layout recommendations for those parts of the circuit that have to be matched. Among others, the most important rules were: the use of unit transistors, making all transis-

374


tors matched in order to drive the drain current in the same direction, placing them as close as possible, using common-centroid techniques or similar techniques, etc. As an illustration, Fig. 6.29 shows the entire layout (without bond pads) of the fourth-order described in this chapter. In this figure the most important recommendations detailed above are pointed out as well as the different components of the chip.


375

376


6.6 Experimental results Two chips were fabricated in a CMOS double-metal single-poly technology. Fig. 6.30(a) shows a microphotograph of the prototype. It occupies a active area without including the bonding pads. The whole silicon area with the pads is . The circuit is biased with a 5V power supply and its power consumption is of 60mW when clocked at 10MHz. Fig. 6.30(b) shows the package diagram of the chip. Note that, due to the large capacitances and bond wire inductances, the digital noise is coupled to pads and pins unless the designer makes a correct pin assignment. It is important that pins carrying sensitive signals and those carrying noisy signals be as separate as possible [Lama92][Tsiv96][Tan97]. This is shown in Fig. 6.30(b) where digital pins are on the opposite side of the analog pins.


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Fig. 6.31(a) shows a microphotograph of the test chip. It includes the following circuits: a current mode buffer, an SI LDI -loop resonator and an It occupies a active area without including the bonding pads and the whole area with the pads is The circuit is biased with a single 5V power supply. Fig. 6.3 l(b) shows the package diagram of the chip. We have taken the precautions described above to separate both the analog and digital pins. Note that, in addition to the current mode buffer itself, other two ones have been integrated, which will allow the testing of both the SI resonator and the

6.6.1 Measurement set-up As stated in Section 6.5.2, during the layout process several points were taken into account in order to avoid digital noise to “contaminate” sensitive analog signals. During the measurement phase the experimental set-up requires an electromagnetic interference-free environment as well. Otherwise, all precautions adopted in the layout phase will be useless. Several techniques have been reported [Lama92] which are being used in industrial test manufacturing and applications of high resolution, high speed A/D converters. In addition to these techniques, special instrumentation is

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required to capture and process the measured data. In this section, both the measurement set-up and the instruments needed for the experimental characterization of the chips treated in this book are described in detail.

6.6.1.1 Mixed-signal printed circuit board External electromagnetic interferences can be injected into the chip through three natural mechanisms [Lama92]: (a) Direct coupling: this interference mechanism is caused by unwanted currents in the ground-plane or other return paths. If these currents are either from the digital part of the chip or from other digital chips, switching noise will be coupled onto the analog lines. (b) Inductive coupling: caused by magnetic fields which induce a noisy current into the signal traces. The magnitude of that noisy current grows with the circuit loop area and with the proximity to the magnetic field source. (c) Capacitive coupling: generated by the parasitic capacitors which increases the crosstalk between traces while the line separations are reduced. In order to reduce these effects, the authors in [Lama92] proposed several techniques for the fabrication of a Printed Circuit Board (PCB) for testing high resolution, high speed A/D converters. These techniques can be summarized as follows: 1. Divide the PCB into an analog area and a digital area. Thus, all analog components are placed in the former and all digital components are placed in the latter. Mixed-signal chips (like ours) must be placed so that analog pins will stand in the analog area and digital pins will be placed in the digital area. 2. Separate digital and analog ground planes. They should be separated with a gap larger than 1/8" and should be connected only at one point. This technique minimizes the noisy return currents. 3. Place bypassing and decoupling capacitors as close as possible to the IC pins. It is recommended to use two types of capacitors: a large electrolytic one and a small ceramic one. The latter should be placed closer to the pin than the former. 4. Keep digital signal traces, especially the clock signal, as far away as possible from analog input and supply pins.


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5. Do not overlap analog-related and digital-related planes in two-layer PCBs. We fabricated one two-layer PCB for each chip following the recommendations above. Fig. 6.32(a) shows the photograph of the PCB for the characterization of the It shows the separate grounds, decoupling capacitors, etc. All the components are shown in the schematic of Fig. 6.32(b). Fig. 6.33(a) shows the PCB for the characterization of the test chip. Many of the electronic components are the same as in the case of the PCB used for testing the SI Separate digital and analog areas are also implemented in this PCB.

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Observe that, compared to the PCB of Fig. 6.32, additional circuitry is placed on the right hand side of the PCB in Fig. 6.33 (analog area). This circuitry is needed for the characterization of both the SI resonator and the current mode buffer. As illustrated in the schematic of Fig. 6.33(b), two types of operational amplifiers – the high-speed amplifier AD844 and the differential amplifier AD830 – are used to implement the I/V conversion of the output for both the buffer and the resonator. First, the output currents provided by those blocks are sensed through a virtual ground realized with AD844 implemented as a second generation current conveyor with gain +1 (CCH+) [Svod91]. Finally, the AD830 is used to amplify the difference of the AD844 output voltages. 6.6.1.2 Instrumentation and test set-up Fig. 6.34 shows the measurement set-up used to test both the and the building blocks. Fig. 6.34(a) illustrates the set-up for the test of the modulators. The input signal is applied using the single-ended sinusoidal signal source HP3314A through an off-chip resistor (for V/I conversion) connected to the input pad (see Fig. 6.32(b)) and then to the on-chip current buffer. The circuit receives the clock signal and other control signals through the HP82000 digital data acquisition unit. The output data are captured at the clock-signal rate by the HP82000 and transferred to a work-station for post-processing using MATLAB [Math91a]. The work-station controls via HPIB both equipments, the HP82000 and the HP3314A. This automatizes the process of capturing output data, allowing us to obtain typical figures such us SNR against input level, SNR against sampling frequency, etc. The set-up described in the above paragraph is smoothly modified in order to test the current buffer and the SI resonator. This is shown in Fig. 6.34(b). As the output data are analog signals, they cannot be captured using the HP82000. Instead of that, we use other instruments: the mixed-signal HP54645D oscilloscope for the SI resonator and both the semiconductor parameter analyzer HP4145b and the network analyzer HP4195a for the buffer. These instruments are controlled by a workstation together with others providing input, control and supply signals to the circuit under test.

The output of both the current mode buffer and the SI resonator are differential signals. Thus, two operational amplifiers are required to capture them.

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6.6.2 Measured results 6.6.2.1 Current mode buffer As was mentioned above, this circuit was integrated in a test chip together with other building blocks needed to implement the The active silicon area occupied by the buffer is The circuit is biased with a 5V power supply and its power consumption is of 22mW. Table 6.7 summarizes measurements made using a single-ended input. Static measurements were realized with the semiconductor parameter analyzer HP4145b (see Fig. 6.34(b)). To obtain the dc input/output transfer characteristics, a single-ended dc current source was connected to one of the input pads of the buffer and its amplitude was varied over the entire range. Note that, using this input signal, a common mode of the same amplitude as the differential mode was applied. However, this configuration was used to test as well. The output current was sensed by connecting two ideal voltage sources at the output pads. Fig. 6.35 shows the measured dc input/output transfer characteristics. Both the differential mode and the common mode output currents are displayed by demonstrating the rejection of the latter. For the ac measurements, the buffer output current was tested using the circuitry shown in Fig. 6.33(b). The data were acquired at the output nodes of the AD844s in order to take full advantage of the high-speed capabilities of these operational ampli-

384


fiers. In this configuration, the AD844 features a 37MHz bandwidth; hence, it can be expected to dominate the high-frequency response of the buffer. This is actually confirmed by the measurements realized with the network analyzer HP4195a. Fig. 6.36 shows an experimental Bode plot for a bonding pad parasitic capacitance of about 10pF (the whole parasitic capacitance in the experimental board). The measured -3dB frequency is the one of the current conveyor, 37MHz, thus confirming that the bandwidth of the buffer is larger (around 90MHz). 6.6.2.2 SI resonator As described in the introduction of this section, an SI resonator of gain was implemented in the test chip of Fig. 6.31 for testing separately. This resonator was tested on the PCB shown in Fig. 6.33 using basically the same circuitry for I/V conversion as the current mode buffer. Fig. 6.37 shows a conceptual schematic of the testing setup. The resonator output nodes are connected at the input nodes of two AD844s driven by an AD830 differential amplifier. In this configuration, the total gain is:


and the gain from the resonator output current,

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to the output voltage is:

Fig. 6.38 shows several impulsive responses at different clock frequencies in the AM bandwidth. The input signal voltage was a pulse of 40ms period and width. Note that, although the setup in Fig. 6.33(b) is suited for ac measurements up to 40MHz as demonstrated from the current buffer measurements, there are some limitations for using this acquisition system for capturing time-domain waveforms. The main limitation is the gain-bandwidth of both the AD844 and the AD830. Thus, if a high bandwidth is required, the gain of both the AD844 and the AD830 should be reduced so that the output voltage, is of the milivolt order, close to the minimum voltage scale of the HP54645D oscilloscope (10mV). Therefore, although the qualitative functionality of the resonator can be tested in the entire AM bandwidth (as shown in Fig. 6.38), the data acquisition from the waveforms (for quantitative evaluation) is subject to large scale errors if a low gain configuration is used. For the mentioned reasons, we will focus on analyzing by measurements the effects of static errors on the resonator behaviour when clocked at Nevertheless, as will be demonstrated in Section 6.6.2.3, dynamic errors do not affect the performance of the modulator up to frequencies beyond AM, and hence, no additional information can be obtained from measurements at the top of the AM bandwidth, (maximum frequency for the testing setup). At the high gain of the AD844 and the AD830 can be used without degrading the transient evolution. As illustrated in Fig. 6.39, the output amplitude is of the volt order. In this case, the values of the parameters in the measurement

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setup were the following:

Fig. 6.40(a) shows a measured impulsive response of the resonator, after capturing data, when clocked at The input signal is a pulse like that of Fig. 6.38 with a 2V offset (the value of the input voltage of the current buffer at the operating point) and the amplitude is 2V. From (6.29) and (6.31), this is equivalent to a current signal at the resonator input current whose amplitude is In order to analyze the effect of static errors, the bias current source of the regulated-cascode stage, (see Fig. 6.8) was varied. As demonstrated in Section 4.7.1.3, by increasing both the linear and the non-linear input impedance are raised (see Fig. 4.27), thus varying several errors: and which degrade the resonator impulsive response. Fig. 6.40 illustrates this by comparing two measured resonator impulsive responses corresponding to (Fig. 6.40(a)) and (Fig. 6.40(b)), respectively. In this figure, continuous line waveforms are the measured output currents (after V/I conversion) and the dots represent the sampled output data – one per clock period. This is best illustrated in Fig. 6.40(c). In order to quantify the influence of on the resonator performance, output data were collected with the mixed-signal oscilloscope HP54645D and post-processed using MATLAB [Math91a]. The Z-transform of those data series is the trans-

388


fer function of the resonator, which can be genetically written as shown in (6.19). In this case, coefficients and were extracted from the experimental data by using the System Identification Toolbox of MATLAB [Math91f]. Note that and are the most critical coefficients because they are directly related with the zeroes of For that reason, we will concentrate on the effect of and on said coefficients. Fig. 6.41 represents and as a function of for different values of Note that no significant variations are obtained from changes on thus indicating that for this input range (from to the effect of SI errors on the impul-


389

sive response of the resonator is dominantly linear. However, as will be demonstrated in Section 6.7, harmonic distortion appears at the output of the bandpass modulators as a consequence of increasing Another conclusion that can be derived from Fig. 6.41 is that is the main SI error responsible for the degradation of the impulsive response with in the experiments. Observe how both and degrade in the same way with This means that there is an SI error, presented in both coefficients, changing with According to (6.20), the only SI error that satisfies this condition is

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At the nominal conditions, i.e, for , the mean of and can be calculated from the data in Fig. 6.41 giving and However, in Section 6.3.3 it was obtained from (6.22) and also from the nominal condition HSPICE simulations that and . In addition to this discrepancy we have observed from the nominal condition HSPICE simulations that the impulsive response is not severely degraded up to However, the experimental impulsive response is degraded for almost the same value as that obtained in worst-case speed condition HSPICE simulations. Fig. 6.42 illustrates this by comparing worst-case speed condition HSPICE results with the measured MonteCarlo HSPICE simulations reveal that and with standard deviations of and thus indicating that in the worst- case speed conditions, simulation values approach measured values. Finally, to conclude this section, it should be mentioned that the knowledge provided by measured values of and allows us to extract other design parameters of the resonator such as the pole location and the resonant frequency. Fig. 6.43 shows the movement of the poles with in the Z-plane, and therefore with The variation of the position of the poles agrees with the theoretical prediction given in Section 4.4, where it was stated that influences both


the ratio of the poles (related to the quency.

391

through (2.70)) and the resonant fre-

This effect is best illustrated in Fig. 6.44 by plotting the resonant frequency, (the notch frequency of the bandpass modulators) as a function of For the nominal condition, we obtain This value is approximately the same as that measured for the second-order as we will see in Section 6.6.2.4. However, it is different from that obtained for the This is because, in this case, there is a cumulative effect of the SI errors from both the first and the second resonators.

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6.6.2.3 SI fourth-order bandpass

modulator

To test the modulator, the input signal is applied using the single-ended sinusoidal signal source HP3341A through an off-chip resistor (for V/I conversion) connected to the input pad and then to the on-chip current buffer (see Fig. 6.34(a)). The buffer included in the chip has the double function of isolating the modulator from the parasitics, and converting the single-ended external input current into a fully-differential one. After capturing the output bit streams with the HP82000, Kaiser 32768-point FFTs were performed using MATLAB [Math91a]. Fig. 6.45 shows two measured modulator output spectra when clocked at different sampling frequencies for the A/D conversion of signals centered on a commercial AM bandwidth. Thus, Fig. 6.45(a) shows the output spectrum for a sinusoidal signal of 488kHz frequency (minimum AM frequency) and a –6dB input (–6dB @488kHz), with a sampling frequency of 2MHz. Fig. 6.45(b) shows the modulator output spectrum for a -6dB@ 1.63MHz input tone (maximum AM frequency) when clocked at 6.67MHz. A correct noise-shaping is observed at both clock frequencies demonstrating the bandstop filtering applied to the quantization noise. The presence of out-of-band spikes suggests that the quantization noise is not a white noise.

Input level is defined as the input signal amplitude referred to the DAC output level.


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In the presence of non-linear errors, out-of-band tones can mix with the input signal and fall into the signal bandwidth, thus degrading the modulator performance. This is not critical in our circuit. To demonstrate this, the harmonic distortion at the modulator output has been measured at the maximum AM sampling frequency, 6.67MHz. The input signal consisted of two –7dB at 1.62MHz and 1.63MHz. Fig. 6.46 shows the central part of the output spectrum. Two third-order intermodulation products appear at both sides of the signals with amplitudes of –69.6dB and -67 dB respectively, which corresponds to an of –59.5 dB. This results in an IP3 of 22 dB, which is low enough for application in digital AM receivers. Although qualitatively the modulator is operating correctly, SNR vs. input level figures have to be computed in order to quantify its performance. Fig. 6.47 shows several measured SNR vs. input level curves. The measurements were made with a single input tone centered at several AM frequencies. Fig. 6.47(a) depicts the SNR vs. input level for the same oversampling ratio, M = 128. Fig. 6.47(b) plots the SNR computed in a 10kHz bandwidth (commercial AM bandwidth). Note that, as a consequence of the larger oversampling, the best SNR -peak in the AM bandwidth is 65dB for a 6.67MHz sampling frequency. Table 6.8 summarizes the modulator performance when clocked at 2, 4 and 6.67MHz for the conversion of commercial AM signals centered at 488kHz, 976kHz and 1.63MHz respectively. The DR is larger than 57dB in the entire frequency range – in accordance with the requirements of AM digital receivers. The modulator also works correctly at frequencies beyond AM bandwidth. This

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Systematic Design of CMOS Switched-Current Bandpass Sigtna-Delta Modulators for Digital Communication Chips

is illustrated in Fig. 6.48 by plotting measured modulator output spectra clocked at 10MHz and 16 MHz. In both cases a good noise shaping is observed. However, as a consequence of the sampling frequency increase, the settling error dominates the inband error power, thus degrading the performance of the modulator. The highest speed operation achieved by the modulator is best demonstrated if the input signal is placed at This is shown in Fig. 6.49 by plotting two measured output spectra when clocked at 10MHz and 14.28MHz, the signal frequency being 7.56MHz and 10.87MHz, respectively. As discussed in Section 1.5.2, one advantage of placing the zeroes of at is that the input signal can be placed at thus allowing the sampling frequency to be reduced by a factor of three. This allows the modulator to achieve a correct noise shaping up to the maximum IF of digital FM radio receivers (10.8MHz) – at the price of reducing the oversampling ratio, and hence worsening the resolution. Nevertheless, this drawback is not so critical if the noise floor is not dominated by the quantization noise.


6.6.2.4 SI second-order bandpass

395

modulator

As stated in Section 6.2, second-order are not appropriate for the application of AM radio receivers for two main reasons. On the one hand, according to (6.2) SI errors should be lowered below 0.01% in order to achieve the required DR. On the other hand, the quantization error and the input signal are correlated in this class of modulators, thus resulting in a non-white quantization noise power. As demonstrated in Section 1.6.1.1, the quantization error in these modulators is discrete,

396


having the so-called idle tones whose location depends on the frequency and the amplitude of the input signal. In this section, this tonal behaviour of the quantization error will be demonstrated experimentally. Fig. 6.50 shows two measured output spectra of the second-order for an input tone of when clocked at and (the minimum and maximum sampling frequencies required for a digital AM radio receiver). Observe the presence of two “valleys” at about 1/8 and 3/8 of the clock frequency. These valleys are actually groups of idle tones caused by the strong correlation between the input signal and the quantization error. To demonstrate this correlation, Fig. 6.51 shows several modulator output spectra corresponding to different input levels when clocked at Note that, because of SI errors, the notch frequency is deviated from the ideal position (at ) to As Fig. 6.51 illustrates, there are four groups of idle tones whose frequencies are a function of the input signal amplitude, Note that, as approaches two of these groups (labelled and in Fig. 6.51) move away from while the other two groups and approach The tones with the largest amplitude are those placed at:


which matches those predicted by (1.44) for resents and as a function of between theory and measurements.

397

As an illustration, Fig. 6.52 repshowing a good agreement

In AM radio applications, out-of-band idle tones are critical because, in the presence of non-linear errors, they can mix with the input signal and fall into the signal band. For the special case of a single tone at the most significant intermodulation components (those corresponding to approaching ) will fall approximately at thus not degrading the linearity of the modulator. Fig. 6.53 illustrates this by plotting the Signal-to-(Noise + Distortion) Ratio (SNDR) as a function of the input level for different sampling frequencies and M = 128. Note that a linear behaviour is obtained over the entire signal range.

398


In practical applications, the input signal will contain spectral components at different frequencies, and according to (1.46), multiple tones will appear inside the signal band. This is verified by the following measurements. Placing the input signal at the notch frequency of a maximizes the dynamic range of such a modulator. However, for the case of a 2nd-order a large number of idle tones will appear, thus destroying the operation of the modulator. Fig. 6.54 illustrates this by plotting two modulator output spectra when the input signal is located at the notch frequency, Fig. 6.54(a) is for an input tone of –6dB@491kHz, and Fig. 6.54(b) is for a –[email protected] input tone clocked at 2MHz and 6.67MHz, respectively.


399

According to (1.46), the frequency of idle tones only depends on the relative location of the input frequency with respect to However, as is also shown in [Gray90] for the amplitude of such tones is strongly dependent on the input signal amplitude. Fig. 6.55 illustrates this by plotting the central part of three measured output spectra corresponding to different input amplitudes. The position of some of the most significant tones is labelled. Observe that the amplitude of said tones is not an increasing function of the input level, in the same way as it happens to the [Gray 90]. The most critical idle tones are those appearing in the signal band because they degrade the linearity of the modulator. This is illustrated in Fig. 6.56 by depicting the measured SNDR as a function of the input level. Note that a hard non-linear behaviour is obtained, thus destroying the modulator performance.

6.6.3 Comparison with the predictive results of the SI bandpass

modulators

Fig. 6.57 compares measured and predicted results for the In order to separate the effects of the memory dc errors ( and ) from those of the incomplete settling error, the half-scale SNR (corresponding to a –6dB input level signal) was obtained for different clock rates and a 50kHz bandwidth. Note that, for clock frequencies below about 3MHz, the SNR increases with at a rate of about 15dB/octave, which corresponds to a dependence on as predicted in (6.5). This means that the quantization noise dominates the performance of the modulator. However, for clock frequencies above 3MHz, the SNR increases with at a rate of

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only 3dB/octave, which reflects a dependence on M, and therefore, white noise is the dominant error source. Finally, for clock frequencies exceeding 10MHz, the settling error dominates and the noise power in the signal band increases very rapidly, as predicted by theory. Fig. 6.57 demonstrates that the dynamic range of the fourth-order modulator is limited by circuit noise, not by quantization noise. However, as shown in Section 6.3.1.2, thermal noise of memory cells is below the measured noise floor. A possible explanation for the noise increase may be digital switching noise which is coupled to sensitive nodes via the additional MOS capacitance, – connected between substrate and the gate of the memory transistor (see Fig. 6.8). Fig. 6.58 compares the measured SNR-vs-M for both the second-order and the fourth-order Data from this figure were obtained by computing the SNR in several signal bandwidths with an input tone placed at the notch frequency, when clocked at Note that, in the case of the fourth-order modulator, for oversampling ratios above 32 white noise dominates the in-band noise power and the SNR increases with M at a rate of 3dB/octave. However, in case of the second-order modulator, the SNR increases with M at a rate of 9dB/octave over the entire range, corresponding to a dependence on as predicted by (6.2). Thus, while the performance of the fourth-order is dominated by white noise, that of the second-order is dominated by quantization noise. This agrees with theoretical predictions as illustrated in Fig. 6.59.

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6.7 Illustrating by measurements the performance degradation caused by SI errors To conclude this chapter, in this section some measured results are given which demonstrate experimentally the performance degradation caused by some SI errors. These results are compared with time-domain simulations from the simulator described in Chapter 5, thus validating the analyses and behavioural models detailed in Chapters 3, 4 and 5. For practical reasons, the effect of each SI error cannot be isolated experimentally. In fact, none of them can be controlled experimentally. Instead of that, we only have off-chip control of the bias currents, supply voltages, input signal parameters (amplitude and frequency) and the sampling frequency. Taking into account these practical limitations, the results here will center on illustrating the effect of: Static errors, mainly the linear and non-linear part of and This will be done by varying the bias current source of the regulated-cascode stage, - see Fig. 6.8. Dynamic errors,

and

by varying the sampling frequency,

(a) Effect of static errors – changes on As increases, the operating-point voltage of the input node increases, forcing transistors (see Fig. 6.8) to leave the saturation region. As a consequence, both the linear and the non-linear part of the input impedance increases with as illustrated in Fig. 4.28, thus degrading the quantization noise shaping of the modulator and increasing the harmonic distortion. Fig. 6.60(a) illustrated this by plotting two measured output spectra corresponding to different values of Observe that three main effects appear as a consequence of increasing an increment of the quantization noise in the signal bandwidth, harmonic distortion and a shift of the notch frequency. The first two effects are due mainly to the increase of the linear and the non-linear part of the finite output-input conductance ratio error while the third effect is caused by the cumulative effect of errors and

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405

These effects are predicted by time-domain behavioural simulations as Fig. 6.60(b) illustrates. Note that a similar degradation is obtained by comparing the spectra in Fig. 6.60(a) and Fig. 6.60(b). However, in the simulations this degradation appears for higher values of This is because nominal conditions were used. Fig. 6.60(c) compares two simulated output spectra for considering both nominal and worst-case speed conditions. Note that the latter approach experimental results better than the former, as was also observed in the measurements from the resonator. The in-band quantization noise degradation is illustrated in Fig. 6.61(a) by showing the several measured SNDR vs. input level corresponding to different values of

406


Note that, as the input level increases, the SNDR curve saturates as a consequence of the harmonic distortion. A similar degradation is obtained by behavioural simulations in Fig. 6.61(b). The effect of static errors on the harmonic distortion is best illustrated in bandpass modulators by measuring Fig. 6.62(a) shows the central part of several measured modulator spectra for different values of and an input signal consisting of two –10dB tones at 486kHz and 488kHz when clocked at These results confirm the degradation of with which was analyzed in detail in Section 4.7.1.4. In that section theoretical analyses were validated by time-domain behavioural simulations using nominal conditions as Fig. 4.32(b) illustrates. Those results have been validated by measurements as


407

Fig. 6.62 demonstrated by representing both measured and simulated (worst-case speed conditions) vs. showing a good agreement. The last effect of changing is shifting the notch frequency position as illustrated in output spectra displayed in Fig. 6.60. This degradation is caused mainly by the variation of the steering switch-on resistance, thus causing resonator scaling errors to increase. This effect was already illustrated by time-domain simulations in Fig. 5.37(b) considering only the influence of In such conditions, the position of the notch frequency can be exactly determined. However, this is more difficult in practice because the in-band noise hides the exact position of the notch frequency. Nevertheless, Fig. 6.63 represents the approximated variation of as a function of comparing both simulations and measurements. For (not represented in Fig. 6.63) the measured value of the notch frequency is – very similar to that extracted from simulation, On the other hand, the variation with respect to is quite similar to that obtained from measurements from the SI resonator. (b) Effect of dynamic errors – changes on Fig. 6.64(a) shows two measured output spectra corresponding to different values of and hence, of the settling error, As discussed in Chapter 4, has two main effects: increasing the quantization noise in the signal band and shifting the notch frequency position. Both effects are demonstrated in the output spectra shown in Fig. 6.64(a) for sampling frequencies above AM. Observe that the in-band quantization noise is increased about l0dB when is doubled. This has been confirmed by theory, as demonstrated in Fig. 6.57. In addition, the notch frequency position has

408


been shifted –1.4% from its nominal position as predicted by theory in (4.60) (data inset Fig. 6.64(a)). This is best illustrated in Fig. 6.64(b) by displaying vs. showing a good agreement between measurements and simulations. Another effect of raising the sampling frequency is the increase of the harmonic distortion. As stated in Chapter 4, this phenomenon is caused by two error mechanisms: the incomplete settling error, and the non-linear sampling-and-hold, As demonstrated in Section 4.7.3, for practical values of the harmonic distortion in is dominated by the second one, This effect has been validated by measurements as follows.


409

Fig. 6.65(a) shows two output spectra for an input signal consisting of two –7.5dB tones when clocked at different frequencies in the AM range and Note that the intermodulation distortion is approximately the same for all sampling frequencies and thus demonstrating that it is not due to a dynamic effect but to a static effect (the non-linear input impedance) . The effect of the cell dynamics is appreciated above the AM bandwidth. Fig. 6.65(b) illustrates this by comparing two measured output spectra when clocked at and In addition to the above-mentioned effects on the quantization noise (due mainly to the

. It may also be due to the charge injection error. Although HSPICE simulations at the cell level reveal that the harmonic distortion caused by is about -120dB, this is not a reliable data because the charge injection error is not well modelled in HSPICE.

410


settling error), the intermodulation distortion rises up to which agrees with that predicted by theory. Thus, by substituting the parameters of the memory cell: in (4.130) we obtain

All these results are predicted by time-domain behavioural simulation as illustrated in Fig. 6.65(c) by comparing two output spectra corresponding to different sampling frequencies, and yielding and respectively.


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SUMMARY This chapter detailed the design, implementation and measurements of two SI bandpass modulators intended for application in digital AM radio receivers. Two single loop architectures have been considered: a second- and a fourth-order. First, a comparative study of the mentioned architectures was performed, from the ideal point of view as well as taking into account the effect of main SI errors. From such a study, it is concluded that the fourth-order architecture is more appropriate than the second-order one for practical reasons. On the one hand, the use of the fourth-order allows us to relax the error bounds from 0.01% – required for the second-order – to 0.5%. On the other hand, in the second-order architecture the quantization error is correlated to the input signal thus causing multiple tones to appear in the signal bandwidth. This behaviour has been validated by measurements. The building blocks of the modulators were designed in order to minimize the main SI errors. A detailed description of the design process is given, especially for the main SI blocks: memory cell, integrator and resonator. In addition to the design of these circuits, some practical considerations have been taken into account. On the one hand, a fully-differential current mode buffer has been implemented at the frontend of the circuits fabricated. This buffer is used to isolate the on-chip circuitry from the parasitic time constants at the chip input pads, thus allowing us to take full advantage of the speed capabilities of the designed SI blocks. On the other hand, special emphasis has been put on two critical issues of the design process: the layout and the measurement set-up. Main recommendations for mixed-signal circuits have been adopted to isolate the critical SI circuits from the digital switching noise. Following those recommendations, two PCBs were fabricated. Two chips were integrated and attached to the mentioned PCBs for testing. One chip contained the SI fourth-order bandpass modulator and the other one contained three circuits: the current mode buffer, the SI resonator and the second-order bandpass modulator. Measurements of all these blocks are given demonstrating a correct functionality. In particular, the fourth-order bandpass modulator features DR>57dB within a 10kHz bandwidth for signals centered on 540-1600kHz – in accordance with the requirements of AM digital radio receivers. Besides, a correct noise-shaping filtering is shown for a sampling frequency of up to 16MHz and for input signals of up to 10.8MHz (maximum IF of FM digital radio receivers) when These results demonstrate the possibility of using SI bandpass modulators in high frequency communication systems.

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To conclude the chapter, the degradation of bandpass modulators with SI errors has been illustrated by measurements. In particular, the effects of the finite output-input conductance ratio error and the dynamics of the memory cell have been verified, thus demonstrating the accuracy of the behavioural models proposed in this book.

References

413

References

[Abid88] [Abid95a] [Adam91]

[Adam97]

[Alle84] [Anac91] [Andr96]

[Andr98]

[Arda87] [Azer96]

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Distortion analysis of SI memory cells with nonstationary input signals using Volterra series

431

Appendix A Distortion analysis of SI memory cells with nonstationary input signals using Volterra series A.1 Introduction Section 3.4.5 demonstrated that when the input signal of an SI memory cell is not maintained constant during the sampling phase, the non-linear transient of the memory-transistor gate-source voltage causes higher harmonic distortion than in the case of previously sampled-and-held input signals. The analysis of this phenomenon was carried out in Section 3.4.5.2, and based on some simplifications, a closed-form expression was derived for the third-order harmonic distortion. This appendix presents a more rigorous approach, based on the Volterra series method [Sche80], for analizing the transient response of a memory cell with continuous-time sinusoidal input signals. Close-form expressions are derived for the harmonic and the intermodulation distortion, which, after some approximations, approaches the expression found in Section 3.4.5.2.

A.2 Review of Volterra series As known, the output signal, be represented by:

of a Linear Time-Invariant (LTI) system can

where h(t) is the impulsive response of the system and x(t) the input signal. Using fasorial analysis, the above expression can be expressed as:

432


where amplitude

is the Fourier transform of h(t) and and angular frequency

is a fasor of

In the more general case, and under some general continuity conditions, a nonlinear time-invariant system can be expanded into a series of the type [Sche80],

which is called the Volterra series, whose convergence is uniform. The above series expansion is sometimes written in the following form:

where is named the nth-order operator with kernel Note that, in the Volterra series the term, usually named nth-order Volterra kernel, plays an analogous role to that of the impulsive response, h(t), in LTI systems, but assuming that their currents and voltages are nth-order signals. It can be shown that Volterra kernels form a basis for sufficiently well-behaved systems so that it is possible to form a series of nth-order equivalent circuits, to solve each one by conventional linear analysis, and to combine their individual responses to form a total solution. Expanding a non-linear system in Volterra series is useful for finding its frequency response and hence its sinusoidal response, which is directly related to harmonic distortion. For this purpose, it is more convenient to use the fasorial analysis


433

in the same way as in linear systems. Thus, assuming that the input signal is a fasor, the output signal will be given by:

where

represents the nth-dimensional Fourier transform of the nth-order Volterra kernel. Using the definitions for the harmonic distortion coefficients, it can be shown that [Will95]:

Assuming two sinusoidal input signals of the same amplitude, and frequencies, and the intermodulation coefficients can be quantified giving:

434


Therefore, the obtainment of is the key in calculating harmonic and intermodulation distortion coefficients of non-linear dynamic systems. The next section will apply this method to an SI memory cell with a continuous-time sinusoidal input signal.

A.3 SI memory cell with continuous-time sinusoidal input signal Let us consider the simple SI memory cell shown in Fig. A.1(a). For our analysis, the following approximations will considered: Only the gate-source capacitor, taken into account.

of the memory transistor M, will be

The output conductance of the bias transistor,

is null.


435

Both transistors are in the saturation region and modelled by the most simple equation:

where Under the above-mentioned conditions, the equivalent circuit of the memory cell is shown in Fig. A.1(b). Note that, except for the half clock period delay, the analysis of the circuit in Fig. A.1(b) is analogous to that of a simple current mirror whose input stage has the equivalent circuit shown in Fig. A.1(c) and the output stage can be represented by the circuit of Fig. A.1(d). Let us consider the circuit in Fig. A.1(c). By applying Kirchoff’s current law, we obtain:

plus an By making the gate-source voltage equal to a quiescent voltage. the above expression simplifies incremental voltage, i.e, into:

where ered. The incremental voltage,

has been consid-

can be expressed in its Volterra series as:

Substituting the above expansion into (A.13) and keeping only the most significant terms, it can be obtained that the differential equations corresponding to the first, second and third-order kernels are, respectively:

436


Performing the same analysis for the output stage yields:

where and are the linear, second-order and third-order term of the Volterra series expansion of Using fasorial analysis and solving for in the above expressions yields:

and


437

where Substituting the above expressions in (A.7), (A.8), (A.9) and (A.10), the expressions for the harmonic and intermodulation distortion coefficients are obtained, giving:

where Assuming that

with

being the amplitude of the input signal. in (A.25) results in:

438


whose module is equal to (3.146). On the other hand, for

which for

the expression in (A.27) simplifies into:

simplifies into:

Effect of mismatch error on the performance of memory cells with non-unity gain

Appendix

439

B

Effect of mismatch error on the performance of memory cells with non-unity gain B.1 Introduction This appendix uses a similar procedure to that in Section 3.5.1 to analyze the impact of mismatch error on the performance of a second-generation memory cell with an output stage of gain The analysis is applied to single-ended memory cells but can be easily extended to fully-differential cells.

B.2 Second-generation memory cell with gain Let us consider the single-ended second generation memory cell with an output stage of gain k shown in Fig. B.1. In the following analysis it will be assumed that all transistors are ideal except for a mismatch error in the nominal value of the threshold voltage, and the large signal transconductance, of memory transistors and

440


During clock phase drain current is given by

where

of period

is diode-connected. Hence its

and

On clock phase will maintain its drain current at the same value as that stored at the end of clock phase and will act as a current source, delivering an output current given by

where gain k .

and

stands for the mismatch error associated to the

From (B.1) and (B.2) it can be shown that the output current is

where Performing a Taylor expansion series of (B.3) for

yields:

where

is the offset current caused by the mismatch error. The linear gain error is

Effect of mismatch error on the performance of memory cells with non-unity gain

441

and represents the lth-order non-linear gain error. The most significant are the second-order and the third-order errors, respectively, given by

Observe that, for the non-linear gain errors are the same as those obtained for a mismatched memory cell with unity gain (see Section 3.5.1). This is a direct consequence of the fact that non-linear errors are only due to Though the linear gain error, has the same expression as that shown in (3.162), its standard deviation, will depend on whether the gain stage is implemented by using unit transistors or not.

B.3 Gain stage implemented using unit transistors Let us assume that both and are formed by connecting in parallel and unit transistors, respectively, so that In such a case, if each unit transistor of area WL has a mean drain current and a variance of then the variance and the mean value of and will be respectively given by:

From (B.9) and (B.10), the variance of k can be found from

442


and the relative variance is

Substituting (3.152) in (B.12) results in

where and are the areas of and respectively. From (B.6) and (B.13) the following expression results for the variance of

B.4 Gain stage implemented without unit transistors In the case that and are not realized by unit transistors, an extra current error appears as a consequence of systematic errors in and which we will represent by and The result is an additional current ratio error

In this case, the total error is the sum of (B.6) and (B.15).


445

Index

A A/D converters Fundamentals, 5 Nyquist-rate, 6 Oversampling 10 Adaptative feedthrough cancellation, 137 Algorithmic techniques, 140 AM (digital) radio receivers, 3, 234, 339 Anti-aliasing filter, 5, 28, 37, 43 Auto-zero effect, 180

B Bandpass Sigma-Delta modulators Applications, 3, 26, 48, 87, 337 Continuous-time, 43, 49 Fundamentals, 25 Ideal noise-shaping, 25, 204 Lowpass-to-bandpass transformation, 30 , 35 N-path architectures, 41 Passband location, 28 Quadrature architectures, 37 State-of-the-Art bandpass A/D converters, 48 Basic building blocks, 62, 227 Behavioural modeling of switched-current (SI) circuits, 285 Current comparators, 309 Implementing behavioural models in SIMULINK, 314 Integrators, 287 Resonators, 307 Biquadratic (filters), 25,81 Buffer, see current mode buffer

C CAD tools Electrical simulators, 280 SDSI – tool for the behavioural simulation of SI modulators, see SDSI Overview of existing SI simulation tools, 282 Cascode technique Simple cascode memory cell, 122 Channel length modulation, 108 Charge injection error, 127, 298, 349 Analysis and modeling, 128 Circuit strategies to reduce the error, 135 Clock feedthrough, 128, 147 Effect on SI integrators, 211 Effect on SI resonators, 213 Effect on the quantization noise-shaping of SI bandpass modulators, 220 Harmonic distortion, 133, 241 Circuit replication technique, 137 Class AB SI circuits, 187 Clock phase generator, 370 Clock jitter, 43, 164, 192, 204 Common mode feedback, 345 Comparators, see current mode comparators Comparison to the predictive results, 399 Complex bandpass modulators, see bandpass modulators (quadrature architectures) Conductance Input conductance, 109, 121, 209, 268, 293 Output conductance, 60, 109, 121, 209, 227, 263, 293, 348

446

Output/Input conductance ratio error, see finite output/input conductance ratio error Cumulative influence of errors, 225, 308, 333, 391 Bandpass modulators, 231 Memory cells, 227 Integrators, 230 Resonators, 231 Current copier, 59 Current memory cell – principle of operation, see memory cell Current mirrors, see output stages Current mode buffer, 338, 368, 383 Current mode comparators, 100 Current steering switch, 357

D D/A converter, 103, 308, 311, 364 Decimation, 29, 46 Differentiators, 19, 74 Backward-Euler (BE), 75 Bilinear, 78 Continuos-time, 74 Discrete-time, 74 Forward-Euler (FE), 78 Digital radio receivers, 1, 3, 37, 48, 53 Distortion, see harmonic distortion Dummy switch, 136 Dynamic Range (DR), 3, 13, 197, 206, 339, 352, 399

F Figure-of-merit for modulators, see modulation Finite output/input conductance ratio error, 108, 208, 289, 308, 348, 411 Circuit strategies to reduce the error, 121 Effect on SI integrators, 208 Effect on SI resonators, 213 Effect on the quantization noise-shaping of SI bandpass modulators, 219 Linear analysis of memory cells, 109 Non-linear analysis of memory cells, 112 First-generation memory cell, 57, 191 First-order modulator, see modulators Flicker noise, see Noise Folded cascode memory cell, 124 Fourth-order bandpass modulators, 204, 208, 247, 324, 366, 391, 411 Fully differential SI circuits, 40, 90, 101, 143, 155, 194, 236, 242, 250, 260, 288, 304, 338, 344

G Generalized integrator, see Integrators Glitches, 191, 363 Grounded-gate amplifier, 126, 146

H E Effective resolution, 10, 13, 23, 53 Electrical noise, 177 Equivalent noise bandwidth, 184, 302, 353 Experimental results Current mode buffer, 383 Fourth-order bandpass modulator, 392 Illustrating the performance degradation with SI errors, 403 LDI-based resonator, 384 Second-order bandpass modulator, 395

Harmonic distortion in bandpass modulators, 249, 258, 260, 265 in memory cells, 115, 121, 126, 134, 158 ,165, 176, 195 in integrators, 238, 251, 264 in resonators, 242, 254 Hysteresis, 310, 331, 363 High abstraction level model, 287

447

I Idle tones, 15, 33, 87, 396 In-band noise power, 10, 204, 249, 276, 402 Incomplete settling error, see settling error Integrators, 61, 208, 238, 251, 264, 272, 353 BE, 62 Behavioural model, 287 Bilinear, 73 Continuos-time, 61 Discrete-time, 61 FE, 61 Generalized, 73 Intermodulation distortion, 249, 258, 266, 331, 408, 431

J Junction leakage current error, 190

L Latch, 102, 310, 361 Layout considerations, 372 Loop gain errors Effect on the quantization noise shaping, 214 Harmonic distortion, 263 Low abstraction level model, 287 Lowpass modulators, see modulation

M MATLAB, 282, 312, 359, 380 Measurement set-up, 378, 411 Memory cell Design considerations, 195, 343 Principle of operation, 57 Metal-metal capacitors, 56 Mismatch error, 169, 218, 290, 326, 363 Effect on fully differential memory cells, 174

Effect on gain stages, 170, 439 Multi-bit A/D and D/A converters, 203, 308 Multi-bit lowpass modulators, 22 Multi-stage architecture (MASH), 20, 204

N Noise Analysis of integrators, 272 Analysis of memory cells, 179 Equivalent noise bandwidth, 184, 302, 353 Flicker noise, 4, 178, 273 In-band thermal noise power in bandpass modulators, 273 Input-equivalent noise, 273 Thermal noise, 7, 178, 196, 236, 271, 289, 301, 317, 352, 401 Noise-shaping, 11, 17, 25, 204, 219, 225, 340, 394 Noise transfer function, 44, 83, 204, 220, 232, 333, 339 Non-linear dynamic errors, 196, 236, 407 static errors, 236, 241, 257, 385, 404 Non-overlapping clock phases, 191, 370 Non-stationary input signals, 158, 261, 352 Notch frequency, 12, 29, 40, 150, 214, 234, 331, 361, 391, 402, 406 N-path bandpass modulators, see bandpass modulators N-step switched-current circuits, 142 Nyquist-rate A/D converters, see A/D converters

O Output stages, 108, 170, 192, 212, 263, 290, 304, 357, 368, 439 Oversampling A/D converters, see A/D converters Ratio, 6, 15, 22, 28, 203, 225, 276, 339, 394

448

P Pattern noise generation in 1st-order lowpass modulators, 16 in 2nd-order bandpass modulators, 33 Phase delay due to non-stationary input signals, 163 Pin assignment, 377 Poly-poly capacitors, 51, 55 Power spectral density, 9, 178, 193, 205, 301, 323, 252, 394 Printed circuit boards for testing, 378 Programmability, 24

Q Quantization error, 8, 204, 219, 247, 258, 396, 401, 411 in bandpass modulators, 33 in lowpass modulators, 16 Quantization noise, 1, 12, 22, 30, 46, 203, 219, 234, 248, 268, 326, 342, 393, 401 Quantizer, 5, 8, 100, 308, gain, 9 overloading, 9 white-noise model, 9 Quadrature modulators, see bandpass modulators

R Radio receivers, see digital radio receivers Regenerative latch, see latch Regulated cascode memory cell, 122, 183, 287 Regulated folded-cascode memory cell, 124, 150, 245, 293, 317, 343, 369 Resonators, 25, 41, 80, 212, 236, 254, 263, 358, 384 Behavioural model, 307 Delay element based, 98 FE-loop based, 94 LDI-loop based, 90

S Sampled noise, 186 Sampling, 5 Sampling-and-hold error, 196, 260, 408 Sampling frequency, 28, 89, 142, 146, 158, 193, 203, 321, 339 SDSI, a MATLAB based behavioural simulator for SI modulators, 285, 312 Application examples, 324 Graphical User Interface, 320 Second-generation memory cell, 59, 108, 174, 191, 367, 439 Settling error, 146, 163, 229, 289, 350, 394, 401, 407 Effect on SI bandpass modulators, 220, 258 Effect on SI integrators, 211, 251 Effect on SI resonators, 213, 254 Linear analysis, 147 Non-linear analysis, 153 S-functions, 312 Shielding, 373 Sigma-Delta Modulation Basic architectures, 11 Figures-of-merit, 13 First-order lowpass modulators, 14 High-order lowpass modulators, 18 Second-order lowpass modulators, 17 State-of-the-Art lowpass SI modulators, 52 Signal-to-Noise Ratio (SNR), 13 SNR degradation due to linear SI errors, 226, 233 SNR degradation due to non-linear SI errors, 268 Signal transfer function, 43, 205 Simulation of modulators, 280 Simulation of SI modulators Basic block, 286 Behavioural simulation, 28, 285 Comparative analysis of reported simulators for SI modulators, 282 High abstraction level models, 287 Low abstraction level models, 287 Mid abstraction level models, 287 Time-domain simulation, 94, 107, 204,

449

240, 254, 270, 284, 312, 385, 403 SIMULINK, 282, 314 Steering switch, 116, 127, 191, 214, 264, 291, 345, 370, 406 Switch-on resistance, 116, 147, 154, 264, 274, 318, 326, 357 Synthesis of bandpass modulators Lowpass-to-Bandpass transformation method, 30 Optimized synthesis of quantization noise transfer function, 36

T Thermal noise, see Noise Total Harmonic Distortion (THD), see Harmonic distortion Transconductance Large-signal transconductance, 171, 295, 305 Small-signal transconductance, 109, 180, 257, 293 Two-step SI memory cells, 142

U Uncertainty on the sampling instant, 193

V V/I converter, see current mode buffer Virtual ground, 379 Volterra series method, 167, 263, 431

W White-noise model, see quantizer

z Zero-voltage technique, 140

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