Silicon RF power MOSFETS

SILICON RF POWER MOSFETS SILICON RF POWER MOSFETS B JAYANT BALIGA North Carolina State University, USA \[p World Sc...

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SILICON RF POWER MOSFETS

SILICON RF POWER MOSFETS

B JAYANT BALIGA North Carolina State University, USA

\[p World Scientific NEW JERSEY • LONDON

• SINGAPORE

• BEIJING • S H A N G H A I

• HONGKONG

• TAIPEI • CHENNAI

Published by World Scientific Publishing Co. Pte. Ltd. 5 Toh Tuck Link, Singapore 596224 USA office: 27 Warren Street, Suite 401-402, Hackensack, NJ 07601 UK office: 57 Shelton Street, Covent Garden, London WC2H 9HE

British Library Cataloguing-in-Publieation Data A catalogue record for this book is available from the British Library.

SILICON RF POWER MOSFETS Copyright © 2005 by World Scientific Publishing Co. Pte. Ltd. All rights reserved. This book, or parts thereof, may not be reproduced in any form or by any means, electronic or mechanical, including photocopying, recording or any information storage and retrieval system now known or to be invented, without written permission from the Publisher.

For photocopying of material in this volume, please pay a copying fee through the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, USA. In this case permission to photocopy is not required from the publisher.

ISBN 981-256-121-8

Printed by Fulsland Offset Printing (S) Pte Ltd, Singapore

Dedication

The author would like to dedicate this book to his wife, Pratima, for her selfless and unreserved support during the time devoted to the development of the SL-MOSFET technology as well as the time taken to prepare its exposition in this tome.

Preface

During the last five years, there has been a phenomenal growth and proliferation of cellular telecommunications around the world. Great improvements in productivity have been achieved in developed nations in the Western hemisphere by the instantaneous access derived from mobile and portable handsets. More recently, countries, such and China and India, with poor telecommunication landlines have leapfrogged to cellular networks to provide connectivity to their citizens. Although most of today's cellular network is based on voice traffic, interest in providing digital services is rapidly growing. Handsets with built in digital cameras have been gaining in popularity for recording and transmitting pictures1. Downloading information from websites with the wireless telephone terminal is expected to become commonplace after the proliferation of third generation (3G) mobile systems2. My personal journey into the wireless infrastructure world began as an off-shoot of my long career devoted to the development of improved semiconductor technology for power electronic applications. Over the last 25 years, first at the General Electric Corporate Research Laboratory in Schenectady, N.Y., and then at North Carolina State University in the Power Semiconductor Research Center, I have had the opportunity to invent, analyze, and develop a variety of semiconductor devices for power management applications. My most successful invention has been the Insulated Gate Bipolar Transistor (1GBT) because of its revolutionary impact on medium (~ 1-10 kW) and high (~ 100 kW -1 MW) power systems. It has been amazing to observe the widespread use of this device for house-hold appliance controls, in white goods such as refrigerators and washing machines, in numerical controls and robots for factory automation systems, in bullet trains and hybrid-electric vehicles, and even for saving lives through adoption in portable defibrillators3.

vii

viii

SILICON RF POWER MOSFETs

A decade ago, I became interested in creating improved technology for power electronic applications operating at relatively low power levels (< 200 Watts). For these applications, the vertical power MOSFET structure had been already recognized to provide the best performance in terms of both conduction and switching losses for applications such as switch-mode power supplies. With continual pressure to reduce the size of the power delivery system within portable computers (laptops), it was clear that reduction in the resistance as well as the switching times for the power MOSFETs was crucial to increasing the power density. An elegant solution to achieve these goals was discovered by me by using a charge-coupling concept with a trenchbased electrode within the power MOSFET architecture4'5. Analysis of this structure, called the GD-MOSFET, indicated that, in addition to achievement of extremely low specific on-resistance (even below the ideal perceived limit for silicon), it was possible to obtain extremely fast switching times making this device very suitable for power delivery in portable appliances. Five years ago, I realized that the superior switching speed of the GD-MOSFET architecture may make it suitable for RF signal amplification at high power levels. In the late 1990s, the prevailing bipolar RF transistors were just being displaced by the emerging LDMOSFET technology. When compared with the bipolar transistor, these devices offered a superior linearity that was becoming increasingly important because of the deployment of Multi-Carrier Power Amplifiers (MCPAs) in cellular base-stations. However, it was well-known that the square-law relationship between the drain current and gate voltage in the saturation region was one limitation to achieving distortion free power amplification6. This square-law relationship resulting from the channel pinch-off physics in MOSFETs was accepted as a fundamental characteristic of long channel MOSFETs as described in many textbooks7'8. However, a linear relationship between the output drain current and input gate voltage was highly desirable for the design of RF multi-carrier power amplifiers in order to mitigate the generation of undesirable inter-modulation products. While analyzing and optimizing the GD-MOSFET structure for RF amplification, I discovered an approach to achieving the desired linear relationship between the output drain current and the input gate voltage while the transistor operated in the pentode (or saturation) region. This 'super-linear' idea was generalized in a patent application when no prior art suggesting this feature was discovered9.

Preface

ix

In June 2000, I was given the opportunity to start a company "Silicon Wireless Corporation" with seed funds provided by Academy and Longleaf Funds to commercialize my super-linear transistor (named SL-MOSFET) inventions. Analysis of product and scientific literature indicated that previous attempts at developing vertical MOSFETs for RF applications had been constrained by structural limitations to frequencies below 500 MHz, and that their output power was limited by the poor thermal resistance associated with isolation of the bottom-side drain terminal. Further, the need to connect the source using wire bonds while packaging the devices degraded the RF gain and efficiency due to the parasitic inductance of the wires. For these reasons, I proposed using a flip-chip approach to packaging the vertical SL-MOSFETs10. This enabled bringing the source connection to the flange of the package (as done for LD-MOSFETs) without wire bonds making this technology compatible with LD-MOSFETs from the standpoint of the package for the end-user. An inherent feature of this idea was to use gold bumps, instead of the usual solder-bumps used in flip-chip technology for ICs, to extract heat from the source side of the die without transporting it through the thick silicon substrate. The reduced thermal impedance of the flip-chip die in conjunction with the support of the electric field within the device along the vertical direction enabled a dramatic six-fold increase in the cell power density when compared with LD-MOSFETs. These features provided a compelling advantage for the adoption of the SL-MOSFETs for MCPAs in cellular base-stations. The practical demonstration of the SL-MOSFET architecture and physics, as well as the proposed flip-chip packaging methodology, was successfully accomplished during the 2001-2002 calendar years. A remarkable -45 to -50 dB IMD3 distortion level with a respectable gain of 15 to 18 dB was achieved at an operating frequency of 900 MHz. A gain of 12-13 dB was achieved even at 2100 MHz indicating that this technology can cover the entire cellular range used in GSM and CDMA networks. Recent tests have demonstrated that the SL-MOSFETs are superior to LD-MOSFETs for wide-band applications being considered for 3G networks. These results have validated the super-linear transistor physics and raised the frequency of operation of vertical power MOSFETs by an order of magnitude. In this regard, I wish to take this opportunity to thank Mr. Glenn Kline, Chief Executive Officer at Silicon Semiconductor Corporation, and Dr. Izak Bencuya, Senior VicePresident at Fairchild Semiconductor Corporation for their support over the last three years; and I want to acknowledge the technical support of

x


the packaging and RF testing team from Silicon Semiconductor Corporation for their roles in developing SL-MOSFET products for cellular base-station applications. This book was prepared, after my return to academia in 2003, as a part of my scholarly activities at North Carolina State University. Once my patents on the super-linear device structures were issued and placed in the public domain, it became appropriate to prepare the description in this book to provide insight into the underlying physics. The purpose of writing this monograph is to provide a comprehensive resource on silicon RF MOSFET technology. In spite of the great importance of these devices for the telecommunications infrastructure, no book has been published with emphasis on RF power MOSFET structures. The emphasis in the book is on the physics of operation of the devices elucidated by extensive two-dimensional numerical analysis. This analysis provides general guidelines for understanding the design and operation of the transistors without reference to any specific company's products. The specific details of the design and layout of the devices can be expected to vary in the industry but they all share a common operating principle. In the introduction chapter, a brief description of the wireless cellular communication infrastructure is provided as background information. This is followed by a chapter on RF Power Amplifiers to give the reader the application context for the transistors analyzed in the book. An analytical treatment of the physics of operation of the conventional MOSFET structure is then provided in Chapter 3 together with that for the new Super-Linear MOSFET structure. Chapter 4 of the book deals with lateral MOSFET structures while the rest of the chapters in the book are devoted to vertical MOSFET structures. Thermal issues are considered whenever appropriate. The format for each of these chapters has been carefully maintained to be the same to provide the reader with a unified reference frame work for comparing the different devices. I am hopeful that this book will be adopted for the teaching of courses on solid state devices and that it will make a useful reference for the telecommunications industry.

Prof. B. Jay ant Baliga 2004

Preface

xi

References 1

R. O. Crockett, "America Zooms in on Camera Phones", Business Week, pp. 44-45, December 22, 2003. 2 S. Baker, N. Gross, I. M. Kunii, and R. O. Crockett, "The Wireless Internet", Business week, pp. 136-144, May 29, 2000. 3 B. J. Baliga, "How the Super-Transistor Works", Scientific American Magazine, Special Issue Commemorating the 50th Anniversary of the Transistor Invention. 4 B. J. Baliga, "Vertical Field Effect Transistors having improved Breakdown Voltage Capability and Low On-state Resistance", U. S. Patent #5,637,898, Issued June 10, 1997. 5 B. J. Baliga, "Power Semiconductor Devices having improved High Frequency Switching and Breakdown Characteristics", U. S. Patent #5,998,833, Issued December 7, 1999. 6 A. R. Hambley, "Electrical Engineering, Section 12.2, pp. 530-533, Second Edition, Prentice Hall, 2001. 7 S. M. Sze, "Semiconductor Devices - Physics and Technology", Section 6.2, pp. 186-192, Second Edition, John Wiley, 1985 and 2002. 8 Y. Taur and T. K. Ning, "Fundamentals of Modern VLSI Devices", Chpter 3, pp. 112-120, Cambridge University Press, 1988 - 2002. 9 B. J. Baliga, "MOSFET devices having Linear Transfer characteristics when operating in Velocity Saturation Mode and methods of forming the same", U. S. Patent #6,545,316, Issued April 8, 2003. 10 B. J. Baliga, "Packaged Power Devices having Vertical Power MOSFETs therein that are Flip-Chip mounted to Slotted Gate Electrodes", U. S. Patent #6,586,833, Issued July 1, 2003.

Contents

Preface

vii

Chapter 1 Introduction 1.1 First Generation Mobile Communication Networks 1.2 Second Generation Mobile Communication Networks 1.3 Third Generation Mobile Communication Networks 1.4 Migration Path to Third Generation Networks 1.5 Base Station Market References

1 2 4 5 5 7 10

Chapter 2 RF Power Amplifiers 2.1 Base Station Basic Architecture 2.2 RF Power Amplifier 2.3 Class A Amplifier 2.4 Class B Amplifier 2.5 Class AB Amplifier 2.6 Multi-Stage Power Amplifier 2.7 Linearization of Power Amplifiers 2.8 Summary References

11 12 13 21 22 23 25 26 30 32

Chapter 3 MOSFET Physics 3.1 Power MOSFET Structure and Operation 3.2 Super-Linear Power MOSFET Physics 3.3 Power MOSFET On-Resistance 3.4 Summary References

33 34 49 64 68 70

xiii

xiv


Chapter 4 Lateral-Diffused MOSFETs 4.1 Device Cell Structure 4.2 LD-MOSFET Simulation Structure 4.3 LD-MOSFET Blocking Characteristics 4.4 LD-MOSFET On-State Characteristics 4.5 LD-MOSFET Output and Transfer Characteristics 4.6 LD-MOSFET Capacitances 4.7 LD-MOSFET RF Performance 4.8 LD-MOSFET Thermal Effects 4.9 LD-MOSFET with Faraday Shields 4.10 LD-MOSFET with Thinner Gate Oxide 4.11 LD-MOSFET Conclusions References

71 72 75 77 80 81 83 84 88 92 98 100 102

Chapter 5 Vertical-Diffused MOSFETs 5.1 Device Cell Structure 5.2 VD-MOSFET Simulation Structure 5.3 VD-MOSFET Blocking Characteristics 5.4 VD-MOSFET On-State Characteristics 5.5 VD-MOSFET Output and Transfer Characteristics 5.6 VD-MOSFET Capacitances 5.7 VD-MOSFET RF Performance 5.8 VD-MOSFET Thermal Effects 5.9 VD-MOSFET with Terraced Gate Oxide 5.10 VD-MOSFET with Thinner Gate Oxide 5.11 VD-MOSFET Conclusions References

103 104 107 109 110 111 113 114 117 120 122 125 126

Chapter 6 Charge-Coupled MOSFETs 6.1 Device Cell Structure 6.2 CC-MOSFET Simulation Structure 6.3 CC-MOSFET Blocking Characteristics 6.4 CC-MOSFET On-State Characteristics 6.5 CC-MOSFET Output and Transfer Characteristics 6.6 CC-MOSFET Capacitances 6.7 CC-MOSFET RF Performance

127 128 132 134 136 137 139 140

Contents

6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16

xv

CC-MOSFET Thermal Effects GD-MOSFET Structure GD-MOSFET Blocking Characteristics GD-MOSFET On-State Characteristics GD-MOSFET Output and Transfer Characteristics GD-MOSFET Capacitances GD-MOSFET RF Performance GD-MOSFET with Thinner Gate Oxide CC-MOSFET/GD-MOSFET Conclusions References

143 144 146 148 149 151 152 155 158 160

Chapter 7 Super-Linear MOSFETs 7.1 Device Cell Structure 7.2 SL-MOSFET Simulation Structure 7.3 SL-MOSFET Blocking Characteristics 7.4 SL-MOSFET On-State Characteristics 7.5 SL-MOSFET Output and Transfer Characteristics 7.6 SL-MOSFET Capacitances 7.7 SL-MOSFET RF Performance 7.8 SL-MOSFET Thermal Effects 7.9 SL-MOSFET with Thinner Gate Oxide 7.10 SL-MOSFET Conclusions References

161 162 166 169 172 173 175 176 178 185 189 192

Chapter 8 Planar Super-Linear MOSFETs 8.1 Device Cell Structure 8.2 Planar SL-MOSFET Simulation Structure 8.3 Planar SL-MOSFET Blocking Characteristics 8.4 Planar SL-MOSFET On-State Characteristics 8.5 Planar SL-MOSFET Output and Transfer Characteristics 8.6 Planar SL-MOSFET Capacitances 8.7 Planar SL-MOSFET RF Performance 8.8 Planar SL-MOSFET Thermal Effects 8.9 Planar SL-MOSFET with Thinner Gate Oxide 8.10 Planar SL-MOSFET Conclusions References

193 194 198 200 203 204 206 207 210 211 216 218

xvi


Chapter 9 Dual Trench MOSFETs 9.1 Device Cell Structure 9.2 DT-MOSFET Simulation Structure 9.3 DT-MOSFET Blocking Characteristics 9.4 DT-MOSFET On-State Characteristics 9.5 DT-MOSFET Output and Transfer Characteristics 9.6 DT-MOSFET Capacitances 9.7 DT-MOSFET RF Performance 9.8 DT-MOSFET Thermal Effects 9.9 DT-MOSFET with Thinner Gate Oxide 9.10 DT-MOSFET Conclusions References

219 220 223 225 228 229 231 232 235 236 241 242

Chapter 10 Hot Carrier Injection Instability 10.1 Quiescent Drain Current Instability 10.2 LD-MOSFET Structure 10.3 GD-MOSFET Structure 10.4 SL-MOSFET Structure 10.5 Planar SL-MOSFET Structure 10.6 Hot-Carrier Injection Conclusions References

243 244 245 255 258 265 272 274

Chapter 11 Synopsis 11.1 Super-Linear Physics 11.2 Comparison of Device Model with Simulations 11.3 Comparison of Silicon RF MOSFET Device Structures 11.4 Conclusions References

275 275 280 282 285 288

Appendix

289

Index

295

Chapter 1

Introduction

The advent of the wireless telecommunications infrastructure has been responsible for one of the social revolutions in the last century1. In the beginning, the benefits of being able to communicate unfettered by landlines was taken advantage of in the business environment. As the networks grew in size and accessibility with concomitant reductions in cost, the benefits expanded to the consumer market2. In more recent years, the plethora of services available in the market have often led to wireless technology supplanting landlines demonstrating that a paradigm shift has occurred. Today, in many under-developed nations, it is often more economical to deploy a wireless network than to invest in the traditional telephone infrastructure. The semiconductor devices discussed in this book are core components in wireless systems. They serve the purpose of boosting the strength of the RF signals to a level essential for consumers to access the telephone network over long distances. Although specific products are optimized for the requirements of individual networks, the operating principles for all these transistors is the same irrespective of the modulation schemes used in the network. The goal of this book is to provide the reader with an introduction to the different styles of silicon power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) that have been developed over the last five years to serve this market. Although the silicon bipolar RF transistors were predominantly used until 1995, the silicon RF MOSFETs have now completely displaced them in network base-stations. In order to elucidate the operating principles and characteristics of these devices, the results of extensive numerical simulations of the device structures are reported in this book. These simulations provide guidelines for understanding the design of modern RF high power transistors. The results of these simulations have been validated in numerous products that are available in the market.

l

2


Links to the datasheets of some representative products have been included in the appendix for reference. Although the focus of this book is on the operating principles of silicon RF power MOSFETs, a description of the application environment is beneficial to the understanding of the design requirements for these devices. For this reason, the rest of this chapter provides some background on the evolution of the mobile communications network. After the advent of the first generation mobile cellular telecommunication systems in the 1980s, the networks have evolved from an analog to a digital framework to enable an increase in voice traffic as well for adding services such as Internet access. The implementation of the third generation system is currently underway with more advances anticipated into the future3'4.

Fig. 1.1 Evolution of Wireless Technology.

A roadmap for the evolution of cellular mobile communication systems is illustrated in Fig. 1.1 to provide a perspective of the time frame over which the transitions are occurring. Some background on this evolution is provided in subsequent sections. 1.1 First Generation Mobile Communication Networks The first generation (1G) of mobile cellular systems was introduced in the 1980s and grew in significance in the early 1990s. The concept of

Introduction

3

dividing the network coverage area into small segments, referred to as cells, provided a modular approach to enhancing telecommunication service while reusing the available frequency spectrum. This method enabled rapid growth in system capacity using analog technology for providing communication by voice. Many competing modulation schemes were deployed in different parts of the world. The most prevalent standards that evolved are shown in Fig. 1.2 below.

System

Deployment

Argentina, Australia, Bangladesh, Brazil, Brunei, Burma, Cambodia, Canada, China, AMPS Indonesia, Malaysia, Mexico, Mongolia, New Zealand, Pakistan, Philippines, Russia, Singapore, South Korea, Sri Lanka, Taiwan, ^^^^___^^^^^_ United States, Vietnam C-NETZ

MMT 45ft "

NMT-900

TACS/ETACS

Germany, Portugal, South Africa Austria, Belgium, Cambodia, Denmark, Finland, France, Germany, Hungary, Iceland, Indonesia, Italy, Malaysia, Netherlands, Norway, Poland, Romania, Russia, Spain, Sweden, Thailand, Turkey, Ukraine Cambodia, Cyprus, Denmark, Finland, France, Greenland, Netherlands, Norway, Serbia, Sweden, Switzerland, Thailand Argentina, Bahrain, China, Ireland, Italy, Japan, Kuwait, Malaysia, Philippines, Singapore, Spain, Sri Lanka, United Arab Emirates, United Kingdom

Fig. 1.2 Deployment of 1G Wireless Networks.

The Advanced Mobile Phone System (AMPS) is a U.S. standard that uses the 800 MHz radio frequency band. In addition to North America, it is utilized in the Far Eastern and South American countries listed in the figure. The C-Netz standard is used primarily in West Germany. The Nordic Mobile Telephone (NMT) standard was initially developed for Scandinavian countries and then adopted in central and southern Europe. The older NMT-450 system is based on the 450 MHz radio frequency band while the more recent NMT-900 system utilizes the 900 MHz band. The Total Access Communication system (TACS) is a

4


standard developed in the United Kingdom that has been adopted by some countries in Southern Europe and the Middle East. It uses the 900 MHz radio frequency band. 1.2 Second Generation Mobile Communication Networks The second generation (2G) mobile cellular systems were based upon maintaining the cellular signal distribution concept but migrating from an analog to one of several digital modulation schemes to enable an increase in voice traffic. This allowed an increase in network capacity within the same radio frequency spectrum licensed by the networks. Four main standards used globally are the Global System for Mobile (GSM) communications, Digital Advanced Mobile Phone Service (D-AMPS), the Code-Division-Multiple Access (CDMA), and the Personal Digital Cellular (PDC) schemes. The most widely used system in the world today is GSM using the 900 MHz radio frequency band. The GSM network utilizes the Time-Division Multiple Access (TDMA) scheme to enable increases in the number of channels. In TDMA, the frequency carrier is divided into short time slots. The Digital Advanced Mobile Phone Service (D-AMPS) was developed in the United States to be backwards compatible with the analog AMPS system. It is also based on the Time-Division Multiple Access (TDMA) scheme to enable increases in the number of channels. The Personal Digital Cellular (PDC) scheme was originally developed in Japan. It operates in the 800 MHz and the 1500 MHz bands. These second generation or 2G networks have been recently upgraded to allow transfer of data. In the High-Speed Circuit-Switched Data (HSCSD) technique, the mobile terminal can use up to four time slots for data connection with each time slot providing either 9.6 Kbps or 14.4 Kbps data rates. This provides a relatively limited data transfer capability as a temporary solution to migration to other techniques. In the General Packet Radio Services (GPRS) method the data rates can be increases up to 115 Kbps making it suitable for e-mail and Web-surfing but not for real-time applications. Although implementation of GPRS requires network investments, it represents an important step towards the migration of the GSM networks to third-generation networks. Another improvement can be achieved with the Enhanced Data rate for Global Evolution (EDGE) scheme which uses phase shift keying to enhance GSM data rates by up to three times. Although the

Introduction

5

EDGE implementation can be done by software upgrades at base stations, the RF amplifiers need to now handle non-constant envelope modulation with a relatively high peak-to-average ratio. When EDGE is used with GPRS, the combination called enhanced GPRS can provide a maximum data rate of 384 Kbps by using eight time slots. The original Code-Division-Multiple Access (CDMA2000) standard, also referred to as the IS-95 standard, provides 9.6 - 14.4 Kbps data rates. This system can be upgraded to the IS-95B standard to obtain 64 Kbps data rates followed by the IS-95C standard, also referred to as the CDMA2000 1XRTT, to enable 144 Kbps data rates. The Japanese Personal Digital Cellular (PDC) system has also undergone upgrades to provide data services. NTT DoCoMo introduced a packet data network (PDC-P) called i-mode that allows consumers to access Internet services over the wireless network. Over 10 million subscribers were signed up within 18 months of launching this service for Web surfing and wireless email. This provided a much needed validation of the premise that data services which complement voice traffic can attract customers. 1.3 Third Generation Mobile Communication Networks The third generation (3G) mobile cellular system is based up on the Universal Mobile Telecommunications System (UMTS) platform. The radio frequency spectrum allocated to UMTS lies between 1900 and 2200 MHz. Wideband CDMA (WCDMA) is one of the more popular proposals for the development of 3G networks. Using a bandwidth of 5 MHz, data rates of 144 and 384 Kbps are anticipated. The UMTS/WCDMA scheme employs spectrally efficient, non-constant envelope digital modulation techniques. Clipping the signal during peak envelop excursions can lead to spectral re-growth that can violate regulatory requirements on the Adjacent Channel Leakage Power Ratio (ACLR). To prevent this problem, high linearity RF power amplifiers are an essential component in WCDMA base stations for 3G networks.

1.4 Migration Path to Third Generation Networks The benefits of migrating from the first generation analog transmission networks to the second and third generation networks are summarized in

6


Fig. 1.3. The digital transmission capability provided by the 2G and 3G networks enables augmentation of voice signals with data that can be used for video display on handsets. This provides the ability to obtain Internet access, which puts vast resources at the fingertips of customers. This evolution has concurrently provided global roaming capability. First Generation Analog Transmission

Second Generation Digital Transmission

Mainly Speech

Mainly Speech

Third Generation Digital Transmission VH

Voice Band data

Digital data J! ° _ Data /-• • P • u J /-i- v o •.. u J Mainly Packet Circuit Switched Circuit Switched : , , c Switched Local Systems Global Roaming Global Roaming Fig. 1.3 Evolution of Wireless Networks.

The improvements in data transmission capability when migrating from the second generation to the third generation mobile communication networks are provided in Fig. 1.4. The migration from the GSM networks in Africa, Asia, Europe, South America, and the USA to the third generation W-CDMA network occurs via the HSCSD, GPRS, and EDGE upgrades, which provide progressive increases in the data transmission rates given in the figure. The migration of TDMA networks to W-CDMA in the USA occurs via the EDGE upgrades, while the cdma2000 networks in Asia and the USA require implementation of the IS-95 B and cdma2000 1XRTT capability to migrate to the 1XEV standard. Meanwhile in Japan, the PDC networks will migrate to the 1XEV and the W-CDMA standards as well, as shown in the figure. When fully implemented, the third generation networks are expected to provide data rates of 144 Kbps at full mobility, data rates of 384 Kbps at limited mobility, and data rates of 2 Mbps at fixed locations.

Introduction

I

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YAntenna Multi-Carrier Power

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RF Transmitter A D CR a d i o

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Fig. 1.5 Block Diagram of a Typical Base Station.

1.5 Base Station Market The deployment of wireless networks that serve an increase in voice traffic with the capability for data transmission at high rates requires investments in new infrastructure. Of particular relevance to this book is

8


the upgrading of the base station architecture to multi-carrier power amplifiers with improved linearity. To gain a proper perspective on the importance of the power amplifier within the base station architecture, a block diagram of the base station footprint is shown in Fig. 1.5. The base station serves as an interface between the antenna for broadcasting the cellular signals and the fixed line telecommunications backbone. The upper portion of the diagram contains the RF circuitry. For a typical cellular base station, the RF section costs about $ 65,000 with the power amplifier comprising $ 40,000 of the cost. Within the power amplifier, the MCPA and linearization circuitry each constitute one-third of the cost today. Since the power amplifier is recognized to be the most expensive portion of the capital expenses in a base station, technology that can reduce the complexity and cost of these components is of great interest to the wireless industry5. As discussed later in the book, the most commonly used method for reducing the distortion produced in today's LD-MOSFET based multi-carrier power amplifiers is the feed-forward technique. The super-linear or (SL) MOSFETs described in this book have been demonstrated to allow the design of multi-carrier power amplifiers that can operate without the feed-forward distortion correction circuitry. The elimination of the linearization circuit from the base station platform would not only reduce cost but also reduce the space and power requirements because of the higher efficiency for RF power transmission.

Fig. 1.6 Base Station Semiconductor Content.

Introduction

9

The growth in the semiconductor content within base stations is illustrated in Fig. 1.6, including the radio frequency, base band processing DSP chips, and the power management segments. The power amplifier component is a significant share of the capital outlay for new deployments. After a drop in revenue during the last two years, it is anticipated that the demand for semiconductors will grow as a result of the deployment of the third generation technology5. The annual revenue for the power amplifier components is about $800 Million. 1.6 Summary The cellular wireless network industry is undergoing a revolutionary advance from analog to digital technology. The push to increase the voice traffic and incorporate data transmission has provided the impetus for upgrading the infrastructure. Although the migration path differs depending upon the modulation protocol used in each system and country, all cellular networks require build-out of base stations with multi-carrier power amplifiers replacing the single-carrier amplifiers that were satisfactory for the analog systems. The implementation of the third generation networks based on W-CDMA requires enhancements in the linearity and efficiency of the power amplification path. The currently used feed-forward architecture required to suppress the distortion products created with LD-MOSFET based power amplifiers is one limitation to achieving this goal. A new super-linear power MOSFET technology has been developed that allows multi-carrier power amplifier designs without the need for the feed forward linearization circuitry. The physics of operation of these transistors is described in this book after first reviewing the principles of operation of the currently used LDMOSFETs. Many novel super-linear power MOSFETs are introduced in this book to demonstrate that the super-linear physics can be achieved using a variety of structural designs. When describing these structures and their characteristics, the same format has been carefully adhered to for each chapter to provide the reader with a unified treatment that allows ease of comparison between the structures.

10


References 1

L. Harte, S. Kellog, R. Dreher, and T. Schaffnit, "The Comprehensive Guide to Wireless Technologies", APDG Publishing, 2000. 2 S. Baker, N. Gross, and I. M. Kunii, "The Wireless Internet", Business Week, May 29, 2000. 3 M. J. Riezenman, "Communications", IEEE Spectrum, January 1998. 4 J. Korhonen, "Introduction to 3G Mobile Communications", Artech House, 2001. 5 S. Lavey and A. M. Leibovitch, "World-wide Base Transceiver Station Semiconductor Forecast, 2002-2006, IDC Report #28297, November 2002.

Chapter 2

RF Power Amplifiers

Cellular base stations serve the function of distributing RF signals within prescribed zones. When transmitting signals to customers, the RF signal must be amplified in order to have sufficient strength to reach hand held terminals up to distances of 15 miles. The boosting of signal strength is performed using RF power amplifiers. In the first generation cellular networks utilizing analog technology, a dedicated RF amplifier was used for each customer for the duration of the call. Modern digital second and third generation networks utilize multi-carrier RF power amplifiers to obtain significant increase in voice traffic while using the same allocated broadcasting spectrum. The linearity and efficiency of the RF power amplifier are paramount in determining the performance of the base station. Although class A amplifiers are well known to provide excellent linearity, their efficiency is prohibitively low for broadcasting cellular signals because of the relatively high power levels involved. Class B RF power amplifiers provide much better efficiency but the degradation in linearity, exhibited by high distortion products, make them unsuitable for cellular base station applications. Consequently, it is common practice to use class AB RF power amplifiers as a good compromise between linearity and efficiency. Using the current generation of RF LD-MOSFETs, the linearity obtained by using the class AB RF power amplifier is unsatisfactory. The inter-modulation products, generated when the main RF signal is amplified, interfere with signals in adjacent channels within the cellular network violating FCC regulations. Many linearization schemes have been proposed to reduce the inter-modulation products generated by the main RF power amplifier. Among these, the feed-forward technique is the most prevalent approach either by itself or in combination with a predistortion circuit.

11

12


In this chapter, the basic operating principles of the RF power amplifier are reviewed to provide the applications context for the RF power MOSFETs that are the subject of this book. More detailed analysis and design considerations for power amplifiers are discussed in the references1'2. Only the class A, class B, and class AB cases are described because other types of RF power amplifiers are not suitable for the cellular base station environment. The waveforms generated with an ideal RF transistor are described using a simple load-line analysis. The impact of device parasitic elements, such as saturation voltages and output capacitances, are discussed to elucidate their importance to practical device designs. The feed-forward and pre-distortion technique for reducing the inter-modulation products generated by the main amplifier is also reviewed to provide a perspective on the complexity added to the overall design by the implementation of these schemes.

Fig. 2.1 Base Station Block Diagram.

2.1 Base Station Basic Architecture The basic block diagram for a base station is illustrated in Fig. 2.1 indicating both the transmission and receiving modes. This function is provided by the transceiver (transmitter and receiver). The main function

RF Power Amplifiers

13

of this unit is to perform the modulation and up-conversion when transmitting signals and the down-conversion and demodulation when receiving signals. The modulation of the carrier wave can be achieved using its amplitude (AM), its phase (PM) or its frequency (FM). Many analog and digital modulation schemes have been proposed and implemented3. The process of up-conversion increases the frequency of the signal from base-band to radio frequencies using intermediate frequencies before the transmission to subscribers. The demodulation and down-conversion steps reverse the process when receiving signals. The power amplifier in the base station boosts the signal strength before deliver to the antenna. With the migration from analog to digital modulation schemes, the linearity of the power amplifier becomes critical to the performance of the base station. Typically, power amplifiers must be able to generate 50-100 watts of clean power with substantially higher peak power capability. Limitations in the linearity of available RF power LD-MOSFETs have demanded the use of correction circuits. The most commonly used Feed-Forward method adds substantial cost and complexity to the base station.

Fig. 2.2 Basic Power Amplifier Circuit.

2:2 RF Power Amplifier The basic circuit diagram for an RF power amplifier is shown in Fig. 2.2 with a power MOSFET as the transistor providing the gain. The DC bias point for the transistor is provided through RF chokes (shown in the figure for the Drain side but not shown for the Gate side) to isolate the

14


DC power supply from the RF signals. The RF signal is transmitted to the load (the antenna after filtering) through a DC blocking capacitor. In today's base stations, the DC voltage is typically between 28 and 32 volts. The ideal transfer characteristic of the transistor that relates the input to the output side has been called the 'ideal strongly non-linear model'4. This characteristic is illustrated in Fig. 2.3.

Fig. 2.3 Ideal Transfer Characteristics.

As shown in Fig. 2.3, the power transistor is biased at a DC gate voltage of V G Q - the quiescent gate bias voltage. This produces a quiescent drain current IDQ corresponding to the DC drain voltage of the power supply. An RF signal superposed on the DC gate voltage on the input side produces an RF drain current on the output side. With a linear transfer characteristic between the gate voltage and the drain current, the drain current will replicate the gate voltage producing a distortion free amplification of the RF signal. This holds true only if the swing in the gate voltage remains between the gate voltage limits of VGi and VG2- The lower gate voltage VG1 is referred to as the threshold voltage for the case of power MOSFETs. The upper gate voltage VG2 defines the limit at which the drain current no longer increases with an increase in the gate voltage. This maximum value Imax of the drain current is referred to as the compression current of power MOSFETs. A large value for I , ^ is desirable for delivering more RF output power. However, in practice the

RF Power Amplifiers

15

on-resistance of the power MOSFET and its quasi-saturation behavior often constrain the utilization of the maximum drain current.

Fig. 2.4 Ideal Output Characteristics.

The output characteristics of an ideal power transistor are shown in Fig. 2.4 together with a resistive load line. When the transistor is biased at a quiescent gate voltage VGQ, a DC drain current IDQ defines the operating point corresponding to the DC power supply voltage VDQ. The RF signal applied to the gate produces a RF drain current IDrms and voltage VDrms that are related by the output load resistance RL: i

y

_ .

Drms

R

L

T7

11

.

For an ideal power transistor with linear transfer characteristics, the spacing between the curves in the output characteristics is equal, independent of the current level. Consequently, for a fixed RF gate voltage signal strength, the RF output voltage increases with increasing load resistance, while the RF output current remains the same as illustrated in Fig. 2.5 for a higher load resistance. For any given input power level, this results in a higher output power level or in other words

16


a higher RF gain. However, a higher load resistance reduces the maximum excursion of the drain current that can be achieved with increase in input gate signal strength. This results in smaller maximum output power delivered by the transistor. The optimization of the load resistance must take into consideration these conflicting requirements for maximizing the RF power gain and maximizing the output power.

Fig. 2.5 Impact of Load-Line on Power Gain.

Actual power MOSFETs not only exhibit non-linear transfer characteristics but also have significant on-resistances that limit the excursion of the drain voltage on the lower side. In addition, the maximum excursion of the drain current is limited by the current compression phenomenon. As an example, the typical transfer characteristics of an LD-MOSFET would exhibit the behavior illustrated in Fig. 2.6. As the gate voltage exceeds the threshold voltage, the device typically exhibits a square-law behavior due to well-known channel pinch-off effects5. At higher current levels, the onset of current compression tends to linearize the characteristics followed by the current becoming independent of the gate voltage. The impact of this behavior on an RF signal is also illustrated in the figure. Although the RF input voltage makes an equal excursion below and above the quiescent gate

RF Power Amplifiers

17

voltage VGQ, the drain current makes a much smaller excursion below the quiescent drain current IDQ than above this value. This produces a distortion of the input signal.

Fig. 2.6 Non-Linear Transfer Characteristics.

Analysis of the distortion produced by non-linearity in the transfer characteristics can be performed by using a power series representation of the relationship4'6 between the RF output drain voltage vd and the RF input gate voltage vg: vd=a,vg+a2v2g+a,vl

[2.2]

where the coefficients ai, a2, and a3 describe the non-linear behavior of the transfer characteristics. Consider an input signal consisting of two tones (coi, 002) of equal magnitude whose spacing is much smaller than either RF frequency: vg - vcos(tf>,f)-l-vcos(*02f) Then the RF drain voltage is given by:

[2.3]

18


vd = a, v[cos(20]2 + a3v3 [cos(*y,0 + cos(« 2 0] 3 Expanding this equation results in the following frequency terms: DC, CQi, o>2, 2coi, 2a>2, coi+ co^ co r CO2, 2coi+ cc>2, 2co r co^ 2CO2+ ©1, 2a>2- coi, 3(Oi, 3o>2. The frequency terms 2©,, 2(0^ C0]+ CO2, co r CO2, 2coi+ co^ 2CO2+ coi, 3coi, 3(»2 that lie much above or below the frequency of operation can be easily filtered out. However, the third-order products 2co r CO2 and 2a>r C0i are detrimental to cellular base station performance.

Fig. 2.7 Spectrum of a Typical Digitally Modulated Signal.

As illustrated in Fig. 2.7, the inter-modulation distortion (MD3) produced by the third-order distortion products create signals that stretch out to three times the original modulation band limits of (co - COM) to (co + (OM), while the fifth-order distortion products create signals that stretch out to five times the original modulation band limits of (co - C0M) to (co + COM). This spill over of the signal byproducts can interfere with signals being broadcast in the adjacent bands that are used as channels for sending other signals. The presence of the distortion by-products in the sidebands is referred to as "spectral re-growth" and is characterized by the adjacent channel power (ACPR). The amplification of signals by the power transistor is also limited by its on-resistance, quasi-saturation characteristics, and the compression current. This is illustrated in Fig. 2.8 where the output characteristics are shown after incorporating the above phenomena in the

RF Power Amplifiers

19

ideal output characteristics shown earlier. The on-resistance and quasisaturation effects reduce the excursion of the drain voltage to zero as well as the drain current on the upper side. The drain current compression limits the maximum drain current that can be delivered by the transistor. Due to the non-linear transfer characteristics, the drain voltage and current excursions become unequal around the quiescent bias point resulting in distortion. These limitations will be discussed for each of silicon power MOSFET structure in subsequent chapters.

Fig. 2.8 Typical Output Characteristics of a Power Transistor.

With a given input RF gate voltage signal, the drain current and voltage excursions can be predicted by using a resistive load-line and the output characteristics of the transistor at lower frequencies. At higher frequencies, the drain current and voltage excursions are reduced due to the output capacitance of the transistor. Consequently, the responsiveness of an RF transistor in terms of amplifying signals depends up on the frequency of the input signal. In order to characterize this response, two figures of merit are commonly used for power transistors7. The first is related to the RF power gain, which is defined as the ratio of the RF output power to the input power: [2.5]

20


Since this gain depends on the output voltage and current, its value depends up on the choice of the load-line as already discussed earlier. The power gain is commonly expressed in the decibel notation:

GP(JB) = 1 0 1 o g J ^ J

[2.6]

The power gain decreases with increasing frequency for power MOSFETs at the rate of 20 dB per decade of increase in frequency. The frequency at which the power gain becomes equal to unity is defined as the maximum frequency of oscillation or f^x- This is one important figure of merit for transistors because it indicates the highest frequency at which the transistor can be used in power amplifiers. A second commonly used figure of merit for RF transistor is the current gain which is defined as the ratio of the RF output current to the RF input current: [2.7]

Expressed in the decibel notation:

G7 =201og 10 f^.J

[2.8]

where ID and IG are the RF gate current and drain current, respectively. The current gain for power MOSFETs also decreases with increasing frequency at the rate of 20 dB per decade of increase in frequency. The frequency at which the current gain becomes equal to unity is defined as the cutoff frequency or fT. This is an important but less useful figure of merit for RF power MOSFETs. In general, the value of f^ for a particular RF transistor can be either larger or smaller than the value of fT. Due to substantial voltage gain in power transistors designed to operate at high drain voltages, the fmax is usually greater than the fT. Although a power transistor can be used in power amplifier designs as long as the frequency of operation is less than its f^* value, it is usually necessary for the f^x of the transistor to be 2 to 3 times the operating frequency to obtain a reasonable power gain.

RF Power Amplifiers

21

2.3 Class A Amplifier In a class A power amplifier, the transistor is biased as illustrated earlier in Fig. 2.4 with a substantial quiescent drain current at the DC operating point. With an ideal linear transfer characteristic, this produces distortion free signal amplification as long as the drain voltage and current swing is kept within the output characteristics of the transistor. Even with a linear transfer characteristic, these excursions can be limited by the onresistance, the on-set of quasi-saturation, and drain current compression as discussed above.

Fig. 2.9 Output Waveforms under Class A Operation.

Maximum output power can be obtained under class A operation when the drain current and voltage are allowed to swing as shown in Fig. 2.9 to twice their quiescent values on one extreme and to zero on the other. Under these conditions, the maximum value for the RF current becomes equal to the quiescent current and the maximum value for the RF voltage becomes equal to the quiescent voltage: * MAX ~ * DQ> ' MAX ~ ' DQ

[2.9]

Consequently, the maximum RF output power becomes p

-OS*V

r

~

MAX

u

-J

*T v

MAX

l

m m

—O^*V*T

MAX ~

yJ

-->

v

DQ

l

DQ

I>-1"J

22


Since the DC power is given by the product of VDQ and IDQ, the maximum efficiency obtainable under class A operation is 7iMAX = (0.5*V D Q *I D Q )/(V D Q *IDQ)

= 0.5

[2.11]

or 50 percent. Under the class A bias conditions, the transistor must continuously dissipate the DC power even when the signal being amplified is small. For these reasons, class A amplifiers are generally not used in high power amplifiers. 2.4 Class B Amplifier

Fig. 2.10 Output Waveforms under Class B Operation.

The power dissipation in the transistor can be considerably reduced by operating under class B conditions. In an ideal class B amplifier, the quiescent drain current is reduced to zero and the transistor is biased at its threshold voltage. The drain current and voltage excursions under

RF Power Amplifiers

23

these conditions are illustrated in Fig. 2.10 when the maximum output power is being delivered. The drain voltage excursion occurs around the quiescent bias point with a maximum drain voltage of twice the quiescent drain voltage. However, the drain current can flow only during one half of the RF cycle. Fourier analysis of the drain current waveform can be used to extract the DC and fundamental components: [2-12]

1DC = 1MAX I * and * RFMAX =*MAX'2

[2.13]

The efficiency under class B operation then increases to: TJMAX =(0.5*VDQ*IRFMAX)/(VDQ*IDC)

= (x/4)

[2.14]

or a maximum value of about 78.5%. It is worth pointing out that, for a given IMAX for the power transistor, the maximum RF output power delivered under class B conditions is the same as under class A conditions because the class A quiescent current (IDQ) is equal to (IMAX/2). However, the DC current is reduced under class B operation resulting in a higher efficiency and less dissipated power. Moreover, the power dissipation in the absence of an RF input signal is zero in the ideal class B amplifier. 2.5 Class AB Amplifier In the class AB amplifier, the transistor is biased just above its threshold voltage. For a typical LD-MOSFET, as discussed later in the book, the transistor exhibits a square-law relationship between the drain current and the gate voltage when the gate voltage is near the threshold voltage. At higher gate voltages, the transfer characteristics become more linear due to the drain current compression phenomenon which counteracts the square-law behavior due to channel pinch-off. The operation of the transistor with a quiescent drain current as shown in Fig. 2.11 enables operation is a more linear regime than when the transistor is biased just above the threshold of current conduction.

24


Fig. 2.11 Output Waveforms under Class AB Operation.

The efficiency obtained under class AB operation is usually a little below that obtained under class B operation but much higher than under class A operation. A detailed analysis of this can be found in the references1. The power dissipation in the transistor is still substantially less than under class A operation making this the design of choice for base station amplifiers. Operation in class AB with a lower quiescent drain current is of course preferable to reduce the power dissipation. The ability to reduce the quiescent drain current is dependent on the nonlinearity of the transfer characteristics of the transistor near its threshold voltage. The new SL-MOSFET discussed in the book exhibit linear transfer characteristics much closer to the threshold voltage enabling improvement of linearity with higher efficiency and reduced power dissipation.

RF Power Amplifiers

25

2.6 Multi-Stage Power Amplifier A single stage of amplification is not generally utilized in high power RF applications. The MOSFETs used in power amplifiers are designed to provide an RF gain in the range of lOdB to 15dB with multiple stages connected in cascade to boost the signal to adequate levels for broadcasting via the antennae. A gain of less than lOdB is not desirable because it increases the number of stages in the design resulting in high cost. A gain of more than 15 dB is also not generally used because it becomes difficult to prevent oscillations within each stage. A typical line up of power transistors to provide a 200W RF output signal is illustrated in Fig. 2.12, where the intermediate matching, splitting and combining elements are included8.

Fig. 2.12 Multi-Stage Power Amplifier.

A multi-stage amplifier consists of the 'Pre-Driver' stage, the 'Driver' stage, and the 'Output' stage, which operate at increasing power levels. Since the power level for the pre-driver stage is low (2W in the above example), it is possible to operate this stage in the class A mode. The driver and output stages are designed to operate in the class AB mode due to the need to maintain reasonable efficiency at the relatively

26


higher power levels. For these stages, either a single internally matched transistor or several transistors can be used in parallel to achieve the desired power level and gain. The gain of each of the stages is indicated in the figure. The stages must be designed not only with the output power in mind but include the effects of losses within the matching networks, the splitters and the combiners. 2.7 Linearization of Power Amplifiers A stand alone RF power amplifier manufactured using bipolar transistors produces significant distortion with third order inter-modulation products (EVID3 products) in excess of -30 dBc. The introduction of silicon laterally diffused (LD) MOSFETs allowed significant reduction of the distortion so that the IMD level is improved by about 10 dB. However, this is insufficient because the adjacent channel power still exceeds the regulations for broadcasting cellular signals. It is necessary to employ distortion correction circuitry to reduce the EV1D3 levels to within acceptable limits. Linearization techniques allow operation of the power amplifier with less back-off enabling an increase in efficiency. There are three basic approaches to linearization of power amplifiers: Feedback, Feed-forward, and Pre-distortion. The feedback and feed-forward techniques were originally proposed by Black9. In the feedback method, a portion of the output signal is fed back to the input terminal and subtracted from it. The feedback method, which has been successfully used at audio frequencies, is not generally useful for RF power amplifiers because the resultant reduction in gain is too expensive. Feed-forward Linearization The feed-forward technique is the most commonly used method for high power RF amplifiers in cellular base stations to achieve ultra-linear performance. This method can be used to reduce the IMD3 levels by up to 40 dB. Reduction of the distortion products depends up on the signal cancellation over a band of frequencies. Based up on manufacturing tolerances, practical values of distortion reduction are in the range of 25 to 30 dB10.

RF Power Amplifiers

27

Fig. 2.13 Feed-Forward Linearization Circuit.

The basic schematic for the feed-forward circuit is illustrated in Fig. 2.13 in which the signal path is indicated by the arrows. In addition to the input signal being fed to the main amplifier, the input signal is split to another path called the feed-forward path containing the error amplifier. When the signal goes through the main amplifier, it contains the distortion products introduced by the non-linearities in the main amplifier. The distortion products are sampled by using the coupler and fed via the attenuator to combiner 1. At the same time, the input signal is sampled via the splitter and fed in opposite phase to combiner 1 via a delay line to synchronize it to the signal derived from the main amplifier. By adjusting the gain of the attenuator, the main carrier signal is cancelled out leaving the distortion products at the output of combiner 1. This signal containing only the distortion products is amplified by the error amplifier and fed to combiner 2. The output of the main amplifier containing the main carrier signal and distortion products is also fed in opposite phase to combiner 2. By adjusting the gain of the error amplifier, the distortion products can be cancelled leaving just the main carrier signal at the output of combiner 2. In a typical power amplifier design using LD-MOSFETs, the main power amplifier delivers two-tone IMD levels of -30 to -35 dBc at the nominal output power. With feed-forward error correction, the

28


distortion can be reduced by 30dB to levels of better than -60 dBc. However, the output signal of the feed-forward circuit will be distortion free only if the error amplifier does not introduce significant distortion into the error correction path. Any distortion created by the error amplifier appears directly at the output. For this reason, the error amplifier is usually operated in the class-A mode with significant backoff from it peak power capability. The outputs of the error and main amplifiers are combined using a directional coupler that can isolate them from each other using a typical coupling ratio of 10 dB. Consequently, although 90 percent of the output power of the main amplifier reaches the output or load, only 10 percent of the power from the error amplifier reaches the load. This makes the amplification of the error signal relatively in-efficient. The error amplifier is as expensive as the main amplifier because high power transistors are required in the error amplifier to provide sufficient power under the backed-off linear operating conditions. Consequently, implementation of the feed-forward architecture can double the cost of the system. Further, it is necessary to tune the attenuator and the delay lines during manufacturing leading to additional costs. It is also necessary to provide real time gain and phase adjustments after deployment of the amplifier in the field to account for component drift and temperature variations 2 . Due to the low operating efficiency of the error amplifier and the losses in the multiple RF components required to implement the feed-forward architecture, the average efficiency is typically about 10 percent 10 . The development of a super-linear power MOSFET technology that can deliver low inter-modulation products without the need for error correction was motivated by the impetus to reduce system cost and increase efficiency via elimination of the feedforward correction circuit.

Linearization by Pre-distortion If the non-linearity in the transfer characteristics of the main amplifier is well defined, it is possible to negate it by using another RF circuit element to produce an equal and opposite signal distortion before the signal is fed to the power amplifier. The combined transfer characteristics of the pre-distorter and the main amplifier then becomes linear to a higher power level allowing a less expensive design for an available RF power transistor line up. As discussed earlier with regard to

RF Power Amplifiers

29

the output characteristics of RF power transistors, the maximum output power becomes limited by the maximum drain current limit and the finite on-resistance, as well as the quasi-saturation behavior, of the power transistor. This leads to a typical compressive power transfer characteristic shown in the middle of Fig. 2.14 for the main power amplifier. This can be compensated by using a pre-distorter with an expansive transfer characteristic as shown on the left hand side of the figure. This combination extends the operation of the main power amplifier to higher output power levels resulting in lower cost and higher efficiency.

Fig. 2.14 Pre-Distortion Linearization Circuit.

A simple pre-distorter circuit can be constructed by using an RF level dependent resistor combined with a fixed capacitor to oppose the distortion of the power amplifier in the pre-compressive region (around the PldB point where the power gain of the amplifier has reduced by 1 dB)11. The signal dependent resistor can be achieved by using a simple series diode12. However, the linearizing element can itself introduce nonlinearities at lower signal levels. Consequently, for multi-carrier power amplifiers used in cellular base stations, the simple (or analog) predistorter provides only very limited improvement in linearity. In order to obtain the correction levels required for multi-carrier power amplifiers used in cellular base stations, a much greater level of precision becomes necessary. A promising approach to achieve this by utilizing digital signal processing (DSP) technology with a power amplifier distortion look-up table is illustrated in Fig. 2.15.

30


Fig. 2.15 DSP-based Pre-distortion Linearization Circuit.

Here, the input signal strength is sampled using the directional coupler. A look-up table containing the non-linear transfer characteristics of the main power amplifier is then used to generate the necessary amplitude and phase correction signal in the pre-distorter. The precision of DSP circuits can be utilized to achieve good distortion suppression. However, the speed of current DSP circuits is sometimes inadequate, even when operated in an open-loop mode, for some applications. The continual and rapid progress with enhancement of DSP technology favors increased adoption of this linearization method in the future. It is ideally suitable for use with the super-linear transistor where the level of distortion correction is significantly less than with typical LD-MOSFETs. A more detailed discussion of digital pre-distortion can be found in the references cited at the end of this chapter.

2.8 Summary Although class A power amplifiers are often used to achieve a high linearity at low power levels, such as in handsets, the power dissipation becomes prohibitive at high power levels required in base stations. It is common place to operate the transistor under class AB conditions to achieve a good compromise between linearity and efficiency. Depending upon the properties of the transistor, the quiescent drain current is tuned to find an optimum point where the linearity is sufficient while maximizing the efficiency. The transistor datasheets (See links to commercially available datasheets in the Appendix) provide the behavior

RF Power Amplifiers

31

of the inter-modulation distortion products (especially IMD3) as a function of IDQ to enable the power amplifier designer to choose an appropriate operating point.

Linearization _, , . Technique

Performance „ , , Enhancement

„„» . Efficiency

, .,.. Bandwidth

n

2 3 d g

5 g %

15-25 MHz

Analog Pre-distortion

3-5 dB

5-8%

15-25 MHz

Feed-Forward

30 dB

6-10%

25-60 MHz

Digital Pre-distortion

15-20 dB

12-14%

15-20 MHz

In-Line Pre-distortion

Fig. 2.16 Comparison of Linearization Techniques.

The IMD level available from commercially available LDMOSFETs has been insufficient for delivering output signals from power amplifiers without significant adjacent channel interference. The methods for reduction of distortion in power amplifiers are compared in Fig. 2.16, which provides the resulting bandwidth and efficiency as well. The most commonly used method to suppress the distortion products arising from the inherent non-linearity in LDMOSFETs is the feedforward technique. This method allows reduction of IMD by 30 dB with a wide bandwidth but the resulting efficiency is low due to the power losses in the error correction loop. A more efficient method to reduce distortion is with digital pre-distorters. This technique is ideally suitable for design of power amplifiers using SL-MOSFETs because of the inherently better linearity of their transfer characteristics.

32


References 1

S. C. Cripps, "RF Power Amplifiers for Wireless Communications", Artech House, 1999. 2 N. Pothecary, "Feedforward Linear Power Amplifiers", Artech House, 1999. 3 J. Korhonen, "Introduction to 3G Mobile Communications", Artech House, 2001. S.C. Cripps, "RF Power Amplifiers for Wireless Communications", Chapter 1, pp. 6-9, 1999. 5 S. M. Sze, "Semiconductor Devices - Physics and Technology", Section 6.2, pp. 186-192, Second Edition, John Wiley, 1985 and 2002. 6 M.P. van der Heijden, H.C. de Graaff, L.C.N. de Vreede, J.R. Gajadharsing, and J.N. Burghartz, "Ultra-Linear Distributed Class-AB LDMOS RF Power Amplifier for Base Stations", IEEE MTT Proceedings, Abstract WEIF-42, pp. 1373-1366,2001. 7 F. Schwierz and J.J. Liou, "Modern Microwave Transistors", Chapter 1, pp. 9-11, Wiley-Interscience, 2003. 8 N. Pothecary, "Feedforward Linear Power Amplifiers", Artech House, 1999. 9 H.S. Black, "Translating System, U.S. Patent 1,686,792, Issued October 29, 1928 and U.S. Patent 2,102,671, Issued December 1937. 10 F. H. Raab, P. Asbeck, S. Cripps, P.B. Kenington, Z.B. Popovich, N. Pothecary, J.F. Sevic, and N.O. Sokal, "RF and Microwave Power Amplifier and Transmitter Technologies - Part 4", High Frequency Electronics Magazine, pp. 38-49, November 2003. 11 S. C. Cripps, "RF Power Amplifiers for Wireless Communications", Chapter 9, pp. 263-267, Artech House, 1999. 12 K. Horiguchhi, M. Nakayama, Y. Sakai, K. Totani, H. Senda, Y. Ikeda, and O. Ishida, "A High Efficiency Feedforward Amplifier with a Series Diode Linearizer for Cellular Base Stations", IEEE MTT Digest, Abstract WE2B-3, pp. 797-80, 2001.

Chapter 3

MOSFET PHYSICS

The focus of this book is on silicon power MOSFETs used for cellular signal amplification. These devices contain a channel region, which enables control of the output current of the transistor with an applied input voltage, and a drift region, which enables the transistor to operate at high voltages typical of base station power amplifier designs. In the case of silicon MOSFETs, the channel region is constructed by using a Metal-Oxide- Semiconductor (MOS) sandwich that allows modulation of the channel conductivity by the applied gate bias. The voltage controlled nature of the channel makes the biasing of power MOSFETs simpler than competing alternate technologies such as Hetero-junction Bipolar Transistors (HBTs). The physics of operation of the basic Metal-OxideSemiconductor (MOS) sandwich has been treated in many textbooks1'2'3. In the interest of space, this treatment will not be repeated here and readers should look to the references for this material. However, the basic theory underlying channel conduction will be reviewed to enable contrasting the well-know channel pinch-off based operation of MOSFETs to the new super-linear characteristics described for the first time in this book. In addition, the various components of the resistance within the power MOSFET structure will be reviewed because they determine the lowest voltage to which the transistor can operate with the RF signals, thus limiting the output power and the efficiency. Since many of the new super-linear MOSFET structures described in subsequent chapters utilize the charge coupling concept to reduce the onresistance, the basic physics determining the on-resistance for these devices will also be described here.

33

34


3.1 Power MOSFET Structure and Operation In this section, the basic physics of operation of the power MOSFET will be described with the aid of the vertical DMOS structure. The same concepts are applicable to the Lateral MOSFET structure as well. A cross-section of the basic Double-diffused or DMOS structure is illustrated in Fig. 3.1. In addition to the Metal-Oxide-Semiconductor structure formed under the gate region, this structure contains a lighted doped N- drift region that enables supporting high voltages. With the gate shorted to the source terminal by an external bias circuit, the doping concentration of the P-base region is designed so that no channel is formed at the surface. Under these conditions, the drain voltage is supported across the P-base/N-drift region junction. The doping concentration and thickness of the N-drift region must be chosen so that the breakdown voltage of the transistor cell shown in the figure exceeds the desired operating voltage in the application. For a typical cellular base station power amplifier application, the DC supply voltage is nominally at 30V (varies from 28-32 V) with the RF signal superimposed on this DC bias. The transistor must sustain up to 60 V without under-going breakdown. With design margins and accounting for electric field enhancement at the edge termination3, the transistor cell must be designed to support about 80 V.

Fig. 3.1 Vertical Power D-MOSFET Structure.

MOSFET Physics

35

The design rules for determination of the doping concentration and thickness of the drift region for obtaining a desired breakdown voltage are derived in reference 3. The relevant equations are:

„

(5.34*10" Y "

[3.1]

which allows calculation of the doping concentration (ND) of the N-drift region for a desired breakdown voltage (BV) and: WD =2.67;cl0 10 ./V D 7/8

[3.2]

which allows calculation of the thickness (WD) of the N-drift region. For the case of the RF power MOSFETs used in base stations with a breakdown voltage of 75-80 V, the drift region doping concentration is found to be about 5 x 1015 cm"3 and its thickness is approximately 5 microns. The resistance for 1 cm2 of area for this drift region is referred to as the specific on-resistance of the drift region. For silicon, the specific on-resistance of the drift region can be calculated using the following expression:

J U = P V ] = 5.93x10- (BV)25

[3.3]

Since this resistance was initially considered to be the lowest value achievable with silicon devices, it has historically been referred to as the ideal specific on-resistance of the drift region. More recent introduction of the charge-coupling concept, described later in this chapter, has enabled reducing the drift region resistance of silicon devices to below the values predicted by this equation. When a positive bias is applied to the gate of the power MOSFET, a channel is induced at the surface of the P-base region by the formation of an inversion layer. A detailed discussion of the physics of formation of inversion layers can be found in the references 1-3. Under strong inversion conditions, where the gate bias substantially exceeds the threshold voltage for formation of the inversion layer, the charge in the inversion layer is given by: Qim=Cox{Vc-VT)

[3.4]

where Cox is the capacitance per unit area of the gate MOS structure, VG is the applied gate bias and VT is the threshold voltage. The gate oxide

36


capacitance per unit area {specific gate capacitance) can be obtained using: [3.5] V ox )

where eox is the dielectric constant for silicon dioxide (3.41xlO13 F/cm) and tox is the gate oxide thickness. If the drain voltage is well below the gate bias, the charge in the channel becomes uniform allowing calculation of the channel resistance using: Rch =

= ZMinvQinv

[3.6] ZjUinvC0X(VG-VT)

where (J.inv is the inversion layer mobility. The channel resistance, together with the JFET and accumulation resistances, adds to the drift resistance (after accounting for spreading resistance effects) to determine the total on-resistance of the power MOSFET. A more detailed analysis of these resistance components is provided in section 3.3. The threshold voltage is an important parameter for power MOSFETs because it determines not only the on-resistance, as discussed above, but has an impact on the leakage current when the device is supporting high voltages. An equation for the threshold voltage can be derived by using the transition point from weak into strong inversion:

\£ox'Kx)

K

_

LD-MOSFET ~

'-'LDP

^

r ., C f t l

[ 3 - 50 J

For silicon devices, the optimum charge is found to be lxlO12 cm"2. Typical electric field values just before the on-set of breakdown are 2.5x105 V/cm along the surface of the LDD region. Using this value, the length (LLDD) of the LDD region required to support 75-80 V is determined to be about 3 microns. Due to junction curvature effects, the LDD length is about 5 microns in practical devices. Using these parameters, the LDD region resistance is found to be about 30 ohms/mm. This determines the on-state voltage drop across the power LDMOSFET, which limits the minimum swing of the drain voltage. 3.4 Summary In this chapter, the physics of operation of the super-linear (SL) MOSFET structure has been contrasted with that of the conventional MOSFET structure by deriving analytical equations that describe the current transport in both types of devices. It has been demonstrated that the conventional MOSFET structure exhibits a square law relationship between the output drain current and input gate voltage, which leads to distortion of signals during power amplification. In contrast, the output drain current for the SL-MOSFET increases linearly with increasing input gate voltage. The results of this theoretical analysis will be compared with the characteristics obtained for specific device structures in subsequent chapters. For the super-linear devices, it has been shown that the drain current-voltage characteristic follows the velocity-field curve for silicon, irrespective of the gate bias. As a consequence, the drain current saturation occurs at the same drain current independent of the gate bias. This is a signature for power MOSFETs that are operating in the superlinear mode. In contrast, in conventional power MOSFETs operating under channel pinch-off physics, the drain current saturates at larger drain voltages as the gate voltage is increased. In addition, in this chapter, analysis of the on-resistance of the power MOSFET structure has been performed. This on-resistance limits the excursion of the drain voltage under large signal amplification conditions. A reduced on-resistance is beneficial for increasing this excursion and improving the power efficiency. It has been demonstrated

MOSFET Physics

69

that the on-resistance can be reduced using the charge coupling concept. This method, called RESURF, has been found to be effective for reducing the on-resistance of lateral MOSFETs. By using a graded doped drift region and an electrode with deep trenches etched into the drift region, charge coupling has also been utilized to reduce the on-resistance of vertical power MOSFETs.

70


References 1

S.M. Sze, "Semiconductor Devices - Physics and Technology", Second Edition, John Wiley, 1985 and 2002. 2 Y. Taur and T.K. Ning, "Fundamentals of Modern VLSI Devices", Cambridge University Press, 1988-2002. 3 B.J. Baliga "Power Semiconductor Devices", PWS Publishing Company, 1996. 4 D. A. Grant and J. Gowar, "Power MOSFETs - Theory and Applications", John Wiley and Sons, 1989. 5 F. Schwierz and J.J. Liou, "Modern Microwave Transistors - Theory, Design, and Performance", Wiley-Interscience, 2003. 6 B.J. Baliga, "MOSFET Devices having Linear Transfer Characteristics when operating in Velocity Saturation Mode and Methods of Forming and Operating Same", U.S. Patent Number 6,545,316, Issued April 8, 2003. 7 C. Canali, G. Majni, R. Minder, and G. Ottaviani, "Electron and Hole Drift Velocity Measurements in Silicon", IEEE Trans. Electron Devices, Vol. ED-22, pp. 1045-1047, 1975. 8 D. A. Grant and J. Gowar, "Power MOSFETs - Theory and Applications", John Wiley and Sons, 1989. 9 G. Deboy, M. Marz, J.P. Stengl, H. Strack, J. Tihanyi, and H. Weber, " A New Generation of High Voltage MOSFETs breaks the limit line for Silicon", IEEE International Electron Devices Meeting Digest, pp. 683685,1998. 10 B.J. Baliga, "Vertical Field Effect Transistors having improved Breakdown Voltage and Low On-Resistance", U.S. Patent # 5,637,898, Issued June 10, 1997.

Chapter 4

Lateral-Diffused MOSFETs

Until the mid-1990s, the cellular RF power amplification applications were based upon utilizing either silicon bipolar transistors or gallium arsenide MESFETs. The introduction of the high voltage lateral-diffused (LD) MOSFET in the latter part of the 1990s altered the market dynamics. Articles written in this timeframe1 describe the LD-MOSFET as a novel technology that is starting to challenge the entrenched position of the silicon bipolar transistor because of reduced distortion, while being more competitive than the gallium arsenide devices due to significantly lower cost. However, significant concerns regarding the ruggedness and reliability of the LD-MOSFETs were prevalent in the industry. Within a few years2, the LD-MOSFETs had successfully displaced the silicon bipolar transistors and shut out the gallium arsenide devices from the cellular base-station market. Improvements in its efficiency and linearity provided significant cost-performance benefits to the end user. In addition, these devices could be operated using a single 28-V supply. However, the drift of the threshold voltage of the transistor during operation at the quiescent operating point continued to haunt the technology. In spite of several generations of technology improvements, the manufacturers could only guarantee a change of less than 10 percent over a 20 year time span in spite of using burn-in to stabilize the devices. The drift in threshold voltage, arising from an injection of hot-electrons into the gate oxide, created a major problem in obtaining stable performance. Fortunately, further structural and process enhancements during the last few years have brought the threshold drift to below 5 percent over a 20 year time span without the expense of performing burn-in. This is believed to be satisfactory for operation of the transistors in power amplifiers without adding costly bias adjustment circuitry. Manufacturers continue to optimize the device structure and process to improve up on the efficiency, linearity, and gain by scaling down the 71

72


channel length and gate oxide thickness while monitoring any degradation in the drift and reliability. In addition, methods for reducing the thermal impedance are a high priority because a rise in channel temperature is detrimental to the gain and linearity. In this chapter, the basic operating principles of the LDMOSFET structure will be discussed. The physics of operation will be elucidated by using the results of two-dimensional numerical simulations3 of a typical cell design. Although the exact values for the doping profiles, the gate oxide thickness, and channel length may vary from manufacturer to manufacturer, the basic structure for the LDMOSFET used in the industry is similar to that described in this chapter. It is commonplace to analyze the RF performance of these devices by using special programs4 with circuit models for the transistor. However, this requires extraction of equivalent circuit parameters for the transistor which must be approximations due to the non-linear nature of some of the circuit elements. An improved approach used in this book utilizes time dependent numerical simulations of the device cell structure with an RF sinusoidal waveform superposed on the DC quiescent operating conditions with a resistive load line. This allows observation of both the steady-state and transient response intrinsic to the silicon transistor at the frequency of choice.

4.1 Device Cell Structure

Fig. 4.1 Lateral-Diffused (LD) MOSFET Structure.


73

A cross-section of the basic cell structure for the Lateral-Diffused (LD) MOSFET is illustrated in Fig. 4.1. The device is fabricated by starting with a P-type epitaxial layer grown on a heavily doped P+ substrate. As implied by the name, the channel is formed by the difference in lateral extension of the P-base and N* source regions produced by their diffusion cycles. Both regions are self-aligned to the left-hand-side of the gate region during ion-implantation to introduce the respective dopants. In order to enable high voltage operation with short channel lengths, a lightly doped drain (LDD) region is formed on the right-hand-side of the gate by implantation of an N-type dopant. The charge in the LDD region and its length along the surface between the gate edge and the drain edge must be optimized to maximize the breakdown voltage. A highly doped, deep P+ sinker region is also incorporated in the structure to connect the source region to the P+ substrate. This allows mounting the chip to the flange of the RF package to create a source connected ground plane without the detrimental effects of source wire-bonds. The doping concentration and length of the P-base region is designed to avoid reach-through breakdown. The Reduced Surface (RESURF) effect5 is utilized to distribute the electric field into the LDD region. It has been found that a charge of about 1 x 1012 cm"2 is optimal for obtaining the highest breakdown voltage. When the charge is too low, a high electric field is created at the drain side of the LDD region reducing the breakdown voltage. In contrast, if the LDD charge is too high, a high electric field is created at the gate edge resulting in low breakdown voltages. In order to obtain a breakdown voltage of 75-80 V, it is necessary to make the length of the LDD region between the gate and the drain at least 5 microns. The breakdown voltage can also be limited by the maximum voltage that can be supported in the vertical direction under the N4" drain region. This breakdown voltage is determined by the thickness and doping concentration of the P-type epitaxial layer. The high electric field at the gate edge in the LD-MOSFET structure has been a major drawback because it enhances hot electron injection into the gate oxide. Unlike power switching MOSFETs, the RF power MOSFETs operate under a constant quiescent DC voltage and current under class A and class AB conditions as discussed in Chapter 2. If the electric field at the gate oxide is large, the electrons can gain sufficient energy to be launched into the gate oxide and become captured by traps in the oxide. The charge contributed by the trapped electrons causes a shift in the threshold voltage which is referred to as the drift

74


phenomenon in LD-MOSFETs. This instability in LD-MOSFETs has been a major concern for the industry resulting in various proposed solutions. Some of these solutions are discussed later in this chapter. Drain current flow in the LD-MOSFET structure is induced by the application of a positive bias to the gate electrode. This produces an inversion layer at the surface of the P-base region under the gate electrode. This inversion layer channel provides a path for transport of electrons from the source to the drain when a positive drain voltage is applied. Due to the high electric field at the edge of the gate during high voltage operation, the channel length of the LD-MOSFET must be sufficiently long to avoid reach-through of the depletion layer in the Pbase region. Consequently, the LD-MOSFETs operate with channel pinch-off as the drain voltage increases as described in Chapter 3 resulting in a square law relationship between the drain current and the gate voltage. In the LD-MOSFET structure, the drain current flows along the surface from the drain electrode to the top surface source electrode. The current is then re-directed via the deep P+ sinker region into the P+ substrate. The on-resistance of the structure is determined not only by the resistance of the channel and drift region but also by the resistance of the P-type substrate: R

on,sp = RCH,Sp + RD,sp + RSUBS,Sp

I4-1]

In this equation, the specific channel resistance RCH,SP is given by: J W K

CH,sp ~

(y _y ) V H-invôxVG T ) c

L4 ZJ

*

where LCh is the channel length, WP is the cell pitch, |j. inv is the channel inversion layer mobility, Cox is the specific oxide capacitance of the gate stack, VG is the applied gate voltage, ad VT is the device threshold voltage. The specific drift region resistance RDsp is given by: R

D,sp ~ —-Z VMnQLDD

[4-3J

where LLDD and QLDD are the length and charge for the lightly doped drain region, and (On is the bulk mobility for electrons in the LDD region. The specific substrate resistance RSUBS,SP is given by:

Lateral-Diffused MOSFETs R SUBS,sp

=

P SUBS* SUBS

75 W- 4 ]

where PSUBS and tSuBs are the resistivity and thickness of the P+ substrate. For a typical LD-MOSFET designed to support 75-80 V, although the length of the LDD region is about 5 microns, the cell pitch is about 15 microns because of the space taken by the deep P+ diffusion and the interdigitated metal contacts for the drain and source. The width of the drain metal is insufficient to allow bonding wires to connect the drain to the package terminal. It is necessary to carry the drain current along the drain metal fingers in the orthogonal direction to the transistor cell cross-section shown in Fig. 4.1 to a drain bonding pad. As the drain current is collected along the finger, the current level, and hence the current density in the drain metal, becomes larger towards the drain bonding pad. The drain metal must be sufficiently thick so that electromigration failures are mitigated during device operation. It is commonplace to use gold metallization in RF LD-MOSFETs, instead of the usual aluminum metal used in power MOSFETs, because of its enhanced resistance to electromigration effects. However, this requires special metal deposition and patterning facilities during device manufacturing.

4.2 LD-MOSFET Simulation Structure

Fig. 4.2 Structure for LD-MOSFET Simulations.

76


Two-dimensional numerical simulations of the LD-MODSFET structure were performed using the structure illustrated in Fig. 4.2 with a gate length (LG) of 2 micron and a drift region length (LLDD) of 4.5 microns. These values are typical for structures reported in the technical literature6'7'8. The thickness and doping concentration for the P-type epitaxial layer were chosen as 3 microns and 1 x 1015 cm"3, respectively. After including the space for the deep P+ sinker diffusion, with a depth of 4 microns, and the drain/source top metal contacts, the cell pitch was 15 microns. As discussed below, the results of numerical simulations are described for structures with two gate oxide thicknesses. The impact of changes to the charge in the LDD drift region was obtained by changing the dose for the N-type dopant in this region. In addition, in order to illustrate the issues associated with conduction of heat from the top surface to the bottom source contact, simulations are described for several cases of P+ substrate thickness (tSuBs)- In these simulations, a non-isothermal condition was chosen with the heat sink located at the bottom source contact. This represents the mounting of the device to the flange on the package.

Fig. 4.3 Three Dimensional Doping Profile for LD-MOSFET Structure.


77

The doping profile used for the simulations of the LD-MOSFET structure is shown in Fig. 4.3. The source and drain N* regions are on the upper left and right sides, respectively. The P-base and LDD drift regions are located between these diffusions. The deep P+ region extends on the left hand side through the P-type epitaxial layer into the P+ substrate. The P+ substrate is located below the plot in the y-direction. The doping profile for the channel is shown in Fig. 4.4 from just beyond the left hand edge of the gate into the LDD region. The channel length (L C H) is 1.2 microns and the peak doping concentration in the P-base region is 3.5 x 1017 cm 3 . These values are typical for devices reported in the literature6.

Fig. 4.4 Channel Doping Profile for LD-MOSFET Structure.

4.3 LD-MOSFET Blocking Characteristics In all the simulations, the bottom source electrode was held at ground potential and the upper surface source contact was left floating using a zero current boundary condition. The ability of the LD-MOSFET to support the required blocking voltage of above 75-80 V was verified by performing simulations with the gate held at ground potential. The breakdown voltage for the structure was found to be about 80 V for the case of an LDD region N-type dose of 1 x 1012 cm"2.

78


Fig. 4.5 Potential Contours at Vds=70V for the LD-MOSFET Structure.

The potential contours are shown in Fig. 4.5 for a drain bias of 70 volts. It can be seen that the drain voltage is supported laterally across the LDD-region between the edge of the gate and the drain N+ diffusion and supported vertically below the N+ drain within the P-epitaxial layer.

Fig. 4.6 Electric Field Profiles in the LD-MOSFET Structure with LDD-Dose of 1 x 1012 cm'2.


79

For the chosen LDD dose of 1 x 1012 cm"2, the potential lines are uniformly spaced within the LDD-region indicating an approximately constant electric field as shown in Fig. 4.6 at the top surface. This is considered to be an optimal dose for RESURF devices5.

Fig. 4.7 Electric Field Profiles in the LD-MOSFET Structure with LDD-Dose of 6 x 1012 cm"2.

Fig. 4.8 Impact of LDD-dose on Electric Field Profiles at Vds=40 V in the LD-MOSFET Structure.

80


For a RESURF device, the resistance contribution from the LDD region can be reduced by increasing the charge. However, this results in a redistribution of the electric field with a higher value near the gate edge as illustrated in Fig. 4.7 for the case of an LDD dose of 6 x 1012 cm"2, hi this case, the high electric field at the gate edge reduced the breakdown voltage to 42 V because of the on-set of impact ionization. This shift in the electric field profile is also illustrated in Fig. 4.8 where the electric field profiles for the case of LD-MOSFET structures with LDD doses of 1, 3, and 6 x 1012 cm"2 are compared at a drain bias of 40 V. The change in the breakdown voltage of the LDMOSFET with increase in the LDD-dose is shown in Fig. 4.9. It can be seen that the breakdown voltage decreases rapidly when the LDD dose exceeds 4 x 1012 cm"2. This is due to the enhanced electric field at the gate edge. This field enhancement at the gate edge is detrimental to device stability because of the injection of hot electrons into the gate oxide under quiescent bias conditions as discussed later in the chapter.

Fig. 4.9 Impact of LDD-dose on Breakdown Voltage and On-Resistance for the LD-MOSFET Structure.

4.4 LD-MOSFET On-State Characteristics When a positive bias above the threshold voltage is applied to the gate of the LD-MOSFET, an inversion layer channel is formed at the surface of


81

the P-base region. This provides a path for the transport of electrons between the drain and source terminals. In the case of the LDMOSFETs, the source current is diverted into the P+ substrate as shown in Fig. 4.10 by using the deep P+ sinker region. It is worth pointing out that the current flows primarily in the upper part of the LDD region because this portion has a higher doping concentration and because its lower portion is depleted by the built-in potential of the P-N junction formed between the N-type LDD region and P-type epitaxial layer. At a gate bias of 10 volts, the on-resistance was found to be 61 Ohms/mm of device width for the LDD-dose of 1 x 1012 cm"2. It can be reduced by increasing the LDD dose as shown in Fig. 4.9 to about 30 Ohms/mm without reducing the breakdown voltage. However, the higher electric field at the gate will degrade the stability of the device.

Fig. 4.10 On-Stale Current Flow in the LD-MOSFET Structure.

4.5 LD-MOSFET Output and Transfer Characteristics The output characteristics for the LD-MOSFET structure with an LDDdose of 1 x 1012 cm"2 arc shown in Fig. 4.11 for gate bias voltages ranging from 3.5 to 7.5 V (in 0.5 V increments). It can be seen that the output resistance decreases at high drain voltages due to the on-set of impact ionization. The non-linear increase in drain current with

82


increasing gate voltage is obvious from the increasing separation between the various curves.

Fig. 4.11 Output Characteristics of the LD-MOSFET Structure.

Fig. 4.12 Transfer Characteristics of the LD-MOSFET Structure.

The non-linear behavior can also be observed in the transfer and transconductance curves for the LD-MOSFET structure. The transfer curve, shown in Fig. 4.12, exhibits a square law behavior followed by the on-set of current compression at a gate bias of 7 volts. The


83

transconductance, shown in Fig. 4.13, increases approximately linearly with gate voltage until 7 volts and then rapidly decreases due to the compression phenomenon. This compression effect has been ascribed to the JFET-like current pinch-off in the drift region6. As shown in the figures, the threshold voltage decreases with increase in temperature. In addition, the compression current reduces with increasing temperature. This behavior is similar to that reported for LD-MOSFETs in the literature9. The reduction in the transconductance and compression current are detrimental to RF performance.

Fig. 4.13 Transconductance of the LD-MOSFET Structure.

4.6 LD-MOSFET Capacitances The input, output and reverse transfer capacitances for the LD-MOSFET structure were extracted by performing two-dimensional numerical simulations of the cell structure with a 1 MHz ac-signal applied to appropriate electrodes. In datasheets, it is customary to display these parameters as a function of the drain bias. The input capacitance (Cgs) has a weak dependence on the drain voltage. For the LD-MOSFET with 500 angstrom gate oxide, the input capacitance was found to be 1.2 pF/mm of device width. The output and reverse transfer capacitances are highly non-linear due to their dependence on the depletion width which is a strong function of the drain voltage. In the LD-MOSFET structure,

84


the output capacitance is primarily determined by the drain-to-substrate junction. These capacitances are shown in Fig. 4.14. At a drain bias of 30V, the output capacitance (Cds) has a value of 0.25 pF/mm and the reverse transfer capacitance (Cgd) has a value of 0.01 pF/mm. These values are similar to those reported in the literature6 and device datasheets10.

Fig. 4.14 Capacitances in the LD-MOSFET Structure.

4.7 LD-MOSFET RF Performance It is customary to extract the large signal RF performance of power MOSFETs by first constructing a circuit model that can then be used in an RF simulator such as ADS. A major problem with this methodology is the difficulty of creating an equivalent circuit that effectively mimics the device characteristics under large dynamic swings in drain current and voltage. For this reason, an alternative method based up on simulation of the temporal response of the complete two-dimensional device structure has been utilized in this book. In this approach, the sinusoidal RF input gate voltage is discretized into time intervals that are a small fraction of the time period of the RF signal. Within each time interval, the gate voltage is ramped to the value of the sinusoidal voltage pertaining to the end of the interval. This method allows simulation of the RF response of


85

the device structure over several time periods of the RF signal. Both the steady-state and the transient response of the device structure can then be observed.

Fig. 4.15 RF Load-line for the LD-MOSFET Structure.

Fig. 4.16 RF Input Gate Signal.

The RF response of the LD-MOSFET when biased in the class A mode was analyzed by using the load-line shown in Fig. 4.15 with a

86


quiescent drain voltage of 30 volts. The load-line was chosen to obtain the largest output power by maximizing the swing in the drain current and drain voltage. An RF input gate signal with maximum value of 0.5 V (rms value of 0.35 V) was superimposed up on the 6 V DC gate bias point. The resulting input gate voltage waveform is shown in Fig. 4.16. This resulted in a RF drain voltage shown in Fig. 4.17. It can be seen that drain voltage exhibits an exponential transient response superposed on the steady-state AC response. The drain current is a mirror image of the drain voltage because of the resistive load-line used for this simulation. Using the gate and drain currents and voltages obtained using this simulation methodology, the current gain, power gain, as well as the output power, could be extracted using the maximum and minimum values of the sinusoids after the transient is completed to obtain the rms values for the RF signals.

Fig. 4.17 RF Output Drain Signal.

The frequency response of the transistor was obtained by repeating the temporal simulations at a variety of frequencies ranging from 0.1 to 16 GHz. The reduction in the current gain and power gain is shown in Fig. 4.18. This behavior is similar to that predicted by the analytical solutions in Chapter 3 (see Fig. 3.9). The cut-off frequency and maximum operating frequency are 1.1 and 2.6 GHz, respectively.


87

Fig. 4.18 Current and Power Gain for the LD-MOSFET Structure.

Fig. 4.19 RF Output Power for the LD-MOSFET Structure.

The change in the output power with increasing frequency was obtained by performing the temporal simulations at a variety of frequencies ranging from 0.1 to 16 GHz with an input gate voltage of 0.5 volts. The reduction in the output power can be seen in Fig. 4.19. This behavior is in good agreement with the analytical predictions in Chapter 3 (see Fig. 3.10). A larger output power can be derived from this structure by using a larger ac gate drive voltage. Base upon the available drain current and voltage excursions within the domain of the output

88


characteristic shown in Fig. 4.15, the maximum RF output power that can be obtained from the LD-MOSFET structure is about 0.3 W/mm of cell width. This is consistent with values reported in the literature. 4.8 LD-MOSFET Thermal Effects As discussed in Chapter 3, an increase in the device temperature leads to degradation in RF performance due to the reduction in the channel inversion layer mobility. Isothermal simulations at elevated temperatures allow an assessment of the change in the transfer curve and transconductance as already shown in Fig. 4.12 and Fig. 4.13, respectively. The change in the output characteristics is shown in Fig. 4.20. The saturated drain current increases with temperature due to a reduction in the threshold voltage. This effect becomes weaker at larger gate voltages due to the impact of the mobility reduction.

Fig. 4.20 Effect of Temperature on the Output Characteristics of the LD-MOSFET Structure. (Solid Line: 300K; Dashed Line: 400K; Dotted Line: 500K)

When the LD-MOSFET is used in amplifiers, the chip is soldered down to the flange of the package which is then mounted on a


89

heat sink. Since the high electric field in the LD-MOSFET structure is located within the LDD-region, most of the power dissipation occurs within about 5 microns at the top of the silicon chip. Consequently, the heat must flow through the P+ substrate to the bottom source contact and then into the flange. This results in a thermal gradient across the wafer. In order to understand the impact of this gradient, non-isothermal simulations were performed for the LD-MOSFET structure with the bottom of the wafer held at a constant temperature of 300° K. The first example of non-isothermal simulations is shown in Fig. 4.21 for the case of 200 micron substrate thickness. For purposes of comparison, the isothermal characteristics are also shown in this figure. It can be seen that the characteristics undergo distortion as a consequence of the temperature rise.

Fig. 4.21 Non-Isothermal Output Characteristics of the LD-MOSFET Structure. (Solid Line: Isothermal; Dashed Line: Non-Isothermal)

The temperature distribution within the LD-MOSFET structure can be observed in the temperature contours shown in Fig. 4.22 for the case of Vgs=6V and Vds=60V. The highest temperature is observed within the LDD-region because it supports the electric field under the high drain bias conditions resulting in power dissipation in this region followed by heat flow downwards through the P+ substrate.

90


Fig. 4.22 Temperature Contours for the LD-MOSFET Structure for 200 micron substrate (Vgs=6V, V J S =60V).

Fig. 4.23 Surface Temperature in the LD-MOSFET Structure for 200 micron substrate (Vgs=6V, Vds=60V).

The temperature variation along the top surface for the same bias point is shown in Fig. 4.23. It can be observed that the highest


91

temperature occurs in the LDD region towards the drain end. However, the temperature at the channel increases to 563° K (290° C) generating concerns regarding the reliability. The vertical temperature profile at the channel is shown in Fig. 4.24 for the same bias point. The heat flow through the thermal impedance of the P+ substrate is responsible for the increase in channel temperature.

Fig. 4.24 Thermal Gradient in the LD-MOSFET Structure for 200 micron substrate thickness

Fig. 4.25 Thermal Gradient in the LD-MOSFET Structure for 100 micron substrate thickness

92


Due to the significant thermal impedance of the silicon substrate, it is common practice to reduce its thickness in spite of the complications with wafer handling and breakage. The benefit of reducing the substrate thickness from 200 microns to 100 microns is illustrated in Fig. 4.25. The channel temperature is now reduced to 394° K (121° K) which is acceptable from the reliability standpoint.

Fig. 4.26 Non-Isothermal Output Characteristics of the LD-MOSFET Structure. (Solid Line: Isothermal; Dashed Line: Non-Isothermal)

The lower channel temperature rise results in much less distortion of the output characteristics as shown in Fig. 4.26 for the device with 100 micron P+ substrate thickness. Recently, substantial improvements in the RF performance of LD-MOSFETs have been reported by reducing the substrate thickness to 50 microns11. 4.9 LD-MOSFET with Faraday Shields When first introduced as a product, one of the major concerns regarding the LD-MOSFET structure was the observation of a change with time in the device characteristics when biased at the quiescent operating point1'2. This so-called "drift" problem was exhibited as a change in the threshold voltage of the device with time. It was recognized that this phenomenon


93

was caused by the high electric field at the gate edge12. A detailed analysis of the 'drift-problem' is provided in Chapter 11 in this book.

Fig. 4.27 LD-MOSFET Structure with Faraday Shield.

The hot carrier induced drift problem in LD-MOSFET structure can be ameliorated by employing a Faraday shield (connected to the source terminal) within the LD-MOSFET structure. The basic structure of the LD-MOSFET device with a Faraday shield is illustrated in Fig. 4.27. The Faraday shield screens the gate from the drain potential and moves the high electric field away from the gate edge. It also reduces the reverse transfer capacitance which results in better RF performance. To illustrate the trade-offs in utilizing the Faraday shield, two examples of LD-MOSFET structures are discussed below. In the first LD-MOSFET structure, the Faraday shield is implemented by using the polycide gate stack to form an additional source connected electrode which is isolated from the LDD region by the gate oxide13. The interposition of this source connected electrode between the gate and drain electrodes requires added space which makes the cell pitch of the device larger. For the simulated device structure, the cell pitch was increased from 15 microns to 19 microns because of the addition of a 2 micron wide Faraday shield electrode spaced at 1 micron from the gate edge. The potential contours for this structure at a drain bias of 70 volts are shown in Fig. 4.28. It can be observed that the potential contours terminate at the Faraday shield instead of the gate edge. This isolates the gate oxide from high electric fields which mitigates the drift problem. The reduced electric field at the gate edge is

94


shown in Fig. 4.29. All the increase in drain bias is supported between the drain and the edge of the Faraday shield.

Fig. 4.28 Potential Contours for LD-MOSFET Structure with Faraday Shield at Vds=70V and Vgs=0V..

Fig. 4.29 Electric Field Profile for LD-MOSFET Structure with Faraday Shield.


95

As expected the Faraday shield was found to be very effective in reducing the reverse transfer capacitance (Cgd). In comparison with a value of 0.01 pF/mm for the conventional LD-MOSFET structure, the Cgd was reduced by about 100 times. Unfortunately, these improvements were found to be accompanied by a significant reduction (5x) in the compression current as shown in Fig. 4.30.

Fig. 4.30 Transfer Characteristics for LD-MOSFET Structure with Faraday Shield.

The reduction in the compression current is due to the depletion of the LDD region under the Faraday shield. The reduced compression current greatly limits the output power than can be derived from this structure. This effect can be counteracted by using additional implant steps to enhance the doping under the Faraday shield but this will also reduce the screening of the gate region by the Faraday Shield. The second LD-MOSFET structure with Faraday shield is implemented with the Faraday Shield electrode located at the top of the field oxide increasing its separation from the LDD region. This structure was analyzed by using a field oxide thickness of 1 micron with the source electrode extending 3 microns beyond the edge of the gate. This structure can be fabricated using the source metal as the field plate as implied in Fig. 4.29. The extension of the source metal towards the drain also requires a widening of the LD-MOSFET cell from 15 microns to 19 microns.

96


Fig. 4.31 Potential Contours for LD-MOSFET Structure with Faraday Shield V j ^ O V and Vgs=OV..

Fig. 4.32 Electric Field Profile for LD-MOSFET Structure with Faraday Shield.

The potential contours for the second LD-MOSFET structure with Faraday Shield are shown in Fig. 4.31 for the case of a drain bias of

Lateral-Diffiised MOSFETs

97

70 volts. The potential contours have a greater separation below the Faraday shield indicating a reduction in the electric field in this region. The reduced electric field is shown in Fig. 4.32 at a drain bias of 70 volts. It can be seen that the Faraday shield screens the gate but is not as effective as in the previous structure. Consequently, it was found that the reverse transfer capacitance for this structure was only 14x lower than for the conventional structure. However, this is still a substantial improvement which is accompanied by much less reduction of the compression current. A more modest 2x improvement in Crss has been reported for an LD-MOSFET with Faraday shield on thick field oxide11.

Fig. 4.33 Transfer Characteristics for LD-MOSFET Structure with Faraday Shield.

The compression current for the second LD-MOSFET structure with Faraday shield can be obtained from Fig. 4.33 which shows the transfer curve for this device. Its value is 50 percent of that of the conventional LD-MOSFET structure. The compression current can be increased by adding another implant step to increase the doping concentration below the Faraday shield electrode but this adds to the process cost and complexity1 .

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4.10 LD-MOSFET with Thinner Gate Oxide

Fig. 4.34 Output Characteristics for LD-MOSFET Structure with Thinner Gate Oxide.

Fig. 4.35 Transfer Characteristics for LD-MOSFET Structure with Thinner Gate Oxide.

As discussed in Chapter 3, the performance of power MOSFETs can be improved by reducing the gate oxide thickness. In order to evaluate the


99

behavior of the LD-MOSFET structure, two-dimensional numerical simulations of the device shown in Fig. 4.1 were repeated using a gate oxide thickness of 250 angstroms. All other structural parameters were left unaltered. As expected, reduction of the gate oxide thickness resulted in an increase in the transconductance and a decrease in the threshold voltage. The impact of this on the output and transfer characteristics is shown in Fig. 4.34 and 4.35, respectively. However, the transconductance is still a strong function of the gate bias, as shown in Fig. 4.36, because of the "square-law" behavior.

Fig. 4.36 Transconductance of the LD-MOSFET Structure with Thinner Gate Oxide.

For the LD-MOSFET structure with reduced gate oxide thickness, the values of input, output and reverse transfer capacitances were found to be 2.4, 0.25, and 0.01 pF per mm of cell width, respectively, at a drain bias of 30 volts. Thus, the reduced gate oxide thickness results in an increase in the input capacitance without altering the other capacitances. The reduced gate oxide thickness improves the frequency response of the LD-MOSFET structure because of the larger transconductance. The current and power gains are shown in Fig. 4.37 as

100


a function of frequency. At 1 GHz, the power gain with the thinner oxide is 14.5 dB compared with 12.5 dB for the 500 angstrom gate oxide case. The maximum operating frequency is also improved slightly. There is no change in the maximum output power that can be delivered from the structure.

Fig. 4.37 Current and Power Gain for the LD-MOSFET Structure.

4.11 LD-MOSFET Conclusions In the 1990s, the silicon LD-MOSFET technology displaced silicon bipolar transistor technology for high power RF applications due its superior linearity. Continuous enhancements in its performance over many generations (some manufacturers are reporting sixth and seventh generation products in 2004) of devices have allowed refining the structure to deliver good gain and efficiency for cellular base station applications in the 0.8 to 2.2 GHz range. However, the linearity of the device is still considered inadequate resulting in the inclusion of feedforward linearization circuits within base station amplifiers. This chapter has provided information regarding the underlying physics of the LD-MOSFET structure, where the channel operates in the pinch-off mode during current saturation. The results of two-dimensional

Lateral-Difftised MOSFETs

101

numerical simulations have been provided to describe its DC and RF characteristics. These characteristics will be used as a benchmark when discussing other structures described in this book.

102


References 1

S. Ohr, "Lateral DMOS gains on GaAs in Cellular Basestations", EE Times, February 10, 1999. 2 A. Bindra, "Lateral-diffused MOS power transistors vie for poweramp sockets by improving efficiency, linearity, peak power, and costper-watt", Electronic Design Magazine, Vol. 48, Number 3, February 7, 2000. 3 MEDICI Two-Dimensional Device Simulation Program, Avant! Corporation, Fremont, CA. 4 Advanced Design System (ADS) Program, Agilent Corporation, Palo Alto, CA. 5 J.A. Appels and H.M.J. Vaes, "High Voltage Thin Layer Devices (RESURF Devices)", IEEE International Electron Devices Meetings, Abstract 10.1, pp. 238-241, 1979. 6 P. Perugupall, M. Trivedi, K. Shenai, and S.K. Leong, "Modeling and Characterization of an 80 V Silicon LDMOSFET for Emerging RFIC Applications", IEEE Trans Electron Devices, Vol. ED-45, pp. 14681478,1998. 7 A. Wood, "LDMOS Transistor Powers PCS Base-Station Amplifiers", Microwaves and RF, pp. 69-80, March 1998. 8 G. Ma, W. Burger, and C. Dragon, "High efficiency LDMOS Power FET for Low Voltage Wireless Communications", IEEE International Electron Devices Meeting, Abstract 4.3.1, pp. 91-94, 1996. 9 O. Lembeye and J-C Nanan, "Effect of Temperature on High Power RF LDMOS Transistors, Applied Microwave and Wireless, pp. 36-43, August 2003. 10 See typical datasheets for an LD-MOSFET provided in the Appendix. 11 S. Xu, A. Shibib, Z. Xie, H. Sofar, J. Lot, D. Farrel, M. Matrapasqua, "High Performance Rf LDMOSFET Technology for 2.1 GHz Power Amplifier Applications", IEEE International Symposium on Power Semiconductor Devices and ICs, pp. 190-195, 2003. 12 J. Jang, O. Tornblad, T. Arnborg, Q. Chen, K. Banerjee, Z. Yu, and R.W. Dutton, "RF LDMOS Characterization and its Compact Modeling", IEEE MTT Digest, pp. 967-970, 2001. 13 A. Shibib, S. Xu, Z. Xie, P. Gammel, M. Mastrapasqua, and I. Kiziyalli, "Control of Hot Carrier Degradation in LDMOS Devices by a Dummy Gate Field Plate: Experimental Demonstration", IEEE International Symposium on Power Semiconductor Devices and ICs, pp. 233-235, 2004.

Chapter 5

Vertical-Diffused MOSFETs

Vertical power MOSFETs, fabricated using the double-diffusion technology, have been commercially available since the mid-1970s. The double-diffusion process allowed control of the channel length to the micron dimension without the need for expensive state-of-the-art lithography tools. The high input impedance of the MOS-gate structure simplified the drive circuit requirements when compared with bipolar transistors being used at that time. In addition, their superior switching speed opened new applications operating at 10-50 kHz. During the last three decades, the design and fabrication technology for power MOSFETs has been improved to enable extension of their applications to switching frequencies up to 1 MHz. The physics and design methodology for these devices has been treated in detail in several textbooks1,2. The vertical double-diffused (VD) MOSFETs were also optimized for RF applications by replacing the traditional polysilicon gate with metal gate structures. Although the vertical architecture enables the design of high voltage devices with significant output power, their operating frequency was limited to below 500 MHz. With a focus on serving avionics and pulse-power applications, the VD-MOSFETs available in the market do not exhibit adequate linearity for cellular power amplifiers. In this chapter, the basic operating principles of the VDMOSFET structure will be discussed. The physics of operation will be elucidated by using the results of two-dimensional numerical simulations3 of a typical cell design. Although the exact values for the doping profiles, the gate oxide thickness, and channel length may vary from manufacturer to manufacturer, the basic structure for the VDMOSFET used in the industry is similar to that described in this chapter. The results and analysis given in this chapter for the traditional VD-

103

104


MOSFET structure provide a background for discussion of improved structures described in later chapters. 5.1 Device Cell Structure

Fig. 5.1 Vertical-Diffused (LD) MOSFET Structure.

A cross-section of the basic cell structure for the Vertical-Diffused (VD) MOSFET is illustrated in Fig. 5.1. The device is fabricated by starting with an N-type epitaxial layer grown on a heavily doped N+ substrate. The channel is formed by the difference in lateral extension of the P-base and N+ source regions produced by their diffusion cycles. Both regions are self-aligned to the left-hand-side and right-hand-side of the gate region during ion-implantation to introduce the respective dopants. The doping concentration of donors in the N-epitaxial drift region and its thickness must be chosen to attain the desired breakdown voltage. In practical devices, the breakdown voltage of the VD-MOSFET is invariably decided by the edge termination that surrounds the device cell, shown in Fig. 5.1, replicated over the die active area. The most commonly used edge termination for VD-MOSFETs is based up on floating field rings and field plates1. The enhanced electric field at the edges limits the breakdown voltage. Consequently, the doping and thickness of the N-drift region must be chosen to achieve a breakdown voltage that is 20 percent larger than that for the parallel-plane junction.


105

In the case of the devices of interest for cellular base station power amplifiers with a rated breakdown voltage of 75 volts, the doping concentration and thickness are 5 x 1015 cm"3 and 6 microns, respectively. This takes into account a highly doped, deep P+ region incorporated in the structure to prevent activation of the parasitic N-P-N bipolar transistor that is inherent in the VD-MOSFET structure. Unlike the LD-MOSFET structure discussed in the previous chapter, the drain contact for the VD-MOSFET structure is located at the bottom of the N+ substrate. Since the high current carrying source and drain electrodes are located on opposite sides of the wafer, it is possible to create a large source contact by overlapping the source electrode over the gate electrode as shown in Fig. 5.1. This eliminates the need for making fine metal patterns on the top surface. Further, the vertical current transport through the source metal reduces the current density preventing electro-migration problems. This design strategy requires making the contact to the gate electrode in the orthogonal direction to the cross-section shown in Fig. 5.1. For a high frequency transistor, it is imperative that the gate resistance be made as small as possible to maintain uniform current distribution within the chip. This can be achieved by using polycide stacks that have a sheet resistance of about one-tenth that achievable using pure polysilicon as the gate electrode. Drain current flow in the VD-MOSFET structure is induced by the application of a positive bias to the gate electrode. This produces an inversion layer at the surface of the P-base region under the gate electrode. This inversion layer channel provides a path for transport of electrons from the source to the drain when a positive drain voltage is applied. The channel length in the VD-MOSFET structure must be sufficiently long to avoid reach-through of the depletion layer in the Pbase region. Consequently, the VD-MOSFET structure operates with channel pinch-off as the drain voltage increases (as described in Chapter 3) resulting in a square law relationship between the drain current and the gate voltage. In the VD-MOSFET structure, the drain current flows from the drain electrode through the N+ substrate, the N-drift region, the JFET region located between the P-base regions, and then through the inversion layer channel to the top surface source electrode. The onresistance of the structure is determined by the resistance of all these components in the current path (neglecting the accumulation resistance): R

on,sp ~

R

SUBS,SP + RD,sp + RJFEJ,sp + RCH,sP

t5'1]

106


In this equation, the specific channel resistance RcH,spis given by: D K CH,SP ~

T W p

2 u

HA" C (V

r-

-V

,1

)

where Lch is the channel length, WP is the cell pitch, |Oinv is the channel inversion layer mobility, Cox is the specific oxide capacitance of the gate stack, VG is the applied gate voltage, and VT is the device threshold voltage. The factor of 2 in the denominator accounts for the presence of two channels that share the current flow from the JFET region. The specific resistance of the JFET region is given by:

_pJFErWP{xP+W0) RJF

^-(LG-2XP-2W0)

l53]

where pJFET is the resistivity of the JFET region, xP is the depth of the Pregions, and Wo is the zero-bias depletion width. It is common practice to increase the doping concentration in the JFET region above that for the N-drift region in order to reduce the JFET region resistance. The specific drift region resistance RDsp is given by: [5.4]

where p D is the resistivity of the drift region. This equation takes into account current spreading from the JFET region with a width of 2a through a drift region thickness of t. The specific substrate resistance RSUBS.SP is given by: ^SUBS.sp

where

PSUBS and tSuBs are

~ P'SUBS1SUBS

[5.5]

the resistivity and thickness of the N* substrate. For power switching devices, it is customary to optimize the length (LG) of the gate to obtain the lowest possible specific onresistance1. Smaller gate lengths result in high JFET resistance contributions while large gate lengths result in high channel contributions. For a typical VD-MOSFET structure designed to support 75-80 V, this optimization results in a gate length of about 6 microns with a cell pitch (WP) of 12 microns because of the space taken by the deep P+ diffusion and relatively deep junctions required to prevent reach-through breakdown.


107

5.2 VD-MOSFET Simulation Structure

Fig. 5.2 Structure used for VD-MOSFET Simulations.

Two-dimensional numerical simulations of the VD-MODSFET structure were performed using the structure illustrated in Fig. 5.2 with a gate length (LG) of 6 micron. The thickness and doping concentration for the N-type epitaxial layer were chosen as 6 microns and 5 x 1015 cm"3, respectively, to achieve a device cell breakdown voltage of 90 volts. This provides margin for breakdown voltage as limited by the edge termination. After including the space for the deep P+ diffusion, with a depth of 3 microns, the cell pitch was 12 microns. Note that this device cell contains two channels formed on either side of a common JFET region. The simulations are described for structures with two gate oxide thicknesses, as well as a structure with a terraced gate region which has been proposed to reduce the reverse transfer capacitance. In addition, since the VD-MOSFET structure has been traditionally mounted to packages with the drain soldered to the package paddle, non-isothermal simulations were performed to illustrate the issues associated with conduction of heat from the top surface to the bottom of the wafer through the N+ substrate. In these simulations, a non-isothermal condition was chosen with the heat sink located at the bottom of the device, namely, at the drain contact.

108


Fig. 5.3 Three Dimensional Doping Profile for VD-MOSFET Structure.

Fig. 5.4 Channel Doping Profile for VD-MOSFET Structure.

A three-dimensional view of the doping profile used for the simulations of the VD-MOSFET structure is shown in Fig. 5.3 for the


109

right-half portion of the device cell. The source N+ region is located in the middle at the top of the structure. The P-base and deep P+ regions are interposed between the N* source region and the N-drift region. The deep P+ region extends on the right hand side to a depth of about 3 microns. The enhanced doping of the JFET region can be observed on the left hand side of Fig. 5.3. The doping profile for the channel in the simulation structure is shown in Fig. 5.4 from just beyond the left hand edge of the gate into the center of the JFET region at the silicon surface under the gate oxide. The channel length (L C H) is 1.2 microns and the peak doping concentration in the P-base region is 3 x 1017 cm'3. These values are typical for devices reported in the literature6. The doping concentration of the JFET region at the surface is 1.5 x 1016 cm"3. 5.3 VD-MOSFET Blocking Characteristics

Fig. 5.5 Potential Contours at Vds=70V for the VD-MOSFET Structure.

In all the simulations, the source electrode was held at ground potential. The ability of the LD-MOSFET to support the required blocking voltage of above 90 V was verified by performing simulations with the gate held

110


at ground potential. The breakdown voltage for the structure was found to be slightly above 90 V for the case of a drift region doping of 5 x 1015 cm"3. The potential contours in the VD-MOSFET structure are shown in Fig. 5.5 for a drain bias of 70 volts. It can be seen that the drain voltage is supported vertically across the N-drift region below the P+ region. The non-uniform potential lines are indicative of a triangular electric field distribution in the drift region under the P+ region. This can be observed in the three-dimensional view of the electric field distribution shown in Fig. 5.6 at a drain bias of 70 volts. Note that there is some enhancement of the electric field at the center of the JFET region under the gate.

Fig. 5.6 Electric Field Distribution in the VD-MOSFET Structure.

5.4 VD-MOSFET On-State Characteristics When a positive bias above the threshold voltage is applied to the gate of the VD-MOSFET structure, an inversion layer channel is formed at the surface of the P-base region. This provides a path for the transport of electrons between the drain and source terminals. In the case of the VDMOSFET structure, the source current is constricted by the JFET region


111

as shown in Fig.5.7. For the structure with a gate oxide thickness of 500 A, the on-resistance was found to be 21 Ohms/mm of device width at a gate bias of 10 volts.

Fig. 5.7 On-State Current Flow in the VD-MOSFET Structure.

5.5 VD-MOSFET Output and Transfer Characteristics The output characteristics for the VD-MOSFET structure (VDMOS1) with 500 Angstrom gate oxide are shown in Fig. 5.8 for gate bias voltages ranging from 3.5 to 10 V (in 0.5 V increments). The non-linear increase in drain current with increasing gate voltage is obvious from the increasing separation between the various curves. This non-linear behavior can also be observed in the transfer and transconductance curves for the VD-MOSFET structure. The transfer curve, shown in Fig. 5.9, shows the square law behavior more clearly. This is also evident from the transconductance, shown in Fig. 5.10, increasing approximately linearly with gate voltage. This behavior is consistent with the channel pinch-off model described in Chapter 3 for the conventional MOSFET structure. The relatively long channel length of 1.2 microns for the VD-MOSFET structure, required to prevent reachthrough breakdown, results in sufficient voltage drop along the channel during current flow to produce channel pinch-off.

112


Fig. 5.8 Output Characteristics of the VD-MOSFET Structure.

Fig. 5.9 Transfer Characteristics of the VD-MOSFET Structure.

As shown in these figures, the threshold voltage decreases with increase in temperature. In addition, the compression current reduces with increasing temperature. This behavior is similar to that of the LD-


113

MOSFETs described in Chapter 4. The reduction in the transconductance and compression current are detrimental to RF performance.

Fig. 5.10 Transconductance of the VD-MOSFET Structure.

5.6 VD-MOSFET Capacitances

Fig. 5.11 Capacitances in the VD-MOSFET Structure.

114


The input, output and reverse transfer capacitances for the VD-MOSFET structure were extracted by performing two-dimensional numerical simulations of the cell structure with a 1 MHz ac-signal applied to appropriate electrodes. The input capacitance (Cgs) had a weak dependence on the drain voltage. For the VD-MOSFET with 500 angstrom gate oxide, the input capacitance was found to be 3.75 pF/mm of device width. The output and reverse transfer capacitances are highly non-linear due to their dependence on the depletion width which is a strong function of the drain voltage. In the VD-MOSFET structure, the output capacitance is primarily determined by the N-drift/P+ region junction. These capacitances are shown in Fig. 5.11. At a drain bias of 30V, the output capacitance (Cds) has a value of 0.42 pF/mm and the reverse transfer capacitance (Cg(t) has a value of 0.023 pF/mm. These values are larger than for the LD-MOSFET structure. However, the VDMOSFET contains two channels per device cell as compared with the single channel in the LD-MOSFET structure. This results in a larger transconductance per mm of cell width for the VD-MOSFET structure.

5.7 VD-MOSFET RF Performance As described in Chapter 4 in the case of the LD-MOSFET structure, the RF response of the VD-MOSFET when biased in the class A mode was analyzed by using a piece-wise temporal simulation using the load-line shown in Fig. 5.12 with a quiescent drain voltage of 30 volts. The load-line was chosen to obtain the largest output power by maximizing the swing in the drain current and drain voltage. An RF input gate signal of 0.5 V in magnitude was superimposed up on the 7 V DC gate bias point. From the gate and drain currents and voltages obtained using these simulations, the current gain, power gain, as well as the output power, could be extracted using the maximum and minimum values of the sinusoids after the transient response was completed to obtain the rms values for the RF signals. The frequency response of the transistor was obtained by repeating the temporal simulations at a variety of frequencies ranging from 0.1 to 16 GHz. The reduction in the current gain and power gain is shown in Fig. 5.13. This behavior is similar to that predicted by the analytical solutions in Chapter 3 (see Fig. 3.9). The cut-off frequency and maximum operating frequency are 1.3 and 3.1 GHz, respectively. The power gain at 1 GHz is 13.5 dB.


115

Fig. 5.12 RF Load-line for the VD-MOSFET Structure.

Fig. 5.13 Current and Power Gain for the VD-MOSFET Structure.

The change in the output power for the VD-MOSFET structure with increasing frequency was obtained by performing the temporal simulations at a variety of frequencies ranging from 0.1 to 16 GHz with

116


an input gate voltage of 0.5 volts. The reduction in the output power with increasing frequency can be seen in Fig. 5.14. At lower frequencies, the output power obtained from the VD-MOSFET device cell is similar to that for the LD-MOSFET structure with the same gate oxide thickness. However, the drop-off in power with frequency is more gradual (as predicted by Eq [3.29]) due to the much lower load resistance possible for the VD-MOSFET structure due to its wider safe operating area. Based upon the available drain current and voltage excursions within the domain of the output characteristic shown in Fig. 5.12, the maximum RF output power that can be obtained from the VD-MOSFET device cell structure is 1.06 W/mm of cell width. This is much greater than that obtained from the corresponding LD-MOSFET structure. In addition, the VD-MOSFET structure is more rugged from the avalanche energy standpoint. These results are consistent with those reported in the literature4'5. These features have made the VD-MOSFET structure attractive for pulse power and avionics applications at lower frequencies. Their application to higher frequencies has been curtailed by package parasitics arising from source wire bonds.

Fig. 5.14 RF Output Power for the VD-MOSFET Structure.


117

5.8 VD-MOSFET Thermal Effects As discussed in Chapter 3, an increase in the device temperature leads to degradation in RF performance due to the reduction in the channel mobility. Isothermal simulations at elevated temperatures allow an assessment of the change in the transfer curve and transconductance as already shown in Fig. 5.9 and Fig. 5.10, respectively. The change in the output characteristics with temperature is shown in Fig. 5.15. The saturated drain current increases with temperature due to a reduction in the threshold voltage. This effect becomes weaker at larger gate voltages due to the impact of the mobility reduction.

Fig. 5.15 Effect of Temperature on the Output Characteristics of the VD-MOSFET Structure. (Solid Line: 300K; Dashed Line: 400K; Dotted: Line 500K)

For vertical power MOSFET, it is commonplace to solder the bottom of the wafer (the drain) to the package because the top surface has two contacts. If the drain of the power MOSFET is connected to the heat sink, its voltage would vary due to the DC bias and super-imposed RF signal. This problem has been overcome by using a Beryllium oxide (BeO) layer within the vertical device package to isolate the drain from the heat sink. Unfortunately, the BeO layer makes the thermal resistance

118


of the package much larger than for the LD-MOSFETs. Moreover, the BeO is a toxic material which is being phased out by the industry. Since the high electric field in the VD-MOSFET structure is located within the drift-region, most of the power dissipation occurs within about 5 microns at the top of the silicon chip. The heat must then flow through the N* substrate to the bottom source contact and then into the flange. This results in a thermal gradient across the wafer. In order to understand the impact of this gradient, non-isothermal simulations were performed for the VD-MOSFET structure with the bottom of the wafer held at a constant temperature of 300° K. The results of non-isothermal simulations of the output characteristics are shown in Fig. 5.16 for the case of 200 micron substrate thickness. For purposes of comparison, the isothermal characteristics are also shown in this figure. It can be seen that the characteristics undergo distortion as a consequence of the temperature rise. At higher gate biases with increased drain current flow, thermal runaway commences at reduced drain voltages due to the larger power dissipation.

Fig. 5.16 Non-Isothermal Output Characteristics of the VD-MOSFET Structure. (Solid Line: Isothermal; Dashed Line: Non-Isothermal)

The temperature distribution can be observed in the temperature contours shown in Fig. 5.17 for the case of Vgs=6V and Vds=30V. The


119

highest temperature is observed at the center of the device where the highest current density occurs due to the JFET region. The increase in the channel temperature under these bias conditions is shown in Fig. 5.18. It can be seen that the channel temperature has risen to 535 °K (or 262 °C). This is too high from a reliability stand point.

Fig. 5.17 Temperature Contours for the VD-MOSFET Structure at V j ^ O V and Vgs=6V.

Fig. 5.18 Temperature Profile in the VD-MOSFET Structure.

120


5.9 VD-MOSFET with Terraced Gate Oxide

Fig. 5.19 The Split Gate VD-MOSFET Structure.

Fig. 5.20 The Terraced Gate VD-MOSFET Structure.

Attempts to improve the frequency response of the VDMOSFET structure have included reduction of the reverse transfer capacitance by using a split gate structure6 shown in Fig. 5.19. This approach has been found to degrade device breakdown voltage and reliability due to a high field created at the edge of the gate (location A in


121

Fig. 5.19). To over come the breakdown problem while reducing the reverse transfer capacitance to a lesser extent, the terraced gate structure shown in Fig. 5.20 has been proposed7. Two dimensional numerical simulations were performed for the VD-MOSFET structure discussed earlier with the addition of a thicker oxide below the electrode where it overlaps the drift region. The width of the thicker oxide portion was 1 micron to avoid its extension over the edge of the P-base region. It has been reported that the on-resistance becomes very large when the thicker oxide portion gets too close to the edge of the channel.

Fig. 5.21 Potential Distribution in the VD-MOSFET Terraced Gate Structure at V(ls=70V and Vgs=0V.

The potential contours are shown in Fig. 5.21 for the terraced gate VD-MOSFET structure at a drain bias of 70 volts. Some electric field enhancement occurs despite the overlap of the gate over the thicker oxide portion. This enhancement can be seen clearly in Fig. 5.22, where the electric field is shown under the same bias conditions. The electric field is still less than that that at the P+/N-drift junction. Unfortunately, the reduction in the reverse transfer capacitance (Cgd) was found to be only 10 percent. This is due to the small width of the thick oxide portion

122


as limited by the device geometry. Thus, the terraced gate oxide is not found to provide sufficient benefits to merit the complexity of the added processing to achieve the structure.

Fig. 5.22 Electric Field Distribution in the VD-MOSFET Terraced Gate Structure at Vds=70V and Vgs=0V.

5.10 VD-MOSFET with Thinner Gate Oxide As discussed in Chapter 3, the performance of power MOSFETs can be improved by reducing the gate oxide thickness. In order to evaluate the behavior of the VD-MOSFET structure, two-dimensional numerical simulations of the device shown in Fig. 5.1 were repeated using a gate oxide thickness of 250 angstroms. All other structural parameters were left unaltered. As expected, reduction of the gate oxide thickness results in an increase in the transconductance and a decrease in the threshold voltage. The impact of this on the output and transfer characteristics is shown in Fig. 5.23 and 5.24, respectively. However, the transconductance is still a strong function of the gate bias, as shown in Fig. 5.25, because of the "square-law" behavior.


Fig. 5.23 Output Characteristics for VD-MOSFET Structure with Thinner Gate Oxide.

Fig. 5.24 Transfer Characteristics for VD-MOSFET Structure with Thinner Gate Oxide.

123

124


Fig. 5.25 Transconductance of the VD-MOSFET Structure with Thinner Gate Oxide.

For the VD-MOSFET structure with reduced gate oxide thickness, the values of input, output and reverse transfer capacitances were found to be 6.05, 0.40, and 0.023 pF per mm of cell width, respectively, at a drain bias of 30 volts. As expected, the reduced gate oxide thickness results in an increase in the input capacitance.

Fig. 5.26 Current and Power Gain for the VD-MOSFET Structure with Thinner gate Oxide.


125

The reduced gate oxide thickness improves the frequency response of the VD-MOSFET structure. The current and power gain are shown in Fig. 5.26 as a function of frequency. At 1 GHz, the power gain with the thinner oxide is 16 dB compared with 13 dB for the 500 angstrom gate oxide case. The maximum operating frequency is also improved slightly from 3 GHz to 4 GHz. There is no change in the maximum output power that can be delivered from the structure. 5.11 VD-MOSFET Conclusions The VD-MOSFET structure was originally developed in the 1970s for power switching applications. Improvements in its high frequency response have been achieved by using metal and polycide gate structures5 and achieving shorter channel length by using the doublediffusion process with ion-implants self-aligned to the gate edge. These devices operate with channel pinch-off determining drain current saturation. This has limited the linearity of these devices. In addition, the use of BeO isolated packages with source wire-bonds has reduced the power gain and maximum operating frequency. This chapter has provided information regarding the underlying physics of the VD-MOSFET structure, where the channel operates in the pinch-off mode during current saturation. The results of two-dimensional numerical simulations have been provided to describe its DC and RF characteristics. These characteristics will be used as a benchmark when discussing other structures described in this book.

126


References 1

B. J. Baliga, "Power Semiconductor Devices", PWS Publishing Company, 1996. 2 D.A. Grant and J. Gowar, "Power MOSFETs: Theory and Applications", John Wiley and Sons, 1989. 3 MEDICI Two-Dimensional Device Simulation Program, Avant! Corporation, Fremont, CA. 4 M. Trivedi, P. Khandelwal, and K. Shenai, "Performance Modeling of RF Power MOSFETs", IEEE Transactions on Electron Devices, Vol. ED-46, pp. 1794-1802, 1999 5 H. Esaki and O. Ishikawa, "A 900 MHz VD-MOSFET with Silicide Gate Self-Aligned Channel", International Electron Devices Meeting, Abstract 16.6, pp. 447-450, 1984. 6 S. Xu, C. Ren, Y.C. Liang, P-D. Foo, and J.K.O. Sin, "Theoretical Analysis and Experimental Characterization of the Dummy-Gate VDMOSFET", IEEE Transactions on Electron Devices, Vol. ED-48, pp. 2168-2176,2001. 7 D. Ueda, H. Takagi, and G. Kano, "A New Vertical Double Diffused MOSFET - The Self-Aligned Terraced-Gate MOSFET", IEEE Transactions on Electron Devices, Vol. ED-31, pp. 416-420, 1984.

Chapter 6

Charge-Coupled MOSFETs

The vertical double-diffused power MOSFET structure discussed in the previous chapter operates by blocking voltage across a P/N junction where the depletion occurs primarily on the lightly doped N-type drift region. This produces a triangular shaped electric field profile in the drift region. Based up on this one-dimensional shape, it is possible to develop a relationship between the specific resistance of the drift region and the breakdown voltage1'2 that has allowed creating the Baliga's Figure of Merit for power devices. An equation for the ideal specific on-resistance for the drift region was provided in Chapter 3. This resistance was believed to be lowest attainable value for power MOSFETs with a specified breakdown voltage until the development of the twodimensional charge-coupling concept. The two-dimensional chargecoupling concept3 was first proposed for enhancing the performance of lateral power MOSFETs. Two methods to extend the two-dimensional charge-coupling concept to vertical devices were independently proposed4'5. In the first method, the two-dimensional charge-coupling is created between the Ndrift region and an electrode embedded within an oxide filled trench located adjacent to the drift region. This method is especially suitable for devices with breakdown voltages ranging from 30 to 200 volts. At lower breakdown voltages, the benefits of the two-dimensional charge-coupling are not significant because the doping concentration of the drift region becomes high even for the conventional device structure. The approach is also difficult to implement at breakdown voltages above 200 volts because of the large trench depth and thick oxide required within the trench. For devices with breakdown voltages above 200 volts, the second method has been found to be more suitable. In this method, alternate lightly doped P and N type regions are formed as columns to simultaneously promote lateral and vertical depletion of the drift region.

127

128


Since the breakdown voltage for the RF power MOSFETs discussed in this book is in the range of 75 to 80 volts, the first twodimensional charge-coupling concept is more relevant. This method can be implemented with a uniformed doped N-type drift region. However, even further improvement in performance can be obtained by using a linearly graded doping profile6 within the drift region. The linearly graded doping profile has been found to make the electric field uniform along the drift region resulting in lower specific on-resistance for this structure. In this chapter, the basic operating principles of the chargecoupled MOSFET structure will be discussed. The physics of operation will be elucidated by using the results of two-dimensional numerical simulations7 of a typical cell design. These results will be compared with the characteristics of the LD-MOSFET and VD-MOSFET structures discussed in earlier chapters. 6.1 Device Cell Structure

Fig. 6.1 Charge-Coupled Vertical (CC) MOSFET Structure.

The two-dimensional charge-coupling discussed above can be obtained by utilizing the structure illustrated in Fig. 6.1 where the trench electrode has been shorted to the gate electrode. This is convenient from a processing stand point because the gate electrode is located just above


129

the trench electrode. However, this approach greatly increases the input capacitance because of the significant contribution from the trench electrode despite the thicker oxide on the trench sidewalls. For a device designed for RF power amplification applications, it is better to use the structure illustrated in Fig. 6.2 where the trench electrode is isolated from the gate and connected to the source electrode in the orthogonal direction.

Fig. 6.2 Charge-Coupled Vertical (CC) MOSFET Structure.

As mentioned above, these device structures can be fabricated with either a uniformly doped drift region (referred to as the CCMOSFET) or a linearly graded drift region (referred to as the GDMOSFET). In either case, the device is fabricated by starting with an Ntype epitaxial layer grown on a heavily doped N+ substrate. The channel is formed by the difference in vertical extension of the P-base and N+ source regions produced by their ion-implant and diffusion cycles. A deep trench is then etched through most of the drift region followed by lining it with a thick oxide layer that partially fills the trench. Polysilicon can be deposited to fill the trench to form the trench electrode. This polysilicon is then partially etched to recess the electrode. The oxide in the trench is then removed and the gate oxide is grown on the trench sidewall. This simultaneously creates an oxide layer on the embedded polysilicon to provide isolation from the gate electrode. The polysilicon

130


gate electrode is now deposited to refill the trench. The gate electrode is patterned to open the top surface for contacting the N* source region, as well as the P-base region in the orthogonal direction. The doping concentration of donors in the N-epitaxial drift region and the width of the 'mesa' region between the deep trenches must be chosen to obtain optimum charge coupling. A good rule of thumb is that the product of the doping concentration and the mesa width must be between 1 and 2 x 1012 cm"2. Under the assumption that a uniform electric field is created along the vertical direction, the depth of the trench can be determined by dividing the desired breakdown voltage by the critical electric field for breakdown in silicon (about 2-3 x 105 V/cm). Further optimization requires two-dimensional numerical simulations. The breakdown voltage of vertical MOSFET structures is usually decided by the edge termination 8 . The most commonly used edge termination for discrete power devices is based up on floating field rings and field plates. This approach is not adequate for the vertical devices that utilize the charge-coupled concept due to the much higher doping concentration for the drift region than in the conventional vertical devices. Fortunately, it has been discovered that breakdown at the edges of the chip can be avoided by using a field plate termination with sufficiently thick field oxide 9 . The breakdown then shifts to the device cells allowing full utilization of the charge-coupling concept. Unlike the LD-MOSFET structure discussed in an earlier chapter, the drain contact for the CC-MOSFET is located at the bottom of the N + substrate. Since the high current carrying source and drain electrodes are located on opposite sides of the wafer, it is possible to create a large source contact by overlapping the source electrode over the gate electrode as shown in Fig. 6.1 and 6.2. This eliminates the need for making fine metal patterns on the top surface. Further, the vertical current transport through the source metal reduces the current density preventing electro-migration problems. This design strategy requires making the contact to the gate electrode in the orthogonal direction to the cross-section shown in Fig. 6.1 and 6.2. For a high frequency transistor, it is imperative that the gate resistance be made as small as possible to maintain uniform current distribution within the chip. This can be achieved by using a polycide stack that has a sheet resistance of about one-tenth that achievable using pure polysilicon as the gate electrode. Drain current flow in the CC-MOSFET structure is induced by the application of a positive bias to the gate electrode. This produces an


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inversion layer at the surface of the P-base region along the trench sidewalls adjacent to the gate electrode. This inversion layer channel provides a path for transport of electrons from the source to the drain when a positive drain voltage is applied. The channel length in the CCMOSFET structure must be sufficiently long to avoid reach-through of the depletion layer in the P-base region. As shown by the results of numerical simulations later in this chapter, the charge-coupling phenomenon in the CC-MOSFET structure enables support of the applied drain voltage within the N-drift region with a low electric field at the P-N junction. This results in very little depletion of the P-base region allowing reduction of the channel length. This is optimal for reducing the device resistance and for obtaining a high transconductance which is beneficial for high frequency operation. The low voltage drop across the channel, even at high drain bias voltages, is also conducive to obtaining the super-linear mode of operation because the channel remains in its linear mode of operation. In the CC-MOSFET structure, the drain current flows from the drain electrode through the N+ substrate, the N-drift region, and the inversion layer channel to the top surface source electrode. The onresistance of the structure is determined by the resistance of all these components in the current path: R

on,sp = RSUBS,sp + RD,sp + RCH ,sp

t6'1]

In this equation, the specific channel resistance RCH,SP is given by: t\.rH

'

—

T W 7

r

2MimC0X(VG-VT)

Lo.^J

where Lch is the channel length, WP is the cell pitch, |J.jnv is the channel inversion layer mobility, Cox is the specific oxide capacitance of the gate stack, VG is the applied gate voltage, and VT is the device threshold voltage. The factor of 2 in the denominator accounts for the presence of two channels that share the current flow from the drift region. The specific drift region resistance RDsp is given by: [6.3]

where po is the resistivity of the drift region, LT is the trench depth, Wm is the mesa width, and QD is the charge (product of doping and mesa

132


width) in the mesa region. This equation does not take into account the depth of the P-base region which is shallow compared with the total trench depth. The specific substrate resistance RSUBS,SP is given by: °SUBS,SP

~ PsvBshuBS

[5.5]

where PSUBS and tsuBS are the resistivity and thickness of the N+ substrate. For a typical CC-MOSFET designed to support 75-80 V, the trench depth is about 5 microns with a cell pitch (WP) of about 1.7 microns if a mesa width of 0.5 microns is chosen with a doping concentration of 4 x 1016 cm"3. The drift region contribution is only 0.5 mOhms-cm2. This low value is due to the relatively high doping concentration in the drift region, which would result in a breakdown voltage of less than 20 volts without the charge-coupling effect. 6.2 CC-MOSFET Simulation Structure Two-dimensional numerical simulations of the CC-MOSFET structure were performed using the structure illustrated in Fig. 6.2 with a trench depth (LT) of 5 microns. The trench width was chosen as 1.2 microns to allow for a thick trench oxide of 3500 angstroms with a polysilicon refill of 0.5 microns. The mesa width was chosen as 0.5 microns resulting in a full cell pitch of 1.7 microns. The simulations were performed using half-cells because they comprise the basic unit for understanding device physics and performance. The results obtained with a uniformed doped drift region will be first described followed by the GD-MOSFET case with the graded doping concentration. In the latter case, the impact of reducing the gate oxide thickness from 500 angstroms to 250 angstroms will also be described. The doping profile used for the simulations of the CC-MOSFET structure is shown in Fig. 6.3 for the entire epitaxial layer thickness. The total epitaxial layer thickness is 5.5 microns with a doping concentration of 4 x 1016 cm 3 . The N* source region has a depth of about 0.1 microns and the P-base region has a depth of about 0.3 microns. This can be seen more clearly in Fig. 6.4 where the channel doping profile is shown. This results in a channel length of only 0.2 microns. Although this may seem inadequate for supporting high drain voltages due to base reach-through breakdown, numerical simulations demonstrate that very little depletion of the P-base region occurs due to the charge coupling effect in the underlying drift region. Note that the peak doping concentration of the P-


133

base region is 1.5 x 1017 cm"3 as controlled by the P-base implant whose peak is located below the depth of the N* source region. This allows more precise control of the threshold voltage.

Fig. 6.3 Doping Profile for CC-MOSFET Structure.

Fig. 6.4 Channel Doping Profile for CC-MOSFET Structure.

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6.3 CC-MOSFET Blocking Characteristics

Fig. 6.5 Potential Contours at Vds=60V for the CC-MOSFET Structure.

In all the simulations, the source electrode was held at ground potential. The ability of the CC-MOSFET to support the required blocking voltage was verified by performing simulations with the gate held at ground potential. The breakdown voltage for the structure was found to be 65 V for the case of a drift region doping of 4 x 1016 cm'3. The potential contours in the CC-MOSFET structure are shown in Fig. 6.5 for a drain bias of 60 volts. It can be seen that the drain voltage is supported vertically across the N-drift region with very little depletion of the P-base region. This allows very narrow channel length in the CC-MOSFET structure. The non-uniform potential lines are indicative of a high electric field in the mesa region both at the top and bottom of the trench. Note that the entire drain voltage is supported across the oxide at the bottom of the trench. For this reason, the trench oxide thickness was chosen as 3500 angstroms so the electric field in the oxide is well below its breakdown strength. A three-dimensional view of the electric field distribution in the mesa region is shown in Fig. 6.6 at a drain bias of 60 volts. Note that


135

there is significant enhancement of the electric field at the bottom of the trench.

Fig. 6.6 Electric Field Distribution in the CC-MOSFET Structure.

Fig. 6.7 Electric Field Distribution in the CC-MOSFET Structure.

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When the drain bias is applied to the CC-MOSFET structure, the voltage is initially supported across the P-base/N-drift region junction. Once the drain bias increases above about 5 volts, the mesa region gets depleted at the upper portion of the mesa leading to the on-set of the charge-coupling phenomenon. Further increase in the drain voltage is then supported by extension of the depletion region within the mesa region. This can be observed in Fig. 6.7 where the electric field is shown at the center of the mesa for various drain bias voltages. As the drain bias increases, the electric field increases at the bottom of the trench. This produces a non-uniform electric field that is not optimal for achieving high breakdown voltages. The uniformity of the electric field distribution can be significantly improved by using a graded doping profile as will be discussed later in this chapter. 6.4 CC-MOSFET On-State Characteristics

Fig. 6.8 On-State Current Flow in the CC-MOSFET Structure. When a positive bias above the threshold voltage is applied to the gate of the CC-MOSFET structure, an inversion layer channel is formed at the


137

surface of the P-base region along the trench sidewall. This provides a path for the transport of electrons between the drain and source terminals. The device current flow pattern is shown in Fig.6.8. It can be seen that current rapidly spreads from the channel and becomes uniformly distributed within the mesa region. This allows calculation of the drift region resistance using Eq. [6.3] without taking spreading resistance into account. For the structure with a gate oxide thickness of 500 A, the total on-resistance was found to be 32 Ohms/mm of device width at a gate bias of 10 volts based upon two-dimensional numerical simulations. The specific on-resistance for the CC-MOSFET structure is 0.27 mOhm-cm2, which is very close to the ideal specific on-resistance or the drift region in a 70 volt device. 6.5 CC-MOSFET Output and Transfer Characteristics

Fig. 6.9 Output Characteristics of the CC-MOSFET Structure.

The output characteristics for the CC-MOSFET structure are shown in Fig. 6.9 for gate bias voltages ranging from 1.5 to 9.5 V (in 0.5 V increments). Drain current reaches its saturation value at approximately the same drain voltage independent of the gate bias. This is a signature of the super-linear mode of operation as discussed in chapter 3. In the current saturation regime of operation, the curves are equally spaced,

13 8


once again indicating super-linear mode of operation. Unfortunately, the output resistance degrades with increasing drain bias. The phenomenon becomes worse with increasing gate bias. The reduction of the output resistance with drain bias is associated with the enhanced current flow by the on-set of impact ionization. As shown in Fig. 6.7, the electric field distribution in the CC-MOSFET has a peak near the bottom of the trench and there is a rapid increase in electric field with drain bias. This results in a poor output resistance for the CC-MOSFET structure.

Fig. 6.10 Transfer Characteristics of the CC-MOSFET Structure. The transfer characteristics are shown in Fig. 6.10 for the CCMOSFET structure at a drain bias of 30 volts. The characteristics are relatively more linear than for the LD-MOSFET and VD-MOSFET structures discussed in earlier chapters. However, the linearity is degraded by the worsening output resistance at larger gate biases. This is also evident from the transconductance characteristics, shown in Fig. 6.11, for the CC-MOSFET structure at 300 and 400° K. The transconductance increases rapidly once the gate bias exceeds the threshold voltage and is then relatively constant, especially at 400° K. The improved linearity at the higher operating temperature is due to suppression of impact ionization with increasing temperature. The transconductance for the CC-MOSFET at 300° K is about 50 mS/mm of gate width. This is much larger (2x) than that for the LD-MOSFET and VD-MOSFET structures because of the shorter channel length. As shown


139

in the figures, the compression current reduces with increasing temperature. This behavior is similar to that of the LD-MOSFET and VD-MOSFET structures described in earlier chapters. The reduction in the transconductance and compression current are detrimental to RF performance.

Fig. 6.11 Transconductance of the CC-MOSFET Structure.

6.6 CC-MOSFET Capacitances

Fig. 6.12 Capacitances in the CC-MOSFET Structure.

140


The input, output and reverse transfer capacitances for the CC-MOSFET structure were extracted by performing two-dimensional numerical simulations of the cell structure with a 1 MHz ac-signal applied to appropriate electrodes. The input capacitance (Cgs) had a weak dependence on the drain voltage. For the CC-MOSFET with 500 angstrom gate oxide, the input capacitance was found to be 0.16 pF/mm of device cell width. The output and reverse transfer capacitances are highly non-linear as shown in Fig. 6.12. This is due to the depletion of the mesa region with increasing drain bias. At low drain bias voltages, the output capacitance (Cds) is primarily determined by the MOScapacitance associated with the source connected electrode in the trench. Once the mesa becomes depleted, the output capacitance reduces abruptly as shown in Fig. 6.12. The source connected electrode in the trench also acts as a shield between the gate and the drain. This greatly reduces the reverse transfer capacitance (Cgd). At a drain bias of 30V, the output capacitance (Cds) has a value of 0.075 pF/mm and the reverse transfer capacitance (Cgd) has a value of 3 x 10"5 pF/mm. These values are much smaller than for the LD-MOSFET and VD-MOSFET structures.

6.7 CC-MOSFET RF Performance As described in Chapter 4 in the case of the LD-MOSFET structure, the RF response of the CC-MOSFET when biased in the class A mode was analyzed by using a piece-wise temporal simulation using the load-line shown in Fig. 6.13 with a quiescent drain voltage of 30 volts. The dashed load-line was chosen to obtain the best linearity. (Although much greater output power can be obtained using the dotted load-line shown in the figure, this produces much greater distortion under large signal operation.) An RF input gate signal of 0.5 V in magnitude was superimposed up on the 2.5 V DC gate bias point. From the gate and drain currents and voltages obtained using these simulations, the current gain, power gain, as well as the output power, could be extracted using the maximum and minimum values of the sinusoids after the transient response was completed to obtain the rms values for the RF signals. The frequency response of the transistor was obtained by repeating the temporal simulations at a variety of frequencies ranging from 0.1 to 16 GHz. The reduction in the current gain and power gain is shown in Fig. 6.14. This behavior is similar to that predicted by the


141

analytical solutions in Chapter 3 (see Fig. 3.9). The cut-off frequency and maximum operating frequency are 4.2 and 9.5 GHz, respectively. The power gain at 1 GHz is 25 dB.

Fig. 6.13 RF Load-line for the CC-MOSFET Structure.

Fig. 6.14 RF Current and Power Gain for the CC-MOSFET Structure.

142


The change in the output power for the CC-MOSFET structure with increasing frequency was obtained by performing the temporal simulations at a variety of frequencies ranging from 0.1 to 16 GHz with an input gate voltage of 0.5 volts. The reduction in the output power with increasing frequency can be seen in Fig. 6.15. At lower frequencies, the output power obtained from the CC-MOSFET device cell is similar to that for the LD-MOSFET structure with the same gate oxide thickness. However, the output power is maintained at up to 1 GHz. The good output power and RF gain for the CC-MOSFET structure indicate that this structure could be used in RF power amplifiers for frequencies that cover the entire cellular spectrum from 0.8 to 2.2 GHz. These features of the CC-MOSFET structure are also attractive for pulse power and avionics applications. Based upon the available drain current and voltage excursions within the domain of the output characteristic shown in Fig. 6.13, the maximum RF output power that can be obtained from the CC-MOSFET device cell structure is about 0.435 W/mm of cell width for the case of the dashed load-line. Nearly twice (0.69 W/mm) this output power can be obtained with the dotted load-line. These values are greater than those obtained from the corresponding LD-MOSFET structure. However, the output power will be constrained by thermal considerations.

Fig. 6.15 RF Output Power for the CC-MOSFET Structure.


143

6.8 CC-MOSFET Thermal Effects As discussed in Chapter 3, an increase in the device temperature leads to degradation in RF performance due to the reduction in the channel mobility. Isothermal simulations at elevated temperatures allow an assessment of the change in the transfer curve and transconductance as already shown in Fig. 6.10 and Fig. 6.11, respectively. The change in the output characteristics with temperature is shown in Fig. 6.16. The saturated drain current is independent of temperature for a gate bias of 2.5 volts, indicating an optimum DC operating point from a thermal standpoint. Fortunately, this is also the optimum DC bias point for an RF stand point as discussed in the previous section. The drain current decreases with temperature for larger gate bias voltages due to a reduction in the channel mobility, and it increases with temperature at lower gate bias voltages due to a reduction in the threshold voltage. As discussed for the VD-MOSFET structure, it is important to provide a low thermal impedance for the CC-MOSFET structure. This is feasible by using a flip-chip packaging concept. This will be discussed in more detail in later chapters.

Fig. 6.16 Effect of Temperature on the Output Characteristics of the CC-MOSFET Structure. (Solid Line: 300K; Dashed Line: 400K; Dotted: Line 500K)

144


6.9 GD-MOSFET Structure

Fig. 6.17 The GD-MOSFET Structure and its Doping Profile.

In the previous section, it was shown that the CC-MOSFET structure offers a low on-resistance due to the high doping concentration in the drift region and a high transconductance due to a short channel length leading to high RF gain and output power. However, its output characteristics are degraded by the on-set of impact ionization current with increasing drain bias. This phenomenon is associated with the nonuniform electric field distribution in the drift region, particularly at the bottom of the trench. This shortcoming is overcome in the GD-MOSFET structure by implementation of a linearly graded doping profile4'6 as shown in Fig. 6.17. Two dimensional numerical simulations were performed for the GD-MOSFET structure to elucidate the operating physics and determine its electrical performance. The doping profile used for the simulations of the GD-MOSFET structure is shown in Fig. 6.18 for the entire epitaxial layer thickness. The total epitaxial layer thickness is 5.5 microns. The doping concentration of the epitaxial layer increases linearly from 2 x 1016 cm'3 at the top surface to about 2 x 1017 cm"3 at the N+ substrate interface. As in the case of the CC-MOSFET structure, the N+ source region has a depth of about 0.1 microns and the P-base region has a depth of about 0.3 microns. This can be seen more clearly in Fig. 6.19 where the channel doping profile is shown. This results in a channel length of only 0.2 microns. Although this may seem inadequate for


145

supporting high drain voltages due to base reach-through breakdown, numerical simulations demonstrate that very little depletion of the P-base region occurs due to the charge coupling effect in the underlying drift region.

Fig. 6.18 Doping Profile for GD-MOSFET Structure.

Fig. 6.19 Channel Doping Profile for GD-MOSFET Structure.

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6.10 GD-MOSFET Blocking Characteristics

Fig. 6.20 Potential Distribution in the GD-MOSFET Structure.

The potential contours are shown in Fig. 6.20 for the GDMOSFET structure at a drain bias of 80 volts. Unlike for the CCMOSFET structure with uniform drift region doping concentration, the potential lines are very uniformly spaced within the drift (mesa) region. Due to the improved potential distribution, the GD-MOSFET structure is able to support over 90 volts for the same 5 micron trench depth. In addition, it is noteworthy that the potential contours do not extend below the bottom of the trench. Consequently, in the GD-MOSFET structure, no electric field enhancement occurs at the trench corner. This is a unique feature of the technology when compared with other trench based power device structures. The absence of electric field enhancement at the trench corners obviates the need for rounding the bottom of the trench. As in the case of the CC-MOSFET structure, the drain voltage is supported within the drift region with very little voltage developed across the P-base region. This allows making the channel length very short without the usual reach-through breakdown problem. Note that entire drain voltage is supported across the oxide at the bottom of the trench.


147

For this reason, the trench oxide thickness is chosen as 3500 angstroms so the electric field in the oxide is well below its breakdown strength.

Fig. 6.21 Electric Field Distribution in the GD-MOSFET Structure.

A three-dimensional view of the electric field distribution in the mesa region is shown in Fig. 6.21 at a drain bias of 80 volts. Note that the electric field is fairly uniform within the mesa region, especially at the center of the mesa. Although some electric field enhancement is observed towards the bottom of the trench at the oxide interface, it is located away from the trench corner. This is favorable from the reliability standpoint. The distribution of the electric field with increasing drain bias in the GD-MOSFET structure is quite distinct from that within the VDMOSFET and CC-MOSFET structures. This is illustrated in Fig. 6.22 where the electric field is shown at the center of the mesa for various drain bias voltages ranging from 5 to 80 volts. The electric field initially developed across the P-base/N-drift junction and is triangular in shape like that for a one dimensional junction. However, once the upper portion of the mesa gets depleted at about 20 volts, the electric field begins to take a rectangular form. At above this voltage, the electric field at the junction stops increasing and the further increase in the drain voltage is supported by extension of the depletion region in the mesa. Very little

148


depletion of the P-base region is observed with increasing drain bias. This is favorable in terms of not only reducing impact ionization but also suppressing reach-through breakdown in spite of the narrow P-base region.

Fig. 6.22 Electric Field Distribution in the GD-MOSFET Structure.

6.11 GD-MOSFET On-State Characteristics When a positive bias above the threshold voltage is applied to the gate of the GD-MOSFET structure, an inversion layer channel is formed at the surface of the P-base region along the trench sidewall. This provides a path for the transport of electrons between the drain and source terminals. The device current flow pattern is identical to that already shown in Fig.6.8 for the CC-MOSFET structure. The current rapidly spreads from the channel and becomes uniformly distributed within the mesa region. The drift region resistance for the GD-MOSFET is even smaller than that predicted by using Eq. [6.3] because of the linear graded doping profile that extends the doping in the drift region to 2 x 1017 cm'3. For the structure with a gate oxide thickness of 500 A, the total on-resistance was found to be only 17.5 Ohms/mm of device width at a gate bias of 10 volts based upon two-dimensional numerical simulations.


149

The specific on-resistance for this GD-MOSFET structure was found to be only 0.15 mOhm-cm2 leading to a very low voltage drop even at high on-state current densities. Remarkably, this value is much less than the ideal specific on-resistance (0.46 mOhm-cm2) of the drift region for a breakdown voltage of 90 volts. This is an illustration of the benefits of the charge coupling concept. 6.12 GD-MOSFET Output and Transfer Characteristics

Fig. 6.23 Output Characteristics of the GD-MOSFET Structure.

The output characteristics for the GD-MOSFET structure are shown in Fig. 6.23 for gate bias voltages ranging from 1.5 to 9.5 V (in 0.5 V increments). Drain current reaches its saturation value at approximately the same drain voltage of about 8 volts independent of the gate bias. This is a signature of the super-linear mode of operation as discussed in chapter 3. In the current saturation regime of operation, the curves are equally spaced, once again indicating super-linear mode of operation. Unlike the CC-MOSFET structure, the on-set of impact ionization does not occur for the GD-MOSFET structure until the drain bias exceeds 60 volts. This is due to the uniform electric field distribution within the drift region for the GD-MOSFET structure as shown in Fig. 6.22, which leads to reduced electric fields even at high drain bias voltages. The

150


suppression of impact ionization results in good output resistance for the GD-MOSFET structure.

Fig. 6.24 Transfer Characteristics of the GD-MOSFET Structure.

The transfer characteristics are shown in Fig. 6.24 for the GDMOSFET structure at a drain bias of 30 volts. The characteristics are extremely linear when compared with the LD-MOSFET and VDMOSFET structures discussed in earlier chapters. The excellent linearity extends to very high current levels due to the large compression current. The compression current density at 300° K is 23,500 A/cm2. The transconductance characteristics are shown in Fig. 6.25 for the GD-MOSFET structure at 300 and 400° K. The transconductance increases rapidly once the gate bias exceeds the threshold voltage and is then relatively constant at both 300° and 400° K. The transconductance for the GD-MOSFET at 300° K is about 50 mS/mm of gate width - the same as for the CC-MOSFET structure. This is much larger (2x) because of the shorter channel length in these devices than that for the LDMOSFET and VD-MOSFET structures. As shown in the figures, the compression current reduces with increasing temperature. The reduction in the compression current from 300° K to 400° K is about 15 percent, which is similar to that observed for the LD-MOSFET and the VD-


151

MOSFET structures. A much larger reduction in compression current by nearly a factor of 2x was observed for the CC-MOSFET structure.

Fig. 6.25 Transconductance of the GD-MOSFET Structure.

6.13 GD-MOSFET Capacitances

Fig. 6.26 Capacitances in the GD-MOSFET Structure.

152


The input, output and reverse transfer capacitances for the GD-MOSFET structure were extracted by performing two-dimensional numerical simulations of the cell structure with a 1 MHz ac-signal applied to appropriate electrodes. The input capacitance (Cgs) had a weak dependence on the drain voltage. For the GD-MOSFET with 500 angstrom gate oxide, the input capacitance was found to be 0.18 pF/mm of device cell width. The output and reverse transfer capacitances are non-linear as shown in Fig. 6.26. This is due to the depletion of the mesa region with increasing drain bias. The output capacitance (Cds) decreases linearly with increasing drain bias. As in the case of the CC-MOSFET structure, the source connected electrode in the trench acts as a shield between the gate and the drain. This greatly reduces the reverse transfer capacitance (Cgd). At a drain bias of 30V, the output capacitance (Cds) has a value of 0.3 pF/mm and the reverse transfer capacitance (Cgd) has a value of 3 x 10"3 pF/mm. The reverse transfer capacitance is much smaller than for the LD-MOSFET and VD-MOSFET structures.

6.14 GD-MOSFET RF Performance

Fig. 6.27 RF Load-line for the GD-MOSFET Structure.


153

As described in Chapter 4 in the case of the LD-MOSFET structure, the RF response of the GD-MOSFET when biased in the class A mode was analyzed by using a piece-wise temporal simulation using the load-line shown in Fig. 6.27 with a quiescent drain voltage of 30 volts. The loadline was chosen to obtain the best linearity. (A slightly greater output power can be obtained using a load-line with smaller resistance.) An RF input gate signal of 0.5 V in magnitude was superimposed up on the 4.0 V DC gate bias point. From the gate and drain currents and voltages obtained using these simulations, the current gain, power gain, as well as the output power, could be extracted using the maximum and minimum values of the sinusoids after the transient response was completed to obtain the rms values for the RF signals. The frequency response of the transistor was obtained by repeating the temporal simulations at a variety of frequencies ranging from 0.1 to 16 GHz. The reduction in the current gain and power gain is shown in Fig. 6.28. This behavior is similar to that predicted by the analytical solutions in Chapter 3 (see Fig. 3.9). The cut-off frequency and maximum operating frequency are 4.2 and 7.0 GHz, respectively. The power gain at 1 GHz is 21 dB.

Fig. 6.28 RF Current and Power Gain for the GD-MOSFET Structure.

The change in the output power for the GD-MOSFET structure with increasing frequency was obtained by performing the temporal

154


simulations at a variety of frequencies ranging from 0.1 to 16 GHz with an input gate voltage of 0.5 volts. The reduction in the output power with increasing frequency can be seen in Fig. 6.29 for the case of two loadlines. At lower frequencies, the output power obtained from the GDMOSFET device cell is similar to that for the LD-MOSFET structure with the same gate oxide thickness for the larger load-line. Moreover, the output power is maintained at up to 1 GHz. The good output power and high RF gain for the GD-MOSFET structure indicate that this structure could be used in RF power amplifiers for frequencies that cover the entire cellular spectrum from 0.8 to 2.2 GHz. These features of the GDMOSFET structure are also attractive for pulse power and avionics applications.

Fig. 6.29 RF Output Power for the GD-MOSFET structure.

Based upon the available drain current and voltage excursions within the domain of the output characteristic shown in Fig. 6.27, the maximum RF output power that can be obtained from the CC-MOSFET device cell structure is about 1 W/mm of cell width for the case of the dashed load-line. This value is much greater than those obtained from the corresponding LD-MOSFET and VD-MOSFET structures. However, the output power will be constrained by thermal considerations.


6.15 GD-MOSFET with Thinner Gate Oxide

Fig. 6.30 Output Characteristics for GD-MOSFET Structure with Thinner Gate Oxide.

Fig. 6.31 Transfer Characteristics of the GD-MOSFET Structure with Thinner Gate Oxide.

155

156


As discussed in Chapter 3, the performance of power MOSFETs can be improved by reducing the gate oxide thickness. In order to evaluate the behavior of the GD-MOSFET structure, two-dimensional numerical simulations of the device shown in Fig. 6.17 were repeated using a gate oxide thickness of 250 angstroms. All other structural parameters were left unaltered. As expected, reduction of the gate oxide thickness results in an increase in the transconductance and a decrease in the threshold voltage. The impact of this on the output characteristics is shown in Fig. 6.30. The separation between the curves is increased while preserving the basic super-linear behavior. No significant change in the compression current is observed. The transfer characteristics are shown in Fig. 6.31 for this GD-MOSFET structure at a drain bias of 30 volts. The characteristics are extremely linear when compared with the LDMOSFET and VD-MOSFET structures discussed in earlier chapters. The excellent linearity extends to very high current levels due to the large compression current. The compression current density at 300° K is 23,500 A/cm2.

Fig. 6.32 Transconductance of the VD-MOSFET Structure with Thinner Gate Oxide.

The transconductance characteristics are shown in Fig. 6.32 for the GD-MOSFET structure with thinner gate oxide at 300 and 400° K. The transconductance increases rapidly once the gate bias exceeds the


157

threshold voltage and is then relatively constant at both 300° and 400° K. The transconductance for the GD-MOSFET at 300° K is about 90 mS/mm of gate width - the same as for the CC-MOSFET structure. This is much larger (2x) than that for the LD-MOSFET and VD-MOSFET structures because of the shorter channel length in these devices. As shown in the figures, the compression current reduces with increasing temperature. The reduction in the compression current from 300° K to 400° K is about 15 percent, which is similar to that observed for the LDMOSFET and the VD-MOSFET structures. For the GD-MOSFET structure with reduced gate oxide thickness, the values of input, output and reverse transfer capacitances were found to be 0.29, 0.30, and 3 x 10"3 pF per mm of cell width, respectively, at a drain bias of 30 volts. Thus, the reduced gate oxide thickness results in an increase in the input capacitance but not in the output or transfer capacitances.

Fig. 6.33 Current and Power Gain for the GD-MOSFET with Thinner Gate Oxide.

The reduced gate oxide thickness improves the frequency response of the GD-MOSFET structure. The current and power gains are shown in Fig. 6.33 as a function of frequency. At 1 GHz, the power gain with the thinner oxide is 25 dB compared with 21 dB for the 500

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angstrom gate oxide case. The maximum operating frequency is also improved slightly from 9.5 GHz to 10 GHz.

Fig. 6.34 Output Power for the GD-MOSFET with Thinner Gate Oxide

The output power obtained with a gate drive signal of 0.5 volts in magnitude is twice as large, as shown in Fig. 6.34, when the gate oxide is reduced in half. There is no change in the maximum output power (1 W/mm of cell width) that can be delivered from the structure because the compression current is unaltered. 6.16 CC-MOSFET/GD-MOSFET Conclusions The charge coupled MOSFET structure, with either uniform or graded drift layer doping, was originally developed for power switching applications. The relatively high doping concentration in the drift region enables reduction of the drift region resistance to even less than the ideal specific on-resistance for silicon devices. As discussed in this chapter, this structure also enables super-linear operation by reducing the voltage developed across the channel. The analysis described in this chapter demonstrates that very high RF gain and output power can be delivered by the structure within the constraints imposed by packaging.


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The GD-MOSFET structure, with a linearly graded doping profile in the drift region, provides uniform electric field distribution within the drift region with very little voltage drop across the P-base region. This allows shortening the channel length without the usual reach-through breakdown problem, resulting in larger transconductance. The high transconductance in the GD-MOSFET enables excellent RF performance with very high power gain in the 1-2 GHz range, as well as high cut-off and maximum operating frequencies. The fabrication of the GD-MOSFET structure described in this chapter requires recessing the source connected electrode within the deep trenches. This creates a problem with making good low resistance contact to the source connected trench electrode which can degrade high frequency response. This issue is resolved in the SL-MOSFET structure described in the next chapter.

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References 1

B.J. Baliga, "Semiconductors for High Voltage Vertical Channel Field Effect Transistors", J. Applied Physics, Vol. 53, pp. 1759-1764, 1982. 2 B.J. Baliga, "Power Semiconductor Device Figure of Merit for High Frequency Applications", IEEE Electron Device Letters, Vol. EDL-10, pp.455-457, 1989. 3 J.A. Appels and H.M.J. Vaes, "High Voltage Thin Layer Devices (RESURF) Devices", IEEE International Electron Devices Meeting, Abstract 10.1, pp. 238-241, 1979. 4 B.J. Baliga, "Vertical Field effect Transistors having Improved Breakdown Voltage and Low ON-Resistance", U.S. Patent # 5,637,898, Issued June 10, 1997. 5 G. Deboy, M. Marz, J-P. Stengl, H. Strack, J. Tihanyi, and H. Weber, "A New Generation of High Voltage MOSFETs breaks the limit line of Silicon", IEEE International Electron Devices Meeting, Abstract 26.2.1, pp. 683-685, 1998. 6 B.J. Baliga, "Power Semiconductor Devices having improved High Frequency Switching and Breakdown Characteristics", U.S. Patent # 5,998,833, Issued December 7, 1999. 7 MEDICI Two-Dimensional Device Simulation Program, Avant! Corporation, Fremont, CA. 8 B. J. Baliga, "Power Semiconductor Devices", PWS Publishing Company, 1995. 9 B. J. Baliga, "Power Semiconductor Devices having Trench-based Gate Electrodes and Field Plates", U.S. Patent # 6,388,286, Issued May 14, 2002.

Chapter 7

Super-Linear MOSFETs

The charge-coupled power MOSFET structures discussed in the previous chapter allow drastic reduction of the on-resistance of the drift region by utilizing the two-dimensional charge coupling between a sourceconnected electrode located within deep trenches and the donors in the drift region. By using a linearly graded doping profile, a rectangular shaped electric field profile can be generated in the drift region with doping levels ranging above 1 x 1016 cm"3. In addition, it was shown in the previous chapter that the charge coupling phenomenon distributes the electric field primarily in the N-type drift region with very little voltage developed across the P-base region. This allows reduction of the channel length which is beneficial for high frequency operation. In the CC-MOSFET and GD-MOSFET structures described in the previous chapter, the channel is formed on the sidewall of the same trench within which the source-connected electrode is located. This imposes fabrication challenges because of the need to isolate the gate and source electrodes within the trench. In addition, the source-connected electrode in the trench must be periodically brought to the surface to make its electrical connection which disrupts the gate layout in the third dimension. In this chapter, an alternate structure that utilizes the charge coupling concept is described with the gate region formed on the top surface1. This structure, named the super-linear (SL) MOSFET structure, can utilize either a uniform or a graded doping profile. In the previous chapter, it was shown that the uniformly doped drift region case has a highly non-uniform electric field distribution which degrades the output resistance. For this reason, the SL-MOSFET structure with just the linearly graded doping profile will be considered in this chapter. As in the case of previous chapters, the basic operating principles of the super-linear MOSFET structure will first be discussed. The physics of operation will be elucidated by using the results of two161

162


dimensional numerical simulations2 of a typical cell design. These results will be compared with the characteristics of the LD-MOSFET and VDMOSFET structure discussed in earlier chapters. 7.1 Device Cell Structure

Fig. 7.1 Super-Linear (SL) MOSFET Structure.

The two-dimensional charge-coupling discussed in the previous chapter can also be obtained by utilizing the structure1 illustrated in Fig. 7.1 where the trench electrode has been brought up to the surface to enable shorting it to the source electrode. The gate structure is formed on the top of the mesa region by using the double-diffusion process. This planar gate architecture simplifies the fabrication and improves the quality of the channel because it is no longer formed on an etched surface3. The channel length can be controlled by the drive-in cycles for the P-base and N* source regions. Note that the contact to the trench-based sourceelectrode and the contact to the N4" source region are not contiguous. An alternate super-linear (SL) MOSFET structure1 is illustrated in Fig. 7.2. In this case, the contact to the trench-based source-electrode and the contact to the N4" source region are made contiguous. This reduces the space taken up by the contact windows allowing a smaller mesa width and cell pitch. This improves the charge-coupling as well as


163

the channel density. For these reasons, only the second SL-MOSFET structure will be analyzed in this chapter for purposes of comparison with the other devices.

Fig. 7.2 Super-Linear (SL) MOSFET Structure with Contiguous Contacts.

The device can be fabricated by starting with an N-type epitaxial layer, with a linearly graded doping profile, grown on a heavily doped N+ substrate. A deep trench is then etched through most of the drift region followed by lining it with a thick oxide layer that partially fills the trench. Poly silicon is deposited to fill the trench to form the trench based source connected electrode. The gate oxide is grown on the top surface of the mesa region. The polycide gate electrode is formed on the gate oxide. The P-base and N* source regions are then formed by ionimplantation of the respective dopants with self-alignment to the gate electrode. A more heavily doped P+ region is formed using higher energy ion implantation to reduce the sheet resistance of the P-base region without altering the surface doping concentration of the P-base region. The drive-in cycles for the P-base and N* source regions determines the channel length, which can be controlled to sub-micron dimensions. The contact etch step simultaneously opens contacts to the P-base, N* source, and the trench based poly silicon electrode. The P-base and N* source regions are shorted together in the orthogonal direction to suppress the

164


parasitic NPN transistor. After depositing the gate isolation dielectric, the source metal is deposited and patterned. Note that the source electrode covers the entire cell structure at the top surface. Consequently, the SLMOSFET structure does not require fine metal patterns that are needed for the LD-MOSFET structure. In addition, the current density in the source metal is the same as within the silicon if a vertical current collection path can be established from the source contact to the package. This has been accomplished by using a flip-chip technology. The low current density in the source and drain metal electrodes for the SLMOSFET structure eliminates the electromigration failures that have been a problem for LD-MOSFET structures. In the SL-MOSFET structure, it is convenient to use the standard Aluminum based metallization commonly available in manufacturing foundries without resorting to special process modules that are required for the gold based metallization needed in the LD-MOSFET structure to prolong electromigration failures. The doping concentration of donors in the N-epitaxial drift region and the width of the 'mesa' region between the deep trenches must be chosen to obtain optimum charge coupling. A good rule of thumb is that the product of the doping concentration and the mesa width must be between 1 and 2 x 1012 cm"2. Under the assumption that a uniform electric field is created along the vertical direction, the depth of the trench can be determined by dividing the desired breakdown voltage by the critical electric field for breakdown in silicon (about 2-3 x 105 V/cm). Further optimization requires two-dimensional numerical simulations. The breakdown voltage of vertical MOSFET structures is usually decided by the edge termination 3 . The most commonly used edge termination for discrete power devices is based up on floating field rings and field plates. This approach is not adequate for the vertical devices that utilize the charge-coupled concept due to the much higher doping concentration for the drift region than in the conventional vertical devices. Fortunately, it has been found that breakdown at the edges of the chip can be avoided by using a field plate termination with sufficiently thick field oxide 4 . The breakdown then shifts to the device cells allowing full utilization of the charge-coupling concept. Drain current flow in the SL-MOSFET structure is induced by the application of a positive bias to the gate electrode. This produces an inversion layer at the surface of the P-base region under the gate electrode. This inversion layer channel provides a path for transport of


165

electrons from the source to the drain when a positive drain voltage is applied. The channel length in the GD-MOSFET structure must be sufficiently long to avoid reach-through of the depletion layer in the Pbase region. As shown by the results of numerical simulations later in this chapter, the charge-coupling phenomenon in the SL-MOSFET structure enables support of the applied drain voltage within the N-drift region with a low electric field at the P-N junction. This results in very little depletion of the P-base region allowing reduction of the channel length. This is optimal for reducing the device resistance and for obtaining a high transconductance which is beneficial for high frequency operation. The low voltage drop across the channel, even at high drain bias voltages, is also conducive to obtaining the super-linear mode of operation because the channel remains in its linear mode of operation. In the SL-MOSFET structure shown in Fig. 7.2, the drain current flows from the drain electrode through the N* substrate, the N-drift region, a transition region located between the P-base regions, and the inversion layer channel to the top surface source electrode. The onresistance of the structure is determined by the resistance of all these components in the current path: R

on,sp

= R

SUBS,sp + RD,sp + RTRAN ,sp + RCH ,sp

t7'1^

In this equation, the specific channel resistance RCH,SP is given by: CHsp

~ 2u C (V -V )

[7.2]

where Lch is the channel length, WP is the cell pitch, (J.inv is the channel inversion layer mobility, Cox is the specific oxide capacitance of the gate stack, VG is the applied gate voltage, and VT is the device threshold voltage. The factor of 2 in the denominator accounts for the presence of two channels that share the current flow from the drift region via the transition region. For the case of an uniformly doped drift region, the specific drift region resistance RDsp is given by: [7.3]

where p D is the resistivity of the drift region, LT is the trench depth, Wm is the mesa width, and QD is the charge (product of doping and mesa width) in the mesa region. This equation does not take into account the

166


depth of the P-base region which is shallow compared with the total trench depth. The specific resistance of the transition region is given by: K

_ pTRANWP{xp +W0) ™--(LG-2xP-2W0)

UA]

where PJFET is the resistivity of the transition region, xP is the depth of the P-regions, and Wo is the zero-bias depletion width. A unique retrograded doping profile is used in the transition region1 to reduce its resistance while minimizing the counter-doping of the P-base region at the surface. The specific substrate resistance RSUBS,SP is given by: **SUBS,sp = P SUBS* SUBS

U-"

where PSUBS and tSuBS are the resistivity and thickness of the N* substrate. For a typical SL-MOSFET designed to support 75-80 V, the trench depth is about 5 microns with a cell pitch (Wp) of about 5 microns if a mesa width of 3 microns is chosen with a doping concentration of about 1 x 1016 cm"3 for the uniformly doped case. In this case, the drift region contribution to the on-resistance is only 0.5 mOhms-cm . This low value is due to the relatively high doping concentration in the drift region, which would result in a breakdown voltage of less than 20 volts without the charge-coupling effect. An even lower drift region resistance contribution is obtained by using a linearly graded doping profile as discussed later in this chapter. 7.2 SL-MOSFET Simulation Structure Two-dimensional numerical simulations of the SL-MODSFET structure were performed using the structure illustrated in Fig. 7.2 with a trench depth (LT) of 5 microns. The trench width was chosen as 1.8 microns to allow for a thick trench oxide of 3500 angstroms with a polysilicon refill of 1.1 microns. The mesa width was chosen as 3 microns resulting in a full cell pitch of 4.8 microns. As in the case of the LD-MOSFET structure, non-isothermal simulations were also performed to understand the impact of the thermal resistance of the substrate. A 200 micron thick substrate was included for this analysis. The impact of reducing the gate oxide thickness from 500 angstroms to 250 angstroms for the SLMOSFET structure will also be described in this chapter.


167

Fig. 7.3 Three-dimensional view of the Doping Profile for SL-MOSFET Structure.

Fig. 7.4 Doping Profile for SL-MOSFET Structure. (Solid Line: x=1.0 microns; Dashed Line: x=2.4 microns)

] 68


A three dimensional view of the doping profile used for the simulations of the SL-MOSFET structure is shown in Fig. 7.3 for the upper right hand side of the mesa region. It can be seen that the P-base region is more lightly doped that the P+ region located below the If1" source region. The N-type transition region has a retrograded doping profile which can be seen more clearly in Fig. 7.4, where the doping profiles are shown at x = 1.0 microns and x = 2.4 microns. The P+ region depth is chosen to match that for the N-transition region profile. It has been found by simulations that the breakdown voltage of the cell can be degraded if the depth of the P+ region is shallower than for the Ntransition region. On the other hand, if the depth of the P+ region is made much deeper than that of the N-transition region, the resistance of the transition region is enhanced resulting in lower compression currents. The total epitaxial layer thickness is 5.5 microns with a linearly graded doping concentration ranging from 5 x 1015 cm"3 at the top of the mesa to 2 x 1016 cm"3 at the N1" substrate. The N* source region has a depth of about 0.1 microns and the P+ region has a depth of about 0.6 microns. The channel length and doping profile is determined by the N-transition, P-base, and N* source ion implants and subsequent drive cycles.

Fig. 7.5 Channel Doping Profile for SL-MOSFET Structure.


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The channel doping profile is shown in Fig. 7.5 for the SL-MOSFET structure. It can be seen that the channel length is only 0.2 microns. Although this may seem inadequate for supporting high drain voltages due to base reach-through breakdown, numerical simulations demonstrate that very little depletion of the P-base region occurs due to the charge coupling effect in the underlying drift region, as well as the shielding provided by the P+ regions. Note that the peak doping concentration of the P-base region is 1.5 x 1017 cm'3 as controlled by the P-base implant. 7.3 SL-MOSFET Blocking Characteristics

Fig. 7.6 Potential Contours at Vds=70V for the SL-MOSFET Structure.

In all the simulations, the source electrode was held at ground potential. The ability of the SL-MOSFET to support the required blocking voltage was verified by performing simulations with the gate held at ground potential. The breakdown voltage for the structure was found to be 85 V for the doping profiles described above. The potential contours in the SLMOSFET structure are shown in Fig. 7.6 for a drain bias of 70 volts. It

170


can be seen that the drain voltage is supported vertically across the Ndrift region with very little depletion of the P-base region. This allows very narrow channel length in the SL-MOSFET structure. The potential lines are fairly uniform in the mesa region. Note that entire drain voltage is supported across the oxide at the bottom of the trench. For this reason, the trench oxide thickness is chosen as 3500 angstroms so the electric field in the oxide is well below its breakdown strength. The potential lines in the transition region indicate that the potential under the gate electrode is small even for the drain bias of 70 volts. This is due to the shielding provided by the P+ regions. The low potential under the gate is beneficial for supporting high voltages with a small channel length. It also enables super-linear operation by maintaining the channel in the linear mode. Further, the low potential under the gate suppresses hot electron injection into the gate oxide providing excellent immunity from the HCI degradation effects that has plagued the LD-MOSFET technology. Very stable operation has been confirmed for the SLMOSFET structure by tests performed on experimental devices.

Fig. 7.7 Electric Field Distribution in the SL-MOSFET Structure.

A three-dimensional view of the electric field distribution in the mesa region of the SL-MOSFET structure is shown in Fig. 7.7 at a drain


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bias of 70 volts. The electric field is uniformly distributed in the middle of the mesa region with some enhancement at the trench oxide interface. It is also noteworthy that there is dip in the electric field under the gate region. This occurs due to the shielding provided by the P+ regions in the SL-MOSFET structure. A reduced electric field at the gate is beneficial for suppressing reach-through breakdown for a narrow base device and for ameliorating hot carrier effects.

Fig. 7.8 Electric Field Distribution in the SL-MOSFET Structure. (Vds = 5, 10, 20, 30, 40, 50, 60, 70, and 80 volts)

When the drain bias is applied to the SL-MOSFET structure, the voltage is initially supported across the P-base/N-drift region junction with a triangular field distribution (for example at Vds = 5 V in Fig. 7.8). Once the drain bias increases above about 20 volts, the mesa region gets depleted at the upper portion of the mesa leading to the on-set of the charge-coupling phenomenon. Further increase in the drain voltage is then supported by extension of the depletion region within the mesa region. This can be observed in Fig. 7.8 where the electric field is shown at the center of the mesa for various drain bias voltages. As the drain bias increases, the electric field becomes rectangular in shape which is ideal for suppressing impact ionization. In addition, it can be observed that the electric field at the surface (under the gate electrode) remains

172


independent of the drain bias. This suppresses reach-through breakdown and hot electron effects. 7.4 SL-MOSFET On-State Characteristics

Fig. 7.9 On-State Current Flow in the SL-MOSFET Structure.

When a positive bias above the threshold voltage is applied to the gate of the SL-MOSFET structure, an inversion layer channel is formed at the surface of the P-base region at the upper face of the mesa region. This provides a path for the transport of electrons between the drain and source terminals. The device current flow pattern is shown in Fig.7.9. It can be seen that current rapidly spreads from the channel and becomes constricted within the transition region before spreading into the drift (mesa) region. For the above structure with a gate oxide thickness of 500 A, the total on-resistance was found to be 19.6 Ohms/mm of device width at a gate bias of 10 volts based upon two-dimensional numerical simulations. The specific on-resistance for the SL-MOSFET structure is 0.94 mOhm-cm2. This value is significantly larger than for the GDMOSFET structure due to the larger cell pitch and the contribution to the resistance from the transition region.


173

7.5 SL-MOSFET Output and Transfer Characteristics

Fig. 7.10 Output Characteristics of the SL-MOSFET Structure.

Fig. 7.11 Transfer Characteristics of the SL-MOSFET Structure.

The output characteristics for the SL-MOSFET structure are shown in Fig. 7.10 for gate bias voltages ranging from 2.0 to 10 V (in 0.5 V

174


increments). Drain current reaches its saturation value at approximately the same drain voltage of about 10 volts independent of the gate bias. This is a signature of the super-linear mode of operation as discussed in chapter 3. In the current saturation regime of operation, the curves are equally spaced, once again indicating super-linear mode of operation. The transfer characteristics are shown in Fig. 7.11 for the SLMOSFET structure at a drain bias of 30 volts. The transfer characteristics are extremely linear when compared with that for the LD-MOSFET and VD-MOSFET structures discussed in earlier chapters. This is also evident from the transconductance characteristics, shown in Fig. 7.12, for the SL-MOSFET structure at 300 and 400° K. The transconductance increases rapidly once the gate bias exceeds the threshold voltage and is then relatively constant. The transconductance for the SL-MOSFET at 300° K is about 80 mS/mm of cell width. This is much larger (3x) than that for the LD-MOSFET structure because of the shorter channel length. As shown in the figures, the compression current reduces with increasing temperature. This behavior is similar to that of the LD-MOSFET and VD-MOSFET structures described in earlier chapters. The reduction in the transconductance and compression current are detrimental to RF performance.

Fig. 7.12 Transconductance of the SL-MOSFET Structure.


175

7.6 SL-MOSFET Capacitances

Fig. 7.13 Capacitances in the SL-MOSFET Structure.

The input, output and reverse transfer capacitances for the SL-MOSFET structure were extracted by performing two-dimensional numerical simulations of the cell structure with a 1 MHz ac-signal applied to appropriate electrodes. The input capacitance (Cgs) had a weak dependence on the drain voltage. For the SL-MOSFET with 500 angstrom gate oxide, the input capacitance was found to be 0.77 pF/mm of device cell width. The output and reverse transfer capacitances are highly non-linear as shown in Fig. 7.13. This is due to the depletion of the mesa region with increasing drain bias. At low drain bias voltages, the output capacitance (Cds) is primarily determined by the MOScapacitance associated with the source connected electrode in the trench. Once the mesa becomes depleted, the output capacitance reduces as shown in Fig. 7.13. The P+ region in the SL-MOSFET structure acts as a shield between the gate and the drain. This greatly reduces the reverse transfer capacitance (Cgd). At a drain bias of 30V, the output capacitance (Cds) has a value of 0.5 pF/mm and the reverse transfer capacitance (Cgd) has a value of only 1.7 x 10"3 pF/mm. The input and output capacitances are comparable to those for the LD-MOSFET structure in spite of the presence of two channels in the SL-MOSFET structure when compared with only one channel for the LD-MOSFET structure. The reverse transfer capacitance is smaller than for the LD-MOSFET structure by an

176


order of magnitude. This is important for reducing any feedback between the input and output side of power amplifiers because this feedback is known to degrade the linearity and lead to signal distortion. To preserve the low reverse transfer capacitance, it is necessary to use a Faraday shield below the gate pad5 in the SL-MOSFET chip design. 7.7 SL-MOSFET RF Performance

Fig. 7.14 RF Load-line for the SL-MOSFET Structure.

As described in Chapter 4 in the case of the LD-MOSFET structure, the RF response of the SL-MOSFET when biased in the class A mode was analyzed by using a piece-wise temporal simulation using the load-lines shown in Fig. 7.14 with a quiescent drain voltage of 30 volts. The dashed load-line was chosen to obtain the best gain and linearity. (A greater output power can be obtained using the dotted load-line shown in the figure but this produces less power gain.) An RF input gate signal of 0.5 V in magnitude was superimposed up on the 2.5 V DC gate bias point. From the gate and drain currents and voltages obtained using these simulations, the current gain, power gain, as well as the output power, could be extracted using the maximum and minimum values of the


177

sinusoids after the transient response was completed to obtain the rms values for the RF signals. The frequency response of the transistor was obtained by repeating the temporal simulations at a variety of frequencies ranging from 0.1 to 16 GHz. The reduction in the current gain and power gain is shown in Fig. 7.15. This behavior is similar to that predicted by the analytical solutions in Chapter 3 (see Fig. 3.9). The cut-off frequency and maximum operating frequency are 3 and 5.5 GHz, respectively. The power gain at 1 GHz is 20 dB and 14 dB at 2 GHz.

Fig. 7.15 RF Current and Power Gain for the SL-MOSFET Structure.

The change in the output power for the SL-MOSFET structure with increasing frequency was obtained by performing the temporal simulations at a variety of frequencies ranging from 0.1 to 16 GHz with an input gate voltage of 0.5 volts. The reduction in the output power with increasing frequency can be seen in Fig. 7.16. At lower frequencies, the output power obtained from the SL-MOSFET device cell is similar to that for the LD-MOSFET structure with the same gate oxide thickness. As mentioned earlier, more output power is obtained for the larger loadline at low frequencies due to the bigger voltage excursion. The good output power and RF gain for the SL-MOSFET structure indicate that this structure could be used in RF power amplifiers for frequencies that cover the entire cellular spectrum from 0.8 to 2.2 GHz. These features of

178


the SL-MOSFET structure are also attractive for pulse power and avionics applications. Based upon the available drain current and voltage excursions within the domain of the output characteristic shown in Fig. 7.14, the maximum RF output power that can be obtained from the SL-MOSFET device cell structure is about 0.7 W/mm of cell width for the case of the dashed load-line. Higher (1 W/mm) output power can be obtained with the dotted load-line. These values are much greater than those obtained from the corresponding LD-MOSFET structure. However, the output power will be constrained by thermal considerations.

Fig. 7.16 RF Output Power for the SL-MOSFET Structure.

7.8 SL-MOSFET Thermal Effects As discussed in Chapter 3, an increase in the device temperature leads to degradation in RF performance due to the reduction in the channel mobility. Isothermal simulations at elevated temperatures allow an assessment of the change in the transfer curve and transconductance as already shown in Fig. 7.11 and Fig. 7.12, respectively. The change in the output characteristics with temperature is shown in Fig. 7.17. The saturated drain current is independent of temperature for a gate bias of 3.0 volts, indicating an optimum DC operating point from a thermal


179

standpoint. Fortunately, this is also the optimum DC bias point for an RF stand point as discussed in the previous section. The drain current decreases with temperature for larger gate bias voltages due to a reduction in the channel mobility, and it increases with temperature at lower gate bias voltages due to a reduction in the threshold voltage. As discussed for the VD-MOSFET structure, it is important to provide a low thermal impedance for the SL-MOSFET structure. This is feasible by using a flip-chip packaging concept.

Fig. 7.17 Effect of Temperature on the Output Characteristics of the SL-MOSFET Structure. (Solid Line: 300K; Dashed Line: 400K; Dotted: Line 500K)

When the SL-MOSFET is used in amplifiers, the chip must be soldered down to the flange of the package which is then mounted on a heat sink. The traditional approach to packaging vertical power MOSFETs is to solder the drain electrode to a pad located on an insulating layer (such as Beryllium Oxide in the CS-12 package) in the package. Since the high electric field in the SL-MOSFET structure is located within the drift region, most of the power dissipation occurs within about 5 microns at the top of the silicon chip. The heat must then flow through the N* substrate to the bottom drain contact and then through the BeO insulator into the flange. This produces a thermal

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gradient across the wafer and a temperature rise associated with the thermal impedance of the BeO insulator. In order to understand the impact of substrate thermal impedance, non-isothermal simulations were performed for the SL-MOSFET structure with the bottom of the wafer held at a constant temperature of 300° K, i.e. neglecting the thermal impedance of the BeO insulator. The first example of non-isothermal simulations is shown in Fig. 7.18 for the case of 200 micron substrate thickness. For purposes of comparison, the isothermal characteristics are also shown in this figure. It can be seen that the characteristics undergo severe distortion as a consequence of the temperature rise. Thermal run-away is indicated by the rapid up-turn of the drain current with increase in drain bias at the ends of each trace in the non-isothermal output characteristics. The temperature distribution within the SL-MOSFET cell can be observed in the temperature contours shown in Fig. 7.19 for the case of Vgs=1.6V and Vds=50V. The highest temperature is observed within the drift-region because it supports the electric field under the high drain bias conditions.

Fig. 7.18 Non-Isothermal Output Characteristics of the SL-MOSFET Structure. (Solid Line: Isothermal; Dashed Line: Non-Isothermal)


Fig. 7.19 Temperature Contours for the SL-MOSFET Structure (Heat Sink at Drain Electrode)

Fig. 7.20 Temperature Gradient in the SL-MOSFET Structure with 200 micron thick substrate. (Heat Sink at Drain Electrode)

181

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The vertical temperature profile at the center of the SL-MOSFET cell structure is shown in Fig. 7.20 for the same bias point. The heat flow through the thermal impedance of the N* substrate is responsible for the increase in channel temperature. One commonly used approach to improving the thermal impedance for the LD-MOSFET structure is to reduce the wafer thickness. Technology has been developed6 to reduce the substrate thickness down to 50 microns (2 mils). Substantial improvements in the RF performance of LD-MOSFETs have been reported by this reduced substrate thickness7. Although this approach could be applied to the SLMOSFET structure, this does not address the problem of the thermal impedance of the BeO insulator and the detrimental impact of the inductance of source wire-bonds. These issues can be resolved by mounting the vertical SL-MOSFET structure using flip-chip technology to attach the source electrode directly to the flange. This requires isolating the gate electrode, which can be achieved by using a slotted package8. The heat generated in the drift region can then be removed directly via the source electrode.

Fig. 7.21 Non-Isothermal Output Characteristics of the SL-MOSFET Structure. (Solid Line: Non-Isothermal; Dashed Line: Isothermal)

The output characteristics obtained using non-isothermal simulations are shown in Fig. 7.21 for the SL-MOSFET with heat sink attached to the source electrode. Very little distortion of the output


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characteristics is obvious in this figure. The output resistance is larger for the non-isothermal case because of suppression of impact ionization due to slight temperature rise in the drift region. The temperature contours in the SL-MOSFET structure with heat-sink attached to the source electrode are shown in Fig. 7.22 for the case of a gate bias of 4 volts and a drain bias of 60 volts. The highest temperature occurs within the drift region at the center of the mesa.

Fig. 7.22 Temperature Contours for the SL-MOSFET structure with Flip-Chip Packaging (Heat Sink at Source Electrode)

The temperature gradient in the SL-MOSFET cell structure with heat-sink attached to the source electrode is shown in Fig. 7.23 and Fig 7.24 for the case of a gate bias of 4 volts and a drain bias of 60 volts. There is large gradient in temperature within the drift region but very little change through the 200 micron thick substrate. A small peak in the temperature occurs in the drift region, as shown in Fig. 7.24, at a depth of 5 microns from the source electrode. Note that the temperature at the top surface (channel temperature) of the cell (x=0 in the plot) is close to the heat sink temperature (300°K). This is responsible for the suppression of distortion of the output characteristics under non-isothermal conditions.

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The lower channel temperature prevents degradation of the channel mobility which is beneficial for RF performance.

Fig. 7.23 Temperature Gradient in the SL-MOSFET structure with Flip-Chip Packaging. (Heat Sink at Source Electrode)

Fig. 7.24 Temperature Gradient in the SL-MOSFET structure with Flip-Chip Packaging. (Heat Sink at Source Electrode)


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7.9 SL-MOSFET with Thinner Gate Oxide As discussed in Chapter 3, the performance of power MOSFETs can be improved by reducing the gate oxide thickness. In order to evaluate the behavior of the SL-MOSFET structure, two-dimensional numerical simulations of the device structure shown in Fig. 7.2 were repeated using a gate oxide thickness of 250 angstroms. All other structural parameters were left unaltered.

Fig. 7.25 Output Characteristics for SL-MOSFET Structure with Thinner Gate Oxide.

As expected, reduction of the gate oxide thickness results in an increase in the transconductance and a decrease in the threshold voltage. The impact of this on the output characteristics is shown in Fig. 7.25. The separation between the curves is increased while preserving the basic super-linear behavior. No significant change in the compression current is observed. The transfer characteristics are shown in Fig. 7.26 for this SL-MOSFET structure at a drain bias of 30 volts. The characteristics are extremely linear when compared with the LDMOSFET and VD-MOSFET structures discussed in earlier chapters. However, the linearity is not as good as that observed for the GDMOSFET structure. The compression current density for the SL-

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MOSFET at 300° K is 5000 A/cm2, which is also less than that for the GD-MOSFET due to the larger cell pitch for the SL-MOSFET.

Fig. 7.26 Transfer Characteristics of the SL-MOSFET Structure with Thinner Gate Oxide.

Fig. 7.27 Transconductance of the SL-MOSFET Structure with Thinner Gate Oxide.


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The transconductance characteristics are shown in Fig. 7.27 for the SL-MOSFET structure with thinner gate oxide at 300 and 400° K. The transconductance increases rapidly once the gate bias exceeds the threshold voltage and is then relatively constant at both 300° and 400° K. The transconductance for the SL-MOSFET at 300° K is about 170 mS/mm of gate width for a cell with two channels. Although transconductance is the same as for the GD-MOSFET structure, it is much larger (2x) than that for the LD-MOSFET and VD-MOSFET structures because of the longer channel length in those devices. As shown in the figures, the compression current reduces with increasing temperature. The reduction in the compression current from 300° K to 400° K is about 15 percent, which is similar to that observed for the LDMOSFET and the VD-MOSFET structures. For the SL-MOSFET structure with reduced gate oxide thickness, the values of input, output and reverse transfer capacitances were found to be 1.4, 0.45, and 1.5 x 10"3 pF per mm of cell width, respectively, at a drain bias of 30 volts. Thus, the reduced gate oxide thickness results in an increase in the input capacitance but not in the output or transfer capacitances.

Fig. 7.28 RF Load-line for the SL-MOSFET Structure with Thinner Gate Oxide.

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The reduced gate oxide thickness improves the frequency response of the SL-MOSFET structure. Piece-wise temporal simulations were performed using the load-line shown in Fig. 7.28 with a quiescent drain voltage of 30 volts. The dashed load-line was chosen to obtain the best gain and linearity. An RF input gate signal of 0.5 V in magnitude was superimposed up on the 3.0 V DC gate bias point. From the gate and drain currents and voltages obtained using these simulations, the current gain, power gain, as well as the output power, could be extracted using the maximum and minimum values of the sinusoids after the transient response was completed to obtain the rms values for the RF signals.

Fig. 7.29 Current and Power Gain for the SL-MOSFET with Thinner Gate Oxide.

The current and power gains are shown in Fig. 7.29 for the SLMOSFET structure with thinner gate oxide as a function of frequency. At 1 GHz, the power gain with the thinner oxide is 22.5 dB compared with 20 dB for the 500 angstrom gate oxide case. The maximum operating frequency is also improved slightly from 5.5 GHz to 6.5 GHz. The output power obtained with a gate drive signal of 0.5 volts in magnitude is twice as large, as shown in Fig. 7.30, when the gate oxide is reduced in half. There is no change in the maximum output power (1 W/mm of cell width) that can be delivered from the structure because the compression current is unaltered.


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Fig. 7.30 Output Power for the SL-MOSFET with Thinner Gate Oxide.

7.10 SL-MOSFET Conclusions The super-linear (SL) MOSFET structure has been shown to exhibit excellent linearity and output characteristics. The relatively high doping concentration in the drift region achieved by charge-coupling associated with a source electrode embedded in deep trenches, enables reduction of the drift region resistance. At the same time, its planar gate architecture simplifies the fabrication process. This structure also enables super-linear operation by reducing the voltage developed across the channel. The analysis described in this chapter demonstrates that very high RF gain and output power can be delivered by the structure within the constraints imposed by packaging. Due to these favorable features, the SL-MOSFET technology has been commercialized (see Silicon Wireless Corporation datasheets in the appendix). The devices were fabricated using 5 micron deep trenches with a cell pitch of 4.8 microns. In spite of using a doping concentration in excess of 1 x 1016 cm 3 for the drift region, breakdown voltages of over 80 volts were obtained demonstrating the charge-coupling concept. A simple field plate edge termination was utilized4. The gate pad was located at about 15 mils away from the source pad to enable flip-chip assembly. Although the device was fabricated using conventional aluminum based metallization for the source contact, gold bumps were

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placed on the source and gate pads using a rapid bumping tool (Palomar Technologies). The chips were attached to the package by using thermocompression techniques enabling the assembly of multiple transistor cells in one operation. The output characteristics of a typical transistor cell are shown in Fig. 7.31 for the SL-MOSFET structure described above. It can be seen that the current saturation occurs at a drain bias of approximately 5 volts independent of the gate bias. This is a signature of the super-linear mode of operation as discussed in chapter 4. The characteristics are uniformly spaced leading to linear transfer characteristic as shown in Fig. 7.32 when the drain current exceeds 0.1 amperes.

Fig. 7.31 Output Characteristics of the Fabricated SL-MOSFET Structure.

The benefits of the linear transfer characteristics of the experimental SL-MOSFETs on RF performance were quantified by using two tone measurements to obtain the third order inter-modulation (EVID) products. As shown in the data sheets provided in the appendix, the EVID levels for the SL-MOSFET are below -45 dBc. These values are about one order of magnitude superior to those reported for the LDMOSFET structures (see link to typical datasheets in the appendix). The SL-MOSFET structures have also been found to amplify RF signals with lower ACPR and to exhibit much superior memory effects when compared with commercial LD-MOSFET structures. It has been


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demonstrated that the SL-MOSFET can be used for RF base station amplifiers without the feed-forward correction circuitry that is necessary with LD-MOSFETs.

Fig. 7.32 Transfer Characteristics of the Fabricated SL-MOSFET Structure.

192


References 1

B.J. Baliga, "MOSFET Devices having Linear Transfer Characteristics when Operating in Velocity Saturation Mode and Methods of Forming and Operating the Same", U.S. Patent # 6,545,316, Issued April 8, 2003. 2 MEDICI Two-Dimensional Device Simulation Program, Avant! Corporation, Fremont, CA. 3 B.J. Baliga, "Power Semiconductor Devices", PWS Publishing Company, 1995. 4 B.J. Baliga, "Power Semiconductor Devices having Trench-based Gate Electrodes and Field Plates", U.S. Patent # 6,388,286, Issued May 14, 2002. 5 B.J. Baliga, "Radio Frequency (RF) Power Devices having Faraday Shield Layers Therein", U.S. Patent # 6,653,691, Issued November 25, 2003. 6 "Improved Electrical and Thermal Performance of Ultra-thin RF LDMOS Power Transistors", Agere Systems Website, March 2003. 7 S. Xu, A. Shibib, Z. Xie, H. Sofar, J. Lot, D. Farrel, M. Matrapasqua, "High Performance Rf LDMOSFET Technology for 2.1 GHz Power Amplifier Applications", IEEE International Symposium on Power Semiconductor Devices and ICs, pp. 190-195, 2003. 8 B.J. Baliga, "Packaged Power Devices having Vertical Power MOSFETs Therein that are Flip-Chip Mounted to Slotted Gate Electrode Strip-Lines", U.S. Patent # 6,586,833, Issued July 1, 2003.

Chapter 8

Planar Super-Linear MOSFETs

The super-linear (SL) MOSFET structure described in the previous chapter utilizes the charge-coupling concept to reduce the resistance in the drift region. The charge-coupling is achieved by forming a source connected electrode within a deep trench that surrounds the (mesa) drift region. In addition to allowing high doping concentrations in the drift region, the charge-coupling distributes the electric field below the P-base region resulting in a low electric field at the surface. This enables maintaining the channel in the linear mode of operation even at high drain bias voltages - an essential feature to obtain the desired superlinear behavior. In this chapter, a planar super-linear (SL) MOSFET structure is described which does not utilize the charge-coupling concept. The device fabrication process is simplified for this planar gate structure because of eliminating the deep trench regions. The super-linear mode of operation is obtained in the planar SL-MOSFET by utilizing a P+ shielding region located below the P-base region. This shielding region depletes the transition region located under the gate at relatively low drain voltages. Once the transition region is pinched off by the depletion layers, the potential under the gate electrode no longer increases with increasing drain bias. This enables maintaining a low voltage across the channel even when the drain bias is increased up to the breakdown voltage of the structure. Thus, the super-linear mode of operation is achieved by keeping the channel operation in the linear regime while operating the drift region under velocity saturation mode. In addition to the reduced process complexity of the planar SL-MOSFET structure, it has been found that its output capacitance is significantly lower than for the SLMOSFET structure described in the previous chapter. This is beneficial for improving RF performance at high frequencies. As in the case of previous chapters, the basic operating principles of the planar SL-MOSFET structure is first discussed in this 193

194


chapter. The physics of operation will be elucidated by using the results of two-dimensional numerical simulations1 of a typical cell design. These results will be compared with the characteristics of the LD-MOSFET and VD-MOSFET structures discussed in earlier chapters. 8.1 Device Cell Structure

Fie. 8.1 Planar Super-Linear MOSFET Structure

The planar SL-MOSFET structure is shown in Fig. 8.1. A unique feature of this structure is a deep P+ region which is located below the P-base and 1ST source regions. In the VD-MOSFET structure discussed in chapter 5, a deep P+ region is used to reduce the sheet resistance of the Pbase region below the N* source region in order to suppress the parasitic bipolar transistor. Since this region has its highest doping concentration located at the top surface, it is offset from the gate edge to prevent its contribution to the channel doping level which is controlled by the Pbase region. In the planar SL-MOSFET structure, the P+ region is located at the gate edge and its peak is located well below the surface by choosing the appropriate ion implantation energy. The channel doping concentration can then be controlled by the P-base region. The planar gate architecture simplifies the device fabrication process and improves


195

the quality of the channel2. The channel length can be controlled by the drive-in cycles for the P-base and N+ source regions. In the planar SL-MOSFET structure, the P+ region not only serves to reduce the sheet resistance below the N* source region to suppress the parasitic bipolar transistor but also serves to reduce the electric field under the gate electrode and to reduce the reverse transfer capacitance. The doping concentration of the transition region and its width between the P+ regions is chosen so that the transition region becomes depleted at relatively low drain bias voltages (typically at 5 volts). Once this occurs, further increase in the drain potential is supported below the P+ regions while keeping the potential below the gate electrode small. The low surface potential allows maintaining the channel in the linear mode of operation enabling the desired super-linear behavior. The low surface potential also allows reduction of the channel length which enables improvements in RF performance. The device can be fabricated by starting with an N-type epitaxial layer, with a uniform doping profile, grown on a heavily doped N* substrate. Since the breakdown voltage of this structure is limited by the edge termination, the doping concentration of the epitaxial layer must be chosen after including the reduction in breakdown voltage due to electric field crowding at the edges. After defining an active area, the gate oxide is grown on the top surface of the epitaxial layer. The polycide gate electrode is then formed on the gate oxide. The P-base and N+ source regions are then formed by ion-implantation of the respective dopants with self-alignment to the gate electrode. A more heavily doped P+ region is formed using higher energy ion implantation without altering the surface doping concentration of the P-base region. The drive-in cycles for the P-base and N* source regions determines the channel length, which can be controlled to sub-micron dimensions. The contact etch step simultaneously opens contacts to the P-base, and N+ source regions. The P-base and N+ source regions are shorted together to suppress the parasitic NPN transistor. After depositing the gate isolation dielectric, the source metal is deposited and patterned. Note that the source electrode covers the entire cell structure at the top surface. Consequently, the planar SL-MOSFET structure does not require fine metal patterns that are needed for the LD-MOSFET structure. In addition, the current density in the source metal is the same as within the silicon if a vertical current collection path can be established from the source contact to the package. This has been accomplished by using a flip-chip technology. The low current density in the source and drain

196


metal electrodes for the planar SL-MOSFET structure eliminates the electromigration failures that have been a problem for LD-MOSFET structures. In the SL-MOSFET structure, it is convenient to use the standard Aluminum based metallization commonly available in manufacturing foundries without resorting to special process modules that are required for the gold based metallization needed in the LDMOSFET structure to prolong electromigration failures. The doping concentration of donors in the N-epitaxial drift region and its thickness must be chosen to obtain the desired breakdown voltage after accounting for the electric field crowding at the edges. A breakdown voltage within 80 percent of the ideal value can be obtained by using multiple field rings and field plates2. For a breakdown voltage of 75-80 volts, it has been found that the epitaxial layer doping should be 5 x 1015 cm"3 with a thickness of 5 microns. Drain current flow in the planar SL-MOSFET structure is induced by the application of a positive bias to the gate electrode. This produces an inversion layer at the surface of the P-base region under the gate electrode. This inversion layer channel provides a path for transport of electrons from the source to the drain when a positive drain voltage is applied. The channel length in the planar SL-MOSFET structure must be sufficiently long to avoid reach-through of the depletion layer in the Pbase region. As shown by the results of numerical simulations later in this chapter, the shielding of the surface by the P+ regions in the planar SL-MOSFET structure enables support of the applied drain voltage within the N-drift region with a low electric field at the P-base/N transition region junction. This results in very little depletion of the Pbase region allowing reduction of the channel length. This is optimal for reducing the device resistance and for obtaining a high transconductance which is beneficial for high frequency operation. The low voltage drop across the channel, even at high drain bias voltages, is also conducive to obtaining the super-linear mode of operation because the channel remains in its linear mode of operation. In the planar SL-MOSFET structure shown in Fig. 8.1, the drain current flows from the drain electrode through the N* substrate, the Ndrift region, a transition region located between the P-base/P+ regions, and the inversion layer channel to the top surface source electrode. The on-resistance of the structure is determined by the resistance of all these components in the current path: R

on,sp = RSUBS,sp + RD,Sp + RTRAN,sp

+ R

CH,sp

t8'1!


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In this equation, the specific channel resistance RCH,SP is given by: c sp

"'

~2u

C (V

-V)

[8.2]

where Lch is the channel length, Wp is the cell pitch, \xim is the channel inversion layer mobility, Cox is the specific oxide capacitance of the gate stack, VG is the applied gate voltage, and VT is the device threshold voltage. The factor of 2 in the denominator accounts for the presence of two channels that share the current flow from the drift region. After account for current spreading from the transition region, the specific drift region resistance RD?sp is given by: pnWp , (a + t\

[8.3]

where p D is the resistivity of the drift region. This equation takes into account current spreading from the transition region with a width of 2a through a drift region thickness of t. The specific resistance of the transition region is given by:

_ pTRANWP{xP+W0) (LG-2xP-2W0)

[8.4]

where PJFET is the resistivity of the transition region, xP is the depth of the P-regions, and Wo is the zero-bias depletion width. A unique retrograded doping profile is used in the transition region3 to reduce its resistance while minimizing the counter-doping of the P-base region at the surface. The specific substrate resistance RSUBS,SP is given by: K SUBS,sp

=

P SUBS t SUBS

[8.5]

where PSUBS and tSuBS are the resistivity and thickness of the N* substrate. For a typical planar SL-MOSFET designed to support 75-80 V, the epitaxial layer doping concentration and thickness are 5 x 1015 cm"3 and 5 microns. A narrow 1 micron gate width can be used by increasing the doping concentration in the transition region to about 1 x 1017 cm"3. This enables reducing the cell pitch (WP) of about 2 microns which is advantageous for obtaining a high channel density and low on-resistance. The small gate width also reduces the reverse transfer capacitance.

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8.2 Planar SL-MOSFET Simulation Structure Two-dimensional numerical simulations of the planar SL-MOSFET structure were performed using the structure illustrated in Fig. 8.1 with a cell pitch (WP) of 2.2 microns. The impact of reducing the gate oxide thickness from 500 angstroms to 250 angstroms for the planar SLMOSFET structure will also be described in this chapter.

Fig. 8.2 Three-dimensional view of the Doping Profile for the Planar SL-MOSFET Structure.

A three dimensional view of the doping profile used for the simulations of the SL-MOSFET structure is shown in Fig. 8.2 for the upper right hand side of the structure. It can be seen that the P-base region is more lightly doped that the P+ region located below the N+ source region. The N-type transition region has a retrograded doping profile which can be seen more clearly in Fig. 8.3, where the doping profiles are shown at x = 0.5 microns and x = 1.1 microns. The P+ region depth is chosen to match that for the N-transition region profile. It has been found by simulations that the breakdown voltage of the cell can be degraded if the depth of the P+ region is shallower than for the Ntransition region. On the other hand, if the depth of the P+ region is made


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much deeper than that of the N-transition region, the resistance of the transition region is enhanced resulting in lower compression currents.

Fig. 8.3 Doping Profiles for the Planar SL-MOSFET Structure. (Solid Line: x=0.5 microns; Dashed Line: x=l.l microns)

Fig. 8.4 Channel Doping Profile for the Planar SL-MOSFET Structure.

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The total epitaxial layer thickness is 5.0 microns with a uniform doping concentration of 5 x 1015 cm'3. The N+ source region has a depth of about 0.1 microns and the P+ region has a depth of about 0.7 microns. The channel length and doping profile is determined by the N-transition, P-base, and N* source ion implants and subsequent drive cycles. The channel doping profile is shown in Fig. 8.4 for the planar SL-MOSFET structure. It can be seen that the channel length is only 0.16 microns with a peak doping concentration of 1 x 1017 cm"3. Although this may seem inadequate for supporting high drain voltages due to base reach-through breakdown, numerical simulations demonstrate that very little depletion of the P-base region occurs due to the shielding provided by the P+ regions. 8.3 Planar SL-MOSFET Blocking Characteristics

Fig. 8.5 Potential Contours at Vds=70V for the Planar SL-MOSFET Structure.

In all the simulations, the source electrode was held at ground potential. The ability of the planar SL-MOSFET structure to support the required blocking voltage was verified by performing simulations with the gate held at ground potential. The breakdown voltage for the device cell


201

structure was found to be 85 V for the doping profiles described above. This indicates that a device breakdown voltage of 70 volts can be obtained with an edge termination that provides 80-85 percent of ideal parallel plane breakdown voltage. This is achievable using floating field rings and field plates. The potential contours in the planar SL-MOSFET structure are shown in Fig. 8.5 for a drain bias of 70 volts. It can be seen that the drain voltage is supported across the N-drift region with very little depletion of the P-base region. This allows very narrow channel length in the planar SL-MOSFET structure without undergoing reachthrough breakdown. The potential lines have greater separation towards the bottom of the epitaxial layer indicating the typical one-dimensional P-N junction behavior2. The potential lines in the transition region indicate that the potential under the gate electrode is small even for the drain bias of 70 volts. This is due to the shielding provided by the P+ regions. The low potential under the gate is beneficial for supporting high voltages with a small channel length. It also enables super-linear operation by maintaining the channel in the linear mode. Further, the low potential under the gate suppresses hot electron injection into the gate oxide providing excellent immunity from the HCI degradation effects that has plagued the LD-MOSFET technology.

Fig. 8.6 Electric Field Distribution in the Planar SL-MOSFET Structure.

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A three-dimensional view of the electric field distribution in the planar SL-MOSFET structure is shown in Fig. 8.6 at a drain bias of 70 volts. The electric field has a maximum value at the P+/N-drift junction (at x=2.2 microns) as expected for a one-dimensional case with a triangular shape. It is noteworthy that there is dip in the electric field under the gate region. This occurs due to the shielding provided by the P+ regions in the planar SL-MOSFET structure. A reduced electric field at the gate is beneficial for suppressing reach-through breakdown for a narrow base device and for ameliorating hot carrier effects.

Fig. 8.7 Electric Field Distribution in the Planar SL-MOSFET Structure. (Vds = 5, 10, 20, 30, 40, 50, 60, 70, and 80 volts)

When the drain bias is applied to the planar SL-MOSFET structure, the voltage is initially supported across the P+/N-drift region junction (for example at V^ = 3 V). Once the drain bias increases above about 5 volts, the transition region gets depleted between the P+ regions. Further increase in the drain voltage is then supported by extension of the depletion region in the drift region. This can be observed in Fig. 8.7 where the electric field is shown at the center of the cell structure (under the gate) for various drain bias voltages. As the drain bias increases, the electric field increases at a depth of beyond 1 micron and has a triangular shape. However, it can be observed from Fig. 8.7 that the electric field at


203

the surface (under the gate electrode) remains independent of the drain bias. This suppresses reach-through breakdown despite the very short channel length (0.16 microns). It also suppresses hot electron effects by pushing the impact ionization below the surface away from the channel region as discussed in the chapter on hot electron injection instability. The value of the electric field at the surface can be adjusted by changing the doping concentration of the transition region. 8.4 Planar SL-MOSFET On-State Characteristics

Fig. 8.8 On-State Current Flow in the Planar SL-MOSFET Structure.

When a positive bias above the threshold voltage is applied to the gate of the planar SL-MOSFET structure, an inversion layer channel is formed at the surface of the P-base region. This provides a path for the transport of electrons between the drain and source terminals. The device current flow pattern is shown in Fig.8.8. It can be seen that current rapidly spreads from the channel and becomes constricted within the transition region before spreading into the drift region. For the above structure with a gate oxide thickness of 500 A, the total on-resistance was found to be 28 Ohms/mm of device width at a

204


gate bias of 10 volts based upon two-dimensional numerical simulations. The specific on-resistance for the planar SL-MOSFET structure is 0.62 mOhm-cm2. This value is significantly larger than for the GD-MOSFET structure due to the contribution from the transition region but is superior to the SL-MOSFET structure discussed in the previous chapter due to its smaller cell pitch. Thus, the smaller cell pitch offsets the benefits of the charge coupling to the drift region resistance. 8.5 Planar SL-MOSFET Output and Transfer Characteristics

Fig. 8.9 Output Characteristics of the Planar SL-MOSFET Structure.

The output characteristics for the planar SL-MOSFET structure are shown in Fig. 8.9 for gate bias voltages ranging from 1 to 10 V (in 0.5 V increments). Drain current reaches its saturation value at approximately the same drain voltage independent of the gate bias. This is a signature of the super-linear mode of operation as discussed in chapter 3. In the current saturation regime of operation, the curves are equally spaced, once again indicating super-linear mode of operation. The output resistance is lower than for the SL-MOSFET structure discussed in the


205

previous chapter because of enhanced impact ionization resulting from the triangular electric field distribution in the drift region.

Fig. 8.10 Transfer Characteristics of the Planar SL-MOSFET Structure.

The transfer characteristics are shown in Fig. 8.10 for the SLMOSFET structure at a drain bias of 30 volts. The transfer characteristics are extremely linear when compared with that for the LD-MOSFET and VD-MOSFET structures discussed in earlier chapters. This is also evident from the transconductance characteristics, shown in Fig. 8.11, for the SL-MOSFET structure at 300 and 400° K. The transconductance increases rapidly once the gate bias exceeds the threshold voltage and is then relatively constant. The transconductance for the planar SLMOSFET at 300° K is about 80 mS/mm of cell width. This is larger (3x) than that for the LD-MOSFET structure because of the shorter channel length and the presence of two channels per cell in the planar SLMOSFET structure. As shown in the figures, the compression current reduces with increasing temperature. This behavior is similar to that of the LD-MOSFET and VD-MOSFET structures described in earlier chapters. The reduction in the transconductance and compression current with temperature are detrimental to RF performance.

206


Fig. 8.11 Transconductance of the Planar SL-MOSFET Structure.

8.6 Planar SL-MOSFET Capacitances

Fig. 8.12 Capacitances in the Planar SL-MOSFET Structure.


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The input, output and reverse transfer capacitances for the planar SLMOSFET structure were extracted by performing two-dimensional numerical simulations of the cell structure with a 1 MHz ac-signal applied to appropriate electrodes. The input capacitance (Cgs) had a weak dependence on the drain voltage. For the planar SL-MOSFET with 500 angstrom gate oxide, the input capacitance was found to be 0.73 pF/mm of device cell width, the same as for the previous SL-MOSFET structure because of a similar gate structure. The output and reverse transfer capacitances are highly non-linear as shown in Fig. 8.12. This is due to the extension of the depletion region with increasing drain bias. At a drain bias of 30V, the output capacitance (CdS) has a value of 0.05 pF/mm, which an order of magnitude smaller than that for the previous SL-MOSFET structure. This is because of the significant capacitance associated with the source electrode located in the deep trenches in the previous SL-MOSFET structure. The low output capacitance is beneficial for preserving good frequency response as discussed in Chapter 3 and demonstrated for this structure later in the chapter. The P+ region in the planar SL-MOSFET structure acts as a shield between the gate and the drain. This greatly reduces the reverse transfer capacitance (Cgd). The reverse transfer capacitance (Cgd) has a value of 3 x 10"3 pF/mm. For the planar SL-MOSFET structure, the input capacitance is comparable to that for the LD-MOSFET structure in spite of the presence of two channels in the planar SL-MOSFET structure when compared with only one channel for the LD-MOSFET structure. The output and reverse transfer capacitance are smaller than for the LDMOSFET structure by an order of magnitude. This is important for reducing any feedback between the input and output side of power amplifiers because this feedback is known to degrade the linearity and lead to signal distortion. To preserve the low reverse transfer capacitance, it is necessary to use a Faraday shield below the gate pad4 when performing the chip layout. 8.7 Planar SL-MOSFET RF Performance As described in Chapter 4 in the case of the LD-MOSFET structure, the RF response of the SL-MOSFET when biased in the class A mode was analyzed by using a piece-wise temporal simulation using the load-line shown in Fig. 8.13 with a quiescent drain voltage of 30 volts and a quiescent gate bias of 2.5 volts. The dashed load-line was chosen to

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obtain the best gain and linearity. (A greater output power can be obtained using the dotted load-line shown in the figure but this produces less power gain.) An RF input gate signal of 0.5 V in magnitude was superimposed up on the 2.5 V DC gate bias point. From the gate and drain currents and voltages obtained using these simulations, the current gain, power gain, as well as the output power, could be extracted using the maximum and minimum values of the sinusoids after the transient response was completed to obtain the rms values for the RF signals.

Fig. 8.13 RF Load-lines for the Planar SL-MOSFET Structure.

The frequency response of the transistor was obtained by repeating the temporal simulations at a variety of frequencies ranging from 0.1 to 16 GHz. The reduction in the current gain and power gain is shown in Fig. 8.14. This behavior is similar to that predicted by the analytical solutions in Chapter 3 (see Fig. 3.25 and Fig. 3.26). Note that the power gain falls off at a higher frequency for the planar SL-MOSFET structure due to its lower output capacitance. The cut-off frequency and maximum operating frequency are 5.5 and 12 GHz, respectively. The power gain at 1 GHz is 24 dB and 20.5 dB at 2 GHz. These values are much superior to those for all the previously described structures.


209

Fig. 8.14 RF Current and Power Gain for the SL-MOSFET Structure.

Fig. 8.15 RF Output Power for the Planar SL-MOSFET Structure.

The change in the output power for the planar SL-MOSFET structure with increasing frequency was obtained by performing the temporal simulations at a variety of frequencies ranging from 0.1 to 16

210


GHz with an input gate voltage of 0.5 volts. The reduction in the output power with increasing frequency can be seen in Fig. 8.15. At lower frequencies, the output power obtained from the SL-MOSFET device cell is similar to that for the LD-MOSFET structure with the same gate oxide thickness. As mentioned earlier, more output power is obtained for the larger load-line at low frequencies due to the bigger voltage excursion. The good output power and RF gain for the SL-MOSFET structure indicate that this structure could be used in RF power amplifiers for frequencies that cover the entire cellular spectrum from 0.8 to 2.2 GHz. The excellent RF response of the planar SL-MOSFET structure indicates that it could be used in applications up to 5-6 GHz. These features of the planar SL-MOSFET structure are also attractive for pulse power and avionics applications. Based upon the available drain current and voltage excursions within the domain of the output characteristic shown in Fig. 8.13, the maximum RF output power that can be obtained from the planar SLMOSFET device cell structure is about 0.75 W/mm of cell width for the case of the dashed load-line. Higher (0.9 W/mm) output power can be obtained with the dotted load-line. These values are much greater than those obtained from the corresponding LD-MOSFET structure. However, the output power will be constrained by thermal considerations. Thermal effects can be minimized in the planar SLMOSFET structure by using flip-chip technology to mount the source electrode directly on the flange as discussed for the SL-MOSFET structure in the previous chapter. This approach keeps the channel temperature close to that of the flange enabling operation at high current and power density. 8.8 Planar SL-MOSFET Thermal Effects As discussed in Chapter 3, an increase in the device temperature leads to degradation in RF performance due to the reduction in the channel mobility. Isothermal simulations at elevated temperatures allow an assessment of the change in the transfer curve and transconductance as already shown in Fig. 8.10 and Fig. 8.11, respectively. The change in the output characteristics with temperature is shown in Fig. 8.16. The saturated drain current is independent of temperature for a gate bias of 2.5 volts, indicating an optimum DC operating point from a thermal stand point. Fortunately, this is also the optimum DC bias point for an


211

RF stand point as discussed in the previous section for the dashed loadline. The drain current decreases with temperature for larger gate bias voltages due to a reduction in the channel mobility, and it increases with temperature at lower gate bias voltages due to a reduction in the threshold voltage. It is important to provide a low thermal impedance for the planar SL-MOSFET structure. This is feasible by using a flip-chip packaging concept as discussed in the previous chapter for the SLMOSFET structure.

Fig. 8.16 Effect of Temperature on the Output Characteristics of the Planar SLMOSFET Structure. (Solid Line: 300K; Dashed Line: 400K; Dotted: Line 500K)

8.9 Planar SL-MOSFET with Thinner Gate Oxide As discussed in Chapter 3, the performance of power MOSFETs can be improved by reducing the gate oxide thickness. In order to evaluate the behavior of the planar SL-MOSFET structure, two-dimensional numerical simulations of the device structure shown in Fig. 8.1 were repeated using a gate oxide thickness of 250 angstroms. All other structural parameters were left unaltered. As expected, reduction of the gate oxide thickness results in an increase in the transconductance and a decrease in the threshold voltage.

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The impact of this on the output characteristics is shown in Fig. 8.17. The separation between the curves is increased while preserving the basic super-linear behavior. No significant change in the compression current is observed.

Fig. 8.17 Output Characteristics for Planar SL-MOSFET Structure with Thinner Gate Oxide.

The transfer characteristics are shown in Fig. 8.18 for this planar SL-MOSFET structure at a drain bias of 30 volts. The characteristics are extremely linear when compared with the LD-MOSFET and VDMOSFET structures discussed in earlier chapters. However, the linearity is not as good as that observed for the GD-MOSFET structure. The compression current density for the SL-MOSFET at 300° K is 8000 A/cm2, which is also less than that for the GD-MOSFET due to the larger cell pitch for the planar SL-MOSFET. The transconductance characteristics are shown in Fig. 8.19 for the planar SL-MOSFET structure with thinner gate oxide at 300 and 400° K. The transconductance increases rapidly once the gate bias exceeds the threshold voltage and is then relatively constant at both 300° and 400° K. The transconductance for the planar SL-MOSFET structure at 300° K is about 160 mS/mm of gate width for a cell with two channels. Although transconductance is the same as for the GD-MOSFET structure, it is much larger (2x) than that for the LD-MOSFET and VD-MOSFET


213

structures because of the longer channel length in these devices. As shown in the figures, the compression current reduces with increasing temperature. The reduction in the compression current from 300° K to 400° K is about 15 percent, which is similar to that observed for the LDMOSFET and the VD-MOSFET structures.

Fig. 8.18 Transfer Characteristics of the Planar SL-MOSFET Structure with Thinner Gate Oxide.

Fig. 8.19 Transconductance of the Planar SL-MOSFET Structure with Thinner Gate Oxide.

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For the planar SL-MOSFET structure with reduced gate oxide thickness, the values of input, output and reverse transfer capacitances were found to be 1.0, 0.05, and 3 x 10"3 pF per mm of cell width, respectively, at a drain bias of 30 volts. Thus, the reduced gate oxide thickness results in an increase in the input capacitance but not in the output or transfer capacitances. The extremely low output and reverse transfer capacitance for this structure are beneficial for good RF response.

Fig. 8.20 RF Load-line for the Planar SL-MOSFET Structure with Thinner Gate Oxide.

The reduced gate oxide thickness improves the frequency response of the planar SL-MOSFET structure. Piece-wise temporal simulations were performed using the load-line shown in Fig. 8.20 with a quiescent drain voltage of 30 volts. The dashed load-line was chosen to obtain the best gain, linearity, and output power. An RF input gate signal of 0.5 V in magnitude was superimposed up on the 3.0 V DC gate bias point. From the gate and drain currents and voltages obtained using these simulations, the current gain, power gain, as well as the output power, could be extracted using the maximum and minimum values of the sinusoids after the transient response was completed to obtain the rms values for the RF signals.


Fig. 8.21 Current and Power Gain for the Planar SL-MOSFET Structure with Thinner Gate Oxide.

Fig. 8.22 Output Power for the Planar SL-MOSFET structure with Thinner Gate Oxide.

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The current and power gains are shown in Fig. 8.21 for the planar SL-MOSFET structure with thinner gate oxide as a function of frequency. At 1 GHz, the current gain with the thinner oxide is 3 dB larger than for the 500 angstrom gate oxide case. The power gain at 1 GHz is about the same with the thinner gate oxide. However, at 5 GHz, the power gain with the thinner gate oxide is 3 dB larger. The maximum operating frequency is also improved from 12 GHz to 15 GHz. The output power obtained with a gate drive signal of 0.5 volts in magnitude is twice as large, as shown in Fig. 8.22, when the gate oxide is reduced in half. There is no change in the maximum output power (0.9 W/mm of cell width) that can be delivered from the structure because the compression current is unaltered. 8.10 Planar SL-MOSFET Conclusions The planar super-linear (SL) MOSFET structure has been shown to exhibit excellent linearity and output characteristics. In spite of the relatively low doping concentration in the drift region required because of one-dimensional breakdown physics, the drift region resistance is only 50 percent greater than that for structures based on the charge coupling concept. Consequently, the maximum RF output power for the planar SL-MOSFET structure is 0.9 W/mm of RF output power - which is only 10 percent less than that for the structures with charge coupling. When compared with the LD-MOSFET structure, the planar SL-MOSFET structure can deliver three times the output RF power. Due to its planar gate architecture, the fabrication process for the planar SL-MOSFET structure is much simpler than that needed for the device with charge coupling concept. This is because of the elimination of the need for etching deep trenches and refilling them to form the source electrode embedded in the trench. The planar SL-MOSFET structure can be manufactured with standard ion-implantation technology available in foundries. In the planar SL-MOSFET structure, super-linear operation is enabled by reducing the voltage developed across the channel by using a deep P+ region to shield the gate from the drain. This shielding reduces the voltage and electric field at the surface under the planar gate structure. The low surface voltage is responsible for maintaining the channel in the linear domain of operation. The low electric field at the


217

gate suppresses hot-electron generation in the vicinity of the gate oxide, ensuring stable operation under quiescent bias conditions. In addition, the planar SL-MOSFET structure has extremely low output and reverse transfer capacitances when compared with other power MOSFET structures. The analysis described in this chapter demonstrates that this results in very high RF gain and output power that can be delivered by the structure within the constraints imposed by packaging. This analysis indicates that the planar SL-MOSFET is not only suitable for the cellular frequency range (0.8 to 2.2 GHz) but could be used up to 5-6 GHz.

218


References 1

MEDICI Two-Dimensional Device Simulation Program, Avant! Corporation, Fremont, CA. 2 B.J. Baliga, "Power Semiconductor Devices", PWS Publishing Company, 1995. 3 B.J. Baliga, "MOSFET Devices having Linear Transfer Characteristics when Operating in Velocity Saturation Mode and Methods of Forming and Operating the Same", U.S. Patent # 6,545,316, Issued April 8, 2003. 4 B.J. Baliga, "Radio Frequency (RF) Power Devices having Faraday Shield Layers Therein", U.S. Patent # 6,653,691, Issued November 25, 2003.

Chapter 9

Dual Trench MOSFETs

The super-linear (SL) MOSFET structure described in Chapter 7 utilizes the charge-coupling concept to reduce the resistance in the drift region. The charge-coupling is achieved by forming a source connected electrode within a deep trench that surrounds the (mesa) drift region. In addition to allowing high doping concentrations in the drift region, the charge-coupling distributes the electric field below the P-base region resulting in a low electric field at the surface. This enables maintaining the channel in the linear mode of operation even at high drain bias voltages - an essential feature to obtain the desired super-linear behavior. The planar gate structure for that device is formed on the mesa surface. Electron transport occurs from the N+ Source region and the inversion layer channel region through a transition region into the N-drift region. The constriction of current flow in the transition region adds to the onresistance of the structure and limits the maximum drain current (i.e. the compression current). In this chapter, a super-linear (SL) MOSFET structure is described which utilizes the charge-coupling concept exploited in the above device structure but relies up on a trench gate region formed within the mesa region1. The trench gate structure eliminates the transition region resulting in superior on-resistance and compression current. When compared with the trench gate GD-MOSFET structure described in Chapter 6, this structure is easier to fabricate because the gate is not formed within the same trench as the source connected deep trench electrode. The super-linear mode of operation is achieved in the Dual Trench (DT) MOSFET structure by keeping the channel operation in the linear regime while operating the drift region under velocity saturation mode. The charge coupling produced by the source connected deep trench electrode shields the channel from the drain potential enabling operation of the channel in the linear regime.

219

220


As in the case of previous chapters, the basic operating principles of the dual trench (DT)-MOSFET structure will first be discussed. The physics of operation will be elucidated by using the results of two-dimensional numerical simulations2 of a typical cell design. These results will be compared with the characteristics of the devices discussed in earlier chapters. 9.1 Device Cell Structure

Fig. 9.1 Dual Trench (DT) MOSFET Structure

The dual trench (DT) MOSFET structure is shown in Fig. 9.1. It contains a deep trench with a source connected electrode which surrounds the drift (mesa) region. The charge coupling produced between the source connected electrode in the trench and donors in the mesa region creates a uniform electric field profile if a linearly graded doping profile is used as described for the GD-MOSFET structure. The shallow trench formed in the center of the mesa contains the gate electrode. The shallow trench must penetrate through the P-base region to enable formation of an inversion layer channel from the N+ source region to the N-drift region along the sidewalls of the shallow trench. The P+ region serves to reduce the electric field at the corners of the shallow trench and suppress reachthrough in the P-base region.

Dual Trench MOSFETs

221

The device can be fabricated by starting with an N-type epitaxial layer, with a linearly graded doping profile, grown on a heavily doped N* substrate. As in the case of the GD-MOSFET structure, the breakdown voltage can be equal to that for the device cell structure by using a special edge termination3. After defining an active area, the deep trenches are etched, coated with a thick oxide and then filled with heavily doped polysilicon. The P-base, P+, and N4 source regions are formed by ion implantation to the desired depth. The energy and dose for the P-base implant can be chosen so that its peak doping falls below the depth of the N* source region. This enables controlling the threshold voltage with the P-base implant dose. The shallow trench is now formed at the center of the mesa followed by the growth of the gate oxide. The polycide gate electrode is then formed on the gate oxide so that it fills the shallow trench. After deposition of an isolating oxide on the gate electrode, the contact etch step simultaneously opens contacts to the Pbase and N+ source regions, as well as the polysilicon in the deep trenches. The P-base and N* source regions are shorted together to suppress the parasitic NPN transistor. Note that the source electrode covers the entire cell structure at the top surface. Consequently, the DTMOSFET structure does not require fine metal patterns that are needed for the LD-MOSFET structure. In addition, the current density in the source metal is the same as within the silicon if a vertical current collection path can be established from the source contact to the package. This can be accomplished by using a flip-chip technology. The low current density in the source and drain metal electrodes eliminates the electromigration failures that have been a problem for LD-MOSFET structures. In the DT-MOSFET structure, it is convenient to use the standard Aluminum based metallization commonly available in manufacturing foundries without resorting to special process modules that are required for the gold based metallization needed in the LDMOSFET structure to prolong electromigration failures. Drain current flow in the DT-MOSFET structure is induced by the application of a positive bias to the gate electrode. This produces an inversion layer at the surface of the P-base region along the sidewalls of the shallow trench. This inversion layer channel provides a path for transport of electrons from the source to the drain when a positive drain voltage is applied. The channel length in the DT-MOSFET structure must be sufficiently long to avoid reach-through of the depletion layer in the P-base region. As shown by the results of numerical simulations later in this chapter, the shielding of the surface by the charge-coupling effect

222


enables support of the applied drain voltage within the N-drift region with a low electric field at the P-base/N-drift region junction. This results in very little depletion of the P-base region allowing reduction of the channel length. The P + regions also provide shielding of the P-base region from the drain potential and they reduce the electric field at the corners of the shallow trench. In the DT-MOSFET structure shown in Fig. 9.1, the drain current flows from the drain electrode through the N+ substrate, the Ndrift region, and the inversion layer channel to the top surface source electrode. The on-resistance of the structure is determined by the resistance of all these components in the current path: R

on,sp = RSUBS,Sp + RD,sp + RCH,sp

t9-1]

In this equation, the specific channel resistance RCH,spis given by: / W p K CH,sp-

'-'chrv P / _ A H-invôx\VG

X TJ

V

r o ~-. P-ZJ

where Lch is the channel length, WP is the cell pitch, |iinv is the channel inversion layer mobility, Cox is the specific oxide capacitance of the gate stack, VG is the applied gate voltage, and VT is the device threshold voltage. The factor of 2 in the denominator accounts for the presence of two channels that share the current flow from the drift region. The specific drift region resistance RDsp is given by:

»*.—jjT- = ^

[

">

where p D is the resistivity of the drift region, LT is the trench depth, Wm is the mesa width, and QD is the charge (product of doping and mesa width) in the mesa region. This equation does not take into account the depth of the P-base region which is shallow compared with the total trench depth. The specific substrate resistance RSUBS,SP is given by: **SUBS,sp ~ PsUBS^SUBS

[9.4]

where PSUBS and tSUBS are the resistivity and thickness of the N+ substrate. As mentioned earlier, the contribution from the transition region has been eliminated in the DT-MOSFET structure resulting in a lower onresistance per mm of cell width.

Dual Trench MOSFETs

223

9.2 DT-MOSFET Simulation Structure Two-dimensional numerical simulations of the DT-MOSFET structure were performed using the structure illustrated in Fig. 9.1 with a cell pitch (WP) of 3.1 microns. A shallow gate trench with width of 0.5 microns and depth of 0.8 microns was used. The P-base region had a depth of 0.4 microns. The impact of reducing the gate oxide thickness from 500 angstroms to 250 angstroms for this DT-MOSFET structure will be described in this chapter.

Fig. 9.2 Three-dimensional view of the Doping Profile for the DT-MOSFET Structure.

A three dimensional view of the doping profile used for the simulations of the DT-MOSFET structure is shown in Fig. 9.2 for the upper right hand side of the structure up to the deep trench boundary. It can be seen that the P-base region is more lightly doped that the P+ region located below the N* source region. The retrograded doping profile of the P-base region can be seem more clearly in Fig. 9.3, where the doping profiles are shown at x = 0.9 microns (deep trench boundary) and x = 1.3 microns (shallow trench boundary). The P+ region depth is chosen to match that for the shallow trench. This provides optimum shielding of the P-base and trench corners from the drain potential.

224


Fig. 9.3 Doping Profiles for the DT-MOSFET Structure. (Solid Line: x=0.9 microns; Dashed Line: x=1.3 microns)

The total epitaxial layer thickness is 5.5 microns with a linearly graded doping profile. A doping gradient of 1 x 1020 cm"4 was found to provide the desired uniform electric field in the mesa region. The N+ source region has a depth of about 0.1 microns and the P+ region has a depth of about 0.7 microns.

Fig. 9.4 Channel Doping Profile for the DT-MOSFET Structure.

Dual Trench MOSFETs

225

The channel length and doping profile is determined by the energy and dose used for the P-base, and N* source ion implants and subsequent drive cycles. The channel doping profile is shown in Fig. 9.4 for the DT-MOSFET structure. It can be seen that the channel length is only 0.25 microns with a peak doping concentration of 2 x 1017 cm"3. Although this may seem inadequate for supporting high drain voltages due to base reach-through breakdown, numerical simulations demonstrate that very little depletion of the P-base region occurs due to the shielding provided by the P+ regions and the charge-coupling effect. 9.3 DT-MOSFET Blocking Characteristics

Fig. 9.5 Potential Contours at Vds=70V for the DT-MOSFET Structure.

In all the simulations, the source electrode was held at ground potential. The ability of the DT-MOSFET structure to support the required blocking voltage was verified by performing simulations with the gate held at ground potential. The breakdown voltage for the device cell structure was found to be 84 V for the doping profiles described above. The potential contours in the DT-MOSFET structure are shown in Fig. 9.5 for a drain bias of 70 volts. It can be seen that the drain voltage is

226


supported across the N-drift region with essentially no depletion of the Pbase region. This allows very narrow channel length in the DT-MOSFET structure without undergoing reach-through breakdown. The potential lines have uniform separation throughout the drift region indicating optimum charge coupling with proper doping gradient. Due to the shielding provided by the P+ regions, the potential lines do not crowd at the corners of the shallow trench. The low potential at the P-base/N-drift junction enables super-linear operation by maintaining the channel in the linear mode. Further, the low potential at the channel suppresses hot electron injection into the gate oxide providing excellent immunity from the HCI degradation effects that has plagued the LD-MOSFET technology.

Fig. 9.6 Electric Field Distribution in the DT-MOSFET Structure.

A three-dimensional view of the electric field distribution in the DT-MOSFET structure is shown in Fig. 9.6 at a drain bias of 70 volts. The electric field has a maximum value within the oxide that coats the deep trenches. This electric field is below 2 x 106 V/cm at a drain bias of 70 volts because a deep trench oxide thickness of 3500 angstroms was chosen. This is sufficiently low for reliable device operation. A threedimensional view of the electric field in the silicon mesa region is shown in Fig. 9.7. The electric field in the mesa region is very uniform due to

Dual Trench MOSFETs

227

the optimum charge coupling effect. The electric field in the gate oxide is only about 7 x 105 V/cm. Further, there is no electric field enhancement in the gate oxide at the edges of the shallow trench due to the shielding provided by the P+ regions in the DT-MOSFET structure. The reduced electric field at the gate is beneficial for ameliorating hot carrier effects.

Fig. 9.7 Electric Field Distribution in the DT-MOSFET Structure.

Fig. 9.8 Electric Field Distribution in the DT-MOSFET Structure. (Vds = 5, 10, 20, 30, 40, 50, 60, 70, and 80 volts)

228


When the drain bias is applied to the DT-MOSFET structure, the voltage is initially supported across the P+/N-drift region junction (for example at V^ = 3 V). Once the drain bias increases above about 20 volts, the upper part of the mesa region gets depleted between the P+ regions. Further increase in the drain voltage is then supported by extension of the depletion region in the drift region. This can be observed in Fig. 9.8 where the electric field is shown at x=1.27 microns (the sidewall of the shallow trench) for various drain bias voltages. As the drain bias increases, the electric field increases at a depth of beyond 0.7 micron and takes a rectangular shape. However, it can be observed from Fig. 9.8 that the electric field at the edge of the channel (y=0.4 microns) remains very low and is independent of the drain bias. This suppresses reach-through breakdown despite the short channel length (0.25 microns). It also suppresses hot electron effects by pushing the impact ionization away from the channel region as discussed in the chapter on hot electron injection instability. 9.4 DT-MOSFET On-State Characteristics

Fig. 9.9 On-State Current Flow in the DT-MOSFET Structure.

Dual Trench MOSFETs

229

When a positive bias above the threshold voltage is applied to the gate of the DT-MOSFET structure, an inversion layer channel is formed at the surface of the P-base region on the sidewalls of the shallow trench. This provides a path for the transport of electrons between the drain and source terminals. The device current flow pattern is shown in Fig. 9.9. It can be seen that current rapidly spreads from the channel and becomes uniformly distributed within the mesa region. This justifies the onedimensional analysis used earlier for the drift region resistance. For the above structure with a gate oxide thickness of 500 A, the total on-resistance was found to be only 8.8 Ohms/mm of device width at a gate bias of 10 volts based upon two-dimensional numerical simulations. The specific on-resistance for this DT-MOSFET structure is 0.27 mOhm-cm2. This value is comparable to that for the GD-MOSFET structure and much lower than for the SL-MOSFET structure. 9.5 DT-MOSFET Output and Transfer Characteristics

Fig. 9.10 Output Characteristics of the DT-MOSFET Structure.

The output characteristics for the DT-MOSFET structure are shown in Fig. 9.10 for gate bias voltages ranging from 2.5 to 10 V (in 0.5 V increments). The device exhibits excellent output resistance with very low on-resistance. In the current saturation regime of operation, the

230


curves are approximately equally spaced, indicating super-linear mode of operation. The compression current is twice that for the SL-MOSFET with the planar gate structure. This indicates that the charge in the transition region of the planar SL-MOSFET structure limits the compression current.

Fig. 9.11 Transfer Characteristics of the DT-MOSFET Structure.

The transfer characteristics are shown in Fig. 9.11 for the DTMOSFET structure at a drain bias of 30 volts. The transfer characteristics are extremely linear when compared with that for the LD-MOSFET and VD-MOSFET structures discussed in earlier chapters. This is also evident from the transconductance characteristics, shown in Fig. 9.12, for the DT-MOSFET structure at 300 and 400° K. The transconductance increases rapidly once the gate bias exceeds the threshold voltage and is then relatively constant. The transconductance for the planar DTMOSFET at 300° K is about 110 mS/mm of cell width. This is much larger (4x) than that for the LD-MOSFET structure because of the shorter channel length and the presence of two channels that simultaneously feed current into the drift region. As shown in the figures, the compression current reduces with increasing temperature. This behavior is similar to that of the LD-MOSFET and VD-MOSFET structures described in earlier chapters. The reduction in the

Dual Trench MOSFETs

231

transconductance and compression current with temperature are detrimental to RF performance.

Fig. 9.12 Transconductance of the DT-MOSFET Structure.

9.6 DT-MOSFET Capacitances

Fig. 9.13 Capacitances in the DT-MOSFET Structure.

232


The input, output and reverse transfer capacitances for the DT-MOSFET structure were extracted by performing two-dimensional numerical simulations of the cell structure with a 1 MHz ac-signal applied to appropriate electrodes. The input capacitance (Cgs) had a weak dependence on the drain voltage. For the SL-MOSFET with 500 angstrom gate oxide, the input capacitance was found to be 1.15 pF/mm of device cell width, which is twice that for the SL-MOSFET structure in Chapter 7 with the planar gate structure. This is due to the larger gate surface contributed by the sidewalls and bottom of the shallow trench in the DT-MOSFET structure. The output and reverse transfer capacitances are highly nonlinear as shown in Fig. 9.13. This is due to the extension of the depletion region with increasing drain bias. At a drain bias of 30V, the output capacitance (Cds) has a value of 0.5 pF/mm, which is the same as that for the SL-MOSFET structure in Chapter 7. This is because of the significant capacitance associated with the source electrode located in the deep trenches in both the structures. The reverse transfer capacitance (Cgd) for the DT-MOSFET structure is 2 x 10"2 pF/mm. This is much larger than that for the SL-MOSFET structure in Chapter 7 because the trench gate extends towards the drain and is not shielded. Thus, although the trench gate structure enhances the transconductance, it degrades the capacitances of the device structure. 9.7 DT-MOSFET RF Performance As described in Chapter 4 in the case of the LD-MOSFET structure, the RF response of the SL-MOSFET when biased in the class A mode was analyzed by using a piece-wise temporal simulation using the load-line shown in Fig. 9.14 with a quiescent drain voltage of 30 volts and a quiescent gate bias of 4 volts. The dashed load-line was chosen to obtain the best gain and linearity. (A much greater output power can be obtained using the dotted load-line shown in the figure.) An RF input gate signal of 0.5 V in magnitude was superimposed up on the 4 V DC gate bias point. From the gate and drain currents and voltages obtained using these simulations, the current gain, power gain, as well as the output power, could be extracted using the maximum and minimum values of the sinusoids after the transient response was completed to obtain the rms values for the RF signals.

Dual Trench MOSFETs

233

Fig. 9.14 RF Load-lines for the Planar SL-MOSFET Structure.

Fig. 9.15 RF Current and Power Gain for the DT-MOSFET Structure.

The frequency response of the transistor was obtained by repeating the temporal simulations at a variety of frequencies ranging from 0.1 to 16 GHz. The reduction in the current gain and power gain is

234


shown in Fig. 9.15. This behavior is similar to that predicted by the analytical solutions in Chapter 3 (see Fig. 3.9). The cut-off frequency and maximum operating frequency are 2.5 and 5.0 GHz, respectively. The power gain at 1 GHz is 20 dB and 13 dB at 2 GHz. These values are only slightly lower than for the SL-MOSFET structure in Chapter 7 with the planar gate structure. Thus, the increase in transconductance in the DTMOSFET structure offsets the higher capacitances in this structure.

Fig. 9.16 RF Output Power for the DT-MOSFET structure

The change in the output power for the DT-MOSFET structure with increasing frequency was obtained by performing the temporal simulations at a variety of frequencies ranging from 0.1 to 16 GHz with an input gate voltage of 0.5 volts. The reduction in the output power with increasing frequency can be seen in Fig. 9.16. At lower frequencies, the output power obtained from the SL-MOSFET device cell is similar to that for the LD-MOSFET structure with the same gate oxide thickness. As mentioned earlier, more output power is obtained for the larger loadline at low frequencies due to the bigger voltage excursion. The good output power and RF gain for the SL-MOSFET structure indicate that this structure could be used in RF power amplifiers for frequencies that cover the entire cellular spectrum from 0.8 to 2.2 GHz. These features of the planar SL-MOSFET structure are also attractive for pulse power and avionics applications.

Dual Trench MOSFETs

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Based upon the available drain current and voltage excursions within the domain of the output characteristic shown in Fig. 9.14, the maximum RF output power that can be obtained from the planar SL-MOSFET device cell structure is about 1.2 W/mm of cell width for the case of the dashed load-line. A larger (2.4 W/mm) output power can be obtained with the dotted load-line. These values are much greater than those obtained from the corresponding LD-MOSFET structure. However, the output power will be constrained by thermal considerations. Thermal effects can be minimized in the DT-MOSFET structure by using flip-chip technology to mount the source electrode directly on the flange as discussed for the SL-MOSFET structure in the previous chapter. This approach keeps the channel temperature close to that of the flange enabling operation at high current and power density. 9.8 DT-MOSFET Thermal Effects

Fig. 9.17 Effect of Temperature on the Output Characteristics of the DT-MOSFET Structure. (Solid Line: 300K; Dashed Line: 400K; Dotted: Line 500K)

As discussed in Chapter 3, an increase in the device temperature leads to degradation in RF performance due to the reduction in the channel mobility. Isothermal simulations at elevated temperatures allow an

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assessment of the change in the transfer curve and transconductance as already shown in Fig. 9.11 and Fig. 9.12, respectively. The change in the output characteristics with temperature is shown in Fig. 9.17. The saturated drain current is independent of temperature for a gate bias of 4.0 volts, indicating an optimum DC operating point from a thermal stand point. Fortunately, this is also the optimum DC bias point for an RF stand point as discussed in the previous section for the dashed loadline. The drain current decreases with temperature for larger gate bias voltages due to a reduction in the channel mobility, and it increases with temperature at lower gate bias voltages due to a reduction in the threshold voltage. It is important to provide a low thermal impedance for the DT-MOSFET structure. This is feasible by using a flip-chip packaging concept as discussed in the previous chapter for the SLMOSFET structure.

9.9 DT-MOSFET with Thinner Gate Oxide

Fig. 9.18 Output Characteristics for DT-MOSFET Structure with Thinner Gate Oxide.

As discussed in Chapter 3, the performance of power MOSFETs can be improved by reducing the gate oxide thickness. In order to evaluate the behavior of the DT-MOSFET structure, two-dimensional numerical

Dual Trench MOSFETs

237

simulations of the device structure shown in Fig. 9.1 were repeated using a gate oxide thickness of 250 angstroms. All other structural parameters were left unaltered As expected, reduction of the gate oxide thickness results in an increase in the transconductance and a decrease in the threshold voltage. The impact of this on the output characteristics is shown in Fig. 9.18. The separation between the curves is increased while preserving the basic super-linear behavior. No significant change in the compression current is observed.

Fig. 9.19 Transfer Characteristics of the DT-MOSFET Structure.

The transfer characteristics are shown in Fig. 9.19 for this DTMOSFET structure at a drain bias of 30 volts. The characteristics are extremely linear when compared with the LD-MOSFET and VDMOSFET structures discussed in earlier chapters. The compression current density for the DT-MOSFET at 300° K is 14,500 A/cm2, which is large when compared with the other structures. The transconductance characteristics are shown in Fig. 9.20 for the DT-MOSFET structure with thinner gate oxide at 300 and 400° K. The transconductance increases rapidly once the gate bias exceeds the threshold voltage and is then relatively constant at both 300° and 400° K. The transconductance for the DT-MOSFET at 300° K is about 220

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mS/mm of gate width for a cell with two channels. Although transconductance is the same as for the GD-MOSFET structure, it is much larger (2x) than that for the LD-MOSFET and VD-MOSFET structures because of the longer channel length in these devices. As shown in the figures, the compression current reduces with increasing temperature. The reduction in the compression current from 300° K to 400° K is about 15 percent, which is similar to that observed for the LD-MOSFET and the VD-MOSFET structures.

Fig. 9.20 Transconductance of the DT-MOSFET Structure with Thinner Gate Oxide.

For the DT-MOSFET structure with reduced gate oxide thickness, the values of input, output and reverse transfer capacitances were found to be 2.0, 0.5, and 2 x 10"2 pF per mm of cell width, respectively, at a drain bias of 30 volts. Thus, the reduced gate oxide thickness results in an increase in the input capacitance but not in the output or transfer capacitances. The reduced gate oxide thickness improves the frequency response of the DT-MOSFET structure. Piece-wise temporal simulations were performed using the load-line shown in Fig. 9.21 with a quiescent drain voltage of 30 volts. The dashed load-line was chosen to obtain the best gain, linearity, and output power. An RF input gate signal of 0.5 V in magnitude was superimposed up on the 2.0 V DC gate bias point.

Dual Trench MOSFETs

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From the gate and drain currents and voltages obtained using these simulations, the current gain, power gain, as well as the output power, could be extracted using the maximum and minimum values of the sinusoids after the transient response was completed to obtain the rms values for the RF signals.

Fig. 9.21 RF Load-line for the DT-MOSFET Structure with Thinner Gate Oxide.

The current and power gains are shown in Fig. 9.22 for the DT-MOSFET structure with thinner gate oxide as a function of frequency. At 1 GHz, the current gain with the thinner oxide is the same as for the 500 angstrom gate oxide case. However, the power gain is 2 dB larger at 1 GHz and 3.5 dB larger at 2 GHz with the thinner gate oxide. The maximum operating frequency is also improved from 5.5 GHz to 7.0 GHz. The output power obtained with a gate drive signal of 0.5 volts in magnitude is more than twice as large, as shown in Fig. 9.23, when the gate oxide is reduced in half. There is no change in the maximum output power (2.4 W/ram of cell width) that can be delivered from the structure because the compression current is unaltered. Thus, the DT-MOSFET structure can provide very high power density, as well as good power gain in the cellular frequency range.

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Fig. 9.22 Current and Power Gain for the DT-MOSFET with Thinner Gate Oxide.

Fig. 9.23 Output Power for the DT-MOSFET structure with Thinner Gate Oxide.

Dual Trench MOSFETs

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9.10 DT-MOSFET Conclusions The dual-trench (DT) MOSFET structure has been shown to exhibit excellent linearity and output characteristics. This device structure has the highest compression current because electron injection into the drift region is not constrained by the charge in the transition region. The analysis described in this chapter demonstrates that very high RF gain and output power (2.4 W/mm) can be delivered by the structure within the constraints imposed by packaging. The analysis indicates that the DT-MOSFET structure is suitable for the cellular frequency range (0.8 to 2.2 GHz). The shallow trench used for the gate region of the DT-MOSFET structure is commonly used for fabrication of trench gate power MOSFET structures. Thus, the DT-MOSFET structure is compatible with the manufacturing of trench gate power devices with the addition of a deep trench region with embedded source connected electrode to provide charge coupling. In the trench gate power MOSFET structure, a high electric field is created at the trench corners necessitating the special etching processes to round the corners. This problem does not occur in the DT-MOSFET structure because of the charge coupling effect moves the electric field lower in the drift region away from the shallow trench. Although the DT-MOSFET structure is comparable to the SLMOSFET structure described in chapter 7 with regard to the current and power gain, much higher output RF power can be obtained from the DTMOSFET structure. This makes it particularly attractive for pulse power and avionics applications.

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References 1

B.J. Baliga, "Vertical Power Devices having Trench based Electrodes Therein", U. S. Patent # 6,649,975, Issued November 18, 2003. 2 MEDICI Two-Dimensional Device Simulation Program, Avant! Corporation, Fremont, CA. 3 B.J. Baliga, "Power Semiconductor Devices having Trench Based Gate Electrodes and Field Plates", U.S. Patent # 6,388,286, Issued May 14, 2002.

Chapter 10

Hot Carrier Injection Instability

The commercial introduction of the silicon RF power LD-MOSFETs in the 1990's was widely accepted by the cellular base station design community due to its superior linearity when compared with the existing silicon bipolar RF power transistors, as well as its lower cost when compared with existing gallium arsenide RF power transistors. However, these devices were found to exhibit instability in the quiescent operating point. It was discovered that the quiescent drain current at the chosen operating DC gate bias voltage changed by more than 20 percent over the operating life of the product. Due to the exponential nature of this variation, the instability was manifested by a large change in drain current at the early stages of the operating life of products. The changes in the quiescent drain current had significant adverse impact on the linearity of the transistor because the quiescent drain current is optimized for delivering the best combination of linearity and efficiency in RF power amplifiers. One approach taken to address this instability was to 'burn-in' the products prior to installation in power amplifiers. Although somewhat effective, this approach adds significant cost to the production of RF LD-MOSFETs because the burn-in must be done with each transistor biased under optimum conditions. Another approach taken was to add additional circuitry in the RF amplifier too monitor and adjust the quiescent drain current. This approach also adds considerable expense because the circuitry must be able to take into account changes in ambient temperature. Meanwhile, improvements to the RF LD-MOSFET structure were implemented to reduce the instability. Modern RF LDMOSFETs, which are in their sixth generation of improvements, have the drift in drain current reduced to less than 5 percent over a 20 year life span. In this chapter, the physics responsible for the instability in the quiescent drain current is described. The impact of changes in the 243

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physical parameters of the LD-MOSFET structure that influence the instability are analyzed using two-dimensional numerical simulations. The trade-off required between reducing the instability and maximizing output power is described. The methodology used to address the root cause of the instability in the new vertical power MOSFET structures is described here with some examples. The results of two-dimensional numerical simulations are used to demonstrate mitigating the instability problem. These measures have been successful in reducing the changes in the quiescent drain current to less than 2 percent over a 20 year life span even for the very first generation of SL-MOSFET products. 10.1 Quiescent Drain Current Instability The instability in the quiescent drain current for the RF LD-MOSFET structure has been traced to the injection of 'hot-electrons' into the gate oxide. This phenomenon has been discussed extensively in the VLSI literature due to its impact on scaling of lateral MOSFETs1'2. The injection of hot-electrons into the gate oxide produces a shift in the threshold voltage of the MOSFET leading to changes in the drain current if the gate bias is held at a fixed level. The hot-electrons are generated by impact ionization in the drift region due to high electric fields created by the applied drain bias. If the energy of the hot-electrons is sufficient to surmount the energy barrier between silicon and silicon dioxide, they can be injected into the gate oxide. Once injected into the gate oxide, the electrons are resident in traps in the oxide. The hot-electron instability in the MOSFET structure involves the generation, injection, and trapping of electrons. The instability can be mitigated by addressing each of these phenomena. The hot-electron generation process is dependent upon the electric field in the drift region adjacent to the gate. Structural design alterations can be made to move the peak electric field away from the gate edge. This will be discussed in more detail in relation to the lateral LD-MOSFET and the vertical SLMOSFET structures. The electric field distribution under the quiescent bias conditions will be analyzed and compared to that under off-state conditions because this determines the generation of hot electrons for each structure. The injection probability for electrons into the gate oxide can be expressed as1:


-p(-|r)-exp(-f)

245

[ill]

where | b is the energy required for electrons to surmount the Si-SiO2 barrier, k is Boltzmann's constant, Te is the electron temperature, x is the distance of the electron from the Si-SiO2 interface, and X is the electron mean free path. The second part of this expression describes the probability for electrons at a distance x to travel to the interface without undergoing inelastic collisions that would dissipate their energy. If the structure is engineered to move the location of the impact ionization that generates the hot-electrons away from the Si-SiO2 interface, the injection of hot-electrons into the gate oxide can be minimized. A strategy to reduce the instability arising from the hot-electrons is to reduce the density of traps in the oxide. Special gate oxide growth conditions and processing with low hydrogen content are known to suppress charge trapping. However, the most prudent approach is to minimize the generation of hot electrons near the gate oxide interface. The impact of structural changes on the electric field at the gate interface is consequently discussed in this chapter for both lateral and vertical devices. For these RF power MOSFETs, the instability is associated with hot-electron injection under the quiescent bias conditions. For the class A operating conditions analyzed in previous chapters, this corresponds to a drain bias of 30 volts with substantial current flow through the channel. It is relevant to examine the electric field and impact ionization in the device structures under these operating conditions to understand their vulnerability to hot-electron effects. 10.2 LD-MOSFET Structure The basic LD-MOSFET structure was shown in chapter 4 (Fig. 4.1.) As discussed in chapter 4, the electric field distribution in the structure is strongly dependent upon the doping concentration in the drift region which is determined by the LDD-dose. At lower dose levels, the peak in the electric field occurs away from the gate edge. The LD-MOSFET structure with a LDD-dose of 1 x 1012 cm"2 was analyzed in chapter 4 because it has a low electric field at the gate edge which promotes stable operation. However, this low dose results in a relatively high resistance (60 ohms/mm in Fig. 4.9) for the LDD-region. The low dose also reduces the compression current resulting in a reduced output power capability.

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Thus, the improved stability has been achieved at the expense of reduced RF performance.

Fig. 10.1 (a) Three-dimensional Electric Field distribution for the LD-MOSFET Structure with LDD-dose of 1 x 1012 cm 2 at Vgs = 0 V and Vds = 30 V.

Fig. 10.1(b) Three-dimensional Electric Field distribution for the LD-MOSFET Structure with LDD-dose of 1 x 1012 cm'2 at Vgs = 6 V and Vds = 30 V.


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Fig. 10.2 Electric Field Profile for the LD-MOSFET Structure with LDD-dose of 1 x 1012 cm 2 at Vgs of 0 and 6 V for Vds = 30 V.

The electric field distribution in the LD-MOSFET structure with LDD-dose of 1 x 1012 cm"2 was shown in chapter 4 (Fig. 4.6) for the case of zero gate bias. This distribution gets altered under the quiescent operating conditions because of the current flow through the drift region. This can be observed in Fig. 10.1 where the three-dimensional distribution of the electric field in the LD-MOSFET structure with LDDdose of 1 x 1012 cm'2 are shown for the case of the quiescent gate bias of 0 and 6 volts at the same quiescent drain bias of 30 volts. In comparison with the Vgs = 0 volt case, the electric field gets severely enhanced under the gate close to the channel. This can be seen more clearly in Fig. 10.2 where the electric field along the top silicon surface is shown for the two gate biases at the same quiescent drain bias of 30 volts. Note that the high electric field point moves under the gate towards the channel and is close to the Si-SiO2 interface. This is detrimental to stable operation because hot electrons are created close to the surface under the gate electrode under the quiescent bias conditions. Under the presence of significant drain current flow through the drift region, the LDD-region is no longer operating as a depleted region as under the zero gate bias conditions. Instead, the drain current flow in

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the LDD region occurs by transport of electrons at the saturated drift velocity. The density of electrons (n) in the drift region is related to the current density (J) by: J = qnvnsat

[10.2]

where vnsat is the saturated drift velocity for electrons. Using a drain current of 2 x 10"5 A/micron at a quiescent gate bias of 6 volts and noting that the drain current flows through a small thickness of about 0.1 microns (see current flow-lines in Fig. 4.10), the calculated electron concentration is about 1 x 1016 cm"3. This value is comparable to the doping concentration (see Fig. 4.4) in the LDD-region. The net charge in the drift region is consequently altered because the electrons add a negative charge to the existing positive charge associated with the donors. This is responsible for the alteration of the electric field under quiescent bias operating conditions.

Fig. 10.3 Hot-carrier generation in the LD-MOSFET Structure with LDD-dose of 1 x 1012 cm"3 at Vgs = 6 V.

The hot carrier concentration generated by impact ionization at a gate bias of 6 volts is shown in Fig. 10.3 for various drain bias voltages. In spite of the low LDD-dose, there are significant impact ionization generated carriers at the gate edge. Similar results have been observed in


249

other studies3. In these studies, one method used to quantify the performance of structures with regard to hot-electron instability is examination of the substrate current. The substrate current (or current flowing in the P-base region) in MOSFET structures has been correlated to the injection of hot-electrons4 into the gate oxide. The substrate (Pbase current) current was extracted for the LD-MOSFET structure with LDD-dose of 1 x 1012 cm"2 as a function of gate bias while maintaining the drain bias at the quiescent value of 30 volts. The plot shown in Fig. 10.4 indicates that the substrate current is low at the quiescent operating gate bias (6 V) leading to stable operation.

Fig. 10.4 Substrate (P-base) current in the LD-MOSFET Structure with LDD-dose of 1 x 1012 cm'3 at Vds = 30 V.

Optimization of the performance of the LD-MOSFET structure requires proper choice of the doping concentration in the LDD-region. As already shown in chapter 4 with the aid of Fig. 4.9, a reduction of the on-resistance can be achieved by increasing the LDD-dose. However, when the dose exceeds 4 x 1012 cm"2, the breakdown voltage degrades. Consequently, it is interesting to consider the option of improving the performance of the LD-MOSFET structure by increasing the dose from 1 x 1012 cm"2 to 3 x 1012 cm"2. From Fig. 4.9, this results in a reduction of the on-resistance from 60 Ohms/mm to 27 Ohms/mm of cell width. A larger LDD-dose also results in a larger compression current. The output characteristics for the LD-MOSFET structure with a LDD-

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dose of 3 x 1012 cm"2 are shown in Fig. 10.5. The basic square-law behavior is retained but a much larger drain current excursion is possible with the higher LDD-dose. This allows the structure to deliver greater output power by using the load-line shown by the dashed line with a quiescent gate bias of 7.5 volts.

Fig. 10.5 Output Characteristics for the LD-MOSFET Structure with LDD-dose of 3 x 1012 cm"2.

Fig. 10.6 Output Power for the LD-MOSFET Structure with LDD-dose of 3 x 1012 cm"2.


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The RF output power for the LD-MOSFET structure with a LDD-dose of 3 x 1012 cm"2 is shown in Fig. 10.6 as a function of frequency. When compared with the structure with LDD-dose of 1 x 1012 cm"2, the output power is smaller at lower frequencies, as shown in Fig. 10.6, because of the smaller load-line resistance used for the structure with LDD-dose of 3 x 1012 cm"2. However, the output power is larger at higher frequencies and, as shown in Fig. 10.7, the power gain is larger by about 3 dB in the frequency range of 1 to 2 GHz. In addition, the maximum output power for this load-line is 0.945 W/mm compared with only 0.27 W/mm for the structure with LDD-dose of 1 x 1012 cm"2.

Fig. 10.7 RF Gain for the LD-MOSFET Structure with LDD-dose of 3 x 1012 cm"2.

These improvements in RF performance are obtained at the expense of device stability. The increase in LDD-dose results in maximum electric field moving from the drain side towards the gate side even for the zero gate bias case as shown by the three-dimensional electric field plots in Fig. 10.8(a) at a drain bias of 30 volts. Under quiescent bias conditions, the peak in the electric field moves under the gate towards the channel as shown by the three-dimensional electric field plots in Fig. 10.8(b). This can be seen more clearly in Fig. 10.9. The peak electric field is high for the LDMOSFET structure with LDD-dose of 3 x 1012 cm"2 and that the peak moves from the LDD-region to underneath

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the gate electrode closer to the channel. This exacerbates the hot-electron problem because they are now generated at the vicinity of the channel.

Fig. 10.8(a) Three-dimensional Electric Field distribution for the LD-MOSFET Structure with LDD-dose of 3 x 1012 cm'2 at Vgs = 0 V and Vds = 30 V.

Fig. 10.8(b) Three-dimensional Electric Field distribution for the LD-MOSFET Structure with LDD-dose of 3 x 1012 cm"2 at Vds = 30 V for Vgs = 7.5 V.


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Fig. 10.9 Electric Field Profile for the LD-MOSFET Structure with LDD-dose of 3 x 1012 cm"2 at Vgs of 0 and 7.5 V for Vds = 30 V.

Fig. 10.10 Substrate (P-base) current in the LD-MOSFET Structure with LDD-dose of 3 x 1012 cm"3 at Vds = 30 V.

The substrate (P-base) current for the LD-MOSFET structure with LDD-dose of 3 x 1012 cm"2 is shown in Fig. 10.10 when the gate

254


bias is varied with the drain bias held constant at 30 volts. The shape and magnitude of this current closely matches that given in the literature3. At the quiescent gate bias, its peak value is larger than for the LD-MOSFET structure with LDD-dose of 1 x 1012 cm"2. This is corroborated by the much higher generation rate for hot carriers at the gate edge as shown in Fig. 10.11. The generation rate due to impact ionization at the gate edge (x=6.5 microns) can be observed to be 1022per cm3 when compared with only 1017 per cm3 for the LD-MOSFET structure with LDD-dose of 1 x 1012 cm"2 (see Fig. 10.3). Thus, the optimization of the LD-MOSFET structure requires a compromise between RF performance and stability.

Fig. 10.11 Hot-carrier generation in the LD-MOSFET Structure with LDD-dose of 3 x 1012 cm 3 at Vgs = 7.5 V.

The above discussion was based up on a quiescent operating point relevant for class A operation with a load-line as shown in Fig. 10.5. It is commonplace in RF power amplifiers to operate under class AB conditions to reduce power dissipation under quiescent bias conditions. This requires biasing the transistor just above the on-set of current conduction. This corresponds to gate bias of 6 volts for the LDMOSFET structure with LDD-dose of 3 x 1012 cm'2. From Fig. 10.10, it can be seen that the substrate current is the largest at this bias point creating hot electron instability.


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10.3 GD-MOSFET Structure

Fig. 10.12(a) Three-dimensional Electric Field distribution for the GD-MOSFET Structure at Vds = 30 V for Vgs = 0 V.

Fig. 10.12(b) Three-dimensional Electric Field distribution for the GD-MOSFET Structure at Vds = 30 V for Vgs = 4 V.

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In Chapter 6, it was demonstrated that the GD-MOSFET structure offers excellent linearity with very high compression current and RF output power. In this section, the electric field distribution in this structure and the generation of hot carriers due to impact ionization under quiescent bias conditions (Vgs = 4.0 V; Vds = 30 V) are examined to determine their impact on device stability. Three dimensional views of the electric field distribution for the GD-MOSFET structure are shown in Fig. 10.12 at a drain bias of 30 volts for the case of gate biases of 0 and 4 volts. Unlike in the LDMOSFET structure, it can be seen that electric field at the edge of the gate becomes smaller when the device is operating at the quiescent gate bias of 4 volts. The reduction of the electric field at the edge of gate can be seen more clearly in the one-dimensional plot, shown in Fig. 10.13, taken along the y-direction at the side wall of the deep trench. The electric field is reduced by nearly a factor of 2x.

Fig. 10.13 Electric Field Profile for the GD-MOSFET Structure for Vgs of 0 and 4 V at Vds = 30 V.

The substrate (Base current) in the GD-MOSFET structure is shown in Fig. 10.14 at a drain bias of 30 volts. The maximum value for the current is about 3x larger than for the LD-MOSFET structure with LDD-dose of 3 x 1012 cm"2. Further, the impact ionization generated carrier density is very high at the gate edge as shown in Fig. 10.15 in the


257

GD-MOSFET structure. At a drain bias of 30 volts with a gate bias of 4 volts, the generated carrier density at the gate edge is 1026 per cm3. This indicates potential stability problems for the GD-MOSFET structure.

Fig. 10.14 Substrate (P-base) current in the GD-MOSFET Structure at V^ = 30 V.

Fig. 10.15 Hot-carrier generation in the GD-MOSFET Structure at Vgs = 4 V.

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10.4 SL-MOSFET Structure

Fig. 10.16(a) Three-dimensional Electric Field distribution for the SL-MOSFET Structure at Vds = 30 V for Vgs = 0 V.

Fig. 10.16(b) Three-dimensional Electric Field distribution for the SL-MOSFET Structure at Vds = 30 V for Vgs = 3 V.


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In Chapter 7, it was demonstrated that the SL-MOSFET structure offers excellent linearity with very high compression current and RF output power. In this section, the electric field distribution in this structure and the generation of hot carriers due to impact ionization under quiescent bias conditions (Vgs = 3.0 V; Vds = 30 V) are examined to determine their impact on device stability. Three dimensional views of the electric field distribution for the SL-MOSFET structure are shown in Fig. 10.16 at a drain bias of 30 volts for the case of gate biases of 0 and 3 volts. It can be seen that electric field becomes smaller, especially at the center of the gate, when the device is operating at the quiescent gate bias of 3 volts. The reduction of the electric field can be seen more clearly in the one-dimensional plot, shown in Fig. 10.17, taken along the x-direction along the mesa surface.

Fig. 10.17 Electric Field Profile for the SL-MOSFET Structure for Vgs of 0 and 3 V at Vds = 30 V.

The substrate (Base current) in the SL-MOSFET structure is shown in Fig. 10.18 at a drain bias of 30 volts. The maximum value for the current is about 2x lower than for the LD-MOSFET structure with LDD-dose of 3 x 1012 cm"2. However, the impact ionization generated carrier density is very high under the gate as shown in Fig. 10.19 in the SL-MOSFET structure. At a drain bias of 30 volts with a gate bias of

260


3 volts, the generated carrier density at the gate edge is 1024 per cm 3 . This indicates potential stability problems for the SL-MOSFET structure.

Fig. 10.18 Substrate (P-base) current in the SL-MOSFET Structure at Vds = 30 V.

Fig. 10.19 Hot-carrier generation in the SL-MOSFET Structure at Vgs = 3 V.


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The generation of hot electrons under the gate of the SLMOSFET structure can be suppressed by reducing the doping concentration in the transition region. A reduction of the doping concentration between the P+ regions allows depletion of the transition region at lower drain bias voltages resulting in a lower electric field under the gate. This in turn produces much less impact ionization induced hot carriers under the gate electrode. Unfortunately, a reduction of the doping concentration in the transition region produces a reduction in the compression current which degrades the maximum output power for the device. In order to demonstrate the above trade-off between hot carrier stability and output power capability of the SL-MOSFET structure, simulations were performed for the structure shown in Fig. 7.2 with a reduction in transition region doping concentration by a factor of 2x. The performance of this structure, called SLMOS7, is described below.

Fig. 10.20 Output Characteristics for the SLMOS7 Structure.

The output characteristics of the SLMOS7 structure obtained by two-dimensional numerical simulations are shown in Fig. 10.20 together with the load-line used for extraction of its RF performance. When compared with the previous SLMOS1 structure, the compression current is found to be reduced by a factor of 2x. The transconductance for the

262


SLMOS7 structure was found to be the same as that for the SLMOS1 structure until the on-set of current compression.

Fig. 10.21 RF Performance of the SLMOS7 structure.

Fig. 10.22 RF Output Power for the SLMOS7 structure.


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The RF performance was extracted for the SLMOS7 structure using the previously described procedure. The RF power gain and current gain are shown in Fig. 10.21 as a function of frequency. When compared with the SLMOS1 structure, the power gain is reduced by about 3 dB. The impact of the reduced transition doping on the RF output power is shown in Fig. 10.22. The output power is slightly reduced at higher frequencies. The biggest impact of the reduced transition doping is a reduction of the maximum RF output power from 1 W/mm for the SLMOS1 structure to 0.5 W/mm due to its smaller compression current. In order to assess the impact of the reduced transition region doping on the stability of the device, a three dimensional view of the electric field distribution for the SLMOS7 structure is shown in Fig. 10.23 at a drain bias of 30 volts at the quiescent gate bias of 3.5 volts. It can be seen that electric field is significantly reduced under the gate electrode when compared with the SLMOS1 structure.

Fig. 10.23 Three-dimensional Electric Field distribution for the SL-MOSFET

The substrate (Base current) in the SLMOS7 structure is shown in Fig. 10.24 at a drain bias of 30 volts. The maximum value for the current is equal to that observed for the LD-MOSFET structure with LDD-dose of 3 x 1012 cm'2. When compared with the SLMOS 1 structure,

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the impact ionization generated carrier density is greatly (107 x) reduced in the SLMOS7 structure as shown in Fig. 10.25. This improved immunity to hot electron induced drift in SL-MOSFET structures has been experimentally confirmed with drain current drift of less than 2 percent over a 20 year time span under quiescent operating conditions.

Fig. 10.24 Substrate (P-base) current in the SLMOS7 Structure at Vds = 30 V.

Fig. 10.25 Hot-carrier generation in the SLMOS7 and SLMOS1 Structures under the Gate Electrode.


10.5 Planar SL-MOSFET Structure

Fig. 10.26(a) Three-dimensional Electric Field distribution for the Planar SL-MOSFET Structure at Vds = 30 V for Vgs = 0 V.

Fig. 10.26(b) Three-dimensional Electric Field distribution for the Planar SL-MOSFET Structure at Vds = 30 V for Vgs = 2.5 V.

265

266


In Chapter 8, it was demonstrated that the planar SL-MOSFET structure offers excellent linearity with very high compression current and RF output power. It also has a low output capacitance which is favorable for RF performance. In this section, the electric field distribution in this structure and the generation of hot carriers due to impact ionization under quiescent bias conditions (Vgs = 2.5 V; Vds = 30 V) are examined to determine their impact on device stability. Three dimensional views of the electric field distribution for the SL-MOSFET structure are shown in Fig. 10.26 at a drain bias of 30 volts for the case of gate biases of 0 and 2.5 volts. It can be seen that electric field becomes smaller, especially at the center of the gate, when the device is operating at the quiescent gate bias of 2.5 volts. The reduction of the electric field can be seen more clearly in the one-dimensional plot, shown in Fig. 10.27, taken along the x-direction along the mesa surface.

Fig. 10.27 Electric Field Profile for the Planar SL-MOSFET Structure

The substrate (Base current) in the SL-MOSFET structure is shown in Fig. 10.28 at a drain bias of 30 volts. The maximum value for the current is about 3x lower than for the LD-MOSFET structure with LDD-dose of 3 x 1012 cm"2. However, the impact ionization generated carrier density is very high under the gate as shown in Fig. 10.29 in the


267

planar SL-MOSFET structure. At a drain bias of 30 volts with a gate bias of 2.5 volts, the generated carrier density at the gate edge is 1026 per cm3. This indicates potential stability problems for the structure.

Fig. 10.28 Substrate current in the Planar SL-MOSFET Structure at Vds = 30 V.

Fig. 10.29 Hot-carrier generation in the Planar SL-MOSFET Structure at Vgs = 2.5 V.

268


The generation of hot electrons under the gate of the planar SLMOSFET structure can be suppressed by reducing the doping concentration in the transition region. A reduction of the doping concentration between the P+ regions allows depletion of the transition region at lower drain bias voltages resulting in a lower electric field under the gate. This in turn produces much less impact ionization induced hot carriers under the gate electrode. However, a reduction of the doping concentration in the transition produces a reduction in the compression current which degrades the maximum output power for the device. hi order to demonstrate the above trade-off between hot carrier stability and output power capability of the planar SL-MOSFET structure, simulations were performed for the structure shown in Fig. 8.1 with a reduction in transition region doping concentration by a factor of 2x. The performance of this structure, called SLMOS8, is described below.

Fig. 10.30 Output Characteristics for the Planar SLMOS8 Structure.

The output characteristics of the SLMOS8 structure obtained by two-dimensional numerical simulations are shown in Fig. 10.30 together with the load-line used for extraction of its RF performance. When compared with the previous SLMOS3 structure, the compression current


269

is found to be reduced by a factor of 1.5x. The transconductance for the SLMOS8 structure was found to be the same as that for the SLM0S3 structure until the on-set of current compression.

Fig. 10.31 RF Performance of the SLMOS 8 structure.

Fig. 10.32 RF Output Power for the SLMOS8 structure.

270


The RF performance was extracted for the SLMOS8 structure using the previously described procedure. The RF power gain and current gain are shown in Fig. 10.21 as a function of frequency. When compared with the SLMOS3 structure, the power gain is reduced by about 2 dB at 1-2 GHz. The impact of the reduced transition doping on the RF output power is shown in Fig. 10.32. The output power is slightly reduced at higher frequencies. The biggest impact of the reduced transition doping is a reduction of the maximum RF output power from 0.9 W/mm for the SLMOS3 structure to 0.6 W/mm due to its smaller compression current. In order to assess the impact of the reduced transition region doping on the stability of the device, a three dimensional view of the electric field distribution for the SLMOS8 structure is shown in Fig. 10.33 at a drain bias of 30 volts at the quiescent gate bias of 3.5 volts. It can be seen that electric field is significantly reduced under the gate electrode when compared with the SLMOS3 structure.

Fig. 10.33 Three-dimensional Electric Field distribution for the Planar SLMOS8 Structure at Vds = 30 V for Vgs = 3.5 V.

The substrate (Base current) in the SLMOS8 structure is shown in Fig. 10.34 at a drain bias of 30 volts. The maximum value for the current is lOx lower than that observed for the LD-MOSFET structure


271

with LDD-dose of 3 x 1012 cm"2. The impact ionization generated carrier density is also greatly (107 x) reduced as shown in Fig. 10.35 in the SLMOS8 structure.

Fig. 10.34 Substrate (P-base) current in the Planar SLMOS8 Structure at Vds = 30 V.

Fig. 10.35 Hot-carrier generation in the Planar SL-MOSFET Structures at Vgs = 3.5 V under the Gate Electrode.

272


10.6 Hot-Carrier Injection Conclusions The hot-carrier induced 'drift' in the characteristics of LD-MOSFET structures under quiescent bias operating conditions has been a serious concern for the cellular power amplifier manufacturers. The first generation of LD-MOSFET products were found to exhibit a drift in the drain current at the quiescent operating point by more than 10 percent for a 20 year time span. Successive generations (now at the sixth for some companies) of LD-MOSFET products have been developed with the objective of reducing the drift in the drain current at the quiescent operating point to less than 3 percent over a 20 year time span. Any competing RF power transistor technology must deliver similar or better stability in performance in order to displace the LD-MOSFET structure in the RF base station power amplifier applications. In this chapter, the physics of the hot electron induced instability has been described. As in the case of short-channel MOSFET structures used in VLSI chips, it has been shown that the instability in the LDMOSFET structures is dependent on high electric fields at the vicinity of the gate electrode because this results in the generation of the hot electrons close to the gate oxide interface. In the case of the LDMOSFET structure, the hot carrier induced instability can be reduced by using a smaller dose in the LDD-region. This moves the peak in the electric field away from the gate edge and towards the drain side. However, the smaller LDD-dose has the detrimental effect of increasing the device resistance and reducing the compression current. This results in a reduction in the maximum RF output power per mm of gate width. For the new super-linear MOSFET structures introduced in this book, the drift instability can also be induced by the generation of hot carriers in the vicinity of the gate region. Although the GD-MOSFET structure has been shown to exhibit excellent linearity and very high maximum RF output power capability, it has been demonstrated in this chapter that a very high concentration of hot carriers are generated close to the gate under quiescent operating conditions. This implies that the GD-MOSFET structure will be prone to drift instability problems. In contrast to the GD-MOSFET structure, it has been shown that the electric field at the gate is reduced by the P+ shielding region incorporated into the SL-MOSFET structure. (This is applicable to both the device with source electrode in a deep trench region for chargecoupling purposes and to the planar structure.) The degree of shielding by the P+ region depends on the doping concentration in the transition


273

region. A lower doping concentration provides stronger shielding resulting in a lower electric field at the gate electrode and much less hot carrier density under quiescent operating conditions. This has been experimentally demonstrated in SL-MOSFET structures with drain current variations projected to be less than 2 percent over a 20 year time span under quiescent operating conditions. The SL-MOSFET technology is therefore suitable as a replacement for the LD-MOSFET technology.

274


References 1

M-L. Chen, C-W Leung, W.T. Cochran, W. Jungling, C. Dziuba, and T. Yang, "Suppression of Hot-Carrier Effects in Submicrometer CMOS Technology", IEEE Transactions on Electron Devices, Vol. ED-35, pp. 2210-2220, 1988. 2 J.J. Sanchez, K.K. Hsueh, and T.A. DeMassa, "Drain-Engineered HotElectron-Resistant Devices Structures: A Review", IEEE Transactions on Electron Devices, Vol. ED-36, pp. 1125-1132, 1989. 3 G. Cao, S.K. Manhas, E.M.S. Narayanan, M.M. De Souza, and D. Hinchley, "Comparative study of Drift Region Designs in RF LDMOSFETs", IEEE Transactions on Electron Devices, Vol. ED-51, pp. 1296-1303, 2004. 4 S. Tam, P-K Ko, C. Hu, and R.S. Muller, "Correlation between Substrate and Gate Currents in MOSFETs", IEEE Transactions on Electron Devices, Vol. ED-29, pp. 1740-1744, 1982.

Chapter 11

Synopsis

A new power MOSFET concept has been introduced in this book. Unlike prior MOSFETs which operate by pinch-off of the inversion layer in the channel, the new concept is based upon retaining the channel in the linear mode of operation and relying upon current saturation by utilizing the velocity-field curve for silicon. Analytical formulations have been provided in chapter 3 that enable an accurate description of the currentvoltage characteristics obtained in devices with this new mode of operation. It has been shown that the new mode of operation allows current saturation while retaining a linear relationship between the output drain current and the input gate voltage. Such characteristics are ideal for amplification of RF and audio signals without distortion. In subsequent chapters of this book, many novel device structures were described that allow physical realization of the proposed super-linear MOSFET behavior. With the aid of two-dimensional numerical simulations, it was demonstrated that it is indeed possible to observe the super-linear output and transfer characteristics. In this chapter, the performance of these devices is compared and contrasted with that for the LD-MOSFET structure. Before doing so, the physics underlying super-linear operation is confirmed in the first section by examination of the potential distribution for one structure as an example. 11.1 Super-Linear Physics The super-linear mode of operation for the MOSFET structure relies up on maintaining the channel in the linear regime of operation even for large drain bias voltages. In addition, the electric field in the drift region must increase to the level at which electron velocity saturation is achieved. Although this is applicable for all the novel structures (the CCMOSFET, the GD-MOSFET, the SL-MOSFET, the Planar SL-MOSFET 275

276


and the DT-MOSFET) that have been discussed in previous chapters, the super-linear physics will be confirmed using the GD-MOSFET structure, that was described in chapter 6, as a representative example. The GD-MOSFET structure is shown in Fig. 6.17. In order to demonstrate the physics underlying the super-linear mode of operation, it is instructive and sufficient to examine the drain current-voltage relationship for one gate bias voltage. Since the RF performance for the structure was obtained under the quiescent gate bias voltage of 4 volts, this value was also chosen to illustrate the device physics in this section. As already shown in Fig. 6.23, the drain current increases linearly for drain voltages below 2 volts and undergoes saturation at about 5-10 volts.

Fig. 11.1 Electric Field distribution for the GD-MOSFET Structure at Vgs = 4 V for various values for Vds.

The development of the electric field in the drift region at the quiescent gate bias of 4 volts is shown in Fig. 11.1 at the middle (x=0.85 microns) of the mesa region in the GD-MOSFET structure. It can be seen that the electric field in the drift region increases to above 5 x 104 V/cm at a drain bias of between 5 and 10 volts. The onset of velocity saturation

Synopsis

277

for electrons in silicon occurs at this range of electric fields1. Once the drain voltage exceeds 15 volts, the electric field in the drift region remains at about 1.5-1.7 x 105 V/cm. This is sufficient to transport electrons at their saturated drift velocity without significant impact ionization in the drift region.

Fig. 11.2 Electron Drift Velocity in the GD-MOSFET Structure at Vgs = 4 V for various values for Vds.

In order to confirm the transport of electrons under the velocity saturation mode, the electron velocity was extracted at various drain bias voltages at a gate bias of 4 volts. It can be seen from Fig. 11.2 that electron transport occurs below the velocity saturation range when the drain bias is less than 3 volts. At a drain bias of 5 volts, the electron velocity reaches its saturated value of 1 xlO7 cm2/Vs at the top of the mesa region. When the drain voltage exceeds 5 volts, the electron transport in the drift region occurs at this saturated drift velocity. Thus, the electron velocity shown in Fig. 11.2 is consistent with the onset of drain current saturation at a drain bias of between 5 and 10 volts. This confirms that the drain current saturation behavior shown in the output characteristics (see Fig. 6.23) is due to the transport of electrons along

278


the velocity saturation curve rather than the channel pinch-off mode typical of previous MOSFET structures. A further confirmation of the super-linear physics can be obtained by observation of the potential distribution within the device structure. This is necessary to establish that the channel is indeed operating in the linear regime even at large drain bias voltages. The potential distribution in the GD-MOSFET structure along the trench sidewall is shown in Fig. 11.3.

Fig. 11.3(a) Potential distribution in the GD-MOSFET Structure at Vgs = 4 V for various values for V,js.

The potential distribution for the entire drift region from the top of the GD-MOSFET structure to 6 microns is shown in Fig. 11.3 (a). The linear variation of the potential with distance is indicative of the relatively uniform electric field distribution in the drift region achieved by the combination of the charge-coupling with the source electrode in the trench and the graded doping concentration in the mesa region. The distance from the surface at which the potential becomes constant for any given drain bias case is indicative of the extension of the depletion region. The edge of the gate is located at a depth of 0.4 microns as indicated in the figure.

Synopsis

279

Fig. 11.3(b) Potential distribution in the GD-MOSFET Structure at Vgs = 4 V for various values for Vds.

The potential in the vicinity of the channel is shown in Fig. 11.3(b) to a depth of 0.4 microns from the surface. In the GD-MOSFET structure, the junction between the P-base region and the N-drift region is located at a depth of 0.3 microns (see Fig. 6.19). Thus, the channel in the GD-MOSFET extends from a depth of 0.1 microns to a depth of 0.3 microns. From the potential plot in Fig. 11.3(b), it is observed that the potential at the edge of the channel at y=0.3 microns is 1.7 volts at a drain bias of 5 volts, while it has a value of 0.5 volts at the other edge of the channel at y=0.1 microns. This voltage difference in insufficient to put the channel into velocity saturation. Even when the drain bias increases to 70 volts, the potential at y=0.3 microns is only 2 volts and the voltage across the channel is inadequate to produce velocity saturation. Thus, the channel operates in the linear regime while the device exhibits current saturation. In conclusion, detailed analysis of the physics of operation of the GD-MOSFET structure by examination of the electric field and potential distribution confirms that the proposed super-linear mode of operation for MOSFET structures can be realized in physical devices by appropriate structural design. This phenomenon is also observed in the

280


other device structures described in earlier chapters that exhibit superlinear output and transfer characteristics. Thus, the super-linear physics proposed in chapter 3 is a new mode of operation for MOSFET structures that is generally applicable to vertical and lateral devices, as long as the device structure is capable of maintaining the channel in the linear domain of operation while obtaining sufficiently high electric fields in a concatenated drift region to produce electron drift velocity saturation. 11.2 Comparison of Device Model with Simulations In chapter 3, an analytical expression for the RF power gain was derived based up on the equivalent circuit for the MOSFET shown in Fig. 3.8. It is interesting to compare the gain as predicted by this simple equation with the gain obtained via the numerical simulations.

Fig. 11.4 RF Power Gain for the SLMOS1 Structure (Analytical Model versus Simulations).

Synopsis

281

Fig. 11.5 RF Power Gain for the SLMOS3 Structure (Analytical Model versus Simulations).

In Fig. 11.4, the RF power gain obtained using the model derived in chapter 3 is compared with the RF gain obtained by using the twodimensional numerical simulations for the SLMOS1 structure. For the model, a transconductance of 70 mS/mm was used and an output capacitance (Cds) pf 0.3 pF/mm was used to obtain a very good match with the simulated gain curve. After taking into consideration the fact that the output capacitance for the device is non-linear as shown in chapter 7, the agreement between the model and the simulated graph is remarkably good. Similarly, in Fig. 11.5, the RF power gain obtained using the model derived in chapter 3 is compared with the RF gain obtained by using the two-dimensional numerical simulations for the planar SLMOS3 structure. For the model, a transconductance of 80 mS/mm was used and an output capacitance (Cas) of 0.05 pF/mm was used to obtain a very good match with the simulated gain curve. After taking into consideration the fact that the output capacitance for the device is non-linear as shown in chapter 7, the agreement between the model and the simulated graph is again remarkably good. This indicates that the models described in chapter 3 can be quite useful for the analysis

282


of the RF power MOSFETs described in this book before resorting to extensive numerical simulations. 11.3 Comparison of Silicon RF MOSFET Device Structures Structure LDMOSln LDMOS6n VDMQS1 GDMOS3 CCMQS1 SLMQS1 SLMOS3 SLMOS7 SLMOS8 DTFET1

Ron/mm gm/nim Cgs/mm (fl) (mS) (pF) 60 30 1.2 27 30 1.3 20 55 3.75 32 55 0.16 18 46 0.18 20 80 0.77 28 80 0.73 33 75 0.85 37 ~ 80 ~ 0.7 9 110 1.15

CJmm C g< j/mm (pF) (pF) 0.25 0.01 0.30 0.024 0.42 0.02 0.075 3x10 5 0.30 ~~0.003 0.50 0.002 0.05 0.003 0.47 0.001 0.05 0.001 0.5 0.02

Table 11.1 Comparison of Electrical Parameters for MOSFET Structures with 500 Angstrom Gate Oxide.

In the previous chapter of the book, many novel devices that exhibit super-linear characteristics have been described in addition to the conventional LD-MOSFET and VD-MOSFET structures. In this section, the electrical performance of these devices will be summarized and the performance of the various devices will be contrasted with each other to provide a better perspective. In order to make this comparison, the key electrical parameters for the various MOSFET structures are summarized in Table 11.1 for devices modeled with 500 angstrom gate oxide. In comparing these parameters, it is important to keep in mind that the LDMOSFET and the GD-MOSFET structures had one channel per cell during the simulation while the rest of the structures had two channels per cell during the simulations. The transconductance of the GDMOSFET structure can be seen to be 65 percent larger than for the LDMOSFET structure. This is due to the shorter channel length for the GDMOSFET structure where the channel is shielded from reach-through during blocking the drain voltage. The SL-MOSFET structure exhibits

Synopsis

283

30 percent larger transconductance than the LD-MOSFET structure for the same reason even after account for the two channels per cell. The DT-MOSFET structure has the highest transconductance among the structures with a value of 83 percent greater than for the LD-MOSFET structure due to its short channel length. The input capacitance (Cgs) is relatively high for the VDMOSFET structure resulting in degradation of its high frequency performance. The input capacitance for the SL-MOSFET and DTMOSFET structures is about one-third that for the LD-MOSFET structure after taking into account the presence of the two channels in these structures. The GD-MOSFET structures have 7.5x lower input capacitance when compared with the LD-MOSFET structure. This lower input capacitances result in superior gain at high frequencies. The SLMOSFET and GD-MOSFET structures have extremely low feed-back capacitances (Cga) making them well suited for amplifier designs requiring low (IMD) distortion products. The planar SL-MOSFET structures (SLMOS3 and SLMOS8) have remarkably low output capacitances (CdS) which is favorable for producing higher power gain at high frequencies and for increasing the maximum operating frequency (see Fig. 3.25). Structure LDMOS8n VDMOS3 GDMOS4 SLMOS2 SLMOS4 DTFET2

Ron/mm gm/min (fl) (mS) 57 50 19 UP 17 90 19 " 170 28 160 8 200

Cgs/mm (pF) 2.4 6.05 0.29 1.40 0.98 2.00

Cds/mm (pF) 0.25 0.40 0.30 0.45 0.05 0.50

Cgd/mm (pF) 0.01 0.02 0.003 0.002 ~ 0.003 0.02

Table 11.2 Comparison of Electrical Parameters for MOSFETs with 250 Angstrom Gate Oxide.

The key electrical parameters for the various MOSFET structures are summarized in Table 11.2 for devices modeled with 250 angstrom gate oxide. As expected, the transonductance and input capacitance increase by a factor of approximately 2x for each structure. This is a favorable trade-off in terms of getting larger power gain at high

284


frequencies because the power gain varies as the square of the transconductance and is inversely proportional to the input capacitance (see Eq. [3.19]). There is no impact of the thinner gate oxide on the output and feedback capacitances.

Structure I

G^ I G^ I

ft

(lGHz) (2GHz) (dB) (dB) (GHz) LDMOSln 12.5 4.0 1.1 LDMOS6n 15.5 10 2.0 VDMOS1 13.5 6.0 1.3 GDMOS3 25 20 4.2 GDMOS2~ 21 16 " 4.2 SLMOsT~ 20 14 ~ 3.0 SLMOS3 24 20.5 5.5 SLMOS7 18 ~ 10.5 ~ 2.0 SLMOS8~ 22 14 4.5 DTFET1 20 13 2.5

I

f^

I P ^

(GHz) 2.6 4.5 3A 9.5 7.0 5.5 12 4.2 12 5.0

(W/mm) 0.27 0.945 1.06 0.69 1.0 1.0 0.90 0.50 0.60 24

Table 11.3 Comparison of RF Performance for MOSFETs with 500 Angstrom Gate Oxide.

The RF performance of the power MOSFETs is compared in Table 11.3 for devices modeled with gate oxide thickness of 500 angstroms. Enhancement in the RF performance can be obtained for the LD-MOSFET structure by increasing the dose in the LDD-region. However, as pointed out in Chapter 11, this degrades the hot-electron induced instability due to the larger electric field in the vicinity of the gate. In contrast to the LD-MOSFET and VD-MOSFET structures, the super-linear devices offer much higher gain. The planar SL-MOSFET structure (SLMOS3) has the best maximum operating frequency because of its very low output capacitance. The largest output power can be obtained with the DT-MOSFET structure because of a high compression current attained by elimination of the JFET region. However, the trench gate structure utilized in this structure leads to a larger reverse transfer capacitance.

Synopsis

Structure I G^ I G^ I LDM0S8n VDM0S3 GDMQS4 SLMQS2 SLMQS4 DTFET2

285

Tt

I f^

(lGHz) (2GHz) (dB) (dB) (GHz) (GHz) 14.5 6.0 1.05 3.0 16 9.0 1.4 4J) 25 19 5.0 10.0 22.5 ~ 17 3.0 6.5 24.5 21.5 6.0 15 I 22.5 | 16 | 2.6 | 7.0

I P ^ (W/mm) 0.27 1.06 1.0 1.0 0.90 | 2.4

Table 11.4 Comparison of RF Performance for MOSFETs with 250 Angstrom Gate Oxide.

The RF performance of the power MOSFETs is compared in Table 11.4 for devices modeled with gate oxide thickness of 250 angstroms. As expected, the power gain increases by 3 dB in all instances with the reduction in gate oxide thickness by a factor of 2x. The maximum operating frequency also improves slightly. There is no change in the maximum output power because the structures with the thinner gate oxides have the same compression currents as their counterparts with the thicker gate oxides. The highest maximum operating frequency is obtained with the planar SL-MOSFET structure while the greatest output power is obtained with the DT-MOSFET structure. Its output power per mm of gate width is competitive with that reported for wide band-gap semiconductors. Operating at such high power densities requires paying careful attention to the packaging to reduce the rise in junction temperature. This is feasible by using the flipchip approach2.

11.4 Conclusions This book has described a new mode of operation of power MOSFET structures that enables obtaining a linear transfer characteristic in the current saturation mode. Many novel device structures have been proposed and analyzed to demonstrate that this super-linear mode of operation is achievable by many methods. Among these structures, the SL-MOSFET structure described in Chapter 7 has been fabricated and

286


prototypes have been made commercially available3. Since the datasheets for these devices are not readily available, selected electrical characteristics for these products are provided in the Appendix for the readers benefit. (The RF characteristics of the LD-MOSFET products are not reproduced in the appendix because their datasheets can be easily down-loaded from the websites of their manufacturers using the links in the Appendix). The output characteristics of the super-linear MOSFET devices exhibit the signature for super-linear mode of operation namely, the drain current saturates at the same drain voltage independent of the gate bias voltage. The transfer characteristics measured for these devices exhibits very good linearity after the drain current exceeds about 0.1 amperes. The SL-MOSFET products have been extensively tested against the available LD-MOSFET products. It has been found that the linearity offered by the SL-MOSFET products is approximately 10 dB superior to that for the LD-MOSFET products (i.e. the IMD3 is less than -45 dBc when compared with about -35 dBc for the typical LD-MOSFET products). This improvement has been found to be sufficient for operation of SL-MOSFET based RF power amplifiers without the need for feed-forward linearization4. A simpler and less expensive predistortion scheme is adequate with the SL-MOSFET structure to ensure the linearity requirements of 3G base station power amplifiers. The elimination of the feed-forward linearization circuitry can significantly reduce base station cost and improve the operating efficiency. Characterization of LD-MOSFET structures indicates strong memory (or dynamic non-linearity) effects. In contrast, the SL-MOSFET structures exhibit smaller memory effects4. Dynamic non-linearity leads to a broad spectral re-growth occupying several neighboring channels. It has been determined that the dynamic non-linearity in the SL-MOSFET devices can be corrected by simple pre-distortion algorithms. In future communication systems, the modulation bandwidth will increase because of greater data demands requiring wider bandwidth modulation formats. The SL-MOSFET technology is more suitable for these applications because the bandwidth enlargement factor for the SL-MOSFET devices is only 3x while that for the LD-MOSFET devices has been found to be 7x in the comparative evaluations. In addition, pulse power tests on the SL-MOSFET products have shown that they can withstand VSWR levels of 10:1 which is far superior to those (about 3:1) tolerated by LD-MOSFET products. This is a consequence of the shielding of the gate structure and the more uniform

Synopsis

287

electric field distribution within the SL-MOSFET structure. These results indicate suitability of the SL-MOSFET structure for Radar/Avionics applications. The much higher power density in the SL-MOSFET architecture is particularly attractive for this application. The high power density of the SL-MOSFET structure is due to its low on-resistance, large compression current, and small cell size when compared with LDMOSFET structures.

288


References 1

B.J. Baliga, "Power Semiconductor Devices", PWS Publishing Company, 1996. 2 B.J. Baliga, "Packaged Power Devices having Vertical Power MOSFETs Therein that are Flip-Chip Mounted to Slotted Gate Electrode Strip-Lines", U.S. Patent # 6,586,833, Issued July 1, 2003. 3 Silicon Semiconductor Corporation, 633 Davis drive, Durham, NC 27713. 4 G. Fischer and B.J. Baliga, "Super-Linear (SL) RF Power MOSFET Technology for Cellular Base Station Applications", IEEE Transactions on Microwave Theory and Techniques, (Submitted for publication).

Appendix

This appendix provides access to datasheets of RF power MOSFET products. The widely accepted technology for RF power amplifiers used in cellular base stations is the silicon LD-MOSFET structure. This device is manufactured by several companies. Datasheets for their products can be obtained by using the links provided on the next page. The SL-MOSFET technology was commercialized by Silicon Wireless Corporation (whose name has since been changed to Silicon Semiconductor Corporation). The company announced a line-up of products for 900 MHz applications. This consisted of a pre-driver (9SL2), a driver (9SL7), and an output transistor (9SL25). The last number on the name of the product indicates the super-linear power. This was defined as the RF power up to which a third-order distortion (IMD3) level of less than 45 dBc was guaranteed. In the case of the LDMOSFET products, it has been traditional to use the PldB (power level at which the power gain drops by 1 dB) power in the product nomenclature. For the SL-MOSFET products, the PldB power level is about 4 times the super-linear power. Due to changes in product focus at Silicon Semiconductor Corporation, the datasheets for the RF products are no longer available on the website. Consequently, selected data from the datasheets has been reproduced in this Appendix.

289

290


LD-MOSFET Datasheets The datasheets for LD-MOSFET can be obtained from the following websites: (1) MRF Series: www.freescale.com (2) PTF Series: www.infineon.com (3) AGR Series: www.agere.com (4) BLF Series: www.philips.com

Appendix

291

SL-MOSFET Data The datasheets for the SL-MOSFET products developed by Silicon Wireless Corporation in 2001 are no longer available at a website. Selected data for the 9SL7 product is provided for the benefit of readers.

Fig. Al RF Power Gain for 9SL7 Product measured at 900 MHz.

The RF power gain for the 9SL7 product is shown in Fig. Al at a measurement frequency of 900 MHz. The measurements were taken at several quiescent current levels to demonstrate that the gain is not sensitive to the quiescent operating point. The RF power gain drops by 1 dB at an output power level of 25-28 watts.

292


Fig. A2 Third-Order Distortion measured for the 9SL7 Product at 900 MHz.

The third-order distortion product is of dominant concern when characterizing RF power transistors. The results of two-tone RF measurements performed at 900 MHz on the 9SL7 product are shown in Fig. A2. An IMD3 level of less than -45 dBc can be obtained for the 9SL7 product for an output power level of up to 7 watts. Note that extremely low DVID3 levels (< -60 dBc) are observed when the power is backed-off to less than 3 watts. These low IMD3 levels are sufficient for operation of SL-MOSFET based RF power amplifiers without feedforward linearization.

Appendix

293

Fig. A3 Measured Efficiency for the 9SL7 Product at 900 MHz.

The RF output power efficiency for the 9SL7 product measured at 900 MHz is shown in Fig. A3. At the PldB point (25-28 watts), the efficiency is close to 50 percent, which is competitive with that obtained in LD-MOSFET products. More importantly, the efficiency for the SLMOSFET product at the super-linear 7 watt level is 24 percent. This indicates that SL-MOSFET based RF power amplifiers can achieve efficiencies in excess of 20 percent without the use of the feed-forward linearization circuitry. In contrast, the efficiency of an LD-MOSFET based RF power amplifier degrades to the 8-10 percent level due to the utilization of the feed-forward EVID correction loop.

Index

Accumulation resistance, 64, 105 Acoustical phonon scattering, 50 Adjacent channel leakage ratio, 5, 18, 190 Aluminum metallization, 75, 164, 189, 196, 221 Amplifier, 21-23 AMPS, 2-3 Analog cellular system, 2-3 Analog pre-distortion, 29 Angular frequency, 43 Avalanche, 55 Avalanche energy, 116 Avionics, 103, 116, 142, 154, 178, 210, 234, 241, 287

Cascade, 25 CC-MOSFET, 127, 282 CDMA, 2, 4 Cell pitch, 64, 74, 76, 93, 106107, 131-132, 165-166, 172, 197-198, 204, 212, 222-223, 287 Cell structure, 72-73, 104, 128, 194, 220 Cellular spectrum, 177, 210, 234 Channel density, 64, 66, 185, 197 Channel length, 37,44, 59, 64, 67, 71, 73-74, 77, 103, 105-106, 109, 111, 131-132, 134, 138, 146, 157, 162-163, 165, 168170, 174, 187, 195-197,200201, 203, 205, 213, 221-222, 225-226, 228, 230, 238, 282283 Channel resistance, 36, 64, 74, 106, 131, 165, 197, 222 Channel pinch-off, 38, 74, 105, 111, 278 Channel temperature, 91, 118, 182-184, 210, 235 Channel width, 37, 51 Charge-coupling, 52, 65-66, 127, 130, 132, 136, 145, 149, 161, 164-166, 169, 171, 189, 193, 219-220, 225-227, 241, 272,278

Baliga's figure of merit, 127 Bandwidth, 31, 286 Base station, 7-8, 12, 34, 71, 191, 286 Beryllium oxide, 117, 179, 182 Bipolar transistors, 71, 103, 243 Blocking characteristics, 77, 109, 134, 146, 169, 200, 225 Boltzmann's constant, 245 Boundary condition, 77 Breakdown voltage, 34, 77, 8081, 103, 110, 120, 127, 130, 132, 134, 145, 164, 166, 168, 195-196, 198, 200, 225, 249 Burn-in, 71, 243 295

296


Charge trapping, 245 Choke, 13 Class A, B, AB amplifiers, 2123, 28, 73, 254 Class A mode, 85, 114, 140, 153, 176, 207, 232, 245, 254 Compressive characteristics, 29 Coulombic scattering, 50 Counter doping, 166, 197 Current compression, 14, 16, 19, 82, 95, 97, 113, 139, 150151, 156-158, 168, 174, 185, 187-188, 199, 205, 212-213, 216, 230, 237-239, 241, 245, 249, 256, 261, 263, 268-270, 272, 284, 287 Current density, 105, 130, 156, 163-164, 195, 212, 221, 235 Current distribution, 81, 105, 111,136,172,203,228 Current gain, 20, 43,45-47, 5961, 63, 67, 86-87, 100, 114-115, 124-125, 140-141, 153, 157, 176-177, 188, 208-209, 214216, 232-233, 239-240, 262263, 269-270, 284 Current pinch-off, 83 Current spreading, 65 Cutoff frequency, 20, 44, 86, 114, 141, 153, 177, 208, 234, 284 Datasheets, 30, 83-84, 190, 286, 289 Delay lines, 27-28 Depletion capacitance, 48 Depletion width, 65, 114, 166, 197 Depletion region, 55, 74, 131132, 147, 165,169-171, 175,

193, 202, 207, 222, 225-226, 228, 247, 261, 268, 278 Device model, 42, 44, 280 Dielectric constant, 36, 51 Digital cellular system, 2, 4 Digital pre-distortion, 30 Distortion, 17-18, 48, 55, 89, 92, 118, 140, 176, 180, 182-183, 190, 207, 275, 283, 289, 292 D-MOSFET, 34, 48, 64-65 DoCoMo, 5 Donors, 50 Doping gradient, 224 Doping profile, 35, 65, 76-77, 108, 132-133, 144-145, 167168, 198-200, 223-225 Double-diffusion, 34, 67, 103, 162 Drain capacitance, 44-45, 84, 113 Drift, 71-73, 92-93, 264, 272 Drift region, 34-35, 65-66, 106, 127, 172, 179, 183, 189, 202203, 205 Drift region doping, 34 Drift region thickness, 34 Drift phenomenon, 73, 93, 272 Drift resistance, 65, 74, 106, 131, 137, 165, 197, 204, 222, 229, 245 Drift velocity, 56 Drive-in cycle, 168, 195, 200 Driver stage, 25, 289 DSP, 8-9, 29 DT-MOSFET, 219, 282-285 EDGE, 4, 6-7 Edge termination, 34, 104, 107, 130, 164, 189, 195-196, 201, 221

Index

Efficiency, 22-24, 31,71, 243, 293 Electric field, 52 Electric field profile, 67, 78-79, 94, 96, 110, 135, 147, 202, 226227, 246-247, 252-253, 255256, 258-259, 263, 265-266, 276 Electromigration, 75, 105, 130, 164, 196, 221 Electron mobility, 50, 56, 66 Electron temperature, 245 Electron velocity, 51-52 Embedded electrode, 127, 129 Epitaxial layer, 73, 104, 132, Equivalent circuit, 42,44, 48, 72, 84 Error amplifier, 27-28 Expansive characteristics, 29 Faraday shield, 92-94, 96-97, 176, 207 Feedback, 26, 48, 176, 207 Feed-back capacitance, 48-49, 62, 207 Feed-forward linearization, 2627, 31, 191, 286, 292-293 Field oxide, 164 Field plate, 95, 104, 130, 164, 189, 196, 201 Field ring, 104, 130, 164, 196, 201 First generation network, 2 Fixed oxide charge, 36 Flange, 88-89, 118, 179, 182, 210,235 Flip-chip, 58, 143, 164, 179, 182-184, 189, 195, 210-211, 221, 235-236, 285 Frequency response, 86

297

Gallium arsenide, 71, 243 Gate capacitance, 36, 43 Gate edge, 245 Gate length, 76, 106 Gate oxide, 39, 51, 54, 60,7173, 76, 80, 83, 93, 98, 111, 170, 195, 198, 203, 207, 212, 214, 217,221,223,226-227,229, 234, 237-239, 244-245, 249, 272, 282-285 Gate pad, 176, 189-190, 207 Gate resistance, 105, 130 Gate signal, 85 Gate width, 64, 197 GD-MOSFET, 144, 219-221, 229, 238, 255-257, 272, 276280, 282-285 Gold bumps, 189 Gold metallization, 75, 164, 196, 221 GPRS, 4 Graded doping profile, 128, 136, 144, 148, 161, 163, 166, 168, 220-221, 224, 278 Gradual channel approximation, 37, 55 GSM, 4, 6-7 HCI degradation, 170, 201, 226, 228, 243 Heat sink, 76, 89, 117, 181-184 Hot carrier, 93, 171, 202, 227, 259, 261, 268 Hot carrier generation, 217, 244, 248, 254, 256-257, 260, 264, 266-267,271 Hot electrons, 49, 71, 73, 80, 170,172, 201, 203, 226-228, 244-245, 247, 249, 252, 261, 264, 268, 272, 284

298


Hydrogen, 245 Ideal specific on-resistance, 35, 65, 137, 149 IMD-3, 18, 292 Impact ionization, 49, 80-81, 138, 144, 148-149, 171, 183, 203, 205, 228, 244-245, 248, 254, 256, 259, 261, 264, 266, 268 Inelastic collisions, 245 Input capacitance, 43, 48, 54, 59-60, 83, 99, 114, 124, 129, 140, 152, 157, 175, 187, 207, 214, 231-232, 238, 282-283 Input impedance, 103 Interdigitated metal, 75 Interface charge, 36 Inter-modulation distortion, 18, 190,283,289,292 Intrinsic carrier concentration, 36 Inversion, 35, 74, 80, 105, 110, 131, 136, 148, 164-165, 172, 196, 203, 220-222, 229 Inversion layer charge, 35, 51 Inversion layer mobility, 36, 40, 57, 64, 74, 88, 106, 131, 143, 165, 178-179, 184, 197, 210211, 222, 235-236 Ion implantation, 67, 73, 104, 129, 163, 168, 194-195, 200, 216, 221, 225 IS-95 B, 7 Isothermal simulations, 88, 117, 143, 210, 235 JFET resistance, 65, 106

LD-MOSFET, 66-67, 71, 243254, 259, 272, 282-285 LDD dose, 79-81, 245, 247-251, 254, 256, 259,284 Leakage current, 36, 44 Lightly doped drain, 67, 72-74, 78-79, 89, 245-246, 249 Linear regime, 37, 49-50, 131, 219, 275 Linearity, 71, 103, 138, 140, 150, 153, 156, 174, 176, 185, 188, 207-208, 212, 214, 232, 238, 241, 243, 256, 286 Linearization, 7, 26-27, 31 Load resistance, 42, 44-45, 56 Load-line, 15-16, 19, 22, 24, 8586, 115, 140-141, 152, 154, 176, 187, 207-208, 210, 214, 232233, 235-236, 238-239, 250251,254,261,268 Matching network, 25 Maximum operating frequency, 20, 44, 62, 86, 114, 125, 141, 153, 158, 177, 188, 208, 216, 234, 239, 283-285 Maximum output power, 21, 88, 100, 116, 125, 142, 154, 178, 188, 210, 216, 235, 239,251, 261, 263, 270, 272, 284-285 Mean free path, 245 Memory effect, 190, 286 Mesa, 130, 136-137, 140, 146147, 152, 162-165, 168, 170172, 175, 183, 219-220, 222, 226, 228-229, 259, 266, 276277 Mesa width, 131-132, 164, 166

Index

MESFET, 71 Migration path, 5 Mobility-inversion, 36, 40, 57, 64 Mobility-bulk, 50, 56, 74 MOSFET, 33 Multi-carrier power amplifier, 7-8 Multi-stage power amplifier, 25-26 Negative feedback, 48 Non-isothermal simulation, 76, 89, 118, 166, 180, 182 On-resistance, 15, 19, 64, 68, 80-81, 111, 121, 131, 137, 148, 165-166, 172, 196-197, 203, 222, 229, 249, 272, 282-283, 287 On-resistance-specific, 35, 66, 149, 166, 172, 204, 229 Optical phonon scattering, 50 Output capacitance, 19, 44-45, 60, 62, 83-84, 99, 113-114, 124, 139-140, 151-152, 157, 175, 187, 193, 206-208, 214, 231232, 238, 281-283 Output characteristics, 15, 4041, 53, 55, 58, 81-82, 88, 92, 98, 111-112, 117-118, 123, 137, 141-143, 149, 155, 173, 178, 182, 185, 190, 204, 210-212, 229, 235-237, 249, 261, 268, 277 Output power, 43, 46-47, 53, 60-64, 86-87, 95, 114, 116, 140, 142,153-154, 158, 176, 188189, 208-210, 214-216, 232,

299

234, 23 8-241, 250-252, 262263, 268-270, 291 Output resistance, 53, 55-56, 81, 138, 150, 183, 204, 229, 282 Output stage, 25, 289 Oxide capacitance, 35, 106 Oxide traps, 73, 244 Package, 67, 73, 76, 88, 116117,143,179,182-184,190,

211,236,241,285

Parallel plane breakdown voltage, 201 Parallel-plane junction, 104 Parasitic bipolar transistor, 105, 164, 194-195, 221 PDC, 5 Pinch-off MOSFET physics, 37 Planar gate, 104, 162, 193-194, 216,230,232,234 Polycide gate, 93, 105, 130, 163, 195, 221 Polysilicon, 128-130, 132, 163, 166, 221 Polysilicon gate, 103, 105 Polysilicon window, 64 Potential contours, 78, 93-94, 96, 109, 121, 134, 146, 169, 200-201, 225 Potential distribution, 278-279 Power amplifier, 7-8, 10, 13, 25, 176-177, 191, 207, 243, 254, 272, 286, 292-293 Power amplifier revenue, 9 Power density, 285, 287 Power dissipation, 89, 179 Power gain, 19, 43, 45-47, 5961, 63, 67, 86-87, 100, 114-115, 124-125, 140-141, 153, 157,

300


176-177, 188, 208-209, 214216, 232-233, 239-240, 251, 262-263, 269-270, 280-281, 284-285, 291 Pre-distorter, 30-31 Pre-distortion, 28, 286 Pre-driver stage, 25, 289 Pulse-power, 103, 116, 142, 154, 178, 210, 234, 241, 286 Quasi-saturation, 15, 19 Quiescent bias, 14-15, 72-73, 80, 86, 114, 153, 176, 188, 207, 214, 217, 232, 238, 243-245, 247-251, 254, 256, 259, 263264, 266, 272-273, 276, 291 Radar, 287 Radio, 7 Reach-through, 55, 74, 165 Reach-through breakdown, 105106, 131-132, 145-146, 148, 165, 169, 171-172, 196, 200203, 220, 225-226, 228, 282 Receiver, 7 Refill, 132 Reliability, 72, 91-92, 119, 120, 147, 226 Resistivity, 65, 165, 197, 222 Retrograded profile, 166, 168, 197-198, 223 RESURF, 67, 73, 79 Reverse transfer capacitance, 48, 83-84, 93, 95, 97, 99, 113114, 120-121, 124, 139-140, 151-152, 157, 175-176, 187, 195, 197, 206-207, 214, 231232, 238, 282-283 Rugged, 116

Safe-operating-area, 116 Saturated drain current, 37, 51, 88 Saturated electron velocity, 4950, 57, 248, 277 Second generation network, 4 Self-aligned, 163, 195 Shielding, 44, 140, 152, 169, 170, 175, 193, 196,200-202, 207, 216, 221-223, 225-227, 232, 272, 282, 286 Silicon dioxide, 36, 51, 244 Sinker, 66, 72-74, 76, 81 SL-MOSFET, 161, 193, 229230, 232, 234-235, 241, 244, 258-272, 280-285 Source pad, 190 Source inductance, 67, 182 Source wire-bonds, 73, 182 Specific gate capacitance, 36, 51, 64, 74, 106, 131, 165, 197, 222 Specific on-resistance, 35, 127, 137, 149, 172, 204, 222, 229 Spectral re-growth, 286 Split gate structure, 120 Square-law behavior, 16, 37, 74, 82, 99, 105, 111, 122, 250 Steady-state response, 72, 85-86 Submicron transistor, 49 Substrate current, 249, 253-254, 256-257, 259-260, 263-264, 266-267, 270-271 Substrate resistance, 75, 106, 131-132, 166,197, 222 Substrate thickness, 91-92 SL-MOSFET, 161,193, 219 Super-linear MOSFET physics, 49,275-280

Index

Super linear mode, 131, 137138, 149, 156, 165, 170, 174, 185, 190, 193, 195-196, 201, 204, 212, 219, 226, 230, 237, 279, 286 Super-junctions, 65 Switching speed, 103 TDMA, 2, 4, 7 Temperature contours, 89-90, 119,180-183 Temperature dependence, 4041, 56, 58 Temperature distribution, 89, 180 Temperature profile, 91,119, 181-183 Temporal response, 84 Temporal simulations, 87, 114, 140, 153, 177, 188, 207-209, 214, 232-234, 238 Terraced gate structure, 120-121 Thermal effects, 88, 117, 143, 154, 178, 210, 235 Thermal gradient, 89,91,118119, 179, 181, 184 Thermal impedance, 58, 71, 9192, 143, 179-180, 182, 211 Thermal resistance, 117, 166 Thermal runaway, 118, 180 Thermo-compression, 190 Thin gate oxide, 39, 54, 60, 98, 122, 155, 185, 211, 236, 239240, 285 Third generation network, 5 Threshold voltage, 35-36, 40, 49, 51, 57, 64, 71, 73-74, 80, 83, 88, 92, 99, 106, 110, 112, 122, 131, 138, 143, 148, 150, 156157, 165, 174, 185, 187, 197,

301

203, 205, 211-212, 221-222, 229-230, 236-237, 244 Transceiver, 7, 12 Transconductance, 37-39, 4143, 45, 51, 54, 58-59, 67, 82-83, 88, 99, 111, 113-114, 117,122, 124, 131, 138-139,143, 150151, 156, 165, 174, 178,185187, 196, 205-206, 211-213, 230-231, 236-238, 261, 269, 281-283 Transfer characteristics, 14, 17, 82, 88, 95, 97-98, 111-112, 117, 123, 138, 143, 150, 155, 173174, 178, 185-186, 190-191, 204-205, 210, 212-213, 230, 236-237,286 Transient response, 72, 85-86, 140, 153, 177, 208, 214, 232, 239 Transition region, 163, 165, 168, 172, 193-198, 201-204, 222, 261, 263, 268, 270, 272 Transition resistance, 166, 197, 199 Transition voltage, 53 Transmitter, 7 Traps, 244-245 Trench, 128-129, 134, 136, 144, 146, 152, 161, 163, 170, 219, 221, 229, 232, 241, 256 Trench gate, 219, 241, 284 Trench depth, 131-132, 164, 166, 188, 222-223 Trench electrode, 128, 140, 152, 162-163, 175, 207, 216, 219220, 232, 241, 272, 278 Trench oxide, 134, 147, 171, 226 Trench width, 132, 166, 223

302


UMTS, 5 VD-MOSFET, 103, 282-285 Velocity-field curve, 50, 275 Velocity saturation mode, 193, 219,277 VSWR, 286 Wafer breakage, 92 Wafer thinning, 92, 182 W-CDMA, 2, 6-7 Wide band-gap semiconductors, 285 Wire bonds, 116, 182 Wireless evolution, 6 Work function, 36

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