Handbook of RF and Microwave Power Amplifiers Whether you are an RF transistor designer, an amplifier designer, or a system designer, this is your one-stop guide to RF and microwave transistor power amplifiers. A team of expert authors brings you up-to-speed on every topic, including: r r r r r r r
devices (Si LDMOS and VDMOS, GaAs FETs, GaN HEMTs); circuit and amplifier design (discrete, hybrid and monolithic); CAD; thermal design; reliability; system applications/requirements for RF and microwave transistor amplifiers; amplifier measurements.
Covering state-of-the-art developments, and emphasizing practical communications applications, this is your complete professional reference on the subject. John Walker is currently European Sales Manager at Integra Technologies, Inc. He received his Ph.D. from the University of Leeds in 1976 and has since held various industry positions, including Microwave Hybrids Manager at Thorn-EMI Electronics and RF Division Manager at Semelab. He is the Editor and Coauthor of the books High Power GaAs FET Amplifiers and Classic Works in RF Engineering. He is a Fellow of the IEE.
The Cambridge RF and Microwave Engineering Series Series Editor Steve C. Cripps, Distinguished Research Professor, Cardiff University Peter Aaen, Jaime Pl´a and John Wood, Modeling and Characterization of RF and Microwave Power FETs Dominique Schreurs, M´airt´ın O’Droma, Anthony A. Goacher, and Michael Gadringer, RF Amplifier Behavioral Modeling Fan Yang and Yahya Rahmat-Samii, Electromagnetic Band Gap Structures in Antenna Engineering Enrico Rubiola, Phase Noise and Frequency Stability in Oscillators Earl McCune, Practical Digital Wireless Signals Stepan Lucyszyn. Advanced RF MEMS Patrick Roblin, Nonlinear FR Circuits and the Large-Signal Network Analyzer Matthias Rudolph, Christian Fager, and David E. Root, Nonlinear Transistor Model Parameter Extraction Techniques Forthcoming Sorin Voinigescu, High-Frequency Integrated Circuits David E. Root, Jason Horn, and Jan Verspecht, X-Parameters Richard Carter, Theory and Design of Microwave Tubes Anh-Vu H. Pham, Morgan J. Chen, and Kunia Aihara, LCP for Microwave Packages and Modules Nuno Borges Carvalho and Dominique Scheurs, Microwave and Wireless Measurement Techniques
Handbook of RF and Microwave Power Amplifiers Edited by
JOHN WALKER Integra Technologies, Inc.
CAMBRIDGE UNIVERSITY PRESS
Cambridge, New York, Melbourne, Madrid, Cape Town, Singapore, S˜ao Paulo, Delhi, Tokyo, Mexico City Cambridge University Press The Edinburgh Building, Cambridge CB2 8RU, UK Published in the United States of America by Cambridge University Press, New York www.cambridge.org Information on this title: www.cambridge.org/9780521760102 C Cambridge University Press 2012
This publication is in copyright. Subject to statutory exception and to the provisions of relevant collective licensing agreements, no reproduction of any part may take place without the written permission of Cambridge University Press. First published 2012 Printed in the United Kingdom at the University Press, Cambridge A catalog record for this publication is available from the British Library ISBN 978-0-521-76010-2 Hardback The technical descriptions and procedures in this book have been developed with the greatest of care; however, they are provided as is, without warranty of any kind. The author and publisher of the book make no warranties, expressed or implied, that the equations, programs, and procedures in this book are free of error, or are consistent with any particular standard of merchantability, or will meet your requirements for any particular application. They should not be relied upon for solving a problem whose incorrect solution could result in injury to a person or loss of property. Cambridge University Press has no responsibility for the persistence or accuracy of URLs for external or third-party internet websites referred to in this publication, and does not guarantee that any content on such websites is, or will remain, accurate or appropriate.
Contents
List of contributors Preface 1
Silicon LDMOS and VDMOS transistors: physics, design, and technology
page xiv xv 1
Wayne Burger and Christopher P. Dragon
2
1.1
Technology overview 1.1.1 Introduction/history 1.2 LDMOS and VDMOS construction 1.2.1 LDMOS 1.2.2 VDMOS 1.3 Device physics 1.3.1 Current transport 1.3.2 Behavior of parasitic elements/models 1.3.3 BVDSS , RDSon , HCI boundaries 1.3.4 Snapback/ruggedness 1.3.5 Operating voltage considerations 1.4 Design/layout 1.4.1 Top-down finger layout 1.4.2 Bond pad manifolds 1.4.3 Metal design – electromigration 1.4.4 Thermal 1.4.5 Operating voltage considerations 1.4.6 Frequency considerations: gate length, gate width, resistors 1.4.7 HVICs References
1 1 2 2 8 10 10 12 17 22 26 27 27 29 30 32 34 36 37 39
GaAs FETs – physics, design, and models
42
Rob Davis
2.1
Introduction 2.1.1 Properties of GaAs and related compounds 2.1.2 The Schottky barrier gate and the MESFET 2.1.3 The Pf 2 limit 2.1.4 Types of GaAs FET
42 43 45 45 46
vi
Contents
2.2
2.3
2.4
2.5
2.6
3
Power device physics 2.2.1 The device I–V characteristic and loadline 2.2.2 The dynamic I–V characteristic 2.2.3 The consequences of trapping effects 2.2.4 Device breakdown 2.2.5 Breakdown mechanisms and optimisation 2.2.6 Comments on GaAs FET breakdown ratings 2.2.7 The FET equivalent circuit 2.2.8 Device gain and figures of merit Device design 2.3.1 Power device design 2.3.2 FET channel and recess design 2.3.3 Power cell design 2.3.4 Power cell combination 2.3.5 Thermal design Device fabrication 2.4.1 Overview 2.4.2 Key process steps 2.4.3 Low-cost GaAs device fabrication 2.4.4 Packaging Models 2.5.1 Device models 2.5.2 Small-signal models 2.5.3 Large signal models 2.5.4 Load-pull Concluding remarks References
Wide band gap transistors – SiC and GaN – physics, design and models
51 51 53 54 57 58 59 60 61 63 63 63 67 71 72 74 74 75 81 81 84 84 84 85 89 90 91
103
Robert J. Trew
3.1 3.2
3.3 3.4 3.5
3.6
Introduction Background 3.2.1 SiC transistors 3.2.2 AlGaN/GaN transistors Material parameters Transistor amplifier operating principles Device design and RF performance 3.5.1 4H-SiC MESFET amplifier 3.5.2 AlGaN/GaN HFET amplifier Transistor DC and large-signal RF models 3.6.1 Equivalent circuit transistor models 3.6.2 Physics-based large-signal transistor models
103 105 106 108 111 115 118 120 123 125 125 128
Contents
3.7
3.8
4
Large-signal effects 3.7.1 Space charge limited current transport 3.7.2 Nonlinear source and drain resistance 3.7.3 Gate leakage 3.7.4 Reliability and time-dependent performance degradation Summary References
Amplifier classes, A–S
vii
130 130 133 144 146 152 153 159
Steve C. Cripps
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12
5
Introduction Active device models Class A Class AB and Class B Class C Class F Class J Inverted modes, inverted Class F Class E Class S Multimodes Conclusions References
159 161 162 164 171 173 176 179 181 183 184 186 186
Computer-aided design of power amplifiers
188
Stephen Maas
5.1 5.2
5.3
5.4
Introduction Methods of analysis 5.2.1 Linear analysis 5.2.2 Harmonic-balance analysis 5.2.3 Time-domain analysis 5.2.4 Applications of analytical methods Passive circuit structures and simulation accuracy 5.3.1 Scattering parameter models 5.3.2 Closed-form models 5.3.3 Models from EM simulation 5.3.4 Database models 5.3.5 Parasitic extraction Solid-state device models 5.4.1 Power device models 5.4.2 Modeling cell interconnections in large devices 5.4.3 Thermal effects in device models
188 188 188 193 202 205 205 206 208 210 212 212 213 213 213 214
viii
Contents
5.5
5.6
6
Special aspects of power-amplifier modeling 5.5.1 Loss in circuit metalizations 5.5.2 Loss in circuit components 5.5.3 Bond wires Practical aspects of nonlinear circuit simulation 5.6.1 Convergence difficulties 5.6.2 SPICE models in harmonic-balance analysis 5.6.3 Problem size minimization and solution optimization 5.6.4 Numerical considerations 5.6.5 Design flow References
Practical HF/VHF/UHF RF power amplifier realization
216 217 219 219 221 221 226 226 227 228 230 232
Daniel P. Myer
6.1 6.2 6.3
6.4
6.5
Introduction RF power amplifier markets The realization process 6.3.1 RFPA qualitative specification delineation 6.3.2 RFPA specifications, generic list and quantification guidelines 6.3.3 Specification/hardware realization RFPA system level design overview 6.4.1 RF power amplifier module design overview 6.4.2 RF power transistor device selection process guidelines 6.4.3 RF power transistor bias/thermal tracking networks 6.4.4 RF input/output coupling/decoupling networks 6.4.5 Power transistor impedance matching 6.4.6 Feedback networks 6.4.7 Thermal management Hypothetical amplifier design example 6.5.1 Hypothetical application example overview 6.5.2 Amplifier qualitative specification delineation 6.5.3 Amplifier specification quantification 6.5.4 Amplifier hardware design/realization 6.6.5 RF transistor selection 6.5.6 Gate bias/temperature tracking/compensation network 6.5.7 Input/output RF/DC coupling/decoupling networks 6.5.8 Input/output impedance matching networks 6.5.9 Feedback network 6.5.10 Test setup configuration/analysis 6.5.11 Physical RFPA module construction 6.5.12 RFPA module test results 6.5.13 Beyond the test data References
232 232 233 234 236 241 242 243 246 249 250 250 251 251 252 252 252 253 254 255 257 259 259 267 268 271 273 281 283
Contents
7
Microwave hybrid amplifier realization
ix
284
Dominic FitzPatrick
7.1 7.2 7.3
7.4
7.5
7.6 7.7
8
Introduction Printed circuit boards Housing 7.3.1 Materials 7.3.2 Sealing and hermeticity 7.3.3 Construction 7.3.4 Thermal issues and heat sinking 7.3.5 RF connections Components 7.4.1 Passive – lumped components 7.4.2 Passive – distributed components 7.4.3 Transistors Amplifier design 7.5.1 Topologies 7.5.2 Matching and stability 7.5.3 Internally matched device amplifiers 7.5.4 Combining 7.5.5 Module size/system integration Biasing and control 7.6.1 Control and interfacing Tuning techniques References
Monolithic power amplifiers
284 285 293 294 294 299 305 311 315 315 323 331 333 333 336 343 344 344 345 352 353 355 357
Inder J. Bahl
8.1
8.2
8.3
8.4
Overview of MMIC power amplifiers 8.1.1 Brief history of MMIC power amplifiers 8.1.2 Advantages of monolithic power amplifiers Monolithic IC technology 8.2.1 MMIC fabrication 8.2.2 MMIC substrates 8.2.3 MMIC active devices 8.2.4 MMIC matching elements MMIC design methodology 8.3.1 CAD tools 8.3.2 Design procedure 8.3.3 EM simulators MMIC PA summary and examples 8.4.1 Narrowband power amplifier 8.4.2 Broadband power amplifiers 8.4.3 Ultra broadband power amplifiers 8.4.4 High-power amplifiers
357 357 358 359 360 361 361 362 370 370 371 372 372 374 376 377 381
x
Contents
8.5
8.6
9
8.4.5 Millimeter-wave 2.4W PA 8.4.6 Wireless 3W power amplifier 8.4.7 High-voltage monolithic PAs Packaging of MMIC PAs 8.5.1 Ceramic packages 8.5.2 Plastic packages 8.5.3 Package assembly MMIC power amplifier characterization References
RF power amplifier thermal design
386 386 387 389 390 394 396 401 406 411
Mali Mahalingam
9.1 9.2
9.3 9.4 9.5 9.6
10
Why thermal design deserves careful attention? RFPA thermal design – basics 9.2.1 RFPA thermal design in a typical portable product 9.2.2 RFPA thermal design in a typical radio base station 9.2.3 Basic heat transfer processes and their role in an RFPA thermal performance Thermo-physical properties of materials in an RFPA Tools to characterize and predict the thermal performance of RFPAs RFPA thermal design and management – advanced RFPA thermal design – trends and prognostication References
Reliability
411 413 413 416 419 423 427 432 440 442 446
Bill Roesch
10.1 Introduction 10.2 Vocabulary and definitions (units, goals, and strategy) 10.2.1 Reliability goals 10.2.2 Semiconductor reliability strategy 10.3 Failure criteria 10.4 Failure modes 10.5 Failure mechanisms 10.5.1 Metalization 10.5.2 Dielectric 10.5.3 Bulk substrate material 10.5.4 Schottky gate FET failure causes 10.6 Failure distributions 10.7 Acceleration factors 10.7.1 Thermal acceleration 10.7.2 Current acceleration 10.7.3 Voltage acceleration factors 10.7.4 RF bias acceleration
446 447 448 448 449 450 451 451 453 454 454 455 458 458 462 465 472
Contents
10.8 10.9
10.10 10.11 10.12 10.13
11
Reliability predictions (MTBF, MTTF, FITs, etc.) Wear-out versus defects (acceleration versus real life) 10.9.1 Thermal excursion example no. 1. Interconnect vias 10.9.2 Thermal excursion example no. 2. Copper bump 10.9.3 Defect amplification and K factors 10.9.4 Environmental example – humidity activation energy Process effects and influence Design for reliability Historical trends and technology comparisons Summary References
Power amplifier applications
xi
473 475 475 478 482 488 492 495 501 502 505 508
Mustafa Akkul and Wolfgang B¨osch
11.1 Introduction 11.2 System design parameter tradeoffs 11.2.1 Output power–efficiency tradeoff 11.2.2 Linearity, modulation scheme, and crest factor 11.3 System level linearization techniques 11.3.1 Introduction to linearization techniques 11.3.2 Digital baseband predistortion 11.3.3 Memory effect compensation 11.3.4 Impact on power efficiency 11.4 Wireless communication power amplifiers 11.4.1 Mobile radio communication today 11.4.2 System level and power amplifier requirements 11.4.3 Power amplifier design outline 11.4.4 Doherty amplifier for efficient base stations 11.5 Military power amplifiers 11.5.1 Radar Tx/Rx modules 11.5.2 EW applications 11.5.3 Anti-IED applications 11.6 In-phase power combining techniques 11.6.1 Wilkinson power combiners 11.6.2 Gysel combiner 11.7 Quadrature-phase power combining – balanced amplifiers 11.7.1 Branch-line quadrature hybrid [19] 11.7.2 Lange coupler 11.8 Anti-phase power combining – push–pull amplifiers 11.8.1 Coupled coil transformers 11.8.2 Transmission line transformers 11.8.3 RF/microwave push–pull amplifier
508 509 509 512 514 514 514 517 517 519 519 522 523 527 530 530 534 538 538 538 542 544 547 549 552 553 554 557
xii
12
Contents
11.9 Doherty combining 11.10 Conclusions References
559 567 568
Amplifier measurements
570
Michael G. Hiebel
12.1 Introduction 12.2 Power measurements 12.2.1 Typical power sensor principles 12.2.2 Typical sources of measurement uncertainties 12.2.3 High-power RF measurements and directional power 12.2.4 Power measurements using a spectrum analyzer 12.3 S-parameter measurements 12.3.1 The concept of S-parameters 12.3.2 Scalar network analyzers and their limitations 12.3.3 Vector network analyzers 12.3.4 Introduction to system error correction 12.3.5 Calibration with different connector types 12.3.6 Calibration with PCBs, test fixtures, and wafer probers 12.3.7 Calibration consideration for high-power setups 12.3.8 Residual errors and measurement uncertainties 12.4 Further linear measurements 12.4.1 Amplifier gain definitions 12.4.2 Efficiency factor 12.4.3 Linear distortion, phase and group delay measurement 12.4.4 Linear stability considerations 12.4.5 Mixed-mode S-parameters 12.5 Nonlinear measurements 12.5.1 Inter modulation distortion (IMD) and harmonic distortion (HMD) 12.5.2 Compression point 12.5.3 Large-signal network analysis 12.5.4 Load- and source-pull measurements 12.5.5 Hot S-parameters 12.6 Modulated measurements 12.6.1 Crest factor and CCDF 12.6.2 Adjacent channel power ratio (ACPR) 12.6.3 Noise–power ratio (NPR) 12.6.4 Error vector magnitude (EVM) and constellation diagram 12.6.5 AM/AM and AM/PM measurements 12.6.6 Memory effects
570 570 570 574 576 579 580 580 582 586 588 589 593 596 598 599 599 602 603 605 608 611 611 615 616 619 622 623 624 625 630 630 632 632
Contents
xiii
12.6.7 Pulsed measurements 12.6.8 Bit error ratio (BER) and symbol error ratio (SER) 12.7 Noise measurements 12.7.1 Amplifier noise factor and noise figure 12.7.2 Noise figure measurement 12.7.3 Noise parameters 12.8 Conclusions References
633 635 636 637 637 640 641 642
About the authors Index
644 651
Contributors
Mustafa Akkul ASELSAN A.S.
Dominic FitzPatrick PoweRFul Microwave
Inder Bahl Cobham Sensor Systems
Michael Hiebel Rohde & Schwarz GmbH & Co. KG.
¨ Wolfgang Bosch Graz University of Technology
Stephen Maas AWR, Inc.
Wayne Burger Freescale Semiconductor
Mali Mahalingam Freescale Semiconductor
Steve Cripps Cardiff University
Daniel P. Myer Communication Power Corporation (CPC)
Rob Davis RFMD
Bill Roesch TriQuint Semiconductor
Chris Dragon Freescale Semiconductor
R.J. Trew North Carolina State University
Preface
In 1989, I was responsible for organizing a workshop at the European Microwave Conference on High-Power Solid State Amplifiers. This workshop proved popular and so Artech House asked me to persuade the speakers to turn their material into a form suitable for publication, the result was the book entitled “High-Power GaAs FET Amplifiers” of which I was editor and a coauthor. That book is of course not just out of print but also largely out of date. This book adopts the same philosophy as the previous one with chapters on device technology, amplifier design, CAD, thermal design, reliability, measurements, and applications – but with a completely different set of authors and with every chapter completely re-written to bring the content up to date. The political, economic and technical landscape has changed almost beyond recognition in the intervening two decades. In the 1980s most RF and microwave engineers were working in military electronics, defense spending was largely responsible for all the technical advances, and there were no mobile phones! Compare that with the situation now where there are probably just as many RF and microwave engineers working on commercial applications as there are in military electronics, commercial applications often drive technical advances, and most households will have not just one but several mobile phones – and it is the mobile phone industry that has largely been responsible for this shift toward commercial applications. However, there is one consequence of this sea-change in the industrial and technical environment which has had a profound knock-on effect when it comes to writing a book such as this. Now the commercial pressures of shortest possible time to market and minimum cost, etc. are so intense that any prospective author working in this field has to be prepared to commit endless hours of their own rather than their employer’s time to the task. I want to publicly acknowledge my deep debt of gratitude to all the authors in this book for making that commitment and hence making this book possible. John Walker
The “Handbook” is a comprehensive reference for RF and microwave power amplifiers. It includes both theory and practice as well as a variety of different applications. Often overlooked supporting topics such as CAD, thermal design, and reliability are treated in depth. John Walker has put together an outstanding team of authors, each of whom is well qualified to address his topic. Finally, I like the way it is organized with separate chapters for three types of RF-power transistors (silicon, GaAs, and GaN/SiC) and separate chapters for amplifiers of different frequency types (HF/VHF/UHF, microwave, and IC). Fritz Raab, Green Mountain Radio Research Company John has successfully brought together, in one book, the current knowledge from world experts actively involved with the characterisation and modelling of devices together with those developing and designing RF and microwave power amplifiers. The timely publication of this book will serve as a useful reference source for engineers working in both the commercial and military market sectors. Steve Nightingale, Cobham Technical Services
1
Silicon LDMOS and VDMOS transistors Physics, design, and technology Wayne Burger and Chris Dragon Freescale Semiconductor
1.1
Technology overview
1.1.1
Introduction/history Power amplifiers are at the core of nearly all high-power (i.e., >5 W) RF applications. The application space includes cellular phone basestation transceiver systems, pulsed radar, ISM (industrial, scientific, medical), avionics, digital television broadcast, etc. This diverse and evolving RF power amplifier landscape dictates the strategy for the design, fabrication, and optimization of multiple generations of RF power devices. The RF power transistor must satisfy a broad and often conflicting set of application requirements, including but not limited to power, linearity, efficiency, gain, reliability, thermal management, bandwidth, ruggedness, digital predistortion (DPD) linearizability, and cost effectiveness. The amplifier architecture has also evolved to adapt to the everchanging system requirements, most recently with the widespread adoption of Doherty amplifiers to boost back-off efficiency in linear applications. These architectural evolutions create opportunities for further refinements in the RF power transistor to extract peak performance from the architecture. The various major market segments of the RF power market tend to embrace a dominant device technology that meets a broad range of these requirements until a new technology emerges to offer a more compelling solution. Through the late 1970s, silicon bipolar transistors were the preferred RF power device technology [1–2]. The relatively low frequencies and amplifier requirements of the era were compatible with silicon bipolar transistor technology, which was capable of providing a robust, cost-effective solution. The bipolar transistors had adequate gain and efficiency, could be readily scaled to achieve the desired power levels, and offered linearity that was consistent with the modest requirements of that era. On the other hand, power gain was relatively poor, packages with isolated flanges were expensive, thermal runaway due to the negative temperature coefficient had to be carefully managed (usually at the expense of degraded performance because of the need to incorporate ballast resistors), and the evolving and increasingly more stringent linearity and efficiency requirements were becoming difficult to design into the transistors. The limitations of the silicon bipolar transistor eventually created an opening for a new generation of transistor technology that offered superior performance without
2
Silicon LDMOS and VDMOS transistors
these limitations. The early 1980s witnessed the emergence of double diffused MOS (DMOS) transistors that were superior to silicon bipolar transistors for many highpower RF amplifier applications [3–4]. A range of factors contributed to this improved performance, starting with the improved frequency response inherent to a majority carrier device compared to the minority carrier transport in the bipolar transistor. Second, the DMOS transistor structure lends itself to high breakdown voltage designs without seriously compromising frequency performance, opening up the possibility of increasing the power supply voltage, lowering the power supply cost, and simplifying the design of ever higher power devices. Another key advantage is that MOSFETs are not susceptible to thermal runaway, due to the positive coefficient of thermal resistance [5]. The ability to design DMOS transistors with high linear efficiency has also emerged as a key factor in their widespread deployment. These topics will be explored in greater detail later in this chapter. DMOS transistor structure and fabrication technology diverged into two main subgroups depending on the direction of current flow, lateral DMOS and vertical DMOS transistors (LDMOS and VDMOS, respectively) [6–11]. Each of these variants has their strengths and weaknesses, and each has largely succeeded in finding appropriate market segments within which to flourish. The doping profile in the channel region of both transistors is formed through the overlap of lateral diffusion profiles, but LDMOS maintains the drain region and current flow laterally near the surface where it can be easily modified and optimized, making it more attractive where linear efficiency and high-frequency operation are important. VDMOS, on the other hand, can achieve excellent power density (i.e., extremely low RDSon /area) since the large drain drift region needed to sustain high breakdown voltages extends vertically below the surface. This same structure tends to limit the scaling of the gate structure, detracting from the high-frequency performance. This makes it the logical choice for applications that require very high-power density at relatively low frequencies. Comparisons between these two technologies will be explored throughout this chapter.
1.2
LDMOS and VDMOS construction
1.2.1
LDMOS Figure 1.1 shows a picture of a packaged high-power LDMOS transistor, a view of the internal construction, and a higher magnification image of the LDMOS die. Figure 1.2 shows a cross-section of a standard LDMOS die. LDMOS die are n-channel enhancement mode MOSFETs. The LDMOS transistor has a long, lightly-doped n-type drift region (hereafter referred to as the n-drift region) between the drain contact and the gate/channel of the device. The LDMOS transistor has the n-drift region oriented laterally referenced to the silicon surface, the origin of the “L” in LDMOS. The drain supply voltage to first order determines the length and doping level in the n-drift region. LDMOS devices optimized for handsets may have an n-drift length of less than 0.5 μm, while an LDMOS device designed to operate at 50 V in an industrial application may require a drift region
3
1.2 LDMOS and VDMOS construction
(a)
Figure 1.1a 2.1 GHz, 170 W LDMOS single-ended part in an air cavity package.
Ceramic substrate
Embedded capacitor Drain lead Transistors
Array of bonding-wires
Gate lead MOS capacitors 50 0m
il
Flange (b)
Figure 1.1b High-power LDMOS device with lid removed illustrating the LDMOS building
blocks, MOSCAPs, and extensive wirebond arrays in the input and output matching networks.
4
Silicon LDMOS and VDMOS transistors
ESD Protection
(c)
Gate Lead
Drain Lead
Figure 1.1c Typical layout of a 50 W LDMOS building block designed for ∼2 GHz operation.
Drain
Gate oxide gate oxide metal strap n + source
n -drift region
n + drain
Channel
p + “sinker”
PHV region p-type epitaxy
p + substrate
Source
Figure 1.2 LDMOS cross-section illustrating key features, including topside gate and drain connections and a backside source.
5–6 μm long. The vast majority of cellular infrastructure base stations are designed with a supply voltage of 28–32 V. When the transistor is turned on, the drift region simply acts as a voltage variable resistor and creates a voltage drop such that the potential in the drain region below the gate is significantly less than the applied DC bias in order to preserve the integrity of the gate oxide and ensure that HCI (hot carrier injection) is limited. Most LDMOS designs also leverage a technique termed RESURF – REduced SURface Fields [12], which relies upon a rapid two-dimensional expansion in the depletion region width with increasing drain bias that keeps the peak electric field below the critical field for impact ionization, without compromising the low drain bias RDSon of the transistor; this technique enables very high breakdown voltages while maintaining the low RDSon necessary to achieve high-power density. Unless stated otherwise, references to power
1.2 LDMOS and VDMOS construction
5
gate n-region
n + drain
n+ source VD = 0 V
5V p-type substrate
10 V 20 V 50 V
Figure 1.3 Depletion region boundaries for VDS voltages of 0, 5, 10, 20, and 50 V in an LDMOS
device.
density refer to W/mm gate periphery; with this definition, high-power density correlates with improved performance for most figures of merit. The nature of the reactive circuit elements in an RF transistor enables the peak drain voltage to reach approximately twice the drain supply voltage Vdd during class AB operation, and even higher during other modes of operation [13]. The ability to withstand these peak voltages explains why data sheets for transistors designed for 32 V Class AB operation typically specify 65 V minimum for drain-to-source breakdown voltage, BVDSS . The lightly doped n-drift region in the LDMOS device, along with the lightly doped p-epi region, are designed to deplete as the drain voltage increases, in alignment with the RESURF principle. The epi depth/doping as well as the n-drift’s depth/doping/extension must be optimized such that the peak electric field across this depletion region does not exceed critical avalanche breakdown levels during the application’s RF voltage swings. Figure 1.3 illustrates through simulation how the depletion region edge progresses through the n-drift region as the drain bias voltage is increased from 1 V to 65 V, with the gate biased at a typical voltage for Class AB operation. Since this region is the largest parasitic resistance within the transistor, it also determines the saturation current and hence power density. Keeping this resistance as low as possible while maintaining an appropriate breakdown voltage and HCI reliability is a critical part of the design tradeoff made in the LDMOS transistor design process. Proprietary techniques are employed to increase the power density without compromising BVDSS or HCI. These three parameters (BVDSS , HCI, RDSon ) define the boundary within which the transistor drain structure is optimized. The lightly doped p-type epitaxial layer is also important to achieve low drain to source capacitance, Cds , which is important to achieve good high-frequency performance. The gate of the LDMOS transistor is most commonly composed of a stack of polysilicon and a silicide (e.g., WSi, CoSi) [14–15]. While a DC current will not flow in the gate of a MOSFET, displacement current from the AC waveform will flow through the gate capacitance, resulting in an undesirable voltage drop across the width of the gate
Silicon LDMOS and VDMOS transistors
1E20 n + source Net Dopant Conc (cm –3 )
6
n + drain
1E19
1E18
p-type lateral channel diffusion
1E17 n − drift region 1E16
1E15
Figure 1.4 Lateral doping profile along the surface of an LDMOS device.
finger. The silicide lowers the gate resistance by at least an order of magnitude over that of highly doped polysilicon. In the case of WSi this can range from 10 /sq to less than 1 /sq, depending on thickness. If the gate resistance is too high, the power gain of the device will suffer. The gate length and gate oxide thickness are key in determining the frequency response of the transistor (i.e., ft , the unity current gain frequency of the transistor). Thinner gate oxides and shorter gate lengths result in a higher ft . In addition, a thinner gate oxide results in a higher device transconductance (gm ), but not necessarily higher RF power gain. This is because the thinner gate oxide also increases the input capacitance of the device which can lower gain. This is another example where design tradeoffs must be considered. The asymmetrical p-channel region of the device is one of the distinguishing features that differentiates the DMOS transistor from the standard MOSFET. For the LDMOS transistor, this region is created by using the gate to self-align a moderate dose p-type implant (referred to as the PHV implant) to the source edge of the gate of the transistor. A subsequent furnace anneal is used to laterally diffuse (the “D” in DMOS) this implant into the channel. The source-side structure is completed by the self-aligned implant and subsequent diffusion of the heavily doped n-type source/drain implant. Figure 1.4 presents the simulated profile from the source to the drain contact along the surface of the transistor, illustrating the four distinct regions of the device (n + source, PHV, n-drift, and n + drain). The result is a MOSFET with a nonuniform channel doping profile, with the source side more heavily doped than the drain side. One advantage of this is that the dopant gradient generates its own electric field which provides a small boost to the overall current transport of the device [16]. More importantly, this design allows the large supply voltages described earlier to be applied without suffering punch-through. As the
1.2 LDMOS and VDMOS construction
7
drain voltage is increased, the depletion region will spread away from the n–p junction formed by the intersection of the n-drift and PHV/p-epi regions. If that depletion region were to reach the source side of the device, the n + source to PHV junction barrier would be lowered resulting in a dramatic increase in the supply of electrons injected into the channel and swept to the drain terminal by the applied electric field. This phenomenon is referred to as punch-through, and results in a loss of control of the drain current by the gate voltage. Since the depletion region width is inversely proportional to the doping density, the growth of the depletion region into the PHV slows considerably as it moves towards the more heavily doped source side of the channel in an LDMOS device (see Figure 1.3). This preserves the high-voltage capability of the transistor. The source of the transistor is unique in an RF LDMOS device because it gets shorted to the body of the transistor. The body cannot be biased separately from the source. This is done so that the back of the wafer can be used as the grounded source in the application. Making electrical ground connection to the back of the die obviates the need for source wires to be present to make a top-side connection. By eliminating the topside source bond wires, a large amount of source inductance is eliminated, increasing the gain of the transistor. To make this backside source possible, the n + source is shorted to a heavily doped p-type region called the p+ sinker by metal 1 (typically an aluminum alloy). This metal is not contacted by a bond wire for biasing and simply acts as a means to short the pn junction between the two regions. The p+ sinker is implanted very early in the process and is thermally diffused until it meets the p+ substrate doping which is gradually diffusing upward during this thermal cycle. The p-epi must not be entirely consumed by the substrate up-diffusion because of the breakdown voltage and capacitance constraints described earlier. A balance between keeping a low-resistance path through the p+ sinker into the p+ substrate and retaining ample lightly doped p-epi for breakdown and low Cds must be struck. The wafer is then thinned through a backgrind process (to thicknesses in the 2–6 mils range) and back-metal is deposited on the wafer backside so that a good, low-resistance contact can be made between the die and package. There are two components of the device design that are located above the silicon surface: the field plate and the drain metallization. The field plate provides an extra degree of freedom within the n-drift optimization tradeoff described earlier. By placing a grounded conductor (i.e., the field plate) close to the surface of the n-drift region, the field plate can perturb the depletion region and electric fields such that a higher doping and/or shorter extension can be used for the n-drift region for a given amount of breakdown voltage and HCI. In other words, the parasitic drain resistance of the device can be lowered, the RF power density of the device can be increased, and the HCI levels in the device can be reduced if the field plate is designed correctly. Figure 1.5 is a simulation of the subsurface electric field for a device both with and without a grounded field plate, from which the peak electric field can be seen to be dramatically reduced for the device with a field plate. In addition, since this field plate is grounded, it can act as a shield between the drain metals and the gate of the transistor, reducing the feedback capacitance Cgd . The drain metallization must be designed to meet the application’s electromigration requirements. RF power devices are typically
8
Silicon LDMOS and VDMOS transistors
with shield
Lateral E-Field Magnitude (V/cm)
4.0e+05
without shield
2.0e+05
0.0e+00 n + source
channel and n − drift
Figure 1.5 Comparison of the lateral electric field magnitude with and without a field plate shield.
designed to operate at a junction temperature up to 200 ◦ C at relatively high current densities. A typical device design target might be a 100-year electromigration median time to failure (MTTF) at rated power and 200 ◦ C. This requires a very robust metallization, and is typically satisfied with a thick aluminum or gold top metal with dimensions (thickness and linewidth) that are appropriate to keep the current density low enough to meet the MTTF goals.
1.2.2
VDMOS The VDMOS transistor (Figure 1.6) shares many of the device design and operational considerations described for the LDMOS transistor. The most significant difference is that the body/substrate of the VDMOS transistor is n-type rather than p-type, and it serves as the drain of the VDMOS transistor whereas the body/substrate is the source for the LDMOS device. The n-drift region is a lightly doped n-type epitaxial layer on top of a heavily doped n-type substrate; the VDMOS epi thickness is the equivalent of the n-drift “extension” in the LDMOS device. This region is also the primary source of parasitic resistance in the VDMOS device but it extends down towards the backside of the die rather than remaining at the surface. This design allows the epi thickness to be adjusted to achieve the target breakdown voltage. For very high breakdown voltages in the 200 + V regime, this vertical design is more appropriate than the lateral design of the LDMOS transistor. VDMOS transistors suitable for RF operation at drain bias levels in excess of 100 V are now on the market [17–18], whereas 50 V is the highest drain voltage operational rating on an LDMOS transistor available today [19–21]. Increasing the drain voltage is the logical pathway to develop high-power parts with user-friendly impedance levels. This has led to a divergence in the market where these technologies
1.2 LDMOS and VDMOS construction
9
Gate
Source metal overlay
Source oxide Gate n + source
n + source p+ diffusion
Channel n-type epitaxy
n + substrate
Drain
Figure 1.6 VDMOS cross-section illustrating key features. Unlike the LDMOS structure, the gate
and source are on the topside while the drain is on the backside of the structure. Adapted from reference [25].
compete against each other, with LDMOS tending to have the highest values of gain, efficiency, and operating frequency, while the VDMOS can achieve higher power levels at higher drain bias values, but at lower frequencies. While the vertical drift region design enables higher drain voltage ratings and power capability, which are significant advantages for certain applications, this drift region design is not amenable to the incorporation of field plates; the performance gains achieved by LDMOS for the past half dozen years were enabled by the incorporation of field plates to allow for aggressive reductions in RDSon and increases in power density without compromising reliability or breakdown voltage. The vertical drift region design also leads to the backside of the device being the drain rather than source/ground terminal (the LDMOS transistor brings the source to the device backside). Since the transistor mounting flange is mechanically and electrically connected to the PA heat sink and to ground, this introduces complexity into the packaging environment for the VDMOS device compared to the LDMOS transistor. Finally, the transition of current flow from lateral to vertical induces current crowding that tends to limit performance compared to the LDMOS purely lateral transport [22].
10
Silicon LDMOS and VDMOS transistors
0.45
7.0 V
0.40
6.0 V 5.4 V
0.35
5.0 V
IDS (A)
0.30 0.25
4.4 V 0.20 4.0 V
0.15
3.4 V
0.10
3.0 V
0.05
VGS = 2.0 V
0V
0.00 0
10
20
30
40
50
60
70
80
VDS (V)
Figure 1.7 IDS -VDS family of curves for various VGS values.
1.3
Device physics
1.3.1
Current transport DMOS devices behave largely the same as standard three-terminal n-channel MOS devices with regard to transistor operation. The current-voltage response can be characterized as having cutoff, linear, and saturation regimes of operation (see Figure 1.7). Current equations for the linear and saturation regions of operation can be approximated by equations (1.1) and (1.2), respectively [23], where ID is the drain current, μS is the electron surface mobility, Cox is the gate oxide capacitance per unit area, W is the total gate width, L is the effective gate length, and VG , VT , and VD are the gate, threshold, and drain voltage, respectively. Due to the graded doping profile within the channel of the device, there is an additional electric-field induced drift current component which is not present in standard MOSFETs, providing an additional boost to the apparent mobility and gm . Note that for small drain voltages, the VD2 term can be dropped from equation (1.1), which then reduces to the familiar linear relationship between ID and VD . μs Cox W 1 2 (VG − VT )VD − VD ID = (1.1) L 2 ID =
μs Cox W (VG − VT )2 2L
(1.2)
It is worth noting that DMOS devices as commonly designed for RF operation cannot be used as four terminal devices (i.e., gate, drain, source, and body). In both LDMOS
11
1.3 Device physics
Gate
Drain
Source
Figure 1.8 Illustration of the current flow in the LDMOS structure. The current flow is lateral
across the drain and channel, and is then shunted to the source connection at the backside of the wafer.
and VDMOS devices, the body of the device is used as the source or drain, respectively. In both cases this eliminates the need for a top-side contact for all three terminals of the device (i.e., gate, source, drain). In the case of LDMOS, only the gate and drain have top-side contacts allowing for the source to remain a low-resistance, lowinductance connection (i.e., wirebonds are replaced by diffusions that electrically connect the source to the backside of the wafer, which is then connected to system ground – see Figure 1.2) which is important for RF applications. VDMOS has only gate and source top-side contacts, which has layout densification advantages, especially for very high voltage operation, as will be discussed in a later section. The drain of the VDMOS transistor is internally shorted to the substrate which, as previously described, requires an accommodation during packaging since the wafer backside cannot be mounted directly to the package flange and heat sink. The current paths for the LDMOS and VDMOS transistors are illustrated in Figures 1.8 and 1.9, respectively, but remember that current flow is the opposite of electron flow. The LDMOS device shows current beginning at the drain where a positive voltage has been applied and flowing through the lightly doped n-drift region before crossing the channel. The current then passes through the n+ source into the metal which shorts the n+ source to the p+ sinker, and then into the p+ sinker. The current then moves vertically through the silicon and out the backside of the substrate to ground. The VDMOS device has a current path which begins at the back of wafer and moves vertically to the surface, transitioning through the lightly doped drift region formed by the epitaxial layer. It then crosses the channel and exits out of the source contact terminal.
12
Silicon LDMOS and VDMOS transistors
Gate
Source metal overlay
Source oxide Gate
p + diffusion
Drain
Figure 1.9 Illustration of the current flow in the VDMOS structure. The current flow is vertical through the drain region, turning lateral across the channel and into the source.
1.3.2
Behavior of parasitic elements/models In RF power applications, the operational effectiveness (e.g., gain, power density, efficiency, etc.) of a transistor is mostly limited by its parasitic elements. It is in minimizing these elements that the true challenge of device design becomes apparent. Capacitances and resistances pose the biggest problems. Resistances are a problem because they not only dissipate energy but also limit the peak current and hence peak power capability, and contribute to an increase in the knee voltage and hence degrade the peak efficiency of the transistor. Parasitic resistances, although a necessary by-product of certain regions of the device (i.e., the n-drift region) to meet breakdown voltage and HCI reliability goals, tend to degrade the overall performance of the transistor. Many variations of the basic DMOS structure have been reported in an attempt to reduce RDSon without compromising BVDSS . Capacitances pose several problems. The most classical impact is simply to degrade the frequency response of the transistor. Equations (1.3) and (1.4) are simplified equations for fT (unity current gain frequency) and fmax (unity power gain frequency), respectively [24], where Cgs is the input capacitance, Rout is the real part of the output resistance, and Rin is the real part of the input resistance. fT =
gm 2πC gs
(1.3)
1.3 Device physics
13
1.20E-12
CDS/mm (F/mm)
1.00E-12 8.00E-13 6.00E-13 4.00E-13 2.00E-13 0.00E+00 0
10
(a)
20 VDS (V)
30
Figure 1.10a Typical drain-source capacitance (CDS ) versus voltage curve for an LDMOS device.
1.35E-12
CGS/mm (F/mm)
1.30E-12 1.25E-12 1.20E-12 1.15E-12 1.10E-12 1.05E-12 0 (b)
1
2
3
4
5
6
VGS (V)
Figure 1.10b Typical drain-source capacitance (CGS ) versus voltage curve for an LDMOS device.
f max
fT = 2
Rout Rin
(1.4)
The other impact is that many transistor capacitances are nonlinear functions of the junction voltage and therefore can result in a distortion of the signal being passed through the PA. Figure 1.10 presents input capacitance Cgs , output capacitance Cds , and feedback capacitance Cgd versus voltage curves that are representative of an LDMOS transistor, illustrating the sensitivity of the capacitances to terminal voltage. The variation of these capacitances degrades the efficiency of the input and output matching networks since the fixed value passives in these networks must be designed to operate in an environment where the capacitances being matched depend on voltage. What
Silicon LDMOS and VDMOS transistors
5.00E-14
4.00E-14 CDG/mm (F/mm)
14
3.00E-14
2.00E-14
1.00E-14
0.00E+00 0
5
10
(c)
15
20
25
30
35
VDG (V)
Figure 1.10c Typical drain-source capacitance (CGD ) versus voltage curve for an LDMOS device.
Gate
Drain RG
n+
n−
n+
p
p+
CGS
CGD
RD
CDS
RS p-epi
p + substrate
Source
Figure 1.11 Key parasitic capacitances and resistances superimposed on the LDMOS structure. The gate resistance RG is actually perpendicular to the plane of the drawn structure (i.e., into the page).
follows is a more detailed discussion on each of the key parasitic elements of DMOS transistors. Figure 1.11 shows the various parasitic resistances and capacitances in an LDMOS transistor. The drain resistance (Rd ) is largely dominated by the n-drift region and must be designed to sustain appropriate levels of breakdown voltage while minimizing HCI.
1.3 Device physics
15
1E20
Dopant Conc (cm–3)
1E19
1E18
1E17 good sinker linkage poor sinker linkage 1E16
Figure 1.12 Comparison of the vertical doping profiles through the sinker region of an LDMOS device with and without good linkage to the substrate.
This is discussed in more detail in the next section. The gate resistance (Rg ) is kept low through the use of a silicide which sits atop the polysilicon gate. The silicide provides at least an order of magnitude reduction in gate resistance over just polysilicon. Given the high-power capability of these devices, total gate widths tend to be measured in millimeters rather than microns. How this is achieved from a layout perspective is shown in a later section. The important aspect to consider is that the RF signal is traveling down long stretches of gate and therefore it must also be considered to act as a transmission line. If Rg gets too high, a voltage drop occurs along the gate width and the gain of the device becomes poor. Finally, Rs is driven primarily by the sinker region, the link to the p+ substrate, the p+ substrate resistance, and various smaller resistances associated with the die attach and metal package flange. If one were to take a vertical look at the dopant profile seen through the sinker to the substrate it would look like the solid line in Figure 1.12. A failure to form a low-resistance link between the p+ sinker and the substrate is illustrated by the dashed line in Figure 1.12, which will degrade the RF performance of the transistor. The capacitances in the LDMOS device typically have both fixed and nonlinear components. Beginning with the drain-to-source capacitance Cds , a typical Cds C–V curve is plotted in Figure 1.10a. The nonlinear nature of the curve is due to the nonlinear spreading of the depletion region into both the body and n-drift region as the drain voltage is increased (see Figure 1.3). It is affected by the dopant levels in the device as well as the shield designs which can perturb the n-drift depletions if placed close to the surface. In addition, there are fixed, voltage-invariant intermetal fringing capacitances within the device that shift the entire C–V curve up. The nonlinear nature of Cds can be a problem since voltage swings will create a range of capacitances for each RF cycle. This leads to distortion and can also become problematic for specific types of PA design such as
16
Silicon LDMOS and VDMOS transistors
envelope tracking that vary the drain voltage dynamically to adjust output power levels. Another challenge from nonlinear capacitances is the impact of the nonlinearity on the matching network design; since the matching network components are voltage invariant (inductors and MOS capacitors, typically), the instantaneous impedance transformation will vary across the RF cycle as the device intrinsic capacitance varies, resulting in compromised performance over most of the RF cycle. And finally, Cds determines, to first order, the intrinsic output impedance of the transistor; for silicon transistors in particular, this junction capacitance can lead to very low impedances that are difficult to design broadband matching networks for. The gate-to-source capacitance Cgs in the device is highly dominated by the gate oxide of the transistor. Due to the nature of all MOSFETs the Cgs C–V is highly nonlinear and shown in Figure 1.10(b). Prior to the device reaching threshold there is no inversion layer to span the channel directly below the oxide. Therefore a depletion region is created to uncover charge to balance the applied gate voltage. Once the device goes into inversion, there is an ample supply of electrons directly beneath the oxide surface on which E-field lines can terminate. The capacitance becomes much larger since it now consists of only the gate oxide rather than the gate oxide in series with a depletion capacitance; the onstate Cgs for an LDMOS device is typically two to four times larger than Cds measured at 28 V whereas for a VDMOS device the ratio is closer to unity. This nonlinear behavior of the input capacitance with voltage also creates problems with linearity in the form of phase delays from the input to the output of the device. The gate-to-drain feedback capacitance (Cgd ) has the same C–V shape as Cds but the magnitude in a typical LDMOS device is much lower – Cdg at 28 V is typically less than 5% of Cds at 28 V. The nonlinear contribution stems solely from where the n-drift region is overlapped by the gate and is therefore manipulated by the n-drift doping, the extent of the lateral diffusion of the PHV in the channel, the gate oxide, and the variation in depletion region locations with bias. There are also significant contributions to Cdg from intermetal fringing. Various shield designs have been used to conceal the gate from the drain metal and hence reduce the feedback capacitance. The shield is grounded and therefore terminates E-field lines originating with the drain. Excessive Cgd can lower power gain in the device and increase the instability. The descriptions applied to the parasitic resistances and capacitances for LDMOS also apply to the VDMOS structure. In exchange for the n-drift region becoming vertical and thereby increasing the flexibility to design for breakdown voltages of 100 V or higher, the parasitic capacitances of the VDMOS structure tend to be higher than for the equivalent power RF-LDMOS device. In addition, compared to LDMOS the VDMOS structure lends itself towards lower operational frequencies (i.e., lower gain at a given frequency). The lack of a grounded shield structure in the VDMOS device (see Figure 1.6) tends to increase Cgd , in addition to not providing the additional device design flexibility that a grounded shield layer provides (i.e., the grounded shield has enabled higher n-drift doping concentrations to increase power density without sacrificing HCI performance). There are few benign parasitic elements when considering the performance of highpower RF transistors. A robust design process based upon models that include these parasitic elements is critical to enable optimization of the design across a broad range
1.3 Device physics
17
of performance metrics. An excellent reference for the characterization and modeling of RF power devices is [25].
1.3.3
BVDSS , RDSon , HCI boundaries Breakdown voltage (BVDSS ), linear regime on-resistance (RDSon ), and HCI are three critical parameters that are traded off against one another in the pursuit of higher RF performance. Many aspects of the transistor design are constrained by these parameters and for the most part are controlled by the drain region of the device. Manipulating the drain of the device in various ways (i.e., n-drift doping, n-drift length, shield placement, and design) is collectively referred to as drain engineering. This section is devoted to this topic. Breakdown voltage between the drain and source of a MOSFET while the transistor channel is OFF (i.e., gate voltage is zero for standard LDMOS and VDMOS devices) is referred to as BVDSS . For a typical wireless base station application with the PA operating in Class AB bias, the drain DC supply voltage will be in the 26–32 V range, but the peak RF voltage which occurs on top of the DC bias will essentially be double this value. This would imply a minimum BVDSS requirement of 64 V. For this reason the data sheets typically specify 65 V minimum BVDSS for cellular infrastructure applications. This is achieved with the lightly doped n-drift region that is designed to operate in the RESURF regime. Discussion of the breakdown mechanism is required to understand how this works. The drain-source breakdown in an LDMOS or VDMOS device occurs when the electric field across the n-drain/p-source junction (the junction which is vulnerable in these devices is actually between the drain and the body of the MOSFET, but recall that the source and body are shorted so the drain-source vernacular remains accurate) exceeds the critical level required for a phenomenon known as avalanche breakdown to initiate. With any p/n junction that is reverse biased (as is the case when a positive voltage is applied to the n-type drain while the p-type source is grounded), a depletion region extends into each side of the junction creating a balance of charge. There are no free-flowing electrons in the n-type depletion region or free-flowing holes in the ptype depletion region, hence they are depleted of mobile carriers. Without these mobile carriers, the dopant atoms within the silicon lattice present a fixed charge (i.e., positive charge in the n-type depletion region and negative charge in the p-type region). These fixed charges set up an electric field across the depletion regions. The integrated fixed charge in the depletion regions on either side of the junction is always equal. If the drainsource voltage is increased, the depletion regions grow uncovering additional fixed charge which in-turn results in a larger electric field. How large the depletion region is depends on the level of dopant in that region. If the region is highly doped, the depletion region is quite small since a very small depleted area uncovers a large amount of fixed charge (recall that the fixed charge comes from the dopant in the lattice). If the region is lightly doped the opposite is true: the depletion region must extend a large distance to expose the necessary fixed charge. This concept is important in that for a given applied voltage, the peak value of the electric field that extends over a long distance is lower
18
Silicon LDMOS and VDMOS transistors
than one which occurs over a very narrow region. It is the peak value of the electric field which incites avalanche [26]. Within the depletion region electron-hole pairs are constantly being generated that are swept from the depletion regions by the electric field created by the applied voltage, resulting in the leakage current in the device. As the voltage across the junction increases, the peak electric field will eventually reach a value where the spontaneously generated electron-hole pairs gain sufficient energy from the field to break electron bonds during collisions with the lattice atoms, leading to the generation of new electron-hole pairs. This newly formed electron–hole pair repeats the pattern; it is easy to see how the process can lead to an exponential increase in current for a sufficiently large applied voltage. This process is termed avalanche breakdown. The resultant electrical curve is shown in Figure 1.7. In this example it is clear that an exponential growth in current is occurring at ∼72 V. Designing for high BVDSS is most easily achieved by using a light dopant level on both sides of the drain–source (body) junction. In both LDMOS and VDMOS cases, the body is already lightly doped. The drain however has many design elements which can be adjusted to achieve the desired breakdown voltage. The most obvious given the discussion thus far is to simply use a lightly doped drain. However, if the n-drain region is short and shallow, then the depletion region will very quickly consume the entire n-area and hit the n+ drain contact area, pinning the lateral growth of the depletion region. This means that length and depth of the n-drift region become additional parameters which must be carefully designed. The result is a two-dimensional depletion region spread (RESURF) that does not occur in simple one-dimensional junction theory [12]. Referring to Figure 1.3, the progression of depletion laterally from the channel and vertically from the body causes a reduction in field strength as the overall electric field is now split into vectors which are orthogonal to one another. A full discussion of RESURF is beyond the scope of this chapter but the typical pattern in lateral electric field across the n-drift region is seen in Figure 1.6 with two electric field peaks: one near the channel and one near the n+ drain contact area. To maximize BVDSS the n-drift doping, depth, and length are designed so that these peaks are nearly equal. Another element of drain engineering design is the use of shields or field plates above the n-drift region (see Figure 1.2). The concept behind field plates is to provide an additional degree of freedom to modify the field distributions within this critical region of the device. If a grounded conductive layer is placed close enough to the surface of the device it creates a surface for electric field lines to terminate upon; this structure is commonly referred to as a field plate. The field plate serves several purposes. One is to reduce capacitive coupling between the drain and gate which improves highfrequency performance. It should be noted that early devices placed a grounded metal shield between the drain and gate to reduce capacitance, but far enough from the silicon surface to have minimal effect on the electric field distribution in the drain. Over the past ten years, LDMOS device design has evolved to place the field plate closer to the silicon surface to intentionally alter the field distribution in the drain region. In this regime, the coupling between the drain and the field plate enhances the RESURF behavior in the device, allowing a higher dopant level to be used to achieve a given BVDSS .
1.3 Device physics
19
The higher dopant level increases the power density, improving device performance. In addition, the device engineer can place the shield only above the portion of the n-drift region that is needed and can also control how close it is by choosing the thickness of the dielectric deposited below the shield, providing additional flexibility in the device design. It is important to note that the field plate integrates easily into the lateral structure of the LDMOS device; the VDMOS structure is inherently incompatible with field plate structures. Looking at a typical family of ID –VD curves for various VG values there are two general regions of MOSFET operation as discussed earlier: linear and saturation. In the linear region of operation the MOSFET current versus voltage curves exhibit a slope whose reciprocal is referred to as RDSon . The steeper this slope is then the larger the RF signal can swing before becoming limited by the capability of the transistor. A lower RDSon value typically translates into higher power density and higher efficiency and is considered a critical design component in any LDMOS or VDMOS device. The desire is to keep RDSon as low as possible. The largest contributor to RDSon is the n-drift region where the breakdown voltage discussion above illustrates the need for a lightly doped (more resistive) design. This is one of the fundamental tradeoffs to be made when designing an RF PA transistor, and it is of little surprise that the vast majority of the device design activity is devoted to drain engineering precisely this particular tradeoff. This drove the need for shields/field plates in LDMOS and experimentation with a variety of doping techniques in the n-drift area. Other contributors to RDSon include the source resistance components of the LDMOS and VDMOS devices already covered as well as the channel resistance contribution which is negligible if designed properly. LDMOS devices rely on the lateral diffusion of a p-type implant to create the channel doping profile. This results in the preferred higher doping at the source end of the channel and lower doping at the drain end of the channel (see Section 1.3). However, if the lateral diffusion is too great due to either a thermal cycle which is too aggressive or a gate length which is too short, the p-type dopant will reach the n-drift region and overcompensate. This results in the p-type dopant counter-doping the n-type dopant and that area of overcompensation becomes a p-type region. If there is no n-type region to link up to the drain edge of the gate (see Figure 1.2) then the small p-type region becomes a large parasitic resistance, RDSon increases dramatically, and power capability is lost in the device. This makes controlling gate length and lateral diffusion thermal cycles a critical manufacturing concern for LDMOS. The VDMOS transistor has similar considerations in terms of controlling the lateral diffusion of the PHV implant. HCI in MOSFET transistors must be considered with respect to the impact it will have in RF PA applications. HCI is the third major consideration (the other two being BVDSS and RDSon ). There are a variety of metrics available to characterize HCI, including threshold voltage shift, transconductance degradation, etc. The two critical parameters impacted by HCI for RF power devices are shifts in RDSon and bias current (commonly referred to as IDQ ). For a thorough understanding of these effects a discussion of the device physics involved is required. Two things must be present for HCI to occur: an electric field strong enough to impart significant energy to the carriers making them “hot” and the carriers themselves
Silicon LDMOS and VDMOS transistors
1.00E+00 1.00E-01 1.00E-02 1.00E-03 1.00E+04 IDS (A)
20
1.00E-05 1.00E-06
VDS = 0.1 V
1.00E-07
VDS = 28 V
1.00E-08 1.00E-09 1.00E-10 1.00E-11 0
0.5
1
1.5
2
2.5
3
VGS (V)
Figure 1.13 Sub-threshold ID –VD curves for an LDMOS device (VD = 0.1 V, VD = 28 V).
(i.e., electrons). In the BVDSS discussion the concept of RESURF was used to illustrate that there are two electric field peaks within the n-drift region of an LDMOS device. The electric field peak at the drain edge of the gate is the one which results in HCI if it gets too strong. Under normal transistor operation, electrons are flowing across the channel with the aid of a lateral electric field. As with avalanche breakdown, the field can become strong enough that the electrons are accelerated to a point where collisions with other electron-hole pairs or the silicon lattice occur. While the field is not strong enough to begin the avalanche process, the carriers traveling near the surface can get misdirected during a collision and end up being injected into the gate oxide. How deep into the oxide they are injected depends on the energy of the electron and the available energy states in the oxide. Once injected this electron acts as a fixed negative charge which induces a positive charge in the channel below it. Depending on exactly where the electron is injected there are two different device degradation mechanisms which can occur. If the electron is injected directly over the channel of the device (see Figure 1.2) the impact is on the bias current or IDQ under RF operation. Looking at subthreshold curves of a typical LDMOS device (Figure 1.13) taken with a drain voltage of 0.1 V and 28 V there is an observed shift in the curves. The threshold voltage (VT ) is lower when 28 V is applied to the drain. This is due to a short-channel effect within the field-effect transistor (FET). At the surface of the channel a larger depletion region extends into the channel when larger drain voltages are applied. This uncovers fixed negative charge in the channel. When a positive gate voltage is applied, it is looking to generate an equivalent
1.3 Device physics
21
negative charge in the channel. This leads to inversion as electrons are created at the channel surface and the threshold voltage has been exceeded. If the larger depletion region has already created some negative charge for the gate electric field to terminate upon, then less inversion electrons are required to create a completely turned-on channel. The result is a lower VT . PA applications will set the DC bias using the 28 V (in this example) drain supply by increasing the gate voltage above VT until the desired IDQ is reached. If HCI is occurring during normal device operation, electrons above the channel will induce a positive charge essentially reversing the increased depletion spread caused by the 28 V. This increases VT and starts to de-bias the part (i.e., IDQ decreases). Over time as more electrons are injected, the device slowly loses its bias and the part will no longer operate as needed in the PA. If the electron is injected above the n-drift region, the induced positive charge simply increases RDSon which, as stated earlier, will result in decreased power capability. Robustness to HCI must be designed into the transistor and characterization performed to define acceptable levels. Characterization of HCI affects is performed through stress testing at the DC bias which will be applied to the device in the application. A typical base station PA could require a drain voltage of 32 V and an IDQ of 4 mA/mm of total gate width. A drain voltage of 32 V is applied and then the gate voltage is increased until the 4 mA/mm is reached. A rapid assessment of the HCI would entail applying the steady state DC stress to the transistor for 16–48 hours so that an extrapolation can be made out to 20 years; the RDSon and IDQ drift are established by taking periodic measurements throughout the stress period. Care should be taken to control the temperature of the device under test (DUT) as well as the ambient temperature as VT is temperature sensitive and can also impact the IDQ readings. As described earlier, HCI into the gate oxide above the channel region reverses the depletion region spread caused by the DC bias drain voltage. Referring to our example once again, this means that the VT curve at 32 V begins to move toward the VT curve at a drain voltage of 0.1 V. This is a self-limiting phenomenon which means that the initial impact to IDQ is quite large and then additional injection has less and less effect as time goes on. HCI degradation can be estimated as a logarithmic response by plotting the IDQ response against the time of stress and (Figure 1.14). Most of the degradation occurs in the first few hours and then levels off dramatically. Using this log response, an estimation for the degradation out to 20 years can be made. A well-designed transistor will keep the 20-year degradation in IDQ below 10%. This is usually adequate for ensuring that the PA remains within performance specifications. RDSon increases are also tabulated after the stress testing described above. Again, the 20year response should be below 10% but also of importance is the initial 16 h shift which should be lower than 5% (preferably lower than 3%). It is important to note that HCI is a function of temperature, voltage, and current, and that the above DC testing is intended to provide a device with acceptable HCI sensitivity under most operating conditions. The final assessment of HCI requires testing in the actual application environment to properly account for the actual stress conditions. Many facets of the device structure impact HCI sensitivity, including surface oxide quality, n-drift junction profiles, shield design, etc. HCI mitigation strategies typically work against another device parameter (e.g., reduced n-drift doping to lower HCI will
22
Silicon LDMOS and VDMOS transistors
0.0024 0.00238 0.00236 0.00234
IDQ (A)
0.00232 0.0023 0.00228 0.00226 0.00224 20 years 0.00222 0.0022 1E+01
1E+02
1E+03
1E+04
1E+05
1E+06
1E+07
1E+08
1E+09
Time (s)
Figure 1.14 HCI induced degradation of the quiescent current (IDQ ) in an LDMOS device.
degrade Rdson and potentially impact BVDSS ). The tradeoffs between BVDSS , RDSon , and HCI are fundamental to the design of LDMOS and VDMOS transistors. Engineering various ways of improving these tradeoffs to allow for improvements in RF performance has driven device development in this application space for more than 10 years and continues today. Extensive device simulation is needed to fully understand the complex interactions which are involved with any particular device design. It is also important to periodically characterize HCI under typical application conditions to ensure that the DC characterization remains relevant in its ability to predict application HCI behavior.
1.3.4
Snapback/ruggedness Various RF applications require that the devices be able to withstand different levels of RF stress – they need to be considered “rugged” enough for the application. Usually what drives the ruggedness required is the level of RF voltage/current excursions expected to be experienced by the transistor. These excursions are frequently created by mismatch conditions that occur at the output of the device. Radar applications, for instance, use pulsed signals which may incur transients which stress the device, while applications such as a CO2 laser routinely have the PA operating into what is essentially an open circuit. Usually various voltage standing wave ratios (VSWRs) are used to stress the devices to determine the level of ruggedness. Devices are tested at 5:1 or 10:1 (or higher) VSWRs at different levels of input overdrive to assess robustness. It is also common to
23
1.3 Device physics
Gate
Drain
oxide gate oxide metal strap n + source
n − drift region
n + drain
p + “sinker” PHV region p − type epitaxy
p + substrate
Source
Figure 1.15 LDMOS cross-section illustrating the parasitic npn bipolar formed between the drain,
channel, and source regions.
characterize ruggedness at elevated drain voltages where the device is more sensitive to ruggedness failures. There are two device related design concerns which must be considered when ensuring adequate transistor ruggedness: breakdown voltage and snapback current. The avalanche breakdown concept has already been discussed in detail in the previous section. If RF voltage swings are allowed to exceed the breakdown voltage then the current within the device rises rapidly and there is a risk of a catastrophic thermal failure of the transistor. This means that the first measure of defense against ruggedness failures is designing the part such that the voltage swings spend very little time exceeding breakdown. Of course one could design the part with an extremely large BVDSS to ensure a high level of ruggedness but as is made clear in the previous section this would result in a loss in RF performance. Ideally, the transistor should have the lowest level of BVDSS needed to provide adequate ruggedness for the application. This means that at the extremes the BVDSS will be exceeded, therefore the second aspect of ruggedness design involves increasing the current level which can be withstood while in breakdown. This is most directly linked to a phenomenon known as snapback. Referring to Figure 1.15, there is a parasitic bipolar device within the LDMOS structure (a similar parasitic bipolar device exists within the VDMOS structure – indeed, it is a byproduct of typical MOSFET structures). The emitter is the n+ source, the base is the body of the device and the collector is the drain. When impact ionization is initiated and avalanche breakdown occurs, there is a sudden and dramatic increase in the level of electrons and holes in the drain region of the device. The built-in electric fields pull
Silicon LDMOS and VDMOS transistors
0.45
7.0 V
0.40
6.0 V 5.4 V
0.35
on-state breakdown
5.0 V
0.30 IDS (A)
24
0.25 4.4 V 0.20 4.0 V
0.15
off-state breakdown
3.4 V
0.10
3.0 V
0.05
VGS = 2.0 V
0V
0.00 0
10
20
30
40
50
60
70
80
VDS (V)
Figure 1.16 On-state versus off-state breakdown curves.
the electrons out of the drain of the transistor, while the holes are injected into the base region of the bipolar transistor. The hole current can forward bias the emitter–base junction, and so more electrons are injected across the channel and into the high field drain region which creates more holes and electrons due to avalanching and creating a feedback loop that can result in extremely large, localized current flows that result in catastrophic thermal failure of the transistor. This is referred to as snapback, and can be characterized by both a snapback voltage and current. The goal of enhancing ruggedness is to prevent snapback from occurring by both delaying the onset of impact ionization, and to design the transistor to minimize the injection of holes into the base of the parasitic bipolar once impact ionization has been initiated. Increasing the snapback voltage typically entails increasing BVDSS . However, BVDSS is the off-state breakdown voltage; it is equally important to increase the onstate breakdown (see Figure 1.16). The drain region design (doping levels, shields, etc.) dictates the on and offstate breakdown behavior; design for ruggedness becomes another of the tradeoffs of the drain engineering process. Strategies to increase the snapback current entail both moving the location of impact ionization away from the base of the parasitic bipolar transistor, and designing the device to shunt the hole current to ground, bypassing injection into the base of the bipolar. Figure 1.17 is an example illustrating the effect on hole current by modifying the drain of the device to accomplish both goals (moving the impact ionization away from the base of the bipolar, and shunting the hole current to ground).
1.3 Device physics
Gate
Drain
Hole current injected into base
Gate
25
Drain
Hole current shunted to substrate
Baseline
Optimized
Figure 1.17 TCAD simulation of hole current density for two structures taken into avalanche breakdown. The one of the left depicts a baseline device with the majority of the hole current being injected into the base of the parasitic npn, while the optimized structure on the right shunts the hole current to the grounded substrate, preventing latch-up.
1.4
1.2
TLP Current (A)
1
snapback
0.8
0.6
0.4
0.2
0 0
10
20
30
40
50
TLP Voltage
Figure 1.18 Typical snapback curve due to turn-on of the parasitic bipolar transistor in an LDMOS device.
Characterization of snapback voltage and current is typically carried out using a transmission line pulse generator (TLPG) system, in a similar manner to how ESD sensitivity is characterized. The system works by charging up a transmission line to successively higher voltages and then throwing a switch allowing the stored energy on the transmission line to enter the transistor. At each pulse the voltage and current are recorded allowing a plotting of the snapback curve (see Figure 1.18). Simple DC
26
Silicon LDMOS and VDMOS transistors
measurements will end in destruction once the snapback voltage is exceeded. The TLPG system allows various design parameters to be investigated for their efficacy in adding ruggedness to the device. Finally, the fully designed part is tested as described earlier with various levels of VSWRs and overdrives. This is also a test to destruction where the final level of survivability is recorded. It is important to note that ruggedness performance is a function not simply of the device but the complete operating environment (surrounding circuit, input waveforms, operating temperature, etc.); the final assessment of ruggedness performance must be conducted in the final application under realistic operational and stress conditions.
1.3.5
Operating voltage considerations Although considerable time has been spent in this section discussing ways of designing the breakdown voltage for a given device, the focus has largely been on base station type designs where a voltage supply of 26–32 V is used. LDMOS and VDMOS devices, however, can be easily adapted to the voltage supply requirements of a wide range of applications. The optimum voltage level tends to be proportional to the RF power requirements of the application. In general, changing the n-drift region length (laterally by layout for LDMOS and vertically by epi thickness for VDMOS) and doping level is the easiest way to tailor the breakdown voltage to a given supply voltage requirement. For lower voltage applications such as handset PAs, the voltage can drop as low as 3 V, while for broadcast applications 50 V is quickly becoming commonplace. Other applications in the industrial/scientific/medical (ISM) space are amenable to even higher operating voltages, with VDMOS devices on the market designed for 100 V or higher operation (i.e., BVDSS over 200 V). Typical n-drift region lengths range from 3 μm for cellular infrastructure’s 28–32 V requirements down to the range of 0.5 μm for the low voltage, low-power applications, but can be as high as 6–9 μm for the 50 V applications and very high RF powers. Each end of this range has its own set of design concerns to consider. At the low-voltage end of the spectrum, such a short n-drift region makes it difficult to make the part resistant to snapback. Just by the nature of such a small drift region, the avalanche process is going to occur in close proximity to the base of the parasitic bipolar transistor. This makes the use of a p+ region around the n+ source to lower the gain of the bipolar transistor that much more important in these designs. For 50 V LDMOS designs there is the challenge of achieving breakdowns in excess of 100 V. Long n-drift regions coupled with intelligent shield designs are needed to optimize the usual set of tradeoffs (RDSon, HCI, ruggedness, and BVDSS ). But at some point, the vertical breakdown begins to be the limiting factor as opposed to the lateral breakdown. To circumvent this limitation, a thicker epitaxial layer must be used to extend the amount that the depletion region can extend vertically before hitting the highly doped p+ substrate. The link-up between the p+ sinker and the substrate must be redesigned since there is now a thicker epi layer through which a low-resistance path must be created. The VDMOS device structure is more amenable to increasing the operating voltage. In VDMOS the epi layer thickness and doping level determine the breakdown characteristics. The LDMOS structure has
1.4 Design/layout
27
Figure 1.19 LDMOS discrete transistor layout for an ∼50 W device with 500 μm unit gate width
(UGW).
more flexibility to be designed for very high-power density (W/mm gate periphery) with low parasitic capacitance due to the lateral structure and access to shield layers, but this flexibility tends to be limited to breakdown voltages in the 100–130 V range. VDMOS devices, on the other hand, can be designed with breakdown voltages in excess of 200 V, but with relatively higher parasitic capacitance levels that tend to limit the frequency of operation.
1.4
Design/layout
1.4.1
Top-down finger layout LDMOS and VDMOS devices for RF PAs deliver very large amounts of power. It is not uncommon for a single transistor die to deliver 50 W, and often two to four of these blocks are arranged in parallel within a package to create a single device which delivers in excess of 200 W. Generating this amount of power requires a very large gate width. Single transistor gate widths are routinely over 50 mm and have been known to run to over 1 m. This is an extremely large amount of gate periphery which must be given a layout design which is efficient and optimized for RF operation. This section will discuss the various critical design concerns regarding top-down layout of LDMOS and VDMOS devices. The layout of power transistors with very large gate periphery is designed to satisfy a number of considerations, including thermal, aspect ratio for stress and package compatibility, and frequency of operation. The solution to this challenge is to arrange a large number of shorter gates in parallel such that they operate in unison as one transistor. This parallel arrangement is referred to as an array of gate fingers. All of these fingers sit within one large active area surrounded by some type of field oxide isolation. Figure 1.19 shows a top-down view of a typical LDMOS layout designed for ∼50 W RF power at 2 GHz. Each gate finger is 500 μm wide and is referred to as the unit gate width (UGW) of the transistor. Two fingers in parallel yields 1 mm of gate periphery. The fingers are arrayed such that there is symmetry around the center of each drain and each source. This leads to twice as many gate fingers as there are drain fingers as each drain (and source) feeds two gates. The RF signal and biases are going to be applied to the bond pads at the end of the fingers. This means that each finger will act as a transmission line as the signal progresses
28
Silicon LDMOS and VDMOS transistors
Figure 1.20 Layout showing gate buses feeding gate taps spaced at 100 μm intervals along the fingers in an LDMOS device.
down its length. To minimize the transmission line losses or phase delays which can result, the concept of gate taps is introduced. Notice in Figure 1.20 that there is a gate contact every 100 μm attached to a metal line connected to the gate bond pad. This gate metal line or gate bus is used to carry the input signal down the length of the finger with minimal transmission line effects due to the high conductivity of the aluminum alloy. This bus is then electrically connected to the gate itself such that each 500 μm gate is actually five 100 μm gates in parallel. Recall that the gate itself also typically has a silicide atop the polysilicon to keep the intrinsic gate resistance low. This silicide resistance, however, is two to three orders of magnitude higher in resistance than the metal gate bus, illustrating the necessity of the gate bus. Other unit gate widths and gate tap spacings are employed, typically dictated by the power level and frequency. Larger and larger UGWs eventually generate transmission line losses even within the gate bus while very small UGWs make for very poor aspect ratio devices. Higher frequencies will cause transmission line losses to appear sooner due to the shorter wavelengths and it is therefore more common to see large UGW devices operating in the 900 MHz space and below in the cellular infrastructure arena. Finally the device pitch must be considered. The drain-to-source pitch for LDMOS or source to gate pitch for VDMOS of a given layout is the distance between each axis of symmetry within a single finger (i.e., from the center of the source to the center of the drain for LDMOS, or center of gate to center of source for VDMOS). The LDMOS drain region is typically kept to a minimum because the n+ implant region needed to
1.4 Design/layout
29
make a good drain contact is a large contributor to the output capacitance within the device. Therefore, the minimum n+ drain is determined by the minimum drain contact dimension plus enclosure rules for the n+ implant. The rest of the drain contribution to pitch is set by the n-drift region requirements of the transistor. The source side of the device allows for more flexibility and can usually be expanded or contracted to fit a given package space or meet a thermal requirement. When shrinking the source area for LDMOS care must be taken that the p+ sinker implant does not get too close to the channel of the device. Recall that the p+ sinker undergoes an aggressive thermal drive to diffuse the dopant down through the epi to meet the p+ substrate. Lateral diffusion of the dopant is occurring at the same time and typically reaches several microns. Device pitch, unit gate width, and gate tap spacing are all flexible design parameters that are adjusted based on the performance requirements of the part.
1.4.2
Bond pad manifolds To provide an RF signal to the transistor, wires much be connected from the leads of the package to the silicon die. In the case of LDMOS there are only gate and drain wires since the source is connected through the package flange to ground. This seemingly simple electrical connection turns out to be quite complex in the field of RF device design, since these elements are not merely electrical conductors but instead these conductive elements have capacitance, inductance, and transmission line behaviors that are fundamental to the RF performance. Despite the design considerations mentioned in the previous section, the transistor die still has a large aspect ratio. It is not uncommon to have die which are 1–3 cm wide with an array of fingers spanning most of the length (see Figure 1.1). Placing one gate wire in the center of this array will cause a transmission line affect to be present from the center fingers to the outside fingers. Each finger will not receive the same RF stimulus and this can introduce nonuniformities in device operation due to phase differences between the individual fingers. To remedy this situation, a large number of wires in parallel are bonded from the package lead to a bond pad which spans the entire width of the device. The bond pads incur parasitic capacitance but this is minimized by placing them on top of the field oxide. The goal is to feed the array of fingers as uniformly as possible to maximize performance. This parallel arrangement of wires introduces inductance at the input and output of the device and this must be incorporated into any matching intended for the transistor. Moreover, this wire array is typically utilized and optimized by designers to present a desirable level of impedance at the package lead to ease the customer’s use of the part. At a finer level of detail, there is design of the metal which connects the bond pad to the finger itself. The primary consideration in this region of the device is resistive losses due to large amounts of RF current being funneled out of each finger into the large expanse of bond pad metal. However, designing to meet electromigration requirements typically minimizes this resistive loss (see Section 1.4.3), so this is not typically a problem. Nevertheless, flares such as shown in Figure 1.21 can be used to minimize the impact.
30
Silicon LDMOS and VDMOS transistors
Figure 1.21 Drain metal flare designs for transitioning from drain bus to drain bond pad.
1.4.3
Metal design – electromigration Electromigration is a phenomenon which occurs in metal lines when the DC current density within the lines becomes excessive in conjunction with elevated temperatures – conditions that are easily met in RF power devices. Momentum transfer due to collisions between electrons and the metal conductor atoms can displace the metal atoms which leads to resistance increase and eventually an open circuit under severe conditions. This is a wearout mechanism which occurs over the lifetime of the part and, as such, is a reliability consideration. Electromigration is discussed further in Chapter 10, but this section discusses how to design a device properly such that adequate electromigration lifetimes are achieved. To begin designing for electromigration robustness, the metal being used must be characterized with various current and temperature stress tests. Different metal alloys and metal types vary widely in their electromigration responses. Gold, for instance, has much higher electromigration resistance than aluminum. Aluminum alloys, typically formed by the addition of a small percentage of copper [27] have been developed and are in widespread use in the semiconductor industry; AlCu alloys have excellent electromigration properties compared to pure Al. Copper is another conductor with good electromigration properties. It is important that the electromigration characterization of the metal conductor uses the same processing and structures (linewidth, topography) as the actual device to accurately reflect the microstructure and stresses in the conductor. Once the necessary material constants for the chosen conductor and design have been generated, a simplified form of Black’s equation [28] can be used to begin the design calculations. A MTTF = 2 e J
EA KT
(1.5)
where MTTF is the median time to failure (typically defined as a certain percentage increase in line resistance), A is a material constant (includes geometry effects), J is the current density, EA is the activation energy, k is Boltzmann’s constant, and T is the temperature.
1.4 Design/layout
31
Figure 1.22 Top-down illustration of the current flow in an LDMOS device.
One of the first things to notice about Black’s equation is that the lifetime it predicts is inversely proportional to the square of the current density. Assuming that the material properties of the conductor have already been optimized to maximize the MTTF performance, the current density is the next parameter that the device engineer will manipulate to improve the MTTF. The current density is typically controlled by using a thick top metal layer, consistent with fabrication design rules and the device structure, stacking metal layers to reduce the current density, and finally by drawing wider and wider lines to lower the current density until the target MTTF is reached. There are of course limits to how wide the metal layers can be due to parasitic capacitance considerations, so careful consideration of electromigration is required in the design of the device. In LDMOS devices, the drain lines carry the largest currents. A top-down view of the current flow (Figure 1.22) shows that there is a greater and greater amount of current being carried by the line as it nears its connection with the drain bond pad. Therefore the electromigration critical design point is the end of each drain finger as it enters the drain bond pad. One common practice is to flare the metal making it wider as it approaches the end of the finger. This keeps the current density relatively constant along the finger length. The downside is that extra parasitic capacitance is generated between the drain metal and the underlying structure (i.e., the gate and source). One technique that can be used to enhance electromigration performance is to design the high-current conductors so that they are in the so-called bamboo regime [29]. Each metal line is comprised of metal grains (see Figure 1.23). If the metal linewidth is kept below the median grain size the line begins to look like a piece of bamboo with the grain boundaries traversing the line laterally. Electromigration occurs preferentially along grain boundaries, so keeping the metal line within the bamboo regime results in
32
Silicon LDMOS and VDMOS transistors
Figure 1.23 The figure on the left is a cross-section TEM through the drain metal of an LDMOS device showing the intersection of three aluminum grains; the image on the right is a contrast-enhanced optical microscope view of the aluminum drain bondpad, showing the distribution of grains in the film.
greatly enhanced electromigration lifetimes. Typical grain sizes can range from less than 1 μm to greater than 5 μm depending on the metal deposition process. The other critical parameter to note in Black’s equation is temperature. The lifetime is exponential with temperature. Given that many PA power transistors run at high-power densities, temperatures can get as high as 200 ◦ C. Hence, the thermal performance of the device and package are important considerations that affect the peak temperature. It is common to find RF power transistors designed to occupy a larger area than is necessary to reduce the areal power density and thereby lower the junction temperature. Once the device design is completed a design curve or calculator is typically generated and made available to enable the customer to calculate the MTTF for their application condition (see Figure 1.24).
1.4.4
Thermal Given the large amount of power dissipated in LDMOS and VDMOS transistors for PA applications, thermal heating within the device must be accounted for. Excessive temperatures will degrade both the performance and reliability. This means that the thermal resistance of the part must be engineered to manage the heat generated during operation. The factors which contribute to the thermal resistance are the materials which the heat must pass through as well as the cross-sectional area through which the heat passes. LDMOS and VDMOS transistors are made from silicon which is given a metal backing (typically gold or a solderable metal film) which is attached either eutectically or soldered to the package flange, which in turn is mounted to the heat sink. Factors which must be considered in the thermal design include layout (increasing the source-drain pitch reduces the power density), substrate thickness (50–75 μm is a typical thickness for high-power parts), die attach technology (gold eutectic being the best, followed by
33
1.4 Design/layout
Pout (W)
25
Vdd (V)
28
Drain Eff (%)
42
10,000 Electromigration MTTF vs. Temperature
MTTF (Years)
1,000
100
10 110
120
130
140
150
160
170
180
190
200
210
Temperature (C)
Figure 1.24 A graph of the electromigration MTTF vs. temperature. The variables are output power, drain voltage, and drain efficiency. The equation for the curve is based upon Black’s equation.
solder), voids formed during die attach (paradoxically, accounting for voids can actually cause the optimum substrate thickness to increase since it acts as a heat spreader around the void), and flange thermal conductivity and thickness (thermal performance is an important driver of package technology). The heat in a DMOS transistor is generated within the primary parasitic resistance of the device: the n-drift region. Looking at the top-down view of an LDMOS transistor (see Figure 1.1) there is an array of drain regions which are all generating heat during operation. From each of these regions the heat will fan out laterally as it moves towards the backside of the wafer. It is therefore a very good approximation to use the total active tub area as the cross-sectional area driving thermal resistance. There are exceptions to this such as when a device is quite small and the edge effects begin to become a large
34
Silicon LDMOS and VDMOS transistors
contributor to the overall thermal resistance cross-section, but for large transistors the approximation is valid. This begins to play a role into how the UGW and pitch are chosen when designing the transistor. Choosing the largest pitch possible for a given package area will yield the best thermal resistance. For a given amount of gate periphery and a given package constraint, moving to the largest UGW that is consistent with electromigration and performance considerations allows the source-drain pitch to be increased, improving thermal performance. It is apparent that there are a wide range of considerations that must be managed during the device design process to achieve the best balance of performance and reliability. Over the years these techniques have held increasing importance as power density within the device has improved. Customers are always seeking more power out of a given package footprint, which places continued challenges on maintaining good thermal resistance. One aspect of device design which helps is the increase of efficiency. As devices have become more and more efficient, either through intrinsic performance or through high-efficiency architectures like Doherty, the heat dissipation has improved for a given amount of delivered power. Thus, a 50 W part with 45% efficiency generates significantly less heat than a 50 W part with 35% efficiency, making thermal resistance design a more important factor for the 35% efficiency part (these are typical efficiency levels in cellular base stations operated in Doherty or simple Class AB, respectively). It should also be mentioned that thermal properties affect the uniformity of the transistor. Figure 1.25 shows an infrared scan of a typical LDMOS transistor. The center of a transistor generally runs hotter than the edges. This creates nonuniformity within the device as the edge fingers will have a slightly different threshold voltage, etc., due to the heat profile. Good thermal design practices will minimize these temperature variations.
1.4.5
Operating voltage considerations This book is focused on RF technologies for power levels exceeding 1 W, or to generalize, noncellular handset RF power applications. For these powers levels and for frequencies up to ∼3 GHz, silicon technologies and in particular LDMOS and VDMOS dominate. The reasons are fairly simple – a low-cost structure, good performance (gain, efficiency, linearity), excellent reliability, and relatively straightforward scalability to powers up to ∼1 kW. The market has segmented by application voltage into three primary bands: 12 V, 28–32 V, and 50 V or higher. As would be expected, the range of device power levels also scale with operating voltage. The 12 V market ranges up to ∼70 W devices, the 28–32 V market ranges up to 300–400 W, and the 50 V + market includes devices rated at over 1 kW. The 12 V market application is primarily for land mobile applications (fire, police, taxi, etc.). The specified maximum application voltage is typically 16 V to allow for automotive battery chargers operating in worst case conditions. Excluding low cost, the most important requirement of this market given the harsh environmental and application conditions that can be encountered is ruggedness. Ruggedness considerations dictate BVDSS in the 50 V or higher range. The land mobile market is characterized by slices of spectrum that vary by country, but in general operate at frequencies under 1 GHz;
35
7S18125AH
Temperature (°C)
GATE
DRAIN
1.4 Design/layout
Figure 1.25 Thermal scan for a 125 W LDMOS device. The PA is typically designed to limit the maximum junction temperature below 150 ◦ C, although the devices are typically rated to operate up to 200 ◦ C to 225 ◦ C.
efficiency at these power levels and frequencies can reach in excess of 70% at P1 dB for class AB operation. Linearity requirements are fairly modest compared to cellular. The dominant technology for this market segment is LDMOS. The 28–32 V market application is dominated by cellular infrastructure, but also includes broadcast, avionics, and other noncellular applications. The cellular infrastructure market is also dominated by LDMOS. This market segment is very performance competitive, requiring state-of-the-art gain, efficiency, and linearity. The application ruggedness requirements are less demanding than for land mobile. Cost is an important consideration, so long as performance is competitive. The cellular infrastructure market has been under significant cost pressures for the past decade, which has driven packaging innovation such as high-power over-molded plastic transistors that have a lower cost structure than the historical ceramic air-cavity packages. The BVDSS minimum for these voltages is typically 65 V. LDMOS products are on the market for frequencies up to 3.8 GHz for WiMAX applications; VDMOS devices compete in the subGHz, noncellular arena where their more limited frequency capability is not a limitation. The 50 V and higher markets are concentrated in the relatively broad noncellular application space that includes ISM, avionics, and broadcast markets. These markets
36
Silicon LDMOS and VDMOS transistors
have a very diverse set of performance requirements, with certain applications requiring high-pulse CW with no linearity requirements, while others demand stringent back-off linearity with good efficiency. These devices require excellent ruggedness performance; certain applications like CO2 lasers routinely subject the transistors to open circuit conditions at high power levels, representing a testing ground for a transistor’s ruggedness capability. This application space typically requires higher power transistors than are practical with 28 V devices, with products on the market at power levels exceeding 1 kW. 50 V devices tend to have minimum BVDSS values in the 105 V–120 V range, but applications with extreme ruggedness requirements could have even higher breakdown values. It is only within the past several years that 50 V LDMOS devices have been on the market [19–21]. VDMOS competition is robust, particularly at lower frequencies and high power levels. The vertical structure of VDMOS also enables scaling of the breakdown voltage to allow operating voltages of 100 V [17–18]. The lateral LDMOS structure does not scale as readily to support BVDSS values of 200 V or higher that are necessary to operate at 100 V.
1.4.6
Frequency considerations: gate length, gate width, resistors Before delving into frequency considerations, it is worthwhile to consider the impact of transistor gain on efficiency and cost. It becomes challenging to design stable parts with good isolation if the gain exceeds about 25 dB in a single stage transistor (multistage lower power ICs have been designed with gain up to ∼35 dB [30–31]). The desire for high gain is primarily cost – a higher gain, high-power final stage in the PA lineup will require a lower power and hence lower cost driver, potentially fewer devices in the lineup, and require less space on the printed circuit board (which also translates into cost savings). There are also lineup efficiency benefits with a high-gain final stage. The power-added efficiency (PAE) is a metric that tracks the conversion efficiency of DC from the power supply into RF power, and is defined by the equation: PAE =
Pout − Pin PDC
(1.6)
where Pout is the RF output power, Pin is the RF input power, and PDC is the power from the DC power supply to the device. PAE, as the name indicates, is a measure of how efficiently the device converts DC power to RF power, and hence can be used to determine power dissipation in the device. A 50% PAE device must dissipate an amount of power equal to its output RF power while a 25% PAE device dissipates three times as much power as it transmits. The highest possible PAE that meets other system requirements is clearly the goal. By manipulation of the variables, PAE can also be written as: 1 PAE = η D 1 − (1.7) G where ηD is the drain efficiency (defined as the ratio of Pout to PDC ), and G is the RF power gain. For a gain of 20 dB (a factor of 100), the PAE is within 1% of the drain efficiency. As the gain falls below 15 dB, the PAE begins to fall rapidly, degrading
1.4 Design/layout
37
overall efficiency and increasing operating costs in addition to requiring more expensive techniques and mechanical items to manage the dissipated heat. By the same token, there is little efficiency motivation for the gain to exceed 20 dB from an efficiency perspective, although there are still cost and board space considerations. Simple filter theory predicts for a single pole transfer function that power gain will follow a 6 dB/octave rolloff with frequency, i.e., a 20 dB gain part at 2 GHz will have 26 dB gain at 1 GHz, 32 dB gain at 500 MHz, etc. A common approach during device design is to develop the transistor to have as high a gain as possible at its maximum operating frequency without compromising other parameters (i.e., reliability, ruggedness, etc.), and then to limit the gain increase at the lower frequencies to maintain a stable device and circuit. Maximizing performance at the highest frequencies of operation causes the device designer to migrate towards the classical solutions of shorter gate lengths, thinner gate oxides, and aggressively reducing all parasitic capacitances and resistances. The LDMOS structure is more amenable to optimizing for high frequency compared to VDMOS, with LDMOS dominating the cellular infrastructure frequencies. Excessive gain at lower frequencies can be countered by degrading the intrinsic gate of the transistor (longer gate length, thicker gate oxide). Another approach that offers ancillary benefits is to add series resistance to the gate feed network, which not only decreases the gain to manageable levels but also lowers the Q of the input network, facilitating the design of broadband matching networks. High-power device design also requires careful optimization to the layout of the individual fingers. Practical limits of gate width at frequencies of 1–3 GHz are of the order of 1000 μm, with the maximum gate width decreasing as the frequency is increased. Excessive gate widths exacerbate distributed effects (transmission line delays, phase shifts, etc.) and lower the gain and can impact efficiency and linearity. As frequencies decrease below 1 GHz, these distributed effects become less important and the device layout tends to be dictated by package constraints and reliability considerations, such as electromigration.
1.4.7
HVICs High voltage integrated circuits (HVICs) in the context of high-power RF devices typically refers to having at least two stages of amplification along with elements of the matching network (e.g., inductors, capacitors, resistors) all integrated onto the same semiconductor substrate. HVICs in cellular infrastructure were first introduced as driver devices that were designed to power the final stage of the PA lineup. The first highpower cellular infrastructure HVIC in production was the MRFIC5001, introduced by the semiconductor sector of Motorola (now Freescale) in 1999. The MRFIC5001 is a 10 W, 900 MHz GSM driver HVIC; this HVIC is a two-stage device having 26 dB gain at 26 V, and was based on the third-generation HV3 LDMOS platform from Motorola. The design of both driver stage and final stage high-power HVICs has flourished since this time, with almost all PA designs now including HVICs in the lineup [32–35]. The advantages of integration are well known, and include a dramatic reduction in component count and board space, lower cost, and reduced overall performance
38
Silicon LDMOS and VDMOS transistors
Output stage
Input stage
GND
VD1
NC
NC
NC RF in RF in
NC
VG1
VG2
NC
GND
Figure 1.26 Assembly drawing of a 2 GHz, 100 W LDMOS high-power IC. This is a 2-stage IC, with a fully integrated input and interstage match (input impedance is 50 ), and an integrated shunt-L output match.
variation. Modern HVICs are two stage designs due to the high gain of the individual LDMOS stages. A traditional discrete design matching network is constructed using high-Q inductors and capacitors. The inductor is formed from wirebonds and can have a Q in the 50–100 range. The matching network passive elements in HVICs include spiral metal inductors and integrated series and shunt capacitors. The most challenging passive to integrate into the LDMOS flow is the spiral inductor which, due to the heavily doped substrate, is limited to Q values in the 5–10 range; integrated capacitor performance does not tend to be the limiting factor in HVIC designs. The relatively low value of the integrated inductors is adequate for the design of input and interstage matches, but is too low for the output stage. Wirebonds continue to be employed at the output of the final stage of HVICs where the much higher currents require the highest possible inductor Q to achieve target performance levels. The performance of HVICs has advanced over the past decade. This has been enabled not only by the improved performance of the LDMOS transistor, but also by passive component optimization and refinements in the design methodology to extract as much performance as possible. An example of the state-of-the-art in IC design today is the MW7IC18100N [36], which is a two-stage IC rated at 100 W at 1.8 – 2.0 GHz with 30 dB gain, designed as a high-gain, high-power output device for GSM and GSM Edge applications (see Figure 1.26). Another example of the progress made in HVIC performance is found in the MW7IC3825N [37]. This IC is designed for 28 V operation
References
39
in the 3.4–3.6 GHz band, is rated at 25 W P1 dB , and has been characterized for WiMAX operation. These examples illustrate the significant progress made in both the process technology as well as the design methodology to enable the design of high-performance, high-power HVICs.
Summary The application space for high-power RF transistors is broad and growing, ranging from the ubiquitous cellular base station to avionics, broadcast, industrial, scientific, medical, etc. The requirements placed upon the RF power transistor varies depending upon the application requirements, including power gain, linearity, efficiency, reliability, thermal management, bandwidth, ruggedness, linearizability and, last but certainly not least, cost. LDMOS and VDMOS technologies dominate these applications due to an excellent combination of these factors. VDMOS is strongest at lower frequencies and higher power levels where the vertical structure can best be leveraged into a higher operating voltage capable of very high power levels. LDMOS is the dominant device technology for cellular infrastructure basestation PA applications, and has over the past few years been introduced into markets that were traditionally the domain of VDMOS and silicon bipolar transistors. VDMOS and LDMOS together dominate the market for high-power PAs from frequencies in the low MHz range up to 4 GHz, and for power levels that exceed 1 kW. Investments continue to be made in both VDMOS and LDMOS to further improve performance and meet the evolving requirements of the end applications.
Acknowledgments The authors would like to acknowledge the support and assistance provided by our colleagues at Freescale, without which much of this chapter would not have been possible.
References 1. J. T. C. Chen and C. P. Snapp, “Bipolar microwave linear power transistor design,” IEEE Trans. Microw. Theory . Techn., vol. MTT-27, no. 5, pp. 423–430, May 1979. 2. C. P. Snapp, “Microwave bipolar transistor technology – present and prospects,” Ninth European Microwave Conference, Sept. 1979, pp. 3–12. 3. E. Fong, D. C. Pitzer, and R. J. Zeman, “Power DMOS for high-frequency and switching applications,” IEEE Trans. Electron Devices, vol. ED-27, no. 2, pp. 322–330, Feb. 1980. 4. O. Ishikawa, H. Yamada, and H. Esaki, “A 2.45 GHz Power LD-MOSFET with reduced source inductance by V-groove connections,” International Electron Device Meeting, 1985, pp. 166–169.
40
Silicon LDMOS and VDMOS transistors
5. J.-J. Bouny, “Advantages of LDMOS in high power linear amplification,” Microwave Eng. Europe, pp. 37–40, 1997. 6. A. Wood, W. Brakensiek, C. Dragon, and W. Burger, “120 watt, 2 GHz, Si LDMOS RF power transistor for PCS base station applications,” IEEE MTT-S Microwave Symp. Dig., vol. 2, pp. 707–710, 1998. 7. C. Cassan, J. Jones, and O. Lembeye, “A 2-stage 150 W 2.2 GHz dual path LDMOS RF power amplifier for high efficiency applications,” IEEE MTT-S Microwave Symp. Dig., pp. 655–658, 2008. 8. F. van Rijs, “Status and trends of silicon LDMOS base station PA technologies to go beyond 2.5 GHz applications,” IEEE Radio and Wireless Symposium, 2008, pp. 69–72. 9. P. H. Wilson, “A novel high voltage RF vertical MOSFET for high power applications,” Tenth IEEE International Symposium on Electron Devices for Microwave and Optoelectronic Applications, 2002, pp. 95–100. 10. M. Trivedi and K. Shenai, “Comparison of RF performance of vertical and lateral DMOSFET,” Eleventh International Symposium on Power Semiconductor Devices and ICs, 1999, pp. 245– 248. 11. J. Zhang, D. Sdrulla, D. Tsang, D. Frey, and G. Krausse, “Design of rugged high voltage high power p-channel silicon MOSFET for plasma applications,” 38th European Solid State Device Research Conference, 2008, pp. 71–74. 12. J. A. Appels and H. M. J. Vaes, “High voltage thin layer devices (RESURF Devices),” International Electron Device Meeting, vol. 25, pp. 238–241, 1979. 13. F. H. Raab, F. H. Raab, P. Asbeck, S. Cripps, P. B. Kenington, Z. B. Popovic, N. Pothecary, J. F. Sevic, and N. O. Sokal, “Power amplifiers and transmitters for RF and microwave,” IEEE Trans. Microw. Theory Techn., vol. 50, no. 3, pp. 814–826, 2002. 14. W. R. Burger, “Recent advances in RF-LDMOS high-power IC development,” IEEE International Conference on IC Design and Technology, 2009, pp. 35–38. 15. S. J. C. H. Theeuwen and H. Mollee, “S-band radar LDMOS transistors,” European Microwave Integrated Circuits Conference, 2009, pp. 53–56. 16. W. Xie and B. Li, “An analytical current model for lateral gradual doping channel in LDMOS,” IEEE International Conference of Electron Devices and Solid-State Circuits, 2009, pp. 16–19. 17. STMicroelectronics, “RF power transistors HF/VHF/UHF N-channel MOSFETs,” STAC4932B datasheet, Feb. 2010 Revised Aug. 2010. 18. Microsemi, “RF power MOSFET n-channel enhancement mode,” ARF1500 datasheet, Rev. E, Oct. 2008. 19. P. Piel, W. Burger, D. Burdeaux, and W. Brakensiek, “50 V RF LDMOS: An ideal RF power technology for ISM, broadcast, and radar applications,” 2008. [Online] Available: http://www.mwjournal.com/2008/DownloadablePDFs/FREESCALE50VLDMOS.pdf [Accessed: 6 Aug. 2010]. 20. Freescale Semiconductor, “RF power field effect transistor,” MRF6VP11KHR6 datasheet, Jan. 2008 [Revised April 2010]. 21. NXP, “LDMOS avionics radar power transistor,” BLA6H0912–500 datasheet, Mar. 2009 [Revised May 2010]. 22. M. Trivedi, P. Khandelwal, and K. Shenai, “Performance modeling of RF power MOSFET’s,” IEEE Trans. Electron Devices, vol. 46, no. 8, pp. 1794–1802, Aug. 1999. 23. P. H. Aaen, J. A. Pl´a, and J. Wood, Modeling and Characterization of RF and Microwave Power FETs, Cambridge University Press, 2007, pp. 21–22.
References
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24. P. H. Aaen, J. A. Pl´a, and J. Wood, Modeling and Characterization of RF and Microwave Power FETs, Cambridge University Press, 2007, p. 32. 25. P. H. Aaen, J. A. Pl´a, and J. Wood, Modeling and Characterization of RF and Microwave Power FETs, Cambridge University Press, 2007. 26. S. M. Sze, Physics of Semiconductor Devices, New York, NY: John Wiley & Sons, 1981. 27. M. C. Shine and F. M. d’Heurle, “Activation energy for electromigration in aluminum films alloyed with copper,” IBM J. Research Develop., vol. 15, no. 5, pp. 378–383, 1971. 28. J. R. Black, “Electromigration failure modes in aluminum metallization for semiconductor devices,” Proc. IEEE, vol. 57, no. 9, pp. 1587–1594, 1969. 29. S. Vaidya, T. T. Sheng, and A. K. Sinha, “Linewidth dependence of electromigration in evaporated Al-0.5%Cu,” Appl. Physics Lett., vol. 36, no. 6, pp. 464–466, 1980. 30. G. Bouisse, “High power silicon MMIC design for wireless base stations,” 30th European Microwave Conference, 2000, pp. 1–3. 31. Freescale Semiconductor, “RF LDMOS wideband integrated power amplifiers,” MW7IC915NT1 datasheet, Sept. 2009 [Revised Dec. 2009]. 32. G. Wang, L. Zhao, and M. Szymanowski, “A Doherty amplifier for TD-SCDMA base station applications based on a single packaged dual-path integrated LDMOS power transistor,” IEEE MTT-S Microw. Symp. Dig., pp. 1512–1515, 2010. 33. L. Zhao, G. Bigny, and J. Jones, “A 120 watt, two-stage, LDMOS power amplifier IC at 1.8 GHz for GSM/EDGE applications,” IEEE MTT-S Microw. Symp. Dig., pp. 1509–1512, 2008. 34. C. Cassan and P. Gola, “A 3.5 GHz 25 W silicon LDMOS RFIC power amplifier for WiMAX applications,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2007, pp. 87– 90. 35. C. D. Shih, J. Sjostrom, R. Bagger, P. Andersson, Y. Yinglei, G. Ma, Q. Chen, T. Aberg, “RF LDMOS power amplifier integrated circuits for cellular wireless base station applications,” IEEE MTT-S Microw. Symp. Dig., pp. 889–892, 2006. 36. Freescale Semiconductor, “RF LDMOS wideband integrated power amplifiers,” MW7IC18100NR1 datasheet, May 2007 [Revised Mar. 2009]. 37. Freescale Semiconductor, “RF LDMOS wideband integrated power amplifiers,” MW7IC3825NR1 datasheet, Nov. 2008.
2
GaAs FETs – physics, design, and models Rob Davis RFMD
2.1
Introduction The manufacture of Gallium Arsenide FET devices and integrated circuits is now a mature industry. The GaAs FET was first developed in the 1960s and 1970s [1], with the impetus to establish a manufacturing capability coming in the 1980s driven by governmental support – most notably the comprehensive “MIMIC” programme in the United States. In the intervening time the GaAs FET became the default solid-state device for all manner of RF and microwave applications. However, the position of the GaAs FET in this arena has not gone unchallenged. It was soon joined by the GaAs HBT which has dominated the cellular handset power amplifier market. The upper frequency limit of silicon LDMOS technology has steadily increased over recent years as its highly mature technology was further refined with the result that this technology currently dominates high-power RF applications below 3 GHz. More recently, gallium nitride devices join the fray. The GaN FET is a device technology of great promise that is steadily being made available by more vendors as its reliability is established. Initially, gallium nitride is also targeting the lower frequency bands but is capable of being developed for applications across the whole microwave bandwidth. For the higher millimetre-wave frequencies indium phosphide technology has a place. However, GaAs FET technology is proven, competent, mature, and remains a good choice for many applications including high-frequency power and high linearity. GaAs technology also has significant cost advantages over its nonsilicon competitors. The economies of scale that the cellular communications market has brought to GaAs technology has revolutionized the manufacture of GaAs products and has given rise to dramatic reductions in cost. It is in the area of continued cost reduction that the most significant new developments in GaAs device and associated technologies are focused. This chapter aims to introduce contemporary GaAs-based power FET technology. It is written with the perspective of the user of the technology in mind. The material properties and the pertinent device physics are reviewed and relevant concepts are recapped briefly as necessary. The device design issues are described followed by a section on fabrication with particular focus on low-cost manufacture. The chapter concludes with a discussion of device models for circuit design.
43
2.1 Introduction
Table 2.1 GaAs FET materials properties [2, 3] Parameter
Si
GaAs
Al0.22 Ga0.78 As
In0.2 Ga0.8 As
Units
Band gap, Eg Conduction band step, Ec (wrt AlGaAs) Electron mobility, μ (undoped) Electron mobility, μ (Nd = 3E17 cm–3 ) Lattice constant Breakdown field, EBR Thermal conductivity, κ
1.12
1.424 0.17
1.698 0
1.14 0.31
eV eV
1400
8500 4000 5.653 4 × 105 0.44
3600
6900
5.655 (4–6) × 105 0.2
5.734 (2–4) × 105 0.05
Cm/V.s Cm/V.s ˚ A V/cm W/cm.C
2.1.1
3 × 105 1.3
Properties of GaAs and related compounds GaAs and its related compounds offer inherently good electronic properties for microwave semiconductor devices. Key material properties of GaAs and two common partner materials – AlGaAs and InGaAs – are given in Table 2.1 with the corresponding values for silicon provided for reference. The GaAs-based materials shown have direct band-gaps and high electron mobilities. High mobility results in lower access resistance and rapid acceleration of channel electrons to their saturated velocity over a short distance. These are important benefits for microwave devices. Further performance enhancement may be engineered by combining compatible materials with differing band-gaps to form heterojunction devices. Suitable combinations of materials allow very effective device structures to be manufactured that can provide a high degree of spatial control of the charge thereby allowing device performance to be optimized. AlGaAs has a wider bandgap than GaAs or InGaAs material. The resulting step in the conduction band when AlGaAs is used in conjunction with GaAs or InGaAs channel layers allows the current to be confined in the narrower band-gap material. The step in the conduction band edge between AlGaAs and InGaAs can be engineered to be considerably greater than that between AlGaAs and GaAs, and therefore the former combination provides a significantly higher degree of electron confinement. Heterojunction devices are only possible if the desired material combinations are sufficiently compatible to allow defect free growth across the crystal interfaces. The AlGaAs crystal has the same face-centered cubic structural form as GaAs with a lattice constant that remains very close to that of GaAs for all fractions of aluminum composition. Consequently Alx Ga1–x As is crystallographically compatible for all values of mole fraction x. Unfortunately, high values of aluminum composition x are unattractive for other reasons. The first limiting factor is the emergence of a high density of deep levels called “DX centers” [4] which are formed for x ≥ 25% and their density rises sharply for values of x above this value. For the case of InGaAs, high indium fractions are desirable as the conduction band offset and mobility improve with increasing indium content. InGaAs also has the same crystal form as GaAs, however the indium atom is relatively large compared to gallium with the result that the lattice constant of Iny Ga1–y As increases
44
GaAs FETs – physics, design, and models
with mole-fraction y. Consequently, when a thin channel layer of InGaAs is grown on a GaAs or AlGaAs crystal the InGaAs layer structure pseudomorphically adopts the template of the host crystal and this gives rise to a strained (compressed) layer. Naturally, there is a limit to this behavior and for a given thickness of the Iny Ga1–y As layer there is a maximum value of y which should not be exceeded in order to maintain an acceptable degree of strain [5]. For thicknesses or mole fractions beyond the critical limit then the crystal strain will be relaxed by the generation of misfit dislocations. For useful AlGaAs/Iny Ga1–y As devices with a channel thickness in the region of 10 nm, the maximum useable value of y is of the order of 20–22%. The above issues therefore constrain the molecular compositions that are possible for practical AlGaAs/GaAs/InGaAs devices and the compositions of AlGaAs and InGaAs given in Table 2.1 are chosen to satisfy the constraints described above and are typical of those used in practical device structures. Although the bulk material data given in the table does not strictly apply to thin or strained-layer structures with adjacent heterojunction interfaces affecting electron transport, the data shown is indicative and useful in conveying the basic principles. A further important attribute for a semiconductor for microwave applications is the ability to engineer substrates with very high electrical resistivity in order that RF signals carried by the tracks on the finished device should experience low attenuation. GaAs is naturally blessed in this regard due to the relative ease with which the material may be made into a good insulator. High-purity GaAs naturally has a high resistivity and is deemed to be semi-insulating (SI). The high resistivity arises because the Fermi-level is pinned very deep in the forbidden band by a naturally occurring crystal defect known as “EL2” (Electron Level 2). EL2 is a near mid band-gap electron trap which effectively clamps the Fermi-level so deep that very few free electrons or holes are available for a meaningful current flow. The natural resistivity of pure GaAs is typically 106 –107 -cm at room temperature. Substrate manufacturers further refine the degree of insulation by incorporating very small amounts of carbon during the crystal growth process. Carbon is a p-type dopant in GaAs and this is used to counter-dope the slightly n-type nature of pure GaAs. By compensating the high density of deep-donor EL2 defects with a low concentration of shallow acceptors from the carbon doping, the resulting resistivity can be fine-tuned. A typical commercial SI GaAs substrate exhibits a resistivity >108 -cm at room temperature. Of course no semiconductor material is ideal and GaAs and its related compounds come with some natural drawbacks that must be accommodated in the design of successful products. Notable disadvantages of GaAs are a relatively low thermal conductivity and the absence of a native oxide or similar passivant. The former issue limits the ability of GaAs devices to dissipate heat through the substrate thereby making thermal design an area of particular attention in the design of high-power products. The second issue of imperfect passivation gives rise to “slow-state” phenomena. A number of alternative terms are used here to describe the mechanisms and their effects. The terms: “traps,” “deep-levels,” “surface-states,” and “dispersion” are all commonly used. They refer to an undesirable feature of semiconductor devices where crystalline imperfections result in electron or hole states that are of intermediate depth in the band-gap such that they
2.1 Introduction
45
interact with the free carriers at noticeable levels but at rates which are slow compared to the intended transistor response. The result is that, in addition to the desired fast response, there follows a secondary slow tail that can compromise the device performance in a variety of ways. Effective control of dispersive phenomena in GaAs devices took many years to adequately resolve. Both of these topics are addressed in more detail in the sections to follow.
2.1.2
The Schottky barrier gate and the MESFET A class of transistor which is very suitable for GaAs is the Schottky-gate FET. This form of FET is a natural choice for GaAs because, unlike the MOSFET, the Schottky-gate FET can accommodate an imperfectly passivated surface. A host of device variations have followed since but the primary device of the family is the MEtal-Semiconductor FET or MESFET. This is essentially a Schottky barrier gate between two ohmic contacts on a layer of n-type semiconductor that forms a conducting channel. A Schottky barrier is formed when a metal is brought into contact with a semiconductor surface. Given a suitable difference in material work-functions, charge redistribution in the semiconductor occurs which depletes the adjacent semiconductor region of its mobile carriers (in the manner of a one-sided p +-n junction). The extent of the depletion depth is controllable by the amount of bias across the junction, and by this means a bias applied to the Schottky gate will modulate the available charge and hence the current in a FET channel. The rate that the junction can control the current limits the frequency response of the device. The limiting processes here are the RC time-constant of the gate junction and the time for the carriers to travel along the channel. The relevant key material properties are the mobility and the saturated velocity, and in high-mobility materials such as the GaAs family then the saturated carrier velocity is the dominating factor.
2.1.3
The Pf 2 limit The maximum power obtainable from a transistor manufactured from a given semiconductor material is dependent on the frequency at which the device is required to operate. The relationship of power with frequency is an inverse-square law, sometimes referred to as the “Pf 2 = constant” limit [6]. The factors that determine this relationship are the breakdown field, the saturated carrier velocity, and the physical size of the device footprint. The rms power density, P’ , obtainable from a sinusoidally driven transistor with the peak current density Jmax and voltage swing of Vmin to Vmax is given by: P =
Jmax (Vmax − Vmin ) 8
(2.1)
For a FET with its speed limited by the electron transit-time τ , traveling at the saturated velocity vsat , over characteristic length L, with a peak voltage limited by the breakdown
46
GaAs FETs – physics, design, and models
field Eb , and approximating Vmin to zero, then: Jmax E br L 8 Jmax E br vsat τ = 8 Jmax E br vsat = 16π f T 1 ∝ fT
P =
(2.2) (2.3) (2.4) (2.5)
where fT is the cut-off frequency. This same analysis is used to define the Johnson figure of merit for a semiconductor material JFOM [7]: E br vsat . (2.6) 2π Returning to equation (2.4), Jmax is crudely of the order of 500 mA/mm for most flavours of GaAs power FET irrespective of operating frequency. However, the ability of a FET to deliver Jmax across the entire gate periphery of a device diminishes as the frequency increases. This is primarily due to de-phasing of the input signal along gate fingers and across the multigate manifolds. Consequently, the remote regions of the device are driven progressively out of phase compared to the region in the immediate vicinity of the gate terminal thereby resulting in a net reduction in current delivered to the drain. In order for the phasing effects to remain invariant the physical device width must be scaled inversely with the frequency thereby giving a further 1/f contribution. In combination with equation (2.5) the overall effect on the total power, P, is then: JFOM =
P∝
1 . f T2
(2.7)
Clearly this is a simplification which omits a host of other factors such as RC losses, matching effects and thermal considerations, but it does capture the dominant limiting processes for a well-designed microwave power FET. Validation of equation 2.5 is given in Figure 2.1 which shows the rated breakdown voltages versus process fT for a variety of commercially available power FET processes of the varieties described in the next section.
2.1.4
Types of GaAs FET Four key GaAs FET variants are compared in Figure 2.2. The first type, shown in Figure 2.2a is the MESFET consisting of a Schottky gate controlling the current in a simple uniformly-doped channel. The first devices were ion-implanted structures and this approach became the standard manufacturing technique for GaAs transistors for a number of years. The MESFET was gradually refined with enhancements that included optimizing the doping profiles, the use of epitaxially grown layers, and the development of recessed gate structures for enhanced breakdown. The advent of “bandgap engineering” introduced AlGaAs as a partner material. A variety of heterostructure
47
2.1 Introduction
0.15 μm P
100 0.15 μm P
0.15 μm P
fT GHz
80
0.15 μm P
0.25 μm P
60
0.25 μm P 0.25 μm P 0.25 μm P 0.3 μm P
40
0.5 μm P
0.5 μm P 0.5 μm M
0.5 μm M 0.5 μm P 0.5 μm H
20
0
5
10
15
20
25
30
BVgd V
Figure 2.1 Breakdown voltage – frequency relationship for commercial power FET processes
(M: MESFET, H: HFET, P: pHEMT).
Figure 2.2 Key GaAs FET device types; (a) metal-semiconductor FET (MESFET) (b) doped-
channel heterojunction FET (HFET); (c) high-electron mobility transistor (HEMT); (d) pseudomorphic high-electron mobility transistor (pHEMT).
48
GaAs FETs – physics, design, and models
FET (HFET) developments then followed. The most straightforward HFET, depicted in Figure 2.2b, uses a wide bandgap AlGaAs spacer layer that spaces the GaAs channel from the gate [8–10]. This structure constitutes an effective power device with excellent power and linearity performance [11]. The transconductance achievable from this structure is relatively modest, however a valuable attribute is the near constant value with gate bias [8, 12, 13] that is achievable which is important for improving linearity. A number of developments of the HFET have been investigated, typically involving the use of InGaP as an alternative wide bandgap layer and with InGaAs as the doped channel layer. Reference [14] summarizes the benefits and drawbacks of an InGaP barrier layer including its absence of DX centers and that it is less likely to suffer surface oxidation. However, it is also has a less advantageous conduction band alignment than AlGaAs, and its use as an HFET barrier layer has not found widespread use. The further device developments described here focus on improvement of the channel properties so as to enhance the frequency performance. A key development was the AlGaAs/GaAs high-electron mobility transistor (HEMT) or modulation doped FET (MODFET) [15]. These are equivalent names for a device structure shown in Figure 2.2c which avoids doping the channel directly and instead dopes the adjacent AlGaAs layer. Mobile electrons then populate the GaAs channel but, at low fields at least, suffer much less scattering as the doping impurities have been separated from the conduction channel. HEMTs of this type have been superseded by the pseudomorphic device discussed below, but the concept was a key stepping-stone in the development of the microwave FET. The pseudomorphic-HEMT (pHEMT) shown in Figure 2.2d is a significant enhancement of the HEMT that introduces the benefit of an InGaAs channel [16–18]. InGaAs is a narrow band-gap material with excellent electron transport properties. The first incarnation of the pHEMT was a single heterojunction device with an AlGaAs barrier and charge supply-layer above the InGaAs channel. As material growth quality improved, a second AlGaAs layer beneath the channel was added which provides better charge confinement and hence higher current capability. The principle of modulation doping for the double pHEMT is illustrated in Figure 2.3 which shows the idealized band diagram for a pHEMT channel. However, as described above, InGaAs possesses a larger lattice spacing than GaAs and AlGaAs which limits the indium mole fraction to around 20%. This is a fairly modest indium fraction with the result that the exceptionally high mobilities that are the norm in the higher indium composition channels of the lattice-matched In0.52 Al0.48 As/In0.53 Ga0.47 As/InP HEMT devices are not achieved in GaAs-based structures. However, it should be realized that the key device benefit achieved in AlGaAs/InGaAs devices comes not from the fundamental mobility of the channel material, but rather from the separation of the carriers in the channel from their dopant atoms in the adjacent wide band-gap region. In this respect the increased conduction band step introduced by the use of InGaAs for the channel layer is very beneficial. Although the innate channel mobility is not improved above pure GaAs, it is substantially improved above doped GaAs and in AlGaAs/InGaAs pHEMT devices channel mobilities exceeding 6000 cm2 /Vs are obtained. For a MESFET with a directly doped channel then the achieved mobilities would typically be less than half that of
2.1 Introduction
Doping plane
49
Doping plane
+
+
_
_
EF
High mobility channel
AlGaAs
InGaAs
AlGaAs
Figure 2.3 Idealized pHEMT band diagram and modulation doping principle.
the pHEMT value. This improvement is comfortably sufficient to ensure that the device speed of the pHEMT is not significantly limited by the channel mobility. The semiconductor band-diagrams that correspond to the key device types of Figure 2.2 are given in Figure 2.4. The diagrams were calculated using a public-domain Poisson-Schr¨odinger equation solver [19] and the figure shows the equilibrium conduction and valence band solutions for the zero-bias condition together with the resulting electron concentration. The four band diagrams highlight the differences in the nature of the confinement of the channel electrons (electron density n) in the region between the Schottky barrier of the gate terminal on the left-hand side and the mid band pinning of the Fermi-level of the insulating substrate that occurs off-scale on the right-hand side of the plots. For the MESFET of Figure 2.4a the channel charge distribution is essentially that of the bulk semiconductor layer with an effective width modulated by the extent of the depletion of the Schottky gate. The application of negative gate bias further increases the energy difference between the Fermi-level and the conduction band and thereby extends the gate depletion reducing the available charge in the channel. For the situation where a positive bias is applied to the gate then by the reverse process the depletion depth reduces and the MESFET channel widens towards the gate. The use of negative, zero and positive gate biases for a MEFSET structure are shown in Figure 2.5a. The HFET structure with a band diagram shown in Figure 2.4b differs from the previous case due to the AlGaAs spacer layer beneath the gate, and the mobile charge from the doping in this layer is transferred to the (also doped) channel where it is energetically favourable to remain. A change to the gate bias voltage modulates the depletion edge in the same manner as the MESFET, but now the presence of the heterojunction provides a constraint on the minimum depth of the depletion layer edge. As shown in Figure 2.5b, under positive gate bias conditions the electron concentration remains largely confined by the heterojunction barrier and so, unlike the MESFET, the upper extent of depletion layer edge is constrained and does not move significantly towards the gate. The HEMT
50
GaAs FETs – physics, design, and models
Ec
Ef
0.6
−0.5 0.4
−1.0
Ev 0.2
−2.0
0
50
(a)
100 150 Depth (nm)
1.0
0.8
Ef
0.6 0.4
−1.0
Ev 0.2
−1.5 −2.0 (c)
0
50
100 150 Depth (nm)
0.2
n 0
50
100 150 Depth (nm)
200
200
1.0 x1018
0.5
n (cm–3)
−0.5
Ev
1.0
Energy (eV)
Ec
0.6 0.4
−1.0
(b)
0.0
n
Ef −0.5
−2.0
200
1.0 x1018
0.5
0.0
−1.5
n
0.8
n (cm–3)
0.0
−1.5
Energy (eV)
0.5
0.8
n (cm–3)
Energy (eV)
Ec
Energy (eV)
0.5
1.0 x1018
1.0
Ec
0.8
Ef
0.6
0.0
n
−0.5
0.4
−1.0
Ev 0.2
−1.5 −2.0 (d)
n (cm–3)
1.0 x1018
1.0
0
50
100 150 Depth (nm)
200
Figure 2.4 Zero-bias band diagrams and electron densities for key GaAs FET device types; (a) metal-semiconductor FET (MESFET); (b) doped-channel heterojunction FET (HFET); (c) high-electron mobility transistor (HEMT); (d) pseudomorphic high-electron mobility transistor (pHEMT).
structure of Figure 2.4c has a similar AlGaAs/GaAs heterojunction to the HFET just discussed but with the difference that the GaAs region is undoped. The band-bending of the junction creates a small well that is populated with carriers from the doped AlGaAs region. The mobility of the channel is intended to be that of the intrinsic material as the scattering from the dopant ions is eliminated now that they are spatially separated from the path of the mobile electrons. However, the confinement capability of this modest well is quite limited and this structure is therefore not effective as a power device. This issue is resolved in the pHEMT of Figure 2.4d with an InGaAs channel. Here the deeper conduction band offset between AlGaAs and InGaAs provides a high degree of confinement and the use of a double heterojunction with doping provided from both the upper and lower AlGaAs barrier layers achieves a high sheet-charge density. Also employed
51
2.2 Power device physics
Ec
0.0
Ef
0.6
−0.5 0.4
−1.0
Ev 0.2
−1.5
(a)
n 0
50
100 150 Depth (nm)
200
1.0 x1018
0.5
0.8 n (cm–3)
Energy (eV)
Ec
Energy (eV)
0.5
−2.0
1.0
1.0 x1018
0.8
0.0
Ef
0.6
−0.5 0.4
−1.0
Ev 0.2
−1.5 −2.0 (b)
n (cm–3)
1.0
n 0
50
100 150 Depth (nm)
200
Figure 2.5 Effect of variation of gate bias on device band diagrams and electron density for (a)
MESFET and (b) HFET. Solid line is the zero gate bias condition, long dash is for reverse bias and short dash is for forward bias.
here is the use of delta doping. In conventional doping the dopant atoms are included uniformly in the crystal at modest concentrations. However, in delta-doping the silicon dopant atoms are deposited in a continuous thin layer just a few atoms deep. This has benefits to device operation in that the dopant atoms are all very close to the channel ensuring maximum transfer of electrons into the channel – the so-called “modulation efficiency.” A further benefit is that it is easier to manage the MBE growth reactor to dope in this way.
2.2
Power device physics
2.2.1
The device I–V characteristic and loadline An idealized I–V characteristic is shown in Figure 2.6. The knee voltage, Vknee , is the voltage where the current saturates. Below this point the device is a voltage controlled resistor and above Vknee the DC current is saturated and ideally is independent of drain voltage. The maximum current Imax is typically defined just above the knee voltage and is the maximum current the device can supply before the gate junction becomes forwardbiased and starts to draw gate current. Another key parameter for a power device is the breakdown voltage as this limits the peak voltage that the device load-line can swing up to. The pinch-off voltage Vp is the gate voltage required to turn-off the drain current (typically to a threshold value of order 1 mA/mm). The detailed behavior of the FET I–V characteristic is determined by the combination of the Schottky gate depletion dependence on the gate-channel potential and the velocity-field characteristic of the source-drain channel. In reality this is a complex and interdependent 2D problem. However, for submicron gate GaAs-based devices where the electron velocity saturates under the gate over much of the I–V space then a useful
52
GaAs FETs – physics, design, and models
Imax Vgs > 0 Idss Ids
Vgs = 0 QA
Vgs < 0
QB V knee
Vds
Vgs = Vp Vmax
Figure 2.6 Ideal FET DC I–V characteristic with class A and B loadlines.
simplified description can be considered. In this model the current is determined by the saturated electron velocity and the number of available carriers. The fraction of the maximum channel current that is available is determined by the extent that the gate depletion region extends down into the channel. An important benefit of the saturated velocity mode of device operation is that over the main part of I–V space the drain current is generally a more linear function of gate voltage. Good linear behavior may be pictorially observed from the family of Id –Vd curves that make up a device I–V graph having approximate equal spacing as Vg is varied. Such behavior is unlike the long-gate or “gradual channel” case of the traditional JFET where saturation is a low-field and constant mobility process resulting in a square-law dependence of drain current on gate voltage [3, 20]. It is readily apparent that a good power device has high peak current Imax , a high breakdown capability, a low Vknee and equally spaced curves on the I–V characteristic. Figure 2.6 illustrates the maximum power class A and class B load-lines that may be supported on the idealized I–V characteristic. The class A loadline is the simplest to understand and the figure shows the I–V locus swinging from the peak current value Imax and minimum voltage value Vknee to a maximum voltage at zero current limited by the device breakdown. The resultant quiescent bias point is QA . The maximum output power for the idealized class A situation is given by equation (2.1). The class B loadline is achieved by reducing the operating current to bias point QB . The same load resistance is required and a similar maximum power is delivered but with higher efficiency achieved due to a reduced DC dissipation. For a real device the I–V characteristic departs from the ideal in a number of important ways. Figure 2.7 highlights some key features of a more realistic DC I–V characteristic which would be observed using a slow-sweep curve tracer. The figure illustrates “thermal droop” where self-heating of the device causes a reduction of electron velocity and mobility. The spacing of the lines of constant gate voltage is also no longer ideal and exhibits compression at the limits of the gate voltage range.
2.2 Power device physics
53
Imax
Vgs > 0
Idss Ids
Vgs = 0 Vgs < 0
Vknee
BVds
Vds
Figure 2.7 Practical FET DC I–V characteristic exhibiting breakdown, thermal droop, and
transconductance compression. 100
DC Q A (6V, 0V) Q AB (6V, -0.3V) Q B (6V, -0.6V)
80
60 Id mA
QA
40
Q AB
20
0
QB
0
1
2
3
4
5
6
7
Vd V
Figure 2.8 Measured pulsed I–V characteristic for 0.25 μm pHEMT process at class A, AB, and B bias points.
2.2.2
The dynamic I–V characteristic A further departure from the ideal characteristic occurs when the dynamic response is considered. Figure 2.8 shows typical pulsed I–V characteristics that have been measured with a commercial system [21, 22]. A set of dynamic I–V plots are overlaid onto a conventional DC I–V measurement. In the pulsed case the device is biased at quiescent bias points indicated on the figure and short, low-duty cycle pulses from this bias point are then used to explore the I–V plane and map out the characteristic. The bias point should be chosen to be typical of the intended operating point with the aim that the measured dynamic I–V will replicate the RF behavior of the device. As is apparent in Figure 2.8 the dynamic behavior differs significantly from the static case. The difference
54
GaAs FETs – physics, design, and models
is, for the most part, due to the presence of slow traps in the semiconductor. Traps are deep-level states that can capture and retain electrons or holes for extended periods. The possible causes and locations are numerous [23–26] and include traps at the un-gated semiconductor surface and the substrate interface, DX levels in AlGaAs, and free ions in passivating materials. A concise overview of the phenomena for both GaAs and GaN devices is given in reference [27]. The traps are energy states that have energies sufficiently deep into the semiconductor forbidden band that the likelihood of a carrier interacting with the state is relatively small and when a carrier does occupy such a state then a further low probability event is needed in order for it to be released again. The result is that the lifetime in a deep-level state can be quite long, and time constants of microseconds to milliseconds are commonplace. The impact of the trapped charge in the deep states is that the associated field affects the passage of the free carriers in the channel thereby modifying the device characteristic. Because the capture and release time constants of the traps are very long compared to the period of a microwave signal, the RF (carrier) signal and trap occupancy do not directly interact. However, the trap occupancy is affected by the mean bias condition giving rise to the situation that the dynamic I–V changes slightly as the mean bias position changes. A useful way to think of this is that there isn’t a unique and definitive I–V characteristic for a particular FET, but rather there is a slightly modified one for every mean bias condition. A helpful physical model is that of the field associated with the trapped charge acting as a slowly varying “virtual gate” that modifies the effect of the physical gate. A particular area of concern for trapping effects is the semiconductor surface. Without a suitable passivant material there are inevitably a large number of surface states present. Indeed, it is worth noting that the density of available surface states is typically comparable with the intended doping of the device channel. It therefore becomes an important device design task to minimize their impact on the device performance. This is achieved by such measures as keeping the etched surface area to a minimum, maximizing the distance of such areas to the channel and the use of charge-screening layers to isolate the channel from changes to the surface potential. In contemporary optimized FET structures the trapping effects have been addressed to a substantial degree. Improved materials growth quality, improved wafer processing techniques, and advances in device design techniques have reduced the density of available states and mitigated their impact on the device response. Nevertheless, discernable slow-state effects are the norm and these effects have an impact that can limit the device performance and introduce difficulties in device characterization and modeling.
2.2.3
The consequences of trapping effects The physical processes described above give rise to a multitude of observable device effects to be minimized by the device designer and accommodated by the circuit designer. The effects are summarized in the following paragraphs. Reduced output power: For devices operating as an amplifier and biased as such, the resulting equilibrium trapping state reduces the peak device current due to increased surface depletion and increases the effective knee voltage by increasing the dynamic
2.2 Power device physics
55
Id
Time (a) Gate lag
Time (b) Drain lag
Figure 2.9 Typical GaAs FET gate and drain lag responses; (a) gate lag; (b) drain lag.
channel access resistances. These modifications to the device I–V are illustrated in Figure 2.8 and reduce the maximum output power that a device can deliver. Gm and gds dispersion: Measurements of device transconductance (gm = dId /dVgs ) and output conductance (gds = dId /dVds ) with frequency are observed to undergo a transition from their DC values, and this variation with frequency is called dispersion [25, 26, 28]. The transition frequency range is typically in the 1 kHz to 1 MHz range with the transconductance decreasing from the DC value and the output conductance increasing from the DC value. Historically, dispersion measurements were a primary assessment tool for device trapping effects before pulsed I–V assessment came to the fore. For contemporary GaAs power devices transconductance dispersion is usually small and the dispersion of the output conductance is the dominant phenomena. This is clearly observed in FET DC I–V characteristics such as Figure 2.8. The spacing of the lines of constant gate voltage has remained largely invariant indicating minimal difference in transconductance. However the increase in the slopes for the pulsed characteristic demonstrates the increased output conductance experienced by a dynamic stimulus. It should be realized, however, that the difference between the DC and dynamic I–V slopes does not indicate that slow-states have compromised the output conductance for the RF signal. It is more accurate to view the dynamic I–V measurement as revealing the underlying “true” output conductance that is obtainable from the short gate structures that are typically employed in GaAs-based devices. For the DC case, the aforementioned underlying I–V is modified by changes in the equilibrium trap occupations which evolve with the (slowly varying) bias voltage in such a manner so as to supplement the action of the gate and so reduce the resulting output conductance. The mechanism can be visualized such that as the drain voltage is increased then the amount of trapped charge in the vicinity of the gate also increases and the field associated with the trapped charge acts in concert with that of the Schottky gate bias thereby helping to suppress the increase in drain current that would otherwise occur. Gate and drain lag: Gate and drain lag are terms that describe the delayed response of the drain current to changes in the gate and drain voltages, respectively [26, 29–32]. Typical gate lag and drain lag responses are illustrated in Figure 2.9 and show how the dominant fast response is followed by a slow tail. The tail can persist for timescales
56
GaAs FETs – physics, design, and models
ranging from a few microseconds to milliseconds depending on the detail of the device construction and the fabrication techniques employed. The plots relate to the same physical test as is performed in the pulsed I–V plot of Figure 2.8; however, the x-axis on the plot is now time rather than drain voltage and the traces show the time evolution of just one sample point on that I–V plot. With gate-lag the drain voltage is held constant and the gate voltage is stepped from the quiescent value to the required sample point, and with drain lag the gate voltage is held constant and the drain voltage is stepped. Memory effects: In addition to the modifications to the device characteristics described so far, the dispersion mechanism also results in hysteresis in the device response, or in other words the device can exhibit a memory of a recently applied stimulus. As discussed, the trapped carrier population is a function of the mean bias condition. For a highfrequency continuous-wave signal where the period of the RF is short with respect to the trap time-constant then an equilibrium trap occupation will be achieved and a stable dynamic device characteristic is observed. However, for low-frequency signals or, more likely, an RF carrier modulated with a modulation frequency that is comparable with the trap time-constant, then the trap occupation can be influenced by this low-frequency variation. The result is that the RF characteristic can be subtly modified by the lower frequency component of the signal thereby giving a dependence on the recent history. Of course this is a familiar problem for all semiconductor devices even if trapping mechanisms were to be completely controlled as thermal time constants have similar consequences. The impact of trapping effects on a modulated signal is simulated in reference [33]. Inaccuracy in large-signal models: Traditional device models are based on I–V characteristics measured at DC. However, as has been shown, the trapping effects give rise to dynamic I–Vs which are noticeably different from the static one. This means that models which simply use the static characteristic do not accurately predict the device performance. Invariably, the real device will provide less power and exhibit less gain than the DC-derived model. Techniques for the generation of improved large-signal models are addressed later in the chapter. Increased breakdown voltage: So far the list has given a series of detrimental effects that arise from the presence of surface states. However, they do have an important beneficial impact on breakdown voltage. As will be discussed in more detail in the next section, the associated surface charge located in parallel with the channel has the positive benefit of assisting to spread the electric field in the gate-drain region over a longer distance thereby reducing the peak field developed and hence increasing the device breakdown voltage. Kink effect: The list ends with a phenomenon that has long been observed where traces on the I–V characteristic can exhibit a kink to a higher drain current as if the gate bias was suddenly adjusted higher as the drain voltage is swept. Similar effects have been reported in various kinds of semiconductor transistor, such as silicon MOSFETs, GaAs-MESFETs, doped channel HFETs, AlGaAs/InGaAs-HEMTs, and InAlAs/InGaAs-HEMTs [34]. Various mechanisms have been explored and it is clear that there are a number of different kink-effect processes that may be present depending on the detailed device
2.2 Power device physics
57
D BVgd BVds
G BVgs
S Figure 2.10 Breakdown voltage definitions.
construction. It is possible to observe mechanisms that affect the DC characteristic but are not observed at RF [35], while for other structures they may be observed also or exclusively in the dynamic characteristic [34, 36]. The possible mechanisms that may be involved include field ionization of traps where an increase in the drain voltage induces release of trapped electrons thereby allowing the associated channel depletion to lessen [34, 37]. Other processes involve the presence of hole charge generated by impact ionization. Here a build up of hole charge at the source end of the gate can give rise to a parasitic bipolar effect that can cause current injection thereby reducing the effective source resistance [38]. It is also possible that associated change in the channel potential reduces the effective pinch-off voltage [39]. A further mechanism suggested by 2D simulation is for impact ionization generated holes to interact with and partially discharge surface electron traps thereby widening the channel [40]. Other simulations indicate a possible contribution from redistribution of the 2D electric field when the lateral extension of gate depletion reaches the edge of the recess [36].
2.2.4
Device breakdown The three breakdown conditions generally quoted for FETs are the Gate-Source, GateDrain and Drain-Source breakdown voltages BVgs , BVgd , and BVds , respectively, as illustrated in Figure 2.10. The typical definition employed is the voltage for which a current of 1 mA/mm of gate width is observed. BVgs and BVgd are so-called two-terminal tests (i.e., with the third terminal floating) and, with the notation used here, are negative. In power devices the gate is usually positioned asymmetrically to optimize the gate-drain breakdown value. BVds is a three-terminal test with the gate bias set to a sufficiently negative value so as to ensure that the device is pinched off. BVds is positive. It is common for only two-terminal tests to be quoted on data-sheets or in wafer acceptance criteria. However, the three-terminal drain-source breakdown is also an important parameter, particularly so for power devices, as this configuration corresponds to how the device is actually used. Different physical mechanisms are generally observed for the breakdown processes experienced under two and three-terminal conditions with the result that BVds can be significantly less than might be expected from a simple consideration of the
58
GaAs FETs – physics, design, and models
combination of the gate-drain breakdown and the applied gate voltage (i.e., Vgs -BVgd ) [41].
2.2.5
Breakdown mechanisms and optimization Significant attention has been paid to the optimization of breakdown performance in order to optimize output power, and breakdown performance for power devices has been developed to the point that power GaAs FET devices are usually thermally limited rather than being limited by device breakdown. A number of physical processes are involved in the evolution of the breakdown process and depend on the precise device construction and on the operation of the device. The key processes described here are [42–47]: r thermionic field emission (TFE) over the reverse-biased gate barrier; r tunneling through the gate barrier which narrows as the device is heavily reversebiased; r impact ionization in the channel; r parasitic bipolar effect; r electric field spreading due to the surface potential. These processes can all operate in concert to give a variety of interesting behaviors. A typical evolution of a breakdown event begins in a high-field low-current condition with increased gate-drain leakage caused by field-emission of current over the reverse-biased gate-drain barrier. It is normal for the field to be so high that the barrier becomes thinned which causes the field-emission to be enhanced by quantum-mechanical tunneling. Energetic electrons can then find themselves injected into the high-field channel with excess energy. The electrons will relax their energy by various means and one possibility is impact ionization where electron-hole pairs are created caused by collisions with the lattice. Impact ionization is self-reinforcing in a high-field channel as the electron-hole pairs produced can go on to seed other ionization events in an avalanche multiplication process. Breakdown tends to be a fairly gradual process at first as the applied voltage is increased and steadily over several volts the total breakdown current becomes progressively dominated by the impact avalanche component. Detailed studies analyzing this behavior in GaAs FETs have used the differing temperature dependence of the TFE and impact ionization processes to identify the relative contributions.1 The picture so far then is that of energetic electrons defeating the gate barrier, seeding impact ionization and the breakdown current running away with a positive feedback mechanism. However, this is not necessarily quite the end of the story. On some devices it is possible to observe a “snap-back” effect where, as a certain current threshold is crossed, the device can no-longer support the breakdown voltage resulting in the breakdown characteristic of Figure 2.11. In this event then the voltage collapses to a low value and the device current rises markedly [48]. This process may or may not be fatal depending on the device 1
TFE has a positive temperature coefficient which is to say the current over the barrier increases with temperature [42, 46]. Conversely, in GaAs devices, the temperature dependence of the ionisation coefficients acts in the opposite sense.
59
Id
2.2 Power device physics
Snap-back
Impact ionization TFE/Tunnelling
Vd Figure 2.11 Breakdown snap-back caused by a parasitic bipolar effect.
and the circuit. The mechanism giving rise to the snapback is a by-product of impact ionization where the resulting equilibrium hole concentration can induce a “parasitic bipolar effect” (PBE). Once created, the ionized holes can follow a number of paths: They can be collected by the gate terminal and add to the gate current, they can escape into the substrate, or they can flow to the source. A common understanding of the parasitic bipolar effect is that the holes collecting in the substrate act as a parasitic back gate and have the effect of opening the channel “from the back” [49, 50]. However, in a heterojunction FET holes tend to be confined in the channel by the valence band well and in this case may not readily flow into the source contact or substrate. Instead they will drift to the source region and an equilibrium hole charge is developed there. This localized positive charge favours injection of electrons from the source contact into the channel thereby inducing an increased drain current by another means [49]. Parasitic bipolar effects are well known in silicon devices [51, 52] but appear less so in the GaAs community.
2.2.6
Comments on GaAs FET breakdown ratings GaAs FET circuits are often designed to operate quite close to the transistor rated breakdown limits with safety margins less than are typically employed with other technologies. A number of factors make this a safe thing to do. The nature of GaAs FET breakdown is such that it is typically quite gentle in its onset and results in significant circuit performance reduction before device degradation is observed [43]. Also, the typical dominant aging mechanism of devices operating under high-field conditions is a hot-electron induced surface degradation. The surface damage leads to a subsequent increase in trapped surface charge causing increased spreading of the electric field and hence an increase in the breakdown voltage [53]. This so-called “breakdown walkout” provides a fail-safe mechanism where the failure process effectively hardens the device against further degradation.
60
GaAs FETs – physics, design, and models
Lg
Cgd
Rg Cgs
Rd
+
Ld
Rds
--
Cds
Ri
gm
Rs
gm = gm0.e
−jωτ
Ls
Figure 2.12 Common GaAs FET equivalent circuit network.
A further relevant phenomenon is the observation that the RF breakdown of GaAs FETs can be frequently higher than their DC breakdown data would suggest [54]. The literature is not comprehensive but the perception of devices safely operating at values not commensurate with their DC breakdown values is a common one. A popular explanation is that of avalanche delay [55], which can inhibit the onset of breakdown because the period of a microwave signal is typically comparable with the characteristic delays of the avalanche process. An attempt to quantify the effect was given by Shrikov [56] who measured a modest one volt enhancement to the drain-source breakdown. Snap-back effects (if present) may also be too slow to respond to the RF signal which in that case could be expected to give an apparent RF breakdown enhancement.
2.2.7
The FET equivalent circuit The usual small-signal equivalent circuit network used to represent a GaAs FET is shown in Figure 2.12. The prime elements are the voltage-dependent drain current generator of transconductance gm0 and the gate capacitance Cgs across which the controlling voltage is developed. The remaining elements are unavoidable parasitic components whose presence degrades the device performance and so whose values are minimized as much as possible in the device design and the fabrication approaches employed. Figure 2.13 illustrates the mapping of the equivalent circuit onto the physical structure. The parasitics which are commonly particularly significant are the shunt feedback capacitance Cgd and the access resistances Rg , Rs , and Rd . The gate and source resistances Rg and Rs compromise gain by reducing the fraction of the input signal that reaches the intrinsic gate. The source and drain Rs and Rd compromise output power and efficiency. The source inductance, Ls , is often a critically important parasitic which, together with Rs , gives rise to series feedback compromising device gain. However, the value of Ls is dominated by the interconnection network including the via to ground and therefore not shown on the cross-section view of Figure 2.13. The remaining parasitics usually have a lesser impact though can still be significant.
2.2 Power device physics
S
G
n+
D n+
Rg
Ledge
Ledge Rs
Cgs Cgd Ri
Channel
61
Rd
gm Rds
Substrate
Cds
Figure 2.13 Correspondence of GaAs FET physical structure and equivalent circuit network.
An area of particular note in the mapping of the equivalent circuit is the network of elements used to model the depletion region. The depletion region is a single entity that delineates a single region of space-charge. However, it is accessed by all three device terminals and so in the equivalent circuit the depletion region must therefore have a connection to the three terminals. This is achieved in the lumped model by the use of two capacitance elements Cgs and Cgd . The gate-source capacitance, Cgs , connects across the depletion region from the gate metal to channel forming the main contributor to the input capacitance. The gate-drain capacitance, Cgd , connects from the gate metal across to the drain-side of the depletion region and forms a shunt feedback capacitance. Modulation of gate depletion region edge requires charge to be added to or removed from the depletion region. In the low-field region this process is dielectric relaxation [57] modeled by the Cgs -Ri arrangement where the gate-charging resistance, Ri , represents the nondepleted low-field channel resistance of the channel under the gate. In the highfield region the modulation of the depletion region edge is limited by the finite saturated velocity of the channel carriers limiting the rate that carriers can be supplied or be swept away. There is therefore a time delay given by the product of the length of the saturated region and the carrier velocity that limits the speed of this process and this gives rise to a delay term,τ , for the current generator equivalent circuit element.
2.2.8
Device gain and figures of merit The key gain quantities for a microwave FET are illustrated in Figure 2.14 which shows a set of typical commonly used gain curves for a pHEMT device. The most straightforward microwave gain quantity is the power gain in a 50 system. In Figure 2.14 this is shown as S21 . This curve shows a one-pole response dominated by the 50 source impedance and the device input capacitance. Once above the 3 dB corner frequency S21 falls at 6 dB/octave. In order to achieve a useful gain performance the device must be presented with more appropriate terminating impedances. The remaining curves on the plot are the
GaAs FETs – physics, design, and models
U
Gain (dB)
62
MSG
S21
h21
MAG
log(Frequency Hz)
fT
fmax
Figure 2.14 Microwave gain curves and figures of merit.
quantities generally employed to indicate what performance is achievable from a device for specific terminating conditions. h21 : The hybrid parameter h21 is the current gain into a short-circuit load. The intersection of this curve with the unity gain axis is a key device figure of merit called the transition frequency, fT which is discussed in more detail below. Gmax: The Gmax curve is the composite plot of the maximum available gain and maximum stable gain curves (MAG and MSG, respectively). MAG is the gain obtained when the input and output are both simultaneously matched for optimum gain. This quantity may only be determined when the device is unconditionally stable. Where it is possible that a combination of source and load impedances will cause the device to oscillate then MAG is undefined and so instead the MSG is plotted. MSG provides the theoretical gain obtained immediately before oscillation occurs and has a slope of 3 dB/octave. The slope of MAG is of the order of 6 dB/octave but varies due to the variation of the optimal termination conditions which are frequency dependent. Figure 2.14 shows just one transition frequency between MSG and MAG. In highperformance FETs it is quite common for there to be a further transition at higher frequencies back to MSG as the device becomes conditionally stable again. In practice, Gmax can be thought of as the best gain obtainable but its interpretation is complicated by the conditional stability issue. U: A somewhat theoretical gain quantity often favoured by device specialists is the Unilateralized gain “U” [58], also known as Mason’s invariant gain [59]. For this quantity the feedback has been perfectly neutralized to give a gain measure that is free from complications of the effects of conditional stability. fT and fmax : Two popular figures of merit for RF devices are fT and fmax . They assist in the ready assimilation of a device’s performance and to allow convenient comparisons of different devices. The transition frequency fT is the unity gain frequency of h21 – the
2.3 Device design
63
frequency for which the current gain of the device has fallen to 0 dB. fT is a useful and reasonably unambiguous figure of merit that is convenient to measure and relates directly to the primary equivalent circuit elements that determine the device RF gain. The elements concerned are the intrinsic transconductance of the gate gm0 and the associated capacitance Cgs that limits the rate at which the input voltage may be varied. The usual approximate expression for fT is given in equation (2.8). fT ∼
gm0 2π (C gs + C gd )
(2.8)
A significant weakness of fT as an indicator of device performance is that it neglects other important parasitics, and in particular takes no account of device input resistance. This is because h21 is the current gain for the case of an input current generator with infinite output conductance. It is therefore quite possible for a device with a high fT rating to actually have a relatively poor power gain. Clearly however, a device chosen for a power amplifier should have a low input resistance and high power gain. A figure of merit that addresses this requirement is fmax , the so-called “maximum frequency of oscillation.” This parameter is the frequency for which the power gains U and Gmax have fallen to 0 dB, as a power gain of unity is the minimum gain required for a device to be able to oscillate (see Appendix 2.1 and reference [60]). The expression for fmax can be determined for the network of Figure 2.12 [61] and is given in equation (2.9) which illustrates the relative significance of the various parasitic components. f max =
fT
2 (Rg + Rs + Ri )/Rds + 2π f T Rg C gd
0.5
(2.9)
A difficulty with fmax is that there is no universally adopted approach to its determination and it is commonly overestimated. This is discussed in Appendix 2.1 where recommended methods for the practical determination of fT and fmax are described.
2.3
Device design
2.3.1
Power device design The process of optimizing a power device comprises three main steps: (a) designing the basic FET device structure, (b) designing the power cell where a set of gates are assembled to form a stackable unit, and (c) forming a composite device from a set of cells to provide a device with the required power for a given requirement.
2.3.2
FET channel and recess design Here the task is essentially to select the FET type and gate length appropriate for the operating frequency and to optimize the current density capability and breakdown voltage without unduly compromising the other competing specifications such as gain and linearity. Key areas of attention are the epi-design and the gate recess.
64
GaAs FETs – physics, design, and models
Epi-layer design: GaAs FET epitaxial layer structures vary in complexity from the simplest uniformly-doped MESFETs [62], through reasonably straightforward multilayer designs for HFETs [8], to complex many-layer quantum-well structures for pHEMTs [63]. In uniformly-doped MESFETs the epi-layer design choices are fairly limited. High power requires high current which is achieved by a high doping density and/or a thick channel. Both of these factors have limits. For the case of doping density, then as this parameter is increased the breakdown voltage falls due to the increased electric field that is developed. In addition, the semiconductor mobility is degraded due to increased scattering associated with the dopant atoms. Alternatively, as the channel thickness is increased then, for a given gate length, the output resistance falls and this can compromise the device’s ability to deliver current into the desired load resistance. To prevent this problem the gate aspect ratio (the ratio of gate length to channel depth) should be maintained to be of the order of five or more in order to ensure a satisfactory output resistance. The aspect ratio constraint presents no issues for longer gate devices but for higher frequency applications requiring submicron gate lengths, then the restriction on channel depth forces high levels of channel doping to achieve the desired current density thereby resulting in a compromised breakdown voltage and undesirable channel mobility. MESFETs with tailored doping designs are employed with the aim of achieving improved device characteristics such as linearity and noise. More ideal device performance is achieved by concentrating the doping deeper into the device with the objective of achieving, for example, a step-doped or similar profile. A desirable outcome from this measure is to introduce less variation in depletion depth as the channel is modulated thereby resulting in a more constant device transconductance and gate capacitance. However, this benefit comes inevitably at a cost of reduced current density for a given peak doping and gate length. Such devices therefore tend to have lower current capabilities than uniformly doped FETs. The limiting case for a step-doped profile is the HEMT which seeks to restrict the current flow to a narrow plane at a fixed depth into the semiconductor. The HEMT achieves this while being substantially free from the mobility degradation associated with increased doping densities as described above for the MESFET. This is because in the case of the HEMT the current-carrying channel is physically separated from the donor ions and so much higher doping levels can be used without adversely impacting the mobility. GaAs-based HEMT structures typically achieve sheet-charge densities above ˚ would correspond to an 1.5 × 1012 cm−2 which, for channel depths of order 100 A, 20 −3 equivalent bulk-doping density in excess of 1 × 10 cm . Even if such a bulk-doping density was a practical proposition (which it isn’t as this density is considerably greater than the solubility limit of the n-type silicon dopant in GaAs), the mobility would be enormously degraded and not be more than a few hundred V/cm2 s at best. In the HEMT the doping limit now becomes that for which the associated electrons can be effectively contained in the heterojunction channel. For the AlGaAs/GaAs HEMT the difference in band-gaps between the two materials is relatively modest with a commensurately limited degree of charge confinement. Consequently this device has a modest peak current capability. However, as shown in Table 2.1 the AlGaAs/InGaAs pHEMT has
2.3 Device design
Gate metal Inner recess
65
Outer recess
n+
n+ Ledge Cap layer Channel
Figure 2.15 GaAs Power FET recess structure.
a much more substantial band-gap difference with the result that the pHEMT device variant allows a high current density of order 500 mA/mm to be maintained for all practical gate-lengths. The gate-recess design: A most significant advance that allowed the GaAs FET to be developed into a useful power device was the development and optimization of the double gate-recess. The earlier devices had a simple single recess that was typically created by simply etching into the channel until the desired current was achieved. At this point the gate metallization would be deposited within the recessed region. The breakdown voltage is enhanced by increasing the width of the recess, thereby giving an increased separation between the gate metal and the drain n + contact region and reducing the peak field. However, in practice the increased expanse of free surface typically results in poor device performance with significantly reduced current and slow-state effects. The solution for this problem is the double recess [64–67] depicted in Figure 2.15. Here the gate is deposited in a small inner recess that lies within a larger outer one. In this construction the outer recess is larger on the drain side to provide the gate depletion with room to extend towards the drain as the gate-drain voltage is increased thereby reducing the peak electric field developed. In contrast to the single recess structure, the variations in surface depletion on the extended etched surface caused by changes in trap occupations now usefully attenuated by virtue of increased physical separation from the channel. This attenuation is generally further enhanced by the inclusion of moderate levels of n-type doping which act as a charge screen. Considerable attention has been paid to optimizing GaAs FET breakdown in the recent past. A significant driver has been cellular base-station PAs requiring a few hundred watts of peak power at 0.8–2.1 GHz. For a technology that hitherto operated power amplifiers with a typical drain bias of the order of 6–8 V, this application provided a significant challenge. Initial attention focused on optimization of the design of the epi-layers and of gate-recess structure. Figure 2.16 shows the impact of one design
GaAs FETs – physics, design, and models
50
BVdg BVds
40 Breakdown Voltage (V)
66
30
20
10
0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
Lgd (micron)
Figure 2.16 Breakdown voltage dependence of gate-drain voltage separation.
variable, namely the length from the gate to the edge of the outer recess on the drain side (Lgd ), on breakdown voltage for a 0.5 μm gate power device. The two-terminal breakdown BVgd is seen to be readily controlled by the size of the recess but the three-terminal breakdown BVds exhibits a more limited dependence. The figure provides a reminder that even though BVgd is the normally quoted breakdown voltage measurement, in reality the device operates in a three-terminal condition and for a power amplifier the drain-source breakdown voltage, BVds cannot be neglected. Fortunately, in practice, commercially available device power processes are appropriately designed and the quoted BVgd data is generally a good indicator of the breakdown capability in a power amplifier configuration. Optimization of the recess gave a significant step forward in increasing the breakdown voltage but its ability to spread the field is limited. To improve further a greater degree of field spreading is required. Some attempts were made to employ reduced surface field p-layers as used to great effect in silicon LDMOS [69, 70], but most focus has been on the use of field-plate electrodes located in the gate-drain recess area [68]. Field-plates: As discussed above, the charge trapped in deep-levels on the surface of the gate recess provides a naturally occurring assistance in the field spreading. The use of field-plates makes it possible to engineer a more substantial effect and this has been an area of significant attention for higher voltage GaAs devices. In this context a field-plate is an extra electrode positioned on an insulating layer in the high-field gate-drain recess region. Its function is to provide a controlled potential that acts to suppress the peak field at the gate edge. The simplest construction is the gate-connected
2.3 Device design
67
field-plate investigated by a number of groups [71–75]. As the normal shape for a power FET gate is a T-shape (as discussed in Section 2.3.3), the simplest form of field-plate construction is merely an extension of the top of normal T-shaped gate in the direction of the drain to form a so-called -gate (“gamma-gate”). The field-plate approach can be very effective in increasing the breakdown field, and research work achieved device operation at and beyond a drain bias voltage of 28 V. Unfortunately however, the impact on the device gain is significant [76]. Both the gate-source and gatedrain capacitances are compromised making the technique unattractive for frequencies above L band. A more recent development has been the source-connected field-plate [77]. This configuration requires a more complex manufacturing process but has the great benefit of shielding the gate-drain coupling thereby reducing Cgd and actually improving Gmax. The input capacitance is still significantly affected and the device fT is consequently compromised, however for applications such as cellular communications for which the technology was targeted then this additional input capacitance can be accounted for in the input matching circuit. Significant effort was deployed on fieldplate technology for GaAs devices and with notable success. However, the efforts were largely overtaken by wideband gap technology such as GaN which has now become the preferred technology for high-voltage RF FET devices.
2.3.3
Power cell design Gate width: Power FET cells invariably require as much gate periphery as possible and a key factor which inhibits increasing the width2 of the gate finger is the impact of the cumulative loss and delay of the gate signal as it travels along the gate electrode [78–80]. The gate electrode is depicted in Figure 2.17a which shows a discretized model of a loaded transmission line. The gate metal is modeled by the incremental series resistance and inductance elements dRg and dLg with the associated gate capacitance elements dCg . The gate voltage waveform applied to the gate finger propagates along the structure and is progressively attenuated as it travels thereby reducing the overall device gain. In addition the finite time to traverse the structure further degrades the signal by introducing a progressive phase delay that adds to the overall signal degradation. In order to improve matters attention must be paid to the gate cross-section as the short gate length required for fast transit along the channel length would otherwise result in a reduced cross-sectional area thereby providing high series resistance and inductance along the finger width. The solution widely employed as shown in Figure 2.15 is to form a T-shaped gate to improve the propagation along the gate metal while still maintaining a short gate contact length for good gain performance. Power cell manifold issues: Having optimized the unit finger the next task is to design an assembly of unit fingers suitably combined so as to achieve an optimal power performance that has scaled well with respect to the innate performance of the unit finger [79–81]. Figure 2.17(b) illustrates the principle for an example network of four 2
By convention, the width of a gate is the long dimension perpendicular to the channel direction and the length of a gate is the dimension in the direction of channel current flow.
68
GaAs FETs – physics, design, and models
dRg Gate Terminal
dLg
dRg dLg
dCg
dRg dLg
dCg
dCg
(a)
Drain Gate
(b)
Figure 2.17 Power FET cell; (a) gate finger equivalent circuit; (b) gate manifold with four fingers.
fingers combined to make a modest multifinger cell and shows the fingers connected by an assembly of short transmission lines. As fingers are added then the overall device gain is further impaired due to the successive phase delay contributions experienced by the additional fingers. At first thought it might be imagined that this phase difference could be corrected by the use of an alternative layout which collected the drain currents with compensating delays in the output circuit. However, this neglects the impact of the high capacitive loading on the input network by the gate capacitance resulting in this network being relatively slow compared to the output network. The high impedance of the drain side of the device means that the output current contributions are collected with relatively small phase differences compared to the cumulative phase differences in the input that build up from the interfinger and along-finger delays. Another approach to maintain the gain would be to minimize the finger–finger phase delay by designing the device with fingers as close together as possible. Unfortunately the heat generated in power FETs is usually substantial and so the design freedom here is usually quite limited in order to maintain an acceptable channel temperature required for reliable device operation. Common-lead inductance: As the gate periphery is increased to achieve higher current capability then the importance of the inductance of the source connection becomes
2.3 Device design
D G
(a)
D
D G
69
G
(b)
(c)
Figure 2.18 GaAs FET power-cell layout variants; (a) gate-side source vias for high packing density; (b) source-bridge for reduced inductance of smaller cells; (c) individually via’d source stripes for highest frequency performance.
increasingly significant. The negative feedback generated by the common-lead inductance can be a significant factor reducing the gain of the power cell and close attention to minimizing its value is often required. A very common topology for power FETs is shown in Figure 2.18a which provides two vias per cell. The vias are located to the side of the device and connection to the source fingers is made by an air-bridge over the gate manifold. This layout is very effective for power cells as it allows multiple cells to be efficiently stacked in a row for a high density of fingers. The disadvantage of this configuration is that it results in a relatively long path from the via to each source finger. Higher gain can be achieved with the “source-stitched” layout of Figure 2.18b. Here the vias are located adjacent to the first and last unit fingers and connected to the source stripes by a low inductance bridged feed. The improvement is particularly significant for a modest numbers of gate stripes, however the via location does not make efficient use of die area for arrays of many fingers. Figure 2.18c makes use of recent improvements in via technology and the ability to fabricate narrow width slotted vias. Narrow via width allows source fingers to have directly attached ground vias and the slot shape allows the amount of via wall presented to the device source connection to be maximized keeping the source inductance per finger to a minimum. In general, the style for Figure 2.18a is most efficient on semiconductor area but styles (b) and (c) have gain benefits that can be attractive for higher frequencies. Many of the factors in the design of the power-cell are amenable to mathematical analysis and modeling [82]. However, the pragmatic and most accurate approach to the determination of the scaling behavior is merely to design a mask set of device variants that covers the required set of layout styles, gate widths, number of fingers per cell and gate spacings, and then fabricate the devices and characterize them. The results of such an exercise for a 0.5 μm gate power FET process are illustrated in Figures 2.19a and b. Figure 2.19a shows the fT of the power cell as the unit gate width is varied for a range of gates per cell. Figure 2.19b shows the corresponding curves for fmax . In general, the performance reduction with unit gate width is driven by the combination of increased gate finger resistance and increased via inductance/mm of gate periphery. The reduction with number of gates is dominated by the via inductance/mm of gate periphery.
GaAs FETs – physics, design, and models
25
8 gates 10 gates 12 gates 14 gates
20
fT (GHz)
15
10
5
0 100
200
300
400
500
Unit gate width (micron)
(a)
50
8 gates 10 gates 12 gates 14 gates
40
fmax (GHz)
70
30
20
10
0 100
(b)
200
300
400
500
Unit gate width (micron)
Figure 2.19 GaAs FET power-cell performance; (a) fT as a function of unit gate width and number
of gates; (b) fmax as a function of unit gate width and number of gates.
2.3 Device design
2.3.4
71
Power cell combination Power-cells are required to be combined to form a composite high-power device. Of course, combining has to be done in a manner that takes into consideration the same gain degradation issues that arose in the design of the power cell. Furthermore, the approach has to contend with the issue that the input impedance of the cell is likely to be challengingly small. The simplest approach, commonly done for modest frequencies and impedance levels, is to combine the required number of cells, provide each one with appropriate sets of gate and drain bond pads, and leave the end-user free to combine in the circuit as required. The individual cells can have common gate and drain bus bars, or be wholly separate cells depending on the size of the cell and the approach used to achieve satisfactory stability. Some examples of the variety of power device layouts used in GaAs device technology are given in Figure 2.20. The devices shown range from 200 mm discrete devices able to provide output powers of 100 W at 2 GHz to mm-wave power cells with a power capability of 0.5 W. The die can be supplied either packaged or as bare die. The latter approach provides the highest performance as it avoids the introduction of significant package parasitics in a sensitive part of the circuit. However, the assembly costs are higher and the circuit module has to provide a higher degree of environmental protection. The circuit designer will face the task of stabilizing, matching and combining the cells to achieve the required power amplifier performance. At this level the device combination cannot be treated as a “lumped” problem and is typically done with a corporate combing approach using a distributed network [83, 84]. One to three levels of corporate combining can be considered which combine 2, 4, or 8 die, respectively. Unfortunately the losses associated with each level of the combination build up and so the benefit diminishes. Generally up to two levels of combination are effective but going beyond three levels is unlikely to be worthwhile. In order to achieve optimal performance from a packaged power device then it is common to perform at least some of the impedance matching and combining functions “inboard” of the package parasitics. By including matching circuitry at the device terminals the impact of the package is incurred at a less sensitive part of the circuit. This approach is very common for high-power devices [85–88], so much so that the name internally matched FET (or IMFET) has emerged as almost a device type in its own right. It is normal in IMFET products to combine the functions of prematching with power combining techniques in order to combine the power of multiple devices. An illustration of the typical circuit topology used to achieve this is shown in Figure 2.21. Another aspect that can make large power die difficult to deal with is their propensity to oscillate. Their large periphery gives huge low-frequency gain which must be accomodated. Even more problematic is the risk of odd-mode oscillation which can arise due to loops in the combiner networks. Internally matching provides the opportunity to substantially alleviate this problem for the customer by including suitable internal stabilization techniques within the package [89]. A further option is to provide internal control of the harmonic terminating impedances as required for high-efficiency amplifier modes [90, 91].
72
GaAs FETs – physics, design, and models
(f)
(g)
(e)
(a)
(b)
(c)
(d)
Figure 2.20 Power FET photos: (a) 200 mm multicell L-band power FET; (b) 60 mm power L-band FET; (c) C-band power FET; (d) power combination in X-band power MMIC; (e) conventional power cell evaluation structure (BCB coated for mechanical handling protection); (f) source bridge power cell evaluation structure; (g) electron microscope image of power cell (evaporated second metal).
2.3.5
Thermal design Thermal design is a critical part of a power FET design process. The junction temperature must be maintained within operational limits in order to ensure reliable operation. Ohmic contacts to GaAs are observed to degrade at elevated temperatures, but normally the dominant degradation mechanism is gate-sinking. Here the gate metal diffuses into the semiconductor thereby moving the effective location of the Schottky junction and so reducing the device current [92]. A typical requirement is to maintain the junction temperature below 150 ◦ C in order to achieve a predicted operating life of 1 million hours. Gate sinking is discussed in greater detail in Section 10.7.1. A difficulty encountered in this endeavor is the level of uncertainty in the determination of the channel temperature. The available methods all have significant potential sources of error. Commonly available measurement methods are infra-red imaging, use of the
2.3 Device design
73
D G
Figure 2.21 Corporate combining and prematching circuit topology used in IMFETs.
liquid crystal transition temperature, or use of the gate junction as a thermometer [93– 99]. Infra-red imaging is relatively convenient for surface temperature measurement, but FETs present difficulties as the gate-drain area that needs to be resolved is small with respect to the infrared wavelength. The liquid crystal approach is limited in that it can only indicate when the transition temperature threshold is crossed rather returning a value for the peak temperature for a given operating condition. The electrical approach inevitably returns a measure of the average temperature across the device rather than the peak temperature and, for the traditional switched approach of reference [98], error is introduced by the delay involved in switching from the active operating mode to passive sensing mode. Newer measurement techniques being developed are Raman spectroscopy [100] and scanning thermal microscopy [101]. A recent advance to the electrical approach has also been published that uses the gate junction state directly in an admirably simple manner obviating the need to switch the gate into a sensing mode [99]. In this latter approach a change to the base-plate temperature is compensated by an adjustment to the drain voltage in order to return the gate junction thermometer to its original condition before the base temperature was adjusted. From this measurement a value for the mean thermal resistance can be obtained. An alternative approach is to use thermal simulation. The detailed device structure and the thermal properties of the materials used are well characterized and 3D thermal simulation tools are comfortably able to model structures to the required degree of problem complexity [102–104]. There are also numerous approximate methods in common usage. Typical techniques are 2D analytic solutions or basic numerical methods limited to linear thermal conductivities. Such approaches should be treated with some caution [102] as the approximations involved frequently do not apply to GaAs FET devices, and in the case of power FETs the thermal operating window available can provide significant design constraints with minimal margin for error. Table 2.2 shows the results of a series of calculations of thermal resistance for a microwave power FET that illustrates the variation in predicted values for different calculation methods and for different levels of physical detail that are included. It is also important to realize that the there is the potential for inaccuracy with even the most comprehensive simulation tool. For example, there remain some unknowns such as the contributions of thermal interfaces [100, 104], and usually some uncertainty over the precise construction of the thermal problem. It is clear then that whatever the approach
74
GaAs FETs – physics, design, and models
Table 2.2 Comparison of peak thermal resistance calculations for a 4 × 120 μm GaAs FET cell with a junction temperature Tj of 150 ◦ C on 100 μm substrates mounted with 15 μm epoxy (the linear analytic cases use an empirical approximation to include the contribution of the epoxy) Rth C/W (Tj ∼ 150 ◦ C)
Calculation method 2D linear analytic [107] 2D linear analytic with end-effect included 3D linear semianalytic (TXYZ) [107] 3D linear finite difference 3D nonlinear finite difference 3D nonlinear finite difference with surface metallization 3D nonlinear semianalytic [105] 3D nonlinear finite difference with surface metallization and plated vias
240 206 184 208 237 221 226 213
Table 2.3 Simulated thermal resistances (◦ C/W) for central finger (RC ) and outer finger (RO ) compared against measured values (100 ◦ C liquid crystal transition temperature) for packaged RFMD discrete FET devices [105] Device type
RC
RO
(RC + RO )/2
Measured
FPD1500SOT89 FPD1500DFN FPD2250SOT89 FPD2250DFN FPD3000SOT89
75 70 53 50 41
54 51 37 34 28
64.5 60.5 45 42 34.5
60 60 48 40 35
used there is scope for significant error. A good approach then is to support thermal simulations with experimental evidence of cases that can be accurately measured. An example of this is given in Table 2.3 where the temperature predicted by simulation is compared to 100 ◦ C liquid crystal transition temperature for a series of packaged discrete FET devices [105]. A further, particularly detailed comparison is given in reference [108] where a special device was constructed with one finger of a power cell array connected as a passive thermometer. A sensible and pragmatic way to mitigate any residual systematic error is to employ the same technique in the thermal design of product as was used by the fabrication facility in the generation of the device life data.
2.4
Device fabrication
2.4.1
Overview In this section GaAs device fabrication techniques are described from the starting point of the manufacture of blank wafers with suitable active layers on the surface of an insulating GaAs substrate. For a MESFET a simple doping scheme comprising a channel layer
2.4 Device fabrication
75
accessed by a highly doped upper contact layer is all that is required. MESFET layers can be created either by using ion-implantation of dopant ions into the substrate, or by epitaxial growth of layers onto the substrate. For more complex devices such as HFETs and HEMTs then epitaxial growth is required. These layers are a suitable combination of GaAs and AlGaAs/InGaAs partner layers doped as necessary to construct the required devices. The grown wafers are then transferred into a wafer processing facility where the semiconductor layers are patterned, implanted, etched, metallized and coated as required to fashion the desired devices and circuits. In the following discussion the focus will be on epitaxially grown layers, now the more common approach for GaAs-based FET device manufacture. In commercial devices, epitaxial layers are grown by molecular beam epitaxy (MBE) or metal organic chemical vapour deposition (MOCVD). In MBE, a substrate is heated under high vacuum and beams of the appropriate proportions of the constituent atoms are directed at the substrates, condensing on the surface to form very high-quality layers of the required compounds. The layers can be deposited with very high precision with layer thickness control down to a few atomic layers. After growth the layers are inspected for accuracy, typically assessing the sheet charge and layer thicknesses, the molecular compositions of the AlGaAs/InGaAs ternary layers and the quality of the surface. In MOCVD the constituent atoms are delivered to the surface of a heated substrate by means of suitable precursor organic gas molecules that chemically decompose at the heated surface and deposit the desired atoms at the surface layer by layer. Typical source gases are trimethylgallium, trimethylaluminum, trimethylindium and arsine with a hydrogen carrier gas. The crystal composition is controlled by adjusting the relative proportions of the gas flow over the surface.
2.4.2
Key process steps Upon receipt of the epi-wafers device processing can commence. To form the devices a set of process modules are developed that perform functions such as creation of ohmic contacts, recess etching, Schottky gate deposition, metal interconnect deposition, insulating film deposition and etching, substrate thinning, and via etching. These modules employ a set of process steps that are optimized to work in concert and are characterized and maintained to meet the necessary manufacturing tolerances. The menu of process steps that are typically employed are described in the following paragraphs [109, 110]. Lithography: All of the wafer processing operations need to be selectively applied in controlled areas. This is achieved by lithography – most commonly photolithography. Here a suitable photosensitive “resist” film is patterned with an image that has previously been created on a photographic glass plate called a mask. The resist film is spun onto the wafer, exposed with the required image and then chemically developed. For so-called “positive” resist the unexposed area remains intact thereby shielding the covered region from a subsequent etching or metal deposition process step. By this means the various device features may be patterned as required. Alternatively, “negative resist” can be used. This behaves in the opposite sense so that the exposed area remains after being developed.
76
GaAs FETs – physics, design, and models
Three types of lithography are in common usage for GaAs wafer processing. The simplest is contact printing. Here, after the photoresist has been applied, the technique is to align the mask to existing features previously fabricated, clamp the mask to the wafer and then expose the assembly to light. This is a low-cost approach capable of feature sizes down to 0.5 μm and is quite suitable for small-volume manufacture. It does however suffer from mask wear and registration accuracy issues across the wafer. The resolution is fundamentally limited by diffraction of the incident light source and for higher resolution other approaches are necessary. For GaAs FETs the highest resolution requirement is for the gate metal which is usually of the order of 0.5 μm or less. Traditionally, electron-beam lithography has been the solution adopted for fine geometry gate definition below 0.3 μm. Here the gate pattern is created by steering an energetic electron beam to the desired areas and thereby exposing a suitable resist material in those regions. This eliminates the optical diffraction problem (the electron de Broglie wavelength for kV electrons is below 0.1 nm), and gives a resolution limited by the scattering in the resist and backscattering from the wafer. For research devices E-beam gate lengths have been driven down to 0.05 μm or less. In commercial devices E-beam gates are typically available down to 0.15 μm. The chief disadvantages of E-beam lithography are complexity and throughput. The serial nature of the writing process means the exposure times are lengthy. The third lithographic technique in common usage is the optical stepper. Here the pattern is imaged on a portion of the wafer with refractive optics. The mask is usually enlarged, typically 5 times greater than the final image and the pattern, or shot, is stepped and repeated to cover the wafer. Shot sizes are typically up to the order of 20 × 20 mm2 . The use of optical steppers is the dominant approach for high-volume, high-yield processing. The precision of the stepper optics is extremely stringent and requires associated control of vibration and temperature, compensation for air pressure variation coupled with precise alignment tools, stage-stepping control, and complex focusing systems capable of adapting to lens aberration. Liftoff: In the patterning of metals on GaAs devices much use is made of a procedure called “liftoff.” This is a different approach to that used in silicon processes where the aluminum tracks are formed by depositing the metal film, applying and patterning the photoresist and then etching back where the metal is not required. The situation is different for GaAs devices which make use of gold tracks and composite metal stacks which are not readily etched. The approach for these metals is to apply and pattern the resist before the metal is deposited and therefore to use the resist to control where the metal is deposited. When the resist is dissolved, the unwanted metal that was deposited on the resist film is lifted off and removed. To facilitate this process the edge profile of the resist apertures is fashioned by various means so as to have an overhang or “lip” and the metal is evaporated with a near normal incidence to the wafer so that a clean break in the metal film is created by the shadowing effect of the overhang. Device isolation: Wafers with epitaxially grown active device layers require that the individual devices on the wafer be isolated from each other. This is either done using mesa etching or ion implantation. With mesa etching, islands of active material are retained and the regions of interconnecting epi-layers are removed by an etching process. Mesa etching is an effective approach that avoids the need for expensive implantation
2.4 Device fabrication
77
equipment. However, it introduces undesirable surface relief and introduces increased gate leakage at the point where the gate metal stripe rises up the side of the mesa and crosses the active layer. Any surface relief is unwanted from a processing perspective as it inhibits uniform photo-resist coverage for subsequent process stages, and steps tend to compromise the integrity of any metal tracks that have to go over them. With ion implantation the active device regions are protected with thick photo-resist and the areas to be isolated are deliberately damaged by an energetic beam of ions thereby rendering the exposed regions to have high resistivity. For ion-implanted MESFETs then device isolation may not be necessary as the doping for the device active areas can be done selectively in the regions where it is required. In this case implantation is serving the opposite purpose to the isolation case above. Silicon donor ions are implanted with energies to achieve the required depth profile. The wafer is then heated so that the damage done to the crystal structure during implantation is annealed out and the dopant ions incorporated into the crystal lattice in order to activate them as donors. Alternatively, a blanket doping implant over the whole wafer can be used and the active areas are then isolated either with an isolation implant or mesa etching as for epi-wafers. Ohmic contacts: The function of an ohmic contact is to make a low-resistance electrical connection from the metal tracks to the semiconductor active layers. Ohmic contacts to GaAs are made by the use of a nickel, gold and germanium metal stack deposited on to a heavily doped GaAs contact layer and annealed at approximately 400 ◦ C. The essential purpose is to reduce the thickness and effective height of the Schottky barrier that forms at metal-semiconductor junctions to such an extent that the behavior is ohmic. The exact mechanism remains somewhat elusive but involves the generation of a highly doped surface layer of germanium substituting for gallium in the crystal lattice. The nickel component first acts as a wetting agent for the GeAu but it is also believed to enhance the diffusion of germanium into GaAs [109]. Gate Etch: Prior to the gate formation a recess is etched into the semiconductor material to remove the highly-doped contact material above the channel. Historically, this was an “etch-to-current” activity where the etch rate would be carefully calibrated and a timed etch would be used to target the desired recess depth. Subsequent verification by testing the drain current of the etched structure would result in the wafer being returned for a top-up etch if the measured current was too high. Such crudity was eliminated with the advent of “etch-stops” where the etch chemistries are chosen so as to be selective to the various heterojunction layers. The heterojunctions may therefore be used to stop the etch process at precise depths with high accuracy and, crucially, the accuracy is maintained over the whole wafer. This advance was key to the development of high-yield manufacture and the use of large area wafers. For example, reference [111] demonstrates that the use of an AlGaAs etch-stop layer for a GaAs MESFET reduced the process standard deviation for Idss from 25% to 5%. Layers that are already present in the epi-stack for their electrical function may be employed if appropriate [111] or specific etch-stop layers may be added to the epitaxy design that are there purely for control of the etch process. Alternative dedicated etch-stop layers are AlAs [112] and InGaP [113].
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There are two main approaches to GaAs etching: “wet” or “dry.” Wet etchant solutions consist of an oxidizing agent to oxidize the surface and a second component to dissolve the oxide. Commonly used etches able to provide etch selectivity with AlGaAs are dilute hydrogen peroxide/ammonia, hydrogen peroxide/citric acid and hydrogen peroxide/succinic acid [111, 114, 115]. Dry etching uses plasma chemistries involving a combination of chlorine and fluorine radicals in concert with energetic ion bombardment [115, 116, 117]. The chlorine produces the etching reaction and the fluorine produces an etch-stop reaction with aluminum due to the formation of a nonvolatile aluminum fluoride protective layer on the surface. Both approaches have relative advantages and disadvantages. A wet chemical etch provides a low-damage surface and for this reason is often preferred. However, wet etching is isotropic and so has less dimensional control. Dry etching has the advantage of good directionality giving a high degree of dimensional control, but this can come at a cost of some surface damage from the ion bombardment. However, it is found to be possible to tailor the dry etch recipe so as to minimize the ion energy towards the end of the etch process and suitably control the degree of etch damage [116]. Therefore both wet and dry etches can be used for GaAs FET gate etching and both are in use in commercial processes. Schottky gate electrode: The gate structure must make a good Schottky barrier contact to the semiconductor, one that is stable over the life of the device and that provides a low resistance along the gate finger. The Schottky barrier height is largely pinned by surfacestates to about 0.7 eV rather than controlled by the relationship of the semiconductor and gate metal work-functions as normally described in introductory text books. Therefore in principle many metals will provide adequate Schottky barriers. In reality, considerations such as metal adhesion and thermal stability provide the practical selection criteria. The result is that there is a choice of two approaches to the formation of the gate electrode: an evaporated gold-based gate or a sputtered refractory metal approach [118, 119]. The most common technique is to use an evaporated gate typically using a titanium-platinumgold (Ti-Pt-Au) metal stack. Here the titanium layer ensures good adhesion, the gold provides low feed resistance and the intervening platinum layer acts as a diffusion barrier keeping the gold safely from diffusing into the gate junction. The second approach is the use of a wholly refractory metal approach, generally using tungsten-silicide or titanium tungsten. The Ti-Pt-Au approach is a simpler technology however refractory gates are more thermally stable. This is advantageous not just for device operation but also for device fabrication. The thermal resilience of a refractory gate allows the gate metal to be deposited before the ohmic contact metal thereby making the critical gate lithography much easier and allowing the ohmic metal to be self-aligned to the gate [120]. With the conventional Ti-Pt-Au stack the ohmic contact anneal step must be completed prior to the gate metal deposition. For power FETs it is generally the case that in order to obtain high power it is essential to be able to operate with as wide a device finger as possible. A limiting factor here is the gate metal resistance and so power FETs usually use some form of ‘T’-shaped gate where the top of the gate metal is widened to reduce the resistance along the stripe. In the case of E-beam gates the “T” is achieved by a multilevel resist approach, typically employing PMMA (polymethyl methacrylate) thermoplastic resist materials in
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a typically bi- or tri-layer scheme to produce a mushroom-shaped profile in the resist comprising a narrow stem and a wider T or mushroom top. This is typically achieved by using layers of resist that differ in their sensitivity to the developer solution and to use the more sensitive material for the definition of the T-top. A final thin layer may be employed to create a lip for improved liftoff. Following the creation of the mushroom cross-section in the resist the gate metal stack is deposited over the wafer and the resist developed away lifting off the unwanted metal and leaving the gate structures behind. An example of a developed PMMA resist cross-section that provides a good illustration of the approach is given in reference [121]. The result of the multilayer approach is to create the desired “T” shape with minimized gate resistance and capacitance. The use of stepper-based lithography introduces a different method of forming the gate. Here the approach is to form the T-gate with the T-top supported on a dielectric layer [122–124]. The gate-support layer is deposited, a T-stem is defined and etched in this dielectric layer and the T-top is defined in photo-resist on the top. Gate metal is then evaporated to form a gate of the required shape thereby giving the resistance benefit required. The drawback relative to the E-beam gate process described previously is that the gate capacitance is increased slightly due to a higher degree of dielectric loading associated with the dielectric layer supporting the “T” and typically, a larger T-top overlap area. Dielectric layers: A number of dielectric layers are required for a variety of purposes including protective coatings, supporting metal track cross-overs, and for the formation of integrated capacitors. A commonly used material for GaAs processes is silicon nitride deposited using plasma-enhanced chemical vapour deposition (PE-CVD). This technique is compatible with the modest thermal constraints of GaAs device manufacture. In this approach silicon nitride films are deposited during a plasma-enhanced reaction of silane, ammonia and nitrogen gases. Careful process optimization is required for the successful deposition of device films, with particular attention to film stress and plasma-induced damage. Film stress is a significant factor for GaAs devices as the material is piezo-electric [125]. The plasma is typically generated with a 13.56 MHz RF power source and the resulting film from this arrangement is stressed and typically tensile in nature. Control of the stress from tensile to compressive can be achieved by a number of methods including adjustment of gas composition or the addition of a component of lower frequency power, typically 1–2 MHz [125, 126]. The latter approach introduces a high energy ion-bombardment of the growing silicon nitride film and this results in a controllable change to the resultant stress state. Although effective in controlling the film stress, ion bombardment employed in the vicinity of a GaAs surface introduces unacceptable degradation of the surface thereby introducing a tradeoff of film-stress against surface degradation. However, devices are usually fabricated with a number of film layers and a good degree of stress control can be achieved by designing the stack of composite layers appropriately so that the overall film stress is acceptable and the surface damage arising from the near-surface layers is minimal. In order to pattern a silicon nitride film after deposition it must be etched and either dry or wet etching approaches may be used. Dry etching is preferred due to its superior dimensional control. It is typically performed using a sulphur hexafluoride (SF6 ) plasma diluted in helium in order to achieve a
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controllable etch rate. Wet etching of silicon nitride is uncommon but can be performed using a buffered Hydrofluoric acid etch. Interconnect metals: Usually, two levels of interconnect metal are required in order to make connections between devices and other components and external bond-pads. The first level metal is generally evaporated gold and is generally deposited to a thickness of 1–2 μm. A second level metal is needed so that one track may cross-over another, for capacitor formation, and to provide thicker tracks in order to carry high currents. Second metal tracks are usually electro-plated gold onto a sputtered seed layer. More recently some manufacturers are now employing evaporated second metal rather than using electroplating [127]. This can have cost advantages particularly for high volumes as the highly uniform finish of evaporated metal is more easily compatible with automatic visual inspection tools. Backside processing: GaAs RF technology is usually of the microstrip variety requiring a ground-plane on the backside of the wafer. Connection to the ground plane is made by through-wafer vias. Processing of the underside of the wafer therefore consists of thinning, via etching and metal deposition. The completed front surface is protected and then temporarily adhered to a supporting carrier with a wax or photoresist. The wafer is then ground down to the desired thickness. For power devices the final thickness requirement is normally governed by the thermal design and is typically in the range 50–120 μm. Through-wafer via etching is performed using directional dry etching. The backside is then metallized using electroplated gold onto a sputtered seed layer. Process Monitoring: In order to evaluate the performance of each wafer and to provide data for statistical control of the process, a number of standardized test cells are included on each wafer. The cells are called process control monitor (PCM) cells or “the coupon.” The number used per wafer varies and depends on the wafer size, the maturity of the process and local policies and can vary from ten to a hundred. The PCM contains both structures to assess individual process steps and standard devices which are evaluated at various points in the process flow. Structures are included to assess the contacts, the efficacy of the isolation, the quality of each of the various metal and dielectric layers, and any GaAs or thin-film resistors that might also be in the process. These and the standard device cells are typically assessed after the gate has been deposited, after the front-face has been completed, and finally at the end of the process. The device tests performed while the device is in the production line concentrate on cardinal parameters including the pinch-off voltage, drain current for Vg = 0 V (Idss ), maximum drain current, breakdown voltage, diode built-in voltage and ideality, gate leakage and the DC transconductance. These are monitored with a view to obtaining constant feedback on the process so as to keep it in control and for identifying occasional errant wafers so that they can be scrapped as soon as possible to eliminate the cost of further processing. Upon completion of the wafers, a standard PCM FET structure designed to be suitable for on-wafer RF testing is usually assessed with some level of RF test. This typically consists of a measurement of S-parameters at a specific standard bias point from which an indication of RF performance is obtained by extraction of fT , fmax , or Gmax. Some manufacturers also perform equivalent circuit extraction in order to be able to monitor key equivalent circuit parameters.
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At the end of the production line a set of the most critical parameters that have been tested are collated and used in the wafer acceptance test (“WAT”). For this test a defined fraction of the PCM structures have to be within the specification limits for the wafer to be acceptable to go on for visual inspection and release to the customer.
2.4.3
Low-cost GaAs device fabrication The recent increase in GaAs production volumes and the cost pressures of the cellular handset market that have driven that volume have revolutionized GaAs device manufacture and the capabilities that can be brought to bear. Key developments here are an increase of GaAs wafer diameter from 4 to 6 and the use of stepper-based lithography with its inherent benefits of high throughput, uniformity and yield. As discussed in the Schottky gate electrode part of Section 2.4.2, dielectrically defined gate techniques used in stepper-based processes inevitably have higher parasitic gate capacitance than unsupported approaches used by e-beam processes. However, the reduction of performance is acceptable for many applications and the benefits of lower cost and greater uniformity are substantial. Furthermore, the higher degree of die encapsulation required in order to provide the level of environmental protection that is increasingly demanded anyway involves an increased amount of encapsulating dielectric material. In this case, the fact that dielectric-defined gate processes start with a higher degree of dielectric loading becomes less of an issue. The substantial advantages of 6 stepper-based wafer fabrication has therefore led to the major manufacturers adopting this approach and offering optically defined gate technologies [128–130]. The initial use of optical steppers was for 0.5 μm applications and made use of relatively affordable “i-line” steppers (365 nm wavelength). This technology is suitable for devices with fT ’s of the order of 25 GHz and for applications to X band. More recently processes have been developed to be able to fabricate smaller gates for higher performance devices. The options here are to use a deep-UV stepper or one of a number of “gate-shrink” approaches. With a deep-UV stepper a shorter wavelength of 248 nm is employed to directly image gates down to the order of 0.25 μm [131]. Alternatively, or in combination, one of the gate-shrink approaches can be employed to pattern the gate dimension below the resolution of the stepper. Techniques that have been successfully employed include the use of dielectric sidewall spacers [120], chemical shrink [132], reflowed resist [133, 134] and the use of phase-shift mask technology[135]. With these techniques stepper-based approaches can be employed in production at and below 0.15 μm.
2.4.4
Packaging Packages are used for ease of handing the fragile die and for environmental protection. The range of available package types is extensive reflecting diverse requirements that stretch from DC to millimetre wave. The packaging solutions range from plastic molded structures for high-volume applications to hermetically sealed ceramic housings with high-quality integral heat sinks for the highest performance products. Figure 2.22 shows a selection of packages used for GaAs power devices.
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AF
SOT89
(a)
(b)
QFN
AS
(c)
(d)
Figure 2.22 Typical power FET packages; (a) SOT89; (b) ceramic flange mount; (c) leaded ceramic surface mount; (d) leadless plastic surface mount (QFN).
Traditionally, the packaging route for microwave power transistors was essentially limited to the metal-ceramic air-cavity package consisting of an alumina housing brazed onto a metal flange such as the AF package in Figure 2.22. This approach provides good heat dissipation properties, a good RF ground, a well-controlled parasitic environment, and hermetic sealing options. This approach remains the highest performance packaging option but this is achieved at a significant cost. Not only is the package cost the most expensive component in a packaged power transistor part, they are also expensive to assemble and the resulting components are not amenable to high-volume circuit board manufacturing processes. The high cost of conventional ceramic packaging encourages the development of alternative technologies and a sustained focus has been on the development of plastic packages [136]. The use of plastic packages introduces a number of difficulties compared to ceramic technology including increased ground inductance, substantial dielectric loading, and thermal dissipation and expansion issues. Established over-molded plastic packages such as the SOT89 style equipped with a reasonably heavy lead-frame are employed for modest power and frequency applications. More demanding situations have driven appropriate technology developments. Silicon LDMOS devices targeting
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(a)
(b)
Figure 2.23 QFN package cross-section; (a) over-molded package; (b) air-cavity package.
frequencies up to the order of 2 GHz have pursued over-molded plastic encapsulation of devices mounted on an integral copper heat spreader. Such solutions are suitable for in excess of 100 W [137]. However, GaAs devices generally address higher frequency and lower power applications. Surface mount packages, such as the AS and QFN styles in Figure 2.22 are desirable for high-volume assembly requirements. Leaded and leadless surface mount ceramic packages are well established and plastic surface mount techniques are currently receiving much attention. Of particular note is the example of the QFN package (Quad Flat No leads, JEDEC standard MO220 [138]) of which a 3 × 3 mm 12-pad style is shown in Figure 2.22. This package standard was originally developed for low-speed general electronics, however its construction is amenable for development for microwave frequencies and QFN packages have found application for a range of microwave devices and MMIC circuits. Standard plastic QFN packages such as is depicted in Figure 2.23a are used in applications up to 18 GHz and approximately 1 W dissipation. Developments have included power variants with a heavier duty lead frame and employing solder die attach [139, 140]. For higher frequencies the use of alternative materials and constructions are attractive in order to achieve lower dielectric loading. Significant attention has been paid to organic polymers which have superior microwave properties to plastic [141, 142]. Millimetre-wave capable approaches have been developed using multilayer approaches with air cavities as illustrated in Figure 2.23(b) [143]. Ceramic implementations are also pursued for higher frequency applications due to the superior mechanical precision of those materials and 40 GHz operation has been demonstrated [144]. An activity of significant interest for low-cost manufacturing is the optimal route to achieving acceptable environmental protection. Traditional ceramic packages were able to provide high levels of hermeticity. Alternatively, the environmental protection could be provided at the module level. However, the continual drive for lower manufacturing cost now increasingly excludes such options and recent work has focused on the development of hermetic low-cost packages [143] or adequate encapsulation at the die level. The latter objective is achieved by ensuring that the finished semiconductor die survive standard
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tests for hermeticity and are sufficiently robust that the encapsulation survives the mechanical handling encountered in the plastic packaging process. Two standard tests here are the “85/85 THB” and “HAST” tests which are discussed in more detail in Section 10.9.3. In the former the packaged parts must survive 1000 h at 85 ◦ C temperature, 85% humidity and the operating bias. The latter highly accelerated stress test aims to replicate the same stress in a much shorter time frame. The standard HAST conditions of 130 ◦ C with 85% relative humidity is achieved at approximately 18 psi overpressure. The standard assumption is that the 1000 h THB test is equivalent to 96 h of HAST based on earlier work on silicon device technology. This equivalence has been questioned for the case of compound semiconductor devices by a number of workers [145, 146] and the GaAs device industry has found the routine satisfactory attainment of the 96 h HAST requirement a difficult hurdle [147].
2.5
Models
2.5.1
Device models Device models are employed to simulate device behavior in circuit design. The accurate simulation of GaAs FET power amplifiers can present a number of difficulties for the presently available modeling techniques and the degree of success achieved varies considerably depending on the precise application. Available models for moderatelysized devices (up to a few mm of gate periphery) can generally predict first-order parameters satisfactorily such as terminal impedances, gain, power and power saturation, and give a reasonable indication of efficiency. However, the situation for more demanding requirements such as accurate modeling of very large devices, for the precise prediction of large-signal nonlinearity and for the impact of some transient phenomena such as selfheating and slow-state effects on digitally modulated waveforms is often less satisfactory.
2.5.2
Small-signal models Extraction of the parameters of the equivalent circuit model of Figure 2.12 is well established. For devices of gate peripheries up to the order of a millimeter or so, this model is readily extractable from a suitable set of bias dependent S-parameters using the direct extraction technique introduced by Dambrine et al. [148] and subsequently further refined by numerous authors. The essential technique relies on a set of off-state or “cold-FET” biases to extract the embedding parasitic elements from a simplified equivalent model applicable to this bias condition. The embedding parasitics obtained for this simpler network are assumed to be also appropriate for the on-state or “hot-FET” bias condition. These parasitic values may therefore be used to de-mbed the hot-FET data, thereby obtaining the y-parameters of the intrinsic FET equivalent circuit and, at this point, solving for intrinsic elements is straightforward. The model obtained from this process is usually acceptable for frequencies below around 10 GHz. At higher frequencies it is normal to find that the accuracy of the reverse isolation parameter S12
2.5 Models
Lg
Cgd
Rg Cgs
Rd
+ --
Ri
85
Ld
Rds Cdc
gm Cds Rs
Ls
gm = gm0.e−jωτ
Figure 2.24 High-frequency GaAs FET equivalent circuit network.
becomes unacceptable. The reason for the discrepancy is due to the inadequacy of the equivalent circuit topology. Better fits than that obtained from direct extraction methods may be readily obtained but it is generally found that this involves non-physical values for some of the elements. Alternatively, modified equivalent circuit topologies may be employed which attempt to address the additional complexity in the frequency response at the higher frequencies. Such factors as dipole capacitance and distributed effects [148–152] give rise to modified equivalent circuit models such as that of Figure 2.24. These more complex equivalent circuit topologies don’t lend themselves to a wholly direct extraction algorithm, however the Dambrine model can be taken as the starting point and strategies developed to deal with the additional elements in a structured manner [153]. As mentioned above, direct extraction performs well for devices of modest size. As the device size is increased above a few mm of gate periphery the device becomes increasingly distributed in nature, and also the device measurements become less reliable due to the low impedance level that results. Very low impedances are difficult to measure accurately in a 50 system and the obvious solution of scaling up smaller device measurements to replicate a very big device is not straightforward. A particular issue is that the thermal environments can be very different [154]. However, for the most part, at least for devices that are directly measurable, the development of small-signal models is a reliable activity.
2.5.3
Large-signal models The situation for large-signal models is less straightforward. Here the desire is to model the device response to an arbitrary signal. The difficulty of this challenge is perhaps not always fully appreciated. The normal approach is to use large-signal equivalent circuit models which have been created by transforming a set of bias-dependent linear models into a single nonlinear one. At the heart of this approach, at least for commonplace models, lies the “quasi-static assumption” where it is assumed that the instantaneous
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values of the equivalent circuit elements are uniquely dependent on their controlling voltages [155]. In other words the device is assumed to be memory-less. As has already been discussed this actually isn’t the case and both thermal effects and dispersion effects cause this assumption to be violated. Consequently, large-signal models employ various measures in attempt to account for these effects and a range of large-signal model formulations have been developed over the years. They typically have focused on particular aspects of device behavior and a Darwinian process of natural selection, skewed by the choices of models that the simulator vendors have chosen to support has resulted in a range of models coming to the fore. A FET model for PA applications should possess the following attributes: 1. 2. 3. 4.
Replicate the DC I–V well in order to accurately reproduce the correct bias point. Account for the effects of dispersion so that the RF swing is accurately modeled. Properly represent the bias-dependence of the capacitances. Accurately reproduce differentials of the bias dependent parameters as well as their absolute values. 5. Include the impact of temperature on device characteristics. 6. Include time delays for high-frequency models.
The commonly available models tend to have strengths that have addressed a subset of the above requirements and there is no obvious “best” model. For example, the Triquint “TOM” series of models introduced an effective approach to model the bias dependence of the drain conductance [156] whereas the Angelov/Chalmers model [157] is notable in including the characteristic peak in the transconductance dependence on gate bias typical of HEMT devices. The I–V characteristic is the focus of the Parker–Skellern model [158] which has a flexible functional form and well-behaved continuous derivatives. Many models include dispersion effects with various degrees of sophistication with the extended Angelov [159, 160] and Parker–Skellern models being comprehensive examples. It is not unusual for models to concentrate heavily on the device I–V, however for accurate simulation of linearity as frequencies increase then the accuracy of the reactive elements is also important [161]. The Angelov [160] and TOM3 models [162] have comprehensive bias dependent capacitance models. Another development is the (unpublished) Auriga model which is a further development of the Angelov model and which claims improved capacitance models and a modified drain current equation [163]. The popular EEFET3 and EEHEMT models [164] bring together a number of these features in two widely used forms. An appreciation has grown with time of the importance of charge conservation for the gate capacitance. As discussed in Section 2.2.7, the gate depletion region is a single entity but is accessed by all three terminals. It is seemingly straightforward to extend the small-signal model to employ two bias-dependent capacitors Cgs (Vgs , Vds ) and Cgd (Vgs , Vds ) to represent the depletion reactances with independent charge or capacitance functions of the remote controlling voltages. However, this approach will generally result in a non-conservative system so that the total gate charge is (Vgs , Vds ) path dependent. The consequences of this are the possibility of an unintended net gate current [165] and, as circuit simulators are required to maintain charge-conservation
2.5 Models
87
at each node, then simulator non-convergence and spurious results can occur. Other work has demonstrated that charge conservation is important for accurate prediction of nonlinear effects [166, 167]. Two approaches to resolve the problem are possible. The direct and conceptually straightforward approach is to construct the model in terms of a single gate charge entity that is a function of the local variables Vgs and Vgd . This is the approach used in the widely available TOM3 model [162]. The charge function cannot be directly measured and must be inferred from the small-signal Cgs and Cgd capacitances. The resulting model is fundamentally and unequivocally charge-conservative [167]. Alternatively, the charge may be separated into independent functions Qgs (Vgs , Vds ) and Qgd (Vgs , Vds ). To achieve charge conservation these elements must be augmented by additional charge control elements called trans-capacitances which are required in order to properly account for the contributions to the partitioned reactive currents that arise from both controlling voltages [168, 165, 169]. An example of a gate-charge model employing separate gate-source and gate-drain functions and employing transcapacitance to restore charge conservation is the formulation used in the EEFET3 and EEHEMT models. The functions employed are charge-conservative in the saturation region of the device I–V and so are valid for power amplifier circuits. However, the use of smoothing functions in order to force symmetrical behavior of the charge functions around Vds = 0 results in non-physical (negative) drain-source capacitance in the linear (i.e., subknee) region [170]. Large-signal models are developed by fitting the model equations to measured data by numerical optimization. The number of fitting parameters can be extensive and so to obtain good models robust methodologies are required to segment the problem into parameter subsets and to select good initial values. The most straightforward procedure is to use measured DC data for the I–V equation and to use bias-dependent S-parameter data to extract the charge functions and to model the correction terms necessary to modify the dynamic response of the I–V. The impact of dispersion can be a significant source of error for PA design and a more accurate approach can be to directly measure the dynamic I–V with a pulsed I–V measurement system [21, 22, 171, 172] and to use that to represent the model I–V [173]. This approach provides a direct model of the dynamic I–V at the quiescent bias point of interest and avoids the need to develop a complex empirical correction factor. The main drawback of this approach is that the resulting I–V model is no longer applicable for the whole bias plane but is specific to operation points in the vicinity of the quiescent point in the pulsed I–V set. The traditional compact device models generally do a reasonable job of describing first-order amplifier performance and adequately represent the terminal impedances and power saturation behavior. However, they are usually less successful at next-level parameters such as linearity measures, and usually do not include such refinements as self-heating or accurate bias-dependence of trapping phenomena. These shortcomings have inspired a lot of efforts spanning many years to enhance commonly available models. A substantial degree of improvement was obtained by augmenting the quasi-static models with corrective terms for trapping effects. Measures to accomplish this include empirical methods to modify the large-signal I–V response by means of corrections to the
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dynamic output conductance [174]. Later developments have been to make use of pulsed I–V data to frame the construction of more physics-based trapping models [175–177]. Thermal effects are also be included in this work by the use of self-heating terms and a thermal impedance model [178]. The next stage of this approach is to include the impact of the self-heating on to the trapping state by including a temperature dependence to the trap correction terms [179, 180]. The refinements to the trapping models have successively improved the state-of-art in this aspect of modeling. However, an area somewhat less developed is the provision of a satisfactory approach for the modeling of large periphery devices. A common experience is that conventional circuit model approaches do not satisfactorily scale above a few mm of gate width. However, such devices are required for numerous applications in the L to C band range. GaAs devices with 100–200 mm of periphery are capable delivering 50–100 W from a single die at 2 GHz but the circuit design approaches are largely “cut and try.” Conventional modeling approaches are ill-equipped to cope with this distributed problem and a number of new dimensions need to be added if models are to be adequate. Such devices have many fingers – frequently over a hundred – which see differing and coupled thermal and electromagnetic (EM) environments. A particular problem is also to model accurately the stability of such devices. The complete model for this highly complex situation is a coupled electro-thermal and EM model. There is an emerging body of academic literature on this topic with recent developments towards simplification and manageable computation speed. Reference [181] describes circuit simulation software coupled with a highly efficient thermal solver. Individual fingers of a power cell are modeled with a compact equivalent circuit model and the fingers are thermally coupled by a thermal circuit. Reference [182] specifically addresses the topic of large power devices with a similar approach that also includes coupled EM simulation. The latter approach is notable for being deployable on standard commercial simulators. Another direction in modeling aims to avoid the whole messy business of trying to persuade an equivalent circuit model with elements that follow prescribed bias-dependent functions into representing the measured data. An alternative approach instead employs table-based techniques where the nonlinear data is accessed and interpolated from lookup tables. The most well-known implementation of this approach is the Root model [183] available as a turn-key commercial modeling solution. Subsequent developments of this approach make use of more sophisticated interpolation schemes which provide better simulation of nonlinearity [184, 185]. A further theme receiving much recent attention has been the use of direct large-signal measurement [186]. Techniques explored here include fitting conventional equivalent circuit model parameters directly to observed large-signal behavior [187] and the direct extraction of extrinsic current and charge functions to describe the nonlinear behavior directly at the device terminals [188]. However, the ultimate logical end-point of this direction is to eliminate any level of equivalent circuit description altogether and instead to implement a wholly mathematical “black-box” or “behavioral” description of the data. The approach that has been adopted to achieve this is based on poly-harmonic distortion (PHD) modeling [189] which describes large-signal behavior by means of an
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89
extension to linear S-parameters. In this scheme additional terms are added to the linear parameters to account for harmonics and intermodulation frequency components. By this means complex waveforms may be described. The term X-parameters has been coined to describe the new nonlinear parameters and a commercial nonlinear vector network analyzer capable of their measurement are available. In order to be useful for characterizing transistors the X-parameters must be measured over the appropriate region of the Smith chart requiring the X-parameter characterization to be combined with a load-pull system [189, 190]. The resulting dataset is large requiring the dimensions of frequency, bias, signal amplitude and impedance state all to be characterized and recorded. However, the approach is mathematically rigorous and has been verified to high levels of compression [191]. In many ways conventional empirical models and new behavioral data models are complementary. The former possess such benefits of an innate generality, compactness and scalability by virtue of the underlying physics embodied in their construction. These are attractive qualities for device manufacturers who need to characterize a process in a general fashion. They also make use of relatively straightforward and widely available test equipment. Black-box behavioral models offer the prospect of automatic generation of high-accuracy models for specific devices and operating conditions. This latter picture is attractive for specific design requirements focused on particular devices where the generation of large datasets and a lack of model scalability are manageable issues.
2.5.4
Load-pull A long established, pragmatic, and reliable alternative to the nonlinear device model is the long-standing load-pull measurement. Here the device performance is explored with carefully characterized tuners and the circuit is designed to replicate the desired matching impedances. This approach has evolved to employ computer controlled tuners that are now able to include effective control of the source and load harmonic impedances [192]. The key limitation of the passive tuners provided by commercial vendors is that the losses arising between the tuner instrument and the device under test restricts the maximum reflection coefficient that can be attained and this rather limits the size of the device that can be characterized. Pre-matching circuitry can help here but the ultimate solution is achieved by the use of an active load-pull system such as that described in reference [193] where the reflected signal is synthesized as required to account for the loss so as to achieve the effective impedance as if an ideal lossless tuner were used. Active load-pull systems have been successfully demonstrated by a number of workers over many years but they have yet to achieve widespread use outside of the R&D lab due to reasons of cost and complexity. In this light it is interesting to note that a remarkably effective but simple and extremely low-cost alternative to load-pull test equipment is available using nothing but a simple linear model for the device output impedance [194]. Experience has shown that the estimate for the output power match condition obtained from this approach is consistently in excellent agreement with load-pull measurement and the technique remains a popular approach for first-cut circuit design.
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2.6
Concluding remarks This chapter has reviewed GaAs power FET technology. It has covered materials properties, device types and their operation, key device physics, and critical aspects of power device design. A summary of GaAs device fabrication has been provided contrasting established processes with new low-cost approaches and the chapter concludes with a brief review of device models. The wide range of subjects covered spans several decades of development by numerous research groups and industrial companies. It is therefore impossible to fully reference such a body of work and a balance had to be struck that weighed recognition of historical significance with clarity and brevity for the contemporary reader. A further limitation is this author’s limited capacity to read, digest and retain the breadth of literature. It is consequently inevitable that omissions will have occurred and for which it is hoped the relevant parties will understand.
Acknowledgment The author would like to thank the engineering team at the RFMD facility in Newton Aycliffe (members past and present) who have all contributed to the understanding that is contained in these pages. Particular appreciation is expressed to Mike Brookbanks, Richard Davies and Rob Dry who gave helpful support in the writing of the chapter.
Appendix 2.1 Comments on the determination of fT and fmax The h21 function is generally very well behaved and is easy to calculate in an unambiguous manner. This should be performed from a linear part of the h21 versus log. frequency curve where the first pole of the frequency response dominates. For a microwave device a frequency of around 5–10 GHz is typically a good frequency to use. An extrapolation to 0 dB at 6 dB/octave will give a reliable value and this may be simply calculated thus: f T = f h 21 ( f )
(A1)
= f 10
(A2)
h 21 d B( f )/20
where f is the frequency of evaluation, h 21 is the magnitude of the forward hybrid parameter and h 21 d B is its value in dB. The measurements should be properly deembedded to the device reference plane for the appropriate terminating impedances to apply. A useful “rule of thumb” for a well-designed device is that it will likely be an appropriate choice for an application for frequencies up to ∼fT /2. The situation for fmax is not as straightforward. In theory there is no issue as both Gmax and U both cross the 0 dB line at the same frequency and this point uniquely defines fmax [60, 195]. However, in practice for microwave FETs, fmax is usually somewhat
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higher than the upper limit of the available test equipment and examination of the gain curves for frequencies well below fmax invariably suggests Gmax and U will have distinct intercepts. The situation typically observed is that of Figure 2.14 with U following a well-behaved 6 dB/octave roll off and giving no hint that it will converge with Gmax. Vendelin [60] explains how additional terms in the frequency response will ultimately restrain the U curve; however, a judgment has to be made on the data that is available. In practice one of the U or Gmax curves is chosen and extrapolated to determine the 0 dB intercept. It is also very common not to specify which curve was used for this procedure. Many workers choose a 6 dB/octave extrapolation of U. For some this is due to a belief that it is the correct one or because of its apparent well-behaved slope. Others choose Gmax and return a commendably more conservative value; however the complicated Gmax curve provides ambiguity as to how it should be extrapolated. Given these issues there is a good argument not to quote fmax at all but to provide explicit Gmax curves or quote Gmax at particular frequencies. In any event, a degree of caution is required when comparing devices based on fmax values that one has not measured for oneself. Should a value for fmax be required and it is beyond the frequency range of available test equipment then, in this author’s opinion, a reasonable approach to its determination is to extrapolate Gmax at 6 dB/octave from a frequency where the device is unconditionally stable and with stability factor, k, comfortably above unity so as to be reliably free of the gain-peaking near the MAG/MSG stability break-point.
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3
Wide band gap transistors – SiC and GaN – physics, design and models R. J. Trew ECE Department, North Carolina State University
3.1
Introduction Although solid-state transistors have replaced vacuum electronics in the vast majority of microwave electronic systems over the past 40 years the revolution is not complete. In particular, the areas of high RF power for microwave and millimeter-wave radar and communications transmitter applications, the ability to produce adequate RF power levels at frequencies greater than 100 GHz, and the ability of devices to operate at high temperatures greater than about 250 ◦ C remain dominated by microwave tubes. Further solid-state material and transistor developments in these areas are among the last frontiers for semiconductor electronics. In these areas solid state transistors have not been able to compete with vacuum tube devices, and most systems that must deliver kW to MW power levels are designed using various types of microwave tube. The current state-of-the-art for microwave solid-state devices and for microwave tubes is shown in Figure 3.1. As indicated, solid-state devices produce RF power levels less than about 100 W and operate with reasonable RF output power to frequencies of about 100 GHz. The RF performance status shown in Figure 3.1 is for single device operation, and does not necessarily represent a true comparison of the RF output power capability of a system. Power combining and phased array technology permit the outputs of many solid state transistors to be combined, thereby producing significantly improved RF output power and solid state systems can, in practice, compete in terms of RF output power with tube-based systems in some cases. Combining technology can raise microwave RF output power into the kW range, at least through S band and into Ku band [1–4], and theoretically to much higher power levels. However, such multidevice concepts are increasingly difficult to apply as operating frequency increases and cannot extend the upper frequency limit beyond the present state-of-the-art. Operation at frequencies above X band and up to 100 GHz with RF output power in the hundreds of watts or kW range will require new semiconductor materials and/or transistor concepts. The upper frequency capability of a solid-state transistor is fundamentally dependent upon the charge carrier velocity in the semiconductor material from which it is fabricated, and the physical dimensions of the device. Modern semiconductor material growth technology and fine line lithography permit transistors with critical dimensions less than a micron (30 W/mm was reported for a field-plate device biased at a drain voltage of 120 V [45]. High PAE has also been reported, and an AlGaN/GaN HFET grown by MBE on a 4H-SiC substrate produced 8.4 W/mm with 67% PAE with a drain bias of 30 V [46]. Silicon has emerged as a viable substrate material for AlGaN/GaN HFETs and excellent RF performance has been obtained. Johnson et al. [47] reported RF output power of 12 W/mm with 52.7% PAE and 15.3 dB gain for a 0.7 μm gate length device. The HFET was biased at 50 V and operated at 2.14 GHz. The transistor is intended for communications band applications. Dumka et al. report 7 W/mm with 38% PAE and 9.1 dB gain at 10 GHz from a AlGaN/GaN HFET fabricated on a Si(111) substrate [48]. The device was biased at a drain voltage of 40 V. Reduction of the drain bias to 20 V resulted in a decrease in RF power to 3.9 W/mm, but an improvement of the PAE to 52%. high-frequency Ka-band performance has also been reported. At 18 GHz Ducatteau et al. report an RF power density of 5.1 W/mm with 20% PAE and 9.1 dB gain from a nitride HFET fabricated on a Si substrate [49]. The device had a 0.25 μm gate length and a current gain bandwidth of fT = 50 GHz. An AlGaN/GaN HFET fabricated on a SiC produced 5 W/mm with 30.1% PAE and 5.24 dB gain at 26 GHz [50]. Lee et al. [51] report 4.13 W/mm with 23% PAE and 7.54 dB gain at 35 GHz. The HFET was biased with a drain voltage of 30 V. The HFET was fabricated on a SiC substrate. At 40 GHz an RF power density of 2.8 W/mm, 10% PAE, and 5.1 dB gain was obtained from a device with a 0.18 μm gate length device [52]. The performance of the device was sensitive to frequency, and RF output power density increased to 3.4 W/mm by reduction of the operating frequency to 38 GHz. Using a recess gate design an RF output power density of 5.7 W/mm with 45% PAE was obtained with a drain bias of 20 V [53]. Increasing the drain bias to 28 V resulted in an increase in RF output power density to 6.9 W/mm. Palacios et al. [54] report excellent RF performance at 40 GHz from an AlGaN/GaN HFET fabricated on a 4H-SiC(0001) substrate. Devices with similar structures were fabricated using both OMCVD and MBE. The device
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produced 8.6 W/mm with 29% PAE and gain of about 5 dB. The OMCVD grown device had improved performance, with 10.5 W/mm, 33% PAE, and about 6 dB gain. Attempts to improve device performance include novel surface passivation and charge confinement. Lau and her colleagues [55] introduced a surface passivation technique involving a fluoride-based plasma treatment. The fluoride-based plasma treatment, along with a post-gate rapid thermal annealing step, was found to effectively incorporate negatively charged fluorine ions into the AlGaN barrier and positively shift the threshold voltage. The technique was used to fabricate an enhancement-mode (E-mode), HFET. Shen et al. [56] used the fluorine plasma process, along with a deeply recessed gate HFET design, to fabricate a device that produced 17.8 W/mm with 50% PAE and 15 dB gain at 4 GHz. The passivation process limited gate leakage and thereby permitted a drain voltage of Vds = 80 V to be applied, without the use of a field-plate. The strong polarization effects of the AlGaN/GaN structure may be a source of some of the reliability problems experienced with these devices. Attempts to investigate this include utilization of alternate barrier materials that are less polar. One such structure can be fabricated using InAlN, rather than the commonly employed AlGaN. An InAlN/GaN HFET with a gate length of 0.7 μm produced a gain-bandwidth product of fT = 13 GHz and and fmax = 11 GHz. The 2DEG was very high, with nss = 4 × 1013 cm−2 and an electron mobility of μn = 750 cm2 /V-s [57, 58]. An InGaN layer was used as a back-barrier to improve confinement of the 2DEG electrons [59]. The confinement improved the output resistance, and a device with a gate length of 100 nm produced a gain-bandwidth product of fT = 153 GHz and an fmax = 198 GHz. By adjusting the bias the same device produced an fmax = 230 GHz. A double heterojunction device design using an InGaN notch fabricated on a sapphire substrate produced RF output power of 3.4 W/mm and 41% PAE at 2 GHz [60]. Good RF performance has also been obtained from a GaN FET, fabricated using a novel surface passivation consisting of a thin AlN layer located between the GaN channel and a SiN surface passivation [61]. The resulting structure is basically a metal-insulator-semiconductor (MIS) FET. A device with a gate length of 60 nm produced fT = 107 GHz and fmax = 171 GHz. Most of the early results were for devices with very narrow gate widths to minimize device heating and thermal effects. More recent work has focused upon producing highpower devices and amplifiers suitable for use in applications such as communications base station transmitters. Ando et al. [62] reported RF output power of 10.3 W with 47% PAE and 18 dB linear gain at 2 GHz. This result was for a device with a gate width of 1 mm. Linear gate-width scaling with drain current and RF output power has also been demonstrated. A high-power integrated circuit using 8 mm of gate periphery yielded 51 W RF output power at 6 GHz under pulse bias conditions [63]. A communications band amplifier, using AlGaN/GaN HFETs fabricated on SiC substrates, and biased at 48 V produced CW RF output power of 100 W at 2.14 GHz [64]. A C-band amplifier using a 0.4 μm gate length and 50.4 mm gate width AlGaN/GaN HFET fabricated on a SiC substrate produced RF output power of 140 W with 25% PAE. The amplifier was operated with a pulse bias of 40 V [65]. A push–pull transmitter amplifier for 3G wireless base station applications was constructed using AlGaN/GaN HFETs fabricated on SiC substrates [66, 67]. At a drain bias of 50 V the amplifier produced 250 W RF output
3.3 Material parameters
111
power and, using digital predistortion linearization, an adjacent channel leakage power ratio (ACLR) of less than −50 dBc for four-carrier W-CDMA signals was obtained. Very high RF output power was obtained from wide gate width AlGaN/GaN HFETs fabricated on Si(111) substrates [67]. The individual HFETs had a gate width of 36 mm and when operated under CDMA modulation produced 20 W RF power with a drain efficiency of 27% when biased at a Vds = 28 V. The amplifier was fabricated using two of the devices and produced a maximum RF output power of 156 W with 65% drain efficiency at 2.14 GHz and no modulation. The same authors report further improvements by employing a source-grounded field plate on the HFET, and when biased at Vds = 60 V and under pulsed RF conditions, a saturated RF output power of 368 W with 70% PAE was obtained. Wide gate width devices require effective means for grounding, and a laser-assisted processing procedure for fabricating via holes was reported [68]. The process permits wide gate width devices to be effectively grounded, and a 20 mm gate width device biased at Vds = 26 V produced 41.6 W with 55% PAE at 2 GHz. Amplifiers fabricated using AlGaN/GaN HFETs have produced over 400 W of pulsed power with 600 MHz of bandwidth (2.9 to 3.5 GHz) and 50% PAE [69], a two-stage amplifier has produced 58 W with 38% PAE and 15 dB gain at X-band [70], and a MMIC amplifier has produced 500 mW RF power with 17% PAE and 12 dB gain in E-Band (71–95 GHz) [71]. The nitride devices are being aggressively developed for application in amplifiers for S-band communications band base station transmitters, and as amplifiers for X, Ka, and W-band radar transmitters.
3.3
Material parameters The DC and RF performance capability of electronic devices is fundamentally dependent upon the electronic, thermal, and mechanical properties of the materials from which the devices are fabricated. Of particular importance are the charge transport characteristics as a function of electric field for the material. Each semiconductor has a different velocityfield characteristic, and semiconductors of most interest for device fabrication will have high carrier velocity capability. The quality of semiconductor epitaxial material has continually improved, and the DC and RF performance of semiconductor transistors have experienced significant performance improvements as a result. A variety of technologies for growth of semiconductor epitaxial layers, such as molecular beam epitaxy (MBE) and organo-mellatic chemical vapor deposition (OM-CVD), have been developed and these technologies permit the growth of epitaxial layers of precise thickness and impurity doping concentration. It is now possible to fabricate solid state devices with layer thickness of only a few angstroms with precise defined impurity concentrations, and this level of control permits devices with frequency performance well over 100–300 GHz to be fabricated. The advantages of device fabrication from wide bandgap semiconductors can be seen from a comparison of fundamental electronic transport and material parameters. A summary of the semiconductor material properties most important to electronic device performance is listed in Table 3.1 for several semiconductors.
112
Wide band gap transistors – SiC and GaN – physics, design and models
Table 3.1 Material properties for several semiconductors Material
Eg (eV)
εr
σ (W/◦ K-cm)
Ec (V/cm)
Si GaAs InP 3C-SiC 4H-SiC 6H-SiC GaN Diamond
1.12 1.43 1.34 2.3 3.2 2.86 3.4 5.6
11.9 12.5 12.4 9.7 10.0 10.0 9.5 5.5
1.5 0.54 0.67 4 4 4 1.3 20–30
3 × 105 4 × 105 4.4 × 105 1.8 × 106 3.5 × 106 3.8 × 106 2 × 106 5 × 106
For transistors the most important material properties for fabrication of highperformance microwave structures include a large energy gap, Eg (eV), a low value of dielectric constant, εr , high thermal conductivity, σ (W/◦ K cm), and high critical electric field for breakdown Ec (V/cm). Wide energy bandgap generally translates into an ability to support high internal electric fields before electronic breakdown occurs, and also provides for improved radiation resistance. Most transistor fabrication has been in Si, GaAs, and InP and related compounds and the vast majority of all devices commercially available are fabricated from these materials. The SiC and GaN-based materials have energy bandgaps about two to three times larger than those in the conventional semiconductors, such as Si, GaAs, and InP. The dielectric constant is an indication of the capacitive loading of a device and affects the terminal impedance. Generally, for solid state devices a low value for the semiconductor dielectric constant is desired, and this permits a solid state device to be larger in area for a specified impedance value. Increased area permits larger RF currents and higher RF power to be generated. The wide bandgap semiconductors have dielectric constants about 20% lower than the conventional materials. This, in turn, permits a wide bandgap semiconductor device to be about 20% larger in area compared to a comparable device fabricated from Si or GaAs for a specific impedance magnitude, and increased area permits larger RF currents and higher RF power to be generated. The thermal conductance of the material is extremely important since this parameter indicates the ease with which dissipated power can be extracted from the device. Poor thermal conductivity results in device operation at elevated temperature with degraded performance. Conventional semiconductors are, in general, poor thermal conductors, particularly the GaAs and InP materials. Conversely, SiC is an excellent thermal conductor and GaN is about the same as Si, the best of the conventional semiconductors. Diamond has the highest thermal conductivity of any known material and is often used to fabricate heat sinks for semiconductor devices that must operate in high-power applications. Finally, the critical electric field for electronic breakdown should be high. This parameter is an indication of the strength of the electric fields that can be supported internally to the device before breakdown. High electric fields permit large terminal RF voltages to be supported, and this is necessary for the generation of high RF power. The critical fields for the wide bandgap materials are excellent and very high, typically an
3.3 Material parameters
113
Velocity (x107 cm/s)
10
4H-SiC GaAs
AIGaN/GaN 6H-SiC
1 Si GaN
0.1 1
10
100
1000
Electric Field (kV/cm)
Figure 3.2 Electron velocity versus electric field transport characteristics for various n-type
semiconductors (Nd = 1017 cm−3 ).
order of magnitude greater than for the conventional semiconductors. In general the wide bandgap semiconductors have more optimum values for all these parameters compared to conventional semiconductors. Basically, a current is defined as the movement of charge and expressed as the product between the charge density and transport velocity. Therefore, the DC and RF currents that flow through a device are directly dependent upon the charge carrier velocity versus electric field transport characteristics of the semiconductor material. Generally, for high currents and high frequency, high charge carrier mobility and high saturation velocity are desirable. A comparison of the electron velocity-electric field (v-E) characteristics for several semiconductors is shown in Figure 3.2. The v-E characteristic is described in terms of charge carrier mobility μn , (units of cm2 /V s) defined from the slope of the v-E characteristic at low electric field, and the saturated velocity vs (units of cm/s), defined when the carrier velocity becomes a constant, field-independent magnitude, generally at high electric field. The high value for electron mobility of GaAs (typically, μn ∼5000 cm2 /V s) is the main reason that FETs fabricated from this material have such excellent high frequency performance. A primary disadvantage of fabricating transistors from SiC and GaN is the relatively low values for the charge carrier mobilities (typically, μn ∼200–500 cm2 /V s). In general, the wide bandgap semiconductors have relatively low mobility, but very high saturation velocity (typically, v s ∼1–2 × 107 cm/s). However, the mobility of SiC and GaN is adequate for transistors designed for high power operation [72] due to the large RF terminal voltages these transistors can sustain. The low mobility produces a relatively high knee voltage (i.e., the transition voltage between the linear and saturation regions on the transistor I–V curve), but the ability of the device to produce good RF output power and PAE in amplifier circuits is not seriously compromised by the relatively high knee voltage due to the large RF terminal voltages, which are on the order of 10–20 times the magnitude of the knee voltage. In practice, near ideal PAE is obtained for amplifiers fabricated from wide bandgap semiconductor transistors, and
Wide band gap transistors – SiC and GaN – physics, design and models
mobility Sheet Charge Density
1015
1014
1013
1000 10
100
Sheet Charge Density (cm–2)
1016
10 000 2DEG Mobility (cm –2/V-s)
114
1012 1000
Temperature (K)
Figure 3.3 Electron mobility and sheet charge density versus temperature for a 2D electron gas from Shubnikov–DeHaas measurements [5].
the AlGaN/GaN HFET amplifiers obtain near-ideal PAE up to X-band, and potentially higher. For a typical device doping density of Nd ∼2 × 1017 cm−3 , the electron mobility for 6H- and 4H-SiC are about 250 cm2 /V s and 500 cm2 /V s, respectively. The factor of two increase in mobility for 4H-SiC compared to 6H-SiC is one of the major reasons that the 4H polytype is preferred for device applications. The electron saturation velocity in both 6H- and 4H-SiC is v s ∼2 × 107 cm/s, which is a factor of two higher than for Si (v s ∼1 × 107 cm/s) and a factor of four higher than for GaAs (v s ∼(0.5–0.6) × 107 cm/s). The mobility and saturation velocity for the 2DEG for the AlGaN/GaN heterointerface is very suitable for device applications. The room temperature mobility of the 2DEG is in the range of 1000–1500 cm2 /V s, which is significantly better than for SiC or bulk GaN. The sheet-charge density for this structure can be very high and greater than nss ∼1013 cm−2 due to piezoelectric and spontaneous polarization induced effects. The measured sheet-charge density is about a factor of five better than is obtained for the more commonly employed AlGaAs/GaAs heterostructure. The characteristics for the 2DEG are shown in the Shubnikov-DeHaas and Hall mobility measurements in Figure 3.3 [5] for an AlGaN/GaN heterostructure grown on a sapphire substrate. The measurement over temperature indicates that the 2DEG mobility is very sensitive to temperature, demonstrating about ∼T −2.3 dependence. This indicates that devices fabricated from this type of structure will be temperature sensitive and performance will degrade rapidly with elevated temperature. The magnitude of electric field that produces saturated charge carrier velocity is also important since the device must be able to develop the saturation field to obtain maximum RF performance and high-frequency operation. The saturation fields for 4H-and 6H-SiC are about Es ∼60 kV/cm and Es ∼200 kV/cm, respectively, which are high relative to the comparable values of Es ∼3 kV/cm and Es ∼35 kV/cm for GaAs and Si. The saturation field for the AlGaN/GaN heterostructure 2DEG is less than for either 6H- or 4H-SiC.
3.4 Transistor amplifier operating principles
Zs = Rs + jXS
Pin
Pout
Z in
Z out
115
IL VL
Network
ZL = RL + jXL
Vs
Figure 3.4 General two-port network used for amplifier analysis.
Hole mobilities in SiC and GaN-based materials are very low, and on the order of 10–50 cm2 /V-s, and it is very difficult to observe saturation effects for hole transport. Extremely low mobility requires very high saturation fields, which approach the critical field for avalanche breakdown. Low mobility also results in high values for resistance, which limits device performance. The low hole mobility presents serious problems for use of p-type wide bandgap material in devices. For this reason, most devices under development are majority carrier devices, such as FETs and static-induction transistors that can be fabricated using only n-type semiconductor material.
3.4
Transistor amplifier operating principles The basic configuration for an amplifier is shown in Figure 3.4 [73]. The amplifier is a two-port network that consists of a source that feeds the input with a load connected to the output. The network has gain and thereby amplifies a signal passing through it from the source to the load. RF power can only be generated from a real source (i.e., resistance) and delivered through a network to a real load (i.e., resistance). Since electronic devices and networks, as well as most microwave sources and loads, also include reactance it is necessary to employ reactive tuning to obtain optimum power transfer. Conjugately tuned output and load impedances deliver maximum RF output power from the source to the load. The power delivered to the load, PL , from the network can be written as PL =
1 1 Re VL I L∗ = |I L |2 R L 2 2
(3.1)
where VL and IL are the voltage and current at the load impedance, and RL is the real part of the load resistance. The power delivered to the load can be written as a function of the reflection coefficient at the load, PL = Pout 1 − | L |2
(3.2)
where Pout is the RF power available from the network and L is the reflection coefficient at the load. Maximum RF power transfer occurs for no reflection from the load, L = 0
(3.3)
Wide band gap transistors – SiC and GaN – physics, design and models
0.7 0.6 Drain Current (A)
116
−1 dB Compression
0.5
−3 dB Compression
0.4 0.3 0.2 0.1 0
Linear
−0.1 0
5
10 15 20 Drain Voltage (V)
25
Figure 3.5 Dynamic current-voltage load lines superimposed upon the DC I–V characteristics for a GaAs MESFET amplifier (the three dynamic load lines indicate operation for linear, −1 dB, and −3 dB compression conditions) [5].
This condition occurs when the load impedance is set to the complex conjugate of the network output impedance ∗ Z L = Z out
(3.4)
The amplifier PAE is P AE =
(G − 1) PL − Pin x100% = Pin x100% Pdc Pdc
(3.5)
where Pin is the RF power into the network, PDC is the DC power dissipated in the network, and G is the network gain, expressed as G=
PL Pin
(3.6)
The dynamic characteristics of an amplifier using a GaAs MESFET as the active device are illustrated in Figure 3.5, which shows dynamic load lines (i.e., I–V characteristics) for three conditions: linear operation; −1 dB in compression; and −3 dB in compression. The dynamic load lines are superimposed upon the DC I–V characteristics for the active device. For the situation shown in Figure 3.5 the GaAs transistor is biased with a drain-source voltage of Vds = 8 V, and the network is tuned for maximum PAE for each dynamic load line. Since RF power can only be generated by a real source and delivered to a real load, the dynamic load line would be a straight line oscillating up and down the DC load line for the network. However, since the device has capacitance, the dynamic load line demonstrates elliptical behavior. While the device is operating below saturation the load line is confined within the DC I–V characteristics. As the device is driven into saturation the dynamic load line shifts and extends outside the DC I–V characteristics on both the high-current and low-current portions of the RF cycle. The average value of the RF current also increases, indicating that the device DC current increases as the device is driven into saturation. The extension of the dynamic load line outside the DC I–V characteristics is possible due to the complex nature of the network. The total RF current consists of conduction and displacement components and
3.4 Transistor amplifier operating principles
117
although the conduction current is limited by the I–V characteristics, the displacement current maintains current continuity at the terminals. That is, as the device is driven into saturation the conduction current is clipped by the I–V characteristics for the device, but the total RF current continuity is maintained by displacement current. Device capacitance increases as it is driven into saturation and inductive tuning is necessary to obtain optimum RF performance. Optimizing the inductive external impedance to match the capacitive impedance of the transistor results in the reversal of dynamic load line direction, as shown in Figure 3.5. Under optimum tuning conditions the network is essentially a resonant circuit with the reactive energy shifting between the capacitive and inductive fields. As the network is driven further into saturation the current clipping behavior increases, with a net increase in both DC current and device capacitance. The dynamic behavior of the amplifier network defines the factors that determine the RF performance limits of the device and the materials from which it is fabricated. The power delivered to the load is a product of the RF voltage and RF current that can be established at the load, and this is determined by the active device. Semiconductors are limited in the bias voltage that can be applied by the critical electric field for breakdown of the semiconductor material. Therefore, semiconductors that have high critical electric fields for breakdown are desirable for power device applications. The critical field for breakdown is a function of bandgap energy and wide bandgap semiconductors are desirable for power applications. The I–V characteristics shown in Figure 3.5 can be used to explain the basic classes of amplifier operation. For example, if the transistor is biased at a DC voltage and DC current located near the middle of the I–V characteristic plane, and the input and output impedances are tuned so that the dynamic RF I–V characteristic is confined completely within the I–V characteristic plane, the amplifier will operate under class A conditions. The transistor is always in an ‘on’ state and the maximum PAE is 50%. By changing the gate (or base) bias to reduce the DC drain (or collector) current the dynamic I–V characteristic will begin to clip on the high-voltage portion of the RF cycle. The waveform clipping will result in no channel conduction current, but the RF waveform will be maintained by capacitive current. The reduction in the drain current will produce a reduction in the DC power dissipation within the transistor, and the waveform clipping will produce a reduction in the RF power delivered to the load. However, the reduction in the DC power dissipation occurs more rapidly than the reduction in the RF output power, with a result that the PAE increases. For a bias condition where one half of the RF waveform is clipped, the RF output power will decrease by a factor of two (−3 dB). The ideal PAE for this mode has a theoretical value of 78.5%. Although the PAE is increased, the half-sinusoid current waveform produces harmonics at the output, although it is linear in the sense that an x dB increase in the input power results in an x dB increase in output power until the device is driven sufficiently hard to cause clipping of the top of the current waveform. Linearity is very important for amplifiers designed for communications systems. Using two transistors in a push–pull configuration, where each transistor is in the ‘on’ state for one-half of the RF cycle, doubles the output power and hence extends the linear range while maintaining the high PAE. The penalty is
118
Wide band gap transistors – SiC and GaN – physics, design and models
the requirement for the additional transistor, along with the necessary RF circuitry to accomplish the final circuit. For operation between the class A mode and the ideal class B mode, the RF waveform is partially clipped and the PAE will be somewhere between 50% and 78.5%. This mode is generally termed class A-B, and many practical transistor amplifiers are designed to operate in this mode. This is necessary because real transistors have a soft-turn-on characteristic and so if operated in a pure class B mode then they are nonlinear at small signals and show a gain expansion region before saturating and then eventually entering the traditional nonlinear gain compression region. A very high-PAE mode can be obtained by biasing the transistor well below the voltage that permits channel conduction current to flow. In this mode, termed class C, the transistor only conducts during the peak of the voltage during the RF cycle. The current waveform becomes essentially a pulse. The ideal theoretical efficiency for class C is 100%, although this is only obtained with no power delivered to the load. Practical class C amplifiers, however, can be designed to operate with PAE in the 80–90% range. Electronic devices designed for microwave and RF applications operate in a transittime mode and are scaled in size by frequency considerations. Under normal operation the electric fields within the devices vary from low magnitude near the electron injection location to a magnitude sufficient to produce electron velocity saturation in the charge control/modulation region. Therefore, large current capability requires semiconductor materials that have high electron velocity. In general, both high-mobility and highsaturation velocity are desirable for high RF current. Traditional semiconductors such as Si and GaAs have electron saturation velocities that are limited to about vs = 1 × 107 cm/s, and this limits both the power that can be generated and the frequency response of the device. Wide bandgap semiconductors have electron saturation velocities that can be a factor of two higher. The combination of high-current and high-voltage capability make wide bandgap semiconductors very attractive candidate materials for fabrication of high-power and high-performance electronic devices.
3.5
Device design and RF performance The most promising devices for high-power, high-frequency RF applications are the 4H-SiC MESFET and the AlGaN/GaN HFET. Since the 4H-SiC MESFET can be fabricated entirely from n-type material the losses associated with use of p-type SiC can be avoided. The device is also relatively easy to fabricate due to a simple structure. The basic MESFET structure consists of a highly doped n-type epitaxial layer grown upon a highly resistive substrate, as shown in Figure 3.6. The drain-to-source current is thereby confined to the highly doped n-type layer. A control electrode (the gate) is located between the source and drain electrodes, which are designed to have ohmic current-voltage characteristics. The gate electrode is a nonlinear Schottky contact, which in normal operation is reverse biased, which creates a depletion region in the conducting channel, thereby permitting control of the drain-to-source current. Modulation of the voltage applied to the gate electrode permits the channel current to be modulated, and since a large channel current can be modulated with a small gate voltage, a large
3.5 Device design and RF performance
119
Figure 3.6 SiC MESFET structure.
n+ cap
n+ cap
Figure 3.7 AlGaN/GaN HFET structure.
transconductance (i.e., gain) is achieved. The magnitude of the transconductance and the upper frequency of operation of the device scale with reductions in gate length, and for this reason short gate lengths are desirable. In practice, gate lengths on the order of Lg ∼0.1–1 μm are routinely realized, and this permits operation with good gain to be realized above X and Ku-bands for SiC-based MESFETs. The AlGaN/GaN HFET is also readily fabricated and demonstrates excellent RF performance. These devices are similar to the MESFET, but differ in the semiconductor layer structure. A HFET structure is shown in Figure 3.7. Typically, an undoped layer of GaN is grown upon a highly resistive substrate, often SiC. A GaN buffer layer is often used to account for the lattice mismatch between the SiC and GaN layers. A thin updoped AlGaN layer is then grown upon the undoped GaN layer. The energy band discontinuity between the AlGaN and GaN layers creates an energy ‘notch’ at the heterointerface, and this results in the creation of a 2D electron gas (2DEG), which establishes a conducting path between the drain and source electrodes, which are fabricated in an analogous manner to the MESFET. A Schottky gate contact is located between the drain and source electrodes, as in the MESFET, and the same scaling rules apply. However, since the
120
Wide band gap transistors – SiC and GaN – physics, design and models
0.7 +Vgs = –1 V 0.6
Ids (A)
0.5
Vgs = –2 V
0.4 0.3
Vgs = –5 V
0.2 Vgs = –8 V
0.1 0 0
10
20
30
40
50
Vds (V)
Figure 3.8 DC I–V characteristics for a SiC MESFET (Nd = 1017 cm−3 , Lg = 0.5 mm,
W = 1 mm) [5].
electron transport characteristics are much superior in the nitride heterointerface 2DEG compared to the bulk SiC, the AlGaN/GaN HFET is capable of much improved RF frequency performance. In fact, the nitride devices are capable of RF operation with good gain well above 100 GHz. In the next section the DC and microwave performance of these devices is described, and performance projections are presented. The investigation makes use of theoretical simulations and the results are compared to experimental measurements. Excellent agreement between the simulated and measured data is obtained. Once the device simulator is calibrated and verified against experimental data, the simulator is used to determine the performance for optimized device structures. The optimized device structures are tuned in Class A and Class A/B amplifier networks to investigate predicted performance.
3.5.1
4H-SiC MESFET amplifier The MESFET, since it is a majority carrier device, is an ideal transistor for fabrication using wide bandgap semiconductors [7]. The DC I–V characteristics for a MESFET fabricated from 4H-SiC and with gate length Lg = 0.5 μm and gate width W = 1 mm are shown in Figure 3.8. The device has been optimized for microwave performance in X-band and has a uniform channel impurity doping density of Nd = 5 × 1017 cm−3 and a channel thickness of a = 0.15 μm. The conducting channel is grown on a high-resistivity, semi-insulating substrate. The transistor produces a maximum channel current of Idss = 550 mA and a maximum transconductance of gm = 65 mS/mm, which is low by GaAs MESFET standards where the transconductances are generally in the range of several hundred mS/mm for an X-band transistor. The I–V characteristics indicate a knee voltage where the channel current saturates, with a drain voltage of about 9 V, which is high by GaAs MESFET standards where the devices typically saturate at less than a volt.
3.5 Device design and RF performance
121
40
H21 (dB), Gmax (dB)
35 30 25 20 Gmax 15 10 H21 5 0 1
100
10 Frequency (GHz)
Figure 3.9 Current gain (H21 ) and power gain (Gmax ) small-signal RF performance versus frequency for a SiC MESFET amplifier [5].
Po (dB m), PAE (%), G (dB)
60 PAE
50 40
Po
30 20
G
10 0 0
5
10
15
20
25
30
35
40
Pin (dB m)
Figure 3.10 Large-signal RF performance versus RF input power for a SiC MESFET amplifier (Freq = 10 GHz, Vds = 40 V, Class A operation).
The small-signal current (h21 ) and power gains (Gmax) for the device are shown in Figure 3.9. Although the transconductance for the 4H-SiC MESFET is low by GaAs MESFET standards, the device produces a gain-bandwidth product of fT = 24 GHz and a maximum frequency of oscillation of fmax = 56 GHz. The fmax is high due to a high-magnitude output impedance, which permits high-voltage gain to be developed. The small-signal RF parameters shown in Figure 3.9 indicate that the device is capable of producing good RF output power through X-band, and potentially higher. This is demonstrated in Figure 3.10, which shows the operation of the transistor when operated in a Class A amplifier circuit. The amplifier is biased at Vds = 40 V and is tuned for maximum PAE at 10 GHz. The amplifier produces a maximum RF output power of
Wide band gap transistors – SiC and GaN – physics, design and models
60 PAE (%), Po (dB m), G (dB)
122
50 PAE 40 Po
30 20
G
10 0 0
5
10
15
20
25
30
35
Frequency (GHz)
Figure 3.11 RF performance versus frequency for a SiC MESFET amplifier (Vds = 40 V, Class A operation).
5 W/mm with a maximum PAE of 50%, the ideal value for Class A operation. The linear gain of the amplifier is 14.8 dB. These results are excellent and superior to those obtained from a comparable gate width GaAs MESFET, which can only produce RF output power on the order of ∼1–1.5 W/mm. The relatively low electron mobility of SiC and high-saturation knee voltage of the transistor do not limit the RF performance of the device because the 40 V drain bias that can be applied is sufficient for the region under the gate to operate in velocity saturation conditions and efficient gate modulation of the channel current is maintained [72]. The gate breakdown voltage for this transistor is Vg dB = 100 V, thereby permitting the 40 V drain bias to be applied without encountering RF breakdown phenomena. The small-signal RF parameters indicate that the amplifier should operate above the X band. To explore the performance of the amplifier as a function of frequency it is operated over a frequency range extending from 3 GHz to 30 GHz and tuned for maximum PAE. The results are shown in Figure 3.11. As indicated the amplifier produces near ideal class A performance through X-band (12 GHz). At 12 GHz the amplifier produces 4 W RF power with 48% PAE and 10 dB linear gain. Above X-band the gain and PAE decrease due to increased losses that result from the low electron mobility. The PAE decreases from 48% at 12 GHz to 26% at 30 GHz. The high-frequency gain is significantly reduced and at 30 GHz is only about 3 dB, which is too low for practical use. These results stem from extensive investigations and have been calibrated and verified with experimental results. The study indicates that 4H-SiC MESFET amplifiers will be useful through X-band, but will have limited application at higher frequencies. The low mobility of SiC produces relatively high access region and contact resistances that severely limit RF performance at frequencies above X-band.
3.5 Device design and RF performance
123
60 Po (dB m), PAE (%), G (dB)
PAE 50 Po
40 30 20
G 10 0 0
5
10
15
20
25
30
35
Frequency (GHz)
Figure 3.12 Large-signal RF performance versus frequency for an AlGaN/GaN HFET amplifier (Vds = 25 V, Class A operation).
3.5.2
AlGaN/GaN HFET amplifier FETs fabricated using the AlGaN/GaN heterostructure offer the potential to produce a class of devices with excellent DC and RF performance. The charge density and electron transport characteristics of the 2DEG at the heterointerface between the AlGaN and GaN layers are excellent, with very high sheet-charge density on the order of 1013 cm−2 routinely realized. This magnitude is typically a factor of five higher than for the AlGaAs/GaAs 2DEG used in GaAs-based HEMTs. The sheet-charge density is higher than would be expected from standard 2DEG theory and this has been shown to be due to piezoelectric and spontaneous polarization effects. The 2DEG at the AlGaN/GaN heterojunction has excellent charge transport characteristics and the saturation velocity has a magnitude of about 1–2 × 107 v/cm and mobility in the range of 1000–1500 cm2 /Vs at room temperature. The combination of high sheet-charge density and high carrier velocity result in high current capability for the transistor. In practice, high channel current is obtained from these structures, and AlGaN/GaN HFETs with maximum channel currents over 1 A/mm and approaching 2 A/mm are routinely obtained experimentally. The simulated microwave performance as a function of frequency for an optimized AlGaN/GaN HFET Class A amplifier tuned for maximum PAE is shown in Figure 3.12 [7]. The transistor has a gate length of Lg = 0.5 μm, and a width of W = 1 mm and is biased at Vds = 25 V and Vgs = −4 V. This gate bias would be expected from the DC I–V characteristics to place the amplifier in class A operation. However, due to rectification effects under overdriven large-signal operation the transistor bias point shifts as a function of frequency and the amplifier shifts between class A and class AB operation from 3 GHz to 18 GHz. This is evidenced by the PAE, which was over 50% from 3 GHz to 25 GHz. The PAE peaked at about 58% from 12 GHz to 18 GHz. At frequencies above 18 GHz the PAE decreases to about 44% at 30 GHz due to increased
Wide band gap transistors – SiC and GaN – physics, design and models
60 Po (dB m), PAE (%), G (dB)
124
50 PAE 40 Po 30 20 G 10 0 0
5
10
15 20 Frequency (GHz)
25
30
35
Figure 3.13 Large-signal RF performance versus frequency for an AlGaN/GaN HFET amplifier optimized for high RF output power (Vds = 25 V, Class A operation) [5].
losses. The amplifier produces RF output power of about 3–5 W over the frequency range of 3 GHz to 30 GHz, which is excellent for a HFET with a 1 mm gate width. The linear gain is above 10 dB from 3 GHz to 18 GHz, and is still at 9 dB at 30 GHz. FETs can be designed to maximize RF output power, gain, or PAE, but it is, in general, not possible to obtain optimum performance for all three parameters simultaneously [74]. For the transistor described here, the modification of the structure for increased channel current and with retuning of the input and output impedances for an optimized combination of performance measures, it is possible to get an RF output power on the order of 10–12 W/mm while maintaining high PAE at high operating frequencies, as shown in Figure 3.13. In fact, even higher RF output power could be obtained, but at the expense of PAE and gain, which rapidly degrade as operating frequency is increased. In fact, a spot RF output power density greater than 30 W/mm at 4 GHz has been reported [45] for a transistor having Lg = 0.5 μm with a drain bias of Vds = 120 V. The breakdown voltage for the transistor was reported to be VdB = 170 V, which indicates that significant channel breakdown occurred on the high voltage portion of the RF cycle. Nevertheless, the peak PAE was 54.8% with an associated gain of 14 dB. For the results shown in Figure 3.13, the device is biased at Vds = 40 V and the gate bias is adjusted for Class A operation, which results in good PAE. The PAE is about 50% from 3 GHz to 10 GHz, and declines monotonically above X-band. However, at 30 GHz the PAE is still 30%. The gain remains above 10 dB up to about 25 GHz, and is still 8 dB at 30 GHz. By retuning for reduced PAE and gain it is possible to further increase the RF output power to slightly greater than 12 W/mm. These results indicate that AlGaN/GaN HFETs are capable of excellent DC and RF power performance well into the mm-wave frequency spectrum, and potentially well above 100 GHz. Excellent W and E-band RF performance has been reported [71, 75], and an E-band amplifier produced 500mW output power with 12 dB associated gain with about 10% PAE. With transistor power combining technology amplifiers with hundreds
3.6 Transistor DC and large-signal RF models
Iin
Vin
125
Iout Two-Port Network
Vout
Figure 3.14 Small-signal two-port network.
to thousands of watts of RF output power should be achievable. These amplifiers may be capable of competing with vacuum tube amplifiers in many applications.
3.6
Transistor DC and large-signal RF models Mathematical models for transistors find wide application for both device structure optimization and circuit design applications. Basically, there are two major types of model in practice: (1) equivalent circuit oriented models that are used in DC and RF circuit and system design applications; and (2) models that are based upon semiconductor device physics. The equivalent circuit based models require that the transistor be fabricated and characterized before the model can be defined. However, once defined, the model can be used in RF circuit and system design applications and it provides a means to investigate RF circuit performance and optimization without the need to actually fabricate the circuit until an optimized design is determined. The equivalent circuit models have been extensively developed and a variety of models are now readily available in virtually all commercially available simulators. The equivalent circuit based models are only accurate over the range of parameters for which they were defined, and often fail when extended outside these parameters. For this reason, new models are continually being derived and reported in the literature. The physics-based models offer an alternate approach. These models are based upon the fundamental semiconductor device equations and can be used to investigate the physical operation of the transistor before fabrication occurs. In this manner, the physics-based models can be used to investigate anomalous physical phenomena that are observed to occur in the transistor under various operating conditions, as well as for device design optimization applications. The physics-based models are, in general, more difficult to develop and require more intense computer resources for solution. The models are significantly more difficult to integrate into circuit and systems level simulators, and most of these models have been developed as stand-alone device level simulators. A variety of these simulators is commercially available and are very useful, particularly for device design optimization applications.
3.6.1
Equivalent circuit transistor models Equivalent circuit models for transistors follow from linear two-port circuit analysis. For example, a linear two-port can be represented by the block diagram shown in Figure 3.14. The input to the circuit block has input current and voltage, iin and vin ,
126
Wide band gap transistors – SiC and GaN – physics, design and models
Cgd
Rg
Rd
g Cgs
gm τ
Ri
rds
d
Cds
Rs s
Figure 3.15 Small-signal tee-equivalent circuit for FETs.
and the circuit block output has output current and voltage, iout and vout . Any two of the four variables may be selected as the independent variables, and the other two as the dependent variables and network equations established. For transistor applications it is common to select a combination of the input voltage, vin , and the output current, iout , as the dependent variables, and the input current, iin , and the output voltage, v out , as the independent variables. The network can then be described by the matrix equation vin h 11 h 12 i in = (3.7) i out h 21 h 22 vout This formulation can be used to define the equivalent circuit model for the transistor. The various h-parameter terms take on a physical meaning. For example, the h11 term has units of resistance and represents the input impedance to the network when a shortcircuitis placed at the output terminals. Likewise, the h22 term has units of Siemens (inverse ) and is the output admittance when an open circuit is placed at the input terminals. The h21 parameter has no units, and represents the output current normalized to the input current, which is the forward current gain for the network. Likewise, the h12 parameter is the input voltage normalized to the output voltage, which is the reverse voltage gain for the network. Other formulations are possible depending upon the parameters selected as the dependent and independent variables. Since the entire network is linear, one set of parameters is easily converted to another through simple linear transformations. The formulation permits an equivalent circuit for the transistor to be established. All that needs to be done is to determine a configuration of circuit elements that replace the general network block and that generate the exact same dynamic response at the network terminals as the original circuit. Various circuit configurations can be developed, such as the hybrid-pi, or the T (tee) circuit. For microwave transistors the tee circuit is most commonly used. The basic circuit is shown in Figure 3.15, and various circuit elements are also included to indicate various parasitic elements associated with transistor operation. The equivalent circuit is ‘exact’ in that it accurately reproduces the linear electrical response of transistor performance and the main elements of the equivalent circuit can be directly derived mathematically from the original two-port network. The
3.6 Transistor DC and large-signal RF models
127
equivalent circuit is very useful for small-signal characterization of the transistor since the equivalent circuit element values can be directly determined from measured data by a parameter extraction process. Suitable routines are available and numerous practical techniques have been extensively reported in the literature. Parameter extraction software is commercially available from a variety of vendors. Nonlinear models for large-signal RF performance have been determined, based upon the linear equivalent circuit model for the transistor. However, this process is not exact, and it is, in general, not possible to theoretically derive an accurate nonlinear largesignal model directly from the linear equivalent circuit. Although many large-signal equivalent circuit models have been reported in the literature and are readily available in commercial RF circuit simulators, all of the models have been derived by developing nonlinear expressions for the various equivalent circuit elements and then using the resulting expressions to ‘define’ the large-signal equivalent circuit model. The procedure can become complex, and generally the linear equivalent circuit model is reduced to the most important, basic equivalent circuit elements, which are then characterized by nonlinear functions of various combinations of input and output current and voltage. The reduced equivalent circuit showing only the basic circuit elements is shown in Figure 3.16. The most important elements are the current generator and the input capacitance, and nonlinear expressions based upon power law, tanh(Vds ), Volterra Series, etc. formulations have been developed. As the model development progresses, additional elements in the equivalent circuit can be formulated as nonlinear functions and included in the model. The resulting equivalent circuit model can accurately predict the largesignal RF performance of the transistor, but requires that the parameters in the nonlinear expressions be determined. The only way this can be accomplished is by an experimental parameter extraction process whereby the nonlinear terms can be determined from measured data. The complete model can be complex, with the requirement to define many parameter values from the extracted measurement data. Many techniques for accomplishing this have been reported in the literature and most commercially available circuit and systems simulators include suitable large-signal parameter extraction routines. A major issue with the large-signal equivalent circuit models is that, since they are based upon experimental extraction of the nonlinear elements, they are generally accurate only for the range of parameters over which they have been calibrated. When the model is driven to regions outside the original characterization space, there is no reason to expect the circuit response to be accurate. In fact, the models often fail. For this reason new models are continually being developed and reported. Each iteration and new equivalent circuit model development effort is directed towards solution of a previously observed or reported failure. The new model, of course, also requires determination of the element parameter values by experimental extraction and calibration with measured data. The process requires that transistors be fabricated and characterized before a suitable model can be developed, and many transistor manufacturers routinely produce equivalent circuit models for their transistors. However, these manufacturer’s models generally only consider typical operating range data, and specific applications may require that a new model be defined. However, once the equivalent circuit models are determined they have proved very useful in circuit design applications.
128
Wide band gap transistors – SiC and GaN – physics, design and models
Idg (Vout, Vin)
Cdg
Rg
Gate
Rd Drain
Cgs (Vin, Vout) Vin(t)
Igs (Vin)
Ids (Vin, Vout) Rds
Rin
Cds
Vout(t)
Rs Source Nonlinear Circuit Elements Idg (Vout – Vin)
Drain-gate voltage-controlled current source due to drain-gate avalanche breakdown
Igs (Vin)
Gate voltage-controlled current source due to forward biasing of the gate
Ids (Vin,Vout)
Drain-source voltage-controlled current source
Cdg (Vout – Vin)
Drain-gate capacitance
Cgs (Vin,Vout)
Gate-source capacitance
Cds (Vout)
Drain-source capacitance
Rin (Vin,Vout)
Gate-source charging resistance
Rds (Vin,Vout)
Drain-source resistance
Figure 3.16 Large-signal tee-equivalent circuit for FETs.
3.6.2
Physics-based large-signal transistor models An alternate approach to the development of transistor models is based upon solution of the basic semiconductor device equations. The semiconductor equations consist of: (a) the current density equations for electrons and holes, J n = qμn n E + q Dn ∇n
(3.8)
J p = qμ p p E − q D p ∇ p
(3.9)
and
where J is the current density, μ is the charge carrier mobility, n, p are the free electron and hole densities, and D is the diffusion coefficient.
3.6 Transistor DC and large-signal RF models
129
(b) The continuity equations for electrons and holes, 1 ∂n n − n0 + ∇ · J n = ∂t τn q
(3.10)
p − p0 ∂p 1 = − ∇ · J p ∂t τp q
(3.11)
and
where no and po are the thermal equilibrium density of electrons and holes, and τ n and τ p are the electron and hole recombination lifetimes. (c) Faraday’s Law, ∂ B ∇ × E = − ∂t
(3.12)
which completes the basic set of equations, where E and B are the electric and magnetic fields. These equations can be solved simultaneously to develop a model for a semiconductor device. Generally, solutions to these equations applied to a transistor structure are complex and difficult to solve analytically. However, the equations are readily solved using numerical techniques and a variety of simulators based upon either finite-difference or finite-element methods have been reported and are commercially available. These device level simulators permit detailed investigation of the physical operation of the device and can be used to both investigate phenomena observed in experimental measurements or they can be used for device design and optimization studies. In general, these simulators require significant solution time and are difficult to employ in circuit-level simulators. The physical models, however, can be extremely accurate as all phenomena known to affect device performance can be included. The physical models take as input data the device structure, semiconductor material and transport parameters, and bias conditions. The model can be set to take the voltage applied to the device terminals as input data and return the resulting currents that flow, or set up to take the current applied to the terminals as input data and return terminal voltages. The device input and output impedances can then be calculated from the terminal voltages and currents. The physical models are extremely flexible and can be modified to include phenomena that are found to affect device performance, such as charge trapping, breakdown mechanisms, surface and interface charging and discharging, and leakage currents, etc. Additionally, the device models can be modified to include transient and nonequilibrium phenomena, ballistic transport effects, and quantum physics behavior. These effects will increase the complexity of the model and generally increase the simulation time, but the resulting model can be made extremely accurate. Device simulators of this type find wide application in device investigations of operational physics, however, the models are generally not suitable for inclusion in circuit-level simulators. It is possible to generate a modified physics-based model that is suitable for integration into circuit and systems-level simulators [76]. In order to accomplish this, it is necessary to compromise the formulation between inclusion of pertinent physical phenomena and
130
Wide band gap transistors – SiC and GaN – physics, design and models
solution efficiency. The goal is to produce a model that maintains the important physical phenomena that dominate device performance, while producing a model that can be very quickly and efficiently solved. In this manner the utility of the physics-based approach can be coupled with the simulation efficiency of the equivalent circuit-based approach. The model development proceeds by coupling a two-dimensional Poisson equation solution technique with a one-dimensional current density equation. By focusing the Poisson equation solution on the area under the gate electrode in a FET an analytic solution can be obtained [76]. The Poisson solution permits the electric field within the transistor to be calculated as a function of structure, impurity doping, and bias conditions. The electric field is then used to calculate the channel current density with use of the current density equation. This approach works well for structures where the channel is narrow so that the current flow is essentially one-dimensional. In fact, this model approach results in a physics-based transistor model that retains the accuracy of the physics-based approach, but can be solved in an efficient manner. The model can be integrated into circuit and systems-level simulators with great success. The simulation work reported in this chapter makes use of the model described above, which has been modified for use with wide bandgap semiconductor devices. Excellent results are obtained and the model very accurately predicts the DC and RF performance obtained experimentally.
3.7
Large-signal effects The wide bandgap semiconductor FETs are candidates for high-RF power applications since they can operate under high-voltage and high-current conditions. However, under these operating conditions the devices experience a variety of physical phenomena that affect their performance, and in some cases, produce deviations from the expected response. In most cases the phenomena are natural physical responses to the very high voltages and currents that occur under RF large-signal operation. The most significant of these phenomena are described in this section.
3.7.1
Space charge limited current transport Under high-current conditions the injected charge in a semiconductor can become comparable in magnitude to the background impurity density and space-charge limited transport can occur [77, 78, 79]. This condition can be achieved in practical devices under large-signal RF operation when high-magnitude input RF power is applied. The voltage that can be supported by a semiconductor device is limited by the internal resistance, and when high input power is applied, the injected current will increase to satisfy the boundary conditions imposed by the applied source. Generally, under these conditions the input impedance to the device is driven to a reduced magnitude, and although some of the input power is reflected by the reduced impedance of the device,
3.7 Large-signal effects
131
current injection increases. The injected charge and the internal electric field are related, as expressed by Poisson’s equation, dE q (3.13) = (Nd − n) dx ε where E is the one-dimensional electric field in the direction of current flow, Nd is the effective donor density that represents the positive polarization/piezoelectric charge in HFETs, n = n o + δn is the free electron density where n o is the thermal equilibrium density of charge, and δn is the density of injected charge. The thermal equilibrium density of electrons is essentially equal to the donor density (i.e., n o ∼ = Nd ) and when the injected charge becomes comparable in magnitude to the thermal equilibrium density of electrons Poisson’s equation is written as q q dE = (Nd − n o − δn) ∼ (3.14) = − δn dx ε ε Under high-injection conditions the electric field is reduced in magnitude as a function of increasing charge injection, and the resistivity and resistance of the semiconductor material become a function of current injection. This effect can become significant for semiconductor devices operated under high-current injection conditions. For low-level injection conditions where δn no , the E field is essentially independent of injection level. In order to determine the conditions under which space-charge effects become significant, it is illustrative to solve equation (3.13) analytically. The current density is J = qnv
(3.15)
where J (A/cm2 ) is the magnitude of the current density and v (cm/s) is the nonlinear velocity–field curve, which is modeled as v=
μE 1 + |E| /E sat
(3.16)
where μ (cm2 /V s) is the low field mobility and E sat (V/cm) is the magnitude of electrical field that produces velocity saturation, expressed as Esat = vsat /μ = 8.0 kV/cm.
(3.17)
Equation (3.13) can be written in the form: λ dE J E + E sat = −1 + E sat d x Jsat E
(3.18)
where the λ parameter is λ=
εE sat q Nd
(3.19)
and has the dimensions of length. The λ parameter is typically very small for an AlGaN/GaN heterojunction 2DEG, since the effective doping is very high.
Wide band gap transistors – SiC and GaN – physics, design and models
D = 3.5 μm
0.8
D = 2.5 μm Resistivity (Ω-cm)
132
0.6 D = 1.5 μm 0.4
D = 0.5 μm
0.2
0 39
39.5
40
40.5
41
Current Density (MA/cm2)
Figure 3.17 Semiconductor resistivity versus current density at the onset of space–charge limited transport (the various curves indicate resistivity determined at locations from the current injection point) [77].
The solution of equation (3.18) depends on its magnitude at x = 0 which should reflect a combination of low E and high n. For the limiting case E(0) = 0, equation (3.18) has a solution: (Jsat −J )2 x E sat J (3.20) E(x) = 1 + W −e−1− Jsat J λ Jsat − J that can be simply written in terms of the principle real branch of the Lambert W function for J < Jsat and the other real branch of W for J > Jsat . In equation (3.20), the length scale L J = λ Jsat J (Jsat − J )2
(3.21)
is larger than the length scale λ of equation (3.19) but is still less than an Angstrom for ∼ J = 12 Jsat . L J diverges near J = Jsat . The resistivity, ρ = E J , as a function of distance from the source for semiconductor fabricated using an AlGaN/GaN heterojunction 2DEG is shown in Figure 3.17. The resistivity is essentially independent of J until a critical threshold current, JSC , is achieved. In this example JSC ≈ 39.6 MA/cm2 . For a current density in excess of JSC the resistivity increases rapidly both with current, and with distance from the source injection point. Therefore, once space-charge limited transport conditions are established, the resistivity of a semiconductor will rapidly increase, and the effect is more significant with the length of the semiconductor region. The analytic solution of equation (3.18) is continuous at J = Jsat but its character changes. For J < Jsat , E(x) ∼ = E sat J (Jsat − J ) is almost independent of x except in the
3.7 Large-signal effects
region 0 < x < L J where E(x) ∝ linearly with x. Furthermore,
√
133
(J −J ) x. For J > Jsat , E(x) ∼ = x εvsatsat increases almost
E(x) = E sat J (Jsat − J )
(3.22)
is a second exact solution of equation (3.18) for J < Jsat , in addition to being an approximation of equation (3.20) in the region x > L J near the gate edge. In contrast to equation (3.20), however, equation (3.22) is not continuous at Jsat and is not physical at J = Jsat . This peculiar situation raises the possibility of mode-switching between the continuous solution and the constant solution. The mode-switching transition may occur for L J > L sg , when the length scale L J of equation (3.21) exceeds the length of the access region. This transition would be abrupt in practical devices where L sg is ˚ on the order of a micron and is much larger than λ = .32
A, the length parameter of equation (3.19), because L J > L sg only for J Jsat > 1 − λ L sg as J approaches Jsat . The magnitude of the JSC threshold current is approximately given by the expression JSC ∼ = q Nd vsat
(3.23)
and for a heterojunction 2DEG, it is assumed that Nd ∼ = n ss / h, where h is the width of the 2DEG quantum well. For a typical AlGaN/GaN 2DEG space-charge effects are expected to set in for a threshold current in the range of JSC ≈ 40 MA/cm2 . This is lower than the current density measured in experimental devices. Practical devices generally have a maximum drain current of Ids ≈ (1 − 1.2) A/mm, and for a quantum well width ˚ the current density is in the range of J ≈ 50 MA/cm2 . This indicates of about h = 25 A, that these devices most likely operate under space-charge limited conditions, particularly during the high-current portion of the RF cycle. In addition, the magnitude of JSC is expected to vary with n ss and vsat , and these parameters vary in magnitude with DC and large-signal RF operating conditions. The magnitude of JSC , therefore, can vary with HFET bias and RF drive, and this increases the nonlinearity of the gate-source resistance for an HFET under large-signal drive.
3.7.2
Nonlinear source and drain resistance The onset of space-charge limited current transport in a microwave HFET under largesignal operation will cause the source and drain resistances to significantly increase during the high-current portion of the RF cycle. Although both the source and drain resistances are affected, the increase in source resistance has the most significant effect upon transistor performance. The drain resistance is essentially in series with the relatively high-magnitude output load resistance and, therefore, the increase in the device drain resistance has minimal effect upon device performance. The source resistance, however, is common to the transistor input and output, as indicated in the tee-equivalent circuit, as shown in Figure 3.16, and any increase in source resistance will degrade the transconductance of the transistor by reducing the voltage that drives the current generator. For this reason it is imperative to reduce the source resistance in a FET to the greatest
134
Wide band gap transistors – SiC and GaN – physics, design and models
Cgsi
gmi
Rgs
Figure 3.18 Simplified equivalent circuit for a FET with a nonlinear source resistance.
Cgsext
gmext
Figure 3.19 Simplified equivalent circuit for a FET with the nonlinear source resistance transformed to the gate capacitance and transconductance.
possible extent. The increase in source resistance due to the onset of space-charge limited transport conditions will degrade transistor performance, both by decreasing the gain capability of the transistor, and by introducing undesirable nonlinearity. The effect of the nonlinear source resistance can be seen by reducing the equivalent circuit in Figure 3.16 to its basic circuit elements, as shown in Figure 3.18. This equivalent circuit can be transformed to the equivalent circuit shown in Figure 3.19 by rewriting the element values as gm i (3.24) gm ext = 1 + Rgs gm i + jω R gs C gsi and C gsext =
C gsi . 1 + R gs gm i + jω Rgs C gsi
(3.25)
In these expressions gm ext and C gsext are the transconductance and gate-source capacitance that are observed at the input to the equivalent circuit in Figure 3.18 and gm i and C gsi are the transconductance and gate-source capacitance intrinsic to the transistor, and represented by the equivalent circuit shown in Figure 3.19. For low frequencies, these equations simplify to gm i gm ext ∼ (3.26) = 1 + Rgs gm i and C gsext ∼ =
C gsi . 1 + Rgs gm i
(3.27)
According to equations (3.26) and (3.27), both the transconductance and gate-source capacitance observed at the terminals of the transistor will decrease as the gate-source resistance increases. The decrease in C gsext is particularly interesting, since this indicates that the magnitude of the input impedance to the HFET will increase as the device is driven into saturation. This is opposite to the normal operation of a FET, where the input impedance is driven to a lower magnitude as the device is driven into saturation.
3.7 Large-signal effects
135
2
Cgs (pF)
1.5
1 Eqn( ) Cgs_4_0_20 0.5
Eqn( ) Cgs_4_0_30
0 –4
1
6
11
16
21
Pin (dB m) (GHz)
Figure 3.20 Measured gate–source capacitance as a function of RF input power for an AlGaN/GaN HFET for Vds = 20 V, and Vds = 30 V.
The behavior indicated in equation (3.27) is supported by measured data, as shown in Figure 3.20. In this figure the measured input capacitance as a function of input RF power drive is shown for an AlGaN/GaN HFET. The increased RF power drive causes increased channel current, which has a magnitude sufficient to exceed the threshold for spacecharge limited current transport. The SCL current conditions produce an increase in the gate-source resistance, which produces the reduction in C gsex as expressed in equation (3.27). The C gsex magnitude is reduced by almost a factor of two over the measured range of input power, and this produces an increase in the device input impedance by a corresponding factor. The SCL current transport phenomenon has the desirable result of increasing the terminal impedances, which make it easier to design the transistor input amplifier, and other circuits. The onset of space-charge limited current can theoretically affect both depletion mode HFETs, as well as enhancement mode MOS type FETs (e.g., Si LDMOS FETs). The depletion mode HFETs have an inherent advantage of lower input capacitance compared to the enhancement mode FETs for a constant RF output power and supply voltage due to geometrical factors (e.g., thicker dielectric layers that result in the conducting channel being located farther from the gate electrode). It should be noted that the onset of space-charge limited current and the increase in the gate-source resistance under large-signal operation conditions has not been observed in the normal operation of Si LDMOS FETs or compound semiconductor MESFETs and HEMTs. The affect is commonly observed and appears to dominate in the nitride-based HFETs, most likely due to the higher current densities and internal electric fields under which the wide bandgap semiconductor nitride-based HFETs operate. The measured and simulated performance of the source and drain resistances as a function of current for an AlGaN/GaN HFET are shown in Figure 3.21. As shown, once
Wide band gap transistors – SiC and GaN – physics, design and models
12
10 Simulated 8 Rs, Rd (Ohm)
136
Measured
6 Rs 4 Rd 2
0 –0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Drain Current (A)
Figure 3.21 Measured and simulated source and drain resistances as a function of drain current for an AlGaN/GaN HFET.
space-charge limited current transport conditions are achieved the source and drain resistances demonstrate current-dependent characteristics and increase with current drive. In fact, simulations indicate that under high-current drive conditions the source and drain resistance for the HFET can increase by up to an order of magnitude. The effect of a nonlinear source resistance upon on an HFET amplifier circuit can be significant. This can be shown by a circuit simulation in which a nonlinear, currentdependent source resistance is included [77, 80]. For this study, a harmonic-balance simulator that includes a physics-based FET model [76] is used. The HFET device model has been modified by inclusion of a source resistance in the form Rs = rss + rss =
rss 1−
I
,
(3.28)
I SC
where Rs is the source resistance, rss is the low-current magnitude of the resistance in the gate-source region, r ss is the increase in resistance after the onset of spacecharge effects, and I SC is the space–charge threshold current previously discussed. The nonlinear source resistance is a function of the time-dependent RF current and is included on the time domain, nonlinear side of the harmonic-balance interface. In this manner the source resistance is a function of the conduction current in the transistor. The modified simulator was used to investigate the DC and RF operation of a communications band AlGaN/GaN HFET amplifier. The HFET device had a gate length and width of L g = 0.8 μm and W = 0.4 mm, respectively. The device was biased with a drain voltage of Vds = 28v and was operated class A-B at a frequency of F = 2.14 GHz. The device demonstrated premature gain compression and was, therefore, selected as a
3.7 Large-signal effects
137
0.4 Vgs = +1 V
Vgs = 0 V
Drain Current (A)
0.3
Vgs = –1 V 0.2 Vgs = –2 V
0.1 Vgs = –3 V Vgs = –4 V 0 0
5
10
15
20
25
Drain Voltage (V)
Figure 3.22 Measured and simulated DC I–V characteristics for an AlGaN/GaN HFET
(Lg = 0.8 mm, W = 0.4 mm) [77].
candidate to determine if a nonlinear source resistance could explain the gain compression behavior. The measured and simulated DC I–V characteristics for the HFET are shown in Figure 3.22. As indicated in Figure 3.22, excellent agreement between the measured and simulated data is obtained. In the simulation a low-field mobility of μ = 1500 cm2 /V − sec and an electron saturation velocity of vsat = 1.25 × 107 cm/sec were used. The mobility was measured and the saturation velocity was adjusted to get agreement with the measured I–V characteristics. The saturation velocity used is below the theoretical value for electrons in an AlGaN/GaN 2DEG, but is consistent with measured data. Without inclusion of the current-dependent nonlinear source resistance, the simulated current increasingly deviated from the measured data as the gate bias voltage was increased from pinch-off and adjusted for increasing channel current. The measured and simulated RF performance and the DC drain and gate current as a function of input power to the amplifier are shown in Figures 3.23, 3.24, and 3.25, respectively. In the simulation seven harmonics were used in the harmonic-balance routine. The amplifier was tuned for maximum PAE. Excellent agreement between the measured and simulated device performance and the DC drain and gate current are obtained. The amplifier produced a peak PAE of 53%, with RF output power of 34 dBm and a gain of 19 dB. The linear gain for the amplifier was 25 dB. The experimental amplifier demonstrated premature gain compression and a degradation of gain beginning at an input power of slightly below about 0 dBm. Significantly, the simulated results accurately predict the change in slope of the gain response, as shown in Figure 3.23. The
Wide band gap transistors – SiC and GaN – physics, design and models
55 Sim. Po Meas. Po Sim. G Meas. G Sim. PAE Meas. PAE
50
Po (dB m) Gain (dB) PAE (%)
45 40 35
Nonlinear Source Resistance Onset
30 25 20 15 10 5 0 –10
–5
5
0
10
15
20
Input Power (dB m)
Figure 3.23 Measured and simulated RF output power, gain, and PAE versus RF input power for an AlGaN/GaN HFET amplifier (freq = 2.14 GHz, Vds = 28 V, Class AB) [77].
0.18 0.16
Simulated Measured
0.14 Drain Current (A)
138
0.12 0.1 0.08 0.06 0.04 0.02 –10 –8 –6
–4 –2
0
2 4 6 8 10 Input Power (dB m)
12 14
16
18 20
Figure 3.24 Measured and simulated DC drain current versus RF input power for an AlGaN/GaN HFET amplifier (freq = 2.14 GHz, Vds = 28 V, Class AB) [77].
3.7 Large-signal effects
139
0.001 0.0008
Gate Current (A)
0.0006 0.0004 0.0002 0 –0.0002 –0.0004 –10 –8 –6 –4 –2
0
2
4
6
8
10 12 14 16 18 20
Input Power (dB m)
Figure 3.25 Measured and simulated DC gate current versus RF input power for an AlGaN/GaN HFET amplifier (freq = 2.14 GHz, Vds = 28 V, Class AB).
2
Pin = 14.8 dB m Pin = 0.0 dB m
Gate Voltage (V)
0 –2 –4 –6 –8 –10 0 (a)
50
100
150
200
250
300
350
400
450
500
Time (ps)
Figure 3.26a RF gate voltage versus time response for an AlGaN/GaN HFET amplifier (the two waveforms indicate operation at the onset of space–charge-limited transport, and under maximum PAE).
simulator predicts both the change in gain slope at Pin = 0 dBm, and the gain saturation that occurs after maximum PAE is achieved. The change in gain slope is caused by the onset of space-charge limited current transport conditions. The time domain voltage and current waveforms at the gate and drain terminals are shown in Figures 3.26 and 3.27. Figures 3.26a and 3.26b show the voltage
Wide band gap transistors – SiC and GaN – physics, design and models
0.2 Pin = 14.8 dB m Pin = 0.0 dB m
0.15
Gate Current (A)
0.1 0.05 0 –0.05 –0.1 –0.15 –0.2 0
50
100
150
200
(b)
250
300
350
400
450
500
Time (ps)
Figure 3.26b RF gate current versus time response for an AlGaN/GaN HFET amplifier (the two waveforms indicate operation at the onset of space-charge-limited transport conditions, and under maximum PAE.
60 50 Drain Voltage (V)
140
Pin = 14.8 dB m Pin = 0.0 dB m
40
30
20
10
0 0 (a)
50
100
150
200
250 300 Time (ps)
350
400
450
500
Figure 3.27a RF drain voltage versus time response for an AlGaN/GaN HFET amplifier (the two
waveforms indicate operation at the onset of space–charge-limited transport conditions, and under maximum PAE).
and current waveforms at the gate terminal under low drive (Pin = 0 dBm) and large-signal operating conditions where the input power is sufficient to produce maximum PAE. The same waveforms at the drain terminal are shown in Figures 3.27a and 3.27b.
3.7 Large-signal effects
141
0.4 0.35
P in = 14.8 dB m P in = 0.0 dB m
Drain Current (A)
0.3 0.25 0.2 0.15 0.1 0.05 0 –0.05 0 (b)
50
100
150
200
250
300
350
400
450
500
Time (ps)
Figure 3.27b RF drain current versus time response for an AlGaN/GaN HFET amplifier (the two waveforms indicate operation at the onset of space–charge-limited transport conditions, and under maximum PAE).
For the low RF drive Pin = 0 dBm condition, the gate voltage and current are essentially low-amplitude sinusoids, as expected. Since the Pin = 0 dB drive condition is sufficient to produce some saturation, a slight deviation from pure sinusoidal behavior is noted, particularly in the RF voltage. The shift in phase in the gate RF voltage waveform at the higher drive condition shown in Figure 3.26a is due to the shift in gate-source capacitance at the higher drive levels, as previously discussed. As the device is driven into saturation the gate voltage grows in amplitude and shows the effects of harmonic generation. The gate RF current waveform shown in Figure 3.26b becomes highly nonlinear as the device is driven into saturation, and the seven harmonics are clearly evident. The mechanism that causes the nonlinearity is not evident in the gate terminal waveforms. The gate voltage does not obtain a magnitude sufficient to cause either forward or significant reverse conduction of the gate electrode. Some reverse conduction does occur and this generates a small, but finite, DC reverse conduction in the gate electrode. The small negative reverse gate conduction was observed in both the experimental data and the simulation. However, the small amount of reverse conduction is not sufficient to clip the gate RF current waveform and generate the nonlinear behavior observed in the waveform in Figure 3.26b. The RF voltage and current waveforms at the drain terminal are shown in Figures 3.27a and 3.27b, respectively. Again, the waveforms for the low-drive and maximum PAE conditions are shown. The low-drive RF drain voltage waveform shown in Figure 3.27a indicates the onset of saturation, and slight deviation from sinusoidal behavior is observed. The large-signal RF waveform demonstrates significant clipping, both at low and high RF voltages, and the waveform becomes more “squared” in shape. The clipping at the low-drain voltages is caused by the total RF terminal voltage dropping
Wide band gap transistors – SiC and GaN – physics, design and models
5 Nonlinear Source Resistance (Ohm)
142
4.5 4
P in = 14.8 dB m P in = 0.0 dB m
3.5 3 2.5 2 1.5 1 0
50
100
150
200
250
300
350
400
450
500
Time (ps)
Figure 3.28 Source resistance versus time response for an AlGaN/GaN HFET amplifier (the two waveforms indicate operation at the onset of space–charge-limited transport conditions, and under maximum PAE).
below the RF knee of the I–V characteristic, and the clipping at high drain voltages is caused by the onset of RF breakdown in the conducting channel. The RF drain current waveforms are shown in Figure 3.27b. The large-signal RF current demonstrates the “squaring” behavior caused by the drain voltage waveform clipping mechanisms that occur at low and high voltage magnitudes. The RF voltage and current are essentially out-of-phase, with the current magnitude being high when the voltage magnitude is low, and vice versa. The waveform clipping generates harmonics, which are clearly observed in the large-signal RF current. The RF drain current shown in Figure 3.27b consists essentially of conduction current, which flows through the conducting channel from the source to the drain. When the threshold for space-charge limited flow is reached the resistance of the material will become a function of the magnitude of the current and the gate-source resistance will become nonlinear. The magnitudes of the source resistance under the low drive and large-signal conditions are shown in Figure 3.28. The onset of space-charge dependent resistance is observed for the Pin = 0 dBm input drive condition during the high-current portion of the RF cycle. The source resistance increases from a DC magnitude of Rs = 1.85 to a peak magnitude of about Rs = 2.4 . However, under large-signal conditions the source resistance becomes highly nonlinear and increases significantly during the high-current portion of the cycle. Since the RF drain current shown in Figure 3.27b is composed essentially of conduction current, the magnitude of the source resistance is directly dependent upon this current. The magnitude of the source resistance increases from the DC magnitude of Rs = 1.85 to almost Rs ∼ = 5 during the peak of the RF drain current. Increasing the drain voltage results in an increased magnitude of the nonlinear source resistance during the high-current portion of the RF cycle, as shown
3.7 Large-signal effects
143
Nonlinear Source Resistance (Ohm)
10 9 8 7
vds = 28 V vds = 38 V vds = 48 V
6 5 4 3 2 1 0
50
100
150
200
250
300
350
400
450
500
Time (ps)
Figure 3.29 Source resistance versus time response for an algan/gan HFET amplifier at maximum PAE conditions for Vds = 28 V, 38 V, and 48 V.
in Figure 3.29. In this figure the results obtained by increasing the drain voltage from Vds = 28 V, to Vds = 48 V are shown. For Vds = 48 V the source resistance increases by almost an order of magnitude during the high-current portion of the RF cycle compared to the small-signal value. The nonlinear behavior of the source resistance helps explain the behavior of the RF gate current shown in Figure 3.26b. Although the RF gate current is composed essentially of displacement current, the gate circuit requires conduction through the gate-source region, which is normally a low-value resistance, and the magnitude of the RF gate current is dependent upon the magnitude of the source resistance. The harmonic generation due to the clipping of the RF drain current is transferred to the gate circuit and the magnitude of the gate current is, therefore, affected by the magnitude of the source resistance. The input impedance to the transistor is essentially a series combination of the gate-source capacitance and the nonlinear source resistance. The nonlinear source resistance has a significant effect upon the operation of the device. The source resistance essentially couples the input gate circuit to the output drain circuit for the device, as shown in the equivalent circuit shown in Figure 3.18. The drain current generator is driven by the voltage generated across the gate-source capacitance, according to the expression, i out = gmi vgs e− jωτ
(3.29)
where i out is the HFET RF output current, gmi is the intrinsic transconductance (mS), τ (s) is a delay time, and vgs is the RF voltage across the gate–source capacitance. The transconductance that is developed at the device output is reduced by the source resistance, according to equation (3.26), as previously discussed.
144
Wide band gap transistors – SiC and GaN – physics, design and models
@ Surface of AlGaN Layer
E (V/cm)
E (V/cm)
@ Mid-Point of Conducting Channel
Microns
Microns
E = 2 × 106 V/cm
Figure 3.30 Electric field magnitude versus distance at the mid point of the conducting channel and at the surface of the AlGaN Layer for an AlGaN/GaN HFET (the top curve is the total E field and the bottom curve is the x-directed E field. The dotted lines indicate the critical E field for breakdown in GaN.) [79].
3.7.3
Gate leakage When a high drain bias voltage is applied and the HFET is driven with a large RF signal the peak voltage at the drain can obtain a magnitude essentially twice the magnitude of the bias voltage. Detailed simulations indicate that the magnitude of the electric field at the edge of the gate electrode on the drain side can easily exceed Ec∼6–8 MV/cm, as shown in Figure 3.30, which is sufficient to produce quantum mechanical electron tunneling. The curves in Figure 3.30 indicate the electric field at the mid-point of the conducting channel and at the surface of the AlGaN layer. Both the magnitudes of the total electric field and the x-directed (i.e., in the direction of current flow) electric field are shown. The dotted line indicates the assumed breakdown voltage, which is in the range of Ec∼2 MV/cm. As indicated, both the total and x-directed electric field for the stated operating conditions significantly exceed the breakdown voltage. The electric field at the gate edge near the surface has a magnitude on the order of E∼8 MV/cm, which is sufficient to produce significant electron tunneling. Experimental data indicates that electron tunneling, in fact, occurs. The electrons that tunnel from the gate electrode can (a) accumulate on the surface of the semiconductor next to the gate, (b) conduct along the surface by a trap-to-trap hopping mechanism, creating a gate-to-drain leakage current, or (c) possibly travel through the AlGaN layer to the 2DEG conducting channel, as shown in Figure 3.31. Measured data indicate that the surface leakage path is dominant under practical operating conditions,
3.7 Large-signal effects
145
Electrostatic feedback Surface Leakage (Primary mechanism) Gate
AIGaN
Electron Tunneling
Gate/Channel Leakage (Secondary mechanism)
Electrostatic depletion
2DEG GaN
Figure 3.31 Gate electron leakage paths in an AlGaN/GaN HFET [79].
and the path through the AlGaN layer only occurs for extreme conditions following defect creation that can occur under high electric fields, etc. In addition, if the energy of the electrons is sufficiently high, they can cause avalanche ionization on the surface next to the gate. When this occurs electrons tunnel from the gate metal to the semiconductor surface area adjacent to the gate with sufficient energy to cause avalanche ionization, which is accompanied by light emission from the gate edge. Light emission from the gate edge is often observed in the large-signal operation of GaAs MESFETs and InP-based HEMTs, and has been observed in AlGaN/GaN HFETs under certain operating conditions. This indicates that surface breakdown occurs in the nitride devices and can be a factor affecting reliability. Avalanche ionization also occurs in the conducting channel of these devices and is a factor in the RF operation of the device when operated under large-signal drive. RF channel breakdown is, in fact, a factor that affects gain saturation in the HFET devices. When the electrons accumulate on the surface of the semiconductor at the gate, a “virtual gate” effect is created, where the gate effectively increases in length as the electron tunneling proceeds and the density of electrons on the semiconductor surface increases. The electrons that accumulate on the surface of the semiconductor create an electrostatic charge that produces a partial depletion of the conducting channel electrons, thereby causing a reduction in the channel current, and a corresponding decrease in RF output power. The electron tunneling and charge accumulation continue as a function of time. This mechanism is the primary physical basis for the nondestructive reliability problem associated with these devices. Typical performance degradation is shown in Figure 3.32, which shows the measured DC channel current and RF output power as a function of time. The increasing electrostatic charge acts to suppress further tunneling of the electrons from the gate metal, thereby limiting the effect. In this manner, the mechanism is self-limiting. The measured DC conduction current degradation shown in Figure 3.32 correlates with a degradation in RF output power. The current conduction characteristics vary with time and with device design, surface processing, and passivation, and varying power degradation results are obtained. It is possible to modify and reduce the tunnel leakage by the use of optimized field-plate device designs, and by the use of passivation, which minimizes the RF power degradation. With proper and optimized passivation, DC current
146
Wide band gap transistors – SiC and GaN – physics, design and models
Change in Idss (%)
10
0
–10
–20 0
100
200
300
(a)
400 500 600 Stress Time (hr)
700
800
900
700
800
900
Change in Pout (dB)
1
0
–1
–2 0 (b)
100
200
300
400
500
600
Stress Time (hr)
Figure 3.32 (a) Measured change in channel current (Idss ) and (b) RF output power versus time for
an AlGaN/GaN HFET (various lines indicate different devices included in the measurement) [79].
and RF output power degradation can be minimal, at least for limited ranges of DC bias voltage.
3.7.4
Reliability and time-dependent performance degradation One of the dominant reliability problems experienced by nitride-based HFET devices has been linked to gate leakage [79, 80]. Although gate leakage is not the only problem affecting device reliability, it is a first-order problem that needs to be solved before these devices find widespread application. The problem is manifested as a time-dependent decrease in drain current and RF output power, as shown in Figure 3.32, and has been primarily addressed through surface passivation techniques. The degradation is observed to vary significantly with surface passivation processes and from manufacturer to manufacturer. Also, gate leakage is not the only mechanism that results in drain current and RF output power degradation but it was among the first to be addressed. The phenomenon is reversible and does not produce permanent damage
3.7 Large-signal effects
147
Gate tunnel leakage
Itun Irev
Id
Ig Gate
t – τt
Drain [C] Icon
Ichbd Rd
Ifor
Rs
RF channel breakdown
Source
Figure 3.33 Large-signal HFET model used in the performance simulations [79].
or degradation to the device, and a period of inactivity generally results in the device returning to its initial performance. However, this recovery has also been observed to be a false recovery as when stress is reapplied to the device, it quickly degrades to its last degraded state. Additionally, under certain operating conditions, a “sudden reliability” problem has been observed [81], where permanent degradation in device performance occurs. Devices that experience this problem are characterized by high-magnitude gate leakage. A model for gate tunnel leakage in GaAs MESFETs has been reported [82]. This model has been modified for use with AlGaN/GaN HFETs, and the modified model can be used in a harmonic-balance simulator to investigate the gate tunnel mechanism as a function of DC and RF operating conditions. The model is shown in Figure 3.33. The gate tunnel leakage is represented as a current generator between the gate and drain electrodes. The model also includes RF breakdown within the conducting channel, which is represented by a current generator between the drain and source. This model accurately simulates the DC and RF performance of AlGaN/GaN HFETs, and the simulated and measured RF performance for a class A-B 2.14 GHz communications band AlGaN/GaN HFET amplifier are shown in Figure 3.23, and the measured and simulated Ids and Igs as a function of input power were shown in Figures 3.24 and 3.25, respectively. As shown in Figure 3.25, the gate conducts a small, but finite and negative leakage current for the entire range of input power, until the gate junction is driven into forward conduction at an input RF power of about Pin = 17 dBm. The model is in excellent quantitative agreement with the measured data for the reverse leakage conduction characteristics of the gate, and in qualitative agreement for the forward conduction, but slightly underestimates the input power required to drive the gate into forward conduction. As electrons tunnel from the gate to the AlGaN surface they can accumulate next to the gate electrode. The space charge from the electrons provides an electrostatic feedback to the gate that works to suppress the tunnel leakage, as shown in Figure 3.31.
Wide band gap transistors – SiC and GaN – physics, design and models
Electrostatic feedback
ntun (t )
Surface charge Nd Surface conduction
NTA
AIGaN
Figure 3.34 Gate electron tunnel leakage and surface conduction model [79, 83].
6.40E-02
6.30E-02 NTA = 2 × 1011 cm–2 6.20E-02 Ids (A)
148
6.10E-02
6.00E-02
NTA = 5 × 1011 cm–2
5.90E-02 0
200
(a)
400
600
800
1000
Time (s)
Figure 3.35a Simulated DC channel current versus time for two values of the acceptor-like surface
trap (NTA) density [79, 83].
This introduces time dependence to the gate leakage, with a corresponding time dependence associated with the RF power degradation. This effect can be modeled by introduction of a surface conduction layer that permits a variable surface charge, as shown in Figure 3.34. The NTA term represents the acceptor-like surface trap density, and can be expressed as NTA = Nd − n tun (t),
(3.30)
where Nd is the surface conduction layer charge density, and ntun (t) is the time-dependent tunnel charge density. In this model, the electrons that tunnel and accumulate next to the gate effectively reduce the density of the surface conduction electrons in this region and permit a varying surface trap density next to the gate to be determined. The model shown in Figure 3.34 reproduces the drain and gate currents observed in measured data. Measured and simulated time-dependent DC drain and gate currents are shown in Figure 3.35a and 3.35b, respectively, for two values of the acceptor-like surface trap density. Note that as the electrons accumulate on the surface near the gate, the magnitude of the tunnel leakage current is affected and the gate and drain currents become time-dependent. As the NTA density varies, the degree of electrostatic feedback is affected, with corresponding effects upon the gate leakage current, and the drain current degradation.
3.7 Large-signal effects
–2.28E-05
149
NTA = 5 × 1011 cm–2
–2.32E-05 –2.36E-05 Ig (A)
–2.40E-05 –2.44E-05
NTA = 2 × 1011 cm–2
–2.48E-05 –2.52E-05 –2.56E-05 –2.60E-05 0 (b)
200
400
600
800
1000
Time (s)
Figure 3.35b Simulated DC gate current versus time for two values of the acceptor-like surface trap (NTA) density[79, 83].
The magnitude of the electric field at the gate edge is a function of the device design and the magnitude of the terminal voltages experienced by the device while in operation. A reduction in the electric field will reduce the gate leakage current. AlGaN/GaN HFETs produce a very high-magnitude electric field at the gate edge due to the high sheet carrier concentration in the 2DEG. Very low channel resistance results, and minimal potential drop occurs along the channel region from the drain to the gate until the gate depletion region is encountered. Essentially the entire drain potential is supported over the narrow depletion region and a very high-peak E field results. Techniques to reduce the magnitude of the electric field at the gate edge include the use of field-plates, n-doped GaN cap layers, controlled polarization-induced surface charges [81], and modifications of the 2DEG sheet-charge density. Two main current paths for gate leakage currents can be identified. The main path is established by electron tunnel leakage from the gate, with electrons flowing along or near the AlGaN surface to the drain contact. The electron conduction occurs by a trap-to-trap hopping mechanism, where both thermionic emission and tunneling are likely involved, as illustrated in Figure 3.36. Simulations indicate that it is likely that the exact conduction mechanism changes as the electric field increases due to high DC and RF terminal voltages. This performance degradation process is essentially reversible and nondestructive, and removal of the bias and drive signals, with a period of device inactivity, causes the device to return to its initial state. However, as previously indicated, reapplication of DC and RF voltages often result in the device returning to a degraded state, which indicates that some permanent damage has occurred. The second current path consists of electron tunneling from the gate, with electron flow through the AlGaN layer to the 2DEG conducting channel. This current path requires a higher electric field, and often produces permanent damage to the AlGaN semiconductor lattice, with increased gate leakage. The lattice damage is observed in TEM images.
Wide band gap transistors – SiC and GaN – physics, design and models
Electrons can accumulate creating ‘virtual gate’ Strained Energy Band Electron tunneling E parameters Nss, M *tun
Thermionic Emission Tunnel Emission
Vdg = 0 EF
ΔG
s Surface hopping parameters ΔG, s Vdg = V Gate Metal
AIGaN Surface
Figure 3.36 Detailed model for gate-tunnel leakage and surface trap-to-trap hopping conduction [79].
0.2 Vg s = 0 V
0.18 0.16 0.14 Ids (A/mm)
150
0.12 Solid Lines: Measured Data Points: Simulation Data
0.1 0.08 0.06
Vg s = –2.5 V
0.04 0.02
Vg s = –5 V
0 0 (a)
1
2
3
4
5 Vds (V)
6
7
8
9
10
Figure 3.37a Measured and simulated DC I–V characteristics for an AlGaN/GaN HFET using the gate-tunnel leakage and surface conduction model [79, 83].
Using the gate tunnel leakage and surface conduction model it is possible to simulate the drain and gate current characteristics with excellent accuracy in comparison to measured data [83, 84]. For example, the model shown in Figure 3.34 produces the drain and gate I–V characteristics shown in Figure 3.37. Figure 3.37a and Figure 3.37b show the measured and simulated drain current and gate current for a AlGaN/GaN HFET. The gate tunnel leakage and surface conduction model accurately predicts the gate leakage and surface conduction current and accurately simulates both the drain and gate current
3.7 Large-signal effects
151
0.00E+00 Vgs = –1 V –2.00E-05 Vgs = –3 V
Ig (A)
–4.00E-05 –6.00E-05
Vgs = –5 V –8.00E-05 –1.00E-04
Vg s= 7 V (measured) Vg s= 5 V (measured) Vg s= 3 V (measured) Vg s= 1 V (measured) Vg s= 7 V (simulated) Vg s= 5 V (simulated) Vg s= 3 V (simulated) Vg s= 1 V (simulated)
Vgs = –7 V
–1.20E-04 0.00E+00 2.00E+00 4.00E+00 6.00E+00 8.00E+00 1.00E+00 Vds (V)
(b)
Figure 3.37b Measured and simulated DC gate current characteristics for an AlGaN/GaN HFET using the gate-tunnel leakage and surface conduction model [79, 83].
48.5 48
Id (m/A)
47.5 47 46.5 46 45.5 45 44.5 0 (a)
100
200
300
400
500
Time (s)
Figure 3.38a Measured and simulated DC drain current versus time for an AlGaN/GaN HFET including the effects of gate tunnel leakage and surface conduction (points are measured data and the line is simulated data) [79, 83].
characteristics. The model can be extended to time-dependent conditions, as shown in Figure 3.38 [83, 84]. Figures 3.38a and Figure 3.38b show the measured and simulated time-dependent DC gate and drain currents, respectively. The simulations are performed with a model that includes the effects of electrostatic feedback from the electrons that tunnel to the surface of the AlGaN layer adjacent to the gate electrode. The simulation results are compared to experimental data and excellent agreement between the measured and simulated data is obtained. The electrostatic feedback reduces the electric field at the edge of the gate electrode, thereby reducing the electron tunnel leakage. As electrons accumulate at the gate edge as a function of stress time, the feedback produces reduced gate leakage current. Also, the increased electron
152
Wide band gap transistors – SiC and GaN – physics, design and models
0 –0.001
Ig (m/A)
–0.002 –0.003 –0.004 –0.005 –0.006 –0.007 0 (b)
100
200
300
400
500
Time (s)
Figure 3.38b Measured and simulated DC gate current versus time for an AlGaN/GaN HFET including the effects of gate tunnel leakage and surface conduction (points are measured data and the line is simulated data) [79, 83].
density on the AlGaN surface partially depletes the 2DEG electrons, and a reduction in gate current occurs.
3.8
Summary Wide bandgap semiconductors, that is SiC and nitride-based heterostructures, can be used to fabricate high-frequency transistors with RF power performance superior to those fabricated from GaAs or Si. The most promising RF devices are FETs fabricated from 4H-SiC and HFETs fabricated from the AlGaN/GaN heterostructure. Optimized 4H-SiC FETs can produce RF output power on the order of 4–5 W/mm, which is a factor of four greater than obtainable from GaAs devices. Amplifiers fabricated from 4H-SiC MESFETs will be useful, particularly for RF applications in S and C-band communications, and potentially for X-Band radars. The AlGaN/GaN HFET can produce RF power density on the order of 10–12 W/mm, with very good PAE. Prototype nitride-based HFETs have produced a spot RF output power density as high as 30 W/mm, although this required drain bias of Vds = 120 V. The high mobility and sheet-charge density of the AlGaN/GaN heterostructure permit the fabrication of HFETs with excellent high-frequency performance, and devices that can operate up to and potentially exceed 100 GHz have been demonstrated. For both 4H-SiC and AlGaN/GaN HFETs poweradded efficiencies approach the ideal for operation up to X-band in both Class A and B operation. For X-band and below the SiC and AlGaN/GaN transistors are competitive with each other, and both produce RF output power superior to GaAs-based and InP-based transistors, while providing equivalent gain and PAE. Above X-band the AlGaN/GaN HFETs will dominate. However, improved thermal design is required to obtain the theoretically predicted performance, particularly for AlGaN/GaN HFETs, which are generally fabricated from material grown on SiC substrates. Both 4H-SiC and AlGaN/GaN devices are likely to find application in power amplifiers for base
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15. C-F. Huang, I. Perez, F. Zhao, J. Torvik, R. Irwin, K. Torvik, F. Abrhaley, and B. Van Zeghbroeck, “215 W pulsed class A UHF power amplification based on SiC bipolar technology,” Device Res. Conf. Dig., pp. 2–3, June 21–23, 2004. 16. C. D. Brandt, R. C. Clarke, R. R. Siergiej, J. B. Casady, S. Sriram, and A. K. Agarwal, “SiC for applications in high-power electronics,” Chapter 5 in Y. S. Park, Ed., Sic Materials and Devices, Semiconductors and Semimetals, vol. 52, Academic Press, 1998. 17. R. R. Siergiej, R. C. Clarke, A. K. Agarwal, C. D. Brandt, A. A. Burke, A. Morse, and P. A. Orphanos, “High power 4H-SiC static induction transistors,” IEDM Dig., pp. 353–356, Washington DC, Dec. 1995. 18. R. C. Clarke, A. K. Agarwal, R. R. Siergiej, C. D. Brandt, and A. W. Morse, “The mixed mode 4H-SiC SIT as an S-band microwave power transistor,” Device Research Conf. Dig., pp. 62–63, Santa Barbara, CA, June 1996. 19. A. W. Morse, P. M. Esker, R. C. Clarke, C. D. Brandt, R. R. Siergiej, and A. K. Agarwal, “Application of high power silicon carbide transistors at radar frequencies,” 1996 IEEE MTT-S Dig., pp. 677–680, San Francisco, CA. 20. R. C. Clarke, A. W. Morse, P. Esker, and W. R. Curtice, “A 16W, 40% efficient, continuous wave 4H SiC L-Band SIT,” Int. Microw. Symp. Dig., pp. 141–143, 2000. 21. G. C. De Salvo, P. M. Esker, T. A. Flint, J. A. Ostop, E. J. Stewart, T. J. Knight, K. J. Petrosky, S. D. Van Campen, R. C. Clarke, and G. M. Bates, “Ion implanted SiC static induction transistor with 107 W output power and 59% power-added efficiency under CW operation at 750 MHz,” Int. J. High Speed Electronics and Syst., vol. 14, no. 3 pp. 906–908, 2004. 22. R. J. Trew, “SiC microwave devices,” Chapter 6 in SiC Materials and Devices, pp. 272–279, Y. S. Park, Ed., Semiconductors and Semimetals, vol. 52, Academic Press, 1998. 23. S. Sriram, R. Barron, A. W, Morse, T. J. Smith, G. Augustine, A.A. Burk Jr, R. C. Clarke, R. C. Glass, H. M. Hobgood, P. A. Orphanos, R. R. Siergiej, C. D. Brandt, M. C. Driver, and R. H. Hopkins, “High efficiency operation of 6H-SiC MESFET’s at 6 GHz,” Device Research Conf. Dig., pp. 104–105, 1995. 24. C. Weitzel, J. W. Palmour, C. H. Carter, and K. J. Nordquist, “4H-SiC MESFET with 2.8 W/mm power density at 1.8 GHz,” IEEE Electron Dev. Lett., vol. 15, pp. 406–407, Oct. 1994. 25. K. E. Moore, C. E. Weitzel, K. J. Nordquist, L. L. Pond, J. W. Palmour, S. Allen, and C. H. Carter, “4h-sic mesfet with 65.7% power-added efficiency at 850 MHz,” IEEE Electron Dev. Lett., vol. 18, pp. 69–70, Feb. 1997. 26. S. Sriram, G. Augustine, A. A. Burk, R. C. Glass, H. M. Hobgood, P. A. Orphanos, L. B. Rowland, T. J. Smith, C. Brandt, M. C. Driver, and R. H. Hopkins, “4H-SiC MESFET’s with 42 GHz fmax,” IEEE Electron Dev. Lett., vol. 17, pp. 369–371, July 1996. 27. A. W. Morse, P. M. Esker, S. Sriram, J. J. Hawkins, L. S. Chen, J. A. Ostop, T. J. Smith, C. D. Davis, R. R. Barron, R. C. Clarke, R. R. Siergiej, and C. D. Brandt, “Recent application of silicon carbide to high power microwave,” IEEE Int. Microw. Symp. Dig., pp. 53–56, 1997. 28. R. A. Sadler, S. T. Allen, T. S. Alcorn, W. L. Pribble, J. Sumakeris, and J. W. Palmour, “SiC MESFET with output power of 50 Watts CW at S-Band,” Device Research Conf. Dig., pp. 92–93, 1998. 29. R. A. Sadler, S. T. Allen, W. L. Pribble, T. S Alcorn, J. J. Sumakeris, and J. W. Palmour, “SiC MESFET hybrid amplifier with 30 W output power at 10 GHz,” IEEE Int. Microw. Symp. Dig., pp. 173–177, 2000 30. B. Luo, P. Chen. A. Higgins, H. Finlay, K. Boutros, B. Pierce, A.Jones, D. Griffey, and J. Kolosick, “56 W SiC MESFET transistors with >50% PAE for L-band applications,” Proceedings of the 17th International Symosium on Power Semiconductor Devices & IC’s, Santa Barbara, CA, May 23–26, 2005, pp. 1–3.
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4
Amplifier classes, A to S1 Steve Cripps Cardiff University
4.1
Introduction The alphabetical classification of electronic amplifiers appears to date back to the earliest era of electronics, and as such could well be approaching the centenary mark. Its survival to the present day represents a remarkable continuity, given the vast changes in technology that have taken place in the intervening decades. It can also represent a distraction for the modern RFPA designer working with solid state active devices and GHz frequencies, both of which were well below the horizon when the original classification came into general use. The plan in this chapter is to introduce and define the various Classes,1 and then consider how the original intent is often modified in typical modern applications, sometimes to the point where the original concept migrates into something palpably different. Although the definitions of Class A, AB, B, and C are well established and have a long historical precedent, the subsequent Classes (D, E, F, etc.) are of much more recent origin and in some cases have suffered from different interpretations by different authors. A curious but endemic feature of this subject is the assertive use of classifications by authors and designers when the final amplifier current and voltage waveforms have not been (and in many cases cannot easily be) measured directly. This has been known to lead to considerable controversy, given that some amplifier “Classes” have even been patented. Another issue which comes up when addressing this subject with a modern perspective is the intrusion of digital approaches to power amplification, primarily in the form of so-called “switch modes.” As active device technology improves, the frequency range at which it can be made to behave as a near-ideal switch increases. Until recently, this range could be reasonably restricted to the “HF” (MHz to tens of MHz) region, but newer technologies such as gallium arsenide and gallium nitride have extended this region into the “VHF” (hundreds of MHz), and more arguably into the “microwave” (GHz) region. There is thus something of a “gray” area, where a particular amplifier can be considered as a “smoothed-out” switch mode, or alternatively as a more conventional analogue PA class with some extra harmonic components. Both of these approaches will be described in the later sections on Class S, E, and J amplifier.
1
The word “Class” has such specific and specialised importance in this chapter that I will capitalize it throughout.
160
Amplifier classes, A to S
Efficiency is the central issue in the evolution of amplifier classes. The Class A amplifier can be considered to be a logical starting point, and will be described first. It has several positive attributes, notably simplicity of implementation, linearity, and high potential operating bandwidth. It does however have only moderate efficiency, even at maximum signal drive conditions, and this is what led early amplifier developers to explore Class AB modes, where the device is deliberately shut off for a portion of each RF signal cycle. This can have a dramatic effect in terms of increased efficiency, but almost always comes at a price of reduced overall linearity. As we progress through the alphabet in the PA idiom, this tradeoff between efficiency and linearity in general continues. A highly efficient Class C amplifier, for example, cannot be considered at all in applications having any form of amplitude modulation on the signal carrier. Since the start of the digital communications era, there has been a marked emphasis on linear RF power amplification, that is to say the system RFPA is required to amplify the signal in its final, fully modulated form. This represented something of a seachange for the RFPA industry, since in older systems it was more common to use the RFPA itself as a high-level modulator. Vacuum tubes appear to have been very amenable to the use of supply voltage variation as a means of imposing amplitude modulation (AM) on to the carrier. As silicon RF power transistors began to appear in the early 1960s, it seems that a major re-think took place, since these devices displayed highly nonlinear behavior under conditions of supply modulation. Conveniently (and, presumably, not serendipitously) there was a shift to “angle modulation” (frequency and phase modulation), especially in mobile transmitters, whereby the transmitter RFPA could be run at constant amplitude level. This allowed the ongoing use of efficient Class C-type amplifier designs and was something of a disincentive for device technology development towards more linear performance. But the more recent development of systems using complex, digitally based, modulation schemes has forced RFPA design, and the underlying device technology, to comply with stringent linearity specifications. There is nevertheless a counter-culture evident in the modern RFPA community, which seeks to reinstate the old regime. In principle, a digitally modulated signal can still be sent using only nonlinear RF amplification. The basic concept is to generate a constant envelope signal which carries the appropriate phase modulation, and then use supply modulation (and/or alternatives) to generate the required AM. The nonlinear relationship between the supply voltage and the output RF envelope amplitude can be managed in a modern system through the use of digital correction techniques, either on the tracking voltage itself, the signal envelope, or both. Such “LINC” (linear amplification using non-linear components) RFPA systems can in principle be much more efficient than the linear approach, although the efficiency at which the tracking voltage supply can be generated is a negative factor which must always be taken into account. LINC system design has thus renewed interest in the design of highly efficient amplifiers without the constraint of linearity. The classical solution of Class C mode is less attractive in solid state design, and this is the area in which switching, or quasiswitching RFPAs such as Classes D and E may well have a major role to play in future systems.
4.2 Active device models
161
Despite these possible future directions, the vast majority of RFPAs in current use have been designed for Class A (Section 4.3) or Class AB (Section 4.4) operation. Class A tends to predominate at higher GHz frequencies where applications usually demand highly linear performance, and RF bandwidths can be 10% or greater. Wireless communications systems, which typically use much narrower bandwidths, usually favour Class AB operation in order to maximize efficiency. Linearity requirements are, however, rapidly approaching those encountered in satellite communications and microwave link applications, and digital signal processing usually has to be employed in order to meet linearity specifications in Class AB operation. We note Class B (Section 4.4) somewhat in passing, as a singular point that divides Class AB from Class C (Section 4.5). Class F (Section 4.6) is something of the joker in the pack, in at least one sense, but has been the subject of much research over the last decade or so. It can be considered as a derivative of Class AB operation, and has been used in both linear and LINC applications. In a linear application, it can in principle increase the efficiency at peak power levels, without compromising linearity, but in practice poses some difficult circuit design issues, especially for higher power devices at GHz frequencies. In LINC applications it can challenge the efficiency of the more fashionable switch modes, and in specific cases may supply a higher output power due to better control of peak voltage. Other PA classes come and go according to the whims of researchers and patent attorneys, so as we proceed beyond Class F then definitions become a little harder to find, let alone to summarize. There are also some discrepancies between audio and RF electronics in the definition of some amplifier classes. The most notable of these is the Class D audio amplifier which is basically a pulse width modulator and is usually denoted as Class “S” at RF and Microwave frequencies (hence there is no section in this chapter on Class D). Also, in the audio world Class G and Class H are well defined but these terms have not come into general use at RF. Ironically, the audio definitions essentially utilize a technique known as “envelope tracking,” or ET, which is used at RF but has never been classified alphabetically. Section 4.11 attempts to summarize some of the “miscellaneous” categories.
4.2
Active device models In defining and analyzing RFPA Classes it is logical to adopt a common device model. At the outset, however, it has to be noted that RFPA devices fall into two distinct physical kingdoms, the bipolar transistor and the FET. Within these two kingdoms lie numerous genera; for example the most widely used bipolar device at GHz frequencies is the Heterojunction Bipolar Transistor, or HBT, but at higher power levels and lower (UHF) frequencies, the more traditional Si bipolar junction transistor (BJT) still survives. FET devices come in a somewhat greater diversity, both in terms of materials and structures. Gallium arsenide metal semiconductor FETs (GaAs FETs) dominated the GHz sector for several decades, somewhere between the late 1960s and the 1990s. More advanced material growing machinery such as molecular beam epitaxy (MBE) became commercially available in the early 1990s and led to the development of more
162
Amplifier classes, A to S
D
Imax
Ids
Vgs (linear steps)
G Ids Vgs
S
0 Vknee ( K. This is equivalent to setting all the embedding impedances in the circuit to zero at those frequencies. Since the frequency spectrum is strictly bandlimited, the v(t) waveform used to calculate the current in the nonlinear subcircuit is very “clean”; that is, unaffected by aliasing or other Fourier-transform errors. The current, i(t), is then obtained from the nonlinear function, i(t) = fNL (v(t)). The fourier transform
5.6 Practical aspects of nonlinear circuit simulation
225
of this quantity is not strictly bandlimited to Kωp . If the waveform is oversampled (i.e., the sampling interval is much less than the Nyquist limit), the harmonics of interest are not affected significantly by those higher harmonics, so the harmonics k > K are discarded without incurring error. If the sampling interval is minimal, however, the lower harmonics can incur aliasing errors, a form of numerical noise that changes from iteration to iteration, making convergence difficult or impossible.
Termination criteria Earlier we made the point that harmonic-balance analysis is a process of iteratively improving an estimate of the solution. At some point, that solution is “good enough” and the process must terminate. How do we decide what is “good enough”? A number of possibilities are immediately evident. The first is simply to require that the magnitude of the current-error vector be less than some threshold: |ILIN (V) + INL (V)| < ε
(5.53)
Another is that the individual current errors at each harmonic be below some threshold; that is, |ILIN (kω0 ) + INL (kω0 )| < ε
(5.54)
for all harmonics at all nonlinear elements. Finally, we could require that the fractional error in each harmonic be below some threshold: |ILIN (kω0 ) + INL (kω0 )| 1 octave). Gain linearity/AM-AM distortion (units: + / −dB versus a specified power domain dynamic range): the ability of an amplifier to hold its gain constant throughout the application of an RF input signal with varying power levels. What is ideal: the RFPAs nominal gain value (gain = G dB + / −0 dB) remains perfectly constant from an output power of 0 W to the maximum power demanded by the application. What is typical: gain variations of + / −1 dB are readily achieved by Class A and AB amplifiers, over a dynamic range of 40–60 dB. Gain linearity is class dependent with Class A being the most linear and least efficient, while Class D/E are the most nonlinear but most efficient. Gain temperature stability (units: + / −dB): the ability of an RFPA to hold its gain constant over varying levels of ambient temperature. What is ideal: absolutely no ( + / −0 dB) of gain variation regardless of ambient temperature variations. What is typical: gain variations of 6 dB over temperature swings of −10 to +80 ◦ C are common. The variations are easily corrected for with ALC control loops or open loop gain stabilization networks. Gain stability of + / −0.25 dB over 40–50 ◦ C is achievable with open loop temperature compensation networks. ALC loops can improve these values further. Phase linearity/AM–PM distortion (units: + / − ◦ versus a specified power domain dynamic range): insertion phase linearity or AM to PM distortion, is the ability for an RFPA to hold its insertion phase constant over varying output power levels. What is ideal: an insertion phase variation of Θ + / −0 ◦ from zero power output to full rated power. What is typical: an insertion phase variation of + / −10 to + / −15 ◦ around a nominal insertion phase value (Θ) over a 40–60 dB dynamic range is easily achieved via Class A amplifiers. Predistorted and feed-forward amplifiers can have much less phase variation. Dynamic range (units: dB): the range of output power levels that an RFPA must work over. Usually the maximum power output is the upper limit. What is ideal: the RFPA’s output would be linearly controllable with no non linear deviations from exactly 0 W
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Practical HF/VHF/UHF RF power amplifier realization
r
r
r
r
r
r
to the required maximum rated power. What is typical: the linear classes of RFPAs; A, AB, and B offer the best dynamic range (approx 40–60 dB), Class C, D, and E have limited dynamic ranges (50–70% and relatively constant over a limited dynamic range; however, linearity (both gain and phase) will suffer. Broadband Class AB efficiency runs in the 40% range, but drops substantially at reduced power output levels. Rise time (rising transition duration) (units: s): the amount of time it takes an RFPA to progress from 10 to 90% (in voltage) of any given rectangular RF pulse output. What is ideal: the amplifier’s output power rising transition duration is exactly equal in time to the RF input signal’s rising transition duration, regardless of how fast or slow. What is typical: rise times of 250–750 ns are readily accomplished. Fall time (falling transition duration) (units: s): the amount of time it takes an RFPA to progress from 90% to 10% of any given RF pulse output. What is ideal: the amplifier’s output power falling transition duration is exactly equal in time to the RF input signal’s falling transition duration, regardless of how fast or slow. What is typical: fall times of 50–500 nS are readily accomplished. Pulse overshoot (units: %): the amount an RFPA’s output deviates from an expected 100% output power value during the period directly following the rise time transition duration. What is ideal: 0% overshoot, the amplifier’s output exactly follows the input. What is typical: 10–15% overshoot is common though controlling overshoot becomes more problematic with faster rising transition duration times along with lower operating frequency range into the 1–30 MHz range. Pulse droop (pulse tilt) (units: %): the amount an RFPAs output either decreases (negative tilt) or increases (positive tilt) across the duration of a rectangular RF output pulse. What is ideal: 0%, an RFPA with a perfectly flat rectangular RF input pulse delivers an amplified exact replica on the output. Note: pulse tilt can be an extremely elusive pulse parameter to define let alone design for or even measure. The most problematic issue with pulse tilt is the pinpoint assignment of the 100% power amplitude discrete location on the rectangular RF pulse envelope which will serve as the reference point. Pulse waveforms can manifest themselves in an infinite amount of subtly different shapes, even if they are all classified as “rectangular” pulses. What is typical: a pulse tilt value of 10% is common. Less than 5% becomes very difficult to manage over broad frequency and dynamic ranges. Ringing/settling time: (units: seconds): The duration of time that an RFPAs output overshoots and exponentially decays sinusoidaly down to a 100% pulse power output. What is ideal: absolutely no ringing or overshoot which might initiate ringing. What is typical: depending on the frequency range and rising transition duration time, ringing can occur and last for 20–500 nanoseconds or perhaps longer.
6.3 The realization process
239
r Distortion, harmonic (units : -dBc): the level of unwanted signal components which are integer multiples of the RF input signal frequency that are measured relative to the magnitude of the RF output signal. What is ideal: absolutely no harmonics, the only output of the amplifier is a replica of the input RF spectrum, with all frequency components amplified exactly the same. What is typical: even-order harmonics are less than −20 dBc at the second-order harmonic and decreasing further at higher even-order frequencies, Odd-order harmonics are less than −12 dBc at the third-order harmonic and decreasing further at higher odd-order frequencies. r Distortion, inter-modulation (units: dBc): the level of unwanted signal components that arise from the application of two or more RF input signals propagating through a nonlinear medium. The distortion signals are close in frequency to the original input signals. What is ideal: there are no IMD components, the output frequency spectrum is an exact, amplified replica of the input spectrum. What is typical: IMD distortion components will typically fall −20 to −30 dBc down from the two-tone output signals. r Noise floor (units: dB relative to thermal noise floor): the amount of noise an amplifier puts out when its input is terminated with a 50 resistor. RF power amplifiers typically are not concerned with noise as their primary task is to provide large amounts of electrical energy. In other words, the amplifier, per se, can be a substantial noise source. There are, however, situations where an RFPA may be required to emit as little transmitted noise as possible at frequencies other than the carrier. What is ideal: the amplifiers noise output is zero dB over the noise power of a 50 Ω resistor. What is typical: a noise output level of 10–15 dB above the thermal noise of a 50 Ω resistor. r VSWR, input (units: dimensionless): a measure of the RFPAs ability to keep its input impedance close to a specific value (i.e., 50 ) over a given frequency range so as to achieve a maximum transfer of power from a signal source to the amplifier input. What is ideal: a 1:1 VSWR is a perfect match, all the signal sources power will enter into the input port of the RFPA for all frequencies. What is typical: a 2:1 VSWR (or less) over a broad frequency range is commonly acceptable. Usually the input of an RFPA requires a small amount of signal power (on the order of 0 dBm), so a 2:1 VSWR corresponds to approximately 90% of the signal source power entering into the RFPA’s input port. r VSWR, load (units: dimensionless): a measure of the RFPA’s output impedance relative to a given load. An RFPA’s output impedance is a dynamic parameter depending on a variety of variables; power output, supply voltage and frequency. It is a desirable to match the RF transistor to its load impedance for maximum power transfer. Unfortunately, for many applications, the load will vary widely and present a serious challenge to the RFPA Engineer to design an RFPA that can withstand adverse load VSWRs and maintain specified performance. What is ideal: a perfect match, 1:1 VSWR for all frequencies and power levels. What is typical: this depends heavily on the end use application, but can vary anywhere from a close match 1.2:1 to an open or shorted load (∞:1). r Stability, spurious output, load pull dependent (units: -dBc): this defines an amplifiers ability to maintain stable operation (i.e., not generate any unwanted spurious signals and maintain an output power that remains controlled by the input power
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Practical HF/VHF/UHF RF power amplifier realization
and a stable transfer function) while the input/output load VSWR is varied. This is sometimes defined as load pull stability. A word of caution here to those who specify or have been requested to design an amplifier as “unconditionally stable,” implying the amplifier will not oscillate terminated by any input/output load VSWR. While there does exist ways to theoretically show an amplifier is unconditionally stable into adverse loads, it is strongly argued here that no such thing as a truly “unconditionally stable amplifier” has or ever will exist in the real world. The basis for this argument is that any physical amplifier whether broadband or narrowband, can be subjected to virtually infinite number of operating points, assembly process control variations, device lot/date code variations and changing environments, be it frequency, output power levels, operating temperatures, modulation formats, input/output port isolation values and combinations of complex input/output load terminations. To be certain, there will be one combination of the listed operating points that will cause an oscillation or some level of spurious output. Since an infinite amount of operating points exist, it would require an infinite amount of time to test and verify a given amplifier is “unconditionally stable,” unfortunately (or perhaps fortunately, at least for the poor soul tasked with testing an RFPA for unconditional stability) no one can live long enough to test and confirm this. What is ideal: unconditional stability, no oscillations for any condition of operation. What is typical: conditional stability, the amplifier will be stable under a defined, discrete set of conditions such as Load VSWR up to a given point (i.e., 3:1, fully rotational about the Smith Chart), dynamic range, fixed frequency ranges, or at an output for spurious frequencies that are an acceptable amount below the carrier. Typical values of load pull spurious are −40 to −60 dBc. r Operating temperature range (units: degrees): the temperature range over which the amplifier will be expected to meet all specifications. Every component in an RFPA will have electrical characteristics that are temperature dependent. This dependency can cause an RFPA to be specification compliant at one temperature and out of specification at another. The key is to design the RFPA so that the effects of varying temperature are minimized. What is ideal: the RFPA will operate uniformly at all temperatures with no variation in gain, output power, distortion, etc. What is typical: the RFPA will operate over a limited temperature range (−50 to +125 ◦ C, for example) where the high end of the temperature range is determined by the RF power transistor’s junction temperature and required failure rate. r Altitude (units: feet, meters above mean sea level (AMSL)): the altitudes within which the amplifier is expected to meet full specification. Altitude can impact an RFPA’s performance primarily with ones that use forced air cooling as air becomes thinner are higher altitudes, rendering the efficacy of this cooling method problematical. What is ideal: an RFPA is operational from Submarine to Outer Space with no variation in performance. What is typical: the RFPA is limited to certain altitudes by the method by which heat is removed, for low altitudes forced air cooling is adequate, for high altitudes and space, liquid cooling becomes more effective. r Shock/vibration (units: G, rms): the level of six axes (x, y, z and rotational: yaw, pitch, and roll) mechanical energy an RFPA can withstand and still be specification compliant. What is ideal: the RFPA can withstand exposure to shock and vibration
6.3 The realization process
241
resulting from transportation (shipping) and application (military applications: airborne, ground transport, colocated ordinance etc.) and remain functional regardless of what level of mechanical shock is imparted. What is typical: an RFPA will have set limits of how much shock the unit can endure, amplifiers have been designed to withstand as much as 5000 G of transient shock and as much as 60 G of continuous, random, six axis vibration. r Conducted/radiated emissions: the level of unwanted RF noise whether signal, spurious, distortion or other that gets out of the RFPA either on physical wires (conducted emissions) or through an improperly shielded enclosure (radiated emissions). What is ideal: the RFPA will contain all radio frequency energy within the confines of the physical housing of the amplifier system. The RF energy will only exit the chassis through coaxial cables and connectors. What is typical: all RF power amplifiers will emit and conduct some level of RF energy unintentionally to other collocated circuits, subsystems, and equipment, shielding measures must be deployed such that the emissions are within acceptable limits based on the particular application EMC guidelines. r Conducted/radiated susceptibility: the ability of an RFPA to maintain its specified performance with unwanted signal/spurious/noise energy from other collocated circuits, subsystems and equipment getting into its on physical wires (conducted susceptibility) or through improperly shielded RFPA enclosures (radiated susceptibility). What is ideal: an RFPA can operate normally regardless of being subjected to any level of electromagnetic (EM) interference or impulse. What is typical: All RF power amplifiers will be affected at some level of RF energy unintentionally coupled into it from collocated circuits, subsystems and equipment. Shielding measures must be deployed such that the susceptibility thresholds are within acceptable limits based on the particular application EMC guidelines. r Mean time to failure (units: hours): the average amount of time an amplifier will function before experiencing a malfunction or failure. What is ideal: a particular amplifier will be operated within its specified ranges and perform flawlessly indefinitely. What is typical: it depends heavily on the temperature of the RFPA’s semiconductor or “die” temperatures, MTTFs of 20,000 to 100,000 h are common.
6.3.3
Specification/hardware realization Regardless of the application, a specification defining an RFPA will draw from some or all the above listed Operating Specifications. How these parameters are specified closely influence how a particular RFPA design is realized. There are multitudes of applications for RFPAs, it is nearly impossible to illustrate one particular method to realize an RFPA design for each. However, it is possible to cover techniques that can address Specifications that are common to several applications. The steps exhibited and taken will progress from specification delineation and quantification to block/wire design, then to RFPA module design.
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Practical HF/VHF/UHF RF power amplifier realization
Figure 6.1 Simplified system level block and wiring diagram for a typical RFPA system.
RFPA system design can be best accomplished by working “backwards” if you will. That is, an RFPA system design begins by starting with the maximum RF power requirement of a particular application, and designing the RFPA output section first, as opposed to last. We begin with output section first for the following reasons: 1. The application (or end use) demand for RF power is the first and foremost requirement for an RFPA to meet and the output section addresses this directly. 2. How the output module design of the RFPA evolves, and what its transfer/distortion characteristics are, will dictate the design of the stages that will precede it (low-level driver and intermediate power amplifier stages). 3. Depending on what RF power transistors are chosen for the RFPA section and how they perform from a DC standpoint (i.e., DC operating voltages and DC current demands) will also determine what type of DC power supplies are required.
6.4
RFPA system level design overview The step following specification delineation and quantification for a RFPA system design is the System Block and Wire diagram. A simplified System Block and Wire diagram is shown in Figure 6.1 for a 1 kW amplifier example. The architecture in this diagram can be used to realize any RFPA system application requirement. It shows the basic elements or subsystems: r low-level driver stage; r intermediate power amplifier stage; r RF power divider;
6.4 RFPA system level design overview
r r r r r
243
RF power amplifier section (usually consisting of multiple, identical RFPAs); RF power combiner; directional coupler; DC supply section; digital control section.
The top of the system level block and wire diagram shows the output power requirement of each stage and above each subsystem block diagram are typical gain/loss values relative to each stage. Working the power requirement from right to left, it is apparent how the application power requirement demands a focus on the output RFPA section first. Based on the application power requirement, we need to select aN RF power transistor that can provide adequate RF power, and most importantly, provide the necessary power while concurrently satisfying the application requirements for linearity, efficiency, distortion, transition duration response times and anticipated load VSWR excursions. Another reason for working on the RFPA output first is the initial verification of meeting specifications on a modular, scaled down level. If, for example, distortion levels cannot be met on a modular level, either the designer has to improve the RFPA module design or plan for ways to provide system level error correction. There are a variety of processes occurring in any RFPA system; however, if you were to break them down and classify them, there are primarily two: r power amplification; r power transfer. Power amplification, obviously, is accomplished with the RF power transistors; power transfer is accomplished with matching networks, dividers and combiners. Therefore, it is readily apparent that RF device selection and impedance matching will be critical steps.
6.4.1
RF power amplifier module design overview After the block/wiring top level system design, the output RFPA section itself can be broken down further into a generic lower level block diagram as show in Figure 6.2. RF power modules have the some or all of the following basic sections: r r r r r r
RF power transistor; device bias/temperature compensation network; input/output RF and DC coupling/decoupling networks; input/output matching networks; feedback networks; heat removal.
This leads to the first major task in RF power amplifier stage realization: selection of an RF power transistor. This is perhaps the single most important decision the RF power amplifier design engineer makes, there are other decisions, for sure, but this is the most critical. This is also not a decision that is made by merely comparing RF transistor data
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Practical HF/VHF/UHF RF power amplifier realization
Figure 6.2 Block diagram of the component level view of an RFPA module.
sheets of different RF transistor manufacturers; it is a decision that is made after data sheet review, CAD simulation, prototyping, rigorous testing of individual PA stages and then comparison of actual, application specific results. Careful review of RF transistor data sheets is a very important, albeit initial step. Figure 6.3 is part of a typical RF power transistor data sheet. Although the data sheet contains a large amount of data, determining whether or not a particular device is suitable for a given application may not be readily apparent when reviewing it. The reason is that RF power transistor manufacturers simply cannot fully anticipate all the applications for which a particular device may be deployed, they will make generic recommendations for applications, but it is up to the RF power amplifier design engineer to make the final judgment call, and only after several devices have been tested and evaluated. In spite of its vague nature, the RF transistor data sheet is at least a starting point. The following is a brief overview of its major sections: 1. Applications: manufacturers recommendation of potential applications for the device; i.e.; medical, broadband, VHF communications, etc. 2. Absolute maximum ratings: maximum values for power dissipation, junction temperature, supply/breakdown voltages and device currents. 3. Electrical characteristics: quantification of key parameters: r power output: how much power the device can reliably deliver when matched into a 50 load. r frequency range: what frequencies the device can be used over. r gain: typical power gain level, usually at the maximum operating frequency. r efficiency: how efficiently the device can convert DC power into RF power. r thermal resistance: a measure of the devices ability to remove the heat of its semiconductor dies to an outside surface.
245
6.4 RFPA system level design overview
TetraFET
D1020UK METAL GATE RF SILICON FET MECHANICAL DATA
B
C (2 pls)
2
G (typ)
3
1 H
P (2 pls) A
D
4
5
E (4 pls)
GOLD METALLIZED MULTI-PURPOSE SILICON DMOS RF FET 150 W – 28 V – 400 MHz PUSH–PULL
F I
FEATURES • EXTRA LOW Crss
N
O
M
J
K
• SIMPLIFIED AMPLIFIER DESIGN
DR PIN 1 PIN 3 PIN 5
SOURCE (COMMON) DRAIN 2 GATE 1 DIM A B C D E F G H I J K M N O P
Millimeters 19.05 10.77 45° 9.78 5.71 27.94 1.52R 10.16 22.22 0.13 2.72 1.70 5.08 34.03 1.61R
PIN 2 PIN 4
DRAIN 1 GATE 2
• SUITABLE FOR BROADBAND APPLICATIONS • SIMPLE BIAS CIRCUITS
Tol. 0.50 0.13 5° 0.13 0.13 0.13 0.13 0.13 MAX 0.02 0.13 0.13 0.50 0.13 0.08
Inches 0.75 0.424 45° 0.385 0.225 1.100 0.060R 0.400 0.875 0.005 0.107 0.067 0.200 1.340 0.064R
Tol. 0.020 0.005 5° 0.005 0.005 0.005 0.005 0.005 MAX 0.001 0.005 0.005 0.020 0.005 0.003
• LOW NOISE • HIGH GAIN – 10 dB MINIMUM
APPLICATIONS • HF/VHF/UHF COMMUNICATIONS from 1 MHz to 500 MHz
ABSOLUTE MAXIMUM RATINGS (Tcase = 25 °C unless otherwise stated) PD
Power Dissipation Drain – Source Breakdown Voltage * Gate – Source Breakdown Voltage * Drain Current * Storage Temperature Maximum Operating Junction Temperature
BVDSS BVGSS ID(sat) Tstg Tj
389 W 70 V ±20 V 25 A –65 to 150 °C 200 °C
* Per Side Semelab Plc reserves the right to change test conditions, parameter limits and package dimensions without notice. Information furnished by Semelab is believed to be both accurate and reliable at the time of going to press. However Semelab assumes no responsibility for any errors or omissions discovered in its use. Semelab encourages customers to verify that datasheets are current before placing orders.
Semelab plc.
Telephone +44(0)1455 556565. Fax +44(0)1455 552612. E-mail:
[email protected] Website: http://www.semelab.co.uk
Document Number 2599 Issue 5
Figure 6.3 Typical datasheet of an RF power transistor (courtesy Semelab Ltd., UK).
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Practical HF/VHF/UHF RF power amplifier realization
r breakdown voltages: voltage levels (at the device terminals) where the device will break down and fail. r threshold voltages: range of DC voltage levels (for FETs) where the device begins to conduct current. r load mismatch tolerance: a measure of what level of load VSWR the device can safely tolerate. r large signal impedances: usually plots of large signal input/output impedances plotted on a Smith chart that the device needs to see in order to deliver its rated power output, gain and efficiency at a specific power input, frequency, supply voltage and bias current. r typical transfer function plots: power output, efficiency, gain and distortion versus power input and output. r typical scattering (S) parameters versus frequency for broadband computer aided simulation. r input, reverse transfer and output capacitances versus supply voltage plots which visually show how the devices parasitic capacitance varies as a function of supply voltage.
6.4.2
RF power transistor device selection process guidelines The following is a discussion in more detail of each major section of a typical RF transistor data sheet. Proper RF transistor selection starts by taking into consideration the intended application, in other words, primarily what RF signal/modulation format the RFPA will ultimately be expected to amplify, to what power level with an acceptable level of distortion. A particular application may not demand a power level that will exceed that of an individual transistor, however if it does, combiners and dividers must be employed to reach a desired power output level. In either case, whether an RFPA design requires one or more RFPA stages, the system level specification must be met with substantial design margin at the individual final output stage level (if one transistor stage has adequate power) or scaled up (if one transistor stage does not have enough power).This margin will be eroded as more amplification stages are cascaded. Inside the device selection process exists the decision not only for what particular part within a class of transistors but also a selection of the specific class of transistor itself. By “class” of transistor, it is meant bipolar junction transistor (BJT), vertically diffused MOSFET(VDMOS), laterally diffused MOSFET (LDMOS), gallium arsenide FET (GaAsFET), gallium nitride (GaN) and silicon carbide (SiC) transistors. No one class of transistor is universally better than the others, each class of device has salient features that make it more amenable to a particular application than another. While BJT transistors have less gain and are more difficult to match across broad bandwidths than their MOSFET counterparts, in some pulse applications they can exhibit faster rising and falling transition durations. A disadvantage of BJTs currently is that there are fewer companies manufacturing these devices. MOSFETs (both vertically
6.4 RFPA system level design overview
247
and laterally diffused) offer higher Gain, easier bias configurations, higher large signal impedances and are less prone to thermal runaway. A limitation of MOS FETs is the availability of devices operating broadband over 1 GHz. GaAsFET and especially GaN devices offer excellent choices for ultra-broadband operation from 20 MHz to over 6 GHz. However, GaAS and GaN devices are more expensive and require more sophisticated bias schemes (sequencing) to safely turn the devices on. Silicon Carbide transistors offer a significantly higher maximum junction temperature ( + 255 ◦ C as opposed to + 200 ◦ C for LDMOS). Therefore, in the device selection process, the initial step is selection of which class of RF power transistor, then selection of a particular device within that class amongst device power levels and different manufacturers. Although it may be desirable to use as few RF power transistors as possible, there are applications and situations where it can be prudent to use multiple devices as opposed to fewer. For example, in mission critical Military applications, where reliability and “battle sure” characteristics are key, it is preferable to use more RF power transistors since the heat will be spread out over more devices (which can yield lower die temperatures) and in the event there is a single device failure, the impact on overall system performance is minimized. With this in mind, RF power transistor data sheets within a preselected class are first compared in terms of end use application compatibility. Although RF device manufacturers would prefer to make one transistor suitable for all uses, they do at some point optimize transistors to lend themselves better to certain applications. For example, Avionics RFPAs operate primarily in pulse mode and there exist RF transistors that are designed to put out substantial power, but expressly in pulse format. Try to get the same power out of this device in CW mode (or even extended pulse widths for that matter) and the device will be destroyed. A close review of absolute maximum ratings will cover just how far the device will hold up under extreme conditions such as maximum dissipation and junction temperature. The power output of a transistor states how much RF power a device can deliver. Take care in reviewing this parameter and note the conditions in which the device manufacturer has specified the output power. Remember, the RFPA has to deliver power, but is more accurate to state the RFPA has to deliver concurrent power, that is, deliver power while concurrently maintaining a variety of other specifications such as distortion levels, pulse fidelity, efficiency, etc. A particular transistor may deliver 300 W of RF power, but if the application demands 300 W of power with less than 1 dB of Gain Compression and your device is compressing 5 dB, the device, while capable of delivering the power is not capable of concurrently delivering the power at the required Gain and Gain Linearity level. The frequency range of a particular RF device should not be thought of in an absolute sense, that is, if a power transistor has a maximum specified frequency of 500 MHz, this does not mean the device will cease to function at 501 MHz. It will function at 501 MHz, it may even function at 600 MHz, and you may be able to use it there, but bear in mind if you do other parameters may not remain in specification such as minimum
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Practical HF/VHF/UHF RF power amplifier realization
Gain. The designer who does operate transistors far above their maximum frequency should do so only with a good amount of design margin. The gain specification of RF power transistors depends on many factors, frequency of usage, how the device is matched (narrowband versus broadband), output power level, temperature and load VSWR. Usually, a manufacturer will rate a device at a minimum gain at a particular frequency. This is a minimum value; however the devices they supply will usually have gain in excess of this amount. For the application where large quantities of amplifiers are expected to be produced, be cautious to design an RFPA stage that anticipates the “minimum,” and NOT “typical” gain of the device. The reason is that over time, the wafer fabrication process may yield transistors with lower gain than the typical value, and if you have designed a stage to require a device with typical gain, if a lot code of transistors is delivered with minimum gain, your amplifier will be out of specification and there will be no recourse with the manufacturer. A way of insuring your transistors are more uniform in performance is to put their performance under the restrictions of a source control drawing, or SCD. The SCD is a document of mutually agreed upon RF Transistor performance specifications, where the two parties in the agreement are the transistor manufacturer and RFPA manufacturer. This document calls out tighter performance specifications than exist on the standard device data sheet. It will force the device manufacturer to “cherry pick” devices from a lot that meet the values in the SCD. This will invariably lead to higher transistor costs, especially if the volume is low, but this issue can be eradicated by high-volume production quantities. How efficient a transistor operates is tied in closely with what class of amplification the transistor is biased to, if it is operated broadband or narrowband, what load VSWR it sees and what type of power combiner (zero degree versus quadrature) is used to sum the power of multiple stages. Usually, the efficiency listed on a data sheet was measured under narrowband, conjugate matched conditions so broadband efficiency will be lower and frequency/output power level dependent. The thermal resistance value is a measure of how easily the device can remove the heat its die generates to an external heat sink. Selecting a device with the lowest possible thermal resistance will yield lower die temperatures and failure rates. A low thermal resistance also provides for better pulse tilt performance. The breakdown voltages quantify what level of voltage the device will fail at, the larger this value the more a particular device will tolerate load mismatches. Device manufacturers specify transistors to handle severe load VSWRs, and they may in fact be able to withstand load VSWRs of 10:1; however, sometimes a severe load VSWR may precipitate oscillations which in turn can damage the part. The threshold voltages show a range of where the particular device begins to draw current based on a gate bias voltage. This voltage and its variation as a function of temperature will play a key role in the design of the bias thermal tracking network. The input and output impedance of the RF transistor is characterized by large signal impedance parameters. This is usually presented on the data sheet as complex series equivalent impedance that is plotted on a Smith Chart. The lower the input and output impedances are the more difficult it becomes to match it to 50 . The lower the Q of the impedances the better, as devices with a low Q lend themselves more readily
6.4 RFPA system level design overview
249
Figure 6.4 Generic circuit architecture for a thermally compensated bias network.
to broadband operation. These impedance levels provide a good starting point when determining input and output transformation ratios. Transfer function plots provide a good visual indication of how a device performs over a specific dynamic range of output power levels in terms of gain, efficiency and distortion. Scattering or “S”-parameters and “X” Parameters when provided, will enable computer aided simulations. CAD simulations are an invaluable tool to optimize input/output matching, broadband gain and efficiency. Input, reverse transfer and output capacitances are parasitic capacitances that exist within the semiconductor device. These capacitance values are dynamic (i.e., they vary with DC supply voltage and output power level). The lower the capacitance values the better as they will influence a host of parameters including gain, maximum operating frequency, stability and phase linearity.
6.4.3
RF power transistor bias/thermal tracking networks As discussed, there are three broad classes of RF power transistor: r BJTs; r metal oxide semiconductor FETs (vertically and laterally diffused, VDMOS, LDMOS); r gallium devices: arsenide (GaAsFET) and nitride (GaN). All three transistor types require unique bias networks and some form of thermal tracking to help maintain relatively constant quiescent currents while being subjected to varying thermal environments. Without the thermal tracking networks, RF bias currents may tend to drift and move into bias points that yield excessive or unstable gain or undesirable transfer functions. Figure 6.4 shows a simplified block diagram for a thermal tracking network architecture that might bias Bipolar, LDMOS/VDMOS and GaAs/GaN FET transistors. Bipolar
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Practical HF/VHF/UHF RF power amplifier realization
biasing requires a higher current capability than MOSFET devices. Bias networks for FETs, in the simplest form, can be a simple potentiometer. In any case, the bias networks must contain some source of temperature dependent voltage. Thermal tracking (or compensation) is a way to reduce bias current (or voltage) such that the quiescent currents and bias point of the RF transistor remains reasonably constant over temperature. The bias networks for GaAsFET or GaN devices are more elaborate sequenced networks, i.e.; the gate and drain voltages are “sequenced” or turned on/off in a defined order so as not to damage the device. GaAs transistors will draw heavy and perhaps destructive levels of drain current if a drain voltage is applied with zero gate voltage. To safely turn these devices on, the gate voltage needs to be brought negative first, the drain voltage is then applied, and the gate voltage is incrementally raised. The process is reversed to turn the device off. The main roll of the sequencer is to control this process.
6.4.4
RF input/output coupling/decoupling networks The input and output coupling capacitors are chosen to block DC and provide minimum capacitive reactance at the low end of the amplifier’s frequency range. These capacitors must maintain resonance free operation across the amplifier’s operating band. Capacitor manufacturers’ data sheets usually show a typical capacitor series resonance performance curves over a particular frequency range. These curves convey that even chip capacitors will series self-resonate at some frequency. For narrowband applications, the series resonant frequency of a particular chip capacitor will be the best frequency to use the device as a coupling/decoupling capacitor as it exhibits the lowest possible impedance. RF chokes are employed to decouple the RF signal and to feed in the DC operating bias and supply voltages/currents. As in the case of coupling/decoupling capacitors, the RF chokes should also exhibit resonance-free operation where a particular choke exhibits only inductive reactance across the entire band of intended amplifier operation.
6.4.5
Power transistor impedance matching There are a variety of methods to match the impedances of an RF power transistor to 50 . What method to use is determined by the frequency range and required bandwidth. High frequency and very high frequency (HF, 1–30 MHz, VHF 30–300 MHz) RFPAs are best matched with discrete LC networks for narrowband and transmission line transformers for broadband (>1 octave) applications. Ultra-high-frequency (UHF, 300 MHz-1 GHz) RF power transistors are matched with printed micro-strip, transmission line transformers or combinations of the two. For the HF to UHF frequency range, transmission line transformers are by far the most versatile matching technique as they are architecturally identical regardless of where in the frequency spectrum they are applied. The frequency range may be different, however the transformer coaxial impedances and interconnections are the same. How long the coaxial line elements are, and whether or not they are ferrite loaded are the primary differences between a transformer operating at HF or UHF frequency ranges. In addition to extreme bandwidth capability, the transmission line transformer has the
6.4 RFPA system level design overview
251
Figure 6.5 Schematic of an RLC feedback network applied to an enhancement-mode, N-channel
MOSFET.
ability to convert an unbalanced signal to a balanced drive required for commonly available Gemini RF Power transistor packages that are prevalent in this frequency range.
6.4.6
Feedback networks Feedback can be employed to reduce low-frequency gain and help improve the individual amplifier module gain flatness. Figure 6.5 shows the generic circuit architecture for an resistive-inductive-capacitive (RLC) feedback network. The inductor (L) and capacitor (C) are chosen to resonate at the lowest operating frequency of the RFPA. The intent is to have maximum negative feedback where the gain of the transistor is greatest. The capacitor will also block the DC supply voltage from reaching the gates (or bases) of the RF transistors. The value of (R) adjusts the amount of feedback. This represents only one method of RF Feedback, there are other more complex methods (transformer based) that achieve DC isolation by magnetically coupling the feedback signal.
6.4.7
Thermal management While generally not considered part of the RFPAs circuitry, the method by which heat is removed from an RFPA is equally vital. Improper heat removal can lead to degradation of an array of RF performance parameters including linearity, efficiency, gain and stability,
252
Practical HF/VHF/UHF RF power amplifier realization
etc. In addition, higher operating die temperature equates to reduced operating lifetime and increased Failure Rates. For most applications, forced air cooling is adequate, in high-altitude airborne applications, liquid cooling is a preferred option as the reduction in air density inhibits the efficacy of forced air. In either case, however, the thermal interface between the RF power transistor and the module base, heat sink or chill plate is critical, so the details of creating a proper transistor flange thermal interface are covered.
6.5
Hypothetical amplifier design example: (20–400 MHz RFPA subsystem module for 1 kW amplifier application in electronic warfarecommunication jamming) To help illustrate and better convey a typical RFPA module realization, a hypothetical amplifier design example is presented. The process will involve: r r r r r r r
6.5.1
hypothetical application example overview; RFPA qualitative specification delineation; RFPA specification quantification; RFPA module hardware design; RFPA module physical construction; test setup; test results.
Hypothetical application example overview RF Power amplifiers that are used for electronic warfare (EW) communication jamming applications must have very broad bandwidth capability such that they have the ability to jam various communication bands. Frequencies in the range of 20–200 MHz are popular for land/mobile communications and military aviation bands heavily populate 225– 400 MHz. It is beneficial to have one amplifier cover both bands so the design goal is to span 20–400 MHz. The amplifier will be used to selectively inhibit communications; its output will be connected to a broadband antenna, so the load VSWR will deviate far from a perfect match.
6.5.2
Amplifier qualitative specification delineation The following is a list of specifications that are critical to broadband jamming applications. This is a cursory initial attempt, only field trials and beta testing will reveal if certain parameters are more essential than others. 1. High power: the RFPA must have enough output capability to overpower receivers and block enemy signal transmissions. 2. Broad bandwidth: the RFPA must have adequate operating frequency range to cover a variety of communication bands.
6.5 Hypothetical amplifier design example
253
3. High gain: the amplifier must have enough gain such that it can be driven to full power output by a small signal level input. 4. Flat frequency response: the amplifier should perform uniformly at all frequencies within the desired range. 5. Load VSWR tolerant: since the RFPA will be used to jam point to point communications at various frequencies; it will more than likely have to drive antennas that present less than ideal load VSWRs which may go as high as 5:1. The amplifier must be able to drive into these loads without damage. 6. Stability, spectral load pull: as the RFPA must not be damaged by driving adverse load VSWRs, it also should not oscillate at unacceptably high power levels under these conditions as well. 7. Linear: although high gain linearity is not usually critical, certain jamming situations will require the RFPA’s output levels to be precisely controlled. 8. Temperature range/stability: the amplifier will be most likely used in adverse field environments where high temperatures are common. The amplifier will be expected to provide acceptable performance in these temperature extremes. 9. Altitude: the amplifier may be in an avionics platform if it is expected to jam airborne communications, in this case, forced air cooling will not be an option, liquid cooling and chill plates are preferable. 10. Shock/vibration: most military amplifiers are deployed in mobile transport environments. Ability to withstand severe shock and continuous vibration is essential. 11. Radiated emissions and susceptibility: while the RFPA is intended to render specific enemy communication equipment ineffective, it must not interfere with or have its own operation impaired by other colocated equipment. The RFPA must then be adequately shielded for EMI. 12. Mean time to failure: the amplifier, above all, must be reliable, lives will depend on it. To ensure this, the transistor silicon (or die) temperature must be kept as low as possible.
6.5.3
Amplifier specification quantification With a generic list of required specifications, the next step is to assign quantities to each line item. Since the focus here is on HF/VHF/UHF RFPAs, the specifications that directly address the power amplifier module will be covered quantitatively. (Note: for ease of illustration, quantities will be loosely assigned and may not represent actual system requirements, which in many cases, is classified information). r r r r r r
system power output: 1 kW, continuous wave, minimum; bandwidth: 20–400 MHz, minimum; gain: +60 dB, nominal; gain flatness: + / −3 dB, maximum; antenna load VSWR: 100,000 h, minimum, calculated.
6.5.4
Amplifier hardware design/realization The requirement has now been defined quantitatively. The process to start the physical realization begins with the System Block and Wire diagram as shown in Figure 6.6. The simplified diagram shows all the stages in the RFPA system. While there do exist RF transistors that can deliver 1 kW of CW output power, the challenge becomes heat removal and AC coupling of the RF signal. If an RF device puts out 1 kW of RF power at, for example, 50% efficiency, then 1 kW of heat will need to be dissipated. Add in bad load VSWR and the dissipation will worsen. In addition to heat dissipation, the RF current that will be present at the low-impedance output of a 1 kW transistor will tax even the highest quality chip capacitor. It will be a more reliable approach to use multiple RF power transistors. One of the benefits of a system level block and wiring diagram is it shows the insertion gain, loss and RF power levels as power propagates through the amplifier
6.5 Hypothetical amplifier design example
255
stages. It displays just how much power is lost through directional couplers, RF dividers and combiners. The loss values shown in the block and wire diagram are from actual couplers and hybrid combiners. Note that for an amplifier to produce 1 kW of linear load power into a 5:1 VSWR it actually needs to be capable of driving 2788 W of power into a 50 load. After adding losses for the coupler and combiners, the total required RF transistor die power is about 4172 W. Choosing a binary multiple port combiner with 32 ports, then 4172 W divided by 32 yields about 130 W. We now have an approximate maximum RF transistor output power. The next phase is RF device selection where the selection guidelines are for an RF power transistor capable of 20–400 MHz operational bandwidth at a power level of at least 130 W of linear power. The system block and wire diagram is broken down further in Figure 6.7 to a block diagram of the basic RFPA module.
6.6.5
RF transistor selection Current popular output power ranges for RF transistors are 100, 150, and 300 W of output power. Since we need approximately 130 W of CW output power, the focus is on the 150 W range of CW RF power transistors that are designed for operation up to 400 MHz. An overview of classes of transistors was first considered. Since the frequency of operation was only to 400 MHz, GaAs and GaN devices were ruled out. They will work far in excess of 400 MHz; the added cost for this unneeded capability is not economically justifiable. BJTs were not selected due lower gain and most importantly, a limited amount of device manufacturers. Few manufacturers mean a low probability of obtaining a “second source” (i.e., an alternate manufacturer with an equivalent part that will replace the primary device in terms of form, fit and function) of BJT transistors. It sounds innocuous, but not having a second source of a replacement RF transistor is a very difficult situation to be in. You simply do not want to one day find yourself in this particular fix and here’s how this might happen: 1. RF transistor semiconductor wafer fabrication processes are fickle, although they are tightly controlled, in the end they are run by humans. At any point in time a particular device process control can vary yielding devices that may work on a substandard level and can render an RFPA with slim design margins in violation of specification. 2. RF transistor device manufacturers have, can and someday may either discontinue, de-rate or sell a particular line of transistors to another manufacturer. If either of these situations occur, a once profitable RFPA design can overnight devolve into a “lab queen” (an amplifier that can only meet specification by copious amounts of tuning, requiring days or weeks in the test lab) or, even worse, cause a “stop production” mode where shipments have ceased leaving the RFPA engineer (yes, this would be you) frantically searching for an alternative part.
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Practical HF/VHF/UHF RF power amplifier realization
Figure 6.7 Multilevel breakdown of an RFPA module to component level.
6.5 Hypothetical amplifier design example
257
D1020UK Vgs vs Temp 5.6 5.4
Vgs for Ids = 2 amps
5.2 5 4.8 4 8 4.6 4.4 4.2 4
Flange Temperature°C
Figure 6.8 2 A Idq bias point of the D1020UK versus temperature.
This leaves the MOSFET class of devices. For this particular application, either vertical or lateral MOSFETs will work equally well. The selection process now descends to segregating parts that work across the 20–400 MHZ band at a minimum of 150 W of linear CW power with a manufacturer recommended application for communications in the HF/VHF and UHF band and a load tolerance at least up to 5:1 VSWR. Several devices were considered, their data sheets compared and RFPA stages were constructed and actual test data compared. The Semelab D1020UK was selected based on its ability to satisfy the design criteria. The data sheet for this device is in Figure 6.3.
6.5.6
Gate bias/temperature tracking/compensation network The gate voltage versus temperature plot of the D1020UK is shown in Figure 6.8. This was obtained by biasing the device to 2A quiescent and varying the gate voltage for a constant Idq as the ambient temperature was varied from −50 to +150 ◦ C. Note the gate voltage level to sustain 2A quiescent drops approximately 4.4 mVDC/◦ C. In other words, if the gate bias voltage is held constant over increasing temperature, by virtue of the fact that the 2A bias voltage point is continuously lowering with increasing temperature, then the fixed gate bias voltage migrates by default into higher and higher drain currents. This makes the gain and operating class point of the FET dependent on temperature. To mitigate this issue, an open loop thermally tracked bias voltage can be deployed. This is accomplished by mounting a temperature sensing IC mechanically adjacent to the device that is to be compensated. Ideally, it is desired to have the bias voltage dropped by the equivalent amount that the 2 A gate bias voltage point drops. What is nice about the bias voltage variation of the D1020UK is that it is approximately linear. This makes it easy to correct as temperature sensors that have linear outputs (in mV/◦ C) are readily available.
Practical HF/VHF/UHF RF power amplifier realization
Vtemp 0.1
Figure 6.9 Operational amplifier based thermal tracking circuit for the D1020UK.
D1020UK Quiescent Bias Current vs Temperature 3 2.5 D1020UK IDQ (Amps) mps)
258
2 1.5 Uncompensated
1
Compensated
0.5 0 -10
0
10 20 30 Ambient Temperature (Degrees Celsius)
40
50
Figure 6.10 Comparison of the quiescent currents of D1020UK without (dashed trace) and with (solid trace) a thermally tracked bias voltage.
All that needs to be done is to adjust the transfer function slope of the temperature sensor such that it has the inverse slope of the gate voltage. The gate bias/temperature compensation network for the amplifier is shown in Figure 6.9. It consists of a simple precision variable voltage divider ( −5 VDC) network that is summed together with a temperature dependent voltage (Vtemp) that is mechanically linked to the RF transistor to lower its bias voltage as the device heats up. The part chosen for the temperature sensor is the Analog Device TMP35 which has a scale factor of about 10 mVDC/◦ C. The 5 K resistor and 10 K potentiometer adjust this scale down to 4.4 mVDC/◦ C and then it is summed into the precision variable −5 VDC reference. This is an open loop compensation network and helps the D1020UK maintain a more temperature stable bias current. Figure 6.10 shows the drain current versus temperature with and without thermal tracking. Without thermal tracking the Drain current varies
6.5 Hypothetical amplifier design example
259
1.1 A over the −10 to +50 ◦ C temperature range. Adding the thermal tracking network reduces this by over 80% to 0.2 A of drain current variation. While this is considered good performance, it is important to note that this is open loop correction and the temperature compensation accuracy can vary from lot code to lot code and also on the same device due to memory effects. Thermal compensation networks can be designed with greater accuracy if they take into account the behavioral modeling of a particular class of device.
6.5.7
Input/output RF/DC coupling/decoupling networks A coupling/decoupling network is merely another name for capacitors and coils in an RFPA. Coupling networks are usually capacitors that pass the RF power signal from one device to another while blocking DC voltages and currents. Decoupling capacitors are used to bypass RF signals to ground. Inductors in coupling networks perform the duality function, that is they will pass DC voltages and currents while suppressing RF signals. In a broadband RFPA, the values selected for these components are solved for at the extremes of the operating band edges. These networks will be based relative to the large signal input and output impedances of the D1020UK. The coupling/decoupling components generally have to meet three criteria: r satisfy a minimum reactance(impedance) requirement at the lower frequency limit; r handle high DC and RF currents, voltages, and power; r sustain resonance-free operation beyond the RFPA upper frequency limit. By viewing the three requirements, one need only solve for a component value at the lower band edge. The remaining criteria are assessed by manufacturer’s data sheets and component verification testing on a vector network analyzer (VNA). The values for the coupling and decoupling inductors and capacitors are solved for in the next section as it will be required to see what impedance matching network is required first.
6.5.8
Input/output impedance matching networks There is a multitude of ways to match the input and output impedances of an RF power transistor. If one looks at the characteristics of the input and output impedance of the D1020UK, it becomes apparent (at least for a broadband amplifier application), that it will be difficult, if not impossible, to provide an exact, complex conjugate match for the device at all frequencies and input drive/output power levels to be expected to be used. A balance has to be struck between where to choose to match a particular device. On the input, the device should be matched at the point in the frequency range where its gain is lowest (the highest frequency it will operate at). The output is matched at the highest level of expected RF output power. To match impedances over multiple octaves in the HF/VHF/UHF band, the transmission line transformer is the most effective method. In addition, it converts an
260
Practical HF/VHF/UHF RF power amplifier realization
unbalanced signal to a balanced drive required for Gemini packaged transistors such as the D1020UK. The transformer, while able to transform impedances over wide frequency ranges, only does a fixed transformation ratio. RF power transistor terminal impedances will vary, so a transformer will transform impedances of a transistor effectively over a limited frequency range and output power level. Outside of these areas, input VSWR, gain, and efficiency will suffer. Starting with the input matching network, the input terminal impedance of the D1020UK is extracted from its Smith chart on the device data sheet. The gate to gate series equivalent input impedance at 400 MHz is 0.4-j2.3 . Converting this to a parallel equivalent impedance yields a real portion of 13.62 from gate to gate. Dividing 50 by 13.62 equates to 3.67:1. The nearest realizable balanced drive transformation ratio is 4:1. A rough estimate of output impedance from drain to ground is given by the equation: Ro =
2 Vdd 2Po
(6.1)
The transistor will be operated at 28 VDC and at approximately 75 W of power per side. This estimates approximately 5.23 from drain to ground. The push–pull configuration of the Gemini package doubles this to 10.45 . We can also extract a close value also from the Smith chart drain to drain series equivalent impedance as was done for the input. The series equivalent value is 0.9-j3 at 400 MHz. Converting to the parallel equivalent yields a real portion of 10.84 . Dividing 50 by 10.45 equates to 4.78:1. Again, the nearest realizable ratio with a balanced drive capability is 4:1. The term “realizable ratio” means a value of transformation ratio that can be physically constructed with a finite number of transmission lines. For a particular transformation ratio to be physically realized, the square root of the transformation ratio must be a rational number. If it is not, an infinite number of transmission lines would be required to realize the ratio, an obvious impracticality. For both the input and output transformations, an approximate 4:1 ratio is required. Invoking a topological network synthesis procedure [1] for transmission line transformers, the first step is to satisfy the necessary and sufficient conditions for finite coaxial element equal delay transmission line transformers: √ N = Rational Number (6.2) where N = required transformation ratio. The square root of 4 is 2, a rational quantity. The necessary and sufficient realizability condition is satisfied. The synthesis procedure can now begin with the reasonable expectation of a physically realizable network. The first step is to determine the number of coaxial lines in the first subgraph: √ (6.3) n 1 = 4 = 2, where n1 is the truncation of the square root of the transformation ratio N, and in this case is the number 2.
261
6.5 Hypothetical amplifier design example
Zo
Z in
Z out Zo
Figure 6.11 Subgraph result of a topological synthesis of a 4:1 transmission line transformer.
Z in
Zo Zo
Z out
Zo
Figure 6.12 Completed unbalanced to balanced drive 4:1 transformer network.
The synthesis procedure will terminate if: √ N1 = √ N − n 1 = 0 N1 = 4 − 2 = 0
(6.4)
The process terminates and two coaxial lines are inserted into subgraph 1 as shown in Figure 6.11. The characteristic impedance, Z0 , of the coaxial lines is solved for by: (6.5) Z 0 = Rs Rl where Rs and Rl are the source and load resistances terminating the transformer, respectively. These values are 50 and 12.5 and solve for a characteristic impedance of 25 . The synthesis procedure provides a transformer architecture that is applicable to unbalanced to unbalanced loads. The D1020K in a push–pull configuration demands a balanced drive network. Therefore the transformer of Figure 6.11 needs to be converted to a true balanced network (one that would present an electromagnetically balanced distributed network) by interchanging the shield and center conductors of the lower transmission line element. The transformer configuration now provides a balanced to balanced drive. A 1:1 balun transformer is added at the high impedance port to provide the unbalanced to balanced drive conversion such that the input to the transformer can be reached by ground referenced coaxial or micro strip feeds. The final 4:1 unbalanced to balanced transmission line transformer architecture is realized and shown in Figure 6.12. The synthesized 4:1 architecture is a “boiler plate” circuit structure, that is, in this format it is an engineering construct that can conceivably work in broad frequency spans
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Practical HF/VHF/UHF RF power amplifier realization
Figure 6.13 Simplified parasitic model of 4:1 transformer network.
anywhere from 10 kHz to well over 1 GHz. That’s comforting, but the RFPA specification only requires 20–400 MHz. The transformer architecture needs some massaging to get it to have a “sweet spot” of 20–400 MHz. By “sweet spot” it is desired to have the transformer’s absolute values of insertion loss minimized and return loss maximized from 20–400 MHz. In the world of engineering constructs, the physical transmission line transformer is an ideal transformer nested in a plethora of parasitic reactances. These reactances will limit the usable frequency range. The reactances that limit the lower and upper frequency range of the transmission line are primarily inductive in nature. The low-frequency range is limited by shunt inductance, the high end is limited by parasitic series inductance, and these are shown schematically in Figure 6.13. Parasitic distributed gradient capacitive reactances will resonate with line inductances and may cause in-band insertion loss “suck-outs,” a narrow band of frequencies within the pass band where the insertion loss spikes to very high values and then returns to low values. Additional losses in the transformer are from ferrite cores, coaxial line dielectric, copper conductors as well as radiation losses. After realizing the 4:1 architecture, the next step is ferrite loading the coaxial line elements in order to suppress even mode (nontransmission line) currents and create a net mutually coupled inductance that is in far excess of the impedance to be transformed so that its parallel loading effect is immaterial. As shown, a physical transmission line transformer is a complex model, an ideal transformer, mutually coupled inductors, parasitic reactances, and transmission lines. An equivalent circuit of the mutually coupled inductors is shown in Figure 6.14. There are essentially four inductors in the 4:1 transformer section, two in each coaxial transmission line. For all intents and purposes, inside the coaxial lines, the coefficient of coupling is
6.5 Hypothetical amplifier design example
i
263
i L1
L1
L3 M12/21
L2
M34/43
L3
L2 L4
L4
Figure 6.14 Mutually coupled inductances of a 4:1 transmission line transformer.
considered bi-directionally unity, that is, all the flux generated by the center conductor of the coaxial line is linked to the outer shield and vice versa. The 4:1 is open circuited to help visualize the mutually coupled inductors with a common-mode current, i, flowing through all four inductors. The net value of this inductive reactance should be at least 5–10 times the value of impedance of 50 so it does not adversely load down the very impedances the transformer is trying to step up. The path for finding the total inductance starts with: vi = L 1
di di di di di di di di + M12 + L 3 + M34 + L 2 + M21 + L 4 + M43 dt dt dt dt dt dt dt dt
(6.6)
where Mx y = k
Lx L y
(6.7)
and k=1 Lx = L y
(6.8)
L 1 = L 2 = L 3 = L 4 = M12 = M21 = M34 = M43 L t = 8L SW
(6.9)
So
What the above equations state is that due to the 4:1 transformer configuration of four mutual, bi directionally unity coupling coefficient inductors, to solve for the net shunt inductance, simply multiply the inductance of what will result from winding an inductor of a single wire on a given ferrite (Lsw ) by eight. We would like to have the shunt inductance to be >5–10 times greater than 50 so as not to load it down. We also must keep the length of the 25 coaxial lines as short as possible so as not to incur in-band resonances in the response of the 4:1 transformer. We therefore start out with keeping the number of turns through a ferrite core to a minimum of two turns.
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Practical HF/VHF/UHF RF power amplifier realization
Figure 6.15 Measured results of mutually coupled inductances of a 4:1 transformer.
Solving for the required inductance factor at 20 MHz: Xl ∼ = ωl ∼ = + j500 ∼ = ω8n 2 Al
(6.10)
where n = number of turns through the ferrite core = 2. Note that the above equation is laced with “approximately equal to” (∼ =) signs instead of “equal to” (=). The reason is that the inductance factor tolerance of ferrite toroids is about + / −25% at best, so there is little point in trying to solve this equation precisely as any inductor or transformer you might construct using ferrites will vary wildly in value. It has been factored in ahead of time to have the shunt inductance of the transformer to be 5–10 times 50 , so if you land in this region, the transformers low-end response will be acceptable. The equation was nevertheless solved and an approximate inductance factor of 124 nh/n2 was calculated. A ferrite core from ceramic magnetics (Part 6.T503125T-C2050) was chosen as its measured inductance factor is 100 nh/n2 . The transformer is constructed with 25 coaxial lines with two turns through each ferrite toroid core. The transformer was evaluated on a VNA with the low-impedance side of the transformer loaded by an open circuit. This will measure the parallel inductance. The plot in Figure 6.15 shows the results with the value of inductive reactance at an adequate level of 4.3 μH which yields a parallel inductive reactance of + j540 , more than enough so as not to impair the low-frequency return loss response. The transformer can
6.5 Hypothetical amplifier design example
265
Figure 6.16 Input return loss of the 4:1 input transformer with 6.25 chip resistor terminations on the low-impedance port.
then be terminated with 6.25 chip resistors to evaluate how the device transforms the resistances to 50 . The graph of the transformer’s input return loss is shown in Figure 6.16. It yields an average of −21.6 dB of return loss. The plot of the transformer’s input Insertion Loss is shown in Figure 6.17, (note the values on the data need to be divided by two as the plot is of the transformer’s return loss with an open circuit load, hence the insertion loss is half). There is a small resonance at 383.62 MHz, these can occur in ultra-broadband transformers, the best way to mitigate them is to shorten the length of the coaxial lines. Typically, the transformer will also have series inductive reactance that will impair the high-frequency range. This can be tuned in with compensation capacitors. Although these can be calculated, it is fairly quick to optimize a transformer by substituting different values of shunt capacitance during test procedures and selecting the value that yields the best broadband return loss. Since both the input and output ports of the amplifier demand a 4:1 transformer, the same device architecture will be used both ports. The output transformer uses larger cross-sectional area ferrites and larger diameter coaxial cable to accommodate the higher power levels. With the impedance matching transformers solved for, it is now a fairly simple task to go back to solve for the coupling capacitors. We know the capacitance value must present a low reactance at 20 MHz. The coupling capacitors are to be inserted at the
266
Practical HF/VHF/UHF RF power amplifier realization
Figure 6.17 Low-impedance open port return loss of 4:1 transformer (to obtain insertion loss, divide plotted values by 2).
50 point between the 4:1 and 1:1 transmission line transformers. It is desired to have the reactance at least 1/100th of 50 or less than –j0.5 at 20 MHz. Solving for C: 1 = 0.0159 μF (6.11) ω.0.5 The maximum amount of average current that the series coupling capacitor will see occurs at 150 W CW, therefore √ √ Pmax .z 150.50 vrms Imax = = = = 1.73 A (rms) (6.12) z z 50 Based on the three criteria set earlier we have two of them solved for, the minimum value of capacitance and the maximum average current with a 50 load. To be conservative, the maximum current will be doubled to account for driving adverse load VSWRs. The D1020UK is a + 28 VDC device, so the DC operating voltage must be in excess of this value. The chip capacitor selected is a 0.1 μF, 50 WVDC 200B series capacitor manufactured by ATC. The capacitor can handle over 9 A of average RF current so it will be suitable not only for the output coupling capacitors but the input as well. The remaining issue is to verify the capacitor, on its own, will maintain a lowimpedance, resonance-free, operation throughout the entire amplifier bandwidth. This C≥
6.5 Hypothetical amplifier design example
267
Figure 6.18 Impedance of 0.1 μF chip capacitor from 20–400 MHz.
is verified by doing a one-port impedance analysis using a VNA. Figure 6.18 shows the response of the coupling capacitor across the 20–400 MHz bandwidth.
6.5.9
Feedback network Manual calculation of the feedback resistance value can be very roughly determined by the following equation [2]: (V2 + V3 ) R f = V1 −V2 V2 − R4 − R2 R1 where: Rf = feedback resistance in ; V1 = voltage gate to gate at 400 MHz = 9.7 V rms; V2 = voltage gate to gate at 20 MHz = 2.17 V rms; V3 = voltage drain to drain on D1020UK at 150 W output = 43.3 V rms; R1 = R2 = impedance on output of input matching transformer = 12.5 ; R4 = output load, drain to drain = 12.5 .
(6.13)
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Practical HF/VHF/UHF RF power amplifier realization
This equation only provides a rough estimation of feedback resistance value. In a broadband amplifier, intentional negative feedback can swing positive if not carefully modeled. In this particular case, the equation yielded a value of 52.5 . At some levels of drive the amplifier went into oscillation, so the value was increased to 100 and the amplifier became stable. With this level of feedback the gain at 20 MHz was reduced by approximately 8.3 dB. The small signal gain plots are given in Section 6.5.12.
6.5.10
Test setup configuration/analysis Prior to the discussion of the example RFPA’s construction and electrical test results, some effort will be devoted to what is required to verify the amplifier is specification compliant on a modular level. It is prudent to verify compliance at a modular level for the obvious reason that if you can’t meet specification there, in certain parameters, it is unlikely performance will improve at a system level. Knowing how to test an RFPA is every bit as essential as knowing how to design one. How accurately the test results are acquired will ultimately advise the RFPA engineer of how much design margin does/doesn’t exist. The tests must be performed only on test equipment that is within its calibration cycle and has National Institute of Standards and Technology (NIST) traceability. This is to insure that whatever test results you obtain will ultimately agree with your customer’s data. Even though the module is fairly small and may cost only a few thousand dollars to fabricate, to fully analyze and test for this particular requirement will require several million dollars in test equipment. Decisions will need to be made along the way whether or not to purchase, rent, lease or use a test facility’s equipment. The key piece of test equipment is the VNA. This unit has the ability to measure input return loss, transformer insertion loss, small/large signal gain, gain flatness, and insertion gain/phase linearity. The spectrum analyzer in conjunction with the paralleled loads and binary stepped transmission line will monitor the modules spurious response while being subjected to various load VSWRs. The binary stepped transmission line [3] is simply lengths of coaxial cable cut to specific lengths and switched in line with 2, 3, 4, and 5:1 load VSWRs such that impedances along constant load VSWR circles can be applied to the output of the RFPA module. This leads back to an earlier discussion in this chapter on the topic of unconditional stability. This is the very test that is performed to assess load pull stability. It becomes apparent that it is impossible to present a circuit at the output of an RFPA that can emulate all impedance points bounded by constant load VSWR circles on the Smith Chart. Figure 6.19 is a block diagram that illustrates the interconnection of a typical test setup that will verify a substantial portion of the module’s performance. The output of the VNA is fed to a low-level test driver to increase the power to the point where it is sufficient to drive the RFPA to full power. The precise output power level of the RFPA is sampled with a calibrated directional coupler and fed to an RF Power meter. For gain, gain flatness, and insertion gain/phase linearity, the VNA has the ability to calibrate out the response variations of the low-level driver. The VNA can characterize a majority of the amplifier’s frequency and power domain responses. In addition, when the RFPA is
6.5 Hypothetical amplifier design example
269
Figure 6.19 Typical RFPA module/system test configuration.
subjected to temperature, altitude and vibration analysis, the very same test setup can be deployed with the initial response transfer functions stored in memory and compared as temperature and vibration levels are increased. While the setup in Figure 6.19 can cover a majority of the required tests, to execute radiated and conducted emissions tests will require the sophisticated setup in Figure 6.20. These are highly elaborate systems, the center of which are 3 and 10 m anechoic chambers which effectively provide a controlled EMC environment in which to test the amplifiers susceptibility to, and emission of, EM radiation. The RFPA is placed in a 3 m chamber and subjected to high-power RF energy emitted from closely placed bi-conical log and double ridge horn antennas. The amplifier is then monitored for its ability to maintain specified operation without degradation of performance while the frequency and field strength of the radiated RF energy is varied over very broad ranges. For radiated emissions, the amplifier is placed on a turntable within the semi anechoic 10 m chamber; it is then rotated while transmitting full RF power output. Highly sensitive, Bi-conical, Log periodic and Active Loop antennas are located about 20 feet away and will be elevated and lowered based on the EMI/EMC specifications. The signal received by the antennas is plotted on a graph with limit lines that show if the amplifier is emitting RF energy beyond acceptable amounts. Radiated emissions is one of the few requirements of the RFPA specification that if the amplifier is not compliant at a module level, it remains possible to be compliant at a system level since the amplifier will be mounted within a metal chassis that will allow for further shielding and reduction of emissions.
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Practical HF/VHF/UHF RF power amplifier realization
Figure 6.20 Simplified block diagram of 3 and 10 m EMC test chambers.
A highly accelerated life test (HALT) chamber is shown in Figure 6.21. This has the unique ability to apply random vibration to the RFPA module in six axes (X, Y, Z, yaw, pitch, and roll). This is more effective than a single or dual axis vibration table as it can effectively impart vibration energy to the module that is close in line with what it will encounter in the field. In addition, the HALT chamber has the ability to change temperature from −100 to +200 ◦ C.
6.5 Hypothetical amplifier design example
271
Figure 6.21 HALT chamber.
6.5.11
Physical RFPA module construction A photo of the individual breadboard RFPA stage is shown in Figure 6.22. The printed circuit board with micro strip interconnecting transmission lines is mounted into an aluminum module. There are two PC boards, one for the input divider/matching network and one for the output. The transistor is mounted in a milled-out channel 0.070" deep such that the gate and drain leads sit flush with the PC board. This channel is perhaps the most important machined surface within the entire module, care was taken to specify that it has a surface flatness of better than 5 μm/cm along with an RA (average surface roughness) of better than 1 μm. The device manufacturer has provided this mounting information [4]. With the mating surface ready, a very thin layer of thermal compound was applied to the bottom of the RF transistor’s flange. The compound is applied such that the color of the gold plating on the flange is visible through it. The idea here is that the best thermal interface is metal to metal contact, but since the surfaces of both the transistor and finely machined surface are not perfect, very small air pockets will exist. The role of the thermal compound is therefore not to get in between the module to transistor (metal– metal) contact, but rather to fill the minute air pockets. The final step in mounting the transistor is to use the appropriate screws with the recommended mounting torque. In this particular case, two 4–40 screws were deployed with a torque of 5.0 in.lbs.
272
Practical HF/VHF/UHF RF power amplifier realization
Figure 6.22 Breadboard of 20–400 MHz, 150 W CW RFPA module; thermal tracking sensor is located in the front center on the module wall.
The input 1:1transformer consists of two turns of 0.062 inch, sleeved, 50 semi rigid coaxial cable on a 0.5 inch Ceramic Magnetics ferrite toroid part 6.T503125T-C2050. The input 4:1 transformer consists of two turns of 0.062 inch, sleeved, 25 semirigid coaxial cable on two of the same cores. The input coupling capacitors isolate the DC bias voltage on the gates and couple the RF input signal from the 1:1 to the 4:1 transformer. The temperature compensated bias voltage sensor is mounted to the side wall and its output is fed to the gates of the transistor through a 5 K resistor. The resistor values can be this high as the gates of a MOSFET present an extremely high DC impedance. The output 1:4 transformer is constructed with a heavier gauge (0.085 ) sleeved 25 and 50 semirigid coaxial cable. Three turns of 25 coaxial cable are wound through Ceramic Magnetics toroid part 6.T874525T-C2050 for the 4:1 transformer and similarly for the 50 coaxial cable on the output 1:1 transformer. The selection of toroidal transformers helps also to meet EMC requirements as transformers wound on toroids will radiate less RF energy. Although not shown, the RFPA module will be populated with three more identical amplifier stages, the outputs of which will be connected to a four port combiner. With 150 W of output capability per stage, one module will yield about 500 W of output power after combiner losses.
6.5 Hypothetical amplifier design example
273
Figure 6.23 Rubberized EMI gasket seated in milled out channel in RFPA module wall top surface.
The module is a machined out enclosure, the side walls have a channel milled out to seat a metallized rubber EMC gasket (Figure 6.23) that will seal the interface to the top cover. This mechanical configuration will provide an effective method of limiting unwanted radiated emissions at a modular level. While there exist many numerical methods to design an RFPA to meet certain electrical specifications such as power output and gain, designing an RFPA to comply with radiated/conducted emissions and susceptibility represents a formidable challenge. This is due to the fact that many of the things that influence the module’s shielding properties are difficult to model. This will tax even the most sophisticated EM simulation programs. There are preventative measures one can take in the design phase of an RFPA: 1. Form all inductive (transformers and chokes) components on toroidal cores if possible. 2. Individually shield each stage with milled out enclosures and covers that seal the gain stage with EMI rubberized gasketing. 3. Use inline filtercons on all DC/signal feeds into and out of the RFPA module where possible. 4. Test each unique RFPA for EMC compliance at a modular level.
6.5.12
RFPA module test results The final RFPA module schematic is shown in Figure 6.24, the transistor is connected to the input–output transformers, bias adjust and thermal tracking networks. The values
274
Practical HF/VHF/UHF RF power amplifier realization
Figure 6.24 Complete 20–400 MHz, 150 W CW RFPA module schematic.
of compensation capacitance will change and depart from those that provided the best return loss with chip resistor test terminations and will now be chosen to satisfy the best input match/gain at 400 MHz and best efficiency at 150 uniformly across the band. The two port small signal response of the network is shown in Figure 6.25a, b. Figure 6.25a shows the input match characteristics. The RFPA module stage has high gain at the 20 MHz low-frequency band edge with poor return loss and the inverse at the high end of the band. The RLC feedback networks as shown in Figure 6.5 were used to lower the gain 8.3 dB at the low end of the band and improve the overall gain flatness. Figure 6.25b shows the gain flatness plot with this feedback. The gain flatness is 6.8 dB peak to peak, this can be compensated for on a system level by using a small signal gain equalization network or an ALC loop. The feedback capacitor is chosen primarily as a DC blocking component and the inductance value is chosen so as to resonate at 20 MHz such that the feedback and gain reduction is maximized where the device’s gain is greatest. The gain and phase linearity (AM–AM and AM–PM distortion) response of the amplifier is shown in Figure 6.26a–e. With a bias current of 2A at a Drain voltage of +28 VDC , the linearity response of this device is very good for a broadband class AB biased device. On average the gain linearity is + / −0.74 dB, with a peak deviation of + / −1.05 dB. From the average value vantage point, there is + / − 0.76 dB of gain linearity margin, however the peak gain linearity deviation at 400 MHz is + / −1.05 dB. This leaves + / −0.45 dB of gain linearity margin. In other words, the low-level driver gain and intermediate power amplifier stage gain linearity transfer functions will have to have substantially less gain linearity error if the aggregate response of the entire system (Figure 6.6) is to maintain the specification compliance value of + / −1.5 dB.
6.5 Hypothetical amplifier design example
a)
b)
Figure 6.25 (a, b) Input return loss, and small signal gain of the RFPA module.
275
276
Practical HF/VHF/UHF RF power amplifier realization
a)
b)
Figure 6.26 (a–e) Phase and gain linearity test results over 20 dB dynamic range to 150 W.
6.5 Hypothetical amplifier design example
c)
d)
Figure 6.26 (cont.)
277
278
Practical HF/VHF/UHF RF power amplifier realization
e)
Figure 6.26 (cont.)
The same is true with phase linearity; overall the average phase linearity error is + / −4.4◦ with a peak deviation of + / −7.9◦ at 400 MHz. This leaves + / −2.1◦ of allowable phase linearity error in the front two stages of the RFPA system. This is not leaving much room for these stages to have any non linearity present in their own transfer functions. A possible remedy is optimize the transfer function of the D1020UK at 400 MHz, or move to a higher frequency part that will have improved gain and phase linearity at 400 MHz. Figure 6.27 shows the efficiency of the amplifier from 20–400 MHz. The average efficiency is 56.8% with a worst case value of 42.9%. The device’s data sheet specifies a minimum efficiency of 50%, so between the gain/phase linearity and efficiency, we have a reasonably good indication that the output impedance of the device is well matched. Using the test setup of Figure 6.19, the output of the RFPA module is connected to a binary stepped transmission line, then into 50 high-power loads that are paralleled. First two loads are paralleled for a 2:1 VSWR. The binary stepped transmission line will switch in 50 coaxial cable lengths that will ultimately rotate the impedance in discrete steps about a constant 2:1 VSWR circle. While this is occurring, the RFPA’s frequency and output is incremented from 20–400 MHz and 0–150 W, respectively. The spectrum analyzer is monitoring the frequency spectrum to confirm that there are no
6.5 Hypothetical amplifier design example
279
D1020UK Drain Efficiency vs. Frequency @ Pout =150W CW 80 70
Drain Efficiency(%) ency(%)
60 50 40 30 20 10 0 20
115
210 Frequency (MHz)
305
400
Figure 6.27 Broadband drain efficiency of the 20–400 MHz RFPA module at 150 W CW.
spurious signals that rise above −45 dBc. This process is then repeated for a 3:1 load VSWR, then 4:1, and finally 5:1. The RFPA module did exhibit some spurious oscillations that were −60 dBc down below the carrier level. One might be lulled into a false sense of security that the Spectral load pull stability requirement is met as the spurious outputs that did appear are lower than −45 dBc. This may be the case, but to confirm this continuously over all frequencies, power levels, load impedances, potential modulation formats and temperatures represent countless hours of bench testing, even with automated load pull test setups. Any load pull stability test, no matter how comprehensive, will only be a cursory attempt at best. It may be fair to say the amplifier module has conditional stability within the limits and scope of the available test methods and conditions. Figure 6.28 shows the RFPA module undergoing six axis random vibration and temperature stress. As with other requirements, it is beneficial to evaluate random vibration on a modular level. Random vibration performance is similar to radiated emissions in that an RFPA that meets specification at a modular level will more than likely pass at a system level as the chassis that the module is integrated into will absorb a good portion of the random vibration energy imparted to it. The module was subjected to 15G rms of random, six-axis vibration. This was 50% over the required specification on a system level. RFPA circuitry, by virtue of its nature in terms of construction (i.e., chip capacitors, resistors) readily lend itself to be inherently immune to high levels of mechanical shock. The weak point in the RFPA circuitry is any component that protrudes well off of the PC board with some degree of mass to it. In this particular case, the ferrites loaded onto the transmission line transformers can sometimes impart enough force on the coaxial lines on which they are wound to generate enough torque that may either crack the solder joint
280
Practical HF/VHF/UHF RF power amplifier realization
Figure 6.28 RFPA module undergoing vibration and temperature qualification testing.
or delaminate the metallization of the PC board. Care must be taken to secure these and other devices with similar mechanical properties. While the thermal circuit is usually considered separate from the electrical network, it is every bit as important and has perhaps more direct impact on reliability than anything else. The section on RFPA module construction covered the details in preparing a proper thermal interface between the RF transistor and the module base. The next task is removal of the heat from the module of the entire system. While this is outside the scope of this material, the objective of whatever method of cooling is deployed is simple; the transistors die temperature must be kept as low as possible. Lower die temperature will not only increase MTBF, but lessen the amplifier’s vulnerability to failure from excessive overdrive and load VSWRs. Bear in mind, a 10 ◦ C reduction in die temperature may seem trivial, however, it can approximately halve the failure rate of the transistor. The plot in Figure 6.29 shows typical MTBF of RF power transistors versus die temperature and drain current. Both of these two quantities can be minimized with optimized thermal design, system architecture and output matching networks. Thermal design will cover mechanical interfaces, appropriate selection of chill plates, heat sinks and exchangers. If the heat generated by any given architecture yields excessive die temperatures, then adding modules may be an option to spread the heat out amongst more devices. In either of these cases, the output matching networks of the RF transistors must be optimized such that the efficiency is the best it can be.
6.5 Hypothetical amplifier design example
281
Mean Time To Failure
MTF, Mean Time To Failure (Hrs)
10000000
ID = 1 A
1000000
3A 100000
5A
10000
1000 120
140
160
180
200
220
TJ , Junction Temperature (°C)
Figure 6.29 Graph of a typical RF power transistor MTTF versus junction temperature and drain
current.
6.5.13
Beyond the test data The test data on the amplifier looks good and with some CAD based circuit optimization will probably yield better design margin. It is important to note at this time that the test data itself should be used for more than determining whether or not a particular module is meeting specification. Data in discrete form is no doubt useful, it defines the performance of a particular module, however, RFPA data in comparative trend format is far more powerful. It not only defines the performance of a particular module, but also highlights potential hidden process variations that may be in decline, not only in the manufacture of the RFPA, but also in the component suppliers. The HF/VHF/UHF RF power amplifier market has never seen demands for true commodity commercial volumes of millions of amplifiers. As such, attempts to try to apply statistical control processes such as Six Sigma can end in frustration. There are, however, facets of Six Sigma that lend themselves to lower volume production runs. Short term sigma level (or Zst ) scorecards look at amplifier test data in small lot quantities (say, for example, 25 systems). In this environment, amplifier performance of 25 systems can be statistically compared and areas where the amplifier is running close to specification or experiencing a transient period of either marginal or exceptionally good performance can be easily highlighted and brought to attention. This attention to test data trends along with root cause analysis will uncover both supplier and manufacturer process deviations and flaws.
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Practical HF/VHF/UHF RF power amplifier realization
Another useful process to consider primarily in the testing of RFPAs is gauge repeatability and reproducibility (gauge R&R). The underlying concept behind this is determining or quantifying the variability in a measurement system by measuring the performance of a particular RFPA several times to determine repeatability. Reproducibility is found by having several different RF technicians measuring the RFPA performance in order to quantify the variation in a measurement system resulting from operators. The net result of a gauge R&R study is that it will ultimately provide error tolerances that may require certain amplifier parameters to be more tightly specified in order to circumvent the possibility that even in the event of the presence of manufacturer measurement errors, the system still arrives at the customer within specification. While the above two topics relate to test data and test equipment, the following topics address what the module design should go through next. A manufacturing engineer should assess the module construction with a design for manufacturability (DFM) study to ensure that its construction is amenable to low-cost assembly processes such as semiautomated or fully automated assembly and acceptance test procedures (ATPs). Further along in the design process, quality engineers need to be involved to perform failure mode and effects analysis (to identify RFPA design and process problems before they occur). Wiebull analysis along with calculated and demonstrated MTBFs will provide insight into the expected lifetime of the newly minted RFPA design.
Summary/conclusions: current technology/future trends in amplifier design It has been said here that two things primarily occur in any RF power amplifier: r efficient amplification; r efficient or maximum power transfer. One must amplify a signal, transfer it to the next stage, then do it all over again. The devices responsible for amplification are obviously transistors. So if we wanted to know what may happen in the future, we can extrapolate what has occurred in the past. Twenty-five years ago, the class of RF transistors most common were BJTs. MOSFETS were starting to become commercially available. Since then, MOSFETs (whether vertical or lateral) have been the workhorses of HF/VHF/UHF RF power amplifiers. BJTs for now, appear to be in decline. In the 1985–90 timeframe, MOSFETS that could operate up to 175 MHz at power levels of 300–600 W became available. In the last year, 50 V LDMOS FETs have arrived that can deliver 1 KW up to 500 MHz. What was true then is still true now, namely operating such high-power devices presents the same challenges of heat removal and the AC coupling of high-power, high-current RF signals. GaN and GaAsFET devices continue to find themselves in amplifiers that are breaking barriers in ultra broad bandwidths. It is apparent that a continuing trend in RF power transistor technology can be expected with higher and higher power outputs and broader bandwidths found in smaller or equivalent sized packages. No one, however, has found a way to produce a device
References
283
that is distortion free or has significantly improved efficiency performance; all devices discussed have varying degrees of non linear transfer functions and inefficiencies. This is not to say a device of this nature will never arrive, only that in over a half century of transistor development, it simply has not. On the topic of matching and maximum power transfer, suffice it to say, if the computer industry progressed with the same speed, we would all still be using abacuses. A quick review on one of the earliest papers on transmission line transformers by Guanella [5] and Ruthroff [6] show that they remain virtually unchanged in construction and application since the 1940s. It is a testimony to what elegant and efficient devices they are, and also to how difficult they are to improve upon. So if we match transistors the same way and if they really are not more linear or much less efficient, then where are the improvements to come from? Based on advances in the cellular and plasma processing amplifier markets, improvement on raw amplifier performance has, can and will come in the form of advanced amplifier error correction techniques such as predistortion, feed-forward and high-speed, digitally based ALC loops. These advances evolve primarily from advances in higher speed analog to digital conversion, digital signal processing and error correction.
Dedication I would like to dedicate this chapter to my wife, Catherine Leigh, son Justin Daniel, and daughter Mikaela Sienna Myer.
Acknowledgments The author would like to acknowledge the contributions of Robert Schoepfer, Gregory Muller, and Thuy Lu.
References 1. D. Myer, “Synthesis of equal delay transmission line transformer networks,” Microw. J., vol. 35, no. 3, pp. 106–114, March 1992. 2. N. Dye and H. Granberg, Radio Frequency Transistors-Principles and Practical Applications, Butterworth-Heinemann, 1993, pp. 193–197. 3. R. K. Blocksome, “A binary stepped transmission line,” R.F. Des., July/August 1982, pp. 22–29. 4. N. Padfield, “Mounting guidelines for SEMELAB RF MOSFETs” Semelab PLC Application Note, pp. 1–9. 5. G. Guanella “New method of impedance matching in radio-frequency circuits,” Brown Boveri Rev., Sept. 1944, pp. 327–329. 6. C. L. Ruthroff, “Some broad-band transformers,” Proc. IRE, vol. 47, pp. 1337–1342, Aug. 1959.
7
Microwave hybrid amplifier realization Dominic FitzPatrick PoweRFul Microwave
7.1
Introduction The variety of approaches taken in the design of power amplifiers is vast and the subdividing of the approaches into various categories, such as “hybrid” is (like the term microwave itself) a generalization in which the edges are somewhat blurred. The Cambridge Advanced Dictionary defines hybrid as something “that has been produced from two different types . . . especially to get better characteristics, or anything that is a mixture of two very different things.” In this case the mixture is considered to be of lumped and distributed components. Until recently a hybrid amplifier was considered as one which used packaged devices, however in striving to achieve better performance at higher frequencies discrete devices and MMICs have been integrated into circuits containing both distributed circuits and discrete components, see Figure 7.1. Hybrid amplifiers have thus been created as an effort to “cherry pick” the best technical solutions within an economic framework. The place of hybrid amplifiers in the market ranges from the prototype and feasibility proving stages of product development, to volume manufacturing, to low-quantity highest performance products. Microwave hybrid power amplifiers (MHPAs) are used in low-volume applications such high-energy physics particle accelerators to volume applications in mobile phone base stations. Solid state powers amplifiers (SSPAs) have become the technology of choice for the mobile communications market and a significant proportion of the satellite communications market. The advent of wide bandgap materials has seen huge improvements in bandwidth performance below 6 GHz, and the next generation of commercial products will see these advances cover X band and beyond. Many electrical engineering students undertake an amplifier design project as part of their studies, while large engineering companies have found amplifier design groups expensive and difficult to manage (often leading to very successful “spin-out” companies!). Some managers have struggled to understand why the design and development of MHPAs is not as predictable a process as the design of other electronic system components. This chapter seeks to highlight some of the pitfalls that have so troubled some design programmes; it will also hopefully help designers in selecting the optimum approach to meeting customer requirements. Too often the term “black art” has been applied to what is in effect a process which is poorly controlled, and this starts right at the very basic level of the design . . . .
7.2 Printed circuit boards
285
Figure 7.1 Mixed technology microwave hybrid power amplifier. Photo courtesy of Cree Inc.
1–2.3 GHz SiC 50 W Amplifier, www.cree.com.
7.2
Printed circuit boards It might seem strange to start a chapter on MHPAs with a discussion on printed circuit boards (PCBs). However, as with house building, this is the foundation of our structure and a poor choice here will lead to the final design solution being compromised. Microwave PCBs are divided into two categories, hard and soft substrates. Hard substrates are primarily alumina, a ceramic with a tightly controlled dielectric constant (εr ≈ 9.8) although other materials such as glass and sapphire are used. Alumina substrates benefit from high thermal conductivity and high operating temperatures which has made them popular in military and space applications. The patterning of the conductive circuits is achieved either by deposition (thick film) or etching (thin film). Resistors can be integrated into the circuits by adjusting the metalization (such as using a nickelchromium layer). Grounding is an issue as the material is brittle and holes either need to be punched when the material is in its “green,” unbaked form or laser drilled. Similarly, the mounting or attachment of the substrate can cause problems due to poor thermal coefficient of expansion mismatch with some of the common metal housing materials, see Figure 7.2. New electrically conductive adhesives have been developed which allow a sufficient amount of “give” between the layers, however this is neither a cheap material nor is the dispensing and curing easy. Metal alloys with a closer thermal expansion have been developed as will be discussed later. Soft substrate is the term applied to a now vast range of products that are composite materials, either fibre or particle based. The all-pervading FR4 fibre glass material of the conventional electronics industry is inappropriate for MHPAs as the dielectric constant is poorly controlled and the dielectric losses high. At the other end of the spectrum is pure polytetrafluoroethylene (PTFE), a synthetic fluoropolymer which has a low dielectric constant, which can be tightly controlled, with low loss. However, it has poor thermal performance. By mixing PTFE with fibre based boards then low loss, controlled dielectric constant, and a reasonable thermal performance can be achieved. Additionally, profiling and drilling the boards is cheap and relatively simple. By adding ceramic particles the
Microwave hybrid amplifier realization
500 450 Silver Copper
400 Thermal Conductivity (W/m°C)
286
350 Gold
300 250
Aluminium
200 Tungsten
150
Molybdenum
100 50
Alumina
Solder (PbSn) Teflon
Kovar
0 0
GaAs
10
20
30 40 50 60 70 Thermal Coefficient of Expansion × 106/°C
80
90
100
Figure 7.2 Thermal properties of common microwave materials.
dielectric constant can be adjusted, even to the extent that they can be close to that of alumina, thus offering circuits of similar dimensions. A further advantage of these substrates is that they are easily laminated, so a wide range of thicknesses are available, and they can be provided with a range of metal backings. Processing is similar to that of conventional circuit boards except that with PTFE based materials an additional stage to “roughen up” the surfaces is necessary in order to successfully plate to the surface. As the demand for circuits for the mobile phone industry rose then so the number of PCB processors who could handle PTFE substrates increased and prices fell. The key parameters of substrates commonly used in hybrid amplifiers are shown in Table 7.1. Not included in the table is cost, this is because when considering the cost of a circuit substrate one should not only consider the purchase price of the raw material but also the processing costs. For example, a circuit on a low dielectric maybe three times larger than on a high dielectric. Furthermore, the finished PCB cost needs to be put into the context of the whole amplifier itself. What is the cost/W of output power? Knowing this figure of merit will aid the decision in choosing an output PCB; is it more cost effective to opt for an expensive low-loss board or a cheaper higher loss material? Non-PTFE materials have been developed so that standard PCB fabrication techniques can be employed. A side benefit of this development has been that the step change in dielectric constant, εr , at around room temperature has been removed. The typical change in εr due to the crystalline structure altering in a PTFE material can be seen in Figure 7.3. This change causes equally sharp changes in the equivalent electrical length of transmission lines. Some materials (such as ceramic loaded PTFE), while not displaying as significant an inflection point, have a much greater overall change in εr
287
7.2 Printed circuit boards
Table 7.1 Properties of common substrates used in MHPAs
Property Dielectric constant Thermal coefficient of dielectric constant Dielectric loss (tan ) Dielectric strength Volume resistivity Thermal conductivity Coefficient of thermal expansion Water absorption (ASTM-373) Type
Soft
Units
Hard Alumina1 99.6%
RT/duroid 5880
RT/duroid TMM10i
RT/duroid R4003C
ppm/◦ C
9.9 −
2.2 −125
9.8 −43
3.55 +40
0.0001 8.7 1014 26.6 8.2
%
0
0.0009 285 2 × 1013 0.20 X = 31 Y = 48 Z = 237 0.015
0.002
AC-kV/mm -cm W/m/K ppm/◦ C
2 × 108 0.76 X = 16 Y = 16 Z = 20 0.16
0.0027 31.2 1.7 × 1016 0.64 X = 11 Y = 14 Z = 46 0.06
Ceramic loaded thermoset plastic
Woven glass, ceramic filled thermoset
Substrates
Ceramic
PTFE/ microfibre
Er(T)Er(25)
Chart 1: RO4000 Series Materials Dielectric Constant vs. Temperature 1.008 1.006 1.004 1.002 1.000 0.998 0.996 0.994 0.992 0.990 0.988 –50
–30
–10
10
30
50
70
90
110
130
150
Temp°C RO4003
RO4350
PTFE/Woven Glass
Figure 7.3 Relative change in dielectric constant with temperature. Courtesy of Rogers Corp.
www.rogerscorp.com.
with temperature. Another advantage of thermoset materials is that they do not soften when heated and thus are more suitable for wire bonding applications. In the ideal world we would want the substrate to be a totally homogeneous material where the dielectric constant is isotropic, i.e., has a consistent value throughout. Due to the manufacturing processes and material compositions this does not happen and the 1
CoorsTek, ADS-996.
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Microwave hybrid amplifier realization
dielectric constant may even vary with orientation of board, thus if the circuit layout and the substrate orientation is not consistent between manufacturing runs there may be variations in performance. It is obviously essential that board manufacturers are aware of these differences and take account accordingly. The effects of these dielectric constant changes are most dramatic in high “Q” elements such as resonators. Thus, isotropy of the substrate material is an important consideration in the design of narrow-band amplifiers. It can also affect wide-band designs where coupling structures are produced on the PCB, such as Lange couplers [1]. Generally speaking, the finer and more randomly placed the loading materials in substrate the lower will be the variation in dielectric constant, thus woven glass based materials tend to exhibit the highest anisotropy. Very consistent dielectric materials such as pure PTFE can be used; however these have their own problems. The thermal conductivity of the PCB is important in medium power amplifiers where surface mount devices are used, although even in these cases the majority of the heat generated is conducted to the heatsink through the grounding vias. In high-power amplifiers the power devices are bolted through the PCB to the housing floor or directly to a heatsink. The amount of power dissipated in the circuit structures themselves should not be underestimated. If a power device delivers 100 W and the output circuit following it has 0.5 dB of loss this means that 11 W is dissipated in the PCB (assuming the majority of the loss is not radiated). There are two main methods of loss in the PCB, resistive loss in the metal conductors and dielectric loss in the substrate. The conductor loss is determined by the properties and dimensions of the metal used while the substrate loss is dependant not only on the loss of the material itself (quantified by tan δ) but by the percentage of the electric fields flowing through the substrate. These two have a tendency to work against each other; to get the lowest substrate loss one would look to use as thin a substrate as possible and narrower lines, while for minimizing conductor loss one needs wider lines. The thickness of a transmission line, particularly in MHPAs, is affected by two considerations, the DC current and the frequency of operation. For DC currents the cross-sectional area of the transmission line is inversely proportional to the resistance, i.e., double the cross-sectional area, halve the resistance. At microwave frequencies however, the currents are flowing only in a limited proportion of the thickness, the extent of which is referred to as the “skin depth.” This term leads to a common misconception, the current flows in the electrical surface closest to the ground plane (the electrical fields are between the surface of the ground plane and the underside of the transmission line), thus plating up or changing the metalization of the top surface conductor may make no difference. The formula for skin depth, δ, (in metres) is: δ=
2ρ 2π f μo μr
(7.1)
where ρ is the bulk resistivity of the conductor (-cm); f is the frequency (Hz); μo is the permeability constant (H/m) = 4π × 10−7 , and μr is the relative permeability.
7.2 Printed circuit boards
289
Table 7.2 Bulk resistivity of commonly used metals Material
Aluminum Copper Chromium Gold Nickel Palladium Silver
Bulk Resistivity 2.65 (μ-cm)
1.67
18.0
2.30 8.71
10.8
1.59
Table 7.2 lists the bulk resistivities of some common materials. For example, at 5 GHz the skin depth in a copper conductor will be 0.92 μm, while a 1/2 oz. copper plated PCB has a copper thickness of 18 μm. A common rule of thumb is that the copper PCB trace should be at least 5δ to minimize loss. Also note that the purpose of gold plating or flashing on microwave PCBs is to passivate the surface or improve the contact of bonding areas, not to reduce the RF resistivity. As the RF current flow is primarily on the underside of the track the surface roughness of the substrate will impact the loss. The most common conductor material is copper. There are two standard approaches to attaching the copper to the substrate material. The lowest cost and hence most common method is electrodeposited or ED copper. The alternative is rolled copper, where thin sheets of copper are bonded to the substrate material. Rolled copper has lower insertion loss due to the uniformity of the material and the reduced surface roughness; this is particularly noticeable as frequency increases. However, ED has a better adhesion to the substrate, i.e., higher peel strength. Traditionally, both types are specified in ounces, this comes from the number of ounces of copper per square foot of board area, (1 oz. ≈ 0.0355 mm). Copper cannot be left bare and so it is common practice to either plate or coat the copper. Such treatments range from “flashing” with a nonreactive metal such as gold (typically 5 μm), to hot air solder leveling (HASL), and conductive polymers. When selecting the substrate material the most significant consideration is the impedance range that can be realized. The general rule of microwave design, “Watch out when dimensions approach a significant fraction of a wavelength” applies here. If the substrate thickness is too large then instead of the electromagnetic (EM) fields forming in the quasi-TEM mode, other modes propagate. A good rule of thumb is that the thickness of the substrate should not exceed 20◦ phase length at the highest operating frequency. Table 7.3 summarizes the impedances, circuit dimensions, and current limitations for a range of substrate materials. Other considerations in the selection of the dielectric and its thickness are the current capacity required (usually limited by DC bias currents), and the size of discrete components, such as device tabs. In linear design software models there are limitations on the ratio of track width to substrate thickness, which usually restrict the minimum impedance to ∼25 . Therefore it may be necessary to use an EM analysis for parts of the circuit where wide lines are unavoidable. When deciding whether a hard substrate is the optimum solution it is important to consider the surface area of the circuit. Generally, hard substrates are limited to a maximum size of 50 × 50 mm. Hence, a circuit may need to be made from a number of ceramic “tiles.” Conversely, antennas have been made on soft substrates over 1 meter long. Typically, however, blank soft substrates sizes range from 250 × 250 mm to 800 × 600 mm.
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Microwave hybrid amplifier realization
Table 7.3 Typical substrate trace dimensions with approximate current rating
Substrate
εr
Thickness (mm)
50 width (mm)
Alumina (Thin-film) (Thick-film) CuClad 217LX RO4350B TMMi 10
9.8
0.635
0.61
λ/4 (90◦ ) @ 10 GHz (mm) 2.87
2.17
0.787
2.40
5.46
3.66 9.8
0.508 0.508
1.09 0.48
4.41 2.90
Current for a 30 ◦ C temp. rise2 (A) 12 12 5 3.8 2.3
Figure 7.4 Impact of processing on track dimensions and edge coupling (slopes exaggerated).
In the design of microwave circuits it is easy to assume that the circuit dimensions produced by the CAD software are those that will be fabricated; however it is essential to understand the processing that will be involved in manufacturing the PCBs and to take into account the impacts. For example, where the production process involves etching away the unwanted copper the actual shape of the cross-section of the track is trapezoidal, and the size of the etch angle is proportional to the thickness of the track, see Figure 7.4. There are two main PCB conductor creation approaches, (a) subtractive, and (b) additive. In the subtractive process the etch angle results in the track width being wider at the bottom (remember that this is what determines the RF impedance), while in the additive process the track is plated up from a thin layer and thus is wider at the top. Also worthy of note is that the edge coupling between the adjacent tracks (and ground planes) is 2
Approximate as this depends on a number of factors including peripheral circuit features, trace termination, backing material and fixing method (see later).
7.2 Printed circuit boards
291
assumed in most simulator models to be between vertical walls (or whatever the etching process was of the sample from which the models were derived). A further complication is that some PCB manufacturers take into account the etch factor of their process, while others don’t, hence the designer must know whether or not to take this into account when creating the mask. Grounding is an important part of microwave circuit designs. Typically, the ground plane is a continuous conductor on the reverse side of the substrate, so it is necessary to connect to it. The standard approach is to drill the substrate material and then plate the hole with a conductor (plated through hole – PTH) to create a via. With many RF substrate materials this has its own problems. PTFE materials are difficult to bond to and hence the surface of the hole must be roughened to promote adhesion of the copper during the plating process, and this is particularly difficult to achieve in through-holes. Also, due to the differing thermal coefficients of expansion between the conductor and the substrate, cracking around the top of the via can result, particularly where the PCB undergoes significant temperature cycling. These factors therefore push the designer to use larger holes and thicker plating. Rather than using via holes, slots may be cut in the board and their edges plated, but this may be a nonstandard approach for some PCB manufacturers, who would normally do slot cutting after plating and should therefore be highlighted in the requirement drawings. Inserting pins through boards is acceptable for simple prototype circuits, but the result is generally not flush with the substrate surfaces and thus may necessitate profiling of the box floor or restrict the placement of components. Substrates can be supplied metalized on the back side which makes it possible to directly solder the substrate to the metal; however this will require using background heating. When using aluminum backing it is necessary to plate the aluminum first (not a trivial process), hence copper or brass backing are preferred. Electrically conductive adhesives are also available and can be used to bond the metal and substrate together. For large bonding areas the adhesive can be supplied in films which may be more convenient. The use of metal backed substrates is popular for a number of reasons: r r r r r
it provides good heat sinking; edge mounted connectors can be directly attached; good mechanical base for mounting large components; shrinkage and warping of the PCB is reduced; easier attachment to housings.
However, weight, substrate, and processing costs are increased. Metal backed materials are particularly popular for test jigs and prototypes where the expense of a custom housing can be avoided and weight is not a significant issue. Mounting PCBs within housings or directly to heat sinks can be done simply using screws to clamp the board in place. However, care should be taken to ensure that the contact between the board and the backing material is consistent by the use of appropriate screw head size and quantity dependent upon the “stiffness” of the substrate. Areas where particular care should be taken are around the input and output connections and where pockets are machined out for the devices. Gaps between the ground plane on the back of the substrate and the box floor may produce resonant cavities which will alter the response
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Microwave hybrid amplifier realization
of the amplifier. They can also provide feedback paths leading to oscillations. Screws should have metal lands under them, especially with PTFE boards as under compression the PTFE has a tendency to “creep” away from under the screw. It is advisable to use cap heads to avoid damage from screwdrivers slipping, especially where there are fine tracks, or delicate air-wound inductors. Crinkle or spring washers are usually adequate to lock the screws. The standard size is sometimes larger than the screw head, so where space is at a premium the next size down or an imperial size will fit the body of the screw and not protrude far beyond the screw head. Direct screw clamping is not recommended for hard substrate materials such as alumina due to the brittleness of the material. Most commonly the substrate is soldered or epoxied directly onto a metal carrier which in turn is screwed into the housing. Alternatively, spring clips can be used to hold the tiles in place. Modern epoxies have proved increasingly popular in mounting both substrates and active devices. The type of epoxy used must be considered carefully, some can crack under thermal stress. For such applications thermo-plastic adhesives which have some “give” are a better solution. Conventional PCBs may also be soldered directly into housings. This gives excellent thermal and electrical conductivity with the added advantage that no board “real estate” is taken up by the mounting screws. In order to get an even solder join, solder paste is screen printed onto the underside of the PCB or a preform used. Pressure needs to be applied across the PCB during reflow to prevent areas from lifting and, if not constrained by walls, to keep the PCB correctly aligned. Attention must be paid to the temperature distribution across the unit as all parts of the solder joint must reach the reflow point, but without going so high as to damage the substrate, housing plating or degrade the solder. A low-flux solder should be used, particularly when large boards are involved, otherwise pockets of flux may form under the board. Some solder pastes may require a drying period after application to the PCB to allow solvents to dissipate. An alternative configuration to microstrip is to use coplanar waveguide (CPW). In this construction method the ground plane is brought to the top surface, this produces a circuit with very tightly contained fields which is therefore less susceptible to proximity effects such as lids and to radiative coupling. Although popular for low-power devices it has draw backs for MHPAs, due to the need to heatsink devices. With flange mounted devices there is a discontinuity in the odd and even modes at the device package junction, and for surface mount there needs to be a ground plane connected to with vias. Typically the substrate requires a large number of vias to ensure ground continuity, hence losing one of the advantages of CPW. Another major drawback is that tuning of line impedances in CPW is very difficult compared with microstrip. It is often necessary to have slots in the PCB material for flange mounted components. Rather than being directly attached to the PCB these are bolted to the housing floor with leads soldered to the substrate tracks. For microwave devices the alignment of the PCB and housing is critical so that gaps are minimal as they can cause unwanted impedance changes and resonances, as shown in Figure 7.5. As the same requirements are imposed on the input and output connector launches the dimensional tolerances on the housing and PCB can be extremely tight. One solution, particularly suitable to PCBs soldered into housings or test fixtures, is to machine the slots into the PCB and housing simultaneously. This ensures precise alignment between the two. Unfortunately, this
293
7.3 Housing
RF Link
W, width of microstrip
L
W
Substrate H
Metal Backing
X
Housing Z
Z
H
S s Z = 377 × — w X = Z tan
2πH λ
L = Inductance of RF Link (e.g. bondwire or device tab) Note: H is in metres
Figure 7.5 Ground path effects.
option is not possible with hard substrates, and with soft substrates held in place a much higher degree of clamping is required, and care must be taken to ensure “swarf ” is not forced into the gaps between board and ground plane. A final consideration with soft substrates is their moisture absorption. During processing and cleaning, PCBs are subjected to a large number of chemicals. These can cause a variety of problems, from producing corrosive liquids to changing the electrical properties of the substrate. For instance, the dielectric constant can alter and if the circuit is tuned to compensate for this, then over time as the substrate “dries out” the εr will change and hence, the circuit performance changes. Thorough cleaning followed by a baking out stage is necessary.
7.3
Housing Other than for prototypes and test jigs MHPAs require housing. Although this may at first seem trivial, before considering the construction of a suitable housing the requirements should be considered. r interference: to stop the signals in the amplifier interfering with and being interfered by external signals, circuits and materials; r protection: to prevent the circuits being harmed by mechanical or chemical action; r heat sinking: the heat generated by the power components needs to be removed in a controlled manner. The housing can either incorporate or provide the connection to the method of heat removal; r mounting and connecting: the amplifier does not exist in isolation; it requires signal connections, supply connections and a method of fixing to its surroundings. The role of the housing is to ensure that these are reliable and convenient.
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Microwave hybrid amplifier realization
The relative importance of each of these must be balanced against the other considerations of cost and weight. The same approach would not be taken in a safety-critical application in a harsh environmental to a laboratory test amplifier. As in all elements of design, the end solution is a compromise between conflicting needs.
7.3.1
Materials The most common material for MHPA housings is aluminum. It is relatively cheap, easily machined, strong and light weight. It has good electrical and thermal conductivity and so is excellent for screening and heat sinking. The main drawback is that it cannot be directly soldered to. This can be overcome through plating, but this is a multistage process with typically first a nickel seed layer followed by the gold or tin plating. It is rare that the aluminum is left untreated as although the oxide layer that forms on the surface is fairly un-reactive, there is a danger that small residues of acidic solutions will be left behind from the flux used in many solders. These can react with the aluminum oxide to form salts which can cause dendrites to grow leading to short circuits. A lowcost aluminum surface treatment is chromate conversion, commonly known by the brand names Iridite or Alodine. Some forms of this process are banned under the Restriction of Hazardous Substances (RoHS) legislations as they contain toxic hexavalent chromium. Care should also be taken as the electrical conductivity can be inconsistent and dependent upon thickness. The coating cannot be soldered to. For high-performance hermetically sealed systems Kovar is used as an alternative to aluminum as will be discussed later. Kovar’s thermal coefficient of expansion (TCE) is closer to that of GaAs, see Figure 7.2; however, it is three times denser and its thermal conductivity is considerably lower than aluminum which is an obvious drawback for MHPAs. Aluminum alloy 6061 is preferred due to its good mechanical properties and machinability. Where the lid is to be welded to the unit (rather than clamped) then aluminum alloy 4047 is preferred. This contains silicon which improves the ductility of the weld and reduces cracking.
7.3.2
Sealing and hermeticity Very few things are as likely to illicit impassioned debate amongst MHPA design engineers as the issue of the appropriate level of sealing. When one looks into the area in depth, one can easily be lead to despair that there is nothing that can be done to prevent moisture ingress. However, we should take heart from the fact that systems continue to operate for many years, and in fact the ruggedness and survivability of some relatively cheap products such as mobile phones, satellite low-noise down-converters (LNBs), and GPS receivers is impressive. The aim should be to provide reliability commensurate with the cost of the unit (including cost of replacement). In fact many military systems providers are now looking at availability of parts rather than requirements to survive storage of 20 years in harsh conditions. Protection of amplifier circuits is required not only from mechanical damage but also from corrosion and vapour ingress. In the fabrication of amplifiers there are a large number of chemicals used, from the lubricant used during machining of the housing, to
7.3 Housing
295
those used in the PCB processing and housing plating, to the fluxes in solders. These, especially in the presence of water, can form particularly corrosive solutions. Condensation can cause short circuits or changes to performance in RF applications by changing the electric fields around transmission lines. Avionic systems have proved particularly vulnerable to condensation, where equipment can be sitting in warm moist air, and within only a few minutes be at high altitude and low temperatures. The temperature at which condensation forms is called the Dew Point and varies with the humidity of the air; as the air temperature increases so does its ability to “hold” water. The extent of the protection required is dependent upon the expected lifetime of the product, temperature range (higher temperatures increase chemical activity – hence storage temperature is a key factor), and sensitivity of the circuits to corrosion, which in turn depends upon the materials used and how the active circuits are packaged. Standards were established for military systems covering many areas of the design and testing of electrical systems. MIL-M-38510, the general specification for microcircuits, required that all hybrid microcircuits that contain active semiconductors should be hermetically sealed. The MIL standards are no longer supported, mainly because they could not keep pace with the speed of component and process developments, but many of their requirements have been assumed into requirement specifications. Recent work [2] has shown that hermetic sealing to MIL-STD 883 may not be adequate and that modern plastic packaging can provide better reliability. A big fear in the early days, particularly of GaAs circuits, was “hydrogen poisoning” and so hydrogen “getters” were incorporated into circuit packages. Improved passivation of the active devices has resulted in the virtual elimination of this issue. A complete seal against moisture ingress is difficult if not impossible to achieve. Welding, brazing, or soldering all of the joints can produce an adequate seal; however there is the need to provide RF and DC interfaces and access to the unit for repair and maintenance. Moisture can ingress into a housing in three ways: r diffusion; r capillary action; r breathing. Diffusion: water vapour will diffuse in if the partial pressure differential is inwards even if there is an absolute pressure differential in the opposite direction. Hence, a condition can exist where a filler gas in the housing (such as nitrogen) can be diffusing outwards while the water vapour is diffusing inwards. It is often not realized that water vapour molecules are smaller than the other main gases in the atmosphere – oxygen and nitrogen. Water vapour (H2 O) has a molecular weight of 18 as compared to nitrogen (N2 ), 28 and oxygen (O2 ), 32. Thus, the water vapour seal is the hardest to achieve. The measure of diffusion is moisture vapour transmission rate (MVTR) and is dependent upon the relative concentrations on either side of the barrier. Table 7.4 shows the MVTR values for different composition rubber o-ring seals tested under identical conditions. No material provides a 100% seal, the relative gas permittivity of various materials is given in Table 7.5 [3], however the real question should be, when does a leak become critical, which comes back to the intended life and operating and storage conditions.
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Microwave hybrid amplifier realization
Table 7.4 Relative rubber o-ring sealing performance
O-ring material
MVTR (g m−1 day−1 )
Fluorocarbon Nitrile Silicone Polyurethane
9.5 × 10−4 40 × 10−4 90 × 10−4 130 × 10−4
Table 7.5 Relative gas permittivity for various materials
Nylon
Silicones
Epoxies
LCPs
Glasses/ ceramics
Metals
1
10−2
10−4
10−6
10−8
10−10
Capillary action: water may form on the outside of the unit from direct exposure or condensation, depending upon the environment. The rate at which the water permeates the unit will depend upon the nature of the material in which any hole or crack exists. Obvious risk areas are along the lid edge and any screw holes that break through into the chamber. Breathing: for unsealed units the majority of the water ingress will be through breathing. As the pressure changes between the inside and outside of the unit there will be a movement of air. Thus, moisture will be contained within the unit. A degree of protection to components and tracks can be offered by conformal coatings, however these can affect the RF impedance of circuits, there is also the problem of when to apply them. Application before tuning may mean that the coating integrity will be breached if it is necessary to change components during tuning and test, however adding the coating afterwards runs the risk of altering the circuit performance in an uncontrolled manner. Also, although a conformal coating protects from short circuits, condensation above the protective layer can still detune the matching circuits. The ultimate solution is to hermetically seal the amplifier. The argument against hermetically sealing is that if harmful chemicals build up over time then by allowing the unit to “breathe” the concentration is reduced, whereas in a sealed chamber it may reach harmful levels and cause corrosion. The main problem is due to water moisture, thus not only is it necessary to seal the amplifier but also to reduce the moisture content within the unit (obviously cleaning so as to remove as much of the contaminants as possible is essential), therefore air is driven out before sealing and replaced with an inert gas such as nitrogen. The decision to hermetically seal should not be taken lightly as this requires special components such as the RF and DC connectors as well as the lid seal itself, and with each one there is not only a high-integrity seal to produce but another potential failure point. Of course if it is decided that the unit requires to be sealed then an additional test stage needs to be incorporated to prove the integrity of the seal.
7.3 Housing
297
Studies have shown [2] that the required level of hermetic sealing for high reliability is 5 × 10−11 mbar l/s. However, standard leak testers struggle to meet these levels so often specifications have actually been set lower at about 10−8 mbar l/s. Hermetic joints must be metal; epoxies and gaskets do not offer sufficient sealing, hence solder or welded joints are used. The standard approach to hermetic sealing is for the lid of the housing to be laser welded or soldered to the walls. Specialist advice should be sought for laser sealing as to the dimensions of the lid and housing as these are critical to producing a good seal and related to the laser power. Of course this process must be carried out after tuning and testing, and if there is a subsequent failure then the lid must be machined off to allow for repair/retuning. For RF and DC connections, hermetic feed-throughs are usually made from a Kovar (an iron nickel cobalt alloy) outer ring and center pin with a glass body. The TCE of Kovar is close to that of glass and the Kovar can be plated so that it can then be soldered in place. For RF connections the ratio of the diameter of the center pin to the outer barrel must be such as to present a 50 impedance. It is obvious from the reliability of modern electrical components such as mobile phones and LNBs that it is not necessary to provide a hermetic seal to achieve reasonable reliability. Improvements have been made in the passivation layers on the surface of active semiconductors and in the construction of the device packages themselves. However, system specifications tend to be conservative and a degree of environmental screening is often required. An alternative approach, where full hermetic sealing is not required, but where protection from harsh environments is necessary, is to use a compression gasket around the lid. Sometimes environmental and electrical screening cannot be achieved to the degree required in a single gasket so two separate ones used. There is a large variety of gaskets including solid and hollow tubes to flat custom forms. They can be complete rings, spooled line or moulded in place. The benefits of this approach are that the unit can be opened at any time making tuning and repair simpler (especially important in power amplifiers!), also no specialist equipment such as a welding system is required. Some of the key considerations are shown in Figure 7.6. To ensure that the correct amount of compression occurs the dimensions of the trough are critical. Typically, the gasket is compressed 25–30% hence the dimension d in Figure 7.6b should be such that this is achieved, similarly w should be determined such at that at the correct compression the gasket is not restricted horizontally. Where the gasket is not recessed (e.g., flat gaskets) it is advisable to include protrusions in the machined face which ensure the correct amount of compression is achieved, but not overdone. A disadvantage of the gasket sealing approach is that the wall width required to fit the gasket and fixing screw is greater than without, which can lead to space issues. With appropriate cutting tools the material under the gasket can be removed as shown in Figure 7.6d, however this results in more difficult assembly, hence it may not be an option for volume applications. The lowest cost form of the gasket material is provided on a spool and can be laid in the recess, which can include intricate routing. Fixing screws need to always be outside of the sealing ring, or where this is not possible (for example, in center posts) include their own gaskets. When joining up the ends of the gasket it is better that the two ends overlap rather than form a butt joint as shown in Figure 7.6e
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Microwave hybrid amplifier realization
Lid d w Housing Wall
Conductive Gasket
(a) Before compression.
(b) After compression.
Fixing hole separation
(c) Housing gasket detail and mounting screws.
(d) Under cutting the gasket recess.
(e) Joining Gasket ends, butt join (left) and angled join (right) -preferred.
Figure 7.6 Housing sealing using compression gaskets.
and manufacturers can supply suitable adhesives to join the ends. An example of this type of seal can be seen in Figure 7.7. Although not a MHPA, this is an example of a hybrid microwave assembly that is mounted externally and subject to a north European climate and must be highly reliable. The housing is made from cast aluminum with a chromate passivation. The RF circuits are electrically sealed by an internal lid which includes compartments. The environmental seal is provided by a compression gasket and a layer of silicon rubber. RF screening is provided by an interference fit between the internal lid and PCB. The unit is designed to be mounted at an angle so that if there is any condensation within the unit it will drain to the lower right hand corner away from the active circuits.
7.3 Housing
299
Figure 7.7 Gasket sealed satellite down converter (LNB), manufactured by Grundig Ltd.
[1] Pinned through board connection, [2] waveguide to microstrip interface, [3] Die cast main housing with gasket recess, [4] Foam RAM for mode suppression, [5] internal lid with cavity walls and connecting “mouse-holes.”
One consideration specific to MHPAs is that the unwanted by-product which we seek to minimize – heat – actually works to our advantage. Although the danger of short circuits exists at switch on, especially after storage in cold conditions, the operating temperature of most MHPAs will keep the air in the unit above the dew point and so condensation is less likely.
7.3.3
Construction The construction of MHPAs can vary from the simple to the very intricate. The basic model is a cavity into which the RF and DC circuits are all fitted, as shown in Figure 7.8. For larger amplifiers it is often preferred to separate the DC circuits into another chamber. This may be so that bias adjustment can be carried out with the lid in place for the RF unit, for electrical isolation, for testing and monitoring, or because the sealing method of the DC components is different to that of the RF. It can also reduce the lengths of feed connections which are areas of danger for interference and oscillation. The variety
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Microwave hybrid amplifier realization
Figure 7.8 Simple construction, wideband hybrid amplifier module, before and after lid sealing and painting. Courtesy of Labtech Microwave Ltd. www.labtech.ltd.uk.
of configurations for amplifier modules is enormous; Figure 7.9 describes some of the more common approaches. a. “H” section: this is simple to construct and has the benefit that the RF and DC cavities can be sealed independently. The feed locations of DC and monitoring points to the RF PCB can be positioned where needed, with complicated routing being kept in the DC compartment. The drawback with regard to MHPAs is that the heat sinking for power devices is poor. Floor thickness can be increased under the power devices; however this still gives a higher thermal resistance due to the thermal path length than other options. b. Orthogonal Cavities: Similar benefits to the “H” section, but with longer wire links to the RF PCB. The depth of the cavity of the RF section is related to the minimum height of the DC PCB, which could cause issues with box modes. It does offer the ability to have the power devices mounted on a face which can be attached onto a heat sink or cold wall. c. “Wrap around”: a good solution where there are power components in the DC section that also require heat sinking. The long RF section would typically be split into a number of chambers using internal dividing walls as shown in Figure 7.10.
7.3 Housing
301
RF PCB DC PCB Feed through
(a)
Coaxial Connector
(b)
Link cable
(c)
(d)
Lid
Heatsink/Base (e) Figure 7.9 Typical amplifier housing formats: (a) cross-section of “H” section module;
(b) cross-section of orthogonal cavity module; (c) “wrap-around” module; (d) split section module; (e) planar module.
d. Split section: this format, although requiring additional RF connectors and a cable, has the benefit of giving interstage access which can be useful in tuning and fault finding. e. Planar: one of the problems with the previous module formats is that the circuits are within cavities and this can cause production issues with assembly and test due to
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Microwave hybrid amplifier realization
Figure 7.10 (a) X band and (b) S Band MHPA modules: (a) wrap-around construction showing bias control with RF chambers around the perimeter. Note the weight reduction removal of excess material where possible; (b) side-by-side construction. Photos courtesy of Surrey Satellite Technology Ltd. www.sstl.co.uk.
access. A solution to this problem has been to incorporate the sidewalls into the lid. The RF and DC circuits may then be incorporated into a single PCB. The circuit design must have a low susceptibility to ground proximity effects; otherwise the fitting of the lid will detune the performance. The construction allows power devices to be mounted directly to the heatsink thus maximizing thermal transfer. Another
7.3 Housing
303
Figure 7.11 Handling internal corners.
issue with this design is that the RF connections need to come vertically through the board which can give rise to difficulty linking to them and launching unwanted modes (see later). It is possible to mount connections in line with the PCB; however the junction with the lid requires close attention. The housings themselves may be formed by three main methods: direct machining, casting, and piece parts. Improvements to the performance and speed of computer numerically controlled (CNC) machining centers has dramatically reduced the cost and increased the possible intricacy of housings. Designs should be discussed with the machinist before finalizing, as there are a number of simple aspects that will reduce cost and improve manufacturability. These include: 1. Use as large a cutter as possible for the internal cavities, where possible avoid tight corners. If necessary a corner can be opened up using a drill hole, see Figure 7.11. 2. Holes that require tapping are best drilled through to stop taps from jamming. Use as large a hole and thread size as possible. The minimum tap depth is 1.5 × diameter of the fixing. Blind holes can be a store for the chemicals and substances used in processing; it is much easier to completely clean through holes3 . 3. Reduce as far as possible the number of cutting axes required, this will speed up machining and reduce cost. 4. Countersinking holes is an additional operation, only countersink where necessary. 5. Minimize the number of different cutters and drills required. Making amplifier housings from cast parts is limited to volume requirements, and for MHPAs the parts will still require some machining to produce the necessary surface finishes for mounting power devices. Complex shapes can be created and this has lead to this being a popular option for base station amplifiers. 3
This caused a problem with flange mounted transistors failing over time. Removing the blown devices revealed a very thin layer of sticky ‘goo’ under the devices. Assembly technicians were reminded of the need for scrupulous cleaning under the devices and an inspection stage was introduced prior to device fitting. Still the transistors failed. Eventually, running a cotton bud down the transistor mounting holes revealed the source of the ‘goo.” As the devices were being clamped down, dissolved flux was forced up the holes and spread under the device flange, increasing the thermal resistance. In this case the RF PCBs were soldered into the box and then cleaned in an ultrasonic surfactant cleaner, leaving residue in the blind holes.
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Microwave hybrid amplifier realization
The third option of using piece parts covers a number of different applications ranging from low-cost custom assemblies to high-cost light weight units for the avionics industry. In the first case simple box extrusions are used for the side walls which can be bolted to heatsinks or lids. The second case utilizes a process called aluminum dip brazing. This can produce assemblies with very thin walls (40 GHz. A modification of this is to create a taper transition from coplanar to microstrip. A drawback of this approach is that the PCB needs to be mounted under the connector. It is sometimes required to mount the connector through the substrate material as shown in Figure 7.14c. PCB mount connectors are becoming increasingly popular; however care must again be taken to avoid moding. Many conventional PCB connectors have integral posts at the four corners of the flange which are intended to be soldered through the PCB. As well as providing a mechanical connection these can also help to reduce moding at the right-angle connection. As the operating frequency increases four posts are not sufficient and additional vias are required. These grounds can be posts, plated vias, or mounting screws. Direct solder attachment of the center pin to the PCB track is the standard approach with soft substrates as the “give” in the substrate material provides thermal and mechanical stress relief. Mechanical pressure is put on the pin during the mating cycle. For hard
7.4 Components
315
substrates there is little compliance so a direct solder attachment is not recommended. There are a number of variations on the wire bond link shown in Figure 7.14d, including having the center pin flattened at the end and the wire bond at right angles to the pin (which is slightly offset from the track). A very successful solution is shown in Figure 7.14e where a sliding contact fits over the center pin. This contact can itself be soldered directly to the PCB track.
7.4
Components The components used in hybrid microwave amplifiers can be divided into active and passive. MHPAs take advantage of the compact space that a lumped element component can provide or the tailored frequency performance of a distributed component. Advances in processing have produced low-temperature co-fired ceramic (LTCC) discrete packaged devices, which may contain a mixture of discrete and distributed components in what appears to be a single element, thus there is even a blurring of the categorization between lumped and distributed. A conflict exists between accepted practice in the general electronics engineering industry and what “tricks” you can play to improve RF performance. For example, mounting a surface mount chip resistor on its side can shift a package resonance up in frequency – out of the wanted band – but will give production engineers with automated assembly lines high blood pressure! Chip components have recommended pad sizes for solder connections. These pads will have an associated capacitance which the designer may want to minimize. Hence, a compromise needs to be reached between the RF performance and the production requirements. In the end, the component must meet its RF performance requirements while still being manufacturable.
7.4.1
Passive – lumped components Amplifiers require capacitors, resistors and inductors for their operation. In microwave design such elements do not behave as a pure element. By knowing the properties of the element, these can be incorporated into the circuit design and used for our advantage. For example, a feedback network may comprise of a resistor, a capacitor and an inductor. The capacitor (C), and resistor (R), will have parasitic inductance. By choosing the appropriate physical size and shape for the capacitor and resistor they can either reduce the inductance needed or encompass it entirely within the two elements. Modeling the Rs, Ls, and Cs can be done either using a physically based model or by using experimentally measured S-parameters. Many component suppliers now produce libraries of data on their components which can be readily used in simulators. Users should approach these with caution, particularly as frequency increases. Ideally, the surroundings should have been entirely de-embedded so that the model exists independent of its environment. It is important to verify the models used in the environment in which the components are intended. It is also useful to understand the construction of the components so that there may be some expectation of the behavior with frequency.
316
Microwave hybrid amplifier realization
Resistors These have a wide variety of uses in amplifier circuits, e.g., low-frequency biasing, loads, attenuators and feedback elements, and signal balancing in combiners. In microwave applications resistors are mainly made from metal films, the metal being chosen for its resistance properties rather than its conductivity as in PCB tracks. The majority of resistors used are based upon a surface mount chip, however there are times (particularly below 3 GHz) when the inductance associated with a leaded resistor can be of benefit. Leaded resistors for such applications should be metal film as carbon composition or wire wound resistors generally contain many parasitic elements and thus have widely varying impedance characteristics. The inductance of the lead lengths associated with the resistor is calculated from: 4l Inductance in nH = 0.2 × l 2.3 × log − 0.75 , (7.6) d where l is the lead length and d is the diameter (in mm). Chip resistors basically consist of a ceramic tile onto which has been deposited a metal film (thin film) or paste (thick film). The paste is fired at high temperatures and then the resistance can be trimmed to the necessary value. The continued miniaturization of electronics has been beneficial to the microwave industry as the smaller the component then the lower the parasitics and hence the closer the performance is to that of the “pure” element. With size reduction comes lower power handling. The exact power handling ability is dependent on a large number of factors and has been excellently documented in other work [7]. As discussed in Section 7.2, at high frequencies the current is not evenly distributed through the conducting material, thus the quality of the conducting surface is of paramount importance, and this tends not to be well controlled in thick film products due to the nature of the paste. The key aspect of thick film is that it is low cost. Thin-film resistors are more expensive to manufacture. A thin resistive layer, typically of nickel/chromium (nichrome) or tantalum nitride is deposited on the ceramic and then conductive terminations are deposited at either end. Sheet resistances vary between 5 and 250 /sq which are very suitable for the typical resistances required in amplifier circuits. It is important to check how the resistance values are trimmed, see Figure 7.15a, as sometimes a path is cut in the conductor which can have intrinsic capacitive and inductive effects. The end terminations on standard resistors tend to be “wrap-around” as the topside is also often printed with the resistive material. Better RF behavior may be achieved by mounting the resistors upside down as this reduces the effective electrical length, but it will also increase the capacitance to ground. High-performance thin-film resistors are often offered with the option to have the end terminations on the top side only, and are mounted “flip chip.” For high-power application a third metallization can be added to the underside of the resistor so that it may be soldered directly to the ground plane for optimum thermal transfer. Specific values for resistors, such as 50 , have been produced with one of the end terminations wrapped around to cover the complete underside of the resistor. This is for use in terminations or loads. The majority of surface mount resistors are made using alumina substrates. For high-power applications beryllium oxide (BeO), thermal conductivity 290W/m ◦ C, or
317
7.4 Components
CAP ID=Cf C=0.021 pF
Helical Trim
PORT P=1 Z=50 Ohm
RES ID=R1 R=100 Ohm
IND ID=L1 L=LPS nH
PORT P=2 Z=50 Ohm
Pulsed Trim CAP ID=Ci C=0.02 pF
CAP ID=Ci C=0.02 pF
Meander Trim
(b) (a)
Thru Loss
Insertion Loss (dB)
–6
–8
DB(|S(2,1)|) 100R_Modelled_RTD DB(|S(2,1)|) 100R_Modelled_AI
–10
DB(|S(2,1)|) 100R_Sparams DB(|S(2,1)|) Lumped Model AI
–12
DB(|S(2,1)|) Lumped Model RTD
–14
0
5
10 Frequency (GHz)
15
20
(c)
Figure 7.15 Surface-mount resistors: (a) resistor trimming approaches; (b) simple equivalent circuit for 0603 resistor on 0.8 mm thick εr = 2.2 with recommended mounting pads; (c) performance of 0603 100 resistor, manufacturer’s raw data (100R_Sparams), resistor model and EM on 0.635 mm alumina and RT duroid 5880 substrates and lumped equivalent circuit.
aluminum nitride (AlN), thermal conductivity 170W/m ◦ C, are used. Despite having lower thermal conductivity, AlN is increasingly popular as beryllia is highly toxic in its powder form. It is banned in a number of applications and countries, products containing it must be appropriately labelled, and it is difficult to dispose of. Increasing volumes and the number of suppliers have seen the price of AlN products fall to acceptable
318
Microwave hybrid amplifier realization
Table 7.8 Conventional thick-film resistors mounted on 0.8 mm FR4 substrate
Reference
Size (mils)
Size (mm)
Power rating (mW)
0201 0402 0603 0805 1206 2010 2512
20 × 10 40 × 20 60 × 30 80 × 50 120 × 60 200 × 100 250 × 120
0.51 × 0.25 1.02 × 0.51 1.52 × 0.76 2.03 × 1.27 3.05 × 1.52 5.08 × 2.54 6.35 × 3.05
50 63 100 125 250 500 1000
levels. Where single terminations cannot handle the power level required, resistors can be used in parallel. This has the added advantage of reducing the series inductance, but capacitance can increase. Resistors in microwave circuits are often approximated by a simple equivalent circuit, as shown in Figure 7.15b. However, it should be noted that the value of Ci is dependent upon the pad size and the substrate used, hence a generic model for the resistor should not be used. The value of Cf depends upon the resistor size, pad dimensions, and end terminations. An example of how different models and substrates will affect the model performance is shown in Figure 7.15c. A 100 resistor has measured S-parameters from 45 MHz to 2 GHz; these are extrapolated to 20 GHz as a reference. The resistor is modeled using both a lumped element equivalent circuit as in Figure 7.15b and a using a modified equivalent circuit replacing Ci with an EM simulation for the mounting pads. The parasitic inductance and the resistance are constant for all simulations. This shows that the performance of the resistor itself cannot be taken in isolation. If S-parameters are used they need to cover the full frequency range and be properly de-embedded from the measurement test fixture. The mounting pads need to be included in the simulation, either directly or as tracks feeding the component. Table 7.8 lists the power rating and size of common surface-mount resistors.
Capacitors These are essential in the operation of microwave amplifiers, they have functions at both DC and RF and the requirements are often at odds. They are used for interstage bias de-coupling, matching, by-passing and localized charge storage. As with resistors, not only must their primary characteristic – capacitance – be considered but also the parasitic elements. In its most basic form a capacitor consists of two parallel plates separated by an insulating material. Such capacitors, called single-layer capacitors (SLCs), are commonly used in microwave applications. The capacitances that can be achieved are determined by the relative dielectric constant of the insulating material, εr . The capacitance, C in pF is given by C=
0.00885εr A , d
(7.7)
7.4 Components
319
Horizontal Orientation C17AH101K-7UN-X0T 100.0 pF Temp = 25 0 –1
S21 (dB)
–2 –3 –4 –5 –6 0
1
2
3
4
5
6
7
8
9
10
Frequency (GHz) Vertical Orientation C17AH101K-7UN-X0T 100.0 pF Temp = 25 °C 0 –1
S21 (dB)
–2 End termination
–3
Capacitive Plates, end termination removed.
–4 –5 –6 0
1
2
3
4 5 6 Frequency (GHz)
7
8
9
10
Figure 7.16 Effect of plate orientation. Courtesy of Dielectric Laboratories, Inc., www.dilabs.com.
where A is the area of the plates in mm2 and d is the separation in mm. Working against the application of the capacitor in MHPAs is that the closer the plates are then the lower the breakdown voltage, and the higher the εr the worse the temperature stability and often the loss. In order to achieve high capacitance values layers of capacitors can be made with alternate plates joined together as shown in Figure 7.16, hence their name “multilayer capacitors” (MLCs). In this way higher capacitance values can be achieved for the same foot print. The parasitic elements of a capacitor are largely due to the dielectric materials and the physical size. The inductance is proportional to the length of the plates. The loss in the dielectric, (the energy that is dissipated as heat) is expressed as a resistance in parallel, RS . Modeling capacitors in the microwave region can become very tricky, not least because the performance changes dramatically with orientation, as shown in Figure 7.16. With the plates parallel to the ground plane (horizontal) a series of resonances exist, rotating the capacitor 90◦ so that the plates are now perpendicular to the ground plane (vertical) removes half of the resonances. There are a number of
320
Microwave hybrid amplifier realization
Table 7.9 Characteristics of various dielectric materials and approximate changes with frequency Material
εr
Tan δ (DF)
Q100 MHz
∼Q1 GHz
∼Q10 GHz
Barium Titanate Ceramic Alumina Porcelain
1200–8000 30 10 15
0.03–0.1 0.002 0.0005 0.00007
33–10 500 2000 ∼14000
3–10 50 200 1400
500 3.39 ≥5000
1
Pure materials at room temperature.
One can find comprehensive information on the design, fabrication, and performance of monolithic microwave and millimeter-wave integrated circuits as well as their applications in IEEE Microwave and Millimeter-Wave Monolithic Circuits Symposium Digests published from 1982 to 1996, IEEE RFIC Symposium Digests published since 1997, and IEEE GaAs IC Symposium Digests published since 1980. Several other books listed [2–23] deal with this subject either partially or exclusively.
8.2.2
MMIC substrates Various substrate materials used for MMICs are bulk silicon, silicon carbide, GaAs, InP, and GaN. Their electrical and physical properties are compared in Table 8.1. The semi-insulating and high-thermal conductivity property of the substrate material is crucial to providing higher device isolation and lower dielectric loss, and a good heat dissipation path for power MMICs. Silicon dominates the marketplace and GaAs is used widely at RF, microwave, and mmW frequencies. For high-voltage, high-power and high-temperature applications, wide-bandgap materials with relatively high thermal conductivity, such as SiC and GaN, play a significant role as a substrate material. The recent development of high-voltage active devices with very high-power densities on a SiC substrate was only possible due to its high thermal conductivity, which is a prime requirement for any semiconductor material to be used as a substrate for high-voltage and high-power density devices and MMICs.
8.2.3
MMIC active devices The MESFET (0.25–1.0 μm gate lengths) has been the workhorse for analog integrated circuits (ICs) since 1976. MESFET based power MMICs demonstrate excellent performance at microwave frequencies. However, HEMT and HBT devices offer potential advantages in microwave and millimeter-wave IC applications, arising from the use
362
Monolithic power amplifiers
2b W
εr
(a)
W = 2a h
S
εr
(b)
Figure 8.3 Transmission lines for MMICs: (a) microstrip, (b) coplanar waveguide.
of heterojunctions to improve charge transport properties (as in HEMTs) or p–n junction injection characteristics (as in HBTs). HEMTs appear to have an advantage in ultralow-noise and mmW applications. The MMICs produced using novel structures such as pseudo-morphic, lattice-matched HEMTs, also known as pHEMTs, have significantly improved the power performance and high-frequency (up to 280 GHz) operation. AlGaN/GaN HEMT devices have demonstrated power densities greater than five times higher than that of conventional GaAs-based transistors [24, 25]. HBTs are vertically oriented heterostructure devices and are popular as power devices. GaAs HBTs are extensively used as power devices for high-volume wireless applications because of their high-gain, good efficiency, and single power supply low-voltage operation. They also offer better linearity and lower phase noise than do FETs and HEMTs. For power circuits, where one needs much higher current, either a large number of cells are employed or larger gate periphery devices are used. The performance of microwave transistors in MMIC technologies is improving every year. The upper frequency limit of MMICs is generally dictated by the active device technology used. The performance of these devices (FETs, HEMTs, and HBTs) depends on the substrate material, process type, and channel physical dimensions. A commonly used figure of merit for devices is known as the maximum frequency of oscillation and denoted by fmax . Generally, for amplifiers the maximum frequency of operation is about half of fmax [26]. As reported in the literature, the fmax values for a 0.1 μm gate-length pHEMT on an InP substrate is about 600 GHz, and for a 1 μm emitter HBT it is about 170 GHz. A three-stage amplifier fabricated using a 0.1 μm pHEMT on an InP substrate has exhibited about 12 dB gain at 153–155 GHz [27]. MESFETs, HEMTs, and HBTs have been described in detail in Chapter 2.
8.2.4
MMIC matching elements In addition to active devices, MMICs require high Q passive circuit elements. Like hybrid ICs, monolithic circuits use distributed as well as lumped matching elements. The microstrip line and coplanar waveguide (CPW) are the two most commonly used transmission media in MMICs. Microstrip is more popular because of its quasi-TEM nature and excellent layout flexibility. Microstrip line is exclusively used in MMIC amplifiers due to high current handling capability. Cross-sectional views of these lines with physical parameters are shown in Figure 8.3. Sections of microstrip lines and coplanar waveguide constitute the basic passive component building blocks of
8.2 Monolithic IC technology
363
Table 8.2 Microstrip data summary on GaAs substrate: h = 100 μm, t = 5 μm, tan δ = 0.0005, f = 10 GHz and εr = 12.9
W (μm)
W/h
Z0
εre
α (dB/cm)
Line capacitance (pF/100 μm)
Line inductance (nH/100 μm)
10 20 30 40 50 75 100 125 150 200 250 300 400 500
0.10 0.20 0.30 0.40 0.50 0.75 1.00 1.25 1.50 2.00 2.50 3.00 4.00 5.00
87.8 75.1 67.2 61.4 56.8 48.4 42.5 38.1 34.5 29.2 25.4 22.5 18.3 15.5
6.89 7.23 7.45 7.62 7.76 8.06 8.31 8.52 8.71 9.03 9.30 9.52 9.89 10.18
0.716 0.541 0.468 0.422 0.390 0.342 0.315 0.301 0.293 0.282 0.276 0.271 0.265 0.262
0.010 0.012 0.014 0.015 0.016 0.020 0.023 0.026 0.028 0.034 0.040 0.046 0.057 0.069
0.077 0.067 0.061 0.056 0.053 0.046 0.041 0.037 0.034 0.029 0.026 0.023 0.019 0.016
monolithic microwave integrated circuits. When the size of the microstrip section is reduced to dimensions much smaller than the wavelength, the section can be treated as a lumped element. Examples of lumped microstrip elements are spiral inductors, thin-film resistors, and interdigital capacitors. Microstrip sections in lumped and distributed forms are commonly used in passive and active monolithic microwave integrated circuits. To realize compact circuits, lumped element matching networks, or lumped-distributed circuit elements are utilized to transform device impedance to 50 . An overview of these circuit elements is given below [28].
Microstrip Several methods used to determine microstrip parameters are summarized in reference [28]. The microstrip propagation properties, such as the characteristic impedance (Z0 ), effective dielectric constant (εre ) and attenuation constant (α) are controlled by conductor width W and substrate height h for a given dielectric constant value (εr = 12.9 for GaAs). Table 8.2 summarizes Z0 , εre , α, line capacitance and line inductance data calculated for various line dimensions and for a GaAs substrate. As an example, for a 50 line on a GaAs substrate, the value of width-to-height ratio W/h is about 0.7. As shown in Figure 8.4, the characteristic impedance Z0 decreases and the effective dielectric constant εre increases when the strip W/h of the line is increased. The measured attenuation constant of microstrip as a function of line width on 100 μm thick GaAs at 1, 10, 20, and 30 GHz is shown in Figure 8.5. The attenuation in the line decreases with increasing line width. Wavelength in microstrip λ is related to εre by √ λ = λ0 / εr e where λ0 is the free space wavelength.
(8.1)
Monolithic power amplifiers
120
12
100
10 εre
80
Z0(Ω)
60
8 6 εre
Z0
40
4
20
2
0 0.01 0.02 0.05
0.1
0.2
0.5
1
2
5
0 10
W/h Figure 8.4 Variation of characteristic impedance and effective dielectric constant of microstrip versus W/h on 100 μm thick GaAs.
1.6
1.2 α (dB/cm)
364
0.8 f (GHz) 30 20 10
0.4 0 10
1
20
40
100
20
400
Line Width (μm) Figure 8.5 Measured attenuation constant of microstrip versus line width on 100 μm thick GaAs at 1, 10, 20, and 30 GHz.
The maximum frequency of operation of a microstrip transmission line is limited as a result of several factors including excitation of spurious modes, higher losses, pronounced discontinuity effects, low Q caused by radiation from discontinuities, effect of dispersion on pulse distortion, tight fabrication tolerances, handling fragility and, of course, technological processes. The maximum frequency of operation of a microstrip transmission line, the frequency at which significant coupling occurs between the dominant quasi-TEM mode and the lowest-order surface wave spurious mode, is given by [28], 150 fT = πh
2 tan−1 εr εr − 1
(8.2)
8.2 Monolithic IC technology
365
where fT is in gigahertz, h is in millimeters and the inverse of tangent is expressed in radians. The excitation of higher-order modes in a microstrip can be avoided by operating it below the cut-off frequency of the first higher-order mode, which is given approximately by fc = √
300 εr (2W + 0.8h)
(8.3)
where fc is in GHz, and W and h are in mm. This limitation is mostly applicable for low-impedance lines that have wide microstrip conductors. The calculated value for the maximum thickness of the GaAs substrate for microstrip circuits designed at 100 GHz is less than 0.3 mm. Since it is impossible to do tuning on GaAs MMICs, an accurate and comprehensive modeling of microstrip discontinuities is required to save expensive and time-consuming iteration of mask and wafer fabrication and evaluation. As the yield of MMICs depends on the size (the smaller the chip, the higher the yield), and the circuit’s acceptable electrical performance, discontinuities play an important part in the development of MMICs. The effect of discontinuities becomes more critical at higher frequencies. The discontinuities should be either taken into account or compensated for at the final stage of design. In most cases discontinuities are basically undesirable circuit reactances, and in a good circuit design, efforts are made to reduce or compensate for these reactances as discussed in reference [28]. In most high-frequency applications, the compact matching circuits are electromagnetic (EM) simulated.
CPW Several methods used to determine CPW parameters are summarized in reference [28]. CPW properties are controlled by the center conductor width W and the spacing between the strip and the ground-plane conductor denoted by S in Figure 8.3b. In CPW, the substrate thickness generally used is large so that if the substrate has a conductor backing to improve the mechanical strength, its effect is insignificant on the electrical characteristics of the CPW. Figure 8.6 shows the variation of Z0 and εre as function of the conductor width to gap separation ratio. The characteristic impedance of the line decreases with increasing a/b ratio. The measured attenuation versus characteristic impedance Z0 for CPW is shown in Figure 8.7. The attenuation in the line at 60 GHz has a minima when the characteristic impedance of the line is about 60 . For thick substrates the coupling of power from the dominant mode to higher-order modes takes place. The coupling to surface waves and radiation from unwanted (parasitic) modes contributes additional loss to the total loss of the CPW. The parasitic mode in a coplanar waveguide is the odd-mode with antiphase voltages in the two slots. This mode can be excited at discontinuities, and radiation may occur. Radiation from this mode can be minimized by maintaining symmetry of the circuits and thus avoiding its excitation or by using air bridges connecting the ground planes at regular intervals to short circuit it out. In a conductor-backed coplanar waveguide, the parallel-plate waveguide modes are other parasitic modes. Surface waves or the substrate modes are the TM and TE modes supported by the substrate. Excitation of these modes can be avoided if
Monolithic power amplifiers
160
7.5 h/b h/b 0.5 1.0
140
7.0
∞
120
6.5
∞ 1.0
6.0
100
εre
Z0(Ω)
0.5
80
5.5
60
5.0
40
4.5
20 0.01 0.02 0.05 0.1 0.2 0.5 a /b
4.0 0.01 0.02 0.05 0.1 0.2 0.5 a /b
1
1
Figure 8.6 Variation of characteristic impedance and effective dielectric constant of CPW versus slot dimensions on GaAs.
10 b (mm) = 0.10 0.15 0.20
5 α (dB/cm)
366
1 0.5
0.1 10
50
90
130
170
Z0 (Ω) Figure 8.7 Measured attenuation constant of CPW versus slot characteristic impedance on 100 μm thick GaAs at 60 GHz.
a thin substrate is used such that the cutoff frequency of the surface modes is pushed above the operating frequency. This is achieved if the substrate thickness h is chosen such that √ h ≤ 0.12λ0 / εr
(8.4)
where λ0 is the free space wavelength. Like microstrip discontinuities, CPW discontinuity effects must also be taken into consideration. CPW MMICs, compared with microstrip-based MMICs, can have lower loss at millimeter-wave frequencies with proper design of the matching networks, require
8.2 Monolithic IC technology
367
Figure 8.8 Microstrip lumped elements:(a) inductors and (b) capacitor.
S
W
Di
Do (a)
(b)
Figure 8.9 Coil inductor configurations:(a) circular and (b) rectangular.
no via-hole technology for RF ground connections, and are more suitable for flip-chip mounting.
Lumped elements A lumped element in radio frequency and microwave circuits is defined as a passive component whose size across any dimension is much smaller than the operating wavelength so that there is no appreciable phase shift between its input and output terminals. Generally, keeping the maximum dimension less than λ/20 is a good approximation. Lumped elements for use at RF and microwave frequencies are designed on the basis of this consideration, and the three basic lumped element building blocks are inductors, capacitors, and resistors. Figure 8.8 shows basic microstrip line inductors and a capacitor. Their simple forms are realized using microstrip sections. Among various inductor shapes, circular and rectangular spiral inductors, shown in Figure 8.9, and metal-insulator-metal (MIM) and interdigital capacitors, shown in Figure 8.10, are commonly used. A microstrip section realized employing a lossy conductor is used as a resistor. At RF, lumped inductors and MIM capacitors are widely used in MMIC matching networks. Lumped-element based power amplifier circuits have the advantage of smaller size, lower cost, and wider bandwidth characteristics. These are especially suitable for MMICs
368
Monolithic power amplifiers
Table 8.3 Coefficients for general inductance expression Inductor geometry
c1
c2
c3
c4
Square Hexagonal Octagonal Circle
1.27 1.09 1.07 1.00
2.07 2.23 2.29 2.46
0.18 0.00 0.00 0.00
0.13 0.17 0.19 0.20
Bottom conductor
Top conductor W
d
εrd
(a)
(b)
Figure 8.10 (a) MIM capacitor, (b) interdigital capacitor and (c) equivalent circuit.
where real-estate requirements are of prime importance and applications where broadband is required. Currently, MMIC technologies have reached a mature stage; lumped elements working even up to 60 GHz are more suitable for low-cost circuit solutions. At frequencies below S band, MMICs using lumped inductors and capacitors are an order of magnitude smaller than ICs using distributed elements. At RF and the low end of the microwave band, the use of lumped elements makes the chip size significantly smaller without affecting the RF performance, increasing the number of PA chips per wafer, and giving improved visual and RF yields. All these factors can reduce the chip cost drastically. One can buy 1–2 W power amplifiers for as low as $5. Lumped element models can be developed using analytical, physics and EM, and measurement-based methods. A more general expression for inductance of arbitrary shape has been reported in the literature and reproduced as follows [20] μ0 n 2 Dav c1 (8.5) n (c2 /χ ) + c3 χ + c4 χ 2 2 where coefficients ci for various geometries are given in Table 8.3, χ is the fill ratio and Dav is the average diameter of the inductor, and their expressions are given below L=
χ=
Do − Di Do + Di
(8.6)
1 (Do + Di ) (8.7) 2 MMIC capacitors are classified into three categories: microstrip (Figure 8.8b), MIM, and interdigital as shown in Figure 8.10. A small length of an open circuited low-impedance microstrip section can be used as a lumped capacitor with a low capacitance value (90%) Ag epoxy WCu (80/20) Cu laminates (Cu-CuMo-Cu) Cu AlN Al2O3 (96%) BeO Diamond Thermal grease Thermal pad (graphite pad)
95 50 35 ∼10 180–200 220–250 390 60–190 20–30 210–230 500–2000 3 In plane: 240 Thickness Direction: 5 167
1.57
0.15
Al alloy (6061)
Density (g/cm3 )
Specific heat (J/g K)
15.6 8.95 3.5 3.8 2.1–2.5 3.5
2.7
0.385
0.9
CTE (ppm/K) 2.6 5.7 3.2 (orthogonal) 5.6 (parallel) 4.3 (orthogonal) 4.7 (parallel)
7.6 ∼8–9 16.5 4.5 6.5 6–8.5 ∼1.5 In Plane: ∼1 Thickness Direction: 30 24
Note: All properties are at 300 ◦ K. All values provided here should be considered as guidance; for rigorous design/research work, consult original literature.
materials (thermal grease, compliant thermal pad) and heat sink materials (Cu, Al alloy); in addition, it also has entries for a few other thermo-physical properties (such as density, specific heat and coefficient of thermal expansion). General references are cited [23, 24] to literature to look up the thermo-physical properties for many of these materials of interest. Some general discussions on the behavior of k are in order. Composition and purity of the material generally affect its k. Typically, the purer the material is, the higher its k. Typically, alloys and intermetallics have lower k compared to the pure elements that make up the alloy. A good example would be pure Cu versus alloys of Cu such as Cu-151 and Cu-194; all three Cu materials are typically used in RFPA packaging applications. Compared to pure Cu (k = 385 W/m K), these alloys have lower values of thermal conductivity e.g., Cu-151 has k = 350 W/m K while Cu-194 has k = 240 W/m K, 60% lower than pure copper. Added elements in the pure material to create the alloys typically create new grain structures; the grain boundaries cause more scattering centers for the phonons and electrons which are the carriers of thermal energy in the material body, leading to a reduced k value for the alloys. Increased temperature typically adversely
Thermal Conductivity (W/m/K)
9.3 Thermo-physical properties of materials in an RFPA
425
1.00E+03 8.00E+02 6.00E+02 4.00E+02 2.00E+02 0.00E+00 0.00E+00 1.00E+02 2.00E+02 3.00E+02 4.00E+02 5.00E+02 6.00E+02 7.00E+02
Temperature (K)
Figure 9.11 k of Si as a function of temperature.
affects k for certain classes of material. For example, k of Si drops from about 148 W/m K to about 100 W/m K as the operating temperature of Si rises from about 25 ◦ C to 150 ◦ C. As a consequence, the thermal resistance of the Si device will be higher at a higher operating temperature. This needs to be taken into account in the thermal design of a high-power RFPA using Si transistors dissipating substantial heat. In contrast, the thermal conductivity of some types of material do not show much dependency with temperature. Good examples are metals (Cu), metal alloys (Cu-194, Cu-151), metal composites (CuW, CuMo, and Cu-CuMo-Cu laminates), and intermetallics (AuSi, AuSn). For these classes of material, thermal energy is predominantly carried by the charge carriers such as electrons and scattering is dominated by the fixed grain boundaries in the material and not by the electron-phonon scattering, thus there is a weak to no dependency on temperature. Comparing the thermal conductivity of RFPA device materials (Si, GaAs, GaN, and SiC) at room temperature of 20 ◦ C, SiC has the highest value, about three times higher than Si, while GaAs has the lowest value, about 2.5 times lower than Si, and GaN is similar in value to Si. Thus, in a steady-state thermal flow situation with a similar device layout, the thermal resistance of a GaAs device will be the highest, the SiC device the lowest, and a GaN device will be comparable to a Si device. The detailed behavior of k versus temperature of Si is shown in Figure 9.11. In the thermal design of a high-power RFPA using Si transistors then such detailed knowledge must be taken account of. In an effort to reduce the thermal resistance in a high-power RFPA, the device package flanges use materials of increasingly higher k values. CuW with a k value of about 180 W/m K had been the work-horse for many years. This has been replaced in many applications [25, 26] by Cu laminates (Cu-CuMo-Cu and Cu-Mo-Cu) with a k value of about 250 W/m ◦ K. In certain cases, Cu with an even higher k value of 385 W/m ◦ K is used for RFPA package flanges. In the construction of an RFPA transistor package, materials of differing strength and coefficient of thermal expansion (CTE) are joined together at various temperatures. Typical examples are the joining of an alumina ceramic window frame to a metallic flange material such as CuW or Cu-CuMo-Cu using a high-temperature brazing material, e.g., CuAg, to create an air-cavity transistor package. Such a manufacturing process creates
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a very large stress due to the mismatch in the CTE values between alumina and the Cu-laminate flange and the high-temperature brazing. This can affect the robustness of the transistor package and can manifest itself in a dramatic manner such as ceramic window-frame cracking or severe de-lamination. It can also have a more subtle impact such as warping of the flatness of the flange, which can potentially result in higher interfacial thermal resistance between the RFPA component package and the next level assembly. Thus, the choice of package flange material is usually a compromise between the desire to get the highest k value for the flange material versus the need to closely match its CTE to the ceramic window-frame. Substantial technical and trade literature exists [27] on the topics of tailoring the compositions of CuW and CuMo, and of tailoring the relative thicknesses of the laminates such as Cu/CuMo/Cu, and of controlling the amount of cross-rolling various layers in creating the transistor flange material for an RFPA package header. In the making of very high-power RFPA devices, there are three very commonly used metallurgical material systems for joining the semiconductor device to the flange (commonly called die attach materials): AuSi eutectic hard solder, AuSn eutectic hard solder, and PbSnAg soft solder. Achieving a high-quality die attach joint is critical in realizing low thermal resistance for the device as well as for creating a robust product under power and temperature cycling stresses of the RFPA that it will be subjected to during its operational life. The thermal resistance of such joints and contacts will be discussed later in further detail. Since such joints are very thin, of the order of 5 μm for AuSi eutectic, 25 μm for AuSn preform- based attach, and 40 μm for PbSnAg solders, k alone does not play the main role in determining the joint’s thermal resistance; the quality of the joint (as determined by any voids at the interface and in the bulk of the die bond) plays an equally important role in determining the joint’s thermal resistance. As in the joining of a ceramic window frame to the metal substrate, the joining of the semiconductor device to the package flange material requires careful attention to minimizing the thermo-mechanically induced stresses in the device material and achieving the required flatness for the header. k values for the three joining materials are compared in the Table 9.2; AuSi has the highest k value (about 100 W/m ◦ K) and enables the lowest thermal resistance for the joint between the Si RFPA device and the package header; however, it is also one of the most demanding in manufacturing discipline to achieve a high-quality joint. AuSi, being a hard solder, is not forgiving in absorbing CTE mismatch induced stresses; thus extreme care must be taken in managing the CTE mismatch between the Si device and the package flnge material. This explains the development of various material systems such as CuW, CuMo, Cu-CuMo-Cu laminates where both CTE and k values are optimized to provide the best thermal solution for the package flange. PbSnAg soft solder, although having the lowest k value (35 W/m ◦ K) among the three metallurgical diebond materials mentioned, reduces the thermomechanical stress in the joint under low duty-cycle thermal fatigue stress conditions, thus enabling the joining of a thermo-mechanically mis-matched structure such as a Si device to Cu flange in a high-power RFPA device. Due to its desirable low duty-cycle fatigue behavior, PbSnAg-based soft solder die attach is extensively used in high-power Si RFPA device packaging. AuSn reform-based die attach is less commonly practiced for
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Si power devices; however, it is very commonly used in bonding GaAs and GaN RFPA devices to metal flanges. Typically, AuSn die attach thermal performance falls between that of AuSi eutectic die attach and PbSnAg solder die attach. Finally, there is another class of die attach material, outside the class of metallurgical die attaches, that is used in RFPA device construction; this is Ag-filled epoxy adhesives. They have relatively low k values (in the range of 5 W/m ◦ K to 10 W/m ◦ K) but these epoxies typically handle the mis-match induced thermo-mechanical stresses well. However, their bond strength typically degrades with moisture and increased temperature. Typical bond line thickness falls in the range of 25 μm to 50 μm. For these reasons, these Ag-filled epoxies are typically used for die attach in low-power RFPAs such as those used in portable products, general purpose amplifiers, and in predrivers in a high-power RFPA lineup. We described earlier that in typical use the high-power RFPA component is physically secured to a Cu pallet/heatsink to enable removal of the waste heat (Figure 9.9). If the RFPA component is not soldered to the Cu pallet, then it is mechanically fastened. In such a scenario, to reduce the thermal interface resistance between the RFPA component and the Cu pallet, thermal grease or a mechanically compliant thermal pad is used. Thermal grease is typically silicone fluid filled with metal oxide powders with an effective k value of ∼3 W/m ◦ K [28]. They fill the interstitial space between the two mating metal surfaces. The thermal interface consists of two parallel paths for heat flow, one through multiples of metal-metal point contacts and the other through multiples of interstitial space filled with thermal grease. The silicone fluid can be lost or the joint can become dry, thus their long-term effectiveness is a concern. The other class of material is a physically compliant thermal pad. Though there are numerous types, the most effective ones are pyrolytic graphite such as TgonTM [29]. Such thermal pads are polymeric material with embedded pyrolytic graphite fibers. They are available in various thicknesses, 0.125 mm to 0.5 mm. They have k values ∼200 W/m ◦ K in the planar dimension and ∼5 W/m ◦ K in the thickness dimension of the pad. In RFPA applications, metal foils (such as Indium or Cu or Solder) are also used.
9.4
Tools to characterize and predict the thermal performance of RFPAs A key metric in assessing the thermal performance of a component such as an RFPA is Rjc (or θ jc ), the junction-to-case thermal resistance. Rjc is pictorially explained in Figure 9.9b. This metric is analogous to the electrical resistance, R. The dissipated power in the device, P (analogous to the current I in an electrical circuit), flows from the device junction to the heatsink under the driving force of the temperature differential Tj –Tc (analogous to voltage difference in the electrical circuit), overcoming the thermal resistance Rjc (analogous to electrical resistance, R). For a quantitative determination of Rjc , one needs to determine the parameters Tj , Tc , and P. In this section we will address this area, with a focus on measuring and predicting Tj , the device junction temperature. Experimental thermal characterization and computer aided thermal modeling are two approaches to characterize and optimize the thermal performance of electronic devices and systems. Experimental thermal characterization usually can provide a direct and
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accurate measurement of device or package temperatures; however, assembling the experimental hardware, the effort to prepare samples, and the number of experiments needed all take up considerable time and expense. Also, any measurement has associated errors arising from calibration, methodology, operator, and sample distribution. On the other hand, advancements in modeling and simulation software as well as computing speed make thermal simulation effective in analyzing and predicting the thermal performance and thus offers an attractive alternative. However, the simplifications and assumptions made in constructing the computer model of the physical reality, and the uncertainties in our knowledge of material properties and boundary conditions, all impact the accuracy of the simulated thermal results. A careful use of both experimental characterization and computer-aided simulation can make up the deficiencies in each and provide realistic and accurate results. In this section we will review both approaches and their applications towards thermal characterization of high-power RFPAs.
Measurement: methods, tools, current status During experimental thermal characterization of an RFPA device, we typically measure the temperatures of the active device junction, the mounting chassis, and the ambient. In addition, we measure any relevant boundary condition such as air flow conditions. We will first address the measurement of surface temperatures of a component package or module or heatsink using a thermocouple thermometer. A thermocouple thermometer is a temperature sensing junction created by joining two dissimilar metals together. When such a thermocouple junction is heated or cooled, a voltage is produced that can be measured and correlated to temperature. Thermocouples are available as wires with different combinations of metals or calibrations. The four most common types of thermocouple are J, K, T, and E. As an example, Type J thermocouple is made of the dissimilar metals iron and constantan, and can be used in the temperature range of −40 ◦ C to +750 ◦ C and has a temperature sensitivity of 55 μV/◦ C. Excellent product information is available on thermocouples [30]. However, a number of precautions need to be taken in applying a thermocouple to measure surface temperatures accurately. The diameter of the thermocouple wire should be small such that heat loss along the wire does not cause an erroneous reading [31] of the surface being measured; gauge 36 or gauge 40 wire is preferred. The thermocouple bead should make good physical, and thus thermal contact, to the surface being measured. When we refer to device temperature, typically it is the device junction (also called channel) temperature; for many RFPA devices, the device junction is typically located close to the surface of the die (for an LDMOS device, it is about 10 μm below the surface), thus the surface temperature measured on the die is nearly the same as the junction temperature. Techniques to measure the operating temperature of a semiconductor device can be broadly grouped into two categories, direct and indirect methods. Direct methods include infrared (IR) thermometry [32, 33], liquid crystals [34], and thermographic phosphors [35] which allow direct mapping of the surface temperature of the device. Among these direct techniques, IR thermometry is the only technique capable of quantitative temperature measurement; the other two techniques are qualitative. The
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indirect techniques use a temperature sensitive electrical parameter of the semiconductor device (such as Vf for a diode, or Veb for a bipolar transistor, or Vds for a FET) to measure the device temperature [36]. However, this technique typically provides only an average temperature for the chip and is prone to many errors and difficulties when applied to RFPA devices. Thus, Infrared Thermometry is the most commonly used technique to provide direct, quantitative thermal mapping of an RFPA device. Before we address Infrared Thermometry in detail, we will briefly review other measurement techniques that are commonly used in characterizing the thermal performance of electronic devices, packages and modules in general. In the context of selecting or developing a suitable package to house a semiconductor device, one may use a thermal test chip or an active device to thermally characterize the package or module. In such an approach a calibrated (with respect to temperature) electrical parameter such as the forward-biased diode voltage (Vf ), or forward biased device junction voltage (such as Vds for a FET or Veb for a bipolar transistor) is used as temperature sensitive parameter to measure the device temperature. Abundant literature exists on this approach of using active devices [36, 37] and thermal test chips [38] to perform such a task. If one were to use a thermal test die to characterize a package or a module, the typical thermal test die will consist of a separate heating source (typically, a thin-film resistor deposited on the die) and temperature sensors e.g., diode, transistor or metal-film resistor, all integrated into the test die. Typically, such sensing diodes are calibrated for Vf versus T prior to use. They typically have a temperature sensitivity in the range of 2 to 3 mV/◦ C. To improve the accuracy in measuring the voltage drop across the temperature sensing diode, four-wire Kelvin contacts should be used (i.e., separate forcing and sensing lines are used to contact each sensing diode). In the absence of the availability of thermal test chips, active devices (transistors, ICs) can be used to provide both heating and temperature sensing functions. In such a situation, an electronic switching circuit is used to switch the device from a powering function to a sensing function. With the use of electronic switching, the time delay between powering and sensing can be made very short (of the order of a few tens of micro-seconds). Shorter delay times are preferred, but one needs to allow the electrical transients due to switching in the measurement region of the active device to die down so that one captures the true electrical signal representing the temperature effect. Nevertheless, the junction region will cool rapidly during this delay time. One needs to balance these two considerations in selecting a suitable delay time. There are known techniques to calculate and correct for the cooling that occurs in the sensing region before the temperature sensing is performed. Abundant literature exists on this methodology [39–41]. Getting back to IR thermometry, excellent IR measurement equipment is commercially available to perform accurate quantitative temperature measurements [42]. Figure 9.12 displays a state-of the-art IR microscope that is typically used in characterizing RFPA devices. Objects in the temperature range 0 ◦ C–200 ◦ C emit infrared radiation in the EM spectrum of wavelength 2 μm–10 μm. The emitted radiation is governed by: q = σ ∈ AT 4
(9.9)
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Figure 9.12 An IR microscope with an RF test bench.
where q is the radiant flux/unit area/unit solid angle in W/cm2 -ster, σ is the Stephan– ◦ Boltzmann constant (5.673 × 10–12 W/cm2 K4 ), ε the emissivity and T is the temperature in ◦ K. An IR transmitting (or reflecting) lens system collects the heat radiation from the device under test (DUT) and focuses it onto a liquid nitrogen cooled InSb detector. Stateof-the-art equipment uses focal plane array (FPA) detectors, thus a thermal image of the DUT’s entire surface is brought into focus. The signal from the detector is processed by suitable electronics and displayed as a color intensity map. The color intensity map is converted to a quantitative temperature map by a calibration procedure using a blackbody radiator. Various lens choices enable spatial resolution at the DUT level of the order of 2 μm and a temperature resolution of the order of 0.1 ◦ C for a DUT at about 80 ◦ C. Since the radiant energy from the DUT is a function of both the temperature and the emissivity of the surface, the emissivity needs to be known to arrive at the temperature from the image. Current day IR microscopes have special algorithms to determine the emissivity of a DUT pixel-by-pixel through measurement of radiant images at known temperatures. However, the emissivity determining procedures that are typically available as part of the measurement equipment can introduce errors for materials like Si that are IR translucent. To overcome this difficulty, typically the surface of a Si DUT is uniformly coated with an IR-opaque high emissivity paint. This procedure assures fixed emissivity for the surface of the DUT, thus simplifying the temperature determination and increasing the accuracy. The challenges in selecting a coating material and applying
9.4 Tools to characterize and predict the thermal performance of RFPAs
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Si LDMOS RFPA at 20W output RF power
• Max die temperature (Tj max) = 129.7°C
• Case temperature (Tc) = 73°C • Calculated Pdiss = 72.93W
Rjc = (129.7 – 73)°C / 72.93 W = 0.78°C/W
0.0
43.2 86.5 Temperatrure (°C)
129.7
Figure 9.13 Temperature profile of an RFPA device captured by an IR microscope.
it to an RFPA device surface such that it has low to no impact on the RF performance of the device are addressed in the literature [43]. A typical infrared thermal profile for a Si LDMOS RFPA device is shown in Figure 9.13. An RFPA device may exhibit temperature nonuniformities; however, the highest measured device temperature (Tjmax ) is used in characterizing the thermal performance metric Rjc .
Modeling and simulation: methods, tools, current status The mathematical simulation of fluid flow and heat transfer involves solving simultaneously the conservation of mass (continuity equation), conservation of momentum, and conservation of energy equations. This involves seeking a solution for a set of coupled, nonlinear second-order, partial differential equations, involving variables such as u, v, and w for the velocity of the flowing fluid, P for the pressure, and T for the temperature. Needless to say, this is a very complex undertaking. However, state-of-the-art software tools exist today to handle this class of problem very well. There are two main approaches, one based on finite volume/difference methods (FVM) and the second based on finite element methods (FEM). FVM is used in many CFD tools. For electronic cooling applications, many CFD tools have been tailored to focus on fluid flow and heat transfer only. In the use of a CFD tool, the spatial domain is discretized into small cells to form a volume mesh; the conservation equations for these discretized volumetric spaces are expressed in algebraic form, then suitable algorithms solve the equations of continuity, momentum and energy simultaneously. The CFD tool not only determines the fluid field, but it also solves any solid conduction within the computational domain (conjugate solution). In CFD analysis, there is no need to assume convective heat transfer correlations at the solid-fluid boundaries; exact fluid fields external to the solid surfaces are predicted during conjugate analysis. Thus, CFD tools have greater appeal for system level thermal simulations. In the FEM approach, the conservation equations are solved by approximating continuous quantities at discrete points spaced into a grid or mesh. Generally, FEM can
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handle more complex geometrical shapes coupled with large differences in the thermomechanical properties. At the component level analysis where conduction is the dominant heat flow process and where reliable boundary conditions can be used, FEM has greater appeal since it can handle very complex shapes with large differences in levels of detail, from the die active area layout to a completely assembled component device, all in one model. Thus, at component level analysis, typically FEM tools are used; empirical convective and radiative heat transfer correlations are applied to all the boundary surfaces of the package/PCB. Thus, a-priori engineering knowledge/judgment is needed to achieve good results. Furthermore, temperature profiles obtained from such an FEM analysis can be directly used in subsequent thermo-mechanical analyses to assess the various structural stresses in the component. ANSYS [44], Abaqus FEA [45], MSC Sinda [46], COSMOS [47] are some of the R [48], ANSYS leading FEM simulation tools commercially available. FloTHERM Icepak [44], ANSYS FLUENT [44] are some of the leading CFD simulation tools. To execute efficiently on any of these simulation tools mentioned here, it is imperative to have good models that truthfully represent the physical reality. Key steps and tools in building good models are: R r producing a CAD geometry for the structure using a program such as AutoCAD [49] R R or Pro-E [50] and/or using ECAD programs such as Cadence Allegro Package R Designer [51] or Mentor Graphics [52]; r assigning material properties (thermal conductivity, mass density, specific heat, viscosity) to the various physical regions of the model; r assigning proper boundary conditions such as a fixed temperature (e.g., ambient) to a reference location, and convective and radiative heat transfer coefficients at the heatsink surface in an FEM approach; r creating the mesh/grid with the appropriate level of detail (balancing the desired level of physical details versus model size and simulation time); r post-processing to display and extract the information (temperature, heat flux, fluidflow profile, contour plots of temperatures and air flow, numerical tables, etc.). Many of these supportive tools have become smart and user friendly. Thus, model building and simulation have become an integral part of RFPA thermal management.
9.5
RFPA thermal design and management – advanced In this section we will discuss in greater detail the thermal design and thermal management of high-power RFPA components. Though much of the discussion will generally be applicable to various RFPA device technologies, we will focus on Si laterally diffused metal oxide semiconductor (LDMOS) devices. The Si LDMOS device technology has many advantages such as high RF power gain, good efficiency, excellent linearity, and ruggedness, requiring only a single supply voltage, inherently good thermal structure, and all at low cost. Figure 9.14 compares two Si technologies, bipolar versus LDMOS. Bipolar transistors require complex packages as the underneath side of the
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Gate
LDMOS
Drain
Bipolar
Source
n+
n+
Base p
p+
n–
sinker
p – epi backside metal
collector V = ~26V
p+ substrate
n+ substrate Pkg Metal Flange
• Source at Ground Potential • Vertical current flow
Emitter n+
Dielectric (Beo or AIN) Pkg Metal Flange
Figure 9.14 Cross-sectional view of Si LDMOS and Si Bipolar RFPA devices.
die is the collector and hence it requires an electrical isolator such as BeO or AlN to be inserted between the die and the flange. Also, as the emitter is on the top of the die, a bond wire is required to connect it to the flange which adds inductance and lowers the RF gain. In contrast, LDMOS transistors can be bonded directly to the metal flange as the underneath side of the die is the source. This results in lower source inductance and hence higher gain, lower thermal resistance, and simpler packages which are lower cost. Si LDMOS device technology has almost totally replaced Si bipolar technology for RFPA devices in wireless infrastructure base-station applications, and increasingly also in other high-power RF applications such as wireless broadcasting, industrial and avionics. LDMOS device technology has continuously evolved since the first generation in 1993 to the current eighth generation device structures [53], improving upon many RF performance metrics, notably efficiency, power density (W/mm of gate periphery), linearity, and ruggedness. To achieve the lowest junction-to-heatsink thermal resistance for an LDMOS RFPA, an integrated and comprehensive approach from Si device layout, die thinning, package material selection, assembly manufacturing processes, to device mounting in the end application is required. We will address each of these areas. The basic LDMOS device structure has three electrodes – drain, source, and gate. Current flow between the drain and the source is controlled by the gate. Heat dissipation occurs in the current flow path in the high-resistance region, creating increased temperatures. A simplified view of this heat source description is shown in Figure 9.15, highlighting the heat dissipating structure, marked as a “heat source finger.” In creating an RFPA transistor, multiple device fingers are laid out, as shown in Figure 9.16. Thermal resistance due to the heat source layout can generally be understood using the “spreading thermal resistance” concept. Spreading thermal resistance is inversely proportional to the geometrical size of the heat source and the effective thermal
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Heat Source “Finger” Gate Metal
Gate Drain 4mil Thick Silicon
Source Metal
drain-source pitch “one finger” 0
Figure 9.15 Cross-section of an LDMOS device structure, describing the heat source.
Transistor fingers (channel) Cross section plane Periodicity
Figure 9.16 Representation of an LDMOS RFPA device, showing multiple heat source fingers laid out in parallel array.
conductivity of the semiconductor material and flange combination on which the heat source is laid out. It can be written as a (9.10) Rspreading = kdth where a is a constant, k is the effective thermal conductivity of the semiconductor material and flange combination, and dth is the equivalent thermal diameter representing the heat source. dth is proportional to the square root of the area of the heat source. Thus, to reduce the spreading thermal resistance arising from device layout, we need to increase the active area. Furthermore, for a given heat source area, maximizing the bounding perimeter of the area reduces the spreading thermal resistance. Thus, in laying out highpower devices, it is common practice to divide the total active area into multiple small segments (such as multiple parallel fingers) and utilize various meandering patterns (such as interdigitated rectangles). In the previous section under design tools, it was mentioned that the field of thermal model building and thermal simulation have become
9.5 RFPA thermal design and management – advanced
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Line Trace
Temperature (°C)
124.00 110.00 100.00 90.00 80.00 70.00 60.00 50.00 0 Distance (um)
50 27576
100
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200 Pixel #
250
300
350 382
Save Line Trace to Text File
Figure 9.17 IR thermal image and the temperature line profile of an RFPA device. Temperature nonuniformities among the three active Si transistor chips as well within each chip are shown. Peak die temperature = 124 ◦ C at Tcase = 70 ◦ C.
very robust and thus it is common practice to simulate and optimize device layouts for improved thermal performance using such computer-based thermal models. In a typical LDMOS device layout, a single heat dissipating finger is a few micrometers (∼2 μm) wide, a few hundred micrometers (∼300 to ∼1000 μm) long, and located a few micrometers (∼10 μm) below the Si surface. Multiples of such finger-like line structures are laid out with typical pitch between the fingers in the range of 20 to 100 μm. The author has carried out a systematic study of many such lay-outs, leading to some general guidelines: r finer pitch between heat source fingers results in a higher temperature for an array of fingers; coarser pitch results in lower array temperature; r for a given array finger design (i.e., width, pitch), temperature profiles along the fingers are similar for central and outer fingers; for any finger, temperature peaks near the center of the finger and falls to a lower value towards the end of the finger; r arrays with longer fingers result in a higher temperature uniformity along the finger. Thus, to maximize the uniformity of temperature across and along an array of fingers, the layout should use a large number of long fingers. To minimize the thermal resistance due to layout, coarser pitch should be used within any other constraints such as realizing adequate active area for the intended RF power in a given size Si chip. Even with careful attention to the layout of the active area to minimize temperature nonuniformities, such nonuniformities do exist in an RFPA device. Figure 9.17 is an IR image of an RFPA with three active Si chips, showing some level of temperature nonuniformity between the three chips as well as within each chip.
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Observed temperature nonuniformities could be due to: (a) nonuniform RF excitation of a multifinger device caused by small differences in the amplitude and phase of the input RF signal feeding the device; this causes an associated nonuniform Pdiss in such a multifinger device array, (b) even with uniform Pdiss in a multidie/multifinger layout, due to the geometrical effects associated with heat diffusion, temperatures in the interior die/structure tend to be higher compared to temperatures in the die/structure near the outer boundaries, (c) manufacturing defects such as a die bond void could create local hot spots, thus causing temperature nonuniformities in the device, (d) thermal spreading effect of the underlying substrate also contributes to the temperature nonuniformities seen in the active devices. Another contributor to the overall device thermal resistance is that from the finite thickness of the Si chip itself. This thermal resistance is directly proportional to die thickness. Typical Si thickness in high-power RFPA LDMOS devices is about 100 μm whereas in the main-stream semiconductor devices, the typical die thickness is about 300 μm. There are many manufacturing challenges to overcome in thinning large diameter (200 mm) wafers [54] to 100 μm thickness and subsequently handling the wafers through backside metallization, transport and sawing. However, new product requirements such as stacked memory in consumer products (e.g., mobile phone with camera) have made a favorable impact in the development of wafer thinning technologies in the semiconductor industry. Backgrinding is the most common method to thin wafers. Backgrind usually leaves grind damage such as micro-cracks on the wafer surface; back-grind also leaves sharp wafer edges which become the weakest part of the wafer. Additional stress relief processing such as polishing, dry etch, or wet etch is usually necessary following back-grind. Such a follow-up process typically reduces the grind damage, reduces wafer stress and thus warping and bow in the wafer, and improves wafer and die strength [55]. Producing strong Si die from the wafer thinning process is essential to realize a high-assembly yield and a reliable product as the Si chip is die bonded to CTE mismatched metal flanges. In earlier discussions on thermal conductivity, we had mentioned that GaAs has lower thermal conductivity by about 2.5 times compared to Si. Hence, high-power GaAs RFPA devices are thinned to 25 μm to 50 μm thickness to reduce the thermal resistance due to the GaAs substrate. Thus, considerable manufacturing investment is needed to enable leading edge performance in high-power RFPA devices. Next, we will consider thermal resistance in the die bond, the interface joint between the RFPA die and the underlying metal flange. We described in an earlier section the general properties of and the relative merits of four different die attach materials used in the RFPA industry: AuSi, AuSn, PbSnAg, and Ag filled epoxy. To lower the thermal resistance in the die bond, we seek a high k for the die bond material as well as a void-free and thin bond line. AuSi eutectic die attach can fulfill all these requirements. AuSi die attach for high-power RFPA Si devices is typically accomplished by an in-situ metallurgical reaction between Si (being supplied from the Si die) and Au (supplied by the Au metallization on the back of the die and on the flange surface). An SEM view of a AuSi die attach cross-section is shown in Figure 9.18. A nearly void-free die bond with a bond line thickness of about 5 μm can be typically achieved with AuSi eutectic die attach. Thus, AuSi die bond provides the best die bond method available for high-power
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Figure 9.18 An SEM image of AuSi die-bond of an LDMOS Si RFPA device to a W/Cu metal flange. Bond line is thin (∼5 μm), of uniform thickness, and void free.
RFPA Si devices. Furthermore, AuSi die attach does not show any hardening or fatigue behavior after long thermo-mechanical cycling since, being a hard solder, it behaves elastically. Understanding the stress created in the Si and designing for the stress to be well below the strength of Si is key in the successful practice of AuSi die attach in high-power RFPA devices. It is well known that any void in the die attach interface can add additional thermal resistance to the path and it usually manifests itself as a hot spot in the active region of the die [56, 57]. AuSn die attach is less common in bonding high-power Si RFPA devices. However, it is one of the most common die attach methods in bonding high-power GaAs and GaN RFPA devices. Typically, AuSn die attach is accomplished with the help of a AuSn preform or predeposited AuSn solder, thus the bond-line thickness is in the range of 25 μm. The AuSn die attach interface layer typically has a higher thermal resistance compared to a AuSi die attach interface layer both due to its lower k value (∼50 W/m ◦ K versus ∼100 W/m ◦ K) and larger bond line thickness. PbSnAg die attach is very common in bonding Si power devices to a CTE mismatched substrate such as Cu because PbSnAg soft solder has excellent thermal cycle fatigue behavior. PbSnAg die attach is typically accomplished by dispensing molten liquid solder or solder paste, thus the bond-line is thicker and typically in the range of 40 μm. The PbSnAg die attach interface layer typically has higher thermal resistance compared to AuSi die attach interface layer both due to its lower k value (∼35 W/m ◦ K versus ∼100 W/m ◦ K) and greater bond line thickness. Ag-filled adhesive die attach is most commonly used in the manufacture of low-power RFPAs for various mobile devices and in the manufacture of general purpose amplifiers (GPA) and predriver PAs that have lower thermal dissipation. Typical bond-line thickness ranges from 25 to 50 μm. Ag-filled adhesive die attach has the highest thermal resistance compared to the other three metallurgical die attach methods both due to it having the lowest k value (1 dB change in input at 1 dB compression
Transistor wear-out
Channel current Beta Leakage current Breakdown
>20% decrease in channel current >20% decrease in beta >10 times increase in reverse current >10% reduction in breakdown voltage
Interconnect wear-out
Resistance
>10% increase in resistance
Capacitor wear-out
Leakage Capacitance
>10 times increase in leakage >10% change in capacitance/unit area
Resistor wear-rout
Resistance
>10% increase in resistance
is the specified value or datasheet limit. The use of a specification threshold as a failure criterion is easy to apply since it is clearly documented and most likely already part of an electrical measurement regimen included in the product testing routine. However, using a datasheet failure criteria is not a consistent gauge of degradation since the sample population could lie anywhere within the specification range. If the population was near the specification edge, then only a slight shift would be needed to result in a failure. If the population had excess margin, and was at the opposite extreme from the wear-out edge of the specification, then a large change in the parameter of interest would need to occur before the population would begin to exceed the data sheet limit. Thus, two samples from a common population may have the same rate of degradation, but different times-to-failure – if the failure criterion is an arbitrary specification limit. Table 10.1 shows several examples of criteria used for mechanisms and measurements selections. Whatever failure criteria is selected, the threshold must be easily discernable by the instrumentation. In most cases, it would be expected that measurement resolution should be at least 10 times better than the failure criteria. For example, if a 1mA change of channel current is equivalent to the 20% increase in channel current, then an instrument capable of resolving 100 μA (or less) would be needed to assess the failure criteria. The 10 times rule of thumb for resolving failure criteria can be more formally evaluated with a gage repeatability and reproducibility (GR&R) study of the measurement instrumentation [3]. An easy method of selecting appropriate failure criteria is one that matches with previous published results, but the best measure of failure criteria is one that correlates to customer findings and feedback.
10.4
Failure modes The failure mode of a device is a description of the symptom of failure that is observable from external evaluation. For example, a common failure mode is “output degraded.”
10.5 Failure mechanisms
451
Table 10.2 Some common failure modes and mechanisms Failure mode
Failure mechanism
Reduced output Reduced output Reduced output Reduced output Reduced output
Gate metal sinking on third-stage output transistor Q9 Electrostatic discharge damage between source and drain at transistor Q1 Die crack through capacitor C12 17 nA leakage through a gold filament between pad 14 and pad 15 Poor solder joint wetting on pad 15
The mode by itself does not provide sufficient information to understand the failure. The mode does not describe how much degradation, nor does it describe the cause of the degradation. The mode is an intermediate classification that provides a common vocabulary between the customer and supplier. Often, the customer will simply describe the failure as “the part is dead.” The failure analyst would prefer more descriptive failure modes, such as “the output power began to slowly degrade after 10 months of nominal use, and failed to meet minimum requirements in the 350th day of use,” or “the gain degraded with use and failed after long transmit sequences – the part would recover after cool down or if mechanical pressure was applied to the case of the circuit.” The failure mechanism describes what causes the degradation of the mode, preferably in terms of the physical location and the physics behind the degradation. Table 10.2 shows some examples of failure mechanisms for one particular failure mode. Although the failure mechanism may be a more specific description of a failure than the mode, the mechanism is not necessarily a description of the root cause.
10.5
Failure mechanisms Whether made from compound semiconductors or silicon, integrated circuits are susceptible to the same classes of failure mechanism. Failure mechanisms can generally be differentiated into three types of physical structure: metallization, dielectric, and semiconductor.
10.5.1
Metallization Interconnects are expected to be conductive, to be immune to electromigration, to be bondable, to be able to adhere to other circuit layers, to resist corrosion, to form good contacts, and to be patternable into the desired structure. Metallization failures result from degradation in one or more of these attributes. Silicon technology uses aluminum (with small percentages of copper and silicon added) almost exclusively for all metallization, which has some advantages. Adding about 2% silicon aids the formation of direct ohmic contacts to the silicon active regions without interdiffusion and contact spiking. The addition of small amounts of copper has become popular to increase aluminum’s immunity to electromigration as metallization feature sizes decrease.
452
Reliability
Because of its maturity, the aluminum processing used in silicon-based devices generally meets all the above mentioned criteria for metallization. There have been persistent aluminum problems with corrosion, intermetallic formation, and electromigration, but in modern processes these have been “controlled.” Compound semiconductor processing generally involves different specialized metallizations for ohmic contacts, Schottky gate formation, and interconnects (including capacitor electrodes). Naturally, each of these types of metal are designed to meet specific metallization properties, sometimes at the expense of other properties. Most commercial compound semiconductor ICs employ gold-based metals, principally with titanium and various other refractory metals. Gold/germanium is generally used for ohmic contacts. Aluminum has been used for the gates of discrete power MESFETs and for some interconnects, and some of the afore-mentioned aluminum problems have been observed. Gold-based connections avoid the possibility of the intermetallic problems that an aluminum/gold metallization introduces. Gold-based metals have therefore dominated compound semiconductor IC production. The performance of gold metallization in terms of conductivity, bondability, and adherence are probably about equal to that of aluminum used in silicon processing. These have not been mentioned as problems as long as the metal system has been primarily gold. Intermixing of gold and aluminum introduces the typical intermetallic problems such as purple plague [4]. Next, metallizations are expected to have an immunity to electromigration and resistance to corrosion. Tests on aluminum and gold metallized ICs have indicated susceptibility to both these mechanisms. As silicon geometries have decreased, aluminum electromigration issues have been alleviated by use of copper metals. However, copper is much more reactive and susceptible to corrosion, so protective metals are added to surround the copper and prevent reactions with subsequent process chemicals and with moist environments. Because of the increasing price of gold and because of the advent of copper bump technologies, some compound semiconductor metallizations are also converting to copper. Electromigration and corrosion are not considered to be primary failure mechanisms for gold interconnects but gold corrosion has been discovered in highly accelerated humidity testing. However, gold corrosion has not been reported after years of normal field use in nonhermetic packages. Metallizations should also be fairly inert with respect to other materials used in the processing. Aluminum probably has the edge in this category. Even though goldGaAs interdiffusion is essential in forming ohmic contacts, too much interdiffusion of gold, either on the ohmic contacts or the Schottky gates, is the primary wear-out mechanism in GaAs ICs. This interdiffusion may be at a “controlled” state, but the variety of existing metal schemes and process techniques would indicate there is no single, superior answer to the interdiffusion problem. Some gate metallizations are being produced from refractory metals which can withstand high temperatures without interdiffusion. But Au-Ge-type ohmic contacts, which are susceptible to interdiffusion after long high-temperature exposures, are still in widespread use. Copper is also a fast diffuser and would be detrimental to all semiconductor contacts if not separated by the moisture and diffusion barrier metals that accompany its use.
10.5 Failure mechanisms
453
Pattern definition of the metallization is performed differently for each of the metallizations. Because of the history of processing the aluminum metal used in silicon devices, dry etching is usually done on all layers. Compound semiconductor metals are usually formed by a liftoff process, at least at the ohmic, gate, emitter, base, and collector contact levels. Upper layers may be etched or plated, but sometimes liftoff is used for all metal layers. Liftoff is less complicated than the etch-back process because it usually requires no etching steps, but liftoff is a procedure that requires careful control. Both gold and copper are difficult metals to etch. Most copper patterning on silicon devices uses a chemical mechanical polishing (CMP) process to achieve planarization and patterning of their ever-decreasing feature sizes. So, aluminum, gold, and copper metallizations each have advantages and disadvantages, but all three have been proven to have adequate reliability for use in devices and ICs.
10.5.2
Dielectric The next classification of failures is related to dielectrics. For the most part, materials used to form dielectrics are quite similar, but their requirements are not. Silicon has the advantage of an ability to grow a stable, high-quality oxide which is used principally to form MOS gates and surface dielectrics. The silicon oxide is also used to isolate individual transistors and to form MOS capacitors. Above the surface of silicon, layers of nitride are generally used for interlevel dielectrics. Compound semiconductors have no useful oxide, therefore silicon oxide is often used in processing as a capping material or sometimes for interlevel dielectrics. Silicon nitride is the dielectric usually used in metal-insulator-metal (MIM) capacitors. Silicon nitride is also often used as the interlevel dielectric. The usual form of deposition is plasma enhanced chemical vapor deposition (PECVD). The silicon industry has devoted much work to the development of dielectrics because of their importance in gate formation and isolation. Compound semiconductor suppliers have taken advantage of this work even though the requirements of the dielectric are much more forgiving, because Schottky rather than MOS gates are used and the compound semiconductor substrates are self-insulating. For some compound semiconductor processes, interlevel dielectrics are not needed since airbridges are supported above the base interconnect and contact layers. Except for capacitors, some ICs could conceivably be constructed without any dielectric at all. The special challenges of power amplifier performance make the dielectric a critical consideration for silicon devices. The gate dielectrics are continuing to get thinner as silicon geomtries shrink. There is a number of gate dielectric degradation mechanisms that need to be considered in the design of a CMOS power amplifier and each can degrade during amplifier operation. There are three predominant degradation mechanisms that can result in silicon dielectric failure. Hot carrier injection (HCI) is the predominant degradation mechanism in NMOS devices whereas negative bias temperature instability (NBTI) dominates in PMOS devices. In addition, PMOS devices can also experience HCI. Time-dependent dielectric breakdown (TDDB) is a failure mechanism due to catastrophic failures of the transistor gate dielectric resulting in a hard failure of
454
Reliability
the device. TDDB failures are classified in two main categories: intrinsic and extrinsic failure modes. The extrinsic mode is a function of the defects in the oxide during the fabrication process. Usually, it results in infant mortality types of failure at a relatively low electric field of 2–4 MV/cm. The intrinsic TDDB mode corresponds to the technology capability and is a function of the transistor or capacitor design and also of the dielectric composition and quality. In the new process technologies, the intrinsic failure mode occurs for an electric field strength of >10 MV/cm. As one might expect, a variety of failure mechanisms affect this wide variety of dielectric materials, but the most important failure mechanisms are related to insulated gates and capacitors.
10.5.3
Bulk substrate material The final general physical category of failure mechanism involves the substrate material. The difference in resistance and mobility gives compound semiconductors some performance advantages in this area compared with silicon. The semi-insulating properties of compound semiconductors have, for the most part, eliminated first-order problems with isolation and latch-up which are constant nuisances for silicon. However, the complexities of compound semiconductor epitaxial layers make their transistors susceptible to traps, and circuit interactions called “backgating” or “sidegating” have been discovered. Semi-insulation may not be quite enough to prevent substrate conduction for microwave and radio frequency circuits, but many performance issues are significantly reduced compared to silicon devices. Of the three physical classifications for failure mechanism, the substrate is arguably the least significant for reliability issues.
10.5.4
Schottky gate FET failure causes The primary failure mechanisms for silicon technology generally involve gate oxide integrity, electromigration, corrosion, and isolation while gallium arsenide problems center around interdiffusion of metallizations. The FET is most often the center of attention in compound semiconductor circuits. Testing has revealed degradation of channel resistance and decreasing channel current as clear failure modes of metal semiconductor FETs (MESFETs) and high-electron mobility transistors (HEMT) at the end of their expected lifetimes. Early GaAs MESFETs suffered from direct channel burn-out. The shorting of the channel from gate-to-drain, gate-to-source, and drain-to-source resulted from a lack of consistent processing and poor substrate material. More recent studies have found this shorting to occur only when MESFETs are overstressed in terms of current density, voltage breakdown, and/or excessive power dissipation. Another reported failure mechanism which could often account for increased channel resistance and decreased saturation current was ohmic contact degradation. Interdiffusion of gallium and gold was a problem for manufacturers a few years ago. This interdiffusion often caused increased effective channel resistance and contact degradation. As manufacturers standardized on Au-Ge-Ni ohmic materials, instead of incorporating
10.6 Failure distributions
455
Cr or In, this problem subsided. Anecdotal evidence also seems to suggest that the deposition technique is also a key to stable ohmic contacts. Deposition of ohmic metals serially in distinct stacks has reportedly been more stable than ohmic contacts which are deposited simultaneously or from a precombined source of metals. As compound semiconductor development has progressed, the ohmic contacts have become less of a problem. Investigations into FET degradation on a device physics level has found that changes in pinch-off and/or transconductance often occur at the end of life and cannot be explained by ohmic contact degradation. Analysis generally also indicates an effective reduction of carrier concentration in the channel of the FET. At least three possible mechanisms could be responsible for this predominant failure mode. Changes in the carrier concentration of the FET can be caused by compensation from gate atoms, diffusion of carriers out of the channel, or effective reduction of the channel depth by the encroachment of the gate. Compensation can be measured by DLTS (deep level transient spectroscopy). Diffusion can be assessed by the effects of bias during life-testing, and movement of the gate into the channel can be confirmed by Auger or other destructive analytical techniques. The effects of burn-out, ohmic contact degradation, carrier compensation, carrier diffusion, or gate metal interdiffusion is specifically dependent on the manufacturer’s process. It is possible that several mechanisms at work simultaneously.
10.6
Failure distributions One of the keys to understanding reliability is an understanding of failure distributions. Any particular sample of devices will have a unique type of failure signature for each mechanism that causes degradation. Analysis of these distributions is necessary to characterize each type of failure mechanism, and to eventually predict expected lifetime for all the relevant environmental conditions. Separation of failure distributions is not always easy. When multiple failure mechanisms are causing degradation, it may be easier to physically separate the effects by breaking down a circuit into each of its elements. Testing of individual transistors, capacitors, and resistors can expose a single failure mechanism that is easier to analyze than a hodge-podge of factors causing ICs to degrade. However, further breakdown of the individual elements into even simpler individual contacts and interconnects, etc., may help to reveal more insight into the cause of the problem. The measurement of reliability for semiconductors generally involves failure rates. Traditionally, several classifications of failure types have resulted from the failure experience of large systems during their use. This experience is commonly translated to the “bathtub curve” [5] shown in Figure 10.1. Whether measuring computers, automobiles, or even human lifetimes early, random, and wear-out failure types are generally expected. Over many years experience, and across a wide variety of mechanical and electronic components, machines, and systems, people have measured empirical population failure rates as a function of time. If the population is large enough, each study will produce
456
Reliability
Figure 10.1 Traditional reliability “bathtub” curve.
Figure 10.2 Human mortality rates (in %) for males and females in the USA c.1990. Source: “Age-specific death rates from the human mortality database (HMD)” from http://www.mortality.org.
results which mimic the human results shown in Figure 10.2. and are generalized by a graph with the shape of a bathtub shown in Figure 10.3. Because of the similarities in shape of these failure rate curves, the curve has become widely known as the “Bathtub” curve. The initial region that begins at time zero when a customer first begins to use the product is characterized by a high but rapidly decreasing failure rate. This region is known as the early failure period and is also referred to as infant mortality period (from the actuarial origins of the first bathtub curve plots). Burn-in can be used as a means of weeding out infant mortalities and this is discussed in Appendix 10.1.
10.6 Failure distributions
457
Figure 10.3 Alternate generalized bathtub curve composed of a “defective” failure distribution and a “wearout” failure distribution. The combined distributions result in a population exhibiting the traditional bathtub shaped failure rate.
Next, some systems have a period where the failure rate “levels off” and remains roughly constant (and hopefully very low) for the majority of the useful life of the product. This long period of a low failure rate is usually identified as the “random” failure period, and is sometimes called the stable failure period. The random failure period characterizes the useful life of the system where the lowest failure rate occurs. Random failures may be caused by infant mortality failure mechanisms which had extraordinary long lives or by devices which wear-out prematurely. Random failures may also be caused by misapplication of devices or by latent damage caused during manufacturing and use. Additional application problems have been noted, such as electrostatic discharge and failure to adequately heatsink higher power devices. As with infant mortality failures, inherent random failures eventually achieve undetectably low levels during the maturation of a new technology. Finally, if units from the bathtub curve population remain in use long enough, the failure rate begins to increase as materials wear out and degradation occurs at an ever increasing rate. This is known as the “wear-out” failure period. Gradual degradation in device parameters is typical for amplifying devices when subjected to extremely accelerated life-test conditions. Occasionally, this degradation leads to functional failure, but in all cases, catastrophic failure mechanisms are rare except when devices are overstressed, either by application or design. For the system designer, early, random, and wear-out failure risks must be considered for the selection of each component. The infant and random failure periods are dependent on device processing, testing and screening – and those risks should abate as technologies mature. It is debatable as to whether the bathtub curve represents a single distribution or an accumulation of multiple distributions. When examining semiconductors under various accelerated aging methods, the early and wear-out distributions are often distinguished. Ideally, the burn-in conditions would exclusively accelerate the early failure mechanisms without shortening the useful life of the device by accelerating the wear-out mechanisms.
458
Reliability
After 4380hrs at 260 °C
Typical FET Curve Idss = 94 mA Rds = 8.4 ohm
Baseline FET 3
Vp = – 1.310 V
10 mA
Idss = 19 mA Rds = 43.75 ohm Vp = –0.818 V
Aged FET 3 10 mA
500 mV
500 mV
200 mV
200 mV
per step
per step
gm = 50 m
gm = 50 m per div.
per div.
Reference Device (time = 0 hours)
Extreme Wearout after 26 week life test.
Figure 10.4 Electrical characteristics of MESFET degradation.
However, if the wear-out mechanisms have margin to spare, then the effect of burn-in may be negligible. For semiconductors, the failure rates of the bathtub curves are depicted with a log scale. The constant failure rate region may be simply the sum of the tails of the early and wear-out distributions. It is expected that systems spend most of their lifetimes operating in this very low failure rate portion of the bathtub curve, so it is sometimes called the “intrinsic” region. The wear-out failure distributions should not be detected until after the warranty lifetime of the product unless some form of accelerated life-testing is employed.
10.7
Acceleration factors
10.7.1
Thermal acceleration One of the primary failure mechanism for FETs is “sinking gates.” Sinking gates are caused by gate metal interdiffusion into the channel. This interdiffusion produces shifts in several MESFET parameters as the effective channel thickness is reduced. The largest parameteric change caused by gate sinking is in channel current. Therefore, a 20% change in channel current may be arbitrarily selected to define a FET failure. In addition, as the gate sinks, channel resistance increases and the magnitude of the voltage required to pinch-off a FET is reduced (this usually means pinch-offs are more positive). The sinking gate failure mechanism is gradual rather than a catastrophic failure mechanism. It is also self-limiting in a sense because as the channel current decreases so does the power in the FET and thus the temperature is lowered; causing the gates to sink more slowly. An example of the electrical and physical effects of extreme gate sinking is shown in Figures 10.4 and 10.5. Figure 10.4 shows the curve tracer characteristics for a typical MESFET and for a MESFET after exposure to 4380 h at 260 ◦ C under bias and RF stimulus. Identical
10.7 Acceleration factors
459
Figure 10.5 Focused ion beam (FIB) cross-sections of reference (left) and degraded (right) MESFETs subjected to 260 ◦ C lifetest. Gate metal width is approximately 0.5 mm. Note: the electrical parameters of these two FETs match those in Figure 10.4.
degradation was observed at the same temperature without bias or RF drive. This degradation is well beyond the 20% change failure threshold, but it was purposely induced to ensure that an accompanying physical change could be detected. The physical change which caused this electrical change is shown in Figure 10.5. As with the electrical data, a virgin gate is shown as a reference. Both of these cross-sections were made using a focused ion beam. The movement of the metal gate at the semiconductor surface is dramatic on the degraded transistor. Some voiding is also present in the degraded gate, probably because of the mass of material which has moved into the transistor channel. This is an extreme failure which resulted in a 2.2 dB change in the insertion loss of the MMIC, but remember, this occurred at 260 ◦ C. In a similar life-test at 250 and 225 ◦ C, less than 0.8 dB and 0.08 dB change occurred, respectively, for the same 4380 h test duration and similarly stressed MMICs. Operation at the maximum rated temperature (150 ◦ C) would be expected to exceed 2000 years before a 1 dB change could be observed. This expected longevity of sinking gates is acceptable in terms of common reliability goals, and is not considered as a threat to device lifetimes under normal operating conditions. To further analyze the sinking gate mechanism, an example of individual transistor life-testing will be used. The changes in channel current during a six month, 245 ◦ C life-test are shown in Figure 10.6. An arbitrary failure criterion of a 20% Ids reduction was chosen because in the amplifiers using this transistor, a 20% drop in channel current resulted in a 1 dB drop in output power. As shown in Figure 10.6, the time to failure is not constant. In fact, no failures occur in this sample until 1700 h have elapsed. The times to failure follow a distribution in time. If time is plotted on a log scale and failure accumulation on a normal scale, then a straight line results, and then a distribution can be characterized with just two simple parameters, a point and a slope. The result of plotting the time to failure data in Figure 10.9 is shown on a lognormal plot in Figure 10.7. The first parameter used to characterize this distribution is the median life (ML). It is determined by the time elapsed to cause half of the samples to become failures, or approximately 4770 h for this life-test. The median life is a point selected as a convenience, it has no particular significance in terms of the distribution, but it is a popular convention to select the median life since there is no zero on the normal scale
Degradation (% Change in Idss)
Reliability
+10 0.0 –10 –20
Failure Criteria
245 °C Life Test
–30 –40
1.0
0.5
1.5
2.0
2.5
Stress Duration (Thousands of Hours) Figure 10.6 Degradation in channel current for a 245 ◦ C FET lifetest. A total of 24 individual transistors were tested for 6 months, only the 12 fastest degrading samples are shown here for the first 2600 h of the accelerated lifetest.
100,000 Sigma
245 °C 10,000 1,000
Median Life
Test Time (Hours)
460
100 10
Normal Scale
1 10%
50%
90%
Cumulative Failure Percentage
Figure 10.7 Lognormal plot of time to failure for a 245 ◦ C FET lifetest.
so an axis intercept is not possible. During conversions and mathematical curve-fitting, the 50% failure point becomes the intercept because the normal scale is symmetric about it. Once the median life is selected as a reference point, the distribution can be fully described with a slope parameter, called sigma. Sigma is sometimes called the distribution’s “shape parameter” and it physically defines the spread of the distribution. The sigma for the data in Figure 10.7 is 0.90. Large sigmas (high slopes) indicate the distribution generates failures over a relatively long span of the test. For any particular failure mechanism, the sigmas should be similar, regardless of the stress temperature or resulting median lifetime. In order to predict lifetimes at lower stress i.e., lower temperature, then the acceleration factor of the stress must be determined. By common definition, the acceleration factor is the median life at low temperature divided by the median life at higher temperature.
10.7 Acceleration factors
100,000
Test Time (Hours)
10,000
Failure Criteria: 20% Idss Change
461
245 °C 260 °C
1,000
275 °C 100
290 °C
10 1
310 °C Biased at Idss 10%
50%
90%
Cumulative Failure Percentage Figure 10.8 Lognormal plot of degradation in channel current for five FET lifetests at different temperatures.
Acceleration factors for thermally accelerated failure mechanisms are typically found to follow the Arrhenius equation. Ea 1 1 − − Acceleration Factor = e K T2 T1 (10.1) where Ea is Activation Energy (eV), K is Boltzmann’s constant (8.61423 × 10−5 eV), and T is absolute temperature (K). The median lives are determined by the methodology described in the previous section (using the lognormal distribution) and the temperatures are the life-test temperatures (converted to K). The remaining unknown value is the activation energy. With just two temperatures, the activation energy can be determined by direct substitution. If lifetests are performed at more than two temperatures, then the activation energy can be determined by performing a least squares linear fit as shown in the following example. Figure 10.8 shows the lognormal failure distributions for life-tests conducted at five different temperatures of 245, 260, 275, 290, and 310 ◦ C. These are all plotted using the failure criteria of 20% change in channel current – caused by the sinking gate mechanism. Whereas the transistors could last 4770 h at 245 ◦ C, they are degrading beyond the 20% limit in only 7.4 h at 310 ◦ C. Thus, lifetime is reduced by more than three orders of magnitude for a temperature increase of just 65 ◦ C. It is clear that the sinking gate mechanism is highly accelerated by temperature. Figure 10.9 shows a graph of median life versus junction temperature using a least squares linear fit. The activation energy, which in this case is 2.56 eV, is the slope of this line divided by K. Compared to failure mechanisms for silicon devices, which have activation energies from 0.3 to 1.2 eV, this activation energy is extremely high (remember, activation energy is an exponential term). Higher activation energy implies faster degradation in MTTF with increased temperature. Although high, it is not unexpected since the measured activation energy for the diffusion of Au and Ti in GaAs is 2.64 eV and 2.93 eV,
462
Reliability
Median Life (hours)
108
Biased at Idss
10K Years
107
1K Years
106
100 Years
2.56eV
105
10 Years
104 103 102
10 1 Hour
1 Year 1 Month 1 Week
Failure Criteria: 20% Idss Decrease 75 85 100
125
1 Day
150
175 200 225 250
300
Temperature (°C) Figure 10.9 Arrhenius-style plot showing median lifetime versus temperature extracted from Figure 10.8.
respectively, which is similar to the activation energy of sinking gates. Very similar results have been demonstrated for various FET devices, including pHEMTs. Now that a method of determining thermal acceleration factors has been defined, the previous question about predicting when failures will occur can be addressed. If the maximum specified operating peak hot spot temperature of a FET in a power amplifier application is limited to 150 ◦ C, then Figure 10.9 shows the projected median life for FETs at 150 ◦ C is about 1 billion hours, or 114,000 years! This prediction indicates that the sinking gate failure mechanism is not likely in need of improving, at least for the next few thousand years. One reason to use such a robust example to describe distributions and acceleration factors is to further delineate the difference between accelerated failure mechanisms and natural failure mechanisms. The accelerated test will often find the wear-out failure mechanism for the respective accelerated conditions, but the customer will experience failures caused by defects. We would not expect customers to ever see a sinking gate, and in fact they have not.
10.7.2
Current acceleration One of the principal wear-out failure mechanisms is electromigration. Electromigration is the mass transport of a metal due to the momentum transfer between conducting electrons and diffusing metal atoms. Discovered more than 100 years ago, electromigration became a concern only when the relatively severe conditions necessary for operation of integrated circuits made it painfully visible. Although electromigration exists whenever current flows through a metal wire, the conditions necessary for electromigration to be a problem simply do not exist on a macro scale. In bulk wires, such as those used for home appliances, the maximum current density is about 10,000 A/cm2 Any current density that exceeds this value will produce enough heat to melt a metal wire. However,
10.7 Acceleration factors
463
the driving force from electrons colliding into diffusing metal atoms would be insufficient to make electromigration a significant problem at those current densities used for industrial power distribution. All of this changed in 1966 when the integrated circuit was invented. Electromigration was rediscovered by semiconductor engineers. In circuits, electricity is conducted by interconnects that are miniature thin-film stripes that are capable of dissipating heat from very high current densities. Thin-film conductors can withstand current densities at least two orders of magnitude greater than traditional bulk wires. This allows current densities of nearly 106 A/cm2 without building-up enough heat to melt the interconnect. At current densities above 10,000 A/cm2, electromigration becomes a significant degradation mechanism. The first integrated circuits were constructed with metal lines made of pure aluminum, a material with a low melting temperature, which implies fast diffusion at low temperatures. Thin-film conductors on the semiconductor scale contain small grains with many grain boundaries that can be conduits for even more rapid diffusion. This combination of high current density and fast diffusion at low temperatures was disastrous for early circuits. Semiconductors were supposed to be very reliable compared to vacuum tubes, but when the first ICs were placed into service, they failed within weeks. The shock to the industry forced everyone to become an expert in understanding the electromigration failure mechanism. Since those early days the electromigration mechanism has not gone away, but it is now under control. Electrons flow through a metal film and collide with metal atoms. The collisions produce a force from momentum exchange on the metal atoms in the direction of electron flow for n-type materials (opposite for p-type materials). This force causes the metal atoms to move and this is termed electromigration. Electromigration is only significant at high current densities. The magnitude of the electromigration force is proportional to the current density, but Black [6] showed that electromigration failures have an inverse square dependence on current density J rather than the expected purely inverse dependence and that it is given by H t50 = A J −2 e( kT )
(10.2)
where t50 is the median time to failure in an ensemble of samples, A is a constant that needs to be empirically determined, and H is the activation energy for failure. Equation (10.2) is known as Black’s Law and has proven to be adequate even to the present day. To ensure that electromigration failure does not occur in the field, we need to limit the current density such that electromigration failure will not become significant until long after the projected useful lifetime of the circuit. This is a function of not only the current density in the metal lines and contacts, but also of temperature and other variables, such as interdiffusion, mechanical stress and the grain structure of the conductor. Interconnects and resistors also suffer from electromigration but the dependence on current density is no longer a pure inverse square law relationship. Thus, Black’s equation is generalized to median life =
Area ( Ea ) e kT Jn
(10.3)
464
Reliability
Median Life (Hours)
106
Plated Gold 250 °C n=4
105
NiCr Resistor 200 °C n=3
104 103 Ohmic Contact n=3.5 203 °C
102
n=1.5 Deposited Gold 300 °C
10 1 0.1
1.0 Current Density (M Amps/sq. cm.)
10
Figure 10.10 Current density acceleration factors for example metals used in amplifiers. Slope is
the current density exponent identified as “n” in equation (10.3).
30
60 40 20 0
40
Jc = 101 kA/cm2
100 80
Ic (mA)
Ic (mA)
120
20 10
0
2000
4000
6000
Time (Hours)
8000
0
Jc = 34 kA/cm2 0
2000
6000 4000 Time (Hours)
8000
Figure 10.11 L-Band HBT biased high-temperature operating lifetest degradation at a junction
temperature of 250 ◦ C and at two different current densities for transistor samples having 2.2 × 45 μm2 active area.
where J = current density, n = current density exponent, Ea = activation energy, K = Boltzmann’s constant, and T = temperature. Just as with the Arrhenius equation, the electromigration effects on lifetimes can be determined using a graphical approach. Figure 10.10 shows the graphed results for several example metallizations life-tested with different current densities applied. We can follow the same failure distribution and acceleration factor graphing technique for electromigration as we did for the metal interdiffusion mechanism of the sinking gate and extend the effect of current density into the realm of transistors. Many published results on HBT amplifiers have demonstrated that collector current density has a significant impact on transistor degradation. Most HBT suppliers recommend current density levels between 20 KA/cm2 and 50 KA/cm2 [7]. Degradation data for an L-Band HBT amplifier is shown in Figure 10.11. Plotting the time to failure versus the collector current using the data in Figure 10.11 results in the lognormal plots of the degradation distributions shown in Figure 10.12. Finally, the median times to failure for each HBT life-test done at different current densities as determined from Figure 10.12 will produce an estimate for the current density exponent if plotted against current density as shown in Figure 10.13.
10.7 Acceleration factors
100000
Time (Hours)
Time (Hours)
10000
465
1000
100
10000
1000
Tj = 250 °C Jc = 101 kA/cm2 10
10
2
30 50
70
90
98
Tj = 250 °C Jc = 34 kA/cm2 100 2
Cumulative % Failure
10
30 50 70
90
98
Cumulative % Failure
Figure 10.12 250 ◦ C Lognormal failure distributions of L-Band HBT biased HTOL degradation at
two different current densities.
Median Life (Hours)
106 HBT at 250 °C
105 104 n=1.5
103 102 10 1 10
100 Collector Current Density (K A/cm2)
1000
Figure 10.13 Current density exponent determination for 250 ◦ C L-Band HBT biased HTOL
degradation.
This plotting analysis exercise using Figures 10.11 to 10.13 demonstrates several important results. First of all, current density is an accelerating stress that degrades transistors in a similar way to interconnect metals. Second, HBT transistor reliability may be predicted by multiple applied current densities at constant temperature. Finally, HBT current handling capabilities are about an order of magnitude less than those of interconnects for roughly the same temperatures. These findings might indicate that even though HBTs are accelerated by thermal failure mechanisms, current density may be a more useful acceleration tool for measuring the reliability of these transistors.
10.7.3
Voltage acceleration factors (MIM capacitors are an important component of any RF circuit. As such, their long term reliability is an integral part of the overall dependability of an RF device. However, the accelerating stress for capacitors is almost entirely voltage. So unlike electromigration
466
Reliability
degradation, the effect of temperature as an accelerating stress is almost negligible. By employing the method of ramped voltage testing, almost any capacitor structure can be used to assess dielectric reliability. However, to measure defect density, larger capacitors are preferred. The expected failure mechanism for MIM capacitors is determined by measuring the TDDB. Ramped voltage testing is a viable process monitoring methodology which can be easily and effectively realized by on-wafer probing. Although thin dielectrics are used as gate dielectrics in silicon technologies, for the most part silicon nitride (SiN) capacitors with films less than 100 nm thick are uncommon in the compound semiconductor industry. However MIM capacitor thicknesses are expected to shrink, albeit at a much slower rate than gate dielectrics. For this example, we will examine a 50 nm thick silicon nitride capacitor. The bottom and top plates of these capacitors generally consist of sputtered gold metallizations. The bottom plate is built using the first local interconnect layer while the top plate is a restricted metal layer used solely for capacitors. The silicon nitride is a PECVDdeposited film with a dielectric constant of 6–8. These thin-film capacitors allow higher capacitance in a smaller chip area. While thinner nitride films are beneficial for on-chip density, they set a higher bar for manufacturability and long-term reliability. It then becomes essential to continuously monitor the quality of thinner nitride films and the over all capacitor fabrication process. Silicon nitride films are often categorized by their corresponding breakdown voltage. Different films have different breakdown voltage characteristics. In general, thicker nitride films exhibit higher breakdown voltages and are thus more forgiving of process and film variations. Thin MIM capacitors are more susceptible to deviations from the normal film quality as well as defectives introduced by the fabrication process. The robustness of a nitride film is generally characterized by an associated TDDB graph [8–10]. This is often used to predict a capacitor’s lifetime at a given voltage. Many publications on capacitor reliability have demonstrated the use of both constant voltage and ramp-to-breakdown methods in silicon nitride lifetime studies. The capacitance per unit area and leakage current at a set voltage are the typical parameters used as a figure of merit for MIM capacitors. The voltage-ramping of a capacitor to breakdown provides a means of monitoring capacitor quality, defect density, and allows TDDB analysis to predict MIM film robustness. Ramped TDDB studies are an accepted method of benchmarking capacitor reliability in today’s compound semiconductor industry. The capacitors used were manufactured using a mask set with MIMs of various sizes ranging from 1 × 103 μm2 to 8 × 105 μm2 . There were 6100 MIM capacitors on a wafer that could be individually probed and voltage ramped. Example ramping results on a population of capacitors is shown in Figure 10.14. When the results are ordered or plotted on a probability axis, the population of intrinsic and extrinsic devices is clearly obvious. Failure is defined to be when the leakage current exceeds 10 mA. This test is destructive. Voltage ramping is a powerful tool in the identification and classification of capacitor defects. For the ramp to breakdown measurements on large area capacitors, a ramp with voltage steps of 1 V was selected for convenience. The ramp rate was then adjusted
10.7 Acceleration factors
467
Process Variation 110
25 K um2 Capacitor
100
Intrinsic capacitor population (Good Capacitors)
Ordered Capacitor Data
Ordinal
90 80 70 60 50 40
Defect Density
Extrinsic capacitor population (Defect-driven)
30 20 10 0 0
5
10
15
20
25
30
35
40
45
50
55
60
Capacitor Fail Voltage (Volts) Figure 10.14 Ramp to failure data on a population of 25,000 μm2 capacitors.
to compensate for the size of the capacitor under test. Several intrinsic test capacitors were chosen and ramped to breakdown with at least two different voltage ramp rates to characterize the electric field acceleration factor, δ. Once this is known, the TDDB performance of the silicon nitride film can be predicted. For thinner SiN films the small area capacitors exhibit a small extrinsic population. The data was collected with a ramp that used 0.25 V steps. Based on these observations, the 5 × 103 μm2 capacitor was selected as the main test vehicle for ramped TDDB studies. In addition to limiting the maximum size to avoid extrinsic defects, a conscious effort was made to ensure a purely intrinsic population by including only voltages between the 5th and 95th percentile. Statistically, this did not affect the median voltage for each ramp rate but significantly improved the standard deviation of the data. The Table 10.3 shows the resulting median and standard deviation when the exclusion is applied to the data collected on various capacitors. Having selected an appropriately sized test capacitor and established a methodology to ensure an intrinsic population of capacitor breakdown voltages, several voltage ramp rates were investigated. Voltage steps of 1 V, 0.25 V, 0.1 V were utilized in combination with different time steps that varied from 5 ms to 200 s to achieve the desired ramp rates. Table 10.4 summarizes the different voltage and time steps that were used in the course of this investigation. This resulted in a broad distribution of voltage ramp rates. Early on it was evident that selecting the height of the voltage step dictated the granularity of the data. As such the use of steps of 1 V misleadingly quantized the distribution of capacitor breakdown voltages. The 1 V voltage step also necessitated longer time steps to achieve reasonable ramp rates negating one of the benefits of ramped voltage testing. Using this larger step size presented challenges to the test instrumentation. For
468
Reliability
Table 10.3 Comparison of median and standard deviation
Ramp rate
Cap size
Median
Std dev
Median exclude
Std dev exclude
0.5 V/s
1 K um2 5 K um2 10 K um2
46.75 46.50 46.00
0.88 0.92 1.32
46.75 46.50 46.00
0.47 0.45 0.47
5.0 V/s
1 K um2 5 K um2 10 K um2
51.25 50.25 50.00
0.81 2.12 0.73
51.25 50.25 50.00
0.43 0.45 0.36
50.0 V/s
1 K um2 5 K um2 10 K um2
54.50 54.00 53.75
7.34 1.05 0.94
54.50 54.00 53.75
0.38 0.42 0.37
Table 10.4 Voltage ramp rates Voltage step (V)
Time step
Ramp rate (V/s)
0.1
20 ms 40 ms 400 ms 1s
5.00 2.50 0.25 0.10
0.25
5 ms 50 ms 500 ms
50.00 5.00 0.50
1
20 ms 200 ms 2s 20 s 200 s
50.00 5.00 0.50 0.05 0.005
several combinations of time steps and capacitor sizes, the test system was erroneously reporting a higher voltage than what was actually being applied to the capacitor. For the TDDB studies, it was determined that smaller step sizes are more useful. Voltage steps of 0.1 V and 0.25 V provide a broad distribution of voltage ramp rates with reasonable test times. The selected voltage and time step combinations were successfully implemented by a parametric test system. Besides capacitance and breakdown voltage, the leakage through a capacitor is also measured. This is usually done at a single voltage and a shorted capacitor would be easily evident. The data collected from this measurement can be interpreted into a defect density number at that voltage. But by doing so, the only extrinsic defects that can be detected would be those which short the capacitor at voltages lower than or at the test voltage. The advantage of a ramped voltage test would be the ability to detect defects
10.7 Acceleration factors
469
99.9
Size 25 K um2 50 K um2 100 K um2 200 K um2 400 K um2 800 K um2
99
Population (Percent)
95 90 80 70 60 50 40 30 20 10 5 1 0.1 0
6
12
18
24
30
36
42
48
54
60
Ramp Failure Level (Volts) Figure 10.15 Capacitor breakdown voltage for various area capacitors.
at every voltage step. Its only disadvantage is that it is a destructive test which damages the capacitor. Figure 10.15 shows all the data collected from one of these reliability test wafers sorted by capacitor size. For the ramped voltage TDDB studies, three different wafers were used to collect the necessary data. Two of the wafers came from a single fabrication lot while another wafer was taken from a separate lot. All 50 nm capacitors measured in this study had the same SiN MIM film. This exercise was done to make certain of the consistency of the ramped voltage method across material. Figure 10.16 shows the ramped voltage data collected for 5 × 103 μm2 MIM capacitors using voltage steps of 0.1 V and 0.25 V. Ramp rates of 0.1 V/s, 0.25 V/s, 0.5 V/s, 2.5 V/s, 5 V/s, and 50 V/s were used. Table 10.5 summarizes the median and standard deviation of the capacitor breakdown voltage for the material subjected to the ramped voltage test. Using the data from Table 10.4, the electric field acceleration factor δ can be calculated using any combination of two different ramp rates and median failure voltages using the equation below: 1 ln Rate Rate 2 δ= (10.4) E1 − E2 The results of this calculation are shown below in Table 10.6. Different combinations of ramp rates and median failure voltages result in a consistent value for the electric field acceleration factor. This is also seen to be relatively constant when tested across different wafers.
Reliability
Table 10.5 Capacitor breakdown voltage
Material
Voltage step
Lot A, Wafer 1
Ramp rate
Median
Std dev
0.25 V
0.5 V/s 5.0 V/s 50.0 V/s
46.50 50.25 54.00
0.64 0.68 0.59
Lot B, Wafer 2
0.25 V
0.5 V/s 5.0 V/s 50.0 V/s
47.50 51.25 55.00
0.76 0.89 0.76
Lot B, Wafer 3
0.10 V
44.4 49.3 49.6 50.7
0.84 0.92 0.79 0.83
0.1 V/s 0.25 V/s 2.5 V/s 5 V/s
Table 10.6 Electric field acceleration factor δ
Ramp combinations Combination 1 Combination 2 Combination 3 Combination 4 Combination 5 Combination 4
Lot A, Wafer 1 0.25 V step
Lot B, Wafer 2 0.25 V step
Lot B, Wafer 3 0.10 V step
3.07E-08 3.07E-08 3.07E-08
3.07E-08 3.07E-08 3.07E-08
3.15E-08 3.12E-08 3.10E-08 3.11E-08 3.10E-08 3.05E-08
99.9 99
Population (Percent)
470
5 K um2 Capacitors
5.0 V/s 5.0 V/s
0.1 V/s
95 90 80 70 60 50 40 30 20 10 5 1 0.5 V/s
50.0 V/s
1.0 V/s 2.5 V/s
0.1 42
44
46
48
50
Ramp Failure Level (Volts) Figure 10.16 Ramped voltage data at various ramp rates.
52
54
56
10.7 Acceleration factors
471
1014 1013 1012
Time To Failure (Seconds)
1011 1010 109 108 107 106
Me
dia
105 104
n
103 102 10
100
1
pp
0.1 10–2
m
10–3 10–4
0
5
10
15
20
25
30
35
40
45
50
55
Applied Voltage (Volts) Figure 10.17 Lifetime prediction for capacitors relative to applied voltage.
Once the electric field acceleration factor is known, predictions of capacitor lifetimes can be made. Since all capacitor ramp measurements were made at room temperature, the TDDB equation does not need to include the Arrhenius portion, so lifetimes can be represented by Time to failure = e−δ E
(10.5)
where E is the electric field. Figure 10.17 shows the resulting lifetime prediction for capacitors with a constant voltage applied. Note that the median time to failure is plotted as well as the time to the first 100 parts per million (1 in 10,000 capacitors). Ramped voltage testing of capacitors across a wafer allows a process monitoring methodology that facilitates the improvement of capacitor yield and long-term reliability. Capacitor defect densities at a suitable voltage and capacitor operating lifetimes can be measured and monitored for a particular nitride film thickness. Just as current density is an important stress for HBT devices and ICs, applied voltage has been found to accelerate failure mechanisms in GaN HEMT devices. AlGaN/GaN HEMTs were investigated [11]. Standard life-tests were conducted at drain-to-source biases of 15, 20, 25, and 30 V at 10 GHz drive with the devices driven 3 dB into compression at room temperature. Under these stress conditions, the change in output power was monitored for 20 h and the results are shown in Figure 10.18. The degradation distribution of each group of the transistors was analyzed, and Figure 10.19 shows the resulting prediction of time to failure (1 dB failure criteria) for the respective channel voltages that were applied. The logarithmic relationship of lifetime to applied voltage is very similar to those found for capacitors. These HEMT results indicate that applied voltage with RF drive provides a viable stress for life-testing of AlGaN/GaN HEMTs. No temperature acceleration is needed to examine this degradation mechanism. In fact, a negative activation energy was observed
472
Reliability
0.2
Change in Power Out (dB)
0.0 –0.2 –0.4 Vds = 15 V –0.6 Vds = 20 V –0.8
Vds = 25 V Vds = 30 V
–1.0 –1.2 0
5
10
15
20
Stress Time (Hours) Figure 10.18 Change in output power for AlGaN/GaN HEMTs stressed with four different
channel voltages and under 3 dB compression at room temperature.
Time to 1 dB loss of Pout (hours)
10000
1000
100
10
1
30
25
20
15
Vdg in Volts Figure 10.19 Time to fail versus applied voltage to the transistor.
in thermal life-tests on these devices. Results are consistent with a hot carrier induced failure mechanism.
10.7.4
RF bias acceleration One aspect of accelerated reliability stress that is relatively new is RF biasing. Testing of individual transistors with RF bias has been conducted from time-to-time, but the concept of RF drive as a wear-out mechanism is new. Past RF drive tests have included
10.8 Reliability predictions (MTBF, MTTF, FITs, etc.)
473
6 5 Thick Gate Oxide 1dB compression
Projected Degradation (% Id sat)
7
4 3 2 1 0 –25
Thin Gate Oxide –20
–15
–10
–5
0
5
10
15
5 Year RF Input Drive (dB m) Figure 10.20 Model of % degradation of Ids after five years versus RF input power drive for thick
and thin NMOS devices. Note, this integrated power amplifier is at 1 dB compression at an applied input power level of +8 dB m.
temperature as the primary method of acceleration. Even though some RF drive conditions have added considerable power (and temperature) the tests would keep RF stimulus constant and conduct stress testing with multiple temperatures. As RF power continues to increase in commercial applications – such as for cell phones – interest in RF acceleration also increases. Some cell phone PA module qualification testing has recently shown that filters subjected to high RF drive levels will degrade while the active parts of the module seem to be relatively unaffected. The design models for the hot carrier injection failure mechanism in CMOS devices has progressed enough that a recent model was utilized to predict the degradation of a radio chip under various RF inputs [12]. The authors determined that the primary wear-out mechanism in their integrated power amplifier would be caused by hot carrier injection since the RF transistors in the amplifier core are NMOS devices configured in a cascade structure which was susceptible to Vds swings which were modeled for various RF drives and also for two different oxide thicknesses. Figure 10.20 shows the projected degradation after five years of stress. As more RF biased life-testing is conducted, perhaps more reliability relationships will be discovered for use in predicting lifetimes.
10.8
Reliability predictions (MTBF, MTTF, FITs, etc.) It is a basic belief of reliability engineers that failures must be generated to quantify product reliability. Failures are required to identify the root causes of reliability problems, or to evaluate the weakest link of an IC so that changes can be made to improve the
474
Reliability
reliability. Failures also provide the reference point for future comparisons. If life-tests are performed before and after a process change, and they both result in zero failures, there’s no way to decide if the process change improved or impaired the reliability. Most importantly: without fallout, a failure distribution cannot be determined. It is auspicious that the published work on amplifier reliability contains many thousands of failures. Just any failure will not do, however. The failure must be representative of degradation that occurs in actual use. To ensure the usefulness of the failures generated, a five-step procedure for evaluating devices is recommended: Step 1. Operational analysis. Step 2. Thermal analysis. Step 3. Step stress test. Step 4. Life-test. Step 5. Acceleration factor test. The five steps begin with an operational analysis. The operational analysis is simply an investigation into the normal operating conditions of a particular device. During the analysis, the proper biasing techniques to cause the device to be in a representative state are investigated. The operational analysis includes developing fixturing which can maintain the device in its desired state and engineering a technique or methodology for electrical measurements which will ensure repeatable and reproducible results throughout all the subsequent testing. Part of this first step includes an evaluation of the device as configured for testing. Specific checks are conducted to ensure that the device does not oscillate or otherwise switch into an anomalous state, especially at high temperature. Power supply interactions are also investigated as to the effects of proper power-up and power-down sequencing, overshoot at turn-on, soft shut-off, and the effects of glitches or other interruptions during operation. The second step in finding representative failures is a thermal analysis. This is an absolutely necessary step. Determining device temperatures is a key part of any reliability study, especially if acceleration factors are to be determined accurately. There are several possible methods for measuring temperature, each with different advantages and disadvantages. Temperatures of the entire IC package environment are best evaluated from case to hotspot. The hotspot temperature is important for accurate calculations, but the case is the best reference point for a packaged device. It has been determined that peak hotspot temperatures are the least ambiguous parameters to define because environmental effects such as air flow, humidity, and heat-sinking need not be examined. The measurement and calculation of die temperatures is discussed in detail in Chapter 9. Systems which exhibit constant failure rates may be characterized by a simple parameter – mean time between failures (MTBF). In such cases, the mathematics of reliability becomes very simple. However, the assumption of constant failure rates in systems is not correct for most integrated circuits, which instead follow more complex distributions of degradation that may vary significantly with the type of accelerating stress being applied and with the actual conditions the device experiences throughout its lifetime. Although well understood since the early seventies, nonuniform failure distributions were largely ignored by systems engineers in favor of the simpler constant failure
10.9 Wear-out versus defects (acceleration versus real life)
475
rate and MTBF calculations. Even today, the simpler calculations shown in equations (10.1) and (10.2) are preferred over the more complex relationships between failures and time as shown in equation (10.6) where Q(t) is defined as the probability that a device will fail in a time equal to or less than t (i.e., the fraction of the population that has failed up to time t) t Q(t) =
f (t)dt
(10.6)
0
where f (t) is the failure probability density function which, for a log-normal distribution, is given by 1 1 2 (10.7) f (t) = √ exp − 2 ln t tm 2σ 2π σ t where σ and tm are the standard deviation and median time to failure, respectively. The failure rate λ for a constant failure rate system is defined as the number of failures divided by the total time for these parts to fail and in this case MTBF = 1 λ (10.8) The reliability unit commonly used for failure rates today is the FIT. A FIT is a shorthand unit of measure for the rate of failures in time. Originally, reliability engineers measured the failure rate in units per hour. As the reliability of semiconductors improved, they changed this to % per 1000 h. Then when reliability improved beyond 0.01% per thousand hours, they made up a Failure unIT, which was equivalent to 0.0001% per thousand hours, and gave it the name FIT. Over the past 30 years, engineers switched the name from Failure unIT to the acronym Failures In Time, but they kept the units the same. So, the FIT is merely a rate unit of convenience, similar to measuring speed in MPH, a FIT has the units of failure fraction per hour. For mathematical convenience, we sometimes refer to a FIT as failures per billion hours – but even though that statement is easy to understand mathematically, failures per billion hours is not technically correct.
10.9
Wear-out versus defects (acceleration versus real life)
10.9.1
Thermal excursion example no. 1. Interconnect vias The focus of most reliability testing has been on high-temperature life testing. Several failure mechanisms are highly accelerated by temperature, so this methodology has produced data that is easy to analyze and straightforward to predict applicable – albeit very long – lifetimes. However, some devices actually fail for quite different failure mechanisms during typical use. This section will address a failure mechanism accelerated by thermal excursions such as temperature cycling, thermal shock instead of high temperatures. This short summary is intended to provide information on the methodology, implementation, and results of reliability assessments enacted by thermal excursion testing.
Reliability
Table 10.7 Standard thermal excursion definitions
Test
Type
JEDEC specification reference
Range
1 2 3 4 5
Infrared reflow Thermal shock Thermal shock Temperature cycle Thermal shock
JESD22-A113 JESD22-A106 condition D JESD22-A106 not specified JESD22-A104 condition G JESD22-A106 condition B
+25 ◦ C to −65 ◦ C to −40 ◦ C to −40 ◦ C to 0 ◦ C to
Cycles +240 ◦ C +150 ◦ C +125 ◦ C +125 ◦ C +100 ◦ C
50 ohm
Input (unbalanced) 50 ohm
Figure 11.54 Coaxial balun structure.
(baluns), 3 dB quadrature couplers (like branch line or Lange couplers), and in-phase couplers (like Wilkinson couplers). Push–pull configurations are extensively used for high-power GaAs FETs for relatively narrow band commercial applications from UHF to S band. Figure 11.53 shows the conceptual block diagram of a microwave push–pull amplifier. Figure 11.54 shows a balun structure used at RF and microwave for push–pull amplifiers. One of the key requirements is to keep the balun structure sufficiently away from the ground such that the impedance from either end of the balanced outputs to ground is as high as possible. This structure was originally developed to feed antenna structures where balanced dipole ends need to be fed from an unbalanced source. The advantages of a push–pull amplifier can be summarized as follows: r four times higher device impedance (Zin gate–gate and Zout drain–drain) in comparison to single-ended device impedances with the same output power, which makes it easier to match and also obtain broader bandwidths; r a virtual ground exists across the symmetry plane which can be used for more compact and simpler matching structures; r cancellation of even products and harmonics, such as f2 − f1 , 2f1 , 2f2 , f1 + f2 , etc.
11.9 Doherty combining
559
The disadvantages of a push–pull amplifier are: r poor input and output external match due to the fact that the baluns used for push–pull amplifiers do not eliminate the input and output power reflected by the device, unlike in balanced configurations; r with conventional baluns, isolation between the two sides of the part is theoretically only 6 dB; this poor interdevice isolation can cause instability and loop oscillation problems; r manually made coaxial baluns are simple to make for laboratory use, but in production they require considerable labor that makes mass production expensive, and repeatability of the performance is not trivial. Surface mount baluns are available but add cost and tend to occupy more real estate than equivalent quadrature couplers. Another option for a microwave PA designer is the microstrip rat-race coupler shown in Figure 11.55. This is a planar structure and does not suffer from the same production, precision, and performance repeatability problems as the coaxial balun counterpart. However, it should be noted that rat-race ports are all at the Z0 (50 ) level, making the balanced impedance 2Z0 ; in this respect the rat race is not a true balun. Thus, the rat-race coupler does not provide the impedance transformation properties of a true coaxial balun and it has a narrower bandwidth, but the bandwidth is still large enough to satisfy the needs of various wireless power amplifiers.
11.9
Doherty combining An ideal Class-B amplifier schematic is given in Figure 11.56. The device’s Vgs is biased to its pinch-off value and the RF voltage magnitude is large enough to drive the gate–source junction such that the device delivers maximum drain current at the output terminals. There is a high-Q resonator tuned to f0 so the impedance presented to the drain terminals of the device is perfectly real at f0 and 0 at all harmonics. The load resistor is chosen carefully to maximize the power output from the device. The high-Q resonator allows all harmonic currents to flow through the device drain-source terminals, but allows only the fundamental voltage to exist across the device which results in a sinusoidal voltage and a half sinusoid current waveform. The peak current is Imax so the amplitude of the fundamental frequency component of the drain current is Imax /2. The voltage waveform swings from 0 to 2Vdc , so the optimum load impedance presented to the device terminals is: 2Vdc Imax
(11.27)
Vdc Imax 4
(11.28)
Ropt = The RF output power is given by: PRF =
560
Power amplifier applications
Isolated port
Output Port 1
l /4
l /4
Input port
l /4 Output Port 2
3l /4
(a)
(b)
Figure 11.55 (a) Rat-race coupler, (b) performance of rat-race coupler.
and because the DC value of the half sinusoid current waveform is Imax /π , the DC supply power is given by: PDC =
VDC Imax π
(11.29)
which gives a drain efficiency of: η= or 78.5%.
PRF π = PDC 4
11.30
561
11.9 Doherty combining
Let us now consider what happens when the input power level is backed off. Figure 11.56 shows the resulting waveforms when the input RF voltage swing is halved (power input is 6 dB backed off ). In this case the output current and output voltage swing magnitude scales down by the same amount. So in the general case, assuming that the gate-source input voltage swing is reduced by a factor p, then the fundamental component of the output current will be: I1 =
Imax 2p
(11.31)
and the output voltage swing will be given by: V1 =
Imax Imax 2VDC VDC = Ropt = 2p 2 p Imax p
(11.32)
Hence, the RF output power, DC supply power, and the resulting efficiency will be: VDC Imax 4 p2 VDC Imax PDC = pπ π1 η= 4 p PRF =
11.33
For example, a 6 dB reduction in RF input power level corresponds to p = 2 and the efficiency drops from π /4 to π /8 (from 78.5% to 39.3%). This is where the debate starts between the RF power amplifier designers and the telecommunications society. As the available frequency spectrum gets narrower there is a requirement to be able to accommodate higher data rates in smaller frequency bandwidths. In recent years new spectrum-efficient modulation techniques have been invented with the widespread use of available wireless technologies. Nowadays the information is not only stored in the phase but also in the envelope of the RF carrier signals. QPSK, QAM, and OFDM modulation schemes are a few of the modulation techniques developed so far. The two main requirements from the power amplifiers are efficiency and linearity. Linearity means small EVM in the modulation domain and low adjacent power levels. In a simple Class-B amplifier the only solution to sustain linearity under these complex modulation schemes is to back-off the signal, where the required back-off level depends on the amount of PAR level. This will have a negative impact on the average efficiency of a Class-B power amplifier as the efficiency degrades by the square root of the power back-off level. In order to get a better understanding of the requirements of a power amplifier which needs to be designed for a WIMAX (802.16e) basestation, let’s have a look at a couple of basic parameters: Pout, avg = 2W, EVM25 dB cannot be used
+20 dBm to −30 dBm 20 dB +++ 1 s to 100 s >25 dB cannot be used
Pe(t)
Pp
Pavg 0
tp
t T
Figure 12.4 Typical properties of a (pulse) modulated signal [1].
rectification. The DC voltage of the detector circuit is approximately proportional to the input power. CW and modulated signals are converted according to their power. The voltage obtained is about 10−10 V to 10−5 V. 2. With increased power levels, the square-law region will be exceeded. Highly stable, noise-free measurements are possible due to output voltages of approximately 10 mV to a few volts. Compared to the square-law region, the sensor becomes very fast but measures the RF voltage instead of the RF power. It behaves like a diode rectifier, weighting the peak of the RF voltage, which is approximately proportional to the peak envelope power of the RF. Nevertheless, today’s sensors can be calibrated so that their output voltage is interpreted as an (average) power level, but this is based on the assumption that the signal to be measured is a pure unmodulated CW signal.
574
Amplifier measurements
Table 12.2 Power sensor side effects and compensation techniques Effect
Compensation technique
Drift of zero value Thermal drift of temperature-dependent parameters Aging of sensitivity Calibration factor K( f ) Power linearity at 23 ◦ C Noise Mismatch effect Connector repeatability
Zeroing Built-in temperature sensor and sensor-specific data of temperature effects Reference oscillator of the power meter Sensor-specific data supplied with sensor Sensor-specific data supplied with sensor Averaging, video filter ** Compensation usually not done! ** ** Compensation not possible! **
Power sensors are of a broadband design. They therefore exhibit a limited dynamic range of typically 30 dB to about 50 dB depending on the type of sensor. However, a high dynamic range up to 90 dB can be achieved by implementing the following techniques: 1. Average several measurement values by using digital signal processing (DSP). 2. Introduce a video filter at the DC part of the sensor, which is actually implemented by a DSP. 3. Use a chopper amplifier within the DC part to overcome the zero drift of the signal chain. 4. Combine several detectors with different sensitivities in a single power sensor. A large dynamic range for modulated signals is obtained by operating each detector exclusively in its square-law region, and by using only the optimally driven detector for the measurement.
12.2.2
Typical sources of measurement uncertainties Power sensors are accompanied by various side effects (Table 12.2). To increase measurement accuracy, techniques for compensating for these effects are available. Zeroing and compensation using a reference oscillator can be performed by the operator on site. All of the other compensation techniques require sensor-specific data (e.g., stored in an EEPROM) that have to be measured in a traceable, commonly accepted manner by the sensor manufacturer or at an accredited calibration service. The compensation techniques listed in Table 12.2 leave some residual uncertainties, e.g., due to the uncertainty of the sensor-specific data. Unfortunately, the mismatch effect usually is not compensated for even though it is the dominant effect in the residual measurement uncertainty. Therefore, it deserves a closer look. The port that the power sensor is connected to and all RF circuitry in front of the power sensor’s reference plane can be considered to be an equivalent generator. The measurement task is to quantify the nominal source PZ0 . It is the power that the equivalent generator would deliver if terminated by the reference impedance Z0 (e.g., 50 or 75 ). Ideally, the power sensor would exhibit this impedance.
12.2 Power measurements
575
Pd Pi
Pr G
Equivalent generator
ΓG
ΓL L
Power sensor
Figure 12.5 Power flow between equivalent generator and power sensor.
However, the actual situation is more complicated, as shown in Figure 12.5. The power sensor’s impedance ZL is not exactly equivalent to the reference impedance Z0 . Therefore, it exhibits a reflection coefficient L = 0, where L =
Z L − Z0 Z L + Z0
(12.1)
A portion of the power Pi incident to the power sensor is reflected as power Pr and travels back toward the generator. The power Pd dissipated by the power sensor remains as: Pd = Pi − Pr = Pi (1 − | L |2 ).
(12.2)
A typical equivalent generator will have a source impedance ZG somewhat different from Z0 , and it will therefore exhibit a reflection coefficient of G = 0. G =
ZG − Z0 ZG + Z0
(12.3)
Consequently, the power Pr traveling back toward the generator will not totally be absorbed by the equivalent generator. The electromagnetic (EM) fields related to the powers Pr and PZ0 will superimpose with one another. Assuming a real-valued characteristic impedance Z0 this can be described by the powers Pr and PZ0 instead of using the relevant wave quantities introduced later in Section 12.4.1. Assuming L < 1 and G < 1, this process can be described as follows: Pi = PZ 0
1 |1 − G L |2
(12.4)
Not all the power dissipated as Pd will be converted to the measured power Pm . A factor called effective efficiency ηe has to be introduced: Pm = ηe · Pd
(12.5)
Using equations (12.2) to (12.5), the relation between the measured power Pm and the nominal source power PZ0 is calculated as follows: Pm = ηe (1 − | L |2 ) ·
1 · PZ 0 |1 − G L |2
(12.6)
576
Amplifier measurements
The first factor ηe (1 − | L |2 ) is the calibration factor K( f ). It is based on the sensor’s inherent properties and is independent of the equivalent generator. It is determined as a function of frequency using an ideal generator G = 0 with known nominal source power PZ0 and known CW frequency f. In practice, a calibration system formed from traceable components such as a precision power sensor (traveling standard), a precision power splitter and a generator involving an automatic level control (ALC) is used. Once factor K( f ) is known, the following relation between measured power Pm and the nominal source power PZ0 applies. PZ 0 =
1 · |1 − G L |2 · Pm K( f )
(12.7)
Most modern power sensors provide phase and magnitude information of L ( f ) as premeasured data that are referenced to the power sensors reference plane. If the complex coefficient G of the equivalent generator is known, then correction for the factor |1 − G L |2 is possible. This technique is called gamma correction of the power meter. However, the phase of the generators reflection coefficient is often unknown and it will be changed due to adapters and other things introduced between the generator and power sensor. Thus, it is only possible to determine the uncertainty that is introduced by the factor |1 − G L |2 using the magnitudes | G | and | L | and the following relation: (1 − |G | | L |)2 · ≤
PZ 0 K ≤ (1 + |G | | L |)2 Pm
(12.8)
A power sensor cannot accurately measure the nominal power PZ0 of a mismatched source unless it is ideally matched itself. In other words, the magnitude | L | is a very important quality criterion of a power sensor.
12.2.3
High-power RF measurements and directional power Measurements One approach to connecting a power sensor to a high-power RF source is to use an attenuator to adapt the level between RF source and sensor. The following is an example of how to measure a 60 W output power of a GSM base station amplifier. The attenuator (Figure 12.6) consists of several stages for distributing the power dissipation between the stages in nearly equal amounts of approximately 20 W. The last stage has the most attenuation (d3 = 15 dB). In contrast to other stages, it is designed as a -circuit because it is more convenient than the T-circuit if an attenuation value di above 10 dB is required. This attenuator design has a dedicated input and output port. Interchanging these ports would dramatically alter the power distribution between stages. The stage with the 15 dB attenuation would then have to cope with ≈58 W of dissipated power and burn-out. Although attenuators are reciprocal devices (S21 = S12 ), most high-power attenuators can only handle a fraction of their nominal power rating when being operated in the reverse direction!
12.2 Power measurements
577
Table 12.3 Multistage implementation of a high-power 20 dB attenuator
Stage
Attenuation di
Power dissipation
Stage output power
1st 2nd 3rd Cumulated values
2 dB 3 dB 15 dB 20 dB
22.14 W 18.93 W 18.33 W 59.40 W
37.86 W 18.93 W 0.60 W (28 dBm)
R1
R1
Input
R3
R3 R4
R2
1st Stage
G Equivalent generator
R5
2nd Stage
S11 Z0
R6
S21
Output R5
3rd Stage
S22
S12 High-power attenuator
Z0 Power sensor
Figure 12.6 Implementation of the high-power attenuator.
Assuming a source/load impedance of Z0 = 50 and ideal matching S11 = S22 = 0, resistors R1 to R6 in Figure 12.6 can be calculated as follows: R1 = Z 0
1 − 10−d1 /20dB 1 − 0.794 = 5.73 = 50 −d /20dB 1 1 + 10 1 + 0.794
R2 = Z 0
2 · 10−d1 /20dB 2 · 0.794 = 215.24 2 = 50 −d /20dB 1 − 0.63 1 − 10 1
(12.10)
R3 = Z 0
1 − 10−d2 /20dB 1 − 0.708 = 50 = 8.55 −d /20dB 2 1 + 10 1 + 0.708
(12.11)
R4 = Z 0
2 · 10−d2 /20dB 2 · 0.708 = 141.93 2 = 50 −d /20dB 1 − 0.50 2 1 − 10
(12.12)
1 + 10−d3 /20dB 1 + 0.178 = 50 = 71.63 1 − 10−d3 /20dB 1 − 0.178 2 1 − 10−d3 /20dB 1 − 0.032 = 136.14 = 50 R6 = Z 0 −d /20dB 3 2 · 10 1 − 0.178 R5 = Z 0
(12.9)
(12.13) (12.14)
578
Amplifier measurements
Transmission lines between individual stages can be used to distribute the attenuators on the heat sink. The characteristic impedance of these interconnections should be Z0 . In contrast, connections within a single stage should be as short as possible to avoid any unwanted impedance transformation. The mechanical dimension of a single stage is the limiting factor on its maximum frequency. A compromise between RF performance and thermal requirements must be found. The power dissipation of a single stage is shared between its resistors. Exactly how this is done depends on the attenuation value and the source/load impedance. The worst-case scenario needs to be considered: a source impedance of 0 (equal to doubled input voltage) and simultaneously a load impedance of 0 or ∞ (depending on the resistor to be considered). However, not all commercially available attenuators can be assumed to comply with this worst-case dimensioning. Therefore, source and load mismatch must be kept within specification when applying the maximum rated power to an attenuator. Self-heating of the attenuator may cause a temperature drift if improper resistor material is used. An attenuator input reflection coefficient S11 very close to 0 is a further prerequisite for low measurement uncertainty. Its role can be compared to L of equation (12.8). The attenuator’s output reflection coefficient S22 is not as critical if the power sensor is well matched and the attenuation S21 is somewhat greater than 15 dB. The frequency response of S21 ( f ) can be measured by a network analyzer. But the small-signal values typically obtained from such measurements are not valid for high-power operation. A compromise to partially mimic the high-power scenario is to use a DC-bias that provides the necessary power to the attenuator under test and to simultaneously measure the frequency response using the network analyzer. Based on these measurements a calibration factor K( f, Pm ) dependent on the frequency and measured power can be calculated. High-power measurements with an attenuator have some drawbacks: 1. The measurement range is limited to approximately 1 kW, while liquid-cooled dummy loads are available up to approximately 300 kW. 2. No in-circuit test using the original operating load is possible. 3. Monitoring mismatch to detect critical load situations is not possible. This is why directional power sensors have been developed. Versions with a measurement range up to several kW are available. As shown in Figure 12.7, these sensors are connected between source and load to measure the power flow in both directions. The built-in high-power dual-directional coupler provides a small fraction of incident power Pi and reflected power Pr to separate power sensors. A typical directional power sensor exhibits an insertion loss of less than 0.5 dB between its RF connectors. For frequencies below 100 MHz, a more compact lumped-coupler design by Buschbeck [2] or further developments [3] are mostly used. VSWR bridges are not recommended because of their significant insertion loss of 6 dB. Due to the coupling effect, directional power sensors are limited in bandwidth, covering a range of one octave to about two decades.
12.2 Power measurements
579
Pr Pi G Directional coupler
Generator
Dummy load or antenna
Secondaryline terminations and frequencyresponse compensation Rectifier
V~Pi To power meter
V~Pr
Figure 12.7 Application of a directional power sensor [1].
A directional power meter (also called power reflection meter) is used to operate the power directional sensor. It involves automatic functionality for calculating the magnitude | L | of the load reflection coefficient from formula (12.2). It can also convert this value to the voltage standing wave ratio VSWR. VSWR =
1 + | L | 1 − | L |
(12.15)
The mismatch uncertainty of terminating power sensors (see Section 12.2.2) can be overcome. The reflection coefficient at the RF ports of the directional power sensor and its insertion loss are usually negligible. But there are two effects introduced by the directional coupler: 1. The electrical length at the reference plane where the directional power sensor is inserted will change. As a consequence, the phase relations compared to the operating conditions without the sensor will not be the same. This can lead to significant power changes if the generator and load are mismatched. Built-in couplers that remain in the circuit are one solution. 2. The coupler’s capability to separate incident and reflected power is limited by its directivity D (for details, see Section 12.3.2).
12.2.4
Power measurements using a spectrum analyzer Spectrum analyzers measure the power density spectrum. Integrating the power density spectrum over a specific frequency range can be done to identify the power present in this range. The following properties of spectrum analyzers are significant:
580
Amplifier measurements
1. The measurement is performed based on a heterodyne concept with a selectable resolution bandwidth (e.g., 1 Hz to 40 MHz). As a consequence, the dynamic range is far beyond that of power sensors. 2. Spectrum analyzers are able to unambiguously correlate a specific receive power to a specific frequency. Techniques such as a high first IF or a tracking filter for higher frequencies are involved here. But the use of additional harmonic mixers to extend the frequency range leads to image reception and spurious responses. 3. Spectrum analyzers exhibit a quasi-continuous, or seamless, sweep. They are designed so that the power displayed as a measurement point involves the power spectral density toward its adjacent points. This makes them different from the receivers of vector network analyzers and prevents the user from “overlooking” spectral components hidden between the measurement points. 4. Supplementing the spectrum analyzer with a precision power splitter and a power sensor helps to yield the advantages of both instruments. This can, for example, lead to a measurement uncertainty of 20 dB
>38 dB
0.5 W
16 dB
>18 dB
1 W to 10 W
15 dB
>10 dB
several kW
28 dB
30 dB
16 dB
>16 dB
50 W to 100 kW depending on frequency 1 W to 10 W
>16 dB
20 dB
2 W to 100 kW
6 dB
3 dB to 25 dB 24 GHz may come up with polynomial coefficients L0 , L1 , L2 , and L3 for characterizing their parasitic inductance. This standard exhibits a length offset l and parasitic fringing capacitances, which are characterized by a set of polynomial coefficients (C0 , C1 , C2 , and C3 ). The open standard cannot be realized in waveguide systems. It is then usually “replaced” by an offset short. This precise broadband impedance is matched to the system impedance. In the past, it was commonly assumed to be ideal ( = 0) and was not modeled. If it is supplemented with characteristic data then the precision can be raised close to that achieved by a sliding match. An air line with specified characteristic impedance can be manufactured more accurately than a broadband match. A cylindrical ferrite rod that is introduced into the air line absorbs a large portion of the magnetic energy starting from a minimum frequency of approximately 2 GHz. If the ferrite rod is moved along the line, the length offset and therefore the phase changes but the magnitude remains nearly constant. Operators typically orient themselves on the marks on the sliding match. The corresponding reflection coefficients lie on a circle around the air line’s characteristic impedance. The through is a two-port standard that allows a suitable low-loss connection of both test ports. It is characterized by its delay or electrical length, its loss and its characteristic impedance. In some cases (e.g., sexless connector system), a direct connection of test ports with electrical length 0 mm is permissible. Any two-port whose S-parameters fulfill the reciprocity condition (s21 = s12 ) can serve as an unknown through. This one-port has a reflection coefficient of || > 0. The exact reflection value is not needed. However it must be identical at both test ports. To characterize the standard, its behavior at low frequencies is classified as more capacitive (Im{}< 0) or more inductive (Im{}< 0). The electrical length is relevant if it alters the classification at higher frequencies. In coaxial systems, this two-port standard is implemented as an air line. Its characteristic impedance has to be well matched to the system impedance. The difference in electric length between through and the line standard must not be equal to an integer multiple of half of the wavelength. Start versus stop frequency is therefore restricted to 1:8. This can be overcome by using multiple lines and a fixed match for lower frequencies. This two-port has symmetrical reflection coefficients s11 = s22 = 0 and any transmission coefficient, even 0 or 1. Similar to the reflect standards, a classification for more capacitive or more inductive is necessary. This two-port standard has to be well matched on both sides. Unlike the through, it should have an unknown insertion loss which is in the range 10 dB to 55 dB.
R
12.3 S-parameter measurements
591
Table 12.6 Typical raw and effective system data of a VNA
System data
Raw system Effective data system data
Forward measurement
Reverse measurement
Reflection tracking Directivity Source match Transmission tracking Load match
≤2 dB ≥29 dB ≥22 dB ≤2 dB ≥22 dB
e10 e01 e00 e11 e10 e32 e22
e23 e32 e33 e22 e01 e23 e11
≤0.04 dB ≥46 dB ≥39 dB ≤0.06 dB ≥44 dB
Note that directivity e00 , e33 in this table and directivity D in Section 12.3.2 are defined differently. D = e00 − (e10 e01 ) or D = e33 /(e23 e32 ). The error terms e00 and e33 are similar to s31 of Figure 12.9.
(a)
(b)
(c)
(d)
(e)
(f)
Figure 12.15 Typical coaxial RF connector types (for a, b, c, . . . , see Table 12.8).
for by an offset length assigned to test port 2. The offset length has to be increased because of dielectric inner conductor support or discontinuities between the inner and outer conductor. An alternative is to mount an N-type short standard on the open end of the adapter to use the auto length functionality of the VNA to obtain an estimated overall length. Taking into account the offset length of the N-type short, the adapter’s insertion length can be calculated and the length offset can be modified accordingly. Nevertheless, strategy 1 does not compensate for the frequency-dependent attenuation of the adapter and is therefore limited in frequency range. The s11 and s22 of the adapter have a significant influence on the test port match and the directivity obtained (for a similar discussion, see s11 and s22 of the attenuator used in Section 12.3.7). If available, a high-quality adapter from a calibration kit should be chosen.
Strategy 2: UOSM calibration with mixed test port types The adapter is mounted prior to calibration, and calibration will therefore compensate for it. A suitable calibration kit is required for each of the connector types involved. The calibration kit must include, at a minimum, the standards that are needed for oneport calibration. In addition to the adapter that has been mounted at test port 2, a second adapter to be used only during calibration is required. The purpose of the second adapter is to establish the unknown through. This adapter does not have to feature good matching. It merely has to satisfy the reciprocity condition (s21 = s12 ). To ensure proper results, the second adapter’s insertion loss should not exceed 20 dB. Strategy 2 even
592
Amplifier measurements
Table 12.7 Properties of the various calibration techniques [4] Calibration Technique Other names Error model DUT type Suitable for transmission measurements No band limitation due to singularities Indirect plausibility check Partially unknown standards Consideration of DUT depended cross talk Usage of standards with different gender Suitable for noninsertable DUTs Possible usage of sliding match Well-suited for on-wafer measurements Effective directivity attained Number of receivers in N-port VNA Minimum number of calibration standards Contacts3 in two port VNA
OSM SOL,OSL 3-term one-port
✓
TOM TRM TRL OLT LRM1 LRL1 7-term two-port or multiport ✓ ✓ ✓
TNA TAN
UOSM TOSM SOLR SOLT 12-term
✓
✓
✓
✓
✓
✓
✓
✓
✓ ✓
✓
✓
✓
✓
✓2
✓2
✓2
✓
✓
✓
✓
✓ ✓
✓
✓
✓ ✓ ✓
✓
+ N+1 3
+ 2N 3
+ 2N 3
+++ 2N 3
+ 2N 3
+ 2N 4
+ N+1 4
3
6
6
6
6
8
8
The through (which may exhibit a length l = 0) is replaced by a line standard l > 0. Assuming that the standards produce symmetrical reflections. 3 The number of “contacts” is used to assess the amount of work involved in the calibration procedure. By contact, we mean setting up an electrical connection. For example, mounting a one-port standard requires one contact. Mounting a two-port standard requires two contacts. 1 2
works with frequencies above 40 GHz (if the connectors involved are suitable for these frequencies) or with adapters between media (e.g., coaxial to waveguide or coaxial to coplanar), which usually exhibit greater frequency-dependent behavior than intercoaxial adapters. Strategy 2 can even be used to characterize the unknown through and to store its S-parameters. Once characterized, the second adapter can be used in strategy 4 or 5.
Strategy 3: adapter removal technique The UOSM calibration technique is based on a seven-term error model. Vector network analyzers that exhibit a reduced architecture with a common reference channel cannot be described by the seven-term error model. A calibration technique based on the 12-term model and referred to as the adapter removal technique has to be used instead of strategy 2 (details may be found in operating manuals of older VNAs that have been based on a three-receiver architecture).
593
12.3 S-parameter measurements
Table 12.8 Typical coaxial RF connector types and their properties
Connector type
Figure
fmax GHz
Z
Mechanically compatible with
Ttyp 2 Nm
7/16 DIN 14 mm
a –
7.5 GHz 8.5 GHz
50 50
– –
25.0 4.0
N
b c
7 mm SMA PC 3.5 2.92 mm (K)1 2.4 mm 1.85 mm (V)1 1.00 mm
– d e – – f –
50 75 50 75 50 50 50 50 50 50 50
–
BNC
18 GHz 4 GHz 4 GHz 1 GHz 18 GHz 18 GHz 34 GHz 40 GHz 50 GHz 67 GHz 110 GHz
1 2
– – 3.5 mm; K SMA; K SMA; 3.5 mm 1.85 mm 2.4 mm –
1.36 – 1.36 0.56 0.90 0.80 0.90 0.90 0.45
Note high power high power sexless medium power bayonet coupling sexless – – – – – –
The names “K Connector,” “V Connector” are trademarks of Wiltron/Anritsu Corporation. The torque Ttyp can vary between manufacturers.
Strategy 4: de-embedding the adapter As in strategy 1, the adapter is mounted on test port 2 after calibration. In strategy 4, however, all four S-parameters of the adapter are available as a function of frequency and entered into the VNA (e.g., by data file). A technique called de-embedding is applied to port 2. This technique is internally based on a transmission matrix calculus. It compensates the adapter in a more precise way than is done in strategy 1. Within the relevant frequency range, the transmission characteristic of the adapter should not exhibit any zeros or any attenuation values above 20 dB. This is due to signal-to-noise aspects. The advantage of strategy 4 is that once the through is characterized, no second calibration kit (N-connector in the example here) is necessary. Plus, the user may choose any calibration technique preferred (e.g., the one-path, two-port technique suggested in Section 12.3.7). But the VNA is not informed if the adapted port is connected to a dispersive media (e.g., waveguide), which would be necessary in some cases.
12.3.6
Calibration with PCBs, test fixtures, and wafer probers With printed circuit boards (PCB), an adaptation of their microstrip design to the coaxial connectors of the VNA is necessary. This can be achieved by using SMA connectors and a test PCB as shown in Figure 12.16 left. This test board carries all calibration standards necessary to perform several calibration techniques and two bays for inserting one-port or two-port DUTs. The fringing capacities at the open end of the microstrip line and the parasitic inductances introduced by the ground vias of the short and match standard have to be calculated by an EM solver or using [6, 7]. The microstrip lines are
594
Amplifier measurements
l Cross section with fringing capacitances
Open Via Short Via + 100Ω Match
Equivalent circuit without DUT
Via + 100Ω One-port DUT Through
Cross section with Two-port DUT 2l Two-port DUT Ground (Amplifier)
DUT
(Bias)
l
l Two-port DUT with capacitances
Line standard 2l
x
Figure 12.16 Test PCB carrying microstrip calibration standards and DUTs bays.
designed to have a characteristic impedance of 50 . A minimum distance of l = 20 mm to 50 mm (depending on the wavelength) must be maintained on the PCB between the coaxial connector and the reference plane so that the higher modes that arise at the transition from the coaxial system to the PCB can fade away. If all of the standards are implemented with the same distance l and if the through-connection is made by a length of 2l, a length offset of 0 mm can be specified in the characteristic data of the standards. In this case, the bays of the DUTs must have exactly the same distances l from the SMA connectors in order to locate the reference plane at the component’s edge. For frequencies above 6 GHz, the TRL calibration technique is strongly recommended. The line standard can be characterized by its additional length x. To overcome the frequency restriction that comes with the value of x (see Table 12.5 row “line standard”), the match can be included in the TRL calibration to allow an extension down to 0 Hz. One-port devices can be measured in the one-port or two-port bay. In the first case, the parasitic inductance of the ground via may be relevant. Fringing capacities and parasitic inductance are dependent on the PCB material and via diameter, respectively. For universal use in electronic design automation tools, a characterization without these influences is required. The following guidelines are therefore recommended:
12.3 S-parameter measurements
595
1. Low-impedance one-port devices can be measured in the one-port bay as fringing capacitances will not have any significant influence, which means that it is sufficient to de-embed just the parasitic inductance of the via. In this special case, the location of the DUT and parasitic inductance can be assumed to be interchangeable (necessary for one-port de-embedding). 2. High-impedance, one-port devices and all two-port DUTs have to be measured in the two-port bay. Before mounting, the DUT measurements on the four S-parameters of the empty bay have to be carried out and the values of the parasitic capacitors and resistors have to be calculated (see Figure 12.16, right-hand side). After measurement, the parasitic component values have to be de-embedded. Substrates like Al2 O3 are very brittle, therefore connectors cannot directly be mounted on to them. A test fixture employed for these requires a reproducible contacting of the microstrip, coplanar or grounded coplanar waveguide. A test fixture typically has two clamping jaws that are placed on the front sides of the substrate. One of the jaws can be adjusted in both horizontal directions. This makes it possible to adapt the test fixture to different substrate sizes and also to handle diagonally arranged contact interfaces. The jaws consist of two strip-shaped ground contacts that squeeze the substrate. In the upper ground contact, an inner conductor is opened up to adapt to a coaxial line system. During calibration, different substrates with different standards are used. To ensure correct results, care must be taken to ensure that the inner conductor contacts the substrate at the proper position. Test fixtures generally have a mechanically rugged design, but their inner conductors do require careful handling. The TNA calibration technique is particularly well-suited for measurements using a test fixture. The primary benefit of this calibration technique lies in the minimum requirements that are placed on the properties of the standards. A microstrip calibration kit includes a straight 50 microstrip section with length 2l that is characterized as a through with length 0 so that l becomes the distance of the reference plane on both sides of the substrate. It also requires a symmetric network standard that can either be an empty substrate or the test fixture left opened without any substrate, and an attenuator standard which can be manufactured with extreme precision on substrates using thin-film technology with laser-trimmed resistors. To obtain the best possible interface to the coaxial system, a suitable ground connection must be provided at the transition to the substrate. In the case of on-wafer measurements, the circuits are not accessible from their backside; they are only accessible via their top side. To ensure a suitable ground connection at the contact point, coplanar waveguide (CPW) ground (G), signal (S), and ground (G) contacts are situated on the top of the wafer and have dimensions of less than 0.1 mm. A special micromechanical manipulator, referred to as a wafer prober, is necessary to contact the GSG pads. Characterized calibration standards are defined on a substrate known as an impedance standard substrate (ISS). The TRL calibration technique is awkward with wafer probers because of the multiple line spacing necessary to establish the through (T) and line (L) standard so the TRM calibration technique is preferred. The match standard necessary can be provided by laser-trimmed small resistors and modeled as a constant resistance with a series
596
Amplifier measurements
VNA Booster amplifier
Receiver and generator section of the VNA
Test port 1
Test port 1
Test port 1 Reference plane 1
to b1 channel Reference plane 1
Reference plane 1
SA22 S∏12 R
Power sensor
Reference plane 2
Reference plane 2 S∏21
Reference plane 2
S∏22
to b2 channel e33
to b2 channel
Test port 2
Test port 2
Test port 2
Configuration with reduced precision
Optimized high-power configuration
Optimized high-power configuration with boosted source
Figure 12.17 High-power setup with and without significantly reduced precision.
reactance. The through can be very short so that its matching is not a critical issue. The reflect standard need have no known properties and can be implemented with the probes in the air.
12.3.7
Calibration consideration for high-power setups With DUTs such as power amplifiers, the output power of the DUT may exceed the linear input range of the VNA. As an example, the test port input power should be kept below 0.2 W so as not to exceed the linear range of the VNA. Suppose the amplifier had an output power of 20 W, then a 20 dB attenuator pad between the amplifier output and test port 2 would be just sufficient enough to prevent any overdrive. However, this attenuator would have significant disadvantages as described below. The amplifier and attenuator can be described by their S-parameter matrix SA and Sπ , respectively. The VNA’s test port 2 is characterized using directivity D, test port match S and reflection tracking R. The reference plane of the measurement should be located at the input and output of the amplifier. This means that it is located prior to the attenuator and that the attenuator becomes part of the test set (see Figure 12.17, left). This combined test set at port 2 is described using directivity D , test port match S and reflection tracking R . During reflection measurements at port 2, the signal passes the reflection tracking (R), the 20 dB attenuator two times (sπ 12 = sπ 21 ), and the output reflection coefficient sA22 of the DUT (see Figure 12.17, left). The reflection tracking R is thus altered by the attenuator to R = sπ2 21 · R.
(12.29)
12.3 S-parameter measurements
597
The test port match S revealed to the amplifier is dominated by the reflection coefficient sπ 11 of the attenuator because of its high attenuation (20 dB) i.e., S = s11
(12.30)
The parasitic crosstalk e33 = R · D is a bypass to the measurement functionality of the directional element. In this case, an additional crosstalk path is formed by R · sπ 22 , thus contributing to the overall crosstalk. Obtaining the directivity D’ requires taking the quotient of the overall crosstalk R · D + R · sπ 22 and the reflection tracking R from formula (12.29). Thus, D =
R · D + R · sπ 11 D + sπ 11 = 2 R · sπ 21 sπ2 21
(12.31)
Using typical system raw data as stated in Table 12.6, and assuming an attenuator with a return loss of 20 dB and an insertion loss of 20 dB, the raw directivity is degraded by 33 dB which is the most unwanted effect of this setup. It is hardly possible to compensate this using a calibration technique because of influences like thermal drift, connector repeatability and phase stability of the cabling. There are two workarounds that can help. 1. If the output match of the amplifier needn’t be measured, then choose the one-path two-port calibration technique. It is a combination of a complete one-port calibration on test port 1 and transmission normalization. It is a unidirectional error correction which means that the same test port (test port 1 in this case) is always operated as active port. It does not correct any reflection at test port 2 and it does not correct for any multiple reflections caused by the attenuator. Therefore the attenuator should exhibit a return loss better than 25 dB in this case. 2. If information regarding the output reflection coefficient sA22 of the amplifier is needed, then choose a setup with an external directional element (see Figure 12.17 middle). The reference channel can be tapped inside the VNA as before, but the directive element is placed directly behind the power amplifier in order not to risk any degradation of directivity. An introduction on how to design the necessary highpower coupler can be found in reference [8]. Because it is only needed for the small operating frequency range of the amplifier, a circulator is often preferred instead of the coupler. Before the signal is fed into the VNA via an external receiver input, level adjustment has to be done using a second attenuator. In some respects the configuration can be compared to Figure 12.13 if the receiver and generator attenuators (dashed) are present, but the components of Figure 12.13 are designed for medium-power measurements. Power amplifiers typically require significant RF input power, more than can usually be provided by a VNA. A booster amplifier (see Figure 12.17 right) can be used to raise the source level. To make sA11 measurements, an external coupler is required for the measurement of channel b1 . If the linearity of the booster amplifier is not sufficient or if it exhibits drift effects then the reference channel a1 should also be monitored by an
598
Amplifier measurements
external coupler. This coupler (not shown in Figure 12.17) has to be located between the booster amplifier and the b1 -coupler. To control the actual input power to the DUT, a power calibration at reference plane 1 (using a power sensor) is strongly recommended. Afterwards, one of the calibration techniques described above has to be applied.
12.3.8
Residual errors and measurement uncertainties Every measurement result is subject to some uncertainty that characterizes the expected deviation of the measured value from the true value. According to reference [9], a distinction must be made between two types of uncertainty: Type A is caused by random measurement errors, while type B is generated by systematic errors and can be compensated for as shown in Sections 12.3.4 to section 12.3.7. Uncertainties of type A cannot be compensated for, but instruments are designed to keep them at a minimum. The following guidelines should be observed to minimize type A uncertainties: 1. A warm-up time should be observed to ensure that the equipment is operated in thermal equilibrium. Once the equipment has warmed up, an environment with a stable temperature helps to keep thermal drifts as small as possible. 2. Connectors are subject to wear. Using the applicable tightening procedure (torque wench, rotating the connecting nut but not rotating the connector) and careful cleaning reduce wear to a minimum. Regular inspections also involving a pin depth gauge help to detect faulty connectors. 3. The noise superimposed on the measured values can be reduced using a smaller IF bandwidth or increasing (if possible) the stimulus power. If the measurement or reference receivers are operated near their upper power limit, compression effects will occur and cause avoidable uncertainties. 4. Calibration techniques can be used to overcome systematic errors. Although a calibration is done in the correct manner, some small errors will remain. The calibration kit involved and the precision of its characterization are the primary factors with a modern VNA. Calibration kits are available with different capabilities and should be selected based on the accuracy requirements. The time intervals between calibrations should be kept according to influences such as stability of temperature, etc. The network analyzer settings used for calibration and measurement should vary only to a certain extent. The residual errors form an error model similar to that shown in Figure 12.14 but exhibit the effective system data e’ik instead of the error terms eik . For typical values, see Table 12.6. A distinction must be made between effective system data and faulty calibrations that arise as a result of operator errors, defective network analyzers and damaged standards. The implicit plausibility check provided in the TOM calibration technique helps to detect a faulty calibration early on in the process. The T-check (see [10]) and the Beatty standard serve the same purpose. A common misinterpretation is that the same set of standards used for calibration can be reconnected to detect faulty calibrations. In fact, this measurement only provides information about reproducibility. A second calibration kit providing other sets of the standards (not involved in the
12.4 Further linear measurements
599
calibration) can be used to detect faulty calibration. If the calibration is double-checked by measuring all standards of the second calibration kit, the effective system data e’ik of the present calibration can be calculated. But this verification would be based upon the characteristic data of the second calibration kit and the uncertainties of these data. Since these data items are normally in the same order of magnitude as the expected effective system data, this method is only of academic value. In practice, a verification kit has to be used. It involves standards that are especially designed to meet the high accuracy demands, e.g., air lines without the need for an inner conductor support, precision attenuators and mismatch standards.
12.4
Further linear measurements A vector network analyzer is mainly designed to perform S-parameter measurements. Based on these measurements further linear descriptions can be calculated, either by the operator or the analyzer (e.g., using trace mathematics).
12.4.1
Amplifier gain definitions The first step is to consider a simple circuit consisting of a source S and a load L . At the source, a distinction must be made between the following r available power PA , which is the maximum power that can be drawn from the source under power matching condition ( S = L * ). The quantities PA and S are sufficient to characterize the RF source by a linear model. r delivered power PD , which is the power transmitted to any arbitrary load considering the mismatch caused by source and load reflection coefficients (i.e., PA − PD = power lost due to mismatch). The next step is to consider an amplifier connected between an RF source with reflection coefficient S and a load with reflection coefficient L . The power flow diagram Figure 12.18 shows this scenario, using four important RF power definitions: r r r r
available power of the source PAS ; delivered power from the source PDS ; available power of the amplifier’s output PAO ; delivered power from the amplifier’s output PDO .
Based on the four power definitions, various amplifier gains can be stated. The transducer gain GT is an overall quantity that regards the mismatch at the input, the RF power added by the amplifier, and the output mismatch. Therefore, it is well suited for power optimization design techniques. The operating power gain GP and the available power gain GA disregard the input or output mismatch, respectively. The gain measured by a VNA is G0 = (s21 )2 or 20log(s21 ) dB in dB scale. This gain can be considered as the transducer gain GT under the constraint that the amplifier is embedded in an environment offering a port impedance exactly equal to the
600
Amplifier measurements
GP
Different gain definitions: GA GT RF power flow chart:
PDS
PAS
PAO Power loss due to mismatch at input
Power added by the amplifier
PDO
Power loss due to mismatch at output
Figure 12.18 Power flow and gain definitions of an amplifier.
system impedance Z0 (generally 50 ). Most amplifiers exhibit an input and output impedance that is notably different from Z0 . This means that mismatch will occur if they are directly connected to the test ports of a VNA. In order to operate the amplifier economically, the application circuits are designed to minimize mismatch, thus achieving the maximum possible transducer gain. A similar situation arises for the operating power gain GP and the available power gain GA . The values of the different gains GT , GP , and GA can be calculated from the amplifier’s S-parameters, the source reflection coefficient S , and the load reflection coefficient L if the amplifier behaves linearly as follows: |s21 |2 1 − | S |2 1 − | L |2 PD O GT = = (12.32) PAS |(1 − s11 S ) (1 − s22 L ) − s12 s21 S L |2 |s21 |2 1 − | S |2 PAO = GA = PAS |1 − s11 S |2 − |s22 − S det(S)|2
(12.33)
|s21 |2 1 − | L |2 PD O GP = = PDS |1 − s22 L |2 − |s11 − L det (S)|2
(12.34)
where det(S) = s11 s22 − s21 s12 It should not be overlooked that formulas (12.31) to (12.34) are based on a linear assumption which makes them insufficient for strong nonlinear behavior, necessitating load-pull techniques (see Section 12.5.4) for accurate measurements. But the formulas do consider the fact that the matching condition of the output affects the input impedance of the amplifier and, vice versa, the input matching affects the output impedance. This is a consequence of the finite s21 s12 term. In some cases, if s21 s12 is small enough or if additional elements are used to neutralize the parasitic elements responsible for s12 = 0, the amplifier can be assumed as unilateral (s12 = 0). This means that input and output
601
12.4 Further linear measurements
–1 dB 0 dB cT 2 dB
rT
3 dB
Direction of (s22)∗
Figure 12.19 Example for constant gain circles of GL .
matching can be optimized independently of one another, and formula (12.32) can be split into three independent factors GT =
1 − | S |2 1 − | L |2 2 |s | · · if s12 = 0. 21 |1 − s11 S |2 |1 − s22 L |2 GS
(12.35)
GL
In this special case the source and load reflection coefficients that yield the maximum transducer gain GTMAX are given by the conjugate complex values of the amplifier’s input and output reflection coefficients. G T MAX =
1 1 · |s21 |2 · 2 1 − |s11 | 1 − |s22 |2
if s12 = 0, S = (s11 )∗ , L = (s22 )∗ . (12.36)
The optimum value of the load reflection coefficient L = (s22 )* can be marked in the L -Smith chart as a single point (see Figure 12.19 point “3 dB”). If the factor GL of formula (12.35) is set to a specific value (e.g., GL = 1 equals 0 dB), then GL can be solved for L . This leads to solutions in the form of a circles with the center located along the vector (s22 )* at a distance cT from the origin L = 0. The circle’s radius is rT . cT =
rT =
G L |s22 | 1 + G L |s22 |2
1 − G L 1 − |s22 |2 1 + G L |s22 |2
(12.37)
(12.38)
The same considerations are possible concerning factor GS of formula (12.35), i.e., replacing s22 by s11 and GL by GS in formula (12.37) to (12.38). The insertion gain is a figure of merit that compares the situation of the source and load connected without the amplifier to the situation with the amplifier in between. The
602
Amplifier measurements
insertion gain GINS is defined as the ratio of the power PDO that is delivered at the amplifier’s output to the load L versus the power that is delivered from the source S if the load L is directly connected to the source. G INS =
|s21 |2 |1 − S L |2 |(1 − s11 S ) (1 − s22 L ) − s12 s21 S L |2
(12.39)
For reflection coefficients S = L = 0, as occurs ideally with a VNA, the insertion gain becomes equal to G0 = (s21 )2 .
12.4.2
Efficiency factor Low power consumption is an important requirement not only for battery-operated power amplifiers but also because lost power is converted to heat. The efficiency describes the percentage of applied power that is converted to RF power. The drain efficiency is simply the ratio of the output RF power to the DC input power necessary to bias the amplifier. This definition does not consider the incident RF power that is fed to the amplifier’s input, and that may be a substantial value in the case of a power amplifier. The (PAE) is a more adequate measure. It is the ratio of the RF power added by the amplifier to the DC bias power. The RF power added is the difference between the power PDO delivered to the load at the output and the power PDS delivered to the amplifier’s input. The DC power is calculated from bias voltage v DC and bias current iDC using PDC = v DC · iDC . PAE1 =
PD O − PDS · 100%. PDC
(12.40)
An alternative definition of the PAE considers the amplifier’s input power using the available power PAS instead of the delivered power PDS , as a consequence this definition counts mismatch loss at the amplifier’s input as a degrading effect on the efficiency, which is more realistic. PAE2 =
|b2 |2 − |a1 |2 PD O − PAS · 100% = · 100%. PDC PDC
(12.41)
A VNA with an active test set can directly bias an active device through its test ports without the need for a bias network between test port and DUT. In this case, characterization of the active device can be done without a degradation in directivity and without the need for de-embedding the bias network. Modern VNAs have special DC measurement inputs for measuring the DC power consumption of the amplifier under test. The voltage v BS can usually be applied directly to these inputs. However, the current iBS must be measured indirectly as a voltage drop across a precision resistor. The efficiency can be calculated automatically from the DC measurements and the wave quantities. It should not be overlooked that nonlinear effects cause the efficiency of a power amplifier to be dependent on several parameters: 1. The PAE can be improved by optimized input and output terminations for fundamental frequency and higher-order harmonics. 2. The PAE typically reaches its maximum near the 1 dB compression point.
12.4 Further linear measurements
0 0
f0
f1
f2
603
f
τG
arg(s 21(f ))
Figure 12.20 Definition of the group delay.
3. The PAE depends on the operating frequency (similar to gain). 4. The PAE is strongly related to the bias conditions. A VNA offers frequency sweeps, power sweeps or CW sweeps helping to search for the best operating parameters. Optimizing the PAE experimentally over input and output impedance requires the load and source pull technique (see Section 12.5.4).
12.4.3
Linear distortion, phase and group delay measurement A two-port network is free of linear distortion in a specific frequency range f1 to f2 if it meets the following requirements in this frequency range: r constant group delay τ G in the interval f1 to f2 (see Figure 12.20); r constant magnitude of the transmission coefficient | s21 ( f0 )|. Under these circumstances, the group delay τ G is a measure of how long it takes the modulation components of a signal with frequency f ∈ [f1 , f2 ] to propagate through the amplifier. These spectral components can be observed in the time-domain as the envelope curve of the modulated signal. The group delay τ G is typically calculated from the transmission coefficient s21 . The group delay τ G ( f0 ) is defined as the slope of the phase arg(s21 ( f0 )) at the frequency f0 . This slope is scaled by the factor –1/(2π) or –1/360◦ , yielding the physical unit of the group delay to be the second (s). τG ( f 0 ) = −
1 d arg (s21 ( f 0 )) 360◦ d f
(12.42)
Academic examples are based on algebraic expressions which can be directly inserted in to formula (12.42) to derive them by algebraic means. In contrast, a network analyzer measures S-parameters over a discrete frequency axis. This frequency axis has a step size of f. Therefore, the derivative d/df must be approximated numerically by a difference quotient. For greater flexibility, it is useful to distinguish between f and a frequency step size of fd = κ · Df, which is used for calculating the difference quotient, known as the aperture. The factor κ is then called aperture stepwidth. τG ( f 0 ) ≈ −
1 arg (s21 ( f 0 + f d /2)) − arg (s21 ( f 0 − f d /2)) 360◦ fd
(12.43)
604
Amplifier measurements
Trc1
S21 Delay 30 ns/ Ref 80 ns
1
S21 Aperture selected optimal
200 170 140 110 80
Aperture selected too large
50 20 10 –40
Aperture selected too small
Ch1 Center 2.222 GHz
Pwr 16 dB m
Span 60 MHz
Figure 12.21 Examples for group delay measurements of a bandpass filter with a VNA [4].
0
f arg(s21(f 0)) − arg(s21(0)) f0
arg(s21 (f ))
Figure 12.22 Definition of the phase delay.
The selected aperture fd has an influence on the calculated group delay curve τ G ( f ). A value that is too large results in a loss of details, while a value that is too small will overemphasize the influence of the noise that is superimposed on the measured values (see Figure 12.21). Unfortunately, there is no general rule for selecting the aperture. The necessary value must be determined empirically and should be stated with the result. The phase delay τ P ( f ) is a function of the absolute phase at frequency f. It is normally calculated from the transmission coefficient s21 . The phase delay τ P ( f ) is proportional to the phase range covered between 0 Hz and the observed frequency point f divided by the frequency of observation. In this computation,
12.4 Further linear measurements
605
the phase at 0 Hz is assumed to be arg(s21 (0 Hz)) = 0 even if it is theoretically not defined because of s21 (0 Hz) = 0. τP = −
1 arg(s21 ( f )) − arg(s21 (0 Hz)) 3600 f
(12.44)
In a dispersion-free network, the phase delay remains at a constant value that is specific for this network (e.g., a TEM transmission line). This value indicates the time delay in seconds experienced by any sinusoidal component when passing through the network. Thus, the phase delay is strongly related to the length of a transmission line. Typical transmission lines exhibit a phase delay of a few ps up to a few ns for longer lines. Network analyzers typically use the phase value at the start and stop frequency of the sweep instead of the phase value at 0 Hz and f. Consequently, they use the difference between the stop and start frequency in the denominator of formula (12.44).
12.4.4
Linear stability considerations Instability is a basic risk with any power amplifier (PA). In an unstable state, the amplifier acts like an oscillator and will produce an (undesired) output signal even if there is no input signal present. In the rest of the frequency range, the oscillation will reduce the gain in most cases. For amplifiers measured far below their saturation power, it is important to know that when the amplifier starts oscillation it typically produces an output power with a level up to its saturation power. If the measurement equipment is not designed for that power, it may be damaged. The stability considerations have to be applied for all potential oscillation frequencies and not only for the operating frequency band in which the amplifier is intended to be used. The active circuit elements (transistors) exhibit a unity gain frequency fu upon which they turn into passive devices. Therefore, it is sufficient to consider the frequency range [0; fu ] for stability analysis. The calculations presented here are based on a pure linear circuit model and on the assumption that all parameters are accessible (this is violated in a multiple stage amplifier which requires a separate analysis for each individual stage). The first step is to consider a simple circuit consisting of a source (reflection coefficient S ) being connected to a load L (Figure 12.23a). The initial wave launched by the source is reflected by the load L and travels back to the source. At the source, in turn, it is reflected back with S . This complete cycle exhibits a weight of S · L . The power during a cycle obviously increases if | S · L | > 1. This is equivalent to unstable behavior. However, the circuit can be predicted as stable if | S | | L | < 1
(12.45)
The next step is to consider an amplifier that exhibits two loops, one at the input and one at the output (see Figure 12.23c). Formula (12.45) must be rewritten as | S | · | IN | < 1 for the input loop and as | L | · | OUT | < 1 for the output loop. The source and load are assumed to have positive resistance, which is equivalent to |S | ≤ 1
(12.46)
606
Amplifier measurements
Simple loop Source a0 1
Amplifier
Source
ΓIN
Load a0 1
a
Γs
ΓL b
Load
Γs
a1
s21
s11
s22 s12
Input loop b2 ΓL a2
b1
Equivalent circuits
a0 1
a1
Γs
Output loop a′0 1
a2
ΓIN ΓOUT b1
ΓL b2
ΓOUT
Figure 12.23 Signal flow chart for determining stability.
and | L | ≤ 1
(12.47)
Applying the constraint (12.45) for a stable condition to the input and output loops leads to | IN | < 1 and | OUT | < 1, respectively. It is now necessary to redraw the amplifier’s signal flow chat (Figure 12.23b) to the simplified equivalent chart (Figure 12.23 c) used above. IN has to consider the s11 -parameter but also the output embedding L · s11 as it is passed through the amplifier by s12 and s21 . A similar consideration holds for OUT . Consequently, the conditions | IN | < 1 and | OUT | < 1 can be expanded to s11 + s12 s21 L < 1 (12.48) 1 − s22 L s22 + s12 s21 S < 1 (12.49) 1 − s11 S The independent variable to solve equation (12.48) is L . The boundary case (using “= 1” instead of “ 1 is required but not sufficient for unconditional stability. To become a required and also sufficient criterion, then either |s12 s21 | < 1 − |s11 |2
(12.53)
|s12 s21 | < 1 − |s22 |2
(12.54)
or
Alternatively, a different definition of stability factors μ1 or μ2 known from the literature [12] can be used. For the unconditional stability of linear two-port devices, it is necessary
608
Amplifier measurements
Single ended transmission lines (a) (c) (b)
GND
GND
GND
(d)
GND
(e)
GND
Symmetrical transmission lines with ground (f)
GND
GND
(h)
(g)
GND
(i)
GND
(j)
GND
Symmetrical transmission lines ground suspended (m) (k) (l)
Figure 12.25 Typical single-ended and symmetrical transmission lines; (a) coaxial line,
(b) microstrip line, (c) triplate line (strip line), (d) coplanar line, (e) grounded coplanar line, (f) shielded twisted pair, (g) symmetrical microstrip line, (h) symmetrical triplate line, (i) symmetrical coplanar line, (j) symmetrical grounded coplanar line, (k) twisted pair, (l) suspended ground symmetrical microstrip line, (m) suspended ground strip line.
and sufficient to check one of the factors either μ1 > 1 or μ2 > 1 offering a compact criterion.
12.4.5
1 − |s11 |2 μ1 = ∗ s22 − s11 det(S) + |s21 s12 |
(12.55)
1 − |s22 |2 μ2 = ∗ s11 − s22 det(S) + |s21 s12 |
(12.56)
Mixed-mode S-parameters Symmetrical transmission lines (see Figure 12.25 f–m) are used in several applications because, when compared to single ended designs (see Figure 12.25 a–e), they offer improved immunity against EM interference and they come with reduced radiation due to mutual compensation of both symmetric conductors. Many antenna designs (dipole antenna, loop antenna) are based on differential feeding. To avoid the necessary balun with its imperfections and to benefit from differential design, a comprehensive concept including a power amplifier with differential ports and symmetrical transmission to the antenna offers a promising alternative to traditional single-ended concepts. If a signal is transmitted over a pair of symmetrical coupled conductors, interferences can be expected to be coupled into both lines equally. On the other hand, if the wanted signal is fed into one conductor with 0◦ phase shift and into the other conductor with 180◦ phase shift, it is very easy to distinguish the arising differential signal from the commonmode interferences. In the real world, however, a ground is usually present near the line.
12.4 Further linear measurements
609
Therefore, not only the desired differential-mode signal, but also a common-mode signal can propagate along the transmission line. A mode conversion between common and differential mode must be avoided since otherwise a clear distinction between the wanted signal and the interference is no longer possible. These considerations can be expanded to any four-pole structure used for differential signals (including differential power amplifiers). A description is required that allows a separate observation of the differential and common modes and that provides information about the mode conversion. Two physical ports with single-ended wave quantities a1 , b1 and a3 , b3 are combined to form a balanced port. From the four-pole theory the differential mode voltage v d = v 1 − v 3 , the differential mode current id = 1/2(i1 − i3 ), common mode voltage v c = 1/2(v 1 + v 3 ) and the common mode current ic = i1 + i3 are known. However, voltage and current are awkward in the microwave range. To adapt these to wave quantities ac , bc (commonmode wave quantities) and ad , bd (differential wave quantities) the well-known relation a = (v + iZ0 )/(4Z0 )−1/2 and b = (v − iZ0 )/(4Z0 )−1/2 with the related system impedances Z0 (single-ended), Z0c (common mode), or Z0d (differential mode) can be used to form a direct relation between single-ended and common-mode wave quantities or single-ended and differential-mode wave quantities: ∗
(2Z 0 + Z 0d ) (a1 − a3 ) + (2Z 0 − Z 0d ) (b1 − b3 ) √ ad = 4 Z 0d Z 0
(12.57)
∗
(2Z 0 − Z 0d ) (a1 − a3 ) + (2Z 0 + Z 0d ) (b1 − b3 ) √ bd = 4 Z 0d Z 0
(12.58)
∗
(Z 0 + 2Z 0c ) (a1 + a3 ) + (Z 0 − 2Z 0c ) (b1 + b3 ) √ ac = 4 Z 0c Z 0
(12.59)
∗
(Z 0 − 2Z 0c ) (a1 + a3 ) + (Z 0 + 2Z 0c ) (b1 + b3 ) √ bc = 4 Z 0c Z 0
(12.60)
The parts of formulas (12.57) to (12.60) that are marked with an asterisk will disappear if the differential mode system impedance Z0d and the common mode system impedances Z0c are selected so that they meet the following relation with the single-ended system impedances Z0 . Z 0d = 2Z 0
(12.61)
Z 0c = Z 0 /2
(12.62)
and
This means that single-ended and balanced-wave quantities can be transformed into one another without any mixing between incident and reflected waves. This is equivalent to a matched transition between a single-ended design (e.g., the test ports of VNA with Z0 = 50 ) and a symmetrical transmission line (e.g., offering characteristic impedances
610
Amplifier measurements
Z0d = 100 and Z0c = 25 ). Using the relations stated above, a VNA can measure balanced S-parameters by calculating them from single-ended measurements. This method is known from [13] as modal decomposition. During these measurements, the number of active ports is always one. But certain nonlinear balanced devices are sensitive to the excitation scheme, necessitating a true differential stimulus. This stimulus involves two active ports with the same stimulus frequency but adjustable phase relation, e.g., 180◦ (differential mode excitation) or 0◦ (common mode excitation). A balanced one-port device has two physical ports. Equivalent to formula (12.21), it can be described by means of reflection coefficients. dd dc ad bd = (12.63) bc cd cc ac Reflection coefficients cc and dd describe reflections that are within common or differential mode, whereas reflection coefficients cd and DC describe transmodal reflections that have incident and reflected waves belonging to different modes. A balanced two-port consists of four physical ports 1–4 that can be grouped as balanced port 1 (physical port 1, 3) and balanced port 2 (physical port 2, 4). The following is the multimode equivalent of formula (12.20). ⎡ ⎤ ⎡ ⎤⎡ ⎤ bd1 sdd11 sdd12 sdc11 sdc12 ad1 ⎢ bd2 ⎥ ⎢ sdd21 sdd22 sdc21 sdc22 ⎥ ⎢ ad2 ⎥ ⎢ ⎥ ⎢ ⎥⎢ ⎥ (12.64) ⎣ bc1 ⎦ = ⎣ scd11 scd12 scc11 scc12 ⎦ ⎣ ac1 ⎦ bc2
scd21
scd22
scc21
scc22
ac2
The upper left and the lower right quadrant of the mixed mode S-parameter matrix (12.64) describe S-parameters that belong to one certain mode. In contrast, the upper right and lower left quadrant describe intermodal S-parameters that have incident and reflected waves belonging to different modes. An ideal differential amplifier should exhibit those S-parameters as 0. Input and output reflection should be sdd11 = sdd22 = scc11 = scc22 = 0. The S-parameter sdd21 is responsible for the desired differential mode gain, while scc21 belongs to the common mode gain. Assuming the assignment of physical ports as above, the multimode S-matrix can be calculated from single-ended measurements (matrix S) as follows: ⎤ ⎤ ⎡ ⎡ ⎤ ⎡ ⎤⎡ bd1 1 0 −1 0 1 0 1 0 ad1 ⎥ ⎢ bd2 ⎥ 1 ⎢ 0 1 0 ⎢ ⎢ −1 ⎥ 1 0 1⎥ ⎥ ⎢ ⎢ ⎥ ◦ S ◦ ⎢0 ⎥ ⎢ ad2 ⎥ (12.65) ⎣ bc1 ⎦ = 2 ⎣ 1 0 1 ⎦ ⎣ ⎦ ⎣ ac1 ⎦ 0 −1 0 1 0 bc2 ac2 0 1 0 1 0 −1 0 1 A description of cascaded balanced systems and balanced de-embedding techniques can be found in reference [14]. Active or passive baluns are three-port devices that are used as an interface between the single-ended and the balanced world. Assuming port 1 as single-ended and
12.5 Nonlinear measurements
611
ports 2, 3 to form the balanced port 2, the following mixed mode S-parameter matrix can be stated. ⎤ ⎡ ⎤⎡ ⎤ ⎡ sss11 ssd12 ssc12 as1 bs1 ⎣ bd2 ⎦ = ⎣ sds21 sdd22 sdc22 ⎦ ⎣ ad2 ⎦ (12.66) bc2 scs21 scd22 scc22 ac2 The parameter sds21 describes the conversion from single-ended to differential mode and ssd12 describes the opposite direction. The matching of the balun is stated by sss11 , sdd22 , scc22 . The parameter scs21 and ssc12 are the unwanted transmissions. Assuming the assignment of physical ports 1–3 as above, the multimode S-matrix can be calculated from single-ended measurements (matrix S) using ⎤ ⎡√ ⎤⎡ ⎤ ⎤ ⎡√ ⎡ as1 bs1 2 0 0 2 0 0 1 ⎣ bd2 ⎦ = ⎣ 0 (12.67) 1 −1 ⎦ ◦ S ◦ ⎣ 0 1 1 ⎦ ⎣ ad1 ⎦ 2 bc2 ac2 0 1 1 0 −1 1 The common-mode rejection ratio CMRR characterizes how much the separation of the differential mode and the common mode is maintained when the signal passes through the balun. It can be directly calculated from (12.66) depending on the direction of signal flow. |sds21 | (12.68) CMMR = 20 log10 |scs21 | or |ssd12 | CMMR = 20 log10 (12.69) |ssc12 |
12.5
Nonlinear measurements Power amplifiers are typically operated in the nonlinear region. Therefore, nonlinear measurements are of primary importance.
12.5.1
Intermodulation distortion (IMD) and harmonic distortion (HMD) Nonlinear distortions have been discussed extensively in previous chapters. IMD and harmonic distortion are explained by a Taylor series model of the DUT considering two-tone or single tone excitation, respectively. Figure 12.26 shows a typical output spectrum of an amplifier fed by a two-tone signal. The level differences DIM2 , DIM3 (in dBc) between LOUT (in dBm) at fundamental frequencies and a second- or third-order intermodulation product LIM2OUT or LIM3OUT (in dBm) are referred to as intermodulation suppression DIM2 , DIM3 . DIM2 = L OUT − L IM2OUT
(12.70)
DIM3 = L OUT − L IM3OUT
(12.71)
612
Amplifier measurements
20
LOUT/dB m
LOUT/dB m DIM3/dBc
15 10
DH3/dBc
DIM2/dBc
LIM3OUT/dB m
DH2/dBc
5 0
LIM2OUT/dB m
LH 3/dB m
–5
LH 2/dB m
–10 –15 f1 – f2
2f1 – f2 f1 f2 2f2 – f1
–20
2f1
2f2
3f1
f1 + f2
Ch1 Start 10 Hz
3f2
2f1 + f2 2f2 + f1 Stop 10 GHz
Figure 12.26 Spectrum analyzer readout with intermodulation products.
Two important properties that characterize the DUT are the second-order intercept point (SOI) IP2 and the third-order intercept point (TOI) IP3 . They can be related either to the input level LIN (in dBm) or to the output level LOUT = LIN + G (in dBm). Generally, intercept points IPn of nth order can be defined for higher-order intermodulation suppression DIMn (in dBc) according to L IP2IN = DIM2 + L IN DIM3 + L IN 2 DIMn = + L IN n−1
(12.72)
L IP3IN =
(12.73)
L IPnIN
(12.74)
L IP2OUT = L IP2IN + G = DIM2 + L OUT DIM3 + L OUT 2 DIMn +G = + L OUT n−1
(12.75)
L IP3OUT = L IP3IN + G =
(12.76)
L IPnOUT = L IPnIN
(12.77)
The level LIP3IN corresponds to the fictitious input level at which the output level LOUT of the fundamental frequencies and the output level LIM3OUT of the third-order intermodulation product are the same value. IP3 is not attained in most cases due to saturation effects, but it is useful for a global characterization of the DUT. Using it, the two straight lines for LOUT and LIM3OUT can be constructed immediately without requiring
12.5 Nonlinear measurements
613
LOUT dB m IP2 LIP 2OUT IP3
LIP 3OUT
LOUT
LOUT
2 dB m
1 dB m
LIM 3OUT
1 dB m
LIM 2OUT Saturation
3 dB m
DIM 2(Lx)
DIM 3(Lx)
1 dB m
1dB m
Lx
LIP3IN
LIP2IN LIN dB m
Figure 12.27 Second- and third-order intercept points [4].
any additional information (see Figure 12.27), and the intermodulation suppression DIM3 for various input levels can be predicted. On the other hand, the intercept points IP2 and IP3 can be determined graphically using the straight-line slopes outside the saturation area in order to construct the point IP3 (LIM3IN , LIM3OUT ) in the power sweep (Figure 12.27). However, measurements are typically performed as shown in Figure 12.26, yielding the values (LOUT , DIM2 , DIM3 ) only for a certain input level LIN . When applying formulas (12.72) to (12.77), the user must make sure that the DUT has not been measured in its saturation area. The two-tone stimulus can be generated using two RF generators with the same output level. All instruments should be synchronized to a common frequency reference, e.g., the internal reference of generator 1 (see Figure 12.28). Lowpass filters can be applied to reduce higher harmonics of the driving signals beyond the 50 dBc of a highend signal generator. One main aspect is to avoid any significant intermodulation in the instrumentation so that measured values can clearly be assigned to the DUT. A difference of at least 10 dB between DUT and instrumentation is a rule of thumb. Typical problems experienced in a measurement setup are as follows: 1. The mutual intermodulation between the two signal generators must be reduced by applying a coupler or Wilkinson divider and optional isolators. 2. A booster amplifier to amplify the two-tone signal should be avoided. Instead, separate amplifiers should be used for each tone.
614
Amplifier measurements
Generator 1 Lowpass Frequency f1 Driver Magnitude A1=A(optional) (optional)
Bias source
10 MHz Reference
G
Isolator (optional) 10 MHz Reference
Combiner network Isolator (optional)
High-power attenuator or coupler with dummy load
DC
Z0
Amplifier under test
Spectrum analyzer
Two-tone stimulus
Z0 Typical combiner networks Power splitter Coupler or Wilkinson Power divider
G
Generator 2 Driver Lowpass Frequency f2 (optional) (optional) Magnitude A2=A
Z0 Z0
Matching towards DUT Matching towards inputs
typ. > 20 dB typ. < 12 dB
Isolation between inputs
typ. < 12 dB
Insertion loss
typ. > 6 dB
Z0/3 Z0/3 Z0/3
Z0
typ. > 20 dB typ. > 20 dB
typ. > 20 dB typ. > 20 dB
typ. < 6 dB
typ. > 20 dB
typ. > 6 dB
typ. > 3 dB
Figure 12.28 Measurement setup for intermodulation measurements.
3. Passive intermodulation (PIM) occurs in passive devices. If connectors are not tightened properly or if their contacts are dirty, oxidized or made of two galvanically unmatched metals, these junctions form a weak nonlinear transition. If circulators or transformers are operated to saturation, they also behave as nonlinear components. The PIM is typically below −110 dBmc, and high power levels are required for these effects to occur. 4. To assess the intermodulation of the spectrum analyzer, its step attenuators can be used. Since these mechanical attenuators consist of passive resistor networks, their intermodulation effects are negligible. If the step attenuator is increased, the input level of the internal receiver will decrease. The attenuator setting is compensated on the display so that displayed power remains constant. Inter-modulation products that are generated outside the spectrum analyzer will behave the same. In contrast, intermodulation generated in the spectrum analyzer will vary by more than the attenuator setting and can therefore be distinguished. For some devices (e.g., FET), the IPn also depends on the input level because these devices defy a Taylor series approximation. A simplified setup can be achieved by reducing Figure 12.28 to only one signal generator to measure the harmonic distortion (HMD). Because no second tone is present, only harmonics LOUT , LH2 , LH3 , . . . , LHk at f1 , 2f1 , 3f1 , . . . , kf1 will occur at the measurement
12.5 Nonlinear measurements
615
result (Figure 12.26). The harmonic suppression DHn (in dBc) can be calculated from the output level LOUT (in dBm). D H n = L OUT − L H n .
(12.78)
As with equations (12.74) and (12.77), an nth order intercept point for harmonics can be calculated using DHn instead of DIMn . A quite different approach is to use the harmonic suppression values DH1 and DH2 to predict the intermodulation suppression DIM2 and DIM3 as presented in reference [15] or [16]. Based on the DIM2 and DIM3 values an intercept point related to intermodulation can then be predicted. However, this calculation assumes that the Taylor series is a valid approximation of the DUT, which may be doubtful in the context of power amplifiers. D H 2 = DIM2 + 6.02dB
(12.79)
D H 3 = DIM3 + 9.54dB
(12.80)
The total harmonic distortion (THD) is calculated from the sum of all higher harmonic powers divided by the power at fundamental frequency. It can be calculated from the output level at fundamental frequency Lout (in dBm) and the higher-order harmonic levels LHn (in dBm). ⎛$ ∞
10(L H n /10)
⎞
⎜ n=2 ⎟ ⎟ THD = 10 log10 ⎜ ⎝ 10 L OUT /10 ⎠
12.5.2
(12.81)
Compression point The saturation effect seen on the fundamental frequency (see Figure 12.27) is used to define the 1 dB compression point. This is the point (LIN1 dB , LOUT1 dB ) at which the level LOUT is 1 dB less than the expected value assuming a linear increase. Most power amplifiers are specified by the output level LOUT1 dB and not the input level LIN1 dB of the 1 dB compression point. A VNA supplemented by high-power setup (see Section 12.3.7) and calibrated using a power meter is a convenient way to achieve a power sweep and to find the compression point on the s21 trace as a drop by 1 dB (see Figure 12.29). This can be automated by marker functions providing LIN1 dB and LOUT1 dB levels. It is also common practice to define a 0.1 dB compression point. In some literature e.g., [15], the relation between the output-related 1 dB compression point LOUT1 dB and the output-related third-order intercept point LIP3OUT may be found as LOUT1 dB = LIP3OUT −10.63 dB. However, it is only valid if the Taylor series approximation holds true for the DUT, which is typically not the case for power amplifiers. As a rule of thumb a difference of typically 10 dB to 15 dB is observed in real-world examples.
616
Amplifier measurements
File Trace Channel Display System Window Info Help Compression Level:
1 dB
Trace Punct Trace Statist Min/ 1 Max/ Peak-Peak
Close 1 dB Compression Point
Trc1 S21 dB Mag 1dB/ Ref 0 dB •Mkr 1 –14.40 dB m
S21 26
Trace Statistics Cmp In: Cmp Out
25
2.826 dB Mean/ Std Dev 11.7 dB m 23.5 dB m RMS
24 Mkr 1
Phase Delay/ El Length Cmp
22
Compression Point
21
Define Compression Value... Eval Range ...
20 –21 –22
Ch1 Mix Start -15 dB m
Freq 4 GHz
Stop 15 dB m
- Menu UpLOCAL
Figure 12.29 A power sweep with automated compression point measurement [4].
12.5.3
Large-signal network analysis A current application of harmonic measurements is to reconstruct the time domain signal at the input and output of a DUT. Time domain analysis provides deep insight into an amplifier’s operating class (A, B, AB, etc.) and helps to select the optimum bias point. Traditional time domain analysis involved oscilloscopes and was restricted to a maximum frequency in the GHz range and had a dynamic range of about 30 dB. This is not sufficient for up-to-date needs. A VNA operating in the frequency domain offers a dynamic range beyond 130 dB and a maximum frequency of 67 GHz or even higher. A VNA is able to measure absolute power levels but the phase is always measured relatively between test ports. It is not possible to yield meaningful phase information when displaying the phase of a wave quantity versus frequency. The phase will alter from sweep to sweep because there is no fixed phase relation between stimulus generator and the LO (see Figure 12.13). This is sufficient for S-parameter measurement because, from equation (12.19), the common arbitrary phase offsets of the wave quantities bi and ak cancels out. To obtain a stable phase for wave quantities, one of the receivers must be freed up so that it can receive the comb spectrum generated by the synchronizer. The synchronizer is driven by a fixed frequency that is adjusted prior to the measurement setup, and defines the frequency spacing of the comb spectrum (see Figure 12.30). The comb spectrum provides a set of constant phase relations for different frequencies which all wave quantities can be related to. This setup is often called a large signal network analyzer (LSNA).
617
12.5 Nonlinear measurements
LO generator Generator
3 GHz + fIF
1st Stimulus generator
2nd Stimulus generator
1 GHz
3 GHz
1 GHz
1 GHz
IFb1
IFa1
IFa2
IFb2
IFphase
Receiver section
Test set
Test port 1
1 GHz
External termination
Test port 2
3 GHz
DUT
Synchronizer
Figure 12.30 A VNA supplemented to form a LSNA according to reference [17].
After the comb generator has been configured, a receiver and stimulus level calibration must be performed using a power sensor followed by a receiver phase calibration using a precision phase reference. These calibration steps also involve the use of a standard calibration kit. The following formulas are based on the Fourier series and the permissible assumption of real-valued time-domain wave quantities a(t), b(t). N −1 2π nm 2 |a( f 0 · n)| cos a(t · m) = + arg(a( f 0 · n) 2N − 1 n=1 2N − 1
(12.82)
N −1 2π nm 2 |b( f 0 · n)| cos b(t · m) = + arg(b( f 0 · n) 2N − 1 n=1 2N − 1
(12.83)
t =
1 f 0 (2N − 1)
(12.84)
In the above equations, the time resolution t is based on the fundamental frequency f0 and the number of harmonics N. Applying techniques such as windowing or extrapolation with linear prediction to the frequency-domain samples may lead to further improvement. The time-domain voltage v(t) and current i(t) can be calculated from the wave quantities a(t) and b(t) and the reference impedance Z0 and the DC values measured from the bias condition (v DC , iDC ): v(t) = Z 0 (a(t) + b(t)) + v DC (12.85) 1 (12.86) i(t) = √ (a(t) − b(t)) + i DC . Z0 An example of v(t) and i(t) of an AB class amplifier is shown in Figure 12.31.
Amplifier measurements
7
160 m
6
140 m 120 m
5 4
A
V
100 m 80 m
3
60 m
2
40 m 20 m
1
0 0
500 p
1n Time (s)
1.5 n
2n
0
500 p
1n Time (s)
1.5 n
2n
Figure 12.31 Voltage and current at an Excelis EPA120B amplifier output driven with 1 GHz
sinusoidal input, courtesy of [17].
160 m 140 m 120 m V(m)
100 m A
618
80 m 60 m 40 m 20 m 0 0
2
4
6
V
Figure 12.32 Dynamic load line corresponding to Figure 12.31, courtesy of reference [17].
The waveform of the output current is typically described using the conduction angle α (in ◦ or rad). It represents the proportion of the RF cycle for which the device is active. Figure 12.31 displays a conduction angle α = 360◦ · 700 ps/1 ns = 252◦ . A typical visualization tool is the dynamic load line as shown in Figure 13.32. The tuple of drain voltage and current (vD (t), iD (t)) of a complete RF cycle are plotted on top of the DC IV curves that have been precharacterized for different gate voltages. Figure 13.32 uses a color code (reprinted in gray scale) to assign the relevant gate voltage to all measured voltages. It reveals that a gate voltage down to −1.8 V is used and that a phase shift between dynamic gate voltage and static IV curves occurs. By changing the external termination in Figure 12.30 from match to open the influence of load termination on the dynamic load line can be studied, which leads to the topic of the next section.
12.5 Nonlinear measurements
619
Load/source-pull principles Passive Principles
Solid-state tuners
Active principles
Mechanical tuners
Active loop
Source signal splitting
DUT DUT
Slide screw tuner Slug
y
Stub tuner y
y
x
Mechanical sketches
x
Short or open
Iy Z0 I0 - Ix
Zy
Z0
Iy
Ix
Single screw tuner x and y movement necessary
Equivalent circuits
Z0 Z0 Ix
Multiple screw tuner
Prematching tuner Combines 2 slugs to yield high Γ
Z0 I0 – Ix
Single stub tuner x and y movement necessary
Non-varying x tuner 2-3 slugs to avoid x movement
Multiple stub tuner
Prematching tuner Combines 2 stubs to yield high Γ
Non-varying x tuner 2-3 stubs to avoid x movement
Figure 12.33 Source- and load-pull principles.
12.5.4
Load- and source-pull measurements A good power amplifier design utilizes the power capability of an active device with good efficiency for a specified complex modulated signal. One of the main tasks is to design optimal input and output matching. A straightforward approach is to determine the required impedances by varying the source impedance S and load impedance L provided to the active device using a measurement setup called a load- and source-pull system. Figure 12.33 provides an overview of principles that can be applied. Active systems are based on injecting signals with adjustable phase and magnitude to mimic the reflected wave of a specific load impedance. The required signal can be generated from an active loop or branched from the stimulus source. These techniques offer the unique capability to synthesize load impedances with || = 1 or (to compensate
620
Amplifier measurements
Bias DUT
Tuner 3f0 influences f0
Tuner 2f0 influences f0
Power sensor
Tuner f0
Figure 12.34 The cascaded tuner method of harmonic load-pull.
Bias Power sensor
Tuner f0 DUT
Triplexer (losses, band limitation)
Tuner 2f0
Match
Tuner 3f0
Match
Figure 12.35 The triplexer method of harmonic load-pull.
for losses) even || > 1. However, active systems include the risk of oscillation due to a loop architecture or when || > 1 is directly applied to the DUT. Passive tuners operate like adjustable line transformers. They employ cascaded transmission lines, where some of them have adjustable impedances and positions (slide screw tuner) or a variable shunt susceptances of one or more short-circuited variable length lines (stub tuner). The number of elements (slugs or stubs) can be increased to eliminate x movement or to yield a high VSWR value of approximately 200:1 from a combination of medium VSWR elements. Tuners can be operated manually or automated by precision stepping motors. Alternatively, several fixed stubs can be combined by a PIN-diode switching network to eliminate the mechanical problems (response time, wear-out) but with the tradeoff of additional losses and reduced power handling capability. An amplifier’s efficiency is considerably improved by shorting its higher harmonics 2f0 and 3f0 which means that reflection factors of ideally | L (2f0 )| = 1 and | L (3f0 )| = 1 with an adjustable phase are required. Fundamental tuning, which controls only the load condition L ( f0 ) at the fundamental frequency f0 , can be expanded by additional hardware to control the load condition at one or more harmonics (harmonic tuning). With a cascaded structure (Figure 12.34), the harmonic tuners 3f0 and 2f0 are typically placed next to the DUT to avoid unnecessary degradation of | L (2f0 )| and | L (3f0 )| due to losses. Stub tuners or prematching tuners used for this purpose are optimized. But tuning the harmonics has a significant effect on the fundamental impedance, requiring its re-tuning after the harmonics are set and vice versa. This may lead to an iterative process. The triplexer method (Figure 12.35) uses filters to decouple the tuners and allows independent tuning of f0 , 2f0 , and 3f0 . The main disadvantage of this method is limited bandwidth caused by the filters/triplexer. Active harmonic pull (Figure 12.36) can be achieved in several ways. It can even be combined with passive tuners to boost their | L (2f0 )| and | L (3f0 )| values.
12.5 Nonlinear measurements
621
3f0 2f0 f0 Bias DUT
Figure 12.36 Harmonic active load-pull setup.
Dual channel power meter
PC
Automatic bias supply Remote control Tuner controller Power Booster sensor and “A” isolator (optional) RF source
High-power Filter and attenuator (optional) isolator (optional) Tuners
DUT
Power sensor “B”
Tuners
Input block
Output block
Figure 12.37 Source- and load-pull setup for performing power measurements.
The block diagrams can be supplemented to form the complete load- and source-pull setup shown in Figure 12.37. It is used to perform typical power measurements. During a precalibration step with a VNA directly connected to the input or output block, the S-parameters of various tuner settings are obtained. After calibration, a required load and source impedance combination can be synthesized automatically by the tuner control software. The DUT measurement relies on the power measurements performed by two power sensors and a correction scheme that calculates the available input power PAS at the DUT from the available gain of the input block (see formula (12.33)) and the readout of power sensor A. By taking the delivered power (power sensor B) and the operating power gain (see formula (12.34)) of the output block, the delivered power PDO from the DUT can be calculated. Using these two corrected measurement values, the transducer gain can be calculated as follows: G T,DUT =
PAS PD O
(12.87)
622
Amplifier measurements
Other typical properties can be analyzed as a function of the load/source match: r PAE2 calculated from formula (12.41); r harmonic distortion using a spectrum analyzer instead of power sensor B; r intermodulation distortion by replacing the RF source with a two-tone source as described in Figure 12.28 and using a spectrum analyzer; because tuners synthesize the desired impedances only in a narrowband manner, spacing of the two-tone signal must be selected carefully. The impedance setting of the tuner cannot be monitored during DUT measurement. The measurement relies on the repeatability of the tuner. One means of verification is to replace the DUT by a through with known S-parameters. Using formula (12.32), the transducer gain GT of the through can be predicted for various source- and load-pull settings ( S , L ). These values are then compared to the transducer gain measured as described above. Before the delivered input power at the DUT can be calculated, the input reflection factor of the DUT must be determined. This measurement also reveals that the input reflection factor depends on both the power level and the load matching. To do this, power sensor A and its coupler are replaced by the test set of a VNA. The VNA is calibrated to the input of the source tuner, and the reference plane is then shifted to the DUT, thus de-embedding the input block by its known S-parameters. Similar measurements can be done at the output to obtain the available power of the DUT. The tuner and coupler can be interchanged so that the coupler is next to the DUT. For greater insight, this arrangement can be used with a LSNA (see Figure 12.30). The influence of the LSNA’s test set has to be included in the source/load block characterization (precalibration step of tuners). The test set’s loss may prevent the system from applying the tuner’s maximum || to the DUT.
12.5.5
Hot S-parameters The characteristics of PAs are power-level dependent, especially since the amplifiers are operated near their 1 dB compression point. Besides the gain compression of s21 as shown in Figure 12.29, other changes in characteristic values like s22 can be recognized. It is therefore necessary to perform measurements under real operating conditions. As described in Section 12.3.3, a standard s22 parameter measurement would be performed in reverse operation. This means that the stimulus at port 1 is switched off, and port 2 becomes the active port instead. This does not correspond to the original operating condition. In the hot s22 measurement, the amplifier has an input signal at the operating frequency f1 applied to it. The level of this signal is configured such that the amplifier exhibits the output power level that it is designed for. At the same time, a reflection measurement is performed at the output at the probe frequency f2 = f1 + f. The power used for this probe tone is significantly lower than the amplifier’s output level (typically −30 dB lower). The a2 -wave and b2 -wave are recorded at the probe frequency f2 . Depending on the shape of IF filter used in the VNA, the frequency spacing f should be three
623
12.6 Modulated measurements
S22
S22 without stimulus at port 1
0
Hot S22 -10 -20 Port Configuration -30
#
-40 -50
Receiver
Meas Physic Source Gen
Frequency
Frequency Result
Power
Power Resu Frequency Frequency Result
Port 1
fb
1.4 GHz … 3 GHz
Pb
12 dB m
Port 2
fb + 10 MHz
1.41 GHz … 3.01 GHz
0 dB m - 20 dB
-20 dB m
Port 3
fb
1.4 GHz … 3 GHz
Pb
12 dB m
Port 4
fb
1.4 GHz … 3 GHz
Pb
12 dB m
fb + 10 MHz
1.41 GHz … 3.01
-60 -70
Displayed Columns…
Balanced and Measured Ports…
Measure "a" Waves at Receiver Frequency
Freq Conv Off
Source Frequency Stimulus…
Same Connector Type at All Ports
-80 OK
Arb Start 1.4 GHz
Pwr -25 dB m
Cancel
Help
Stop 3 Ghz
Figure 12.38 Hot s22 measurement performed using a state-of-the-art VNA and the DUT present between port 4 (input) and port 2 (output).
to ten times the value of the IF bandwidth to ensure sufficient separation between operating frequency and probe tone. Nevertheless, the S-parameter measured at f2 is close enough to f1 to determine the output impedance of the amplifier at f1 under regular forward operating conditions. The example in Figure 12.38 has been measured with a state-of-the-art VNA, which involves two internal stimulus generators configured in the dialog additionally shown. System error correction is used to ensure traceable results. The concept of hot S-parameters can be expanded to use it in a load-/source-pull environment [18]. A further extension is to use the intended modulation pattern at frequency f1 , as the real-world operating signal of the amplifier [19]. This will lead to the discussion in the next section.
12.6
Modulated measurements For wireless information transmission, a sinusoidal carrier is modulated by a baseband signal that contains the desired information. The most significant effect for power amplifiers is that modulation usually causes a time dependent variation of the carrier magnitude which is referred to as “modulation envelope.” The nonlinearities described in Section 12.5 cause imperfect reproduction of the amplified signal resulting in distortion and channel interferences. This section describes the measurement of the relevant figures of merit.
624
Amplifier measurements
12.6.1
Crest factor and CCDF The peak-to-average power ratio (PAR) describes the relation between the peak power and the average power of an RF signal and is usually stated in dB. Instead of the power the crest factor (CF) may use other parameters such as voltage or current. In this case, the average value has to be replaced by the rms value. Assuming the related impedances to be independent of the level (linear approach), then the resulting crest factors will be the same as those derived from the power ratios. The first definition calculates the crest factor CF1 based on the highest amplitude peak power PMAX that occurs in the modulated carrier signal and its average power value PAVG . PMAX C F1 = 10 log10 (12.88) PAV G The second approach, which leads to a smaller crest factor CF2 , uses the ratio of the peak envelop power PPEP of the modulation envelope to its average value PAVG (see Figure 12.4 of Section 12.2.1). PPEP (12.89) C F2 = 10 log10 = C F1 − 3.01 dB PAVG The crest factor of periodic signals (e.g., CW, regular pulsed CW) can be measured by comparing the results of a peak power sensor and a thermal power sensor. But this is not the case with random modulated signals such as OFDM, CDMA, and WCDMA. Due to their statistical nature, a very long observation time (e.g., several years) would be necessary until their exact peak power occurs again in the signal. A compromise using a practical observation time (seconds or minutes) is necessary. For these measurements, high-end spectrum analyzers provide the necessary functionality. They also display the measured complementary cumulative distribution function (CCDF), which describes the statistical probability of the occurrence of signal peaks that are greater by a factor of k in dB than the average value. Here, too, it is important to distinguish whether values are related to the carrier or the envelope. The CCDF helps the operator to consider the right observation time and makes it possible to compare the degradation of the CCDF due to compression or clipping effects. Aside from multiple carrier modulation techniques (e.g., OFDM), other applications such as satellite repeaters or cellular base stations require simultaneous amplification of multiple signals by multicarrier power amplifiers (MPCPA). An MPCPA has to cope with an increased crest factor different from that of single carrier operation, even if the individual signals exhibit a crest factor of CF2 = 0 dB (e.g., constant amplitude modulation pattern). Therefore testing of an MPCPA must be performed with an adequate multicarrier signal. Considering thermal issues the average power PAVG is most important. However, the highest amplitude peak power PMAX or its related voltage are responsible for flashover and possibly a standing arc as well as intermodulation effects.
12.6 Modulated measurements
625
RBW 10 MXs Ref 11.7 dB m
Att 40 dB
ACT 312.5 xs
0.1
A 0.01 1 SA CLRWR
2 SA VIEW
1E-3 1E-4
Before predistortion
After predistortion
1E-5 1E-6
Center 690 MHs
2 dB/
Mean Pwr + 2c dB
Comlementary Cumulative Distribution Function (10000000 samples) Trace
Mean Peak Crest 10% @ 1& @ .1% @
1
Trace
2
-3.54 dB m 6.10 dB m 9.64 dB
-3.55 dB m 5.60 dB m 9.16 dB
3.65 dB 6.47 dB 7.92 dB
3.65 dB 6.28 dB 7.53 dB
Figure 12.39 CCDF of a DVB-T signal (OFDM) measured at a PA output (envelope related values) before and after predistortion [20].
Figure 12.40 Influence of a nonlinear amplifier on a multitone signal.
12.6.2
Adjacent channel power ratio (ACPR) Each wireless device operates in a specific frequency channel to which it has been assigned, which will be temporary when using frequency hopping. Leakage of the channel power can lead to interference with other services. A two-tone approach to mimic the scenario was introduced in Section 12.5.1. The third-order intermodulation products have been identified as particularly disruptive since they are relatively close to the useful signal and are difficult to suppress by filtering. Therefore, they normally affect adjacent channels. To obtain a more realistic scenario, the number of tones with equal amplitudes has to be increased to N 2. Assuming the tones are equally spaced with f, the Taylor series model will lead to a spectrum similar to that in Figure 12.40. The third-order intermodulation products form a spectral re-growth of N − 1 tones on both sides of the N-tone channel.
626
Amplifier measurements
Simplified block diagram of a spectrum analyzer:
Remote control (Optional e.g. for Sweept ACPR Measurements)
PC
Step Attenuator
1st IF
RF -18 dB m RMS -6 dB m peak
10 MHZ
Q
I=44.1 MHz, P=-18dB m Modulation: ON IQ Input : EXTERN Ref. Osc. : INTERN
-18 dB m RMS -6 dB m peak
-19.3 dB m RMS -9.3 dB m peak
Spectrum analyzer
Baseband generator Data
Analog filter Log. Amp. & DSP 3rd IF
1st mixer
TRG
I I Q RF
: 44.1 MHz
Stop Att Ref. Osc. Rof. Level RBN SWP Tine Detector
: 30 dB : EXTERN : 0 dB : 30 kHz : 2s : RMS
RF
19 dB m (RMS) 31 dB m (peak)
DUT
I/Q-Modulated RF generator
Contor
Amplifier under test (e.g. with Pull-environment)
High-power attenuator (optional)
Figure 12.41 Typically setup to perform ACPR measurements.
The ACPR or adjacent channel leakage ratio (ACLR) is a commonly accepted metric for quantifying the effect of spectral regrowth for digitally modulated signals. The ratio is usually expressed as the total power over a certain frequency band B adjacent to the main channel versus the total power in the main channel. The total powers can be determined by integrating the appropriate power spectrum p( f ) over the relevant frequency ranges. In some cases, an frequency response H( f ) of the pulse-shaping filter (typically raised cosine) is applied. The ACPR has the unit dBc. It depends on the signal characteristic (e.g., modulation standard, power, frequency channel, number of coded channels in OFDM). Usually a distinction is made between upper ACPR and lower ACPR referring to the leakage above or below the main channel. A typical example of spectral leakage caused by an amplifier is sketched in Figure 12.41 at the DUT’s output. Additionally, an alternate channel power ratio (ACPR2) is specified using a higher frequency offset than the ACPR. The integrated and weighted adjacent channel powers can be expressed by the levels LUP (in dBm) or LLOW (in dBm) of upper or lower channels, respectively. The integrated and weighted main channel power is stated by the level LCH (in dBm). ⎞ ⎛ ( p( f ) |H ( f )|2 d f ⎟ ⎜lower channel ( (12.90) ACPRLOW = 10 log10 ⎝ ⎠ = L LOW − L CH p( f ) |H ( f )|2 d f ⎛
main channel
(
⎜upper channel ( ACPRUP = 10 log10 ⎝
p( f ) |H ( f )|2 d f p( f ) |H ( f )| d f 2
⎞ ⎟ ⎠ = L UP − L CH
(12.91)
main channel
The integrated bandwidth method uses a spectral integration to calculate the channel level LCH . It can be performed using a spectrum analyzer with the resolution bandwidth
12.6 Modulated measurements
627
BRBW set narrow compared to the channel bandwidth BCH (typically BRBW /BCH = 0.5 to 5%). The minimum time tSWP necessary for one frequency sweep of F can be estimated using a typical factor C = 3 and the following formula. tSWP = C
F 2 BRBW
(12.92)
Because of the modulated signal’s random nature an RMS detector and a manually increased sweep time of about 15 · tSWP is required to yield a stable trace. To calculate the level LCH the individual levels Ln of the N frequency samples in the relevant frequency range have to be summed up according to formula (12.93). A correction factor KRBW = 1.06 to 1.14 is used to obtain the noise equivalent bandwidth from the resolution bandwidth BRBW . The term |H(f · n)|2 with the frequency step-width f is used to implement the spectral weighting.
N BCH 1 (12.93) · |H ( f · n)|2 · 10 L n /dBm L CH PWR = 10 log10 K RBW · BRBW N n=1 The levels LLOW and LUP can be determined in a similar way. Automatic spectrum analyzer functionalities are available for these numeric calculations. A typical setup for performing ACPR measurements on a power amplifier is shown in Figure 12.41. It consists of an IQ-modulated RF source (depending on the modulation scheme using an external baseband generator) and a high-end spectrum analyzer. A trigger signal (see Figure 12.41 signal “TRG”) or a broadband level detector inside the spectrum analyzer (RF trigger) has to be used when measuring TDMA systems. These systems pulse their signal power to provide timeslots for other services. Measurement values should only be recorded within the active timeslots (burst) and the sweep must be paused outside the active timeslots. The ACPR caused by the transient effects cannot be detected correctly by the integrated bandwidth method due to the fact that its narrowband resolution filter (BRBW ) causes a comparably long settling time. An alternative method described in the next paragraph is preferred in these cases. The method of channel power measurement in time-domain is a different approach that omits formula (12.93). Using digital signal processing then any type of channel filter H( f ) can be digitally implemented in the spectrum analyzer. This allows channel power measurements in the time domain with the spectrum analyzer working like a tuned receiver. In this way it is possible to obtain a short measurement time. The method yields much better reproducibility of results and detects transient signals (e.g., from TDMA systems) correctly. If several channels are to be measured the spectrum analyzer successively tunes to the respective channel center frequencies. One main aspect of all the methods is to avoid any significant ACPR from occurring in the spectrum analyzer. A simplified block diagram of a spectrum analyzer is shown in Figure 12.41, upper right. The available dynamic range of the spectrum analyzer has to be considered to ensure minimal phantom reception in the adjacent channels: The peak power of the measured channel has to be within the linear region of the first mixer and the stages in front of the IF filter (RBW). The step attenuator can be used to
628
Amplifier measurements
ACPR/dBc −50 −55 −60 −65
Total ACPR
−70 −75 −80
ACPR due to inherent spectral regrowth
ACPR due to inherent noise floor
−85 −90 −95 −24
−22
−20
−18
−16
−14
−12
−10
−8
−6
−4
Mixer Level/dB m
Figure 12.42 Contributions for inherent ACPR of a high-end spectrum analyzer dependent on its
input mixer level [22].
optimize the peak envelope power level at the first mixer to a value 10 dB below the 1 dB compression point of the first mixer. The noise floor determines the lower limit for power measured in the adjacent channels. A spectrum analyzer’s noise figure NF is typically in the range of 13 dB to 19 dB. A correction factor KH( f ) is used to obtain the noise equivalent bandwidth for the pulseshaping filter H( f ). The thermal noise power level NCH within the channel bandwidth BCH can be calculated according to the following formula. K H ( f ) BC H dB + NF (12.94) NCH = −174 dBm + 10 log10 1 Hz In this example a noise figure of NF = 15 dB, a channel bandwidth of BCH = 4.096 MHz and a correction factor K ≈ 1 (typical K for all common H( f )) is assumed. Therefore, formula (12.94) leads to a noise power level of NCH = −92.8 dBm. The phase noise of the spectrum analyzer’s internal local oscillators leads to an inherent noise in the adjacent channel (reciprocal mixing). The spectrum analyzer assumed in this example exhibits a contribution of 85 dB below the transmit carrier which can be neglected. The dynamic range can be visualized as shown in Figure 12.42. The horizontal axis of the diagram shows the channel power at the first mixer. This is the signal power at the spectrum analyzer’s RF input minus the step attenuator setting (see Figure 12.41, upper right). The vertical axis shows the inherent contribution of the spectrum analyzer
629
12.6 Modulated measurements
Ref Lvl –30 dB m
Marker 1 [T1] -102.04 dB m 1.99250000 GHz
RBW vBW SWT
30 kHz L MHz 2s
−30
1
−40
RF Att Unit
[T1]
CH PWR ACPR Up ACPR Low
−50
0 dB dBm
–102.04 dB m 1.99250000 GHz –17.99 dB m –62.60 dBc –62.64 dBc
−60 1RM −70 −80 −90 −100 −110 −120 cI1
cI1
CO
CO
cu1 cu1
−130
Center 2 GHz
1.5 MHz
Span 15 MHz
Figure 12.43 Display of ACPR test result [21].
to the ACPR for a channel bandwidth of BCH = 4.096 MHz (in this example). The contribution due to the spectrum analyzer’s thermal noise floor reduces with increasing input level and is described by a slope of −1 dBc/dBm. The ACPR due to inherent spectral re-growth increases with a 2:1 slope like third-order intermodulation products (see multitone approach at the beginning of this section). The 2:1 slope will be shifted vertically depending on the crest factor of the signal applied. This is due the fact that the horizontal axis relates to the channel power while the spectrum analyzer’s inherent intermodulation depends on the peak power applied. In Figure 12.42 a wideband CDMA signal with a crest factor CF2 = 12 dB was assumed. This value also depends on the type and number of coded channels. The power contribution of all these inherent effects can be combined to form the total inherent ACPR. The optimum total ACPR of 73 dBm is obtained with a first mixer input level of −16.2 dBm. An example using an −18 dBm channel power level and a step attenuator setting of 0 dB is shown in Figure 12.43. The measured ACPR values of about −62.6 dBc can clearly be assigned to the DUT’s broadband noise because Figure 12.42 reveals an inherent ACPR contribution of 72.6 dBc. This is 10 dB below the measured value and causes an error of approximately 0.5 dB.
630
Amplifier measurements
I
Intended vector
Error vector
Actual vector Q
Figure 12.44 Illustration of the error vector.
12.6.3
Noise–power ratio (NPR) As pointed out in Figure 12.40, the third-order intermodulation products of a multitone signal with N > 2 tones also affect the in-band level of the N-tone channel as the third-order intermodulation products coincide with some of the in-band signals. The noise–power ratio (NPR) assumes the amplifier is driven with Gaussian noise and a notch placed in one segment of its input spectrum. Nonlinearities cause power to appear in the notched band of the spectrum when the signal passes the amplifier. The NPR is the ratio of the notch power to the total signal power. The numeric calculation presented with formula (12.93) can easily be adapted to the needs of this measurement. The RF source of Figure 12.41 has to be replaced by a suitable Gaussian shaped noise source and a notch filter. To prevent the mismatch of the stop-band of the notch filter at the amplifier’s input from interfering with the amplifier, an isolator should be inserted between the filter and the amplifier under test.
12.6.4
Error vector magnitude (EVM) and constellation diagram The EVM is a convenient metric of how intermodulation products, memory effects and noise contributions affect the detection process in the baseband. At the output of a power amplifier (which is located at the beginning of the transmission chain) noise contributions should be negligible. Memory effects are described in later sections. The EVM is defined as the distance between the intended and the actual signal vectors, normalized to a fraction of the signal amplitude (see Figure 12.44). The EVM is thus stated in percentage. It is important to distinguish whether values are specified as peak or RMS value. Typical modern communication standards require an EVM of 22 to 30% peak and 7 to 12% rms depending on the communication standard (details may be found in the applicable standards). A setup similar to that of Figure 12.41 can be used to measure the EVM, but the spectrum analyzer has to be replaced by a vector signal analyzer as shown in Figure 12.45. The first analog stages of both instruments are very similar. The samples obtained from
631
12.6 Modulated measurements
Re{X} Step attenuator RF
1st IF
A
3rd IF
D
I Digital filter
A/D converter
Analog filter
1st mixer
RAM
X
90°
NCO
Analog section
Q
Im{X}
Digital filter
IQ-Samples (baseband)
IQ Reference signal
Modulator
Demodulator
− + Synchronization
IQ
Fitting
IQ Error signal IQ Measurement signal
Figure 12.45 Block diagram of a modern VNA.
the digital IQ down-conversion process are stored in a random-access memory (RAM) instead of feeding them to the selected detector as normally occurs in a spectrum analyzer. A vector signal analyzer employs a digital-signal processor (DSP) to perform the following steps on the readout of the RAM. A combination of demodulator and modulator blocks is used to generate an undistorted IQ reference signal by employing the bit level between both blocks. The synchronization block compensates the measured signal (RAM readout) for center-frequency offsets, phase and symbol timing. The measured synchronized signal is then fitted to the undistorted IQ reference signal. The magnitude and phase parameters applied in this process correspond to the RMS value of the EVM. Finally, a comparison between the undistorted IQ reference signal and the measured IQ signal is carried out to provide magnitude and phase error versus time. The measurement values obtained in Figure 12.45 can be used to plot a constellation diagram. This diagram is the baseband representation of the individual symbols normalized to a complex plane spanned by −1 to + 1 and –j to + j. The transients between symbols may not be plotted. Ideally, each symbol is assigned to a single discrete point of the diagram. Practical measurements show a cloud pattern around each ideal constellation point. The size of the clouds and their center positions give important information (e.g., saturation effects will shift the outer constellation points towards the origin of the diagram or insufficient phase synchronization will lead to sickle shaped constellation points). Alternatively, the ideal and measured I or Q signals can be plotted versus time. This can help to detect certain symbol sequences that lead to maximum error, e.g., caused by memory effects.
632
Amplifier measurements
conscellation diagram 1 0.8 0.6
Imaginary part
0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1 −1
−0.8 −0.6
−0.4 −0.2
0
0.2
0.4
0.6
0.8
1
real part
Figure 12.46 Constellation diagram for a [21] DVB-T signal.
12.6.5
AM/AM and AM/PM measurements The various levels applied by high-order digital modulation schemes can be used to plot the amplitude error as a function of the ideal levels provided by the undistorted IQ reference signal. This diagram is also called AM/AM distortion characteristic. If the signal power is in the vicinity of the 1 dB compression point, the amplitude error can be used to predict a dynamic 1 dB compression point. A similar diagram called AM/PM distortion characteristic can be obtained from plotting the phase error instead of the amplitude error. A setup similar to Figure 12.41 involving a vector signal analyzer (Figure 12.45) can be used to perform the AM/AM and AM/PM measurements. The measurement result of Section 12.5.2, Figure 12.29 is very similar to the AM/AM measurement above. Instead of the magnitude in Figure 12.29 the phase of s21 also can be displayed leading to an AM/PM diagram. But the main difference to the discussion presented above is that the power sweep applied in Figure 12.29 exhibits a comparatively slow time gradient. For a memory-less amplifier the approaches of Sections 12.5.2 and 12.6.5 should lead to the same results.
12.6.6
Memory effects The Taylor series model assumed in Section 12.5 did not consider any dynamic effects. However, memory effects exist and create another type of distortion. Memory effects
12.6 Modulated measurements
633
are identified using variable-rate swept AM/AM measurements or applying pulsed measurements with variable pulse repetition rate. Memory effects also come to attention through the asymmetry in the output intermodulation products. Another result of memory effects is the AM to PM conversion. Memory effects can be classified as long-term and short-term. Long-term memory effects are caused by electro-thermal interactions, varying power supply, and electron traps. Short-term memory effects are a result of the transistor’s time delays that are modeled by energy storage elements such as capacitances or inductances. Nonlinear charge functions result in an instantaneous phase angle that is modulated due to the level-dependent instantaneous capacitance. Even linear charge functions combined with nonlinear conductance result in an instantaneous phase angle that is modulated by the varying instantaneous conductance.
12.6.7
Pulsed measurements Pulsed operation can be compared to a very simple modulation scheme that switches the carrier on and off (on-off keying). Radar applications use a very short RF burst of several tens of nanoseconds. Amplifiers for the mobile communication market such as GSM mobile phones are often designed for pulsed operation using their bias voltage to realize the “on” and “off” state. Continuous operation would damage the amplifiers due to overheating. The desired performance of these amplifiers can only be studied under pulsed conditions and measurements must be adapted to this requirement. A periodically pulsed signal can be described by its carrier frequency fc , pulse width tp and pulse period T (see Section 12.2.1 Figure 12.4). Some related parameters are the duty cycle D = tp /T and the pulse repetition frequency PRF = 1/T. The following measurements can be performed using a modern VNA. The point-in-pulse method, acquires the measurement data only during the on-state of the RF bursts. Therefore, it is necessary that the sampling time to acquire the measurement data is shorter than the pulse width tp . The sampling time is mainly determined by the measurement bandwidth of the analyzer. To obtain a sampling time of 200 ns (too long for some of the radar applications) a measurement bandwidth of at least 5 MHz is required. A sampling time of 0.500 ms (sufficient for most GSM mobiles) can typically be achieved with a 300 kHz measurement bandwidth. The resulting dynamic range (noise floor) is dependent on the measurement bandwidth used in the analyzer and therefore related to the pulse width tp . The dynamic rage can be improved using averaging, while keeping the measurement bandwidth to its needs. A trigger signal is necessary to ensure that data acquisition is done only during the on-state of the RF bursts. The point-in-pulse method is not suitable to analyze the very short transient state of the amplifier under test. In order not to acquire data during the transient state a trigger delay must be used and the acquisition time must be short enough to make sure that data sampling is only done at the settled roof of the pulse. The average pulse method uses a totally different approach. The pulsed signal can be described as a CW signal of frequency fc that is multiplied by a LF signal. The LF signal toggles between “0” and “1” state with the pulse repetition frequency PRF and a duty
634
Amplifier measurements
cycle D. The multiplication in the time domain is a convolution of the spectra of CW and LF signals in the frequency domain, i.e. a1 ( f ) =
∞ sin (π Dk) A1 (δ( f − f c ) + δ( f + f c )) ∗ D δ( f − k · PRF) 2 π Dk k=−∞
(12.95)
The convolution of equation (12.95) can be simplified. If a single sideband description is used (only frequencies f ≥ 0 are exclusively considered) then one would obtain a1 ( f ) =
∞ sin (π Dk) A1 D δ( f − f c − k · PRF) 2 k=−∞ π Dk
(12.96)
This is a comb spectrum that has a sin(x)/x envelop and is centered on the carrier frequency fc . To perform S-parameter measurements it is sufficient to observe the same specific tone in both wave quantities ak and bi (see formula (12.19)). For this purpose the spectral component at the carrier frequency fc is used because it exhibits the maximum power. The sin(x)/x envelop becomes 1 at this component. Thus, the magnitude obtained at frequency fc is scaled by the duty cycle D (see formula (12.96)). The measured power is therefore quadratically related to the duty cycle D. A duty cycle of D = 1% thus reduces the signal-to-noise ratio by 40 dB. The distance between two adjacent spectral components δ( f – fc– k · PRF) is given by the pulse repetition frequency PRF. In order to suppress all spectral components different from δ( f – fc ) a measurement bandwidth considerably smaller than the pulse repetition frequency must be selected (typically BRBW < PRF/10). To achieve a suppression of 40 dB and more, special high selectivity filters may be used. If necessary, the carrier frequency and the pulse spectrum can be shifted and the measurement can be repeated at that different carrier frequency. Proceeding like this yields a swept measurement result. The additional tones of the pulse spectrum are only used to support realistic operation conditions, like applying the correct bias voltage. The pulse profile method is intended to analyze the time dependent behavior of the DUT during a burst including analysis of the rise and fall time as well as overshoot and drop. For this purpose the measurement must have a time resolution significantly shorter than the pulse duration. To overcome the time resolution limit known from point-in-pulse method a variable trigger delay and a time window is used to “chop up” the pulsed signal into slices with different timing positions within the pulse. The trigger delay is kept constant over some hundred pulse instances. As a consequence the measurement bandwidth can be selected according to the average pulse method. The trigger delay is then increased and the next set of slices with a constant trigger delay is measured. Finally, the pulse waveform is reconstructed from the measurement results obtained at different trigger positions. The results measured on a pulsed power transistor are shown in Figure 12.48. The measurement was performed using two external couplers and a booster amplifier as described in Section 12.3.7 (Figure 12.17 right). The pulsed signal can be provided by a pulse modulator connected into the vector network analyzer’s generator path or by use of an external RF source that can be pulsed. In the lower half of Figure 12.48 an overshoot
635
12.6 Modulated measurements
Moment of observation
Pulse envelop of a1
t τD
τD “Sliced” pulses of a1
τD
2τD
2τD
2τD
3τD
3τD
3τD
Measurement with const. trigger delay
Floating trigger delay
t
Figure 12.47 An example of pulse chopping [23].
Trc6 S21 Phase 1°/ Ref 80 ° Cal Math S21
TRG
M4
M3
Ch1 Profile Start -10 μs
Freq 1.3 GHz Pwr 0 dB m
2 M1 20.0000 μs 81.277 M2 200.0000 μs M3 260.0000 ns 81.119 M4 2.0000 μs 82.969
Stop 20 μs
Trc7 S21 dB Mag 0.2 dB/ Ref21 dB Cal Trc8 b2 dB Mag 0.2 dB/ Ref51 dB m Math 3 M1 20.0000 μs 20.600 dB b2 TRG 51.8 M2 200.0000 μs M3 260.0000 ns 20.891 dB 51.6 M4 2.0000 μs 20.612 dB 51.4 M1 20.0000 μs 50.420 dB m 51.2 M2 200.0000 μs M3 M3 260.0000 ns 50.653 dB m 51.0 M4 2.0000 μs 50.261 dB m M3 M4 50.8 50.6 M4 50.4 50.2 Ch1 Profile Start -10 μs
Freq 1.3 GHz Pwr 0 dB m
Stop 20 μs
Figure 12.48 Pulse profile measurement of an radar transistor [22].
of s21 at the beginning of the pulse can clearly be identified as well as a phase deviation of approximately 2◦ that gradually settles.
12.6.8
Bit error ratio (BER) and symbol error ratio (SER) The figures of merit described in this section are related to signal quality. Digital modulation techniques allow some degradation of signal quality while causing almost no loss of information. Describing systems on a more abstract level requires a metric that
636
Amplifier measurements
characterizes the transmission quality. The BER is the number of erroneous bits received divided by the total number of bits transmitted. The SER is defined in the same way but considers the symbols which typically encompass several bits (e.g., 6 bits per symbol for the constellation diagram Figure 12.46). The measurement of the BER and SER is done using a bit error tester. For amplifier test a setup similar to Figure 12.41 is used. The baseband generator is used to form a pseudo random binary sequence (PRBS) that modulates the RF generator. The output signal derived from the amplifier under test is demodulated using a spectrum analyzer or another suitable receiver. The decoded bit stream is fed back to the baseband generator and synchronized. The data bits are checked for errors. The total of the transmitted bits and the faulty bits are counted. If the stream contains headers or guard bits, the counting process should be paused for those bits.
12.7
Noise measurements Active and passive circuits are subject to noise. Noise occurs in various forms such as thermal noise, Schottky noise, etc. Those that are relevant to RF amplifier design exhibit nearly uniform noise power spectral density. The thermal noise power PN0 that is available from a resistor at temperature T0 = 290 K (= 16.8 ◦ C = 62.3 ◦ F) to a matched load can be calculated as follows using Boltzmann’s constant k = 1.38 · 10-23 Ws/K and the noise equivalent bandwidth B: PN 0 = kT0 B = 4 · 10−21
W ·B Hz
(12.97)
corresponding to N0 = −174 + 10 log10
B Hz
dBm
(12.98)
The available noise power PNO (not the delivered noise power) is independent of the noise source impedance. The temperature T0 = 290 ◦ K used above has been set as a reference value by IEEE standards. The noise power PN typically exhibits very small values and is cumbersome to express. Since most noise calculations are based on summing up linear values, the dBm scale of N cannot serve as an alternative. The most convincing answer offering convenient values is to describe the noise power by a fictitious temperature. This noise temperature T does not mean that the device is at that physical temperature. PN = kTB
(12.99)
N = 10 log(kTB/1mW )
(12.100)
corresponds to
12.7 Noise measurements
12.7.1
637
Amplifier noise factor and noise figure This approach considers an amplifier embedded in a matched environment with a system impedance Z0 . The amplifier’s available gain Ga applies to both the signal power PSin and noise power PNin present at the input. In addition, the amplifier internally adds some inherent noise power PNa . Hence, the noise power exiting the amplifier’s output is PNout = G a PNin + PNa .
(12.101)
The signal-to-noise ratio PS /PN compares the signal power and the noise power, and this ratio will degrade when the signal passes through an amplifier. The noise factor F is the ratio of the signal-to-noise power ratio PSin /PNin at the input divided by the signal-tonoise power ratio PSout /PNout at the output. By definition, the input noise power is given by equation (12.97). The linear assumption PSout = Ga PSin and equation (12.101) yield the following: F=
PSin /PNin PNa =1+ PSout /PNout kT0 BG a
(12.102)
The dB representation of the noise factor F is called the noise figure NF (unfortunately, this looks like the product N · F, but it isn’t). The output noise power exiting two cascaded amplifiers deserves a closer look. The noise power PNa1 internally added by stage 1 is amplified through stage 2 while the noise power PNa2 added by the last stage is directly present in the output signal. Consequently, the noise power PNout2 present at the multistage output can be calculated from the input noise power PNin , the available gains Ga1 , Ga2 and noise powers PNa1 , PNa2 of amplifier stages 1 and 2, respectively. PNout2 = PNin1 G a1 G a2 + PNa1 G a2 + PNa2
(12.103)
The noise factor definition (12.102) can be applied to multiple stage systems. The overall system noise factor Fsys can be derived from formulas (12.102) and (12.103) leading to the Friis [23] equation: Fsys = F1 +
F2 − 1 G a1
(12.104)
where F1 , F2 are the individual noise factor and Ga1 is the gain of the first stage. The second stage contribution ( F2 − 1)/Ga1 can be reduced if the first stage exhibits a high gain Ga1 . That is one reason why low-noise amplifiers should be put close to the signal source (antenna) and why they are chosen to have a relatively high gain of 25 dB to 50 dB.
12.7.2
Noise figure measurement To perform direct noise measurement, the output noise power of the DUT is measured using an input termination at room temperature (approximately 290 ◦ K). If the gain Ga and noise equivalent bandwidth B of the amplifier under test are known, the noise factor can be determined using formulas (12.101) and (12.102). This method is limited
638
Amplifier measurements
Table 12.9 Typical noise power and noise temperature values PN related to B = 1 Hz ≈ 1.06 × 10−21 W
≈ 4.08 × 10−21 W
≈ 5.15 × 10−21 W
typ.138 × 10−21 W
N related to B = 1 Hz Noise temperature T Remark
≈ −174 dBm ≈ +296 K Resistor at room temperature (23 ◦ C)
≈ −173 dBm ≈ +373 K Resistor in boiling water (100 ◦ C)
typ. − 159 dBm typ. + 10,000 K Biased solid state noise source
≈ −180 dBm ≈ 77 K Resistor in liquid nitrogen (−196 ◦ C)
Noise meter
Through
ENR
Y
F2 Noise source
T h , Tc
DUT F1
Nh , Nc
Figure 12.49 Measurement setup for Y-factor method.
to devices with a very high noise figure of >20 dB because only these devices exhibit an output noise power that can be detected with a reasonable measurement uncertainty. The Y-factor method relies on an input termination that can be operated in two states: “cold state” offering noise temperature Tc and “hot state” offering noise temperature Th . Originally, a resistor cooled in liquid nitrogen or warmed in boiling water was used as input termination. The excess noise ratio (ENR) describes the change in noise temperature between hot and cold state relative to the standard noise temperature T0 = 290 ◦ K. ENR =
Th − Tc T0
(12.105)
According to Table 12.9, ENR ≈ 1 is calculated when using liquid nitrogen and boiling water. The need to perform automatic measurements and the fact that measurement accuracy can be improved by higher ENR values led to the use of solid state noise sources. Without bias, they exhibit noise generated at room temperature Tc ≈ T0 . Common noise sources use external 28 V for the “hot state” in which they generate a noise equivalent to Th = 4T0 , . . . , 1000T0 depending on the type of source. Commercially available models can be divided into three groups: low ENR (5 dB to 7 dB) for measuring low-noise figures ( F1 > F2 /G a1
(12.108)
The noise figure of a spectrum analyzer used as a noise meter can be improved with a low-noise preamplifier. Assuming the example values of Table 12.10, the noise factor of the spectrum analyzer is improved from 1000 to 2.41. Noise measurements are based on very low RF levels, and the best possible shielding is an important requirement. If the noise source uses a standard laboratory power supply, then a low-pass filter in front of its bias connector is important. Some spectrum or network analyzers may come with an integrated AGC. To keep the gain control from altering the noise figure F1 of the instrument, this automatic feature should be switched to manual operation. Unlike spectrum analyzers, most network analyzers have a double side-band architecture, whereby the received noise is actually measured at two frequency bands and internally correlated in the analyzer, which may lead to considerable deviations. Noise is random in nature, which makes noise reading unstable. Averaging the rms values of several measurements instead of using a very small bandwidth can help to overcome this. A reduced bandwidth may help to improve the noise figure of the analyzer but may require a higher number of averages to yield a stable readout. The measurement bandwidth should be selected to be smaller than the DUT’s bandwidth because otherwise the calibration measurement (through-connection) would differ in bandwidth as compared to the DUT measurement. The ENR values of a noise source vary over frequency. They have to be provided with the source. Typical uncertainties for these values are in the range of 0.15 dB. But the characterization of the ENR values is done at temperature T0 , where the application exhibits a room temperature different from T0 . More important is the fact
640
Amplifier measurements
that characterization relies on a noise meter with 50 input impedance while typical DUTs exhibit different input impedances. This mismatch error is the most important contribution to measurement uncertainty. A similar problem is the remaining impedance difference between hot and cold state which is significant for high ENR sources because they are not equipped with an internal attenuator. The Y factor method relies on relative level measurements. Therefore, the linearity of the noise meter is a very important prerequisite that can be violated using an improper preamplifier. The DUTs discussed here (PAs) are typically operated in the nonlinear region. This would lead to intermodulation between carrier signal and noise. Furthermore, it will violate the constant gain assumption that has been made on the right hand side of equation (12.102). This topic far exceeds the scope of this section; a recent discussion can be found in reference [24].
12.7.3
Noise parameters The simple noise figure is based on the assumption that the noise PNa internally added by the amplifier under test is constant. But practical measurements show that this is affected by the source impedance. The actual noise figure performance of the device in its operating environment will be determined by the match of adjacent system components. The noise factor F of an amplifier depends on the complex source reflection coefficient s as stated by the following equation s − opt 2 4Rn F = Fmin + Z 0 1 + opt 2 1 − |s |2
(12.109)
where Fmin is the minimum noise factor, opt is the optimum complex reflection coefficient, Rn is the noise resistance and s is the complex source reflection coefficient. The quantities Fmin , opt , and Rn are referred to as the noise parameters. With given noise parameters and a fixed expected noise factor F, formula (12.109) leads to a circle in the s Smith chart similar to those presented in Figure 12.19 (Section 12.4). But the minimum noise figure does not necessarily occur at either the system impedance Z0 or at the conjugate match impedance that maximizes gain Ga . To determine the three noise parameters and since opt is complex, a total number of at least four scalar noise figure measurements involving four different source impedances is necessary. The impedance transformation of the noise source can be performed using a microwave tuner. Alternatively, [25] suggests using a 10 dB coupler and three selectable impedance standards to achieve different source reflection coefficients. A calibration measurement must be carried out to determine the noise parameters of the measurement equipment so that they can be separated from the measurement based on formula (12.104). The cold-source method found in reference [26] is a direct noise measurement method that uses the noise source most of the time in its “cold state.” The “hot state” is used only when a scaling factor is required for the procedure.
12.8 Conclusions
641
Through Noise meter Noise source
Th , Tc
DUT
Figure 12.50 Noise parameter measurement setup.
12.8
Conclusions The functional principle of the transistors used to build solid state power amplifiers is based on semiconductor physics. What happens inside the transistor is primarily described by electrical fields and charge flows. Taking the integral over these parameters leads to voltage and current as the first choice description. On the other hand, neither current nor its phase shift can be accurately measured in the microwave range whereas wave quantities are directly accessible by means of vector network analyzers. S-parameters and wave quantities provide an easy understanding of power flows between source, active component and load. Due to the high frequencies measurements must be done in the frequency-domain and in a narrow-band manner to meet the dynamic requirements. It can not be overlooked that S-parameters have not been intended to model nonlinear effects. A mathematical embedding using S-parameters is not generally valid within the context of power amplifiers. Furthermore, observed S-parameters will depend on the applied power levels and modulation patterns. But a valid S-parameter description can be measured for a specific set of operating parameters. Consequently, traditional network analyzers can be supplemented by the following components: r a load- and source-pull system to provide the embedding physically to the DUT (e.g., to determine the optimum L and G from several S-parameter measurements); r a power sensor as a traveling standard for power calibration (e.g., to determine the 1 dB compression point from an s21 power sweep); r a modulated or pulsed signal source to mimic the application-specific driving signal (e.g., to observe pulsed S-parameters or to carry out hot S-parameter measurements); r a monitored DC supply to observe DC current and voltage (e.g., to calculate the PAE). Besides S-parameters, other frequency domain parameters like harmonic distortion and intermodulation distortion can be measured. These parameters rely on the multifrequency response that is generated by the nonlinearities from a single or two-tone stimulus. If performed by a large-signal network analyzer these multifrequency responses can be combined to form a time-domain result. It is than possible to plot voltage and current versus time which are the most meaningful parameters to observe the functionality of a power amplifier (class A, class AB, class B identification, conduction angle, and dynamic load line). Finally, applications come with their own specific quality criteria like adjacent channel power ratio, noise-power ratio, error vector magnitude, bit error ratio and symbol error
642
Amplifier measurements
ratio. These are defined on particular measurement setups using a specified modulation pattern and channel coding. This chapter has provided an overview of not only what is meant by these various measurement parameters but, more importantly, how they are actually measured in practice, what equipment setup is needed to perform the measurement, and what errors exist in the measurement process and how these can be minimized.
References 1. T. Reichel, “Voltage and Power Measurements”, Rohde & Schwarz GmbH & Co. KG, Munich, Germany, Sept. 1999 [Online]. Available at: www.rohde-schwarz.com. 2. W. Buschbeck, “Hochfrequenz-Wattmeter und Fehlanpassungsmesser mit direkter Anzeige [translation: RF power meter and mismatch tester with direct indication],” Hochfrequenz und Elektroakustik vol. 61, no. 4, p. 93, 1943. 3. K. Hupfer, “Anordnung zum Messen der vor- und r¨ucklaufenden Welle auf einer Hochfrequenzleitung [translation: Configuration for measurement of incident and reflected wave of a transmission line],” patent DE 42 39 740 C1, grant of patent 23. June 1994. 4. M. Hiebel, “Fundamentals of Vector Network Analysis,” Rohde & Schwarz GmbH & Co. KG, Munich, Germany, 4th Edn., 2008, sample chapter at: www.books.rohde-schwarz.com. 5. Anonymous, “IEEE standard for precision coaxial connectors (DC to 110 GHz),” The Institute of Electrical and Electronics Engineers Inc. IEEE-Standards Board, IEEE Std 287TM-2007, Sept. 2007. 6. G. A. Kouzaev, M. J. Deen, N. K. Nikolova, H. Ali and A. H. Rahal, “Cavity models of planar components grounded by via-holes and their experimental verification,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 3, pp. 1033–1042,. March 2006. 7. V. Sokol and K. Hoffmann, “Improvement of microstrip open-end calibration,” Radioelektronika 2003 – Conference Proceedings Brno: VUT v Brne, FEI, Ustav radioelektroniky, 2003, pp. 245–248. 8. N. Benahmed and N. Benmostefa, “Design directional couplers for high-power applications,” Microw. & RF, pp. 90–98, Oct. 2006. 9. Anonymous, “ISO/IEC Guide 98-3:2008 Uncertainty of measurement – Part 3: Guide to the Expression of Uncertainty in Measurement” (GUM, 1995), International Organization for Standardization, Geneva, Switzerland, first edition 2008, reissue with minor corrections of the 1995 version of Guide to the Expression of Uncertainty in Measurement (GUM), International Organization for Standardization, Geneva, Switzerland 10. O. Ostwald “T-check accuracy test for vector network analyzers utilizing a Tee-junction,” Application Note 1EZ43, Rohde & Schwarz GmbH & Co. KG, Munich, Germany, version 0E, June 1998 [Online]. Available at: www.rohde-schwarz.com. 11. J. M. Rollet “Stability and power gain invariants of linear two-ports,” IRE Trans. Circuit Theory, vol. CT-9, no. 3, pp. 29–32. Mar. 1962. 12. M. L. Edwards and J. H. Sinsky “A new criterion for linear 2-port stability using a single geometrically derived parameter,” IEEE Trans. Microw. Theory Tech., vol. 40, no. 12, pp. 2303–2311, Dec. 1992. 13. D. E Bockelman and W. R Eisenstadt, “Combined differential and common-mode scattering parameters: theory and simulation,” IEEE Trans. Microw. Theory Tech., vol. 43, no. 7, pp. 1530–1539, July 1995.
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14. J. Frei, X.-D. Cai, and S. Muller, “Multiport S-parameter and T-parameter conversion with symmetry extension,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 11, pp. 2493–2504, Nov. 2008. 15. S. Winder, “Single tone intermodulation testing,” RF Des., pp. 34–44, Dec. 1993. 16. D. Agahi, W. Domino, and N Vakilian: “Two-tone versus single-tone measurements of secondorder nonlinearity,” Microw. J., pp. 82–94, Mar. 2002. 17. M. Van den Bossche, “Workshop: ZVxPlus application – PA design,” NMDG nv, Cesar van Kerckhovenstraat 110 – Bldg 5, B-2880 Bornem, Belgium [Online]. Available at: www.nmdg. be/ZVxPlus.html 18. T. Gasseling, D. Barataud, S. Mons, J.-M. Nebus, J. P. Villotte, J. J. Obregon, and R. Quere, “Hot small-signal S-parameter measurements of power transistors operating under large-signal conditions in a load-pull environment for the study of nonlinear parametric interactions,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 3, pp. 805–812, Mar. 2004. 19. J. Martens and P. Kapetanic, “Probe-tone S-parameter measurements,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 9, pp. 2076–2082 Sept. 2002. 20. B. Kaehs, “The crest factor in DVB-T (OFDM) transmitter systems and its influence on the dimensioning of power components,” Application Note 7TS02, Rohde & Schwarz GmbH & Co. KG, Munich, Germany, Jan. 2007, version 2E [Online]. Available at: www.rohde-schwarz. com. 21. J. Wolf, “Measurement of adjacent channel power on wideband CDMA signals,” Application Note 1EF40, Rohde & Schwarz GmbH & Co. KG, Munich, Germany, Mar. 1998, version 0E [Online]. Available at: www.rohde-schwarz.com. 22. R. Minihold: “Testing S-paramters on pulsed radar power amplifier modules,” Application Note 1MA126, Rohde & Schwarz GmbH & Co. KG, Munich, Germany, Feb. 2009, version 0E [Online]. Available at: www.rohde-schwarz.com. 23. H. T. Friis, “Noise figures of radio receivers,” Proc IRE, vol. 32, no. 7, pp. 419–422, July. 1944. 24. L. Escotte, E. Gonneau, C. Chamborn, and J. Graffeuil, “Noise behavior of microwave amplifiers operating under nonlinear conditions,” IEEE Trans. Microw.Theory Tech., vol. 53, no. 12, pp. 3704–3711, Dec. 2005. 25. L. F. Tiemeijer, R. J. Havens, Randy de Kort, and A. J. Scholten, “Improved Y-factor methode for wide-band on-wafer noise-paramater measurements,” IEEE Trans. Microw. Theory and Tech., vol. 53, no. 9, pp. 2917–2925, Sept. 2005. 26. A. C. Davidson, B. W. Leake, and E. Strid, “Accuracy improvements in microwave noise parameter measurements,” IEEE Trans. Microw. Theory Tech., vol. 37, no. 12, pp. 1973– 1978, Dec. 1989.
About the authors
Mustafa Akkul Mustafa Akkul achieved BSc, MSc. and Ph.D. degrees in Electrical and Electronics Engineering from Middle East Technical University, Ankara-Turkey in 1989, 1991, and 1999, respectively. Currently employed as the manager of Microwave Products Division, Aselsan A.S.-Turkey. Major interest areas are MIC/MMIC power amplifiers for radar and EW applications, Tx /Rx modules for phased array systems, transceiver and multifunction module designs for military applications.
Inder J. Bahl Inder J. Bahl received his Ph.D. degree in Electrical Engineering from the Indian Institute of Technology, Kanpur, India in 1975. He joined the ITT Gallium Arsenide Technology Center in 1981 and has been working on microwave and millimeter wave GaAs ICs since then. At Cobham (formerly ITT GTC/Tyco Electronics), in his present capacity as a Distinguished Fellow of Technology, his interests include device modeling, highefficiency high-power amplifiers (HPAs), broadband HPAs, high-power limiter/LNAs, compact and low-loss multibit phase shifters, 3D MMICs, and development of MMIC products for commercial and military applications. Dr. Bahl is the author/coauthor of over 155 research papers. He authored/coauthored 14 books and holds 16 patents. He is an IEEE Fellow and a member of the Electromagnetic Academy. He is the Editor of the International Journal of RF and Microwave Computeraided Engineering.
¨ Wolfgang Bosch In March 2010 Professor Dr. Wolfgang B¨osch joined the Graz University of Technology in Austria to establish a new Institute for Microwave and Photonic Engineering. Previously he has been the CTO of the Advanced Digital Institute in the UK, a not-forprofit organization to promote research activities in the Yorkshire/Humberside Region. He has also been the Director of Business and Technology Integration of RFMD UK. For more than nine years he has been with Filtronic plc as Chief Technology Officer
About the authors
645
of Filtronic Integrated Products and Director of the Global Technology Group. Prior to joining Filtronic, he held positions in the European Space Agency (ESA) working on amplifier linearization techniques for space applications, MPR-Teltech in Canada working on MMIC technology projects and in 1991 he had joined the Corporate R&D group of M/A-COM in Boston where he worked on advanced topologies for high-efficiency power amplifiers. From 1996 to 1999 he was with DaimlerChrysler Aerospace in Germany, working on T/R Modules for airborne radar. Wolfgang received his engineering degrees at the Technical University of Vienna and Graz/Austria. He finalized his MBA with distinction at Bradford University School of Management in 2004. For several years he was on the Supervisory Board of the EMRS Defence Technology Centre in the UK, he is a Senior Member of the IEEE, a Fellow of the IET and a panel member of the EPSRC. He has published more than 40 papers and holds four patents. He was a Non-Executive Director of Diamond Microwave Devices (DMD) and is currently a Non-Executive Director of the Advanced Digital Institute (ADI) and VIPER Company.
Wayne Burger Wayne Burger received a Ph.D. in Electrical Engineering from the Massachusetts Institute of Technology in 1987, with his thesis work focusing on the deposition and characterization of low temperature silicon epitaxial films. After working on front-end process integration for BiCMOS SRAMs at National Semiconductor for two years, he joined Motorola’s Semiconductor Product Sector (which later became Freescale Semiconductor) in 1990. Early projects at Motorola include 0.60 μm CMOS, 0.35 μm BiCMOS, and SiGe bipolar development. He has been manager of the RF-LDMOS Device Development team at Freescale Semiconductor since 1994. During this time, RF-LDMOS has evolved into the dominant RF power transistor technology for the cellular infrastructure market, and is now expanding into adjacent RF power markets. Wayne has authored, coauthored, or presented at numerous conferences, workshops, and technical journals on the topic of RF-LDMOS device technology and applications. He is a Distinguished Member of the Technical Staff at Freescale and a member of the IEEE.
Steve C. Cripps Dr Steve C. Cripps obtained his Ph.D. from Cambridge University, England. He worked for Plessey Research (now GECMM) on GaAsFET hybrid circuit development. Later he joined Watkins-Johnson’s solid state division, Palo Alto, CA, and has held Engineering and Management positions at WJ, Loral, and Celeritek. During this period, he designed the industry’s first 2–8 Ghz and 6–18 Ghz 1 W solid state amplifiers, and in 1983 published a technique for microwave power amplifier design, which has become widely adopted in the industry. In 1990 he became an independent consultant and was active in a variety of commercial RF product developments, including the design of several cellular telephone power
646
About the authors
amplifier MMIC products. In 1996 he returned to England, where his consulting activities continue to be focused in the RF power amplifier area. In 2006, Dr. Cripps published a second edition of his best-selling book, RF Power Amplifier Design for Wireless Communications (Artech House). He is currently vicechair of the High Power Amplifier subcommittee of the Technical Co-ordination and Technical Program Committees of the IEEE Microwave Theory and Techniques Society, and writes the regular “Microwave Bytes” column in the IEEE Microwave Magazine. He is the recipient of the 2008 IEEE Microwave Applications Award. Dr. Cripps is a professorial research fellow at Cardiff University, UK. He is a Fellow of the IEEE.
Rob Davis Rob Davis is a senior manager at RF Micro-Devices in County Durham, UK. His primary technical interests lie in the areas of III–V semiconductor device engineering and the development of compact models for circuit design. He received B.Sc. and Ph.D. degrees in Physics from the University of Lancaster in 1983 and 1987, respectively. He began his career at the Royal Signals and Radar Establishment at Malvern in 1986 where he was engaged in device research gaining experience in a variety of compound semiconductor FET and bipolar devices. In 2000 he joined Filtronic Compound Semiconductors Ltd., now RFMD (UK) Ltd. Here his work has included the development of GaAs pHEMT MMIC processes and he currently leads the device and test engineering functions.
Christopher P. Dragon Christopher P. Dragon received a bachelor’s degree in Electrical Engineering from Louisiana State University and went on to receive a Masters of Engineering in Microelectronic Engineering from Rochester Institute of Technology. In 1991, he began his career in an RF development division of Motorola’s Semiconductor Products Sector in Phoenix, Arizona. It was at this time that the first RF-LDMOS transistor was developed and launched into production. Chris has remained working on the development of RF-LDMOS devices for cellular basestation applications throughout his career up to the present where the work continues at Freescale Semiconductor in Tempe, Arizona. He has been involved with and overseen the development of eight generations of RF-LDMOS devices. Chris is a Senior Member of the Technical Staff at Freescale Semiconductor and a member of the IEEE.
Dominic FitzPatrick Dominic FitzPatrick has been involved with the design of solid state microwave amplifiers for over 25 years. He graduated from the Portsmouth Polytechnic, England, in 1984
About the authors
647
joining Pascall Electronics and in 1988 returned to Portsmouth to undertake a Masters in Solid State Microwave Physics. After working for a small consultancy, he joined Wessex Electronics, eventually becoming Technical Director. In 1999, he joined Milmega to head up the engineering department, and early in 2004, he was part of the successful management buy-out team. Leaving at the end of 2006 Dominic returned to academia to pursue a Ph.D. in Novel Wideband Amplifier Design Techniques at Cardiff University.
Michael G. Hiebel Michael G. Hiebel was born in Munich (Muenchen) Germany in 1970. He received the diploma degree in Electrical Engineering from the Munich University of Technology. Since 2003 he is a member of the Institute of Electrical and Electronics Engineers IEEE and senior member since 2011. Mr. Hiebel is a member of the VDE (German Electrical Engineering Association), as well. He has been employed by Rohde & Schwarz GmbH & Co. KG in Munich since 1999 and is currently a senior development engineer, focusing on vector network analyzers. His main interests are vector network analyzer calibration techniques, nonlinear device measurement (mixers, power amplifiers, and oscillators) and millimeter wave network analysis. Since 2006 he is involved as a teacher in the company’s professional training program. He contributes to a periodic course on RF engineering at the Carl-Cranz-Gesellschaft in Wessling (Southern Germany). He has written a number of articles, scientific contributions, white papers, and application notes. He is author of the book Fundamentals of Vector Network Analysis (c.420 pages), which is published by Rohde & Schwarz in English, German, Chinese, and Russian.
Stephen Maas Stephen Maas received BSEE and MSEE degrees in Electrical Engineering from the University of Pennsylvania in 1971 and 1972, respectively, and a Ph.D. in Electrical Engineering from UCLA in 1984. He joined the National Radio Astronomy Observatory in 1974, where he designed the low-noise receivers for the Very Large Array radio telescope. Subsequently, at Hughes Aircraft Co. and TRW, he developed low-noise microwave and millimeter-wave systems and components, primarily FET amplifiers and diode and FET mixers, for space communication. He has also been employed as a Research Scientist at The Aerospace Corp., where he worked on the optimization of nonlinear microwave circuits and the development of circuit-design software based on harmonic-balance, Volterra-series, and time-domain methods. Dr. Maas joined the UCLA Electrical Engineering Faculty in 1990, left it in 1992. He is currently Chief Scientist of AWR Corp. and also consults independently. Dr. Maas is the author of Microwave Mixers (Artech House, 1986 and 1992), Nonlinear Microwave Circuits (Artech House, 1988 and 2003), The RF and Microwave Circuit Design Cookbook (Artech House, 1998), and Noise in Linear and Nonlinear Circuits (Artech House, 2005). From 1990 until 1992 he was the editor of the IEEE Transactions
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About the authors
on Microwave Theory and Techniques, and from 1990–3 was an Adcom member and Publications Chairman of the IEEE MTT Society. He received the IEEE MTT Society’s Microwave Prize in 1989 for his work on distortion in diode mixers and its Application Award in 2002 for the invention of the FET resistive mixer. He is a Fellow of the IEEE.
Mali Mahalingam Mali Mahalingam received the Ph.D. degree in Physics from Carnegie-Mellon University. Currently, he is manager of Packaging Operations, Radio Frequency Division, Freescale Semiconductor Inc. focusing on high-power RFPAs for wireless markets. He has 31 years of experience in packaging, assembly, and manufacturing technologies in the semiconductor industry of which the initial 25 years were with Motorola Inc. Mali has made numerous contributions to both technology development and their successful implementation in products. His technical accomplishments are spread to thermal, mechanical, materials, electrical, simulation/validation and computer-aided design disciplines. He has earned world-class recognition for his pioneering work in thermal technology applied to micro-electronics. He has published 70 + technical papers and has three issued patents. Mali has taught professional courses on packaging and thermal technology at universities and electronic manufacturing plants. He has mentored graduate level research at universities. He is an IEEE Fellow.
Daniel P. Myer Daniel P. Myer is President and Founder of Communication Power Corporation (CPC, www.cpcamps.com). He received his B.S. in Electrical Engineering from Polytechnic University in Brooklyn, New York, and an A.A.S. from S.U.N.Y. Farmingdale, New York. Mr. Myer is the author of over 15 technical papers, coauthored several books (Classic Works in RF Engineering, Artech House 2006, coeditor/author, Encyclopedia of Magnetic Resonance, John Wiley, coauthor) and has been issued two US patents. In 1990 and 1992, he introduced a new topological network synthesis procedure for equal delay transmission line transformers along with the fundamental realization criteria. Prior to founding CPC, Mr. Myer was an RF design engineer at M/A-COM Microwave Power Devices (MPD) and Comtech/PST where he codesigned high-power solid-state RF amplifiers for high-profile military programs such as Rivet Rider (Commando Solo), employed in the USAF’s Airborne EC-130E based, psychological warfare programs. In addition, Mr. Myer codeveloped RF amplifiers for use in marine search radar, missile command/destruct, L-band airborne radar tracking, submarine position emergency radio beacon and multicarrier feed-forward networks for cellular phone/wireless base-stations.
Bill Roesch Bill Roesch has a bachelor of science degree in Electrical and Computer Engineering from Oregon State University. He started his engineering career at Tektronix;
About the authors
649
scrutinizing purchased component reliability for five years. In 1985, Bill joined TriQuint Semiconductor to explore aging, stressing, analyzing, and improving GaAs devices. Bill is a 25-year contributing member of JEDEC and he is also a member of the IEEE. Bill has numerous publications, tutorials, and conference presentations on Compound Semiconductor reliability and he has received nine different best paper awards. For his innovative reliability techniques and device physics insight, Bill was recently inducted into the Oregon State University Academy of Distinguished Engineers. For twelve years, Roesch guided the quality and reliability engineering group at the Hillsboro, Oregon, factory. In 2007, he moved from management back onto the technical ladder and in 2009, Bill was designated a TriQuint Senior Fellow in Reliability.
Robert J. Trew Robert J. Trew is the Alton and Mildred Lancaster Distinguished Professor of Electrical and Computer Engineering at North Carolina State University, Raleigh. He received his Ph.D. degree from the University of Michigan in 1975. He has served as the ECE Department Head at North Carolina State University, Virginia Tech, and Case Western Reserve University. Dr. Trew is currently serving as the Director of the Electrical, Communications, and Cyber-Systems Division in the Engineering Directorate of the US National Science Foundation. From 1997 to 2001 he was Director of Research for the US Department of Defense, with management oversight responsibility for the $1.3 billion yearly basic research programs of DOD. Dr. Trew served as Vice-Chair of the US Government interagency committee that planned the US National Nanotechnology Initiative (NNI). Dr. Trew is a Life Fellow of the IEEE, and was the 2004 President of the IEEE Microwave Theory and Techniques Society. He is currently the editor-in-chief of the IEEE Proceedings and previously served as editor-in-chief of the IEEE Transactions on Microwave Theory and Techniques and was founding coeditor-in-chief of the IEEE Microwave Magazine. Dr. Trew was twice been named an MTT Society Microwave Distinguished Lecturer. Awards received by Dr. Trew include the 2001 IEEE-USA Harry Diamond Memorial Award, an IEEE Third Millennium Medal Award, the 1998 IEEE MTT Society Distinguished Educator Award, the 1991 Alcoa Foundation Distinguished Engineering Research Award, and a 1992 NCSU Distinguished Scholarly Achievement Award. He received an Engineering Alumni Society Merit Award in Electrical Engineering from the University of Michigan in 2003. He has published over 170 articles, 21 book chapters, and has given over 390 conference/workshop presentations. Dr. Trew has 10 patents.
John Walker John Walker received his BSc, MSc, and Ph.D. degrees from the University of Leeds in 1971, 1972, and 1976, respectively. In 1974 he joined GEC Hirst Research Centre where he worked on the design of microwave transistor amplifiers before becoming Group Leader of IMPATT diodes and oscillators and, finally, Chief Engineer of the
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About the authors
Compound Semiconductor laboratory. In 1984 he joined Thorn-EMI Electronics as Microwave Hybrids Manager. In 1995 he moved to Semelab as RF Division Manager where he was responsible for all commercial and technical aspects of the company’s RF power transistor products. In 2011, he became European Sales Manager for Integra Technologies, Inc. He is the editor and coauthor of the books High-Power GaAs FET Amplifiers and Classic Works in RF Engineering, both published by Artech House. John is a Fellow of the IEE and a Senior Member of IEEE.
Index
Abaqus FEA, 432 acceleration factors, 446, 458–473, 504 current, 462–465 current density, 464 determination, 460–461 in gallium arsenide processes, 500 highly accelerated stress test, 492 humidity, 488–492 see also electric field acceleration factor; RF bias acceleration; thermal acceleration; voltage acceleration acceptance test procedures (ATPs), 282 ACLR see adjacent channel leakage power ratio (ACLR) ACPR see adjacent channel power ratio (ACPR) activation energy, 461–462 active harmonic load-pull, 620, 621 active load-pull schematics, 563–564 active systems, 619–620 adapters de-embedding, 593 inserted after calibration, 589–591 removal techniques, 592 adhesives, electrically conductive, 285 adjacent channel leakage power ratio (ACLR), 110–111 limits, 522 specifications, 517 adjacent channel power ratio (ACPR), 625–629 code division multiple access, 629 concept of, 625 determination, 626 measurements, 626 spectrum analyzers, 627, 628 test results, 629 adjacent channel powers integrated, 626–627 weighted, 626–627 admittance (Y) parameters, 189 applications, 206 in database models, 212 AGC (automatic gain control), 570 air flow fields, mobile phones, 414–415
ALC (automatic level control), 576 ALC (automatic level controlled) loops, 283 AlGaAs see aluminium gallium arsenide (AlGaAs) AlGaN/GaN HFETs see aluminium gallium nitride/gallium nitride heterostructure field effect transistors (AlGaN/GaN HFETs) Allegro Package Designer, 432 AlN (aluminium nitride), applications, 316–318 Alodine, 294 aluminium advantages, 452 applications housings, 294, 311 metallization, 451–452 electromigration, 30–31 surface treatment, 294 thermal conductivity, 311 aluminium alloy 4047, applications, housings, 294 aluminium alloy 6061, applications, housings, 294 aluminium gallium arsenide (AlGaAs) bandgap, 43 crystal structure, 43–44 properties, 43 aluminium gallium nitride/gallium nitride heterostructure field effect transistor amplifiers, 123–125 current waveforms, 139–142 drain current, 138 efficiency, 138 gain, 138 operation, 136–137 performance, 123–125 RF, 123, 124, 137–139 RF drain current, 140, 142–143 RF drain voltage, 139–142 RF gate current, 139, 143 RF gate voltage, 139–142 RF power input, 138, 139 output, 123–124, 138 source resistance, 142, 143 nonlinear, 143 voltage waveforms, 139–142
652
Index
aluminium gallium nitride/gallium nitride heterostructure field effect transistors (AlGaN/GaN HFETs) advantages, 119–120, 123 applications, 105–106, 110–111 microwave power amplifiers, 105 power amplifiers, 111 avalanche ionization, 145 background, 108–111 channel current, 146, 148 current conduction degradation, 145–146 current–voltage relationships DC, 137 gate and drain, 150–151 development, 110–111 drain current, 150–151 electric field magnitudes, 144–145 electron tunneling, 144–145 fabrication, 108–110, 119–120 future trends, 152–153 gate current, 148, 150–151 gate edge, electric fields at, 149 gate electron leakage paths, 145 gate leakage, 146 current paths, 149 gate tunnel leakage model, 147–148, 150 gate-to-source capacitance, 135 materials, parameters, 114 performance, 108–110, 124–125 polarization effects, 110 power output, changes, 472 resistances drain, 135–136 source, 135–136 resistivity, 132 RF power, output, 124, 146 saturation fields, 114 space-charge effects, 133 structure, 119 sudden reliability problem, 146–147 surface trap-to-trap hopping conduction, 149, 150 virtual gate effect, 145 aluminium nitride (AlN), applications, 316–318 AM/AM measurements, 632 AM/PM measurements, 632 amplifiers bias screening, 505 booster, 597–598 burn-in, 505 Class H, 161 classification classes A to S, 159–186 development, 159 and efficiency, 160 historical background, 159
inverted modes, 179–180 issues, 184–186 multimodes, 184–186 current waveforms, 185 defect-related problems, 447 distributed, 340–341 gain definitions, 599–602 humidity acceleration factors, 488–492 measurements, 570–642 reliability issues, 447 switch modes, 159 voltage waveforms, 185 wear-out, 447 see also aluminium gallium nitride/gallium nitride heterostructure field effect transistor amplifiers; Class A amplifiers; Class AB amplifiers; Class B amplifiers; Class C amplifiers; Class E amplifiers; Class F amplifiers; Class G amplifiers; Class J amplifiers; Class S amplifiers; Doherty amplifiers; hybrid amplifiers; power amplifiers (PAs); push-pull amplifiers; 4H-silicon carbide metal semiconductor field effect transistor amplifiers; transistor amplifiers amplitude–phase conversion, nonlinear, 512 Angelov–Chalmers model, 86 ANSYS, 432 ANSYS FLUENT, 432 ANSYS Icepak, 432 antenna towers, 416–417 apertures and group delay, 603–604 stepwidth, 603–604 Arrhenius equation, 460–461 ATPs (acceptance test procedures), 282 attenuators diode sensors, 571 high-power, 577 in high-power RF measurements, 576–579 disadvantages, 578 and power sensors, 576–577 scattering parameters, 596 self-heating, 578 step, 587–588 AutoCAD, 432 automatic differentiation, applications, 222 automatic gain control (AGC), 570 automatic level control (ALC), 576 automatic level controlled (ALC) loops, 283 autotransformers, 553 avalanche breakdown, 25 concept of, 23 use of term, 18 average efficiency, 278
Index
Class A amplifiers, 164 definition, 510 determination, 510–511 average power, 624 average pulse method, 633–634 back substitution, 191 backgating, 454 balanced mode configuration, vs. Doherty configuration, 529 balanced one-port devices, 610 balanced power amplifiers, 340–341, 544–550 configurations, 544–545 as power combiners, 546–547 balanced two-port devices, 610 balanced–balanced transformers, 556–557 ballast resistors, 216 baluns, 552 active, 610–611 configurations, 556 Guanella, 554 passive, 610–611 structure, 558 two-hole cores, 553–554 bamboo regime, use of term, 31–32 bandpass filters, 586, 604 barretters, 571 base stations see radio base stations (RBSs) bathtub curves, 412, 455–456, 457 regions, 412–413, 456–457 Beatty standard, 598–599 BeO (beryllium oxide), applications, 316–318 BER (bit error rate), 635–636 beryllium oxide (BeO), applications, 316–318 bias decoupling, 349–352 bias networks, 350 configurations, 345–347 constant impedance, 351 FETs, 249–250 GaAs FETs, 250 GaN FETs, 250 in microwave hybrid power amplifiers, 345–353 requirements, 345 transistors, 345, 346 bias screening, amplifiers, 505 biasing narrow band designs, 349 sequences, 347 vs. RF performance, 348–349 bipolar junction transistors (BJTs), 249 applications, RF power amplifiers, 161–162, 282 cross-sections, 433 disadvantages, 246–247, 255 materials, 106 stable thermal operating points, 216, 217
653
see also heterojunction bipolar transistors (HBTs); 4H-silicon carbide bipolar junction transistors (4H-SiC BJTs) bit error rate (BER), 635–636 BITE (built in test), applications, 353 BJTs see bipolar junction transistors (BJTs) black-box models, 89 Black’s equation, 30–31, 33, 463 generalization, 463–464 parameters, 32 bolometers, principles, 571 bond wires DC fusing current, 220 impedance determination, 220 as inductors, 219–220 models, 399 in power amplifier models, 219–221 booster amplifiers, 597–598 bootstrap configuration, 555–556 box truncations, 224 branchline couplers, 328–331, 349 impedance transforming, 549 branchline quadrature hybrids, 547–549 characteristic impedance, 547–548 frequency response, 548 output impedances, 548–549 performance, 548 breakdown curves, on-state vs. off-state, 24 breakdown voltage–frequency relationships, 45–46, 47 breakdown voltages, 57–58 capacitors, 469, 470 definition, 57 RF power transistors, 246, 248 silicon nitride films, 466 see also drain-to-source breakdown voltage (BVds ); gate-to-drain breakdown voltage (BVgd ); gate-to-source breakdown voltage (BVgs ) breakdown walkout, use of term, 59 breathing, and moisture ingress, 296 built in test (BITE), applications, 353 burn-in, 457–458, 504–505 amplifiers, 505 use of term, 504–505 BVds see drain-to-source breakdown voltage (BVds ) BVgd see gate-to-drain breakdown voltage (BVgd ) BVgs see gate-to-source breakdown voltage (BVgs ) CAD see computer-aided design (CAD) Cadence, 432 calibration adapters inserted after, 589–591 with different connector types, 589–593 high-power setups, 596–598
654
Index
CAD (cont.) with PCBs, test fixtures and wafer probes, 593–596 standards, 590 techniques, properties, 592 through–open–match, 598–599 see also unknown–open–short–match (UOSM) calibration capacitors applications, 318–320 breakdown voltages, 469, 470 chip, 265–267 closed-form models, 209–210 defects, 483 as distributed components, 324 equivalent circuits, 209 high-Q, 353–355 ideal, 320 interdigital, 367, 368–369 lifetimes, predictions, 471 losses, 219 lumped, 367 microstrip, 368–369 in microwave hybrid power amplifiers, 318–321 in MMICs, classification, 368–369 modeling, 315 plate orientation effects, 318–320 quality factor, 320 ramp to failure data, 467 scattering parameters, 206–207 voltage acceleration, 487–488 see also metal–insulator–metal (MIM) capacitors; multilayer capacitors (MLCs); silicon nitride capacitors; single-layer capacitors (SLCs) capillary action, and moisture ingress, 296 cascaded tuner method, 620 castings, housings, 303 CCDF (complementary cumulative distribution function), 624, 625 CDMA see code division multiple access (CDMA) CDPD (cellular digital packet data), 513 Cds see drain-to-source capacitance (Cds ) cell interconnections, modeling, in large devices, 213–214 cell phones see mobile phones cellular digital packet data (CDPD), 513 cellular telephony see mobile telephony ceramic packages air-cavity surface-mount, 392–393, 394 applications, in MMIC PAs, 391, 392, 393 assembly, 398 flow, 400 configuration, 393 cost factors, 393 design, 391–393 issues, 391
development, 390–391 low-cost, 394 manufacture, 393–394 flow processes, 396 materials, 391 properties, 391 multi-lead, 392–393 properties, 392 substrates, 392–393 types of, 390–391 ceramics, applications, packaging, 82, 390–394 CFD see computational fluid dynamics (CFD) CFs see crest factors (CFs) Cgd see gate-to-drain feedback capacitance (Cgd ) Cgs see gate-to-source capacitance (Cgs ) channel power measurement, 627 see also adjacent channel powers chemical mechanical polishing (CMP), 453 chromate conversion, 294 circuit analysis applications, 205 methods, 188–205 integration, 205 software and electromagnetic analysis software, 229 power amplifiers, 188 see also harmonic-balance analysis; linear analysis; nodal analysis; time-domain analysis circuit components, losses, in power amplifier models, 219 circuit metallizations losses calculations, 219 factors affecting, 218–219 in power amplifier models, 217–219 multilayer, 218 circuit simulation accuracy, and passive circuit structures, 205–213 see also nonlinear circuit simulation circulators functional diagrams, 323 in microwave hybrid power amplifiers, 322–323 Class A amplifiers, 162–164 advantages, 164 applications, 161 characteristics, 160 and Class AB amplifiers compared, 164–165 current–voltage relationships, 162 efficiency, 163–164 average, 164, 511 maximum, 510 under power back-off conditions, 164, 180 output power, 163–164
Index
waveforms, 163 zero-knee assumption, 163–164 Class AB amplifiers, 164–171 applications, 161 and Class A amplifiers compared, 164–165 design, 171 issues, 165–166 early studies, 160 efficiency, under power back-off conditions, 169 linearity, 170 issues, 169–170 operation, 170–171 output capacitance, 171 output voltage, 165, 166, 618 supply voltages, 524–525 topology, 170 waveforms, 165 Class B amplifiers, 161, 164–171 efficiency, 166–168, 186, 510, 561 under power back-off conditions, 168–169 inverted mode, 179 operation, 166–168 schematics, 559 waveforms, 167, 562 voltage, 173 zero-bias condition, 168 Class C amplifiers, 160, 171–173 applications, 173 disadvantages, 172–173 efficiency, 160 input voltages, excess, 172 operation, 171 RF power reduction, 171–172 waveforms, 172 Class D amplifiers audio, 161 use of term, 183 Class E amplifiers, 181–183 circuits, 181–182 current waveforms, 181–182 efficiency, 183 operation, 181 research, 183 waveforms, 182 Class F amplifiers, 161, 173–176, 186 design, 176 inverted, 179–180 clipped variations, 181 waveforms, 179, 180 knee region, 175 operation, 173 output capacitance, 175–176 research, 173 topology, 176 voltage waveforms, 173–174 zero-grazing, 174–175
655
waveforms, 175 Class G amplifiers, 161 use of term, 180 Class H amplifiers, 161 Class J amplifiers, 176–179 advantages, 178–179 circuits, 178–179 operation, 176–177 topology, 178 waveforms, 178 voltage, 177–178 Class S amplifiers, 161, 183–184 concept of, 183 configuration bogus, 184 viable, 184 design issues, 183–184 operation, 183 clipping, 514 closed-form models, 208–210 applications, 209 capacitors, 209–210 characteristics, 208–209 planar spiral inductors, 209 strip transmission lines, 210 CMP (chemical mechanical polishing), 453 CMRR (common-mode rejection ratio), 611 CNC machines (computer numerically controlled) machines, applications, housing construction, 303 coaxial connections, 311–312, 554–555 interfacing issues, 595–596 overview, 589 power handling calculations, 312 printed circuit boards, 312, 313 properties, 593 transition parameters, 314 types of, 591, 593 code division multiple access (CDMA), 110–111, 331 adjacent channel power ratio, 629 power output control, 511–512 see also Wideband Code Division Multiple Access (W-CDMA) coefficient of thermal expansion (CTE), joining materials of different, 425–426 cold-source method, 640 cold-wall, use of term, 311 COM (component object model), 229 comb spectra, 634 combining advantages, 344 applications, 344 in Doherty amplifiers, 344 in microwave hybrid power amplifiers, 344 parallel, 334
656
Index
commercial markets, RF power amplifiers, 236 common-mode rejection ratio (CMRR), 611 common-mode signals, 608–610 compensation techniques, 574 complementary cumulative distribution function (CCDF), 624, 625 component object model (COM), 229 components active, 315 integrated, in microwave hybrid power amplifiers, 322 lumped, equivalent circuits, 324, 325 in microwave hybrid power amplifiers, 315–332 passive, 315 distributed, 323–331 lumped, 315–323 reliability, and temperature, 305 see also capacitors; diodes; distributed components; inductors; resistors; transistors; vacuum tubes compression points, 615, 616 computational fluid dynamics (CFD), 431 applications, 431 computer numerically controlled (CNC) machines, applications, housing construction, 303 computer-aided design (CAD) MMIC PAs, 370 power amplifiers, 188–230 tools, 370 condensation, equipment vulnerability to, 294–295 condition numbers, 227 conduction steady-state, 420 and thermal performance, RFPAs, 420–421 three-dimensional, 420–421 see also reduced conduction angle conductors in printed circuit boards, 289 substrate attachment, 289 see also interconnects; vias conformal coatings, 296 conservation of energy equation, 431 conservation of mass equation, 431 conservation of momentum equation, 431 constellation diagrams, 630–631, 632 construction, 631 contact printing, in GaAs FET fabrication, 76 contact thermal resistance concept of, 438–439 factors affecting, 439 pictorial description, 438 reduction strategies, 439 continuation methods in nonlinear circuit simulation, 223 use of term, 223 continuity equations, 128–129
convection heat sinks, 421 and thermal performance, RFPAs, 421–422 convective heat transfer coefficients, 421–422 coplanar waveguide (CPW) applications, 292 in MMICs, 362–363, 365–367 attenuation coefficient, 366 characteristic impedance, 365, 366 dielectric constant, 366 disadvantages, 292 discontinuities, 366–367 modes, 365–366 parameters, 365 copper applications, conductors, 289 electrodeposition, 289 electromigration, 30–31 interdiffusion, 452 metallization, 453 pattern definition, 453 rolled, 289 thermal conductivity, 311 copper bumps, thermal excursions, 478–482 correction factors, 626–627 corrosion, and metallization, 452 cosimulation, 229 COSMOS, 432 coupled-coil transformers, 553–554 equivalent circuits, 553–554 impedances, 553 performance, limitations, 553–554 winding topologies, 553 couplers characteristics, 330 discrete quadrature hybrid, 328, 329 as distributed components, 326–331 in microwave hybrid power amplifiers, 353 rat-race, 559, 560 Wireline, 328, 329 see also branchline couplers; Lange couplers; power combining; quadrature couplers CPW see coplanar waveguide (CPW) crest factors (CFs), 512–514, 624 definition, 513 determination, 624 periodic signals, 624 CTE (coefficient of thermal expansion), joining materials of different, 425–426 current definition, 113–114 see also snapback current current acceleration, 462–465 current density acceleration factors, 464 exponent determination, 465
Index
current density equations, 128–129, 131, 132–133 current distribution, and metal losses, 218 current sense, 348 current transport, DMOSFETs, 10–11 D1020UK (MOSFET) datasheet, 257 drain current vs. temperature, 257, 258–259 gate voltage vs. temperature, 257–258 input/output impedance, 259, 260 thermal tracking circuit, 258 data rates, and efficiency, 520–522 database models, 212 datasheets D1020UK, 257 interpretation issues, 331 RF power transistors, 244–246 DC–DC converters, 348 DCS1800 system, 513 DDE (dynamic data exchange), 229 de-embedding, adapters, 593 DECT (Digital Enhanced Cordless Telecommunications), 513 defect amplification, 482–488 defect-related problems, amplifiers, 447 defects capacitors, 483 liftoff, 483 predicted, 495 types of, 483 vs. wear-out, 475–492 see also failures depletion region, 17–18 GaAs FETs, 61 silicon LDMOSFETs, 5 design balanced, MHPAs, 334 ceramic packages, 391–393 issues, 391 GaAs FETs, 63–74 gallium nitride wide bandgap transistors, 118–125 heat sinking, 308–309 HFETs, 64–65 hypothetical RFPA subsystem modules, 252 MESFETs, 64–65 MHPAs, 333 MMIC PAs, 370–372, 525–526 pHEMTs, 64–65 plastic packages, 395 power amplifiers holistic, 526, 528 overview, 523–526
657
parameter trade-offs, 509–514, 525, 567–568 processes, 525 power FET cells, 67–69 for reliability, 495–500 RF power transistors, 1 RFPAs, 242 silicon carbide wide bandgap transistors, 118–125 silicon LDMOSFETs, 27–39 silicon VDMOSFETs, 27–39 see also computer-aided design (CAD); thermal design design flow barriers to, 229 in nonlinear circuit simulations, 228–230 design for manufacturability (DFM) studies, 282 designers, and failure mechanisms, 447 device junction temperature, 428–429 device pitch, issues, 28–29 devices under test (DUTs) heat radiation, 429–430 power input, 622 power output, issues, 596 radiant energy, 430–431 temperature control, 21 two-port, 581 wave propagation, 580 dew point, 294–295 DF (dissipation factor), 318–320 DFM (design for manufacturability) studies, 282 die attach eutectic, 397 materials, 397, 426–427 methods, 396–397 in MMIC PA package assembly, 396–397 solders, 426–427 thermal resistance, 436–437 uniform, 401 see also flip-chip die attach; gold–silicon die attach; lead–tin–silver die attach die bonding, 493–494 die thickness, and thermal resistance, 436 dielectric constants, and temperature, 287 dielectric layers, in GaAs FET fabrication, 79–80 dielectrics degradation mechanisms, 453–454 failure mechanisms, 453–454 gate, 453–454 properties, 320 dies, in silicon LDMOSFET construction, 2–5 differential equations, in time-domain analysis, 202
658
Index
differential-mode signals, 608–610 diffusion assessment, 455 measurement, 295 and moisture ingress, 295 see also interdiffusion digital baseband pre-distortion (DPD), 514–517, 524, 567–568 block diagrams, 515, 516, 517 disadvantages, 516 feedback loops, 515, 516–517 performance plots, 517, 518 and power amplifier design, 524 power dissipation, 517–518 principles, 515–516 requirements, 516 Digital Enhanced Cordless Telecommunications (DECT), 513 digital-signal processors (DSPs) applications, 515 power consumption, 517–518 diode sensors, 570–571 attenuators, 571 circuit diagrams, 571 fast, 571 input power ranges, 572–573 optimization, 571 diodes DC voltages, 194–195 reliability guidelines, 499 Schottky, 345–347 sinusoidal voltages, 196–198 Zener, 347 directional elements, 582 directivity, 585 frequency range, 585 functions, 582 implementations, 585 test port match, 585 directional power measurements, 576–579 directional power meters, applications, 579 directional power sensors applications, 579 development, 578 directivity, 584, 596–597 determination, 583–584 directional elements, 585 raw, 597 discontinuities coplanar waveguide, 366–367 microstrip, 205, 206–208, 209, 365 simulations, 212 and RF connections, 314 waveguides, 211–212
dispersion-free networks, phase delay, 605 dissipation factor (DF), 318–320 distortion nonlinear, 512–513, 611 see also harmonic distortion (HMD); intermodulation distortion (IMD); linear distortion; pre-distortion distributed amplifiers, 340–341 distributed components, 323–331 capacitors as, 324 couplers as, 326–331 definition, 323–324 equivalent circuits, 324, 325 resistors as, 323–324 transmission lines as, 324 DMOSFETs see double diffused metal–oxide–silicon field effect transistors (DMOSFETs) Doherty amplifiers, 1, 514, 524–525 combining in, 344 development, 563 efficiency, 564–566, 567 for efficient radio base stations, 527–530 future trends, 440–441 main and auxiliary voltages and currents, 566 peaking stage, 173 power output, 566, 567 principles, 561–563 single-stage, 528, 529 Doherty combining, 523, 527, 559–567 efficiency improvement, 529 representations, 563–564, 565 Doherty configuration, vs. balanced mode configuration, 529 double diffused metal–oxide–silicon field effect transistors (DMOSFETs) advantages, 1–2 breakdown voltage, 17–22 current transport, 10–11 current–voltage responses, 10 development, 1–2 device physics, 10–27 heat generation, 33–34 historical background, 1–2 hot carrier injection, 17–22 linear regime on-resistance, 17–22 operating voltage, issues, 26–27 operation, 10 linear region, 19 saturation region, 19 parasitic elements, behavior, 12–17 ruggedness, 22–26 snapback, 22–26 terminals, 10–11 types of, 2
Index
see also lateral double diffused metal–oxide–silicon field effect transistors (LDMOSFETs); vertical double diffused metal–oxide–silicon field effect transistors (VDMOSFETs) DPD see digital baseband pre-distortion (DPD) drain efficiency, 33, 110–111, 559–560 broadband, 279 definition, 36–37, 509–510, 602 drain engineering and ruggedness, 24 use of term, 17 drain switching, high-power amplifiers, 532–533 drain voltage control, 348 drain-to-source breakdown voltage (BVds ), 2–5, 57–58 DMOSFETs, 17–22 high, designing for, 18 increase, 56 LDMOSFETs, 5 mechanisms, 17–18 optimization, 65–66 and ruggedness, 23 use of term, 17 drain-to-source capacitance (Cds ), silicon LDMOSFETs, 5, 15–16 DSPs see digital-signal processors (DSPs) DUTs see devices under test (DUTs) dynamic data exchange (DDE), 229 dynamic load lines, 618 dynamic range, 628–629 power sensors, 574 RF power amplifiers, 237–238 vector network analyzers, 616 ED see electrodeposition (ED) edge coupling, 290–291 EDGE (Enhanced Data Rates for Global Evolution), 508–509 EEFET3 model, 86 EEHEMT model, 86 EER (envelope elimination and restoration) schemes, 514 efficiency and amplifier classification, 160 Class A amplifiers, 511 collector, 509–510 and data rates, 520–522 Doherty amplifiers, 564–566, 567 enhancement, 514 and gain, 36–37 instantaneous, 510 measurement, 602–603 peak, 511 power amplifiers, 508, 524–525, 567–568 factors affecting, 602–603
659
improvements, 620 power conversion, 509–510 radar, 508 RF power transistors, 244 RFPAs, 238, 282, 416, 440 see also average efficiency; drain efficiency; maximum efficiency; power efficiency; power-added efficiency (PAE) efficiency factor, 602–603 EIA (Electronic Industries Association) (US), 321 EL2 (electron level 2), definition, 44 electric field acceleration factor, 470 determination, 469 electric field spreading, 58–59 electrical ratings, 496–497 electrodeposition (ED) advantages, 289 applications, in printed circuit board manufacture, 289 electromagnetic analysis software, and circuit analysis software, 229 electromagnetic compatibility (EMC), 268–269 RF power amplifiers, 235, 241 electromagnetic simulation applications, 210 models from, 210–212 electromagnetic simulators, 210–212 in MMIC PA design, 372, 373 three-dimensional, 211–212 three-dimensional predominantly planar, 211 two-dimensional, 210–211 see also plant simulators electromigration definition, 462–463 design issues, 30–32 HBTs, 464–465 integrated circuits, 463 interconnects, 463–464 and lifetimes, 464 mechanisms, 463 and metallization, 452 metals, response differences, 30–31 performance enhancement, 31–32 prevention, 463 requirements, in MMICs, 369–370 resistors, 463–464 vs. temperature, 33 electron gas two-dimensional electron mobility, 114 sheet charge density, 114 electron level 2 (EL2), definition, 44 Electronic Industries Association (EIA) (US), 321
660
Index
electronic warfare (EW) communications jamming, hypothetical RFPA subsystem, 252–282 power amplifiers in, 534–537 RF power amplifiers in, 252 see also jammers electrostatic discharge (ESD) guidelines, 499 input protection circuits, 499 electrothermal equivalent circuits, 214–215 element testing, 448–449 EMC see electromagnetic compatibility (EMC) emissivity, 422, 430–431 definition, 422 encapsulation, MMIC PAs, 400 Enhanced Data Rates for Global Evolution (EDGE), 508–509 ENR see excess noise ratio (ENR) envelope analysis, 201–202 computational costs, 202 envelope elimination and restoration (EER) schemes, 514 envelope tracking, 161 concept of, 524–525 environmental testing, plastic packages, 491–492 epitaxial layers, growth, 111 epoxies, and screw locking, 304 equalizers, 325–326 behavior, 326 lossy stub, 327 equivalent circuits capacitors, 209 coupled-coil transformers, 553–554 distributed components, 324, 325 electrothermal, 214–215 GaAs FETs, 60–61, 85 GaN wide bandgap transistors, 125–127 gate finger, 68 gate manifold, 68 large-signal models, 85–86 limitations, 127 lumped components, 324, 325 reduced, 127 resistors, 318 small-signal models, 84–85 two-port networks, 125–126 transistors, 125–127 see also tee-equivalent circuits equivalent generators, and power sensors, 574–576 error models 3-term, 589 7-term, 588, 589, 592 error vector magnitude (EVM), 522, 525, 630–631 definition, 630 measurement, 630–631
ESD see electrostatic discharge (ESD) etch-stops, 77–78 etching dry, 78 issues, 290–291 mesa, 76–77 wet, 78 see also gate etching eutectic systems, for die attach, 426–427 EVM (error vector magnitude), 522, 525 EW see electronic warfare (EW) excess noise ratio (ENR), 638–640 determination, 638 F see noise factor (F) failure criteria, 449–450, 480 measurement selection, 450 specification thresholds, 449–450 failure distributions, 446, 455–458 HBTs, 465 separation, 455 thermal excursions, 477 failure mechanism analysis (FMA), 478–479 failure mechanisms, 446, 451–455 bulk substrate materials, 454 definition, 451 designers and, 447 dielectric, 453–454 in gallium arsenide processes, 500 metallization, 451–453 Schottky gate FETs, 454–455 semiconductors, humidity, 490 failure mode and effects analysis (FMEA), 282, 478–479 failure modes, 450–451 definition, 450–451 failure rates, 447 definition, 475 semiconductors, 455–456, 458 see also mean time between failure (MTBF); mean time to failure (MTTF) failures definition, 449 early, 504–505 evaluation procedures, 473–474 infant, 504–505 probabilities, 446 see also defects failures in time (FIT), 475 fans, reliability issues, 311 Faraday’s Law, 128–129 fast Fourier transforms (FFTs), 204 FDD (frequency-division duplexing), 519–520 FDMA (frequency division multiple access), 511–512
Index
feedback in microwave hybrid power amplifiers, 335, 336 issues, 335–336 resistive-inductive-capacitive networks, 251, 274, 315 in RF power amplifiers, 251, 267–268 see also gate-to-drain feedback capacitance (Cgd ) FEM see finite element method (FEM) FETs see field effect transistors (FETs) FFTs (fast Fourier transforms), 204 FIB (focused ion beam), applications, 459 fiberglass, applications, substrates, 285–286 field effect transistors (FETs) applications, RF power amplifiers, 161–162 bias networks, 249–250 characteristics, idealized, 162 current–voltage relationships, 162 degradation, 455 failure mechanisms, 454 gate-to-source capacitance, 134–135 life testing, 460, 461 lifetimes, temperature effects, 498 metal–insulator–semiconductor, 110 nonlinear source resistance, equivalent circuits, 134–135 power device models, 213 reliability guidelines, 497–498 RF power output, 124 sinking gates, 458 source resistance, 133–134 tee-equivalent circuits large-signal, 128 small-signal, 126 transconductance, 134–135 see also gallium arsenide field effect transistors (GaAs FETs); heterostructure field effect transistors (HFETs); metal semiconductor field effect transistors (MESFETs); metal–oxide–silicon field effect transistors (MOSFETs) field plates concept of, 18–19 effects, 8 in GaAs FETs, 66–67 in 4H-SiC MESFETs, 108 in silicon LDMOSFETs, 7–8, 18–19 finite element method (FEM), 431 applications, 431–432 finite impulse response (FIR) models, 201 finite volume method (FVM), 431 FIR (finite impulse response) models, 201 FIT (failures in time), 475 flares, 29, 30 flashing, 289 flip-chip die attach failure cross-sections, 481–482
661
failure mechanisms, 478–479 technology, 479 test structure, 479 thermal excursion testing, 478 FloTHERM, 432 fluid flows, simulations, 431 FMA (failure mechanism analysis), 478–479 fmax see maximum oscillation frequency (fmax ) FMEA (failure mode and effects analysis), 282, 478–479 focal plane array (FPA) detectors, 429–430 focused ion beam (FIB), applications, 459 forced air, and heat sinking, 310–311 Fourier transforms, 196–198, 204, 227 fast, 204 FPA (focal plane array) detectors, 429–430 frequency and gain, 37 see also maximum oscillation frequency (fmax ); transition frequency (fT ) frequency division multiple access (FDMA), 511–512 frequency modulation schemes, analog, 508–509 frequency sets box truncations, 224 in nonlinear circuit simulation, 224–225 rectangular truncations, 224 triangular truncations, 224 use of term, 224 frequency-division duplexing (FDD), 519–520 frequency-domain models, 204 frequency-shift keying (FSK), efficiency, 512–513 FSK (frequency-shift keying), efficiency, 512–513 fT see transition frequency (fT ) fuses, 347 FVM (finite volume method), 431 2.5G (mobile phone standard), 508–509 3G (mobile phone standard), 508–509, 519–520 power amplifiers, 509 4G (mobile phone standard), 508–509 power amplifiers, 509 GaAs see gallium arsenide (GaAs) GaAs FETs see gallium arsenide field effect transistors (GaAs FETs) GaAs HBTs (gallium arsenide heterojunction bipolar transistors), development, 42 GaAs MESFETs see gallium arsenide metal semiconductor field effect transistors (GaAs MESFETs) gain definitions, 599–602 and efficiency, 36–37 flatness, 237, 253 and frequency, 37 GaAs FETs, 61–63
662
Index
gain (cont.) hypothetical RFPA subsystem modules, 253 independent factors, 600–601 insertion, 601–602 linearity, 237, 253, 254 RF power amplifiers, 237 RF power transistors, 244 temperature stability, 237 transducer, 599–600 see also unilateralized gain (U) gain circles, constant, 601 gain compression, 622 gallium, interdiffusion, 454–455 gallium arsenide (GaAs) bandgap, 43 charge carrier mobility, 113–114 crystal structure, 43–44 disadvantages, 44–45 and hydrogen poisoning, 295 processes acceleration factors, 500 failure mechanisms, 500 properties, 43–45 resistivity, 44 thermal conductivity, 436 wafers, 357 see also aluminium gallium arsenide (AlGaAs); indium gallium arsenide (InGaAs) gallium arsenide field effect transistors (GaAs FETs), 42–91, 249 applications, 161–162 in RF power amplifiers, 282 band diagrams, 50 bias networks, 250 breakdown, 57–58, 66 mechanisms, 58–59 optimization, 58–59, 65–66 ratings, 59–60 RF vs. DC, 60 capacitances gate-to-drain, 60 gate-to-source, 60 parasitic, 60 channel temperature, 72–73 characteristics, 332 current–voltage characteristics, 51–52 detailed behavior, 51–52 dynamic, 53–54 idealized, 51, 52 practical, 53 pulsed, 53–54, 87 real devices, 52 depletion region, 61 design, 63–74 epi-layer, 64–65 FET channel and recess, 63–67
gate-recess, 65–66 power devices, 63 power FET cells, 67–69 thermal, 72–74 development, 42 doping profiles, 64 drain lag, 55 efficiency, 331 equivalent circuits, 60–61, 85 fabrication, 74–84 backside processing, 80 device isolation, 76–77 dielectric layers, 79–80 gate etching, 77–78 gate-shrink approaches, 81 interconnect metals, 80 liftoff, 76 lithography, 75–76, 81 low-cost, 81 ohmic contacts, 77 overview, 74–75 packaging, 81–84 process monitoring, 80 processes, 75–81 Schottky gate electrodes, 78–79 field plates, 66–67 figures of merit, 61–63 gain, 61–63 gate lag, 55 gate sinking, 72 historical background, 42 junction temperature, 72, 74 loadlines, 51–52 class A, 52 class B, 52 materials, properties, 43 models, 84–89 device, 84 gate-charge, 86–87 large-signal, 56, 85–89 load-pull, 89 small-signal, 84–85 packaging, 81–84 physics, 51–63 pulsed operation, 332 resistances, parasitic, 60 thermal resistance, 74 thermal simulation, 73–74 trapping effects, 53–54 consequences, 54–57 minimization, 54 types of, 46–51 gallium arsenide heterojunction bipolar transistors (GaAs HBTs), development, 42 gallium arsenide metal semiconductor field effect transistors (GaAs MESFETs) applications, 357–358
Index
dynamic characteristics, 115–117 failure mechanisms, 454 gallium arsenide technology, advantages, 42 gallium nitride (GaN) applications, 105–106, 161–162 charge carrier mobility, 113–114 hole mobilities, 115 gallium nitride field effect transistors (GaN FETs), 249 applications, in RF power amplifiers, 282 bias networks, 250 characteristics, 332 development, 42 efficiency, 331 gallium nitride RF power amplifiers (GaN RFPAs) applications, 441–442 die attach, 437 gallium nitride wide bandgap transistors, 103–153 breakdown, 112–113 development, 104–105 device design, 118–125 future trends, 152–153 large-signal effects, 130–152 gate leakage, 144–146 nonlinear source and drain resistances, 133–143 reliability and time-dependent performance degradation, 146–152 space-charge limited current transport, 130–133 material parameters, 111–115 models, 125–130 equivalent circuits, 125–127 physics-based large-signal, 128 properties, 112 RF performance, 118–125 thermal conductance, 112–113 GaN see gallium nitride (GaN) GaN FETs see gallium nitride field effect transistors (GaN FETs) GaN RFPAs see gallium nitride RF power amplifiers (GaN RFPAs) gasket sealing, 298, 299 approaches, 297 disadvantages, 297–298 gate capacitance, charge conservation, 86–87 gate dielectrics, degradation, 453–454 gate etching approaches, 78 in GaAs FET fabrication, 77–78 gate finger arrays, 27, 28 gate resistance, 347 gate taps, 28 concept of, 27–28 gate voltage control, 348 gate-to-drain breakdown voltage (BVgd )
663
definition, 57–58 optimization, 65–66 as two-terminal test, 57–58 gate-to-drain feedback capacitance (Cgd ) GaAs FETs, 60 silicon LDMOSFETs, 16 silicon VDMOSFETs, 16 gate-to-source breakdown voltage (BVgs ) definition, 57–58 as two-terminal test, 57–58 gate-to-source capacitance (Cgs ) AlGaN/GaN HFETs, 135 FETs, 134–135 GaAs FETs, 60 silicon LDMOSFETs, 16 gauge repeatability and reproducibility (GR&R), 282, 450 Gaussian minimum-shift keying (GMSK), applications, 513 gds (output conductance), dispersion, 55 generalized minimum residual (GMRES), 193, 199–200 Global System for Mobile Communications (GSM), 508–509, 513 standards, 519 gm see transconductance (gm ) Gmax curves, 62, 90–91 GMRES (generalized minimum residual), 193, 199–200 GMSK (Gaussian minimum-shift keying), applications, 513 gold applications, metallization, 452 electromigration, 30–31 interdiffusion, 452, 454–455 gold–silicon die attach applications, 437 thermal resistance, 436–437 goodness, measures, 447 3GPP see 3rd Generation Partnership Project (3GPP) GR&R (gauge repeatability and reproducibility) studies, 282, 450 grounding, printed circuit boards, issues, 285, 291 group delay and apertures, 603–604 calculation, 603–604 definition, 603 measurements, 603–605 GSM (Global System for Mobile Communications), 508–509, 513 Guanella baluns, 554 Gysel combiners, 533–534, 542–544 advantages, 542–544 frequency response, 544 layouts, 542–544 modes, 544 and Wilkinson power combiners compared, 545
664
Index
h parameters, 90 h21 , determination, 90 Hall mobility measurements, 114 HALTs (highly accelerated life tests), 270, 271 handset amplifiers, simulations, 219, 220 hard substrates, 285 dimensional issues, 289 mounting, 292 harmonic distortion (HMD), 239, 611–615 measurement, 641 harmonic load-pull active, 620, 621 cascaded tuner method, 620 triplexer method, 620 harmonic matching, 185–186 harmonic suppression, determination, 614–615 harmonic-balance analysis, 193–202 applications, 205 large circuits, 196–198 convergence failure, 195 convergence testing, 195–196 development, 193 improvements, 199–202 envelope analysis, 201–202 error equation weighting, 200 Krylov subspace methods, 199–200 multitone excitations, 200–201 norm reduction, 199 Semanskii iteration, 199 multidimensional problems, 196–198 performance, 195 procedures, 194–195 scattering parameter models in, 207–208 SPICE models in, 226 HASL (hot air solder leveling), 289 HASTs see highly accelerated stress tests (HASTs) HBTs see heterojunction bipolar transistors (HBTs) HCI see hot carrier injection (HCI) heat sinking design issues, 308–309 and forced air, 310–311 housings, 293, 305–311 heat sinks construction, 309–310 convection, 421 fin alignment, 310–311 RFPAs, 417 thermal resistance, 439–440 types of, 309 heat transfer efficiency, 421–422 mobile phones, 414–415 PCBs, 414–415 simulations, 431 and thermal performance, in RFPAs, 419–423
see also conduction; convection; phase change cooling; radiation heat transfer coefficient, 421–422 heatpipes, 311 HEMTs see high-electron mobility transistors (HEMTs) hermetic sealing, 295, 296–297 approaches, 297 MMIC PAs, 400 heterojunction bipolar transistors (HBTs) applications, 161–162 in MMICs, 361–362, 386 development, 358 electromigration, 464–465 failure distributions, 465 life testing, 464 thermal stability, 216 heterostructure field effect transistors (HFETs), 47 band diagrams, 50 gate bias effects, 51 current–voltage relationships, DC, 137 depletion mode, 135 design, epi-layer, 64–65 developments, 48 fabrication, 74–75 gate leakage, 144 materials, 104–105 models, large-signal, 147 resistances drain, 136 source, 136 structure, 46–48 see also aluminium gallium nitride/gallium nitride heterostructure field effect transistors (AlGaN/GaN HFETs); high-electron mobility transistors (HEMTs) HFETs see heterostructure field effect transistors (HFETs) high-electron mobility transistors (HEMTs), 47 applications, in MMICs, 361–362 band diagrams, 49–50 channel mobilities, 48–49 development, 161–162, 358 doping profiles, 64–65 fabrication, 74–75 failure mechanisms, 454 indium gallium arsenide-based, RF performance, 103–104 modulation doping, 48–49 structure, 48 voltage acceleration, 471–472 see also pseudomorphic high-electron mobility transistors (pHEMTs) high-frequency devices, 105–106 high-power amplifiers (HPAs), 374–375, 388 applications, 532
Index
drain switching, 532–533 multi-octave, 377–380 single-stage, 385–386 thermal management, 400–401 high-power attenuators, 577 high-power RF measurements, 576–579 high-temperature life testing, 475 high-voltage integrated circuits (HVICs), 37–39 development, 37 performance, 38–39 two-stage, 37–38 high-voltage p region (PHV) implants silicon LDMOSFETs, 6–7 silicon VDMOSFETs, 19 high-voltage zero-power moisture (HVZPM), 489 highly accelerated life tests (HALTs), 270, 271 highly accelerated stress tests (HASTs), 83–84, 489–490 acceleration factors, 492 applications, 488 HMD see harmonic distortion (HMD) hole current density, simulations, 25 hot air solder leveling (HASL), 289 hot carrier injection (HCI) characterization, 19 stress testing, 21 degradation mechanisms, 453–454 DMOSFETs, 17–22 LDMOSFETs, 2–5 levels, 7–8 mitigation, 21–22 occurrence, 19–21 and RF bias acceleration, 473 sensitivity, 21–22 housings connections, 293 construction, 299–305 construction methods, 303–304 castings, 303 machining, 303 piece parts, 304 cost reductions, 303–304 heat sinking, 293, 305–311 hermeticity, 294–299 interference issues, 293 internal corners, 303 materials, 294, 311 microwave hybrid power amplifiers, 293–315 mountings, 293 protection, 293, 294–295 factors affecting, 295 standards, 295 RF connections, 311–315 screw locking, 304 sealing, 294–299 thermal issues, 305–311
665
thermal performance, 306 water cooling, 311 see also packaging HPAs see high-power amplifiers (HPAs) humidity semiconductor failure mechanisms, 490 and temperature, 488–489 humidity acceleration factors, 488–492 humidity activation energy, 488–492 humidity testing bias, 488–489 HVICs see high-voltage integrated circuits (HVICs) HVZPM (high-voltage zero-power moisture), 489 hybrid, definition, 284 hybrid amplifiers markets, 284 substrates, parameters, 286 use of term, 284 see also microwave hybrid power amplifiers (MHPAs) hybrid parameters, h21 , 62, 63 hydrogen poisoning, 295 hypothetical RFPA subsystem modules, 252–282 altitude, 253, 254 antenna load, 253 bandwidth, 252, 253 breadboards, 271, 272 capacitors chip, 265–267 coupling, 265–267 feedback, 274 design preventative measures, 273 processes, 252 efficiency, 278, 279 feedback networks, 267–268 frequency response, 253 gain, 253 flatness, 253 linearity, 253, 254, 274–278 gaskets, 273 gate bias/temperature tracking/compensation networks, 257–259 hardware, design/realization, 254–255 input/output impedance matching networks, 259–267 input/output RF/DC coupling/decoupling networks, 259 components, 259 mean time to failure, 253, 254, 280, 281 overview, 252 phase linearity, 254, 274–278 physical construction, 271–273 power output, 252, 253, 255 radiated emissions, 253, 254 RF transistor selection, 255–257 schematics, 273–274
666
Index
hypothetical RFPA subsystem modules (cont.) shock/vibration, 253, 254 specifications qualitative delineation, 252–253 quantification, 253–254 stability, 253, 279 susceptibility, 253, 254 system block and wire diagrams, 254–255 temperature range, 253, 254 temperature stress tests, 279–280 test data, 281–282 test results, 273–280 test setup configuration/analysis, 268–270 block diagrams, 268–269, 270 transformation ratios, 260–261 transformers, output, 272 two-port small-signal responses, 274, 275 vibration tests, 279–280 voltage standing wave ratios, load, 253, 278–279 ICs see integrated circuits (ICs) IEDs see improvised explosive devices (IEDs) IIR (infinite impulse response) models, 201 IMD see intermodulation distortion (IMD) IMFETs see internally matched field effect transistors (IMFETs) impact ionization, 58–59 impedance matching hypothetical RFPA subsystem modules, 259–267 microwave hybrid power amplifiers, 337 power field effect transistor cells, 71 RF power transistors, 250–251, 259–267, 283 HF, 250 UHF, 250 VHF, 250 stubs, 338 transistor amplifiers, 117 impedance range, and substrate materials, 289 impedance standard substrates (ISSs), calibration standards, 595–596 improvement cycles, mobile phones, 502 improvised explosive devices (IEDs) countermeasures, power amplifiers in, 538 jammers, 538 see also radio-controlled improvised explosive devices (RCIEDs) incident power, 581 incident waves, 580 magnitude, 582 indefinite admittance matrices, 190 indium gallium arsenide (InGaAs) bandgap, 43 crystal structure, 43–44 in HEMTs, RF performance, 103–104 in pHEMTs, 48–49 properties, 43
inductance, general expression, coefficients, 368 inductors air-cored, advantages, 322 bond wires as, 219–220 configurations, 367 losses, 219 lumped, 367 in microwave hybrid power amplifiers, 321–322 modeling, 315 planar spiral, closed-form models, 209 industrial markets, RF power amplifiers, 235 inexact Newton methods, 199–200 infinite impulse response (IIR) models, 201 infrared (IR) microscopes, 429, 430 infrared (IR) reflow thermal profiles, 476 infrared (IR) thermometry, 428–429 InGaAs see indium gallium arsenide (InGaAs) insertion gain, 601–602 insertion loss minimization, 321 transmission line transformers, 264–265, 266 instability, power amplifiers, 605 integrated circuits (ICs) design, reliability issues, 496 electromigration, 463 fabrication, reliability issues, 496 materials, limitations, 446–447 microwave, 357–358 in microwave hybrid power amplifiers, 322 see also high-voltage integrated circuits (HVICs); monolithic microwave integrated circuits (MMICs); radio frequency integrated circuits (RFICs) intercept points, 611–613 interconnects electromigration, 463–464 metallization failures, 451, 484 metals, 80 reliability guidelines, 498–499 see also vias interdiffusion copper, 452 gallium, 454–455 gold, 452, 454–455 interferences common-mode, 608–610 transmission lines, 608–610 intermodulation distortion (IMD), 235, 611–615 measurement, 641 minimization, 236 RF power amplifiers, 239 intermodulation measurements, 614 intermodulation suppression, 611–613 internally matched field effect transistors (IMFETs) characteristics, 71 topology, 73
Index
ion implantation, in GaAs FET fabrication, 77 IR (infrared) microscopes, 429, 430 IR (infrared) reflow thermal profiles, 476 IR (infrared) thermometry, 428–429 Iridite, 294 isolators issues, 323 in microwave hybrid power amplifiers, 322–323 performance, 343 ISSs (impedance standard substrates), calibration standards, 595–596 Jacobian matrices, 197–198, 226 poor conditioning, 227–228 jammers in electronic warfare, hypothetical RFPA subsystem, 252–282 I/J band, 537, 538 power amplifiers, 534 broadband, 538 prototypes, 535, 536, 537 for radio-controlled improvised explosive devices, 538 RF power amplifiers, 234 junction temperature, reduction, 311 junction-to-case thermal resistance (Rjc ) definition, 427 determination, 427 K factors, 482–488 determination, 486 kink effect, 56–57 mechanisms, 56–57 Kirchhoff’s current law, 194–195, 196–198 knee regions, negligible impacts, 162 Kovar applications in ceramic packages, 391 housings, 294 hermetic sealing, 297 properties, 294 Krylov subspace methods, 193, 199–200 λ parameter, 131 Lambert W function, 132 land grid arrays (LGAs), 413–414 land mobiles applications, 34–35 markets, 34–35 Lange couplers, 287–288, 330, 547, 549–550 advantages, 328–331 applications, 549 characteristic impedance, 550 development, 549
667
frequency range, 550 frequency response, 549–550 limitations, 550 performance, 550, 551 Laplace transforms, 204 large devices, cell interconnections, modeling, 213–214 large-signal models attributes, 86 black-box, 89 compact, 87 comparisons, 86 development, 87, 129–130 direct large-signal measurements, 88–89 equivalent circuits, 85–86 limitations, 127 for GaAs FETs, 85–89 HFETs, 147 for large periphery devices, 88 nonlinear, 127 physics-based, 128 table-based, 88 and trapping effects, 87–88 large-signal network analysis, 616–618 calibration, 617–618 large-signal network analyzers (LSNAs), 616, 617 set up, 622 lateral double diffused metal–oxide–silicon field effect transistors (LDMOSFETs), 249 cross-sections, 434 see also silicon lateral double diffused metal–oxide–silicon field effect transistors (silicon LDMOSFETs) LDO (low drop out) voltage regulators, 348 lead frames (LFs) materials, 395 in plastic packages, 395, 402 types of, 395 lead–tin–silver die attach, 426–427 applications, 437 thermal resistance, 437 LFs see lead frames (LFs) LGAs (land grid arrays), 413–414 life testing FETs, 460, 461 HBTs, 464 high-temperature, 475 highly accelerated, 270, 271 MESFETs, 459 transistors, 459–462 lifetimes capacitors, predictions, 471 and electromigration, 464 FETs, temperature effects, 498 vs. temperature, 462
668
Index
liftoff, 453 defects, 483 in GaAs FET fabrication, 76 metallizations, 483 processes, 483 LINC systems see linear amplification using nonlinear components (LINC) systems linear amplification using nonlinear components (LINC) systems, 160, 514 applications, 161 linear analysis, 188–193 early, 188 nodal incidence matrices, 188 two-port, 125–126 see also nodal analysis linear distortion measurement, 603–605 two-port networks, 603 linear measurements, 599–611 linear stability issues, 605–608 linear regime on-resistance (RDSon ) DMOSFETs, 17–22 factors affecting, 19 minimization, 19 silicon LDMOSFETs, 5 linear two-port circuit analysis, 125–126 linearity Class AB amplifiers, 169–170 enhancement, 514 gain, 237, 253, 254 limits, 525 phase, 237, 254, 274–278 power amplifiers, 512–514 measurement, 512 linearization techniques overview, 514 power efficiency impacts, 517–519 system level, 514–519 see also digital baseband pre-distortion (DPD); memory effect compensation liquid crystals, operating temperature measurement, 428–429 lithography electron-beam, 76 in GaAs FET fabrication, 75–76 optical steppers, 76, 81 stepper-based, 79, 81 types of, 76 load lines, dynamic, 618 load-pull measurements, 619–622 active harmonic, 620, 621 set up, 621 see also harmonic load-pull local oscillators (LOs), 587 Long Term Evolution (LTE) bandwidths, 517
standards, 520 LOs (local oscillators), 587 low drop out (LDO) voltage regulators, 348 low temperature co-fired ceramics (LTCCs), 315 developments, 322 LSNAs (large-signal network analyzers), 616 LTCCs see low temperature co-fired ceramics (LTCCs) LTE see Long Term Evolution (LTE) LU decomposition, 191, 199 computational loading, 191 lumped elements advantages, 367–368 definition, 367 microstrip, 367 in MMICs, 367–369 lumped-element models development, 368 vs. scattering parameter models, 208 machining, housings, 303 MAG curves (maximum available gain) curves, 62 magnetic resonance imaging (MRI), RF power amplifiers, 235 magnetic resonance spectroscopy (MRS), RF power amplifiers, 235 Mason’s invariant gain see unilateralized gain (U) matching harmonic, 185–186 see also impedance matching; transformer matching materials AlGaN/GaN HFETs, 114 bipolar junction transistors, 106 ceramic packages, 391 properties, 391 die attach, 397, 426–427 GaAs FETs, 43 HFETs, 104–105 housings, 294, 311 lead frames, 395 limitations, 446–447 metallization, 451–452 microwave, 286 pHEMTs, 48–49 radio absorbent, 304–305 RFPAs, thermo-physical properties, 423–427 substrates, 289 soft, 285–286 thermal conductivity, 423–424 at room temperature, 425 behavior, 424–425 wide bandgap, 284 see also thermoset materials mating surface flatness, RFPAs, 439
Index
matrices indefinite admittance, 190 port, 191 processing, 192–193 sparse, 192–193 storage issues, 192–193 see also Jacobian matrices; LU decomposition; nodal matrices maximum available gain (MAG) curves, 62 maximum efficiency Class A amplifiers, 510 power amplifiers, 510 maximum norms, 227 maximum oscillation frequency (fmax ), 63 definition, 62–63 determination, 90 limitations, 63 maximum ratings, 497 maximum stable gain (MSG) curves, 62 MBE see molecular beam epitaxy (MBE) mean time between failure (MTBF) applications, 474–475 and bathtub curves, 412–413 temperature and, 412 mean time to failure (MTTF) and electromigration, 30–31 hypothetical RFPA subsystem modules, 253, 254, 280, 281 microwave hybrid power amplifiers, 305 RF power amplifiers, 241 measurements AM/AM, 632 AM/PM, 632 amplifiers, 570–642 directional power, 576–579 group delay, 603–605 Hall mobility, 114 high-power RF, 576–579 of interest, selection criteria, 449 intermodulation, 614 nonlinear, 611–623 pulsed, 633–635 requirements, 641 scalar reflection, 582 transmission, 586 uncertainties, 598–599 sources of, 574–576 see also linear measurements; load-pull measurements; modulated measurements; noise measurements; power measurements; scattering (S) parameter measurements; source-pull measurements median, and standard deviation compared, 468 median lives (MLs), 459–460 determination, 461, 463–464 transistors, 461
669
median time to failure see mean time to failure (MTTF) medical heating, RF power amplifiers, 235 medical markets, RF power amplifiers, 235 memory effect compensation, 517, 567–568 memory effects, 56, 259, 630 modulated measurements, 632–633 Mentor Graphics, 432 mesa etching, in GaAs FET fabrication, 76–77 MESFETs see metal semiconductor field effect transistors (MESFETs) metal alloys, development, 285 metal organic chemical vapor deposition (MOCVD), applications, 75 metal semiconductor field effect transistors (MESFETs), 45, 47 applications, in MMICs, 361–362 band diagrams, 49–50 gate bias effects, 51 channel mobilities, 48–49 degradation, 458–459 electrical characteristics, 458 design, epi-layer, 64–65 doping profiles, 64 fabrication, 74–75, 107–108, 360 ion implantation, 77 failure mechanisms, 454 lifetests, 459 structure, 46–48 see also gallium arsenide metal semiconductor field effect transistors (GaAs MESFETs); 4H-silicon carbide metal semiconductor field effect transistors (4H-SiC MESFETs) metal–insulator–metal (MIM) capacitors, 367, 368–369 dielectrics, 453 reliability guidelines, 499 structure, 369 time-dependent dielectric breakdown, 466–471 voltage acceleration, 465–466 voltage ramping, 466–471 see also silicon nitride capacitors metal–insulator–semiconductor field effect transistors (MISFETs), 110 metal–oxide–silicon field effect transistors (MOSFETs), 249 advantages, 246–247, 257 applications, RF power amplifiers, 282 availability, 282 see also double diffused metal–oxide–silicon field effect transistors (DMOSFETs) metallization, 451–453 and corrosion, 452 and electromigration, 452 interconnects, 484 liftoff, 483
670
Index
metallization (cont.) materials, 451–452 pattern definition, 453 and reliability, 494–495 semiconductors, 488 metals imperfections, 218 oxidation, 218 resistivity, 218–219 bulk, 289 surface roughness, 218 MGRS (migrated gold resistive shorts), 490 MHPAs see microwave hybrid power amplifiers (MHPAs) Microsoft Windows component object model, 229 dynamic data exchange, 229 microstrip, 80, 218 alternatives to, 292 attenuation constant, 364 in calibration, 593–594 characteristic impedance, 363, 364, 392–393 data, 363 design issues, 325 dielectric constant, 364 discontinuities, 205, 206–208, 209, 365 simulations, 212 loss models, 218 lumped elements, 367 in MMICs, 359, 362–365 operating frequency, 364–365 parameters, 363 rat-race couplers, 559 tee junctions, 229 transmission-line models, 229 wavelength, 363 microwave absorbers, 304–305 microwave devices, 105–106 microwave hybrid power amplifiers (MHPAs), 284–355 applications, 284 balanced design, 334 disadvantages, 334–335 biasing, and control, 345–353 broadband matching strategies, 340–341 cavities orthogonal, 300 resonant frequencies, 304–305 components, 315–332 configurations, 299–300 H-section, 300, 301 orthogonal cavities, 300, 301 planar, 301–303 side-by-side, 302 split section, 301 wrap around, 300, 301, 302
construction, 299–305 control and biasing, 345–353 and interfacing, 352–353 couplers, 353 design, 333 balanced, 334 combining, 344 internally matched device amplifiers, 343–344 issues, 284 matching, 336–343 module size, 344 number of stages, 333 risk reduction, 344 stability, 336–343 system integration, 344 topologies, 333–336 fault finding, 344 feedback, 335, 336 issues, 335–336 housings, 293–315 impedance matching, 337, 339–341 interfacing and control, 352–353 thermal resistance reduction, 307–308 mean time to failure, 305 modules, configurations, 299–300 operating temperatures, 299 reduction, 307 printed circuit boards, 285, 293 substrates, properties, 287 thermal resistance, 305 tuning techniques, 353–355 see also components; housings; printed circuit boards (PCBs) microwave integrated circuits (MICs), development, 357–358 microwave materials, properties, 286 microwave power amplifiers developments, 357 RF power performance, 105 see also monolithic microwave integrated circuit power amplifiers (MMIC PAs) microwave power field effect transistors power-frequency limit, 45–46 thermal resistance, 73–74 microwave systems solid-state transistors in, 103 vacuum tubes in, 103 MICs (microwave integrated circuits), development, 357–358 migrated gold resistive shorts (MGRS), 490 MIL-STDs (military standards) (US), 295 military markets power amplifiers, 530–538, 567–568 RF power amplifiers, 234–235
Index
military standards (MIL-STDs) (US), 295 MIM capacitors see metal–insulator–metal (MIM) capacitors MIMIC program (US), 42 MIMO (multiple-input–multiple-output), 520 MISFETs (metal–insulator–semiconductor field effect transistors), 110 mixer sets, 224 MLCs see multilayer capacitors (MLCs) MLs see median lives (MLs) MMIC PAs see monolithic microwave integrated circuit power amplifiers (MMIC PAs) mobile phones air flow fields, 414–415 block diagrams, 413–414 exploded views, 413–414 heat transfer, 414–415 improvement cycles, 502 sealing, 414 talk time, 508 temperature field patterns, 414–415, 416 thermal behavior, 414–415 thermal design, 413–415 mobile radio communications efficiency trends, 520–522 networks, operating costs, 523 power amplifiers, 519–522 design, 523–524 standards, 519 mobile telephony applications, 35 base stations, RF power amplifiers, 236 historical background, 508–509 power amplifiers, 509 MOCVD (metal organic chemical vapor deposition), applications, 75 modal decomposition, 608–610 MODFETs see high-electron mobility transistors (HEMTs) modulated measurements, 623–636 memory effects, 632–633 modulated signals, properties, 573 modulation doped field effect transistors (MODFETs) see high-electron mobility transistors (HEMTs) modulation envelope, use of term, 623 moisture ingress and breathing, 296 capillary action, 296 diffusion, 295 and sealing, 295–296 moisture sensitivity level (MSL), 491–492 moisture vapor transmission rate (MVTR), 295 molecular beam epitaxy (MBE) applications, 75 development, 161–162
monolithic microwave integrated circuit power amplifiers (MMIC PAs), 357–406 advantages, 358–359 broadband, 372–373, 376–377 2W C-band, 376, 377 10W X-band, 377, 378 performance, 373 characterization, 357, 401–406 power, 404–405 procedures, 401–403 test fixtures, 403–404, 405, 406 tests, 403–406 design, 370, 525–526 CAD tools, 370 electromagnetic simulators, 372, 373 flowcharts, 371 issues, 370 methodology, 370–372 procedures, 371–372 developments, 358 evaluation, 401 examples, 372–389 high-power, 372–373, 381–386 14W with 60% PAE, 384–386 15W C-band, 385–386 20W X-band, 383, 384 50W S-band, 383 design, 381–383 power output, 385–386 high-power-added efficiency, 372–373 high-voltage, 372–373, 374, 387–389 10W GaAs HV FET, 388, 389, 390 GaN HEMT-based, 388–389, 391 limitations, 387–388 operation, 388 historical background, 357–358 millimeter wave 2.4W, 386, 387 narrowband, 372–373, 374–375 7W Ku-band, 374–375 performance, 373 operating range, 358–359 overview, 357–359 packaging, 389–401 assembly, 396–401 ceramic, 390–394 plastic, 394–396 requirements, 389–390 selection criteria, 389 power dissipation, 401 RF parameters, 405–406 summary, 372–389 technology, 359–370 three-dimensional views, 359 ultra-broadband, 376–377 2–18 GHz distributed, 380, 382 8W 2–8 GHz, 379–380, 381
671
672
Index
monolithic microwave integrated (cont.) 15W L- to S-band, 378–379, 380 power output, 379 wireless 3W, 386, 387 design, 386 measured performance, 386, 388 performance specifications, 386 stages, 386 monolithic microwave integrated circuits (MMICs) active devices, 359, 361–362 conductors current-carrying capacity, 369–370 dimensions, 369 coplanar waveguides, 362–363, 365–367 electromigration requirements, 369–370 fabrication, 360–361 processes, 360 recessed-gate process, 360 frequency limits, 362 literature, 361 lumped elements, 367–369 matching elements, 362–370 microstrip, 359, 362–365 performance, 362 and radio frequency integrated circuits compared, 357 substrates, 359, 361 technology, 359–370 transmission lines for, 362 mortality rates, 456 MOSFETs see metal–oxide–silicon field effect transistors (MOSFETs) MPCPA (multiple pulses chirped pulse amplification), 624 MRI (magnetic resonance imaging), RF power amplifiers, 235 MRS (magnetic resonance spectroscopy), RF power amplifiers, 235 MSC Sinda, 432 MSG curves (maximum stable gain) curves, 62 MSL (moisture sensitivity level), 491–492 MTBF see mean time between failure (MTBF) MTTF see mean time to failure (MTTF) multilayer capacitors (MLCs) applications, 320–321 use of term, 318–320 multiple devices, advantages, 307 multiple pulses chirped pulse amplification (MPCPA), 624 multiple-input–multiple-output (MIMO), 520 multitone analysis, 204–205 multitone excitations, 200–201, 625 MVTR (moisture vapor transmission rate), 295
National Institute of Standards and Technology (NIST) (US), 268 NBTI (negative bias temperature instability), 453–454 negative bias temperature instability (NBTI), 453–454 network analyzers for S parameter measurements, 641 see also large-signal network analyzers (LSNAs); scalar network analyzers; vector network analyzers (VNAs) Newton’s method, 194–195 inexact, 199–200 issues, 221–222 modified, 197–198 rules, 221 NFs see noise figures (NFs) NIST (National Institute of Standards and Technology) (US), 268 NMR (nuclear magnetic resonance) spectroscopy, RF power amplifiers, 235 nodal analysis, 188 advantages, 188–189 disadvantages, 189 procedures, 189–191 nodal matrices, 190–191 factoring, 191 singular, 191 noise sources of, 636 thermal, 636 noise factor (F), 637 minimum, 640 noise figures (NFs), 637 assumptions, 640 measurement, 637–640 spectrum analyzers, 628 typical, 639 noise floor, 628 noise measurements, 636–640 direct, 637–638 noise parameters, 640 measurement, 641 noise power, 637 values, 638 noise reduction, 348 noise temperature input, 639 values, 638 noise–power ratio (NPR), 630 noninsertable devices, 589 nonlinear circuit simulation analysis characteristics, 223–226 continuation methods, 223 convergence improvement, 223 design flow, 228–230
Index
frequency sets, 224–225 model characteristics, 221–223 numerical issues, 227–228 practical issues, 221–230 problem size minimization, 226–227 solution optimization, 226–227 termination criteria, 225–226 nonlinear distortion, 512–513, 611 nonlinear measurements, 611–623 norm reduction, 199 NPR (noise–power ratio), 630 nuclear magnetic resonance (NMR) spectroscopy, RF power amplifiers, 235 numerical derivatives, applications, 222–223 O-rings, rubber, sealing performance, 296 OFDM (orthogonal frequency-division multiplexing), 508–509, 513–514, 520 ohmic contacts degradation, 454–455 in GaAs FETs, 77 on-wafer tests, 401–403, 404 open circuits, 490 operational analysis, reliability predictions, 474 orthogonal frequency-division multiplexing (OFDM), 508–509, 513–514, 520 oscillations, minimization, 352 output conductance (gds ), dispersion, 55 package assembly die attach, 396–397 in MMIC PAs, 396–401 thermal issues, 400–401 wire bonding, 396, 397–398 packaging ceramics, 82, 390–394 environmental protection, 83–84 GaAs FETs, 81–84 MMIC PAs, 389–401 hermetic sealing and encapsulation, 400 plastics, 82–83, 394–396 silicon VDMOSFETs, 9 thermal models, 400–401 types of, 81 see also ceramic packages; housings; plastic packages; surface mount leadless packages (SMLPs) PAE see power-added efficiency (PAE) pallet amplifiers, 343–344 PAPR see peak-to-average power ratio (PAPR) parameters hybrid, 62, 63 monitoring, 449 most rapidly degrading, 449–450 see also noise parameters; scattering (S) parameters
673
parasitic bipolar effect (PBE), 58–59 parasitic crosstalk, 596–597 parasitic elements, behavior, 12–17 parasitic extraction, 212–213 software, 212 Parker–Skellern model, 86 PAs see power amplifiers (PAs) passive circuits, structures, and simulation accuracy, 205–213 passive intermodulation (PIM), 613–614 passive tuners, 620 pattern definition, metallization, 453 PBE (parasitic bipolar effect), 58–59 PBO see power back-off (PBO) PCBs see printed circuit boards (PCBs) PCDE (peak code domain error), 522 PCMs (process control monitors), 80 PCS1900 system, 513 PDF (probability density function), 510–511, 512 peak code domain error (PCDE), 522 peak envelope power (PEP), importance of, 513 peak power, 627–628 peak-to-average power ratio (PAPR), 513–514, 624 definition, 513 reduction, 514 PECVD (plasma enhanced chemical vapor deposition), applications, 453 PEP (peak envelope power), importance of, 513 performance power amplifiers, 567–568 and reliability, 448 and semiconductor properties, 111 vs. temperature, 411–412 see also thermal performance periodic signals, crest factors, 624 Pf2 (power-frequency) limit, 45–46 phase, measurement, 603–605 phase change cooling, and thermal performance, RFPAs, 423 phase delay definition, 604 determination, 604–605 in dispersion-free networks, 605 phase-shift keying (PSK), 513–514 efficiency, 512–513 see also quadrature phase-shift keying (QPSK) phased array antennas, 533, 534 PHD (poly-harmonic distortion) models, 88–89 pHEMTs see pseudomorphic high-electron mobility transistors (pHEMTs) photoresists, 483, 493 PHV implants see high-voltage p region (PHV) implants physical amplification, 504 piece parts, in housing construction, 304 PIM (passive intermodulation), 613–614
674
Index
plant simulators, 211 advantages, 211 open vs. closed formulations, 211 plasma enhanced chemical vapor deposition (PECVD), applications, 453 plastic packages, 398 applications, MMIC PAs, 394 assembly, 398–400 flow, 402 design, 395 developments, 394 environmental testing, 491–492 lead frames, 395, 402 molding, 394–395 tests, 405 plastics, applications, packaging, 82–83, 394–396 plated-through holes (PTHs), 291 PMMA (polymethyl methacrylate), applications, resists, 78–79 point-in-pulse method, 633 trigger delays, 634 Poisson’s equation, 130–131 solutions, 129–130 poly-harmonic distortion (PHD) models, 88–89 polymethyl methacrylate (PMMA), applications, resists, 78–79 polytetrafluoroethylene (PTFE) applications, substrates, 285–286 dielectric constant, 286–287 disadvantages, 286–287, 291 port matrices, 191 power amplifiers (PAs) applications, 508–568 anti-improvised explosive device, 538, 539 electronic warfare, 534–537 jammers, 534 military, 530–538, 567–568 mobile telephony, 509 wireless communications, 519–530 broadband, 538 circuit-analysis software, 188 computer-aided design, 188–230 crest factors, 512–514 design holistic, 526, 528 issues, 619 overview, 523–526 parameter trade-offs, 509–514, 525, 567–568 processes, 525 devices, 105–106 efficiency, 508, 524–525, 567–568 factors affecting, 602–603 improvements, 620 power conversion, 509–510 functions, 508 instability, 605
linearity, 512–514 limits, 525 measurement, 512 linearization techniques memory effect compensation, 517 overview, 514 power efficiency impacts, 517–519 system level, 514–519 models bond wires, 219–221 circuit component losses, 219 circuit metallization loss, 217–219 ideal, 162 special issues, 216–221 modulation schemes, 512–514 nonlinearity, 508 output power–efficiency trade-off, 509–512 performance, 567–568 power combining anti-phase, 552–559 Doherty, 559–567 in-phase, 538–544 quadrature-phase, 544–550 power output average, 509, 522–523 control, 511–512 definition, 509 prototypes, 535 reliability, 504, 523 reliability goals, 448 requirements, 522–523 trends, 508–509 responses, nonlinear, 524 solid-state, applications, 284 in telecommunications systems, 508 see also balanced power amplifiers; high-power amplifiers (HPAs); microwave hybrid power amplifiers (MHPAs); microwave power amplifiers; push-pull amplifiers; RF power amplifiers (RFPAs) power back-off (PBO) Class A amplifiers, 164, 180 Class AB amplifiers, 169 Class B amplifiers, 168–169 power combining anti-phase, 552–559 balanced power amplifiers in, 546–547 Doherty, 559–567 in-phase, 538–544 see also couplers; Gysel combiners; quadrature-phase power combining; Wilkinson power combiners; Wilkinson splitters power consumption, low, 602 power conversion, efficiency improvements, 411 power cycling, thermal excursions, 480–481
Index
power density definition, 2–5 silicon LDMOSFETs, 441 trends, 441 power device models, 213 thermal effects, 214–216 see also self-heating models power efficiency impacts, 518–519 linearization effects, 517–519 power field effect transistor cells combination, 71 common-lead inductance, 68–69 design, 67–69 modeling, 69 dies, 71 gate finger equivalent circuits, 68 gate manifold equivalent circuits, 68 gate width, 67 images, 72 impedance matching, 71 layouts, 69, 71 manifold issues, 67–68 performance, 70 power field effect transistors field plates, 66–67 packages, 82 Schottky gate electrodes, 78–79 topology, 68–69, 73 see also microwave power field effect transistors power flow, 600 diagrams, 599 power sensors, 575 power measurements, 570–580 directional, 576–579 high-power RF, 576–579 spectrum analyzers in, 579–580 uncertainties, sources of, 574–576 power quad flat no lead (PQFN) packages see surface mount leadless packages (SMLPs) power sensors advantages, 571 applications, 570 modulated signal verification, 571 attenuators, 576–577 comparisons, 573 compensation techniques, 574 disadvantages, 571 dynamic range, 574 and equivalent generators, 574–576 impedance, 574–576 limitations, 570 power flow, 575 principles, 570–574 side effects, 574 see also directional power sensors
675
power supply–device resistance, 352 power-added efficiency (PAE), 509–510 definition, 36–37, 602 in MMIC PAs, 384–386 power-frequency (Pf2 ) limit, 45–46 PQFN packages see surface mount leadless packages (SMLPs) pre-distortion concept of, 514–515 schemes, 514 see also digital baseband pre-distortion (DPD) preconditioners, 199–200 preconditioning, 491–492 printed circuit boards (PCBs) alignment with housing, 292–293 calibration with, 593–596 guidelines, 594–595 coaxial connections, 312, 313 conductors, 289 dielectric losses, 288–289 etching, issues, 290–291 flange-mounted components, 292–293 ground path effects, 292–293 grounding issues, 285, 291 heat transfer, 414–415 lamination, 285–286 manufacturing issues, 290–291 in microwave hybrid power amplifiers, 285, 293 mounting, 291–292 solder, 292 patterning, 285 resistive losses, 288–289 resistors, integration, 285 RF connections, 312, 314–315 substrates, mounting issues, 285 thermal conductivity, 288–289 through-holes, 291 types of, 285 see also substrates Pro-E, 432 probability density function (PDF), 510–511, 512 process control monitors (PCMs), 80 process effects, 492–495 production-line testing, 570 prototypes jammers, 535, 536, 537 optimization, 570 power amplifiers, 535 pseudomorphic high-electron mobility transistors (pHEMTs), 47 applications, in MMICs, 361–362 band diagrams, 49, 50–51 current–voltage characteristics, pulsed, 53 design, epi-layer, 64–65
676
Index
pseudomorphic high-electron mobility (cont.) development, 358 gain, 61–62 humidity acceleration factors, 488–492 materials, 48–49 gallium arsenide vs. gallium nitride, 534–535 structure, 48–49 PSK see phase-shift keying (PSK) Psy-Ops (psychological warfare operations), RF power amplifiers, 235 psychological warfare operations (Psy-Ops), RF power amplifiers, 235 PTFE see polytetrafluoroethylene (PTFE) PTHs (plated-through holes), 291 pulse chopping, 635 pulse profile method, 634 transistors, 634–635 pulse width modulation (PWM), and Class S amplifiers, 183 pulsed measurements, 633–635 pulsed operation, principles, 633 push-pull amplifiers, 552–559 advantages, 552 baluns, 552 disadvantages, 552 operation, 552 schematics, 552 see also RF/microwave push-pull amplifiers PWM (pulse width modulation), and Class S amplifiers, 183 pyrolytic graphite, 427 Q see quality factor (Q) QFN (Quad Flat No leads) packages see surface mount leadless packages (SMLPs) QPSK see quadrature phase-shift keying (QPSK) Quad Flat No leads (QFN) packages see surface mount leadless packages (SMLPs) quadrature couplers, 328–331 frequency response, 546, 547 structure, 547 quadrature phase-shift keying (QPSK), 513–514 offset, 513 quadrature-phase power combining, 544–550 branchline hybrid, 547–549 qualification testing, 496 quality criteria, 641–642 and reliability, 447–448, 486 vs. spacing, 485, 494 vs. voltage, 486–487 see also reliability quality factor (Q), 318–320 load, 337–338
radar duplexers, functions, 530–531 efficiency, 508 limiters, 531 phased array, 530 RF power amplifiers, 235 transmitter/receiver modules, 530–534 block diagrams, 530, 531 performance requirement, 533 phased array antennas, 533 specifications, 533–534 variable phase shifters, 531 radiation, and thermal performance, RFPAs, 422–423 radiative energy, 422 radiative heat transfer, determination, 422–423 radiative heat transfer coefficient, 422–423 radio absorbent materials (RAMs), 304–305 radio base stations (RBSs), 417 bandwidth, 522 carrier capacity, 522 controllers, 417 efficiency, 440 improvements, 441 efficient, Doherty amplifiers for, 527–530 energy consumption, 411 power classification, 523 power output, 416 measurement, 576–577 RFPAs for, 411–412 running costs, 508 technologies, 523–524 thermal design, 416–419 thermal management, 411 waste heat, 411 removal, 416–417 radio frequency integrated circuits (RFICs) applications, 357 and monolithic microwave integrated circuits compared, 357 radio-controlled improvised explosive devices (RCIEDs) construction, 538 jammers, 538 ramped voltage testing, 466, 470 advantages, 468–469 disadvantages, 468–469 see also voltage ramping RAMs (radio absorbent materials), 304–305 rat-race couplers, 559, 560 ratings, maximum, 497 RBSs see radio base stations (RBSs) RCIEDs see radio-controlled improvised explosive devices (RCIEDs) RDSon see linear regime on-resistance (RDSon ) realizable ratio, use of term, 260
Index
recessed-gate process, 360 reconstruction filters, use of term, 183 rectangular truncations, 224 reduced conduction angle concept of, 171 in RF power amplifiers, 164, 166, 167 reduced surface fields (RESURF), 18 concept of, 19–21 LDMOSFETs, 2–5 reflected power, 581 reflected waves, 580 reflection coefficients, 337, 574–576, 596–597, 605–606, 610 complex source, 640 hot, 622 load, 600–601 optimum complex, 640 reflection measurement, values, 586 reflection normalization, 582–583 reflection tracking, 582–583, 596–597 relative gas permittivity, 295, 296 relative humidity testing, 491–492 reliability, 446–504 amplifiers, 447 analysis, 496 definitions, 447–449 issues, 447–448 design for, 495–500 design-controlled, 496–497 and device application, 496 estimation, 486–487 fans, 311 future trends, 504 gallium nitride wide bandgap transistors, 146–152 goals, 448 components, 448 goodness measures, 447 historical trends, 501–502 importance of, 446 and metallization, 494–495 models, 496 optimization, 499–500 overview, 446, 503–504 and performance, 448 power amplifiers, 504, 523 and quality, 447–448, 486 semiconductors, 446, 502–503 strategies, 448–449 silicon carbide wide bandgap transistors, 146–152 sudden reliability problem, 146–147 technology comparisons, 501–502 terminology, 447–449 vs. temperature, 412 components, 305
677
see also quality; ruggedness reliability budgeting, 500 reliability predictions, 473–475, 503–504 evaluation procedures, 473–474 operational analysis, 474 thermal analysis, 474 reliability tests, methodologies, 446 remote radio heads (RRHs), 441 residual errors, 598–599 resistive-inductive-capacitive (RLC) feedback networks, 251, 274, 315 resistivity AlGaN/GaN HFETs, 132 bulk, metals, 289 gallium arsenide, 44 metals, 218–219 substrates, 44 resistors ballast, 216 chip, 316 as distributed components, 323–324 electromigration, 463–464 equivalent circuits, 318 lead-length inductance, 316 lumped, 367 in microwave hybrid power amplifiers, 316–318 modeling, 315 in printed circuit boards, 285 scattering parameters, 318 in silicon LDMOSFETs, 36–37 in silicon VDMOSFETs, 36–37 surface mount, 316–318 thick-film, 318 thin-film, 498 resists, 78–79 photoresists, 483, 493 Restriction of Hazardous Substances (RoHS), 294 RESURF see reduced surface fields (RESURF) return loss (RL), 336–337 RF bias acceleration, 472–473 applications, 472–473 and hot carrier injection, 473 RF connections current maximization, 314 and discontinuities, 314 housings, 311–315 printed circuit boards, 312, 314–315 RF performance, vs. biasing, 348–349 RF power, definitions, 599 RF power amplifiers (RFPAs) altitude, 240 AM–AM distortion, 237 AM–PM distortion, 237 applications, 1, 233 commercial, 236 industrial, 235
678
Index
RF power amplifiers (RFPAs) (cont.) medical, 235 military, 234–235 radio base stations, 411–412 scientific, 235 basic elements, 242–243 building blocks, 526 capacitors, input/output coupling/decoupling, 250, 259 classes A to S, 159–186 active device models, 161–162 inverted modes, 179–180 multimodes, 184–186 variances, 186 concurrent power, 247 conducted/radiated emissions, 241 conducted/radiated susceptibility, 241 design future trends, 282–283 hypothetical, 252–282 issues, 1 procedures, 242 redundancy, 247 system level overview, 242–252 thermal, 411–442 distortion harmonic, 239 intermodulation, 239 dynamic range, 237–238 efficiency, 238, 282, 416, 440 trade-offs, 527 equipment, 416–417 fall time, 238 feedback networks, 251, 267–268 frequency response, 236–237 gain, 237 gain flatness, 237 gain linearity, 237 gain temperature stability, 237 hardware, realization, 234, 241–242, 254–255 heat flows, 419 heat sinks, 417 historical background, 160 inductors, coupling/decoupling, 250, 259 input/output coupling/decoupling networks, 250, 259 IR images, 435 linear, 160 linearity, trade-offs, 527 markets, 1, 232–233 materials, thermo-physical properties, 423–427 mating surface flatness, 439 maximum power transfer, 282, 283 mean time to failure, 241
modules block diagrams, 243, 244 design overview, 243–246 hypothetical, 252–282 multilevel breakdown, 256 physical construction, 271–273 test results, 273–280 multistage, 527 noise floor, 239 operating temperature range, 240 pallets, 417, 418 thermal stack-up, 417–418, 438 phase linearity, 237 physical construction, 418–419 power output, 236 practical realization, 232–283 overview, 232 processes, 233–242 RF power transistor selection, 243–244 processes, 243 pulse droop, 238 pulse overshoot, 238 rack-mounted, 417 reduced conduction angle, 164, 166, 167 ringing/settling time, 238 rise time, 238 shock/vibration, 240–241 specifications qualitative delineation, 233–236, 252–253 quantification, 234, 236–241, 253–254 realization, 241–242 stability, 239–240 system block and wire diagrams, 242–243, 254 temperature profiles, 430–431 thermal design, 411–442 advanced, 432–440 basics, 413–423 future trends, 440–442 importance of, 411–413 in portable products, 413–415 thermal management, 251–252, 432–440 thermal performance characterization and prediction tools, 427–432 conduction and, 420–421 convection and, 421–422 and heat transfer, 419–423 phase change cooling and, 423 radiation and, 422–423 topology, 525 voltage standing wave ratios input, 239 load, 239 see also gallium nitride RF power amplifiers (GaN RFPAs); hypothetical RFPA subsystem modules; microwave hybrid power amplifiers (MHPAs)
Index
RF power transistors absolute maximum ratings, 244, 247 applications, 39, 244, 247 bias/thermal tracking networks, 249–250 breakdown voltages, 246, 248 capacitances input, 246, 249 output, 246, 249 reverse transfer, 246, 249 classes, 249, 255–257 datasheets, 244–246 design issues, 1 efficiency, 244, 248 electrical characteristics, 244 frequency range, 244, 247–248 future trends, 282–283 gain, 244, 248 as ideal current sinks, 165 impedance input, 248–249 output, 248–249 impedance matching, 250–251, 259–267, 283 HF, 250 UHF, 250 VHF, 250 joining processes, 426–427 large signal impedance, 246 load mismatch tolerance, 246 power output, 244, 247, 255 scattering parameters, 246, 249 selection, 243–244, 255–257 applications and, 246 class, 246 process guidelines, 246–249 thermal performance, 32 thermal resistance, 244, 248 threshold voltages, 246, 248 transfer function plots, 249 typical, 246 RF testing, 430 accurate, 570 automatic, 370 on-wafer, 80 RF/microwave push-pull amplifiers, 557–559 advantages, 558 balun structures, 558 block diagrams, 557–558 disadvantages, 559 RFICs see radio frequency integrated circuits (RFICs) RFPAs see RF power amplifiers (RFPAs) Rjc see junction-to-case thermal resistance (Rjc ) RL (return loss), 336–337 RLC (resistive-inductive-capacitive) feedback networks, 251, 274
679
RoHS (Restriction of Hazardous Substances), 294 Root model, 88 RRHs (remote radio heads), 441 ruggedness, 22–26 and drain engineering, 24 factors affecting, 23 measurement, 22–23 Ruthroff unbalanced–unbalanced transformers, 555, 556, 557 S parameter measurements see scattering (S) parameter measurements S parameters see scattering (S) parameters safety regulations, 570 SAGs see self-aligned gates (SAGs) satellite down converters, gasket-sealed, 299 saturation effect, 615 scalar network analyzers limitations, 582–586 measured values, determination, 582–583 parasitic effects, 583–584 scalar reflection measurements, 582 scalar transmission measurements, 585 scattering (S) parameter measurements, 580–599 requirements, 641 uncertainties, 598–599 scattering (S) parameters, 88–89 applications, 206 attenuators, 596 capacitors, 206–207 concept of, 580–581 in database models, 212 DC, 208 definition, 581 dummy, 207–208 hot, 622–623 limitations, 641 magnitudes, measurement, 586–587 mixed-mode, 608–611 models, 206–208 in harmonic-balance analysis, 207–208 interpolation, 206 issues, 206–208 vs. lumped-element models, 208 phase, measurement, 586–587 resistors, 318 RF power transistors, 246, 249 SCDs (source control drawings), 248 Schottky barrier gate, 45 Schottky diodes, 345–347 Schottky gate electrodes, 78–79 Schottky gate field effect transistors, 45 failure mechanisms, 454–455 materials, 45 scientific markets, RF power amplifiers, 235
680
Index
screw locking epoxies and, 304 housings, 304 torques, 308 sealing housings, 294–299 issues, 294 mobile phones, 414 and moisture ingress, 295–296 see also gasket sealing; hermetic sealing second-order intercept (SOI) point, 611–613 self-aligned gates (SAGs) multifunction, 360 process, 360 self-heating models, 214–215 disadvantages, 215–216 self-resonant frequencies (SRFs), 320–321 SEM (spectrum emission mask), 522, 525 Semanskii iteration, 199 semiconductor equations, 128–129 semiconductors electron velocity vs. electric field transport characteristics, 113 failure mechanisms, humidity, 490 failure rates, 455–456, 458 manufacture, processes, 492–493 metallization, 488 operating temperature, measurement, 428–429 properties, 112 and performance, 111 reliability, 446, 502–503 strategies, 448–449 RF output power vs. frequency, 104 see also diodes; transistors sensors temperature, 258, 429 thermistor, 571 see also diode sensors; power sensors; thermal sensors sequencing circuits, 348 SER (symbol error rate), 635–636 shape parameter, definition, 459–460 shooting methods, 203–204 short standards, 582–583 short-term signal level scorecards, 281 Shubnikov–DeHaas mobility measurements, 114 SiC see silicon carbide (SiC) 4H-SiC BJTs see 4H-silicon carbide bipolar junction transistors (4H-SiC BJTs) 4H-SiC MESFETs see 4H-silicon carbide metal semiconductor field effect transistors (4H-SiC MESFETs) sidegating, 454 sigma (shape parameter), 459–460
signal flow charts, stability, 606 signal-to-noise ratio (SNR), 637 significance testing, 449–450 silicon thermal conductivity, 425 wafers, 357 silicon bipolar transistors historical background, 1 limitations, 1–2 silicon carbide (SiC) applications, 105–106 charge carrier mobility, 113–114 hole mobilities, 115 4H-silicon carbide bipolar junction transistors (4H-SiC BJTs) fabrication, 106 gain, 106–107 high-power, 106–107 performance, 106 4H-silicon carbide metal semiconductor field effect transistor amplifiers, 120–122 current gain, DC, 121 performance, 122 RF, 121, 122 power gain, DC, 121 power gains, 121–122 small-signal current gains, 121–122 4H-silicon carbide metal semiconductor field effect transistors (4H-SiC MESFETs) advantages, 118–119 applications, microwave power amplifiers, 105 background, 106–108 current–voltage relationships, DC, 120 development, 107–108 fabrication, 107–108, 118–119 field plates, 108 future trends, 152–153 limitations, 108 performance, 107–108, 120 structure, 119 β-silicon carbide nanowires, applications, 108 silicon carbide transistors, background, 106–108 silicon carbide wide bandgap transistors, 103–153 breakdown, 112–113 development, 104–105 device design, 118–125 future trends, 152–153 large-signal effects, 130–152 gate leakage, 144–146 nonlinear source and drain resistances, 133–143 reliability and time-dependent performance degradation, 146–152 space-charge limited current transport, 130–133
Index
material parameters, 111–115 models, 125–130 equivalent circuits, 125–127 physics-based large-signal, 128 properties, 112 RF performance, 118–125 thermal conductance, 112–113 silicon lateral double diffused metal–oxide–silicon field effect transistors (silicon LDMOSFETs), 1–39 advantages, 2, 432–433 applications, 39, 433 50V and higher, 35–36 land mobiles, 34–35 mobile telephony, 35 radio base stations, 523–524 bondpad manifolds, 29, 32 breakdown voltages, 5, 17–22 capacitances, 15–16 drain-to-source, 5, 13, 15–16 gate-to-drain feedback, 16 gate-to-source, 16 parasitic, 12–15 channel doping profiles, 19 construction, 2–8 dies, 2–5 cross-sections, 4, 23, 32, 433 current flows, 11, 31 current paths, 11 current transport, 10–11 current–voltage characteristics, 20 depletion region boundaries, 5 design, 27–39 metal, 30–32 thermal, 32–34 device physics, 10–27 disadvantages, 2 doping profiles, 6, 14–15 drain metallization, 7–8 drain resistance, 14–15 drain structure optimization, 5 drain-to-source pitch, 28–29 efficiency, 34 electrodes, 433 electromigration, 30–32 enhancement mode, 135 field plates, 7–8, 18–19 effects, 8 frequency issues, 36–37 frequency limits, 42 frequency optimization, 37 frequency responses, 12–14 gate construction, 5–6 gate finger arrays, 27, 28 gate length, 5–6, 36–37 gate oxides, 5–6
gate resistance, 5–6, 14–15 gate width, 27, 36–37 limitations, 37 heat dissipation, 433 historical background, 1–2 hot carrier injection, 2–5, 17–22 levels, 7–8 infrared scans, 34 layout, 3, 27–39 top-down finger, 27–29 linear regime on-resistance, 5, 17–22 market domination, 39 multiple heat source fingers, 433, 434 n-drift region, 2–5, 7–8 and field plates, 18–19 length change, 25–26 long, 26–27 operating voltage, issues, 26–27, 34–36 overview, 1–2 P + sinker, 7, 28–29 p-epi region, 5, 26–27 packaging, 82–83 parasitic drain resistance, 7–8 parasitic elements, behavior, 12–17 PHV implants, 6–7 power density, 441 power levels, 34 power output, 27 quiescent current degradation, 22 reduced surface fields, 2–5 regions, 6–7 resistances, parasitic, 12–15, 33–34 resistors, 36–37 ruggedness, 22–26 snapback, 22–26 source, 7 terminals, 10–11, 29 thermal design, 432–440 thermal flux, 441 thermal performance, 32–33 thermal resistance, 433 spreading, 433–436 thermal scans, 35 silicon LDMOSFETs see silicon lateral double diffused metal–oxide–silicon field effect transistors (silicon LDMOSFETs) silicon nitride, applications, dielectrics, 453 silicon nitride capacitors structure, 466 voltage acceleration, 466–471 silicon nitride films breakdown voltages, 466 characterization, 466 silicon VDMOSFETs see silicon vertical double diffused metal–oxide–silicon field effect transistors (silicon VDMOSFETs)
681
682
Index
silicon vertical double diffused metal–oxide–silicon field effect transistors (silicon VDMOSFETs), 1–39 advantages, 2 applications, 39 50V and higher, 35–36 bodies/substrates, 8–9 bondpad manifolds, 29 breakdown voltages, 17–22 capacitances gate-to-drain feedback, 16 gate-to-source, 16 parasitic, 12–14, 16 construction, 8–9 cross-sections, 9 current flows, 12 current paths, 11 current transport, 10–11 design, 27–39 metal, 30–32 thermal, 32–34 device physics, 10–27 disadvantages, 2, 9 drain, 8–9 drain voltage, 8–9 drift region design, 9 efficiency, 34 electromigration, 30–32 frequency issues, 36–37 frequency optimization, 37 frequency responses, 12–14 gate finger arrays, 27 gate length, 36–37 gate width, 27, 36–37 limitations, 37 historical background, 1–2 hot carrier injection, 17–22 layout, 27–39 top-down finger, 27–29 linear regime on-resistance, 17–22 market domination, 39 n drift, 8–9 n-drift region, length change, 26 operating voltage, issues, 26–27, 34–36 operation, high voltage, 26 overview, 1–2 packaging issues, 9 parasitic elements, behavior, 12–17 PHV implants, 19 power levels, 34 power output, 27 resistances, parasitic, 8–9, 12–14, 16, 33–34 resistors, 36–37 ruggedness, 22–26 snapback, 22–26 source-to-gate pitch, 28–29
terminals, 10–11 thermal performance, 32–33 simulators three-dimensional, 211–212 see also electromagnetic simulators; plant simulators single-layer capacitors (SLCs) applications, 318–321 structure, 318–320 sinking gates FETs, 458 mechanisms, 459–462 skin depth determination, 288–289 use of term, 288–289 skin effects, and metal losses, 218 SLCs see single-layer capacitors (SLCs) small-signal models equivalent circuits, 84–85 for GaAs FETs, 84–85 Smith charts, 337–338, 586–587, 600–601, 606–607, 640 SMLPs see surface mount leadless packages (SMLPs) snapback, 22–26, 59 effects, 58–59, 60 prevention, 24 use of term, 23–24 snapback current characterization, 25–26 increase, 24 and ruggedness, 23 snapback voltage, 23–24 characterization, 25–26 SNR (signal-to-noise ratio), 637 soft substrates, 285 dimensional issues, 289 materials, 285–286 moisture absorption, 293 use of term, 285–286 SOI (second-order intercept) point, 611–613 solders, for die attach, 426–427 solid-state devices models, 213–216 thermal effects in, 214–216 solid-state power amplifiers (SSPAs), applications, 284 solid-state transistors applications, microwave systems, 103 upper frequency limits, 103–104 and vacuum tubes compared, 103 source control drawings (SCDs), 248 source stepping, use of term, 223 source-pull measurements, 619–622 set up, 621 spacing, vs. quality, 485, 494
Index
sparse matrices, 192–193 specification thresholds, as failure criteria, 449–450 spectrum analyzers, 268 adjacent channel power ratio, 627, 628 applications, 586 power measurements, 579–580 implementation, 580 intermodulation products, 612 noise figure, 628 properties, 579–580 spectrum emission mask (SEM), 522, 525 SPICE models, 222, 223 development, 205 in harmonic-balance analysis, 226 SRFs (self-resonant frequencies), 320–321 SSPAs (solid-state power amplifiers), applications, 284 stability linear, issues, 605–608 signal flow charts, 606 stability circles, 606–607 stability factors, 341–343 definitions, 607–608 standard deviation, and median compared, 468 static induction transistors (SITs) applications, 107 fabrication, 107 operation, 107 Stefan–Boltzmann constant, 422 step attenuators, 587–588 stubs distributed, 324 impedance matching, 338 lossy, 325–326, 327 open-circuit, 325–326, 354 short-circuited, 324, 326, 349, 354 substrates backings, 291 metal, 291 ceramic packages, 392–393 dielectric constant, 287–288 factors affecting, 293 dielectric losses, 288–289 impedance standard, calibration standards, 595–596 isotropy, 287–288 materials, failure mechanisms, 454 materials selection, and impedance range, 289 MMICs, 359, 361 comparisons, 361 mounting, 292 parameters, for hybrid amplifiers, 286 properties, 287 resistivity, 44 and test fixtures, 595 thermal resistance, 437–438
683
thickness, 289 issues, 289 trace dimensions, 290 types of, 285 see also hard substrates; soft substrates success, probabilities of, 447 sudden reliability problem, 146–147 surface mount devices, heat transfer, 307 surface mount leadless packages (SMLPs), 83, 395–396, 399 construction, 82–83 development, 394 types of, 394 sweet spot, use of term, 261–262 symbol error rate (SER), 635–636 system error correction 3-term error model, 589 7-term error model, 589, 592 overview, 588–589 in vector network analyzers, 588 T-check, 598–599 TACS (Total Access Communication System), 508–509 Taguchi technique, 377 talk time, mobile phones, 508 tantalum nitride, applications, 316 Taylor series, 201, 611, 614–615, 625, 632–633 TDDB see time-dependent dielectric breakdown (TDDB) TDMA see time division multiple access (TDMA) technology comparisons over time, 501–502, 503 of reliability, 501–502 tee-equivalent circuits, 126–127 large-signal, 128 small-signal, 126 telecommunications systems, power amplifiers in, 508 temperature and component reliability, 305 and dielectric constants, 287 and humidity, 488–489 and mean time between failure, 412 vs. electromigration, 33 vs. lifetimes, 462 vs. performance, 411–412 vs. reliability, 412 see also noise temperature temperature acceleration effects, on FET lifetimes, 498 temperature field patterns, mobile phones, 414–415, 416 temperature monitors, 479–480 temperature profiles, RFPAs, 430–431 temperature sensors, 258, 429
684
Index
temperature-humidity-bias (THB) test, 83–84 termination space, multidimensional, 185–186 test fixtures calibration with, 593–596 and substrates, 595 test port match, 583–584 directional elements, 585 testing element, 448–449 environmental, plastic packages, 491–492 inaccurate, 570 on-wafer, 401–403, 404 production-line, 570 qualification, 496 relative humidity, 491–492 significance, 449–450 three-terminal, 57–58 two-terminal, 57–58 verification, 496 wafer acceptance, 81 see also devices under test (DUTs); highly accelerated stress tests (HASTs); life testing; ramped voltage testing; RF testing TFE (thermionic field emission), 58–59 Tgon, 427 THB (temperature-humidity-bias) test, 83–84 THD (total harmonic distortion), 614–615 thermal acceleration, 458–462 factors, determination, 462 thermal analysis, reliability predictions, 474 thermal characterization, experimental, 427–428 thermal conductivity, 420, 423 gallium arsenide, 436 homogeneous, 420–421 materials, 423–424 at room temperature, 425 behavior, 424–425 see also conduction thermal cycling, 477–478 thermal design mobile phones, 413–415 radio base stations, 416–419 RF power amplifiers, 411–442 silicon LDMOSFETs, 432–440 thermal diffusivity, 420, 423 thermal droop, 52, 53 thermal effects, in solid-state device models, 214–216 thermal excursions copper bumps, 478–482 failure criteria, 480 failure distributions, 477 interconnect vias, 475–478 power cycling, 480–481 profile data, 477 standards, 476
testing, 476 thermal flux, trends, 441 thermal greases, 427 thermal inertia (TI), 305–307 thermal load, spreading, 307 thermal management cost overheads, 411 future trends, 442 radio base stations, 411 RFPAs, 251–252, 432–440 see also heat sinking; heat transfer thermal modeling, computer-aided, 427–428 thermal noise, 636 thermal pads, 427 thermal performance and heat transfer, in RFPAs, 419–423 housings, 306 LDMOSFETs, 32–34 measurement, 428–431 modeling, 431–432 RF power transistors, 32 RFPAs characterization and prediction tools, 427–432 conduction, 420–421 convection, 421–422 phase change cooling, 423 radiation, 422–423 simulation, 431–432 VDMOSFETs, 32–34 thermal ratings, 496–497 thermal resistance (TR) determination, 305–307 die attach, 436–437 and die thickness, 436 factors affecting, 436 heat sinks, 439–440 lead–tin–silver die attach, 437 microwave hybrid power amplifiers, 305 microwave power field effect transistors, 73–74 reduction, 307–308, 425 RF power transistors, 244, 248 silicon LDMOSFETs, 433 spreading, 433–436 substrates, 437–438 vias, 307 see also contact thermal resistance; junction-to-case thermal resistance (Rjc ) thermal scaling, 214–215 thermal sensors, 571, 572 applications, 571 thermal shock, 477–478 thermal test chips, 429 thermal vias, 414 thermionic field emission (TFE), 58–59 thermistor power meters, 571 principles, 572
Index
thermistor sensors, 571 thermocouple thermometers, 428 thermographic phosphors, in operating temperature measurement, 428–429 thermoset materials advantages, 286–287 dielectric constant, 286–287 thick-film resistors, 318 thin-film resistors, reliability guidelines, 498 third-order intercept (TOI) point, 611–613 3rd Generation Partnership Project (3GPP), 519–520 power classes, 522 specifications, 518–519 three-dimensional simulators, 211–212 three-terminal tests, 57–58 threshold malfunction, 490 through–open–match (TOM) calibration, 598–599 TI (thermal inertia), 305–307 time division multiple access (TDMA), 511–512 measurement, 627 time in operation, wireless sensor networks, 508 time-dependent dielectric breakdown (TDDB), 453–454 measurement, 465–466 MIM capacitors, 466–471 time-domain analysis, 202–203 applications, 616 computational costs, 203 differential equations, 202 procedures, 202–203 variants, 203–205 frequency-domain models, 204 multitone analysis, 204–205 shooting methods, 203–204 TLPGs (transmission line pulse generators), applications, 25–26 TMAs (tower mount amplifiers), 441 TOI (third-order intercept) point, 611–613 TOM (through–open–match) calibration, 598–599 toroids, 553–554 Total Access Communication System (TACS), 508–509 total harmonic distortion (THD), 614–615 tower mount amplifiers (TMAs), 441 TR see thermal resistance (TR) track dimensions, 290–291 transconductance (gm ), 60, 353 compression, 53 dispersion, 55 FETs, 134–135 transducer gain, 599–600 determination, 621–622 maximum, 600–601 transformer matching, 339–341 capacitor-loaded, 342 double short, 341
685
transformers autotransformers, 553 balanced–balanced, 556–557 input, 265 output, 272 quarter-wave, bandwidth, 339 see also coupled-coil transformers; transmission line transformers; unbalanced–unbalanced transformers transistor amplifiers configuration, 115 two-port network, 115 current–voltage relationships DC, 115–117 RF, 117 efficiency, 117–118 impedance matching, 117 operating principles, 115–118 power delivery, 115–117 RF performance, 117 transistors, 331–332 bias networks, 345, 346 channel current degradation, 460 degradation, 461 life testing, 459–462 median lives, 461 models, 125–130 equivalent circuits, 125–127 physics-based large-signal, 128 out-of-band performance, 349 performance, false claims, 331 properties, 112 pulse profile method, 634–635 reliability guidelines, 497–498 screw fixing issues, 308 selection criteria, 332 silicon carbide, background, 106–108 time to failure vs. voltage, 472 see also bipolar junction transistors (BJTs); field effect transistors (FETs); high-electron mobility transistors (HEMTs); RF power transistors; solid-state transistors; static induction transistors (SITs); wide bandgap transistors transition frequency (fT ) definition, 62–63 determination, 90 limitations, 63 transmission coefficient, 585, 603–604 transmission line pulse generators (TLPGs), applications, 25–26 transmission line transformers, 250–251, 259–261, 262–265, 554–557 building blocks, 554 coaxial quarterwave, 555 input insertion loss, 264–265, 266
686
Index
transmission line transformers (cont.) maximum power transfer, 556 mutually coupled inductances, 263, 264 parasitic models, 262 topological synthesis, 261 transmission lines cascaded, 620 as distributed components, 324 in high-power RF measurements, 578 interferences, 608–610 for MMICs, 362 parameters, 355 selection criteria, 554–555 single-ended, 608 strip, closed-form models, 210 symmetrical, 608 thickness, factors affecting, 288–289 as unbalanced transformers, 555–556 see also microstrip; stubs; waveguides transmission loss, 337 transmission measurements, 586 transmission normalization, 585 transmitted power, 581 transmitted waves, 580 trapping effects, 53–54 consequences, 54–57 breakdown voltage increase, 56 drain lag, 55–56 gate lag, 55–56 kink effect, 56–57 large-signal model inaccuracies, 56 memory effects, 56 output conductance dispersion, 55 power output reduction, 54–55 transconductance dispersion, 55 and large-signal models, 87–88 minimization, 54 traveling-wave tube amplifiers (TWTAs), 534 triangular truncations, 224 trigger signals, 627 triplexer method, 620 Triquint TOM models, 86–87 tuners, passive, 620 tuning disks, 355 tunneling, 58–59 two-dimensional simulators, 210–211 two-port networks, linear distortion, 603 two-terminal tests, 57–58 two-tone signals, 613–614 generation, 613–614 measurement issues, 613–614 TWTAs (traveling-wave tube amplifiers), 534 U see unilateralized gain (U) UGW see unit gate width (UGW)
UMTS see Universal Mobile Telecommunications System (UMTS) unbalanced–unbalanced transformers, 555–556 Ruthroff, 555, 556, 557 uncertainties measurements, 598–599 sources of, 574–576 types of, 598 unilateralized gain (U) curves, 62, 90–91 definition, 62 unit gate width (UGW) definition, 27 large, 27–28 unity circles, 606–607 Universal Mobile Telecommunications System (UMTS) bandwidth, 522 base station power classification, 523 standards, 519–520 Unix, pipes, 229 unknown–open–short–match (UOSM) calibration and 7-term error model, 592 with mixed test port types, 591–592 UOSM calibration see unknown–open–short–match (UOSM) calibration vacuum tubes applications, microwave systems, 103 RF output power vs. frequency, 104 in RF power amplifiers, 160 and solid-state transistors compared, 103 valves see vacuum tubes VCVSs (voltage-controlled voltage sources), 191–192 vector network analyzers (VNAs), 264–265, 586–588, 604 applications, 268, 586 scattering parameter measurements, 599 architecture, 587–588 building blocks, 587, 602–603, 631 calibration, 622 dynamic range, 616 effective system data, 589, 591 raw system data, 589, 591, 597 sweeps, 603 system error correction, 588 two-port, 587 velocity-field curves, nonlinear, 131 verification testing, 496 Verilog A, 222 vertical double diffused metal–oxide–silicon field effect transistors (VDMOSFETs), 249 see also silicon vertical double diffused metal–oxide–silicon field effect transistors (silicon VDMOSFETs)
Index
vias manufacture, 291 thermal, 414 thermal excursions, 475–478 thermal resistance, 307 see also interconnects virtual gate effect, 145 VNAs see vector network analyzers (VNAs) voltage vs. quality, 486–487 see also breakdown voltages; snapback voltage voltage acceleration, 484 capacitors, 487–488 factors, 465–472 HEMTs, 471–472 MIM capacitors, 465–466 silicon nitride capacitors, 466–471 voltage ramping, 468 MIM capacitors, 466–471 see also ramped voltage testing voltage regulators, 348 low drop out, 348 voltage standing wave ratios (VSWRs), 337 RF power amplifiers input, 239 load, 239 in ruggedness testing, 22–23, 25–26 voltage waves, 580 voltage-controlled voltage sources (VCVSs), 191–192 VSWRs see voltage standing wave ratios (VSWRs) W-CDMA see Wideband Code Division Multiple Access (W-CDMA) wafer acceptance test (WAT), 81 wafer probes, calibration with, 593–596 waste heat disposal, 411, 427 radio base stations, 411, 416–417 WAT (wafer acceptance test), 81 water cooling, housings, 311 water vapor and sealing, 295 thresholds, 490 wave propagation, devices under test, 580 waveform balance approach, 201 waveguide flanges, 589 waveguides, 299, 311–312 discontinuities, 211–212 see also coplanar waveguide (CPW); stubs; transmission lines wear-out, 457 amplifiers, 447 mechanisms, 462–463 vs. defects, 475–492
687
wide bandgap materials, applications, 284 wide bandgap semiconductors, 372–373 wide bandgap transistors advantages, 111, 118 applications, 105 electron saturation velocities, 118 properties, 112 see also gallium nitride wide bandgap transistors; silicon carbide wide bandgap transistors Wideband Code Division Multiple Access (W-CDMA), 349–352, 508–509 handset amplifier simulations, 219, 220 output spectra, 529–530 Wiebull analysis, 282 Wilkinson power combiners, 334, 533–534, 538–541 amplitude imbalance, 540 applications, 538–540 frequency bandwidth performance, 541, 542 and Gysel combiners compared, 545 phase imbalance, 540–541 single-section, 540 Wilkinson splitters, 328–331, 547, 552 design, 541, 542 layouts, 541, 542 performance, 543 WiMAX see Worldwide Interoperability Microwave Access (WiMAX) wire bonding methods, 397 in MMIC PA package assembly, 396, 397–398 modeling, 397–398 procedures, 397 wireless communications power amplifiers, 519–530 design, 523–526 requirements, 522–523 requirements, system level, 522–523 wireless sensor networks, time in operation, 508 Wirelines, 328, 329 Worldwide Interoperability Microwave Access (WiMAX), 38–39 frequency bands, 520, 521 standards, 520–522 X-parameters, 88–89 Y parameters see admittance (Y) parameters Y-factor method, 638–640 setup, 638 yield, measurement, 484 Zener diodes, 347 zeroing, 574
