Planar Double-Gate Transistor: From Technology to Circuit

Planar Double-Gate Transistor Amara Amara • Olivier Rozeau Editors Planar Double-Gate Transistor From Technology to ...

Author: Amara Amara | Olivier Rozeau

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Planar Double-Gate Transistor

Amara Amara • Olivier Rozeau Editors

Planar Double-Gate Transistor From Technology to Circuit

Amara Amara Institut Supérieur d’Electronique de Paris (ISEP) 21 rue d’Assas 75006 Paris France [email protected]

ISBN 978-1-4020-9327-2

Olivier Rozeau CEA, LETI-MINATEC 17 rue des martyrs 38054 Grenoble CX 9 France [email protected]

e-ISBN 978-1-4020-9341-8

Library of Congress Control Number: 2008939918 c 2009 Springer Science + Business Media B.V. No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Printed on acid-free paper. 9 8 7 6 5 4 3 2 1 springer.com

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

Multiple Gate Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thierry Poiroux, Maud Vinet, and Simon Deleonibus 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Advantages of Multiple Gate Technologies . . . . . . . . . . . . . . . . . . . . 1.2.1 Requirements for Future Technology Nodes . . . . . . . . . . . 1.2.2 MOSFET Electrostatics Control . . . . . . . . . . . . . . . . . . . . . 1.2.3 Variability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4 Gate Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.5 Carrier Transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.6 Series Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Planar Double Gate Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 Double Gate Transistors by Layer Deposition . . . . . . . . . . 1.3.2 Non Self-aligned Transistors by Wafer Bonding . . . . . . . . 1.3.3 Self-aligned Transistors by Wafer Bonding . . . . . . . . . . . . 1.3.4 Suspended Channel Based Approaches . . . . . . . . . . . . . . . 1.4 Non Planar Multiple Gate Technologies . . . . . . . . . . . . . . . . . . . . . . 1.4.1 FinFET Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 Trigate Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 Surrounding Gate Transistors . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Conclusions and Perspectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Compact Modeling of Independent Double-Gate MOSFET: A Physical Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daniela Munteanu and Jean-Luc Autran 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Drift-Diffusion Drain Current Modeling . . . . . . . . . . . . . . . . . . . . . . 2.2.1 2-D Potential Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Inversion Charge Calculation . . . . . . . . . . . . . . . . . . . . . . . .

3 4 4 6 8 9 11 11 12 13 13 15 15 16 17 18 19 20 20 27 27 30 30 34

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2.2.3 Drift-Diffusion Drain Current . . . . . . . . . . . . . . . . . . . . . . . 2.2.4 Model Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Ballistic Current in the Subthreshold Regime . . . . . . . . . . . . . . . . . . 2.3.1 Physics of the Ballistic Transport . . . . . . . . . . . . . . . . . . . . 2.3.2 Potential Profile in the Subthreshold Regime . . . . . . . . . . . 2.3.3 Ballistic Current Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4 Model Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.5 Discussion: Impact of the Source-to-Drain Tunnelling Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

38 39 42 42 44 45 47

Compact Modeling of Double Gate MOSFET for IC Design . . . . . . . . Marina Reyboz, Olivier Rozeau, and Thierry Poiroux 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Modeling of Double Gate MOSFET with Independent Driven Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Challenge of the Surface Potential Based Model in Compact Model for IC Design . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 How to Model IDG MODEL with a Threshold Voltage Based Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Long Channel IDG Mosfet Threshold Voltage Based Model . . . . . . 3.3.1 Subthreshold Slope Factor (n) . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Threshold Voltage Modeling (Vth ) . . . . . . . . . . . . . . . . . . . . 3.3.3 Offset Voltage in Strong Inversion (Voff ) . . . . . . . . . . . . . . . 3.3.4 Drain Saturation Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.5 The Transconductance Behavior in IDG MOS . . . . . . . . . . 3.3.6 The Drain Conductance Behavior in IDG MOS . . . . . . . . 3.3.7 Mobility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.8 Charges Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Short Channel Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Subthreshold Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Threshold Voltage and the Subthreshold Factor Modeling 3.4.4 Short Channel Effect in Strong Inversion . . . . . . . . . . . . . . 3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

55

Low Frequency Noise in Double-Gate SOI CMOS Devices . . . . . . . . . Jalal Jomaah and Gérard Ghibaudo 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Low Frequency Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Carrier Number Fluctuations and Correlated Mobility Fluctuations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Hooge’s Mobility Fluctuations . . . . . . . . . . . . . . . . . . . . . . 4.2.3 Coupling Impact on Fluctuations . . . . . . . . . . . . . . . . . . . . .

48 50 51

55 56 56 58 60 60 63 67 70 72 73 73 75 77 77 79 80 82 83 84 89 89 90 90 91 91

Contents

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4.3 Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5

Analog Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Philippe Freitas, David Navarro, Ian O’Connor, Gérard Billiot, Hervé Lapuyade, and Jean-Baptiste Begueret 5.1 Double Gate MOSFET in Analog Design . . . . . . . . . . . . . . . . . . . . . 105 5.1.1 Double Gate Transistors Characteristics . . . . . . . . . . . . . . . 106 5.2 Current Mirrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.2.1 Threshold Voltage Modulation . . . . . . . . . . . . . . . . . . . . . . . 110 5.2.2 Performance Tunability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.3 Differential Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.3.1 Back Gates in Differential Mode . . . . . . . . . . . . . . . . . . . . . 114 5.3.2 Back Gates in Common Mode . . . . . . . . . . . . . . . . . . . . . . . 115 5.4 Low Voltage OTAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 5.4.1 IDGMOS Differential Current Mirror . . . . . . . . . . . . . . . . . 119 5.4.2 Fully Differential IDGMOS Low Voltage OTA . . . . . . . . . 124 5.5 High Speed Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

6

Logic Circuit Design with DGMOS Devices . . . . . . . . . . . . . . . . . . . . . . 137 Ian O’Connor, Ilham Hassoune, Xi Yang, and David Navarro 6.1 DGMOS Characteristics and Impact on Digital Design . . . . . . . . . . 137 6.2 Standard Cells Using DGMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.2.1 Benchmark Structures and Simulation Conditions . . . . . . 140 6.2.2 Results on FDSOI DGMOS Technology . . . . . . . . . . . . . . 141 6.2.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 6.3 Ultra Low Power Full-Adder using Double Gate SOI Devices . . . . 145 6.3.1 DGMOS NDR Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6.3.2 Ultra-low Power Full Adder (ULPFA) and Simulation Results in FDSOI DGMOS Technology . . . . . . . . . . . . . . . 148 6.3.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 6.4 DGMOS DEVICE Based Reconfigurable Cells . . . . . . . . . . . . . . . . 151 6.4.1 Generic m-Input Reconfigurable Cell . . . . . . . . . . . . . . . . . 152 6.4.2 Static-Logic Reconfigurable Cell DG-SLRC . . . . . . . . . . . 154 6.4.3 Tests with Two-Input DG-xLRC . . . . . . . . . . . . . . . . . . . . . 156 6.4.4 Comparison to Conventional LUT . . . . . . . . . . . . . . . . . . . 159 6.4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

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SRAM Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Bastien Giraud, Olivier Thomas, Amara Amara, Andrei Vladimirescu, and Marc Belleville 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 7.2 SRAM Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7.2.1 SRAM Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7.2.2 Basic Operation of an SRAM Memory . . . . . . . . . . . . . . . . 171 7.2.3 SRAM Memory Cell Design Parameters . . . . . . . . . . . . . . 172 7.3 Double Gate 6T SRAM Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 7.3.1 DGMOS with Tied Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 7.3.2 Innovative 6T SRAM Cell Architectures . . . . . . . . . . . . . . 182 7.3.3 Summary and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . 193 7.4 Double Gate 4T & 5T SRAM Memories . . . . . . . . . . . . . . . . . . . . . . 195 7.4.1 DGMOS with Tied Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 7.4.2 DGMOS with Independent Gate Biasing . . . . . . . . . . . . . . 197 7.4.3 Electrically Asymmetrical DGMOS . . . . . . . . . . . . . . . . . . 199 7.4.4 Summary and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . 201 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Introduction

Until the 1990s, the reduction of the minimum feature sizes used to fabricate integrated circuits, called “scaling”, has highlighted serious advantages as integration density, speed, power consumption, functionality and cost. Direct consequence was the decrease of cost-per-function, so the electronic productivity has largely progressed in this period. Another usually cited trend is the evolution of the integration density as expressed by the well-know Moore’s Law in 1975: the number of devices per chip doubles every 2 years. This evolution has allowed improving significantly the circuit complexity, offering a great computing power in the case of microprocessor, for example. However, since few years, significant issues appeared such as the increase of the circuit heating, device complexity, variability and difficulties to improve the integration density. These new trends generate an important growth in development and production costs. Though is it, since 40 years, the evolution of the microelectronics always followed the Moore’s law and each difficulty has found a solution. For example, the circuit heating is a real problem. How to reduce heating of future processor generations to avoid a huge increase of the temperature in a computer? Circuit heating is meanly due to dynamic power consumption, leakage currents (subthreshold currents, gate currents, etc.), also to the thermal resistance of the packaging. Introducing high-k gate oxide, the static power consumption can be reduced. By reducing circuit clock frequency and by using new circuit architectures to improve the computing capabilities, the dynamic power consumption can also be reduced. By optimizing circuit packaging and fan efficiency, the heat can be more easily evacuated. Solutions exist in term of circuit architectures, device and packaging optimization to improve the performances while maintaining power consumption and heat at a reasonable level. Design and technology optimization must be concurrently considered for more efficiency. The scaling of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) predicted by the ITRS [1] should involve very important leakage current issues in the circuit for the 32 nm technology node and beyond. At the present

A. Amara and O. Rozeau (eds.), Planar Double-Gate Transistor. c Springer Science + Business Media B.V. 2009

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Introduction

time, the increase of these leakage currents seems to be not easily manageable with conventional MOS architectures. An alternative solution consists in employing field-effect transistors on siliconon-insulator substrate (SOI). This solution exists since a long time but is not widely used in an industrial context. However, the main advantage of using ultra thin silicon is to guarantee an excellent electrostatic channel control by the gate, thus reducing the short channel effects and consequently the leakage currents even for channel length lower than 20 nm. When a second gate is introduced under the silicon film in the buried oxide, this electrostatic control is drastically improved. This last category of device architecture, called double gate MOSFET (DGMOS), offers serious advantages in term of electrical performance. In addition, when both gates can be independently driven, this device architecture opens new perspectives in term of innovative circuit design. This technology involves a rupture for designers. This book describes this double gate CMOS technology, from the MOS transistor to the circuit design. The goal is to give to the reader an overview on the capabilities offered by this technology. The first chapter presents a state of the art of device performance required for future technology nodes. So, we analyze why multiple gates architectures and in particular double-gate devices appear to be excellent candidates for the sub-32 nm technology nodes. The physical behavior of double gate MOSFET is more developed in the second chapter where physical modeling of this device architecture is presented. As noted previously, double gate transistor with independent gates offers new design opportunities. To optimize circuit design and to develop new circuit architectures, a compact model is needed. In Chapter 3, we expose a threshold-voltage based compact model of double gate transistors with independent gates. To complete these three chapters, the low-frequency noise characteristics are detailed in the Chapter 4. Finally, the three last chapters are focusing on circuit designs using double gate CMOS technology. We present the advantages and the drawback in term of leakage optimization and functionality for analog, digital and SRAM designs.

Reference 1. International Technology Roadmap for Semiconductors, 2007 edition, http://www.itrs.net

Chapter 1

Multiple Gate Technologies Thierry Poiroux, Maud Vinet, and Simon Deleonibus

1.1 Introduction For several decades, the continuous performance improvement that made the success of semiconductor industry relies on the dimension downscaling of the basic component of integrated circuits, the Metal Oxide Semiconductor Field Effect Transistor (MOSFET), together with the dimension downscaling of interconnects. While the 45 nm technology node is entering in production, the scaling of MOSFETs to the 22 nm technology node and beyond is anticipated by the International Technology Roadmap for Semiconductors [1] as a major near term challenge. According to the ITRS 2007 edition, planar bulk CMOS will require high channel doping in order to maintain acceptable electrostatic control of the channel and will face with increased band-to-band tunnelling, gate induced drain leakage and large variability induced by channel doping level statistical fluctuations. Thus, ultra-thin body single gate (FDSOI) or multiple gate devices with undoped channel are the most promising candidates that can allow MOSFET scaling down to the 10 nmrange and below. The main challenges for these ultra-thin body devices will be the control of the body thickness and its variability, and the optimization of the access regions in order to benefit from the intrinsic device performance. In a longer term, quasi-ballistic operation with enhanced carrier injection velocity at the channel entrance appears to be needed to achieve the required drive current of highly scaled transistors. In the first part of this chapter, we analyze the performance needed at the device level to fulfil the requirements for future technology nodes and we show how multiple gate transistor architectures can surpass conventional single gate devices. From the first studies published on multi-gate devices in the 1980s [2–4], various architectures in which the channel is controlled by two or more gates have been proposed to overcome the electrostatic loss induced by the gate length decrease. Thus, in the T. Poiroux, M. Vinet and S. Deleonibus CEA-LETI Minatec, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France


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following parts, we make a review of the works published on planar and non planar multiple gate MOSFETs, highlighting the advantages and the drawbacks of each approach. The last part is dedicated to multi-channel devices, in which several layers of mono-crystalline semiconductor material are stacked, each layer corresponding to a transistor channel completely surrounded by the gate material.

1.2 Advantages of Multiple Gate Technologies Multiple gate technologies present decisive advantages over conventional ones, from both electrostatics and transport points of view. In this part, we first make an overview of the requirements at the transistor level for future technology nodes. Next, we detail the associated technological challenges, in terms of electrostatic control, variability, gate stack, carrier transport and parasitic resistances in order to highlight the advantages of multiple gate transistors and to point out the specific challenges of these architectures.

1.2.1 Requirements for Future Technology Nodes For logic technologies, one usually distinguishes between several technology options: high performance (HP), low operating power (LOP) and low stand-by power (LSTP). High performance logic corresponds to high complexity integrated circuits that require high clock frequencies and can deal with high power consumption, such as for example microprocessor units for desktop computers. The targeted increase of clock frequency from one technology node to the following can be translated at the device level by an improvement of the intrinsic switching time of the transistor of 17% per year, while maintaining the transistor off-state current to a value acceptable from a power consumption point of view. This intrinsic switching time τ is the time needed by a transistor supplying on-state current to make the gate of an identical transistor switching from the ground to the supply voltage: τ=

CV I

(1.1)

with C the gate capacitance, V the supply voltage and I the on-state current of the device. The most efficient way to increase the performance is to scale aggressively the gate length of the transistor, since it allows reducing the gate capacitance while increasing the on-state current. Low operating power technology option aims relatively high performance mobile applications, such as notebook computers. The key issue is then to increase the circuit performance while reducing as much as possible the power consumption when the circuit is operating. At the device level, a relevant metric of this dynamic power

1 Multiple Gate Technologies

5

consumption is the power-delay product, corresponding to the energy required for a single transistor switch. This power-delay product is simply: Pτ = CV2

(1.2)

with C the gate capacitance and V the supply voltage. The most efficient way to decrease the dynamic power consumption is thus to reduce as far as possible the supply voltage. Finally, low standby power option is used for lower performance, low cost consumer applications, such as cellular phones. For such applications, the main concern is to continue increasing performance while maintaining the power consumption as low as possible when the integrated circuit is idle. At the transistor level, this static power consumption is directly governed by the leakage current of the devices. Thus, this technology option requires very low transistor off-state currents, as well as very low parasitic currents (such as gate leakage). Table 1.1 summarizes the requirements for double gate MOSFETs for future technology nodes, from 32 to 16 nm nodes, estimated by the “Process Integration, Devices, and Structures” team of ITRS. Notice that the frequency improvement is 17% per year for HP option, while it is 14% per year for LOP and LSTP. In order to reach these performances, several technological challenges have to be addressed. First, the transistor electrostatic control must be improved, in order to reach low off-state current and to maintain at the same time a sufficiently high gate overdrive to maximize the on-state current. With that respect, thin film and multiple gate architectures are clearly seen as a relevant alternative to conventional bulk MOSFETs. Second, process-induced and intrinsic device variability need to be minimized in order to enlarge the circuit design window and to ensure high integrated circuit yields. To reduce the parasitic gate leakage current and to continue increasing the gate to channel capacitive coupling, high permittivity dielectrics and metal gates are required whatever the device architecture. In addition, carrier transport boosters, such as process-induced strain, are needed and already implemented to further improve the transistor performance. Finally, to benefit fully from all these improvements, parasitic resistances and capacitances must be reduced. In particular,

Table 1.1 Future technological node requirements, from ITRS 2007 edition Option

High performance

Low operating power

Low standby power

Year

2013

2016

2019

2013

2016

2019

2013

2016

2019

Node (nm) Lgate (nm) EOT (nm) Vdd (V) Ioff (μA/μm) Ion (μA/μm) Rsd (Ω.μm) CV/I (ps)

32 13 0.60 0.90 0.37 2,204 170 0.26

22 9 0.55 0.80 0.44 2,627 155 0.15

16 6 0.50 0.70 0.47 2,768 145 0.10

32 16 0.90 0.60 9.10−3 754 180 0.53

22 11 0.80 0.60 1.10−2 916 170 0.36

16 8 0.70 0.50 3.10−2 900 140 0.24

32 20 1.30 0.85 2.10−5 612 210 0.90

22 14 1.10 0.80 3.10−5 738 200 0.61

16 11 0.90 0.75 3.10−5 895 170 0.41

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series resistance in the channel access regions will play a more and more important role as we reduce the gate length (and consequently the channel resistance). These topics are detailed in the following sections.

1.2.2 MOSFET Electrostatics Control The bi- or tri-dimensional nature of the MOSFETs is characterized from an electrostatic point of view by the so-called short channel effects, including threshold voltage roll-off (threshold voltage dependence with the gate length at low drain voltage), drain induced barrier lowering (threshold voltage dependence with the drain bias), and sub-threshold slope degradation. The origin of these short channel effects is the electrostatic effect of the source/drain electrodes on the channel. Therefore, in order to improve the electrostatic integrity of a transistor, one has to increase the gate to channel capacitive coupling with respect to the source/drain to channel coupling. A metric of the transistor integrity is thus given by the ratio CGC /(CGC + CDC + CSC + CBC ), where CGC , CDC , CSC and CBC are respectively the gate, drain, source and bulk to channel capacitances. To ensure a good electrostatic control of the channel, planar bulk MOSFET technologies require high channel doping levels, together with additional localized pocket implanted regions, in order to limit the penetration of the electrical fields from the source and drain junctions in the channel. This will lead to large band to band tunneling current across the source/channel and drain/channel junctions and to large gate-induced drain leakage (GIDL), these parasitic current components being detrimental for the static power consumption. In addition, ultra-shallow source/drain junctions will be required to reduce the source/drain to channel capacitance, which will tend to increase the access resistance to the channel. Thus, it is foreseen that bulk MOSFETs will reach their limits in terms of electrostatic control for gate lengths of about 25 nm. Then, thin film fully depleted SOI (FDSOI) will be needed to further scale down the transistors. In FDSOI architecture, the channel is defined in a very thin silicon film, separated from the bulk silicon substrate by an insulating layer, called buried oxide (BOX). The first advantage of this kind of architecture lies in its ideal long channel subthreshold slope. Indeed, for long channel devices, the sub-threshold slope, which is the gate voltage excursion required to increase the drain current by one decade in the weak inversion regime, results from the voltage sharing between the gate dielectrics and the depletion region of the transistor. It is expressed as: Cdep kT S= (1.3) ln(10) 1 + q Cox where k is the Boltzmann constant, q the elementary charge, T the temperature, Cdep and Cox the depletion and the gate oxide capacitances, respectively.


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While in bulk MOSFETs, the depletion capacitance is about one third of the gate capacitance, leading to typical sub-threshold values of 80 mV/dec, the depletion charge in thin film devices is simply the product of the channel doping times the film thickness. This charge is thus independent from the gate voltage and, consequently, the depletion capacitance Cdep is null, which gives an ideal sub-threshold swing of 60 mV/dec at room temperature. In addition, the use of a thin silicon active film allows a significant reduction of the capacitive coupling between the source/drain electrodes and the channel. Short channel effects are then mainly controlled by adjusting first the thickness of the silicon film, and second the gate dielectric thickness. That way, very good MOSFET electrostatic control (DIBL below 100 mV/V and sub-threshold swing below 80 mV/dec) can be achieved when the ratio between the channel length and the film thickness ratio (Lch /tSi ) is larger than 4 [5, 6]. Nevertheless, in such devices, the buried insulator thickness plays a significant role on the electrostatic control. Indeed, electrical fields generated by the drain in the buried oxide are curved into this BOX and take part to the potential barrier lowering at the channel entrance. This fringing field effect can have a significant contribution to the DIBL and to the sub-threshold swing degradation in very short transistors [7, 8]. This effect can be reduced by using very thin buried insulator layers. However, this may not be sufficient, since the fringing fields can go through the depleted region of the substrate beneath the BOX if the substrate surface is left undoped. Thus, a way to further reduce the fringing field effect is to use a metallic or a heavily doped layer at the substrate surface. In that case, the fringing fields vanish in this conductive layer, called ground-plane. If the buried oxide thickness is reduced to that of the gate dielectrics, and if the ground plane is electrically connected to the transistor gate, then the ground plane acts as a second gate. The gate to channel coupling is thus doubled, leading to a significant improvement of the electrostatic control of the device. This configuration corresponds to the double gate concept, introduced in the 1980s by Balestra et al. [4]. In that case, the minimum ratio Lch /tSi required to keep a correct control of the transistor by the gate is reduced from 4 for single gate devices to about 2 for double gate. One can also design device architecture in which the channel is controlled on three sides, or ultimately, with a channel completely surrounded by the gate. In order to estimate the scaling potential of the device architectures, characteristic scale lengths can be derived from Poisson equation and boundary conditions for these different transistor architectures. The following table summarizes the scale lengths obtained for undoped channel single gate FDSOI, double gate and surrounding channel MOSFETs [9–12] (Table 1.2). The indicated channel length is the minimum length that ensures a DIBL lower than 100 mV/V with a film thickness (tSi ) of 5 nm and an equivalent oxide thickness (EOT) of 0.8 nm. This value, which is approximately 4.4λ , is obtained from an analytical calculation of the DIBL, which scales roughly as exp(−L/(2λ )). It should be noticed that in the case of low-doped channel devices, the subthreshold conduction is located in the middle of the film. Thus, reducing the film thickness leads also to an increase of the gate to channel capacitance, making the film thickness more influent on electrostatics than the gate dielectric thickness.

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Table 1.2 Characteristic scale length for thin film transistor architectures (From [9–12]) Device architecture

Scale length

Single gate FDSOI

λ=

Double gate

λ=

Surrounding channel

λ=

εSi εox tSi εSi tSi εox 2 εSi tSi εox 4

Minimum channel length for tSi = 5 nm, EOT = 0.8 nm tox + εεox Si

tox + εεox

tSi 2

tSi Si 4

tSi 2

22 nm 13 nm

ln 1 + 2tt ox + εεox Si

tSi Si 4

9 nm

By designing slightly underlaped devices (i.e. with a channel length larger than the gate length thanks to the patterning of offset spacers before extension implantation step), multiple gate architectures allow scaling the gate dimension down to the sub-10 nm range.

1.2.3 Variability Regarding the numbers of published papers on variability (∼15% of the Symposium on VLSI Technology 2007), it is obvious that dealing with fluctuations of electric characteristics of MOS transistors have become a major critical point for sub-65 nm technologies. The MOS transistor performance is particularly sensitive to variations of gate length, oxide thickness, or to the random variations in the number of dopants. These variations arise either from the process and/or from the discrete nature of the matter. The reason why dealing with variations is now considered as a current difficult challenge [1] is linked to the gate length: variation of 1 nm on the gate length of 20 nm has a significant impact on the variations of the threshold voltage, the conduction current and leakage current whereas it was negligible on a transistor with a gate length of 0.1 μm. Thin film architectures such as multiple gate devices are expected to be very competitive with respect to variability because of their undoped channel. Indeed channel doping dispersion in bulk is significant problem: current channel doping level is in the order of 5.1018 cm−3 , the simulations of random distributions of dopants show that the number of dopants in a cube of (20 nm)3 differ by a factor of 2, between 24 and 56 [13]. This dispersion dramatically affects the electrical characteristics of the transistor, for resulting standard deviation on threshold voltage is about 40 mV for a 20 nm gate length MOSFET. Currently, solutions to take into account these dispersions on bulk silicon rely on developments at the system architecture and the circuit design levels. This leads to worst case designs, where circuits are oversized and thus performance, consumption and density are degraded.


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Table 1.3 Comparison on the dispersion source between multiple gate and bulk architectures Conventional architectures

Multiple gate architectures

Channel Gate material

Channel doping Gate doping

Gate dielectric

Oxide thickness

Silicon thickness Gate workfunction Induced strain Dielectric charges

In undoped channel architectures, the fluctuation on the dopant number is replaced by dispersion on silicon thickness. This dispersion is of a new type: first it is a long-scale dispersion and, second, it is nowadays limited by technological issues (CMP dispersion). SOI suppliers tend to increase the silicon thickness uniformity [14]. Table 1.3 compares the sources of dispersions for multi-gate and bulk architecture. Some of them are quite new and emerged with the scaling of the gate length. For instance the polysilicon gate was replaced by a metal gate and the way to deal with this new type of dispersions has to be found. Note that this table is not exhaustive since the change in architecture is also accompanied by other changes in the manufacturing process, for example in terms of isolation (MESA for SOI, STI for bulk, which will involve changes in the dispersion on the active width) and the realization of source and drain. As a conclusion, in spite of the few results on variability in multiple gate architectures, promising results have already been shown [15, 16] which confirm that mismatch can be decreased thanks to the use of undoped channels. In addition, the suppression of halos and pockets is thin film architectures is another key point for decreasing the mismatch.

1.2.4 Gate Stack With the need to decrease the equivalent gate oxide thickness in the nanometer range, conventional nitrided silicon dioxide leads to unacceptable gate leakage currents [1]. Thus, in order to further increase the gate to channel capacitive coupling while maintaining low gate leakage currents, high permittivity dielectrics have been introduced. Materials such as hafnium based dielectrics are widely studied, since they exhibit dielectric permittivity four to six times larger than conventional silicon dioxide, and sufficiently wide energy gaps to ensure large barrier potentials for electrons and holes. With the use of hafnium dioxide, a reduction of the gate leakage of three to four decades with respect to silicon dioxide can be achieved at a given equivalent oxide thickness (i.e. at a given gate to channel coupling) [17]. Hafnium based oxide are already in production in the most advanced high performance technologies (45 nm node) [18].

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Furthermore, with the heavily doped polysilicon gates used until now, the depleted region formed at the bottom of the gate when the device is biased in strong inversion leads to a capacitance in series with the gate dielectric capacitance. This effect, known as poly depletion, can be translated from an electrostatic point of view in an increase of the apparent oxide thickness. Since the depleted layer thickness is typically about one nanometer, it increases the electrical equivalent thickness by three to four angstroms. This component can thus no longer be neglected, as the gate dielectrics thickness is scaled down to the sub-nanometer range. To get rid of this detrimental effect, metal gates are introduced in novel technologies together with the high permittivity dielectrics [18]. On bulk silicon, the transistor threshold voltage is given by both the gate workfunction and the channel doping level. N+ and P+-like metal gates are required for n- and p-MOSFETs respectively. In case of thin film and multiple gate technologies, the devices are designed with a very thin active area. The use of polysilicon gates would lead to unacceptable channel doping levels, higher than 1019 cm−3 , in order to get appropriate threshold voltages. These devices have thus also to be designed with metal gates and can benefit from the enhanced transport properties of low doped channels, their threshold voltage being adjusted thanks to appropriate gate workfunctions. In case of a low doped thin film channel double gate transistor, the threshold voltage is given approximately by [19]: 2Cox kT k. h¯ 2 π2 Vth = Δφmi + ln (1.4) + q q2 ni tSi 2qm⊥ t2Si where Δφmi represents the gate workfunction with respect to that of intrinsic silicon, k is the Boltzmann constant, T the temperature, Cox the gate oxide capacitance per surface unit, q the elementary charge, ni the carrier concentration of intrinsic silicon, h¯ the reduced Planck constant and m⊥ the carrier confinement mass in the transverse direction. The last term of the previous equation is due to the confinement induced by the quantum well formed by the thin silicon layer between the gate dielectrics and the buried oxide. It becomes significant for film thickness below 5–7 nm. Since the logarithmic term is typically between 0.46 and 0.5 V for an equivalent oxide thickness (EOT) of 1 nm and a silicon film thickness in the 5–15 nm range, one can estimate the gate workfunctions required for thin film devices for the sub-32 nm nodes (Table 1.4). Table 1.4 Gate workfunctions required for the different technology options with fully-depleted and multiple gate devices Technology option High performance Low operating power Low stand-by power

nMOSFET range

pMOSFET range

4.4–4.5 eV 4.5–4.6 eV 4.7–4.8 eV

4.7–4.8 eV 4.6–4.7 eV 4.4–4.5 eV


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It should be noticed that the threshold voltage of undoped channel thin film transistors is independent from the channel doping level. This is true as long as the depletion charge plays insignificantly on electrostatics in the channel. With an EOT of 1 nm and a film thickness around 5–10 nm, this condition is verified for channel doping levels lower than a few 1017 cm−3 .

1.2.5 Carrier Transport As explained above, thin film devices can be designed with undoped channels. They can thus benefit from high mobilities since the carrier interactions with channel impurities are suppressed. Furthermore, the mobility at a given inversion charge is increased on fully-depleted devices with respect to bulk, because fully-depleted transistors operate at lower transverse electric field. Indeed, the transverse effective field is given by: η Qinv + Qdep Eeff = (1.5) εSi with Qinv and Qdep the inversion and depletion charges respectively, εSi the permittivity of silicon, and with η ≈ 1/2 and 1/3 respectively for electrons and holes. While the depletion component is as high as 0.5 MV/cm in a bulk device with a 1018 cm−3 doping level, it is negligible in the case of low doped fully-depleted transistor. The effective field range in strong inversion regime is then reduced from 0.6–1.5 MV/cm for bulk device to 0.1–1.0 MV/cm for fully-depleted. Furthermore, in multiple gate MOSFETs, the drain current per layout width unit is roughly multiplied by the number of gates. This can not be translated in an equivalent decrease of the CV/I, since the gate capacitance is also multiplied by the same number. However, taking into account the extrinsic capacitances that have to be loaded by the transistors in a real circuit (in particular interconnect capacitances), the increase of drain current in multiple gate transistors leads to an overall circuit performance improvement. In addition, if we take into account the better electrostatic control of the device, the gate overdrive at a given off-state current can be increased with respect to that of single gate transistor for the same supply voltage, leading to a further performance improvement [20]. To maximize the performance in current technologies, carrier transport boosters such as process or substrate-induced strained channel are implemented [21]. These strain techniques have also shown their efficiency in thin film and multiple gate devices [22–24].

1.2.6 Series Resistances In order to fully benefit from the expected performance of the coming technology nodes, all the parasitic components have to be reduced as much as possible. In particular, the resistance in series with the transistor channel will have to be

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Total and series resistance (W.mm)

300 250 200 Total resistance

150 100 50 0 2011

Source+drain series resistance

2012

2013

2014

2015 2016 Year

2017

2018

2019

2020

Fig. 1.1 Total and series device resistance required to reach the ITRS high performance specifications

drastically decreased as we will reduce the channel length. Indeed, to reach the high performance ITRS predictions in terms of on-state current, the total source to drain resistance will have to be decreased to values of about 100–150 Ω.μm. This will be possible only with series source plus drain resistance well below 100 Ω.μm (Fig. 1.1). This point is particularly crucial for thin film devices, where a significant contribution of the access resistance comes from the thin silicon film extension region. Thus, dopant implantation and activation in these extension regions has to be carefully optimized, in order to have very low sheet resistance and to avoid a complete amorphization of the film during the implantation step [6]. In addition, selective epitaxial growth of silicon or SiGe in the source/drain region is mandatory in order to perform the salicidation of the source/drain electrodes. The thermal budget during this epitaxial growth process has to be lowered as much as possible, since thin silicon films are very sensitive to high temperature treatments. In particular, an epitaxy pre-annealing step at a too high temperature can lead to an agglomeration of the silicon film into solid droplets. Here again, multiple gate devices present an advantage over single gate transistors, since the film thickness can be relaxed to achieve the same electrostatic control. In a longer term, metallic source and drain can be an alternative to conventional silicon electrodes to further reduce the series resistance [25–27].

1.3 Planar Double Gate Technologies Several technological approaches can be followed to design multiple gate MOSFETs. The various proposed architectures differ mainly by the number of gates and by the orientation of the conduction channel. We can define three main types of


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multiple gate devices: planar transistors, in which the gates and the channel are horizontal, FinFETs, in which the channel is vertical and the conduction is parallel to the wafer surface and the vertical transistors, in which the conduction direction is vertical. While these architectures behave quite similarly in terms of electrostatic control, the process integration sequences are significantly different one from the other, each with advantages and drawbacks. This part is dedicated to planar double gate approaches, which can be considered as the logic extension of SOI technologies. Indeed, fully depleted SOI transistors have a natural double gate structure, since the buried oxide and the substrate can be used respectively as a second gate dielectrics and gate electrode [28]. The main ways followed for the fabrication of planar double gate devices are based on the successive deposition of the layers constituting the double gate stack, on the use of wafer to wafer bonding or on the fabrication of a suspended channel, subsequently surrounded by the gate.

1.3.1 Double Gate Transistors by Layer Deposition Several approaches have been proposed in order to fabricate planar double gate transistors by the successive deposition of the back gate stack, the channel and the front gate stack. The major issue of these approaches is to obtain by deposition a channel with a high crystalline quality. In [29], the lateral epitaxial regrowth of the channel layer is performed after the back gate patterning from a cavity opened to access the substrate. The front gate is then deposited and patterned and the source/drain electrodes are implanted with the front gate as hard mask. Another approach, base on the lateral recrystallization of amorphous silicon, allows a self-aligned double gate with independent gates [30]. On an oxidized bulk silicon substrate, the back gate stack and a nitride layer are deposited. This stack is then patterned down to the buried oxide to define the back gate and amorphous silicon is deposited and planarized with a stop over the nitride layer. This amorphous silicon is at this stage in the source/drain areas. After the removal of the nitride, a thin amorphous layer of silicon is deposited and recrystallized thanks to a Metal Induced Lateral Crystallization (MILC) process. Then, the front gate stack is deposited and planarized in a Damascene way. Both approaches have been demonstrated on long channel devices only (in the micrometer range), and suffer from the poor crystalline quality of the channel.

1.3.2 Non Self-aligned Transistors by Wafer Bonding The idea of using wafer bonding for the fabrication of double gate transistors comes from the need to have a mono-crystalline layer of excellent quality for the channel.

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To achieve this goal, the non self-aligned architecture by wafer bonding is one the most straightforward approach to integrate planar double gate MOSFETs [31]. To fabricate such devices, a first gate stack is deposited onto a SOI wafer in which active areas have been previously patterned. After the first gate etching and encapsulation by planarized dielectrics, the wafers are bonded on handling substrates and the silicon substrate and the buried oxide of the initial SOI wafers are removed selectively with respect to the thin silicon active film. Then, the second gate stack is deposited and etched, the second gate lithography being aligned to the first gate patterns. To achieve a good alignment, alignment marks used for the first gate can be regenerated after wafer bonding in such a way that the same marks can be used for both gate lithography steps. Indeed, the success of this approach relies on the lithography capability to align very short gates one to the other. After the second gate patterning, the process follows a standard FDSOI process, with extension implant, spacer patterning and epitaxial growth of elevated source/ drain. Fig. 1.2 shows a 10 nm non self-aligned planar double gate transistor fabricated that way. Notice that a quasi-perfect gate alignment can be achieved, with an accuracy of a few nanometers [31]. An advantage of this approach is to allow separated electrical contacts to the two gates without any additional process step. Indeed, as the gates are designed in a non self-aligned way, the contact pads for the front and for the back gate can be designed in distinct locations, allowing the contact opening on both gates during the same etching process step. While very good performances have been demonstrated with that kind of approach, the gate misalignment remains a source of performance fluctuation. In order to fabricate transistors that are tolerant to misalignment, slightly oversized back gates can be patterned. In that case, a compromise has to be found between

Salicided elevated source/drain

TiN Back gate

Fig. 1.2 TEM cross-section of a 10 nm planar bonded double gate transistor with TiN metal gates

6nm thick mono-Si channel

Front gate


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tolerance to process fluctuations and intrinsic switching speed of the device, since oversized back gates induce extra capacitance to be loaded [32].

1.3.3 Self-aligned Transistors by Wafer Bonding To overcome this particular issue, several approaches have been proposed to fabricate self-aligned planar double gate MOSFETs. In the PAGODA architecture [33], the unpatterned back gate stack is deposited and encapsulated before wafer bonding. After initial substrate removal, the front gate is patterned and encapsulated with oxide spacers. Then, a polysilicon layer is deposited and etched to form silicon spacers besides the top gate. These spacers are recrystallized from the channel and salicided. This silicide layer is then used as a hard-mask for back gate etching and undercut. The process flow of the Super Self-aligned Double Gate architecture (SSDG) [34] starts also from back gate stack deposition and wafer bonding. The whole stack, comprising the front gate, the channel and the back gate is then etched anisotropically. Insulated layers are formed besides the gates by use of oxidation rate difference between the gate (poly-crystalline) and the channel (mono-crystalline) materials. Source/drain regions are then regenerated by lateral epitaxial regrowth from the channel edges. The key technological issues of these planar architectures are the precise controls of the back gate dimension, since the back gate is not directly accessible from the top of the wafer, and the realization of high quality source/drain electrodes to reduce as much as possible the parasitic resistances. To ensure the same dimension for both gates when going to very aggressive gate dimensions, one has to use the top gate as a hard mask for the back gate patterning, as shown in [35], and to limit as much as possible the gate size reduction process, required to isolate electrically the gates from the subsequently fabricated source/drain electrodes. The gates electrical separation can be obtained either by using an additional lithography step before back gate etching, in order to design a specific contact pad for the back gate, or by removing the front gate material from the area reserved to connect the back gate before the contact process steps. Up to now, no demonstration of ultra-short double gate MOSFETs fabricated that way has been shown. The minimum gate length demonstrated today with such self-aligned processes is 250 nm with the PAGODA approach [33].

1.3.4 Suspended Channel Based Approaches An alternative to wafer bonding, allowing also keeping an excellent mono-crystalline semiconductor layer for the channel is to etch a tunnel below the crystalline surface layer of a substrate and to fill this tunnel with a buried gate. This approach requires

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the presence of a layer below the channel layer that can be removed with a very high selectivity. The very first double gate MOSFET was fabricated by patterning a narrow silicon active area on a SOI substrate, etching chemically a localized cavity under this active area into the buried oxide, and filling it by the gate material [36]. After gate patterning, the silicon active area was surrounded by the gate. This first demonstration allowed the fabrication of functional long channel transistors. More recently, a gate-all-around (GAA) architecture, based on the silicon-onnothing (SON) process [37], has been proposed [38]. This GAA-SON approach starts from bulk silicon substrates and relies on successive epitaxial growth of cristalline SiGe and Si layers. After the formation of a Shallow Trench Isolation (STI), the SiGe layer is selectively grown and a non selective epitaxial growth of silicon is performed. The SiGe layer is then selectively etched to form a tunnel below the silicon film. During the gate stack conformal deposition, the tunnel is filled by the gate material, which results in a channel completely surrounded by the gate. A very high selectivity of the SiGe layer etching with respect to silicon is required in order to avoid any channel consumption, which would induce variations in the film thickness between the edge and the center of the structure. This approach has been further improved to ensure the same dimension of the gate above and below the channel. It has been shown that excellent device performance can be achieved that way down to 30 nm gate lengths with transistors incorporating high-k gate dielectrics and metal gate [39]. In these processes, the electrical separation of the gates is more difficult to achieve than in wafer bonding based technologies, since the gate material surrounds completely the channel. It would require additional process steps to remove the gate material from the lateral edges of the channel and to take the contacts on both gates.

1.4 Non Planar Multiple Gate Technologies Double gate behavior can also be achieved by etching very narrow silicon membranes to form the channel and by patterning a gate that controls the channel from both sides of this membrane [3]. These devices, called FinFETs because of the finlike shape of the silicon membrane, are the most studied multiple gate architecture, since their fabrication process is very close to that of conventional transistor. They require the patterning of high aspect ratio fins, in order to ensure a good layout density. If the fin height is comparable to its width, a gate control can be obtained on three sides of the channel. Depending on the exact shape of the gate, these devices are called Trigate [40], Π-gate [41] or Ω-FETs [42, 43]. Ultimately, the best electrostatic control is obtained with a cylindrical channel completely surrounded by the gate [44].


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Fig. 1.3 Schematic of a FinFET

Drain Drain Gate Gate Fin

Source

1.4.1 FinFET Devices The first implementation of FinFET devices has been published at the end of the 1980s, by D. Hisamoto et al. [3]. This transistor was initially named DELTA (fully DEpleted Lean-channel TrAnsistor) and has been renamed FinFET in 1999 [45] (Fig. 1.3). The fabrication process is the following. Starting from an SOI wafer, very narrow silicon membranes are etched. Then, the gate stack is deposited and patterned on this topology. After spacer formation, selective epitaxial growth of silicon on the extension and source/drain areas is performed in order to reduce as much as possible the series resistances. These extension and source/drain electrode regions are then implanted and silicided. As for FDSOI and planar double gate architectures, the channel can be left undoped, the threshold voltage being adjusted by choosing the appropriate metal for the gate material. The height of this fin will be at the end the electrical width of the device. Indeed, contrary to planar devices, the conduction takes place on the vertical sidewalls of the fin. The conduction width is thus twice the fin height (hfin ). As the fin height is limited to typically 50–100 nm, FinFETs are usually designed as multifinger transistors, with a conduction width quantified by 2hfin . The impact of this width quantization on the circuit design flexibility has to be accounted for. Furthermore, in order to reach high layout density, the ratio between the fin height and the achievable pitch between two successive fins has to be maximized. In particular, the fin height has to be higher than the pitch between the fingers in order to obtain the same drive current per silicon area as planar double gate transistors. To improve this ratio with respect to the pitch achievable by lithography, the use of spacers as hard-mask for the fin patterning can be used. That way, the fin density can be doubled [46]. The other key technological issue is to obtain ultra-narrow fins, with a very good control of its width and shape and with a very low dispersion. By using a combination of 193 nm immersion lithography together with dry and wet etching steps, well controlled fin widths down to 5 nm can be achieved [47]. Since the conduction takes

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place on the vertical sidewalls of the fin, the interface quality has to be very good to ensure high carrier mobility. To improve this interface quality, a sacrificial oxidation of the silicon fin can be carried out [48]. Finally, it should be mentioned that FinFETs can be designed with two independent gates. To obtain this gate separation, one can remove the gate material at the top of the fin by chemical-mechanical polishing with a stop over the hard mask used to pattern the fins [49]. Asymmetrical FinFETs have also been demonstrated in order to adjust the threshold voltage excursion [50].

1.4.2 Trigate Transistors Another approach consists in designing the fin with roughly a square cross-section (Fig. 1.4). In that case, the channel is controlled by the gate on three sides. This device, called Trigate [40], has a conduction width given by twice the fin height plus the fin width. Trigate is still a multifinger device, and the pitch between fins has to be lower than hfin + wfin /2 to obtain higher drive currents per silicon area than with planar devices. This limit is far more strict for Trigate than for FinFET, since the fin height must be as low as the fin width in order to operate in trigate mode, and comparable to the gate length to benefit from a good electrostatic channel control. To further improve the electrostatic control of the channel, the buried oxide can be slightly etched during the fin patterning. In that case, the gate material is also deposited below the bottom face of the channel and the electrostatic control of this back interface can be improved, thanks to the electrical fields generated by the gate. These devices are called Π-Gate transistors (Fig. 1.5, left), or Ω-FETs when the buried oxide is undercut (Fig. 1.5, right). Ω-FET and Π-Gate architectures are very similar to Trigate, but their channel control is close to that of a quadruple-gate device [5].

Drain Drain

Gate Gate

Source Source

Fig. 1.4 Schematic of a Trigate transistor


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Gate

Gate Gate

Fin

Fin

Buried oxide

Buried oxide

Fig. 1.5 Schematic cross-section of a Π-Gate (left) and a Ω-FET (right)

Drain

Gate

Source

Fig. 1.6 Schematic of a cylindrical surrounding-gate device

1.4.3 Surrounding Gate Transistors Finally, the best electrostatic control is achieved with a cylindrical channel completely surrounded by the gate (Fig. 1.6). The most advanced practical realization of such a device is the 5 nm gate length nanowire-FET [44]. The key technological points in the fabrication of such a transistor are the definition of the wire, which requires a very aggressive lithography and the use of silicon surface smoothing techniques, such as high temperature hydrogen annealing, and the patterning of the gates, which requires a isotropic etching step in order to remove the gate material below the extension regions. For all these non planar multiple gate technologies, the fin and the gate are patterned with two different lithography steps. In other words, the gate is not selfaligned with the source/drain electrodes. Thus, the channel is accessed through a narrow fin region, which length is given by the lithography alignment capabilities. An epitaxial regrowth of silicon of these access regions is mandatory to allow their salicidation and to limit the access resistance. Notice that Trigate, Π-Gate, Ω-FET and surrounding gate transistor can have only one gate electrode. Contrary to planar and to FinFET technologies, they do not offer a two separated gates option.

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1.5 Conclusions and Perspectives Thin film and, further, multiple gate transistor architectures are expected to be required for the 32 nm or the 22 nm technology node, mainly because they provide a much better electrostatic control than conventional bulk silicon devices. From a technical point of view, these architectures are scalable down to the sub-10 nm gate length range, as already demonstrated by some prototypes. To achieve this goal, the channel thickness (for planar approaches) or the fin width (for non planar architectures) will have to be decreased down to about 5 nm, in a very well controlled way to avoid any significant variability induced by some width or thickness dispersion. FinFET architecture is the most studied and the most mature of all the multiple gate technologies, with some demonstrations of highly performing SRAM cells and ring oscillators [51]. However, from a scalability point of view, the dispersion on the fin width that can be expected from the anticipated progress in lithography and etching in the coming years should be higher than the dispersion on the film thickness in planar approaches, fabricated either by wafer bonding (in that case, the film thickness dispersion is that of the initial substrate) or by the GAA-SON technology (in that case, the film thickness is defined by epitaxial growth). From a circuit design point of view, both planar and FinFET technologies can offer a gate electrical separation option, which allows benefiting from an additional degree of freedom for power saving concern or analog design. Furthermore, some planar technologies such as the GAA-SON approach give the opportunity to fabricate multiple gate devices with several stacked channels. These devices, called multi-channel transistors [52] or MBCFET (for Multi-Bridge Channel MOSFET) [53], exhibit outstanding drive current per layout width unit (more than 3.4 mA/μm at a supply voltage of 1.0 V demonstrated in [54]) together with very low sub-threshold leakage currents, thanks to their multi-gate electrostatics control. 122 Mb high speed SRAM cells have already been demonstrated with 25 nm gate length MBCFETs [54]. In a longer term, the advantages of the multi-channel technology can be further improved by combining the multi-channel and the FinFET processes. That way, matrices of nanowires completely surrounded by the gate can be envisaged between the source and drain electrodes, as demonstrated in [55]. This will constitute the ultimate integration of silicon based devices in terms of electrostatics control and current drivability. By incorporating insulators between the nanowire layers, devices with two independent gates can be fabricated [56].

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GAA (NBG) FinFETs with HfO2/TiN gate stack”, in Technical Digest of IEEE International Electron Device Meeting, pp. 997–1000, San Francisco, CA, December 2006. 56. C. Dupre, T. Ernst, C. Arvet, F. Aussenac, S. Deleonibus and G. Ghibaudo, “Stacked Nanowires ΦFET with Independent Gates: A Novel Device for Ultra-dense Low-Power Applications”, in Proceedings of IEEE International SOI Conference, pp. 95–96, Indian Wells, CA, October 2007.

Chapter 2

Compact Modeling of Independent Double-Gate MOSFET: A Physical Approach Daniela Munteanu and Jean-Luc Autran

2.1 Introduction The bulk MOSFET scaling has recently encountered significant limitations, mainly related to the gate oxide (SiO2 ) leakage currents [1, 2], the large increase of parasitic short channel effects (SCEs) and the dramatic mobility reduction [3, 4] (due to highly doped Silicon channels precisely used to reduce these short channel effects). Technological solutions have been proposed in order to continue to use the “bulk solution” until the 32 nm ITRS node. Most of these solutions envisage the introduction of high-permittivity gate dielectric stacks (to reduce the gate leakage, [2, 5, 6]), midgap metal gate (to suppress the Silicon gate polydepletioninduced parasitic capacitances) and strained materials-based channel (to increase carrier mobility [7–9]). In parallel to these efforts, alternative solutions to replace the conventional bulk architecture have been proposed and studied in the recent literature, such as the introduction of new device architecture (e.g. multiple-gate devices, Silicon nanowires MOSFET). Ultra-thin film body Double-Gate (DG) structures become to be envisaged as a possible alternative to the conventional devices, due to its enormous potentiality to push back the integration limits to which conventional bulk transistor are subjected [10–13]. The main advantage of this architecture is to offer a reinforced electrostatic coupling between the conduction channel and the gate electrode. In other terms, a double-gate structure can efficiently sandwich (and thus very well control, electrostatically speaking) the semiconductor element playing the role of the transistor channel, which can be a Silicon thin layer or nanowire. In this way, Double-Gate devices could be designed with intrinsic channels, offering then an enhanced mobility, the elimination of doping fluctuations and a high probability of ballistic transport. Further, for the symmetrical DG device, the condition of “volume inversion” [14] can be beneficial with regard to carrier mobility and sourcedrain transport. In spite of excellent electrical performances due to its multiple D. Munteanu and J.-L. Autran IM2NP-CNRS, 49 rue Joliot Curie, BP 146, 13384 Marseille Cedex 13, France


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conduction surfaces, conventional DG MOSFET allows only three-terminal operation because the two gates are tied together. DG structures with independent gates have been recently proposed [15–19], allowing a four terminal operation. Independent Double-Gate (IDG) MOSFETs offer additional potentialities, such as a dynamic threshold voltage control by one of the two gates and transconductance modulation in addition to the conventional switching operation [15, 16]. Although the operation of DG transistor is similar to the conventional MOSFET, the physics of DG and IDG MOSFETs is more complicated. Moreover, physical phenomena such as 2D electrostatics or carrier quantum confinement have to be considered, since these structures will be precisely used to design very integrated devices (with short channels and ultra thin films). Therefore, new compact models, dedicated to circuit simulation, have to be developed for DG and IDG MOSFETs. Nanoscale DG and IDG MOSFETs introduce challenges to compact modeling associated with the enhanced coupling between the electrodes (source, drain, and gates), quantum confinement, ballistic or quasi-ballistic transport, gate tunneling current, etc. [20]. In the case of IDG MOSFET, the modeling task is even more difficult due to the influence of the second gate which can be independently switched. For DG MOSFET devices, drain current compact models can in general be surface potential or charge based. Most models presented to date are developed for undoped devices with a long enough channel to assume that the transport is mainly governed by the drift-diffusion mechanism [21–30]. Regarding the modeling of the electrostatics, most of the work has been based on solving one-dimensional (1-D) Poisson’s equation perpendicular to the gates, thereby neglecting SCEs. For example, Taur [21,22] developed a framework of two equations to describe the electrostatic potential in the Silicon film of the DG MOSFET. Charge-based drain–current models have been developed by He et al. [27] and Sallese et al. [28] to avoid the numerical solution of the transcendental equation used in the surface potential-based models. Recently, a unified model for DG MOSFETs was derived by Taur et al. [23] based on the Pao– Sah’s integral [31]. Ortiz-Conde et al. [24,29] have also proposed a surface potential based drain–current model for DG MOSFETs, which was an extension of their previously proposed Lambert function based analytic solution for the surface potential of single-gate undoped-body bulk devices [32]. These models considered the classical (i.e. without quantum effects) drain current in long channels (i.e. neglecting SCE) DG MOSFETs. However SCE is an important issue for these ultra-scaled devices. Liang and Taur proposed in [33] a drain current model for short channel DG MOSFETs, but this model only applies in subthreshold regime, where the assumption of a negligible mobile-charge sheet density can be used for simplifying the solving of the two-dimensional (2-D) Poisson’s equation. A conventional technique used to take into account SCE is to add the SCEs as a second-order correction using fitting parameters. An alternative solution is the technique based on conformal mapping for obtaining analytical solutions of the 2-D Poisson’s equation, whereby the SCEs are inherently included without the need of additional fitting parameters [34–38]. Advanced physical effects, such as quantization effects and velocity overshoot, have to be taken into account in short-channel DG MOSFET. These effects have

2 Compact Modeling of Independent Double-Gate MOSFET: A Physical Approach

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been considered for the first time by Baccarani and Regianni in [39]. In DG MOSFET the use of ultra-thin channels (typically thinner than 10 nm) implies the existence of important quantum-mechanical confinement effects. This phenomenon lowers the net sheet charge of carriers in the inversion layer and leads to an increase of the threshold voltage of a DG MOSFET. The gate capacitance and carrier mobility are also modified by quantum effects. In [40] Munteanu et al. developed a continuous compact model for the drain current, including short-channel effects and carrier quantization in DG MOSFET. This model has been validated by comparison with 2-D quantum numerical results. The model was also shown to reproduce with an excellent accuracy experimental drain current in Double-Gate devices. For channel lengths shorter than 50 nm, the ballistic/quasi-ballistic character of the transport is expected to become important. A few compact models of ballistic transport have been published for nanoscale DG MOSFETs [41–45]. The sourceto-drain current is usually given by the difference of the fluxes injected from the source and from the drain at the location of the maximum of the energy barrier [41, 42]. Above a certain channel length, backscattering may affect the transport, which therefore cannot be considered as purely ballistic anymore. Reflections of carriers after crossing the barrier may take place within a certain length. In this case, the transport is quasi-ballistic and these reflections can be included in a compact model of the ballistic current by using a backscattering coefficient [43]. Very little work has been done on the transition from the ballistic regime to drift diffusion [46–48]. For very short-channel devices, the quantum tunneling of carriers through the source-to-drain barrier should be added to the ballistic current due to thermionic emission [45]. The case of asymmetric DG or IDG MOSFET is more general and more complex. Several papers have addressed the compact modeling of potential and drain current in asymmetric DG devices [49,50]. For example, Lu and Taur [49] analyzed the DG MOSFETs having asymmetry arising from the different flat-band voltages at the two gates. Roy et al. [50] presented a semi-empirical expression for the drain– current of the asymmetric device obtained from combining several different regional expressions via an interpolation function in order to construct a continuous analytical formulation for a wide range of bias conditions. Concerning the IDG MOSFET, an explicit and continuous threshold voltage-based model has been proposed by Reyboz et al. in [51, 52]; this model is detailed in Chapter 3 of this book. In the present chapter, we detail a physically-based modeling of the drain current in IDG MOSFET. Two approaches are developed: (a) a continuous model of the drift-diffusion transport which applies to all operation regimes [53] and (b) an analytical model for the ballistic drain current in the subthreshold regime. Both approaches include the description of short-channel effects and carrier quantum confinement. The drift-diffusion model is continuous over all operation regimes, which makes it very suitable for implementation in circuit simulators. The development is based on the calculation of the 2D potential distribution in the device taking into account the quantum-evaluated inversion charge. The model very well reproduces the threshold voltage and the current modulation by the back gate bias, as well as the quantum confinement effects on the inversion charge. A full

30


2-D quantum-mechanical numerical simulation code [54] (solving the 2D Poisson equation self-consistently coupled with the 1D Schrödinger equation) is used for completely validating the model. The analytical ballistic model applies to the subthreshold regime of ultra-thin IDG MOSFETs. The present approach captures the essential physics of such ultimate DG devices (quantum confinement, thermionic current) and introduces two main novelties usually neglected in compact modeling: the 2-D short-channel effects and the tunneling of carriers through the source-todrain barrier. Results given by this analytical approach are finally compared with data obtained with a self-consistent Poisson-Schrödinger solver based on a twodimensional (real-space) Non-Equilibrium Green’s Function (NEGF) approach and parallelized code architecture (DGGREEN2D [55]). This chapter is organized as follows: in Section 2.2 the drift-diffusion model is presented, including the calculation of the 2-D potential profile, the energy quantum levels and quantum inversion charge modeling and the final expression of the drain current in the drift-diffusion approach. The model validation by 2-D numerical simulation is also detailed and extensively illustrated. Section 2.3 presents the ballistic drain current model, based on the 1-D potential profile calculation in the subthreshold regime and the expression of both the thermionic and tunneling components of the drain current. The subthreshold ballistic current is validated by numerical simulation and finally, the impact of tunneling component on ultra-short IDG MOSFETs is investigated.

2.2 Drift-Diffusion Drain Current Modeling 2.2.1 2-D Potential Distribution Figure 2.1 shows the schematic description of an IDG MOSFET structure and the band diagram in a horizontal cross-section, together with the first energy subbands. We consider an independent Double-Gate n-channel MOSFET, in which x is the horizontal direction along the channel length and y is the vertical direction across the channel thickness. In the general case, the gates have different work function values and the top and bottom gate oxides are of the same material and have different thicknesses tox1 and tox2 , respectively. The two gates are independently biased with VG1 and VG2 . It can be assumed that the quasi-Fermi level (EFN ) is constant along the y direction, and current flows mainly in the x direction. The energy levels are referenced to the electron quasi-Fermi level of the n+ source region (EFS ). The band diagrams in the vertical (y-) direction are illustrated in Fig. 2.2 for two cases: (a) when both gates are biased in weak inversion and (b) when the gates are biased in strong inversion and VG1 = VG2 . In the first case the potential has a linear distribution in the Silicon film, in the second case the potential distribution can be approximated by a quasi-parabolic dependence as a function of the position in the Silicon film.


B

31

VG1 Front Gate (fM1)

A

t ox1

Source (N

t Si E(x)

SD )

A

ES1 E(x+dx) Channel (N

x

Drain (N

VD

SD )

A)

ES2 t ox2 Back Gate (fM2)

y

(a)

B

PE

E 1t E1

VG2

EC(x) E FN = qV F (x)

EFS = 0

qYS1(x)

qV D

qfS E FD

E Fi (x)

A-A (b)

0

xB-B

L

x

Fig. 2.1 (a) Schematic description of an IDG MOSFET and its electrical and geometrical parameters considered in this work; the dashed area shows the closed surface for the application of the Gauss’s law; (b) band diagram in horizontal cross-section in the Silicon film. PE = potential energy, EC = conduction band energy, EFN = quasi-Fermi level; EFS and EFD = quasi-Fermi-level in the source and drain reservoirs, resp., EFi = intrinsic Fermi level (a)

(b)

B-B

B-B

E1t E1

EFN qΨS1

EC −tox

E1t E1 EFN

qΨ

EFi

qVG y

0

tSi

tSi+tox

qΨ

EC

EFi −tox

qΨS1

qVG y

0

tSi

tSi+tox

Fig. 2.2 Band diagram in vertical cross-section (along the B-B cross-section defined in Fig. 2.1) in the Silicon channel for IDG MOSFET: (a) both front and back gates are biased in weak-inversion; (b) front and back gate biased in strong inversion and VG1 = VG2

32


The drain current modeling starts with the calculation of the 2D potential distribution in the device. In this work we assume a parabolic dependence of the potential in vertical (y) direction, which is modulated by the surface potential at the front interface ΨS1 (x). The surface potential varies in x direction and depends on VG1 , VG2 and VD (the expression of ΨS1 (x) will be developed later in this paragraph). The potential expression is given by the following equation: Ψ(x, y) = ΨS1 (x) + α(x)y + β(x)y2

(2.1)

where α and β are two coefficients depending on x. In the particular case of VG1 = VG2 , Eq. (2.1) gives a parabolic dependence of the potential as function of y. This expression reduces to a linear dependence in the case where both gates are in weak inversion and VG1 is different from VG2 . Coefficients α and β are calculated as function of ΨS1 using the boundary conditions at the front and back interfaces between the gate oxide and the Silicon film: εox VG1 − VFB1 − ΨS1 ∂ Ψ (x, y) ES1 = =− (2.2) εSi tox1 ∂ y y=0 εox VG2 − VFB2 − ΨS2 ∂ Ψ (x, y) ES2 = =− (2.3) εSi tox2 ∂ y y=tSi where ES1 and ES2 are the electric fields at the front and the back interface, respectively, VFB1 and VFB2 are the flat band voltages of the front gate and of the back gate, respectively, tSi is the film thickness, ΨS1 (x) = Ψ(x, y = 0) and ΨS2 = Ψ(x, y = tSi ), are the surface potentials at the front and back oxide/film interfaces, respectively. Then, coefficients α and β are given by: α=− β=

VG1 − VFB1 − ΨS1 γtox

γtox + tSi VG2 − VFB2 − ΨS1 −α (2γtox + tSi )tSi (2γtox + tSi ) tSi

(2.4) (2.5)

where γ = εSi /εox . The potential distribution given by Eq. (2.1) (with α and β calculated using Eqs. (2.4) and (2.5)) includes the dependence on the front gate and back gate polarizations, VG1 and VG2 . In Eqs. (2.4) and (2.5) we have assumed (for simplification) that the front and back gate oxides have the same thickness, tox1 = tox2 = tox . However, this assumption does not reduce the model generality, since similar development procedures can be applied in the case of front gate oxide and back gate oxide with different thicknesses. In order to calculate Ψ(x, y), the surface potential is needed. In ultrathin body DG MOSFET, a proper description of the electrostatics should take into account the effects of both dopants and charge carriers. In nanoscale devices, the doping charge can often be neglected owing to the small volume involved even for high doping densities. However, the contribution due to the inversion charge carrier density is very


33

important, especially above threshold [20]. In this work we will take into account both the doping charge and the free carrier charge in the calculation of the potential distribution. For this purpose, the expression of ΨS1 (x) is obtained by applying the Gauss’s law to the particular closed dashed surface shown in Fig. 2.1a (as shown in [56]): −

tSi

E(x, y)dy +

0

tSi

E(x + dx, y)dy − ES1(x)dx + ES2 (x)dx (2.6)

0

qN tSi dx =− A εSi

−

qi (x)dx εSi

In the right hand side of (2.6), the first term corresponds to the depletion charge (NA is the Silicon film doping) and the second term corresponds to the free carrier inversion charge. qi (x) is the inversion charge density, given by the integration of the electron charge (for an n-channel IDG MOSFET) over the entire Silicon film. For very thin films considered in this approach ( E1,max ) = 1 where the turning point coordinates x1 and x2 have literal expressions due to the analytical character of the barrier: √ 1 A± Δ x1,2 (Ex ) = ln (2.51) m1 2C1 where the quantities A and Δ are defined as follows: A = φS +

E1 Ex R + − 2 q q m1

Δ = A2 − 4C1 C2

(2.52) (2.53)

The WKB approximation has the main advantage to be CPU inexpensive and reasonably accurate for channel lengths down to a few nanometers. Moreover, it has been shown in [66] that differences between results obtained considering the WKB approximation and full quantum treatment (tight-binding scheme) are surprisingly small (typically a few percents), which confers to the WKB approach a reasonable accuracy in the frame of the present analysis.


47

0.9 VG1 =0 V VD = 0.8 V

First energy subband (V)

0.7 VG2 = −0.4 V 0.5 0.3 0.1

VG2 = 0.4 V (0.2 V step)

−0.1 −0.3 −0.5

Analytical

−0.7

Numerical

−0.9

0

5

10 x (nm)

15

20

Fig. 2.10 First energy subband profiles E1 (x) in the Silicon film calculated with the analytical model (Eq. (2.40)) and with the 2D numerical code DGGREEN2D [55]. Device parameters are: L = 10 nm, tSi = 2 nm and tox = 0.6 nm

2.3.4 Model Validation In order to test the validity of the model, we compare the model predictions with those obtained with a self-consistent Poisson-Schrödinger solver based on a realspace Non-Equilibrium Green’s Function (NEGF) approach (DGGREEN2D [55]). Figure 2.10 compares the first energy subband profiles in the Silicon film calculated with the analytical model and with the 2D numerical code DGGREEN2D for an intrinsic channel device with L = 10 nm. A good agreement is obtained between the two barriers in the subthreshold regime. In particular, we note an excellent agreement for the positions of the maximum as well as the amplitude of the barrier between the analytical and numerical curves. The slight difference in the barrier width is due to the electric field penetration in the source and drain regions, only taken into account by the numerical approach. The subthreshold ID (VG1 ) characteristics calculated with the analytical model for IDG MOSFET with L = 10 nm and different back gate voltages are shown in Fig. 2.11. Drain current characteristics for DG MOSFETs are also shown in this figure. Figure 2.12 compares analytical model and numerical data for IDG MOSFET with different channel lengths. These figures show that in the subthreshold regime the analytical model very well fits numerical data obtained with DGGREEN2D for devices in the deca-nanometer range.

48

D. Munteanu, J.-L. Autran DG

10

Drain current (A/ m)

10−1

VG2 = 0.4 V 0.2 V step

10−3

IDG

10−5 10−7 VG2 = −0.4 V

10−9

Numerical Analytical

10−11 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Front gate voltage VG1 (V)

Fig. 2.11 Subthreshold ID (VG1 ) characteristics calculated with the analytical model (lines). Values obtained with the 2D numerical code DGGREEN2D [55] are also reported for comparison (symbols). Device parameters are the same as in Fig. 2.10 102

Drain current (A /m )

L=5 nm

VG2 = 0 V

1 10−2

L=8 nm

10−4 10−6

L=10 nm

10−8

Numerical L=15 nm

Analytical

10−10 0

0.1

0.2

0.3 0.4 0.5 0.6 Front gate voltage VG1 (V)

0.7

0.8

Fig. 2.12 ID (VG1 ) characteristics of IDG MOSFET calculated with the analytical model. Values obtained with the 2D numerical code DGGREEN2D [55] are also reported for comparison. Device parameters are: tSi = 2 nm and tox = 0.6 nm

2.3.5 Discussion: Impact of the Source-to-Drain Tunnelling Current Quantum-mechanical tunneling was often neglected in several previous works, which mainly focused on the modeling of thermionic emission or scattering [67,68].

2 Compact Modeling of Independent Double-Gate MOSFET: A Physical Approach L = 15 nm

0.8 First energy subband (V)

49

Quantummechanical tunneling

0.6 0.4 0.2 0

8 nm

5 nm

10 nm

−0.2 −0.4

VG1 = 0 V VG2 = 0 V VD = 0.8 V

−0.6 −0.8 0

5

10

15

20

25

x (nm)

Fig. 2.13 Variation of the source to drain energy barrier in the channel when decreasing the channel length (VG1 = VG2 = 0V, VD = 0.8 V). Device parameters are: tSi = 2 nm and tox = 0.6 nm

Drain current (A / m )

102

VG2 = 0 V

L =5 nm

1 10−2 L =8 nm 10−4 10−6

L = 15 nm

10−8

Thermionic + tunnel Thermionic

10−10 0

0.1

0.2

0.3 0.4 0.5 0.6 Front gate voltage VG1 (V)

0.7

0.8

Fig. 2.14 Subthreshold ID (VG1 ) characteristics calculated with the analytical model when considering or not the WKB tunneling component in the ballistic current. Device parameters are the same as in Fig. 2.13

However, below 8 nm the width of the channel barrier decreases significantly (Fig. 2.13), increasing the impact of the quantum tunneling on the device characteristics. We have analyzed the impact of carrier tunneling on device performances through a detailed comparison between model predictions with and without quantum-mechanical tunneling. Two cases are considered: (1) thermionic emission for Ex > Emax and T(Ex ) = 0 for Ex < Emax ; (2) thermionic emission for Ex > Emax and quantum tunneling with T(Ex ) given by the WKB approximation (Eq. (2.50)). Figure 2.14 shows subthreshold ID (VG1 ) drain current characteristics calculated

50


with the analytical model for channel lengths from 5 to 15 nm. Two series of curves have been plotted, considering or not the WKB tunneling contribution in the ballistic current. These results highlight the dramatic impact of the source-to-drain tunneling current on the subthreshold slope and also on the off-state current. In such a subthreshold regime, the carrier transmission by thermionic emission is reduced or even suppressed due to the high channel barrier. As a consequence, when the channel length decreases the tunneling becomes dominant and constitutes the main physical phenomenon limiting the devices scaling, typically below channel lengths of ∼8 nm. Quantum-mechanical tunneling significantly degrades the off-state current especially in short channels, where the off-state current increase by more than two decades (Lg = 5 nm). However, the off-state current should be slightly reduced for the shorter geometries since it is calculated assuming perfectly ballistic transport and thus ignoring the partial reflection of electron wave functions on the source barrier. The subthreshold swing also increases (with about 30% for Lg = 8 nm with respect to L = 15 nm) due to quantum-mechanical tunneling. As previously indicated for the off-state current, these results can be considered as an upper limit, since we assume perfectly ballistic transport without wave function reflection at the source barrier. Finally, the threshold voltage roll-off is also notably affected by the carrier tunneling for channels shorter than 8 nm.

2.4 Conclusion In this chapter we have presented two physical-based compact models for the drain current in Independent Double-Gate MOSFETs considering drift-diffusion or pure ballistic transport. The first model is a drift-diffusion model combining 2D electrostatics with vertical quantum confinement effects, which makes it particularly dedicated to ultra-scaled devices, as expected at the end of the ITRS roadmap. This model is based on an analytical expression of the 2D potential distribution in the channel, taking into account the quantum inversion charge. In order to validate the proposed model, an extensive comparison with quantum numerical simulation using a 2D Poisson-Schrödinger code was performed. The model is shown to reproduce very well the threshold voltage and the current modulation by the back gate polarization, as well as the carrier quantum confinement effects on the drain current. The second model is an analytical model for the subthreshold drain current in ultra-thin independent Double-Gate MOSFETs working in the ballistic regime. The model is particularly well-adapted for ultra-short DG transistors in the decananometer scale since it accounts for the main physical phenomena related to these ultimate devices: 2-D short channel effects, quantum vertical confinement as well as carrier transmission by both thermionic emission and quantum tunneling through the source-to-drain barrier. The model has been used to predict essential subthreshold parameters such as off-state drain current and subthreshold slope and can successfully be included in circuit models for the simulation of independent Double-Gate MOSFET-based ICs.


51

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52. M. Reyboz, O. Rozeau, T. Poiroux, P. Martin, M. Cavelier and J. Jomaah, “Explicit short channel compact model of independent double gate MOSFET”, in Tech. Proc. NSTI-Nanotech., vol. 3, pp. 578–581, Santa-Clara, May 2007. 53. D. Munteanu, J. L. Autran, X. Loussier and O. Tintori, “Compact modeling of drain current in Independently Driven Double-Gate MOSFETs”, in Tech. Proc. NSTI-Nanotech., vol. 3, pp. 574–577, Santa-Clara, May 2007. 54. D. Munteanu and J. L. Autran, “Two-dimensional modeling of quantum ballistic transport in ultimate double-gate SOI devices”, Solid State Electron., vol. 47, no. 7, pp. 1219–1225, Jul. 2003. 55. J. L. Autran and D. Munteanu, “Simulation of electron transport in nanoscale independent-gate double-gate devices using a full 2D Green’s function approach”, J. Comput. Theor. Nanosci., in press, vol. 5, 2008. 56. D. Munteanu, J. L. Autran, X. Loussier, S. Harrison and R. Cerutti, “Compact modeling of symmetrical double-gate MOSFETs including carrier confinement and short-channel effects”, Mol. Simulat., vol. 33, no. 7, pp. 605–611, Jun. 2007. 57. R. J. Van Overstraeten, G. J. Declerck and P. A. Muls, “Theory of the MOS transistor in weak inversion-new method to determine the number of surface states”, IEEE Trans. Electron Devices, vol. 22, no. 5, pp. 282–288, May 1975. 58. Y. Taur and T. H. Ning, “Fundamentals of Modern VLSI Devices”, Cambridge University Press, Cambridge, 1998. 59. S. A. Hareland, S. Jallepalli, W.-K. Shih, H. Wang, G. L. Chindalore, A. F. Tasch and C. M. Maziar, “A physically-based model for quantization effects in hole inversion layers”, IEEE Trans. Electron Devices, vol. 45, no. 1, pp. 179–186, Jan. 1998. 60. L. Ge and J. G. Fossum, “Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs,” IEEE Trans. Electron Devices, vol. 49, no. 2, pp. 287–294, Feb. 2002. 61. V. Trivedi and J. G. Fossum, “Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs,” IEEE Electron Dev. Lett., vol. 26, no. 8, pp. 579–582, Aug. 2005. 62. M. Moreau, D. Munteanu and J. L. Autran, “Simulation study of short-channel effects and quantum confinement in independent double-gate metal-oxide-semiconductor field-effect”, Jpn. J. App. Phys., in press, 2008. 63. M. Lundstrom, “Fundamentals of Carrier Transport”, 2nd ed., Cambridge University Press, Cambridge, 2000. 64. D. K. Ferry and S. M. Goodnick, “Transport in Nanostructures”, Cambridge University Press, Cambridge, 1997. 65. C. Cohen-Tannoudji, B. Diu and F. Laloë, “Quantum Mechanics”, Hermann, Paris, 1992. 66. M. Städele, “Influence of source-drain tunneling on the subthreshold behavior of sub10 nm double-gate MOSFETs”, in Proceedings of the European Solid-State Device Research Conference (ESSDERC), pp. 135–138, Florence, Italy, Sept. 2002. 67. K. Natori, “Ballistic metal-oxide-semiconductor field effect transistor”, J. Appl. Phys., vol. 76, no. 8, pp. 4879–4890, Oct. 1994. 68. M. S. Lundstrom, “Elementary scattering theory of the Si MOSFET”, IEEE Electron Device Lett., vol. 18, no. 7, pp. 361–363, Jul. 1997.

Chapter 3

Compact Modeling of Double Gate MOSFET for IC Design Marina Reyboz, Olivier Rozeau, and Thierry Poiroux

3.1 Introduction To take advantage of the double gate MOSFET (DGMOS) architecture with independent driven gates, designers need compact models to imagine new circuits. A model is a description of the device electrical behavior. Thus, the electrostatics part is put in equation, equation’s Poisson with Boltzmann or Fermi-Dirac statistics is solved and a transport phenomenon is added: statistical or quantum. A compact model is a simplified model, which allows designs with a lot of transistors. Criteria of a good compact model are simple equations, short computing time, few fitting parameters and predictive. From a circuit design point of view, the computing time is a very significant parameter, as consequence physical models using non-optimized numerical resolutions are not adapted. They are various methods of modeling a MOS transistor. The main difference is the way of solving equations. The issue is that there is no exact solution of equation’s Poisson. Consequently, different options exist: surface potential, charge or threshold voltage approaches. Surface potential based models are discussed in the first part. The principle is to evaluate surface potential to calculate the currents and charges [1–7]. The modeling challenge is highlight in particular for the independent gate transistors where electrical behavior is very complex. The second method consists in defining a charge model which is a physical model and is based on the derivation of the inversion charge [8–11]. This approach is not described in this book. Finally, threshold voltage based model consists to calculate currents and charges using approximations in different regimes. Using mathematical functions, the currents and charges are compute for all regimes. Because designers are accustomed to using a threshold voltage based compact model, this chapter will be dedicated to this M. Reyboz, O. Rozeau and T. Poiroux CEA-LETI Minatec, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France A. Amara and O. Rozeau (eds.), Planar Double-Gate Transistor. c Springer Science + Business Media B.V. 2009

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way. In addition, this approach seems to be the only solution to provide independent double gate MOSFET (IDGMOS) model allows designing circuits with reasonable computing times. So, the goal of this chapter is to give sufficient information to help the designers using an SOI double-gate CMOS technology. Note that quantum effects and ballistic transport are only detailed in previous chapter. In this chapter, we expose the mathematic development on the model’s core with short channel effects only. The first step to get a compact model is to derive the drain current and charge in all operating modes for a long channel MOSFET. This will be the third part of this chapter. The last part explores the modeling of the short channel double gate devices.

3.2 Modeling of Double Gate MOSFET with Independent Driven Gates 3.2.1 Challenge of the Surface Potential Based Model in Compact Model for IC Design As detailed in the previous chapter, double gate MOSFET is symmetric when the front and back gates are identical (see Fig. 3.1). In other words, it has the same: • • • •

Applied voltage at both gates VG1 = VG2 = VG Gate work functions ΦM1 = ΦM2 = ΦM Gate oxides (permittivity and thickness) Tox1 = Tox2 = Tox and Electrical transport properties of both silicon-oxide interfaces μ1 = μ2 = μ

VG1 −Tox1 Front gate

VS

VD y

Front gate oxide 0

L Silicon film

Source

Drain

Tsi Tsi + Tox2

Back gate oxide Back gate

x

VG2

Fig. 3.1 Schematic description of a double gate MOSFET with independent gates

3 Compact Modeling of Double Gate MOSFET for IC Design

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Double gate transistor is considered as asymmetric when one or several symmetrical conditions are not valuables. To simplify the understanding, we consider only the dissymmetry on gate oxide thicknesses (Tox1 , Tox2 ), gate workfunction (ΦM1 , ΦM2 ) and on gate biases (VG1 , VG2 ) only, see Fig. 3.1. The electrical characteristics are detailed in the next part. In the following, when the dissymmetry is only due to the gate voltages, the structure is named symmetrical DGMOS with independent driven gates. For n-channel MOSFET with undoped silicon film, the electrostatic potential ψ in the silicon is described by the Poisson’s equation: d2 ψ (x) q ni ψ (x) − Vc (y) = exp (3.1) εsi ut dx2 Where q is the electron charge, ni the intrinsic doping, εsi the silicon permittivity, ut = kT/q the thermal voltage and Vc the quasi-Fermi level along the channel. k is the Boltzmann’s constant and T is the device temperature. The first integration of this equation gives: 2 q n i ut ψ (x) − Vc (x) dψ (x) − α0 = exp (3.2) dx εsi ut For symmetrical double gate MOSFET with independent gates, the coefficient α0 depends on the gate biases. Indeed, as explained in the previous chapter, the electrical field inside the silicon film can present a zero value or not (see Fig. 2.2). This condition depends on the MOSFET regime: if both interfaces are in weak inversion, if one interface is in weak inversion and the other in strong and if both interfaces are in strong inversion. Compared with bulk transistor, the IDG MOSFET presents two channels which can be coupled as functions of the bias conditions. At the present time, global analytical explicit solution does not exist for all regimes. Mathematical approximations as used in PSP model [12] are not adequate for this device architecture. Today, some works are focused on methods to solve equation’s Poisson using numerical resolutions [13–16] or approximations for the different regimes [17–19]. However, a great accuracy on surface potential for current calculation is crucial [12]. Unfortunately the actual approximations of surface potential calculation can suffer of a lack of accuracy. In addition, the smoothing condition between the different modes can introduce discontinuities on derivative and by consequence, convergence problems during the circuit simulations. That is why; it seems preferable to compute surface potential with a numerical resolution. The price to pay is a large time computing during circuit simulations. The surface potential based model of IDGMOS remains a giant challenge to provide powerful model to the circuit designers. For these reasons, in this chapter, we choose to detail a threshold voltage based model.

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3.2.2 How to Model IDG MODEL with a Threshold Voltage Based Model The principle of a threshold voltage based compact model is to derive a threshold voltage which links weak and strong inversion. Different models used this approach [20–27]. For the continuation, we will focus on the threshold voltage based compact model as published in reference [28]. The aim of this part is to explain how this new architecture impacts the main characteristics used by designers: the threshold voltage, the subthreshold swing, the transconductance and the drain conductance. The Fig. 3.2 represents the drain current ID obtained using TCAD simulation (Technology Computer-Aid Design) for different gate voltages VG1 and VG2 in linear regime (VDS = 5 mV) for a nMOSFET with a channel length L = 1 μm and a channel width W = 1 μm. For the illustrations, the undoped silicon film Tsi and the gate oxides thickness Tox of the device are 10 and 1 nm, respectively. The Fig. 3.2 shows the drain current in symmetrical and independent gate modes. We can observe the subthreshold slope changes when the back gate voltage varies. Moreover, the logarithmic scale shows that the subthreshold slope is better in symmetrical mode. Part 3.2 will explain why. As discussed later, the drain current is considered as the sum of the front and the back gate currents. Compared with bulk MOSFET, IDG transistor has not one threshold voltage but two threshold voltages. Vth1 and Vth2 are defined as the threshold voltage for the front and back channel, respectively. The Fig. 3.3 shows the front and back channel currents ID1 and ID2 versus the front gate voltage for several back gate voltages. The front channel current depends

10−5 10−6 10−7

ID (A)

10−8

VG2 = 0 to 1.2V

10−9 10−10 10−11

Independent mode Symmetrical mode

10−12 10−13 10−14 10−15 0.0

VDS = 5mV 0.2

0.4

0.6

0.8

1.0

1.2

VG1 (V)

Fig. 3.2 TCAD simulation of the drain current ID versus the front gate voltage VG1 for different back gate voltages VG2 in linear regime (VDS = 5 mv) for independent mode (solid curves) and symmetrical mode (dashed curve). L = W = 1 μm, Tsi = 10 nm, Tox = 1 nm


59

10−5 10−6 10−7 ID1,ID2 (A)

10−8 10−9

Front channel Back channel

10−10 10−11 10−12

VG2 = 0 to 1.2V

10−13

VDS = 5mV

10−14 10−15 0.0

0.2

0.4

0.6 VG1 (V)

0.8

1.0

1.2

Fig. 3.3 TCAD simulation of the front and back channel currents ID1 (grey curves), ID2 (black curves) versus the front gate voltage VG1 for different back gate voltages VG2 in linear regime (VDS = 5 mv). L = W = 1 μm, Tsi = 10 nm, Tox = 1 nm

on the back gate voltage due to the electrostatic interface coupling. Indeed, when the back interface is in weak inversion (VG2 < Vth2 ), the front threshold voltage Vth1 and the subthreshold slope of the front channel are strongly dependent of the back gate voltage. The front threshold voltage Vth1 decreases when the back gate voltage increases [27]. Nevertheless, when the back gate voltage increases and becomes higher than Vth2 , the back channel is strongly inverted and the front current becomes quasi-independent of the back gate voltage. The electrostatic interface coupling becomes very low due to a screening effect. In addition, the back current lightly depends on the front gate voltage due to the back threshold voltage dependence with the front gate voltage. In this case, the subthreshold slope is conditioned by the back channel. As conclusion, the interface coupling exists as soon as both interfaces are in weak inversion and decreases when one interface is strongly inverted. This behavior must be taken into account in the compact model. The total drain current ID is written as the sum of the front ID1 and the back ID2 drain currents. The following equations are the smoothing function used in BSIM model [29] and adapted for an IDG MOSFET. As described by the Eq. (3.3), the total drain current is composed of two channel currents for front and back interface, respectively. Each current is calculated using Eqs. (3.4) to (3.7). ID = ID1 + ID2 (3.3) With,

njeff VDSjeff W VDSjeff IDj = μ Coxj VGtj 1 − L 2 VGtj + 2 ut

(3.4)

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Where μ is the carrier mobility, W the gate width, L the gate length, Coxj = εox /Toxj the gate oxide capacitances. εox is the oxide permittivity. VGtj represents the effective driven gate voltage (see Eq. (3.5)), VDSjeff is the effective drain voltage (Eq. (3.7)) and njeff is an effective coupling factor (see the part 3.4 for more details). j is an index equal to 1 for the front gate and to 2 for the back one. ⎤ ⎡ V Gj −Vthj −Voffj exp 2 ut n j ⎦ VGtj = 2 ut nj ln ⎣1 + (3.5) V −V 1 + 2 exp − 2Gjut n thj j

Where V Gj is the effective gate voltage given by the Eq. (3.6), Vthj is the threshold voltage, Voffj the correction term describing the non-total screening effect of a strong inverted interface (see part 3.3) and nj the coupling factors (see part 3.1). V Gj = VGj − ΦM j

(3.6)

VGj is the gate voltage of the considered channel. For illustration, the gate workfunction ΦM1 and ΦM2 are supposed null. In this case, V Gj = VGj . VDSjeff = Vdsatj −

2 1 Vdsatj − VDS − δ + Vdsatj − VDS − δ + 4 δ Vdsatj (3.7) 2

The effective drain voltages allow continuity between linear and saturation regime. Vdsatj are the saturation drain voltages, deriving afterward and δ a smoothing parameter. Subthreshold slope factors nj , threshold voltages Vthj , offset voltages Voffj and drain saturation voltages Vdsatj are detailed in the following.

3.3 Long Channel IDG Mosfet Threshold Voltage Based Model 3.3.1 Subthreshold Slope Factor (n) 3.3.1.1 Subthreshold Slope in Double Gate MOSFET with Independent Gates For a double gate MOSFET, two subthreshold slopes must be defined, one for the front interface and another one for the back one. The subthreshold slopes are defined by the Eq. (3.8). dVG1 dVG2 and S2 = (3.8) S1 = d (log (ID )) d (log (ID )) The Fig. 3.4 shows that the front subthreshold slope varies with the front gate voltage. For this transistor, the swing will be extracted for VG1 = VG1,Smin (see Fig. 3.4), which corresponds to the minimum values. On the Fig. 3.5, the front swing is plotted for different back gate voltages.

3 Compact Modeling of Double Gate MOSFET for IC Design 10−6

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VDS = 5mV VG2 = 0 to 1.2V

10−12

300

200

10−15

S1 (mV/dec)

ID (A)

10−9

100 10−18 VG1,Smin 10−21

−0.4

−0.2

0.0

0.2

0.4 0.6 VG1 (V)

0.8

1.0

0 1.2

Fig. 3.4 TCAD simulation of drain current ID and the front subthreshold slope S1 versus the front gate voltage VG1 for several back gate voltages VG2 in linear regime (VDS = 5 mv). L = 130 nm, W = 1 μm, Tsi = 10 nm, Tox = 1 nm

VDS = 5mV

VG1,Smin = VG1,Smin

S1 (mV/dec)

120

IDG MOSFET

90 80 70 60 −0.4

Symmetrical DG MOSFET −0.2

0.0 VG2 (V)

0.2

0.4

Fig. 3.5 TCAD simulation of the subthreshold slope of the front interface S1 at VG1,Smin versus the back gate voltage VG2 in linear regime (VDS = 5 mv). L = 130 nm, W = 1 μm, Tsi = 10 nm, Tox = 1 nm

From this figure, more the back gate voltage increases, worst is the subthreshold slope. Indeed, the back channel is being formed. Consequently, to get the better front swing, the back gate voltage should be as low as possible. It is the same for the back one. As illustrated by the Fig. 3.2, the best subthreshold slope is for the symmetrical case [30].

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Fig. 3.6 Capacitive divider for an independently driven DG MOSFET

Cox1 ψs1 Csi ψs2 Cox2

VG2

3.3.1.2 Subthreshold Slope Modeling in Independent Gates In weak inversion at both interfaces and considering the inversion charges negligible, the device can be modeled as a capacitive divider as illustrated by the Fig. 3.6. Where Csi = εsi /Tsi is the capacitance associated to the silicon film. From this schematic, the front and back surface potentials ψs1 and ψs2 , respectively, can be easily calculated: Csi Cox2 ψ = V − G1 s1 Csi Cox1 +Cox1 Cox2 +Csi Cox2 (V G1 − V G2 ) (3.9) ψs2 = V G2 + C C +CCsi CCox1 +C C (V G1 − V G2 ) ox1 ox1 ox2 ox2 si

si

In addition, when both interfaces are in weak inversion, the total drain current can be expressed as [31]: ψs1 ψs2 exp − exp ut ut W VDS 2 ID = −μ q ni Tsi ut · exp − −1 (3.10) L (ψ s1 − ψs2 ) ut Using Eqs. (3.8) and (3.10), the subthreshold slope of the front gate S1 is obtained (for S2 , 1 and 2 indices are permuted): S1 =

−ln(10) 1−α1 −α2 ψs1 −ψs2

−

1−α 1 ψ −ψ ut 1−exp s2 u s1 t

With,

α = 1 α2 =

−

α2 ψ −ψ ut 1−exp s1 u s2

(3.11)

t

Cox2 Csi Cox1 Cox2 +Cox1 Csi +Cox2 Csi

(3.12) Cox1 Csi Cox1 Cox2 +Cox1 Csi +Cox2 Csi


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The difference between the front and the back surface potentials is:

ψs2 − ψs1 =

Cox1 Cox2 (V G2 − V G1 ) Csi Cox1 + Cox1 Cox2 + Csi Cox2

(3.13)

Consequently, from Eqs. (3.9) and (3.11), each swing depends on both gate voltages. Considering the subthreshold slope of the front interface, when the back gate voltage increases for a given front gate voltage, the surface potential difference ψs2 − ψs1 increases following the Eq. (3.13). As consequence, the subthreshold slope of the front interface increases as described by the Eq. (3.11). In order words, when the front gate voltage increases, the front surface potential ψs1 rises but not as much as VG1 increased because the back surface potential tends to oppose this increase. The swing S1 will be worse than for a symmetrical DG MOSFET where both extremities are linked to the gate voltage V G . The front and the back surface potentials Ψs simultaneously evolve. Consequently, all the rise of V G is wholly sent to the surface potentials and so Ψs = V G . Note that the swing is quasi-ideal for the symmetrical case [32].

3.3.1.3 Subthreshold Slope Factors Using the Eq. (3.9), the subthreshold slope factors for front interface n1 and back one n2 are calculated with: dψ sj −1 nj = (3.14) dVGj The results are:

Csi Cox2 n = 1+ 1 Cox1 (Csi +Cox2 ) si Cox1 n2 = 1 + C C(C +C ) ox2

si

(3.15)

ox1

3.3.2 Threshold Voltage Modeling (Vth ) 3.3.2.1 Threshold Voltage Behavior in IDG MOS As illustrated by the Fig. 3.7, the front threshold voltage depends on the back gate voltage because of the interface coupling and until the back interface is weakly inverted [27]. When the back interface is in strong inversion, the front threshold voltage tends toward a limit value, Vth1lim . Note that the film is undoped, the accumulation mode not exists.

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Front interface in SI Back interface in WI

Both interfaces in strong inversion (SI) Limit of Vth1 Expression of Vth1

Both interfaces in weak inversion (WI)

Front interface in WI Back interface in SI

Expression of Vth2 VG2

Fig. 3.7 Threshold voltages and their limit values

3.3.2.2 How Modeling the Threshold Voltage in IDG MOS The threshold voltages Vth1 and Vth2 are defined by an extrapolation of the weak inversion mode. For that, we derive the front and the back inversion charges thanks to the basic equation of physics: Poisson equation, Gauss theorem and the limit conditions. The first integration of Poisson equation (Eq. (3.2)) gives: ψ −V ψs2 −Vc c s1 2 2 u u t t qG1 − qG2 = −2 q ni εsi ut e −e (3.16) qG1 and qG2 are the front and back gate charges, respectively. The limit conditions are writing as: VGj = ψsj +

qGj Coxj

(3.17)

j is 1 for the front gate and 2 for the back one. Charge conservation links the total inversion charge qinv and the gate charges qG1 and qG2 . qG1 + qG2 + qinv = 0 (3.18) Using the Eqs. (3.16) and (3.18):

(qG1 − qG2) .qinv

ψS2 − Vc = 2 q ni εSi ut exp ut ψS2 − ψS1 × tanh 2.ut

ψS1 − Vc + exp ut

(3.19)


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In addition, we define the total inversion charge as: qinv = qinv1 + qinv2

(3.20)

The inversion charges qinv1 and qinv2 of the front and back channels respectively can be defined using: ψ −V ψ −ψ (qG1 − qG2 ) qinv1 = 2 q ni εSi ut exp S1ut c tanh S22 ut S1 (3.21) ψS2 −Vc ψS2 −ψS1 tanh (qG1 − qG2 ) qinv2 = 2 q ni εSi ut exp ut 2 ut So, the front and the back inversion charges, qinv1 and qinv2 , are: 2 q ni εSi ut ψS1 −Vc ψS2 −ψS1 tanh exp qinv1 = qG1 −q ut 2 ut G2 2 q ni εSi ut ψS2 −ψS1 c exp ψS2u−V tanh qinv2 = qG1 −q 2 ut t G2

(3.22)

Thanks to Eq. (3.9), explicit equations of the front and the back inversion charges are found. To get the front and the back threshold voltages, we identify these equations to the classical expression of the inversion charge adapted to the double gate MOSFET. V G1 −Vth1 −n1 Vc qinv1 = − n1 Cox1 ut exp n u 1 t (3.23) V G2 −Vth2 −n2 Vc qinv2 = −n2 Cox2 ut exp n ut 2

Consequently, the front and the back threshold voltages are: ⎞ ⎛ Ceq V G2 −V G1 tanh C 2 ut Si Vth1 = n1 ut ln 2 n1 Cox1 ut − (n1 − 1) V G2 − n1 ut ln ⎝ ⎠ Ceq V G2 −V G1 q ni TSi CSi 2 ut ⎞ ⎛ Ceq V G2 −V G1 tanh C 2 ut Si Vth2 = n2 ut ln 2 n2 Cox2 ut − (n2 − 1) V G1 − n2 ut ln ⎝ ⎠ Ceq V G2 −V G1 q ni TSi CSi 2 ut (3.24) Where, 1 1 1 1 = + + (3.25) Ceq Cox1 CSi Cox2 As discussed in the beginning of this part, these threshold voltages are valid only when the opposite interface is in weak inversion. If it is in strong inversion, the inversion layer creates a screening area and the threshold voltage no more depends on the

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opposite gate voltage. Consequently, the Vth1 and Vth2 tends towards a limit value Vth1,lim and Vth2,lim . To derive the limit value of the threshold voltage, we need coupling conditions on V G1 and V G2 . Eq. (3.23) give: V Gj < Vthj + nj Vc + nj ut

(3.26)

j is 1 for the front gate and to 2 for the back one. When these conditions are not verified, there is no coupling. The limit conditions are drawn Fig. 3.7. Vth1lim and Vth2lim are the coordinates of the intersection point of the curves Vth1 (V G2 ) et Vth2 (V G1 ). By definition, Vth1lim and Vth2 lim verify simultaneously Eq. (3.24). After some algebra, the following relations are obtained: C ΔV eq th tanh C 2 n1 Cox1 ut n1 −1 Si 2 ut Vth1lim = ut ln q ni TSi + n1 ΔV th − ut ln Ceq ΔV th CSi 2 ut (3.27a) C ΔV eq th tanh CSi 2 ut 2n C ut − n2n−1 ΔV th − ut ln Vth2 lim = ut ln q2ni ox2 Ceq ΔV th TSi 2 CSi 2 ut Where, ΔVth = Vth1lim − Vth2lim =

n 1 n2 n1 Cox1 ut ln n1 + n2 − n1 n2 n2 Cox2

(3.27b)

Finally, to unify the threshold voltages, Eq. (3.24) are used when the coupling conditions are realized and Eq. (3.27) else. A smoothing function is used and the result is illustrated by the Fig. 3.8. On this figure, we observe the limit value of the threshold voltage when the back interface is strong inverted.

VG1 = 0V

Vth1

[Eq. 2.13]

[Eq. 2.15]

Fig. 3.8 Front threshold voltage Vth1 versus the back gate voltage

VG2


67

3.3.3 Offset Voltage in Strong Inversion (Voff ) 3.3.3.1 Interface Coupling in Strong Inversion When one interface is in strong inversion, the screening effect is not total. To highlight this effect, the drain current derived using only the threshold voltages (without offset voltages) is compared with TCAD resolution on the Fig. 3.9. Indeed, a coupling field appears between both interfaces reducing the drain current [14]. The drain current still increases when the front interface is strongly inverted. To take into account this effect, a correction factor εj is introduced into the inversion charge expression as following: qinvj = −Coxj V Gj − Vthj − nj Vc 1 − εj (3.28) j is 1 for front interface, and 2 for back one. The goal is to calculate this coefficient. Nevertheless, the coupling field must be evaluated before.

3.3.3.2 Coupling Field and Gate Charges Calculation in Strong Inversion To derive the coupling charge, both interfaces are considered in weak inversion. Using the Eqs. (3.9) and (3.17), the gate charges can be expressed versus the gate voltages: qG1 = −qG2 = Csi (ψs1 − ψs2) = Ceq V G1 − V G2 (3.29)

8.0

ID (μA /μm)

7.0

VDS = 5mV

6.0

TCAD simulation Drain current without Voffj

5.0

VG2 = 0 to 1.2V

4.0 3.0 2.0 1.0 0.0 0.0

0.2

0.4

0.6 VG1 (V)

0.8

1.0

1.2

Fig. 3.9 Comparison on the drain current ID versus front gate voltage VG1 at several back gate voltages VG2 in linear regime (VDS = 5 mv) between the model without offset voltage Voffj and TCAD simulation results. L = W = 1 μm, Tsi = 10 nm, Tox = 1 nm

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For instance, when the front interface becomes in strong inversion, the charge qG2 will depend on V G1 until: V G1 < Vth1 + n1 Vc + n1 ut

(3.30)

qG2 = Ceq V G2 − Vth1 − n1 Vc − n1 ut

(3.31)

Then, qG2 will saturate at:

Consequently, the coupling field in the weakly inverted area is given by: Ecpl =

Ceq V G2 − Vth1 − n1 Vc − n1 ut εSi

(3.32)

In the same way, this field will depend on the back interface till the back interface is not in strong inversion: V G2 < Vth2 + n2 Vc + n2 ut

(3.33)

For the general case, the coupling field becomes: " Ceq ! min V G2 , Vth2 + n2 Vc + n2 ut − min V G1 , Vth1 + n1 Vc + n1 ut εSi (3.34) The coupling charge associated to this field is: ! " qcpl = Ceq min V G2 , Vth2 + n2 Vc + n2 ut − min V G1 , Vth1 + n1 Vc + n1 ut (3.35) Also, the gate charges can be calculated as: qG1 = −qinv1 − qcpl (3.36) qG2 = −qinv2 + qcpl Ecpl =

All charges are localized on the Fig. 3.10.

3.3.3.3 Calculation of the Offset Voltage in Strong Inversion To calculate εj in Eq. (3.28), the front interface is considered in strong inversion and the back interface in weak inversion. The front surface potential is higher than the back surface potential, Ψs1 > Ψs2 + 2ut. Using this condition into the first Eq. (3.22), the hyperbolic tangent term is approximated by -1, this equation becomes: ψS1 − Vc (3.37) (qG1 − qG2) qinv1 = −2 q ni εSi ut exp ut


69

VG1 Front gate

VS

qG1

VD y

y qinv1 y+ dy

0

qcpl

Source

L Drain

qinv2

Tsi

Back gate x

qG2 VG2

Fig. 3.10 Schematic description of charge localization of a symmetrical double gate MOSFET with independent gates

Using Eq. (3.36) and neglecting qinv2 compared to qinv1 , the front surface potential is: qinv1 + 2 qcpl qinv1 ψS1 = Vc + ut ln (3.38) 2 q ni εSi ut With the Eq. (3.17) for the front interface, the front gate voltage is written as: qinv1 + 2 qcpl qinv1 qcpl qinv1 V G1 = Vc + ut .ln − − (3.39) 2 q ni εSi ut Cox1 Cox1 Replacing qinv1 by the expression (3.28) and with a first order Taylor expansion of ε1 , we find: qcpl Va1 − Vth1 − Cox1 − (n1 − 1) Vc ε1 = (3.40a) Cox1 VGt1eff −qcpl 2 ut Cox1 V −2·q + VGt1eff Gt1eff

With,

And,

cpl

! " Cox1 VGt1eff Cox1 VGt1eff − 2 qcpl Va1 = ut ln 2 q ni εSi ut

(3.40b)

VGt1eff = V G1 − Vth1 − n1 Vc

For the back channel, same expressions are obtained replacing index 1 by 2.

(3.40c)

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TCAD simulation Model

1E-04

15.0 1E-06 VG2 = 0 to 1.2V

8.0

1E-08

6.0 1E-10

4.0 2.0 VDS = 5mV 0.0 0.0

ID (A / μm)

ID (μA/ μm)

10.0

0.2

0.4

0.6

0.8

1.0

1E-12 1.2

VG1 (V)

Fig. 3.11 Drain current ID versus the front gate voltage VG1 for different back gate voltages VG2 in linear regime (VDS = 5 mv). Comparison between TCAD simulation (symbols) and the model (grey curves). L = W = 1 μm, Tsi = 15 nm, Tox1 = Tox2 = 1 nm

To include this phenomenon in the Vth-based model, the inversion charges in all regimes are written as: ⎤ ⎡ V Gj −Vthj −Voffj −Vc exp 2 ut n j ⎦ qinvj = −Coxj 2 ut nj ln ⎣1 + (3.41) V −V −Vc 1 + 2 exp − Gj2 ut thjnj With,

Voffj = −εj V Gj − Vthj

(3.42)

Note that Voffj is calculated at the source side (Vc = 0) with small error. The Fig. 3.11 compares the threshold voltage based model with TCAD simulation.

3.3.4 Drain Saturation Voltage Vdsatj is the saturation drain voltage obtained when dIDj /dVDS = 0. It is basically included in the model as in [29]: Vdsatj =

Esatj L

V Gtj +2 ut njeff

Esatj L +

V Gtj +2 ut njeff

(3.43)


71

With, Esatj =

2 vsatj μ

(3.44)

V Gtj is given by the Eq. (3.5). vsatj is the saturation velocity. nieff takes into account interface coupling when the both gate voltages are high. Indeed, both interfaces are in weak inversion in saturation at the drain side. In this case, the interface coupling becomes significant and the threshold voltages are reduced. Considering the drain current given by the Eq. (3.4) and after some algebra, the threshold voltage is equal to Vthj -nj .ut and the effective coupling factor is clamped to 1 at high gate voltages in saturation regime. To unify these both variables in all regimes, the following expressions can be used for the front channel: n1eff =

1 + exp

1 − n1

Vth1eff = Vth1 −

−V G2 +Vth2 7 ut

1 + exp

Vdseff1 + n1 Vdsat1

n u 1 t

−V G2 +Vth2 7 ut

(3.45)

Vdseff1 Vdsat1

(3.46)

The expressions for back channel are obtained permuting the index 1 with the index 2. This model is compared with numerical simulations on the Fig. 3.13. This figure represents the drain current versus de drain voltage VDS for different front gate voltages VG1 with back channel in weak inversion (VG2 = 0, 1 V) and with back channel in strong inversion (VG2 = 1, 2 V) (Fig. 3.12). 800 TCAD simulation Model VG2 = 1.2V

ID (μA/ μm)

600

400 VG2 = 0 to 1.2V 200

0 0.0

VG2 = 0.1V

0.2

0.4

0.6

0.8

1.0

1.2

VDS (V)

Fig. 3.12 Drain current ID versus the drain voltage VDS for different front gate voltages VG1 at two back gate voltages (VG2 = 0.1 V and 1.2 V). Comparison between TCAD simulation (symbols) and the model (grey curves). L = W = 1 μm, Tsi = 15 nm, Tox1 = Tox2 = 1 nm

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gm11

gm (μS)

200

gm1

100 gm12

0 −100 −200

0.2

0.4

0.6

0.8

1.0

VG1 (V)

Fig. 3.13 Front transconductances, gm1 , gm11 and gm12 versus the front gate voltage VG1 at high back gate voltage (VG2 = 1.2 V) in linear regime (VDS = 50 mv). L = 130 nm, W = 1 μm, Tsi = 10 nm, Tox = 1 nm

3.3.5 The Transconductance Behavior in IDG MOS For a double gate MOSFET, two transconductances are defined, gm1 for the front interface and gm2 for the back one. gm1 =

dID dID and gm2 = dVG1 dVG2

(3.47)

More precisely, the front transconductance for instance can be written as: gm1 = gm11 + gm12 with gm11 =

dID1 dID2 and gm12 = dVG1 dVG1

(3.48)

(3.49)

The following figure allows understanding the impact of each term (Fig. 3.13). The black curve represents the total front transconductance which is the sum of gm11 and gm12 (grey curves). The gm11 increases with the front gate voltage until the front channel is created. Then, it screens VG1 and so the gm11 becomes almost constant. gm12 becomes negative when the front interface becomes strongly inverted. Indeed, the back channel tends to slow down the creation of the front channel. This is due to interface coupling.


73

3.3.6 The Drain Conductance Behavior in IDG MOS Another important electrical characteristic for circuit design is the drain conductance. In double gate MOSFET with independent gates, the drain conductance is defined as: gds = gds1 + gds2 (3.50) With, gds1 =

dID1 dID2 and gds2 = dVDS dVDS

(3.51)

The following figure shows that drain conductance depends on the front and the back drain conductance, mainly when the interface is strongly inverted. Indeed, when the back interface is in weak inversion the gds is equal to gds1 whereas the back gate is at 1.0 V, the drain conductance is the sum of gds1 and gds2 . This is only due to the fact that the front and back gate currents act to the total current (Fig. 3.14). How the drain conductance depends on the front gate voltage for instance? The following graph allows answering the question (Fig. 3.15). The front drain conductance increases when the front gate voltage rises because of the generation of the front channel. Contrary to the front one, the back drain conductance decreases when VG1 rises. The back channel tends to opposite itself against the creation of the front channel by the interim of the interface coupling.

3.3.7 Mobility The previous sections assume that the mobility is constant. This is a strong assumption because mobility affects most of the electrical characteristics of a MOSFET. 1E-01 1E-02

gds (S/μm)

1E-03 1E-04 1E-05 1E-06

gds gds1 gds2

gds# gds1 black -VG2 = 1V grey -VG2 = 0.2V

1E-07 1E-08 1E-09 1E-10 0.0

0.2

0.4

0.6 VDS (V)

0.8

1.0

1.2

Fig. 3.14 Front, back and total drain conductances, gds1 , gds2 and gds respectively, versus the drain voltage VDS at high front gate voltage (VG1 = 1.2 V) and two back gate voltage values (VG2 = 0 and 1.2 V). L = 130 nm, W = 1 μm, Tsi = 10 nm, Tox = 1 nm

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gds

gds (mS/ µm)

5.0 4.0 gds2 3.0 2.0 gds1

1.0 0.0

0.2

0.4

0.6 0.8 VG1 (V)

1.0

1.2

Fig. 3.15 Front, back and total drain conductances, gds1 , gds2 and gds respectively, versus the front gate voltage VG1 at high back gate voltage (VG2 = 1.2 V) in linear regime (VDS = 50 mv). L = 130 nm, W = 1 μm, Tsi = 10 nm, Tox = 1 nm

40

Constant mobility

ID (μA / μm)

With mobility degradation 30 VG2 = 1.2V 20 VG2 = 0.0V 10 VDS = 5mV 0 0.0

0.2

0.4

0.6 VG1 (V)

0.8

1.0

1.2

Fig. 3.16 Comparison on the drain current ID versus the front gate voltage VG1 for two back gate voltages VG2 (0 and 1.2 V) in linear regime (VDS = 5 mv), between TCAD simulations with a constant mobility (grey curves) and the CVT degradation model (black curves). L = 130 nm, W = 1 μm, Tsi = 10 nm, Tox = 1 nm

As shown on the following figure, the current is degraded when the numerical simulations are done with the Lombardi-CVT mobility model [33]. This is mainly due to the transverse electrical field because the drain voltage is low. If it was in saturation regime, the longitudinal field provides degradation too (Fig. 3.16). To take into account this phenomenon, physical degradation mobility was included in the model. Because they are two channels, two mobility parameters should


be defined: μ1 and μ2 as [34]: 1 μ1 = 1 μ2 =

1 μ01

+

1 μ02

+

1

a1 Es1 +b1 Ecpl

+

75

1

(

c1

Es1 +Ecpl

)

2

(3.52) 1

a2 Es2 −b2 Ecpl

+

1

c2

(Es2 −Ecpl )

2

μ0i , ai , bi and ci are fitting parameters and Esj + / − Ecpl represents the transverse electrical field which is a physical parameter. Esj is the surface field and Ecpl the coupling one. The first term represents the inter-valley optical phonons, the second one the acoustic phonons dependence and the last term is for the surface roughness. Coulomb scattering is neglected because of the undoped silicon film. Inclusion of the dependence with the longitudinal field is done thanks to the saturation velocities vsati as in [29].

3.3.8 Charges Modeling 3.3.8.1 Charges Distribution The charge localization is given by the Fig. 3.17. For a given position x, the inversion charges in strong inversion are given by the Eq. (3.28) and the gate charges are given by Eq. (3.36). The total front and back gate charges are noted QG1 and QG2 . The front and back inversion charges are Qinv1 and Qinv2 respectively. These charges are coupled by the coupling charge Qcpl as discussed in the part 3.3. The inversion charges are partitioning between drain and source QD and QS . These all global charges are obtained by integration along the channel. VG1 Front gate QG1

VS

VD

0 QS1

Qinv1

QD1 L

Qcpl

Source QS2

Qinv2

QS

y

Drain QD2 QD

Back gate QG2 x

VG2

Fig. 3.17 Schematic description of charge localization of a symmetrical double gate MOSFET with independent gates

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3.3.8.2 Gate Charges Calculation The gate charges are calculated using [35]: QG1 = Qinv1 + Qcpl = W

QG2 = Qinv2 − Qcpl = W

L

qinv1 dx1 + W

L

0

0

L

L

qinv2 dx2 + W

0

qcpl dx1

(3.53)

qcpl dx2

(3.54)

0

Charge calculation is possible if we perform a change of variable from the position y to the quasi-Fermi level. For this, we use the conservation of drain current along the channel given by: Wμ dxj = − qinvj dVc (3.55) IDj After some algebra, the total gate charges can be analytically calculated as described by Y. Tsividis [35] for the bulk case. The Fig. 3.18 shows the front gate charge versus de front gate voltage in linear and saturation regime and when the back interface is in strong and weak inversion. The front gate charge is independent of the back gate voltage in strong inversion and at low drain voltage. However, at low front gate voltage, the gate charge is due the coupling field. This charge variation introduces a significant capacitance between the both gates. In addition, this coupling capacitance also appears in saturation, when the drain side is in weak inversion. 50.0 Front Gate Charge QG1 (fC)

VG2 = 0.1V 40.0

VDS = 0.1V

VG2 = 1V

30.0 20.0

Due to the coupling field

VDS = 1V

10.0 0.0 −10.0 0.0

0.4

0.8

1.2

1.6

2.0

VG1 (V)

Fig. 3.18 Front gate charge QG1 versus front gate voltage VG1 at several back gate voltage (VG2 = 0.1 and 1.0 V) in linear regime (VDS = 0.1 V – grey curves) and in saturation regime (VDS = 1.0 V – black curves). L = W = 1 μm, Tsi = 10 nm, Tox = 1 nm


77

1.0 VG1 = 1.0V, VG2 = 0.0V

Normalized Charge

VG1 = 1.5V, VG2 = 0.0V VG1 = 2.0V, VG2 = 0.0V

0.8

VG1 = 2.0V, VG2 = 2.0V Qinv / Q inv0

0.6

QS /Q inv0 0.4 QD /Q inv0 0.2 0.0

0.4

0.8

1.2

1.6

2.0

VG1 (V)

Fig. 3.19 Normalized drain, source and inversion charges, QD /Qinv0 , QS /Qinv0 and Qinv /Qinv0 respectively drain voltage VDS in strong inversion for several front gate voltage VG1 and several back gate voltage VG2 . L = W = 1 μm, Tsi = 10 nm, Tox = 1 nm

3.3.8.3 Drain to Source Charge Partitioning The drain and source charges are obtained from: QD = QD1 + QD2 = W

L

qinv1 0

Qs = Qs1 + Qs2 = Qinv1 − QD

x1 dx1 + W L

L

qinv2

x2 dx2 L

(3.56)

0

(3.57)

As for the gate charges calculation, these charges can be also calculated [35]. The Fig. 3.19 illustrated the analytical results for the total inversion charge and the drain and source charges versus drain voltage from several gate voltage. From these curves, the charge distribution doesn’t depend on the front and back gate voltages in saturation, the coupling field affects the gate charges only.

3.4 Short Channel Effects 3.4.1 Introduction When the core of the model is defined, short channel effects should be added, mainly because this transistor are processed for very short gate length. Short channel effects impact the electrical characteristics despite this device has a better immunity compared to a bulk MOSFET. Threshold voltage and subthreshold slope are mainly concerned but also the slope in saturation region.

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M. Reyboz et al. 70 VDS = 50mV 60

VG2 = −0.4V

50

L = 30nm

1E-07

L = 130nm

40

1E-09

30 1E-11

L = 30nm 20

L = 130nm 1E-13

10 0 −4.0

ID (A/ µ m)

ID (μA/μm)

1E-05

−2.0

0.0

0.2

0.4 0.6 VG1 (V)

0.8

1.0

1E-15 1.2

Fig. 3.20 Drain current ID versus front gate voltage VG1 at negative back gate voltage (VG2 = −0.4 V) in linear regime (VDS = 50 mv) for two channel length values (L = 30 and 130 nm). W = 1 μm, Tsi = 10 nm, Tox = 1 nm

As you can see on the following figure, the swing is degraded for a short channel device (curves in logarithmic scale) and the threshold voltage is lower (curves in linear scale) than for a long transistor (Fig. 3.20). To model these effects, the 2D Poisson equation should be used: d2 ψ (x, y) d2 ψ (x, y) q ni ψ (x, y) − Vc (y) + = exp (3.58) εsi ut dx2 dy2 Defining the origin at the middle of the silicon film, the limit conditions are: T ψ − si − T , y = V ox1 G1 2 ψ Tsi + T , y = V ox2 G2 2 (3.59) ψ (x, 0) = Eg 2 ψ (x, L) = Eg + V DS 2 Where Eg = ±2qΦM is the silicon bandgap. To solve this problem, many methods exist: charge sharing, parabolic approximation, conformal mapping, superposition theorem with green function or evanescent analysis mode [36–61], but only when the inversion charge is neglected. Consequently, the presented model of the subthreshold slope and the threshold voltage are valid in weak inversion.

3 Compact Modeling of Double Gate MOSFET for IC Design VDS = 5mV VG1 = 0.45V

170 S1 (mV/dec)

79

TCAD simulation

L = 30nm

Model 120

L = 130nm 70

−0.4

−0.2

0.0 VG2 (V)

0.2

0.4

Fig. 3.21 Front subthreshold slope S1 versus the back gate voltage VG2 at a front gate voltage equal to 0.45 V in linear regime (VDS = 5 mv) for two channel length values (L = 30 and 130 nm). Comparison between TCAD simulation (symbols) and the model (grey curves). W = 1 μm, Tsi = 10 nm, Tox = 1 nm

3.4.2 Subthreshold Slope The Fig. 3.21 illustrates the subthreshold slope obtained by TCAD simulation for two transistors with different channel lengths. We note that what whatever the gate length, the swing is higher than 60 mV/dec. This is due to the fact that gates are independently driven as discussed in part 3.1. Nevertheless, more smaller is the gate length, worse is the subthreshold slope. Short channel effects, more precisely the influence of the drain and source voltages on the gate control limits the channel creation. To model the subthreshold slope, we choose the superposition theorem approach combines with the evanescent mode analysis. This solution proposes writing the 2D surface potential as [59]:

ψ (x, y) = ψ1D (x) + ψS (x, y) + ψD(x, y)

(3.60)

After some algebra detailed in [59], the 2D surface potential becomes:

ψ (x, y) =

V G2 − V G1 V G1 + V G2 x + si 2 Tsi + εεox (Tox1 + Tox2 ) y b1 sinh π L−y + c sinh π 1 λ1 λ1 x + cos π λ1 sinh π λL

(3.61)

1

The scale length λ1 and the coefficients a1 , b1 and c1 , are given by X. Liang [59]. For more details, see also [60].

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M. Reyboz et al. 0.70

Vth1 (V)

0.66 0.62 0.58 TCAD simulation Model

0.54 0.50 10

30

50

VDS = 5mV VG2 = 0.0V 70 L (nm)

90

110

130

Fig. 3.22 Front threshold voltage Vth1 versus channel length L at low back gate voltage (VG2 = 0 V) in linear regime (VDS = 5 mv). Comparison between TCAD simulation (symbols) and the model (grey curves). W = 1 μm, Tsi = 10 nm, Tox = 1 nm

Consequently, with the previous expressions (3.11), the subthreshold slope can be easily calculated. A comparison between this model and numerical simulations is shown on the Fig. 3.21.

3.4.3 Threshold Voltage and the Subthreshold Factor Modeling As illustrated by the Fig. 3.22, the threshold voltage decreases when the gate length shrinks due to a lack of gate electrostatic control. With the decrease of gate length, the barrier between the source and the drain diminishes. The electrons need less energy to go from the source to the drain. The electron flux will be higher for the same gate voltage in the case of a short channel MOSFET than for a long one. Note that there is no reverse short channel effect (RSCE) because there is no pocket in the process. To model the threshold voltage versus the gate length, it is assumed that the contributions of the source and the drain on the potential are dominating in xmax and ymin : dψ (x, y) =0 dx dψ (x, y) ymin when =0 dy

xmax when

(3.62a) (3.62b)


81

Thus, using the Eqs. (3.10) and (3.61), the drain current in weak inversion can be written as: Δψ (xmax, ymin ) W V G1 − Vth1 2 n1 cox1 ut exp ID1 = −μ exp L n 1 ut ut VDS −1 (3.63a) × exp − ut Where,

Δψ (xmax , ymin ) =

2 b1 c1 cosh π sinh π

L λ1 L λ1

− b21 − c21 (3.63b)

In addition, considering the expression of the drain current in weak inversion in the case of Vth-based model, this one can be written as: V Gj − Vthj,sce VDS W 2 − 1 exp (3.64) nj coxj ut exp − IDj = −μ L ut nj,sce ut To derive the threshold voltage, we linearize Δψ (xmax , ymin ) around the 2D threshold voltage, Vthj,sce . Finally, identifying the Eq. (3.63a) with the Eq. (3.64), we obtain: −κ1 + κ12 − 4 ν1 σ1 Vth1,sce = Vth1 + (3.65a) 2 ν1 With, χ2 ν1 = 12 sinh2 πL − 21 cosh πL λ λ1 − 1 n 1 1 πL G2 κ1 = χ21 2 E2g − Vth1 +V + V cosh DS 2 λ1 − 1 Eg Vth1 +V G2 πL 2 2 G2 σ1 = −2 χ21 E2g − Vth1 +V cosh − + V DS 2 2 2 λ1 − 1 + VDS χ1 T T 2 λ12 tan π λox1 sin π 2λsi 1 1 ⎡ ⎤ χ1 = T sin π si λ T ⎢ ⎥ 1 si π2 Tox1 ⎣ 2 + T +T Tox1 ⎦ sin π ox1 ox2 λ1 (3.65b) The same expressions are obtained for the back channel permuting index 1 and 2.

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By consequence, the subthreshold factor is given by: 1 1 = n1,sce n1

Vth1,sce +V G2 Eg VDS χ 1 − cosh πL 2 + 2 − 2 λ1 + Vth1,sce +V G2 Vth1,sce +V G2 Eg Eg sinh πL cosh πL −2 − V2DS 2 − 2 2 + VDS − 2 λ λ 1

1

(3.66)

3.4.4 Short Channel Effect in Strong Inversion In saturation region, the main electrostatic effects are the DIBL (Drain Induced Barrier Lowering), which is included in the subthreshold slope and in the threshold voltage (see Section 3.2 and 3.3), and the channel length modulation effect (CLM). This effect is due to the drain biasing which creates a depleted area instead of the inversion charge, at the drain side, see the following picture. The drain current does no more saturate at Vdsat but still linearly rises. The CLM effect is often represented thanks to an Early voltage VEA (Fig. 3.23). To describe this effect, a classical model developed in 1977 by Y. A. El-Mansy and A. R. Boothroyd and adapted to a DG MOSFET is used [62]. The pinchedoff area corresponds to a reduction of the channel: from Lj to L j = Lj – ΔLj . j is

VG1 Front gate Front gate oxide ψss

ψsp

Source

ψsd Drain section

Source section

y

Tox1

ΔL Back gate oxide

Drain

Tox2

Back gate

L

VG2

x

Fig. 3.23 Schematic of a MOSFET where the silicon film was shared in two parts: the source and the drain sections. The drain section represents the pinched-off area


83

20.0 VG2 = 1.2V

TCAD simulation

ID (mA/ µm)

15.0

Model VG1 = 0 to 1.2V

10.0

5.0

0.0 0.0

0.2

0.4

0.6 VDS (V)

0.8

1.0

1.2

Fig. 3.24 Drain current ID versus drain voltage VDS for several front gate voltages (VG1 = 0–1.2 V) at high back gate voltage (VG2 = 1.2 V). Comparison between TCAD simulation (grey curves) and the model (symbols) with constant mobility. L = 30 nm, W = 1 μm, Tsi = 10 nm, Tox = 1 nm

the index equal to 1 or 2 corresponding to the front and back channels respectively. We suppose that each gate voltage affects exactly half of the silicon film. This assumption is right in strong inversion at both interfaces. Moreover, neglecting the transverse electrical field, we get: VDS − Vdsatj εsi Tsi ΔLj = Toxj ln 1 + (3.67) 3 εox 2 VEj VEj are fitting parameters. j is the index equal to 1 for the front gate and to 2 for the back one. Note that the interface coupling was not totally neglected. Indeed, Vdsat1 and Vdsat2 depend respectively on Vth1 (VG1 , VG2 ) and Vth2 (VG2 , VG1 ). Consequently, good results are obtained with this modeling as shown by the Fig. 3.24.

3.5 Conclusion In this chapter, a threshold voltage based model of double gate MOSFET with independent gates is described. The mathematical developments are focused on the model’s core with short channel effects. However, this model is not complete for circuit design. Quantum effects and ballistic transport must be taken into account as discussed in the previous chapter. In addition, leakage currents, such as gate tunneling currents or gate induced drain lowering (GIDL) can degrade device performances and should be implemented (this list is not exhausted). In the next chapters related to the circuit design, these two leakage currents are added in the model.

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These currents are meanly due to the very thin gate oxides. GIDL is a band to band tunneling current which appears when the gate voltage is negative (for an nMOSFET) and when the difference between the drain voltage and the channel voltage is not null. For the bulk MOSFET, this phenomenon is known and modeled [63]. However, this effect is not really physically modeled for double-gate MOSFET. Nevertheless, the model of Y.-K. Choi et al. can be easily adapted for DGMOS and introduced into the compact model with fitting parameters [64]. Concerning, the tunneling gate leakage currents, the effect is the same than for a bulk transistor [65–70] with some small differences. For undoped thin silicon film, the channel can not be in accumulation mode. As consequence, gate leakage currents are mainly due to overlap regions in this mode. The second difference with bulk is the absence of a gate to bulk current. Indeed, the gate current is partitioned between drain, source and overlap regions. To model this effect for double gate architecture, the gate current expressions published by K. M. Cao et al. can be adapted [70]. Finally, others significant effects can affect the device characteristics. For example, the access resistances and parasitic capacitances must be taking into account by the model. The self heating effect can degrades the on-state currents. All these effects are well known for fully depleted MOSFET with single gate and the models developed for this device architecture can be adapted for the double gate transistor.

References 1. Y. Taur, “An Analytical Solution to a Double Gate MOSFET with Undoped Body,” IEEE Electron Device Letters, vol.21, no.5, pp. 245–247, May 2000. 2. Y. Taur, “Analytical Solutions of Charge and Capacitance in Symmetric and Asymmetric Double-Gate MOSFET,” IEEE Transaction on Electron Devices, vol. 48, no. 12, pp. 2861–2869, December 2001. 3. Y. Taur, X. Liang, W. Wang and H. Lu, “A Continuous, Analytical Drain-Current Model for DG MOSFETs,” IEEE Electron Device Letters, vol. 25, no. 2, pp. 107–109, February 2004. 4. M. Chan, T. Y. Man, J. He, X. Xi, C. H. Lin, X. Lin, P. K. Ko, A. M. Niknejad and C. Hu, “Quasi-2D Compact Modeling for Double Gate MOSFET”, in Proceeding of Workshop on Compact Modeling, Nanotech 2004, pp. 108–113, Boston, MA, March 7–11, 2004. 5. J. He, X. Xi, M. Chan, A. Niknejad and C. Hu, “A Non-Charge-Sheet Analytic theory for Undoped Symmetric Double-Gate MOSFETs from the Exact Solution of Poisson’s Equation using SPP Approach,” in Proceeding of Workshop on Compact Modeling, Nanotech 2004, pp. 124–127, Boston, MA, March 7–11, 2004. 6. G. Baccarani, “A Compact Double-Gate MOSFET Model Comprising Quantum-Mechanical and Nonstatc Effects,” IEEE Transaction on Electron Devices, vol. 46, no. 8, pp. 1656–1666, August 1999. 7. T. Nakagawa, T. Sekigawa, T. Tsutsumi, M. Hioki, S. O’uchi and H. Koike, “Capacitance Model for Four-Terminal DG MOSFETs,” in Proceeding of Workshop on Compact Modeling, Nanotech 2006, pp. 800–803, Boston, MA, May 9–11, 2006. 8. J. M. Sallèse, F. Krummenacher, F. Prégaldiny, C. Lallement, A.S. Roy and C. C. Enz, “A Design Oriented Charge-Based Current Model for DG MOSFET and its Correlation with the EKV Formalism,” Solid-State Electronics, vol. 49, no. 3, pp. 485–489, March 2005. 9. F. Prégaldiny, F. Krummenacher, J.-M. Sallese, B. Diagne and C. Lallement, “A Closed-form Compact model for Symmetric Double-Gate (DG) MOSFETs,” MOS-AK Meeting, Grenoble, France, September 16th 2005.


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Chapter 4

Low Frequency Noise in Double-Gate SOI CMOS Devices Jalal Jomaah and Gérard Ghibaudo

4.1 Introduction Double Gate SOI-MOSFETs are attractive candidates for meeting the requirements of the devices miniaturization. The silicon film thickness, tsi being an extra scaling parameter in these devices, offers an additional degree of freedom for threshold voltage adjustment, through the back-gate voltage Vbg [1] thereby controlling the short channel effect (SCE) problems. However, since the carriers in these devices encounter two or more interfaces, the current transport and, hence the fluctuations, will be affected by the back interface, giving rise to coupling effects. The low frequency noise (LFN) being attributed to the fluctuations of the current in MOS transistors would thereby be influenced by the back gate quality and bias [2]. Indeed, excessive low frequency noise and fluctuations could lead to serious limitation of the functionality of the analog and digital circuits. It is well known that the LF noise is a serious concern for the RF IC design [3]. On the other hand, since it is sensitive to defects at the interface and in the dielectric layer, it could be also used as a reliable tool for technological evaluations [4]. A careful analysis is therefore necessary to identify the main noise sources and related parameters on which, the LF noise depends. In this chapter, recent issues about the low frequency noise are presented and discussed through experimental data obtained on advanced DG SOI CMOS generations, featuring the impact of thin film or coupling effects.

J. Jomaah and G. Ghibaudo IMEP-LAHC Minatec-INPG, 3 parvis Louis Néel, BP 257, 38016 Grenoble, France


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4.2 Low Frequency Noise Analysis 4.2.1 Carrier Number Fluctuations and Correlated Mobility Fluctuations In the classical carrier number fluctuation approach, the fluctuations in the drain current stem from the fluctuations of the inversion charge nearby the Si-SiO2 interface, arising from the variations of the interfacial oxide charge after dynamic trapping/detrapping of free carriers into slow oxide border traps. This interface charge fluctuations δQit can be equivalently equated to a flat band voltage variation δVfb = −δQit /(WLCox ). Moreover, in a more detailed analysis one should also takes into account the supplementary mobility change δμeff due to the modulation of the scattering rate induced by the interface charge fluctuations. The drain current fluctuations therefore read [5, 6]: δ Id = −gm δ Vfb − α Id μeff δ Qit

(4.1)

where gm is the transconductance, μeff is the effective mobility, α is the Coulomb scattering coefficient (≈104 Vs/C for electrons and 105 Vs/C for holes). This leads to a normalized drain current and input gate voltage noise SVg = SId /g2m for strong inversion given by, SId /Id2

= 1 + α μeff Cox Id /gm

2

gm Id

2 SV f b

(4.2a)

and SV g = SV f b [1 + α μ0 Cox (Vg − Vt )]2

(4.2b)

Where μ0 is the low field mobility, Cox is the gate oxide capacitance, Vt is the threshold voltage, SVfb = SQit /(WLC2ox ) with SQit (C2 /Hz/cm2 ) being the interface charge spectral density per unit area, W the device width and L the device length. The spectral density of the oxide interface charge depends essentially on the physical trapping mechanisms into the oxide. For a tunneling process, the trapping probability decreases exponentially with oxide depth x, so that the flat band voltage spectral density takes the form [7, 8], SV f b =

q2 k T λ Nt 2 fγ W LCox

(4.3)

where f is the frequency, γ is a characteristic exponent close to 1, λ is the tunnel attenuation distance (≈0.1 nm), kT the thermal energy and Nt is the volumetric oxide trap density (/eV/cm3 ).

4 Low Frequency Noise in Double-Gate SOI CMOS Devices

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It should be mentioned that Eq. (4.2) also apply to the non-linear regime of MOSFET operation [9]. Indeed, the drain voltage dependence of SId /I2d is naturally accounted for by that of the transconductance to drain current ratio squared (gm /Id )2 . This can been checked experimentally by comparing the respective variations with drain voltage Vd of SId /I2d and (gm /Id )2 .

4.2.2 Hooge’s Mobility Fluctuations In the Hooge model [10], the drain current noise results from the fluctuations of the carrier mobility through variations in the scattering cross section entering the collision probability likely due to phonons number fluctuations [11]. This leads to a flicker noise with amplitude inversely proportional to the total number of carriers in the device. The normalized drain current noise and input gate voltage noise in ohmic operation can then be written in the form [7, 12], SId q αh = 2 W L Qi f Id and SV g =

(4.4)

q αh (Vg − Vt ) [1 + θ (Vg − Vt )]2 W L f Cox

(4.5)

where Qi is the inversion charge, αh is the Hooge parameter (αh ≈ 10−4 –10−6 ) and θ is the mobility attenuation coefficient. Similarly, in the case of non-linear region of MOSFET operation, the inversion layer is no longer uniform along the channel and the normalized drain current can be expressed as [12]: SId q αh = f W L2 Id2

L 0

q αh dy = Qi (y) f W L2

Vd 0

W μeff d φc Id

(4.6)

qαh < μeff > Vd = f L2 Id where < μeff > is the average mobility along the channel. Indeed, in ohmic region, Eq. (4.6) reduces to Eq. (4.4). Therefore, in all the cases (ohmic and non-linear regions), the normalized drain current noise due to Hooge mobility fluctuations varies as the reciprocal drain current.

4.2.3 Coupling Impact on Fluctuations In Asymmetric Double Gate structure (Vg1 = Vg2 and Cox1 = Cox2 ) and considering that the noise source is the trapping/de-trapping of carriers with the oxide traps,

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two noise sources have to be considered due to the two silicon/oxide interfaces. Furthermore, each noise source can be associated to a flat band voltage fluctuation as it is the case for classical NMOS transistor [13]. If we assume that the opposite interface is depleted (Qi2 = 0) and that the two noise sources are not correlated (due to their spatial location), we can calculate the drain current spectral density. In the case of the carriers number fluctuations, we have: δ Id δ Id δ Vg1 δ ϕs1 δ Qi δ Qi (4.7) δ Id = δ Qi = δ VFB1 + δ VFB2 δ Qi δ Vg1 δ ϕs1 δ Qi δ VFB1 δ VFB2 The noise sources are related to the fluctuation of the front and back flat band voltages. Moreover, the coupling effects derive from the following expressions [14]: Csi + Cit1 Csi Qi1 + Qd /2 Vg1 = V f b1 + ϕs1 1 + − ϕs2 − (4.8a) Cox1 Cox1 Cox1 Qi2 + Qd /2 Csi + Cit2 Csi ϕs1 − (4.8b) − Vg2 = V f b2 + ϕs2 1 + Cox2 Cox2 Cox2 where Csi and Qd are the silicon film capacitance and the depletion charge. Cox , Cit , ϕs , Qi , Vg , Vfb are respectively the oxide capacitance, the interface state capacitance, the surface potential, the inversion charge, the gate and flat band voltages (with the number 1 for the front interface and 2 for the back one). By this way, the front surface potential ϕs1 is given by (using Eq. (4.8)): 2Qi2 +Qsi Csi i1 +Qsi − V + + V (1 + Csi /Cox2 ) Vg1 − V f b1 + 2Q2C g2 f b2 Cox1 2Cox2 ox1 (4.9) ϕs1 = 1 + Csi (1/Cox1 + 1/Cox2 ) We can observe that the front surface potential depends on the front and back interface characteristics. A similar equation can be obtained for the back surface potential. Then, using Eqs. (4.8) and (4.9), we finally obtained the drain current spectral density as: SId1 = g2m1 SV f b1 + c21 SV f b2 (4.10a) 2 2 (4.10b) SId2 = gm2 SV f b2 + c2 SV f b1 where gm1,2 is the front (back) transconductance (gm1,2 = dId1,2/dVg1,2 ), c1,2 is the front (back) coupling coefficient given by: c1,2 =

Csi

Cox1,2 1 +

Csi +Cit2,1 Cox2,1

(4.11)

where Csi , Cox1,2 , and Cit1,2 are the silicon film capacitance, the front (back) oxide capacitance and the front (back) interface state capacitance respectively and SVfb1 ,


93

SVfb2 are the two noise sources: SV f b1(2) =

λ kT q2 Nt1(2) 2 W LCox1(2) fγ

(4.12)

where λ is the tunneling constant, Nt1(2) are the front and back interface traps densities, f the frequency and γ the slope (0.8 < γ < 1.2). We can notice here, considering c1,2 as a constant, that Eq. (4.10) can be reduced to the classical relationship with an equivalent input gate voltage: SV g1 =SV f b1 + c21 SV f b2

(4.13a)

SV g2 =SV f b2 + c22 SV f b1

(4.13b)

When the back gate is accumulated, the carrier number fluctuations induced by the back oxide traps are screened by the accumulation layer, and thereby the only traps causing the tunneling of carriers to and from traps, are those of the front interface. Hence, the Double Gate device behaves as a bulk or a Partially Depleted SOI CMOS from the noise point of view. If now, we have a symmetrical Double Gate transistors and considering the same interface quality at front and back gates, we obtain c1 = c2 .

4.3 Results and Discussions It should be noted that Fully Depleted (FD) devices can be considered as asymmetric Double-Gate structure with thicker silicon film thickness, allowing a better understanding of coupling effect between front and back interfaces on noise behaviour. For that, N-channel Fully Depleted (FD) and Double Gate (DG) SOI CMOS technologies are studied. The front gate oxide tox is 2 nm for all devices. For the FD CMOS, the back oxide thickness, tBOX , is 400 nm and the silicon film thickness, tsi , is 15 nm, while for the double gate tsi is 6 nm. The channel doping in the FD devices is ∼2 × 1018cm−3 while the DG device have an undoped channel. In the Fig. 4.1, the normalised drain current power spectral density, SId /I2d , of a W/L = 25/0.8μm Fully Depleted device with the drain voltage, Vd , at 50 mV is plotted as a function of the drain current, Id , for different back gate voltages, Vg2 . In this plot, the solid line represents the front gate power spectral density SVg multiplied by the ratio (gm /Id )2 where gm stands for the gate transconductance. The correlation between these two curves confirms the results predicted by the 1/f noise model on carrier number fluctuations [6, 7]. In this model, the fluctuations of the drain current stem from those of the number of inversion charge near the silicon-silicon dioxide interface and the mobility due to the dynamic capture and release of free carriers into states located in the oxide near the interface. The normalized drain current spectral density is given by Eq. (4.2).

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Normalised Drain Current Power Spectral Density(/Hz)

10−7 FD N_MOSFET W/L = 25 / 0 .8um Vd = 50mV f=10Hz

10−8 10−9 10−10 10−11 10−12 10−8

Vg2 = −50V Vg2 = −20V Vg2 = 0V Vg2 = 20V Vg2 = 50V

10−7

(gm/Id)2.SVg

10−6 10−5 Drain Current(A)

10−4

10−3

Fig. 4.1 Normalized drain current power spectral density SId /I2d of a W/L = 25/0.8 μm FD NMOSFET in linear operation and f = 10 Hz for different back-gate voltages. Solid line: SVg (gm/Id) 2 for Vg2 = 20 V

As shown in the Fig. 4.1, varying Vg2 from −50 to 50 V, induces different noise levels, it could be seen that increasing the back gate voltage, increases the value of SID /I2D as well. To explain this effect, the coupling between the two interfaces should be taken into account. When the back gate is accumulated, the carrier number fluctuations induced by the back oxide traps are screened by the accumulation layer, and thereby the only traps causing fluctuations are those of the front interface. Hence the Fully Depleted device (or Asymmetric DG SOI CMOS) behaves as single interface device as a bulk or a Partially Depleted SOI CMOS transistor.When depleting the back interface, the carriers encounter two interfaces and the back oxide traps, which are no more screened, induce another source of capture and release for carriers, hence an extra source of noise. Thereby the noise level increases due to the coupling effect; this increase depends on the ratio of the back and front oxide trap densities and also the oxide thickness. Figure 4.2 shows the normalised drain current spectral density for the same device at drain current Id = 0.1 and 1 μA. The steady increase of both curves while depleting the back interface is obviously seen. Double Gate MOSFETs have been studied in both Single Gate (back gate voltage controlled separately, as FD devices) and Double Gate modes (front gate and back gate with the same voltage). In Fig. 4.3 the normalized drain current power spectral density of a double gate device with W/L = 1/0.05μm at Vd = 10 mV is plotted. The back gate of this device is shifted by 15 nm compared to the front gate [15]. The correlation between the SId /I2d curves and (gm /Id )2 × SVg reveals that the noise source similarly to the FD devices is the carrier number fluctuation. However, the impact of Vg2 is in contrast with that in FD devices, especially in weak inversion. Changing the back gate voltage from −0.4 to 0.8 V decreases the noise level (Fig. 4.4).


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Normalised Drain Current Power Spectral Density(/Hz2)

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Fig. 4.3 Normalized drain current power spectral density SId /I2d of a W/L = 1/0.05 μm DG N-MOSFET at linear operation and f = 20 Hz for different back-gate voltages. Solid line: SVg (gm /Id )2 for Vg2 = 0 V

In the studied double gate devices the silicon film is very thin (6 nm), and even by accumulating the back interface, decoupling the two interfaces is not possible, and thus the back gate would still have an effect on the device behavior. While increasing the back gate voltage, the charge is pushed away from both interfaces and so there would be a screening effect reducing the number of trapped carriers. In other words, moving the carriers away from the Si/SiO2 interfaces and increasing the distance between charges and the oxide traps reduces the tunneling rate into traps in either oxides and hence the LF noise.

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Fig. 4.4 Normalized drain current power spectral density SId /I2d of a W/L = 1/0.05 μm DG NMOSFET in linear operation and f = 10 Hz for different back-gate voltages for Id = 0.1 and 1 μA

When the back interface is inverted (Vg2 = 0.8 V), at low Vg1 , the fluctuations in the back channel gives rise to a higher noise amplitude as compared to the case where the back channel is in depletion mode (Vg2 = 0.4 V). By depleting the front interface, a reduction of noise could be observed due to the increase of the distance between the charges and the interfaces [16]. The different noise dependence on the back gate bias between the FD and DG devices is induced by the different film thicknesses. Depleting the back interface in the FD devices creates a second separate channel and thereby a second source of low frequency noise. In the DG devices, increasing the back gate voltage increases the vertical electric field from the back interface towards the middle of the film. Since the silicon film is thin, the combination of this electric field and that induced by the front gate, through out the film would be strong enough to push the charges away from both interfaces. Consequently, instead of having two separate channels at each interface as it is the case in the FD devices, DG devices exhibits either a wide uniform channel all over the film or a channel, which is denser at the interfaces but still existing in the whole film. It has already been mentioned in earlier studies, that volume inversion could result in a lower low frequency noise level [17, 18]. The coupling effect in FD-SOI devices can be modelled by considering the capacitive coupling between the front (1) and back (2) interfaces, yielding for weak inversion and depletion the established relations (4.13a, b) for the front and back gate input gate voltage noise [19]. Equation (4.13) allow evaluating the ratio between the total input noise seen at each interface and the noise corresponding to just one interface as a function of the film thickness as illustrated in Fig. 4.5. This evaluation has been made considering equal flat band voltage noise at both interfaces i.e. SVfb1 = SVfb2 .(tox1 = tox2 and Nt1 = Nt2 ). Since the coupling effect is reinforced by reducing the silicon film thickness, the above relation implies that, thinner devices have higher total noise


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Fig. 4.6 The ratio of total noise on the noise of the front interface versus Vg1 for different modes of operation of the back interface (Simulations done using FlexPDE)

levels due to the coupling effect when the back interface is not screened. We can also notice that, when the silicon film tSi is relatively thick, the total noise is almost equal to the front gate noise level (SVgtotal = SVfb1 ) due to the weak coupling effect between front and back interfaces. Figure 4.6 shows the results of a numerical simulation of the noise level at different Vg2 , highlighting two main behaviours at low and high front gate voltage Vg1 . When the front channel is in weak inversion and at Vg2 = −0.5 V (accumulated back interface), the total noise is only due to the front interface one (SVgtotal = SVfb1 ).

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108 109 1010 1011 1012 1013 Density of inversion charge(q / c m2)

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Fig. 4.7 Normalised drain current power spectral density as a function of the inversion charge density for different back interface trap densities

At Vg2 = 0 V, both front and back interfaces equally contribute to the total noise of the device (SVgtotal = 2.SVfb1 ). Finally, for Vg2 = 0.5 V, when the conduction is mainly controlled by back channel, the noise is determined by the back interface quality (SVgtotal = 3.SVfb1 ). At strong inversion, the front interface contribution for different back voltages tends to a constant value equal to 75% of the total noise. This ratio is almost equal to the predicted one by relation (4.13) indicated by solid line in Fig. 4.3. The impact of the back interface quality on the total noise is shown on Fig. 4.7. If we consider an ideal back interface (Nt2 = 0), the total noise is only due to the front interface fluctuations. This case is equivalent to accumulated back interface regime. Taking now into account the back interface contribution in the case of the same interface quality at front and back gates (Nt1 = Nt2 ), an increase in the total noise level can be noticed. When the back trap density is twice more than the front one (Nt2 = 2.Nt1 ), the total noise is one decade higher. Thus, back interface quality influences the total noise amplitude, especially in depletion and inversion back gate modes. The model presented above could not be applied for the device with very thin silicon film thickness ( Toxb ) The front gates of these devices are controlled by the m logic inputs. 2(m − 1) control signals are applied to the back gates to configure the logic function dynamically.

6 Logic Circuit Design with DGMOS Devices

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Fig. 6.13 Generic DGMOS dynamic-logic reconfigurable cell (DG-DLRC) Table 6.5 General configuration code table for m-input DG-DLRC Function

NAND NOR INV a

Dx present in expression

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Unless D1 is present in the expression (in this case, Cxa = V+ )

Dynamic logic is generally more compact (in terms of device count) than static complementary logic when implementing complex logic functions, since it does not require a complementary p-device network and thus demonstrates reduced total parasitic capacitance and silicon area, in particular for cells with a large number of inputs. However, this approach requires clock lines and imposes more stringent constraints on device off currents, since leakage leads to a deterioration of calculated results. A simple set of configuration codes (i.e. back-gate voltage sets) can be applied to configure an m-input reconfigurable cell to a particular logic function from those available (NAND, NOR, INV). After having identified the type of function, the presence of each input Dx (∀x ∈ {2, m}) is evaluated, enabling the corresponding configuration codes {Cxa , Cxb } to be extracted from Table 6.5. For the NAND-configuration, 0 V is applied to Cxa such that transistor Mxa operates as a normal n-transistor (i.e. on or off for Dx equal to logic “1” or “0”

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respectively) when Dx is present in the expression. If Dx is not in the expression, then transistor Mxa is turned completely on with Cxa = V+ . Independently of the presence of Dx in the expression, V− is applied to Cxb to turn transistor Mxb off (regardless of the logic value of Dx ). An asymmetric device must be used for Mxb to increase the front-gate threshold voltage and thus enable complete turn-off in the NAND-configuration. The value of V− must be chosen with respect to the gate breakdown voltage limitation. The resulting effective threshold voltage is chosen such that the functionality of the NAND-configuration is met without affecting that of the NOR or INV configurations. In the NOR-configuration and when D1 is present in the expression, V+ is applied to Cxa in order to significantly decrease the threshold voltage of Mxa and turn it completely on, regardless of the logic state of the signal at the front gate. If D1 is not in the expression, then transistor Mxa must be turned off with Cxa = V− . If Dx is in the expression, then 0 V is applied to Cxb for normal operation of transistor Mxb , otherwise Mxb is turned off with Cxb = V− . In the INV-configurations, a single branch is activated to switch with D1 only (by turning Mxa completely on with Cxa = V+ , and turning Mxb completely off with Cxb = V− ) or with Dx only (by turning Mxa completely off with Cxa = V− , and selecting normal operation with Mxb by applying Cxb = V− ). For the latter operation, it is also possible to use Cxa = 0 V to include Mxa in switching with Dx (all other control voltages in this branch should then be set to V+ ), but this results in non-deterministic timing behavior (since the drive strength depends on the state of D1 ).

6.4.2 Static-Logic Reconfigurable Cell DG-SLRC Static logic styles generally feature better noise immunity than dynamic logic, and thus are well-suited to applications that require resistance to harsh environments. The novel m-bit static-logic reconfigurable cell structure (DG-SLRC) is shown in Fig. 6.14. As well as the n-device branch described in the previous section, DGSLRC requires a p-device branch composed of: • One network containing m parallel asymmetric DGMOS devices (with Toxf > Toxb ) • A stack of (m − 1) symmetric DGMOS devices As before, the front gates of these devices are controlled by the m logic inputs. 4(m − 1) control signals are applied to the back gates in order to configure the logic function at the output dynamically. The configuration codes {Cxa , Cxb } to be extracted for the various functions are given in Table 6.6. In the NAND-configuration and when Dx is present in the expression, 0 V is applied to Cxa for normal operation of transistor Mxa , while V− is applied to Cxb . Since Mxb is asymmetric, this device is turned completely off, regardless of the value of Dx . V+ is applied to Cxc for normal operation of Mxc , while 0 V is applied

m-1 stacked symmetric p-devices


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Fig. 6.14 Generic DGMOS static-logic reconfigurable cell (DG-SLRC) Table 6.6 General configuration code table for m-input DG-SLRC Function

NAND NOR INV a Unless

Dx present in expression

Dx absent from expression

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Cxb

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0 0 0

D1 is present in the expression (in this case, Cxa = V+ )

to Cxd in order to turn Mxd on regardless of the value of Dx . If Dx is not present in the expression, then Mxa is turned completely on (Cxa = V+ ) and Mxb completely off (Cxa = V− ). Here again, 0 V is applied to Cxd in order to turn Mxd on regardless of the value of Dx . V+ is applied to Cxc ; this voltage does not ensure that the p-type DGMOS Mxc is switched completely off, although the off-state is nearly reached due to the asymmetric structure of Mxc with high Toxf . However, this situation means that power performance is likely to be poor, and the output logic “0” level is degraded (simulation results in the 2-input case show 60 mV). To avoid this, the strength (i.e. W/L) of Mxc must be reduced. In the NOR-configuration and when D1 is present in the expression, V+ is applied to Cxa in order to ensure Mxa is always on, while 0 V is applied to Cxb for normal

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operation of transistor Mxb (if Dx is in the expression; otherwise Mxb is turned off with Cxb = V− ). If D1 is not in the expression, then transistor Mxa must be turned off and V− is applied to Cxa . In the p-device network, V+ is applied to Cxc to approach the off-state of Mxc if D1 is in the expression (0 V and completely on if not) and V+ is applied to Cxd for normal operation of Mxd (if Dx is in the expression; otherwise Mxd is turned on with Cxd = 0 V). In the INV-configurations, a single branch is activated to switch with D1 only or with Dx only. In the first case, in the n-device network Mxa is turned completely on with Cxa = V+ , and Mxb completely off with Cxb = V− ; while in the p-device network we apply Cxd = 0 V to turn Mxd completely on, and Cxc = V+ to approach the off-state for Mxc . In the second case, we turn Mxa completely off with Cxa = V− , and select normal operation for Mxb by applying Cxb = 0 V in the n-device network; while in the p-device network we set Cxd = V+ to achieve Dx -dependent switching, and Cxc = 0 V to turn Mxc completely on.

6.4.3 Tests with Two-Input DG-xLRC In this section we consider the implementation, in both dynamic- and static-logic forms, of the previously presented reconfigurable cell in its 2-input form. The design of the cells was based on the FDSOI DGMOS technology model mentioned earlier, and simulations were performed throughout with a calculation rate of 50 Mbit/s (i.e. data period = 20 ns), using signal rise and fall times of 40 ps. The load capacitance considered was 5 fF.

6.4.3.1 Two-Input DG-DLRC Figure 6.15 illustrates the 2-input reconfigurable cell (with logic inputs D1 = A and D2 = B), implemented with DGMOS devices and based on dynamic logic. Transistors M1 , M4 , and M5 depict symmetric DGMOS devices (i.e. symmetric oxide thicknesses and work-functions for the front and back gates) with connected front and back gates. Transistor M2 depicts a symmetric DGMOS device, while transistor M3 depicts an asymmetric DGMOS device. Both M2 and M3 use independent gate control. For this mixed (symmetric and asymmetric devices) cell denoted DG-DLRC mixed, asymmetric biasing is used with {V+, V−} = {1.0, −0.5 V}. Another variant of the cell, DG-DLRC asymm, uses only asymmetric DGMOS devices. The use of the same device type in the cell can be more convenient since it eases circuit fabrication. In this case, Vdd = 0.6 V to achieve symmetric gate biasing on C2a and C2b where {V+ , V− } = {+0.6, −0.6 V} while using a maximum absolute gate-source and gate-drain voltage value of 1.2 V.6 6

The devices we used in our simulations have been shown experimentally to operate correctly with gate voltages up to 1.5 V.


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0.35μ/ 0 / 1 3μ M5

clk

F

0.5μ/ 0 .13μ B

C2a 0.5μ/ 0 .13μ

M2

C2b

B M3 0.5μ/ 0 .13μ M1

A

clk

0.5μ/ 0 . 13μ M4

Fig. 6.15 Two-input DG-DLRC Table 6.7 Truth table of two-input DG-DLRC C2a

C2b

F

0 V+ V+ {0, V− } V− X

V− 0 V− 0 V− V+

A·B A+B A B 1 0

Table 6.7 shows the logic state of the cell output (node F) with respect to the applied back gate voltages on the C2a and C2b terminals, as a 2-input implementation of Table 6.5. As can be observed from Table 6.7, the cell can implement the NAND, NOR and INV logic functions. This cell has been evaluated using the simulation conditions described previously. The simulation waveforms for DG-DLRC mixed are shown in Fig. 6.16, where the switching from one configuration to another, as can be observed at the output F, is obtained through the dynamic configuration of signals C2a and C2b . Similar waveforms are obtained with DG-DLRC asymm. The power and delay performance characteristics of both variants are summarized in Table 6.8 for each function configuration. The reconfigurable cell performance (average power and worst case delay) depends not only on the activity factor, the total switched capacitance and device number lying on the critical path, but also on the different back gate biasing used in each configuration. These factors affect, differently from one configuration to another, the total drive current, sub-threshold and gate leakages, and consequently the total power and the worst case delay.

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A·B A+B A B

DG-DLRC mixed

DG-DLRC asymm

Av. power

Worst-case delay

Av. power

Worst-case delay

256 nW 476.7 nW 361 nW 476.3 nW

140.6 ps 740.6 ps 140.6 ps 667 ps

33.2 nW 96.2 nW 71.9 nW 46.8 nW

540 ps 2,590 ps 2,590 ps 2,440 ps

6.4.3.2 Two-Input DG-SLRC The 2-input static reconfigurable cell (with logic inputs D1 = A and D2 = B) is shown in Fig. 6.17. The truth table of the cell is shown in Table 6.9, as a 2-input implementation of Table 6.6. As with DG-DLRC, this cell implements the NAND, NOR and INV functions. Each logic function is obtained by applying the relevant configuration codes in terms of back gate biases C2a−d , as shown in Fig. 6.18. Again, the static variant can also be implemented using all asymmetric DG devices (as DG-SLRC asymm). In this case Vdd = 0.6 V and symmetric biasing is used with {V+ , V− } = {+0.6, −0.6 V}. Correct functionality is observed with this cell due to (i) the reduced Vdd /Vt ratio (Vt ≈ 0.4 V with Vbg = 0 V) thus allowing


159

1.0μ/ 0 . 13μ B

C2d M6 0.25μ/ 0 . 15μ 1.0μ/ 0 .13μ M5

A

C2c

B M4

F 0.5μ/ 0. 13μ C2a

B M2

0.5μ/ 0 . 13μ C2b

B M3 0.5μ/ 0 .13μ

A

M1

Fig. 6.17 Two-input DG-SLRC Table 6.9 Truth table of two-input DG-SLRC C2a

C2b

C2c

C2d

F

0 V+ V+ {0, V− } V− X

V−

V+

0 V+ 0 V+ 0 V+

A·B A+B A B 1 0

0 V− 0 V− V+

V+ V+ 0 0 V+

cut-off of transistor M3 when V− is applied to its back gate and (ii) the small W/L ratio for transistor M4 combined with the small Vdd /Vt ratio. The simulation results obtained from both DG-SLRC mixed and DGSLRC asymm are shown in Table 6.10.

6.4.4 Comparison to Conventional LUT We have carried out experiments to evaluate the performance gain of DG-xLRC with respect to conventional solutions. While this technique can be considered to open up many possibilities for new system-level programming paradigms, it is also

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Fig. 6.18 Simulated configuration of the two-input DG-SLRC to NAND, NOR and INV functions Table 6.10 Simulated performance figures for the two-input DG-SLRC Function

A·B A+B A B

DG-SLRC mixed

DG-SLRC asymm

Av. power

Worst-case delay

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Worst-case delay

1,189 nW 182 nW 2,800 nW 397 nW

590.5 ps 309.4 ps 111.5 ps 295.3 ps

125.9 nW 196.8 nW 330.8 nW 101.8 nW

1,620 ps 660 ps 660 ps 1,740 ps

possible to make a direct comparison to conventional m-bit MUX-based look-up tables (LUTs). It should be noted that the aim of this section is to provide an objective comparison at the circuit level using individual characteristics, rather than a system-level comparison where the impact of cell characteristics is not so clear.

6.4.4.1 Gate Area and Memory Requirements For 2-, 3- and 4-input LUTs and DGMOS-based reconfigurable cells, we evaluated the gate area (i.e. channel dimensions only, Fig. 6.19), and the required number of memory cells to retain the configuration codes (Fig. 6.20). The gate area results reflect the exponential and linear growth of transistor count in LUTs and DG-xLRCs respectively. For LUTs, the transistor count grows with

6 Logic Circuit Design with DGMOS Devices Fig. 6.19 Comparison of m-input DG-xLRC and CMOS-LUT gate area

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CMOS-LUT

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DG-DLRC

gate area/ um2

14

DG-SLRC

12 10 8 6 4 2 0

Fig. 6.20 Comparison of m-input DG-xLRC and CMOS-LUT no. of memory cells

2-input

3-input

4-input

3-input

4-input

18 16 14

CMOS-LUT DG-DLRC

no. memory cells

DG-SLRC 12 10 8 6 4 2 0 2-input

∗ Nmux (2m − 1) (where m represents the number of inputs and Nmux represents the 2 – 1 MUX transistor count, usually equal to 12), while transistor count grows with 3 + 2(m − 1) and 2 + 4(m − 1) for DG-DLRC and DG-SLRC respectively. Total area comparisons incorporate extra interconnect requirements (an extra -V power line, precharge and evaluation lines for the dynamic cell, double inputs) with some reduction in configuration lines for certain variants. The complete layouts (including all routing but excluding configuration memory cells and precharge/evaluate logic buffers) for the 2-input dynamic and static cells show area reduction factors of 6.5 and 4.7 respectively as compared to the CMOS-LUT, instead of 7.8 and 4.9 considering gate area only. The precharge/evaluate logic and signal distribution tree was not included in the analysis.

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6

Fig. 6.21 Number of available functions for m-input reconfigurable cells

The number of memory cells required has an impact not only on auxiliary hardware requirements, but also on configuration time. For LUTs, this increases with 2m , while for DG-DLRC and DG-SLRC it is equal to 2(m − 1) and 4(m − 1) respectively. It should of course however be borne in mind that while a LUT potentially offers m 22 configurations, DG-xLRC offers rather less. The number of available functions corresponding to m-input cells is plotted in Fig. 6.21 and compared to the figures for CMOS-LUTs for values of m ranging from 2 to 6. In practice, the number of inputs that the reconfigurable cells can reasonably handle is 4. Beyond this figure, the number of series devices in a stack becomes too high, leading to insufficient fanout. It is clear from this figure that a direct transposition of this cell as a LUT in conventional configurable logic blocks will result in limited flexibility. For this reason we believe that further work must be carried out to explore new programming paradigms to benefit from the cell performance (and in particular its reduced configuration memory requirements for easier dynamic reconfiguration) at system level.

6.4.4.2 Average Power and Worst-Case Delay We have also carried out detailed simulations of the 2-input solutions to compare average power (Fig. 6.22) and worst-case delay performance metrics (Fig. 6.23). To this end we have simulated the LUTs in a 65 nm CMOS technology, scaling standard cell transistor dimensions to match the 130 nm gate lengths used in the reconfigurable cells for reasons of model validity. Identical simulation conditions


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3000 CMOS-LUT

2500

DG-DLRC_mixed

av. power/ nW

DG-DLRC_asymm

2000

DG-SLRC_mixed DG-SLRC_asymm

1500 1000 500 0 NAND

NOR

INVA

INVB

Fig. 6.22 Comparison of 2-input DG-xLRC and CMOS-LUT average power 3000 CMOS-LUT

2500

DG-DLRC_mixed

worst-case delay / ps

DG-DLRC_asymm

2000

DG-SLRC_mixed DG-SLRC_asymm

1500 1000 500 0 NAND

NOR

INVA

INVB

Fig. 6.23 Comparison of 2-input DG-xLRC and CMOS-LUT worst-case delay

were used, i.e. 50 Mbit/s calculation rate, load capacitance CL = 5 fF, 40 ps rise and fall times on inputs. Comparisons of the CMOS-based LUT figures were carried out for the four operational functions with respect to both DG-DLRC and DG-SLRC, in mixed and all-asymmetric variants. These figures clearly show that, apart from the mixed implementation of DGSLRC, total power performance is systematically better with DG-xLRC solutions, in one case achieving an average of over 90% reduction in power over the four function configurations. For static power, it should be noted that all configurations of both static and dynamic logic cells (except the unconditional ‘0’ configuration) bias N-type and P-type DGMOS back gates to 0 V/V- and V+ respectively (leading to

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either the same or lower Ioff as with connected gates), except when an unconditional short is required – in which case the off current of the branch is defined by another transistor in the equivalent configuration to that of a connected gates transistor. This means that the low Ioff values of DGMOS transistors are exploited in the proposed cells (our simulations show Ioff = 0.7 pA for an N-type DGMOS of 0.5/0.13 μm with Toxf = 2.5 nm and Toxb = 1.2 nm) – however the Ion values are lower than a connected-gates equivalent transistor since the back gate is set to 0 V or V+ for Nand P-type conducting transistors respectively. The peak current value for a transistor with the previously cited characteristics (i.e. for Vfg = V+ and Vbg = 0 V) is around 50 μA. This has an impact on the cell drive current, and the consequences are visible in Fig. 6.23 in terms of the mediocre worst-case delay comparison. The best achievement is an overall 20–30% delay penalty for the mixed solutions. Additional technology and circuit optimization should enable some tradeoff between power and speed through the improvement of cell drive current (by increasing device width) – but clearly the power, gate area and Ioff will all deteriorate by such a strategy. Overall recommendations are that (i) the all-asymmetric device reconfigurable logic cells using {V+ , V− } = {0.6, −0.6 V} are best-suited to low power reconfigurable circuits operating with moderate speed, while (ii) the mixed-device reconfigurable cells using {V+ , V− } = {1.0, −0.5 V} can operate at comparable speeds to CMOS-LUTs but only the dynamic-logic variant shows benefits in terms of power.

6.4.5 Summary In this section, we have presented a new style of reconfigurable cell dedicated to programmable logic applications and based on the DGMOS device, particularly exploiting those with asymmetric oxide thicknesses for the front and back gates and independently controlled gates. Significant gate area reductions are possible compared to conventional CMOS LUT techniques (between 80–95%) while configuration memory requirements are also reduced (up to 60%). The 2-input reconfigurable cell used as a benchmark was implemented in both static and dynamic logic styles. Simulation results in FDSOI DGMOS technology of the proposed cell have shown that it can be used either as an all-asymmetric device variant with low Vdd (0.6 V) in low power reconfigurable applications (up to 90% power reduction is possible) or as a mixed-device variant with a higher Vdd (1 V) to achieve comparable speeds to CMOS-LUTs (20–30% penalty).

References 1. J.-G. Fossum, K. Kim and Y. Chong, “Extremely Scaled Double-Gate CMOS Performance Projections, Including GIDL-Controled Off-State Current”, IEEE Trans. Electron. Devices, vol. 46, no. 11, pp. 2195–2199, November 1999.


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2. K. Roy, H. Mahmoodi, S. Mukhopadhyay, H. Ananthan, A. Bansal and T. Cakici, “DoubleGate SOI Devices for Low-Power and High-Performance Applications,” in Proceedings of the International Conference on Computer Aided Design (ICCAD), pp. 217–224, San Jose, CA, November 2005. 3. T. Dao, “Advanced Double-Gate Fully-Depleted Silicon-on-Insulator (DG-FDSOI) Device and Device Impact on Circuit Design & Power Management,” in Proceedings of the IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), pp. 99–103, Austin, TX, May 2004. 4. J.-P. Colinge, “Silicon-on-Insulator Technology, Materials to VLSI,” Kluwer, Dordrecht, Third Edition, 2004. 5. M.-H. Chiang, K. Kim, C. Tretz and C.-T. Chuang, “Novel High-Density Low-Power HighPerformance Double-Gate Logic Techniques,” in Proceedings of the IEEE International SOI Conference, pp. 122–123, San Jose, CA, October 2004. 6. S. Mukhopadhyay, H. Mahmoodi and K. Roy, “Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50 nm Double-Gate MOSFET”, in Proceedings of the IEEE International Symposium Quality of Electronic Design (ISQED), pp. 490–495, San Jose, CA, March 2005. 7. T.-H. Lee “The Design of CMOS Radio-Frequency Integrated Circuits,” Cambridge University Press, Cambridge, 1998. 8. I. Hassoune, “Design and optimization of Digital Circuits for Low-Power and Security Applications,” Ph.D. thesis, Université Catholique de Louvain, Belgium, 2006. 9. L.O. Hill, D.O. Pederson and R.S. Pepper, “Synthesis of Electronic Bistable Circuits”, IEEE Trans. Circuit Theory, vol. CT-10, pp. 25–35, 1963. 10. V. Dessard, “SOI Specific Analog Techniques for Low-Noise, High Temperature or Ultra-Low Power circuits,” Ph.D. thesis, Université Catholique de Louvain, Belgium, 2001. 11. D. Levacq, C. Liber, V. Dessard and D. Flandre, “Composite ULP Diode Fabrication, Modeling and Applications in Multi-Vth FD SOI CMOS Technology”, Solid State Electron., vol. 48, no. 6, pp. 1017–1025, June 2004. 12. D. Levacq, V. Dessard and D. Flandre, “Ultra-Low Power Flip-Flops for MTCMOS Circuits”, in Proceedings of the IEEE International Symposium Circuits and Systems (ISCAS), vol. 5, pp. 4681–4684, Kobe, Japan, May 2005. 13. I. Hassoune, A. Neve, J.-D. Legat and D. Flandre, “Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell,” in Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 189–197, Santorini, Greece, September 2004. 14. J.-M. Wang, S.-C. Fang and W.-S. Feng, “New Efficient Designs for XOR and XNOR Functions on the Transistor Level,” IEEE J. Solid State Circuits, vol. 29, no. 7, pp. 780–786, July 1994. 15. I. Hassoune, I. O’Connor, “On the Performance of Double-Gate MOSFET Circuit Applications,” in Proceedings of the IEEE Northeast Workshop on Circuits and Systems (NEWCAS), pp. 558–561, Montreal, Canada, August 2007. 16. P. Beckett, “A Fine-Grained Reconfigurable Logic Array Based on Double Gate Transistors,” in Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT), pp. 260–267, Hong Kong, December 2002. 17. S. Kaya, H.F.A. Hamed, D.T. Ting, G. Creech, “Reconfigurable Threshold Logic Gates with Nanoscale DG-MOSFETs,” Solid State Electron., vol. 51, no. 10, pp. 1301–1307, October 2007.

Chapter 7

SRAM Circuit Design Bastien Giraud, Olivier Thomas, Amara Amara, Andrei Vladimirescu, and Marc Belleville

7.1 Introduction Today’s mobile computing and communication devices such as video phone, handheld video games, etc., represent the most important factors driving the need for low power design. The commercial success of these devices depends significantly on the duration of autonomous operation. This class of products therefore requires low power consumption as well as high or medium performance, which in turn depends on the technology and the design techniques used. For cost and reliability issues the preferred components for implementation of state-of-the-art portable devices are System-on-Chip (SoC) ICs. The SoC integrates many functions such as digital, memory, analog mixed-signal, and often radio-frequency functions, all on one chip. To satisfy requirements of multimedia applications, SoCs embed Static-RandomAccess-Memory modules (SRAM), which occupy more than 60% of the total SoC area and are responsible for a large portion of the total power consumption. Therefore, the SRAM module is required to have both high operating performance to deal with multimedia applications and low power consumption to prolong battery life. Active power consumption of CMOS logic circuits increases quadratically with supply voltage; hence, minimizing the supply voltage is one of the most effective ways to reduce energy usage but unfortunately this comes at the expense of lower speed. To get the best trade-off, supply voltage and threshold voltage scaling along with process is needed. However the increase of leakage current limits the threshold voltage reduction as well as the supply voltage scaling. Moreover, in 45 nm technology and below, voltage scaling becomes very complex due to the difficulty of the SRAM operation. In fact, in order to achieve very high density, the SRAM cell is implemented with the smallest size MOS transistors, which in B. Giraud, A. Amara and A. Vladimirescu ISEP, 21 rue d’Assas, 75006 Paris, France O. Thomas and M. Belleville CEA-LETI Mintatec, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France


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turn are more and more impacted by the increase of process fluctuations. It results in many obstacles to overcome to achieve low-voltage operation, such as adequate read margin, write ability and operating speed [1]. Other challenges in 45 nm and below are increased process parameter variability, increased leakage due to Vt reduction, gate tunneling and gate-induced drain leakage (GIDL), and, soft error rate (SER) degradation due to reduced capacitances and supply voltage. Numerous solutions have been proposed in literature to deal with these issues such as additional parasitic capacitance at the storage nodes [2–4], double-Vt transistors, high-Vt transistors being used in the memory cell and low-Vt transistors in the peripherals [5] and finally dual VDD with higher VDD dedicated to the cell. All of these techniques can be combined, i.e. a high VDD and high Vt for the cell, which improves the stability, the SER, the performance and finally the power consumption. However these techniques are conflicting with technology scaling that aims to take maximum advantage of feature size reduction. The challenges raised by 45 nm and finer technologies in bulk CMOS along with the limited solutions raise the urgency to investigate new structures and devices. A brief overview of the state of the art shows that multi-gate devices hold promise to overcome the above issues. The first SRAM cell based on FinFET transistors was announced in 2002 by IBM [6]. Later Samsung announced a FinFET SRAM cell showing an SNM (Static Noise Margin) of 280 mV at 1.2 V. Hitachi demonstrated recently [7] that Fully-Depleted Silicon-on-Insulator technology combined with Double-Gate devices leads to not only a drastic reduction of the process variability but also to three orders of magnitude reduction in power consumption and 20% improvement in speed. IMEC has announced a high-density, triple-gate memory cell featuring a symmetrical butterfly characteristic with an SNM as high as 240 mV at 1.0 V power supply. Some of the presented cells work at ultra low voltage as well. In this chapter an in-depth SRAM study in Independently Driven Double-Gate technology is presented by analyzing several cell topologies and proposing new ones. In conventional transistors the drain current is controlled by a ‘single’ gate voltage, whereas in DG structures two independent gates can be available to adjust the drain current. This double controllability offers a new degree of freedom, which enables novel architectures. However, the design of such SRAM cells involves the study of several characteristics, which are all interdependent. Criteria will be defined and compared in order to underline the best compromise necessary to achieve an ideal cell. These results are provided for a High-K, Metal-gate DGMOS technology with a 45 nm drawn, 25 nm electrical gate length. Section 7.2 reviews the architecture, building blocks, basic operation key design parameters and issues of an SRAM. The analysis revolves around the established 6T SRAM cell. Section 7.3 presents variations of the 6T cell implemented in DGMOS. Several architectures are described which take advantage of the second gate in order to improve operational characteristics as well as performance. A quantitative comparison of all cells based on an ITRS DGMOS predictive model concludes this section.

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Section 7.4 describes other possible SRAM cell implementations, which use less than six transistors and in some cases deviate from the symmetrical structure.

7.2 SRAM Memories 7.2.1 SRAM Architecture The standard architecture of an SRAM memory is depicted in Fig. 7.1, and consists of three main blocks: the storage matrix, the decoder logic and the I/O interfaces.

7.2.1.1 Memory Matrix The memory matrix is a table, which is comprised of 2n rows and 2m columns and stores 2n+m bits. Each bit is stored in one memory cell. Every cell can be randomly addressed by selecting the appropriate wordline (WL) and bitline (BL), respectively, activated by the row and the column decoders. Large size matrices may be divided into sub-blocks, as illustrated in Fig. 7.2. Many techniques have been proposed to minimize the power consumption of SRAM memories [8,9]. As an example, an advanced addressing technique, denoted as DWL (Divided Wordline) [10], uses a two-stage row decoder, where each wordline is replaced by one main wordline and several local sub-wordlines, as depicted in Fig. 7.3. This splitting method brings two main benefits, delay and static power consumption reduction. In fact, only one main wordline and one local wordline are enabled

Fig. 7.1 Standard memory architecture

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Read / W rite

Bloc selection R

Row decoder

Matrix L 2n+m−1

Precharge

Bloc selection L

Precharge

Matrix R 2n+m−1

Read/ W rite

Data in/ out

Fig. 7.2 Memory matrix organized in banks Main row decoders

Local row decoders 1

Sub-array 1

Local row decoders k

Sub-array k

2m/k cells

Fig. 7.3 Divided wordline scheme

at the same time, reducing the number of memory cells activated and therefore the number of gate capacitances by the number of wordline levels [10]. The only drawback is that two metal layers are needed. Other techniques have also been proposed to decrease the memory power consumption, bitline partition [8] and selective precharge [11] being the most common.

7.2.1.2 Decoder Logic Independently of the organization of the memory, decoders are circuits that achieve the communication between the memory matrix and the I/O interfaces. In write mode they allow the transfer of data to be written from the I/O interfaces to the desired memory cells of the matrix selected by the address. In read mode they allow the transfer of data to be read from selected memory cells to the I/O interfaces.


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There are two main types of decoders: the row decoder that selects the worldline to be activated to access a memory row and the column decoder that selects the bit-lines (column) of memory cells to be read or written. Depending on the memory organization, row and column decoders can have different complexities, but their detailed presentation is beyond the scope of this chapter.

7.2.1.3 I/O Interfaces I/O interfaces translate the external signals of the SRAM memory, such as word address, clock and control signals, into internal signals, which enable the corresponding peripheral circuits. They also transfer the data between the memory and the external circuits.

7.2.2 Basic Operation of an SRAM Memory

2m

PRE

BLL

PRE WL

Precharge

BLR

The basic operations of a memory array are Read and Write. Nevertheless a third operation, denoted as the precharge, is most of the time needed to refresh the system after or before one of the previous operations. Figure 7.4a depicts a conceptual memory array, whereas Fig. 7.4b shows one of the 2m columns, consisting of a precharge circuit (PRE), 2n cells, one column decoder (YLi) and one read and write circuit (R/W). Figure 7.4c shows a conventional 6-transistor SRAM cell, which consists of two cross-coupled inverters and two access transistors whose source/drain terminals are connected to the bitlines BLL and BLR and whose gates are connected to WL.

WL

Cell MLL

WL

L=‘1’

Cell

buffers

YLm−1

R/W

(a)

MDL

MAR MDR

R/W I/ O L

R/W I/O

Dout

MLR R=‘0’

MAL BLL

YLi YL0 Din

WL

2n

I/OR

(b)

(c)

Fig. 7.4 (a) SRAM array; (b) column structure; (c) conventional 6T SRAM memory cell

BLR

array

BL

BL

WL

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7.2.2.1 Precharge Precharge is an operation that precedes a read cycle. It aims to initialize the bitlines to the same voltage, in order to make sensing of the state of a cell possible, avoid errors, increase the performance and reduce the overall power consumption. Sometimes the precharge circuits may remain active even during the read cycle, especially when current sense amplifiers are used to read the data stored in the memory. Usually, the precharge equalizes the bitlines to VDD, but in some memories, the bitlines are precharged at 0 V or intermediate values such as VDD /2.

7.2.2.2 Read Operation Once the precharge operation is completed, the selected wordline is enabled, activating the access transistors of the desired row. By turning on the access transistors of a row, a small difference voltage, Vs, is generated between each bitline pair, connected to it. The bitline difference Vs, is detected and amplified by the sense amplifiers.

7.2.2.3 Write Operation A write operation starts by applying a voltage corresponding to the binary information to be stored in the cell, to the I/O lines from the Din buffers and write circuits. Then, this voltage difference is transferred to the bitlines by activating the YL signal. The wordline is enabled and the memory cell flips to the state corresponding to the voltage difference. The write operation is completed by turning off the wordline and the column decoders.

7.2.3 SRAM Memory Cell Design Parameters A memory cell must be designed very carefully for reliable operation and minimum area. Three working modes can be distinguished among which two are active, the read and write operations, and one is passive, the retention mode. The key parameters for performance characterization in the three modes are summarized below: • Retention – Adequate stability in retention to preserve the stored data – Minimum static current for low standby power applications • Read – Adequate stability in read mode for reliable operation – Maximum read cell current to achieve short read access time


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• Write – Adequate cell write margin for reliable operation – Adequate cell write disturb for reliable operation – Maximum write cell current to achieve short write access time • Area – Minimum cell size for high density Compared to digital circuit design, specific and very aggressive layout design rules are used for the memory cell, in order to obtain the minimum area without impacting the reliability of the memory. Some of these criteria lead to opposite design constraints. To achieve high density, low power and high performance at the same time, the design space must be carefully explored to obtain the best trade-off.

7.2.3.1 Read Operation Static-Noise-Margin (SNM) The stability of a SRAM cell in read mode is characterized by the read static noise margin (SNM) when the wordline is activated. The SNM is defined in [12] as the maximum DC noise voltage (±Vn) that can be tolerated at the cell storage nodes (L and R) without changing the stored bit (see Fig. 7.5a). The two DC noise voltage sources Vn are placed in series with the cross-coupled inverters with the worst-case polarity at the internal nodes of the cell. The SNM is obtained by drawing and mirroring the voltage transfer curves (VTC) of the crosscoupled cell inverters and the access transistors together forming the equivalent

+Vn L

F1

R -Vn

F2

Vout(F1) ; Vin(F2) (V)

A

F2 B

-Vn

+Vn F1

Vin(F1) ; Vout(F2) (V)

(a)

(b)

Fig. 7.5 A flip-flop consisted of two inverters with static-noise voltage source Vn (a); Graphical representation of read SNM (b)

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inverters F1 and F2 of Fig. 7.5a, and, locating the largest square of the two delimited by the eyes of the butterfly curve (see Fig. 7.5b). The SNM value corresponds to the side of the smallest square. When Vn is equal to the SNM, the VTCs move horizontally and vertically until the stable point A and the meta-stable point B coincide.

Read Access Time (RT) One of the main timing criteria in memory circuits is the time needed to access the data stored. The read access time measurements are performed on a column of M cells initialized with the worst-case data pattern, where 100% of the cells in retention are in the opposite state to the one of the selected cell. The measurement metric is the length of the time slot starting when the word line reaches 50% of VDD and ending when a difference of 100 mV appears on the bit line pair at the input of the sense amplifier.

7.2.3.2 Retention Mode Static Power Consumption In some applications, such as portable devices, memories have a quite low activity and their leakage seriously impacts the battery lifetime. For sub 100-nm technologies sub-threshold current, gate tunneling and GIDL currents are the dominant leakage

WL = ‘0’ VDD

MLR

MLL

MAR L = ‘1’

BLR = ‘1’

BLL = ‘1’

MAL R = ‘0’

MDR

MDL

NMOS (ON)

ISTH

IGOFF

PMOS (OFF)

IGID/SL

IGON

Fig. 7.6 Leakage current contributions in a standard 6T SRAM cell


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mechanisms. Figure 7.6 illustrates these three contributions in a conventional 6T SRAM cell. They lead to three dominant leakage paths: (i) the leakage from VDD to ground through the cell inverters, (ii) the leakage from the bit-lines (BLL/R ) to ground and (iii) the leakage from BLL/R to the word line (WL). Estimated leakage must take into account all these contributions; for example in 65 nm CMOS-Bulk low-power technology the gate current (IGOFF/ON ) represents roughly 20% of the total leakage current, while in 45 nm node it represents more than 45% [13]. In deca-nanotechnologies leakage current reduction is critical for achieving low power in SoCs. This is especially important for SRAM modules, which need to retain their data while the other SOC modules may simply be switched off. To achieve low standby power, many techniques have been proposed. Two main approaches exist: a process-based one, using dual-VT (ex: LVT PMOS and HVT NMOS) [14] or a design-based approach by controlling the cell node voltages (WL, BLL/R , VDD, V SS, VPWELL and VNWELL) [13]. These leakage reduction techniques must not have a noticeable impact on SRAM cell stability.

Retention-Noise-Margin (Hold-SNM) Typically the cell stability is analyzed in read mode. With the leakage reduction techniques, it must also be analyzed in retention mode. The method to measure the RNM is similar to the one used in read mode (see Section 7.2.3.1) with the wordline inactivated and the access transistors switched off.

7.2.3.3 Maximum Number of Cells per Column The maximum number of cells per column depends on the ratio of the current of the cell being read (ICELL ) and, the access-transistor leakage current of a cell in retention mode (ISBPG ), see Fig. 7.7. This N-Bit Line factor, is a factor of merit on the column functionality, the higher the NBL factor, the higher the number of cells that can be placed per column.

7.2.3.4 Write Operation Write Margin Figure 7.8a represents the write margin (WM) defined as the minimum voltage difference between the bitlines necessary to flip the activated cell, i.e., the voltage difference for node R that switched from 0 to VDD , reaches 90% of VDD.

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L = ‘1’

R = ‘0’

ICELL WL = ‘0’

ISBPG x 2n−1

L = ‘0’

R = ‘1’

ISBPG

BLR = ‘1’

BLL = ‘1’

ICELL

Fig. 7.7 NBL Factor = ICELL /ISBPG

Fig. 7.8 Write margin (a); Write time chronogram (b) for a cell whose bitlines are precharged at high voltage

Write Access Time Figure 7.8b refers to the memory speed in write mode with respect to the activation of the wordline. The write delay is measured between the time when WL reaches 50% of VDD and the time when node R reaches 50% of VDD.


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Fig. 7.9 Write disturb (a); write disturb after several write operations (b) for a cell whose bitlines are precharged at high voltage

Write Disturb Write disturb refers to disturbances caused during a write operation to non-selected cells sharing the same bitlines. Figure 7.9a illustrates the problem for a cell whose bitlines are precharged at high voltage. The write disturb for this non-selected cell corresponds to the length of the time starting when the BLL reaches 50% of VDD and ending when node R, which should store a “0”, reaches 90% of VDD . Disturbance after Repeated Critical Writing Operations The problem corresponds to the worst case of the previous disturbance. It happens in cells in retention mode during repeated operations of writing on other cells sharing the same bitlines. At the end of each precharge cycle and after two consecutive write operations, the voltage of storage node L in Fig. 7.9b, may not return to a voltage as high as at the end of the previous precharge. After a number of write operations the L node voltage approaches VST , the switching threshold voltage of the cell. This write disturb corresponds to the maximum number of critical write operations before the stored data is lost. Both previous phenomena occur in cells that are in the same state as the initial state of the cell being written. Only high-density cells can be affected by these disturbances. 7.2.3.5 Critical Charge SRAMs are particularly susceptible to soft errors because its critical charge (Qcrit), corresponding to the minimum charge collected by a storage node required to upset

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an SRAM cell, is particularly small [2]. This charge can be generated by radiation phenomenon such as alpha particles and cosmic-ray neutrons. With device scaling, low-power designs, and increased circuit density, the SER is a growing concern. The notion of critical charge is used to assess the SER sensitivity of circuits. In SRAM cell, the collection of charge generated in a radiation event can be modeled as a current pulse (Iα ) connected between the high logic level storage node and the ground. The magnitude of the current pulse is increased until the cell flips, and Qcrit is determined as the charge delivered by this critical current pulse. The Qcrit value is evaluated by integrating the current until the cell flips (tf ), as illustrated in Fig. 7.10 (see Eq. (7.1)). Qcrit =

t f

Iα ∂ t

(7.1)

0

The I α current pulse shape, used to model the charge collection and diffusion mechanisms of a junction, is typically expressed as a double exponential [15] of the type: I(t) = I0 . [exp(−β1 .t) − exp(−β2 .t)]

A 3.0e–5

Current (A)

2.5 Current pulse

2.0 1.5 1.0 0.5 0.0

0.0

Voltage (V)

V 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 0.0

1.0 1.5 2.0 2.5 3.0 3.5 4.0 5.0e–9 S Time (s)

V(R) Flip point

V(L)

1.0 1.5 2.0 2.5 3.0 3.5 4.0 5.0e–9 S Time (s)

Fig. 7.10 Reaction of a SRAM to particle [16]

(7.2)


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Where β1 t, β2 t are the pulse rise time and decay time constants and I0 the magnitude of the current induced by the radiation event. In practice Qcrit is estimated by using a triangular shape for Iα as shown in Fig. 7.10, and, integrating the area under the current up to the time point when the cell changes states. This topic will not be addressed in this chapter, but it is expected that DGMOS SRAMs will have, like other SOI devices, a reduced sensitivity to a single event upset, SEU, compared to Bulk devices.

7.3 Double Gate 6T SRAM Memories The planar DGMOS, like the FinFET, is a Double-Gate transistor with two channels and interface coupling, as shown in the schematic view (Fig. 7.11). Figure 1.2, presented in technology chapter, displays the TEM view [17] of a transistor fabricated in the LETI DGMOS process. By modulating one gate voltage, the threshold voltage of the opposite channel will be affected [18]. Table 7.1 lists the main electrical parameters and their standard deviations, in parentheses, relative to process fluctuations, extracted from measurements. The supply voltage VDD is maintained at 1.2 V. The minimal values of gate length and width are 50 and 100 nm, respectively. Fig. 7.11 Cross-sectional schematic of a double-metalgate planar DGMOS front gate Toxf Tsi

source

drain Toxb back gate

buried oxide substrate

Table 7.1 Device parameters Symbol

Label

Nominal value

L (nm) W (nm) VT (mV) μ(cm2 /V/s) TOX (nm) TSI (nm) Racc (Ω · μ m)

Gate length Gate width Threshold voltage Mobility at low field Oxide thickness Silicon thickness Access resistance

50 (0.4) 100 (2) 325 (15) 254 (5) 1.2 (0.012) 10 (0.4) 400 (80)

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VBG = 1.2V

Drain current (A)

1,0E−04 1,0E−05 1,0E−06 1,0E−07 1,0E−08

SYM

1,0E−09

VBG = 0V

1,0E−10

PA

1,0E−11

FA

1,0E−12 0

0,2

0,4

0,6

0,8

1

1,2

Front gate voltage (V)

Fig. 7.12 IDS vs.VFGS at Vds = 1.2 V for different back gate voltages Vbg for NMOS

Figure 7.12 illustrates the NMOS simulated drain current as a function of the front gate voltage when the back gate is connected to ‘0’ and VDD . The first set of curves, with square markers, represents the Ids-Vgs characteristics for a symmetrical NMOS, SYM, with equal TOX for both gates. The two gates of symmetrical transistors have the same impact on the drain current. The curves entitled partially asymmetrical (PA), with diamond markers, show Ids-Vgs curves for an asymmetrical transistor, which is used for specific SRAM cells. In this case the front and back oxide thicknesses have been adjusted at TOXFG = 1.2 nm and TOXBG = 3.5 nm, respectively. The increase of TOXBG reduces its controllability of the channel and leads to the increase of leakage current, for a low voltage applied to the back gate. The Ids-Vgs curves entitled fully asymmetrical (FA), with circle markers, are for a predictive asymmetrical transistor. The threshold voltage difference between FG and BG has been increased by keeping the same values for TOXFG = 1.2 nm and TOXBG = 3.5 nm as for the PA device, but changing the metal used for the backgate; the threshold voltage of the BG is raised in this way from 325 to 800 mV.

7.3.1 DGMOS with Tied Gates 7.3.1.1 Conventional 6T Cell The 6T cell shown in Fig. 7.13 is the most popular SRAM cell, and the most widely used in the industry. The input and output of one inverter are connected to the output and input of the other inverter, respectively. Therefore the retroactive flip-flop allows the data storage. WL is the wordline activation signal. If WL is equal to zero, the cell is in retention mode and thanks to the cross-coupled inverters the data remain stored in the internal nodes L and R. When WL is active, the cell can be accessed either in read or write mode.


181

Fig. 7.13 6T cell

In read mode, the access transistors (MAL and MAR ) are ON and one of the bitlines previously precharged to VDD starts discharging until a given voltage difference between the bitlines is reached, which is amplified by a sense amplifier. In write mode, the access transistors are ON and depending on the data to be written in the cell, one of the bitlines is driven LOW until the cell flips to the opposite state if the previous state and the current state have opposite values. To read and write safely the cell, sizing correctly the transistors is a major concern.

7.3.1.2 Sizing Methodology The different working modes introduced in Section 7.2.3 impose often contradictory requirements on cell sizing. Tradeoffs have to be carefully established. This is mainly the case for the SNM and WM criteria [19] [20]. In read mode, the method consists in determining the storage node value which presents the highest probability to flip first. In the example of Fig. 7.14a, the R = ‘0’ node is the most unstable in read mode. The R node voltage must be less than the switching threshold voltage of the inverter connected to the high logic level storage, node L. The stability condition at this node, Eq. (7.3), is derived from Kirchhoff’s Current Law (KCL) for the currents shown in solid arrows in Fig. 7.14a. IG−L L + IOFF−LR + ION−AR ≤ ION−DR

(7.3)

According to this inequality and by neglecting the IG−LL and IOFF−LR , the read stability is directly proportional to the linear current flowing through the driver transistor and inversely proportional to the saturated current of MAR . The condition in Eq. (7.3) is satisfied for a cell ratio CR, Eq. (7.4), between MDR and MAR , often set to a value higher than 2: CR =

(W /L)MDR (W /L)MAR

(7.4)

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L=‘1’

R=‘0’

BLL

MAL

READ

MAR

MDL

(a)

MDR

BLR

WRITE

MLL

(b)

Fig. 7.14 Current relative to the critical storage node in read mode (a); sizing influences on read stability and writing criteria (b) for 6T cell

In write mode, the write margin WM depends on the voltage divider between the supply voltage of the cell and the bitline (BLL ), formed by the load transistor (MLL ) and the access transistor (MAL ) connected to node L. A write operation is correctly completed if the L node voltage goes down below the switching threshold voltage of the inverter (MLR , MDR ) connected to R. To improve the WM, the current flowing through MLL must be lower than the current flowing through MAL . Usually, the pull up ratio PR (Eq. (7.5)), between MLL and MAR , is often as close to 1 as possible, while ML transistors are set to the minimum size: PR =

(W /L)MLL (W /L)MAL

(7.5)

Figure 7.14b illustrates the impact of transistor sizing on the write margin, left side of the cell, and on read stability, right side of the cell, relative to the storage nodes containing a high logic value and a low logic value, respectively. In deca-nanometer technologies, it is more and more difficult to reach a good write margin (WM) in conjunction with a good read margin (SNM) due to the increase of process variations [6] in addition to the larger memory capacity. Industry targets 100 ppm failures for 10Mbit SRAM per chip, while the threshold voltage variation in mass-produced devices today is between 50 and 100 mV. Because of the reduction of the cell operating window (SNM versus WM), new 6T SRAM cell architectures are needed.

7.3.2 Innovative 6T SRAM Cell Architectures To improve the SRAM cell electrical characteristics, many innovative 6T SRAM cells have been proposed in multiple gate technology, such as DGMOS, FINFET and Ultra-thin-BOX FDSOI. All of them take advantage of the independent biasing of the second gate to increase the CR and PR ratios. To do so, two main approaches


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have been extensively investigated: a static one, cutting off the second gate, or a dynamic one, dynamically controlling the CR and/or PR ratios with feedback while setting the wordline signal according to the operating mode. These approaches are presented and discussed in this section.

7.3.2.1 Independent Gate Biasing SRAM Cell Static Approach As described above the read and write noise margins are correlated to the CR and PR ratios. To improve the read and write margins, the CR ratio must be increased while the PR ratio must be decreased. However, their ratios are limited by the cell aspect ratio for optimum area. To increase the stability while taking advantage of the second gate in multiple-gate technology, Hitachi [7] proposed the SRAM cell architecture depicted in Fig. 7.15. For this structure the access- (MA) and the load transistors (ML) have been weakened by connecting their back-gates to ground and VDD , respectively. Thus, the stability condition, Eq. (7.3) is drastically improved while the degradation of the write margin caused by weakening MA, is reduced by also weakening ML. Therefore, this cell architecture improves the SNM/WM tradeoff compared to a conventional 6T cell. This cell is a good candidate for low power applications, but has limited performance due to the reduction of the MA current, leading to the reduction of the read cell current.

Dynamic Approach In [18], the CEA/LETI-MINATEC proposed a 6T-2WL cell characterized by two word-lines connected to the front and back gates of the access transistors. This new architecture, depicted in Fig. 7.16, consists in connecting the second gate of the access transistors according to the operating mode. During a read operation signal

Fig. 7.15 Hitachi 6T SRAM cell

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Fig. 7.16 6T-2WL SRAM cell

WWL MLL

MLR

L=‘1’

R=‘0’

MDL

MDR

MAL

BLL

BLR

MAR

RWWL

WEN

Read mode

Write mode

RWWL

WWL

DATA

0

1

Fig. 7.17 Timing diagram of a read and write operation of the 6T-2WL SRAM cell

RWWL (Read-Write-WL) is activated while WWL (Write-WL), is disabled. During a write operation both word lines are activated. Figure 7.17 illustrates the read and the write operating modes of the 6T-2WL cell. This configuration improves both the read and write margins by weakening the current flowing through the access transistors in read mode (increasing the CR ratio), and reinforcing the current in write mode (reducing the PR ratio). Compared with the Hitachi 6T cell, the 6T 2WL cell gives a better read and write margin trade-off. Now regarding the cell performance, the 6T-2WL cell is also limited by a lower read current than the conventional 6T cell. However a higher read current can be achieved by applying a low voltage on WWL. To compensate for the SNM degradation, the driver transistor width (WMD ) can be increased. As shown in Fig. 7.18, the read delay measured when WWL equals 200 mV is improved by 30% without degrading the SNM. This simulated result is obtained for a WMD equal to 110 nm. Figure 7.19 depicts the 6T Berkeley Pass-Gate Feed-Back (PGFB) cell presented in [21]. The cell presents a read SNM drastically improved with neither leakage current nor area penalty thanks to the feedback connection that dynamically controls the access transistors. This technique consists in connecting the second gate of the access transistors to the storage node. Thus, the pass-gate transistor on the node storing a low logic


185

300

100%

V(WWL) (mV)

200 150

80% 70% SNM = 102-mV @ FS, 0.72-V

60% 50% 40%

100

30% 20%

50

RD delay (%) @ SF, 0.72-V

90% 250

10% 0

0% 76

80

90

100

110

120

WD (nm) V(WLWR)

RT

RT versus V(WLWR)

Fig. 7.18 Read delay WC (SF, 0.72 mV) variation versus: (1) MD width (WD) and (2) WWL voltage when SNM WC (FS, 0.72 mV) equals 102 mV Fig. 7.19 PGFB 6T SRAM cells

level is weakened, MAR and node R in Fig. 7.19, reducing its ability to pull up the storage node during a read operation and leading to a sizeable SNM improvement. In [22] the authors proposed also the PGFB + PUWG (Pull-up Write Gating) 6T SRAM cell. A write control signal in the PGFB 6T cell architecture is added, to compensate for the degradation of the write margin caused by weakening MA. As illustrated in Fig. 7.20, one of the two gates of the load transistors (ML) has been connected to a Write Word-Line (WWL). WWL is set to VDD in write mode to limit the drain current of the ML transistor connected to the high logic level node, so that the write margin is greatly improved. In read mode however, setting one of the two gates of the transistor to VDD as in the case of the Hitachi cell, leads to a degradation of the SNM. Therefore, in read

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Fig. 7.20 PGFB + PUWG 6T SRAM cell

WWL WL VDD

VDD

MLL

MLR

L = ‘1’

R = ‘0’

1.2

VWWL = 0V VWWL = 0.7V VWWL = 1.2V

VR (V)

1 0.8 0.6 0.4 0.2 0

0

0.2 0.4 0.6 0.8 VL (V)

(a)

1

1.2

Read SNM (mV)

MAR MDL

BLR

BLL

MAL

MDR

175 170 165 160 155 150 145 140 135 130 0

0,2

0,4

0,6

0,7

0,8

0,9

WWL (V)

(b)

Fig. 7.21 Graphical representation of read SNM (a); SNM versus WWL (b) of the PGFB + PUWG 6T SRAM cell (TT, 1.2 V, 27◦ C)

mode, WWL has to be lower than VDD for sufficient charge injection at the high logic level node in order to pull out the upper shoulders of the butterfly curves and at the same time reduce the low logic level voltage (see Fig. 7.21a), as explained in [22]. The WWL voltage can not be lowered too much since it turns both ML transistors on, which degrades the SNM. Figure 7.21b shows the SNM variation versus WWL voltage based on simulations done in typical conditions (TT, 1.2 V, 27◦ C). As one can notice, in this example, an optimum WWL voltage is reached around 0.7 V. In order to increase SRAM circuit density, 4T SRAM cells have been developed. The 4T cells are typically characterized by an excellent write margin but suffer from poor retention and read stability and are sensitive to write disturb. A Hybrid 6T SRAM cell proposed in [23] is shown in Fig. 7.22; it consists of two crosscoupled inverters and two PMOS access transistors whose source/drain terminals are connected to the bitlines (BL) and to the internal storage nodes L and R. The front gates of the access transistors are connected to the wordline (WL) and the source of the load transistors while their back gates are connected to the opposite


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Fig. 7.22 6T Hybrid

storage nodes. The front gates of the load transistors are connected to VDD. Due to the PMOS access transistors, the WL is set to V DD in retention mode and to 0 V in read and write. Due to its inventive architecture, this cell benefits from the advantages of both 4T and 6T cells according to the operating mode. When the cell is in retention mode, WL is equal to one, the sources of the load transistors are directly connected to V DD and the cell acts as a 6T memory cell. When the cell is accessed in read or write mode, WL is equal to zero and the cell acts as a load-less 4T memory cell. The cell architectures based on feedback cannot be directly implemented in a memory matrix with standard DGMOS technology. Biasing of the back gate with the high logic level of one of the two storage nodes sets the NMOS access transistor to the “on” state in all operating modes, i.e. in retention as well as read or write modes. This leads to electrical conflicts between the cells sharing a column, implying disturbance phenomena such as write disturb. To make the feedback cells functional, the current flowing through the access transistors in retention mode must be reduced to a value close to the leakage current. To do so, asymmetrical DGMOS transistors are needed (see the introduction to this section). In this configuration, the transistors are characterized by unequal drain currents for the same voltage applied to either the front or the back gate. Thus, in the cell, the storage nodes are connected to the gate giving the lowest current, i.e., the back gate in our case. According to this condition, the feedback leads to a threshold voltage modulation of the access transistors.

7.3.2.2 Electrical Results in Typical Conditions This section presents the simulated electrical characteristics defined in Section 7.2.3 for the various DG SRAM cells described above. The simulations have been carried out under typical conditions: typical process (TT), 1.2 V power supply (VDD ) and a temperature of 27◦ C. For the timing analysis, the read access time (RT) measurements have been done on a column of 64 cells initialized with the worst-case data pattern. To quantify and compare the advantage of each cell, they have been sized

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Table 7.2 Device parameters of symmetrical and fully asymmetrical DGMOS SYM transistor

FA transistor

1.2 1.2 325 98.5 525

1.2 3.5 800 66.2 8.44

TOXFG (nm) TOXBG (nm) Vt BG (mV) ION (μA) IOFF (pA)

Table 7.3 Electrical characteristics for 6T cells 6T

6T 6T Be. 6T Be. 6T-2WL 6T Hybrid Hitachi PGFB PUWG + PGFB

Transistor type

Sym.

Sym.

FA

FA

Sym.

FA

Retention stability (mV) Read stability (mV) Write margin (mV) Iread (μA) Ileak (nA) ISBPG (pA) NBL (×104 ) Write time (ps) Read time (ps) 64 cells per column Normalized area

357 170 777 55.7 1.35 19.2 290 90 88 1

342 252 1,018 22.2 1.35 19.2 116 160 184 1.3

467 346 1,058 13.8 0.04 2.5 558 144 281 1

429 335 888 13.8 0.04 2.5 558 128 284 1.29

357 286 777 22.2 1.35 19.2 116 90 185 1.4

371 399 477 7.9 0.03 7.3 109 254 1,490 1.3

with the same transistor dimensions as a standard 6T cell used as reference. The 6T cell has been designed in order to reach a static noise margin (SNM) higher than 150 mV with a good write margin (WM). The simulations have been performed with a predictive DG-MOSFET model [24] based on the ITRS forecast values. The 6T, 6T-2WL and 6T-Hitachi cells are based on symmetrical transistor (SYM) and the 6T PGFB, 6T PUWG + PGFB and 6T Hybrid cells are based on fully asymmetrical (FA) transistors. Table 7.2 gives the process and electrical parameters of the transistors. To reduce the back gate current of the FA transistor, the threshold voltage has been increased by 475 mV, reducing the Ion current by 30% and the Ioff current by 98% compared to the SYM device. The Ion/Ioff ratio of the FA transistors has thus improved from 1.88 × 105 to 7.84 × 106. Table 7.3 summarizes the experimental results. The cell results have been normalized in Table 7.4 with respect to the results of the conventional 6T cell. It is apparent from Table 7.4 that in the non-conventional cells, the read SNM is significantly improved, between 48% and 135%. However, the conflicting constraints between read and write operations of the cell entail a WM degradation for the 6T-Hitachi (−31%), 6T PGFB (−36.2%) and the 6T PUWG + PGFB (−14.3%) cells. For these cells, the WM degradation derives from the reduction of the drive current of access transistors needed to improve the SNM. For the 6T-2WL and 6T Hybrid cells, the mechanisms that improve SNM do not affect the WM. Therefore the WM of the 6T 2WL cell is not degraded while the WM of the advantageous


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Table 7.4 Percent increase/decrease of electrical characteristics with respect to the 6T DG cell (100%)

Hold SNM Read SNM WM Ileak WT RT

6T

6T Hitachi

6T Be. PGFB

6T Be. PUWG + PGFB

6T-2WL

6T Hybrid

100 100 100 100 100 100

−4.20 48.2 −31.0 0.0 −77.8 −109

30.8 104 −36.2 97.0 −60.0 −220

20.2 97.1 −14.3 97.0 −42.2 −223

0.0 68.2 0.0 0.0 0.0 −110

3.92 135 38.6 97.8 −182 −1,590

architecture of 6T Hybrid cell is improved by 38.6%. Globally, despite a degradation of the WM for the three cells, the trade-off between the cell stability and the cell write ability is improved. As with the SNM and WM trade-off, the interdependence between cell stability and cell performance must be considered. Improving the SNM inevitably leads to a reduction of the cell performance. The RT and WT degradation comes from the reduction of the drive current of the access transistors. The 6T-2WL cell gives the best performance/stability tradeoff thanks to its similar architecture with the 6T cell in write mode. The RT and WT of cells based on asymmetrical transistors are further deteriorated due to the reduction of the drive current of the transistors. With regard to cell leakage, the cells comprised of fully asymmetrical DGMOS are less leaky due to the increase of threshold voltage to satisfy operating conditions. For the cells based on symmetrical transistors, the leakage currents are the same as the 6T due to the same transistor bias in retention mode. Performance results of the cells can be plotted as Design Space Curves (DSC), see Fig. 7.23. The DSCs allow to quickly assess the benefits and limits of the new cell architectures on the electrical characteristics compared to the conventional 6T SRAM cell. The DSC is a radar graph; for each criterion, the values have been normalized to the best result of the memory cells. The periphery corresponds to the best case, while the center is the worst case. The DSCs consist of two main parts: the right-hand side represents the stability criteria, while the left-hand part represents the performance and the power consumption criteria. It can be concluded that the second gate of the DGMOS technology gives one more degree of tuning to improve the cell stability and write ability while degrading the cell’s response and power consumption. Therefore, taking into account all the SRAM cell specifications, the cells presented appear as good candidates for low voltage applications. This study has been performed with the same cell sizing which was initially used for the conventional 6T architecture. Observe that this sizing is not optimal for the other cells, such as, for instance, the 6T Hybrid that is characterized by high SNMs and longer access times due to the P-type access transistors which present a lower drain current.

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Margin criteria

Perf. criteria

hold SNM

RT

1

Margin criteria

RT

hold SNM

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Read WT SNM

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6T

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Read WT SNM

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Margin criteria

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hold SNM

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0, 4

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Perf. criteria

Margin criteria 1

Read SNM

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Ileak

WM

6T-2WL

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Read SNM

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WT

WM

6T Hybrid

6T

(e)

(d)

25

450 400 350 300 250 200 150 100 50 0

20 15 10

Iread (µA)

Read SNM (mV)

Fig. 7.23 Design Space Curves (DSC) of 6T versus: (a) 6T Hitachi, (b) 6T Berkeley PGFB and (c) 6T Berkeley PUWG + PGFB

5 0 100

150

200

250

300

Width of access transistors (nm)

Fig. 7.24 Variation of read SNM and read current versus the width of access transistors of the 6T Hybrid

According to the sizing of access transistors, the Iread current can be increased at the cost of a slight degradation of the read SNM which has still a more than acceptable value, as illustrated in Fig. 7.24. The same analysis can be performed to fine-tune the trade-off between interdependent criteria of the other bitcells.


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7.3.2.3 Read Stability Versus Supply Voltage Table 7.5 displays the variations of simulated results of read SNM according to the supply voltage reduction from 1.2 V to 700 mV. Figure 7.25 plots the read SNM as a percentage of VDD versus VDD. Although the conventional 6T SRAM cell is characterized by an increase of SNM as a percentage of VDD, see Fig. 7.25, the read stability of the cells with static and dynamic backgate connections are still higher. At VDD = 0.7 V the SNM improvement is between 27% (for the 6T Hitachi) and 70% (for the 6T Hybrid) which corresponds to an SNM between 25% and 33% of VDD, as illustrated in Fig. 7.25.

Table 7.5 Read SNM versus supply voltage VDD (mV)

6T

6T Hitachi

6T Be. PGFB

6T Be. PUWG + PGFB

6T-2WL

6T Hybrid

700 800 900 1,000 1,100 1,200

138 153 164 170 172 170

175 199 220 235 245 252

208 236 265 294 322 346

213 236 261 286 312 335

217 241 260 273 282 286

234 254 284 325 365 399

40.00% 35.00%

Read SNM/VDD

30.00% 25.00% 20.00% 15.00% 10.00% 5.00% 0.00% 700

800

900

1000

1100

1200

VDD (mV) 6T

6T Hitachi

6T Be. pgfb

6T Be. puwg+pgfb

6T-2WL

6T Hybrid

Fig. 7.25 Read SNM degradation versus supply voltage

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7.3.2.4 Impact of Vt Mismatch on Read Stability Scaling leads to a higher spread in technology parameters locally on a chip, across chip and globally across the wafer. In this section, only the mismatch in the threshold voltage (Vt) within a cell, and its impact on read stability are considered. In order to assess the Vt mismatch impact, the transistors responsible for data retention have to be unbalanced to make the memory cell less stable during a read access. Therefore, the threshold voltage has to be either increased to reduce the drain current of the transistor or decreased to increase the drain current. The worst-case scenario and appropriate selection of transistor values are based on the following observations: • Inject maximum of charges into the storage node containing ‘0’ (R node in Fig. 7.26) • Reduce the charge flow from the ‘0’ node towards the ground • Weaken the compensation of charge losses of the storage node containing ‘1’ logic value Figure 7.26 shows a 6T memory cell which has been unbalanced to fulfill the above conditions. Thereby, the MLL and MDR transistors (in dashed) have been weakened whereas the MA R transistor (in bold) has been strengthened. Figure 7.27 depicts the normalized degradation of simulated read stability of the 6T cells compared to their respective nominal value (i.e. without Vt mismatch) as a function of Vt mismatch. The threshold voltages of MLL , MDR and MAR have been modified as illustrated in Fig. 7.26, with a mismatch varying from 5% to 30%. The stability of the conventional 6T, which is the lowest, has been reduced to 58% of its initial value with 30% Vt mismatch. The static and the dynamic approaches (introduced in Section 7.3.2.1) of the advanced SRAM cells have improved both the nominal value of read stability and the resilience of the read stability to Vt mismatch.

WL MLL

MLR

L=‘1’

R=‘0’

Low Vt MAR

MAL

High Vt MDR BLR

BLL

MDL

Fig. 7.26 Unbalanced conventional 6T memory cell to assess the impact of Vt mismatch on read stability


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Read SNM degradation (%)

100 90

6T Be. pgfb 6T Be. puwg+pgfb 6T Hybrid 6T-2WL 6T Hitachi

80 70 60

6T

50 0

5

10

15

20

25

30

Vt mismatch (%)

Fig. 7.27 Read SNM degradation versus Vt mismatch

Furthermore, the SRAM cells based on FA transistors are the least sensitive to Vt mismatch, with degradation around 14% for 30% Vt mismatch.

7.3.2.5 Global Impact of Statistical Variations The sensitivity to process variations can be characterized relative to the standard deviation, which can be extracted from Monte-Carlo simulations, see Fig. 7.28. Monte Carlo runs for 1,000 samples of each cell have been performed where the following parameters were assigned with tolerances of 6σ : gate length L, gate width W, threshold voltage Vt, mobility μ , oxide thickness TOX , silicon film thickness TSI , and, access resistance Racc. The parameter variations are global as well as local, being fully randomized for each transistor. The mean Read Stability and the standard deviations (σ ) are reported in Table 7.6 in mV. The statistical results of stability in read mode show that the 6T Hitachi, the 6T-2WL and the architectures from Berkeley are globally as sensitive as the conventional 6T to fluctuations as the standard deviations shown in Table 7.6, are roughly the same. However, we can notice that the cells with FA transistors seem to be less sensitive to global variation, by displaying the lowest standard deviation, from 7.7 to 5.8 mV. The latter value is for the 6T Hybrid which presents a standard deviation 2.3 mV lower than the one of the conventional 6T.

7.3.3 Summary and Discussions The current trend to increase the density of SRAM memories in 65- and 45 nm bulkCMOS technologies faces serious challenges due to increased process variations. Multi-gate SOI CMOS technologies are being considered as viable alternatives to

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Fig. 7.28 Distribution of SNM in read mode Table 7.6 Statistical results of the read stability 6T Read stability (mV) mean and 170, (σ ) in mV (8.1)

6T Hitachi 6T Be. PGFB 6T Be. PUWG + PGFB 6T-2WL 6T Hybrid 252, (8.8)

346, (7.1)

335, (7.7)

286, (9.3)

399, (5.8)

bulk-CMOS at these new dimensions and mainly below. The double-gate (DG) technology with reduced process variations and better leakage current control is a serious contender to bulk-CMOS. This chapter has presented a number of alternatives to the 6T SRAM cell architecture, which take advantage of the second gate in DG CMOS in order to improve performance during read, retention and write operations. One additional variable available to a designer in a DG process, as the one considered, is the ratio of the thickness of the thin-oxide TOX of the front and back gate. If the two TOX are equal then the two gates have equal impact on the channel and the device is called symmetrical; if the two TOX values differ then one gate, usually the front gate, has more impact on channel current and the device is called partially asymmetrical (PA); if the two TOX values and also the two gate materials differ, then one gate, usually the front gate, has much more impact on channel current and the device is called fully asymmetrical (FA). Six new 6T SRAM cells have been studied and characterized in a double gate CMOS process based on a new compact DG MOSFET model implemented in the


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electrical simulator Eldo. A cell sizing methodology has been described to improve stability and write ability while minimizing the area. The performance of the new cells that take advantage of the extra gate is compared to that of the direct mapping of the 6T cell to DG where the two gates are tied together. The additional gate of access transistors greatly improves the read and retention stability without adding transistors while degrading the write and read access time. In order to reduce the degradation of the WM the 6T Berkeley PUWG + PGFB uses the back-gate of the load transistors and the 6T-2WL has an additional WL to separate and optimize read and write control. In order to make these cells as well as the 6T Berkeley PGFB and 6T Hybrid work well fully asymmetric (FA) DG transistors need to be used. There is no clear winner; one has for instance to sacrifice performance if choosing the advanced 6T cells, which improve on stability parameters over the 6T. Overall all improved cells are good candidates for low voltage applications because of their high stability.

7.4 Double Gate 4T & 5T SRAM Memories 7.4.1 DGMOS with Tied Gates New cells have been introduced in various technologies to increase the circuit density by suppressing transistors. Among them are the 4T cells, which can be classified in two types: the loadless (LL) and the driverless (DL) ones.

7.4.1.1 4-Transistor SRAM Memory Cells The 4T LL in Fig. 7.29a is derived from the 4T NEC in bulk technology [25]. The bitlines, BLL and BLR , of the loadless cells are precharged at VDD in order to be able to pull up a ‘1’ logic value at a storage node.

Fig. 7.29 4T LL cell (a); 4T DL cell (b)

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The 4T DL in Fig. 7.29b is derived from an ultra-low-voltage partially-depleted SOI cell presented in [26]. Its topology is similar to those proposed by TI and MOSYS [27] in CMOS single-gate technology. The bitlines of the driverless cell must be precharged at 0 V to pull down a ‘0’ logic value at one of the storage nodes.

7.4.1.2 Sizing Methodology Concerning the 4T cells, the cell sizing has to take into account two different aspects of stability, retention and read, and not the write mode. In fact, the absence of two inverters makes the cell less stable in retention but faster in write operations than the 6T cells. Therefore, the cells are sized such that the product of the SNMs in retention and read is maximized. However, the critical storage nodes in retention and in read modes are always complementary. By following the same approach used to obtain the stability conditions in 3.1.2, we can derive these conditions for the 4T LL cell (Fig. 7.29a) as represented by Eq. (7.6) for retention mode and Eq. (7.7) for read mode. IOFF−AL ≥ IG−DR + IOFF−DL ION−AR ≤ IG−DL + ION−DR

(7.6) (7.7)

On one hand, increasing the (W/L)MA improves the retention stability and degrades the read stability and on the other hand, increasing the (W/L)MD has the opposite effect. 7.4.1.3 5-Transistor SRAM Memory Cell The 5T cell, depicted in Fig. 7.30, and presented in [28] shows a smaller area, a lower bitline leakage, at the cost of a degradation of the read/write performance compared to a conventional 6T SRAM.

Fig. 7.30 5T cell


197

Fig. 7.31 4T Hitachi cell (a); 4T DL FB cell (b)

7.4.2 DGMOS with Independent Gate Biasing 7.4.2.1 4-Transistor SRAM Memory Cells: 4T Hitachi & 4T DL FB The 4T Hitachi cell (Fig. 7.31a) presented in [7] is derived from the 4T LL presented in Fig. 7.29a. The back gates of access transistors have been connected to the opposite storage nodes to introduce a ‘feedback’ mechanism. As for the 4T LL, the bitlines must be precharged to VDD . The 4T DriverLess cell with FeedBack, 4T DL FB illustrated in Fig. 7.31b [29] takes advantage of the double-gate technology by using the same kind of feedback as the cell in Fig. 7.31a and is derived from [26] (Fig. 7.29b). As for the 4T DL, the bitlines must be precharged to 0 V. 7.4.2.2 4-Transistor and 5-Transistor Asymmetric Single-ended SRAM Cells In some applications and in order to reduce dynamic power consumption and the size of the cell, it is more suitable to use single-ended memory cells. In this case, the cell has to be read or written by using only one bitline and one access transistor. As high density is needed only four or five transistors are used in these asymmetric SRAM cells. Architecture Description Figure 7.32a shows the 4T Asymmetric Single-Ended (ASE) cell [30, 31], based on the 4T DL FB presented in Section 7.4.2.1 and the cell introduced by [32] in bulk technology, which uses 2 bitlines. The cell consists of two PMOS loads MLL and MLR , one NMOS driver MDR and one NMOS access MAL transistors. For the 4T DL FB, the bitline has to be precharged at ‘0’, to increase the retention current flowing through the access transistor. Unlike the symmetrical cells, the asymmetrical ones have to be analyzed by taking into account the data initially stored. When node L contains ‘1’ and node R ‘0’, denoted as ‘state 10’, the information is much

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Fig. 7.32 Schematic diagram of (a) 4T and (b) 5T Asymmetric Single-Ended 4T cells

better maintained than in the opposite state, ‘state 01’, but causes the worsening of the write ability. Stability and Write Ability Issues and Tradeoffs The main issues of the 4T ASE are the stability in retention and in read modes, and the write ability. With regard to stability, by using the method introduced in Section 7.3.1.2, the critical storage node corresponds to the node L, either in retention or in read. The stability conditions in retention are shown in Eqs. (7.8) and (7.9). State 01 : IOFF−AL > IOFF−LL State 10 : IOFF−AL < ION−LL

(7.8) (7.9)

In read mode, the stability conditions are given in Eqs. (7.10) and (7.11). State 01 : ION−AL > IOFF−LL State 10 : ION−AL < ION−LL

(7.10) (7.11)

Unlike the conditions expressed by Eqs. (7.9) and (7.10), the conditions in Eqs. (7.8) and (7.11) are not always satisfied. For a reliable write operation a judicious choice of the pull-up ratio (PR) is required, as defined in Eq. (7.5). In fact, a low PR guaranties a sufficient write margin, but it leads to stability degradation for state 10, see Eqs. (7.9) and (7.11). The WM depends on the voltage at node L of the divider formed by the load (MLL ) and access (MAL ) transistors connected between the supply voltage of the cell and the bitline (BLL ). A write operation is correctly completed if the voltage at node L goes down to the switching threshold of the inverter (MLR , MDR ), assumed to be around half VDD . It means that the PR must be lower than 1, see Eq. (7.12). PR ≤ 1 (7.12)


199

The DG Device Solution The new degree of freedom offered by the DG technology offers a solution to the previous issues due to the connections (i) and (ii) represented in bold (Fig. 7.32a). The back-gate of load transistor MLL is connected to the supply voltage VDD through the connection denoted by (i). The (ii) link connects the back gate of the access transistor, MAL , to storage node R. The (i) connection reduces the drain current by a factor of 3 depending on the transistor type and the model used (Fig. 7.12). Consequently, the size of this load transistor can be divided by 3. The (ii) connection makes the current flowing through the access transistor, IOFF−AL , higher in state 01, see Eq. (7.8), due to the high logic value applied to its back gate. Moreover, it implies also the reduction of ION−AL for state 10, and thus the improvement of the condition in Eq. (7.11). Therefore, all the conditions in Eqs. (7.8)–(7.12) are satisfied, leading to an increase of the operating margins of the cell. As for the 4T DL FB, the cell must be sized such that the smallest SNM value is increased while keeping PR and the cell ratio CR, Eq. (7.4), below 2 to guarantee a small area.

Additional Version: the 5T ASE Architecture Figure 7.32b depicts another asymmetrical cell called 5T ASE. An access transistor and a bitline have been added in order to improve the write operation. During a write operation both access transistors will be activated, whereas, during a read, only the MAL access transistor is used as in the 4T ASE case, to keep the same high stability value and avoid the loss of stored data as described in [33].

7.4.3 Electrically Asymmetrical DGMOS Table 7.7 shows the simulated results of the advanced 4T cells with DGMOS FA transistors. The Write and Ileak characteristics of the ASE cells are given as two numbers corresponding to the cell initially in the state 01 or 10, as defined in Section 7.4.2.2, respectively. For the SNM, only one value is displayed because its value does not depend on the initial stored data. Since the read SNM of the ASE cells increases with CR and PR, they have both been set to 2, the maximum recommended value previously determined (see Section 7.4.2.2). Thereby, PR remains lower than three as established in same section. In retention, the SNM of the 4T DL FB and the ASE cells are almost the same, around 50 mV higher than the SNM of the 4T Hitachi. With regard to read stability, the 4T and 5T ASE cells present the same SNM value as stated in Section 7.4.2.2, which is 130% and 20% higher than the SNM of the 4T Hitachi and 4T DL FB, respectively.

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Table 7.7 Simulated results for 4T Hitachi, 4T DL FB, 4T ASE and 5T ASE cells containing fully asymmetrical (FA) DGMOS 4T Hitachi 4T DL FB 4T ASE Fully 5T ASE Fully Fully asymmetrical Fully asymmetrical asymmetrical asymmetrical Hold SNM (mV) Read SNM (mV) Write margin (mV) Ileak (nA) Write time (ps) Write disturb (μs) Normalized area (=1 for conventional 6T)

419 377 447 0.019 174 ‘∞’ 0.85

466 210 256 0.014 116 ‘∞’ 0.85

464 489 568/518 0.028/0.022 1,170/315 10,9/‘∞’ 0.76

464 489 212/100 0.031/0.022 272/126 10.9/‘∞’ 1.02

The WM of the 5T ASE cells has been greatly improved, by more than half of the 4T Hitachi or the 4T ASE WM. Moreover, the 5T ASE cell displays a WM better than that of the 4T DL FB by 50 mV. The cells present ideal static power consumption (less than 30 pA) due to the 100X reduction of the drain current when the back gate of a NMOS is connected to a low logic value (see Fig. 7.12). The write time of the 5T ASE architecture is comparable to those of the 4T Hitachi and the 4T DL FB cells except for the initial state 01. However, asymmetry has a negative impact on the WT of the 4T ASE cell, which is worse than the other 4T cells by 4.3x and 2.5x for the states 01 and 10, respectively. The 4T cells with FA transistors are not affected by write disturb, apart from the ASE cells with the initial state 01, which may be disturbed beyond 10.9 μs. Nevertheless the ratio of write disturb over write time is equal to 4 × 104, making the cells very robust. The 4T ASE area is 25% smaller than the 6T area and 10% smaller than the 4T DL FB and the 4T Hitachi areas. However, the areas of 5T ASE and the conventional 6T are similar; globally, the increasing number of independent gates makes this innovative architecture more complex, leading to increase of area. The same SRAM memory cells described above have also been characterized for a DGMOS PA implementation. Their simulated characteristics are listed in Table 7.8. The new SRAM cells presented have been designed with the primary objective of increasing the global stability under all bias conditions. The read and retention SNM of the various 4T and 5T DGMOS cells with FA devices depends on the supply voltage; this variation is shown in Fig. 7.33 when the supply voltage is varied from 1.2 V to 700 mV. For clarity, only the minimum of read and retention SNMs for different supply voltages is represented. Observe that the minimum SNM of 4T Hitachi and 4T DL FB cells are almost identical at 700 mV. The ASE bit cells present the best SNM even at low voltage, by exhibiting a SNM/V DD ratio higher than 35%. Thus, these cells are promising candidates for low voltage applications since the minimum


201

Table 7.8 Simulated results for 4T Hitachi, 4T DL FB, 4T ASE and 5T ASE cells containing partially asymmetrical (PA) DGMOS

Hold SNM (mV) Read SNM (mV) Write margin (mV) Ileak (nA) Write time (ps) Write disturb (μs) Normalized area (=1 for conventional 6T)

4T Hitachi Partially asymmetrical

4T DL FB Partially asymmetrical

4T ASE Partially asymmetrical

5T ASE Partially asymmetrical

335 229 507 28.5 96 0.02 0.85

414 50 37 14.9 32 0.02 0.85

280 270 449/356 52.9/19.3 50/244 937p/X 0.76

280 270 401/40 54.2/19.3 50/110 898p/X 1.02

Min(Read SNM, hold SNM) (mV)

500 450

4T/5T ASE

400 350 4T Hitachi

300 250 200 4T DL FB

150 100 50 0 700

800

900

1000

1100

1200

VDD (mV)

Fig. 7.33 Minimum of read and retention SNM versus supply voltage for DGMOS-FA SRAM cells

stability remains higher by more than 70 mV compared to the conventional 4T Hitachi.

7.4.4 Summary and Discussions SRAM cells with less than 6 transistors have been described that take advantage of the second gate to match or beat the performance of 6T cells while reducing area up to 25%. The cells presented can be categorized as symmetrical-based (4T Hitachi and 4T DLFB) and asymmetrical-based (4T/5T ASE). In the symmetrical-based category we have analyzed two 4T topologies: a load-less, LL, and driver-less, DL, cell. In DG technology the back-gates of the four transistors are used to add feedback, which improves stability. The 4T cells

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demonstrate comparable stability to the 6T cells and occupy only 60% to 85% of the area. Performance data have been given for a partially asymmetric, PA, DG device and fully asymmetric, FA, predictive device with a Vt = 800 mV for the back-gate. The 4T LL cell shows very good stability for both PA and FA devices. The 4T DL cell displays good stability only in the FA implementation. In addition FA 4T cells reduce leakage by up to two orders of magnitude when compared to 6T cells if symmetrical transistors are used. If FA devices are used for the 6T, the leakage reduction drops to 2x. In the asymmetrical-based category a 4T and 5T topology has been described. The former operates with only one BL and access transistor while the latter has two BLs. Both have good stability and the 4T ASE has the advantage of needing only 76% of the area taken by a standard 6T cell. Based on the performance results of the analyzed cells it appears that DG implementations allow a reduction of the number of transistors per cells with the added benefit of reduced area, less leakage power and much better stability even at low supply voltage.

References 1. M. Yamaoka, N. Maeda, Y. Shinozaki, Y. Shimazaki, K. Nii, S. Shimada, K. Yanagisawa and T. Kawahara, “Low-power embedded SRAM modules with expanded margins for writing”, ISSCC, SC 26, pp. 480–481, 2005. 2. P. Roche, F. Jacquet, C. Caillat, J.-P. Schoellkopf, “An alpha immune and ultra low neutron SER high density SRAM,” Reliability Physics Symposium Proceedings, 2004 IEEE International Volume, April 2004, pp. 671–672. 3. M. Lysinger, P. Roche, M. Zamanian, F. Jacquet, N. Sahoo, D. McClure, J. Russell, “A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS,” ISQED 2008 San Jose, CA. 4. Philippe Roche and Gilles Gasiot, “Impacts of Front-End and Middle-End Process Modifications on Terrestrial Soft Error Rate,” IEEE Transactions on Device and Materials Reliability, Vol. 5, No. 3, September 2005. 5. S. Date, N. Shibata, S. Mutoh, J. Yamada, “1-V, 30-MHz Memory-Macrocell-Circuit Technology with a 0.5-pm Multi-threshold CMOS”, Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium Volume, Issue, Oct 1994, pp. 90–91. 6. E.J. Nowak, B.A. Rainey, D.M. Fried, J. Kedzierski, M. Ieong, W. Leipold, J. Wright, M. Breitwisch, “A functional FinFET-DGCMOS SRAM cell”, Electron Devices Meeting, 2002. Digest. International, 2002, pp. 411–414. 7. M. Yamaoka, K. Osada, R. Tsuchiya, M. Horiuchi, S. Kimura and T. Kawahara., “Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology”, Symp. VLSI Circuits Dig. 18, 2004, pp. 288–291. 8. K. Itoh, “VLSI Memory Chip Design,”, Springer, 2001. 9. K. Itoh, M. Horiguchi, H. Tanaka, “Ultra-Low Voltage Nanoscale Memories” (Series on Integrated Circuits and Systems), Springer, 2007. 10. M. Yoshimoto, K. Anami, H. Shinohara, T. Yoshihara, H. Takagi, S. Nagao, S. Kayano and T. Nakano, “A 64Kb full CMOS RAM with divided word line structure”, ISSCC Dig. Tech. Papers, pp. 58–59, February 1983. 11. A. Turier, L. Ben Ammar, A. Amara, “Static Power Consumption Management in CMOS Memories,” ISCAS, Sydney Australia, 2001. 12. E. Seevinck Sr., F.J. List, J. Lohstroh, “Static-noise margin analysis of MOS SRAM cells”, IEEE Journal of Solid-State Circuits, vol. 22, 1987, pp. 748–754.


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13. O. Thomas, M. Belleville, F. Jacquet, P. Flatresse, “Impact of CMOS Technology Scaling on SRAM Standby Leakage Reduction techniques”, ICICDT, Padova, 2006. 14. F. Hamzaoglu, Y. Ye, A. Keshavarzi, K. Zhang, S. Narendra, S. Borkar, M. Stan and V. De, “Analysis of dual-Vt SRAM cells with full-swing single-ended bit line sensing for on-chip cache,” IEEE TVLSI systems, Vol. 10, April 2002. 15. G.R. SriniVasan, P.C. Murley, and H.K. Tang, “Accurate, Predictive Modeling of Soft Error Rate due to Cosmic Rays and Chip Alpha Radiation”, Reliability physics symposium, San Jose, CA, 1994. 16. O. Thomas, “Etude de la faisabilité de circuits mémoire SRAM ultra basse tension en technologie SOI partiellement désertée”, Ph.D. thesis defended at ISEP (Paris) in December 2004. 17. M. Vinet, T. Poiroux, J. Widiez, J. Lolivier, B. Previtali, C. Vizioz, B. Guillaumot, Y. Le Tiec, P. Besson, B. Biasse, F. Allain, M. Casse, D. Lafond, J.-M. Hartmann, Y. Morand, J. Chiaroni, S. Deleonibus, “Bonded planar double-metal-gate NMOS transistors down to 10 nm”, IEEE Electron Devices Letters, vol. 26, No. 5, May 2005, pp. 317–319. 18. O. Thomas, M. Reyboz and M. Belleville, “Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology”, ISCAS 2007, New Orleans. 19. J. Rabaey, A. Chandrakasan, and B. Nikolic, “Digital Integrated Circuits 2nd edition,” Prentice-Hall, Englewood Cliffs, NJ, 2003. 20. H. Qin, Yu Cao, Dejan Markovic, Andrei Vladimirescu and Jan Rabaey, “Standby supply voltage minimization for deep sub-micron SRAM,” Microelectron. J. Vol. 36, No. 9, 2005, p. 789800. 21. Z. Guo, S. Balasubramanian, R. Zlatanovici, T. King, B. Nikolić., “FinFET-Based SRAM Design”, UC Berkeley, ISLPED, San Diego, CA, 2005. 22. A. Carlson, Z. Guo, S. Balasubramanian, L.-T. Pang, T.-J. King Liu, and B. Nikolic, “FinFET SRAM with Enhanced Read/Write Margins”, SOI Conference, 2006. 23. B. Giraud and O. Thomas, “Cellule mémoire SRAM a` transistors double grille dote de moyens pour améliorer la marge en e´ criture”, French patent number 08511027. 24. M. Reyboz, O. Rozeau, T. Poiroux, P. Martin and J. Jomaah, “Explicit threshold voltage based compact model of independent double gate (IDG) MOSFET including short channel effects”, 2006 Workshop on Compact Modeling, May 9–11, 2006, Boston, MA. 25. K. Noda, K. Matsui, K. Takeda and N. Nakamura, “A loadless CMOS four-transistor SRAM cell in 0.18-μm logic technology”, IEEE Transactions on Electron Devices, Vol. 48, No. 12, December 2001. 26. O. Thomas and A. Amara, “An SOI 4 transistors self-refresh ultra-low-voltage memory cell”, ISCAS, Thailand Bangkok 2003. 27. W. Leung, F. C. Hsu, “High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process”, US Patent, NO. 6 44 060 B1, Monolithic System Technology, 2002. 28. I. Carlson, S. Andersson, S. Natarajan and A. Alvandpour, “A high density, low leakage, 5T SRAM for embedded caches,” Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European, 21–23 September 2004, pp. 215–218. 29. B. Giraud, A. Vladimirescu and A. Amara, “A comparative study of 6T and 4T SRAM cells in double-gate CMOS with statistical variation”, ISCAS 2007, New Orleans. 30. B. Giraud and A. Amara, “A Novel 4T Asymmetric Single-Ended SRAM Cell in sub-32nm Double Gate Technology”, ISCAS, Seattle, May 2008. 31. B. Giraud and A. Amara, “Single Ended Asymmetric 4T”, EN 07 03955. 32. Byung-Il Hong and Ichon-shi, “Dual Port Sram Cell”, US Patent, NO 7 116 605. 33. J.-J. Kim, K. Kim and C.T. Chuang, “Independent-gate controlled asymmetrical SRAM cells in double-gate technology for improved read stability”, 2006.

Conclusion

Thin film SOI device architectures are serious candidate for sub-32 nm nodes. Their main advantages are an excellent electrostatic control compared to traditional silicon MOSFET, resulting in a lower short channel effects. Some device prototypes were presented in the literature proving that these architectures are scalable down to the sub-10 nm gate length. Since few years, significant publications are focusing on multi gates thin film transistors. Nowadays several process flows to fabricate these devices are made available. The most popular one is the FinFET where the main advantage is the possibility to use similar process than conventional bulk technologies. However, the variability of the fin width can be a significant limiting factor. Other approaches consist in using wafer bonding or epitaxial growth. The first one is described in the first chapter of this book. The main advantage of this architecture is the good control of the silicon film thickness. In term of electrical performance, many research works point out the excellent Ion /Ioff ratio and the dynamic characteristics. In addition, some process flows allow independent control of the front and the back gates. From a circuit design point of view, this option offers a new design perspectives, not only by considering the device as two transistor in parallel but also by taking advantage of the interface coupling between both gates. It is then necessary to develop new compact device models in order to demonstrate the feasibility of innovative circuits. In this book, the device behavior with independent gates is detailed using two physical-based compact models, that consider drift-diffusion or pure ballistic transport. From these models, the electrical characteristics of independent double gate MOSFET can be explained. For exemple, the impact of quantum effets or short channel effect can be estimated. For a circuit designer, understanding the behavior of such device is crucial in order to come up with non-conventional circuit as shown in the chapters dedicated to digital, analog ad memory circuits design. Moreover, low frequency noise characteristics are discussed in Chapter 4 to complete the description of the device behavior. All these results are not sufficient to design circuits with a large number of transistors. For that reason, a threshold voltage based model of IDGMOS has been introduced and detailed in Chapter 3. This model is used in chapters related to IC design.


205

206

Conclusion

As discussed in this book, the independent gate transistors allow the design of new circuit architectures as digital reconfigurable cells or high stability SRAM memory cells. Indeed, it is pointed out in this book that asymmetric DGMOS using thick oxide for example for one gate and thin oxide for the other gate, is very promising for threshold voltage control thanks to the interface coupling effect. In addition to that, the threshold voltage control can be drastically improved by using different metal gates as shown in this book. For digital applications, programmable cell using asymmetric devices reduce significantly the gate area compared to the conventional CMOS lookup table techniques. Also, using this interface coupling, a single component can be used to mix different signals. Some analog blocks are studied and detailed in this book. The use of independent gates transistor allows to design more compact circuit and to reduce the power consumption. For SRAM circuits, 4-T cell using asymmetric transistors shows an excellent stability with a significant reduction of the cell area compared to a classical 6-T cell. New SRAM memory cells that take benefit of the transistor asymmetry are also introduced in this book and intensively analysed. However, asymmetric DG MOSFET is not the best architecture for electrostatic control because the subthreshold leakage current is higher than in the symmetric one. As a consequence, and to fully take benefit of the double gate CMOS technologies, it seems essential to co-integrate asymmetric and symmetric device architectures in the same design. To conclude, this book is the result of more than 2 years of research involving laboratories from academia leaded by a public research laboratory (CEA/LETI) and funded by the “Agence Nationale de la Recherche” (French National Research Agency).

Appendix

Abbreviations A ADG AGW ASE

Asymmetric double gate Asymmetric gate work-functions Asymmetric single-ended

BG BL BOX

Back gate Bitline Buried OXide

CDGMOS CG CLM CMF CMOS CMP CMRR CNF CR

Connected double gate MOSFET Connected gates Channel length modulation effect Correlated mobility fluctuations Complementary metal-oxide-semiconductor technology Chemical-mechanical polishing Common mode rejection ratio Carrier number fluctuations Cell ratio

B

C

D DG, DGMOS Double-gate MOSFET DGMOSFET Double-gate MOSFET DIBL Drain induced barrier lowering effect DL DriverLess DLRC Dynamic-logic reconfigurable cell DSC Design space curves DWL Divided wordline 207

208

Appendix

E EC-QM EOT

Electric field-induced quantum-mechanical Confinement Equivalent oxide thickness

FAD FA FD FDSOI FG FinFET

Full adder Fully asymmetrical Fully depleted Fully-depleted silicon on insulator Front gate Fin field effect transistor

GIDL

Gate induced drain leakage

HP

High performance technology option

F

G

H

I IDG, IDGMOS Independent double-gate MOSFET IDG MOSFET Independent double-gate MOSFET IGC Independent gate control ITRS International technology roadmap for semiconductors K KCL

Kirchhoff’s current law

LFN LL LOP LP LSTP LUT

Low frequency noise LoadLess Low-operating power technology option Low power Low-STandby power technology option LookUp table

MBCFET MILC MOS MOSFET

Multi-bridge channel field effect transistor Metal-induced lateral crystallization Metal-oxide-semiconductor Metal-oxide-semiconductor field effect transistor

NEGF NDR

Non-equilibrium green’s function formalism Negative differential resistance

OTA

Operational transconductance amplifier

L

M

N

O

Appendix

209

P PA PD PDSOI PGFB PR PUWG

Partially asymmetrical Partially depleted Partially depleted SOI Pass-gate feed-back Pull-up ratio Pull-up write gating

QM

Quantum-mechanical

RSCE RNM RT RWWL

Reverse short channel effect Retention noise margin Read access time Read and write wordline

SCEs, SCE SC-QM SER SLRC SNM SOI SON SRAM STI

Short channel effects Structural quantum confinement Soft error rate Static-logic reconfigurable cell Static noise margin Silicon on insulator Silicon on nothing Static random access memory Shallow trench isolation

TCAD TEM

Technology computer-aid design Transmission electron microscope

ULPFA

Ultra-low power full adder

VCO VTC

Voltage controlled oscillator Voltage transfer curves

WKB WL WM WWL

Wentzel-Kramer-Brillouin approach Wordline Write margin Write wordline

Q

R

S

T

U

V

W

Index

6T SRAM memory cell, 171

Multiple gate, 4, 9, 22

Amplifier, 128, 135, 165, 208 Asymmetric DGMOS, 146, 148, 152, 154, 156, 206

Negative differential resistance, 145, 208

Branch-based logic, 145

Pass-transistor logic, 138

Compact modeling, 54 Configuration code, 153–155, 158, 160 Current mirror, 109, 110, 112, 113

Quantum effects, 83 Quantum-mechanical tunneling, 48, 50

Differential pair, 113, 118 Dynamic logic, 153 Feedback, 127, 201 FinFET, 17–20, 24, 85, 168, 179, 202, 203, 205, 208 Fully depleted, 22 Gate stack, 9

OTA, 122–125, 127, 130, 132, 135, 136, 208

Reconfigurable, 165, 207, 209 Ring oscillator, 141, 143 Static logic, 154 Static noise margin, 173, 188 Surface potential based model, 55, 56 Surrounding gate, 19 Threshold voltage modulation, 110 Trigate, 16, 18, 19 Variability, 8

Interface Coupling, 67 ITRS, 1, 3, 5, 12, 27, 50, 137, 151, 168, 188, 208

Weak logic level, 145 Write margin, 173, 175, 182–186, 188, 198

Low frequency noise, 103, 104

XOR, 145, 148, 150, 165

211

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