Handbook of Semiconductor Technology, Volume 2

Handbook of Semiconductor Technology Volume 2 Kenneth A. Jackson, Wolfgang Schroter (Eds.) @3WILEY-VCH Weinheim . New Y...

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Handbook of Semiconductor Technology Volume 2 Kenneth A. Jackson, Wolfgang Schroter (Eds.)

@3WILEY-VCH Weinheim . New York . Chichester . Brisbane . Singapore . Toronto

Editors: Prof. K. A Jackson The Universit) of Arizona Arizona Materials Laboratory 47 15 E. Fort Lowell Road Tucson. A 2 85712. USA

Prof. Dr. W. Schroter IV. Physikalisches Institut der Georg-August-Universitat Gottingen BunsenstraDe 13-15 D-37073 Gottingen, Germany

This book was carefull) produced. Nevertheless, authors, editors and publisher d o not warrant the information contained therein to be free of errors. Readers are advised to keep in mind that statements. data, illustrations. procedural details or other items may inadvertently be inaccurate.

Library of Congress Card N o : applied for British Library Cataloguing-in-Publication Data: applied for Deutsche Bibliothek Cataloguing-in-Publication-Data

.4catalogue record is available from Die Deutsche Bibliothek ISBN 3-527-29835-5

0 WILEY-VCH Verlag GmhH. D-69469 Weinheim (Federal Republic of Germany), 2000 Printed on acid-free and chlorine-free paper. All rights resewed (including those of translation into other languages). No part of this book may be reproduced in any form - by photoprinting, microfilm, or any other means - nor transmitted or translated into machine language without written permission from the publishers. Registered names, trademarks, etc. used in this book, even when not specifically marked as such, are not to be considered unprotected by law.

Composition, Printing and Bookbinding: Konrad Triltsch. Print und digitale Medien GmbH, D-97070 Wiirzburg Printed in the Federal Republic of Germany.

IX

List of Contributors

Dr. Daniel I. Amey DuPont Electronic Materials Experimental Station P.O. Box 80334 Wilmington, DE 19880-0334, U.S.A. Chapter 11

Prof. Thomas F. Kuech University of Wisconsin Department of Chemical Engineering 14 15 Engineering Drive Madison, WI 53706, U.S.A. Chapter 3

Dr. Ken E. Benson Formerly with AT&T Allentown, PA, U.S.A. Chapter I

Dr. Dim-Lee Kwong The University of Texas at Austin Microelectronics Research Center Department of Electrical and Computer Engineering Austin, TX 78712, U.S.A. Chapter 9

Prof. Chun-Yen Chang National Chaio Tung University National Nan0 Device Laboratory 1001- 1 Ta Hsueh Road Hsinchu, Taiwan 30050, R.O.C. Chapter 7 Dr. Kevin G. Donohoe Formerly with Applied Materials Santa Clara, CA. U.S.A. Chapter 6 Prof. Kenneth A. Jackson University of Arizona Arizona Materials Laboratory 47 15 East Lowell Road Tucson, AZ 85712, U.S.A. Chapter 6 Dr. Wulf H. Knausenberger RD Hikuai, via Thames New Zealand Chapter 12

Dr. Juan F. Lam Hughes Aircraft Company Hughes Research Laboratories 301 1 Malibu Canyon Road Malibu, CA 90265-4799, U.S.A. Chapter 8 Dr. Rainer Leuschner Siemens AG Corporate Technology Materials and Manufacturing P.O. Box 32 20 D-91050 Erlangen, Germany Chapter 4 Dr. Wen Lin Lucent Technologies Allentown, PA, U.S.A. Chapter 1

X

List of Contributors

Prof. Subhash Mahajan Carnegie Mellon University Department of Materials Science and Engineering Wean Hall 331 1 Pittsburgh. PA 15213-3890. U.S.A. Chapter 5

Prof. Simon M. Sze National Chiao Tung University Microelectronics and Information Systems Research Center 1001 Ta Hsueh Road Hsinchu, Taiwan 30050. R.O.C. Chapter 7

Dr. J. Brian Mullin EMC Malvern "The Hoo". Brockhill Road West Malvern. Worcs. WR14 4DL. U.K. Chapter 2

Michael A. Tischler Advanced Technology Materials, Inc. Danbury, CT 06810, U.S.A. Chapter 3

Dr. John M. Parsey. Jr. Motorola Semiconductor Products Sector 2100 East Elliot Road Tempe, AZ 85284. U.S.A. Chapter 10 Dr. Georg Pawlowski Clariant Japan K.K.. BU Electronic Materials Shizuoka. Japan Chapter 4 Dr. William E. Stanchina Hughes Aircraft Company Hughes Research Laboratories 301 1 Malibu Canyon Road Malibu. CA 902654799, U.S.A. Chapter 8

Dr. Terry R. Turner Fourth State Technology 2120 Braker Lane, Suite C Austin, TX 78758, U.S.A. Chapter 6 Prof. John G. Wilkes T Formerly with Mullard Ltd., Southampton, U.K. Chapter 1

Preface

In the past, the ages of man have been labeled by the materials over which we have gained control: the stone age, the bronze age, the iron age. This is surely the silicon age, where the term silicon is meant to imply the most ubiquitous member of the class of materials known as semiconductors. The modern electronic industry is based on the technology of these materials, and the information age would not be possible without their remarkable properties. Although silicon makes up one quarter of the earth’s crust in the form of silicate minerals, its use as an electronic material, based on its semiconducting properties, were not realized until about fifty years ago when techniques for purifying and preparing single crystals of silicon were developed. The driving force behind this advance was the developing understanding of the electronic properties of these materials. During the past fifty years, the use of these materials has expanded to the point where their manufacture is a major component of world commerce, and the electronic products which they enable have impacted every aspect of our daily lives. Semiconductors permeate all aspects of modern society. Computers based on these materials have permitted the increasingly rapid processing and interchange of information which is now incorporated into our daily life styles. In addition to increased access to information, modern computers have changed the way science is conducted, they have introduced new paradigms for mathematics, and they are essential to the developing understanding of how our genes are constructed. The technology on which this development is based is simply impressive. The starting silicon material is, by a significant margin, both the purest and most perfect single crystalline material prepared by man. The fabrication technology pushes the limits of the size of the sub-microscopic features created, the limits of the complexity and of the number of steps involved in the processing, the limits of the purity of the chemicals used in the processing including the water, and even the limits of the cleanliness of the manufacturing environment. The volume on Semiconductor Processing describes this manufacturing technology in some detail. This technology continues to evolve and develop very rapidly to maintain the pace of the ever-expanding speed and power of modern computers and of other leading edge electronic components. I am deeply indebted to the contributors to this volume who took valuable time from their busy schedules to write about this impressive technology which they are deeply involved in developing.

Kenneth A. Jackson Tucson, April 2000

Contents

1 Silicon Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 J. G. Wilkes f , K. E. Benson, W Lin 2 Compound Semiconductor Processing . . . . . . . . . . . . . . . . . 67 J. B. Mullin 3 Epitaxial Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7: E Kuech, M. A. Tischler 4 Photolithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . R. Leuschner, G. Pawlowski 5 Selective Doping . . . . . . . . . . . . . . . . . . . . . . . . . . . . S. Mahajan

11 1 177 265

6 Etching Processes in Semiconductor Manufacturing . . . . . . . . . . 291 K. G. Donohoe, ir: R . Turner, K.A . Jackson

7 Silicon Device Structures . . . . . . . . . . . . . . . . . . . . . . . . C.-Y Chang, S. M . Sze

341

8 Compound Semiconductor Device Structures . . . . . . . . . . . . . . 39 1 W. E. Stanchina, J. E Lam 9 Silicon Device Processing . . . . . . . . . . . . . . . . . . . . . . . . 407 D.-L. Kwong

10 Compound Semiconductor Device Processing J. M . Parsey, Jr:

. . . . . . . . . . . . . 489

1 1 Integrated Circuit Packaging . . . . . . . . . . . . . . . . . . . . . . D. I. Amey 12 Interconnection Systems . . . . . . . . . . . . . . . . . . . . . . . . W H. Knausenberger Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

607 649 683

1 Silicon Processing

.

John G Wilkes *

.

Updated by Wen Lin** and Ken E Benson*** . October. 1999 List of 1.1 1.2 1.3 1.3.1 1.3.2 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.5 1.5.1 1S . 2 1S.3 1.5.4 1.5.5 1.6 1.6.1 1.6.2 1.6.3 1.6.4 1.6.5 1.6.6 1.6.7 1.7 1.7.1 1.7.2 1.7.3 1.8 1.8.1 1.8.2 1.9 1.10

* ** ***

2 Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Metallurgical-Grade Silicon . . . . . . . . . . . . . . . . . . . . . . . . . 7 Semiconductor Grade Polycrystal Silicon . . . . . . . . . . . . . . . . . . 11 The Chlorosilane Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 The Silane Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Single Crystal Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 Float-Zoned Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Neutron Transmutation Doped Silicon . . . . . . . . . . . . . . . . . . . . . Carbon and Nitrogen in Float-Zoned Silicon . . . . . . . . . . . . . . . . . 20 Periodic Crystal Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Czochralski Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Dislocation-Free Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Constitutional Supercooling . . . . . . . . . . . . . . . . . . . . . . . . . . 27 The Incorporation of Carbon and Oxygen . . . . . . . . . . . . . . . . . . . 29 Magnetic Czochralski Silicon . . . . . . . . . . . . . . . . . . . . . . . . . 33 Evolution in Czochralski Crystal Diameter . . . . . . . . . . . . . . . . . . 34 Wafer preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Slicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Edge Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Lapping/Grinding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Chemical Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Polishing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 41 Mechanical Damage in Silicon . . . . . . . . . . . . . . . . . . . . . . . . . Oxygen in Czochralski Silicon . . . . . . . . . . . . . . . . . . . . . . . . 46 The Behavior of Oxygen in Silicon . . . . . . . . . . . . . . . . . . . . . . 46 48 The Precipitation of Oxygen in Silicon . . . . . . . . . . . . . . . . . . . . Thermal Donors and Enhanced Diffusion . . . . . . . . . . . . . . . . . . . 52 Gettering Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Extrinsic Gettering in Silicon . . . . . . . . . . . . . . . . . . . . . . . . . 53 56 Intrinsic Gettering in Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Formerly with Philips Components Ltd., Southampton. U.K. Lucent Technologies. Allentown. Pa. U.S.A. Formerly with AT&T. Allentown. Pa. U.S.A.

2


List of Symbols and Abbreviations A"

Fourier series coefficient lattice constant (for Si, N" = 5.42 A) a, A0 constant B slice bow depth C concentration CH crystal habit CI concentration in liquid concentration (of oxygen in oxide) in particle CP concentration in solid c, equilibrium solid solubility concentration Cr 5 co initial concentration d diameter D diffusion coefficient activation energy for the formation of a particle of critical radius EC ft cut-off frequency f; mean value off, volume free energy change of a precipitate mv F,, F,, F , magnitudes of the forces generated at the edge during sawing fraction of melt solidified height enthalpy of reaction detector signal interstitial collector - base current Boltzmann constant effective distribution coefficient equilibrium distribution coefficient number of particles number of particles of critical radius fast neutron, thermal neutron number of oxygen atoms i n axial bonds number of oxygen atoms in other bonds bound interstitial oxygen concentration Prandtl number radius radius of the total volume from which oxygen condenses into a precipitate critical radius radius of a final precipitate particle, small compared with R time absolute temperature melting point (Si: 1412°C) half life of radioactive species thickness of a silicon slice

List of Symbols and Abbreviations

3

temperature difference velocity vacancy velocity of growth intrinsic X-ray signal half width measured X-ray signal half width rocking curve broadening alpha particle absorption coefficient for polarized infrared light parallel to the stress axis absorption coefficient for polarized infrared light perpendicular to the stress axis gamma particle boundary layer thickness strain test sample angle Bragg angle, X-ray reflection Fourier coefficient (with dimensions of inverse length) constant kinematic viscosity surface free energy relaxation time relaxation time constants angular velocity AC ACR ASTM BP CMOS CVD

cz

DC DCS DI DRAM EBE EG FZ HF HI-LO LPCVD MG-Si MOS

NFZ

alternating current advanced carbothermic reduction American Society for Testing Materials boiling point complementary, using both n- and p-type, metal- oxide- silicon device chemical vapor deposition Czochralski material direct current dichlorosilane deionized dynamic random access memory extended bulk epitaxy enhanced gettering float zoned (material) high frequency high temperature - low temperature (heat treatment) low pressure chemical vapor deposition metallurgical-grade silicon metal-oxide-silicon (device) (n-MOS, p-MOS refer to the dopant type structure employed) nitrogen-doped float zone (material)

4

NTD NTP PPba PPma PPt psi RF rPm SANS SIMS SRAM

TCS TD TIR UHF ULSI UV VLSI

WCA


neutron transmutation doping normal temperature and pressure atomic part5 per billion ( lo9) atomic parts per million parts per trillion ( I 0”) pounds per square inch radio frequency rotations per minute small angle neutron scattering secondary ion mass spectrometry static random access memory trichlorosilane thermal donor total integrated reading (of bow or warp) ultrahigh frequency ultra large scale integration ultraviolet very large scale integration water classified alumina

1.1 Introduction

1.1 Introduction Silicon today is a commodity, its price subject to all the forces of supply and demand in an intensely competitive market, and this has driven the development of high yield processes for the tight tolerance materials demanded. While discrete and power device manufacture calls for some float zoned, and neutron transmutation doped (NTD) silicon; the worldwide compass of integrated circuit manufacture consumes more than 75% of all the semiconductor silicon produced. The development of the product market distribution is shown in Fig. 1-1, Supply of this material isdominated by Czochralski crystal growth, the operational scale of which has increased from charges weighing a few hundred grams, around 1962, to the current units of 60 kilogram and more.

The evolution of the semiconductor industry as we now know it began in the 1950s, when many of the then large electrical companies became involved in the chemistry and metallurgy of Germanium. Their starting point was GeO,, the dioxide, which had to be reduced to metal powder, melted, zone refined, and crystals grown, before the machining operations which led to discrete devices. Germanium being an expensive rare element, the machining itself generated valuable byproduct sludges which had to be recovered. The extreme purity necessary led into problems in chemical and physical analysis, materials of containment, and in general chemical engineering. In retrospect, very few of these electrical companies possessed either the resources or the experience needed for such work; so when, only shortly afterwards, silicon was

d

300

VI

250

a

! s1

200

8m

z

2

5

150

d m 100

50

m

Z z z z YEAR

Figure 1-1. Global semiconductor sales forecast (After Winegarner).

6

1 Silicon P r o c e s s i n g

introduced, almost all of them took the opportunity to withdraw from the chemical end of the business. Silicon is one of the most abundant elements, and so the sludges are of no economic importance. Henceforth their starting point became the ultrapure polycrystalline silicon from which they made their own single crystal. Withitime, the number of companies doing even this has steadily declined. until today few of the electronics manufacturers have any involvement in bulk material processing. Indeed most purchase polished slices, cleaned and packaged, furnace ready, for fabrication lines. A number of the device makers still carry out epitaxy and, to that extent alone, retain a residual materials activity. Today’s ultra large scale integrated circuits (ULSI) lithographic feature sizes have been reduced to 0.18 pm (anticipate to be in 0.1 p m region by year 2006 or sooner) as

projected by the National Technology Road Map of Semiconductor. These circuits use multi-level metal interconnects to able the production of highly complex circuits of steadily increasing chip size. Consequently, as the number of chips per wafer decreases, so there has been an accompanying call for ever larger wafer diameter - to reduce perimeter wastage, and to improve the fabrication line yield and throughput, as shown in Fig. 1-2 - hence the continuous need to scale up crystal size, this demanding extremely heavy investment. This scaling has not been at the expense of quality - i n fact quite the reverse. As more has been learned about the relationship between materials properties and the device parameters, so the demand for better performance from the silicon has grown. If one compares a typical purchasing specification of even the mid 1970s, with that in

100,000

10,000

1,000

100

10

1

0

Year Figure 1-2. H i m r i c a l and projected wafer size trends (Source: VLSl Research, SEMATECH. 13001).

1.2 Metallurgical-Grade Silicon

force today for a similar application endproduct, the increase in the number of parameters specified, and the narrowing of virtually all tolerances, is marked. Factors contributing to this position are several. Fine geometry lithography of the ULSI fabrication requires wafer local flatness to match the design rule according to guidance of the National Technology Road Map of Semiconductors (NTRS - 1997). Control of particles of sizes down to one half of the design rules and wafer surface metal contamination at a level near the detection limits (NTRS - 1997). Research into the behavior of oxygen precipitation in bulk silicon under device thermal cycles has led to the introduction of new specification parameters, new crystal growth and wafer processing methods, and to the concept of “crystal engineering”. Controlled oxide precipitation in slices is carried out, prior to their use in fabrication lines, to provide sites for the intrinsic gettering of unwanted fast diffusing electrically deleterious impurities, away from the surface layer where the MOS devices are made. Residual mechanical damage sites after the crystal machining provide similar extrinsic gettering sites. For many applications in “crystal engineering” today, combinations of controlled mechanical and oxide precipitate gettering are used together to achieve optimum performance from the silicon, to match the particular device requirements in MOS, CMOS, and bipolar configurations. To achieve this matching it is necessary to examine the total thermal inventory of the multistage fabrication process, in order to select the most appropriate structure. As semiconductor technology continues to advance, the IC design rule is approaching 0.1 p m by 2006, if not earlier. In parallel with the design rule decrease, the increased circuit design complexity results in

7

increased chip size. This has been the major driving force for increased wafer diameter for the last twenty five years, that is, to increase the required number of IC’s per wafer in order to reduce IC manufacturing cost. Figure 1-2 shows the wafer diameter evolution in the industry since wafer diameter was about 1.5” in 1960s. In the 1990s, 200 mm is the main stream, which was initiated in the late 1980s. In 1995, the development of a 300 mm wafer was begun, targeting for IC manufacture in the 0.25 pm/ 0.18 p m design rule generation. Concurrently, Japan has some development projects on the 400 mm wafer era technology.

1.2 Metallurgical-Grade Silicon The source of the raw silicon used for semiconductor purposes is metallurgicalgrade silicon, manufactured by the carbothermic reduction of silica in an electric arc furnace. Silica, occurring naturally as quartzite, in vein quartz, and in sandstone, and as unconsolidated sands and gravels, is a common mineral with worldwide distribution. Silicon, after oxygen, is the second most abundant element, but does not occur naturally in its elemental form. Silica, either free as in quartz or in the many forms of silicate igneous rocks, constitutes about a quarter of the earth’s crust. However, the silicon metal producers demand an ore purity of better than 99% Si02, and also place tight restrictions on the allowable concentrations of various impurities present - in particular arsenic, phosphorus, and sulfur so that often only a small fraction of an ore deposit meets their purity specification. Geologically washed out gravel from river bed deposits, and similarly leached out quartz sands, are a source of very high purity silica. Vast deposits, yielding quartzite ore of the highest purity available today,

8


have been discovered in Arkansas, U.S.A., from which monocrystals weighing several tons apiece have been displayed i n exhibitions worldwide. In the traditional electric arc furnace process, which has been used for most of this century, chunky quartzite is reacted with carbon, as the reductant, in the forms of coal, coke, or charcoal. which can be a source of at least an order of magnitude greater impurity levels than present i n the silica. The overall reaction appears simple: SiO,

+ 2 C -+ Si + 2 C O

(1)

However. as discussed by Healy (1970), the actual reaction sequence in the different temperature zones of the furnace is far more complex than this, as set out i n the schematic diagram of Fig. 1-3. ( a ) Towards the bottom of the furnace, in the region of the arc between the electrodes where the temperature can exceed 2000 "C. silicon is produced by the reaction

S i c + SiO,

+ Si + S i 0 + CO

(2)

(b) Above this, at a somewhat lower temperature, around 1700-1500"C, the rising byproduct gases react to form the intermediate product silicon carbide by Si0 + 2 C

-+

S i c + CO

(3)

(c) Nearer to the top, where the temperature falls below 150OoC,as is expected thermodynamically, the reverse reaction predominates: S i c + CO -+ SiO,

+C

(4)

The input materials are fed into the top of the furnace, while liquid silicon is periodically tapped from the bottom and cast into ingots. If this casting is carried out directionally, under the conditions referred to as normal freezing, impurity redistribution can be used to effect some purification, following the well equation by Pfann (1952, 1958):

For the arc process to run properly, it is essential to maintain porosity throughout the charge to allow uniform S i 0 and C O gas

Figure 1-3. Schematic diagram of the submerged-electrode electric arc furnace for the production of metallurgical grade silicon.

1.2 Metallurgical-Grade Silicon

flow, and to permit the escape of CO, some SiO, and H,O from the top. To assist this wood chips may be included in the feedstock, and the silica must be of a form which does not readily crumble during initial heating in the upper part of the furnace, which could lead to premature fusion and crusting over, with the risk of a dangerous pressure buildup within the charge. Clearly the carbothermic reduction of silica is not a trivial process. Crossman and Baker (1977) have given a very interesting comparison of the impurities present in typical quartzite and the carbon used, related to the spectrographic analysis of more than 2000 tons of the metallurgical-grade silicon produced. Their data, collected into Table 1- 1, indicated total impurity levels in the quartzite of around 750 ppma; in the carbon 8000 ppma, and in the resulting metallurgical-grade silicon (MG-Si) 4000-4500 ppma. Within this analysis the two predominant impurities are seen to be aluminum and iron, largely originating from the carbon, and taken together accounting for over 80% of that in the silicon product. Since these results referred to

Table 1-1. Impurities in silica, carbon, and metallurgical-grade silicon. Impurity

AI

B Cr Fe

P Others Mn Ni Ti V a

Weighted;

Quartzite (ppma)

Carbona (ppma)

MG-siliconb (pema)

620 14 5 75 10 10

5500

15702580 4 4 2 13 137k 75 2070+5 I O 282 6 -

40 14 1700 140

600

7 0 k 20 4 7 2 28 163k 34 l o o k 47

average value + standard deviation.

9

MG-Si to be used for the production of semiconductor grade polycrystal silicon, the importance of the purity of the carbon source is underlined. Recent developments have focused on improved and cleaner processes, better quality carbon, and efforts to develop quartz sands as an alternative low cost and high purity source. Maintaining charge porosity constitutes the most serious restriction in the operation of the submerged arc furnace, and much attention has been focused on how to meet, or circumvent this problem. In work aimed to reduce drastically the impurities in arc furnace silicon, Dosaj et al. (1978) working at Hemlock Semiconductor Corp. U.S.A. reported using a high purity silica source together with carbon black powder, pelletized with pure sucrose binder, to obtain MG-Si at 99.99% purity. Although the carbon content of the material was relatively low, this particular element tends to be more persistent through the later stages of semiconductor silicon manufacture, and therefore recently there has been interest in exploiting the lower boron content of carbon obtained from petrocoke. The pelletization of upgraded quartz sands can provide very pure silica in a suitable form. This material then has to be agglomerated to lumps, either separately or mixed with carbon powder. This approach has been studied by several groups, including Elkem A B , Norway, the largest European silicon metal producer, but until now it has only been taken to a development stage. The Siemens advanced carbothermic reduction (ACR) process has recently been described by Aulich et al. (1985), in which high purity pelletized quartz sand is reduced by carbon granules, prepared from carbon black briquettes, which had been leached with hot HC1 to a purity comparable to that of the silica. Since in an arc furnace about 10% of the carbon comes from the elec-

10


trode, the effective carbon impurity level was somewhat higher. Nevertheless a substantial overall impurity reduction was achieved. A more radical approach to overcoming the porosity problem has been the application of DC plasma-arc techniques to the production of ferrosilicon alloys and silicon metal. The most important feature of the plasma-arc furnace here is that it can process ore fines directly, without prior briquetting or pelletization. The potential of this route is supported by the extremely efficient plasma purification of normal MGSi, by factors of up to 100 000, reported by Armouroux et ai. (1986). The great evolution of heat from the oxidation of aluminum forms the basis of the Thermit process for the reduction of refractory oxides, such as Cr,03, and MnO,. By the application of this technique to silicon, an entirely new manufacturing route has resulted from the extensive work by Dietl and Holm [see, e.g.. Dietl et al. (1981) and Dietl and Holm (1986)l at Wacker Heliotronic, Germany, on the aluminothermic reduction of quartz sand in a liquid flux system (CaO-SiO,) at a temperature of 16001700°C: 3 SiO,

+ 4 A1 -+ 3 Si + 2 AI,O,

(5)

The flux serves simultaneously as a solvent for the byproduct aluminum oxide, and as a liquid-liquid extraction medium. As the silicon is released it is immiscible in the flux and so separates. Since the silicon is of lower density, if floats as the upper layer and at intervals can be poured off into a mold. where controlled normal freezing further separates low segregation coefficient impurities. The silicon made by this novel semicontinuous process is of relatively high purity compared with normal MG-Si. It is characterized by low boron and carbon levels. and after subsequent grinding, acid

leaching, and liquid-gas extraction, provides a material that is suitable for solar-cell applications. During the past decade, the most important economic trend in silicon metal production has been abandonment of the earlier small scale multi-unit plants, having limited productivity, for the use of very much larger electric arc furnaces, commonly dedicated to a particular product, which operate with lower unit costs. A modern commercial submerged-electrode arc furnace built in a three phase, three electrode configuration, each of these 1.25 m in diameter, and driven from a 24 MW power source, can produce 8000- 10 000 t/a metallurgical-grade Si at an energy consumption of 12-14 kWh/kg. The demand for metallurgical-grade silicon is dominated by the iron-steel and aluminum alloy industries, which require 98% purity metal. A somewhat higher quality, of 99%+ purity, is required for conversion into chlorosilanes, the key intermediates in the synthesis of organo-silicon compounds for the silicone industry, leading to products such as oils, resins, lubricants, and water repellants. Although the semiconductor industry wants the highest purity it can obtain, the amount needed still represents only a very small fraction of the world’s output. For example the global production of MGSi i n 1986 was just under 600 000 t, from which the organo-silicones consumed about 20%. By contrast, in that same year the production of semiconductor-grade, ultrahigh purity, polysilicon reached about 6000 t representing a consumption of less than 2% of total MG-Si output, and, significantly, only a fraction of the capability of a singlearc furnace. Western Europe accounts for over half the world capacity, led by Elkem, Norway, and Pechiney, France at 100 000, and 75 000 tons per annum, respectively. Thus, in summary, while the manufacturers of semiconductor silicon can have only

1.3 Semiconductor Grade Polycrystal Silicon

limited influence over the quality of metallurgical silicon, there have been improvements in this product. While these have probably been driven more by the much larger organo-silicon purity needs, some of the companies in the MG-Si industry have established strong links in the semiconductor market, and their contributions are of greater significance when set against the global background of silicon metal production.

1.3 Semiconductor Grade Polycrystal Silicon As shown in Table 1-1, metallurgicalgrade silicon of 99%+ purity contains, in addition to carbon, the major impurities iron and aluminum at more than lOOOppma, various transition and other metals - titanium, chromium, etc. -at around 100 ppma, and lesser impurities, including boron and phosphorus, at lower levels of 10's ppma. Today, dopants and carbon in semiconductor grade polysilicon are reduced to parts per trillion (ppta: 1 in lo'*) levels. For the producers this extremely demanding task has to be achieved economically, to meet the very competitive market pricing pressures which dominate the industry. Early polysilicon plants were built with a capacity of around 100 t/a, but today, to meet price targets, the latest plants are built with capacities around 1000 tons, or more.

MG-Si

Pure anhydrous HCI

Two main routes are available for the production of semiconductor-grade silicon from MG-Si; either via chlorosilanes (principally trichlorosilane, SiHCl,), or via silane (SiH,). The former has been predominant since the late 1950s. 1.3.1 The Chlorosilane Route

This process, developed at Siemens (Bischoff, 1954), rapidly superceded the earlier SiCl,/Zn method, which had been the principal silicon source until that time. There are three basic key steps in the process: (a) Reaction between powdered MG-Si and hydrogen chloride gas in a fluidized bed reactor to form trichlorosilane (TCS). (b) Fractional distillation of the TCS to provide it in an ultrapure, ppba, form. (c) Reduction of the ultrapure TCS by hydrogen in a chemical vapor deposition (CVD) reaction to yield the desired product - semiconductor-grade polycrystalline silicon. The fundamental, reversible, reaction is Si,,,

+ 3 HCl,,,

fluidized bed

0 CVD

The layout of a fluidized bed unit is shown in Fig. 1-4. However, again the actual reactions are more complex, and between this

H,, HCI

grit

J r

T Heater

11

Condenser

300-4OO0C

I

I

Heating

Cooling

SiHCI,,

SiCI,

Figure 1-4. Layout of a fluidized bed reactor. The high degree of recycling in a chlorosilane plant is similar to that in a silane plant see also Fig. 1-5.

12


and the later stages of the process there is considerable recycling. The overall flow design of the plant, the efficient use of heat exchangers, and precise control of the recycling of intermediates are crucial factors in the operating costs. The reaction between powdered silicon and anhydrous hydrogen chloride gas in the fluidized bed, held at 300 to 400 "C is highly exothermic, producing a mixed output which contains about 90% of the wanted SiHCI, [Boiling point (BP): 3 1.8 "C], about 107~SiC1, (BP: 57.6"C), and also a little dichlorosilane, SiH2C12 (BP: 8.5"C); together with hydrogen, unreacted HCI, and some volatile impurity metal chlorides. For this conversion high purity anhydrous HC1 gas is essential, and a complex purification plant is needed to guarantee the €1 ppma level specified for this stage. Phosphorus trichloride (BP: 76"C), and boron trichloride, which is a gas at room temperature, are the two principal electrically active impurities carried over from the MG-Si; arsenic, as AsCl, (BP: 130°C) is also present to a lesser degree, together with small amounts other volatile metal chlorides, such as AlCI,; but the fluidized bed stage does reduce the incoming impurity levels quite substantially. At the next stage conventional high performance multiplate fractional distillation is employed to refine the TCS, separating i t from other chlorosilanes and Si-H-C-Cl species present, and reducing the undesirable metals to ppba levels. The fractional distillation is backed up by the use of selective adsorption techniques to reach the very highest purity possible. This stage is pure chemical engineering, akin to that to be seen at any petrochemical refinery. Provided that they are kept completely dry, chlorosilanes, and also anhydrous hydrogen chloride, are chemically inactive in both liquid and gaseous form. and therefore can be moved and

transported in conventional carbon-steel pipelines and tanks, but special valves and pumps are needed to maintain a totally leakfree environment. Thus the final ultrapure TCS is relatively easy to handle onwards to the next, silicon deposition, stage. The quality of the semiconductor-grade polysilicon obtained from TCS is seen in Table 1-2, which shows the low levels of all impurities typically achieved. There has had to be much development of new analytical techniques in order to be able to quantify these impurities. Even using the highly sensitive method of ultraviolet spectroscopy, all metals are normally at a level below their respective detection limits. Special grades of even higher purity are available, for example, for epitaxial deposition. At this level often the only way to discriminate between two source materials is by their comparative performance under rigorously controlled conditions. When the data in Table 1-2 are compared with earlier published results, as for example those given by Crossman and Baker (1977) (their studies of MG-Si have already been mentioned). The third stage of the process is silicon deposition, where the Siemens chemical va-

Table 1-2. Impurities in semiconductor-grade polycrystalline silicon* Impurity

Concentration

Carbon Oxygen Donors Acceptors

< S O ppba not quoted <SO ppta < I O ppta

Bulk Metals (Fe. Cr. Ni, Zn and Cu)

< O . l ppbw (cumulative)

Surface Metals Na Other metals individually

5x103, at a stress in the silicon > lo9 N m-2. At higher temperatures, the elastic bending gives way to plastic deformation as the stress is applied, shown in the plot of Fig. 1-25.

Figure 1-24. Surface damage in silicon. Annealing of an abraison scratch in a { 11 1 ] orientation polished slice (1 100°C for 30 min]. (a) Interference contrast microscopy revealing slip relief along [ 11 1 ] planes. (b) X-ray topograph showing the stress relief by plastic flow, creating a network of long dislocation loops on [ 1 1 1 ) slip planes on either side of the original scratch.

Since both silicon and germanium are hard brittle elements of the diamond cubic lattice structure, from the outset of the semiconductor industry diamond sawing has remained the prime route to slicing ingot material. Initially the sawblades were steel discs, slotted around the periphery, into which diamond grit particles were pressed. Such saw discs when rotated at high speed around 1500-2000rpm, with water as a coolant, cut both germanium and silicon

44


Figure 1-25. Deformation and fracture of silicon resulting from mechanical stress. Note: For silicon Y/(l - P ) = 1.8 x IO" ( N m->), and so, approximately, the stresdstrain ratio is 2 x 10" ( Y : Young's modulus, P : Poisson's ratio). Hence for example at a stress of 10' N m-? the corresponding strain is 5 x

1500 r

c

m

W L

n

500 I-

-

Elastic deformation

0 ' 10'

1

I

I

l

l

lo8

1O'O

Yield stress (Nrn-')

well. However, to cut thin slices accurately such blades have to be thicker than the wanted slices, and this is obviously very wasteful of the crystal material. As a result, these peripheral blades were rapidly superseded by internal diameter blades. Thin high tensile rolled steel sheet is punched out into large discs with a central hole around which a band of diamond of closely controlled particle size is electroplated. This blade is clamped into a mounting frame which is stretched over an outer ring in high tension, sufficient to enlarge the central diamond saw hole towards its elastic limit, so providing a thin but extremely rigid blade, capable of very precise slicing with minimum kerf loss of material. Very considerable effort has gone into the development of the internal diameter sawing machines and blades to meet the continuing scaling up of slice diameters. When an internal diameter diamond blade, stretched in tension over an outer ring and rotating at high speed, is driven forward into silicon to saw a slice, the tension is slightly relaxed and the blade vibrates (wobbles) slightly. The ingot on one side of the kerf slot is rigid, whereas the partially cut slice on the other side of the sawblade can relax a little. As the blade edge vibrates. the diamond on its sides impacts

against the ingot and slice, causing differential damage, where, on the next cut, the newly exposed ingot surface becomes the other side of the next slice. Such slices may be cut perfectly uniform in thickness but bowed, until they are etched to remove the damage before polishing, when they relax to a very low bow value. On the other hand, if a blade is mounted and run incorrectly, so that it deflects during slicing, no amount of subsequent etching can correct the ensuing permanent bow. The forces which are generated at the blade edge during sawing can be followed by mounting the ingot on a dynamometer attached to an x - y - z - t chart recorder. The forces F,, F,, and F,, measured simultaneously as the blade traverses the full diameter of the ingot, are related to the operating conditions. Typical results, looking at variable cutting rates, are shown in Fig. 1-26. Here F , is the direct loading force between the advancing ingot and blade, F , is the tangential, dragging, force along the blade periphery, and F , is the smaller, but very important, vibrational force perpendicular to the blade. At a low feed rate the saw is only in gentle contact with the silicon and free to vibrate; then, as the feed rate is increased towards its optimum, the blade is held more firmly and vibration decreases . .. and on the

1.6 Wafer Preparation

45

- 160 -

- 120 -9 ’c

n

L

{

0.4 -

E

5

)r

n

-80

z

.-VI

0.2 -

:40

-I

i A

0

I

1

2

3

I

I

4

5

0

5-

Saw feed r a t e Icm rnin-’1

(a1

-3

-2

-1 0 1 2 3 Saw blade deflection (pml

(b)

Figure 1-26. Damage during silicon slicing. In (a) the force measurements and bow were recorded using distilled water as the cutting fluid ( 0 Fx, x F y , + F,, 0 bow). The effect of replacing this by a 1 % solution of polyethylene glycol (6000 mol wt.) is seen in a force F, ( A ) of 0.04 N, and a bow ( 0 ) of under 10 Fm, Subsequently in (b) it is necessary to etch the sawn slices to reveal the true distortion associated with blade deflection. + marks the zero bow, zero saw blade deflection intersection of the two axes.

slices sawn so does the bow. Finally, as the feed rate is set too high, the pressure between the ingot and the blade begins to relax the blade tension, F , starts to rise again and the bow becomes severe. Taken further, beyond its stress limit, the blade ruptures. The role of the cutting fluid, “lubricant”, can also be studied. As an example: at such high rotation rates, around 2000 rpm, centripetal forces rapidly remove the cutting fluid from the blade edge, and the liquid film whose thickness should provide a cushion against F , is very thin. The long chain molecule polyethylene glycol both improves the streamline flow of high speed liquids and increases their viscosity, so maintaining a thicker film. Applied to silicon slicing under otherwise optimum feed conditions, the F , is halved, and the bow reduced even more. It is recognized that the slicing quality has key influence on the yield on the subse-

quent polished wafer manufacturing steps, and has major impact on the overall production cost. For ULSI fabrication, the mechanical specifications for wafers are stringent and tolerances are tight on parameters such as local flatness, TTV, thickness distribution. To improve these parameters for large diameter wafers (>200 mm) the ID saw is being replaced with multiple-wire saws as previously discussed in the section on sawing. During later device processing the slice meets several high-temperature stages in which, if residual peripheral damage is still present, the heating and cooling gradients will lead to slip, and yield losses. This is shown in Fig. 1-27. Here the transistor printout marking of rejects on-slice at Test1, matches the slip, revealed by etching the back of a slice, which had been inadequately etched after grinding. Lapping is a very different issue. While it is used after slicing to provide slices of

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46


Figure 1-27. Device failures from slice fabrication. The Test-I printout on-slice of UHF transistor rejects in (a) is linked directly to the process induced crystallographic defects revealed by selectively etching the reverse back face. seen in ( b ) .Note the high incidence of failures initiated from the periphery. particularly near to the reference flat. contributed to by insufficient ingot etching after grinding.

the close thickness uniformity necessary to proceed on to etching and polishing, to remove any saw marks, and to improve the planarity and parallelism, fundamentelly i t is a retrograde process. The abrasive pressure is directed into the silicon surface. Under very low load, i n hand lapping, the depth of damage generated is proportional to, but somewhat greater than the abrasive particle size (Buck and McKim, 1956). When the pressure is increased, as is necessary to achieve useful stock removal rates from commercial lapping machines, both the depth of damage. and the site density. rise steeply - under normal operating conditions to at least 3-4 times particle size. For example using a 20 pm, close particle size distribution, water classified alumina. WCA, at a load of 30 g/cm’, the damage extends to a depth of around 90 pm - worse than in the original sawn slice. Where lapping is part of the slice machining, deep etching is needed subsequently to remove the subsurface structural damage i t has caused. The issue of residual mechanical damage and flatness requirements in the large slices,

of diameter 200 mm and above, required for the latest ULSI microprocessor and memory chip applications has focused attention on the lapping process and possible alternatives. The new standards of flatness in the final polished wafers are measured in hundredth of a micrometer (pm). This is needed because, in the fabrication of ULSI circuits, the lithography uses submicrometer dimensions with minimum feature sizes currently around 0.2W0.18 p m but decreasing and expected to be down to 0.1 pm by the year 2006. Associated with these dimensions, the thickness of gate oxides is now below 50 A, and with close tolerances of f a few angstroms, and is decreasing. Thus the underlying substrate surface has to be polished to display required surface micro roughness in additional to the local flatness. The requirements of the wafer characteristics for ULSI processing for the current and future design rule generations is mapped out in the National Technology Roadmap of Semiconductors (SIA, 1997). Overall, mechanical damage and its elimination play an important role in determining the wafer manufacturing process and final mechanical properties of the polished wafers.

1.7 Oxygen in Czochralski Silicon 1.7.1 The Behavior of Oxygen in Silicon The oxygen incorporation behavior in a CZ growth system is the result of dynamic balance between crucible dissolution, melt surface evaporation, thermal convection and forced convection induced by crucible and crystal rotations. Since “oxygen i n silicon melt” is a dynamic system, the oxygen concentration profile along a grown CZ

Previous Page

1.7 Oxygen in Czochralski Silicon

crystal depends on the growing process. Although one can obtain an “effective” segregation coefficient from such an oxygen profile assuming normal freezing behavior, however, the coefficient so obtained has no relationship with the “equilibrium segregation coefficient”, k,. The k, is a physical constant related to the binary phase equilibrium of silicon and oxygen. In general, a segregation coefficient less than unity implies an eutectic phase diagram. The melting temperature of silicon containing oxygen is lower than pure silicon. On the other hand, if k,> 1, the solidus would terminate with a peritectic reaction. The k , = 1 would indicate a situation where liquidus and solidus merge, a condition not consistent with the phase rule. The k, for oxygen in silicon has been widely studied for the last 25 years. The reported values range from greater to less than unity, including unity. Ekhalt and Carlberg (1989), in their study of oxygen solubility, proposed a phase diagram in which the slope of the liquidus near Si is consistent with k , c l . Jackson (1988) calculated the solidus, liquidus, the eutectic point and temperature of the S i - 0 phase diagram at the Si end, using k, = 0.3. The resulting phase diagram is consistent with the properties observed in the silicon containing oxygen. The microscopic oxygen incorporation behavior is, however, intimately related to the equilibrium segregation coefficient, k,, of oxygen, as described by the Burton, Prim and Schlichter (BPS) equation (Eqs. 1-3). Investigations based on crystal growth experiments and the analyses via BPS relation have shown that oxygen does segregate during solidification and assume a non-unity k , value between 0.2-0.3 (Lin, 1996). While carbon enters the lattice as a substitutional impurity occupying a silicon site, oxygen does not, but instead enters as a bound interstitial impurity, bonding be-

47

tween two adjacent silicon atoms, in a structure which permits more complex vibrational modes (Newman, 1973). The broad 9 p m infrared absorption band, seen at room temperature, arises from a number of vibrational modes of similar energies. The concentration of bound-interstitial oxygen in silicon is measured by the 9 p m absorption (ASTM Standard F-121), and if any oxygen is precipitated within the crystal, by heating in the range 105O-60O0C, the absorption decreases. Reheating at a high temperature, > 1300 “C, disperses the precipitates and restores the absorption. However, if the temperature is held at around 450 “C, any unprecipitated interstitial oxygen present forms “thermal donors”, which cause major resistivity changes in the crystal. This thermal behavior pattern was first established by Kaiser et al. (1956) and then expanded (Kaiser, 1957; Kaiser et al., 1958). Long Czochralski crystals, which are grown over a period of many hours, slowly withdrawing into a cooler chamber, experience a different thermal history between the seed and tail ends, depicted in Fig. 1.28. The thermal history of the grown CZ silicon has profound effects on the precipitation kinetics of interstitial oxygen during the subsequent heat treatments. The oxygen precipitate gettering has been related to the reduction of leakage current yield losses of DRAM and other devices (for example, Steinbeck, 1980a, b; Lin and Moerschel, 1986). Other studies have shown device failures associated with crystal defects, either present at the start of the fabrication process or formed during it, and also linked to the oxygen status. From defect etching studies, many observers noted that where a high density of surface defect features (e.g., oxidation induced stacking faults, seen after the first furnace step) was found on one side

48

1 Silicon P r o c e s s i n g

Heat losses: Conduction along crystal and convective transfer from surface to gas

Carbon via

"o"~

Precipitate growth

900°C1

10000[

Oxide precipitation on nuclei - C, or condensing interstitial:

/ /

High temperature radiation

I

fault defects high Si interstitial concentration

1&20°C

Melt stirring and convection

9

ion into m e l t at w a l l

Figure 1-28. The variable thermal history of an as-grown Czochralski silicon crystal

of a slice, the opposite face had a very low density. In one direction, this was soon linked to residual damage remaining after slice polishing. Similar work demonstrated the relation between oxidation-induced stacking faults, the slice heat treatment temperature, and oxygen precipitation (Matsushita, 1982). Much device engineering research was explored the generation and suppression of oxidation-induced stacking faults during fabrication (Stimmel, 1986), but to use bulk silicon it is necessary to understand the basic precipitation mechanism.

1.7.2 The Precipitation of Oxygen in Silicon In normal CZ growth processes, the interstitial oxygen incorporated during solidification is on the order of 1 0 ' 8 / ~ m 3This . oxygen concentration is above its solid solubility limits at the subsequent thermal processing temperatures, Le., the oxygen is supersaturated. The kinetics of the precipitation varies depends on the thermal history, the oxygen concentration and degree of oxygen supersaturation and heat treatment temperatures. Research into bulk crystallization from liquids, to produce, for example, fertilizers and salts, has contributed much to nucleation concepts, and in particular the particle


of critical radius rc. In a supersaturated liquid, or solid, at the outset tiny atomic clusters form and redisperse in a highly dynamic situation, but some merge and grow, until, reaching a certain critical radius, they become stable, and from then on will not redissolve. In such a process there is an initial incubation period during which sufficient nuclei reach r,, then faster precipitation, which dies away as the equilibrium solubility is approached. Many systems exhibit this behavior, including the solid state precipitation of oxygen in silicon, where at 750°C, the process has still not reached equilibrium after over 1000 h - solid state reactions are very slow. In this approach it should be expected that the nuclei formed by other impurities present will affect the initial nucleation induction step. Thus in the silicon case, the distribution of oxide precipitates across a slice after heat treatment closely maps the grown in carbon distribution shown in Fig. 1-1 1 (Wilkes, 1983), and also influences the actual precipitation kinetics (Kishino et al., 1979; Craven, 1981; Shimura et al., 1985; Barraclough and Wilkes, 1986). After nucleation, the main precipitation process reduces the bound interstitial oxygen concentration, developing different numbers and sizes of particles according to the temperature employed. A simple model can be used to predict the qualitative behavior correctly, and provides a basis for understanding the theoretical approach. Suppose two similar, adjacent, samples of the same impurity content, and with the same high background nucleation site density, are annealed for a long time, but at different temperatures in the supersaturation range. (1) In the sample heated at the high temperature the supersaturation driving force for precipitation is low, whereas the

49

diffusion rate of oxygen through the silicon is high. Once a few particles exceed the critical radius, rapid precipitation reduces the oxygen concentration, leading to the formation of a low density of large particles, making use of only a few of the available nucleation sites. (2) Conversely, in the sample heated at a low temperature, by the same reasoning, the supersaturation is high, but now the diffusion is low. The second phase must precipitate, but, since the oxygen only moves slowly and through a short range, a high density of small particles is predicted, making use of many of the available sites. (3) Since the native oxide film on the surface of the silicon sample is effectively a particle of infinite radius, present at time zero, and needing no incubation period, the supersaturation-diffusion model provides a simple and obvious explanation for the existence, close to the surface, of denuded zones, free of any precipitation. From the start of the heating process, oxygen close to the surface can diffuse out into the native oxide layer, so reducing its concentration and inhibiting precipitate formation in this region. The depth of this denuded zone is expected to be of a similar magnitude to the distance between particles in the bulk - deeper when formed at a higher temperature, but very shallow from a low temperature anneal. Again this is as observed in practice. In a quantitative approach, the mathematics of diffusion-limited precipitation (Ham, 1958) have been applied to the case of oxygen in silicon. The starting concentration of bound interstitial oxygen, C,, is assumed to be uniform. After a short induction period

50


small precipitates are formed, whose density, N , remains constant throughout the remainder of the process. The particles are assumed to grow by diffusion with a spherical shape, and a common radius, ro(?),small compared to the interparticle distance, and taken to be a constant corresponding to the final value ro, at r -+ The particle are a form of silica containing oxygen at a concentration C,, while that in the matrix close to the particle is C,,, the equilibrium solid solubility at the temperature chosen. The Wigner- Seitz approximation replaces the cubic cells around each particle, accounting for the total volume, by equivalent spheres of radius R, defined by (4/3) II R3 N = 1. The oxygen concentration profile as a function of position, and time, C ( r , t ) can be represented by a Fourier series:

In this result 5, has the dimensions of inverse length, and can take an infinite number of discrete positive values, which are the required solutions. Expanding this in a power series for small values of the argume nt gives (1-1 1)

CQ.

If a particle does not nucleate, ro = 0; there is no oxygen diffusion, and the supersaturation is maintained indefinitely. Normally, after an initial transient, the first term of the Fourier series in Eq. (1-7) dominates when

(1-13) (1-7)

satisfying the boundary conditions C = C,, at r = ro, and where z,, is the relaxation time constant. Fick's diffusion equation i n spherical coordinates may be written

while the requirement that there be no net oxygen flux across the outer sphere boundary is defined by =0,

(1-12)

I

ri=O

-D($)

and

( 1-9)

D#O

r=R

Differentiating Eq. ( 1-7) with respect to r and t and substituting into Eq. (1-8) leads to the core expression given by Ham: tan [A,?(r-r0)]= A,, r ,

r =R

(1-10)

The constant A, & has the dimensions of concentration and a value somewhat less than Co- C,, . The oxygen distribution so described is essentially uniform, with a value slightly less than C,, throughout the diffusion volume, except i n a small region of radius about 5 ro, around the particle, in what may be described as a random-walk - well model, as shown i n Fig. 1-29. Further manipulation of the equations leads to two important expressions: (1-14) and

If it is reasonably assumed that the oxide is close to SiO, in its composition, then a

51


(SANS) to validate the theoretical model (Livingston et al., 1984), as shown in Fig. 1-30.

10j

Temperature (“0 1100 1000 900 800 700 I

I

l

I

I

(

I

I

O

I

10l4

I

1

I ,/’ !/

,’

I

,’

/ I

;

,

I,’\, \

’.

I

I

/

I

1013m-.

‘\\

I

‘,

\

‘.

10’2

-a6 c .-

) I

Wl

10’0

5

-.-al 109 ; Y

n

Figure 1-29. The random-walk - well model of dif-

108

fusion limited precipitation.

’” 7.0 Only within a region of about 5 x the particle radius does a diffusing oxygen atom become trapped to a particular site and the number of particles formed is strictly defined.

value can be assigned to C,. The values of C,, C,,, and the relaxation time constant, zo, are obtained from the infrared absorption measurements used to follow the precipitation process (Binns et al.; Newman et al., I983 a; Wilkes, 1983). Hence, values for the particle density, N , and its radius, Y, can be obtained at various annealing temperatures, based solely on kinetic data. This can then be compared with direct measurements obtained from integrational etch pit counts, and scattering. By near infrared transmission the optical scattering from the large particles formed by high temperature anneals can be used to calculate Nand Y. Similarly, the very small particles, with radii less than 100 A, can be measured by small angle neutron scattering

8.0

9.0

10.0

11.0

10’

ioL/ T [ K - l I Uxygen precipitation in silicon. 1he particle radii and their corresponding number densities, based on the four methods shown, all assume spherical geometry. However, in the random walkwell theory the particle shape does not significantly affect the overall data given. The symbols are: 0 radius derived from kinetics, radius from etch pit measurements, x radius from neutron scattering, + radius from optical scattering.

kigure

1-JU.

Figure 1-31. Direct lattice image of a platelike oxide precipitate in silicon. Finlike features extend above, and probably below, the main (100) habit plane. Sample annealed at 750°C for 431 h .

52


The analysis of SANS results also provides information about the shape of the particles, which has recently been allied to high resolution transmission electron microscopy, to reveal platelet precipitates, shown i n Fig. 1-31 (Bergholtz et al., 1989). The total assembly of particle radii from these various techniques, plotted against reciprocal temperature in Fig. 1-30, shows a remarkable coherence of results, i n spite of the different nature of the experimental methods and approximations involved, and the diffusion-limited precipitation theory underpins the qualitative model set out earlier.

1.7.3 Thermal Donors and Enhanced Diffusion The problems surrounding the understanding of thermal donors, their formation, and behavior, are aggravated by the lower temperatures involved, 350-5OO0C, in any kinetic study, and by the complexity of their structure, where work suggests that four interstitial oxygen atoms are involved i n a TD center (Newman and Claybourn, 1988). Following the oxygen precipitation kinetics at low temperatures requires a more sensitive method than infrared absorption; this is provided by the technique of the relaxation of stress induced dichroism (Corbett and Watkins, 1961), which has been applied to the silicon-oxygen system (Benton et al., 1983; Newman et al., 1983b). In this procedure, a small silicon rod sample, cut with a [ 1 1 11 axis, is heated at a temperature of 45O-50O0C, under a high pressure applied along the axis; subsequently the sample is cooled while still under stress. As a result of diffusion while stressed, the number of bound interstitial oxygen atoms, n , , linking matrix silicon sites in the [ 1 1 11 axial bonds becomes less than the number, n 2 , in each of the bonds in the [ T I T ] , [TTl].and [lTT].directions. Ifnow

linearly polarized 9 ym infrared light is used to measure the oxygen absorption coefficient, in directions parallel and perpendicular to the stressed [ 1 1 1 ] axis in the samples, the following relations apply:

from which

(aL-q )= const . ( n 2- n l )

(1-17)

When such a prepared test sample is then annealed at some chosen temperature but under no load, further diffusion allows the oxygen to return towards a random distribution, relaxing the induced stress dichroism, by a first order kinetic process, with a relaxation time constant z*.Using a normalized dimensionless parameter ( aL- aii)/a, the constant z* is given by the slope d [log (aL-al~)/a,]/dt, and is equal to z/8 where l / t i s the fundamental frequency of a single diffusion jump at the temperature concerned. The diffusion coefficient then follows from the simple relationship that D = ai/@ t),where a. = 5.42 A, the lattice constant of silicon. An early problem in the understanding of thermal donors arose from their speed of formation, requiring only a short heating time to reach an equilibrium resistivity. The role of lattice defects in this process is now recognized to be a major contributor. In their stress dichroism study, Benton et al. (1983) observed that, if the silicon was given a 9OO0C/2 h heat treatment followed by quick cooling to eliminate donors (but thereby freezing i n excess silicon sei€-interstitials) before going into the stress dichroism procedure as described above, the value of the diffusion coefficient, D, was enhanced by nearly two orders of magnitude. Another way to alter the intrinsic defect balance in silicon is by irradiation. Newman et al. (1983 b) used 2 MeV electrons onto a

1.8 Gettering Engineering

stressed silicon sample target held on a water-cooled block at well below 60°C. After irradiation the 9 pm signal was lowered, while the generation of oxygen-vacancy ( 0 - V ) A-centers was measured by their infrared absorption at 830 cm-’. On subsequent relaxation, the induced dichroism now decayed exponentially - with D several orders higher. Oxygen can also trap mobile silicon self-interstitials, to form an (0-1) center, with absorption at 935 cm-I. Tin is an efficient trap for vacancies in silicon; as-grown Sn-doped crystals have similar (0-1) center concentrations to undoped silicon, but substantially lower ( 0 - V ) A-center levels, and in this material the relaxation of stress dichroism is retarded by a factor of approximately 6. Involvement of both vacancies and interstitials in this diffusion was proposed by Gosele and Tan (1983). A simplistic view of a single jump could be that either oxygen traps a vacancy to form an Acenter, which then intersects a self-interstitial, or, alternatively, an (0-1) center is formed, which then traps a vacancy. The reality is more complex than this. Enhanced diffusion is seen after metallic contamination by copper or iron. Carbon enters into a number of low temperature centers with oxygen and silicon, and as nucleation sites for self-interstitials (Davies, 1989). Free electron effects have been used to provide an explanation for dopant concentration-dependent thermal donor kinetics (Wada, 1984; Wada and Inoue, 1986); while in the precipitation of oxygen in heavily doped, n’ and p’, silicon, Bains et al. (1990) have observed both enhanced (p’) and retarded (n’) precipitation, which they also link to the free electron model. Finally the thermal donor formation in p-type, 0.3 0 cm, material at 450°C is accompanied by the simultaneous loss of substitutional boron (Newman and Claybourn, 1988). Overall, while the diffusion-limited

53

precipitation model provides a sound basis for understanding the behavior of oxygen in dislocation-free silicon, which is applied in the “crystal engineering” discussed next, there is still much to be learned about the detailed mechanism of enhanced diffusion and thermal donors.

1.8 Gettering Engineering In the preceding sections of this chapter, reference has been made at various points to the ability of defects to act as gettering sites, sinks, for fast diffusing impurities. Also the serious deleterious effects of such defects, where they intersect device structures, has been emphasized. In addition the very slow nature of solid-state oxygen precipitation, seen above, has to be overcome if any use is to be made of such bulk precipitates. The controlled application of external surface mechanical damage (extrinsic gettering), and internal bulk oxide particles (intrinsic gettering) is now addressed. 1.8.1 Extrinsic Gettering in Silicon Mechanical damage in a silicon surface has to be quantified in both density and depth, where as seen in Figs. 1-22 and 1-23, only a few damage sites extend to any great depth. Since etch rates are a function of the intensity of damage, they fall rapidly during the initial stages of etching, so it is very difficult to leave a well-controlled residual damage level on the back side and achieve the required slice thickness tolerances by trying to limit the etching. This also leaves more to be polished off the front surface. What is required is to create intentionally a high density of relatively shallow lattice disorder, whose associated stress relaxes into stacking faults and dislocation loops early on the device thermal processing, to

54


provide a high gettering capacity. The lattice distortion around the dislocations sets up strained regions, the actual gettering sites, which, in accommodating the diffusing impurities, relax further into stable lower energy atomic configurations. There are several controlled backside damage options available from polished slice suppliers, aimed to match the individual device processes: MOS, bipolar, etc. The damage is reinserted starting from well-etched slices. One method, widely used, employs a high adjustable-pressure water jet system, commonly used at around 1000 psi (=70 bar), which contains fine ground silica of well-defined particle size (about 1 pm). The grades of damage generated by the impingement of this jet on slices traversed beneath are achieved by varying the pressure, number of jets, and the traverse speed. Afterwards the front surface is polished in the normal way. Typical site densities obtained by this treatment range between 5x 1 O3 cm-’ to 5x10’ cm-’. An example of a higher damage level slice, before and after treatment, is shown in Fig. 1-32, while the rocking

Figure 1-32. Extrinsic gettering by silica-high pressure water jet treatment. Note the well-etched surface to remove uncontrolled damage prior to treatment, and the uniformity of mechanical damage sites generated ( S E M photograph).

curve broadening from this process is low to moderate: AW = 10” to 30”. (Note other values: deep-etched slice 0” to 4/8”, sawn slice 80” to loo”, lapped slice AW> 120”.) Lighter damage is most suitable for MOS device processes when, during the first oxidation at around 1000-1 IOO’C, stacking fault gettering sites are formed on the treated back surface at a density of around lo5 cm-2, which has a negligible effect on the subsequent mechanical behavior, warp, etc. However, as device feature sizes continue to shrink, there is strong emphasis on reducing both the maximum temperatures, and the total thermal inventory, used in fabrication. At temperatures below 1000°C the stacking fault generation is more complex and influenced by the oxidation ambient (Claeys et al., 1981). Again, if the damage is too light, instead of forming getter sites on heating, a large proportion may be annealed out. This is seen when first stage polished surfaces, with some submicrometer damage, are compared by etching to reveal defects before and after an 1100°C thermal cycle, when most of the damage sites disappear, and too low a stacking fault density results. The gettering performance, extrinsic or intrinsic, is monitored by etching the front polished surface, in which the device structures are fabricated, to reveal point defect sites: S-pits - shallow saucer etch pits, or haze, which are known to be related to the presence of heavy metal impurities, to low carrier lifetimes, and to emitter-collector leakage, which are all detrimental to yields. Again where the device process involves a number of high temperature stages, the extrinsic gettering performance gradually falls, and a higher initial damage level is necessary to counter this. For bipolar applications the same rules stand, but now the process employs higher temperatures, up to 1200 “C, where shallow


damage sites are more easily annealed out, and gettering performance falls more rapidly through the successive high-temperature stages. While damage depths around 1-1.5 pm may be adequate in an MOS process, bipolar conditions can demand 24 pm, and even then the efficiency may be lower. Alternative approaches for inserting the mechanical back-surface damage, also widely used, are brush damage, or abrasive polishing, of the deep-etched slice, an example of which is seen in Fig. 1-33. By choice of materials and operating conditions (soft or hard brush, abrasive size, pressure, etc.) well-controlled products result, suitable for both MOS and bipolar applications. Finally, in a further development of extrinsic gettering, it has been recognized that fine grain polycrystalline silicon is an excellent, high temperature resistant, gettering material. Using low pressure chemical vapor deposition (LPCVD) and a silane source, in a process closely similar to that employed during the fabrication of polysilicon interconnects, a thin, 1-2 pm, layer is deposited on the deep-etched slices, at a temperature of 6O0-65O0C, prior to the polishing stage, which becomes the extrinsic gettering backside of the slice. Known as enhanced gettering (EG) this additional step is obviously rather more expensive to manufacture than the other routes described for providing extrinsic gettering, but its performance, particularly in the multistage higher temperature applications, such as in bipolar circuits, is superior, maintaining very low S-pit densities, and high lifetimes, as shown in Fig. 1-34. Achieving the best results in this field involves very close liaison between the slice manufacturer and the consumer device engineer' in Order to match the incoming material to the specific fabrication process.

55

Figure 1-33. Extrinsic gettering by abrasive (brush) treatment: (a) and (b) show lower and higher damage, respectively. Note the well-etched underlying substrates.

56

10'


'

0

I

I

r 3 4 5 Number o f oxidation cycles

1

2

I 6

Figure 1-34. Enhanced gettering by deposited polysilicon. Compariton between EG and mechanical backside damage ( M B D ) treatments. Material: Medium oxygen content, p-type, (100) orientation. Test: bipolar oxidation cycle - 1 I O O T , steam, 2 h. S p i t s : x : lifetime: orientation: 0.

1.8.2 Intrinsic Gettering in Silicon The beneficial effects of oxygen precipitates in the bulk of a device structure, and also in the substrate of an epitaxial slice, were reported by Tan et al. (1977) and Yang et al. (1978). Now there are many papers on this topic, which, since it directly interfaces to device processing, has attracted much attention. The single stage heat treatments described in Sec. 1.7.2 are obviously far too slow to provide crystal-engineered slices tailored to meet device specifications. However, this is not the only constraint. Any useful process must make consistent intrinsically gettered slices using input silicon slices containing the varying amounts of oxygen typical of normal Czochralski growth. Earlier work concentrated on two-step processes, with a first high temperature heat treatment, followed by a second at a lower temperature, the so-called HI-LO, treatment. Typical times and temperatures used

are: 16 h at 1150°C and 64 h at 650°C (Yamamoto et al., 1980). While other variants of two-step treatments have been proposed, this HI-LO process shows the principles, using the models developed in Sec. 1.7.2 above. In the first step, the high temperature, 1 150"C, anneal is in a range where the supersaturation of bound interstitial oxygen is relatively low but diffusion high; any preexisting microprecipitates near the surface tend to dissolve. Oxygen readily diffuses to the surface oxide, so developing a concentration gradient near the surface, while deeper in the bulk, precipitates start to form. In addition to conventional analysis methods, for example, by a SIMS profile on a cut section through the slice, the concentration gradient from the out-diffusion can also be measured by reheating the sample at 450 "C, to generate thermal donors from the remaining interstitial oxygen, and then making a microresistivity scan on a beveled section, to calculate the gradient profile. The results from material with a bulk value [O,] around 8 x lOI7 cme3 show the surface concentration falling to around 5 x 1017 after 6 h, with a precipitate denuded zone 20 pm deep, while after 16 h the values are around 3-4 x I O l 7 with a denuded zone up to 50 p m deep. While the interstitial oxygen content is lowered at step 1, in the following low temperature step 2 at 650 "C the supersaturation is still high and precipitate growth continues at the sites formed at step 1 but there is little added fresh bulk nucleation. The desired intrinsic gettering structure, bulk precipitates and a surface denuded zone, is achieved - but there are problems. The amount of bound interstitial oxygen precipitated by this process, and whether or not a denuded zone is formed, are a direct function of the original oxygen content, as shown in Fig. 1-35. In addition, in this plot


a

Lo, 0

+

IV

~~

7.0

J

Denuded zone

No denuded

1

1

I

8.0

I

, 9.0

I

, 10.0

Initial oxygen concentration [ O , I ( 1 0 ~ ~ 3 )

Figure 1-35. Two-stage oxygen precipitation in silicon. Thermal cycles: 1 150°C, 16 h; 6 5 0 ° C 64 h. Other two-stage processes exhibit similar behavior, with no denuded zone formation below an initial oxygen concentration of around 8x 10" atoms/cm3.

the wider scatter of results from material of lower initial oxygen content reflects the effects of other contributory factors. For example, in the influence of carbon on nucleation, where using material of normal high oxygen content but ultralow in carbon, < 3 x 1015 atoms/cm3, the precipitation is heavily retarded, and there is no denuded zone formation (Wilkes, 1983). The effects of not precipitating enough oxygen have been demonstrated by de Kock (1982), who found that, during an n+ phosphorus diffusion into an epitaxial layer, under the diffused region the denuded zone width shrank, in one case from 50 to 25 ym, in another from 25 y m to zero. His interpretation of the denuded zone shrinkage under the diffused islands is that the rapid formation of critical nuclei and secondary precipitation is due to the local injection of a large excess of silicon self-interstitials. This links to the diffusion jump mechanism and enhanced diffusion described in Sec. 1.7.3. Such secondary precipitation is quite general, and may build up throughout a multistage process, rather than at one particular

57

step. Again, during lower fabrication temperature CMOS device processing, using substrates of medium to high oxygen content, difficulties are often encountered because of thermal donor formation, which make voltage threshold adjustment steps necessary. Reducing the residual oxygen concentration eliminates this problem. Thus, while many intrinsic gettering studies have concentrated on the aspects of denuded zone depths, and the precipitate sizes and number densities, the residual bound interstitial oxygen concentration present afterwards is a crucial performance parameter. Some two-step gettering processes rely on the first oxidation in the MOS fabrication line, at a temperature of 1000-1 lOO"C, to provide some further precipitation, but as the oxides required get thinner, and oxidation times shorter, this is insufficient. An intrinsic gettering process, which overcomes these problems and permits matching, to optimize the material characteristics to individual device lines, is provided by a three-step system which separates control of the desired parameters. The concepts are illustrated in Fig. 1-36, which shows the purpose of each step. The highest oxygen concentrations, normally met at the top of Czochralski crystals, are around 1x10'' atoms/cm3 which corresponds to a maximum solid solubility temperature of approximately 12OO0C, lower for the remainder of the crystal which contains less oxygen. In step 1 the slices are heated at a temperature chosen in the range 11001200"C, above the solid solubility values for most slices, while even in the "worst cases" the supersaturation is very low. There is no precipitation and any pre-existent grown-in nuclei (Fig. 1-28) are dispersed, to ensure that all the material is in a uniform state. Out-diffusion reduces the oxygen content substantially as described above, the time, commonly in the range of

58


5-10 h, defining the chosen depth of the denuded zone to follow, Fig. l-36a. Next, in step 2, the slices are given a low temperature heat treatment, for example, at 750°C for times between 5 to 30 h. In accord with the theory a large number of small nuclei form and begin to grow slowly, except in the reduced oxygen content layer close to the surface, where very few are formed, any that are being of very small size, Fig. 1-36b. The assemblage so produced has a statistical particle size distribution, increasing slowly as longer times are chosen, while, as required by the Ham theory and depicted in

Fig. 1-36c, their total numbers remain near constant. The concept of the stability of particles of greater than some critical radius, rc, has been introduced above. The value of this radius depends on a number of factors: (a) The surface free energy of the particlematrix interface, 0, and the volume free energy change of the precipitate, AF'" (Burke, 1965), where (1-18)

Diffusion

r

1:

n

z

Distance from surface X

(a)

I

Temperature

Distance from surface X id)

(b)

I

IO, 1

Oxygen diffuses t o growing

4

Denudedl zone I

0

0

0

Distance from surface X

(el

Figure 1-36. Three stage oxygen precipitation in silicon. Crystal engineering: (a) stage 1 : outdiffusion of oxygen to surface at 1 IOO'C; ( b ) stage 2: nucleation at 750°C; ( c ) particle size distributions at stage 2; (d) critical radius, rc, for particle growth as a function of temperature; (e) stage 3: particle growth at 1000°C.


(b) The degree of supercooling, AT, the difference between the chosen anneal temperature, T , and that higher temperature at which the solute oxygen concentration, C,, is at saturation equilibrium, and the activation energy, E,, for the formation of a nucleus of the critical radius, are related by

( 2)

N , = Co exp -~

(1-19)

where N, is the concentration of precipitate particles. (c) The volume free energy is related to the supercooling and the enthalpy of reaction, AH, by (1-20)

..=(?)AT

Finally the surface free energy for the precipitate-matrix interface is obtained from (1-21) L

J

Values for critical radii have been calculated for various temperatures and degrees of supersaturation (Freedland et al., 1977; Osaka et al., 1980). These are all very small, ranging from around 10 A at a temperature of 1050"C, which corresponds to nuclei containing clusters of about 100 atoms, down to only 3 - 4 A and clusters of 6-10 atoms at 650°C. While these numbers are very small, it should be remembered that the final precipitates grown at 6 5 0 ° C while of platelet structure, have an "equivalent" spheroid radius of only around 30 P\ (see Fig. 1-30). The form of the temperature dependence of the critical radius is shown in Fig. 1-36d. Further extension of this model to the rates of nucleation leads to predictions

59

of incubation times at the outset of single stage anneals, while stable nuclei are being formed, in accord with observations (Capper et al., 1977; Hu, 1981; Inoue et al., 1981). However, the important point to note is that the critical radius is temperature dependent, and at 750 "C is much smaller than at 1000°C. Therefore, when in stage 3 the slices are heated for some hours at 1000°C most of the small particles generated at stage 2 redissolve, leaving only those at the upper end of the statistical distribution to continue to grow. A longer heating time at stage 2 leaves more larger nuclei - so this stage defines the number density to particles from the overall precipitation process. The final stage then determines how much of the oxygen initially present is to be precipitated, and so the particle size, see Fig. 1-36e (Wilkes, 1988). The matrix of Fig. 1-37, taken from the work of Huber and Reffle (1983), shows this three-stage process in operation. All the slices were given the same stage 1 out-diffusion of 10 h at 1 100"C then groups were nucleated at 750 "C for increasing times, before the final precipitate growth at 1000 "C again for 4 increasing times. The expected pattern is seen with all having about the same denuded zone depth, while the particle density increases with stage 2 time, down the figure, and the particle size with stage 3 time, from left to right across the figure, in a well-controlled manner. The ability of the threestage process to handle a wide range of input oxygen concentrations is shown in Fig. 1-38 in comparison with two-stage results, where the high and consistent reduction in the initial oxygen level achieved ensures minimal further precipitation during subsequent device fabrication. In summary then, a three-stage intrinsic gettering process can overcome the earlier problems met in two-step methods. It ac-

60


Figure 1-37. A three-stage precipitation matrix. Note the clear separation of stage functions defining: (1) the denuded zone depth, ( 2 ) the number density, and (3) the precipitate size. Stage ( I ) was outdiffusion at 1100°C for 10 h. The initial oxygen concentration was 8 . 1 5 ~ 10” atoms/crn3. (By kind permission of Huber and Reffle, 1983.)

cepts a wide input oxygen range, and the functions are separated, with stage 1 defining the denuded zone, stage 2 the particle density, and stage 3 the particle size and the total amount of supersaturated bound interstitial oxygen removed from solid solution. The three stages allow the parameters to be

varied to meet individual customer requirements to match the material to the specific device fabrication process. Today closer links between the silicon suppliers and the users are essential. The crystal engineering of large diameter wafers has been noted previously in regard to the

1.9 Acknowledgements

61

Figure 1-38. The reduction in bound interstitial oxygen after two-stage (0)and three-stage annealing (x). The marked superiority of the three-stage process is obvious.

Initial oxygen concentration 110’~atoms/cm3)

rising demands for the control of the oxygen level in pf and n+ substrate materials, in addition to the attention already paid to this in normal p and n silicon. Both intrinsic and extrinsic gettering have been studied and practiced for many years. Properly engineered CZ crystals incorporating internal or external gettering or both have been shown to benefit device performance. As in the other sectors examined in this chapter, in wafer manufacture the market pressures have been linked closely to the advances demanded in the technical attributes engineered into the material. Knowledge of the interaction between crystal microdefects and impurities, and device fabrication and performance has increased dramatically, and has impinged on the whole process, from crystal growth onwards, which has become more and more specialized, in the hands of the high capacity merchant producers. It is here, where the closest collaboration between the silicon material vendors and the device makers is most essential.

1.9 Acknowledgements The work described here represents over 30 years of continuing research and development. The author is indebted to his many colleagues in the Materials Departments at Philips/Mullard, Southampton for their years of valued, exciting, and enjoyable, support. Particularly I must record my thanks to Dave Perkins, Roland Kingsnorth, Dave Griffiths, and Ian Baldwin, and, for their encouragement, to Stand Bradshaw, and Dr. Max Smollett and Dr. Brian Avient. I also wish to recognize our long collaboration with the U.K. teams led by Prof. Ron Newman (Reading University), Dr. Keith Barraclough (RSRE, Malvern), and Prof. Ed Lightowlers (London University), in a wide range of joint projects. The contributions to my understanding of the silicon field from many friends in the major equipment and materials suppliers, and device houses around the world must be noted. In particular, Bob Lorenzini (Siltec), Rem0 Pellin and Gordon Martin (Monsanto), Ken Jackson (Bell Labs.), Ed Giess (IBM), and Don Jackson (Motorola), have shared and discussed new developments

62


over a long period. The close links with Dr. Erhard Sirtl and Dr. Dieter Huber (Wacker Chemitronic) have contributed directly to the preparation of this chapter. Figure 1-37 (first published by Wilkes, 1983) came from the work of Huber and Reffle, and was reproduced with their permission, while Horst Fleischmann has been a prime source for my awareness of the market pressures and industry trends.

1.10 References Abe, T., Kikuchi, K.. Shirai, S . , Muraoka, S . ( 1 9 8 1 ~ in: Srmicoriductor Silic,ori 1981: Huff, H. R., Kriegler. R. J . , Takeishi, Y. (Eds.). Pennington. NJ: Electrochem. Soc.. PV81-5, p. 54. Akiyama. N., Yatsurugi. Y., Endo. Y., Imayoshi, Z.. Nozaki, T. ( l973), Appl. Phys. Lett. 22, 630. Amouroux, J., Morvan. O., Apostolidou, H., Shootman. F. (1986). Electrochem. Soc. Exretided Abstr. No. 298. PV86-I. 441, Aulich. H. A,, Eisenrit. K. H., Schulze, F. W.. Strake. B.. Urbach, H. P. (1985), 6th E.C. Photo\dtuic Energ? Conf London: Comrnun. Eur. Cornmutiities Rep. EUR 10025. p. 95 I , Bains. S . K., Barraclough. K. G.. Griffiths, D. P.. Series. R. w.. Wilkes. J . G. (1990), J . Electrochem. Sac. 137, 647. Barraclough, K. G . (1982), in: S y m p Aggregtirioti Phenomenu of Point Defects in Silicon, ESSDERC, Munich: Sirtl, E., Goorissen. J . , Wagner, P. (Eds.). Pennington, NJ: Electrochem. Soc., P V83-4, p. 176. Barraclough, K . G.. Series, R. W. (1988), Patent GB 8 805 478. Barraclough, K. G., Wilkes, J. G. (1986), in: Seniicotiductor Silicon 1986: Huff, H. R., Kolbesen, B. 0.. Abe. T. (Eds.). Pennington. NJ: Electrochem. Soc., PV 86-4, p. 889. Batterman, B. W., Hildebrandt. G . ( 1968), Actu Crystallogr: A24, 150. Benton, J. L., Kimmerling. L. C.. Stavola, M. (1983). Physicti B 116, 271. Bergholtz, W.. Binns, M. J., Booker, G. R.. Hutchins o n . J . C.. Kinder, S. H.. Messoloras, S . , Newman, R. C.. Stewart. R. J.. Wilkes. J. G . (1989). Phil. Mug. R 59, 499. Binns, M. J . , Brown, W. P., Livingston, F. M., Messorolas, S . . Newman, R. C., Stewart, R. J., Wilkes. J. G. (19831, Appl. Phys. Lett. 42, 525. Bischoff. F. (1954). Patent DBP 1 134 459. Bloem. J., Classen, W. A. P. (1980), J . Cpsr. Growth 49. 435 (part I ) , and 807 (part 2). Bloem. J . . Classen. W. A. P. ( I 983-84). Philips Tech. Rei: 41. 60.

Bloem, J., Gilling, L. J . (1978), in: Current Topics in Materials Science, Vol. 1: Kaldis, E. (Ed.). Amsterdam: North-Holland, p. 147. Bollinger, D., Zarowin, C. B. (1988), in: Advunces in Fubrication arid Merrologp f o r Optical and Large Optics, Vol. 966: SOC.of Photo-Optical Instrumentation Engineers. Bellingham, WA, pp. 82-90. Bond, W. L., Andrus, J. (1952), Am. Minerul. 37,622. Buck, T. M., McKim, F. S. (1956), J. Electrochem. Soc. 103, 593. Burke. J. ( 1 9 6 3 , The Kinetics of Phase Trunsformariotis iri Mertils. London: Pergamon, Chaps. 6 and 7. Burton, J . A,, Prim, R. C., Schlichter, W. P. (l9S3), J . Chem. Phxs. 21, 1987. Capper, P., Jones, A. W., Wallhouse, A. J., Wilkes, J. G . ( 1977). J. Appl. Phvs. 48, 1646. Carlberg, T. (l986), J . Electrochem. Soc. 133, 1940. Carruthers, J. R. (1967), J . Electrochem. Soc. 114, 1077. Carruthers. J . R., Nassau, K. (1968). J. Appl. Phys. 39, 5205. Carruthers, J. R., Witt, A. F., Reusser, R. E. (1977), in: Semiconductor Silicon 1977: Huff, H. R., Sirtl, E. (Eds.). Pennington, NJ: Electrochem. SOC., PV77-2, p. 70. Cartwright, R. A., El-Kaddah, N., Szekely, J. (1985), IMA J . Appl. Math. 35, 175. Chedzey, H. A,, Hurle, D. T. J . (1986), Nature 210, 933. Chiou. H. D., Lee, T. Y. T., Teng, S. (1997), J. Elecrrochem Soc. 144, 288 1-2886. Claeys, C., Declerck, G., Van Overstraeten, R., Bender, H., Van Landuyt, J., Amelinckx, S . (198l), in: Srmicwnductor Silicon 1981: Huff, H. R., Kreigler, R. J., Takeishi, Y. (Eds.). Pennington, NJ: Electrochem. Soc., P V 8 I - 5 . Cockayne, B., Gates, M. P. (1967), J. Mater. Sci. 2 , 118. Corbett, J . W., Watkins, G . D. (1961),J. Phys. Chem. Solids 20, 3 19. Craven, R. A. ( l 9 8 l ) , in: Semiconductor Silicon 1981: Huff, H. R., Kreigler, R. J., Takeishi, Y. (Eds.). Pennington, NJ: Electrochem. Soc., P V815, p. 254. Crossman, L. D., Baker, J. A. (1977), in: Semiconductor Silicon 1977: Huff, H. R., Sirtl, E. (Eds.). Pennington, NJ: Electrochem. SOC.,PV77-2, p. 18. CLochralski, J . (1917), Z. Phys. Chem. 92, 219. Dash. W. C. (1958), J. Appl. Phps. 29, 739. Dash, W. C. (1959), J. Appl. Phps. 30,459. Dash, W. C. (1960), J . Appl. Phys. 31, 736. Davies. G . (l989), in: Proc. 15th Int. Conf Dejtcts in Semiconductors, Budapest, Aug. 1988. Mater. Sci. Forum 3841 ( I ) , de Kock, A. R. J. (1983), Proc. Symp. ESSDERC, M u nich. Pennington, NJ: Electrochem. Soc., PV83-4, p. 58. Deslattes, R. D., Paretzkin, B. (1968), J. Appl. Crq'srtrllogr: I , 176.

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Dietl, J., Holm, C. (1968), Electrochem. SOC. Extended Abstract N. 299, PV86-I, 441. Dietl, J., Helmreich, D., Sirtl, E. (1981), Solar Silicon, In: Crystals: Growth, Properties, and Applications, Vol. 5: Grabmeier, J. (Ed.). Berlin: Springer, p. 43. Dosaj, V. D., Hunt, L. P., Schei, A. (1978), J. Met. 30, 8. Dupret, F., Ryckmans, Y., Wouters, P., Crochet, M. J. (1986), J. Cryst. Growth 79, 84. Ekhalt, U., Caarlberg, T. (1989), J. Electrochem. SOC. 136, 551. Ellis, W. C., Treuting, R. G. (1951), J. Met. 191, 53. Freedland, P. E., Jackson, K. A,, Lowe, C. W., Patel, J. R. (1977), Appl. Phys. Lett. 30, 31. Gosele, U., Tan, T. Y. (1983), Proc. Symp. ESSDERC, Munich: Pennington, NJ: Electrochem. SOC.,PV834, p. 17. Ham, F. S. (1958), J. Phys. Chem. Solids 6, 335. Healy, G. W. ( 1 970), Earth Mine,: Sci. 39, 46. Herrmann, H. A., Herzer, H. (1975), J. Electrochem. SOC.122, 1568. Herrmann, H. A,, Mucke, E. (1973), 2nd DFG Colloquium on Power Devices, Freiburg. Herzer, H. (l977), in: Semiconductor Silicon 1977: Huff, H. R., Sirtl, E. (Eds.). Pennington, NJ: Electrochem. SOC.,PV77-2, p. 106. Herzer, H. (1980), Proc. 3rd In?. Conf on NTD Silicon, Copenhagen, New York: Plenum. Hirata, H., Hoshikawa, K. (19891, J . Cryst. Growth 96,47-755. Hirata, H., Hoshikawa, K. (1989), J. Crystal Growth 98,777-78 1. Hoffman, A,, Reuschel, K., Rupprecht, J. (1959), J. Phys. Chem. Solids 11, 284. Hoshi, K., Suzuki, T., Okubo, Y., Isawa, N. (1980), Electrochem. SOC.Extended Abst,: No. 324, PV80I , 81 1. Hoshikawa, K. (1982), Jpn. J. Appl. Phys., Parr2, 21, L545. Hoshikawa, K., Kohda, H., Hirata, H. (l984), Jpn. J. Appl. Phys. 23, L37. Hu, S. M. (1981), J. Appl. Phys. 52, 3974. Huber, D., Reffle, J. (l983), Solid State Technol. 26, 137. Hurle, D. J. T. (1967), in: Crystal Growth: Peiser, H. S. (Ed.). Supplement to: J. Phys. Chem. Solids. Oxford: Pergamon, p. 659. Hurle, D. T. J., Jakeman, E., Johnson, C. P. (1974), J . Fluid Mech. 64, 565. Inoue, N., Wada, K., Osaka, J. (1981), in: Semiconductor Silicon 1981: Huff, H. R., Kreigler, R. J., Takeishi, Y. (Eds.). Pennington, NJ: Electrochem. SOC.,PV81-5, p. 282. Jackson, K. A. (1988), Bull. Of Allou Phase Diagrams, Vol. 9, No. 5 , p. 548. Jackson, K. A. (1990), Recent results, private communication. Kaiser, W. (1957), Phys. Rev. 105, 1751. Kaiser, W., Keck, P. H., Lange, C. F. (1956), Phys. Rev. 101, 1264.

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Kaiser, W., Frisch, H. L., Reiss, H. (1958), Phys. Rev. 112, 5. Kakimoto, K., Eguchi, M, Watanabe, H., Hibiya, T. (l988), J. Cryst. Growth 88, 356. Kakimoto, K., Eguchi, M. Watanabe, H., Hibiya, T. (1989), J . Cryst. Growth 89, 412. Keck, P. H., Golay, M. J. E. (1953), Phys. Rev. 89, 4297. Keller, W. (1959), Platent DBP 1 148 525. Kern, W., Puotinen, D. A. (1970), RCA Rev. 31, 187. Kern, W., Puotinen D. A. (1970), RCA Rev. 31, 187-206. Kern, W. (l984), Semicond. International, pp. 94-99. Kim, K. M., Smetana, P. (1990), J. Cryst. Growth 100, 527. Kishino, S., Matsushita, Y., Kanamori, M. (1979), Appl. Phys. Lett. 35, 213. Kobayashi, N. (1978), J. Cryst. Growth 52,425. Kobayashi, N., Arizumi, T. ( 1 970), Jpn. J . Appl. Phys. 9,361 and 1255. Kobayashi, N., Wilcox, W. R. (1982), J . Cryst. Growh 59, 6 16. Kubota, H., Numano, M., Amai, T., Miyashita, M., Samata S . , Matsushita Y. (1994), in: Semiconductor Silicon 1994: Huff, H. R., Bergholtz, W., Surnino, K. (Eds.). Electrochem SOC.Pennington, New Jersey, 225-231. Langlois, W. E. (1984), J. Cryst. Growth 70, 73. Langlois, W. E. (1985), Annu. Rev. Fluid Mech. 17, 191. Langlois, W. E., Shir, C. C. (1977), Comput. Methods Appl. Mech. Eng. 12, 145. Lark-Horowitz, K. (195 I ) , Proc. Con& Semiconducring Materials, Reading, U.K. London: Butterworth, p. 47. Lin, W., Moerchel, K. G. (1986), in: Reduced Temp. Proc. f o r VLSI: Reif, R. (Ed.). Pennington, NJ: Electrochem. SOC.,pp. 438-452. Lin, W., Benson, K. E. (1987), Annual Review of Materials Science 17, 213-298. Lin, W. (1996). in: Proc. 2nd lntern Symp on Adv. Science and Technology of Silicon Materials: Urneno, M. (Ed.). Kono. Livingston, F. M., Messoralas, S., Newman, R. C., Pike, R. J., Stewart, R. J., Binns, M. J., Brown, W. P., Wilkes, J. G. (1984), J. Phys. C: Solid State Phys. 17,6253. Lyon, D. W., Olsen, C. M., Lewis, E. D. (1949), J . Electrochem. SOC.96,359. Matsushita, Y. (1982), J. Cryst. Growth 56, 516. Meese, J. M. (Ed.) (1978), 2nd In?. Conf on NTD Silicon, Missouri, U.S.A. New York: Plenum (29 Refs.). Moody, J. W. (1986), Proc. Semiconductor Silicon 1986: Huff, H. R., Kolbesen, B. O., Abe, T. (Eds.). Pennington, NJ: Electrochem. SOC.,PV86-4, 100. Moreland, J. A. (1985), in: VLSI Electronic Microstructure Science, Vol 12: Einspruch, N. G., Huff, H. R. (Eds.). Academic Press, New York, pp. 63-87.

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Murgai, A,, Patrick, W. J., Combronde, J., Felix, J. C. (1982), IRM J . Res. Der'. 26, 546. Newman, R. C. (1973). Infrared Studies of C y s t a l Defects. London: Taylor and Francis. Newman, R. C. (1988),Mater. Res. Soc. Symp. Proc. 104, 25. Newman, R. C., Claybourn. M. (1988), Inst. Phys. Con$ Sex 95, 2 1 I . Newman, R. C., Binns, M. J., Brown, W. P., Livingston, F. M., Messorolas, s., Stewart, R. J., Wilkes, J. G . (1983a), Physica B 116, 264. Newman, R. C.. Tucker. J . H., Livingston, F. M. (1983b), J. Phys. C: Solid State Phys. 16, L 151. Osaka. J., Inoue. N., Wada, K. ( l 9 8 0 ) , Appl. Phys. Lett. 36, 288. Pfann, W. G. ( 1952), J. Met. 4 , 747. Pfann. W. G . (1958). Zone Melting. New York: Wiley. Robbins, H., Schwartz, B. J . (1960), Electrochem. SOC. 107, 108- 1 1 I . Robertson, D. S . i1966), Br. J. Appl. Phys. 17, 1047. Rutter. J . W., Chalmers. B. (1953), Can. J. Phys. 31, 15.

Schlichting, H. (1968), B o u n d a n Layer T h e o n , New York: McGraw-Hill. Chap. 12. SEMI International Standards, Materials Volume. SEMI International. Mountain View, CA. 1994. Series, R. W. (1989). J . C y s t . GroH,th 97, 92-98 Shimizu, H., Sugino, Y., Suzuki, N., Kiyota, S . , Nagasawa, K., Fujita, M., Takeda, K., Isomae, S . (1997). Jpn. J. Appl. Phxs. 36, 2565-2570. Shimura, F., Hockett. R. S . , Reed, D. A,, Wayne, D . H . ( 1985), Appl. Phys. Lett. 4 7 , 794. Showa Denko, K. K. (l984), Patent Japan 5 930 7 1 1, Steinbeck, H. H. (1980a), Electrochem. Soc. Estended Abstracts. PV80-2, 1325. Steinbeck, H. H. (1980b), Proc. 1st Eur. Symp. Materials and Proc.e.vsing. Mountain View, CA, U.S.A. SEMI, p. 57. Stimmel. J., Strathman, M., Wittmer, M. (Eds.) (1986). Materials Issues in Silicon IC Processing. Mater. Res. Soc. Symp. Proc. 71. Sundermeyer (1957). Patent. Suzki, T., Isawa, N., Okubo, Y., Hoshi, K. (1981). in: Semiconductor Silicon 1981, Huff, H. R., Kreigler, R. J.. Takeishi, Y. iEds.). Pennington, NJ: Electrochem. Soc., P V81-5, p. 90. Tamura, M., Sunami, H. (1972). Jpn. J. Appl. Phy.s. 1 1 . 1097. Tan. T. Y., Gardner, E. E.. Tice, W. K. ( 1 9 7 7 Appl. ~ PhJs. Lett. 30, 175. Tanenbaum, M.. Mills, A . D. (1961), J . Electrochem. SO(.. 108. I7 1 . Tanner. B. K . (1977). X-Ray Di'ruction Topography. Oxford: Pergamon, p. 50. Taylor. P. A. ( 1987). Solid State Technol. 30, No. 7 , 53. Taylor, P. A. (1988). J. C y s t . GroH,th 8 9 , 28. Teal. G . K., Buehler, E. (1952). Phys. Ret: 8 7 , 190. Theurer. H. C . ( l 9 S 2 ) , Patent USP 3 060 123.

Theurer, H. C . (1956), Trans. AIME 206, 1316. Thomas, D. J . D. (1963), Phys. Status Solidi 3, 2261. Tokumaru, Y., Ohushi, H., Masui, T., Abe, T. (1982), Jpn. J. Appl. Phys. 21, 443. Townley, D. 0. ( l 9 7 3 ) , Solid State Technol. 16, 43. Umeno, S . , Okui, M., Hourai, M., Sano, M., Tsuya, H. (1997). Jpn. J. Appl. Phys. 36, L 591. Voronkov, V. V., Falster, R., Holzer, J. C. (1997), in: Cnstalline Defects and Contamination: Their Impact and Control in Device Manufucturing 11: Kolbeson, B. O., Stallhofer, P., Claeys, C . , Tardiff, F. (Eds.). Electrochem. SOC.Pennington, New Jersey, p. 3. von Amrnon. W. (1996), in: Proceeding of 2nd Int. Symp. on Adv. Sci. and Tech. of Silicon Materials: M. Umeno (Ed.). Kono, pp. 233-241. Wada, K. ( 1 984), Phys. Rev. B 30,5884. Wada, K., Inoue, N. (1986), in: Semiconductor Silicon 1986: Huff, H. R., Kolbesen, B. O., Abe, T. (Eds.). Pennington, NJ: Electrochem. SOC., PV864 , p. 778. Walsh, R. J., Hertzog, A. H. (1963), Patent USP 3 170 273. Wanatabe, M. (1991). Solid State Technol. 34, 69, 133. Wilkes, J. G. (1959), Proc. IEE 106 B, Supp. 17, 866. Wilkes, J . G. (1983). J. C y s t . Growth 6 5 , 214. Wilkes, J. G. (1988), Trans.-Inst. Min. Metall. 97, C 72. Wilkes, J. G., Perkins, D. W. (1971-72), DCVD Res. Rep. RP6-62. London: Ministry of Defence. Winegarner, R. M. ( l 9 9 8 ) , Silicon Industrj, Sage Concepts, Forestville, CA, 1998. Witt, A. F., Herman, C. J., Gatos, H. C . (1970), J. Mater. Sci. 5 , 822. Yamagishi, H., Minami, H., Imai, M., Misawa T., Takada. K. (1996). Proc. 2nd Intern. Symp on Adv. Tech. uf Silicon Materials: Umeno, M. (Ed.). Kono, p. 59. Yamamoto, K., Kishino, S . , Matsushi, Y., Iizuka, T. ( 1980). Appl. Phys. Lett. 36, 195. Yang, K. H., Kappert, H. F., Schwuttke, G. H. (1978), Phys. Status Solidi A 50, 221. Yatsurugi, Y., Akiyama, T., Endo, Y., Nozaki, T. ( 1973). J. Electrochem. Soc. 120, 985. Yusa, A,, Yatsurguri, Y., Takaishi, T. (1975), J. Electrochern. Soc. 122, 1700. Zeigler, G . (1961). Z. Naturforsch. 16a, 219.

General Reading Brice, J . C . ( I 973). The Growth of Clystals f r o m Liquids. Amsterdam: North-Holland. Einspruch, N. G., Huff, H. (1985), VLSI Electronics, Vol. 12: Silicon Materials. London: Academic. Gupta, D. C. (Ed.) (1983, 1984), Silicon Processing, Technical Publications 804 and 850. Philadelphia, PA: ASTM.

1 . 1 0 References

Hurle, D. T. J. (1993), Crystal Pulling from the Melt. Heidelberg: Springer. Mikkelsen, J. C., Corbett, J. W., Pearton, S. J., Penneycook, S . J. (Eds.) (1986), Oxygen, Carbon, Hydrogen, and Nitrogen in Crystalline Silicon. Mater. Res. SOC.Symp. Proc., Vol. 59. Pittsburgh, PA: Materials Research Society. Ravi, K. V. (1981), Imperfections and Impurities in Semiconductor Silicon. New York: Wiley. Stavola, M., Pearton, S. J., Davies, G. (Eds.) (1988), Defects in Electronic Materials. Mater. Res. SOC. Symp. Proc., Vol. 104. Pittsburgh; PA: Materials Research Society. Sze, S . M. (Ed.) (1983), VLSI Technology. New York: McGraw-Hill. Wolf, S., Tauber, R. N. (1986). Silicon Processingfor the VLSI Era, Vol. 1: Process Technology. Sunset Beach. CA: Lattice Press.

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Crystals: Growth, Properties, and Applications, Vols. 1-10. Vol. 5 : Freyhard, H. C. (Ed.) (1981) for FZ Si. Vol. 7: Grabmaier, J. (Ed.) (1982) for CZ Si. Berlin: Springer. Semiconductor Silicon. This series of symposia organized by the Electrochemical Society reflects the whole development of silicon materials technology and provide a very important reference and reading resource: 1969 New York; 1973 Chicago; 1977 Philadelphia: 1981 Minneapolis; 1986 Boston; 1990 Montreal; 1994 San Francisco; 1998 San Diego. The proceedings are published by the Electrochemical Society, Pennington, NJ.

2 Compound Semiconductor Processing

.

J Brian Mullin

Electronic Materials Consultancy. Malvern. Worcestershire. U.K.

List of Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Historical Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Purification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 2.3.1 General Purification Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 Zone Refining and Related Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 Problems with Specific Compounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3.1 InSb and GaSb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3.2 InAs and GaAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3.3 InP and G a P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3.4 II-VI Compounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Technical Constraints to Melt Growth Techniques . . . . . . . . . . . . . . . . . . . . . . 2.4.1 Chemical Reactivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 Melting Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.3 Vapor Pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 2.5.1 Horizontal Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 Vertical Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.3 Crystal Pulling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4 Liquid Encapsulated Czochralski (LEC) Pulling . . . . . . . . . . . . . . . . . . . . . . . 2.5.4.1 The Low Pressure LEC Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4.2 The High Pressure LEC Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Crystal Growth of Specific Compounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.1 InSb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.2 InAs and GaAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.3 InP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.4 II-VI Compounds: General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.4.1 Bulk Hg, -,Cd, Te . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.4.2 CdTe and Cd,-,Zn, Te . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.4.3 ZnSe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.4.4 ZnS and CdS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Fundamental Aspects of Crystal Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7.2 Temperature Distribution, Crystal Shape and Diameter Control . . . . . . . . . 2.7.3 Solute Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

69 70 70 73 73 74 74 75 76 76 76 77 78 79 79 79 80 82 84 86 86 86 87 88 88 90 92 92 93 94 94 95 96 96 99

68

2.7.4 2.7.5 2.7.6 2.8 2.9


Constitutional Supercooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Facet Effect. Anisotropic Segregation and Twinning .................... Dislocations and Grain Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wafering and Slice Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

100 102 105

106 107



c,, c,, c, solute or dopant concentration (in the solid, in the liquid, at the interface)

d

depth of volume of convecting gas diffusion coefficient temperature gradient Miller indices latent heat of fusion dopant distribution coefficient equilibrium dopant distribution coefficient thermal diffusivity gradient of liquidus gas pressure pressure of gas, pressure of dissociation vapor of components Rayleigh number temperature growth velocity

D G h, k, 1 Hf k k0

KO m P PG, pd Ra

T V

6

0

boundary layer “thickness”, parameter of BPS model angle kinematic viscosity crystal density thermal conductivity interfacial energies angular rotation rate

ACRT BPS CRA HG LEC LPE MBE MCT MOVPE PBN PPba PPm QA RF SI TGZM THM VGF VP

accelerated crucible rotation technique Burton, Prim and Slichter cast recrystallize anneal horizontal growth liquid encapsulated Czochralski (techniques) liquid phase epitaxy molecular beam epitaxy mercury cadmium telluride metal organic vapor phase epitaxy pyrolytic boron nitride atomic parts per billion parts per million quench anneal radio frequency semi-insulating temperature gradient zone melting traveling heater method vertical gradient freeze (technique) vertical pulling

e

VO

Qs 0

hi$S,

4 G

69

70


2.1 Introduction

2.2 Historical Background

This chapter reviews the general principles and practice governing the preparation and processing of compound semiconductors and their alloys, how they are purified, how they are prepared as single crystals and how they are converted into wafers suitable for epitaxial growth. The range of materials which can be classified as compound or alloy semiconductors is vast and covers the whole of the periodic table. It includes IV-IV, 11-IV, I-v, 11-v, 111-v, I-VI, 11-VI, 111-VI, IV-VI. v-VI, I-111-VI, I-IV-VI, I-vVI, 11-IV and 11-111-V compounds. However, because of the enormous cost of developing these materials as high-quality semiconductors most of these compounds are currently in a relatively primitive state of development when compared with Ge or Si. Indeed the only compounds which have been developed to a state of significant commercial application are to be found in the 111-V and 11-VI semiconductor groups of materials. It is with these classes of materials that this chapter will be mainly concerned. The efficient processing of semiconductors in a form suitable for device application requires a sound understanding of the practical technologies involved together with a knowledge of the scientific principles underlying these technologies. Both the technology and the science of the processing will be covered in this chapter. However, it is important to appreciate that the technology as opposed to the science of semiconductor processing is undergoing a constant evolution driven by ever more demanding specifications arising from of an ever increasing range of devices.

Probably the most important event which promoted significant scientific and technological research in the processing of semiconduction materials was the discovery of transistor action in germanium by Brattain and Bardeen (1948) which had been stimulated by the predictions of Shockley (1949). As a result serious international interest developed in the search for new semiconductors. 11-VI compounds had of course been known since before the beginning of the century, but the early work of Welker (1952, 1953) and his colleagues in Germany on 111-V compounds following the discovery of transistor action marked the beginning of the evolution of compound semiconductor processing. Our knowledge of semiconductor processing (Mullin, 1975 a, b, 1989; Thomas et al., 1993), indeed of all aspects of semiconductors and the solid state, is rooted in research on Ge in the 1950s. Even early work in this period highlighted the two overriding requirements for semiconductors, the need for high purity and the need for single crystals. The first requirement resulted in the creation of new methods of purification and the evolution of a most significant concept, the concept of semiconductor purity. This specified the need for unprecedentedly low levels of impurities, typically less than 10 parts per billion atomic (ppba) of electrically active impurities. The second requirement resulted in the development of new technologies for producing completely single crystals free from defects including dislocations. At the forefront of this materials work aimed at fulfilling these demands of purity and crystalline perfection was the development of the science and technology of crys-

2 . 2 Historical Background

tal growth. In less than a decade the intense research and development effort resulted in the melt growth of Ge developing from an art to a science. In the case of the compound semiconductors, the less difficult materials, like InSb, followed the pattern of evolution of Ge, and single crystals containing less than carriers/cm3 (1 ppba is equivalent to atoms/cm3) were state of the art 2.9 x well within a decade. However, in the case of the more difficult materials like GaAs, InP and Gap, their evolution has taken over three decades and is still in a development phase. For the very difficult materials like ZnSe no melt growth technology has yet been devised that can achieve reproducibly and readily acceptable quality single-crystal material, although there are promising developments (Rudolph et al., 1994). For ZnSe, vapor growth techniques are pioneering the way to semiconductor quality (Cantell et al., 1992). The key to the development of Ge was the creation of new melt growth technologies. Very significant contributions to our knowledge resulted from the pioneering work of Pfann (1966) on zone melting and Teal (1958) on the vertical pulling of single crystals. Pfann (1966) initiated the concept of zone melting. This generic term covers a range of related horizontal crystallization technologies. The simplest technology is the single zone freeze in which a horizontal boat containing a molten charge is progressively frozen from one end. Other procedures were developed involving the translation of a liquid zone through a solid ingot. In particular it created two very powerful processing technologies, zone leveling and zone refining (see Sec. 2.3.2). Zone leveling was initially applied to Ge and resulted in a very successful crystallization technology for the production of

71

uniformly doped single-crystal material. This process involves the formation of a liquid zone in a solid ingot and its movement through the ingot in one direction and subsequently, for ideally uniform material, in the reverse direction. The liquid zone acquires a constant dopant concentration l / k times that in the solid, where k, the distribution coefficient, is given by k = Cs/C, and C, and C, are the concentrations of dopant in the solid and liquid respectively. This process levels out the dopant concentration in the solid so that the dopant concentration of the solid being melted is the same as the concentration in the solid being crystallized. The horizontal technologies were not only used for zone leveling and for purification by zone refining but they were also developed for the growth of single crystals. This was achieved by arranging for a molten zone to melt-back into a single crystal seed positioned at one end of a polycrystalline ingot. The solid which crystallized on the seed as the zone was moved through the ingot took up the orientation of the seed and resulted in the formation of a single crystal. In addition to H G for the growth of single crystals, the use of VP of crystals from the melts was pioneered by Teal (1958). The technique has its origins in the Czochralski technique. Czochralski (1917) arranged to dip a thin rod which acted like a seed into a molten melt of metal and withdraw it from the melt. As the liquid was pulled away from the melt it crystallized, giving regions of single crystal metal. However, this technology is far removed from modern crystal pulling technology. The modern pulling technique (Teal, 1958) was developed during the initial phase of semiconductor research at Bell Labs in the 1950s and early 1960s. The most important innovation was the intro-

72


duction of rotation using a pull rod. A single-crystal seed was mounted in a chuck on the pull rod which could be raised and lowered at a set rate. In the pulling process the crystal nucleated on the seed and its diameter was controlled by adjusting the power to the melt. This concept had profound consequences for the semiconductor processing of single crystals. Theoretical work on crystal pulling has also had an important influence on the development of the technology. The work of Burton, Prim and Slichter (BPS) (Burton et al., 1953) on solute distribution during crystal growth proved to be most significant. They modeled solute transport in the melt adjacent to the rotating crystallizing surface using concepts developed by von Karman (1921) and Cochran (1934). BPS established the flow normal to the disc as a function of the crystal growth parameters enabling quantitative estimates to be made of the solute distribution from the interface into the melt. Use of the BPS model has stimulated much research and laid the foundations of a great deal of our understanding of the science of crystal growth from the melt. It has been used, for example, in the modeling of heavy doping during crystal pulling. This has resulted in a predictive theory of constitutional supercooling (Hurle, 1961; see Sec. 2.7.4). This knowledge is directly relevant to the crystallization of compound semiconductors from nonstoichiometric melts, where constitutional supercooling is a very common occurrence and can be a major problem seriously affecting crystal quality. The causes of nonuniform dopant or impurity incorporation are a major consideration in understanding the mechanisms of crystal growth. Of particular significance has been the discovery of the facet effect (Hulme and Mullin, 1959) and anisotropic

segregation (Mullin, 1962) of dopants during crystal growth. Also important are impurity striations, which are a common occurrence. Crystal rotation introduces periodic impurity incorporation due to the growth rate variations imposed by the rotating crystal. The incorporation of dopants will be developed in further detail in Sec. 2.1.5. The science of horizontal growth (HG) has lagged significantly behind that of vertical pulling (VP). In H G there is no effective working theory for convection in the molten zone and transient control of doping as opposed to uniform doping is not possible as it is in VP. The VP technique thus evolved as a favored tool for investigating the science of crystal growth from the melt. From an historical viewpoint it is instructive to follow the evolution and role of H G and VP techniques in relation to the science and technology of Ge and Si. The horizontal growth of Ge, a technology that pioneered purification by zone refining and the production of doped single crystals by zone melting, gradually emerged as the more cost effective crystal growth process and replaced the VP technique. Ultimately however, the semiconductor applications of Ge were taken over by Si, eliminating the need for Ge altogether with the exception of a few specialist applications such as the growth of very large crystals for detectors. These are fulfilled by pulling. It is interesting that the VP technique that was developed for Ge created the conditions for the single-crystal growth of Si. Silicon with its superior device properties has emerged as the dominant semiconductor and as such has had and continues to have a profound influence on every aspect of semiconductor processing. The VP technique has been refined and developed for Si and is still the dominant industrial tech-

2.3 Purification

nology for Si. But, also of major importance for Si is the float zone technique, in which a liquid zone out of contact with the container is moved through a vertical rod of Si. This zone refining action produces the very highest grade of single-crystal Si, a very important industrial requirement. Nevertheless, it is important to recognize that some of the unique properties of the compound semiconductors have also stimulated developments in semiconductor processing. Undoubtedly the very rapid expansion in our knowledge of semiconductor processing can be attributed to the relative ease of handling Ge and in particular to the ability to hold and crystallize molten Ge with negligible contamination from silica apparatus. The technology of Si is in many ways very different to that of Ge. It reacts with SiO, and cannot be crystallized in a silica boat. It also forms a tenacious oxide which requires special techniques to prevent its formation. Hence the importance of the pulling technique and the noncontacting float zone technique in its development. Technology never stands still. Zone refining has been developed (Hukin, 1989) for Si using a horizontal water-cooled Cu boat. A liquid zone is formed and levitated out of contact with the boat using RF fields. Two-meter, 125 cm2 section solar cell grade Si can be produced in this way. The 111-V and 11-VI compounds present different problems again to those of Si. The antimonides are similar in their attributes to Ge but the arsenides and the phosphides, selenides and tellurides suffer dissociative decomposition near their melting points, resulting in the loss of one of their component elements. As a result, closed-tube techniques needed to be developed in order to prevent vapor loss. This has stimulated new technologies such as

73

liquid encapsulation and more recently the vertical gradient freeze (VGF) technique to overcome this problem. The relatively slow development, over three decades, of these compounds is in no small way due to the difficulties associated with dealing with compounds which have a significant vapor pressure at the melting point. In addition the number of point defects at the melting point is high -10” cm-3. This leads to extended defects and doping nonuniformities and a range of problems not found in Si and Ge. The continuing challenge of processing technology is to understand and control these problems.

2.3 Purification The cost of developing the knowledge and technology to be able to process raw materials into device quality semiconducting compounds is enormous and inevitably involves a very significant research and development effort involving both purification and crystal growth. As a consequence, there are only a few highly developed compound semiconductors. These include InSb, GaAs, InP, GaP and CdTe and its related alloys with HgTe. Most of the IIVI compounds are still not readily available in wafer form as high-quality singlecrystalline material. The basic aspects of the purification technologies required to produce high-purity semiconducting compounds will now be considered. 2.3.1 General Purification Procedures

It is convenient to identify two stages in the purification of semiconductor compounds, firstly the purification of the elements themselves and secondly the purification of the compounds. From an historical perspective the role of the more con-

74


ventional chemical purification procedures has been more useful than zone refining in purifying the elements. This can be appreciated from the early reviews in Willardson and Goering's book on 111-V compounds (1962). It is evident that work on zone refining of group I11 metals as well as phosphorus and arsenic was clearly not seen to be markedly effective. This coupled with the fact that zone refining represented an additional costly batch process meant that its use has always been problematical, especially for elements like In and Ga which are low melting point readily alloyable metals with a tendency, in the case of Ga, to supercool. Whilst zone refining has not been particularly useful for the common elements of groups I11 and V, in the case of groups I1 and VI zone refining has proved to be a very effective process for the production of ultra-pure Cd and Te. This development was made possible by military funding since these elements arse used in the preparation of HgCdTe for infrared detectors. Here very high purity elements, having less than 1 part in lo9 electrically active impurities are essential. It is evident that zone refining is most effective for strongly bonded materials which crystallize well and in which impurities have a low solubility. These criteria apply particularly to the compounds themselves. Thus many compounds can be zone refined but most compounds have their own peculiarities, demanding specialized processes. These will be considered for the more important compounds later.

purification procedure for Ge. The impurities that are less soluble in the solid, or more soluble in the liquid ( k , < l ) , are moved in the direction of crystallization towards the finish (last to freeze) end of the ingot whereas the impurities that are more soluble in the solid ( k , > l), that is, less soluble in the liquid, are moved to the start end of the ingot. Provided the distribution coefficients k , are not close to 1 - a condition satisfied by Ge - this very simple process can after very few zone passes produce semiconductor purity in an ingot. A remarkable result. One can appreciate the effectiveness of zone refining from the graphs in Fig. 2-1, where the theoretical ultimate distributions for impurities having different distribution coefficients are given. Orders of magnitude improvement in purification are indicated. However, these dramatic results must only be taken as a guide since solid-state diffusion and vapor transport can reduce the effectiveness of impurity removal.

2.3.2 Zone Refining and Related Techniques

' The equilibrium distribution coefficient k , of a solute (dopant, impurity or excess component) is the ratio of the concentration of the solute in the solid, C, to the concentration of the solute in the liquid, C,,if the phases are kept in contact for a sufficiently long period for them to come to equilibrium.

Zone refining, which involves the motion of a liquid zone or zones through an ingot, is the most important and effective

2.3.3 Problems with Specific Compounds Processing by conventional zone refining or chemical purification methods is often insufficient on its own as a means of achieving semiconductor purity in compounds. Inevitably there is some problem or problems, some difficult-to-remove residual impurity or some quirk of contamination that needs to be dealt with in an unconventional manner if the ultimate goal of semiconductor purity is to be achieved.

2 . 3 Purification

log

:

Initial concentration

I -24

t/

-30I

Length solidified

I

Figure 2-1. Theoretical ultimate distributions for dopants having different distribution coefficients ( k ) after multiple zone refining passes in an ingot where the zone length is 10% of the ingot length. It is assumed that there is no back reflection of dopant from the freezing of the last zone length. The results highlight the potential of zone refining (see Pfann, 1966).

In this section problems or aspects of purification will be considered which have proved to be important in the achievement of semiconductor purity of the more important compound semiconductors. It should be stressed that achieving semiconductor purity in compounds is a very demanding and generally costly process and one that is frequently underestimated. The processes of purification and the avoidance of contamination represent a continuous battle if the ultimate in semiconductor performance is to be achieved. In the case of many of the 11-VI compounds for example the presence of impurities could still be the principal problem preventing their effective development.

2.3.3.1 InSb and GaSb Indium antimonide (Hulme and Mullin, 1962) has attracted much more research and development (R&D) over the years than GaSb. Major factors in this interest are of course the device applications of the material. InSb, for example, is an impor-

75

tant infrared detector material suitable for detectors working in the 3-5 pm region of the spectrum. The low melting point of InSb, 525"C, combined with the negligible vapor pressure of Sb over its melt make InSb an ideal candidate for conventional zone refining procedures. However, the straightforward process is of limited value because of troublesome impurities, particularly Zn and Te. Not only do they exhibit anisotropic segregation (Mullin, 1962), but in the case of Te the value of its effective distribution coefficient, keff (see Sec. 2.7.5) can range from -0.5 for growth in an non[lll]direction to -4.0 for growth on a (1 11) facet. Thus Te would be distributed in polycrystalline material as though the effective k were some weighted mean of these values, that is, close to one. Zinc has a value of keffranging from 2.3 to 3.0. But more troublesome is its volatility at the melting point of InSb. Vapor transport of Zn above the ingot can reduce the efficiency of zone refining. This problem has been overcome by using the volatility of Zn to advantage in a two-stage evaporation and zone-refining procedure (Hulme, 1959). Zone-refined Sb in excess of that required to form stoichiometric InSb is added to high-purity In in a boat in a modified zone-refining apparatus and melted under vacuum. Both Zn and Sb evaporate from the molten charge and condense on the cooled upper surface of the outer containing tube. The excess Sb traps in the very small quantity of the more volatile Zn. After a timed period when the excess Sb has evaporated the ingot is cooled and frozen. It is then zone refined under an atmosphere of H,, a condition where the Sb has negligible volatility. The purification process is highly reproducible, resulting in the production of very high

- -

76


purity InSb with some 60% of the ingot having a carrier concentration less than i 1014 cm-3. GaSb has not been developed in this way but it can be zone refined. The incentive to purify the material further, however, is limited by the belief that the residual p-type carriers per carrier level, - 2 x cm3, is determined by fundamental aspects of the band structure of the compound.

2.3.3.2 InAs and GaAs InAs and GaAs present additional handling problems because at their melting points the As dissociation pressures are respectively -0.3 and 1.0 atm. Nevertheless, considerable R&D effort has been carried out on GaAs using conventional hot wall technologies. However, a major problem encountered on zone refining GaAs has been the failure to achieve purities with carrier levels below 1OI6 to 10’’ n-type carriers per cm3. This has been shown by Hicks and Greene (1971) to be due to the reaction between Ga in the liquid Ga, As melts and the silica containing vessel, which introduces a fairly constant level of Si into the ingots at about one part per million: (2- 1) 4Ga(L)+Si02(S)=2Ga20(V)+Si(soln)

-

The problem can be overcome by using BN or graphite boats. However, the zonerefining process has generally been superseded and simplified by in situ compounding of very high purity Ga and As which are now available as a result of improvements in chemical purification methods (see Sec. 2.6.2).

2.3.3.3 InP and GaP The very high vapor pressures generated by these compounds at their melting points, some 27 atm and 32 atm for InP

and GaP respectively, makes zone refining a difficult and potentially hazardous process. The compounds can nevertheless be prepared in horizontal systems by distilling the P, into the molten group I11 element contained in a silica or BN boat. By limiting the amount of group V distilled so that the group I11 element is in excess of stoichiometry the working vapor pressures are reduced. Crystallization under these conditions has an additional advantage; there is a very much greater purification effect for impurities from group I11 rich liquids than from stoichiometric melts. The disadvantage of course is that crystallization occurs under conditions of constitutional supercooling, which can result in trapping of the impurity-rich group I11 element in the solid. With the availability of purer starting elements, formation of the compounds from stoichiometric melts is now more usual. Nevertheless, further purification is generally required, and is now often achieved by pre-pulling charges using the liquid encapsulation technique. InP having 1015carriers/cm3 can be produced in this way. A similar purification procedure for GaP can be used. The current commercial demands on GaP are somewhat less than on InP since it is either used as doped material or as a substrate on which active layers are grown. There is clearly scope for the development of further purification procedures for both these compounds.

2.3.3.4 11-VI Compounds The state of development of the 11-VI compounds is significantly behind that of the 111-V compounds even though they have a much longer history. Many of the 11-VI compounds, especially the higher energy gap oxides, sulfides and selenides, are not accessible by melt growth tech-

2.4 Technical Constraints to Melt Growth Techniques

niques and as a consequence there is a much greater emphasis in the use of vapor growth techniques to grow these difficult compounds. Our knowledge of the use of vapor growth as a purification technology is primitive. There is no equivalent to zone refining. Hence there is a more general tendency to rely on the use of elements that have been purified chemically or by zone refining. The elements Hg, Cd and Te, components of the exceptionally well developed infrared detector material Hg, -$d,Te, are now available as very high purity elements as a result of multiple zone refining technologies (Cd and Te) and distillation techniques (Hg). Hence compounds of these elements are prepared in situ by direct reaction. Most of the other elements Zn, Se and S although currently available in conventional high purity form are generally not as pure as the detector materials and do not form very pure semiconducting compounds. Zone refining of the 11-VI compounds is not efficacious because of the volatility of both the group I1 and group VI elements as well as the compounds themselves. Hence there has been little development of conventional zone-refining technology for the compounds. However, a related zone-refining technology called the traveling heater method (THM) or sometimes the traveling solvent method has attracted much interest and development for the 11-VI compounds. In the traveling heater method a molten zone is moved through the ingot as in zone refining, but in THM the zone comprises a solvent of Te or Se. Thus the compound dissolves at the leading edge of the zone and crystallizes out at the trailing edge. This has two advantages. Firstly, it reduces the temperature of crystallization significantly below the melting point of the

77

compound, thus markedly reducing the vapor pressure of the components of the compound, effectively eliminating evaporation. Secondly, it provides a group VI rich solution in which impurities are exceptionally soluble, a condition which results in the crystallization of a very pure compound. Because of the reduced growth temperature it is also possible to eliminate sub-grain boundaries. The technique, however, has not yet been developed to grow large completely single crystals. The process has been exploited particularly by Triboulet (1994) and the CRNS Bellevue group for the preparation and purification of Hg, - $d,Te, Hg, - .Zn,Te, CdTe, HgTe and ZnTe, as well as CdMnTe. It clearly has scope for the preparation and purification of ZnSe and various alloys of the compounds. The potential disadvantage of the technique is that the crystallization occurs under conditions of constitutional supercooling and solvent trapping can occur and give rise to group VI rich precipitates toBether with impurities. Nevertheless it would appear that by optimizing the temperature gradients and the gradient of constitutional supercooling (see Sec. 2.7.4) the worst effects of solvent trapping can be avoided.

2.4 Technical Constraints to Melt Growth Techniques The processing of compound semiconductors by melt growth techniques both for purification and crystal growth is generally much more difficult than the processing of Ge because of constraints imposed by the properties of the materials. Some of the significant properties which lead to constraints in the use of melt growth and related processing are listed in

78


Table 2-1. Material properties of main semiconductors. Compound

Melting point ("C)

Vapor pressure at M.Pt.(atm)

InSb GaSb InAs GaAs InP GaP HgSe H gTe CdSe CdTe

525 712 94 3 1238 1062 1465 799 670 1239 1092

4 x lo-' 1 x 10-6

ZnSe ZnTe Ge Si

1526 1300 960 1420

0.5 0.6

0.33 1.o 27.5 32 12.5 0.3 0.65

CRSS at M.Pt (MPa)

0.7 0.36

0.2

0.70 1.85

Table 2-1. Consideration of a wider range of properties, chemical reactivity, melting point, vapor pressure, critical resolved shear stress and ionicity are important in understanding the suitability, or more often, the unsuitability of a particular technology.

2.4.1 Chemical Reactivity Although not specifically listed in Table 2-1, chemical reactivity is an important constraint in all processing. The main problems arise from the reactivity of the molten semiconductor with the container or the gaseous environment. In this respect container materials have proved to be the dominant source of contamination for compound semiconductor melts. Vitreous silica is widely used as a crucible or boat material and is essentially stable against attack from the lower melting point materials like Ge (937"C), InSb (525°C) and GaSb (712°C). But, for higher melting point materials there is gen-

References

Muller and Jacob (1984) Muller and Jacob (1984) Van der Boomgaard and Schol(l957) Arthur (1967); Thomas et al. (1990) Bachmann and Biihler (1974); Thomas et al. (1990) Nygren et al. (1971) Mayer (1984) Harman (1967); Strauss (1971) Bassam et al. (1994); Lorenz (1967) Isshiki (1992); Strauss (1971); Balasubramanian and Wilcox (1992) Isshiki (1992); Lorenz (1967) Isshiki (1992); Lorenz (1967) Thomas et al. (1990) Thomas et al. (1990)

erally contamination with silicon due to the reduction of the SiO, by the melt, in the case of GaAs (1238°C) it is typically above the part per million (ppm) level in the crystallized material. Pyrolytic boron nitride PBN can be used to overcome this problem and is well suited to the growth of 111-V compounds since it is a 111-V also and does not appear to give rise to electrically contaminating impurities. It is however expensive. Graphite is also used since it is stable in an inert atmosphere and does not appear to directly cause electrically active doping by contaminating melts. Graphite will react with silica at high temperature, but at lower temperatures ( < 900 "C) it is a very useful material and is used as a slider boat material in liquid phase epitaxy (LPE) and as a boat material for 11-VI compounds. But, carbon can be electrically active as an acceptor in GaAs for example. It can be introduced on an As vacancy site via CO under Ga-rich growth conditions, hence the importance of removing 0, and H,O.

2 . 5 Crystal Growth

Another potential source of impurity contamination are the impurities such as S etc. in the graphite. These can generally be removed by vacuum heat treatment at very high temperatures ( > 1500"C). Graphite is a very useful material but since it varies in quality must be used with care. The gaseous environment is also a major cause for concern. Processing in vacuum is possible, but the volatility of the group V, I1 or VI components needs to be taken into account. This is discussed later. All the melts and compounds oxidize readily and it is vital to remove all sources of oxygen such as 0, and H,O from the source materials and the environmental gases. Pure H, or forming gas are very effective reducing agents and will remove oxides readily at temperature. Hydrogen does however react to form unpleasant poisionous 'hydrides and extreme precautions need to be taken to avoid leaks not only with pure H, but also with forming gas (N,/H, mixture). Pure inert gases such as N, ,A or He are safer and consequentally are more frequentally used.

2.4.2 Melting Point The melting point affects the choice of crucible material, and with it the extent of chemical reaction. Also, above about 1000°C radiation fields tend to dominate thermal distribution, creating design problems and the need for radiation baffles. Also, above 1100-1200°C silica starts to soften, which generally means it needs to be supported by another material such as graphite.

2.4.3 Vapor Pressure Vapor pressure is probably the most crucial parameter affecting melt growth technologies. The long delay in the development of GaAs, InP and GaP is attributable

79

in part to the problems posed by the vapor pressure of the group V component generated on melting these compounds. Thus a melt of these materials will rapidly lose its group V component unless there is a pressure of the group V component above the melt at least equal to the equilibrium vapor pressure over the melt. Two types of technology have emerged to deal with this problem: hot wall technology and liquid encapsulation (see Sec. 2.5).

2.5 Crystal Growth The main techniques for growing crystals of compound semiconductors can conveniently be grouped into four categories: horizontal growth, vertical growth, crystal pulling and liquid encapsulated Czochralski (LEC) pulling. Although this classification differentiates the techniques by the physical disposition of the different growth processes it is very important to appreciate that each technology gives rise to different crystallization conditions which affect the quality and efficiency of production for different 111-V compounds. Factors such as the ease of seeding for crystal growth, crystal shape, twinning, the effect of growth in a constrained volume, temperature gradients, visibility and the economics of production and ease of automation are critical factors in the choice of a particular technology. The suitability of these techniques for particular compounds, which are listed in Table 2-2, have evolved with time and experience. They have all been refined for particular applications and are still undergoing both research and commercial development. Their application to the growth of particular compounds will be discussed in later sections.

80


Table 2-2. General applicability of growth techniques. a Technique: Compound ~

Zone melting horizontal Bridgman

VGF vertical Bridgman

Conventional vertical pulling

Liquid encapsulation pulling

Vapor growth

~~

InSb GaSb InAs GaAs InP GaP HgSe H gTe CdSe CdTe ZnSe ZnTe HgS ZnS CdS

*** *** *** *** * *

* ***

P P P

c*** : L*** c * : L** c * : L**

** *** ** *** ** **

*** *** *** ***

*** ***

P P

P P P P

P P

***

*** *** *** *** *** ***

The more stars, currently the more appropriate the technique. P: potentially applicable; C: conventional VGF; L: LEC VGF.

a

2.5.1 Horizontal Growth

Horizontal growth (HG) is used here to cover all the horizontal crystallization techniques. They represent a subset of the zone-melting technologies described by Pfann (1966). A typical horizontal growth arrangement is shown schematically in Fig. 2-2 and discussed more fully in relationship to the growth of GaAs in Sec. 2.6.2. The growth of a single crystal can be carried out by controlled freezing of an ingot of molten semiconductor in a boat. The singularity of the ingot is achieved either by relying on self-seeding or through the use of a single-crystal seed which initially contacts the melt. The technique is often referred to as the horizontal Bridgman technique when the ingot is withdrawn from a furnace. The furnace can of course be moved relative to the ingot and this can be beneficial in that there may be less mechanical disturbance to the ingot and the crystallization process.

In the case of compound semiconductors the main problems generally concern the need to accurately control the thermal profiles, hence the movement of large furnaces tends to be undesirable and a combination of power control and the movement of small independent heaters is generally preferred in order to carry out the crystallization process. These benefits can also be achieved by using furnaces with independently controllable windings so arranged that the thermal profile can be moved. The attraction of H G stems from its relative simplicity and ease of automation. The method can be applied readily to compounds that can be processed in vitreous silica, that is, for compounds melting at temperatures less than about 1250 "C having vapor pressures at the melting point not significantly in excess of one atmosphere. An advantage of the HG is that it can be used to prepare the compound from the elements as an ingot which can then be subsequently zone refined in the same ap-

2.5 Crystal Growth

81

Y

Figure 2-2. Schematic of a conventional horizontal growth apparatus used for the preparation and zoning of 111-V compounds. The ingot in the boat B is contained in a sealed tube A. C is the boat used to hold the volatile component prior to its distillation into the group I11 element in A in order to form the compound. D is an anticonvection bame and E the tube support for the thermocouples H and their support tube. F is a multiple section furnace. G is the traveling heater for the zone formation and movement.

paratus. Such an ingot can also be grown as a single crystal and even zone refined as a single crystal without taking it from the same apparatus. In situ compounding of the elements can also be used in vertical pressure pulling systems (Sec. 2.6.2), but the ability to zone refine in a horizontal system is a distinct advantage when superpure elements are not available. An important advantage of the H G technique is that its design readily lends itself to the establishment of low temperature gradients at the solid-liquid interface without creating a control problem. This contrasts with the situation in the pulling process where relatively high temperature gradients are needed to maintain control of the shape of the crystal. Low temperature gradients are extremely important in minimizing stress induced slip on crystallization and hence in minimizing dislocation formation. In the case of the H G growth of GaAs it is possible to grow low dislocation density material, typically

-

around IO2 dislocations/cm2, a factor of 100 less than currently found in routinely grown LEC vertically pulled crystals. This is very important for laser diodes based on GaAs, where even a single dislocation can readily bring about device failure. There are, however, disadvantages to the horizontal techniques. These can be of a scientific fundamental nature, such as constitutional supercooling or stress, or they can be preparation-related and involve, for example, growth orientation, contamination, or shape. One of the fundamental problems which is not widely recognised is constitutional supercooling, which can occur as a result of a nonstoichiometric melt due to inaccurate vapor pressure control. This can be especially troublesome with low temperature gradients as is analyzed later in Sec. 2.7.4. The most troublesome problems occur as a result of the contact of the melt and the grown crystal with the boat. The long

82


period of contact can be a source of impurities by reaction with the boat. Silicon as noted previously is a major problem with GaAs, but also the diffusion of impurities through the silica with the higher melting point compounds can also result in crystal contamination. Misnucleation from the walls of the container can give rise to twinning, grain boundaries and more often polycrystallinity. Also crystallization in a confined shape with materials like III-V compounds which expand on freezing, especially if combined with localized sticking, will inevitably lead to stress, slip and dislocation formation. However, provided nonwetting surfaces are used for the containing boats and a nonconfining boat shape is used, this problem can be minimized. Most of the disadvantages are qualitative rather than absolute. They detract from the versatility and universality of the technique. In certain cases they may not be significant, such as in the case of the growth of low resistivity GaAs, for example, for especially for material which is subsequently sliced and diced for the fabrication of small discrete devices such as laser diodes. However, for integrated circuit applications where large area uniformity is crucially important H G is unattractive. Indeed the D-shape of H G ingots alone appears to have ruled them out for integrated circuit applications. Also the growth of very large cross section ingots as single crystals is fraught with difficulty. 2.5.2 Vertical Growth

Crystallization of ingots in a vertical container by the Stockbarger or vertical Bridgman techniques used to be associated with the growth of high-quality singlecrystal optical materials like CaF,. But, in the last few years the technology has been

refined and developed as a vertical gradient freeze technique for the growth of GaAs, InP and GaP (Gault et al., 1986; Clemens et al., 1986; Bourret, 1990). The relatively recent application of the VGF technique to the growth of GaAs occurred in response to the need to find a cost effective solution to the production of uniform GaAs wafers compatible with integrated circuit technology. Here there is a requirement for circular wafers having precise dimensions and very good electrical uniformity. “Conventional” wisdom would consider that crystallization in a vertical rigid container would give rise to unacceptable stress due to the expansion of the liquid GaAs on freezing. In the event this has not apparently been a problem. The growth process is fairly straightforward and is illustrated in Figs. 2-3 a and b. In the study by Gault et al. (1986), which was a development of earlier studies (see review by Bourret, 1990), the VGF growth of large diamater Gap, InP and GaAs was reported. No B 2 0 3 encapsulant was used. The type of apparatus is illustrated in Fig. 2-3 a. However, it appears that for the reproducible growth of GaAs it is necessary to use a B 2 0 3 encapsulant in a BN crucible (Bourret, 1990) such as that illustrated in Fig. 2-3b. The B,O,, which is now more generally used for InP, is not only a more effective encapsulant, making for a safer and simpler system, but the nonwetting characteristics of the GaAs melt with respect to the container wall reduce the twinning probability. The vertical gradient freeze technique involves the controlled freezing from the bottom up of a molten charge of material held in a tube-shaped vertical container. The freezing is best brought about not by the movement of the furnace relative to the tube, but by the use of a furnace comprising separate independently controlled

2.5 Crystal Growth

.-A

-B

--A

-B

-C

-C

-D

-D - LE

-E

-F

83

-E

-F

-G

-H

-G

-H -L

-I -M

-J

-K

-L

-M

Figure 2-3. Schematic diagrams of crucibles used in the vertical gradient freeze technique, (a) “Conventional” VGF showing compound F, melt E and separate holder J containing group V component K at a controlled temperature in order to maintain sufficient pressure of V to avoid the dissociation of the compound. Plug B allows pressure equilibration between the crucible and the outer chamber. Loss of group V into the outer chamber is inevitable even when PG> pd and is one of the drawbacks of the technique. A, furnace; C, BN crucible; D, main containing vessel; G, seed: H, crucible support; I, gap for group V transport; J, crucible for holding V; K, source of group V; L, base support; M, holder. (b) Liquid encapsulation VGF with PG> pd; symbols have same meaning as above. B,O, encapsulant LE covers the melt and prevents the loss of the volatile component.

84


heating elements. Adjustment of the heating elements controls the position of the thermal profiles so that the movement of the liquid-solid interface can be raised smoothly to bring about the crystallization of an ingot. The technique provides two important growth conditions. I t naturally lends itself to low temperature gradients, which in turn favor low dislocation densities. And, secondly, it provides an ingot of ideal shape of the required diameter. Provided the interface shape is flat or at least the growth surface is slightly convex the expansion problem on freezing does not appear to be serious and any stress can be annealed out. The main problems appear to be those involving design difficulties of the thermal furnaces, the choice of boat material, BN is generally used, and the choice of conditions which allow seeding and the growth of [loo] crystals without twinning. The ingots are usually encapsulated with B,O,. Whether the technique will supersede the LEC technique for the growth of GaAs is an open question. This can only be effectiveiy assessed when commercially sensitive information on single-crystal growth yield comes available. 2.5.3 Crystal Pulling

The Teal and Little crystal pulling technique which was developed successfully for Ge was naturally tried for the 111-V compounds, but the problem of the volatility of the group V elements and their rapid loss from melts in the case of the arsenides and phosphides presented insuperable problems. The antimonides which have low dissociation pressures at their melting points can, however, be grown by any of the Ge-type semiconductor technologies. The crystal growth of the aluminum com-

pounds by either the horizontal or the vertical pulling techniques has never been developed because of the extreme reactivity of the A1 with traces of oxygen or water and with the silica boats. Any bulk material simply oxidizes in the atmosphere. The VP technique is illustrated in Fig. 2-4. The main factors affecting the design concern the type of heating, the crucible and the outer jacket. Heating can be by resistance heating or, for more versatility, induction-coupled RF power to a conducting crucible, generally graphite or a graphite support to a silica or PBN crucible. The outer jacket is usually silica and for strength reasons can only be used with internal gas pressures not in excess of about 2 atm. The growth of a single crystal involves lowering a seed mounted in a seed holder or chuck on the pull rod into a melt of the compound just above the melting point. After melting back a small amount of the seed, the seed-on process, the power to the melt is controlled so as to allow crystallization of the melt on the seed as it is gradually rotated and withdrawn from the melt. The shape of the crystal is controlled by the shape of the meniscus under the seed (Sec. 2.7.2). The whole process requires considerable operator skill and judgment. The growth can be automated by using a sensor to monitor the crystal diameter and provide feed back to the power control (Sec. 2.7.2).Constant diameter crystals are needed for producing standard sized wafers for device fabrication. This basic process can only be applied to the growth of compounds that have virtually no vapor pressure at the melting point. This is a very restrictive condition for the growth of compounds which generally dissociate near the melting point to some extent. In the case of the 111-V compounds and the 11-VI compounds the technology

2.5 Crystal Growth

is only really suitable for the growth of InSb and GaSb. As a consequence, considerable effort has been devoted to developing alternative technologies for the growth of compounds. Two types of technology aim to overcome the vapor pressure problem and loss of group V component. These are hot wall technology and liquid encapsulation technology. In hot wall technology the walls of the containing vessel surrounding the 111-V compounds are kept sufficiently hot to prevent condensation of arsenic or phosphorus on the walls. This requires temperatures of 600 "C or 700 "C, respectively, for the two elements. This condition is possible to apply in the case of horizontal crystal growth involving the use of a sealed silica tube but it creates serious technical problems in the case of a thermally complex vertical pulling apparatus since it requires the seals, pull rod and bearings, etc., to be heated and inert to the hot reactive component elements. Nevertheless, the problems of hot wall technology have been tackled by a variety of pulling methods with varying degrees of success. They are the syringe pulling and magnetic pulling methods, which have been reviewed by Gremmelmaier (1962) and Fischer (1970), and the pressure balancing technique, which has been proposed by Mullin and coworkers (1972). The principal problem is that of devising a pulling mechanism which prevents the volatile group V elements from being lost or from condensing of the on the walls of the system. Syringe pullers use a pull rod, generally ceramic, which is a close tolerance fit in a long bearing. Although such a seal is not perfect the loss of volatile elements can be minimized. The magnetic puller is a tour de force in which the whole ceramic pulling system contained in the pulling chamber is

-

Figure 2-4. Vertical pulling apparatus for low pressure liquid encapsulation. The silica outer vessel N with viewing port J is held between end plates 0 and P. The induction heating coils couple into the graphite surround F mounted on Q.The seed A is fixed in the chuck on the pull rod K which rotates and moves through the bearing and seal L. The crystal C grows from the seed through a necking process at B and on withdrawal pulls out a layer of B,O, over its surface. Loss of the volatile group V component from the seed, crystal and melt is prevented if PG > pd.

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2 ComDound Semiconductor Processing

kept above the condensation temperature of the volatile component. Translation and rotation are achieved by magnetic coupling to suitably sited and protected magnetic material on the pull rod. Neither syringe pullers nor magnetic pullers have achieved any significant following. They are expensive, technically difficult and not entirely satisfactory technologies. An alternative technology proposed and demonstrated by the author has been referred to as the pressure balancing technology (Mullin et al., 1972). This method overcomes loss of the volatile component up the pull rod by arranging for a liquid seal at the top of the bearing housing through which the pull rod is pulled. The inside of the BN bearing has a screw thread so that rotation of the BN pull rod causes the B 2 0 3 liquid sealant to be "wound up" the shaft and kept in the upper reservoir. The inert gas pressure in the system is kept above the dissociation pressure and through the use of a u-tube gauge internal and external pressures can be kept the same. Of course the whole of the apparatus has to be kept above the condensation temperature of the volatile components. The pressure balancing technology works surprisingly well but was not developed and exploited because of the success of liquid encapsulation technology, which has transformed the whole of 111-V pulling technology for the arsenides and phosphides.

2.5.4 Liquid Encapsulated Czochralski (LEC) Pulling Liquid encapsulation often referred to as the liquid encapsulation Czochralski (LEC) technique is illustrated in Fig. 2-4. The liquid encapsulation technique (Mullin et al.. 1965, 1968; Mullin, 1989) avoids the need for hot walls and permits the use of

conventional pull rods. It is elegantly simple. It involves the use of an inert layer of transparent liquid, usually B,O, , which floats on the surface of the melt, acts as a liquid seal and prevents the loss of the dissociating volatile component provided the pressure of external gas P, is greater than that of the dissociation vapor pressure P, of the volatile component. The encapsulant should possess additional properties. It should be immiscible with the melt and be unreactive towards it. But, most importantly, the encapsulant should wet the crystal and the crucible. Further, its viscosity and the temperature dependence of its viscosity should be such as to allow it to be drawn up with an encase the emerging crystal as a thin film of encapsulant. The latter property is desirable in order to prevent the decomposition of the hot crystal throughout the course of the crystal growing process after it has pulled clear from the layer of the encapsulant. Although many glass-like encapsulants have been tried only B 2 0 3and related mixtures fulfill sufficiently well these characteristics.

2.5.4.1 The Low Pressure LEC Technique For compounds that have dissociation pressures not in excess of about two atmospheres it is possible to apply the liquid encapsulation techniques using Ge-type crystal pulling chambers. For this low pressure liquid encapsulation technology it is possible to use an outer jacket of the growth chamber made of silica such as that illustrated in Fig. 2-4. Such a system would be suitable for the growth of InAs or GaAs (Sec. 2.6.2).

2.5.4.2 The High Pressure LEC Technique Silica growth chambers are not strong enough for compounds having high dissociation pressures ( > 2 atm) and steel or

2.6 Crystal Growth of Specific Compounds

metal pressure vessels are used. Pressure vessels have been designed for working upto 200 atm. The use of such steel pressure vessels has enabled the development of a unique technology which has been applied to the crystal pulling of InP and Gap, compounds which have dissociation pressures at their melting points of -27.5 atm and -32 atm respectively. The technology effectively simplifies the growth of these compounds so that the growth process is very similar to that of Ge except that an encapsulant is used and the pulling is carried out under a high pressure of inert gas in a steel pressure vessel. The process can be viewed directly via an optical window using a video camera. An example of a research system is shown in Fig. 2-5. The technical success of the LEC high pressure technology lies in the confinement of the chemically reactive elements such as arsenic and phosphorus to the region of the melt under the liquid encapsulant and out of contact with the chamber wall, the pull rod assembly, bearings seals, etc. Indeed the pressure chamber walls and the pull rod seals need only be capable of withstanding the inert gas pressure at relatively low temperatures, thus avoiding difficult design problems. Of course, the inert gas pressure must such that P, is greater than P, in order to avoid vapor loss. The overall effect of this technology has been to revolutionize the growth of these compounds, enabling them to be grown commercially.

2.6 Crystal Growth of Specific Compounds In discussing the crystal growth of specific compounds emphasis will be given to what is considered to be the most effective technique for general application. The main considerations under discussion will

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Figure 2-5. 200 atm high pressure LEC crystal puller developed at RSRE showing water cooled steel pressure vessel and two optical ports for viewing, one fitted with a video camera. Below the steel pressure vessel is a large chamber containing the weighing cell for diameter control.

relate to the problem areas of diameter control, dislocations, grain boundaries, twinning and purity. A factor which can be important in the growth of compound semiconductors is the anisotropy introduced by the presence of two dissimilar atoms in the zinc blende lattice (Sec. 2.7.1). Thus the [ l l l ] direction where the surface terminates with group V atoms [some authors confusingly use the reverse designation: see discussion in Hulme and Mullin (1962)l differs in properties and behavior from the [TTT] which terminates in group I11 atoms. The designation [111]A or [111]B, where A and B represent the group I11 and group V atoms respectively, avoids ambiguity. The anistropy al-

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so holds of course for all ( h k f ) versus directions. This anistropy is important for all compounds but is particularly important in the case of the growth of the In compounds and is directly relevant to the problem of twinning.

(hm)

2.6.1 InSb Both the H G and the VP techniques are used for the preparation of single crystals of InSb. The former method is attractive for obtaining a controlled shape and the highest purity compound whereas the VP technique is more versatile and offers scope for growth in specific orientations. The compound can be formed by heating the elements together since molten In will dissolve Sb. Hence the horizontal technique is not required for preparing the compound. However, the technique does offer scope for the growth of single crystals which can be zone refined in order to obtain very high purity uniform crystals. It is particularly important with InSb to avoid growth in the [ l l l ] direction since (111) facet formation gives rise to the facet effect and can cause very nonuniform crystals. The H G technique also enables single crystal zone refining in growth directions, which minimizes facet formation on the growth surface at the solid-liquid interface, such as the [211]Sb or [311]Sb orientations. The technique has been used successfully for the growth of high purity p-type single crystals for detectors but requires considerable care in control of the growth conditions in order to avoid twin formation. Crystal pulling using a Ge-type puller is a more versatile technique and is probably now used more frequently but it does suffer from the same twinning problems as already discussed. The (1ll)Sb facet is more stable, requiring a greater supercool-

ing for nucleation and growth on its surface than the (TTT)In facet. As a result, twinning tends to be more probable on the (1 1 l)Sb facet when it is present at the edge of crystals, where it is subject to liquid motion, exposure to the gas environment and greater temperature fluctations than when it is at the center of a pulled crystal. Thus growth in the [111]Sb direction is least likely to cause twinning even though there is a central (111)Sb facet whereas growth in the reverse [TTiIIn direction has the greatest likelihood of twinning since there is then the possibility of the formation of three (1 11)Sb-type edge facets. Although growth in the [l ll]Sb direction offers the greatest opportunity to avoid twinning and the preparation of completely single crystals it is not to be recommended for undoped crystals or for doped crystals with dopants which exhibit a marked facet effect since the usual capricious size behavior of the central or principal (111)Sb fact can give rise to very nonuniform crystals. Growth in the [211]Sb or [311]Sb direction is usually recommended. Twinning and trapezoidal shape problems for the crystals may ensue, but by careful control of temperature gradient and temperature stability these effects can be minimized.

2.6.2 InAs and GaAs The growth characteristics of both of these compounds are similar and both can be grown by the horizontal technique and by liquid encapsulation. However, the R&D carried out on GaAs vastly exceeds that on InAs. All the early work on these compounds involved their preparation in an H G apparatus (Sec. 2.5.1) in which As was distilled into the liquid group I11 element contained in a boat. The temperature of the liquid alloy was raised to the melting

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point of the compound as the composition of the liquid approached stoichiometry. Finally the melt was progressively crystallized to form an ingot. A fairly high yield of self-seeded single crystal ingots could be obtained in this way. As an alternative a single-crystal seed at one end of the boat could be used to give controlled nucleation, but this is not a simple process and requires considerable development. Although crystals can be grown in low temperature gradients, resulting in low dislocation densities, scaling up the process to cut circular sections is not an efficient or very successful process. It is understandable then that the advantages of the VP technique using the liquid encapsulation technique has resulted in LEC becoming the industry standard for the growth of GaAs and InAs. The role of liquid encapsulation was considerably enhanced by two significant developments: in situ compounding and the production of semi-insulating (SI) GaAs without recourse to Cr doping. In situ compounding of the elements Ga and As was made possible by the introduction of steel pressure vessels. Liquid As at the melting point of GaAs 1238°C has pressure of -80 atm. Thus progressively raising the temperature of a crucible containing a charge of elemental Ga and As under a layer of B,O, in a pressure vessel containing inert gas at 100 atm to a little in excess of 1238 "C is a convenient way of of forming a GaAs melt whilst avoiding significant loss of As. This in situ compounding has eliminated the need for compounding using a horizontal apparatus, a significant simplification. An additional important development was the use of BN crucibles. This had two effects, it avoided contamination by Si, which is endemic with the use of SiO, crucibles, thus giving a convenient very

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rapid processing route to the formation of very high purity GaAs charges for LEC growth. Also, and somewhat inadvertently, it provided a route to the production of SI GaAs. Swiggard and coworkers (1979) reported that GaAs prepared in BN crucibles generally had very high resistivity and furthermore the electrical properties of the product were relatively stable to the type of heat treatments needed to anneal out ion implantation damage. This was a very important result in connection with the use of GaAs for integrated circuits since SI material provided an excellent insulator on which integrated circuits could be fabricated using ion implantation. A complete explanation of the reasons for the formation of SI GaAs and for its semi-insulating character is the subject of continuing scientific debate which is beyond the scope of this article. However, the materials science of the processing of SI GaAs is important. It is evident that the SI properties are fundamentally connected with the EL 2 center, which is a complex defect involving an As antisite, that is, As on a Ga site. EL 2 is a well characterized electron trap 0.75 eV below the conduction band. In detailed studies it has been shown that the acceptor carbon combines with the EL 2 donor to control the resistivity of the GaAs. From a processing point of view a critical preparation parameter was shown to be the melt stoichiometry (Holmes et al., 1982). Thus the As atom fraction in the melt needed to be greater than 0.475 in order for the resulting crystal to be semi-insulating. This result is qualitatively consistent with the concept of an As antisite being responsible for the SI properties. The LEC technique is now a well established industrial process for the production of 2 inch and 3 inch diameter GaAs either as doped n-type material for use as sub-

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strates in the fabrication of devices such as light emitting diodes or as SI material for ion implantation and the fabrication of integrated circuits. However, in the last few years the VGF technique has assumed increasing importance as a means of preparing SI and doped GaAs crystals. As noted earlier the VGF technique involves the progressive crystallization of a molten charge in a vertical crucible by continuous adjustment or programming of the thermal profiles. It is a simple concept but its practical implementation is particularly demanding because of the lack of visibility and inability to follow exactly what is happening in the growth process and identify the onset of defect formation. This is a consequence of the use of nontransparent BN crucibles. Pressure vessels, often used for safety reasons, can also be a hindrance to visibility. Nevertheless, the quality of VGF crystals can be as good if not better than LEC crystals, indeed their dislocation densities are generally lower and more importantly uniformly distributed, a consequence, as with the horizontal technique, of the design resulting in low temperature gradients. The major unknown factors in both techniques are the average reproducible yields of single crystals that can be obtained. Yield is an overriding consideration in any growth process in the assessment of its commercial viability. One of the major factors which affects yield is twinning. The precise cause or causes of twinning in any growth run is difficult to identify, and whilst the general process is understood, what exactly brings about a twin misnucleation, be it an impurity, temperature fluctuation, foreign body or facet size, is rarely identifiable as a cause and effect relationship. As a result, trial and error development effort is normally expended in finding suitable twin-free growth conditions.

Twinning can be a serious problem in the VGF process not least because of the need to use [loo] seeds in order to meet industrial demand for (100) wafers. Here there is the additional problem of seedingon blind. The lack of visibility is a big handicap in VGF. Thus unlike the situation in the LEC process it is not possible to identify, for example, the causes of poor crystal quality and or twinning except by inference after growth. With LEC, twins are generally visible and crystals can often be regrown to eliminate them. Nevertheless, VGF is now a commercial process for GaAs and one must assume that sufficiently twin-free conditions can be developed in the growth process. General crystal growth experience would suggest that B,03 quality, boat material, interface shape and thermal stability would need to be carefully controlled. Indium arsenide has similar processing problems to GaAs, although here the melting point is lower and the vapor pressure at the melting point is -0.3 atm. But there is very much less commercial interest in InAs and only the horizontal growth and LEC techniques appear to be used. Twinning is possibly an even more troublesome problem with InAs than with GaAs. The problem is multiple laminar twinning. Again its origin is uncertain, although it is possible to develop twin-free growth conditions.

2.6.3 InP The application of the concept of liquid encapsulation to the growth of III-V compounds was initially reported for the growth of InAs and GaAs by Mullin and his colleagues (1965). The use of B,O, is well known metallurgically and has a long history in protecting molten metals from oxidation and vapor loss. In the case of the IV-VI semiconductors Metz et al. (1962)


used B 2 0 3in the crystal growth of volatile compounds of PbTe and PbSe. However, the most significant advance in the III-V compounds came with the application of liquid encapsulation to the concept of high pressure pulling in steel pressure vessels. Liquid encapsulation high pressure pulling was initially applied to the growth of InP and GaP (Mullin et al., 1968) and represented a breakthrough in the growth of these materials as high-quality single crystals. There is now considerable commercial interest in InP due in part to the InP-based structures used in the fabrication of very high quality lasers. It is becoming the laser material par excellence. The principal method of preparation of the raw material uses a pressurized horizontal technique involving distillation of P4 into a boat of molten In as discussed earlier. Crystal growth using the LEC technique is often carried out using a pre-pulled charge of InP. The LEC growth of InP has analogous problems to those of GaAs with respect to temperature gradients and the loss of the group V component. However, in addition, twinning of the crystals during growth is more of a problem. The effect of evaporation from the surface of the hot crystal after it has emerged from the B20, is more troublesome than it is with GaAs even though the absolute temperatures are less. The loss of P, from the crystal as it merges from the B 2 0 3 is connected, firstly, with the very high gas velocities near the crystal surface, and secondly with the temperature of the crystal surface, which is controlled by the temperature gradients. The high gas velocities are caused by Rayleigh convection driven by the high pressure, large temperature differences and relatively large dimensions of the Benard cells in the growth chamber. Convec-

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tion that can occur in pressure pulling systems correlates with the magnitude of the Rayleigh number R,, which is given by (Chesswas et al., 1971)

R,

ATg d3 P 2

(2-2) TKovo where AT is the temperature difference of the depth of volume of convecting gas (the temperature difference between surfaces driving the Benard cell), and T is an average gas temperature, d is the depth of volume of convecting gas, KO is the thermal diffusivity, v o is the kinematic viscosity and P is the gas pressure. Note that R, depends on the square of the gas pressure, the cube of d and the temperature difference between surfaces driving the convective Benard cell. It is important therefore in the pulling systems to avoid large free volumes with large temperature differences between the hot and cold surfaces. The temperature gradient effects are basically similar to those encountered in the LEC pulling of GaAs. Attempts to reduce the temperature gradients in order to reduce the dislocation density cause a slower rate of fall off in surface temperature of the crystal surface above the layer of B 2 0 3 with consequent loss of the B 2 0 3encapsulating film. The very high dissociation pressure of the InP also exacerbates the problem of P, loss. The loss of P, results in the deterioration of the surface quality of the InP involving the formation of In droplets which can move into the bulk InP under the applied temperature gradient by temperature gradient zone melting (TGZM) towards the solid-liquid interface. The need for low dislocation density is very important for device applications and there is an imperative need to reduce them well below the norm of lo4 to lo5 cm-2 generally found in undoped and lightly =

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doped material to lo3 or nearer IO2 cm-2 for many device applications. Attempts to reduce the temperature gradients and the dislocation desities have been reported by Hirano et al. (1992). They used a system of double heat shields or baffles in order to reduce the temperature gradients. This was done in a way that minimized P, loss presumably by minimizing gaseous convection.

2.6.4 II-VI Compounds: General The status and development of II-VI crystal growth is very different to that of the III-V compounds. Most strikingly there is no successful pulling technology and it is only in the last few years that large-area CdTe and Cd,Zn - ,Te singlecrystal material has become available. The reasons for this are partly historical and partly materials property related. A significant R&D effort was deployed on the IIVI compounds in the 1950s and 1960s, but following the lack of any significant commercial device promise the major research companies stopped work on the II-VI compounds. The enthusiasts continued, but the problems were formidable and progress was slow. In this phase of development, bulk vapor growth of the II-VI compounds was the most successful crystal growth technology. However, in the early 1980s there was a resurgence of interest in the II-VI compounds partly at least following the availability of the newer low temperature epitaxial technologies which were developed in the 1970s and 1980s for the III-V compounds. The constraints to the melt growth of the II-VI compounds are fundamentally similar to those of the III-V compounds but practically very much more difficult to overcome. All the II-VI compounds exert significant vapor pressures of their compo-

nents at the their melting points. ZnS and CdS have inaccessibly high melting points for melt growth. The more ionic nature of the compounds compared with the III-V compounds gives rise to low critical resolved shear stresses and ease of deformation of the compounds. The high point defect concentrations of the compounds near the melting points conspire with the high diffusion rates in the II-VI compounds, they are orders of magnitude greater than in the III-V compounds, to allow polygonization of dislocations and the formation of grain boundaries and especially subgrain boundaries. The latter are virtually unknown in III-V compounds. Liquid encapsulated pulling cannot be used to overcome the volatility of the compounds since B,03 is partially miscible with II-VI melts. Even if LEC could be used, the ease of deformation would probably limit the value of the technology. The emergence of II-VI epitaxial device structures stimulated new developments in the crystal growth of the II-VI compounds. One can readily identify requirements which were and still are responsible for creating the need for this work: bulk Hg,-,Cd,Te for 3-5 pm and 8-14 pm detectors, CdTe and Cdl -,Zn,Te substrates for epitaxial Hg, -,Cd,Te and ZnSe for blue light emitting diodes and lasers. 2.6.4.1 Bulk Hg

- ,Cd,Te

Research on mercury cadmium telluride (MCT) has never waned since its discovery and it is still an active topic of materials R&D. Three main bulk techniques have been developed, the vertical Bridgman technique, the American quench anneal technique, an equivalent UK technology called the cast recrystallize anneal (CRA) technique and a traveling heater technology.


The vertical Bridgman technique involves sealing the pure elements in a thickwalled (3 mm) silica tube, a requirement needed to handle the Hg pressure, which can exceed 20 atm for melts used in the preparation of Hg,.,Cd,,,Te. After melting and mixing in a rocking furnace, the charge is frozen as an ingot and transferred to a VB apparatus where it is again completely melted and then slowly crystallized by withdrawal from the furnace. The resulting ingot has a composition gradient which varies from an x of 0.3 to less than -0.18 depending on the start composition. Much effort has been devoted on devising controlled mixing schemes to maximize the yield of x=0.2 and 0.3 detector material. These attempts have included work on the accelerated crucible rotation technique (ACRT), which involves increasing the rotation of the crucible in one direction from rest, slowing it down, and then repeating the operation. This can then be carried out in the opposite direction, but this is not essential. A great deal of study has been carried out by Capper and his colleagues (1994) at Mullard/Philips Research Laboratories (now GEC-Marconi) on this technology with very good results. The melt mixing conditions have attracted much study and whilst a great deal has been discovered the interactions between the complex transient Couette flow the spiral shearing and the Eckman flows across the solid-liquid interface are still not understood. The need to prepare very uniform MCT has resulted in the development of a unique technology, that of quench anneal (QA) or CRA. The method involves rapidly casting a melt of the appropriate MCT compositions in order to produce a macro uniform solid. On a micro scale, however, the material is extremely nonuniform a consequence of the dendritic growth as N

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well as the effects of constitutional supercooling. Advantage is then taken of the very high interdiffusion in these compounds and the material is recrystallized in a temperature gradient. This gives uniform MCT but also a high acceptor concentration, which equates to the high Hg vacancy concentration. This is eliminated by a final Hg anneal at low temperature. This is an astonishingly well developed technology, a consequence of support from a military infrared detector programme. The third bulk technology is the travelling heater method (Triboulet, 1994), which was described in connection with the purification and preparation of MCT in Sec. 2.3.3.4. This technique is also used for the growth of Zn,-,Cd,Te an alternative to MCT as a detector material. Material with very uniform x can be grown but the extent of material development is confidential and not available. Although bulk grown MCT is still used it is rapidly being superseded by liquid phase epitaxy (LPE) and by metal organic vapor phase epitaxy (MOVPE) and the less developed molecular beam epitaxy (MBE). These epitaxial technologies require highquality substrates which is the main reason for the extensive development of CdTe and Cd - ,Zn,Te.

2.6.4.2 CdTe and Cd, -,Zn,Te The most developed technology for these materials is the vertical Bridgman technique, where 2 inch and 3 inch diameter crystals, principally of Cd, -,Zn,Te, for use as substrates for MCTZ are under development. Again the technique involves the withdrawal of a molten charge of material from a furnace. The growth of both CdTe (Rudolph, 1995) and Cd,-,Zn,Te (Sen and Stannard, 1995) have recently been reviewed. The major

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problems affecting the production of highquality single crystals are the avoidance of twins and both large and small angle boundaries. Tellurium precipitates cannot be avoided during growth but can be eliminated by a post-growth anneal in Cd vapor. The unequivocal correlation of the causes of the defects with the growth conditions is difficult to establish but it would appear that the main requirements for good growth are a flat to convex growth surface (relative to the solid) together with low axial and radial temperature gradients. The use of too low an axial temperature gradient can cause a condition of constitutional supercooling and hence a compromise value needs to be selected. Naturally a stoichiometric melt is needed which strictly requires a controlled separate Cd vapor source. However, since the effective distribution coefficient of Zn is 1.3 its segregation can also result in a condition of constitutional supercooling and hence it is important to grow ingots slowly to give time for rejected solute to diffuse into the melt and not build up as a solute boundary layer. The horizontal growth technique has also been developed over the last few years to grow high quality CdTe and Cd, -.Zn,Te. Crystals allowing the selection of single crystal sections greater than 2.5 inch in dimension have been grown from 4 kg ingots (Liao et al., 1992). Larger systems are under development. Seeds are mounted in a raised section at the top of the boat. Seeded growth propagates freely across the top of the surface of the liquid, resulting in the formation of large singlecrystal areas. There is very little detailed information available on the reasons for the good growth other than it is important to avoid propagation from the multiple grains which can be initiated by growth

nucleated on the bottom silica surface of the boat.

2.6.4.3 ZnSe The very high melting point of ZnSe, 1526 "C, makes the vertical Bridgman technique very difficult and most studies have been carried out using vertical gradient freeze technology. But neither of these melt growth techniques give really good quality crystals. Significantly, using a bulk seeded physical vapor transport technique better ZnSe crystals have been obtained by Cantwell et al. (1992). This method is now used by Eagle Picher as a production method. The technique uses 2 inch diameter seeds at either end of a quartz tube. A charge is situated half way between the seeds and is transported to the seeds using an appropriate temperature gradient. The growth of up to 2 inches of crystal has been reported. Very good quality ZnSe having etch pit densities of - 5 x lo4 cm-2 has been grown. It is evident that growth at temperatures below the melting point are very important for ZnSe. Indeed bulk vapor growth could be the technology of the future for the II-VI compounds.

2.6.4.4 ZnS and CdS The very high melting points of ZnS and CdS mean that melt growth is not possible. As a consequence considerable effort has been devoted to the development of vapor growth techniques for these compounds. A variety of physical vapor transport arrangements have been attempted. Probably the most successful has been the PiperPolich technique (Piper and Polich, 1961). This is illustrated in Fig. 2-6a. It uses a tube having a coned tip. The charge can first be transported by an appropriate temperature gradient away from the tip. Growth is achieved by physically moving

2.7 Fundamental Aspects of Crystal Growth

G

A

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B

Figure 2-6. Schematic illustrations of vapor growth techniques. (a) Piper-Polich technique showing the growth crucible A supported by an outer jacket B mounted inside the furnace F. Movement of A relative to the heater (thermal profile) causes vapor transport of the charge G and its crystallization in the cone of the crucible. (b) Controlled vapor pressure method; growth crucible A has a long side tube D containing the elemental source E which controls the vapor pressure of the more volatile component; note seed crystal C and charge G and thermal profile.

the tube so that the tip sees a progressively lower temperature than the charge. A single crystal can be grown from the tip. An important factor in the growth of most 11-VI and other compounds is the necessity to maintain similar vapor pressures of both components during growth. This requirement can be fulfilled by using a separate source of the more volatile component. Its vapor pressure can then be independently controlled and adjusted to that of the other component. The concept is illustrated in Fig. 2-6 b. A major problem with this and all the other earlier vapor growth technologies is that the crystal grows against the silica tube, often sticking to it. On cooling, differential contraction between the crystal and the tube causes strain and stress, resulting in the introduction of dislocations. Attempts have been made to develop freegrowing systems for CdTe and other 11-VI

compounds in which the crystal grows out of contact with the tube but it is not an easy technology and very carefully designed thermal systems are required.

2.7 Fundamental Aspects of Crystal Growth The purpose of this section is to provide a brief insight into the origin and mechanism of those dominant phenomena which are of practical importance in the processing of compound semiconductors and which can affect crystal quality and perfection. Only the significant aspects of structure, vapor pressure, temperature distribution, diameter control, facet effect, anisotropic segregation, twinning, solute distribution, constitutional supercooling, dislocations and grain boundaries will be considered.

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2 Comoound Semiconductor Processing

2.7.1 Structure Germanium and Si have a simple diamond cubic structure, which is centrosymmetric, and as a consequence there are no significant growth anisotropies. However, in the case of the compounds the different atoms have different electron affinities and as a result on finds a polarization of properties. In the case of the 111-V and 11-VI compounds the crystal is either zinc blende or wurtzite. This conveys a polar nature to the structure, and as result for the zinc blende, for example, growth in the [hkl] direction is different to growth in the [hkl] direction. The crystal structure shown in Fig. 2-7 highlights this difference. The bond directions are (1 11) or (TIT) where the (TTT) direction terminates in a singly bonded group I11 atom and the opposite (1 11) terminates in a triply bonded group V atom. The (111) planes therefore have different polarities from the {TTT} planes and hence different stabilities. Thus each will require a different supercooling in order to initiate nucleation and growth. One of the most significant phenomena associated with structure is the development of (111) or {?Ti) type facets on growth surfaces. These can give rise to the facet effect and correlate with twin formation (see Sec. 2.7.5).

2.7.2 Temperature Distribution, Crystal Shape and Diameter Control One of the more difficult problems in growing crystals from the melt is the problem of arranging for the most suitable temperature distribution and temperature gradients in the growth chamber. Thermal modeling should ultimately provide a quantitative scientific background to the process but in practice it is still an operation requiring considerable skill and know-how.

Modeling horizontal growth is of course very much simpler than modeling vertical pulling. From the practical viewpoint it is important to appreciate that the relatively low temperature gradients normally used in the growth of compounds means that very small practical changes in the growth chamber, such as a small movement of a heat shield can often have a dramatic effect on crystal growth. It also is evident that many thermal models do not take full account of practical thermal arrangements. A major problem in HG and in VGF is the control of interface shape. It is generally recognised that the growth surface should be flat or slightly convex. Concave growth surfaces frequently result in crystal growth defects such as grain boundaries or trapped-in solute. Unfortunately, many heater designs involving a simple extra heater zone used to form a liquid zone are naturally prone to form concave growth surfaces. The use of modeling and the introduction of better thermal design concepts is beginning to overcome this problem. Vertical pulling apparatus, in contrast, is very difficult to model thermally, especially in the critical region of the solid-liquid interface. Unlike HG, where shape is controlled by the shape of the boat and is not an experimental problem, in VP shape or diameter control is a major problem, and one on which a vast amount of R&D effort is expended. The critical parameters controlling interface shape are the thermal heat balance at the solid-liquid interface and the surface tension forces operating between the solid, liquid and gaseous surfaces. The simplest approximation of the heat balance at the solid-liquid interface is given by


97

Figure 2-7. Zinc blende lattice showing (1 11) and (TTT) bond directions and the nature of the lattice polarity.

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where G is the temperature gradient, cr is the thermal conductivity, e, is the density of the crystal and H, is the latent heat of fusion. The temperature gradient G,(Z=S, L) refers to the gradient normal to the solid-liquid interface. In crystal pulling a net loss or gain of heat normal to the crystal axis at the solidliquid interface will cause the growth surface to become convex or concave. The crystal diameter, however, is determined by the shape of the meniscus above the melt. Figure 2-8 shows the steady-state position of the crystal being pulled from the melt and the shape of the meniscus. To a first approximation a meniscus which increases in diameter from the crystal causes the growing solid to increase in diameter. A meniscus which decreases in diameter or waists in from the crystal causes a growing crystal to decrease in diameter. However, this model is only an approximation since shape is also controlled by surface tension forces. Crystals appear to fall into two categories depending on whether their melts completely wet their solids or not. Melts of diamond cubic or zinc blende do not completely wet their own solids i.e.,

Figure 2-8. Diagrammatic illustration of the meniscus contact between a melt and its crystal at an angle 0,(0: for a crystal growing at constant diameter) to the vertical where the edge of the crystal is at an angle 0, and at a height h above the melt surface.

< 4sL+ 4 L G , where 4rJ refers to the interfacial free energies of the respective pairs of the three phases solid, liquid and gas. Thus under equilibrium conditions where the crystal is growing as a right cylinder the meniscus will contact the solid at a specific angle 0, , but at a general angle 0 when growing in or out (see Fig. 2-8). Thus if @@, the crystal will grow out. It is important to note that 0, is not zero but has a positive value for semiconductors, being 11" for Si and 13" for Ge. Thus the actual pull of crystallizing atoms when the liquid meets the solid at a positive angle 0, gives rise to a right cylinder. Device technology - certainly that related to intergrated circuits - requires wafers having a tight specification on diameter, hence there is a need for diameter control in crystal pulling in order to grow constant-diameter crystals. Since the seeding process uses small-diameter single crystals for use as seeds, the pulling system needs to be able to be programmed to achieve a carefully controlled variation in crystal diameter both at the beginning and end of growth. A number of technologies (Hurle, 1993) have been proposed to monitor and control crystal diameter but the most versatile technique (Hurle, 1977) involves continuously monitoring the weight of the crystal (in practice the crystal plus pull rod), or the weight of the melt (in practice the melt plus crucible) and from a knowledge of the pull rate or, strictly, normal growth rate one can monitor continuously the crystal diameter. Diameter control involves either comparing the weight (weight mode) or the rate of weight change (differential weight mode) to the desired weight or desired rate of weight change and using the difference $SG


or error signal in order to control and vary the power to the melt. An example of a commercially produced weighing cell attached to a RSRE research crystal puller is shown in Fig. 2-5. The weight mode has the advantage of the ability to correct errors generated in the previous stage of growth. The signal-to-noise ratio is good and the system can be used down to low growth rates, but corrected errors can give rise to a damped oscillation in the shape which propagates down the crystal. The differential weight mode seeks to keep the diameter at its present value, ignoring previous history. The signal-tonoise is less good because of the signal differentiation. This mode tends to be a more stable servoloop, which is less sensitive to the thermal lags in the system. One of the problems of growing 111-V compounds using either of the weighing methods is that the immediate response of the error signal to a requested change in diameter is opposite to the intended change. That is, a request for an increase in diameter gives an error signal that causes a decrease in diameter. This so-called weighing anomaly arises from two effects. Firstly, 111-V compounds expand on freezing and, secondly the apparent weight of the crystal contains contributions arising from surface tension forces. A practical solution has been found in that the predicted anomalous error signal is subtracted from the total error signal to give a corrected error signal. This technology has enabled the controlled diameter growth of GaAs, InP, Gap, Ge, Si and many other crystals.

2.7.3 Solute Distribution Dopants and impurities are the main solutes of interest in crystal growth studies of Si and Ge. In the case of the compounds, however, there is an additional source of

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interest and study, which is the solute effect of excess of one of the components. Such an excess is a very common problem in growth of compounds and readily leads to conditions of constitutional supercooling and heavily defected growth. Solute distribution during crystallization can be conveniently described in terms of distribution coefficients as illustrated in Fig. 2-9. As a result of crystallization, since the solute is less soluble in the solid in the example chosen, rejected solute increases in concentration at the solid-liquid interface and assumes a steady-state concentration as a result of diffusion and convective mixing away from the interface. It is convenient to define in this situation an interface distribution coefficient k* (k* = CJC,) and an effective distribution

SOLUTE

1

CONCENTRATION SOLID

ICs SUPERCOOL1NG

*-

SI L INTERFACE

DISTANCE

Figure 2-9. (a) Solute (k, < 1) distribution during crystal growth showing interface and bulk concentrations C, and C, and the “mathematical” boundary layer 6. b) Liquidus distribution corresponding to the solute distribution above showing three different real temperature distributions P,, the stable situation, P,, the critical situation and P,, the unstable situation due to the zone of constitutional supercooling.

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coefficient kerf(k,,, = C,/C,). The latter is the parameter measured experimentally since both the concentration in the bulk melt and the crystal are accessible to measurement. However, k* is not immediately accessible; it is simply the equilibrium distribution coefficient k , modulated by the growth process. If incorporation were an equilibrium process, for example involving growth under ideally slow conditions, then k* would equal k , . In practice, k* is often a function of orientation, growth rate and solute concentration. Most of our knowledge of transport in the melt and its effects, particularly on crystallization, have been obtained on pulled crystals, where the effects of stirring can be modeled. The relationship between k*, k e f , and the stirring conditions was derived by Burton, Prim and Slichter (BPS) (1953) in a classic paper in which they introduced a parameter 6, which was related to but was not the diffusion layer thickness. The mathematical convenience of 6 is that it can be used to model the height of the boundary layer at the growth surface under different stirring conditions. In the BPS model the relationship between kerf and k* is given by keff

=

k* [k* + (1 - k*)e-”]

(2-4)

where A = vG/D and 6 = 1.6D’I3 vAl6 u -l i 2 , where t’ is the growth velocity, D is the diffusion coefficient of the solute in the liquid, v , is the kinematic viscosity and u is the angular rotation rate. The model makes use of an earlier analysis by Cochran (1 934), who analyzed the flow velocity normal to a disc rotating in a semiinfinite fluid. From Eq. (2-4) the effect of growth rate and rotation rate on the incorporation of impurities and dopants can be predicted. Under good stirring conditions 6 -+ 0,

and hence kerftends to the value of k*, but where stirring conditions are poor 6 + 00 and kerf tends to 1. The model has been used in predicting the onset of constitutional supercooling in the growth of heavily doped melts (Hurle, 1961; Bardsley et al., 1962), but here its significance in the growth of compounds growing under nonstoichiometric conditions will be considered. 2.7.4 Constitutional Supercooling

Consider the segregation situation illustrated in Fig. 2-9. In (a) the rejected solute forms a boundary layer where the concentration of solute rejected decreases with distance away from the interface. This concentration distribution is represented in (b) by the liquidus temperature, or freezing temperature distribution. Superimposed on this is the actual physical temperature distribution. If the slope PI is greater than the slope of the liquidus distribution at the solid-liquid interface, then the temperature of the melt will always be greater than the liquidus temperatures in the melt ahead of the interface, giving a stable situation. However, if the actual temperature distribution is, as shown by P,, less than the slope of the liquidus at the interface then in the shaded region there will exist as shown in the diagram a region of the melt where the actual temperature is less than the liquidus temperatures, resulting in an unstable situation. The melt will be supercooled. Under these conditions a perturbation on the growth surface will experience greater supercooling, resulting in accelerating growth into the bulk melt. The critical condition for the onset of supercooling was taken by Hurle (1961) to be the condition when the gradient of constitutional supercooling became equal to or greater than zero. The gradient of con-


stitutional supercooling was defined as the difference between the gradient of the liquidus and the actual temperature gradient at the interface. Using the BPS model the gradient of constitutional supercooling (dS/dx),,, is given by

umC,(1 - k*) - GL D [ k * + (1 - k*)e-A]

(2-5)

where m is the gradient of the liquidus, CL the solute concentration and the other parameters are as defined in Eq. (2-4). Putting (dS/dx),,, = 0 one can obtain the critical growth velocity for the onset of constitutional supercooling. uCritgiven by ucrit

=

D G, [k* + (1 - / ~ * ) e - ~ ] mCL(l- k*)

(2-6)

Thus the critical (maximum) growth velocity for good stirring conditions (6 -,0) is DG,/(mCL) and for bad conditions (6 -,co),[DGJm C,)] x k*. If from Eq. (2-3) asGsis very much larger than UQJH~, we can substitute (as/oL) G, for GL. In the case of GaAs, if G, is 50 "Ccm - and as/ 0,=0.54, and m=3"C (at.%)-', C,=l at.% and D=10-4cm2 s - l for ideally good stirring conditions, the critical growth cm velocity uCritwould be equal to 9 x s - l (3.2 cm h-'). Under poor stirring conditions uCritis modulated by a factor of k*. Thus constitutional supercooling is very sensitive to small distribution coefficients. This is a very important aspect of the growth of compounds where it is often very difficult to control the stoichiometry of the melt of dissociable compounds. In the case of the arsenides and phosphides of the 111-V compounds, the excess component in nonstoichiometric melts behaves as a solute with negligible solubility in the The solid, that is with a k* of significance therefore is that it is extremely difficult to avoid constitutional supercool-

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ing in the growth of compounds unless the melts are very close to stoichiometry. In the case of horizontal growth one has the additional hazard of low temperature gradients. The effect of growth under conditions of constitutional supercooling (Bardsley et al., 1962; Hurle et al. 1961) is illustrated in Fig. 2-10. A planar growth surface initially breaks up into a sinusoidal or rumpled surface. Where the solid-liquid interface becomes parallel to { l l l} planes the growth surface develops a ridge or roof-type structure delineated by (111) facets. The regions between the rooftops are valleys where the rejected solute gets trapped. The regions of the crystals grown behind the rooftops between adjacent valleys are the so-called cells; the growth gives rise to a cellular structure. The cells grow more or less independently of one another. Examples of cellular structure on the surface of a crystal can be seen in Fig. 2-11. The effect of progressive constitutional supercooling is to cause the crystal to de-

Figure 2-10. Effect of constitutional supercooling on a planar growth front 1. Rejected solute causes the growth surface to rumple 2 and then develop a faceted structure 3. The full cellular structure traps in solute as illustrated.

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slowly with good stirring and with as large a temperature gradient at the interface as possible.

2.7.5 Facet Effect, Anisotropic Segregation and Twinning

Figure 2-11. Crystal end showing the development of cell structure which is evident from the faceted grooves on its surface.

velop polycrystallinity. The trapping of excess solute initially represents a separate liquid phase for the case of a group I11 element. The trapped droplets move under the influence of the temperature gradient (TGZM) towards the solid-liquid interface. The droplets ultimately get frozen in since the crystal growth rate is greater than the diffusion-controlled transport rate of the droplets. The resulting two-phase regions create strain and dislocations and marked nonuniformity. Additionally the facets on the ridge structure exhibit the facet effect giving rise to additional nonuniform dopant and impurity incorporation. Great care is therefore required in the melt growth of compound semiconductors if constitutional supercooling effects are to be avoided. The basic need is to maintain stoichiometric melts and to grow crystals

Facets or atomically flat planes, which are generally of low index, so-called singular planes, are a feature of compound semiconductor growth; they can adversely affect both the yield and quality of crystal growth. The most troublesome facets are of the (111) or (TTT) type. Four of each type can occur over a closed volume. Facets develop when the (111) planes become tangential to the solid-liquid interface as illustrated in Fig. 2-12. The majority of the crystal surface, which comprises growth steps which are easy sites for nucleation, requires negligible supercooling for growth and thus follows the melt isotherm. However, where the isotherm becomes tangential to the (111) the facet plane truncates the growth surface, there are no growth steps on the (1 11) plane, and there

‘(111)

FACET

Figure 2-12. Diagrammatic representation of the formation of a (1 11) facet on a growing crystal showing the equilibrium melting point isotherm T,. The TM-AT isotherm illustrates the potential for the development of a maximum supercooling AT


is a difficulty of nucleation. The facet lags in growth behind the rest of the surface defined by the melt isotherm. The facet grows in size sufficiently in order to develop sufficient supercooling AT in the melt above its surface to initiate nucleation and subsequent growth. Hulme and Mullin (1959) discovered that many impurities are preferentially adsorbed on [111] planes. The effect known as the facet effect is dramatically large for the case of Te in InSb, where the distribution coefficient for growth on a { 11l} type facet was 4 whereas just off a { 11l} type facet it was -0.5, giving a facet ratio k[on (111) facet)]/k[off (lll)facet] of -8, which can result in very marked dopant nonuniformities. The diagrams at the bottom of each montage in Fig. 2-13 illustrate the relationship of the { 11l} planes for growth in the [TTTIIn and [loo] growth directions. For growth in the [iii]In direction there will be three (111) directions of the opposite type at 70.5" to the [TTIIIn direction. For the [loo] direction there will be two (iTT)In and two (111)Sb directions at 55" to the [loo]. Differences in facet behavior can be seen in Fig. 2-13, which is a montage of autoradiographs of slices cut from InSb crystals that were grown using radioactive lZ7Teas a dopant. The brighter regions are lz7Terich. The diagrams at the bottom of Fig. 2-13 illustrate the "spraying out" effect of the lz7Teradiation onto the autoradiography film. Slices were taken from different positions down crystals grown in the [TTT] and [loo] directions. The [TTi]In crystal shows the central or principal facet together with the three edge facets which are of the { 111}Sb type. The disappearance of one of the (111)Sb facets in the last slice is indicative of a recently formed twin. The [loo] crystal shows two opposite {TTT}In N

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facets and two opposite (111)Sb facets, the differences in size clearly indicating that the (111)Sb facets are larger than the {ITT}In and require more supercooling for growth. Note the evidence of a small (100) principal facet. Figure 2-14 is a longitudinal section of a '27Te-doped (1 11) crystal which shows the coring effect of the (111) principal facet and also the rotational striations which have a periodicity of one per revolution. The autoradiographs clearly indicate that facet development is an important and critical phenomenon in crystal growth and can bring about very significant dopant and impurity nonuniformities. Twinning can be a particular problem in the growth of 111-V compounds and can strongly affect yield in any growth process. The growth twins occur on { 11l} planes, which is the twin composition plane and can be described as a rotation of 60" about the (1 11) direction. First nearest neighbor atoms are not affected by the rotation, only second nearest neighbors. The interaction energy associated with the marked increase in distance of the second nearest neighbors is thus quite small, a factor which enhances the twinning probability. The exact mechanism of twinning is not understood as a cause and effect phenomenon. Thermodynamic conditions for twinning on edge facets have been proposed by Hurle (1995) in a recent model. Differences in material behavior appear to be predicted, but to what extent kinetic effects are involved is still an open question. Thus anything that could allow an atom to go down on a (111) surface misoriented in rotation by 60" could be implicated, Impurity atoms, temperature fluctuations and stoichiometry have all been invoked but unequivocal proof as opposed to strong evidence, e.g. stoichiometry, has not been established.

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Figure 2-13. Montage of autoradiographs of slices cut from (a) [ l l l ] In and (b) [loo] InSb crystals that had been grown from a '"Te-doped melt. The bright regions of Te-rich growth illustrate the development of facets: (a) the central or principal (TTT) In facet and the large edge (1 11) Sb facets - the disappearance of one facet effect in the last slice shows the momentary effect of twinning; (b) note the development of the opposite (111) Sb edge facets and the smaller (11 1) In facets as well as evidence of a (100) facet. The diagram at the bottom of each montage illustrates the crystallographic directions and the "spraying out" effect of the '"Te radiation into the autoradiographic film.

Twinning continues to be one of the more frustrating and annoying yield-limiting phenomena in crystal growth. Facet formation appears to be a necessary but not unique requirement for twinning. One correlation that is associated with twinning is that the avoidance of facet forma-

tion can reduce or eliminate twinning, However, any surface which is tangenital to a { 111) is prone to develop a facet. Under equivalent growth conditions the lower the temperature gradients, the bigger the facet, since a fixed supercooling is required for growth on a facet. Since low tempera-


105

Figure 2-14. Facet-effect nonuniformities illustrated with an autoradiograph of a longitudinal cross-section of an InSb crystal grown from a '"Te-doped melt. The principal (111) facet causes very marked nonuniformity. Note the oneper-revolution striations.

ture gradients are a basic requirement to minimize dislocation formation, it is often difficult to avoid facet formation and twinning in crystal pulling.

2.7.6 Dislocations and Grain Boundaries Dislocations and grain boundaries are a major impediment to the quality of 111-V (Jordan et al., 1980) and 11-VI compounds (Williams and Vere, 1987) grown from the melt. In the case of 111-V compounds and possibly in the case of the 11-VI compounds one of the main causes of dislocation formation during growth or under post-growth conditions are adverse temperature distributions that give rise to strain and resulting stress. Vertical pulling provides a classic example of this phenomenon. Steep temperature gradients can result in the inner region of the crystal being at a different temperature to the outer. This can give rise to a hoop stress which acts on the inclined (111) planes to produce slip and dislocation formation. Considerable effort has been

devoted to theoretically analyzing (Jordan et al., 1980; Volkl and Muller, 1989) this problem and to practically analyzing means of avoiding or minimizing the problem. Most research has been carried out on the LEC growth of GaAs although other useful information has been obtained from the growth of other 111-V compounds such as InSb, InP and Gap. There is now general agreement that steep temperature gradients which are conductive to good diameter control and pulling conditions are detrimental in LEC growth and lead to relatively high dislocation densities, around 5 x IO4 cm-' for GaAs and InP in the pulled crystals. These densities can be reduced typically by a factor of ten or more by using reduced temperature gradients but these lead to poor diameter control loss of B,O, from the surface of the pulled crystal with consequent deterioration in crystal quality. One of the critical regions requiring good thermal control is at the solid-liquid interface itself and the region around the surface of the B,O,. Thus Jordan and

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coworkers (1980) have shown that the heat loss from the crystal to the B , 0 3 is 50 times as great as the heat loss from the crystal to the ambient gas. In effect the gas acts as a thermal insulator in comparison to the B , 0 3 . This situation favors hoop stresses. It also leads to considerable difficulty in crystal diameter control, thus the well-known phenomenon of the rapid decrease in crystal diameter as it emerges from the surface of the B,O, due to the reduction in temperature gradient due to reduced thermal loss from the top surface of the crystal. Jacob (1982) has advocated the growth of GaAs completely submerged under B,03 but the technique does not appear to have a large following. An alternative way of reducing dislocation densities is to harden the lattice by doping (Jacob et al., 1983). Dopants make dislocation motion difficult either by a pinning effect or by simply reducing dislocation velocities. However, rather high doping densities are required, typically above IOi8 atoms/cm3 and the technique has only very limited scope for heavily doped material for special applications. The current state of development is one where LEC is a commercially viable technique with versatile doping and growth orientation abilities, but where the ultimate low dislocation density, say IO3 cm-2 is not readily achievable. In contrast, VGF can achieve these low dislocation densities but it is not a versatile technique and is more suited to dedicated product applications. The melt growth of 11-VI compounds, unlike that of the 111-V compounds, gives rise to the formation of grain boundaries. The reason for the formation of grain boundaries is probably associated with the more ionic character of the 11-VI lattice and the considerably enhanced diffusion in 11-VI compounds compared with 111-V compounds.

The grain boundaries may be loosely classified as small angle, around IO-’ degree, and large angle, around a degree. Small-angle boundaries are very difficult to remove and indeed are quite stable. Large-angle boundaries can usually be seen visually by lightly grinding a surface. The minority carrier lifetime can be severely affected by grain boundaries, hence the development of methods aimed at eliminating grain boundaries is a priority in IIVI compounds.

2.8 Wafering and Slice Preparation The conversion of a bulk crystal into a form suitable for device fabrication is a vital and crucially important stage in processing. It is not a topic that attracts much published literature (Tada et al., 1990) if only because wafer processing is commercially sensitive, since wafer quality correlates directly with saleability. Most device fabrication procedures involve some form of planar technology. The machinery used for cutting and wafering of compounds is usually the same as that developed for the Si integrated circuit market, where the requirement is for accurately dimensioned circular wafers. In the case of the compounds the diameters are currently much less than the standard 6 inch Si. Two inch GaAs and InP is now being replaced by 3 inch material as the norm. The need for circular wafers is one of the main driving forces for the development of the LEC and VGF processes. The HG technique is supported only where it can achieve characteristics not readily achievable as effectively in other techniques, such low-cost production of very low dislocation density GaAs for laser diodes.

2.9 References

As-grown crystals are not ideally circular and after growth they are normally ground into a right cylinder having the correct diameter. The cylindrical boules are then sliced into wafers. In the Si industry this process is carried out using a high speed diamond slitting wheel. The compound semiconductors are structurally much weaker than Si and early attempts at using this technology often resulted in failure and broken wafers. In the research area slow speed cutting was developed. In an attempt to overcome wheel wobble, cutting wheels were used which were clamped and mounted and driven from their periphery. The narrower diameter internal edge of the wheel was used for cutting. The wheels were stressed to create stiffness. All cutting is a highly skilled process which requires exceptionally high quality machines in which vibration is totally eliminated. The boule is mounted on an adjustable table which fits both the X-ray orientation equipment and the cutting machine. In this way precisely oriented boules are sliced often to 0.1O or less. Commercial pressures and the need to reduce cutting times have resulted in improvements and developments in high-speed saws which can now be used successfully for cutting GaAs and InP and the 111-V compounds. All cutting gives rise to surface damage, which may be c 10 pm for Si, and up to 50 pm for GaAs and even more for 11-VI compounds. This damage must be removed. It can be achieved by a lapping process, but now that surfaces can be cut sufficiently flat it is usually sufficient to chemically polish the surfaces directly removing up to three times the depth of cutting damage at least. Often up to 100300 pm is needed to remove all trace damage and prepare the highest quality polished surface for wafers. The quality of epitaxial growth is crucially dependent on

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the quality of surface finish on wafers. It is a major concern in the purchase of such wafers. The finishing treatment for wafers involves the use of final etches for two reasons. Firstly, even a chemical polish introduces minor damage due to the loading of the specimen, and secondly, there is a need to prevent electropositive elements like Cu plating back onto the highly polished surface since such contamination could be detrimental to subsequent device structures fabricated on the wafers. The technology and know-how of these processes, however, are generally commercially confidental.

2.9 References Al-Bassam, A. A. I., Al-Juffali, A. A., Al-Dhafiri, A. M. (1994), J. Cryst. Growth 135, 476. Arthur, J. R. (1967), J. Phys. Chem. Solids 28, 2257. Bachmann, K. J., Biihler, E. (1974), J. Electrochem. SOC.121, 835. Balasubramanian, R., Wilcox, W. R. (1993), in: Proc. E-MRS Conf. (Symp. F) CdTe and Related Cd Rich Alloys, Strasbourg, June 1992. Mater. Sci. Eng. B 16, 1. Bardeen, J., Brattain, W. H. (1948), Phys. Rev. 74, 203. Bardsley, W., Boulton, J. S., Hurle, D. T. J. (1962), Solid-State Electron. 5, 395. Bourret, E. D. (1990), Am. Assoc. Cryst. Growth Newslett. 20 ( 3 ) , 8. Burton, J. A., Prim, R. C., Slichter, W. P. (1953), J. Chem. Phys. 21, 1987. Cantell, G., Harsch, W. C., Cotal, H. L., Markey, B. G., MacKeever, S. W S., Thomas, J. E. (1992), J. Appl. Phys. 7 1 , 2931. Capper, P. (1994), Prog. Cryst. Growth Charact. Mater. 28, l . Chesswas, M., Cockayne, B., Hurle, D. T. J., Jakeman, E., Mullin, J. B. (1971), J. Cryst. Growth 11, 225. Clemens, J. E., Gault, W. A., Monberg, E. M. (1986), AT&T Tech. J. 65, 86. Cochran, W. G. (1934), Proc. Camb. Phil. SOC.30, 365. Czochralski, J. (1917), Z . Phys. Chem. (Leipzig) 92, 219. Fischer, A. G. (1970), J. Electrochem. SOC.117, 41C. Gault, W. A,, Monberg, E. M., Clemens, J. E. (1986), J. Cryst. Growth 74, 491.

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Gremmelmaier, R. (1962), “Czochralski Technique”, in: Compound Semiconductors, Vol. I : Preparation of 111- V Compounds: Willardson, R. K., Goering, H. L. (Eds.). New York: Reinhold, p. 254. Harman, T~ C. (1967), “Properties of Mercury Chalcogenides”, in: Physics and Chemistry of IIVI Compounds: Aven, M., Prener, J. S. (Eds.). Amsterdam: North-Holland, p. 767. Hicks, H. G. B., Greene, P. D. (1971), Proc. 3rd Int. Symp. on GaAs and Related Compounds, Aachen. 1970, Inst. Phys. ConJ Ser. 9. Bristol: Institute of Physics, p. 92. Hirano, R., Kanazawa, T., Nakamura, M. (1992), 4th In!. Conf. on InP and Related Materials. Newport, JYYL. Yiscataway, NJ: IEEE, p. 546. Holmes, D. E., Chen, R. T., Elliott, K. R., Kirkpatrick, C. G. (1982), Appl. Phys. Lett. 40, 46. Hukin, D. A. (1989), in: Proc. 4th In!. Photovoltaic Science and Engineering Cony. Edge Cliff, NSW, Australia: International Radio and Electrical Engineers of Australia, p. 719. Hulme, K. E (1959). J. Electron. Control 6 , 397. Hulme, K. F., Mullin, J. B. (1959), Phil. Mag. 4, 1286. Hulme, K. E, Mullin, J. B. (1962), Solid-State Electron. 5, 211. Hurle, D. T. J. (1961). Solid-State Electron. 3, 37. Hurle. D. T. J. (1977). J. Cryst. Growth 42, 473. Hurle, D. T. J. (1993), J. Cryst. Growth 128, 15. Hurle, D. T. J. (1995), J. Cryst. Growth 147, 239. Hurle, D. T. J.. Jones, 0..Mullin, J. B. (1961), SolidState Electron. 3. 317. Isshiki, M. (1992), “Bulk Growth of Widegap 11-VI Single Crystals”. in: Widegap 11- VI Compounds for Opto-Electronic Applications: Ruda, H. E. (Ed.). London: Chapman and Hall, p. 3. Jacob, G. (1982), J. Cryst. Growth 58, 455. Jacob, G., Duseaux, M., Farges, J. P., Van Den Boom, M. M., Roksnoer, P. J. (1983), J. Cryst. Growth 61, 417. Jordan, A. S., Caruso, R., Von Neida, A. R. (1980), Bell Syst. Tech. J. 59, 593. Liao, P. K., Chen, M. C., Castro, C. A. (1992), in: 10th In!. ConJ on Crystal Growth, Sun Diego, C A 1992. Oral Presentation Abstracts. Thousand Oaks, CA: American Association for Crystal Growth, p. 161. Lorenz, M. R. (1967), “Crystal Growth of 11-VI Compounds”, in: Proc. Int. ConJ on II- VI Semiconducting Compounds, Providence, RI. New York: W. A. Benjamin, p. 215. Maier, H. (1984). in: Landolt-Bornstein: Numerical Data and Functional Relationships in Science and Technology, new series, Vol. 17: Technology of Semiconductors. Berlin: Springer, p. 5. Metz, E. P. A., Miller, R. C., Mazelsky, R. (1962), J. Appl. Phys. 33, 2016. Muller, G., Jacob, H. (1984), in: Landolt-Bornstein: Numerical Data and Functional Relationships in Science and Technology, New Series, Vol. 17: Technology of Semiconductors. Berlin: Springer, p. 12.

Mullin, J. B. (1962), Segregation in InSb, in: Compound Semiconductors, Vol. 1: Preparation of III- V Compounds: Willardson, R.K., Goering, H. L. (Eds.). New York: Reinhold, p. 365. Mullin, J. €3. (1975a), “Crystal Growth from the Melt: I. General“, in: Crystal Growth and Characterization, Proc. ISSCG2 Spring School, Lake Kawaguchi, Japan, 1974: Ueda, R., Mullin, J. B. (Eds.), Amsterdam: North-Holland, p. 61. Mullin, J. B. (1975b), “Crystal Growth from the Melt: 11. Dissociable Compounds”, in: Crystal Growth and Characterization, Proc. ISSCG2 Spring School, Lake Kawaguchi, Japan, 1974: Ueda, R., Mullin, J. B. (Eds.). Amsterdam: North-Holand, p. 75. Mullin, J. B. (1989), “Melt Growth of 111-V Compounds by the Liquid Encapsulation and Horizontal Growth Techniques”, in: 111- V Semiconducting Materials and Devices: Malik, R. J. (Ed.). Amsterdam: Elsevier, Chap. 1, p. 1. Mullin, J. B., Straughan, B. W., Brickell, W. S . (1965), J. Cryst. Growth 26, 782. Mullin, J. B., Heritage, R. J., Holliday, C. H., Straughan, B. W. (1968), J. Cryst. Growth 3/4, 281. Mullin, J. B., MacEwan, W. R., Holliday, C. H., Webb, A. E. V. (1972), J. Cryst. Growth 13/14, 640. Nygren, S. E, Ringel, C. M., Verleur, H. W. (1971), J. Electrochem. SOC.118, 306. Pfann, W. G. (1966), Zone Melting, 2nd ed. New York: Wiley. Piper, W. W., Polich, S. J. (1961), J. Appl. Phys. 32, 1278. Rudolph, P. (1995), Prog. Cryst. Growth Charact. Mater., to be published. Rudolph, P., Umetsu, K., Koh, H. J., Fukada, T. (1994), J. Cryst. Growth 143, 359. Sen, S., Stannard, J. E. (1995), Prog. Cryst. Growth Charact. Mater., to be published. Shockley, W. (1949), Bell Syst. Tech. J. 28, 435. Straws, A. J. (1971), in: Proc. In!. Symp. Cadmium Telluride, Strasbourg, June 1971: Siffert, P., Cornet, A. (Eds.). Strasbourg: Centre de Recherches Nucleaires, p. l l . Swiggard, E. M., Lee, S. H., von Batchelder, EW. (1979), Proc. 7th In!. Symp. on Gallium Arsenide and Related Compounds, St. Louis 1978. Znst. Phys. Conf: Ser. 456. Bristol: Institute of Physics, p. 125. Tada, K., Tatsumi, M., Morioka, M., Araki, T., Kawase, T. (1990), Semiconductors and Semimetals, Vol. 31, Indium Phosphide: Crystal Growth and Characterization: Willardson, R. K., Beer, A. C. (Eds.), New York: Academic, p. 175; see especially pp. 222ff. Teal, G. K. (1958), Transistor Technology, Vol. 1: Bridgers, H. E., Scaff, J. H., Shive, J. N. (Eds.),, New York: Van Nostrand, Chap. 4. Thomas, R. N., Hobgood, H. M., Ravishankar, P. S . , Braggins, T. T. (1990), J. Cryst. Growth 99, 643.

2.9 References

Thomas, R. N., Hobgood, H. M., Ravishankar, P. S., Braggins, T. T. (1993), Prog. Cryst. Growth Charact Mater. 26, 219. Triboulet, R. (1994), Prog. Cryst Growth Charact. Mater. 28, 85. Van Karman, T. (1921), 2. Angew. Math. Mech. 1, 233. Van der Boomgaard, J., Schol, K. (1957), Philips Res. Rep. 12, 127. Volkl, J., Muller, G. (1989), J. Cryst. Growth 97, 136. Welker, H. (1952), 2. Naturforsch. 7a, 744. Welker, H. (1953), Z . Naturforsch. Sa, 248. Willardson, R. K., Goering, H. L. (Eds.) (1962) Compound Semiconductors, Vol. 1: Preparation of III- V Compounds. New York: Reinhold. Williams, D. J., Vere, A. W. (1987), .L Cryst. Growth 83. 341.

General Reading Bardsley, W, Hurle, D. T. J., Mullin, J. B. (Eds.) (1979), Crystal Growth: A Tutorial Approach. Amsterdam: North-Holland. Brice, J. C. (1965), Growth of Crystals from the Melt. Amsterdam: North-Holland.

109

Hurle, D. T. J. (Ed.) (1993, 1994, 1995), Handbook of Crystal Growth: Vol. 1, Fundamentals; Vol. 2, Bulk Crystal Growth; Vol. 3, Thin Films and Epitaxy. Amsterdam: Elsevier Science. Malik, R. J. (Ed.) (1989), III- VSemiconductor Materials and Davices. Amsterdam: Elsevier Science. Includes chapter on “Melt Growth of 111-V Compounds by the Liquid Encapsulation and Horizontal Growth Techniques” by J. B. Mullin, p. 1. Miller, L. S., Mullin, J. B. (Eds.) (1991), Electronic Materials: From Silicon to Organics. New York: Plenum. Pfann, W. G. (1963), Zone Melting. New York: Wiley. Thomas, R. N., Hobgood, H. M., Ravishankar,P. S., Braggins, T. T. (1993), “Meeting Device Needs Through Melt Growth of Large-Diameter Elemental and Compound Semiconductors”. Prog. Cryst. Growth Charact. Mater. 26, 219. Ueda, R., Mullin, J. B. (Eds.) (1975), Crystal Growth and Characterisation. Amsterdam: North-Holland. Willardson, R. K., Goering, H. L. (Eds.) (1962), Compound Semiconductors: Vol. 1 , Preparation of III- V Compounds. New York: Reinhold. Includes a chapter on “Segregation in InSb” by J. B. Mullin, p. 365. Proceedings of the International Conferences on Crystal Growth. 1965, Oxford: Pergamon. 1968, 1971, 1974, 1977, 1980, 1983, 1986, 1989, 1992, Amsterdam: Elsevier.

3 Epitaxial Growth Thomas E Kuech

Department of Chemical Engineering. University of Wisconsin. Madison. WI. U.S.A,

.

Michael A Tischler

Advanced Technology Materials. Inc., Danbury. CT. U.S.A.

List of 3.1 3.2 3.2.1 3.2.2 3.2.3 3.3 3.3.1 3.3.1.1 3.3.1.2 3.3.2 3.4 3.4.1 3.5 3.6 3.6.1 3.6.1.1 3.6.1.2 3.6.1.3 3.6.1.4 3.6.2 3.6.3 3.6.4 3.7 3.8

Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 The Epitaxial Process: General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Surface Thermodynamics and Surface Structure . . . . . . . . . . . . . . . . . . . . . . . 119 124 Surface Transport and Incorporation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Growth Behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Chemical Vapor Deposition: Technology and Issues ..................... 130 132 Reactors: Mass, Fluid, and Thermal Transport . . . . . . . . . . . . . . . . . . . . . . . . Fluid Behavior and Reactor Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 135 Mass and Thermal Transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Gas Phase and Surface Chemistry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Liquid Phase Epitaxy (LPE) Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 LPE Growth Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Molecular Beam Epitaxy (MBE) Technology . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Specific Epitaxial Systems: Materials and Growth Issues . . . . . . . . . . . . . . . . 152 Silicon Chemical Vapor Deposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Silicon Chemical Vapor Deposition: Surface and Reactor Considerations . 152 Silicon Chemical Vapor Deposition: Growth Chemistry . . . . . . . . . . . . . . . . 156 159 Heterojunction Formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Impurity Incorporation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 GaAS MBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Growth of AlGaAs by LPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 InP Metal Organic Vapor Phase Epitaxy (MOVPE) . . . . . . . . . . . . . . . . . . . 170 Acknowledgement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

112

3 Epitaxial Growth

List of Symbols and Abbreviations A C

cis CS d

D DO

DS E G Gform Grnigr

H J k kB

I(

Kn 1 L

m M n N

4 P pi

Q QWap

R S

S t

T Vms

W X

Xi CI

a0

Y %A

,SEI

surface area; aperture area concentration concentration of solute (As) in the solid local concentration of diffusing species diameter of gas molecule; thickness of epitaxial layer diffusivity; gas phase diffusion coefficient diffusion coefficient surface diffusion coefficient energy free energy free energy of formation free energy of migration enthalpy flux rate constant Boltzmann constant equilibrium constant Knudsen number distance a reactor dimension slope of liquidus curve molecular weight number density of gas Avogadro’s number weight fraction of component i pressure partial pressure of component i activation energy heat of vaporization cooling rate; gas constant height of steps entropy time temperature mean stream velocity of gas work distance mole fraction of component i rate constant rate constant pre-exponential surface tension interfacial energy between solids A and B


energy of solid and vapor interface thickness of diffusional boundary layer energy per unit area of terrace ledge energy per unit length energy per kink site angle fraction of available adsorption sites terrace width; mean free path of gas molecule kinematic viscosity of gas kink density 2DEG AFM APCVD BEP CVD DEZ DFB DH FET FWHM GR LPCVD LPE MBE MOMBE MOSFET MOVPE PBN PL RHEED RTP SBH SI STM TBP TEI TLK TLV TMI UHV

two-dimensional electron gas atomic force microscope or micrograph atmospheric pressure chemical vapor deposition beam equivalent pressure chemical vapor deposition diethyl zinc distributed feedback double heterostructure field effect transistor full width at half maximum growth rate low pressure chemical vapor deposition liquid phase epitaxy molecular beam epitaxy metal-organic molecular beam epitaxy metal oxide semiconductor field effect transistor metal-organic vapor phase epitaxy pyrolytic boron nitride photoluminescence reflection high energy electron diffraction rapid thermal processing Schottky barrier height semi-insulating scanning tunneling microscope tertiary butylphosphine triethyl indium terraces, ledges, kinks threshold limit value trimethyl indium ultra-high vacuum

113

114

3 Epitaxial Growth

3.1 Introduction The development of modern semiconductor devices and circuits has required the integration of a large number of different materials. The formation of these devices requires the controlled deposition and processing of several types of materials: metals, semiconductors and insulators. Metals primarily form the interconnections between different semiconductor regions, while insulators serve to electrically isolate the metal wires from the semiconductor. The deposition of SiO, and other materials may also serve to form the active region of the device structure, as in the case of the Si-based metal oxide semiconductor field effect transistor (MOSFET). Materials deposition and surface modification of the semiconductors are required in order to form the individual elements in devices and circuits. Thus, resistors, pn junctions, transistors and a wide variety of other devices are formed by an assortment of materials processes. These processes, encompassing metals, semiconductors, and insulators, are produced in thin layer form on the surface of the substrate wafer or through modification of the near surface region of the wafer. A typical cross-section of a Si device structure is shown in Fig. 3-1. Many different types of processing steps and materials modification techniques have to be applied to develop such a structure and finally pro-

duce a working device. The formation of conducting regions in the semiconductor wafer, for example, in silicon, has traditionally been performed through the invention and application of processes which can modify the near surface regions of the wafer. The carrier concentration and conductivity type are modified through the processes of ion-implantation and solidstate diffusion. Silicon dioxide is grown through the thermal oxidation of Si or it is deposited, and serves as a local insulator. Deposition techniques, such as sputtering, thermal evaporation and chemical vapor deposition, have all been used to form semiconducting, insulating and metal or metallic conductive regions on the wafer surface. These important processes are discussed in other chapters within this volume. The processing and growth or deposition techniques will determine the final device structure, and hence device characteristics, as discussed in this chapter. The device characteristics depend crucially on the chemical, physical and structural properties of these deposited or fabricated layers, as well as on the interfaces between them. The local properties of these interfaces between dissimilar materials can be complex. The presence of a high concentration of structural defects or chemical impurities at the junction between n- and p-type semiconducting regions can drastically alter the electrical properties of a pn

Figure 3-1. The cross-section of a typical Si-based electronic structure. The device consists of many regions which have a difference in electrical properties. The technology used to generate these regions is indicated in this figure.

3.1 Introduction

junction. Similarly, structural imperfections or impurities at the interface between Si and SiO, can destroy the important passivation properties of the interface as well as degrading the electrical properties of the Si-SiOz junction in a MOSFET. Lastly, the interface between a metal and a semiconductor can yield rectifying or ohmic behavior depending on the electronic structure of the two materials and the physical characteristics of their interface. A major difficulty with many of these interfaces is the stochastic nature of the defects which control the interfacial properties. The rectifying Schottky barrier formed at most metal-semiconductor interfaces can, for example, be controlled only to & 10 meV out of a typical barrier height of 800 meV. This variation in the Schottky barrier height (SBH) of 5 1-2% is due to minor differences in the interfacial structure between the two structurally different materials and the level and distribution of chemical impurities at these interfaces. The growth or deposition of polycrystalline layers on an existing single crystal substrate always leads to micro-structural variations along the interface. As the lateral device dimensions are reduced through improvements in the primary patterning technique, photolithography, these lateral property variations are averaged over smaller areas. Device characteristics and their thermal stability will thus exhibit larger variations as device dimensions shrink. In circuit applications, such variability between adjacent devices could render the circuit inoperable. The trend toward smaller lateral dimensions has been accompanied by a similar decrease in the vertical dimension of device structures. The existing processing techniques have been refined and pushed to produce smaller and thinner structures. Many of the techniques which rely on the

115

modification of the near surface region of a wafer, such as ion implantation and diffusion, are reaching their limits in producing thinner and thinner regions of controlled properties. Both thermal diffusion and ion-implantation are limited by the stochastic nature of the process itself. The impurity distribution in the near surface region of the wafer, produced by both of these processes, typically results in a Gaussian impurity depth profile reflecting the underlying random nature of atomic motion of the process. In addition, these techniques require elevated temperatures for impurity activation, as in the case of ion implantation and impurity redistribution. These thermal treatments can result in non-equilibrium concentrations of native defects which can affect subsequent processing steps and materials properties. The development of smaller, thinner and higher performance devices will require tighter constraints on the thermal and physical extremes during the fabrication process. Each generation of devices has, therefore, spurred innovation in new processing techniques. The resulting processing trends for semiconductor device fabrication are towards low thermal budget (both temperature and time) processing and deposition techniques. Low thermal budget processing offers many advantages in these applications, resulting in a smaller concentration of defects in the material as well as a reduction in the extent of impurity redistribution within the device structure. While control of impurities is important in the development of electronic devices, the physical structure, and in particular, the interfaces between materials are becoming increasingly important as device dimensions shrink. Control over the structural details of the crucial interfaces has been more difficult to achieve over a broad spectrum of processing conditions.

116

3 Epitaxial Growth

Again the trends have been to lower thermal budget processes, where interdiffusion of and reaction between materials is minimized. In this chapter, we will discuss the nature and application of a set of processing techniques collectively called epitaxial growth techniques. In particular, these techniques have been applied to the formation of thin layer semiconductor structures which comprise the active device regions. In most cases. the semiconductor will be deposited, or grown, in a crystalline form. Under special growth conditions, the growing layer can assume or replicate the physical structure of the underlying substrate. This replication of the crystalline arrangement of the substrate is known as epitaxy. Epitaxial growth leads to a structurally perfect film in many cases and is critically important in the formation of most modern device structures. There are many deposition techniques which may be used for semiconductor epitaxial growth. The choice of the specific technique is dependent on several issues. The structure of the growing film, the electrical properties and the interface between the deposited layer and the underlying materials are the principal considerations. The approach taken to control these depends on the specific device application. Amorphous films also have applications in device fabrication and can also be produced by many of the growth techniques described in this chapter. The deposited atoms in the epitaxial growth process arrange themselves on the growing surface, bonding to the underlying atoms of the substrate. The atomic arrangement of the substrate atoms determines the subsequent arrangement of atoms in the growing film, the resulting film being a direct continuation of the atomic structure of the single crystal sub-

strate. In principle, since the film is replicating the substrate, an epitaxial film could be as structurally perfect and free from defects as the substrate itself. Since the type of the deposited atoms can be varied during the deposition process, the composition of the growing film can be controlled in the growth direction, during the deposition. Many deposition techniques can now produce multi-layered epitaxial structures in which the individual layers are less than a nanometer thick and the interfaces between layers are essentially atomically abrupt. The formation of such highly perfect interfaces requires the use of low-temperature epitaxial growth processes. The most widely encountered epitaxial growth process is the formation of Si layers on an existing Si wafer or substrate. This controlled growth of a material on a substrate of the same overall chemical composition, as in, for example, the growth of Si on Si, is referred to as homoepitaxial growth. The homoepitaxial deposition of Si on the Si substrate is often used to form very thin layers of Si in which the electrical properties of the growing layer can differ substantially from these underlying layers. The controlled addition of electrically active impurities, or dopants, during epitaxial growth then allows for the formation of electrical as well as compositional interfaces. For example, a pn junction is formed by the addition of first p-type and then n-type impurities to the growing layer. This transition from p-to-n type material can often occur over only a few atomic layers. Just as the doping of the film can be altered over a few atomic layers, the composition of the film can be changed over similar dimensions. The process of growing materials of different composition, as in the alloy Si,Ge, - x on Si, is referred to as heteroepitaxial growth. The growth of Si,Ge, - x on

3.1 Introduction

117

Table 3-1. Examples of CVD reactants used in the epitaxial growth of semiconductors. Semiconductor

Reactants

Pressure regime

General term for this form of CVD

Silicon

SiCl,H,, SiC1, SiH,, Si,H,

APCVD LPCVD and UHV-CVD

Germanium

GeH,

Sic GaAs

SiH, and C,H, Ga and AsC1, (CH,),Ga and ASH,

near atmospheric CVD near atmospheric CVD and LPCVD near atmospheric CVD and LPCVD near atmospheric CVD near atmospheric CVD near atmospheric CVD

APCVD, LPCVD, and UHV-CVD

InP A1,Ga -,As

near atmospheric CVD near atmospheric CVD

APCVD VPE MOVPE, MOCVD, OMVPE, or OMCVD MOVPE, etc. MOVPE, etc.

Hg,Cdl - xTe

near atmospheric CVD

MOVPE, etc.

near atmospheric CVD

MOVPE, etc.

Si substrates allows for a change in the electronic structure of the film. Such changes in local electronic structure form the basis of many of the new electronic devices. The heteroepitaxial growth of compound semiconductors, such as GaAs/ Al,Ga, -,As and InP/In,Ga, -,As,,P, -,,, is one of the most developed heteroepitaxial growth techniques. Quantum well lasers, high performance heterojunction transistors, and multilayer photodetectors are all products based on heteroepitaxial growth. There are several primary techniques used in the formation of epitaxial layers. The choice of the specific growth technique depends strongly on the required materials and the desired material structure. Physical deposition has been used for the growth of many films. In particular, molecular beam epitaxy or MBE has been used with great success in the fabrication of very thin layer device structures. In this technique, a heated substrate is exposed to

a flux of growth nutrients, usually elemental sources, within an ultra-high vacuum (UHV) environment. Materials growth from the gas phase at higher pressures is far more common and is referred to as chemical vapor deposition, or CVD. CVD techniques utilize high-vapor-pressure compounds of the elements comprising the film. A variety of CVD techniques are summarized in Table 3-1. The volatile source compounds, such as SiH, in the growth of Si, are transported to the growth front, at which point they react, and are incorporated into the growing layer. In all cases, the deposition of the film and the formation of the epitaxial structure proceeds through a series of elementary steps or processes: i) transport of the growth nutrients to the growth front, ii) their decomposition at the growth surface, iii) surface migration of the deposited species and iv) the subsequent bonding into the growth front. The slowest of these elementary processes becomes the rate-limiting step in de-

118

3 Epitaxial Growth

surface must also be very smooth in order to allow photolithographic patterning. Surface defects will reduce the usable area of the deposited film and therefore decrease the yield of devices and circuits generated from the material. There are also defects within the film itself which must be controlled. Defects in the film, in the form of missing atoms (vacancies), rows of atoms (dislocations), or extra or missing planes of atoms (stacking faults), schematically shown Fig. 3-2, must be controlled or eliminated. These structural defects can be electrically active and interact with the electronic or optical devices formed from the epitaxial layers.

termining the growth rate of the film. This chapter will deal with these elementary processes as they apply to CVD-based epitaxial growth and how they affect the formation of the epitaxial structure in the deposited layer. There are many issues associated with CVD of thin films. Since we are limiting our scope in this chapter to epitaxial films, the structure of the deposited layer or layers will have a definite relationship to the substrate. While this term describes the overall physical nature of the film, the details of the physical structure or perfection of the epitaxial layers is also important. In order to be useful. the deposited film must also possess other properties which bear directly on their utility within the overall device formation process. The deposited film must be uniform in thickness, composition, chemical, electrical and, perhaps, optical properties. Variations in the film properties correspond to changes in the resulting device properties over the wafer and from wafer-to-wafer. In general, the

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The growth of an epitaxial film takes place on a crystal surface. This surface could consist of the same material, as in the epitaxial growth of Si on a Si substrate,

-T

* * .

t t

3.2 The Epitaxial Process: General Features

.

e

I

,

*

.

.

P

*--y--

T-

edge or misfit dislocation

E A

C E A C

E A

--

B

-

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C -

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-

C

-

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E A

intrinsic stacking fault

B

A

A

c

' B

B

~

A

A

B

A

C

- - c

a

L -

-

c -

a

-

A

c

E

-

A .~

C

4

-

-

A

__ --

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extrinsic stacking fault

6 A

Figure 3-2. 'There are many defects which can typically form in thin film structures. ranging from missing atoms (vacancies), missing rows of atoms (dislocations) to extra or missing partial planes of atoms (stacking faults) T is the shear stress and S and P define the plane of the dislocation.


or on a surface of a different material, such as Al,Ga, -,As on GaAs. In all cases, the nature of the surface composition, chemistry and structure will play a major role in determining the essential features of the epitaxial growth process. The growth rate, electronic properties, and film structure are determined by the chemical and physical reactions occurring at this growth front. This section will focus on the physical nature of the growth surface and elementary processes occurring there. These processes are important for all forms of epitaxial growth: physical deposition, as in MBE, CVD and liquid phase epitaxy (LPE). The thermodynamic description of the growth surface is the starting point for this discussion. A growing surface, by definition, is not at equilibrium. The rate of materials deposition is very slow, under many growth conditions, compared to those transport and chemical reactions which must take place in order to approach and reach equilibrium. The actual growth of materials can often be assumed to be a small perturbation to the equilibrium structure and composition of the growth front. There are, of course, many occasions when these chemical and physical reactions are very slow and non-equilibrium structures appear on the surface and in the growing film. In any event, a thermodynamic description of the surface serves as a good starting place for the discussion of epitaxial growth processes.

3.2.1 Surface Thermodynamics and Surface Structure Thermodynamics is typically used to describe the relationship between bulk phases. This description, in general, does not recognize that the bulk phases have surfaces and that these surfaces can and do have properties which are different from the bulk

119

phases. The neglect of the surface in thermodynamic calculations is well justified in most cases. Most solid materials have an atomic density of about lo2’ atoms/cm3. Consider a one cubic centimeter block of metal, the number of atoms on the surface of such a cube can be estimated from this bulk atomic density to be about atoms or lo-’ of the total number. Since for typical materials this is a very small fraction, the surface can be ignored in the calculations. The deposition of a thin epitaxial film on an existing substrate, however, is quite a different case. A thin film of 0.1 pm in thickness has an areal density of about lo1’ atoms/cm2. The atoms making up the interface or top surface then comprise 1% of the total number of atoms. In many cases, this 1% of the total number of atoms could possibly be neglected in our considerations. However, in the early stages of growth all the atoms are on or near a surface. The surface energetics can then dominate the film growth over the bulk phase effects. In addition, for structures in which interfaces play a major role, such as MOSFET devices, the interface is composed of the near surface regions of two different materials. The surface regions of these devices often dominate their physical and electronic properties. The atoms in a surface layer are in a completely different environment than the atoms in the bulk of the solid. They have fewer nearest neighbors, the distribution of neighbors is anisotropic and the properties on an atomic scale are different (Le., chemical bonding, positions, and so on). Since these detailed atomistic characteristics determine the thermodynamics of the macroscopic system, it is useful to talk about the surface as a distinct phase from the bulk. Internal surfaces or interfaces can be similarly considered as a distinct phase since the composition changes repid-

120

3 Epitaxial Growth

ly over a few atomic distances. The thermodynamic properties of the system can be considered to be the sum of the bulk and surface contributions, or in the latter case, an interfacial contribution. The most familiar of the characteristic energies associated with a surface is the surface tension. Surface tension, y, is defined as the reversible work involved in the formation of a unit area of new surface at a constant temperature, volume and number of atoms (Adamson, 1990): y- -

as A + O ,

posed of the bulk contributions and the surface contribution (Adamson, 1990): G=G~+G~

(3-2)

The surface contribution GS is defined in the same terms as the bulk free energy G B

G i = H i + TSi

(3-3)

where H iand S i are the enthalpy and entropy of the particular phase and T is the temperature. The surface tension can be expressed as

(3-1)

(3-4)

where d W is the amount of work associated with the increment in area dA. In order to increase the area of the interface or surface, work must be done on the system, hence the sign of this energy term. The work done in forming a new surface is associated with the breaking of bonds, increasing or decreasing the distance between neighbors, and/or rearranging atoms. While the concept of surface tension is usually associated with a liquid, it has a similar physical definition in the case of a solid. The surface tension is used to describe both the work done in creating a new surface, such as cleaving a crystal or nucleating a new solid phase, or increasing the surface area, as in the formation of new internal surfaces or a reconstruction or rearrangement of the surface atoms. A grain boundary is an example of an internal boundary which may be formed by cold working of a material. The surface tension is related to the more familiar energies encountered in thermodynamics. The Helmholtz free energy, entropy, enthalpy and Gibbs free energy can all generally be defined in terms of the surface tension. For example, the total Gibbs free energy of a system can be com-

The other relationships of bulk thermodynamics can be used in the definition of other surface-related quantities. In particular, the surface entropy can be given as

(3-5) or (3-6) The surface energy, E', and enthalpy, H S , are often very close in value, ESrH S , allowing the surface energy to be expressed as

E ~ Z H ~ = G ~ + T S ~

(3-7)

or A.!

(3-8) This concept of surface tension and surface energy of a solid will be useful in determining the underlying causes for surface rearrangement and the nucleation and growth behavior in epitaxial growth. The surface energy is almost always positive, indicating that surfaces are not energetically favored entities. A solid is al-

121

3 . 2 The Epitaxial Process: General Features

ways reluctant to form a new surface since it costs energy. Solids at high temperatures in equilibrium with their vapor or liquid phase will form a surface shape which minimizes this energy expenditure. Solids will therefore minimize their surface energy by altering their shape. The surface energy will be a function, in a crystalline solid, of the orientation of the solid. The surface energy can be estimated by looking at the number of broken bonds which had to be created when the surface was formed. The crystallographic planes of a crystal can and do possess different numbers of bonds. The surfaces with greater number of bonds broken in the formation of the surface will generally result in the higher surface energy. Such high energy surfaces are energetically unfavorable to form and expand. A crystallite at thermodynamic equilibrium will develop well-defined crystallographic facets or planar surface features. The wellknown shape of naturally occurring crystals often reflect these thermodynamic influences. The tendency to form facets on the surfaces is not only manifested at a macroscopic scale but also at the microscopic or atomic scale. The more stable crystallographic faces will be formed at the expense of surfaces with higher free energy. For example, thermal faceting will take place in the case of the (100) surface of Ag at high temperatures. Near the melting point of Ag, the (100) crystal surface will decompose into microscopic facets with a (1 11) orientatios. Most epitaxial growth takes place on a single crystal substrate which has a well defined, overall orientation. Most wafers are oriented to a specific low-index crystallographic direction, e.g., (100) or (11l), within a certain accuracy. If a wafer has a surface which is exactly a crystallographic plane, it is referred to as a singular surface. The wafer surface can have additional

structure aside from the above mentioned faceting. The detailed surface structure is characterized by three separate but related features: terraces, kinks and ledges. Often, the wafer will be specified to have a polished (100) surface which is intentionally misoriented at an angle towards another major crystal direction, as schematically shown in Fig. 3-3. Such surfaces are often referred to as vicinal surfaces. This intentional or unintentional off-orientation of the wafer increases the structure on the wafer surface. The terraces, ledges and kinks (TLK) on a such a surface are schematically shown in Fig. 3-3. The TLK description can be used to attempt to calculate the surface energy of a crystal by separately considering the contributions to the energies associated with the particular defects which make up the surface. In this context, the surface can be thought of as being made up of singular or atomically flat surfaces (terraces), plus steps (ledges) from one terrace to another, and kinks in those steps. This view extends the bond breaking model used in describing the surface energy. The formation of ledges and kinks are a consequence of entropic effects at temperatures greater than

Kink Site

Terrace

,

/ ;

i

Figure3-3. The surface of a substrate which is not perfectly oriented to coincide with an exact crystallographic plane consists of surface structures such as ledges, terraces and kinks in the terrace edges. These basis surface structures can influence the growth of the film.

122

3 Epitaxial Growth

a temperature of absolute zero. At 0 K, a wafer surface which has an orientation close to a major crystal axis, will consist only of terraces and ledges as shown in Fig. 3-4a. A surface which has a general orientation, i.e., not a singular or vicinal surface, will also have ledges consisting of sections interrupted by a jog or kink, i.e., a step in the line as shown in Fig. 3-4b. A vicinal surface is the most commonly used surface in epitaxial growth. The surface energy of a vicinal surface can be described through the aid of Fig. 3-5 which illustrates a wafer surface of a (010) orientation miscut by an angle 8 towards the [loo] direction. We will assume that 6 is small, i.e. 8 1 4 ” . The surface, shown in Fig. 3-5, will consist of monatomic steps of height s, with a density tan (I 8 /)is. The terrace will , have an average width i.where (3-9) At 0 K, the surface energy can be written as &i1)

E S ( 8 ) = E S = ( 0 )cos(@+ -sin(@

(3-10)

S

terrace

\a

b8

terrace

Figure 3-4. a ) At both 0 K and thermodynamic equilibrium, a substrate miscut towards a principal crystallographic plane will have only terraces terminated in ledges. b) A substrate of arbitrary miscut will possess kinks in addition to terraces and ledges.

J

.~

Figure 3-5. A simple semiconductor surface will consist of terraces separated by monatomic steps (s). Under certain conditions, multi-step ledges are formed.

where E S ( 0 )is the energy per unit area of a singular terrace, d’) is the ledge energy per unit length of a ledge and E’(@ is the energy of the actual vicinal surface. It should be noted that the total terrace area is less than the total surface area, cos = (terrace area)/(surface area), where the ‘total surface area’ would be the area of a plane at the vicinal angle 8. As 8 increases, the amount of singular surface, relative to the total surface area, decreases. The last term in the expression is the ledge energy contribution to the surface energy. This is simply the ledge energy per unit length, ~(l), times the ledge density,

(e)

The inclusion of kinks into the calculation of the surface energy involves the addition of a term consisting of the energy per kink site, d2),and the kink density, Q. The kink density will depend, at 0 K, on the specific orientation of the surface. The surface energy then becomes (3-12) &(1) E S ( 6 ) = E S(0) cos(8)+ - sin(@+@E(’) S


Based on the number of possible broken bonds, an atom on a terrace will have the least number of broken bonds and will have the higher number of bonds to adjacent surface atoms. Atoms on ledges will have a higher number of broken bonds than the terrace while the kink sites have the fewest bonds to the surface. The surface energy of a particular feature will increase with the number of broken bonds. The kink sites will have the highest per atom energy followed by the ledge sites and finally the terrace sites. The surface structure, at equilibrium, will be determined by the minimum of this surface energy, at 0 K. It should be noted that the number of kinks, ledges and the terrace width are not independent variables but are constrained by the geometry of the surface, substrate orientation and vicinality. At higher temperatures, such as those used in the growth or deposition of epitaxial materials, the surface will have a more complex structure since entropy can play a role. As indicated in Eq. (3-3), the surface free energy contains both the surface energy (enthalpy) and the surface entropy. The increase in temperature allows the entropy term to gain in significance. Part of the surface energy will be associated with the configuration of atoms on the surface. As the temperature is increased, there is a driving force to increase the amount of disorder on the surface through the generation of atom vacancies, surface ledges and kinks. The addition of the these high energy structures increases surface energy but this increase is offset by the increase in the surface entropy. These energy considerations can lead to complicated surface structures. Such surface structures can be seen using surface sensitive techniques, such as the scanning tunneling microscope (STM) or electron diffraction. A STM micrograph of a Si surface is shown in Fig. 3-6.

123

Figure 3-6. A scanning tunneling micrograph (STM) of a clean (100) Si surface reveals the TLK structure characteristics of most surfaces.

The presence of such surface structures are readily seen in this picture, the flat terrace being bounded by alternating rough and smoother ledges. The alternating structure is attributed to the last aspect of surface structure important to the epitaxial growth of materials, surface reconstruction. So far, we have discussed the surface structure in terms of features residing on the surface of a truncated crystal. A truncated crystal is conceptualized as a surface formed by cleaving the crystal along a specific crystallographic plane. The bonds broken in this process are left ‘dangling’ from the surface. These dangling bonds are very energetic sites on the surface, readily forming new bonds with adatoms. The truncated crystal does provide an idealized view of the surface structure on an atomic scale. The very energetic dangling bonds left on the surface, in this construction, would however prefer to be part of a covalent bond if possible. This covalent bond could be formed through an interaction within an adsorbed species. In

124

3 EDitaxial Growth

the absence of adsorbed reactive species, the dangling bonds on the surface will often reform, bonding to adjacent atoms on the surface. This reformation process results in a new surface arrangement of atoms. This rearrangement away from the truncated crystal arrangement is referred to as surface reconstruction. Surface reconstruction on a semiconductor surface possesses both a short range and long range structure. The nature of the structure will depend on the temperature and surface chemical composition, as in the case of compound semiconductors. The reconstruction of a surface allows the surface energy to be decreased through the reformation of the broken bonds. Since the bonds are not at the angles and length found in the bulk, the energy expended in the creation of the surface is not fully recovered through the reconstruction process and hence the energy of the surface is still positive. The reconstructed surface of semiconductors will possess an altered chemical reactivity and therefore affects the process of epitaxial growth. The best studied surfaces, which are also used in epitaxial growth, are the (100) surfaces of Si and GaAs. In both of these cases the atomic level structure is dominated by the pairing of adjacent surface atoms, forming surface dimers. The dimers themselves can be arranged in a variety of configurations. The surface reconstruction of an epitaxial surface is most readily examined by electron diffraction techniques that can be easily incorporated into high vacuum growth apparatus, and by STM or AFM. The electron diffraction techniques average the surface structure over large dimensions while the STM images the atomic arrangement over a relatively small area. Both techniques can yield information on the details of the surface structure. The Si (100) surface is often characterized by

Figure 3-7. An atomic resolution image of the Si surface reveals that the terrace is composed of Si-dimer rows which alter their orientation with each successive layer.

rows of Si dimers running along the surface, as shown schematically in Fig. 3-7. The diamond structure of Si leads to an alteration of the Si dimer direction on successive planes of the Si crystal. This leads to dimer rows which rotate by 90" on each successive atom plane. This geometrical constraint has many implications for the transport of atoms on the surface and the attachment of new atoms to the growing surface. As seen in the STM micrograph of Fig. 3-7, the dimer rows end at step or ledge edges. If the ledge is parallel to the dimer row direction, a smooth ledge edge results. Ledges consisting of ends of dimer rows tend to be jagged and rough. The structure of these ledge edges is related to the detailed transport phenomena on the surface.

3.2.2 Surface Transport and Incorporation Film growth is the result of interaction between surface transport, structure and chemistry. The adsorbed species on the


growth front is often mobile and moves in order to find a favorable site for further decomposition, if necessary, and incorporation. The favorable sites on the surface are often the ledge edges and kinks described above which present a more reactive site. The initial deposition of an adatomcontaining species is typically thought of as occurring randomly over the surface. This picture is most correct for the physical deposition techniques which take place under ultra-high vacuum (UHV) conditions using elemental sources. The arrival of material to the growth front during CVD is quite different. In this case, adatom-bearing molecules can interact many times with the surface before final attachment to the surface. During these many interactions, the molecules can sample many different types of surface sites, Le., kinks, vacancies, ledge edges, and so on. The final site of incorporation will have the appropriate geometry and chemistry allowing for the chemisorption of material on the surface. The reconstruction and the larger scale surface features therefore play a central role at the atomistic level in the epitaxial growth process. The growth species, once adsorbed on the surface, can often move over the surface through the process of thermal surface diffusion. Surface diffusion will occur at any temperature above absolute zero. Since surface diffusion is a kinetic process, it will be extremely sluggish at very low temperatures and increase exponentially with temperature. Like any other diffusional processes, surface diffusion follows Fick’s laws. The flux of a species across the surface will be proportional to its gradient in chemical potential.or, for dilute systems, its concentration grradient (Borg and Dienes, 1990) (3-1 3)

125

where J is the flux across a surface, D, is the surface diffusion coefficient, and Cs is the local concentration of the diffusing species. The diffusion coefficient is determined by the same factor used in describing an atomistic picture of bulk diffusion. Temperature is the dominant factor in the diffusion Coefficient which depends on an activation energy, Q: D, = D o

.L-Q/(~B~)

(3-14)

If the activation energy is low, large diffusion rates can be observed. In general, activation energies for surface diffusion are smaller than that of the bulk. If diffusion entails the local breaking of bonds, a surface bonded atom most likely has fewer bonds to the substrate than a bulk atom has to neighboring bulk atoms. Hence, surface diffusion processes are typically more rapid. The diffusion coefficient also depends on a variety of factors which can influence both the pre-exponential term, D o , and the activation energy. The activation energy is comprised of the energy required for the atom to migrate from one low energy site, breaking its local bonds, to another low energy site. This contribution is referred to as the free energy of migration, Gmigr.The second contribution is related to the density of available sites for the atom to move into during the diffusion process. In many cases, the number of available sites is a strong function of temperature. The number of surface vacancies, ledges and kinks can all be a function of temperature through an activated process, characterized by an energy of formation, Gform.The concentration of vacancies, for example, typically follows an activated behavior. The activation energy is then the sum of both contributions, Q=Gmigr Gform.The pre-exponential term of the diffusion coefficient contains the frequency of jump attempts and geometrical configu-

+

126

3 Epitaxial Growth

ration (Borg and Dienes, 1990; Skewmon, 1989). The diffusion coefficient, along with the surface and interfacial energies, will determine the structure of the growing surface on an atomic and microscopic level.

3.2.3 Growth Behaviors The growth behavior in epitaxial systems is determined by the surface transport and the surface energetics of the materials system of interest. The above discussion focused on the surface transport required once the atoms are deposited. The atomic level motion and the energetics of the growth front will dictate the physical arrangement of these deposited atoms. The simple models of epitaxial growth predict different growth structures, derived from the chemical nature of the deposited atom, as well as the substrate serving as the template for the atomic arrangement of these species. In this case, there are generally two classes of epitaxial behavior based on whether the deposited atoms build a layer of the same structure and chemical composition as the substrate (homoepitaxial growth) or the growing layer is different in chemical composition, and perhaps physical structure, from the substrate (heteroepitaxial growth). Since epitaxial growth of a semiconductor requires that the deposited atoms assume an orientation which is directly related to the underlying substrate, there will, in both cases, be a known geometric relationship between the deposited layer and the underlying crystalline substrate. There are two dominant forms of growth behavior seen in homoepitaxial growth. These growth modes are related to the transport and incorporation kinetics of the adsorbed atom on the growth surface. Since there is no difference in the physical and chemical properties during homoepi-

taxy, this growth can proceed in a wellcontrolled manner. The growth or addition of atoms to the surface can proceed in two different growth modes or behavior: step-flow growth or layer-by-layer growth. These two-dimensional growth modes are often collectively referred to as Frank-Van der Merwe growth. (Three-dimensional growth can also occur, which results in a rough, uncontrolled interface.) In the stepflow mode, atoms deposited on the growth front diffuse to naturally occurring step edges. Since these step edges and step kinks, shown in Fig. 3-3, provide several atoms for the migrating atom to attach to, diffusing atoms will naturally bind there and be incorporated into the growing film. At high growth temperatures, the atoms have sufficient mobility to migrate across the surface before encountering other adatoms. The epitaxial growth then proceeds with the step-flowing across the growth front, leaving a very smooth atomically flat surface with a terrace-like structure. The characteristic terrace structure of step-flow growth, interrupted by monatomic steps, is seen in Fig. 3-7 for Si atoms on a Si surface. A similar terrace structure is found on GaAs during epitaxial growth by chemical vapor deposition as shown in Fig. 3-8 (Nayak and Kuech). This figure was obtained using an atomic force microscope. This particular epitaxial layer was grown at a high temperature, 650 "C, and a modest growth rate of 0.05 pm/min. At this growth rate, there is about one monolayer being grown every second. In this case, the steps are spaced about 0.1 pm apart. The miscut of this GaAs surface is 2" towards the (1 10) direction. This vicinal surface should have a terrace width of x7 nm if the steps are monatomic in height. The large terrace width indicates that the steps observed in Fig. 3-8 consist of more than a


Figure 3-8. A GaAs growth surface, formed by metalorganic vapor phase epitaxy (MOVPE), is also composed of the TLK structure. The GaAs surface presented here in an atomic force micrograph (AFM) has multi-atomic steps which are 3 to 4 atoms in height (Nayak and Kuech).

single atomic step. This phenomenon is referred to as step-bunching and is often seen in many epitaxial systems. The origin of the step-bunching phenomenon is complex and can be affected by the detailed chemistry of the attachment of atoms to the step edge, the diffusional process on the surface and any impurities on the growth surface. In step-flow growth, the transport of the atoms across the surface is rapid compared to the rate at which adsorbed adatoms would meet, bond together and nucleate a new layer of the growth surface. Since all the atoms are reaching a step, an estimate of the lower limit on the diffusion coefficient on the surface from the terrace spacing, A, can be made through (3-15) where Ds is the surface diffusion coefficient, t is the time for one monolayer growth, and

127

i / 2 is the average distance an atomic would have to move on the surface before reaching a step edge. For the GaAs image shown in Fig. 3-8, this simple formula leads m’js. to a value of about D s x 6 x The self-diffusion coefficient for Ga self-diffusion in GaAs at similar temperatures is much lower, values of Dbulk=IO-’’ m’/s being reported. Such a large difference between the surface and bulk diffusion coefficients is typical of values found in the semiconductor materials systems and reflects the lower number of bonds and the higher number of diffusion sites available to the adsorbed atoms on a surface. The step-flow growth described above does not always occur under the epitaxial growth conditions encountered in many growth techniques. The step-flow mode of growth only occurs when the diffusing atoms have sufficient time and mobility to reach a step edge and be incorporated into the crystal before encountering a sufficient number of other adatoms that can lead to the nucleation of a new atomic layer on an existing terrace. Both a high flux of atoms to the growth front and a low growth temperature, leading to a slow surface diffusiion of adatoms across the growing crystal, can lead to the shift from a step-flow growth behavior to the other dominant growth behavior referred to as layer-bylayer growth. In layer-by-layer growth, adatoms will encounter other adatoms on the growth front. Some of these atoms will bind together and result in the formation of a new layer of the crystal. The surface structure present in layer-by-layer growth can often have growth occurring over several layers at once as depicted in Fig. 3-9c, b. This multilayer growth can lead to a rough surface with many atomic levels. This rough growth can become part of the internal structure of the epitaxial materials. Homoepitaxial growth is often

128

3 Epitaxial Growth

Figure 3-9. There are three principal growth modes commonly identified in thin film formation: a) Frankvan der Merwe or layer-by-layer growth, b) StranskiKrastanov growth (finite layer plus island growth) and c) Volmer-Weber or island growth.

used to create very sharp transitions in doping and hence electrical characteristics within the material. A smooth growth surface results in very sharp and planar internal interfaces. The use of conditions which result in a layer-by-layer growth mode will result, however, in a ragged transition region between two carrier types. Most epitaxial growth therefore is performed under growth conditions which yield step-flow growth behavior. The growth of a smooth internal interface becomes a more important issue when both the chemical composition and electrical characteristics change at the growth front as in the more complicated and yet more interesting case of heteroepitaxial growth. In this case, the deposited atoms

are different in chemical composition from the substrate. The best known heteroepitaxial semiconductor systems are Al,Ga, -,As grown on GaAs and SixGe,-x on Si. Heteroepitaxial growth has several distinct advantages over homoepitaxy as well as several complicating features. The major advantage is the use of bandgap engineering - the construction of layers with different bandgaps to achieve specific optical or electronic properties. There are several considerations which complicate the development of a heteroepitaxial growth technique. The primary considerations are the thermal expansion coefficients and lattice parameters of the two materials and the strength of the chemical bonding across the heterointerface. These three issues are not independent variables but they all contribute to the formation of the thin film structures. The chemical bonding between the growing overlayer and the underlying substrate can determine the growth behavior leading to large scale morphological features. Three fundamental growth behaviors have been identified in heteroepitaxy associated with initial nucleation and growth of the film. They are characterized by the surface energies associated with the interfaces between the epitaxial materials and the substrate. These three modes, Frank-van der Merwe, Stranski-Krastanov, and VolmerWeber growth, can be observed in several growth systems. Frank-van der Merwe growth is the single-layer growth mode discussed in reference to homoepitaxial growth. In terms of surface energies, the heteroepitaxial layer is considered to ‘wet’ the substrate leading to good uniform surface coverage. The formation of the heterointerface results in the destruction of the solid-vapor interfaces which would have been present had the materials chosen to not interact. A simple criterion for the ‘wet-


ting’ of the substrate is then YsA/sB

5 YsA/V + YsA/V

(3-16)

where is the interfacial energy between solid A and solid B and ySiiv is the surface energy of the solid vapor interface. The two solid-vapor interfaces were destroyed in the formation of the heterointerface. The formation of the interface is favored over the two separate interfaces. This type of behavior is found in systems which are chemically similar, e.g., GaAsAl,Ga, -,As, with similar lattice parameters. The ‘non-wetting’ of two materials hinders the formation of an initially single-layer growth mode. The epitaxial material does not bond to the substrate surface due to a difference in crystal structure, chemical reactivity or a very large difference in lattice parameter. Energetically, the inequality given in Eq. (3-16) does not hold and the two materials would prefer to form their own solid-vapor interfaces in preference to the solid-solid heterointerface: YsA/sS

’

YSA/V

+

YSA/V

(3-17)

The resulting initial growth behavior is a Volmer-Weber growth mode in which islands of the heteroepitaxial materials form on the surface of the substrate as shown schematically in Fig. 3-9. The material develops large growth islands whose density and shape are determined by the supersaturation of the growth ambient and the surface energetics of the growing islands. There are intermediate cases between these two growth mode extremes. The last major growth mode develops as a result of the interplay between the mechanical stresses which may develop in the thin film and the forces promoting adhesion between the epitaxial layer and the substrate. Lattice-matched heteroepitaxial semiconductor growth can proceed in a manner

129

quite similar to the homoepitaxial case, as described above, exhibiting a Frank-van der Merwe growth mode. Layer-by-layer and step-flow growth is observed in many systems in which the chemical bonding and lattice parameters are similar between the two materials. However there are many heteroepitaxial systems which have different bond strengths and lattice parameters with respect to the substrate. If the interfacial energy of the epitaxial layer and substrate favors a strong bonding or adhesion to the substrate, the initial stages of growth will generally be characterized by the deposition of thin planar films of epitaxial materials. The difference in lattice parameter will then lead to the development of internal stresses in the film due to the lattice mismatch between epitaxial layer and substrate. As the thin film strives to maintain perfect registry with the atoms in the substrate, the atomic positions in the epitaxial layer are shifted from their normal bulk values to conform to those of the atoms in the substrate. This shift in atomic position leads to a tetragonal distortion of the unit cell within the epitaxial layer and the development of an internal stress. Thin, highly perfect layers can therefore be grown in which the atoms in the thin layer are locked in perfect registry with the plane of the substrate surface despite the lattice mismatch. This process is referred to pseudomorphic growth. It is therefore possible to grow highly mismatched materials, without extended defects, to a limited or ‘critical’ thickness (Fitzgerald, 1991). The exact maximum thickness prior to the formation of extended defects which relieve the built-in stress, commonly referred to as the critical thickness, is specific to the particular materials combination. Many interesting materials structures can be invented and have been developed based on the use of pseudomorphic materials integrated in-

130

3 EDitaxial Growth

to a multilayer structure. The internal stress in the films can modify the electronic band structure which leads to the controlled formation of new optical and electrical properties which cannot be obtained in the nonstressed semiconductors. As the epitaxial layer grows, this internal stress continues to develop until the elastic energy stored in the film is sufficient to be released in the formation of defects. These defects occur typically in the form of dislocations. These dislocation can further multiply and propagate through the extent of the film releasing the internal stress and relaxing the atomic positions in the epitaxial layer to their bulk positions. Once the strain in the deposited film becomes too large, the film relaxes and three-dimensional islands form on the surface. The formation of the strain relieved structure, beyond the critical thickness, often leaves a structure in which there is a thin pseudomorphic layer remaining next to the substrate with the three-dimensional island growth of the defected and strained relieved materials residing above this layer. This growth mode, schematically shown in Fig. 3-9 b, is referred to as a Stranski-Krastanov growth mode. There are several common epitaxial growth modes which have been observed, as described above. The appearance of a particular growth mode has been rationalized in terms of the interfacial energies associated with the epitaxial layer-substrate interface and the stresses induced by the lattic mismatch. Other considerations can often dominate the appearance of a particular growth mode. The temperature and rate of growth, as well as other kinetic factors, can often give rise to growth behavior which would not be expected on the basis of purely energetic considerations. Lastly, the final microstructure and morphology of the epitaxial films will also be affected by

the initial perfection of the substrate and the difference in thermal expansion coefficients of the two materials. Defects in the substrate can propagate into the epitaxial layer. A dislocation intersecting the growth front will continue into the epitaxial layer since this structural information forms part of the epitaxial seed that is replicated into the growing film. Almost all epitaxial films are grown at temperatures which are substantially higher than room temperature. The difference in thermal expansion coefficients may also generate a great deal of strain in the film upon cooling from the growth temperature. This strain may also be released through the formation of dislocations and other extended defects.

3.3 Chemical Vapor Deposition: Technology and Issues Chemical vapor deposition or CVD is the deposition of thin films from the gas phase onto a substrate. As such, this process encompasses a wide variety of concerns which are not seen in other forms of crystal growth, such as those based on physical evaporation. Gas phase and surface chemistry, along with the thermal fluid environment from which the crystal is growing, must be controlled to a high degree in order to produce a high quality crystal that will become the device structure of interest. The basic CVD system consists of a flowing gas phase ambient which passes over a heated substrate. The mechanical aspects of the CVD system are conceptually divided into two separate components: the gas panel and the reactor. The gas panel mixes and schedules the gas phase reactants or nutrients into the reactor. The gas panel construction is designed so that accurately synthesized mixtures of reactants are injected at precisely the cor-

3.3 Chemical Vapor Deposition: Technology and Issues

Induction Coil

131

Silicon Wafers

\

Radiant Heaters

&ccocco,accc

Gas -nI

-

ccoccommm

Horizontal CVD Reactor

yL ,Exhaust Barrel CVD Reactor

control 0

Gas

xhaust

f

Horizontal LPCVD Reactor

Vertical CVD Reactor

Figure 3-10. Schematic of several reactor configurations commonly employed in chemical vapor deposition technology.

rect time to yield the desired structure. The valves and meters used in its construction are designed to exclude unintentional contaminants which would lead to unwanted impurities in the films. While the gas panel is of a common design in most CVD systems, the CVD reactors are quite varied depending on the growth chemistry and desired product. The reactor design is therefore materials specific. Examples of various reactors used in the epitaxial growth of semiconductors are shown in Fig. 3-10. The features important in most of these reactors centers on the uniform flow of nutrients over the growth surface of the wafer and the removal of the reaction by-products. The CVD growth of semiconductors is often conceptualized as consisting of several

steps, as schematically shown in Fig. 3-11 for the case of Si growth. Generally, the slowest of these steps will limit the observed growth rate. There are several principal factors which influence each of these primary conceptual steps in the CVD epitaxial process. Energy is directed into the reactor in order for the desired chemical reactions to occur. This energy comes typically in the form of heat through the placement of the reactor in a furnace or through the use of a locally heated substrate holder. In the latter case, the walls of the reactor and the gas stream can remain cool relative to the hot substrate. This latter configuration suppresses the gas phase decomposition of the nutrients prior to their arrival at the growth front. In all cases, there are common features to the CVD process

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132

3 EDitaxial Growth

‘ w e l l m i x e d ’ g a s at a m b i e n t T _ _ Jnm

3.3.1 Reactors: Mass, Fluid, and Thermal Transport

pw A-

I

3.3.1.1 Fluid Behavior and Reactor Design

Transport to surface:

Surface Reaction:

Jsurllcp

Jgrovrh

= K , Psur‘‘cc Jgas

Jsurlsce

K . Pgrr

Figure 3-11. Si growth. like most semiconductor growth systems. can be conceptualized as consisting of several steps as shown here, involving gas phase and surface chemistry as well as surface transport leading to the incorporation of the deposited atom into the growing structure.

which bear on the growth of most epitaxial films. The specific nature of these elementary steps can influence the film composition, its electrical and optical properties, the uniformity of the thickness of the film and properties across the substrate and between substrates, the structure and abruptness of electrical and compositional interfaces, and finally the presence of defects in the film. The issues of uniformity and defects bear directly on the utility of the epitaxial films in later device processing. Defects, particularly morphological defects on the growth surface, make subsequent processing difficult, particularly the process of photolithography. The discussion of the epitaxial growth of semiconductors by CVD will therefore center on the principal influences of each of these primary steps in the microscopic model of the film growth.

The CVD reactor is typically a reaction chamber through which the reactant gases flow and in which the heated wafers are placed. There are several principal reactor geometries which are,used in the growth of compound and elemental semiconductors. The choice of a specific reactor depends on the growth chemistry and pressure regime used in the growth process. These operating conditions are in turn determined by the growth chemistry. The four reactors shown in Fig. 3-10 are those most commonly found in the manufacturing of epitaxial semiconductors. The horizontal, barrel and rotating disk reactors are all forms of ‘cold-wall’ reactors. These reactors operate at relatively high pressures, between 1 Torr and atmospheric pressure (760 Torr). The fourth reactor pictured in this figure is a low pressure ‘hot-wall’ reactor referred to as an LPCVD system. This reactor operates at pressures as low as 0.001 Torr or about atm. The mass and fluid transport in these systems can be quite different. The first three systems operate in the viscous fluid regime where the continuum mechanics description of the fluid behavior can be used. The LPCVD can be operated in the molecular flow regime. The specific flow regime of the CVD environment is characterized by the Knudsen number which is based on the ratio of the mean free path of the gas molecule, A, to the typical physical dimension of the reactor, L : K n = i / L . The mean free path of a gas molecule of diameter d, at a gas pressure of P, is given by (3-18)

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The Knudsen number is one of the many dimensionless numbers which can be used to describe general features of the fluid, thermal and mass transport. The mean free path of a gas molecule at room temperature is approximately given by A (cm)= O.OOS/P, where P is the pressure in Torr. At atmospheric pressure, ( 760 Torr) the mean free path is about 70 nm while at a low pressure of Torr the mean free path is 5 cm. The major flow regimes are then classified by the magnitude of the Knudsen number:

\

133

LAMINAR

TURBULENT FLOW

N

-

viscous flow transition flow molecular flow

*

Kn 4 1 Kn z 1 Kn 1

I .

Figure 3-12. Laminar flow profiles can be developed in the reactor chamber leading to a controlled and regular flow of gas over the growing substrate surface.

+

The viscous regime is characterized by low temperatures and high pressure. Most CVD systems which operate at moderate or near atmospheric pressures are therefore in the viscous flow regime. In this pressure regime, the fluid transport is described by the traditional fluid transport models which provide the equations governing the thermal, momentum and mass transport in the reactor. While the complete solution of the transport equations is generally dificult, several simplifications have arisen which provide a heuristic model of the growth environment. The design of CVD systems within this pressure regime typically focuses on the development of a laminar flow profile within the reactor. Laminar flow is characterized by the gas flowing smoothly across the surface, without turbulence, as shown in Fig. 3-12 for the case of a horizontal growth system. In the rotating disk reactor, a spinning disk is the substrate holder which acts as a centrifugal pump, resulting in a radial flow of gas across the surface. In the absence of laminar flow, turbulence or irregular mixing leads to a high degree of non-uniformity in the film growth since the gas flow and hence the flux of nutrients to the surface is

changing with time. Laminar flow is readily established in most systems within a short entrance length of the reactor. The full fluid mechanical treatment can be subsequently carried out for most of these reactors. Such modeling efforts, requiring the numerical solution of the coupled heat, mass, and momentum transport equations, can be solved with considerable effort. The results of these calculations provide a detailed picture of the transport of nutrients within the CVD reactor. The calculated flow patterns resulting from such a calculation for a horizontal system is presented in Fig. 3-13 (Vossen and Kern, 1991). A complex fluid flow behavior within the reactor can be seen in this figure. The complexity of these flow fields, which add to the nonuniformity of the growth, can often be suppressed by an appropriate choice of growth conditions. In particular, the reduction in the reactor pressure at a constant mass flow can eliminate many of these recirculation effects and lead to a laminar flow profile in the reactor. Once laminar flow is established, the resulting gas phase fluid transport across the growth front is often characterized by the use of boundary layer

134

3 Eoitaxial Growth

-.

_--

Figure 3-13. Numerical solution of the basic equations governing the mass, fluid and heat transport in the reactor can be used to predict many of the complex flow patterns and phenomena in a CVD reactor. This figure illustrates the results of such a calculation for a horizontal reactor. (a) The predicted flow pattern from a symmetric and asymmetric inlet geometry. The latter leads to a complex fluid flow. (b) Recirculations in the flow field can result from geometric differences in the reactor shape [Vossen and Kern, 19911.

theory. Boundary layer theory is a simplified description of fluid flow based on specific assumptions. A boundary layer is a hypothetical gas phase region near the growth surface over which the gas velocity is zero. This stagnant region of gas allows for the easy solution of the diffusion equation for mass flow across this boundary layer. The extent of the boundary layer is dependent on the gas velocity and viscosity. It arises from the ‘no-slip’ condition at the reactor walls where the gas velocity is zero. In practice, the assumptions of the boundary layer theory are not strictly met for most reactors, yet this simplification can predict some of the general features of the growth process. The flux to the surface is found by postulating a growth reaction at the surface in series with the gas phase transport to the growth front as seen in Fig. 3-1 1. The diffusion of growth nutrients

across this boundary layer provide the growth front with the reactants for the film to develop and grow. .4t steady state, the flux through the gas phase and the reaction rate at the surface are equal. Several reviews and discussions of the modeling methods and considerations used in describing these reactors can be found in the references to this chapter (Hess and Jensen, 1989; Middleman and Yeckel, 1986; Ouazzani and Rosenberger 1990; Vossen and Kern, 1991). LPCVD reactors, as shown in Fig. 3-10, typically have a large number of wafers that are stacked close together within the heated region of the furnace. Models of these reactors consider the gas flow around the wafers as well as between the wafers. The calculation of the fluid flow in such systems is divided into two separate regimes where the gas flow in the annular region around the wafers is often treated as a viscous fluid flow and the mass transport radially between the wafers is considered to be diffusionally based. This model provides an accurate picture of the fluid and mass transport until the characteristic distances, such as the wafer spacing, become less than the mean free path in the gas. Reactors operating in the molecular flow regime, K n 6 1, are often used when the growth rate is limited by the surface reaction rate of a growth species. In this case, the simple models based on continuum fluid mechanics and diffusion are no longer accurate. The detailed motion of individual gas molecules, as they enter, transverse, react and leave the reactor must be considered. This detailed molecular description is addressed through numerical techniques which have been developed to build a macroscopic description of the growth process from the trajectories of individual molecules. These calculational methods, referred to as Monte Carlo techniques, are


based on the statistical nature of molecular flow. Such numerical models require timeconsuming calculations, but can yield an accurate description of mass transport in the reactor. 3.3.1.2 Mass and Thermal Transport

The fluid behavior within the reactor provides a description of the overall mass motion in the system. In LPCVD growth there is a high mole fraction of the reactants in the gas phase, while, in the case of higher pressure growth processes, the reactants are diluted in a carrier gas. A carrier gas is typically an inert dilutent, such as He, N, , or H, , which is used to control the partial pressure of the reactants while maintaining an overall reactor pressure or flow. In the case of LPCVD systems, the mass transport is largely given by the fluid flow. The high pressure reactors possess a reactant mass transport due to both convection, through entrainment in the carrier gas flow and diffusion through the boundary layer. The gas phase diffusion coefficient for thermal and mass transport are similar in magnitude and their transport in these types of reactor are described by similar theoretical formalisms. The uniform growth of an epitaxial film requires that the flux of the reactants to the growth front be uniform over the wafer surface as well as among all the wafers in the reactor. This uniformity requirement places constraints on the mass transport in the reactor. The mass transport must be designed to provide this constant flux to the surface despite changes gas phase conditions in the reactor. The mass transport in high pressure reactors is complicated by the consumption of the nutrients as the gas flows over the heated growth surface. The growth rate, GR, of the film, measured in thickness per unit time, is equal to the flux of nutrients at

135

the growth surface (3-19) where D is the gas phase diffusion coefficient and c is the concentration of reactants in the gas phase at the growth front and no is the number density of atoms in the film. The gas phase diffusion of reactants near the surface is modified by the overall fluid flow and the gas phase concentration of reactants. The gas phase reactant concentration will vary over the surface of the wafer because of depletion of the reactants from the gas stream resulting from upstream deposition of the thin film. The design of the reactor can substantially reduce these depletion effects. Early modeling efforts treated this depletion of the gas phase of reactants through the formation of a diffusional boundary layer of thickness Jdiff,in analogy to the boundary layer formed as the laminar flow profile is generated in the fluid flow. This diffusional boundary layer will grow as the gas flows over the heated substrate and the gas phase near the growing wafer becomes depleted of nutrients (3-20) where v is the kinematic viscosity of the gas, V,, is the mean stream velocity of the gas, and x is the distance along the gas flow. The flux to the surface or GR can then be approximated by D

c

(3-21)

c being the gas phase concentration of the reactants in the bulk of the gas at a given position along the reactor. Since d d i f f is a function of position in the reactor, the growth rate will, in principle, vary along

136

3 Epitaxial Growth

the length of the reactor. In order to achieve uniform growth over large substrate areas in a horizontal reactor, the cross-sectional area of the reactor is often reduced in order to locally increase the V,, in the reactor. This increase in the gas velocity along the reactor can offset the drop in the growth rate due to gas phase depletion. Other approaches to increasing the uniformity have been the use of other alternative carrier gases to H, , which alter the gas phase viscosity, as well as the use of very high reactor flow velocities. The latter approach can lead to the growth of uniform films at the expense of low utilization of the growth reactants.

3.3.2 Gas Phase and Surface Chemistry The description of most chemical systems begins with an equilibrium thermodynamic analysis of the overall process. The term equilibrium implies that the system is unchanging in time which is clearly not the case for the process of crystal growth. The process of crystal growth is inherently not an equilibrium thermodynamic process since it entails a net deposition of material. As described above, the growth rate of a material can be affected by a variety of macroscopic transport phenomena. No matter what the transport limitations are in the system, there must be a thermodynamic driving force for the deposition of material. This driving force or supersaturation can be calculated by the application of conventional concepts of the law of mass action to the chemical reactions of importance for film growth. This driving force arises from the free energy change of the overall chemical reaction responsible for the net deposition of material. The application of thermodynamics can provide some useful and important information on this driving force. Thermodynamics can indi-

cate whether a reaction is energetically possible and, if it is possible, the expected maximum extent of that reaction. While thermodynamics can indicate the feasibility of a reaction, the actual occurrence and rate of the reaction will depend on the temperature and the specific species involved. Not all reactions will occur under the desired thermal conditions supplied in the reactor. In those cases, non-thermal energy sources are often used. External energy sources, such as ultra-violet (UV) radiation or an applied plasma, can provide SUEcient energy to initiate the growth reaction through the breakdown of the growth precursor. In most cases, the simplicity of implementation and uniformity of growth afforded by the simple heating of the substrate is favored over these other energy sources. The growth chemistry occurring within the reactor is generally divided between that occurring in the gas phase and on the surface. There has been a wide assortment of gas phase compounds used in the growth of semiconductors. Some of the more common reactants for silicon deposition are listed in Table 3-2. Many of these compounds will decompose or react in the gas phase at relatively low temperatures. Disilane, Si$,, will rapidly decompose in the gas phase at temperatures of 700°C. The reaction products will further react in the gas phase producing other species which eventually reach the surface. The gas phase decomposition of Si,H, eventually leads to a mixture of SiH,, Si,H,, and SiH, reaching the surface, as shown below. Disilane decomposition (unimolecular decomposition) Si,H,

* SiH,+SiH,

(1)

Silane formation (gas phase reaction) (2) SiH,+H, * SiH,


137

Table 3-2. Thermodynamic and physical properties of Si-based growth sources. State at room temperature

Vapor pressure at 22°C (Torr)

Free energy of formation (kcal/mol)

SiCI, SiHC1,

liquid liquid

- 148.16

SiH,Cl, SiH,Cl SiH, Si,H,

gas gas gas gas

208 533 1200 (23 psig) 47 990 (928 psig)

Compound ~~

Disilane reformation (gas phase reaction) (3) SiH,+SiH, =- Si,H, In this case, the use of disilane leads primarily to the arrival of SiH, and Si,H, to the growth front since reactions (2) and (3) occur very rapidly in the gas phase at elevated temperatures in a H, carrier gas. Such a rapid reaction leads to a very low steady state concentration of SiH, in the gas phase. If the gas phase decomposition of Si,H, goes to completion, i.e., the formation of SiH,, disilane-based growth of Si would then result in a factor of two in growth rate over that found with SiH,. In this case, gas phase reactions result in the in situ generation of a growth precursor, SiH,, which reaches the surface. Not all gas phase reactions lead to benign or useful reaction products. Many compound semiconductors are grown through the metal-organic vapor phase epitaxy (MOVPE) process. A feature of this process is the use of volatile metal compounds, such as (C,H,),Ga and (CH,),In, typically in conjunction with group V hydrides, such as ASH, and PH, . The metal organic compounds, while being stable at room temperature, do undergo gas phase decomposition at temperatures low compared to typical substrate temperatures. These compounds decompose and react in the hot gas phase regions of the

-115.34 -43

+13.6

+ 30.4 reactor, as well as at the growth surface, leading to depletion or elimination of the growth reactant prior to its arrival to the growth surface. The decomposition of the metal organic compounds leads to nonvolatile by-products, containing the metal species, which are deposited on the reactor interior walls. This gas phase pre-reaction results in a reduction of the growth rate and an increase in growth rate non-uniformities along the wafer. Other types of deleterious gas phase reactions lead to the formation of undesired gas phase chemical species which are subsequently transported to the growth surface and result in defect formation. This is particularly true for particle-forming reactions. The gas phase reactions described above all depend on temperature and reactor pressure. In the case of the metal-organic compounds, the use of a ‘cold-wall’reactor allows the gas phase to remain cool prior to its arrival to the growth front. The gas phase reactions are therefore suppressed. Many reactions, such as the uni-molecular decomposition of Si,H, given in Eq. (I), rely on collisions with other gas phase molecules for their initial stages of decomposition. These gas phase decomposition reactions can be effectively suppressed through the use of low reactor pressures. The low reactor pressures reduces the probability of gas phase collisions and sub-

138

3 Epitaxial Growth

sequent decomposition. Low pressure reactors utilize this dependence on the reactor pressure to eliminate the gas phase decomposition of the growth reactants. In these cases, the gas phase chemistry no longer plays a great role in the growth chemistry. As a result, the direct reaction of the growth reactants with the growth front is the principal reaction in the overall growth chemistry. The thermodynamic and mass transport relationships can determine the necessary conditions for growth and the uniform arrival of the growth nutrients to the surface. Once at the surface, the decomposition and incorporation of the material will be dependent on the details of the surface structure and surface chemistry. The elementary steps in these surface processes start with the adsorption of a reactive species. The adsorption of these species depends on the availability of an adsorption site and the energy required or released upon adsorption for reactions. There are often many gas phase species competing for the same surface sites. The resulting surface composition, in terms of adsorbed species, will be the result of this competition, determined by the relative gas phase concentrations and the energetics of the adsorption process. The surface adsorption of reactive species can be described by several simple models. Most of these models are based on equilibrium thermodynamic considerations. In these models, the surface concentration of reacting species will result from a balance between the arriving species, Rgas,interacting with vacant surface sites, V, and those adsorbed species, R,, which may subsequently be available for desorption. adsorption: R,,,+V desorption:

R,+V

% R, Rga,+V

(4) (5)

where kad and k d , are the rate constants for the adsorption and desorption processes. The simplest of these models is the Langmuir adsorption isotherm. This model assumes thermodynamic equilibrium between the gas phase and surface adsorbed species, The constraints in the model include the restriction of only one type of surface site and a limit of one monolayer of adsorbed species. The fraction of available adsorption sites is given in terms of the reactant partial pressure in the gas phase. The fraction of available adsorption sites, 0, covered by given reactive species is given by (3-22) where P is the partial pressure of the reactive species, Rgas,over the growth surface, and c1 is typically written in Arrhenius form as (3-23)

Qad being an activation energy associated with the adsorption process, and a. a constant (Adamson, 1990). This simple equation allows for a description of the temperature dependence and the partial pressure dependence of the surface concentration of reacting species and can often, despite its simplicity, describe the features of many adsorption processes. At low partial pressures, the surface coverage is simply proportional to the gas phase concentration: 0 z a P. Correspondingly, at high pressures, the surface coverage becomes unity. Temperature affects the surface coverage through favoring high coverages at low temperatures where the desorption of species would be suppressed. The Langmuir adsorption isotherm can be modified to account for more than a single adsorbed species. If several species


are competing for the same adsorption sites, the site coverage of each species will be affected by the presence of the other chemical entities on the surface. The site fraction of a particular adsorbed species is then given by

139

The growth rate expression, formed by combining these two expressions, will have a temperature dependence related to both the adsorption and decomposition processes, combined with the gas phase concentration of reactant at the growth front

(3-24)

krxn,O a0

P ~ X(-(Q;+Te,xn)) P

GR = where the sum is over all the species ( j ) available for adsorption. This is a common situation during growth. In the case of SiH,-based Si growth, SiH, , SiH,, and H all complete for the same sites on the surface. Adsorption is the first step leading to a surface reaction. Once adsorbed, the reactant undergoes further decomposition or reaction with an ultimate by-product being the incorporated atom. There are several simple types of surface reactions which may occur. In practice, these simple models may not adequately describe the detailed surface reaction kinetics, but they do serve to describe the overall phenomena. The reaction rate of adsorbed species will be dependent on its surface coverage, the concentration and nature of the nearest neighbors and the temperature. The gas phase chemistry is coupled into the surface or heterogeneous reactions to complete the model of the growth chemistry. The simplest model of the surface growth reactions is the direct decomposition of the reactant on the adsorbed site. In this case, the growth rate will be proportional to the surface coverage of the adsorbed reactant

(3-27) This relationship can lead to a complicated behavior dependent on growth temperature and reactant concentration. For many systems, the partial pressures and resulting surface coverages of reactant are low, leading to the reduced expression

where k,,, is a rate constant for the decomposition of the surface species. This rate constant is also assumed to follow an Arrhenius rate expression

This expression indicates that the growth rate will have a linear dependence on the gas phase reactant concentration and an exponential dependence on temperature. Such behavior is often seen in many CVD growth systems despite the actual presence of a more complicated growth chemistry than assumed in this simple model. More complicated surface reaction schemes have been proposed to describe the CVD growth behavior. Many surface species require the co-reaction of two adsorbed species on nearby sites for the completion of the growth reaction. In this case, the growth rate will be proportional to the surface coverage of both reacting species. Again, the surface coverage of each species could be described by the Langmuir model. The growth rate reaction will then be proportional to both reactant surface coverages. The constant of proportionality will be the reaction rate constant k,,,

(3-26)

(3-29)

GR cc 0 or GR=krX,0

(3-25)

140

3 Epitaxial Growth

This particular model is referred to as the Langmuir-Hinshelwood reaction law and has been used to describe the growth behavior of GaAs from (CH 3 ) ,GA and ASH3 . The temperature and pressure dependencies of this expression are quite complicated and have been used to explain the often observed complex behavior of the growth rate on reactor variables. The generalization to other growth situations can be derived through a combination of the adsorption law and the assumption of a specific chemical mechanism. Examples of the development of these rate relationships for common CVD epitaxial systems will be discussed later. The surface reactions involved in epitaxial growth are dependent on the detailed surface structure present at the growth temperature under the chosen growth conditions. These surface structures are, in turn, partly determined by the presence of adsorbed species. Steps, kinks, and terrace structures, as well as local reconstruction, can present a variety of different adsorption sites for the arriving chemical species. In particular, impurities can adsorb, in addition to the primary growth reactants, on the surface perturbing the growth chemistry and the growth morphology. The incorporation of impurities has been described using the same concepts as discussed for the growth reaction itself. The impurity source can undergo gas phase reactions, adsorb on the surface, and be incorporated into the growing film. Many impurity sources can only strongly adsorb at specific surface sites, e.g., steps on the surface. Small variations in substrate orientation, sometimes referred to as miscut, lead to large changes in the efficiency of impurity incorporation. Such detailed factors can complicate the growth behavior and final properties of the epitaxial film.

3.4 Liquid Phase Epitaxy (LPE) Technology Liquid phase epitaxy (LPE) was first demonstrated by Nelson (1963) and has been used to deposit a wide range of materials, including 111-V and 11-VI semiconductors, as well as magnetic garnet materials (Giess and Ghez, 1975). The flexible nature of LPE and the ability to produce high purity material has been used to produce the first demonstrations of many electronic and optical devices, including the first room temperature cw operation of a GaAs/Al,Ga -,As double heterostructure laser. The advantages of LPE include relatively simple and inexpensive equipment, high utilization efficiency of precursor material and the ability to produce high purit y and high optical efficiency material over a wide range of thicknesses. In addition, LPE is a near-equilibrium growth technique. The growth rate is strongly dependent on the substrate orientation, which leads to unique abilities to regrow and planarize patterned substrates. These advantages have made LPE a common deposition technique for a wide range of LEDs where low cost is a major issue as well as buried heterostructure and DFB lasers which take advantage of LPE’s regrowth capability. The weakness of LPE comes from its inability to controllably grow very thin layers of a specific composition required in heterostructure electronic devices such as superlattice or quantum well devices. The growth rate in LPE is generally higher than in MOVPE or MBE, which limits LPE’s ability to produce very thin layers. Absolute layer thickness control is also not as good as these other techniques, as a result of the manner by which the growth is initiated and terminated. Because LPE is a near-equilibrium technique, not all materi-

3.4 Liquid

als can be grown by this technique. Miscibility gaps occur for some compositions of ternary and quaternary materials which prevent their deposition by LPE due to phase separation during growth. Finally, surface morphology is typically not as good as in MOVPE or MBE, which again precludes its use for the growth of certain device structures. Thus, for more sophisticated devices which include quantum wells, superlattices or etched gratings, MBE and MOVPE are most commonly the growth techniques of choice. LPE growth occurs by precipitation of the desired material out of a supersaturated solution onto a substrate. In contrast to MOVPE and MBE, LPE takes place very near to equilibrium in a column-111-rich environment. The solvent element is typically the column I11 constituent of the compound to be deposited (Ga or In); in some cases other low melting point metals such as Sn, Bi or Pb are used as the solvent. The thermodynamic driving force for LPE growth is produced by cooling the system below the liquidus temperature. In the

0 Ga

0.5 x - b

1 As

Figure 3-14. The Ga-As phase diagram can be used in the development of the LPE growth process of GaAs.

Phase Epitaxy (LPE) Technology

141

phase diagram for GaAs, shown in Fig. 3-14 (Casey and Panish, 1973), only a liquid exists above the convex line. Melt growth (i.e., Czochralski) is performed at the melting point of the stoichiometric solid (1238"C for GaAs) while LPE is performed at much lower temperatures. LPE growth of GaAs takes place by cooling a solution of Ga, containing a small amount of As at a temperature, TI, to its liquidus temperature, T,, at that composition, for example point B in Fig. 3-14. Upon further cooling to temperature, T,, at point C, the solution becomes supersaturated and GaAs begins to precipitate or grow onto the substrate. When suficient GaAs has precipitated out, such that the liquid is no longer supersaturated, growth stops at point D. During this period, the liquid composition changes from B to D. Since most of the 111-V binary compounds are line compounds (i.e., no measurable homogeneity range), only stoichiometric GaAs is deposited. In ternary and quaternary compounds, this is not necessarily true since the composition of the deposited film depends on the supersaturation and liquid composition. As a result, not all alloy compositions can be grown at an arbitrary temperature. Many ternary and quaternary alloys possess a miscibility gap. A miscibility gap in the phase diagram implies that two solid phases or two solid compositions will simultaneously grow out of the liquid solution depending, of course, on the specific temperature and liquid compositions. Three principal variants of the LPE technique have been reported in the literature: tipping, dipping and sliding. Only the latter variant slider-based LPE, has seen widespread use. Tipping was the technique first used for LPE. In the tipping technique, the melt and substrate are placed at opposite ends of a crucible. Growth begins

142

3 Epitaxial Growth

by tipping the crucible so that the melt flows over the substrate. Growth is terminated by returning the crucible to its original position, thus removing the melt from the substrate. This method is limited to the growth of a single layer. The dipping technique permits the growth of multiple epitaxial layers on the substrate. In the dipping technique, the substrate is dipped into the melt to initiate growth, and removed from the melt to terminate growth. The substrate is moved to an additional dipping station and the growth procedure is repeated, accomplishing the growth of an additional layer in a multilayer structure. This technique has been used for multiple layer growths and for some commercial devices, however, like the tipping technique, thickness uniformity is only moderate. Device requirements of multiple layer structures, with thin layers of different compositions, have led to the dominance of the sliding method. The slider method is the most widely used for LPE because it permits straight-

forward growth of multiple layer structures with acceptable thickness uniformity. A schematic view of the slider system is shown in Fig. 3-15 and consists of a tray which holds the substrate and a slider which has multiple bins for different melts (Kuphal, 1991). Each melt is associated with the growth of a different layer and therefore requires a different melt composition. For example, p-n junctions are made by having one melt contain a p-type dopant and the next melt an n-type dopant. Heterostructures can be produced by preparation and use of ternary or quaternary melts. The slider fits over the substrate holder tray and growth is initiated by sliding a bin containing the desired melt over the substrate. The components of the LPE system are made of graphite. The melts do not generally wet the graphite, which permits termination of growth by wiping the melt off from the substrate when the slider is moved. This assembly is housed in a quartz tube which is purged with high purity hydrogen. A movable multi-zone fur-

Solution Bins

I Slider Assembly

Figure 3-15. Schematic view of the commonly used horizontal slider-type LPE system.

3.4 Liquid Phase Epitaxy (LPE) Technology

nace typically surrounds the quartz tube. Often a heat pipe is placed within the furnace to promote flat temperature zones. The slider is positioned using a quartz rod; this can be done manually or through a stepper motor controlled by a computer. Graphite covers are typically placed on top of the melts to prevent evaporation and contamination of the liquid melt. The melts that make up the LPE system can either be single- or two-phase. A single-phase melt is a liquid that is supersaturated at a specific temperature. The supersaturation must be small enough to prevent spontaneous nucleation of the solid phase in the melt. A two phase solution consists of a melt which contains a solid source. The graphite cover may be replaced by a substrate of the type being grown, assuring uniform saturation of the melt. The major advantage of the twophase method is to simplify control over the growth process. For example, in LPE the growth rate is determined by the exposure time and the degree of super saturation. In the two-phase method, the floating substrate melt cap acts as a source or sink of material to ensure saturation of the melt during the initial heating state. In addition to ensuring saturation, the cover also prevents source evaporation and helps control the geometry of the melt. Since there are now two substrates, when the system is cooled, growth takes place on both substrates. Depending on the thickness of the melt, this can result in a desirable decrease in the growth rate on the intentional substrate. It should be noted that this technique is most advantageous for the growth of binary compounds since substrates with arbitrary ternary and quaternary compositions are not available. The slider technique has been developed through many years of research and development experience. Slider LPE production-scale systems

143

exist which are computer controlled and can handle multiple round substrates, up to 50 mm in diameter (Shea et al., 1993). There are a number of practical problems in the LPE-slider technique. For example, enhanced edge growth on the substrate is a potential problem for LPE. Enhanced edge growth occurs for several reasons, such as an orientation-dependent growth rate, thermal convection and nonone-dimensional diffusion of the solute in the melt. If the grown layer thickness at the edge of the substrates becomes larger than the space between the substrate holder and the melt slider, graphite and the grown material will be scrapped off by the slider and cause scratches and other defects on the growth surface. This space cannot, however, be made too large or some of the melt will be carried over and contaminate the adjacent melt. The substrate-slider spacing is typically between 20 and 100 pm, which puts limits on maximum layer thickness as well as tolerances on substrate thickness. Enhanced edge growth can be minimized by reducing thermal convection in the melt through the use of small cooling rates or isothermal (step) growth and through the use of thin melts with lids which reduce two-dimensional diffusion. It can also be eliminated by making the melt contact area smaller than the substrate. 3.4.1 LPE Growth Procedures The growth procedures in the LPE-slider technology are centered on the preparation of the melts and the time-temperature program of the subsequent growth sequence. Figure 3-16 illustrates a representative temperature cycle for LPE growth (Kuphal, 1991). The system is first heated to a temperature which is above the saturation temperature T,. This step produces a homogeneous melt. The temperature is

144

3 Epitaxial Growth

I

b

Time

Figure 3-16. Representative temperature cycle for LPE growth.

then lowered and the melt brought in contact with the substrate. Two common methods for lowering the temperature are shown, ‘equilibrium’ and step cooling. In ‘equilibrium’ cooling, the system is slowly cooled during the growth step from T, to an end temperature, T E .In step cooling, the system is cooled to the supersaturation temperature TA prior to making contact with the substrate, and subsequent epitaxial growth proceeds at this at a fixed temperature. The substrate can also be heated to above the saturation temperature in contact with an undersaturated melt in order to perform an in situ etch of the substrate surface. This etching step can aid in removing saw or polishing damage as well as creating a more uniform density of nucleation sites. The disadvantage of this melt-back procedure is that can adversely affect surface morphology through nonuniform etching. As previously stated, LPE is a close-toequilibrium growth process. If growth went completely to equilibrium, the amount of material deposited would just equal the amount of solid precipitated from the supersaturated melt to re-establish the solid-melt equilibrium at that temperature. This situation does not normally occur because diffusion in the melt is not

rapid enough to achieve equilibrium conditions throughout the melt volume. The growth rate is typically limited by diffusion of the supersaturated species through the melt to the substrate surface. A simple diffusion model can be developed in which the melt is assumed to be semi-infinite in height and isothermal with no convection cells. Growth is assumed to proceed by deposition only on the substrate and the growth rate is determined by diffusion of the solute (the low concentration component of the melt). In the case of GaAs growth, this would be diffusion of As in the G a melt to the GaAs substrate. The thickness of the epitaxial layer, d, that would be grown during time t is given for uniform cooling by

where R is the cooling rate, C i sis the concentration of the solute (As) in the solid, m is the slope of the liquidus curve which is assumed to be constant over the small temperature change associated with growth, D is the diffusivity and tis the growth time. For the step cooling case, the epitaxial layer thickness is given by (3-31) where AT is the temperature step (Casey and Panish, 1978). Growth rates for noninfinite melt heights as well as for ternary and quaternary materials have also been derived (Kuphal, 1991). Typical growth rates for LPE are around 1000A/min. While a variety of techniques have been developed to lower the growth rate and provide short exposure times to the melt, LPE cannot compete with MOVPE or MBE in the formation of extremely thin layers.

3.4 Liquid Phase Epitaxy (LPE) Technology

145

Figure 3-17. Planarization of a 4 pm deep groove by LPE growth of Al,Ga, - .As/GaAs/Al,Ga -,As layers [Kuphal, 19801.

One of the main characteristics of LPE is that it is a simple method to produce material with high purity and high optical efficiency. These positive material properties are derived directly from the growth method. LPE is performed under group 111-rich conditions, which results in a low density of group I11 vacancies. These vacancies have been attributed to non-radiative recombination centers which limit optical efficiency, carrier lifetime and diffusion length (Jordan et al., 1974; Ettenberg et al., 1976).High purity growth is aided by the fact that the melt tends to retain impurities by virtue of their small distribution coefficients. Pre-baking the Ga melt has also been shown to be very effective in reducing unintentional impurities and producing high purity GaAs (Amano et al., 1993).The impurity concentrations of S, Si and C in the melt have been reduced by Ga pre-baking. Oxygen is another deleterious impurity which forms a non-radiative deep level in a number of 111-V materials. If a small amount of A1 is incorporated in the melt, any oxygen present will preferentially form A1,0,, which will remain in the melt

and prevent oxygen incorporation in the crystal (Stringfellow, 1981). The growth rate realized in LPE is orientation-dependent, which can lead to enhanced edge growth as discussed above. This orientation dependent growth rate can also be utilized to great advantage in regrowth on patterned substrates. The main use for this is to produce buried heterostructure and distributed feedback or DFB lasers. Figure 3-17 illustrates LPE growth over a 4 pm deep groove (Kuphal, 1991). The initially grooved surface has been fully planarized by the LPE growth of a series of AlGaAs/GaAs/AlGaAs layers. The large difference in growth rates on the (001) and (111) faces, especially between InP and the InGaAsP quaternary compounds, has even permitted the growth, in one step, of buried heterostructure lasers on pre-patterned substrates. It is almost impossible to produce these kinds of structures using any of the other common epitaxial growth techniques. The difficulty in achieving a smooth planar surface morphology over large areas is a major problem in LPE. As a near-equi-

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3 Epitaxial Growth

librium process, the surface mobility is large and subsequently the lateral growth rates are high. The surface morphology becomes, therefore, very sensitive to the substrate orientation, the nature and number of defects on the substrate and the conditions used for initial nucleation of the growth. The most common LPE morphological feature is a terrace or facet. If the substrate misorientation is large, extended terraces will form which make device fabrication difficult. Small misorientations, < O S ” , produce shorter terraces which have long treads, in the order of 100pm, with short risers in the order of several tens of nanometers. Using specific orientations, these terraces can be made large enough that devices such as lasers can be made completely on the terrace. It has been reported that extremely fine control of the growth temperature and substrate misorientation can be used to produce LPE layers without terraces (Rode et al., 1977). Heterostructure growth by LPE is complicated by the necessity of controlling the composition and diffusion of each species in the melt to achieve the desired composition. In some cases an effect called “lattice pulling” or “lattice latching” occurs which actually perturbs the solid composition of the growing layer to match the lattice constant of the substrate. The minimization of the total energy of the system, consisting of the strain energy combined with the thermodynamic driving force, leads to this shift from the predicted values. Lattice pulling actually makes it easier to produce latticematched heterostructures. This effect does not occur in MOVPE or MBE. Conversely, this effect makes it difficult to grow strained-layer structures, which require the ability to produce layers with specific lattice mismatches.

3.5 Molecular Beam Epitaxy (MBE) Technology Molecular beam epitaxy (MBE) is an ultra-high vacuum evaporation technique which is most commonly used for the deposition of single crystal semiconductors. It has been successfully used for the deposition of 111-V and 11-VI compound semiconductors as well as Si, Ge and related alloys. MBE has also been applied to the single crystal growth of a wide variety of metals and oxides. Like conventional thermal evaporative methods, it consists of a vacuum chamber with internal sources containing the materials to be evaporated. MBE systems are designed for extremely low pressures as well as very low outgassing rates. MBE is carried out under ultra-high vacuum (UHV) conditions. The UHV environment is required to maintain the purity of the growing film. In MBE, the growth rate is small, typically on the order of 1 pm/h. To achieve this growth rate, the source molecules must attach to the surface at about a rate of one monolayer of atoms per second. If all the atoms hitting the surface are incorporated, this impingement rate is equivalent to a vapor pressure of about IOv6 Torr. The residual gases in the vacuum chamber also impinge on the surface, react, and incorporate into the growing surface. The impurity content of the film is dependent, therefore, on the partial pressures of such unintentional impurit y containing gases in the chamber. The total background gas pressure in the chamber must be less than IO-’’ Torr to insure that the relative rate of arrival of impurities to growth nutrients is very low and the purity of the films is maintained at a high level. This high purity environment results in a number of unique characteristics. Among these features are the growth of high purity

3.5 Molecular Beam Epitaxy (MBE) Technology

material at temperatures lower than typically used in CVD, extremely fine control over the growth rate, and the ability to produce very abrupt interfaces, both for intentional dopants and major constituents. In addition, the high vacuum environment permits the use of in situ analytical tools, such as reflection high energy electron diffraction (RHEED) and Auger electron spectroscopy, which aid in monitoring the growth process. A principle advantage of MBE is its ability to utilize relatively low growth temperatures and slow growth rates. Lower growth temperatures result in reduced impurity incorporation from outgassing of hot system components, as well as reduced diffusion or redistribution of impurities and layer components within the device structure during growth. Slow growth rates ease control of film thickness and interface structure. Typical MBE growth temperatures and growth rates for GaAs are in the order of 600°C and 1 pm/h. The low growth temperature is made possible by the slow deposition rate. As discussed in Sec. 3-2, the slow growth rate gives impinging atoms sufficient time to diffuse across the substrate surface and to incorporate at their appropriate lattice sites. If the impinging flux rate becomes too high, the atoms will not have enough time to reach the proper sites and island growth will result. Island growth is undesirable because it can produce non-abrupt interfaces, loss of epitaxial relationship with the substrate and generation of a variety of defects. Defect generation can also result from a local non-stoichiometry, such as G a droplet formation, due to a local flux imbalance. The UHV environment of MBE determines the mode of mass transport in the growth chamber. Because of the low pressure, a large mean free path exists for the evaporated materials. The source materials

147

travel directly from the source to the substrate without scattering, forming a flux beam onto the sample. The beam nature of the flux allows the use of mechanical shutters to effectively interrupt this beam of evaporated species. The flux of nutrients at the growth front can therefore be very quickly and abruptly turned off or on. This fast switching of the sources, coupled with the slow growth rate, generates interfaces which approach atomic abruptness and layers that can approach single atomic layer dimension in thickness. As discussed above, since growth occurs at low temperatures, interdiffusion is often negligible between the layers during the growth process. A general schematic view of a MBE growth chamber is shown in Fig. 3-18. This chamber has three main parts: the vacuum system, the sources and the substrate holder. The vacuum system consists of the chambers, pumps, in situ monitoring equipment and transfer tools to move the substrates in and out of the system. The in situ monitoring tools include flux monitors on the sources and RHEED. RHEED is used during surface preparation prior to growth as well as for in situ calibration of growth rates. The growth sources, typically in elemental form are evaporated from effusion cells onto a single crystal substrate to form an epitaxial single crystal thin film. The flux of the impinging species at the substrate is controlled by the temperature of the individual effusion cells and the mechanical shutter position. The substrate is held in a heater stage, which is generally rotated to improve flux uniformity onto the growth surface. The MBE system is designed to achieve and sustain very low pressures. Base pressures approach Torr, while pressures during growth are about l o p 6Torr. A multi-stage load lock is used for efficient loading and unloading while minimizing

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3 Epitaxial Growth

Growth chamber wall

-

Figure 3-18. Scheme of a typical MBE growth chamber.

RHEED screen

the possibility of introducing air into the growth chamber. As shown in Fig. 3-19, a system usually consists of a load-lock, a buffer chamber and the growth chamber. The vacuum chamber is typically made of stainless steel, and employs metal-sealed

1

fittings and valves for low leak and outgassing rates. In addition to achieving low pressures, the system must be able to generate appreciable fluxes of desired species with very little undesired impurities. All components of the MBE system must be

Growth chamber

I

Heater qtation Buffer chamber

Substrates load here

Figure 3-19. The main components of an MBE system include load lock, buffer and growth chambers.


designed to withstand baking at x 200 "C to enhance desorption of water vapor and oxygen from the internal chamber walls. A 'bake' of the growth chamber is undertaken when the internal surfaces of the system have been exposed to air during the occasional opening of the chamber for maintenance. Air exposure leads to adsorbed water which can be more effectively pumped from the chamber by heating or 'baking' of the chamber walls. The substrates are introduced into the system through the load lock. The load lock utilizes several stages of pumps to quickly achieve a relatively low pressure to lo-' Torr). These might include an adsorption pump followed by a cryogenic or ion pump. Load locks typically also permit low temperature (few hundred degrees) bake-out to desorb a large percentage of adsorbed water vapor from the substrate and holder. The substrate on which the film is to be deposited is attached to a carrier which can be transferred throughout the system. The substrate is attached to the holder using either an indium solder, or more commonly for whole wafers, a set of clips that greatly simplify loading and unloading. Smaller systems load one wafer at a time. Larger, production oriented systems utilize a trolley system to permit the loading or unloading of many substrates. Such wafer handling systems increase the throughput as well as minimize the number of exposures of the system to air. After the load lock is pumped out the substrates are transferred to the buffer chamber. The buffer chamber is the next higher stage of vacuum, typically pumped using an ion pump. The buffer chamber accommodates a higher temperature bakeout stage ( x500 "C) to further remove adsorbed impurities. It may also include some diagnostic equipment such as Auger

149

or RHEED analysis. After further pumping and baking in the buffer chamber, the substrate is introduced into the main growth chamber. This is done using a transfer tool which allows the substrate to be moved from one chamber to another without breaking vacuum. The growth chamber has a large cryogenic or ion pump in order to maintain the required vacuum level and partial pressures of residual gases during growth. These pumps are supplemented with large cryo-panels in the growth chamber which contain liquid nitrogen. The cold surfaces of the cryo-panels condense volatile gas phase impurities and greatly increase the pumping speed for species such as H,O and 0,. Water and other oxygen-containing species have an adverse effect on semiconductor properties, especially in Al-containing compounds. Cryo-panels are typically designed to surround the entire growth area, the source flange and the substrate holder. Excess growth species, such as As in the growth of GaAs, also condense on these panels, and thus are not completely pumped by the main pumping system. The source flange and effusion furnaces are also surrounded by cryo-panels which reduces cross-contamination and leakage of source material when the shutters are closed. The entire pump system ensures a very small partial pressure of unintentional species (H,O, O,, CO and CO,) in the growth chamber, with the result that very high purity materials can be deposited. The substrate, in its holder, is mounted on a heater stage in the growth chamber, It is typically heated by radiation from a filament source. The temperature is measured using a thermocouple behind the substrate as well as a pyrometer which controls the surface of the substrate. Typically an ion gauge is positioned opposite the substrate holder. This ion gauge can be rotated into

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3 Epitaxial Growth

the flux beam to measure the 'pressure' of the flux of each growth nutrient from the sources directly at the substrate position. One of the advantages of MBE over CVD is the availability of in situ surface analysis techniques mentioned above that may be used before and during growth. The most commonly used technique is RHEED. The two major uses of RHEED, within the MBE growth chamber, are (1) to establish the correct surface conditions prior to growth and (2) to perform in situ growth rate determination. The RHEED system, shown schematically in Fig. 3-18, consists of an electron gun producing an electron beam with energies in the range of 5-50 keV and a phosphor screen. The electron beam is incident on the substrate at a very shallow angle ( z1-2"). The electron beam forms a two-dimensional diffraction pattern after reflection from the surface atoms of the growing layer. This diffraction pattern contains information about the overall structure and atomic arrangement of atoms on the surface. The structure of the reconstructed surface can be deduced by examination of the diffraction pattern on the phosphor screen. The choice of the appropriate surface reconstruction during growth can influence the growth mode and uniformity as discussed in Sec. 3-2. The evaporation sources are contained in effusion cells which can very accurately and reproducibly maintain a specified temperature. This control is required because the flux from these cells is mainly determined by the cell temperature. These cells are often called Knudsen or k-cells because they originally approximated the geometrical and equilibrium conditions used in Knudsen's work on molecular effusion (Knudsen, 1909). In an ideal k-cell, the vapor pressure in the cell is assumed to be at equilibrium with the solid or liquid source and only a very small amount of the vapor

species escapes through an aperture in the cell. The aperture is small enough that the equilibrium condition is maintained with the cell. In this case, the flux of atoms J (atoms cm-'s-') which impinge on the substrate, a distance, 1, from the cell aperture, is given by J=

PAN x i 2 (2 x M R T ) ~ ' ~

(3-32)

where P is the pressure in the cell, A is the aperture area, N is Avogardro's number, M is the molecular weight, R is the gas constant and T (K) is the cell temperature. The tight temperature control required for the effusion cells arises from the strong temperature dependence of the vapor pressure of the source materials (3-33) The combination of Eqs. (3-32) and (3-33) leads to a dependence of the flux on temperature given by J cc

T - 1'2 ~ X [ P Qevap/(kB 771

(3-34)

The heat of vaporization for most metals, Qevap,such as Ga is approximately 3-4 eV/ atom. In the case of Ga at 950 "C, the vapor pressure is x 2 x Torr. Using typical values of A=0.78 cm2 and 1 = 20 cm, the Ga flux is x1.5 x 10j4 atoms cm-* s-'. This corresponds to about 0.24 unit cells of GaAs per second or a growth rate of 0.48 pm/h. A temperature variation of 1 "C for a Ga k-cell operated under these conditions would lead to a = 2% change in flux. For many structures this variation must be minimized, constraining the source heater to have a temperature stability of greater than 0.2 "C at these elevated temperatures. In actual systems, effusion cells differ greatly from an ideal Knudsen cell. These differences come about from the necessity of achieving a higher growth rate and improved uniformity over large areas. High


purity refractory materials such as Ta and pyrolytic boron nitride (PBN) are used in the k-cell to prevent contamination of the source and chamber. Much effort has gone into crucible design, the goal of which is to provide a large and controlled flux with a minimum heat load. In all cases, the k-cells are surrounded by the cryo-panel to minimize heating of the chamber by radiation from the glowing heater and sources. As an example, the cell apertures are much larger than in an ideal Knudsen cell. This is done to achieve acceptably high growth rates without excessively heating the k-cell. The evaporation of many low vapor pressure elements, such as Si, may require other forms of heating which allow greater temperatures to be achieved. Electron beam heating, where a small, high current, high energy electron beam is focused onto the source, is a common alternative. The k-cells are held in a source flange which properly orients each cell with respect to the substrate. A short cell-to-substrate distance and large cell aperture are desirable in order to provide a uniform flux and acceptable growth rate over a large substrate area. Gas source or metal-organic MBE (MOMBE) is a variant of MBE, which employs gaseous sources in addition to, as well as replacing, the typical solid sources. The addition of a gas injector allows the use of a wide variety of gaseous and liquid sources such as ASH,, PH,, trimethyl gallium, and so on. Alternate precursors may permit new growth modes and dopant species, as well as easing the control of certain growth species. An example of the latter is the growth of mixed 111-V arsenide/phosphide materials. Growth of these materials using solid P is very difiicult because of the high vapor pressure of P, resulting in high vacuum capability problems, and difficulty in controlling the As/P ratio in the solid. Replacing elemental sources of As and P

151

with ASH, and PH, has greatly improved the ability to grow these materials. Gas source systems have much higher gas loads and thus require high speed pumps such as cryo, turbo-molecular or diffusion pumping systems. Gas introduction is often performed through a high temperature ‘cracker’ cell. The purpose of the cracker cell is to decompose or crack apart the precursor before it impinges on the substrate. Both thermal and plasma cracking have been used successfully. This partial decomposition of the growth sources allows for, at times, lower growth temperatures and higher source utilization. An example of the utility of this approach is in the MBE growth of 11-VI compounds. 11-VI compounds have traditionaIIy been very difficult to dope p-type. Nitrogen is a suitable dopant element in many 11-VI semiconductors, however N, is very unreactive. An ECR plasma cracking cell for N, , generating atomic nitrogen, has resulted in greatly increased p-type doping efficiency and directly led to the demonstration of 11-VI lasers. MBE systems have become increasingly sophisticated in response to the need for increased control, reproducibility and throughput. Computer control of the entire system, including effusion cell temperatures, substrate heater, shutters and the entire pumping system is common. The necessity of producing graded composition and dopant profiles has led to control programs which can produce arbitrary temperature profiles for effusion cells and the substrate heater. The latest developments include the incorporation of direct monitoring and feedback from in situ measurements, such as ellipsometry or reflection electron diffraction, to control the growth process. MBE permits relatively quick realization of specific device structures. MBE is

152

3 EDitaxial Growth

very effective for research projects as well as development and production where a large throughput is not required. Disadvantages of MBE include its high expense and relatively limited ability to grow on a large number of substrates simultaneously. Thus production of low cost devices, such as LEDs, or large area devices, such as solar cells, is better performed using other growth techniques such as CVD.

3.6 Specific Epitaxial Systems: Materials and Growth Issues The epitaxial growth of the common semiconductors has been accomplished by many techniques. The following section will focus on four individual systems currently being used in the semiconductor industry. The materials systems are chosen to highlight a particular growth technique. Silicon chemical vapor deposition is perhaps the most important semiconductor growth system. The analogous system for the growth of compound semiconductors is the metal-organic vapor phase epitaxy system which is discussed in the context of InP-based growth. InP is used in many opto-electronic devices. Liquid phase epitaxy has been replaced in many applications by the techniques of MOVPE and MBE. However, it remains a technologically important process in the growth of many high efficiency light-emitting structures in the Al,Ga, - .As/GaAs system. Finally molecular beam epitaxy is discussed in reference to the growth of GaAs.

3.6.1 Silicon Chemical Vapor Deposition Silicon epitaxy is used in many of the steps in the formation of integrated circuits. The particular form of Si epitaxy depends on the application of the materials

within a device context. Most Si epitaxy has been carried out in atmospheric pressure multi-wafer growth systems. These systems are capable of handling several wafers of large diameter ( 26” diameter). A major use of Si epitaxy is the formation of thick layers of controlled electrical properties on Si wafers at the beginning of the complementary MOSFET (CMOS) technology. The advent of advanced heterostructures in Si technology has been driven by new advances in the CVD growth technology. The growth of Si,Ge, -x\Si based material structures containing very thin layers of Si,Ge, - x grown on Si substrates has lead to an increase in performance of many traditional Si-based devices such as the bipolar transistor. The development of the ultra-high vacuum CVD of Si, referred to as UHV-CVD, has lead to the growth of Si structures at very low growth temperatures which minimizes interdiffusion between the grown layers. The reduced redistribution of impurities and materials preserves the grown-in heterointerfaces and impurity distributions allowing for the development of thin layer structures with abrupt interfaces. These two applications, thick Si layers and heterojunction formation, require different reactor designs and operating conditions, due to a difference in the underlying growth chemistry important to each process. 3.6.1.1 Silicon Chemical Vapor Deposition: Surface and Reactor Considerations

The growth of Si on large Si wafers is a processing technique used primarily at the beginning of the formation of integrated circuits. The reactors used in Si epitaxy are typically either barrel, single wafer, or the multi-wafer hot wall LPCVD tube reactors. The growth conditions employed in each of these systems is different. For each

3.6 Specific Epitaxial Systems: Materials and Growth Issues

of these reactors, the growth procedures have been optimized to yield a uniform, controlled film. The barrel reactor can hold typically 20-40 wafers on the susceptor. The wafers and graphite wafer holder are generally heated by RF induction or by banks of high intensity infrared lamps. The reactors typically run near ambient pressure using a chorine-based growth chemistry, such as SiCl, or SiCl,H,. These reactors can deposit at relatively high rates of xO.1 pm/min, when operated at high growth temperatures. The high growth temperatures, necessary for high growth rates, can lead to the interdiffusion or redistribution of impurities within the growing layers, often making abrupt doping junctions very dificult to achieve. The large thermal mass of these systems can lead to extended processing times at high temperatures. There are several considerations which have lead to the development of single wafer growth systems. The continued increase in wafer diameter has made many of the multi-wafer reactors impractically large. Simple scaling of the reactor size, based on wafer dimensions, has not been possible. In addition, many modern devices have a need for thinner device layers and minimized dopant redistribution. These device constraints only permit short times at high temperature to keep diffusion within acceptable limits. The use of a single wafer reactor allows rapid heating of the substrate through the use of infrared lamps. These systems are referred to as single wafer rapid thermal processing (RTP) based systems. While encountering many technological difficulties, such as uniform radiative heating and cooling of the wafer, these RTP systems can be easily integrated into an automated processing line since only a single wafer must be handled at a given time. In contrast, a barrel reactor

153

often requires operator-assisted loading and unloading of the wafers, leading to increased risk of breakage, contamination, and lost time. The newest form of reactor is the ultrahigh vacuum CVD or UHV-CVD system. This horizontal tube, multi-wafer system is a conventional LPCVD reactor which has been designed to operate at very low pressures. In addition, the reactor is constructed using similar technology to MBE systems to maintain a very low pressure, 5 lo-' Torr, while not in use. Wafer loads of 10-35 wafers or more can be used in a single growth run insuring a high wafer throughput. Wafers are loaded through a vacuum load lock which eliminates exposure of the internal surfaces of the reactor to air during loading and unloading. While insuring a high degree of cleanliness, the UHV-CVD system can produce high quality epitaxial films at temperatures lower than the other growth reactors through the use of lower growth rates. Growth in the UHV-CVD system takes place at a pressure of several micrometers ( % Torr). A hydride-based chemistry is used in this system: SiH, and GeH,. The growth temperatures employed in the UHV-CVD system are typically very low when compared to the growth of structures by the near atmospheric pressure growth reactors. Epitaxial growth of Si has been demonstrated at temperatures of 450-650 "C and at temperatures greater than 750°C. The intermediate growth temperature range (650-750 "C) typically leads to polycrystalline growth. The use of a particular system is dependent on a wide variety of concerns: device application, growth rate and thermal processing considerations, among others. There are common features of Si-CVD which come into play in the design of the operating conditions of the system. The limits to

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3 Epitaxial Growth

the range of operating conditions within the CVD reactor, for a given growth chemistry, are primarily dependent on the residual impurities within the growth system. These impurities, the most important being hydrocarbons and the oxygen-bearing compounds, such as H,O, lead to contamination of the growth front due to the high reactivity of the Si surface. The adsorption and incorporation of carbon and oxygen leads to a variety of deleterious effects, including the introduction of electrically active defects which can reduce device performance or yield a device inoperable. The adsorption of oxygen and carbon on the growth front additionally leads to morphological defects. Localized regions of oxidized Si prevent epitaxial growth from occurring often leading to no-growth regions. At lower oxygen coverages on the surface, the incorporated impurity can disrupt the transfer of the crystallographic information leading to the development of stacking faults and other defects. The tendency for Si to oxidize is very strong. The Si-0 or Si-C bonds readily form in preference to the Si-Si bond, with bond strengths of 191.1, 107.9, and 78.1 kcal/mol, respectively. In the case of oxygen, this strong bond indicates that the amount of H,O in the growth environment must be very small to prevent oxygen incorporation. The equilibrium amount of oxygen tolerated in the growth environment can be calculated through the use of equilibrium thermodynamics. Water and Si react to form SiO, according to the reaction Si+ZH,O o SiO,+ZH, (6) where the equilibrium coefficient is given by

In this expression, is the partial pressure in the system of a particular reactant and

AG,,, is the free energy of reaction. A similar calculation can be carried out for a variety of metal species as shown in Fig. 3-20 (Kuech et al., 1987). This figure indicates that at a growth temperature of 800°C, a H,O-to-H, ratio in the growth environment less than l o p 8is required. Within an atmospheric pressure reactor, this ratio indicates that a H,O concentration of less than 10 ppb is required in the inlet gas stream. The purification of the source gases is not complete enough to insure such high levels of gas purity. Water contamination in the reactor can also arise from adsorbed water on the components introduced into the reactor with the wafers, such as the wafer holders. This internal source of water can prevent the reactor gas phase composition from achieving such low levels of water content.

~~

500

~

600

700

aoo

900

Temperature ?C)

Figure 3-20. The H,O-to-H, ratio determined by thermodynamic equilibrium considerations can be used to provide guidelines on the required purity of a growth system. Values of the H,O-to-H, above a given line can lead to the formation of an oxide.

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The above argument is based on equilibrium considerations. At very low pressures and temperatures, these thermodynamic considerations do not adequately describe the growth environment due to kinetic limitations in achieving equilibrium. In such a case, the adsorption and incorporation of oxygen is limited by the kinetics of oxide formation and oxygen desorption from the growth front. Silicon can form other oxidebased compounds at high temperatures which also play a role in determining the surface concentration of adsorbed oxygen. In particular, the equilibrium between SiO, and 0, within the reactor can be shifted to favor an oxygen-free surface at very low pressures. SiO, and SiO, the high temperature monoxide, compete in the formation versus the removal of surface oxygen. These reactions reach a steady state with 0, and H,O in the reactor SiO, (solid)

=.

SiO(g)+t O,(g) (7)

versus Si(solid)+2H20 +. Si0,+2H2 and Si(solid)+O,

*

SiO,

(8) (9)

A low partial pressure of H,O and 0, in the reactor favors the formation of the volatile SiO. There is a limiting partial pressure at a given temperature of these reactants, below which the surface remains oxide-free. The Si surface then remains free of O-based contaminants allowing epitaxial growth at a low growth temperature. Figure 3-21 indicates this limiting partial pressure of H,O for the growth in the absence of a H, carrier gas due to the evaporation of S i 0 from the growth front (Ghidini and Smith, 1984).At a growth temperature of 650°C, a partial pressure of H,O less than Torr is required. In the case of a CVD system operating at atmospheric

155

pressure, this partial pressure indicates the inlet gases must have a H,O concentration less than about 1 ppb. Even if the inlet gases were purified to such a level, the residual adsorbed H,O on the mechanical parts introduced into the reactor could provide this partial pressure. There have been APCVD systems which have successfully grown Si at reactor temperature less than 800 "C. These systems have been designed with load locks to minimize introduction of gases from the ambient from entering the reactor and very careful purification of gases at the point of use. There are several ways to reduce the impact of the oxide formation on the epitaxial growth of Si. The two primary techniques are the choice of growth chemistry and the use of a low reactor pressure. Si sources containing chlorine have been used to provide a chemical pathway to remove oxygen from the growth front. SiO, can be etched in aqueous solution by HF at room temperature. At high temperatures, other halogen containing compounds can effectively etch the Si surface. During the initial heating of the wafer, HC1 is often introduced into the reactor to etch the Si surface. Silicon, and to a lesser degree SiO,, are etched at high temperatures, such as IOOO'C, through the formation of SiCl, Si+4HC1

o

SiC1,+2H2

SiO2+4HCl o SiC1,+2H2O

(10)

(11)

These etching reactions can remove the initial, chemically prepared, surface of the Si wafer. The chemically prepared surface typically has, in addition to an oxide layer, adsorbed carbon, and other impurities. This in situ or within-the-reactor etch process removes these surface impurities leading to the preparation of a fresh, atomically clean surface for epitaxial growth. These high temperature etching procedures do

156

3 Epitaxial Growth

lead to the redistribution of impurities, as would any high temperature process. In addition, the gas phase etching of Si sometimes preferentially occurs at defects within the Si layer. The HC1 etching process can decorate, through the preferential etching of material, the defect sites and result in a rough morphology of the growing surface. The use of chlorinated silanes during growth, i.e., SiCl,H,-,, allows any oxide which forms to be eliminated through a similar etching reaction. Reductions in the reactor pressure can also affect the range of epitaxial growth temperatures available. If the removal of oxygen from the Si growth front is limited by the formation and desorption of SiO, the reduction of the total reactor pressure insures that the partial pressures of H,O in the reactor is well below the limit required for surface oxide formation. A high purity gas flowing into a reactor at 0.01 Torr total pressure, for example, will have 100 ppb or less contaminants in it. The gas flow into the reactor will lead to a partial pressure of

\

10.8

impurities of z lo-' Torr. This results in a very low impingement and incorporation of impurities into the growing film. The equilibrium between SiO, and 0, within the reactor can be shifted to favor an oxygen-free surface, reducing SiO, through rapid desorption of SiO. According to Fig. 3-21, a reactor running at the pressure of 0.01 Torr and a typical level of carrier gas purity could possess an oxide-free surface for temperatures less than 600 "C. Much lower growth temperatures are achievable, in practice, using a UHV-CVD system. The advantage of an LPCVD system therefore stems from both the lessening of the mass transport limitations in the reactor as well as the production of epitaxial materials at a lower growth temperature.

3.6.1.2 Silicon Chemical Vapor Deposition: Growth Chemistry The growth chemistry used in the formation of epitaxial silicon has centered on

Oxidized Si Surface

_L \

c

109 6.0e-4

7.0e-4

8.0e-4

9.0e-4

inverse Temperature ( K ' )

1.Oe-3

1.1e-3

Figure 3-21. The evaporation of S i 0 from the growth front can lead to a clean Si surface. The balance between the oxide formation and oxide elimination represented in this figure can also determine guidelines for the purity requirements of a growth system with respect to oxygen and water.

3 . 6 Specific Epitaxial Systems: Materials and Growth Issues

157

100

10-1

10-2

't0 ,

the silanes, Si,H,,+ and chlorosilanes, SiCl,H,-, . The chlorosilanes have been generally used in higher pressure growth systems. The reduction of the oxygen incorporation during growth appears to be a key-advantage of these chlorinated growth sources. The chlorosilanes are very stable molecules with a range of free energies of formation as given in Table 3-2. The higher stability of the heavily chlorinated silanes increases the growth temperature required for deposition in the APCVD reactors. Figure 3-22 shows a comparison of growth rates for epitaxial Si grown using four Si precursors: SiCl,, SiH,Cl,, SiH,Cl, and SiH, (Bollen, 1978). The more highly chlorinated silanes lead to a reduced growth rate of Si under the same conditions. There are several other common features to the CVD of Si from this series of precursors. In each case, two temperature regimes of growth are noted in the figure. At low temperatures, the growth rate is strongly temperature dependent. This growth temperature dependence is attributed to the direct surface reaction of the Si precursor with the growth surface as being the rate-limiting step of the growth reaction. The greater stability of the Si source molecule results in a lower reactivity on the growth front with

Figure 3-22. A comparison of growth rates for epitaxial Si grown using four Si precursors, SiCl,, SiH,Cl,, SiH,Cl, and SiH,, indicates that the growth rate of Si from highly chlorinated sources is a function of the number of halogens on the source molecule.

a lower resulting growth rate. The specific surface reaction step responsible for the change in growth rate has not been determined. The suggested mechanisms for the limiting reaction step has been the desorption of hydrogen from the growth front or the surface decomposition of the chlorosilane. The desorption of hydrogen would make available additional surface sites for the adsorption of the Si-containing reactant. The surface coverage of hydrogen will be a function of the growth ambient and the wafer temperature. Higher growth temperatures lead to a reduced coverage of hydrogen on the surface leading to a potentially higher growth rate. An increased stability of the growth source can also lead to a reduced surface reactivity. Stable growth sources can desorb from the surface before they undergo a surface decomposition reaction. This desorption then eliminates the Si nutrient from the surface, again leading to a reduced growth rate. In practice, it is difficult to discern a particular mechanism and the actual growth chemistry is undoubtedly more complex than these simple suggestions imply. The other growth regime shown in Fig. 3-22, exhibits a weak or nearly temperature-independent growth regime. This

158

3 Epitaxial Growth

weak temperature dependence is indicative of a mass transport limited growth behavior. In this case, the surface reactions are very fast and the gas phase concentration of the nutrient close to the surface is near zero. The surface reaction consumes all the available reactants as they reach the surface. The rate limiting step to the incorporation of Si into the growth front is then the transport of the growth reactant in the gas phase to the growth front. The growth rate would then have a temperature dependence characteristic of the gas phase diffusional transport. This diffusional transport has a power-law like dependence as discussed in Sec. 3-2. The transition between the surface reaction limited and the mass transport limited growth regimes occurs at increasingly high temperatures as the stability of the growth precursors increases. The choice of growth precursors therefore depends strongly on the required growth rates, the allowable thermal budget for the device being fabricated, and the background impurity levels in the inlet gas stream. The growth chemistry employed in the has been UHV-CVD of Si and Si,Ge, -, largely based on the hydrides of Si and Ge: SiH, and GeH,. The growth temperature range of UHV-CVD is determined by the kinetics of hydrogen adsorption. The wafer preparation, immediately prior to its introduction into the reactor, often includes a final oxide removal from the chemically prepared surface through the etching of the surface in an H F / H 2 0 solution. This HF/ H 2 0 oxide removal step can leave the surface H-terminated. The H-terminated surface has all available adsorption surface sites populated. The H-termination leaves the surface very inert since the oxygen and H 2 0 in the room ambient cannot adsorb and subsequently react to form a surface oxide. This treatment has a limited lifetime

since even at room temperature some hydrogen will eventually be displaced by oxygen. This pre-growth treatment introduces an oxide-free but hydrogen-terminated surface into the reactor. The wafer does not require additional etching provided the hydrogen passivation remains intact until growth. As the growth temperature is increased the hydrogen will desorb until at very high growth temperatures, greater than 750"C, there is little or no hydrogen adsorbed on the surface at steady state. The epitaxial growth of Si in UHV-CVD can take place under two very different growth temperature regimes. Epitaxial growth has been carried out at low temperatures, from SiH,, over the range 5 650 "C and at higher tem450°C 5 Tgrowth 2 750°C. This bistable peratures of Trow,,, growth temperature regime is directly related to the hydrogen-termination of the surface and the need to preserve an oxidefree surface during growth. At the low temperatures, the extrapolation of the data given in Fig. 3-20 indicates that the H 2 0 partial pressure in the reactor must be below IO-', Torr in order to maintain a clean surface. The inlet gases cannot be purified to the levels required to produce such an environment. Two factors within the UHV-CVD system assist in preventing the formation of the surface oxide and in maintaining a low H 2 0 content growth environment. The internal surfaces of the UHV-CVD reactor becomes coated with Si in the process of the Si growth. This internal surface coating of poly-crystalline Si provides a large reactive surface area for the reaction and removal from the gas stream of any oxygen containing species prior to its arrival on the wafer surface. The removal of impurities from the gas stream within the reactor is referred to as in situ gettering. The second factor which impedes the formation of


the oxide layer on the Si surface is the hydrogen passivation. Just as the hydrogen prevents surface oxidation in the environment external to the reactor, the hydrogen on the Si wafer prevents some of these oxidants in the growth environment from reacting with the growth surface through the lack of reactive adsorption sites. High growth temperatures enhance the removal of hydrogen from the growth front. However at the low temperatures, the surface of the growing film is replenished with hydrogen which is produced from the growth reaction. On such a surface, the reaction sequence would have the SiH, decomposing initially through the sequential elimination of hydrogen to the surface

+

SiH,(g) + 2 Sisurf=. SiH (ad) (1 2) + SiH, (ad)+ Si (solid)

-

SiH,(ad)+Sisurf=. SiH,(ad)+SiH(ad) (13) 2SiH,(ad)

SiH(ad)+H,(gas) (14)

2SiH(ad) =. Si(solid)+H,(gas) (15) where Sisurfis a Si surface site and the subscript ad refers to an adsorbed species. While this is a proposed mechanism, the primary implication of these reactions is that the hydrogen can be replenished to the surface provided a sufficient SiH, overpressure is maintained. In practice, a SiH, over-pressure is always provided over the wafer as it heats up in the reactor. This SiH, over-pressure insures that a SiH, molecule is available for adsorption onto the surface when a site becomes available due to hydrogen desorption. In the UHV-CVD process, the rate limiting step to Si epitaxial growth is the desorption of the hydrogen from the surface allowing for the subsequent adsorption and decomposition of the SiH, source. Since mass transport limitations are absent in this growth technique, the overall reaction

159

scheme is quite simple, based on the rate of desorption of H, from the growth surface, allowing additional SiH, to adsorb, and subsequent hydrogen removal from the SiH, to the growth surface. The epitaxial relationship is maintained through the lateral diffusion of the deposited Si atoms over the surface after SiH, decomposition on an appropriate Si surface site. The growth of the semiconductor alloy Si,Ge, - x utilizes the co-introduction of SiH, and GeH, into the reactor. The growth of the alloy system is complicated by the effect of Ge addition to the hydrogen desorption process. The Ge-H bond is much weaker than the Si-H bond (20 versus 38 kcal/mol). The presence of Ge on the growth surface, when growing Si,Ge, - x , leads to the enhanced desorption rate of hydrogen from the surface. Hydrogen attached to surface Ge is easily desorbed, again opening new adsorption sites. The SiH, and GeH, compete for these new surface adsorption sites. The GeH, is more efficient at adsorption and decomposition, leading to an enhancement of the Ge/Si ratio in the films over the gas phase ratio, shown in Fig. 3-23 (Meyerson et al., 1988). The rapid desorption of hydrogen from the Ge sites also leads to a non-linear growth rate with Ge composition in the solid as seen in Fig. 3-24 (Meyerson et al., 1988). If the ability to adsorb on the growth front were the same for both these sources, a constant growth rate would result. The chemical modification of the surface kinetics leads to an overall increased growth rate of the alloy system over Si with a comSi,Ge, -, plex growth behavior resulting from this surface chemistry. 3.6.1.3 Heterojunction Formation

The utility of the epitaxial growth of Si is not limited to the growth of epitaxial layers

160

3 Epitaxial Growth

15

i

e e

e

0

I

I

I

J

5

10

15

20

Percent Ge in the Gas Phase

0

I

I

I

I

I

2

4

6

8

10

Percent Ge in the Gas Phase

Figure 3-23. GeH, is more efficient than SiH, at adsorption and decomposition, leading to an enhancement of the Ge/Si ratio in the films over the gas phase ratio.

Figure 3-24. The rapid desorption of hydrogen from the Ge sites also leads to a nonlinear growth rate dependence on Ge composition in the solid.

with controlled electrical properties, as in a pn junction. The growth of the alloy semiconductor, Si,Ge,-., on Si allows for the development of many advanced device concepts which utilize the controlled compositional control across a heteroepitaxial interface as the composition is altered during growth. The change in composition must often be very abrupt, over a few nanometers, in order to effectively utilize the change in electronic structure in a device. The abruptness of the interface is directly related to the change in composition of the gas phase ambient out of which the film is growing. In the UHV-CVD growth system, the gas residence time in the reactor is very small. The residence time is defined as the volume of the reactor divided by the volumetric flow rate into the reactor. The UHVCVD systems have residence times of less than a tenth of a second under most growth conditions. The growth rate is very low in these systems, typically only a few nm/min. The short residence time insures that the

growth ambient can change within a fraction of a monolayer of growth. The resulting junctions are abrupt to about a single monolayer within the crystal. The final structure will, of course, be modified through thermal inter-diffusion. The residence time of gases in the APCVD system is not as low as in UHVCVD. This is because APCVD systems typically have larger volumes and lower volumetric flow rates. An additional complicating factor is recirculation within the gas phase environment of the reactor. If the gases within the reactor are susceptible to thermal convection, the convective rolls formed in the reactor act as a reservoir for the unused reactants and reaction by-products. While the simple calculation of the residence time may indicate that there is no difficulty in achieving abrupt junctions, these hydrodynamic effects can lead to the slow grading of the composition and a resulting poor heterointerface.


3.6.1.4 Impurity Incorporation

The controlled placement of impurities within the growing layer is required to define the electrical properties of the epitaxial thin layers comprising the device structure. The introduction of impurities during epitaxial CVD growth requires appropriate gas phase sources. In general, Si-CVD utilizes the hydrides of the impurity. The most common of these sources for Si doping are ASH,, PH,, and BZH6, These are conventient sources for Si doping since they are all gases at room temperature and can be easily handled. These gases, like SiH, and GeH,, are toxic and, in many cases, pyrophoric. The intentional incorporation of impurities requires their controlled introduction into the reactor. The rate of impurity incorporation depends on the nature of the dopant source, growth temperature and the growth surface. The dopant source is introduced into the reactor in a highly diluted form so that the ratio of dopant to growth source, e.g., PH,/SiH,, is very low. The solid concentration of the dopant will be very low, typically within the range of cm-,. The addition of these low levels of impurities can also alter the growth reaction itself due to surface interactions. The addition of PH, or ASH, during the growth of Si from SiH, leads to a dramatic decrease in the growth rate of the film (Farrow, 1974). These hydrides adsorb strongly on the Si surface and subsequently decompose slowly compared to SiH,. The strong impurity adsorption, combined with the low decomposition rates, leads to the accumulation of PH, on the Si surface. Many of the available surface sites are no longer available for SiH, adsorption and hence the growth rate drops significantly. The group I11 hydride, B2H6, can result in a very different reaction. Boron is the most

161

common acceptor in Si and Ge. In contrast to the case of ASH, and PH,, B,H, addition to the gas phase leads to an enhancement of the Si growth rate from SiH,. This effect is presently not well-understood. The presence of a p-type layer near at the growth front is believed to facilitate the desorption of H from the surface leading to the opening of new adsorption sites for the SiH,. As described above, the rate limiting step to the Si growth in many cases is the hydrogen desorption from the growth front. These chemical modifications to the growth front, through the addition of impurities, can alter the overall growth chemistry, despite their low inlet concentrations. The final impurity distribution in CVD systems will be affected by the same residence time considerations, considered above, as well as these additional chemical complications. The impurity profile generated during the growth of the multi-layer structures will be further modified by any thermal processing which will cause solidstate diffusion of the impurities. 3.6.2 GaAs MBE

GaAs is among the best characterized materials grown by MBE. While there are many variations for MBE growth of GaAs, by far the most common MBE technique utilizes elemental sources of Ga and As. These elements are held in effusion cells at temperatures required to achieve the necessary flux for growth. Ga cell temperatures of around 1000°C are required in order to produce an appreciable flux to the surface. The higher vapor pressure of As results in an As cell temperature of around 300-400 "C. Typical substrate growth temperatures are 600-700°C. The growth of GaAs under these conditions can be modeled using the following simplified assumptions: 1) the sticking coefficient of the

162

3 Epitaxial Growth

group111 element (Ga) is unity; 2) only enough group V component (As) is incorporated to achieve stoichiometric GaAs; and 3) GaAs growth is almost always performed under As-rich conditions and the growth rate is controlled by the group I11 Ga incident flux. GaAs (and most compound semiconductors) do not evaporate congruently. In the case of GaAs, non-congruent evaporation implies that above z 650 “C, As evaporates preferentially from the crystal in the form of As,. At even higher temperatures, Ga will also begin to evaporate. Since these temperatures are within the typical growth temperature range, the substrate must be heated and cooled under an ‘over-pressure’ of As to avoid dissociation. The ‘over-pressure’ is provided by a flux of As species, typically As, or As,, onto the growth front. Since solid elemental As is most commonly used as the arsenic precursor, the predominant sublimed species is As,. In some systems this is further cracked at temperatures of x 900 “C to produce As,. When As, is the predominant species, the generally accepted growth model is that two chemisorbed As, species react with each other to produce GaAs and As, which is then desorbed. A simplified overall reaction is as follows: 4Ga+2As4

o

4GaAs+As,

(16)

When the As flux is greater than the Ga flux, there is a high probability that most adjacent sites will be populated with As, species. In this case, the growth rate will be limited by the flux of Ga to the surface, reacting with the adsorbed As,. However, if the As flux is similar to the Ga flux, the rate limiting step is determined by the probability of two As, species meeting and reacting. The model for GaAs growth from Ga and As, is less complex. The As, species is chemisorbed on the surface, in this

case, and reacts with surface- adsorbed G a to form GaAs. It is commonly stated that As, has a sticking coefficient close to 1 whereas As, has a maximum sticking coefficient of 0.5. It has been suggested that As, should then be a better, more efficient source of As for the growth of these compounds. ASH, is a less common As source in MBE. There are several attractions to the use of ASH,. Since ASH, is a gas, ASH, is supplied from a tank outside of the system, and the system does not have to be opened to replenish the As source as is necessary when reloading elemental As into an effusion cell. Another advantage of ASH, is that the flux can be accurately controlled using mass flow controllers which have a much faster time response than thermal effusion cells. Finally, ASH, may be dissociated using a high temperature cracker, leading to the possibility of choosing the incident As species. Disadvantages of ASH, include the added complexity of the pumping system and the large safety infrastructure required for the use of this toxic and hazardous gas. The elemental Ga metal used as a growth source is typically evaporated from an effusion furnace. These effusion sources do have complications. Ga or Ga-related oxide impurities from the cell may be ejected onto the substrate. This effect has been referred to as ‘Ga spitting’. The Ga droplets or oxides deposited have been related to pit and hillock type defects in the grown layer. Reduction of the density of these defects has been accomplished by careful attention to detail in preparing the Ga furnace to eliminate all impurities as well as modified effusion furnaces which have a hotter lip to prevent condensation of Ga at the end of the furnace. GaAs growth is usually performed on a GaAs substrate. These are typically

163


cleaned ex situ using a combination of solvents and acids. Recently so called “epiready” substrates have become available that eliminate the necessity of ex situ cleaning. After introduction to the system and outgassing in the buffer chamber, the substrates are heated prior to growth to desorb the native oxide. This is done in an As flux and the desorption temperature is ~ 6 0 0 ° CThe . RHEED system is used to determine when the oxide has been desorbed. As mentioned previously, GaAs growth is almost always performed in an As-rich ambient. Since the Ga sticking coefficient is about 1, if growth takes place in a Ga-rich ambient, the morphology degrades and eventually the growth becomes non-epitaxial. In the (001) orientation, GaAs consists of alternating layers of Ga and As. Depending on the As and Ga fluxes, an As- or Ga-stabilized surface can be obtained. However, the Ga-stabilized surface is difficult to maintain without morphology degradation. The surface reconstruction is determined using RHEED. The Asstabilized surface has a c(2 x 8) structure while the Ga-stabilized surface has a centered c(8 x 2) structure. Standard pregrowth treatment would consist of heating the substrate in an As flux, desorbing the oxide and obtaining an As-stabilized surface. The surface reconstruction during growth is determined by the As/Ga or V/III ratio. This is a very important parameter, affecting not only the structural but electrical and optical properties of the grown films. Typically growth is carried out with an As/Ga ratio about 1-2; i.e., a ratio that just results in an As-stabilized surface. While the As and Ga fluxes can be estimated from the beam equivalent pressures (BEPs), it is common to determine the desired conditions by examination of the

RHEED pattern and the properties of the grown films. High As/Ga ratios have been shown to result in increased densities of deep levels (Stall et al., 1980), and electron traps (Neave et al., 1980).This relationship is especially strong at low growth temperatures. Typical growth temperatures for GaAs are in the range of 600-650°C. While epitaxial films can be grown at much lower temperatures, the density of electrically and optically active defects strongly increases below about 600 “C. The growth temperature is also determined by the type of device being grown. Electrical devices are usually grown at lower temperatures than optical devices. The lower temperatures result in less impurity incorporation from hot system parts. Optical devices are grown at higher temperatures. The main reason for this is that the luminescence efficiency greatly increases with increasing growth temperature. Figure 3-25 (Cho, 1985a) shows a plot of PL

GaAs ACTIVE LAYERS d

01

-

0.15 - 0.2prn

1

I

I

I

I

450

500

550

600

650

SUBSTRATE TEMPERATURE

(‘c)

Figure 3-25. The photoluminescence intensity obtained from the GaAs active region in a double heterostructure or DH laser increases strongly with growth temperature. The arrows indicate the order in which the samples were grown.

164

3 Epitaxial Growth

intensity from GaAs active layers in a double heterostructure (DH) laser as a function of growth temperature. It is clear that the radiative efficiency strongly increases at higher growth temperatures. The high growth temperatures result in a reduction in the incorporation of oxygen, which acts as a deep level and a non-radiative recombination site. This increase in luminescence efficiency with increasing temperature is even stronger for A1,Ga -,As, where growth temperatures above 700°C are routinely used. However, high temperature growth is complicated by desorption of Ga from Al,Ga, -,As. At high tetmperatures, G a evaporates off the growing surface, resulting in a higher mole fraction of AlAs in the layer as well as a thinner layer. These effects are accounted for empirically and “calibrated out” in high temperature growth. A major advantage of MBE is the ability to determine the growth rate in situ using RHEED. This is done by observing the intensity oscillations in the specularly reflected RHEED spot from the As-stabilized (2 x 4) pattern. The intensity of this spot oscillates with a period that corresponds to one monolayer (Ga + As layer, z 2.83 A) of growth. The oscillations begin as soon as the Ga shutter is opened and stop when it is closed. The growth rate can then be determined by calculation of the period of the oscillations. This technique can also be applied to the growth of AlAs. The cause of the intensity oscillations is believed to be due to the growth mode, which results in a variation in the “smoothness’’ of the surface on a monolayer scale, (Neave et al., 1983). Figure 3-26 shows schematically a model for this type of growth model (Cho, 1985a). At the beginning of growth the surface is smooth and the electron beam is strongly reflected from the surface. Nucleation then begins to oc-

Figure 3-26. Growth of GaAs showing surface variations resulting in RHEED oscillations. 8 = O represents the initial or smooth surface. Fractional 0 values represent partial coverage of one monolayer.

cur at random locations across the surface. When the surface coverage 8 is about 50%, the surface has the most “roughness”, i.e., half the surface is one monolayer above the original surface, but in a random fashion. The reflectivity of this rough surface is at a relative minimum. As growth proceeds, the surface coverage increases and eventually a smooth surface is again achieved. Here,


like at the beginning, the reflectivity is at a relative maximum. If growth were to proceed in this mode, the reflections would be observed indefinitely.In most cases, the oscillations decrease in amplitude. This has been attributed to nucleation of a second layer on a lower layer that has not yet achieved 100% coverage. Unintentionally doped GaAs grown by MBE is typically p-type with carrier concentrations in the 1014 cm-3 range. Carbon has been identified as the dominant residual acceptor by PL and temperaturedependent Hall measurements. While not completely identified, the major suspected sources for C in the MBE system are residual hydrocarbon gases such as CO or CO, . Other residual impurities in unintentionally doped GaAs include silicon, manganese (from hot stainless steel), sulfur (from the As source), and oxygen (residual 0, and H2O). A great deal of effort has gone into increasing the purity of undoped GaAs. First, the growth chamber and sources must be of the highest purity. The growth chamber and all components must be thoroughly baked to desorb as much water as possible. Sources also must be outgassed at temperatures above where they will be used. Liquid nitrogen cryoshrouds (shown in Fig. 3-18) greatly reduce the residual partial pressure in the system, especially of H,O. Finally, for the highest purity, only the required cells should be kept hot and all ion gauges and ionization sources should be turned off to prevent decomposition of any residual gases. Modern MBE systems are designed to address most of these issues. However, the highest mobilities are only achieved through detailed and dedicated efforts - the highest 2DEG (twodimensional electron gas) mobility in GaAs/Al,Ga, -,As was achieved in a specialized dedicated system with high pump

165

speed cryo-pumps and an 8 week bake prior to growth (Pfeiffer et al., 1989). Many elements have been used for intentional doping of GaAs by MBE. Donors include silicon, tin, germanium and carbon. Acceptors include beryllium, magnesium, manganese, carbon, zinc and cadmium. Figure 3-27 (Cho, 1985b) shows the doping concentration of a number of donors and acceptors in GaAs as a function of effusion cell temperature. This figure indicates the wide range of carrier concentrations achievable for both donors and acceptors in GaAs. Silicon is typically the donor dopant of choice because of its well-behaved characteristics and small ionization energy ( x 5.8 meV below EJ. Silicon incorporation varies inversely with the growth rate and is relatively insensitive to the growth temperature. The highest electrical carrier concentrations grown with silicon are about IO1’ ~ m - ~ . . Tin has a similar ionization energy and maximum carrier concentration as silicon. However, tin incorporation is quite sensitive to the growth temperature and it tends to accumulate at the growing surface. However, tin has much less of a tendency to occupy both Ga and As sites (amphoteric nature) and no SnAs-related recombination peaks have been observed in the luminescence spectrum of tin-doped GaAs. For this reason, tin is often the preferred dopant for lasers. Germanium is not widely used, but is of interest because of its strong amphoteric nature (Kunzel et al., 1980; Heckingbottom and Davies, 1980). Depending on the As/Ga ratio and the substrate temperature, Ge can be an acceptor or donor. p-n junctions have been demonstrated using only Ge by changing from As- to Ga-stabilized growth conditions (Cho and Hayashi, 1971).

166

3 Epitaxial Growth TEMPERATURE ('C)

-a a

0 t I

J J w

V

5 W

a

3

v)

v)

W

a

n

a 0

n

a

>

0.700.75 0.80 0.85 0.90 0.95 1.0

1.05 1.10

Beryllium is the most common p-type dopant. Be forms a relatively shallow acceptor ( x 19 meV above E,,) and has wellbehaved incorporation characteristics. In ~ ) addition, very high (lo2' ~ m - carrier concentrations can be achieved. The major disadvantages of Be are its toxic and carcinogenic nature, the fact that it is very reactive with oxygen species and the inability to obtain Be in a purity comparable with other elemental sources. Magnesium is only incorporated eficiently at temperatures below about 500°C. It could be preferable for low temperature growth because it is less toxic than Be. Zn and Cd have vapor pressures too large to make them useful for MBE doping. Manganese produces a relatively deep acceptor ( ~ 9 meV 0 above E"), but has a number of complications in the growth such as surface accumulation and strong dependencies on growth conditions that make it almost impossible to use.

1.15 1.20 1.25

Figure 3-27. The doping concentration of several donor and acceptor elements in GaAs is a strong function of effusion cell temperature due to the exponential dependence of the elemental vapor pressure on the temperature (assuming unity sticking coefficient at the growth surface).

3.6.3 Growth of AlGaAs by LPE The actual practice of LPE can best be described in the context of the formation of a particular materials system. A wide variety of Al,Ga,-,As-based LED and laser devices have been grown by LPE. In this section we will discuss the growth and doping of AlGaAs by LPE. As discussed above, the starting point for LPE growth is the phase diagram. Figure 3-28 (Cassey and Panish, 1978) shows the phase diagram for the ternary compound Al,Ga, -,As. This diagram focuses on the liquidus and solidus lines; the details of the diagram near the As end are not shown here. The shaded area represents the ternary liquidus compositions that can be in equilibrium with the solid. The hatched area represents the solidus compositions. The binary solids GaAs and AlAs are fixed at the midpoints of the sides of the triangles between Ga and As and A1 and As. Figure 3-29 (Stringfel-


Figure 3-28. Liquidus and solidus phase diagram for A1,Ga1-,As which is used in the LPE growth of this material.

r

GaAs

I

X

AlAs

Figure 3-29. Pseudobinary section of the phase diagram, shown in Fig. 3-28, which indicates the solid composition in equilibrium with the liquid melt at a given temperature.

low, 1982) shows a section of this diagram cut parallel to the temperature axis and is sometimes called the pseudobinary section. This can be used to determine the composition of the solid that is in equilibrium with a given composition liquid at a specific temperature. This figure also shows that the composition in the solid is significantly higher than that in the liquid. This is demonstrated in more detail in Figs. 3-30 and 3-31 (Casey and Panish, 1978). Fig-

167

ure 3-30 shows the liquidus isotherms in the Al/Ga/As system while Fig. 3-31 depicts the solidus compositions in the solid as a function of the liquidus composition. These figures exhibit in more detail that the AlAs mole fraction in the solid is significantly larger than the A1 percentage in the liquid, and this ratio increases with decreasing growth temperature. The large difference between the mole fractions of A1 in the liquid and the solid leads to difficulties in composition control. Small errors in the amount of A1 in the melt will have a large impact on the AlAs mole fraction in the growing solid. Furthermore, the small amount of A1 in the melt can be rapidly depleted, which will lead to further compositional grading within the layer. Finally, any solution carry-over from an A1 containing melt to a non-A1 containing melt will cause significant unintentional A1 incorporation. As stated above, the phase diagram is the starting point for determining the growth parameters. As an example, we will determine the melt composition for the growth of Al,~,,Ga,,,,As at a growth temperature of 900°C. It should be noted that the solid composition and the growth temperature are all that are theoretically required, along with the phase diagram, to determine the melt composition. The atomic fraction of A1 in the melt X,, is determined to be 3 x l o p 3using Fig. 3-31. Figure 3-30 indicates that the atomic fraction of As in the liquid X,, is 5 x lo-' with x,,=I- XA,-XA, = 9.47 x lo-'. The atomic fractions of the melt constituents are then converted to weights using the formula

N, xi=3

crv,

j= 1

(3-36)

168

3 EDitaxial Growth L

4

a

X

.-da

w

3

Figure 3-30. Liquidus isotherms in the Al/Ga/As system as a function of temperature. O.OO0

0.002

0.004

0.006

0.008

0.010

0.012

0.016

0.014

A1 Atom Fraction in Liquid, X AI

.o

1

0.9

0.8 e,

0.7

.-

0.6

5

e

0.5

0.4 0.3

a

0.2

0.1 0.0 5

6

10-3

2

3

4

5

6

10-2

2

3

4

5

6

10-1

Figure 3-31. Solidus composition in the solid Al,Ga, -.As as a function of the liquidus composition.

AI Atom Fraction in the Liquid

or

determined using (3-38)

is the weight and M i is the atomic where W. weight of each component, the number of moles being K.= v . / M i . The Ga component makes up the bulk of the melt and hence determines the capacity of the system. In this example we use l o g of Ga which is NGa = 0.143. The respective number of moles of the other constituents are

and (3-39) We find from these equations that NA,=7.57 X and NA,=4.54X w4. The weights of As and A1 are determined,


using the molecular weights, to be WAS = MA,NA,=74.9

= 5.67 x

x 7.57 x lo-’

to-’ g

WA, = MAINA, = 27.0

= 1.23 x lo-’ g

(3-40) x 4.54 x

(3-41)

W,,=lOg Using this method, the composition of the melt can be determined to produce a specific solid composition of Al,Ga, -,As. It should be noted that as the A1 mole fraction X in the solid is increased, the mole fraction of As in the melt is decreased. Since the growth rate is limited by diffusion of As to the substrate, for a given supersaturation, the growth rate will decrease as the A1 mole fraction X in the solid is increased. This effect can become quite significant, a decrease of a factor of five in growth rate has been observed when X is increased from 0 to 0.8 (Wu and Su, 1989). Preparations for growth begin by loading the Ga into the boat. The system is then pumped and purged. The Ga melt is then outgassed to reduce its impurity concentration. Outgassing is performed for 1020 h in purified hydrogen at a temperature equal to or greater than the growth temperature. After outgassing, A1 and As are added. If the two-phase method is used, then GaAs would be added to the melt in the form of a substrate. As long as there is more than 5.67 x lo-’ g of As in GaAs (for the growth example given above), the solution will automatically come to equilibrium. Addition of these elements can be done by opening up the system, or in situ, using specially designed reactors, to prevent exposure to air and water vapor. The melt is then heated to slightly above the growth temperature for several hours allowing the melt to come to a state of equilibrium. Growth can then proceed using either ‘equilibrium’ or step cooling. Typical

169

growth temperatures for (A1,Ga)As are in the range of 80O0C, while typical cooling temperatures are in the range of several tenths to one degree per minute. Growth of AlGaAs is complicated compared to GaAs because A1 will oxidize if there is any oxygen present and form Al’O,. This forms a stable skin which floats to the top of the melt. However some Al,O, will be present at the substrate-melt interface; this interferes with the growth causing defects in the grown layer. The formation of Al,O, is reduced by removing all sources of oxygen. Careful preparation, outgassing of source materials, the use of purified hydrogen as carrier gas and techniques for in situ loading of A1 into the Ga melt have all been developed in order to produce high quality (A1,Ga)As. Special boat designs have been developed to separate the oxide floating on the top from the rest of the melt prior to growth (Lu et al., 1992). Unintentionally doped (A1,Ga)Asgrown by LPE is n-type. The impurities responsible for the n-type conduction are sulfur and silicon. Typical carrier concentrations for Al,Ga,-,As are in the low 10I6cm-3 range for OcxcO.35 (Wu and Su, 1989). There are other complicating factors associated with the heteroepitaxial growth of Al,Ga, -,As. Since Al,Ga, -,As is not typically grown on another Al,Ga, -,As layer of the same composition, it is important to understand the effect of growth on different compositions. It has been observed that in the growth of GaAs/Al,Ga, -,As quantum wells, the interface between the bottom Al,Ga, -,As barrier and the GaAs well can be made quite abrupt, whereas the interface between the GaAs well and the top Al,Ga, -,As barrier is much less abrupt (Chen et al., 1989). The reason for this is that the chemical potential for Al,Ga, -,As is lower than that of GaAs, in other words,

170

3 Epitaxial Growth

the effective saturation is less, and Ga etch melt-back will occur. Etching instead of growth initially takes place, therefore, when the Al-Ga-As melt is brought into contact with the GaAs well. In severe cases, the GaAs well can be locally etched away completely. This effect can be mitigated by using a different melt that has a higher supersaturation. The higher supersaturation effectively prevents melt-back, since a higher driving force for deposition is present, and results in an improved interface at the GaAs-to-Al,Ga, -,As junction. The last issue in LPE is the intentional incorporation of impurities. A wide range of elements have been investigated for donor and acceptor impurities in LPE grown A1,Ga -.As. Group I1 elements, such as Zn and Cd, are acceptors, while S,Se and Te are donors. Group IV elements Si,Ge and Sn are amphoteric. These elements can be incorporated on either the column I11 or column V sub-lattice resulting in either donor or acceptor behavior, respectively. The site dependence of the incorporation of these elements depends on the growth conditions, such as growth temperature and liquidus composition, as well as stoichiometry of the solid.

3.6.4 InP Metal Organic Vapor Phase Epitaxy (MOVPE) The growth of 111-V semiconductors is the most widespread application of the MOVPE technique. There are many features of the MOVPE growth process which are common to most of these materials systems. This section will look at the growth of InP as an example of this technique. The growth temperature dependence, influence of reactor chemistry, and the reactor pressure effects discussed in reference to InP growth will also be found in the growth of GaAs, A1,Ga -,As, and other technologi-

cally important materials. This section will present both the chemistry of InP growth and some of the growth related behavior connected with doping and other issues. The growth of InP and related compounds has progressed from research scale to production over the last decade, mainly driven by applications for light emitters in the 1.3-1.55 pm range for optical fibers. InP and related InGaAsP alloys have direct bandgaps and thus emit light very effciently. The presence of lattice-matched ternary and quaternary alloys and the ability of InP to produce high quality regrown layers has resulted in a very large number of laser structures, including buried heterostructures and ridge waveguides. Electronic applications include devices such as heterojunction bipolar transistor and modulation doped FETs. All of these devices utilize InP substrates and epi-layers in conjunction with ternary and quaternary layers of (In,Ga,Al)(As,P)to form the heterostructures. Two technologically important lattice-matched ternary compounds are In,~,,Ga,,,,As with a bandgap of 0.75 eV and Ino.52Alo,48As with a bandgap of 1.46 eV. Quaternary compounds utilizing InGaAsP, InGaAlP, etc., can provide lattice matched layers over a wide range of bandgaps. InGaAlP alloys have recently been used to produce extremely efficient light emitters in the yellow-orange color range. Trimethyl indium (TMI) and triethyl indium (TEI) are the main In precursors, while phosphine (PH,) is the major phosphorus source. Both 'TEI and TMI are stored in a bubbler, however, TEI is a liquid while TMI is a solid. The vapor pressure of TMI is also about 10 times higher than that of TEI. Much of the early MOVPE work on InP utilized TEI. InP grown using TEI and PH3 appeared to be more reproducible than TMI-based growth.


The delivery of a reactant from a bubbler containing a liquid is much more reproducible and stable than that from a solid. One problem with the use of TEI for the growth of InP results from its room temperature reaction with PH, creating an involatile adduct, removing reactant from the inlet gas stream and thus leading to poor growth uniformity. While lower reactor pressures suppress adduct formation, TMI has generally supplanted TEI for the growth of indium and phosphorous containing compounds. An advantage of TMI is its higher vapor pressure, which reduces the problem of condensation in the gas delivery lines. Tertiarybutylphosphine (TBP) has recently been developed as an alternate P source. TBP is much less hazardous than PH, since it is a liquid with a much lower vapor pressure than the compressed gas, PH,. TMI decomposes at temperatures in the range of 300-400 "C. The decomposition temperature is somewhat dependent on the ambient. In H, and D,, the pyrolysis reaction was found to be a homogeneous gas phase reaction. The decomposition of TMI in D, results in the formation of CH,D and C,H, (Buchan et al., 1988).The carrier gas is found to participate in the decomposition process as seen in the formation of CH, from CH, and H, . The TMI decomposition process is however modified by

v 0 0

0

the presence of PH,. TEI has been less studied than TMI. A major feature of TEI is that its gas phase pyrolysis temperature is lower than TMI. Phosphine decomposes at substantially higher temperatures than TMI. In Fig. 3-32 (Buchan et al., 1987), curve (a) indicates of the PH,, by itself, in D, is that ~ 5 0 % decomposed at about 520 "C. However, the decomposition is strongly catalyzed by the presence of an InP surface, as shown in curves (b)-(d) obtained with increasing amounts of TMI added to the ambient. Several interesting features are seen in this figure. The pyrolysis temperature of PH, is greatly reduced by the addition of TMI. Additionally, the pyrolysis temperature of TMI is also lowered by about 50°C from that observed for TMI alone. Finally, the shape of the TMI+PH, reaction curves show that part of the PH, decomposes at a low temperature with the remainder still decomposing at the higher temperature, indicating that PH, can react with the TMI at very low temperatures. In contrast to the decomposition of TMI alone, TMI with PH, produces only CH, and no CH,D when decomposed in a D, ambient. The gas phase decomposition mechanism is therefore different for the TMI/PH, mixture than for the individual precursors alone. The proposed model for decomposition of this mixture postulates

15%/0%/85% 15 / 0 . 3 2 / 8 4 7 1.5/0.36/98.1 0.5 / 0 . 2 4 / 9 9 . 3

v -

200 250 300 350 460 4 5 0 500 550 600 650 700

Temperature

("CI

171

Figure 3-32. PH, pyrolysis as a function of temperature for PH, alone, and with increasing concentrations of TMI. The ratios of PH, :TMI are 41,4, and 2.

172

3 Epitaxial Growth

that the TMI and PH, react to form a gas phase complex or adduct which then decomposes through elimination of CH,. This reaction, in which only CH, is produced, does not require the participation of the carrier gas, D, (H,). The methane elimination process may occur in both the gas phase as well as on the substrate, generalizing the results from purely gas phase decomposition studies. TBP has been investigated as an alternative source to PH,. The two major reasons for desiring an alternate source are the relatively high decomposition temperature of PH, and its high hazard and toxicity levels. PH, is supplied as a gas in high pressure cylinders and has a threshold limit value (TLV) of 300 ppb. The high pressure storage of PH, gives rise to the potential hazard associated with PH,. TBP is supplied as a liquid with a vapor pressure of 266 Torr at 25 "C. Thus, although the TLV is similar to that of PH,, TBPs much lower vapor pressure greatly reduces the hazards involved in storage and use. Advances in the purification of TBP have permitted the growth of InP with purities rivaling those produced using PH,. InP is usually grown on (001) oriented InP substrates with a mis-cut of 3-5" towards a (011) direction. InP wafers are similar to GaAs substrates in their chemical and structural properties and are relatively fragile when compared to silicon. The use of vicinal substrates result in better morphology compared to exactly on-axis or no-miscut wafers. InP substrates are typically cleaned for growth using a polishing chemical etch. The purpose of this etch is to remove a thin surface region that contains residual polishing damage. The etch is usually composed of DI water, sulfuric acid and hydrogen peroxide. After rinsing in DI water and drying in clean N,, the substrate is loaded into the reactor.

As with GaAs, the group V element, P, is more volatile than the group 111 element, In, and thus InP substrates must be heated in an over-pressure of P to prevent the surface decomposition of the substrate prior to epitaxial growth. In MOVPE growth, PH, is added to the H, carrier gas at temperatures of 2 350 "C. This step also serves to desorb native oxides that have formed during the cleaning steps. If an As containing layer is to be grown on the InP substrate, an InP buffer layer may be grown first. An alternative to the PH,-based heatup process is to heat the InP substrate in ASH,. This will also prevent decomposition of the substrate and desorb surface oxides through the formation of a thin InAs surface layer. The growth of InP using TMI and PH, is typically performed using a H, carrier gas. Growth is performed in an over-pressure of the group V element P, with the growth rate controlled by the partial pressure of the column I11 element In. In practice, the growth rate of InP is found to be directly proportional to the flow of H, through the TMI bubbler and is independent of the PH, flow due to the large excess of group V source in the reactor. At atmospheric pressure, the growth rate is independent of the growth temperature from x550-7OO"C. Below z 550"C, the growth rate decreases, which is a result of a reduction in the decomposition rate of the precursors. Growth at atmospheric pressures uses relatively modest V/III ratios (30-50) compared to low pressure growth where the V/III ratio for good morphology and materials properties is in the range of several hundred. The photoluminescence response (PL intensity and peak FWHM) of undoped InP is also improved at high V/III ratios (Eguchi et al., 1988). A practical issue related to the use of TMI is stability of the flux of TMI from the


bubbler over time. As the TMI is depleted, it is believed to recrystallize (remember that TMI is a solid) and thus its surface area changes with time. The resulting TMI flux per unit of carrier gas through the bubbler tends to decrease over time as the bubbler is used. This often necessitates frequent calibration growths to be able to achieve desired compositions and growth rates. Several methods have been used to reduce this effect, including running the bubbler backwards, depositing the TMI on support material in the bubbler to increase the exposed solid surface area and running the bubbler at reduced pressures. Undoped InP is typically n-type asgrown. A great deal of work has been done to grow high purity InP layers by MOVPE. The major source of impurities in the InP is associated with the TMI source. Using highly purified TMI, mobilities as high as 264 000 cm2 V- s- have been achieved (Thrush et al., 1987). In these high purity layers, the main impurities are C, Si and S . At very high purity levels, the source of these impurities may not be the In and P precursors. In these cases, the actual impurity concentrations depend on the specific reactor and its materials of construction. For example, unintentional silicon incorporation may result from reduction of heated quartzware with the gas phase transport of Si into the growing layer (Briggs and Butler, 1987).The electron mobility is also a function of growth conditions. This growth procedure dependence is related to the particular source of the impurities. The highest mobility is achieved using lower growth temperatures and higher growth rates. These conditions minimize heating of the reactor components (one source of impurity precursors) as well as their concentration (large growth rate) in the grown solid. Since lower growth temperatures result in inefficient decompo-

' '

173

sition of PH, , very high V/III ratios ( > 150) are required to maintain acceptable morphology. The photoluminescence (PL) response of high purity InP is dominated by two peaks, one exciton related and the other acceptor related. The exciton peak dominates the spectrum as the growth temperature is increased. The acceptor peak has been associated with both carbon and zinc; however in higher purity material it is most likely carbon whose source is from the metal-organic In source TMI. Typically, higher growth temperatures also yield higher PL efficiencies of the exciton related peak. For example, increasing the growth temperature from 600 to 650°C results in a decrease in the FWHM of the band edge PL peak as well as an almost total elimination of the PL peak attributed to carbon (Chen et al., 1986). Intentional impurity introduction can also be accomplished in MOVPE growth. A wide variety of dopants have been investigated for InP, to produce n- and p-type material as well as semi-insulating (SI) InP. Donor impurities include silicon, sulfur, selenium, tin (Veuhoff et al., 1992) and tellurium (Clawson et al., 1987), while cadmium (Blaauw et al., 1987), magnesium and zinc have been investigated as acceptors. Iron and chromium have been reported to form SI InP. N-type doping is typically performed using silicon or sulfur. Si and S have different advantages which must be evaluated with respect to the requirements of the final device. Si has a lower diffusion coefficient and is able to produce somewhat more abrupt doping interfaces. However, S is able to produce higher free carrier concentrations and the mobility for equivalent dopant concentrations is typically higher using S. Thus, in the growth of modulation doped heterostructure devices, where abrupt doping and compositional

174

3 Epitaxial Growth

interfaces are of prime importance, silicon is the donor of choice. Where high doping and conductivities are required (for example, in lasers) S is the dopant of choice. Both silane and disilane have been used as precursors for silicon doping. The doping behavior of silane in InP is very similar to that in GaAs. The incorporation is proportional to the mole fraction of silane in the reactor, the reactor pressure and the growth temperature and inversely proportional to the growth rate. Quite high carrier concentrations using SiH, ( x 2 x 1019cm- 3, have been achieved; lower temperatures are found to produce the best morphology at these high carrier concentrations (Clawson and Hanson, 1994). Disilane also acts similarly in InP doping as in GaAs. The main advantage of disilane over silane is the lower pyrolysis temperature and consequent insensitivity to growth temperature. Silicon incorporation from disilane also increases with increasing PH, mole fraction (Rose et al., 1989). H,S is the precursor for S doping. Using H,S, the free carrier concentration is exponentially proportional to the mole fraction of H,S in the reactor. The incorporation of S decreases with decreasing reactor pressure (Moerman et al., 1991) and is also exponentially proportional to 1/T. P-type doping of InP has a more complicated growth behavior than n-type doping. The acceptor diffusion coefficients are typically concentration dependent, and dopant activation is affected by the reactor ambient during cool-down. The most common p-type dopants for InP are Zn and Mg. Zn doping is performed using diethyl zinc (DEZ). At atmospheric pressures, Zn incorporation from DEZ has a similar growth dependence to that of S using H,S. The Zn doping process is, however, much less efficient. Like H,S the incorporation of Zn is exponentially proportional to the

flow of H, through the DEZ bubbler and exponentially proportional to 1/T. At low pressures, the incorporation of Zn from DEZ is linear with the mole fraction of DEZ introduced into the reactor (Veuhoff et al., 1991). The temperature dependence of both of these elements is explained by their high vapor pressures. While a portion of the adsorbed Zn is incorporated into the growing crystal, a fraction of the surface adsorbed Zn evaporates and diffuses into the reactor ambient. This behavior leads to a dependence of dopant incorporation on growth rate. At high temperatures the dopant incorporation increases with growth rate. If the desorption of Zn is kinetically limited, the higher growth rates will trap more of the dopant into the growing layer. Similar to H,S, the incorporation of Zn decreases with decreasing reactor pressure. Lower reactor pressures lead to an enhanced mass transport of Zn from the growth front resulting in a reduced Zn incorporation rate. Mg, Cd and Be (Cole et al., 1991) have also been investigated as p-type dopants in InP. The incorporation of Mg, at low reactor pressures, is superlinear with mole fraction of bis-methyl cyclopentadienyl magnesium in the reactor and thus harder to control than DEZ. Maximum carrier concentrations achievable for both Zn and Mg are about 2 x lo1* ~ m - ~ . An interesting facet of acceptor doping in InP is the observation the acceptor activation is dependent on the gas ambient present in the reactor during cool-down. The acceptor impurities can become passivated with hydrogen during cool-down. The acceptors are still physically incorporated in the crystal, but they are not electrically active due to the co-introduction of hydrogen. Passivation is strongest for cooling in ambients which can produce atomic hydrogen at the growth front. Such hydrogen passivation arises from the surface-

3.8 References

catalyzed decomposition of the group V sources. Since ASH, is more readily decomposed than PH,, this passivation effect is strongest for cooling in ASH,, less for PH, and even less for cooling in H,. This effect is not observed for n-type InP. Semi-insulating InP has also been grown by MOVPE using iron (Franke et al., 1990) and chromium (Harlow et al., 1994). Resistivities of lo8 R cm have been achieved through the incorporation of both of these elements. Both Fe and Cr by themselves act as deep acceptors allowing for the compensation of n-type materials (Wolf et al., 1993).

3.7 Acknowledgement The authors would like to acknowledge the help of Prof. Max Lagally, Department of Materials Science and Engineering, University of Wisconsin, Madison, in the preparation of this chapter. He also provided the scanning tunneling micrographs.

3.8 References Adamson, A. W (1990), Physical Chemistry of Surfaces, 5th ed. New York: Wiley. Amano, T., Kond, S . , Nagai, H., Maruyama, S . (1993), Jpn. J. Appl. Phys. 32, 3692. Blaauw, C., Emmerstorfer, B., Springthorpe, A. J. (1987), J. Cryst. Growth 84, 431. Bollen, L. J. M. (1978), Acta Electron. 21, 185. Borg, R. J., Dienes, G. J. (1990), Introduction to Solid State Diffusion. San Diego, CA: Academic Press. Briggs, A. T. R., Butler, B. R. (1987), J. Cryst. Growth 85, 535. Buchan, N. I., Larsen, C. A,, Stringfellow, G. B. (1987), Appl. Phys. Lett. 51, 1024. Buchan, N. I., Larsen, C. A,, Stringfellow, G. B. (1988), J. Cryst. Growth 92, 591. Casey, H. C., Jr., Panish, M. B. (1978), Heterostructure Lasers, Part B. New York: Academic Press. Chen, C. H., Kitamura, M., Cohen, R. M., Stringfellow, G. B. (1986) Appl. Phys. Lett. 49, 963. Chen, J. A., Lee, J. H., Lee, S . C., Lin, H. H. (1989), J. Appl. Phys. 65, 4006.

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Cho, A. Y. (1985a), in: The Technology andphysics of Molecular Beam Epitaxy: Parker, E. H. (Ed.). New York: Plenum Press. Cho, A. Y. (1985 b), in: The Technology and Physics of Molecular Beam Epitaxy: Parker, E. H. (Ed.). New York: Plenum Press, p. 6. Cho, A. Y., Hayashi, I. (1971),J. Appl. Phys. 42,4422. Clawson, A. R., Hanson, C. M. (1994), in: Proc. 6th Int. Conf. on InP and Related Materials, March 27-31, Santa Barbara, CA. Piscataway, NJ: IEEE, p. 114. Clawson, A. R., Vu, T. T., Elder, D. I. (1987), J. Cryst. Growth 83, 211. Cole, S . , Davis, L., Duncan, W. J., Marsh, E. M., Moss, R. H., Rothwell, W. J. M., Skevington, P. J., Spiller, G. D. T. (1991), J. Cryst. Growth 107, 254. Eguchi, K., Ohba, Y., Kushibe, M., Funamizu, M., Nakanishi, T. (1988), J. Cryst. Growrh 93, 88. Ettenberg, M., Olsen, G. H., Nuese, C. H. (1976), Appl. Phys. Lett. 29, 141. Farrow, R. F. C. (1974), J. Electrochem. SOC.121,899. Fitzgerald, E. A. (1991), Mater. Sci. Rep. 7, 87. Franke, D., Harde, P., Wolfram, P., Grotet, N. (1990), J. Cryst. Growth 100, 309. Ghidini, G., Smith, E W. (1984), J. Electrochem. SOC. f3f, 2924. Giess, E. A., Ghez, R. (1975), in: Epitaxial Growth, Part A : Matthews, J. W. (Ed.). New York: Academic Press. Harlow, M. J., Duncan, W. J., Lealman, I. E , Spurdens, P. C. (1994), in: Proc. 6th Int. Conf. on InP and Rel. Mater., March 27-31, Santa Barbara, CA. Piscataway, NJ: IEEE, p. 64. Heckingbottom, R., Davies, G. J. (1980), J. Cryst. Growth 50, 644. Hess, D., Jensen, K. E (1989), Microelectronics Processing, Adv. Chem., Vol. 221. Washington, DC: American Chemical Society. Jordan, A. S . , von Neida, A. R., Caruso, R., Kim, C. (1974), J. Electrochem. SOC.121, 153. Knudsen, M. (1909), Ann. Phys. (Leipzig) 4, 999. Kuech, T. E, Wolford, D. J., Veuhoff, E., Deline, V., Mooney, P. M., Potemski, R., Bradley, J. A. (1987), J. Appl. Phys. 62, 632. Kunzel, H., Fischer, A., Ploog, K. (1980), Appl. Phys. 22, 23. Kuphal, E. (1980), Appl. Phys. A 52, 380. Lu, Y. C., Bauser, E., Queisser, H. J. (1992), J. Cryst. Growth 121, 566. Meyerson, B. S . , Uram, K. J., LeGoues, E K. (1988), Appl. Phys. lett. 53, 2555. Middleman, S . , Yeckel, A. J. (1986), J. Electrochem. Sac. 133, 1951. Moerman, I., Coudenys, G., Demeester, P., Crawley, J. (1991), in: Proc. 3rd Int. Conf. on InP and Rel. Mater., April 8-11, Cardiff, U.K. Piscataway, NJ: IEEE, p. 412. Nayak, S . , Kuech, T. F., unpublished. Neave, J. H., Blood, P., Joyce, B. A. (1980), Appl. Phys. Lett. 36, 311.

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Neave, J. H., Joyce, B. A., Dobson, P. J., Norton, N. (1983), Appl. Phys. A 3i, 1. Nelson, H. (1963), RCA Rev. 24, 603. I Cryst. . Growth Ouazzani, J., Rosenburger, E (1990), . 100, 545. Pfeiffer, L., West, K. W., Stormer, H. L., Baldwin, K. W. (1989), Appl. Phys. Lett. 55, 1888. Rode, D. L., Wagner, R. W., Schumaker, N. E. (1977), Appl. Phys. Lett. 30, 75. Rose, B., Kazmierski, C., Robein, D., Gao, Y (1989), J. Cryst. Growth 94, 762. Shea, J. B., You, B. T., Kao, J. Y., Deng, J. R., Chang, Y. S., Chen, T. P. (1993), J. Cryst. Growth 128, 533. Shewmon, P. (1989), Diffusion in Solids, 2nd ed. Warrendale, PA: TMS. Stall, R. A,, Wood, C. E. C., Kirchner, P. D., Eastman, L. E (1980), Electron. Leti. 16, 171. Stringfellow, G. B. (1981), J. Cryst. Growth 55, 42. Stringfellow, G. B. (1982), Rep. Prog. Phys. 45, 469. Thrush, E. J.. Cureton, C. G., Trigg, J. M., Stagg, J. P., Butler, B. R. (1987), Chemtronics 2, 62. Veuhoff, E., Baumeister, H., Reiger, J. Gorgel, M.. Treichler, R. (1991), in: Proc. 3rd Int. ConJ on InP and Rel. Mater., April 8-11, Cardiff, U.K. Piscataway, NJ: IEEE, p. 72. Veuhoff. E., Rieger, J., Baumeister, H., Treichler, R. (1992), in: 4th Int. ConJ on InP and Related Materials, April 21-24, Newport, CA, p. 44.

Vossen, J. L., Kern, W. (1991), Thin Film Processing II. San Diego, CA: Academic Press. Wolf, T., Zinke, T., Krost, A,, Bimberg, D. (1993), in: Sth Int. Conf. on InP and Related Materials, April 19-22, Paris, France, p. 707. Wu, M. C., Su, Y K. (1989), J. Cryst. Growih 96, 52.

General Reading Grovenor, C. R. (1989), Microelectronic Materials. Bristol, U.K.: Adam Hilger. Hess, D., Jensen, K. F. (1989), Microelectronics Processing. Washington, DC: American Chemical Society. Hurle, D. T. J. (Ed.) (1995), Handbook of Crystal Growth, Vol. 3. Amsterdam: Elsevier. Lee, H. (1990), Fundamentals of Microelectronics Processing. New York: McGraw-Hill. Massel, L. I., Gland, R. (3970), Handbook of Thin Film Technology. New York: McGraw-Hill. Muraka, S. P., Peckerar, M. C. (1989), Electronic Materials: Science and Technology. San Diego, CA: Academic. Vossen, J. L., Kern, W. (1991), Thin Film Processes II. San Diego, CA: Academic.

4 Photolithography Rainer Leuschner Infineon Technology. Memory Products. Erlangen. Germany

Georg Pawlowski Clariant Japan K . K., BU Electronic Materials. Shizuoka. Japan

List of Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 179 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 4.2 Exposure Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 4.2.1 Image Formation and Resolution . . . . . . . . . . . . . . . . . . . . . . . 184 186 4.2.2 Contact and Proximity Printing . . . . . . . . . . . . . . . . . . . . . . . . 186 4.2.2.1 Optical Mask Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2.2 X-Ray Stepper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 4.2.3 Projection Printing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 4.2.3.1 Near UV Projection Systems . . . . . . . . . . . . . . . . . . . . . . . . . 189 4.2.3.2 Deep UV Projection Systems . . . . . . . . . . . . . . . . . . . . . . . . . 190 4.2.3.3 Nonconventional UV Lithography . . . . . . . . . . . . . . . . . . . . . . 191 4.2.4 Post-Optical Lithography . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 4.3 Photoresist Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 4.3.1 Quality Control and Resist Deposition . . . . . . . . . . . . . . . . . . . . 195 4.3.1.1 Purity and Storage Stability . . . . . . . . . . . . . . . . . . . . . . . . . 195 4.3.1.2 Resist Coating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 4.3.2 Resist Exposure and Development . . . . . . . . . . . . . . . . . . . . . . 197 4.3.2.1 Characteristic Curve and Standing Wave Effects . . . . . . . . . . . . . . . 197 4.3.2.2 Process Latitudes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 4.3.2.3 Dissolution Rate and Development Methods . . . . . . . . . . . . . . . . . 199 4.3.3 Pattern Inspection and Resist Profile Simulation . . . . . . . . . . . . . . . 201 4.3.4 Etching, Resist Stripping and Planarization Concepts . . . . . . . . . . . . 201 4.4 Photoresists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 4.4.1 Principles of Photoresist Chemistry . . . . . . . . . . . . . . . . . . . . . 203 4.4.2 Negative-Tone Resists . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 4.4.2.1 Photocrosslinking via Azides . . . . . . . . . . . . . . . . . . . . . . . . . 204 4.4.2.2 Free-Radical-Initiated Polymerization . . . . . . . . . . . . . . . . . . . . 205 4.4.2.3 Acid-Catalyzed Crosslinking . . . . . . . . . . . . . . . . . . . . . . . . . 206 4.4.3 Positive-Tone Resists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 4.4.3.1 Dissolution Inhibition/Dissolution Promotion . . . . . . . . . . . . . . . . 214 4.4.3.2 Acid-Catalyzed Deblocking . . . . . . . . . . . . . . . . . . . . . . . . . 221 4.4.3.3 Polymer Degradation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

178

4.4.4 4.5 4.5.1 4.5.1.1 4.5.1.2 4.5.2 4.5.2.1 4.5.2.2 4.5.3 4.5.3.1 4.5.3.2 4.5.4 4.5.4.1 4.5.4.2 4.6 4.7

4 Photolithography

Solvents for Photoresists and Main Resist Suppliers . . . . . . . . . . . . . 233 Special Photoresist Techniques . . . . . . . . . . . . . . . . . . . . . . . 234 Nonconventional Diazo Resist Processes . . . . . . . . . . . . . . . . . . . 234 Resist Profile Modification and Image Reversal . . . . . . . . . . . . . . . 234 Bilayer Systems for Contrast Enhancement . . . . . . . . . . . . . . . . . 236 Suppression of Reflections and Standing Wave Effects . . . . . . . . . . . 237 Dyed Resists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Antireflective Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 240 Silicon-Containing Multilayer Resists . . . . . . . . . . . . . . . . . . . . 241 Negative-Tone Silicon Bilayer Resists . . . . . . . . . . . . . . . . . . . . Positive-Tone Silicon Bilayer Resists . . . . . . . . . . . . . . . . . . . . 242 Top Surface Imaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Gas Phase Silylation Systems . . . . . . . . . . . . . . . . . . . . . . . . 245 Liquid Phase Silylation Systems . . . . . . . . . . . . . . . . . . . . . . . 246 Trends in Photolithography . . . . . . . . . . . . . . . . . . . . . . . . . 252 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254


List of Symbols and Abbreviations CD DR DOF D;, Do, Ea FT G k l , k2

n NA 0. N. r R

S TG

a

critical dimension dissolution rate depth of focus dose to clear activation energy film thickness of resist proximity gap constants refractive index numerical aperture Ohnishi number ring parameter reflectivity swing ratio glass transition temperature

Y

resist absorptivity resist contrast extinction coefficient angle wavelength

AAS ABC AFM AHR ALC APSQ ARC ARCH ASIC BARC BCB BDMADS CA CAR CARL CEL CMP coo CQUEST DESIRE DNQ

atomic absorption spectroscopy (azidobenza1)cyclohexanones atomic force microscope acid-hardening resist acid labile compound acetylated phenylsilsesquioxane antireflective coating advanced resist chemical amplified application specific integrated circuit bottom antireflective coating benzocyclobutane bis(dimethy1amino)dimethylsilane chemical amplification chemical amplified resist chemical amplification of resist lines contrast enhancement layer chemical-mechanical polishing cost of ownership Canon quadrupole efficient stepper technology diffusion enhanced silylating resist diazo-naphthoquinone

Y E

8

179

180

DPI DR DRAM DUV EBL ECR EVE excimer FFP FIB-CVD FLEX HAE HELIOS heptaMDS HMCTS HMDS HMMM HX IBL IC ICA ICP-MS ICP-OES IPL KTFR LAE LIGA LSI MAE MCM MEMS MIE MIF MLR MOSFET MSNR MTF NBSE NTRS NUV 0,-RIE OPC OPTIMA OSPR PAC

4 Photolithography

diphenyl iodinium dissolution rates dynamic random access memory deep ultraviolet (300- 100 nm) electron beam lithography electron cyclotron resonance ethylvinylether excited dimer film-forming polymer focused ion beam chemical vapor deposition focus latitude enhancement exposure high activation energy high energy lithography illumination by Oxford’s synchroton heptamethyldisilazane hexamethylc yclotrisilazane hexamethy ldisilazane hexamethoxymethyl melamine hydrogen halogen ion beam lithography integrated circuit indene carboxylic acid inductively coupled plasma mass spectroscopy inductively coupled plasma optical emission spectroscopy ion projection lithography Kodak’s thin film resist low activation energy Lithographie, Galvanoumformung, Abformung large scale integration medium activation energy multichip modulus microelectronic mechanical system magneton enhanced ion etcher metal-ion-free mu1t i -layer resist metal-oxide-silicon field effect transistor methacrylated silicon-based negative resist modulation transfer function nitrobenzyl sulfonate ester National Technology Roadmap for Semiconductors near-ul traviolet oxygen reactive ion etching optical proximity correction outline pattern transfer imaging organosilicon positive resist photoactive compound


PAG PBOCMOST PBOCST PBOST PCM PCVD PEB PHS PI PMGI PMIPK PMMA PROMOTE PSMT PTMS RBS RIE SABRE SAFE SAHR SCALPEL SEM SHRINC SIA SIMS SLR SNR SRAM SUCCESS TARC t-BOC TFT/LCD THP TMAH TMMGU TMSDEA TPS TSI ULSI

uv

VHSI XL XRL

photoacid generator poly -(t-butoxycarbonyl-methoxystyrene) poly-(t-butoxycarbonyl-oxystyrene) poly -(t-butoxy styrene) portable conformable mask plasma chemical vapor deposition post exposure bake polyhydroxystyrene photo initiator poly(methy1 glutarimide) poly(methy1 isoprophenyl ketone) poly(methylmethacry1ate) profile modification technique phase shifting mask technology pyrogallol trismethyl sulfonate Rutherford backscattering spectroscopy reactive ion etching silicon added bilayer resist scanning tunneling microscope aligned field emission silylated acid hardening resist scattering with angular limitation projection electron beam lithography scanning electron microscope super high resolution illuminating control Semiconductor Industry Association secondary ion mass spectrometry single layer resist silicon-based negative resist static random access memory sulfonium compound containing expellable sophisticated side groups top antireflective coating tertiary butyloxycarbonyl thin film transistor/liquid-crystal display tetrah y dropyran tetrameth y lammoniumhydroxide tetramethoxy methyl glycoluril trimethylsily ldiethy lamine triphenyl sulfonium top surface imaging ultra large scale integration ultraviolet very high speed integration crosslinker X-ray lithography

181

182

4 Photolithography

4.1 Introduction The definition of the numerous electrical functions assembled on integrated circuits (ICs) is usually accomplished with the aid of an illumination-based imaging technique called photolithography. Photolithography provides a method to transform a complex master image with radiation into thousands of three-dimensional replicas of a photoresist film coated onto a substrate with utmost accuracy, speed and cost efficiency. The real or digitized master image is provided by either a mask or a serial writing technique. Being stroked by the radiation, the exposed photoresist areas change their solubility or polarity properties. The material’s chemistry selection and its processing conditions determine the tonality of the relief image: If the reproduction corresponds to the original, it is termed a positive; if it is reversed. it is a negative reproduction. The discrimination between image and nonimage areas is accomplished by selective removal of either the exposed (positive) or unexposed (negative) resist through a development method (Fig. 4- l ) , resulting in the desired three-dimensional relief image. The remaining photoresist portions protect the underlying substrate from the attack of processing chemicals, e.g., etching agents, and allow the whole device to be subjected to the undifferentiated action of these. Photolithography has become an inevitable element in the manufacturing sequence of microelectronic circuits and other devices, such as multi-chip modules (MCMs) (La11 and Bhagath, 1993), micromechanical devices (Rogner et al., 1992), thin film recording heads for magnetic disks (Bond, 1993), color filters (Kudo et al., 1996a, b), or thin film transistorAiquid-crystal displays (TFT/LCD) (Howard, 1992; Bardsley, 1998). Many of these products are integral parts of the hardware platform mandatory

for an effective handling of the growing information density worldwide. The base material for the production of an integrated circuit consists of an intensively cleaned, highly polished disk, called a wafer, with a diameter up to 300 mm (Brunkhorst and Sloat, 1998; Bullis and O’Mara, 1993), which has been sliced from a large monocrystalline silicon rod of extreme purity. Each wafer provides hundreds of small separate chips, containing millions of electrical elements, such as capacitors, diodes, and transistors on a field size of 1 to 2 cm2. During its metamorphosis from apolished silicon plate to disk carrying ICs, the wafer is subjected to many different operations. Certain key steps are used repeatedly in IC fabrication, among which lithography plays a dominant role to delineate the patterns of conducting and insulating areas (Einspruch, 1985).

Figure 4-1. Formation of positive and negative tone pattern.

4 . 1 Introduction

Initially, the wafer is thermally oxidized at 1000°C. During this step a thin layer of silicon dioxide grows on the silicon substrate. This SO,-layer will protect selected areas of the substrate from penetration by dopant ions. The wafer is spin-coated with a solution of the photoresist, which solidifies to a uniform 0.5 to 2 mm thick film after the solvent is evaporated on a hot-plate at elevated temperature. The coated wafer is then imagewise irradiated and the soluble resist portions are removed by a development procedure. Next, the SO,-layer, which is imagewise protected by the resist, is etched away where it is uncovered to open the desired portions of the silicon surface. At this point, the resist is removed (stripped) to avoid device contamination with resist impurities. The wafer is now ready for a further key processing step: ion implantation, which gives the silicon its electrical properties. High-energy ions of dopant elements (boron, phosphorus) are fired at the wafer and penetrate the open areas of the silicon surface. The substrate surface is reoxidized,

-

183

and the wafer is again coated with a photoresist to allow further processing, e.g. insulation, or metallization steps. In a final lithographic step, contacts and connections for pins used to plug the chip into a printed circuit board are defined. At present, up to 24 lithographic and more than 250 separate processing steps are employed for the manufacture of electronic devices, resulting in a production time of one month for a single chip (Bullis and O’Mara, 1993). A simplified IC manufacturing procedure is given in Fig. 4-2. An ongoing challenge in IC production is to further shrink the lateral device geometry, with the aim of building even more complex circuits, e.g. dynamic random access memory (DRAM) devices with higher storage capacity. This demand for higher resolution is the driving force for steady improvement of the photolithographic process (Gargini et al., 1998). Figure 4-3 illustrates the developments of storage capacity and required feature size for memory devices (left), and summarizes the applied or required technologies and photoresist characteristics to produce the devices (right).

Figure 4-2. Planar technology: simplified production steps in MOSFET manufacture.

184

4 Photolithography

Technology: UV-broadband contact & proximity printer Chemistry: Azido I isoprene resists Tonality: Negative, single layer Pros: High sensitivity, good adhesion, low cost Cons: Swelling, resolution > 2.0 pm

1 256 kBit DRAM

Technology: g-line 8 i-line (436 & 365 nm) stepper Chemistry: DNQ I novolak resists Tonality: Positive, single layer Pros: High resolution, wide process laditudes Cons: Low sensitivity invariable chromophore

16 MBit DRAM

Technology: DUV (248 & 193 nm) exumer stepper & scanner (*beam, x-ray systems, IPL 7) Chemistry: Chemically amplified resists Tonality Positivelnegative, single (multi) layer Pros: High resolution, high sensitivity, adjustment to any wavelength Cons: Process sensitivity, high investment costs

16 GB1 DRAM

~

1970

~

~~

1980 1990 2000 2010 Availability for production [year]

Figure 4-3. Development of storage capacity and minimum feature size of memory devices (left) and technologies utable for memory debice production

4.2 Exposure Tools 4.2.1 Image Formation and Resolution

ICs are usually patterned with near UV radiation sources, e.g. mercuryhare gas discharge lamps. To achieve optimum resolution. the emitted light is filtered and corrected by filter and lens systems to yield narrow-banded radiation. Contact, proximity or projection exposure tools (Fig. 4-4) have found commercial use, each having certain advantages, and handicaps over the other (Soane and Martynenko, 1989).The history of the different lithographic exposure tools is outlined by Bruning (1997). In an optical lithographical system, light passes through the transparent areas of the mask. In the photoresist, the basic phenomenon to be seen is Fresnel diffraction. Figure 4-5 compares the aerial images of the above-described exposure methods. Con-

tact printing readily approaches a perfect pattern transfer. But, with growing distance between mask and wafer (proximity printing), interference patterns occur, ending in an aerial image with a smooth distribution of the light intensity with its peak in the centre of the slit and tails beyond the area defined by the mask. When adjacent slits are projected, the situation becomes more complex, as a series of undulating maxima and minima are observed, with maxima smaller than 100% and minima greater than 0% transmission. The minimal printable linewidth CD (critical dimension) is given by the wavelength A, the proximity gap G and the resist film thickness FT [Thompson et al., 1983; Eq. (4-1)]: CD = 312 VA(G + FTl2j

(4-1)

In projection printing the special frequencies of the diffraction pattern are collected

4.2 Exposure Tools

185

by the objective lens, which rebuilds the areal image of the mask in the wafer plane. For an ideal lens, the image quality is only restricted by the diffracted light that it does not pass through the lens due to the limited size of the numerical aperture (NA). The NA of a lens system in air is defined in Eq. (4-2), with 8 denoting the maximum angle of the diffracted light that can enter the lens (Mack, 1993a):

NA = sin (8/2)

Figure 4-4. MasWdie arrangement in (a) contact, (b) proximity and (c) projection printing.

(4-2)

A rough estimation of the limits of projection printing can be given by the Rayleigh [Eq. (4-3)]. The resolution (= critical dimension, CD) is a function of the radiation wavelength A,the NA and an empirically determined constant k~ which is governed by the type of photoresist, substrate, and the 9

Relative intensity

100

50

0

Figure 4-5. Comparison of aerial images obtained by contact, proximity and projection printing. (Reproduced after Soane, 1989.)

186

4 Photolithography

process environment (Lin, 1990). Under laboratory conditions, k l is assumed to be 20.5, whereas under production conditions, k , typically has a value of > 0.8 to > 1.2 depending on the reflectivity of the substrate.

C D = kl AJNA '

(4-3)

At a fixed wavelength, a larger NA allows the reproduction of smaller patterns. As seen from inspection of Eq. (4-4), the penalty for obtaining higher resolution by increasing the NA is a smaller depth-of-focus (DOF). The empirical constant k , in Eq. (4-4) also depends on the type of materials used.

DOF = k2 . AJ(NA)'

0.2

0.3

0.4

0.5

0.6

0.7

Numericol operture

'200 /

---

I _ T -I-----

----

I000

436 n m 365nm 248 nm

(4-4) t

Values for k , are in the range of 0.4 to 0.9 under laboratory and production conditions. Studies by Dammel et al. (1990) and Boettiger et al. (1994) revealed that Eq. (4-4) is only roughly valid in the sub-half-micron range, and larger focus budgets than predicted may be observed in reality. From Eq. (4-3) it is obvious that a decrease of A, also will result in improved resolution capability, which thus may be obtained by either using NUV radiation with a high N A system, or by deep UV radiation with a smaller N A . A shorter wavelength A, should yield a better focus budget at a defined resolution but with shrinking feature size it cannot totally compensate the corresponding DOF reduction as shown in Fig. 4-6 (Arden, 1990). The DOF problem is a major physical limitation for single layer resists i n optical submicron lithography, as a minimum resist thickness of >0.35 pm is necessary to ensure both coverage of the topography and sufficient etch resistance. The considerations mentioned above are basedon the assumption that the light strikes the mask only from one direction (coherent illumination). In reality, it comes from a

C

CI 3

600

-

t

0

(L

400 200

0

L

*/ 5

+/4

+/-I

D r p t n of focus [ p m ]

Figure 4-6. The impact of re 5 pm). A mask consisting of a glass or quartz substrate carrying an array of thin chrome pat-

4.2 ExDosure Tools

terns as absorber, is brought into intimate contact with the resist. This allows the simultaneous formation of many dies within one exposure, is cheap, and offers optimal pattern reproduction. Repeated contacts between mask and film may give rise to severe scratches, or sticking of resist pieces on the mask. Damaged mask patterns are then reproduced in the resist, which require additional time for reworking and mask cleaning, and diminish the yield. In shadow proximity exposure, the mask is separated by a gap of about 40 p m from the wafer plane. This avoids contamination and damage problems, but causes degradation of resolution due to diffraction effects (compare Eq. (4- 1>>. Optical mask aligners are usually equipped with mercury/xenon discharge lamps providing high output around: 400 nm, 3 10 nm and 250 nm (Fig. 4-7). In contact printing, broad band illumination is preferred, because standing wave effects are less pronounced when polychromatic light is used. Contact printing can be advantageously used to pattern very thick resist layers (< 200 pm) with high aspect ratios

KrF

248

XeCl ArF 193

t 1

200

300

400

500

Wavelength [nrn]

Figure 4-7. Comparison of emission spectra and energies provided by a mercury lamp and excimer lasers. (Courtesy of W. Spiess. Reproduced with permission.)

187

because the resist thickness is not limited by the depth-of-focus of any optical projection system (Loechel et al., 1994). Specially designed mask aligners allow for front and rear alignment (Cromer, 1993), which is needed for micromechanical applications, where the silicon substrate is etched through. 4.2.2.2 X-Ray Stepper

The resolution limits of optical systems using short wavelength radiation and improved resists together with optical tricks (Chu et al., 1991) are expected to be around 0.10-0.13 p m mainly due to the inadequate depth-of-focus budgets. Surface imaging schemes may give rise to further reductions of the device geometry at the price of increased process complexity. Ultra large scale integration (ULSI) patterns smaller than 0.13 pm without any depth-of-focus problem may be achieved using X-ray radiation (Peters and Frankel, 1989). The basic concept of X-ray lithography (XRL) is proximity printing. The improvement of the aerial image using X-ray beams compared with 200 nm radiation is quite obvious with respect to Eq. (4-1). Laser-based plasma sources (Chaker et al., 1991) emit “soft” X-rays of a wavelength (0.8-2.2 nm), which is short enough to give images not deteriorated by diffraction (Guo and Cerrina, 1991). Their medium brilliance (< 10 mW/cm2) requires highly sensitive resists ( 100 mW/cm2 are candidates to become production tools in the future for sub 0.2 p m

188

4 Photolithography

lithography (Yanof et al., 1992; Simon et al., 1998), due to their high resolution capability (>70 nm; Ogawa et al., 1993) combined with high throughput. Other unique and important advantages of XRL are its insensitivity to dust particles and substrate topography (Yoshioka, 1990), as neither reflection nor backscattering effects occur, resulting in excellent linewidth control over topography as demonstrated in Fig. 4-8. Although these features make XRL superior to any other irradiation technique presently known, several problems exist, which have hampered its introduction into high-end IC production for more than a decade. The large size of, and high capital investments for, synchrotron sources as well as their complex ancillary system are severe drawbacks in the competition with other technologies, but acost per bit analysis demonstrates that synchrotron XRL might be the cheapest method of manufacturing ULSI-

devices (Roltsch, 1991). Various functional circuits (e.g., SRAM with critical dimensions of 0.35 pm) have been manufactured using XRL (Technology News, 1993). The suitability of XRL for the fabrication of three-dimensional microelements for integrated optics, sensors, and microgears by the LIGA process (German: Lithographie, Galvanoformung, Abformung) will only be mentioned here (Rogner et al., 1992; Ehrfeld et al., 1998). The first ‘commercialized’ compact synchrotron with superconducting magnets is the high energy lithography illumination by Oxford’s synchrotron (HELIOS) from Oxford Instruments (Kempson et al. 1991). Several state-of-the-art descriptions of synchrotron sources used in lithography have been given recently (Maldonado, 1991; Schmidtet al., 1991; Yoshihara, 1992; Cerrina, 1992; Smith, 1995). The usable wavelength range of X-rays (0.5-4 nm) is determined by the absorption properties of the mask and of the resist.

Figure 4-8. SEM photograph of AZR PN 114 (left: 0.4 mm lines & spaces; right 0.175 mm lines. Dose: 9 mJ/cm2. development: 60 sec. 0. 135 N AZTkfMIF 3 12) over metal topography exposed with X-ray radiation provided by a laser plasma source. (Courtesy of Hampshire Instruments, Ltd. Reproduced with permission.)

4.2 Exposure Tools

These photons are neither reflected nor refracted by any material known today and have to be used as they are produced by the source. As no optical system can be applied, neither projection nor reduction techniques, only 1 : 1 shadow printing with proximity gaps of -40 p m can be employed (Guo et al., 1991). High quality X-ray masks consist of a thin, X-ray transparent membrane ( 1 4 pm), which makes them very sensitive to distortions due to absorber stress (Acosta, 1991; Chaker et al., 1991). Their defect-free production and repair are difficult tasks (Koek et al., 1993). These problems have not been satisfactorily solved over the last ten years. Recently, progress has been reported (Wasiket al., 1998). High overlay accuracy (< 70 nm) has been demonstrated (Tsuyuzaki et al., 1994; Aoyama et al., 1997).

4.2.3 Projection Printing 4.2.3.1 Near UV Projection Systems

Current IC lithography is clearly dominated by projection printing methods. In the early 1980s, 1 : 1 full-field scanning optical projection cameras were the workhorses of IC lithography (Thompson et al, 1983). These machines operate with a special, low numerical aperture (NA) ring-field mirror lens. Their benefits were high throughput, and the property to allow exposure over a range of wavelengths. But their resolution capability did not meet the aggravating IC design rules. The increase of the NA of the mirror lens gave way to cameras with higher resolving power at the penalty of smaller exposure fields, resulting in the step-and-scan camera concept. Although these new cameras allow the NA to be doubled (> 0.3), they could not compete with the step-and-repeat reduction cameras (stepper), which currently dominate advanced IC production.

189

Modern steppers use monochromatic radiation (e.g. 436 nm or 365 nm, g- or i-line of the mercury emission spectrum, respectively; Fig. 4-7), a complex system of lenses with an NA>0.5 and allow diminution of the mask image by a factor of 5x or lox. As the field dimensions of the imaging system are of limited size, only a small part of the wafer, i.e. a single chip, is exposed during one irradiation step (Fig. 4-9). This lowers the production throughput, but yields highly reproducible patterns, as the same mask is used for each distinct unit. Beside resolution and DOF (Yamanaka et al., 1993), the image field size is another important issue, as it decreases with increasing NA due to difficulties in manufacturing adequate optics of large size (Noelscher et al., 1990). Several IC companies switched from g- to i-line lithography to manufacture the 4 MBit DRAM chips with critical dimensions (CD)of 0.8 pm, and now use this technology for the production of 16 MBit DRAMS or other devices with 0.5 pm design rules (Greeneich and Katz, 1990).

Mirror Light source Filter

I*

Condenser

IA

Reduction lens

I +

x-y stage

Figure 4-9. Schematic drawing of a step and repeat camera.

190

4 Photolithography

These products require a DOF budget of 1.5 pm due to topography, limited wafer flatness and focus error of the stepper (Peters, 1991). The first version of the 64 MB DRAM with CDs of 0.4-0.35 mm has been produced with i-line, but the shrunk versions (0.35 to 0.3 pm) required a switch to DUV lithography for certain critical levels. 4.2.3.2 Deep UV Projection Systems

As the production of small feature sizes is one major challenge i n ULSI lithography, it became inevitable to investigate DUV radiation for providing higher resolution together with an increased DOF budget (Mack, 1993 a). However, previously used lens glass has to be replaced by quartz with high DUV transmission. Mercury-xenon lamps have a high radiation output in the near UV range, but a very low one in the 200 to 300 nm region, which excludes the use of narrow band pass filters to avoid chromatic aberrations and demands mirror projection optics. Two commercial DUV mirror projection systems operate with servicefriendly and inexpensive high pressure mercury-xenon lamps. As their brilliance is poor, resists ofhigh sensitivity ( < 5 mJ/cm') are mandatory. However, antireflective coatings may be omitted i n the case of broadband illumination (Kuyel et al., 199 I ) . The Ultratech stepper operates at a wavelength of 24953 nm, while the SVG Micrascan machine (step-and-scan concept) provides exposure illumination over a 240 to 255 nm bandwidth (Buckley and Karatzas, 1989). A different approach to DUV illumination systems is based on excimer lasers (excited dimer), which are very powerful pulsed gas lasers, in which excited diatomic noble gadhalogen molecules formed by a high voltage electric discharge, e.g. XeCl (308 nm). and especially KrF (248.5 nm) or

ArF (193 nm), emit the laser radiation during their transition to the repulsive ground state (Fig. 4-7; Jain, 1990). By injection locking, their emission is extremely narrow banded ( < 2 pm) and therefore no attention has to be given to chromatic aberration (Preil et al., 1991). Experimental resolutions of 0.15 pm have been reported using this technology (Hartney et al., 1992) and adequate alignment systems with an overlay accuracy ~ 0 . pm 1 have been designed (Fig. 4-10; Wittekoek, 1992). Problems with respect to accurate dose control due to low reproducibility of pulse to pulse laser power have been resolved more recently (Kowaka et al., 1993). Excimer lasers can be integrated with reflective or refractive reduction optics to form useful images. As indicated by the major exposure equipment manufacturers, projection systems for use in 193 nm lithography are currently on the verge of moving from R&D to production tools. It is evident that several basic requirements are still not met by the machines available today. Among the biggest challenges are the material selection for, and optimization of the lens system, as the high-energy radiation causes lens compaction and formation of color centers in al-

25 20

8 $ 15

\

C P)

g

10

?! L L 5 n "

-30 -20

-10

0

10

20

30

Error / nm Figure 4-10. Overlay errors of an ASM-L DUV stepper. (Courtesy of ASM-Lithography. Reproduced after Wittekoek, 1992.)

4.2 Exposure Tools

most all suitable materials (Schenker et al., 1996). The potential and future of optical lithography, including sub-half-micrometer resolution, has been discussed in detail from various more specialized aspects recently (Arden, 1990 and Yamanaka et al., 1993). The supply of irradiation equipment for device fabrication, in general steppers, is presently dominated by six companies: Nikon, Canon, Hitachi (all Japan), Ultratech, Integrated Solutions (U.S.A.), and ASM-Lithography (Netherlands). Step-and-scan machines are available from SVG Lithography (U.S.A.) (Cromer, 1993) and ASM-Lithography, Nikon and Canon also started to offer scanners. More recently, Japan-based Komatsu announced its intention to produce and market lithography exposure tools. 4.2.3.3 Nonconventional UV Lithography

An extension of optical projection lithography is expected from the use of optical tricks, like the phase-shifting mask technology (PSMT; Levenson, 1992), the off-axis illumination technique (Shiraishi et al., 1992), the optical proximity correction (OPC) (Levenson, 1997), the focus latitude enhancement exposure (FLEX; Fukuda et al., 1991), or the outline pattern transfer imaging (OPTIMA; Tanaka et al., 1991 b), pupil filtering (Fukuda et al., 1994) (all developed to practical performance by groups at Hitachi), holography (Omar et al., 199l), imaging interferometric lithography (Brueck, 1998) and phase contrast lithography (Mack, 1993b). Certain restrictions with respect to mask making and pattern geometry limit their general applicability. Levenson (1992) concluded from calculations that g-line PSMT would resolve sub 0.5 mm patterns. Later Terasawa et al. (1 989) presented 0.3 ym wide periodical gratings using a low NA i-line stepper. To-

191

day i-line PSMT is feasible for sub 0.3 pm printing (Shirai et al., 1991; Watson et al., 1997), which favors it as a major competitor to DUV lithography for 64 MBit memory fabrication. Several IC giants with their own well-developed mask shops have selected i-line PSMT as their first candidate for printing 0.35 ym. PSMT is usable for all variants of photonic radiation, including excimer laser lithography (Sewell, 1991). It takes advantage of interference to omit certain diffraction effects typical for light projected through small apertures, which results in an improved aerial image (Fig. 4- 11). Light, as an electromagnetic wave, has a phase and an amplitude. A conventional mask (Fig. 4-1 la) consists of a quartz plate imagewise covered with an opaque layer, which defines the apertures of the patterns. Constructive interference between periodic openings enhances both the electric field and the light intensity to a maximum between them, thus reducing contrast and resolution. In the Levenson-type PSMT (Fig. 4- 1 1b) bordering apertures are covered with a transparent phase shifting layer, which reverses the sign of the electric field with the effect that bordering waves are 180" out of phase with one another. At the wafer plane destructive interference occurs, which minimizes the undesired light intensity between two adjacent openings (Levenson, 1992). Using simple pattern geometries, k l factors of ~ 0 . 3 have 5 been demonstrated under laboratory conditions, resulting in minimum patterns of 0.24 pm and 0.16 pm for i-line and DUV irradiation, respectively (Ohtsukaetal., 1991; Baiketal., 1993; Matsuoka and Misaka, 1997). The Levensontype mask layout offers the greatest increase in resolution and DOF; however, it is limited to periodic grating patterns (Brock et al., 1991), because of its termination problem: phase shifts in the middle of clear ar-

192

4 Photolithography

Radiation

Mask Phase shifter

n n

Electric field at mask

Electric field at wafer

at wafer (a) Conventional mask

(b) Phase shift mask

Figure 4-11. The change of aerial image intensity by applying Levenson-type PSM-technology: use of (a) a conventional and (b) a phase shift mask

eas of the mask produce artefacts on the device, when positive tone resists are used (Jinbo et al., 1990). During the last years, many alternative mask configurations, which can be used for printing of isolated patterns have been discussed (Toh et al., 1991 a; Yanagishita et al., 1991; Levenson et al., 1992: Rome et al., 1993). An overview of the important PSM technology variants is given in Fig. 4- 12. To get highly precise masks is difficult due to possible errors in phase and transparency. Pupil filtering is proposed to relax the mask error tolerances (Nakao et al., 1997). because a strict control in mask structure is required to obtain CD control. The main PSM suppliers, namely Dai Nippon Printing, Hoya and Toppan, have started sampling masks. Currently off-axis illumination has become very popular as a resolution enhancement technique. However, pattern deforma-

tion phenomena may occur mainly in island type patterns (Kim et ai., 1997). Line width deviations caused by lithography or etch effects can result from local pattern density variations (Fujimoto et al., 1997). OPC is a low cost technique to reduce such problems (Liebmann et al., 1997').The FLEX method is used for printing of isolated transparent patterns, like contact holes, using positive resists (Fukuda et al., 1991), while the OPTIMA approach was applied to 0.2 mm regular patterns with practical focus (> 1.0 pm) latitudes and 0.13 pm-wide groove patterns using a 0.5 pm thick negative-tone i-line resist (Tanaka et al.; 1991b). The off-axis illumination techniques are favoured by the exposure equipment suppliers, as only minor modifications in the optical path are required. Canon and Nikon offer units called CQUEST (Canon quadrupole efficient stepper technology) and SHRINC (super high

193

4.2 Exposure Tools

4Phase Shifting Mask Technology

PSMT - Type

Edge

Resolution & DOF Enhancern.

50-80%

15-60%

40-6OYo

15-25%

15-25%

15-25%

10-20°/0

Application

Specialized

General

Packed patterns

General

Contacts

Contacts

General

Resist required

Negative

Pos./ neg.

Negative

Positive

Positive

Positive

Positive

Subresolution Attenuation

Alternating

Chromeless Attenuation

Non Attenuated

Attenuated

Rim

Figure 4-12. Overview of various phase shifting mask technologies. (Reproduced from Buck et al., 1991.)

resolution by illumination control), respectively, for their existing g-line, i-line and DUV steppers, and have reported 100% D O F enhancements (Shiraishi et al., 1992). The advantage of this approach is restricted to the patterning of periodic structures (Partlo et al., 1993). Imaging interferometric lithography combines off-axis illumination with interferometric optics. Modeling results show that the limits of optical lithography should be extended to roughly CD-A/3, which means 120 nm for i-line (Brueck, 1998). A holographic method with an effective NA of 0.7 has been investigated by Clube et al. (1993) from Holtronic Technologies for printing 0.25 pm features into a 0.5 p m thick i-line resist. The holographic proximity printer achieves a high imaging resolution over a very large field size. The improvement of the present overlay capability of k0.5 pm is currently under study.

4.2.4 Post-Optical Lithography The requirements of optics and materials are becoming increasingly crucial for even smaller patterns, such that optical lithography seems to be approaching its technological limit. Therefore, nonoptical lithographies such as electron beam, X-ray, and ion lithographies are increasingly important in order to replace or mix and match with optical lithography. It should be noted that post-optical lithography requires not only higher resolution capability but also more accurate controllability in terms of mask and overlay than conventional optical lithography. High throughput rate is also required (Ishitani, 1998). Direct Writing Electron beam lithography (EBL) currently dominates the photomask manufacturing industry (Pfeiffer and Groves, 1991),

194

4 Photolithography

and has a strong position as patterning method for prototype devices and advanced application specific integrated circuits (ASICs) or very high speed integrated circuits (VHSI), which are produced in small quantities (Newman et al. 1992). EBL is a pivotal element in microlithography and has largely contributed to progress in miniaturization (Pethrick, 1991). Currently used ebeam machines have been developed from the electron microscope. The beam is deflected and shaped by a series of electrostatic and magnetic optics. Direct writing (“scanning”) e-beam lithography employs either a round gaussian or a rectangular (fixed or variable) shaped beam suitable for building high resolution devices or providing high throughputs, respectively. Gaussian e-beam tools work in two scan versions: in the raster mode the beam scans the entire wafer along a serpentine path and is “switched” on and off, whereas in the vector mode it is directly addressed to its pattern position resulting in a considerable throughput enhancement (e.g. Philips Beamwriter). The shaped beam tools normally work i n the vector scan mode. EBL is characterized by an extremely high resolution capability (40 nm; Classen et al., 1992), but electron scattering through the resist material and more intensively through the substrate limit practical resolu-

tions to > 100 nm (proximity effect), especially when thick resist layers are employed. Software for proximity correction has been developed, e.g. CAPROX (Knapek et al., 1991). Figure 4-13 shows a simulation of the electron scattering at 10 keV, and 20 keV acceleration voltage. Obviously, the scattering range increases drastically with increasing energy, while the beam expansion in the resist is significantly reduced resulting in higher resolution (Rosenfield et al., 1991). Unfortunately, this is accompanied by a higher defect density in the substrate, caused by electron bombardment (Pethrick, 199 1). High resist sensitivity helps to reduce these defects. Direct write e-beam lithography is highly flexible because it obviates the use of a mask. The main drawbacks are the low throughput due to serial writing, and the relatively large investment costs making the manufacture of ICs via e-beam equipment only competitive with mask replication methods, if a number of less than 50 wafers is considered. Suggestions have been made concerning raising the wafer throughput by means of an array of microcolumns, based on the scanning tunneling microscope aligned field emission (SAFE) concept (Chang et al., 1992). Throughput of 50 wafers per hour for 100 nm lithography may be achievable, depending on the number of col-

Figure 4-13. Monte Carlo simulated trajectories of 100 (a) 10 keV, ( b ) 20 keV electrons in a 0.4 mm poly(rnethy1 methacrylate) resist layer on silicon. (Reproduced after Kyser et al., 1975.)

4 . 3 Photoresist Processing

umns employed. The extremely sharp tips of a scanning tunnelling or a atomic force microscope (STM, AFM) are a source of low energy electrons (160 eV) even under normal atmospheric pressure, which can be used to pattern very thin resist layers (scanning nearfield lithography). These techniques offer a cheap way to get prototypes of sub- 100 nm patterns but their throughput is extremely low (Marrianet al., 1993; Snow and Campbell, 1994). More recently, optical direct write laser systems as provided by Lasarray using HeCd (442 nm) or Ar' (364 nm) lasers have proven their competitiveness with e-beam based processes by delineation of 0.5 p m structures under manufacturing conditions (Rensch et al., 1989). The writing of mask and ASIC patterns may develop to a domain of this exposure variant, as the equipment is comparatively cheap, less sophisticated, and allows the use of standard resists. Ion beam lithography (IBL), first described in 1973, is under investigation as a method of direct writing (Bischoff et al., 1993). The ions produce very slow secondary electrons with short ranges in the resist: compared to e-beam lithography, the proximity effect is negligible, which is the reason for the tremendous ultimate resolution of IBL. Some special applications include broad beam ion milling to remove resist materials by ions (Bischoff et al., 1993), or the repair of patterns via focused ion beam chemical vapor deposition (FIB-CVD; Robinson, 1989; Morgan, 1998).During the exposure, ions are implanted directly into the substrate, giving rise to yet unknown possibilities for new processes. Electron and Ion Projection Lithography

Electrostatic lenses allow the use of electrons and ions in reduction projection systems which are candidates for post-optical

195

sub- 100-nm-lithography. SCALPEL (scattering with angular limitation projection electron beam lithography) (Liddle et al., 1997) and IPL (ion projection lithography) (Chalupka et al., 1992; Mohondro, 1997) can circumvent the difficulties of low throughput in direct writing and extremely tight manufacture specifications for 1x masks in X-ray proximity lithography. Both particle beam techniques work with existing resists. The most critical challenge is the fabrication of thin membrane masks etched out of silicon wafers . Masks for SCALPEL consist of a silicon nitride membrane on which metal patterns, which scatter the electron beam, define the layout. IPL definitely needs stencil masks which makes resist exposure more complex since two complementary masks are needed for one photo layer. On the other hand, the limited penetration depth of ions into any material has the advantage, that ions can be stopped in the resist very precisely. In consequence, any radiation damage in the device can be avoided.

4.3

Photoresist Processing

4.3.1 Quality Control and Resist Deposition 4.3.1.1 Purity and Storage Stability

Metal ions, especially sodium, iron, potassium, magnesium, manganese, copper and chromium, affect the electrical properties of the final IC devices. In advanced photoresist applications, typically metal contents of c 10 ppb for each distinct metal are required, which are controlled by atomic absorption spectroscopy, AAS, or by inductively coupled plasma-optical emission spectroscopy, ICP-OES, or mass spectroscopy, ICP-MS. These specifications pose new challenges to resist manufacturers, as

196

4 Photolithography

all chemicals have to be synthesized via nonmetal involving equipment. Particles in the resist solution5 will raise the defects, lower the device yield. and increase the rework expenditure. They are removed by simple filtration through microfilters with pore sizes 250°C) and very low dielectric constant. Combinations of novolaks or polyhydroxystyrene (PHS) with new monofunctional azide sensitizers, e.g. 4-azidochalcone derivatives (Reiser, 1989), yield resists with high sensitivity towards i-line (365 nm, 13 pJ/cm2) or g-line (436 nm, 55 pJ/cm2) radiation. The alkaline developers allow delineation of structures in the submicron range without swelling (Bendig and Gruetzner, 1990). Their interesting lithographic performance has revived world-wide activities (Kawai et al., 1989; Nonogaki and Toriumi, 1990). 4.4.2.2 Free-Radical- Initiated Polymerization

Methacrylate based photopolymerization is the basis for most dry-film photoresists and solder masks in printed circuit board manufacture and for high-temperature stable photoresists (e.g. photosensitive polyimides or their precursors) used as dielectric interlayers or buffer coats in the IC industry (Horie and Yamashita, 1995). Compositions useful for photolithography consist of a photoinitiator (PI), a matrix resin (e.g. polymers with methacrylate side groups) and optionally multifunctional monomers. Upon absorption of radiation, the PI is raised to an electronically excited state and generates radical fragments, which add to and initiate the polymerization of an unsat-

205

urated monomer (initiation). The resulting intermediate radical further adds to unreacted monomers, giving rise to molecular growth (propagation). The process is terminated by radical recombination, chain transfer or oxygen inhibition (termination). Oxygen is known to act as a quencher for the excited initiator and as a trap for free radicals by forming peroxy radicals of low reactivity. The chemistry and physics of the photopolymerization process (Fig. 4-24) are discussed in detail elsewhere (Rabek, 1987; Fouassier, 1989). Compared to many other photoimaging processes, systems based on photopolymerization have a remarkable high photospeed due to a chemically amplified mechanism. Although primary quantum yields (radicals produced per photon absorbed) are usually < 1 (Reiser, 1989), one absorbed photon may initiate polymerization of thousands of monomers. Shimizu (1988) reported an ultimate photopolymerization photoresist sensitivity of 13 pJ/cm2.The sensitivity and other resist parameters are strongly governed by the polymer morphology (Maerow, 1986). Like most negative working compositions based on an increase of molecular weight, the exposed, insoluble areas of the photopolymer film tend to swell, in particular during solvent development, making this chemistry definitively unsuitable for the fabrication of sub-ym microelectronic devices. The resolution requirements for hightemperature stable photoresists are less severe (>5 pm) and most of these materials on the market (Photoneece UR 5100@/ Toray, Pimel G-7610B/Asahi Chemical, XB 7020@/OCG, Pyralin 2732@/Du Pont, and Ultradei 7501@/Amoco) are based on special polyimide (pre) polymers with attached photopolymerisable methacrylate side groups. After exposure and development in organic solvents, these side groups

206

4 Photolithography

Formation of radicals:

Initiator (Initiator)'

+

RH

-

(Initiator)' Initiator - H

+

R

.

Initiation reaction:

Propagation reaction: R-CI+-CH

'

I

+ n CI+=CH

R'

Termination reaction:

2

R'

R-Ck-CH

-

RfCb-CH-),+b-CH. I

R-CI+-CH-CH-Cb-R

*

1

I

R'

Oxygen inhibition:

R-Cb-CH'

+

R'

02

I

R'

R'

-

1

R'

R-CH.-CH-O-O.

R'

I

R'

Figure 4-24. Simplified mechanism of the photopolymerization process

are released from the polymer i n a subsequent curing step at temperatures above 300 "C, and the final high-temperature stable (normally insoluble) polyimide is formed (Ahne et al., 1992; Horie and Yamashita, 1995). Most photoinitiators (PIS) are divided into two classes by their reaction mechanism: intramolecular bond cleavage to the radicals P* and I*, called photofragmentation, or intermolecular H-abstraction from a hydrogen donor RH, called a coinitiator, to form PIH* and R*. The former type of initiators is known as PI 1, as radical formation occurs in an unimolecular process, the latter as PI2, since two molecules are involved. Examples of both types and their decomposition mechanisms have been reviewedindetail (Reiser, 1989; Rabek, 1987: Vesley, 1986; Timpe and Baumann, 1988). PI 1 compounds form free radicals mainly via the Norrish type I cleavage (Fig. 4-25). As an example. benzoin alkyl ethers, which exhibit a weak absorption band at 330 nm, decompose to benzoyl and benzylether radicals, which both participate i n the initiation

reaction. The main side reactions of benzoin alkyl ethers are dimerization, H-abstraction and chain termination. Photoinitiators of the PI2 type include benzophenone, Michler's ketone, thioxanthones (QuantacureTM ITX, LucirinTM 85 13), benzil, quinone derivatives and 3ketocoumarines (Fig. 3-26; Reiser, 1989). These compounds abstract hydrogen from H-donors. typically tertiary amines with abstractable a - H atoms, such as triethyl amine, N-methyldiethanol amine, or 4-dimethylamino benzaldehyde. The intermediate exciplex decays to an a-amino radical, which acts as the initiator, while the ketyl radical does not contribute to this process. The oxygen sensitivity of PI2 systems is superior to that of the PI 1 type initiators, because the amine reacts with non-initiating peroxy radicals to reactive a-amino radicals. 4.4.2.3 Acid-Catalyzed Crosslinking

4.4.2.3.1 Cationic-Initiated Polymerization Besides radicals, cations and anions are capable of inducing photopolymerization

4.4 Photoresists

@-

e

207

Figure 4-25. The Norrish type I fragmentation of benzoin ether, benzil diketal and dialkoxy acetophenonederivatives.

o +

Benzoinether

Benzildiketal

'0 Dialkoxyacetophenone

Michler's Ketone

Thioxanthone

Bis (ketocumarin)

Figure 4-26. Chemical structures of some Norrish type I1 photoinitiators.

reactions (Reiser, 1989). Photoinitiated cationic polymerization offers several advantages: (1) new monomers with unique properties can be polymerized, (2) recombination of the carbocations is excluded, giving rise to high polymerization degrees, and

(3) insensitivity to oxygen. Certain limitations have restricted its commercial breakthrough: (1) only few initiators are available, (2) sensitivity to termination reactions by nucleophilic impurities, e.g. bases and humidity, or (3) sensitivity to chain-transfer processes (Timpe and Baumann, 1988). The polymerization process, as exemplified with an epoxide in Fig. 4-27, is initiated by the photogenerated Lewis acid (BF3), which adds to the oxirane with ring opening and the formation of a carbocation. This reacts rapidly with a new epoxide molecule. The energy released during opening of the strained ring contributes to fast propagation of the addition. Several negative resists based on cationic polymerizable materials have been described by Crivello et al. (1988), Ito and Wilson (1984), and more recently by Hatzakis et al. (1991). They employed commercially available epoxy resins (e.g. Epi-Rez@ SU-8, Quatrex@ Epoxy Resins) together with triarylsulfonium salts for DUV and ebeam resists. An optimized material (EPTR) is capable of resolving 0.1 pm features in a 0.8 mm thick resist at an e-beam dose of

208

4 Photolithography

Ringopen R

Monomeraddition R

k Figure 4-27. Reaction mechanism of Lewis acid i n duced cationic photopolymerization.

~ 0 . pC/cm2 5 (Chiong et al., 1990; Hatzakis et al., 1991). Zeng et al. (1989) described a similar approach using alternating copolymers of vinylcarbazole and ethyl glycidyl fumarate. The contrast is approx. 4, and the carbazole unit renders adequate etch resistance to the polymer. A thick-film material developed by IBM using SU-8 resin has recently been investigated for microelectronic mechanical system (MEMS) applications (Lorenz et al., 1997). It was found that the material could be single-spin coated up to a film thickness of 500 pm and to more than 1200 p m upon multiple coating steps. In a thickness range from 80 to 1200 pm structures with an aspect ratio of 18 have been reproducibly formed using a broadband NUV contact aligner (Lorenz et al., 1998). 4.4.2.3.2 Acid Hardening Resists

Significant progress with respect to contrast, sensitivity and image stability was achieved with acid-hardening resists (AHRs) based on the thermally catalyzed crosslinking reaction of an acid-sensitive precursor (Lamola et al., 1991). Commercially available AHRs consist of three components: an alkali soluble matrix resin, e.g. novolak

or a PHS derivative, a photoacid generator (PAG), and an acid-labile crosslinker. AHR systems have a superior potential for optimization. Just by judicious selection of the PAG, the materials can be modified to fully meet the requirements of near UV (Barra et al., 1991), DUV (Pawlowski et al., 1990a), e-beam (Liu et al., 1988), or X-ray lithography (Padmanaban et al., 1992). The process flow and relevant chemistry of AHR systems are outlined in Fig. 4-28. Upon exposure, the initiator is activated to release a strong Bronsted acid, while the crosslinker remains unchanged. In a subsequent bake step the activation barrier of the acid-induced crosslinking reaction is exceeded, resulting in network formation with reduction of the DR (Thackeray et al., 1991). Compared with standard resist processing, this post exposure bake (PEB) step is the only additional process variable. It has a significant influence on the resist performance (Fukuda and Okazaki, 1990; Azuma et al., 1993). The acid is regenerated during the crosslinking reaction, and one absorbed photon may induce a cascade of crosslinking events, giving rise to the phenomena of chemical amplification (CA), responsible for the observed high photospeed of chemically amplified resist (CAR) systems. In the real world several ways of acid loss exist, and as a matter of fact controlled acid consumption is a prerequisite for generating accurate images. It has been proposed that the PEB can induce thermally activated diffusion of the acid catalyst limiting the principle resolution of an AHR. Perkins et al. (1993) extracted an upper limit for the acid diffusion coefficient of 0.3 nm2/s from the PEB-time (1 10°C) dependency of the feature size generated with a scanning tunnelling microscope in an AHR. This value is smaller than reported previously indicating that diffusion of the acid has only a small effect on the linewidth.

4.4 Photoresists

209

Resist Substrate Exposure

OH

T

Acid generation

U

Post exposure bake Acid induced catalytic reaction

Development

Figure 4-28. Process flow and chemistry of three component AHR negative resists.

Suitable crosslinkers for AHR chemistry include melamine and urea resins with a N,O-acetal structure, like hexamethoxy methyl melamine (HMMM), tetramethoxy methyl glycoluril (TMMGU), or mixtures thereof. Under acid catalysis, these compounds form a highly reactive carbocation with the loss of methanol, which either directly attacks the electron-rich aromatic ring of the polymer, or forms an alkyl-arylether bond (Fig. 4-28). This suggests that the reduction of the DR occurs via two separate mechanisms: consumption of phenolic groups, and increase of molecular weight via crosslinking (Thackeray et al., 1991). Both, high crosslinker purity and exclusion of water are mandatory to guarantee acceptable shelf-life stability of the photoresist solution. Beside melamine and urea ethers, the respective alcohols or acetates may be used (Fig. 4-29). In addition, acetal blocked benzaldehyde derivatives (Schaedeli et al., 1993), or multifunctional benzyl alcohols,

ethers, or esters have been recommended (Spak et al., 1990). The methylether derivatives are preferred over any other group because they are the most stable in both solution and film state, and cause a minimum film thickness loss during crosslinking. In contrast to positive tone CARS, AHRs are quite stable towards delay time changes between exposure and PEB: even after 24 hours no sensitivity or linewidth variations were observed on 0.5 ym patterns (Pierrat et al., 1990; Roeschert et al., 1992; Conley et al., 1993). All major photoresist suppliers have developed and are currently marketing i-line and DUV sensitive AHR materials. The iline photoresists are based on novolak as the matrix resin, but use different PAGs and crosslinkers. Their resolution using conventional exposure tools is well below 0.4 y m with a focus budget in the range of 1.5 ym (Amblard and Weill, 1993; Linehan et al., 1994; Puttlitz et al., 1995). As novolaks are

21 0

4 Photolithography R

R R

\

O 7

R

/

fO

04"xN*o OJ"

d Melamine type XL (R = -H, -CH3 [HMMM]. -C4H9, COCH3)

y o\ R

Urea type XL (R = -H, -CH3 [TMMGU], -C4H9, -COCH3)

iH3 iH3

q Y

H3C -0

0 0

dH3 dH3

Terephthal aldehyde tetrarnethyl acetal

4,4'-Di-(methoxymethyl) diphenyl ether

KCH3 0

1,3,5-Tris-(acetoxy methyl) benzene

Figure 4-29. Chemical structures of crosslinkers used in AHR chemistry.

highly absorbing i n the DUV (248 nm) range and thus unsuitable for use in DUV resists, they are replaced with more transparent resins, such as poly-(4-hydroxystyrene) (PHS) derivatives, which typically exhibit optical densities 14) negative image with an DUV dose of 2 mJ/cm’, and alkaline development. It gives positive images by use of a photobase and a thermal labile acid precursor. Hayashi et al. (1990) have formulated negative CARS consisting of a novolak resin, diphenylsilanediol, and an onium salt for i-line, DUV and e-beam applications. These materials resolved 0.3 pm structures at 0.7 pm film thickness upon DUV (NA = 0.42) and phase shift mask supported i-line exposure. The dissolution promoting silanediol is converted into a siloxane oligomer under acidic conditions. The resist material is almost insensitive to the delay time (between exposure and PEB), and exhibits high DUV (3 mJ/cm’) and e-beam

sensitivity (0.8 pC/cm2 at 30 keV). Sachdev et al. ( 1994) crosslinked phenolic hydroxy groups with bifunctional dihydropyran derivatives by photoacid catalyzed acetal formation. This resist is equally well suited for X-ray, DUV and i-line exposure. Acid-catalyzed dehydration of phenylcarbinols is used for the insolubilization of phenolic resins yielding resist materials for i-line, DUV and e-beam applications (Uchino and Frank, 1991; Ueno et al., 1994; Kojima et al., 1996). 4.4.2.3.3 Photoacid Generators The PAG plays a dominant role in chemically amplified resists, such as AHRs. Its absorption properties require careful opti-

CF3SO3

CF3SO3

RH

e

J

..

....

+

R.

+

CF3SO3H

....

..

0

+ &S

A ~ ~ S

’A\) A ,

L/

v

+

2

Figure 4-33. M e c h a n i m of photolytically induced acid formation in iodonium and sulfonium d t \

4.4 Photoresists

mization, and its chemistry governs the acid properties produced upon exposure, such as acid strength, size and mobility, factors which influence the pattern quality. Two main groups are distinguished: salt-like ionic and nonionic PAGs. The most important representatives of the ionic type are the onium salts, e.g. triarylsulfonium or diaryliodonium salts with superacids forming anions (Crivello, 1984; Schwartzkopf et al., 1991). Among these, the trifluoromethane sulfonates are preferred in IC production (Cameron et al., 1997), as the metal-containing superacids, e.g. hexafluoroarsenate, are considered to be device contaminants. A simplified mechanism for the photoacid generation from diphenyl iodonium (DPI+) and triphenyl sulfonium (TPS+) salts is outlined in Fig. 4-33. More detailed mechanisms have been discussed by Tsuda and Oikawa (1990) and

Hacker and Welsh (1991). The excited onium cation cleaves homolytically. The intermediate heteroatom centred radical salt abstracts a hydrogen atom and forms the acid. Standard onium salts are active in the deep- or mid-UV region, their sensitivity may be extended into the near UV range by chromophore modification (It0 et al., 1988; Hayashi et al., 1990) or photosensitization (Crivello et al., 1988). Sulfonium salts are among the most efficient PAGs presently known with quantum yields of 0.24 to 0.4, depending on the polymer matrix (Allen et al., 1989). Nonionic photoacid generators are usually divided into two categories, as they produce either hydrogen halides (HX), or sulfonic acids (RS0,H). Examples of HX-generators include 1,l-bis(4-chlorophenyl)2.2.2-trichlorethane (Feely, 1985), 4,6-bis(trichloromethy1)- 1,3,5triazines (Fig. 4-34),

0 I/

I

O-S-R3

6

OR 1 , t '-Bis-(4-chlorophenyl). 2,Z.Z-trichloroethane

2,l-Diazonaphthoquinone4-sulfonate (R =aryl)

Pyrogallol-tnssulfonate (R = CF3, alkyl, alyl)

a,a-Bis(arylsulfony1) diazornethane (R =alkyl)

a-Hydroxy-P-sulfonyloxy ketone (R = -CF3, alkyl, aryl

CbC'

OSOzR

4,6-Bis-(trichloromethyl)1,3,5-triazin-Z-yl-stilbene (R = alkyl)

HowoHF? 8'

?r

Br

R I

Br

o=s=o I

0

0

0 I

o=s=o

Br OH

Tris-(3,5-dibrorno-4-hydroxyphenyl) ethane

213

02N&No2 2,6-Dinitrobenzylsulfonate (R = CF3, alkyl, aryl)

R Naphthylimidylsulfonate (R = CF3, alkyl, aryl)

Figure 4-34. Chemical structures of photochemically active hydrogen halide and sulfonic acid precursors.

21 4

4 Photolithography

about one order of magnitude slower than TPS+SbF,, and their sensitivity towards PEB conditions is more critical.

or brominated phenols (Buhr et al., 1989a). Sulfonic acid producing PAGs (Fig. 4-34) include 2,1-DNQ-4-sulfonates (Buhr et al., 1989b), a , a - b i s arylsulfonyl diazomethanes (Pawlowski et al.. 1990b), a- and p sulfonyloxyketones (Onishi et al., 1991 ; Roeschert et al.. 1993a), arylsulfonates (Ueno et al. 199 1 ). N-sulfonyloxy-maleimide derivatives (Brunsvold et al., 1991), and o-nitrobenzyl sulfonates (Houlihan et al., 1991 A). The cx,a-bis arylsulfonyl diazomethanes are especially useful for photolithography, as they combine adequate thermal stability with high quantum yields, and efficiently bleach even at small exposure doses as required for DUV sensitive CARS. Houlihan et al. (1991) studied extensively the photochemical behaviour of nitrobenzyl sulfonate esters (NBSE) as PAGs (Fig. 4-35). Electron-withdrawing groups in the sulfonate group increase the acidity of the resulting sulfonic acid. The photospeed of NBSE based deprotection resists is

HO "0

4.4.3 Positive-Tone Resists 4.4.3.1 Dissolution Inhibition/Dissolution

Promotion

The majority of positive resists currently used in the IC industry are based on twocomponent systems, where a dissolution inhibitor, normally a cyclic 2-diazo-1 -naphthoquinone (DNQ) derivative, is transformed upon photolysis into a dissolution promoter for the aqueous-alkaline development of the resist. The base polymers are phenolic resins, typically novolaks (Dammel, 1993). The process flow of DNQnovolak resists and the chemistry of the photoactive compound (PAC) are given in Fig. 4-36. The dominance of DNQ-based resists arose in the 1970's, when they took over

'

/

0 N

T

c

Figure 1-35. Photochemistry of nitrobenzyl sulfonate esters.

4.4 Photoresists

rn

9

215

0

Resist

.u-

~JJJ

Substrate

I-N

Exposure wolf

.u-

I

Development

Figure 4-36. Process flow and relevant chemistry of DNQ-novolak photoresists.

from isoprene resists for the production of 16 kBit DRAMS.Today, the 16 MBit DRAM with a 1000-fold increase in integration density is manufactured, still using the above shown chemical principle but with the aid of DNQ resists with substantially improved performance. However, the end of the DNQnovolak era is in sight now (Holmes and Sturtevant, 1993). 256 MBit DRAM production will definitively require departure from conventional NUV lithography. This long lasting success of DNQ-novolak resists is based on their high resolution capability, their relatively broad processing window and their excellent resistance against dry etch processes. In order to find out the reason for this remarkable performance this system has to be looked at in more detail. The unphotolyzed DNQ acts as an dissolution inhibitor for the alkaline soluble novolak due to molecular interactions between the phenolic groups of the novolak and the DNQ chromophore (Dammel, 1993). This dissolution inhibition phenomenon allows only for a small, but non-zero, dissolution rate (DR) of the resist in the developer which is smaller than that of the matrix resin itself. Upon imagewise irradiation

the DNQ-PAC is converted into an indene carboxylic acid (ICA) derivative which acts as a dissolution promoter, because: (1) the ICA is soluble in the alkaline developer and (2) the dissolution inhibiting interactions between the DNQ and the resin are destroyed. Therefore the exposed resist areas become more soluble in the developer. Modern resist materials may show DR-ratios (DRexposedlDRunexposed) of more than 10 000 with a DNQ loading of -20 % (Fig. 4-20). 4.4.3.1.1 Photoactive Compounds All technically used DNQ-resist formulations are based on two different types of photoactive compounds (PACs), namely aromatic 4- or 5- sulfonate esters of 2-diazo naphthoquinones. While the a-diazocarbonyl unit is the prerequisite for the photochemically induced solubilization reaction, the sulfonate group provides an anchor to modify the PAC properties without interference of the chromophore. Ballast compounds frequently applied for NUV applications include hydroxy-benzophenones (Reiser, 1989), bisphenol A derivatives (Tzeng et al., 1991), curcumin (Martin et al.,

216

4 Photolithography

1987),trihydroxy-phenylmethane (Kajita et al., 1991), and phenolic polymers (Hanawa et al.. 1993). Aromatic 2.1 -DNQ-5-sulfonate esters show absorption maxima at 350 and 400 nm, and are sensitive towards 365 nm (i-line), 405 nm (h-line), and 436 nm (g-line) radiation (Fig. 4-37, Thompson et al.. 1983).The absorption peaks of the aromatic 2.1-DNQ4-sulfonate esters are centred around 3 10 and 380 nm, and these PACs are insensitive towards g-line radiation (Fig. 4-37), but are advantageously used in i-line resists. With the switch from g- to i-line resists, the synthesis of new PACs with i-line transparent ballast compounds was a key project for many resist suppliers. The performance of DNQ-novolak based photoresists, e.g. exposure latitude, depth of focus, and resist profile shapes is characterized by three parameters, which are related to the bleachable (A-value), and the non-bleachable resist absorbence (B-value), and an optical sensitivity term (C-value), known as the Dill

,-line

05

r--

g-line

-

1

05

5

Y

0.4

a C

0.3 0 n y.

02 0' 00 300

350

400

450

500

Wavetengtb [nrn;

Figure 4-37. Comparison of UV Spectrum of a 2,1DNQ-5-sulfonate and a 2.1 -DNQ-4-sulfonate derivative$ with 2,3.4-trihydroxybenzophenone a$ the ballast compound

parameters (Reiser, 1989). Examples of ballast compounds with a small Dill B parameter, include 2,3,4,4'-tetrahydroxy diphenylmethane (Tzeng et al., 1991) or certain spiro compounds (Tan et al, 1990). The photolysis of DNQs (Sues Reaction) is principally ratified, but several details have been understood only very recently (Reiser, 1989; Vollenbroek et al., 1989a, b). By absorption of a photon, an excited singlet state of the PAC is generated with a quantum efficiency of -0.2 (Thompson et al., 1983). 2,l-DNQ-5-sulfonates (Fig. 4-39, I) eliminate molecular nitrogen from this singlet state and undergo a ring contraction (Wolff-rearrangement) to form a highly reactive ketene (Fig. 4-39, 111; Tanagaki and Ebbesen, 1989), which is stable enough to be detectable by laser ilash photolysis (Rosenfeld et al., 1990). It reacts at room temperature immediately with nucleophiles, such as water ubiquitous in the resist film, to generate the main photoproduct (about 85% yield), the 1H-indene-3-carboxylic acid-7-sulfonate (ICA. Fig. 4-39, V) derivative. The mechanism indicates that water is an essential component of DNQ photochemistry, which becomes obvious in thick film applications (Shibayama and Saito, 1990). Two important physicochemical changes go together with the photoinduced transformation of the PAC to the ICA: (1) the resist absorbence i n the near UV region is considerably reduced (bleaching, Fig. 4-38), and (2) the carboxylic acid groups promote the resist dissolution in the exposed areas. If water is absent, the usually much slower ester formation of the ketene 111 with the free phenolic groups of the resin becomes dominant, yielding a crosslinked material with reduced solubility (Fig. 4-39, I + IV), which interferes with the formation of the desired positive image, but has also given rise to new imaging concepts

21 7

4 . 4 Photoresists

.I

Figure 4-38. Dynamic photo1.03

200

I

I

300

1

I

1

resist bleaching absorption spectra of HPR 204 due to the photolysis transformation from DNQ to ICA. (Reproduced from Shankoff et al. (1980) with permission.)

400 500 Wavelength (nm)+

(Mutsaers et al., 1990). Other competing or thermally initiated reactions have been observed (Koshiba et al., 1988, e.g.: I1 in Fig. 4-39). In the presence of even relatively weak bases, the ICA decarboxylates readily via an indenyl anion to the two indene isomers (Fig. 4-39, V + VI, V + VII), which act as strong dissolution inhibitors (Vollenbroek et al., 1989a). The photochemistry described above is valid for both the 2, I-DNQ5-sulfonates and the 2, I-DNQ-4-sulfonates (Vollenbroek et al., 1989a, b). However, their corresponding ICAs may react quite differently under certain conditions. ICAs of 2, I-DNQ-4-sulfonate esters easily hydrolyze to the strongly acidic 1H-indene-3carboxylic acid- I-sulfonic acids, and to the free phenols (Fig. 4-40). This acid-catalyzed hydrolysis proceeds via an elimination-addition mechanism involving a sulfene intermediate (Buhr et al., 1989b). This elimination reaction will not occur with ICAs from 2,l-DNQ-5-sulfonates, as the formation of the corresponding sulfene would be energetically highly unfavorable. 2,l -DNQ-5-sulfonates of 2,3,4-trihydroxybenzophenone are the standard PACs for

g-line resists, e.g. Shipley Microposit 1300 and 1400, OCG WX-I 18, Tokyo Ohka TSMR series or Hoechst AZ 1300 and 4000 series. Occasionally, PACs derived from monofunctional phenols are employed, as

hv

1 -NP

I S03R

CY

(v)

I S03R

'

(VI)

SO3R

(VI/)

Figure 4-39. Possible sidereactions of 2,l-DNQ-5sulfonates.

21 8

4 Photolithography

OR

OR

. ROH

0

t

OH C

+HzO OH

OH

C

t -

o=s=o

0

S

0

0

Figure 4-40. Product formation troni 7.1 -DNQ-Isulfonate\

the cumylphenol 2.1 -DNQ-5-sulfonate in Shipley Microposit 1 1 1 and OCG HPR 204 (Reiser, 1989). while MacDermid PR 1024, or OCG 895i employ partially esterified phenol oligomers. As a rule of thumb, polyfunctional PACs have better dissolution inhibition properties and contribute to a distinct resist contrast enhancement effect. Recently, Trefonas and Mack (1991) have published a plausible explanation for this so-called poly photolysis effect. To take practical advantage of this effect, multifunctional hydroxy-benzophenones are used as ballast compounds. The fully reacted DNQ derivatives are only sparingly soluble and tend to precipitate upon storage. This is the reason why, in technical PAC s y n t he s i s , subst ochio me t ric educt amounts are often applied, resulting in the formation of a complex product mix (Kishimura et ai., 1989). An excellent review on the chemistry and physics of DNQ-based resists has been given by Dammel (1993) recently. For DUV exposure g-line or i-line resist materials are less suitable, because their absorbence is too high below 300 nm to allow uniform illumination within the whole re-

sist cross-section. The first suitable dissolution inhibitor for DUV exposure was developed at IBM in the early 1980s. It was found that diazo derivatives of Meldrum's acid, a cycloaliphatic compound, exhibit high absorbence at 254 nm and undergo a Wolff rearrangement to yield volatile photoproducts (Reiser, 1989). These PACs effectively inhibit the dissolution of novolak resins, but tend to evaporate during the soft bake. A more promising approach is based on a-diazo-P-ketoesters as DUV-sensitive PACs. Suitable multifunctional derivatives have been prepared with effective dissolution inhibition ability for DUV transparent styrene-co-maleimide or PHS type binders (Sugiyama et al., 1989; Pawlowski et al., 1 9 9 0 ~ )A. diazoacetoacetate bound to polyvinylphenol is used by Jagannathan et al. (1994) in a DUV resist with wide process latitudes. In this case the the carboxylic acid generated upon exposure deprotects acid-labile groups bound to a second polymer backbone. Newer additions include the use of diazocoumarins as PAC (Willson et al., 1997). 4.4.3.1.2 Alkaline Soluble Polymers The empirical work of the last thirty years has clearly proven that novolaks, condensation products of phenolic derivatives with formaldehyde, are the best selection as resins for DNQ-based resists. The condensation is catalyzed by acids and yields low molecular weight oligomers with 8 to 25 phenolic units linked by methylene groups (Fig. 4-41) to give a molecular weight of 600-3000 mu (Reiser, 1989). The acidic phenol groups render the polymers soluble in aqueous bases. As a typical example, a mixture of m- and p-cresol isomers, formaldehyde and oxalic acid as the catalyst are heated. With increasing temperature, water formed during condensation is removed: the oxalic acid de-

4.4 Photoresists

CH20

+

H+

H20

U

composes to carbon dioxide, and finally pure novolak resin remains. Although this procedure looks simple, batch-to-batch reproducibility of novolak formation is very poor, and therefore blends of different batches are normally used to provide the required resist uniformity. The exclusion of any metal-ion contamination is a major target of novolak producers (Asaumi et al., 1991). Lithographically useful novolaks are made from meta-cresol with smaller amounts of para-cresol or certain xylenols, which give the polymer appropriate solubility properties in organic solvents. When meta-cresol with its three reactive sites is employed, the formaldehyde has to be added substochiometrically to obtain linear polymers; otherwise branched or crosslinked

H*C+OH + H ~ O

219

Figure 4-41. Chemistry of cresol novolak formation.

resins will result (Noguchi and Hiderni, 1991). This difficult-to-control reaction does not occur if para-cresol is used. Unfortunately, novolaks with a high para-cresol content are less useful, as they have unacceptably low glass transition points and process latitudes (Fig. 4-42a). The use of the different phenols rapidly increases the numbers of structural isomers, which all contribute differently to the resist performance, e.g. contrast, sensitivity and process latitudes (Honda et al., 1991 and Hanabata et al., 1991). metaCresol novolaks with highly regular ortho methylene bonds (high S4 ratio) show a significant decrease of the DR, possibly due to thermally induced coupling reactions with the DNQ during the PEB (Fig. 4-39,II).This

220

4 Photolithography

does not occur i n the exposed resist, resulting in an improved contrast and enhanced exposure latitude. without sensitivity losses (Fig. 4-42b; Hanabata et al., 1989). Besides the novolak isomeric structure, increasing molecular weights of otherwise identical resins decrease the overall D R and the resist sensitivity. but neither the contrast, nor the exposure latitude are influenced (Fig. 4-42c: Hanabata et al., 1989). A narrow molecular weight distribution without low molecular weight fragments improves thermal stability and image resolution. Based on these observations, Hanabata and coworkers proposed the stone wall model of resist dissolution: the low molecular weight fragments are small stones in a wall, which are readily washed out during development giving rise to a steadily growing r e s i d d e veloper interface area. After a certain penetration time, the resist structure collapses under formation of separate lumps, which are easily solubilized (Hanabata et al., 1991). In contrast to solvent developable resists, DNQ-novolak based resists do not swell during their development with aqueousbased developers. Kinetic studies revealed that the dissolution rate is influenced by the size of the base cations and the secondary structure of the novolak resin, in particular by the relative configuration of the phenolic groups (Reiser. 1989; Dammel, 1993). A comprehensive overview on the dissolution characteristics of DNQ-novolak resists (perlocation model of novolak dissolution) has been given by Reiser et al. (1996) recently. Novolaks are transparent above 300 nm (Fig. 4-30) and exhibit glass transition temperatures ( T G ) in a range of 70 to 140°C (Khanna et al., 1991). High TCs (hard bake deformation temperature) can be correlated with improved dry etch resistance (Joubert et al., 1993). Many attempts have been made

0.50

I

10/0

Q/l

8/2

A

7/3 m/P

,

5i

6/4

5/5

1

4/6

y

1.25

0

0

10

20

B

30

40

50

60

54

m/p

= 1o/o S 4 = 14 - 15

h

- 1.009

3

0

v

- 0.75 4

53 m

-

0.50

E

$P W

~

0

C

5000

10000

15000

20000

25000

Moleculare weight

Figure 4-42. Effect of A: metalpara-cresol ratio, B: ortho/para link configuration ratio (S4), and C: molecular weight on contrast and exposure latitude. (Reproduced after Hanabata et al., 1986.)

4.4 Photoresists

to replace novolaks by new polymers to extend the applicability of DNQ resists. Due to their improved transparency in the DUV region and TGs up to 180 "C, poly(4-hydroxystyrene) (PHS) and copolymers thereof have received much attention (Pawlowski et al., 1990a). The film forming properties (Toriumi et al., 1991) and the unusual dissolution behaviour of PHS in aqueous-alkaline developers (Long and Rodriguez, 1991) have been investigated in detail. Its DR in standard MIF developers (2.38% of TMAH) is about 20 pm/min compared to 0.3 to 3 p d m i n for novolaks, which is far too much to delineate well defined relief images. PHS polymers have been modified with hydrophobic groups (Pawlowski et al., 1990a; McKean et al., 1990), which act as internal dissolution inhibitors to the attacking developer and make these materials promising for DUV resists. There are significant differences between, for example, DNQ-novolak and DNQ/PHS resists: while the former are inhibited by even small PAC-loadings, the latter are not. This experimental result suggests that there are links between the inhibitor and the polymer matrix. Depending on the secondary molecular structure, the hydrophilic groups may arrange themselves into more closed intramolecular, or more open intermolecular, hydrophilic assemblies. These assemblies may act as diffusion channels for the attack of the developer (Yeh et al., 1992; Dammel, 1993). The position of the hydroxy group in polyvinylphenols has a large effect on the dissolution rate. While the 2-hydroxy isomer is too slow and the 4-hydroxy isomer too fast for use in DNQ resists, the copolymerization of both allows one to choose any dissolution rate between the extremes (Dammel et al., 1994). The thermal flow resistance of such a 1 : 1copolymer resist was found to be improved over that of novolak resists.

22 1

DNQ resists based on aromatic poly-ortho-hydroxyamides with good lithographic performance have been introduced as photopatternable interlayer dielectric for multilayer electronic devices. These polyamides show comparable dissolution inhibition/ promotion characteristics in alkaline developers like novolaks, but by heating the developed resist pattern up to 350 "C the polymer converts into a high temperature stable polybenzoxazole with good dielectrical properties (Sezi et al., 1994; Sezi et al., 1999). 4.4.3.2 Acid- Catalyzed Deblocking

Conventional DNQ-resists exhibit only moderate photosensitivity and thus relatively poor production economics. With the present switch from NUV to DUV lithography required to print sub-quarter micrometer features, DNQ-based resists are no longer acceptable due to their high opacity below 300 nm. Furthermore, DUV irradiation tools provide only low photon densities due to their extreme spectral narrowing. This makes conventional resists far too slow to give meaningful device yields: resist sensitivity has become an increasingly important issue. New materials based on radiation-induced deprotection reactions and polarity changes of certain acid sensitive polymers meet these challenges (Fig. 4-43). The benefits of such systems for microlithography were first recognized by Ito, Willson, and Frechet (It0 et al., 1987), who introduced the concept of chemical amplification (CA) and called materials of that type chemically amplified resist (CAR). Positive CARS contain at least a photoacid generator (PAG) (compare Sec. 4.4.2.3), and a polymer with acid labile, hydrophobic protecting groups. Upon exposure, the photogenerated acid molecules induce a thermally catalyzed cleavage of the acid

222

4 Photolithography

1

Exposure

Acid generalion

Post exposure bake 7)-

-(-

Alkaline

Solvent

Acid catalyzed deblocking

6

u

Lv C& development

0

- ( / - )

H'

kT

0-C-CH3

3 I

CH3 C-CHs

+

+

COP

CH/

OH

Figure 4-43. CAR concept: process flow of t-BOC protected positive resists

labile groups. A sophisticated design concept allows for regeneration of the photoacid during the deblocking sequence, and thus one single molecule can induce a cataract of cleavage reactions, providing a gain mechanism to overcome the sensitivity limitations imposed by the quantum efficiency of the photochemical event. The usually more polar degradation/deprotection products cause the exposed resist to be soluble in an aqueous alkaline developer (Reichmanis et al., 1992). According to the number of active components i n the resist, twoand three-component chemically amplified systems are distinguished. Ttoo- Cornpoi1 en t Resists

As implicated by the nomenclature, chemically amplified two component resists consist of two active resist components dissolved in a solvent, namely, a polymer masked with acid-sensitive protecting groups and a photoacid generator. According to the energy required for the deprotection reaction, three classes are distin-

guished: low activation energy (LAE) systems (E,30 kcal/mol), such as carboxylic acid esters, or ethers. The first commercially accepted chemically amplified resist material was developed by IBM (APEX series) and is based on the acid induced cleavage of PBOCST (Fig. 4-43). a poly-(4-hydroxystyrene) blocked with r-butyloxycarbonyl (t-BOC) groups (Willson et al., 1990). The photolytically produced acid molecules cleave the carbonate moieties (re)generating the alkali-soluble PHS resin as well as the volatile byproducts of carbon dioxide and isobutene upon application of a PEB at approx. 100°C (MAE system) (Sturtevant et al., 1992). The reaction does not require the presence of water and works equally well under the high vacuum conditions required during electron-beam exposure. The intermediately formed t-butyl cation stabilizes to isobutene, and liberates a new proton, which is

4.4 Photoresists

capable of inducing the next cleavage reaction, The early PBOCST materials were 100% protected. It turned out, however, that a protection degree of 15-35% is sufficient to render the PHS polymer insoluble in the standard MIF developers and additionally improve certain lithographic properties, such as contrast and image stability. While pure, fully t-BOC blocked PHS resins are thermally stable up to 190°C (Reiser, 1989), partially blocked materials decompose at lower temperatures due to an autocatalytic deprotection reaction caused by the presence of acidic phenol groups in the polymer. The catalytic chain length for the deprotection reaction of t-BOC based resists varies from 10 for methane sulfonic acid, through 200 for toluene sulfonic acid to 8.000 for trifluoromethane sulfonic acid (Houlihan et al., 1991), with an acid diffusion radius of less than 5 nm (McKean et al., 1989). These acid parameters have tremendous effects on the resist performance and need careful adjustment (Hashimoto et al., 1997). The selection of non-nucleophilic acids is mandatory for t-BOC chemistry, as nucleophilic acids, such as hydrochloric acid, fail to deblock the t-BOC groups via a catalytic mechanism. Ota et al. (1994) have reported that the intermediate t-butyl cations may alkylate the aromatic rings of the polymer in a competitive reaction to the desired isobutene formation and thus deteriorate the dissolution rate in the exposed areas. PBOCSTsystems behave as a dual tone resist (Fig. 4-43). The negative process with anisol as developer was employed to manufacture 1 Mbit DRAMS via DUV lithography (Maltabes et al., 1990), while the positive one has been investigated for 0.35 mm patterning (Brunsvold et al., 1993a). Several modifications of PBOCST resins have been reported, including t-BOC protected poly(hydroxypheny1 methacrylates)

223

(Przybilla et al., 1991), hydroxystyrene sulfone copolymers (Reichmanis et al., 1991), or the more recently developed hydroxystyrene vinyllactame copolymers (Kim et al., 1997). Although PBOCST materials have several limits in lithographic performance and even some severe shortcomings with respect to delay stability (Nalamasu et a]., 1991), they are still used in state-of-the-art 0.25 pm production processes (Amblard et a]., 1997). More recently developed t-BOC based resist formulations are less susceptible to these problems. A large number of alternative protecting groups has been proposed to block phenolic polymers. Among these, acetal protected PHS resists have received wide commercial interest due to their excellent resolution capabilities (Endo et al., 1991; Pawlowski, 1996). The acetal bond is formed by the reaction of PHS with vinylethers such as ethylvinylether (EVE-PHS, Fig. 4-44) or tetrahydropyran (THP, Fig. 4-44). The activation energy required for the acid-catalyzed acetal deprotection reaction is lower than that for t-BOC material and image formation may occur at room temperature (LAE system). However, completion of the reaction is usually achieved during a postexposure bake at 90°C. Acetal-based resists work well with less powerful acids, such as methane sulfonic acid generated from pyrogallol tris methane sulfonate (PTMS) as the photo acidgenerator(Uen0et al., 1991; Hattori et al., 1993), and require stoichiometric amounts of water for accurate image formation. The polymers exhibit excellent transparency at 248 nm ( 1000 mJ/cm’) are

Figure 4-50. Photoreaction of PMMA

required to obtain adequate dissolution speed (Nakase, 1987). PMMA has several benefits as DUV resist (Wolf et a]., 1987), including excellent resolution capability, ease of handling, good film forming properties, wide process latitude, and low price. I n a 500 mm thick PMMA resist, patterns with nearly vertical sidewall profiles have been printed with XRL (Rogner et al., 1993). However, its low sensitivity is barely acceptable. The efficiency of the cleavage reaction is increased ( - 80 mJ/cm’) when the DUV absorption is intensified by copolymerization with 3-oximino-2-butanone methacrylate or by addition of r-butyl benzoic acid as a photosensitizer (Reiser, 1989). Polymers of polybutene sulfone (Thompson et al., 1983) or poly(methy1 glutarimide) (PMGI) are also scissionable with DUV radiation. The photospeed of PMGI is comparable to PMMA, but, due to its imide groups, it is developable with aqueous bases, has better dry etch resistance, and a high glass transition point (> l8O0C), making PMGI useful as planarizing layer for multi-layer schemes (Reiser, 1989). In addition to PMMA, poly(methy1 isopropenyl ketone) (PMIPK) based resists, commercialized by Tokyo Ohka under the trade name ODUR 1010, are widely investigated as photoscissionable one-component resists (Hesp et al., 1990). All of these mainly aliphatic materials show poor dry etch resistance which limits their application. The principle of chemical amplification can also be applied to polymers which undergo main chain scission (Frechet et al., 1989). Polycarbonates derived from tertiary diols and certain diphenols are degraded i n the presence of a PAG and by exposure to DUV (Fig. 4-5 1 ; Reiser, 1989). During development, advantage is taken of the higher DR of the degraded polymer fragments versus the intact polymer to

4.4 Photoresists

1'

1 hV, PAG 2. kT

mLJ J&b2=&o+cop H+ CH3

Figure 4-51. Photoreaction of main-chain degradable polycarbonates.

generate a positive image. The degradation concept has been extended to generate positive resists using polyacetals, polyazomethines, polyethers and polyesters with acid-cleavable bonds in their main chains (FrCchet et al., 1989, 1990; lto and Schwalm, 1989).

4.4.4 Solvents for Photoresists and Main Resist Suppliers Photoresist materials for IC manufacture are usually sold as thoroughly filtered ( ~ 0 . pm) 2 liquid solutions (liquid photoresists) in organic solvents, which have pronounced effects on certain photoresist properties, such as photospeed, coating uniformity and thermal flow behaviour (Salamy et al., 1990). The ideal solvent is non-toxic and non-hazardous (safer solvents; Boggs, 1989). Examples include 2-heptanone, cyclopentanone, cyclohexanone, 3-methoxybutyl acetate, propylene glycol monomethylether or its acetate, propylene glycol diacetate, ethyl lactate, ethylene carbonate, ethyl 3-ethoxypropionate and ethylpyruvate (Hurditch and Daraktchiev, 1994). The main resist suppliers are Tokyo Ohka, OEM (Olin Electronic Materials), Shipley (Rohm & Haas), Clariant, Sumitom0 Chemical, Nippon Zeon, Japan Synthetic Rubber, Mitsubishi Chemical, Shinetsu, and others (Gutmann et al., 1990 a and

233

SST tabulation, 1993). The field of advanced g-, i-line and DUV resists is highly competitive and rapidly changing. In 1990 the authors believed that the resolution limits of DNQ-novolak resists had been reached with the performance obtained by the Tokyo Ohka g-line material TSMR-V3: 0.4 y m lines and spaces with vertical sidewall profiles were printed with a 0.54 NA stepper in a 1.26 pm thick resist (Satoh et al, 1989). This performance is now beyond standard for the last generation g-line resists. Today, i-line resists are available with an ultimate resolution 2 . 0 pm for 0.35 pm patterns.

Figure 4-52. SEM picture of 0.25 km lines and spaces printed in JSR/UCB new high-contrast i-line resist 1x500 using the ASM-L PAS 5000/50 i-line stepper ( N A =0.48) with a Levenson type phase-shifter design. Courtesy of IMEC, Leuven, Belgium. Reproduced with permission.

234

4 Photolithography

4.5 Special Photoresist Techniques 4.5.1 Nonconventional Diazo Resist Processes 4.5.1.1 Resist Profile Modification

and Image Reversal The perpetual drive to improve the performance of existent DNQ-novolak resists has stimulated research into advanced process schemes. Additional processing steps and modification of the basic chemistry have resulted in variants capable of producing positive and/or negative patterns. Their implementation in a production environment largely depends on the additional complexity they cause. The profile modification technique (PROMOTE) offers the capability of producing positive images with variable profile angles (Vollenbroek et al., 1991). The resist is irradiated (NUV) through a mask to yield the latent positive image. A DUV blanket exposure under anhydrous conditions (vacuum or elevated temperatures of approx. 100°C; Fukumoto et al.. 1989) follows, leading to a selective crosslinking of the resist surface through PAC-resin ester linkages in the previously masked areas (Fig. 4-39 IV). Since the esterified top of the resist exhibits a low dissolution speed, overdevelopment yields negative sloped patterns suitable for lift-off processes. Positive or negative tone images are produced by the image reversal resist schemes. Originally, they were developed to improve the process latitude of DNQ resists, but the use ofthe same photoresist in either its positive or negative mode is of greater practical interest with respect to warehousing, reduction of printing defects by appropriate choice of best defect masking and control of sidewall angles. Several versions of image reversal resists have been described:

The indirect. amine-promoted image reversal process was developed by Moritz and Paal at IBM (Thompsonet al., 1983). In their first experiments 1 -hydroxyethyI-2-alkylimidazoline was added to the DNQ resist. After an imagewise NUV exposure the latent positive image can be developed (positive mode). When a bake step (image reversal bake) is inserted prior to development, the ICA decarboxylates via its ammonium salt to the parent indene derivative, which acts as an effective dissolution inhibitor (negative mode). A subsequent NUV flood exposure converts the unreacted DNQ into the corresponding ICA and enhances the developability. Useful modifications are based on diffusion of amine vapours (Alling and Stauffer, 1988), or a liquid ammonia soak (Ziger and Reighter, 1988), to provide the base catalysts. The ammonia soak process has been used for a lift-off process in fabrication of CMOS devices (Joneset al., 1988). The relevant chemistry of this base-catalyzed process is given in Fig. 4-53 (Reiser, 1989). The indirect image reversal process suffers either from low shelf life (the base is i n the resist), or from an additional soaking step. An elegant approach to image reversal resists based on a 2 , l -DNQ-4-sulfonate ester PAC and a small amount of hexamethoxymethylmelamine (HMMM) has been made available by Clariant (Spaket al., 1985), followed by similar materials from MacDermid and Shipley. This direct image reversal process proceeds according to the reaction sequence in Fig. 4-54: during the bake of the latent image, the ICA photoproduct forms the highly acidic indene, sulfonic acid, which induces the crosslinking reactions of HMMM (Buhr et al., 1989b). A subsequent NUV flood exposure solubilizes the yet unexposed regions; upon alkaline development a high quality negative image is obtained (compare: Figs. 4- 16 and 4-54).

4.5 Special Photoresist Techniques

235

Figure 4-53. Process flow and relevant chemistry of (left) the amine-promoted image reversal process and of (right) the direct image reversal (crosslinking) process (XL = unreacted crosslinker; NW = network).

Figure 4-54. Change of sidewall profile of a direct image reversal resist by variation of 1. and 2. exposure dose. (a) positive [ 1. expos.: 1.5 s, 2 . expos.: 2000 pJ/cm2], (b) vertical [ 1. expos.: 1.5 s, 2 . expos.: 1000 pJ/cm2], and (c) undercut profiles [ 1. expos.: 0.5 s, 2. expos.: 1000 fl/cm2].

This chemistry is the basis of the i-line sensitive AZ@5200 resist series. A related resist with equally good g- and i-line applicability is based on 7-methoxy substituted 2,l-DQN-4-sulfonate esters (Buhr et al., 1989b). This material resolves 0.40 pm lines and spaces with vertical sidewalls with an 0.54 N A g-line stepper (Seha and Perera, 1990). The lithographic properties of direct image reversal resists have been investigated by several groups (Gutmann et al,

1990b; Reuhman-Huisken et al., 1990), and compared with the indirect type (Grunwald et al., 1990). A key feature of image reversal resists is the potential to control the pattern profiles, e.g. vertical slopes for sub-pm etch applications, and undercut profiles for lift-off (Fig. 4-54). Another benefit is the excellent thermal stability of the patterns (> 200 " C ) and the improved linewidth control over topography (Nicolau and Dusa, 1990).

236

4 Photolithography

4.5.1.2 Bilayer Systems f o r Contrast Enhancement

ized by General Electric under the tradename Altilith. The relevant chemistry of CELs is given in Fig. 4-55. The effects of CEL materials on critical dimensions and resist behaviour over highly reflecting topography have been studied intensively (Blanc0 et al., 1987). However, layer intermixing seems to be unavoidable, if CE-layers do not consist of water-soluble bleachable diazonium salts (Endo et al., 1989) and water soluble polymers, e.g. PVA (Halle, 1985). poly(viny1 phenol) (Sakurai et al., 1988), or poly(viny1 pyrrolidone) (Uchino et al., 1988). A system with two layers of different spectral sensitivity, introduced by Lin (IBM), consists of a thick planarization layer of DUV sensitive PMMA or PMGI and a thin NUV sensitive DNQ-novolak toplayer (Lyons and Moreau, 1988; Takenaka and Todokoro, 1989), which is opaque to light below 300 nm. The top material is patternwise exposed and developed, followed by a blanket exposure with DUV radiation and a second development with an organic solvent. The process was termed portable conformable mask (PCM), as the top resist

Contrast and quality of the latent resist image can be improved by the application of a contrast enhancement layer (CEL) on top of a conventional prebaked photoresist (White and Meyerhofer, 1986). A CEL is a thin photobleachable film with high initial absorbence of the applied radiation. During illumination, the CEL is bleached , and its non-linear transmission cuts off low intensity parts of the aerial image, allowing only the high-intensity parts to pass (Fig. 4-55). After illumination. the CEL is removed either prior to, or together with the development of the photoresist. Suitable photobleachable compounds for i - and g-line sensitive CE-layers were found among the substituted diary1 nitrones (West et ai., 1988) which exhibit high extinction coefficients in the near U V ( ~ 3 000) 5 and rearrange on exposure to nonabsorbing oxaziridines ( ~ ~ 5 0 0with 0 ) quantum yields of 0.3. Unfortunately, they are somewhat unstable towards moisture (West et al., 1988). CELmaterials for g- and i-line are commercial-

\

?.

CH=N+

hv A

CEL

Resist

Figure 4-55. Prows5 flow and relebani cherni\try of the CEL-technology


acts as a zero-gap in-situ mask during DUV flood illumination, resulting in a nearly ideal image transfer to the bottom layer. Mid UV sensitive CARS based on blocked poly(viny1 benzoates) as toplayer in combination with PMGI as bottom layer have been described for use as PCM (It0 et al., 1987).

4.5.2 Suppression of Reflections and Standing Wave Effects 4.5.2.1 Dyed Resists

Accurate pattern transfer is heavily degraded when metallized, highly reflective topographic substrates are imaged. The degradation of critical dimensions is caused by both thin film interference effects due to non-uniform resist thicknesses over steps as well as by light scattering from underlying patterns, known as reflective notching (Bolsen et al., 1986). According to Eq. (4-7) (Sec. 4.3.2.1), these problems are alleviated by increasing resist absorption a through the addition of dyes absorbing in the actinic

1.20

I I

1.15

-5 e ‘S

l

h

1.10 1.05 1.00

.- 0.95 -I

0.90

M

0.85 0.80

1.30

1.40 1.50 1.60 1.70 Resist Thickness (prn)

Figure 4-56. Simulation of CD-variations of 1 pm lines and spaces with varying resist thickness on aluminium for undyed resist, dyed resist, and undyed resist with an ARC. (Reproduced from Noelscher et al., 1989 with permission.)

237

region (Fig. 4-56). The requirements with respect to absorbence, particle generation or solubility are met by only few dyes. These include, for example, coumarin and curcumin (Cernigliaro et al., 1989), or azodyes (Cagan et al., 1989). The main trade-offs for gaining added process latitudes on topography are losses in focus latitude and generation of non-vertical sidewall profiles (Fig. 4-57) due to the increase of the non-bleachable absorption (Cagan et al., 1989). Depending on the concentration and the chemical type of the selected dye, increasing dose requirements are often observed, which made the efficiency of this approach to a subject of intensive debate in the literature (Mack, 1988). 4.5.2.2 Antireflective Layers

The use of antireflective coatings (ARCS) is an alternative concept to minimize reflective notching and CD variations caused by interference effects (Brunner, 199 1). The interest in this approach has emerged with the recent progress of DUV lithography, as it is believed that the inclusion of the ARC concepts is vital for DUV technology to become relevant to ULSI mass production (Barnes et al., 1991). The more common way is the deposition of thin sputtered inorganic films with light absorption properties on reflective substrates as bottom antireflective coatings (BARCs). A precise control of their thickness is very critical for maximum effect. Optionally, these films remain in the final device (integrated BARC). Their application introduces additional complexity and new sources of defects (Horn, 1991). Focus and exposure latitudes are significantly enhanced and become less sensitive to substrate reflectivity, resulting in a more robust process (Sethi et al., 1991; Fahey et al., 1994; Figs. 4-56 and 4-57). Anorganic

238

4 Photolithography

Figure 4-57. SEM picture$ of positive resist patterns over silicide topography for (a) undyed resist, (b) dyed resist and ( c ) undyed resist on BARC. (Reproduced from Noelscher et al., 1989 with permission.)

BARC materials can be TIN, TaN, Si,N,, a-Si, a-C : H or other layers made by chemical vapor deposition. More recently, however, the use of organic BARCs has become popular (Krisa et al., 1996). These materials are simply spincoated at an optimized FT of 50- 200 nm on the wafer and baked at high temperature to avoid intermixing with the subsequently coated photoresist. By selection of the BARC material, and depending on the need of the user, conformal or planar coating of the substrate is possible (Fig. 4-58).

Organic BARCs are less sensitive to FT variations, prevent potential contamination of sensitive devices, and bring about tremendous cost reductions as no additional deposition equipment is required. Pattern transfer to the substrate is achieved by an oxygen RIE step after photoresist development. State-of-the-art organic BARCs for NUV and DUV processes are provided by Tokyo Ohka, Brewer Science, Shipley and Clariant. Figure 4-59 demonstrates the elimination of reflective notching (hole burning) by the use of AZ BARLi.

Figure 4-58. Conformal and planar organic BARC arrangement on a topographic wafer.


239

Figure 4-59. Hole burning by accidental mirror elements. Top: without BARC, bottom: with BARC.

From inspection of Eq. (4-7) (Sec. 4.3.2. l), it is obvious that the reflectivity of the resistiair interface also contributes to thin film interference. Improvements of the CD control through the application of a top antireflective coating (TARC), which is spun on top of the resist to minimize the resistlair reflection, have been reported first by Tanaka et al. (1991 a), and later by Brunner (1991). This technique uses a thin (30- 100 nm) organic film with a matched refractive index +ARC and an optimum thickness dTARC as defined by Eq. (4-lo), where A denotes the radiation wavelength. ~ T A R C =a14 ~ T A R C

(4- 10)

The optimum refractive index of the TARC of 1.28 is only met by Teflon, or certain perfluoroalkylpolyethers (Tanaka et al.,

1991 a; Brunner, 1991), which require special coating solvents and removers, and bring severe adhesion problems. Tanaka et al. (1991 a) have reported that on silicon substrates the CD control was improved by a factor of ten. A water-soluble TARC-material has been introduced by Clariant under the tradename AZ AQUATAR (Alexander et al., 1994). Although the optimum value of the refractive index is not matched by Aquatar (1.4), its water solubility allows easy processing and avoids intermixing with the photoresist. More advanced TARCs do not require extra bake, strip or etch steps, are nonabsorbing and therefore cause no exposure penalty or degradation of photoresist contrast. Recent work has demonstrated that TARC applications bring significant im-

240

4 Photolithography

provements, such as reduction of the swing ratio by a factor of 3 , thus improving linewidth uniformity over topography, improved across-the-wafer uniformity, and a larger focus budget. However, TARCs do not eliminate reflective notching effects. Yoshino et al. (1994) compared the BARC and TARC concepts with respect to the simulated process windows in DUV lithography. The TARC has a smaller thickness latitude but it offers a wider process window for the resist. Arrangements with organic ARCS are superior to dyed resists with respect to resolution, latitudes, and linewidth control on topographic substrates, but introduce additional process complexity. Figure 4-56 compares the simulated CD variations as a function of resist thickness for a standard resist, a dyed resist, and an undyed resist with an ARC (Noelscher et al., 1989). Franzen et al. (1998) compared the costs of various lithography technologies (dyed resist, BARC and bilayer CARL resist) for a mass production target of 3000 wafer starts per week. They calculated that the Cost of Ownership value of a dyed resist is lower than for any other process in their comparison. The COO value for an integrated TiN-BARC process without removal of the antireflective layer is 42% less than that of a CARL bilayer resist process (compare 4.5.4.2) and 53% less for an ex-situ TiN-BARC process. The a-Si-process with ex-situ etch and without integrated removal of the a-Si layer in the etch process is by far the most expensive process of all the processes described here. Thus the CARL process is an interesting possibility with high capability and comparable COO value. 4.5.3 Silicon-Containing Multilayer Resists The majority of the photoresists discussed in the previous chapters was devel-

oped for use as single layer resists (SLR). From the discussion it became evident that SLRs have certain limitations: restricted aspect (i.e. height/width) ratios, limited focus budgets, sensitivity to topography and thin film interference effects, and lack of stability against aggressive etch chemicals. Together, these factors have been met only with very few high performance SLRs. A way to alleviate these obstacles is the use of multi layer resist (MLR) systems, which permit specialization of the separate layers, e.g. optimized sensitivity and resolution of the imaging layer, and adjusted dry etch resistance, optical density, and thermal stability of the bottom layer (Miller and Wallraff, 1994). With respect to e-beam lithography, problems arising from proximity, or electrostatic charging effects can be resolved by suitable MLR combinations (Moss et al., 1991). The main handicap of MLR systems is the increase of complexity involved with two or more layers, which translates into multiplying the probability of defects or unexpected aging phenomena. Moreover, MLR processing requires expensive dry etching equipment not commonly available in IC manufacture for oxygen plasmas. Single layer resists will therefore be used as long as they fulfil the respective requirements, and it is difficult to decide at what stage the incorporation of an MLR system is clearly favourable. On the other hand, new prototype devices and ASICs are often tested and manufactured using MLRs (Hatzakis et al. 1988). In reality, all techniques using an organic BARC or TARC are multilayer resist processes and, although they are often termed SLR, their complexity is comparable to MLR systems (Franzen et al., 1998). MLRs are composed of a 0.5 to 4 p m thick radiation-insensitive bottom resist, or planarizing coating, which has low resistance towards oxygen plasmas, submerges


241

the substrate topography and reduces interSpin coating of DNQ- novolak resist ference effects by light absorption at the acand hard bake (> 200 "C) tinic wavelength (Thompson et al., 1983). Examples include hard-baked DNQ-novoSpin coating of silicon lak resists, polyimides or diamond-like carcontaining top-resist bon layers (Namattsu, 1988; Leuschner et al., 1993). In a MLR scheme, a second and normally \1 hv much thinner top resist or imaging layer (0.2 1 I Exposure to 1.0 pm) is coated on top of the planarizing coating. The top layer defines the feature dimensions and is thus sensitive towards radiation. Optionally, these two layers are separated by a third layer, an in Towresist development general extremely thin ( e0.2 pm) but stable barrier layer with respect to an image transfer via dry etching (Hartney et al., 1989). It is most often selected from inorganic mateR R Oxygen RIE rials, e.g. silicon, silicon nitride and dioxide, titanium dioxide, polysilane, or spinon-glass (Hartney et al., 1989), and can be applied by either sputtering, plasma chemFigure 4-60. Typical process flow of a silicon-based bilayer resist arrangement. ical vapour deposition (PCVD), or spincoating. The use of trilayer schemes has become quite unpopular, as the increasing complexity is not usually compensated by their benefits. Therefore, the following discussion will concentrate on silicon-contain2' 300 C .= ing top resists of bilayer schemes (Miller E and Wallraff, 1994). A typical process flow > is given in Fig. 4-60. 100 + The resistance of silicon-containing polymers towards oxygen reactive ion etch4' ing (0,-RIE) is controlled by their chemi0 c 30 cal structure, and the silicon content. Dur-c 0 ing treatment with an oxygen plasma, the ii polymer surface is converted to a thin ( 5 to I I 20 nm) layer of silicon dioxide, which is 10 1 3 10 30 highly resistant towards further plasma atPercentage of silicon in the polymer tack (Hartney et al., 1989). Oxygen etch reFigure 4-61. Effect of silicon content on the etching sistance is not a linear function of the silirate of organosilicon polymers in an oxygen plasma con content (Fig. 4-61): at silicon contents at I O mTorr pressure and power=O.IS W/cm2, The above 10 to 15% it remains constant (Juretching rate is independant from the silicon position. gensen and Shaqfeh, 1989). A problem of(Reproduced from Hatzakis et al., 1988 with permisten encountered with the incorporation of sion.)

.1

.1

0,

Y

'

242

4 Photolithography

silicon is the low glass transition temperature of these materials, which may lead to thermal flow and lack of resolution. Moreover, hydrophilicity is reduced as the silicon content increases, which may become an issue when aqueous-based development is desired. 4.5.3.1 Negative- Tone Silicon Bilayer Resists

The first examples of lithographically useful silicon-containing negative resists were based on poly(alky1 siloxane)s, which show an oxygen etch rate ratio of 1 : 50 compared to hardbaked novolak resist (Shaw et al., 1987). They exhibit low Tc’s ( c 100°C) and tend to image-distorting thermal flow. Poly(si1methylene-) and poly(silpheny1ene si1oxane)s containing highly regular siliconcarbon and silicon-oxygen linkages in their

main chain are reported to have higher TG and e-beam sensitivities ranging from 25 pC/cm’ (Babich et al., 1989). More recently, a three-dimensional crosslinked poly(silpheny1ene siloxane) was prepared as negative-acting photoresist. It exhibits higher rigidity than conventional siloxanes, resulting in an improved contrast, minimized swelling upon development, and improved thermal stability. The addition of 2,2-dimethoxy-2-phenyl acetophenone as a photoinitiator enhanced the UV photospeed by a factor of 20 to about 20 mJ/cm2 without deterioration of the pattern profiles. 0.25 pm patterns could be delineated in a bilayer arrangement (Watanabe et al., 1991). Researchers from NTT obtained a high TGmaterial (150°C) with a partially chloromethylated poly(dipheny1 silsesquioxane) in which two chains are linked together by oxygen atoms (ladder type polysiloxanes).

I

-(-si-O-~-(-Si-o-)I

I

? (-Si-o-)-

0

--(-si-O-)I

I

CH3

CH

C

SNR

d

Vinyl-silsesquioxane

O Q i

QQ:

-(-Si-0-)-(-Si-0-)-OH I

P -(-Si-0-)

-

,i-

LO”, MSNR

I

? (-Si-0-)-OH

APSO

Figure 4-62. Chemical structure of silsesquioxane based negative working resists.

243


The material - called silicon based negative resist (SNR, Fig. 4-62) -is sensitive towards DUV and e-beam radiation ( 5 yC/cm2) and resolves 0.5 ym patterns on a hardbaked novolak (Tamamura and Tanaka, 1987). Adequate near UV sensitivity, resolution and oxygen etch resistance were achieved using the methacrylated silicon based negative resist (MSNR, Fig. 4-62), which utilized a methacrylated poly(pheny1 silsesquioxane) as polymer and a bisazide as PAC (Morita et al., 1986). The same group from NTT applied acetylated phenylsilsesquioxane oligomers (APSQ, Fig. 4-62) as the matrix polymer for both negative and positive bilayer resists (Ban and Tanaka, 1990). APSQ, together with azidopyrenes, gives a negative working DUV and e-beam sensitive resist with good resolution (Kawai et al., 1989). In combination with onium salts, the photoacid catalyzes the condensation reaction of the silanol groups in APSQ (Ban et al., 1990). This process is accelerated by a post-bake step, and 0.3 pm negative patterns have been obtained in a bilayer scheme (Tanaka et al., 1992). A silylated poly(viny1 silsesquioxane) gives an e-beam resist (7.6 pC/cm2) with an estimated etch rate ratio of 1 : 100 compared with a hardbaked positive resist (Saito et al., 1988). A three component material with improved DUV (25 mJ/cm2) and e-beam ( 5 yC/cm2) sensitivity has been formulated from poly(pheny1 silsesquioxane), a photoacid generator, and an additional crosslinker, e,g . hexamethox ymethy lmelamine. Crosslinking probably occurs through etherbond formation. The material offers a tremendous etch latitude (Hiraoka and Yamaoka, 199 1). 4.5.3.2 Positive- Tone Silicon Bilayer Resists

As reported by Miller and Michl (1989), polysilanes are attractive-positive acting

top resists for bilayer arrangements due to their bleaching ability and Si-Si bond scission reactions. These polymers with silicon in the main chain are glassy materials with high TG’s, exhibit good solubility in common organic solvents and form films of excellent quality. Their absorption maximum is centred around 320 nm, making them especially sensitive to mid- or deep UV radiation (Wallraff et al., 1991). Upon exposure, photodegradation occurs through cleavage of the Si-Si bonds into silyl radicals and silylenes, which stabilize via hydrogen abstraction to fragmented polysilanes (Fig. 4-63). As a side reaction, photooxidation to polysiloxanes with smaller molecular weights was detected. The fragmentation is accompanied by a pronounced bleaching effect. An extensive discussion of polysilane photochemistry has been given recently (Miller and Michl, 1989). Not surprisingly, the oxygen etch resistance of polysilanes is comparable to that of polysiloxanes. A large variety of aliphatic or aromatic polysilanes together with sensitizing additives have been studied as positive-acting top resists by Miller et al. (1991) and Wallraff et al. (1991). They have spun high molecular weight materials from toluene solu-

220 100

1060 580

50

20

9

4

1.2

~ n lo3 / 0

0,

2,

4,

v

8 mJ/c

Figure 4-63. Change in molecular weight distribution of a 0.006% solution of poly(dodecy1methylsilane) upon irradiation with 0,2,4, and 8 pJ/cm2 at 3 13 nm. (Reproduced from Miller et al., 1989 with permission.)

244

4 Photolithography

tions on I pm thick hardbaked novolak films to yield adry film thickness of 0.1 pm. Their investigations revealed that high DUV sensitivity ( 15 mJ/cm’). high resolution. and clean oxygen RIE pattern transfer are possible. As main problems remain the low yield polysilane synthesis utilizing difficult-to-handle metallic sodium or potassium (Reiser, 1989). the exclusion of metallic impurities in the resist and the contamination of the exposure tools upon self development. Synthesis problems may be overcome by plasma deposition of polysilanes and, combined with dry development, this allows an all-dry lithographic cycle (Kunz and Horn, 1991; Joubert et al., 1994). Polysilyne derivatives have been explored as photoresists for ArF (193 nm) excimer laser lithography (Kunz and Horn, 1991 ). These materials are photooxidized to polysiloxanes upon exposure to high energy radiation. Wet development using po-

Poly-(allyltrimethylsilane-sulfur dioxide)

lar solvents yields a positive image with feature sizes smaller than 0.2 pm after oxygen RIE. Gozdz et al. ( 1986) prepared a bilayer resist by the copolymerization of sulfur dioxide, butene, and allyltrimethylsilane with 13% silicon content (Fig. 4-64), high ebeam sensitivity of 2 pC/cm2 and good resolution capability. Copolymers of 4-hydroxystyrene and vinyltrimethylsilane (Fig. 4-64) are excellent candidates for aqueous alkaline developable silicon-containing near and deep UV resists, as they show high transparency at 248 nm, no thermal flow up to 150°C and good oxygen RIE resistance (Sezi et al., 1989). Positive-acting DNQbased resists with a silicon content over 10% have been prepared by condensation of formaldehyde and a phenol with a siloxane group (Noguchi et al., 1990)(Fig. 4-64). Using a g-line stepper, 0.5 mm patterns were fabricated.

Silicon containing novolak resin OH I

-(-

CH~--CH-CHZ-CH-)CH3-SI-CH~

, , ,

CH3

C k

CHz

-~-si-o-)-~-sl-o-~ 0 OH

Vinyltrirnethylsilaneihydroxystyrene copolymer

(

SI

-

0

o-~-~-si-o-~--

CH2

/c:,

CHz , ,

A\

\-’, 4

OH Poly-(hydroxybenzylsilsesquioxane)

Figure 4-64. Exdmples of silicon containing positive working remt material5

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By acetylation of phenylsilsesquioxane oligomers, a g-line sensitive alkali developable resist with a thermal stability up to 400°C and an ultimate resolution of 0.35 pm was obtained by Tanaka et al. (1989). The alkaline soluble phenolic groups containing poly(4-hydroxybenzylsilsesquioxane) resin of Hitachi's organosilicon positive resist OSPR-1334 (Fig. 4-64), acts in combination with DNQs as i-line, or g-line sensitive, positive top resist (Sugiyama et al., 1988). OSPR contains 18% silicon, has a TG of 107"C, an 0,-RIE rate ratio to hardbaked novolak of 28 and is strippable with alkaline developers after pattern transfer (Nate et al., 1991). A t-BOC blocked resin of this type has been evaluated by Brunsvold et al. (1993b) as DUV resist for 64 MBit DRAM production. The top layer materials for the MLR systems described so far contain silicon incorporated in their polymer structures. Another approach is to add a low molecular weight poly(pheny1 silsesquioxane) to a conventional g-line DNQ-resist. This mixture is commercialized by Hitachi under the tradename RG 8500P and has a submicron resolution capability (Toriumi et al., 1987). 4.5.4 Top Surface Imaging

Surface imaging in combination with dry development by means of an oxygen plasma has been suggested as a method of overcoming the inherent limitations present in conventional wet development photolithography. The strategy is to enhance the oxygen etch resistance of a metal-free resist through selective incorporation of silicon into the latent resist image by a suitable technique during or after the exposure (Roland, 1991; Taylor et al., 1990). The advantage of this top surface imaging (TSI) technique is obvious: the formation of the silicon-containing protective layer requires only a surface

245

modification. This should result in a reduction of exposure time, and an alleviation of both the depth-of-focus and thin film interference problems, as multilayer performance can be obtained with a single layer resist process. 4.5.4.1 Gas Phase Silylation Systems

The most prominent TSI scheme is the so-called DESIRE-process (diffusion enhanced silylating resist), which was developed in the mid 1980s by Roland at UCB Electronics, and Coopmans at IMEC. The pronounced interest arises from the fact that resists, based on dyed DNQ-novolak chemistry, with reproducible properties are commercially available (Plasmask) for g-line (150-G), i-line (200-g) and DUV (301-u) applications (Roland et al., 1990; Bauch et al., 1991). A scheme of the negative-tone DESIREprocess is outlined in Fig. 4-65. The resist is imagewise exposed, subjected to a socalled presilylation bake at approx. 160"C, and silylated in the gas phase at elevated temperature (140 to 170°C) to form a thin resist layer rich in silicon, which builds up the etch resistant SiO, layer during the oxygen etch (Laporte et al., 1991). The selectivity of the silylation has been determined by Rutherford backscattering spectroscopy: The thickness of the silylated layer is in the range of 150 to 200 nm in the exposed, and only 5 to 10 nm in the unexposed areas (Dijkstra, 1991). The silylation mechanism is critical and has been investigated in detail by Visser et al. (1987). It is a kinetically controlled simultaneous diffusion/reaction process following Fick's diffusion law. Its diffusion coefficient depends on the PAC concentration. A thermally induced crosslinking reaction between the unphotolized PAC and the resin occurs in the unexposed areas during the

Previous Page

246 Resist

4 Photolithography

r--l

Dark area

0

Substrate

C&-

-* -Nz kT

,Novolak

p-j o=s=o

OH

I

OR

U

Bake & Silylation

Exposed area C%-)-

U

kT

Oxygen RIE

-+

- NH3 OH

0

Si(CH3)3

Figure 4-65. Process flow of the DESIRE process.

presilylation bake. Therefore only the exposed areas can accommodate a large volume of the silylation agent. Due to finite contrasts of both the aerial image and the silylation, sloped silylated profiles are obtained (Reuhman-Huisken and Vollenbrock, 1991; Taira et al., 1991). Using the common silylation reagents, only the hydroxyl moieties of the resin are silylated in the exposed regions. while the carboxylic acid groups of the ICA are not. The Plasmask g-line material incorporates about 1 1 % silicon, which is accompanied by a vertical and lateral resist swelling. While the vertical swelling does not affect the image accuracy, lateral swelling results in a kind of proximity effect, which may give rise to image distortions. The lateral swelling is influenced by the silylation agent and decreases in the following order (Dao et al., 1991): 1,1.3,3.5,5-hexamethylcyclotrisilazane (HMCTS) > heptamethyldisilazane (HeptaMDS)> hexamethyldisilazane (HMDS)>trimethylsilyl-diethylamine (TMSDEA) >> I1l,3,3-tetramethyldisilazane (TMDS) (Fig. 4-66); it has been

reported that the latter suppresses any swelling and improves the processing latitudes (Goethals et al., 1991). Several research contributions denote specific advantages or drawbacks of DESIRE, when applied to practical design, imaging problems and proximity effects (Op de Beeck et al., 1990; Garza et al., 1991; Goethals et al., 1994). The main obstacles to the application of this technology are additional costs for a silylation machine and a plasma reactor, and low wafer throughput (approx. 5- 15 wafer/h). The major lithographic concerns are that of linewidth loss during etching, proximity effects, and stripping of the patterned silicon-containing resist. However, several advantages, such as the very impressive CD control over topography, offset some of these drawbacks (Fig. 4-67). The potential of DESIRE i n production has been evaluated by Garza et al. (1991). The results from more than 1250 wafers indicate that it certainly extends the applicability of exposure equipment already in place. Linearity and process windows were found to be superior to standard resists. A study by Tak-


7

b C C b H-Si-N-Si-H

4

Trimethylsilyldiethylamine TMSDEA

7 Fb

H35 H3C-Si-N-Si-CH3

\

CI-b

Tetramethyldisilazane TMDS

247

Figure 4-66. Chemical structures of silylation agents.

/

H3C

CI-b

Hexamethyldisilazane HMDS

H,H3c CH3 N-S< ‘ / Si, N-H Ch’ ,N-S/ H

C b

Heptamethyldisilazane HeptaMDS

1,1,3,3,5,5-Hexamethylcyclotrisilazane HMCTS

Figure 4-67. 0.25 mm lines and spaces of the Plasmask resist over aluminium topography (ASM-L PAS 5000/ 70 DUV stepper (NA=0.42)). Courtesy of IMEC, Leuven, Belgium. Reproduced with permission.

ehara et al. (1991) using the i-line material revealed that the resolution limit ( 5 have been obtained. The TSI scheme has been applied to PBOCST CARS (Fig. 4-68). Imagewise DUV exposure is followed by a PEB, to deprotect the phenol, and a treatment with a metallization agent, e.g. HMDS (Willson et al., 1990), chlorotrimethylsilane, (dimethy1amino)-trimethylsilane (MacDonald et al., 199 1 ), or titanium tetrachloride (Nalamasu

Resist

I

I

et al., 1989). Upon oxygen plasma etching, a negative image is obtained. The process offers an excellent silylation selectivity, because the unexposed, blocked polymer does not react. A positive working process, called SABRE (silicon added bilayer resist), is applied as a bilayer scheme. A planarization layer is coated with a thin imaging layer (< 0.5 pm) of a standard DNQ-novolak resist, which allows high resolution. The unexposed areas of the top resist remaining after development are subjected to a silylation treatment i n the gas phase. Upon oxygen plasma etching of the bottom layer, positive relief images are obtained (McColgin et al., 1988). A surface imaging scheme to yield positive dry etch resistant materials upon DUV irradiation was first described by Mutsaers et al. (1990). It relies on the AHR concept (Lamola et al., 1991): irradiated areas crosslink upon the application of a PEB at 80 to 120°C and thus prevent silicon uptake in the imaged areas.

07s'

Substrate Exposure

CF3SO3

RH

(PpS

+

(PR + CF3S03H

-(&)-- -(d): Ch' I?CH2

H+ kT

Bake & Siiylatlon

Y F 0

0

Fh

0-c-C&

OH

AH3 kT

.u.

Oxygen RIE

Figure 4-68. Process flow of surface imaging with t-BOC reAiqs.

1

HMDS

+

Con

249


A similar concept is employed in a DUV TSI process, developed at Shipley, called SAHR (silylated acid hardening resist; Pavelchek et al., 1993). SAL 607, a negative CAR for e-beam irradiation, was selected as resist and TMSDEA was used as the silylating agent. A contrast value of 6 has been obtained using low exposure doses ( l l 0 mJ/cm2). The process has been transferred to e-beam lithography, resolving 0.3 pm patterns with doses c 10 pC/cm2 (Vachette et al., 1991). The SAHR concept has been evaluated for 256 MBit DRAM patterns (0.24 pm) using a special resist and TMDS (Han et al., 1993; Park et al., 1997). 4.5.4.2 Liquid Phase Silylation Systems

A new resist chemistry based on carboxylic acid anhydride groups in the resin gives access to liquid phase silylation (Sebald et al., 1990). In a bilayer system the developed top resist patterns are treated at room tem-

perature on normal puddle equipment with a nontoxic aqueous/alcoholic solution of a bisaminosiloxane, resulting in a time-controllable widening of resist lines, called CARL (chemical amplification of resist lines) process (Figs. 4-69 and 4-70). As resin, co- or terpolymers of maleic acid anhydride with trimethylallylsilane, styrene or maleimide are employed, which have high glass transition points and are transparent above 230 nm. The selection of the DNQPAC thereby determines the spectral sensitivity. The i-line version is commercially available from Clariant. As DUV and ebeam sensitive CARS for the CARL-process, t-BOC-blocked maleimide or t-butylmethacrylate copolymers in combination with onium salts have been applied (Leuschner et al., 1992, 1994; Hien et al., 1998). The incorporation of cyclic anhydride groups into the polymer is mandatory for the process. The anhydride moiety is opened by the amino groups of the siloxane under the

0

OH

b

U uuu ,,

d

TOPresist Bottom resist Substrate Exposure

I

I It

'7'

0

Bottomresist

I

I

-I

Top resist

OR

dR Alkaline 7H3

7H3

N-R-Si-(-O-Si-&o-R-NH2 I H? I CH3 CHI

2 :(:'+

U Aqueous/

alcoholic silylatlon

0 Oxygen RIE

H

-

Si CARL

-

TOP CARL

Figure 4-69. Process flow and chemistry of (left) the Si-CARL and (right) the Top-CARL process.

250

4 Photolithography

Figure 4-70. Lateral CD increase vs. vertical silylation increase of 180 nm nested lines (diagram) and selected crossection SEMs after development and after two different silylation conditions. (Reproduced from Hien et al. (1998) with permission.)

formation of carboxamide linkages and the respective ammonium salts, as evidenced by FTIR (Sebald et al., 1990). The silicon uptake of - 25% by weight is responsible for the high etch selectivity. The lateral widening of resist lines makes it possible to compensate for linewidth loss during 02-RIE and to print equal lines and spaces in the sub quarter micron domain (Franzen et al., 1998). Furthermore, chemical biasing (CARL effect) after wet development can be used advantageously for a dramatic increase of focus windows in the high resolution domain at k , < 0 . 5 . Bossung plots of 160 nm dense lines (simulated by Prolith/2) in Fig. 4-7 1 show that the isofocal point is obtained

.-E

-

024

3 020

Chemical Elaslng

016

'$

at an overexposure of approx. 60 nm i n this case, i.e., 100 nm lines and 220 nm spaces in resist. Using silylation conditions that increase the linewidth for 60 nm, the isofocal line is shifted to the target CD value and the maximum depth of focus is now available for the 160 nm equal lines and spaces in the resist (Fig. 4-7 1 ) . However, the silylation conditions and thus the extent of chemical biasing has to be adapted carefully in order to result in optimum process windows for a given target linewidth (Hien et al., 1998). Structures down to 0.3 mm were resolved with a g-line stepper (NA = 0.55) and 0.16 pm lines and spaces were achieved upon DUV exposure ( N A = 0.60), both cor-

(Silylatlon)

012

3 ow

!-I

Poor process window -06

-04

-02

Eesl

02

Fms

Focus Setting [pm]

0.04

Large process window 04

06

-06

-04 - 0 2

Best Fours

0.2

04

06

Focus Setting [pm]

Figure 4-71. Concept of Chemical Biasing in the CARL process shown for 160 nm dense lines. (Reproduced from Hien et al. (1998) with permission.)


responding to a k , factor of 0.38 (Sebald et al., 1990; Hien et al., 1998). The CARL process gives photolithographical accessibility to space dimensions that are beyond the resolution limit of the optics used; even 170 nm spaces and 150 nm contact holes have been made by Sebald et al. (1990) with i-line exposure ( N A = 0.40) and simply controlling exposure dose and silylation time. Recently, the CARL process has been applied in volume production with good CD control over severe topography and a defect density comparable to standard lithography (Franzen et al., 1998). Figure 4-72 demonstrates the resolution capability and focus latitude of the CARL process with 193 nm exposure wavelength. In a dry developing scheme called TopCARL the same chemistry is applied but the

251

development step is omitted (Sezi et al., 1990). A thin film (0.4 pm) of an anhydridecontaining copolymer and a DNQ-PAC is coated on a hardbaked bottom resist. The top layer is imagewise exposed, silylated selectively in the exposed areas and then dry developed to yield negative patterns (Fig. 469). The high etch stability of this system makes it possible to print 0.40 pm patterns in 2 ym thick resist with an i-line stepper (NA= 0.40) or structures with steep profiles in up to 42 pm thick polyimide layers (Leuschner et al., 1993). A positive working variant makes use of a photobase additive to the DNQ-based resist and an image reversal bake with subsequent flood exposure to change the tonality of the resist (Leuschner et al., 1993). For DUV exposure, a CAR version of the Top-CARL re-

Figure 4-72. (a): Crossection SEMs of 130 nm isolated and dense lines and 120 nm dense lines after dry development (imaging dose=6 pJ/cm2) best focus, standard illumination, COG mask); (b): Top view of dry developed 130 nm dense lines at different focus settings (values given in pm, imaging dose=6 pJ/cm2) (Reproduced from Hien et al. (1998) with permission.)

252

4 Photolithography

Silylation agent

Silylation time (min)

OH-silylation ( )

COOH-silylation (YO)

77.0 79.0

55.4

Figure 4-73. Chemical structures of several silylation agents with Si-N units, and the degree of phenolic OH-group and indene COOH-group silylation. (Data taken from Babich et al. (1991) with permission.)

58.9

H,

CH3

H> ?-Ai: *Si; N-H C&’ ,N- S i I ‘CH3 H H

2

26.6

62.1

4

35.5

69.3

2

20.0

56.5

4

21.7

61 .O

1.7

2.6

1.7

4.8

H

CH3’

‘CH3

sist has been evaluated by Sezi et al. (1991) using a copolymer containing the r-butylester group and a PAC. It shows a high silylation contrast and resolves 0.30 pm patterns in 1.8 pm resist thickness with a DUV stepper ( N A =0.37). While the CARL process employs an aqueous phase based silylation, Yang et al. (1989) and Stewart et al. (1990) have investigated solvent based liquid phase processes with a variety of polyfunctional organosilicon compounds (Fig. 4-73). DNQ-novolak based resists are imagewise exposed, developed and treated with a xylene or n-decane solution containing a resist solvent as diffusion promoter and a silylation agent, e.g. hexamethylcyclotrisilazane (HMCTS; Stewart et al., 1990). orbis (dimethylamino) dimethylsilane (BDMADS; Babich et a]., 1991). In contrast to vapour phase silylation, liquid silylation causes crosslinking of

the resist and drives more silicon into it, resulting in higher thermal resist stability and better etch resistance. An ultimate resolution of 50 nm has been obtained by Vettiger et al. (1989). In a single layer arrangement, negative or positive tone patterns can be printed when the Plasmask 200-G or the acid hardening resists AZ 5214 and SAL-601 are used, respectively (Baik et al., 1993; Gogolides et al., 1994; Kerber et al., 1992). In the latter case, crosslinking of the exposed areas prevents penetration by the liquid silylation agent.

4.6 Trends in Photolithography Tremendous progress has been made in the development of new lithographic techniques during the last few years. Despite this, i t is anticipated that the majority of vol-

4.6 Trends in Photolithography

ume-orientated production processes will continue to use the established optical lithographic methods, mainly due to cost reasons and practical experience of the workforce. Wafer fabrication will continue to be a mix-and-match situation with state-ofthe-art lithography being used only for the most critical applications. Delineation of reproducible 0.25 pm patterns (and below) with high throughput seems to be the barrier for current i-line lithography. Short wavelength optical lithography using 248 nm or 193 nm excimer laser based systems is the candidate to delineate high resolution features down below 0.18 pm, and 0.13 pm, respectively, without any restrictions to pattern layout. Phase shifting mask or off-axis illumination techniques improve the resolution capability, but these approaches are not as easy to apply to isolated or random patterns (Okazaki, 1991). The combination of high NA DUV stepper with phase shifting mask and off-axis illumination seems to offer reasonable process windows even for ~ 0 . 1 pm 8 patterns (Van den hove and Ronse, 1994). An extension to sub 0.15 pm patterns using ArF lithography seems plausible. Next generation DUV lithography (157 nm) might even be able to print features well below 100 nm by using of F, excimer lasers and CaF, optics and masks in vacuum (Bloomstein et al., 1997). Tighter CD control and increasing reflection problems will expand the use of top and bottom antireflective coatings, thus blurring the current borders between single and multilayer resist applications. The depth-of-focus problem and the high absorbence of etch resistant materials stress the need for top surface imaging systems (Hartney et al., 1992). Approaching the resolution limits, optical proximity effects will become dominant and require sophisticated proximity correction strategies (Van den hove and Ronse, 1994).

253

X-ray lithography offers the potential to print features below 0.10 pm, but still suffers from difficult mask fabrication, inspection and repair, because the required accuracy for 1 : 1 X-ray masks is at least one magnitude higher than for optical reticles. Although the general infrastructure has been improved, several issues, such as metrology have not yet been addressed, and the rapid progress of optical lithography keeps XRL on the waiting list. Soft X-ray (13- 16 nm) projection lithography has considerably matured during the last few years. Despite the progress made in the coating techniques (White et al., 1991; Ito et al., 1994; Montcalm et al., 1998), the required reflection optics need improvements with respect to alignment, optical substrates and stage scanning (Sweeney et al., 1998; Kinoshita et al., 1998). And for all next generation lithography technologies mask fabrication is a challenge because chrome-coated quartz glas is no longer the mask material of choice (Abboud et al., 1998). Advanced parallel printing e-beam systems, like cell projection lithography, may develop to a competitive technique with respect to resolution and throughput. Questions remain with respect to wafer heating in the exposed areas, proximity correction and device damage due to high voltage. Fascinating evolutionary concepts, like the high voltage SCALPEL approach (Liddle et al., 1997) or the parallel-working direct writing system based on micro columns operating at low voltage may provide the best choices for future nanolithography (Chang et al., 1992; Kratschmer, et al., 1995). Ion projection lithography, however, has proven its capability to print sub-100 nm patterns (Mohondro, 1997). Independently of the above-mentioned advanced lithographic techniques, resist sensitivity will be an important issue because all new lithographic approaches pro-

254

4 Photolithography

vide lower radiation densities than conventional exposure tools. Therefore chemical amplification systems may be a prerequisite for cost-effective production of post 64 MBit DRAM generations, thus posing significant quality and specification control challenges to the resist suppliers. To avoid delay time effects between exposure and post exposure bake, improved cluster processes using environmental chambers have to be developed (Holmes and Sturtevant. 1993). Besides sophisticated lithographic techniques new IC-generations require improved design concepts like e.g. pass-transistor circuits or silicon-on-insulator MOS devices (Takeda. 1994) and new multilevel metallization techniques (e,g, global planarization by chemical-mechanical polishing (Murarka and Hymes, 1995). copper interconnects (Li et al., 1994) or new nonsilicon based elements with reduced space consumption, like giant magnetoresistance ratio materials as memory cells (Nordquist et al., 1997). Future electronics beyond the year 2000 may have totally different designs since even smaller feature sizes go hand in hand with even less controlled electrons per action which sets a trend towards single electron devices (Rohrer, 1994). On the other side, photolithography will be extended to even larger feature sizes for micro-mechanical or optical purposes thus providing integrated devices and machines with elements ranging from the nanometer to the millimeter scale.

4.7 References The literature cited here mainly considers articles published after 1987. Older publications can be found in the citation lists of these articles.

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4.7 References

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Cagan, M., Blanco, M., Wise, V., Trefonas, P., Daniels, B. K., McCants, C. A. (1989), Proc. SPlE 1086, 515. Cameron, J. F., Adams, T. G., Orellana, A. J., Rajaratnam, M. M., Sinta, R. F. (1997). Proc. SPlE 3049, 473. Cernigliaro, G. J., Cronin, M. F., Fisher, T. A,, Perkins, M. E., Turci, P. (1989), Proc. SPIE 1086, 106. Cerrina, F. (1992), Jpn. J. Appl. Phys. 31, 4178. Chaker, M., Boily, S . , Ginovker, A,, Jean, A,, Kieffer, J. C., Mercier, P. P., Pepin, H., Leung, P. K., Currie, J. F., Lafontaine, H. (1991), Proc. SPlE 1465, 16. Chalupka, A , , Fegerl, J., Fischer, R., Lammer, G., Loscher, H., Malek, L., Nowak, R., Stengl, G., Traher, C., Wolf, P. (1992), Microelectr: Engin. 17, 229. Chang, T. H. P., Muray, L. P., Staufer, U., Kern, D. P. (1992), Jpn. J. Appl. Phys. 31, 4232. Chiong, K., Wind, S., Seeger, D. (1990), J. Vac. Sci. Technol. B8, 1447. Chu, R., Greeneich, J., Katz, B., Lin, H.-K., Huand, D. T. (1991), Proc. SPIE 1465, 238. Classen, A,, Kuhn, S., Straka, J., Forchel, A. (l992), Microlectr: Eng. 17, 21 Clube, F., Gray, S., Struchen, D., Tisserand, J.-C. (l993), Optical Engin. 32(10), 2403. Conley, W., Brunsvold, W., Ferguson, R., Gelorme, J., Holmes, S., Matino, R., Petryniak, M., Rabidoux, P., Sooriyakumaran, R., Sturtevant, J. (1993), Pruc. SPIE, 1925, 120. Conley, W., Brunsvold, B., Buehrer, F., Dellaguardia, R., Dobuzinsky, D., Farrell, T., Ho, H., Katanani. A., Keller, R., Marsh, J., Muller, P., Nunes, R., Ng, H., Oberschmidt, J., Pike, M., Ryan, D., CotlerWagner, T., Schulz, R., Ito, H., Hofer, D., Breyta, G., Fenzel-Alexander, D., Wallraff, G., Opitz, J., Thackeray, J., Barclay, G., Cameron, J., Lindsay, T., Cronin, M., Moynihan, M., Nour, S., Georger, J., Mori, M., Hagerty, P., Sinta, R., Zydowsky, T. (1997), Proc. SPlE 3049, 282. Cowie, J. M. G . (1994), Advanced Materialsfor Oprics and Electronics 4, 155. Crivello, J. V. (1984), Adu. Polym. Sci. 62, 1 Crivello, J. V., Lee, J. L., Conlon, D. A. ( 1 988), Makromol. Chem. Makromol. Symp. 13/14, 145. Cromer, E. G. (1993), Solid State Technol. 36 (41, 23. Dammel, R. (1993), Diazonaphthuqinone-based Resists, SPIE Optical Engineering Press, Bellingham, Washington, USA. Dammel, R., Doessel, K. F., Lingnau, J., Theis, J., Huber, H. L., Oertel, H. (1987), Micruelectr: Engin. 6, 503 Dammel, R., Lindley, C. R., Meier, W., Pawlowski, G., Theis, J., Henke, W. (1990), Proc. SPIE 1264, 26. Dammel, R., Rahman, M. D., Lu, P. H., Canize, A,, Elango, V. (1994), Proc. SPIE, 2195, 542. Dao, T. T., Spence, C. A,, Hess, D. W. (1991), Proc. SPlE 1466, 257.

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4 Photolithography

Das, S., Thackeray, J. W.. Endo. M.. Langston. J., Caw. H. (1990). Proc. SPIE 1262, 60. Dijkstra, J. (1991). Proc. SPlE 1466, 592. Ehrfeld. W., Schmidt, A. ( 1998). J . Vac. Sei. Tech. B (Microelectronics and Nanometer Structures), vol. 16. no. 6, pp. 3.526-3534. Einspruch, N.G . (ed.) (198.5). V I S 1 H ~ l d h ( l ( J k Aca, demic Press, New York. Endo. M., Sasago. M., Hirai. Y.. Ogawa, K., Ishihara. T. (1989), J. Electrochem. Soc. 136. 508. Endo. M., Tani. Y., Yabu. T.. Okada, S., Sasago, M.. Nomure. N. ( I99 1 1. J . Phoropolytt~.Sci. Technol. 4 . 361. Fahey, J., Moreau. W., Welsh. K.. Miura, S.. Eib. N.. Spinillo, G. (1994). Proc,. SPIE, 2195. 422. Feely. W. E. (1985). EP 164 248 (Rohm & Haas) Flarnm. D. L. ( 1992). S<J/it/Srare Techriol. 35 (X),37 arid 3s (91. 43. Fouassier. J. P. ( I989), in Photopolymeri,ation sciCIW iriid techriology, Allen. N . S . ed., Elsevier Publ.. London. Fracko\,iak, J., Celler. G. K., Jurgensen, C . W.. Kola, R. R.. Novembre. A. E.. Tomes. D. N.. Trimble, L. E. (1993). Proc. SPlE 1924. 258. Franzen, R., Grassmann. A,. Kirschinger. M., Schedel, T.. Wiedenhofer. H.. Witte, M. ( 1998). Proc. SPIEInr. So(,. Opr. D i g . , vol. 3333, pt. 1-2, pp. 860-868. Frechet. J. M. J., Stanciulescu. M.. Iizawa, T., Willson, C . G . ( 1989j . Polymer Mater: Sci. Eng. 60. 170. Frechet, J. M . J., Krycrka. B.. Matuszczak. S., Reck. B., Stanciulescu. M., Willson, C . G . ( 1990), J . Phoropolym. Sci. Technol. 3. 235. Frechet, J. M. J . , Matuszczak, S.. Lee, S. M., Fahey. J.. Wil1son.C. G . ( 1991 1. Proc. SPEEl1enw”le 1991, 31. Fujimoto. M., Hashimoto. T., Uchiyama, T.. Matsuura. S.. Kasarna, K. ( 1997). Proc. SPIE-lnr. Soc. Opt. Eng., vol. 305 1 pp. 739-750. Fukuda, H . , Okazaki. S. (19901, J . E/ectrochem. Soc. 137 (21, 675. Fukuda. H., Imai. A,. Terasawa. T.. Okazaki, S. ( 1991 ). IEEE Truns Electrori Dei: ED-38. 67. Fukuda. H., Kobayashi. Y.. Tawa. T., Okazaki, S . ( 1994). Interri. Cori,f on Mic,ro- rind Natio-Engineering 94, Davos ( C H ) . Sept. 26-29, paper D2/3. Fukumoto. H.. Okuda. Y., Takashima, Y., Ohkurna, T.. Ueda. S.. Inour. M . (1989), J . Photopolyrn. Sci. Techno/. 2. 365. Gardiner. A . B.. Qin, A , . Henderson. C . L., Pancholi. S.. Koroj. W. J . . Willson. C . G . . Darnrnel, R. R.. Mack. C.. Hinsberg. W. D. ( 1997 j Proc. SPIE 3049. x50.

Gargini. P.. Glare. J . . Williams. 0. ( 1998). Solid StrIre Tec,/irio/. 41 f I ) , 73. Garza. C . M., Catlett. D. L.. Jackson. R . A . (1991 1. P,nc,. SPIE i466.6 16. Goethals, A . M . , Baik, K. H., Van den Hove, L., Tedesco. S . ( 1991 ). Proc. SPlE 1466, 604. Goethals. A . M.. Balk. K. H., Ronse. K.. Vertomrnen. J.. Van den Hobe. L. (1994). Proc. SPIE. 2195. 394.

Gogolides, E., Baik, K. H., Yannakopoulou, Van den Hove. L.. Hatzakis, M . (1994), Microelecrr: Engin. 23, 267. Gozdz. A. S., Carnazza, C., Bowden, M. J. (1986). P r ~ cSPlE . 631, 2 . Greeneich, J.. Katz, B. ( 1990), Solid Srate Technol. 3 3 f 3 ) .6 3 . Grunwald, J. J., Gal, C., Spencer, A. C., Eidelman, S. ( I990j, Proc. SPlE 1262, 444. Guo. J . Z. Y., Cerrina, F. ( 199 1 ), Proc. SPlE 1465,330. Gutrnann, A., Binder, J., Czech, G., Karl, J., Mader, L., Sarlette, D., Henke. W. (1990a), Proc. SPlE 1264. 40. Gutmann, A., C x c h , G., Lenz, H., Meier, W. (1990b). Microelectr: Eng. 11, 565. Hacker, N. P., Welsh, K. M . (1991). Proc. SPlE 1466, 384. Halle, L. (1985), J . Vac. Sei. Techno/. 53, 323. Han, W.-S., Lee, J.-H.,Park, J.-C., Park, C.-G., Kang, H.-Y., Koh, Y.-B., Lee, M.-Y. (1993), Proc. SPlE 1925. 29 1 , Hanabata, M., Furuta, A., Uemura, Y. (1986), Proc,. SPlE 631, 76. Hanabata, M.. Oi, F., Furuta, A . (1991), Tech. Paper of SPE Regional Conf on Photopnlymer.r, Ellenville ( N . Y.) 1991, 77. Hanabata, M., Uetani, Y., Furuta, A. (1989), J . Vac. Sci. Technol. 57, 640. Hanawa R., Uetani. Y., Hanabata, M . (1993), Proc. SPIE, 1925, 227. Hanson, J. E., Reichrnanis, E., Houlihan, F. M., Neenan, T. X. (1992). Chem. Marer: 4 , 837. Hartney, M . A . (1994), Advanced Materials f o r Optics and Elec~rronic.~, 4, 165. Hartney. M . A.. Hess, D. I%., Soane, D. S. (1989), J. Vac. Sci. Technol. B7, I . Hartney. M . A., Horn, M . W., Kunz, R. R., Rozhschild, M., Shaver, D . C . (1992), Microlirhogr. Worlrl I ( 2 ) *16. Hashimoto, S., Itani, T., Yoshino, H., Yarnana, M., Samoto, N., Kasarna. K. ( l 9 9 6 ) , J . Phoropolym. Sci. Technol. 9, 59 1. Hattori. T., Schlegel, L., Irnai, A , , Hayashi, N., Ueno, T. (1993), P r ~ c SPlE . 192S, 146. Hatzakis, M., Shaw, J., Babich, E., Paraszczak, J. ( 1988), J . Vac. Sei. Technol. B6, 2224. Hatzakis, M., Stewart, K. J., Shaw, J. M., Rishton, S. A. ( 199 I ), J . Electrochem. SOC.138, 1076. Havashi, N.. Tadano. K.. Tanaka. T.. Shiraishi. H.. Ueno, T.. Iwayanagi, T. ( I 990), Jpn. J . Appl. Phys. 29 ( 1 11. 2632. He. Q., Krisa, W. L., Lee, W. W., Hsu, W. Y., Tang, H. (1997), Proc. SPlE 3049, 988. Hesp, S . A. M.. Guillet, J . E. (1990), in Tabata, Y. et al. (ed.), Polymers f o r Microelectronics - Sciene and Technology. Kodansha, TokyolVerlag Chernie, Weinheirn, I 13. Hien, S., Czech, G., Dornke, W.-D., Raske, H., Sebald. M., Stiebert. I . (1998), Proc. SPIE-lnr. Soc. Opr. Eng., vol. 3333, pt. 1-2, p p ~154-164.

4.7 References

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Ito, H., Willson, C. G., Frechet, J. M. J. (1987), Proc. SPlE 771, 24. Ito, H., Flores, E., Renaldo, A. F. (1988). J. Electrochem. SOC.135, 2328. Ito, H., Schildknecht, K., Mash, E. A . (1991), Proc. SPIE 1466, 408. Ito, H., England, P., Clecak, N. J., Breyta, G., Lee, H., Yoon, D. Y., Sooriyakumaran, R., Hinsberg, W. D. (1993), Proc. SPIE 1925, 65. Ito, H., Breyta, G., Hofer, D., Sooriyakumaran, R.; Petrillo, K., Seeger, D. (1994), J . Photopolym. Sci. Technol. 7, 433. Ito, M., Oizumi, H., Yamanashi, H., Ogawa, T., Katagiri, s.,Seya, E., Takeda, E. (1994). Intern. Con& on Micro- and Nano-Engineering 94, Davos (CH), Sept. 26-29, paper J l / l . Jagannathan, P., Huang, W. S., Katnani, A. D., Hefferon, G. J., Wood, R. L. (1994), Proc. SPIE, 2195, 28.

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258

4 Photolithography

Koshiba. M.. Murata. M.. Matsui. M.. Harita. Y. (1988). Proc. SPIE 920, 364. Kowaka. M.. Kobayashi. Y.. Wakabayashi, O., Itoh, N., Fujimoto, J.. Ichihara. T., Nakarai. H., Mizoguchi. H.. Amada. Y.. Norue. Y. (1993). Proc. S P I E 1927. 241. Kratschmer, E.. Kim. H. S.. Thomson. M. G . R . , Lee, K. Y.. Rishton. S. A., Lu, M. L.. Chang, T. H. P. (1995). J . VUC.Sci. Tec,/itiol. B13, 2498. Krisa, W. L.. G a m . C., McKee. J. ( 1996). Proc. SPIE 2724. 724. Kudo. T.. Nanjo. Y.. Nozaki. Y.. Nagao, K.. Yamaguchi, H., Kang. W. B., Pawlowski, G . (1996a). J . Photopolytn. .%i, Techno/. 9. 109. Kudo. T.. Nozaki. Y.. Nanjo. Y.. Yamaguchi, H., Nagao, K.. Okazaki. H., Pawlowski. G . (1996b). J. Photopolxrn. Sci. Techno/. 9, 12 1 , Kudo. T.. Aramaki. M . . Pawlowski. G. (1998), J . of Photopol. Sci. Tedi., vol. 1 I , no. 3, pp. 445454. Kumada, T.,Tanaka. Y.. Ueyama, A,. Kubota. S.. Koew k a . H . . Hanawa. T.. Morimoto. H. (1993). Proc. SPIE. 1925, 3 1 . Kunz.R. R., Horn, M. W. (1991).Tech. P a p e r o f S P E Regimnul Con$ on Photopolwiers, Ellenville f N . Y j 1991, 291. Kunz. R. R.. Palmateer. S. C., Forte. A. R., Allen, R. D.. Wallraff., G . M., Di Pietro. Hofer. D. (1996). Proc. SPlE 2724, 365. Kuyel. B., Barrick. M., Hong. A , , Vigil, J. (1991). Proc. SPlE 1463 646. Kyser. D.. Viswanathan. N . S. ( 1975). J . VW. Sci. Techno/. 12, 1305. Lai, K., Chen. S., Kahsab. B., Bunday. B. D., Liu. Z., Samarakone, N. ( 1997). Pro an arrow) in a (001)Si sample implanted with 100 keV Si' ions to a dose of 2 x IO" cm-' (Narayan and Holland, 19841.

Figure 5-21. High resolution electron micrograph showing the interface between amorphous and crystalline Si. Note the presence of microcrystals in the amorphous regions that are indicated by an arrow (Narayan and Holland. 1984).

-

5.3 Ion Implantation

50nm

loo

t

1

-I a-GaAs

1

285

50 nm

100

150

200 Dislocations Isolated Faults

300

t

Unannealed

1

350

400°C 350

Figure 5-22. Schematic diagram of damage distribution in (001) GaAs samples implanted with a dose of 1014 Se' ions cm-' at 450 keV (Sadana et al., 1985).

Figure 5-23. Schematic diagram illustrating the damage distribution observed after the annealing of GaAs samples implanted with l O I 4 Se' ions cm-2 at 450 keV (Sadana et al., 1985).

are electrically active, as-implanted materials have poor electrical characteristics. Generally, the minority carrier lifetime and mobility are severely degraded after ion implantation. Furthermore, only a fraction of the implanted ions are located on substitutional sites and contribute to the carrier concentration. To eliminate the detrimental effects of ion implantation, the material has to be annealed at elevated temperatures. This procedure serves two purposes. First, the point defect density is reduced because of the annihilation of some of the vacancies by the interstitials. Second, the implanted dopant atoms in interstitial sites could m,igrate to lattice sites and become electrically active. It is emphasized that unless the implantation energy and doses are

low, the implanted material cannot be restored to its pristine condition by annealing. This limitation has not so far posed a problem in the fabrication of devices using ion implantation. The residual damage after annealing may consist of dislocation loops, dislocations, faults, and twins. This is illustrated in Fig. 5-23 for -(001) GaAs implanted with 1014 Se' ions cm-2 at 450 keV, and subsequently annealed at 400°C (Sadana et al., 1985). Comparing Figs. 5-22 and 5-23, it is clear that the extrinsic dislocation loops form in the channeled cascades, whereas isolated faults and dislocations are seen near the original amorphous-crystalline interface. A high density of faults is observed in the formerly amorphous region.

286

5 Selective Doping

In addition, the orientation of the crystalline region is replicated in the volume that evolves from the amorphous solid during annealing. This is only possible if the crystalline region in Fig. 5-22 serves as a template during the amorphous-to-crystalline transition on annealing. This type of growth is referred to as solid phase epitaxy. The production of damage during ion implantation is statistical in nature, and this affects the damage distribution. It is, therefore, difficult to predict a priori the type and the nature of the residual damage after annealing. However, some generic ideas can be developed to understand the evolution of the defect structure during annealing. When the implanted materials are annealed, vacancies and interstitials that are within the capture volume of one an other are annihilated. Complete mutual annihilation of the two types of defects is not possible because of their spatial separation. Consequently, after a short anneal, the implanted material will contain residual concentrations of the two types of point defect. However, the respective distributions and concentrations of the point defects are different in the two cases. O n further annealing, the point defects coalescence together to form intrinsic and extrinsic faulted dislocation loops lying on { 111) planes that are bounded by ( a / 3 ) (1 11) Frank partials. The driving force for the coalescence is the reduction in the surface energy of the defects. To form such loops in group 111-V materials, groups 111 and V vacancies and groups 111 and V interstitials are required simultaneously. The faulted loops can grow on further annealing. This is achieved by absorption of the appropriate point defects at the cores of Frank partials. When the loops grow, their energies increase because the fault area and the length of the partial increase. At a certain size, the energy of the faulted

loop will become equal to that of the unfaulted loop bounded by f( 4 2 ) (1 10) dislocations. Conversion of the faulted loops into unfaulted loops is accomplished by the passage of Shockley partials across the fault planes. If the implanted material is still saturated with point defects, perfect loops can also expand by the absorption of point defects. During growth, different loops may interact with each other according to the following reaction to form a dislocation network:

Generally, the covalent tetrahedral radii of the implanted ions are different from the radii of the host atoms. Consequently, the occupation of substitutional sites by implants during annealing would lead to local strains. The overall strain energy of the system can be lowered by the migration of implanted atoms to dislocation loops and dislocations produced during the anneal because of favorable elastic interactions of the dislocation and the impurity strain fields. The fault bundles shown in Fig. 5-23 are very likely growth faults. If the amorphousto-crystalline transformation occurs at a very rapid rate, growth mistakes can occur in the { 11l } stacking sequence, leading to stacking faults. This situation may be further complicated by stresses that may develop in the lattice due to the incorporation of dopant atoms of different tetrahedral radii. Now let us apply the above generic ideas on damage production and annealing to two specific situations: the isochronal annealing behavior of Si implanted with B or P ions. Figure 5-24 shows the isochronal annealing behavior of B ions implanted into Si at 150 keV and at three different doses (Seidel and McRae, 1971). The low-

5.3 Ion implantation

1.o

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1

I“

a

0.1

0.01 400 500 600 700 800 900 1000

T/J0C) Figure 5-24. Isochronal annealing behavior of B. The ratio of free carrier concentration, PHall, to dose, I$, is plotted against the anneal temperature, T,, for three doses of B.

dose samples implanted to 8 x 10” cm-’ show a monotonic increase of the free carrier concentration, i.e., PHallin Fig. 5-24, implying that the implanted ions shift to lattice sites on annealing. However, the annealing behavior of the samples implanted to higher doses is much more complex and can be divided into regions I, 11, and 111. In region I, the free carrier concentration increases with the annealing temperature. Extended defects, such as faulted dislocation loops, are not observed in this regime. The plausible explanation is that B atoms are migrating to the lattice sites during annealing. In region 11,the free carrier concentration decreases with increasing temperature. In addition, a dislocation substructure is observed after annealing. It is likely that B atoms migrate to the dislocation cores. This is due to the fact that B atoms are extremely small and will have strong elas-

287

tic interactions with dislocation cores. Once the dopant atoms are removed from substitutional sites, they will not contribute to the free carrier concentration. In region 111, the free carrier concentration increases with increasing temperature, indicating that B atoms are returning to the lattice sites. This suggests that the binding energy between B atoms and dislocations is overcome thermally. The released B atoms migrate to the lattice sites and increase the carrier concentration. It is apparent from the above example that interactions between the implanted atoms and the annealing-induced defect structure could complicate the activation of the dopants. To develop a full understanding of the behavior of the implanted dopants during annealing, electrical measurements must be coupled with structural observations. Figure 5-25 shows the isochronal annealing behavior of P ions implanted into Si at 250 keV and at six different doses (Crowder and Morehead, 1969). Comparing Figs. 5-24 and 5-25, it is clear that the annealing behaviors of Si implanted with B or P are qualitatively different. When the dose is increased from 3 x 1 O I 2 to 3 x 1014 ions/ cm’, higher annealing temperatures are required to eliminate the progressively more complex damage. Amorphous layers are produced at doses of 1 x 10” and 5 x 10” cm-’, and they extend to the surface. On annealing, the amorphous-tocrystalline transition occurs by solid-phase epitaxy. During regrowth of the amorphous layers, the implanted atoms are incorporated into substitutional sites. Furthermore, after annealing, the carrier concentrations in the samples implanted to higher doses are lower than the low dose specimens. It could be that after annealing the residual damage in the high-dose samples is considerably more extensive.

288

5 Selective Doping

280 keV Phosphorus

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The annealing behavior of Si implanted with As or Sb ions at room temperature is similar to that for P ions, except that lower doses are required for amorphization. This is due to the fact that As and Sb ions are considerably heavier than P ions. (The doping of compound semiconductors by ion implantation is also treated in Chap. 10 of this Volume.)

5.4 Comparison Between Diffusion and Ion Implantation for Selective Doping For selective doping, ion implantation is superior to chemical diffusion because the lateral diffusion effects are minimal. As a result, implantation has essentially replaced diffusion doping in the fabrication of stateof-the-art microcircuits. Ion implantation offers the following advantages over diffusion doping: 1. The total amount of dopants introduced can be controlled because it depends on the total ion flux.

Figure 5-25. The ratio of free carrier concentration N,,,,to dose $ plotted against the anneal temperature (TA)for various P doses. The solid curves represent amorphous layers that anneal by solid phase epitaxy. The dashed curves represent implantation where the damage is not amorphous (Crowder and Morehead, 1969).

2. The dopant can be deposited uniformly over a large wafer by carefully designing the rotation and translation of the wafers through the ion beam. 3. The penetration depth of ions into a substrate increases with increasing accelerating voltage. Therefore, by varying the voltage, the implant depth can be controlled. 4.For Si and group 111-V technologies, ion implantation is generally carried out below 673 K. Consequently, the thermal stability requirements on mask materials are less stringent than those for chemical diffusion; silica, silicon nitride, and different metallizations can be used as masks for selective doping. 5. A wide range of ion doses, l o l l to i o i 7cm-2, i.e., from very low to very high, can be delivered to substrates and the dose can be accurately controlled ( -t 1 YO). The lateral uniformity in the ion concentration is also fairly good. In both of these aspects, ion implantation is superior to chemical diffusion. 6. Various ions can be mass separated to produce monoenergetic, highly pure, dopant ion beams.

5 . 5 References

7. Ion implantation is a nonequilibrium process. It is therefore possible to dope the substrate in excess of the solid solubility limits in the host lattice. However, for implanted species to remain in solution, the wafers should not be subsequently processed at high temperatures where excess dopant atoms become mobile and cluster together to form precipitates. There are some inherent disadvantages to ion implantation. The high-energy ions damage the lattice. Therefore, the implanted materials must be annealed at high temperatures to “heal” them. Since Si is quite stable at high temperatures, the annealing step does not entail any problems. However, in implanted group 111-V materials the group V atoms tend to boil off due to their high vapor pressures. Another complication is that the implanted profile may change during annealing because of bulk diffusion. The equipment for ion implantation is highly sophisticated, is very expensive, and has to be manned by experienced operators. However, the high degree of process control results in reproducible dopant profiles, and this has made ion implantation the method of choice for doping semiconducting wafers.

289

Ghandhi, S. K. (1983), VLSI Fabrication Principles. New York: Wiley. Gosle, U., Morehead, F. E (1981), J. Appl. Phys. 52, 4617. Kennedy, D. P., O’Brien, R. R. (1965), IBM J. Res. Devel. 9, 179. Levine, E., Washburn, J., Thomas, G. (1967), J. Appl. Phys. 38, 61. Lindhard, J., Scharff, M., Schiott, H. (1963), Mat.Fys. Medd. K. Dan. Vidensk. Selsk. 33, 1. Narayan, J., Holland, 0. W. (1984), J. Appl. Phys. 56, 2913. Prussin, S. (1961), J. Appl. Phys. 32, 1876. Ravi, K. V. (1981), Imperfections and Impurities in Semiconductor Silicon. New York: Wiley. Sadana, D. K., Zavada, J. M., Jenkinson, H. A . , Sands, T. (1985), Appl. Phys. Letts. 47, 691. Seeger, A., Chik, K. P. (1968), Phys. Status Solidi 29, 455. Seidel, T. E., MacRae, A. U. (1971), in: f s t Int. Con$ on Ion Implantation: Eisen, E, Chadderton, L. (Eds.). New York: Gordon and Breach. Shaw, D. (1975), Phys. Status Solidi 72, 11. Shewmon, P. G. (1963), Diffusion in Solids. New York: McGraw-Hill. Smith, B. (1977). Ion Implantation Range Data for Silicon and Germanium Device Technologies. Forest Grove, OR: Research Studies. Sze, S. M. (1985), Semiconductor Devices, Physics and Technology. New York: Wiley. Tan, T. Y (1994), in: The Encyclopedia of Advanced Materials. Bloor, D., Brook, R. J., Flemings, M. C., Mahajan, S. (1994), Oxford: Pergamon, p. 635. Tan, T. Y., Gosele, U., Ya, S . (1991), Crir. Rev. Solid State Mater. Sci. 17, 147. Yu, S., Gosele, U., Tan, T. Y. (1989), J. Appl. Phys. 66, 2952.

General Reading

5.5 References Crowder, B. L., Morehead, E E , Jr. (1969), Appl. Phys. Lett. 14, 313. Fair, R. B. (1981), in: Impurity Doping Processes in Silicon: Wang, E E Y. (Ed.). New York: NorthHolland, Chap. 7.

Bentini, G. G., Golanski, A , , Kalbitzer, S. (Eds.) (1989), Deep Implants. Amsterdam: North-Holland. de Souza, J. P., Sodana, D. K. (1995), in: Handbook on Semiconductors, Vol. 3: Mahajan, S. (Ed.). Amsterdam: North-Holland, p. 2033. Sze, S. M. (Ed.) (1983), V L S I Technology. New York: McGraw-Hill. Wolf, S., Tauber, R. N. (1986), Silicon Processingfor the V L S I Era. Sunset Beach, CA: Lattice Press.

6 Etching Processes in Semiconductor Manufacturing

.

Kevin G Donohoe Formerly with Applied Materials. Santa Clara. CA. U.S.A. Terry Turner Fourth State Technology. Austin. TX. U.S.A.

.

Kenneth A Jackson Arizona Materials Laboratory. University of Arizona. Tucson. AZ. U.S.A.

List of Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Wet Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 Dry Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.3 Etch Control and Metrology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Equipment: Description of Hardware ................................. 6.2.1 Wet Sinks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Dry Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3 Etch Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3.1 Barrel Etchers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3.2 Plasma Etchers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3.3 Reactive Ion Etchers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3.4 Remote Plasma Generation: Microwave and ECR . . . . . . . . . . . . . . . . . . . . . 6.3 Endpoint, Diagnostic and Control Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Endpoint Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1.1 Optical Emission Spectroscopy (OES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1.2 Laser Interferometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1.3 Residual Gas Analysis/Mass Spectroscopy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1.4 R F and Bias Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Diagnostic Tools/Metrology for Process Control . . . . . . . . . . . . . . . . . . . . . . 6.3.2.1 Machine Related Metrology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2.2 Process Related Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 Control Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3.1 Present Control Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3.2 What is Needed? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3.3 Possible Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Process Discussion: General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

293 294 295 294 296 296 297 297 298 299 300 301 301 304 305 305 306 307 309 310 312 312 315 317 318 318 319 320 320

292

6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.5 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.6 6.5.7 6.5.8 6.5.9 6.5.10 6.5.11 6.5.12 6.5.13 6.5.14 6.6 6.7


Gate Definition . . . . . . . . . . . . . , . . . . . , , . . . . . . . . . . . , , . . . . . . . . . . , , . . . . . ................ Silicides . . . . , , . . . . . . . . . . . . . . . . . . , . . . . . . . . . . Contact Etching . . . . . , . . . . . , , . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . Planarization Etch Steps . . . . . . . ............................... Via Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........... .... ..................... Metal Etching Etch Processing r 4Mb DRAM . . , , . . . . . . . . .. ... .* * ..* * .......* Wafer Preparation . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . N-Well . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P-Well Field Implant , , , , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .......................... Is0 Mask . . . . , . . . . . . . . , . . . . . . Connector Mask . . . , , , . , . , . . . . . . . . . . . . . . . . . . . . . . , , . . . . . . . . . . . . . . . . ................ Trench Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . Inter-Polysilicon Oxide Mask . . , . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . , , . . . Gate M a s k . . . , . . . . . . . . . . . . . . . . . . . ... ....................... . . . . . . . . . . . . . . .. . . . . . . . . . .....,.......... LDD Spacer Etch . . Contact Etch . , . . . . , . , . . . . , , . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . Poly 3 Polycide Etch . , ......................................... Contact Mask 2 . . . . . , . . . . . . . . . . . . . . . . . . . . . . . , . . , . . . . . . , . . . . . . . . . . Metal 1 Mask . . . . , , . . . . . . . . . . . . . . . . . . . . . . . . . , . . , . . . . . . . . . . . . . . . . . ............................... Pad Mask;’Polyimide Mask . . . . . . ........................ Summary . . . . . . . . . . . . . . . . . . . . . . . , . . . . . I

I

.

.

.

.

.

.

.

.

I

.

8

References I , . I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I . . . . . . . . . . . . .

321 322 323 326 328 329 331 331 331 334 334 334 334 335 335 336 336 331 331 331 331 338 338


293

List of Symbols and Abbreviations B d D E I n n, V r/; 1.

ARC ASIC BPSG CCD CD CMP CVD DRAM ECR IC I LD IMD LDD LOCOS MERIE MFC MOS NIST NTT OES

ON0 PID

Poly PSG RC RF RGA RIE ROI

magnetic field thickness of film drift vector electric field current refractive index density of intrinsic carriers potential threshold voltage wavelength anti-reflection coating application-specific integrated circuit boron phosphorus silicate glass charge coupled device critical dimension chemical-mechanical polishing chemical vapor deposition dynamic random access memory electron cyclotron resonance integrated circuit interlayer dielectric inter-metal dielectric lightly doped drain local oxidation of silicon magnetically enhanced RIE mass flow controller metal-oxide-semiconductor National Institute of Standards and Technology Nippon Telegraph and Telephone Corporation optical emission spectroscopy oxide-nitride-oxide proportional-integral-derivative. A proportional controller which uses an integral of the sensor signal to stabilize the long-term behavior of the control system, and uses a derivative of the sensor signal to adjust for rapidly changing conditions polysilicon phosphorus silicate glass time constant (characteristic time in a resistor-capacitor electrical circuit) radio frequency residual gas analyzer or analysis reactive ion etching return on investment

294


RSM SEM SILO SIMS SOG SPC SWAMI TEOS VLSI

response surface methodology scanning electron microscope sealed interface local oxide secondary ion mass spectroscopy spin on glass statistical process control side wall mask isolation tetra-ethyl-ortho-silicate very large scale integration

Glossary The point in an etching operation where the desired etching has taken place, and the etching process should be terminated to minimize unwanted etching. The active region between the source and drain in a MOS device. gate: Dielectric isolation, a dielectric layer providing electrical insulation. iso, isolation: First metallic conducting layer. Metal 1: poly, polysilicon: Fine-grained polycrystalline silicon. A conducting layer consisting of a layer of polysilicon and a layer of polycide: metal silicide. A polymer with a high glass transition temperature, used as a dielectric. polyimide: salicide: Self-aligned metal silicide. A hole through a dielectric layer to provide electrical connection via: through the layer. endpoint:

6.1 Introduction

6.1 Introduction Semiconductor device processing consists of patterning dopant distributions, dielectric layers and conductors on the surface of a semiconductor wafer. There are typically ten to twenty of these patterned layers in a semiconducting device. A layer is patterned in a sequence of steps such as: the required layer to be patterned is deposited on the surface; a photoresist layer is then deposited on top of it; the photoresist is exposed through a mask and then developed to make patterned holes in the mask; the underlying layer is then etched through the holes in the photoresist; then the remaining photoresist is stripped off. The scope of this chapter is to describe the dry and wet etching processes used in this pattern transfer technology. The etching technology has become very sophisticated in order to assure that etching occurs only where it is supposed to, and not elsewhere. Extensive use is made of selective etches which preferentially etch one material: ideally, the etch should etch the pattern into the layer and then stop, with no attack on the layer below, in order to compensate for the inevitable variations in etch rate across a large wafer. In addition, the shape of the side walls of the etched region becomes increasingly important as the feature size on ICs decreases. The primary focus of this chapter will be on dry etch processing in the silicon based IC industry with emphasis on techniques and etch tools which have been demonstrated to support volume production. The industry has moved substantially from wet etches to dry etches for reasons discussed below, and that trend is continuing. The use of wet etch steps (including cleans) is also an important issue because these steps must be well understood prior to either

295

replacing them with dry processing or continuing to use them. The structure of the chapter is to first discuss etch equipment and plasma generation technologies, then to discuss diagnostic techniques for process control and troubleshooting, and finally to discuss the specific etch processes used in IC manufacture. A process flowsheet for a 4 Mb DRAM will be used to discuss both the process steps and the interactions which can occur between them. See also Chap. 10, Sec. 10.5.

6.1.1 Wet Etching Wet etching for both cleaning and pattern transfer dominated the IC industry until the mid 1970s, when critical dimensions began to approach film thicknesses (Irving, 1971; Vossen and Kern, 1978). All semiconductor wet etching processes have had the same basic limiting factor: isotropy. Whether etching oxide or metal, the amount of lateral etching nearly always approximates the vertical etch depth. Along with the basic technology limiting quality of isotropy, wet etching also suffers from the downtime created by bath changes and poses a safety hazard even during normal operation. Regardless of the safety and technology related problems, wet processes are still widely used in the cleaning and preparation of wafers in the early stages of a process flow. Wet cleans for the complete removal of “buffer” or sacrificial films used during implantation and hard masks are still widely used. However, because of the problems outlined above, wet etches have been replaced by dry etching for pattern transfer even though the dry processes were originally not anisotropic.

296


6.1.2 Dry Etching The use of dry etch processing grew from stripping resist, thin nitride etching, and the isotropic etching of gate material, contact and via etching, and aluminum, to the highly anisotropic and selective etching of the same films. By the time the 1 Mb DRAM was in production in 1987, dry etching processes dominated all pattern transfer steps. Increases in IC performance requirements drove the development of etch tools that had better C D (critical dimension) control. better selectivity to mask and underlying films, and better particle and foreign material control. Cost (including operating costs. maintenance and downtime) became important once hardware that met product performance specifications was available. Damage issues, especially lattice and gate oxide damage, became process and hardware drivers in the late 1980s as the 1 Mb DRAM was being developed. More attention was focused on yield loss from microcontamination. Finally, the drive for more efficient production capability drove etch equipment to be designed and assembled to run for longer times between failures and between scheduled maintenance procedures. Both equipment suppliers and equipment users began to include measurements of, or at least expected, values of uptime, availability. mean time (or mean wafers) between failures and mean time to repair in their equipment performance specifications. It is normal for current etch tools to operate for more than 200 hours between failures. Many reviews of etch processing can be found in the literature: some are mentioned below. Early descriptions of the mechanisms responsible for RIE etching were presented in detail by Coburn (1982). An overview of chemistry and etch mecha-

nisms by Flamm and Herb (1989) uses classical engineering concepts of similarity variables to describe etch processing. Discussion of earlier technologies, including some considerations of radiation damage and sodium contamination was published in 1979 (Kalter and van de Ven, 1979). More recent discussions of etching (Powell and Downey, 1984; Coburn et al. 1986; Bondur and Turner, 1991) cover most of the current issues in plasma etching. Good sources for the latest results and trends in plasma processing are the yearly proceedings of the Electrochemical Society, the Materials Research Society, the American Vacuum Society. and SPIE meetings. The proceedings of the Dry Processing Symposium held every fall in Tokyo are also a valuable source of information on new processing techniques and are available in English. 6.1.3 Etch Control and Metrology Whether wet or dry technology is used, some form of control must be imposed on the process. To d o this, three basic components are necessary: a) sensing technology; b) control algorithm; c) communications among subsystems. Also, since no manmade system is perfect, some strategy to identify and correct fault(s) which cause the process to deviate from optimum or even catastrophically fail should be available, including the metrology tools to identify the fault(s). With regard to control technology, the objective is simply to maintain a consistent reaction throughout the process until the “endpoint” is reached. The endpoint of a process is attained when the film to be removed has been cleared. Therefore, the argument could be made that even if the process characteristics drift, as long as an endpoint can be detected, the run-to-run

6.2 Equipment: Description of Hardware

results should be similar. For this simple reason, the most important sensing technology on any etch process is an endpoint monitor. However, variations within the process can adversely affect run-to-run repeatability, so that process sensors and diagnostic tools are also important to successful production processing. In the early years of IC manufacturing, not much attention was paid to control techniques. Equipment was set up manually and operation verified by checking the various setpoints As repeatability became more important with increasing production volume and costs of manufacturing, the need for automated control of equipment operation became evident. Today, manufacturing is faced with the need to increase the return on investment (ROI) while meeting the needs of advanced product designs. It is evident that the control algorithms implemented in the late 1970s and early 1980s will not meet tomorrow’s process performance requirements and must be updated. The conflict between manufacturing ROI and improved performance requirements is not trivial and will require novel implementation of sensor and control algorithm technologies.

6.2 Equipment: Description of Hardware This section presents general descriptions of the various types of etching equipment used in manufacturing environments today. The basic physics and chemistry that differentiate various types of plasmas are discussed. Also, some indication of the track record of different types of dry processing equipment in industry is included. One important way to differentiate various styles of the same type of equipment (i.e.,“RIE etcher” or “microwave etcher”) is

297

in the techniques used a) to control the process and b) to terminate a step in the process. Batch size and level of integrated processing are also important differences between reactors of the same type. Included in control strategies are diagnostics which are commonplace (MFCs, leak rate tests) and strategies which are not yet in common use (for example, Langmuir probes for density evaluations). 6.2.1 Wet Sinks

Most wet process steps perform cleans: these steps serve to either prepare a surface for a subsequent step or remove a film from the wafer surface. Wet cleans are technically complex because different cleans leave different surface conditions on the wafer. However, pattern transfer is not usually accomplished with wet steps in today’s manufacturing technology because they produce isotropic profiles. The most important control required in wet stations is to control particle contamination by filtering and by preventing suspensions from forming particles downstream of the bath filters. The process flow discussed in Sec. 6.5 uses standard sinks for the various cleaning procedures including the RCA, phosphoric/HF, buffered HF, sulfuric acid/hydrogen peroxide steps. Most wet etching is still performed in an immersion mode. The precision of the removal is controlled by the temperature of the etchant, the time of immersion and the composition of the acid etchant. The composition of the etchant is adjusted to produce a controllable etching time, generally between one and seven minutes. Below one minute, the time for the operator to remove the wafers from the bath becomes an appreciable fraction of the etching time, thus introducing variations in the etch results. Above 7 min, the photoresist tends to

298


lift, resulting in excessive undercutting. A typical target etching time is 5 min. Spray applications, especially those applied when the wafer is rotating, result in a more uniform process. However, since spray etch processing has not been completely spray automated, most wet etching is still immersion based. Kern (1990) has reviewed wafer cleaning technology and discussed both spray and immersion cleaning techniques. Silicon wet cleans were studied by van den Meerakker and van der Straten (1990). Some new dry cleaning techniques which replace sinks include anhydrous H F wafer cleaning: see Deal et al. (1990) and Miki et al. (1990). 6.2.2 Dry Processing

A useful model of both dry process equipment and the processing itself is the idea that dry process results come from a balance between physical and chemical processes at the wafer surface. Figure 6-1 illustrates how a process dominated by sputter etching at low pressure and high ion energy can be compared to a process dominated by chemical etching at high pressure and low ion energy. Typically, LOW

PRE SSURF

1 1

HIGti

PHYSICAL PLASMA PROCESS

-

BALANCtD

-*

HIGH

NF I N (;Y

LOW

sputter etching processes provide anisotropic profiles but do not provide selective etching between the different films on the wafer such as the photoresist, the etch film, and the layer under the etch film. Faceting of the mask is also a characteristic of sputter etch processes. At the other extreme is purely chemical etching, often referred to as plasma etching, which usually provides excellent selectivity between films that have different chemical composition but tend to etch with isotropic profiles. Successful etch processing occurs when the correct balance between these two extremes is struck. Figure 6-2 illustrates the same trade-off in terms of the effect on etched features. The term “reactive ion etching” or “RIE” is used to describe etch processes which combine both physical and chemical processes to give the desired balance bet ween anisotropy, selectivity, and damage. This concept, the idea of considering process results as a balance of two types of processes - physical and chemical will be used discussed further below. During the discussion of the tool designs, the reader should remember that each tool design has a certain range of ion energies, ion densities and neutral densities in which it

SPUTTER ETCHING

REACT1 VE ION

ETCHING

PLASMA ALl:!prPROCESS

-

PLASMA ETCHING

Figure 6-1. Physical and chemical processes in a plasma.

6.2 Equipment: Description of Hardware SPUTTER ETCHING

(PHYSICAL)

REACT1 VE ION ETCHING

LOW

HIGH

299

HIGH

t t

I

I

SELECT1 VI TY

ANISOTROPY

I

HIGH

DAMAGE POTENT I AL

LOW

Figure 6-2. Results on the wafer for physical and chemical etching.

Table 6-1. Trends of DRAM process technology Characteristic

1 Mb

4 Mb

16 M b

64 M b

256 M b

1.3-1 0.3-0.4 3.0-2.5 2 1.o 1.2 200

1.0-0.7 0.2-0.3 2.0- 1.5 3 0.7 1.o 150-100

0.5 0.1 -0.2 1.5 4 0.5 0.7 125

0.35 0.12 1.2 5-6 0.35 0.5

polycide

polycide

polycide

Storage capacitor

buried/ stacked

buried/ stacked O N 0

buried/ stacked O N 0

100 pol ycide/ refractory buried/ high E

0.25 0.08 0.9 6 0.25 0.35 I80

Wafer size (mm) Production

125-1 50 1987

150 1989

150-200 1992

200 1995

Design rule (pm) Overlay (pm) A1 pitch (pm) Conductor levels Contact size (pm) Via size (pm) Gate oxide thickness Gate conductor

(A)

can operate while still providing reasonable etch rates. For example, RIE tools are not usually operated below 25 mtorr because the large RF voltages required to sustain low pressure capacitively coupled plasmas result in excessively high ion energies.

6.2.3 Etch Hardware Historically, dry etch equipment developed from sputter etch tools (dominated by physical etch mechanisms) and from isotropic barrel etchers (dominated by chemical etch mechanisms) into what have been termed RIE etchers and plasma etch-

polycide,’ refractory buried! high E 200 - 300 1998

ers. In these etchers, the etch chemistries involve a balancing act between ion and chemical dominated mechanisms. Table 6-1 summarizes the pattern transfer requirements of existing and evolving technologies (Cook, 1991). The need for better CD control, selectivity to mask and underlying films and improved damage control has led to newer types that combine multiple sources of excitation energy. In these evolving tools, the functions of plasma generation of sufficient numbers of ions and neutrals are decoupled from the control of the ion energy at the wafer surface. Typically, the source is physically removed from the region near the wafer and is called

300


a “remote source”. These include low pressure etchers such as low pressure microwave, helicon, and ECR sourced tools as well as high pressure microwave sources which are typically used for isotropic, low damage processing such as resist stripping. The tools described below are summarized in Table 6-2. Details of their operation have been specifically discussed by Fonash (1985):a good review of equipment choices and a discussion of their physical characteristics is provided by Broydo (1983).The typical pressure ranges that each type of tool operates in as well as the range of ion energies at the wafer surface are listed in Table 6-3. Typical values for n i , the ion density, are also listed in this table. Note the relatively high ion energies which always accompany RIE and Magnetron tools compared to those obtained with barrel and ECR tools. These estimates of

energy describe values typical for real operating conditions that give reasonable throughput. If low ion energies are required for future processes, the parallel plate reactors will not be able to meet this requirement. The flowing sections detail the characteristics of equipment presently used in the manufacturing environment.

6.2.3.1 Barrel Etchers

A typical barrel etcher is shown in Fig. 6-3a. The chamber consists of a vacuum vessel, large enough to hold 1 or 2 boats of 25 wafers. The RF electrodes are usually located outside the quartz vessel and consist of coils or simple electrode pairs. Inductively coupled geometries in which the outer electrode consists of a number of turns of copper tubing wound around the vessel often actually operate with capacitive coupling. Ion-surface reactions driven by the difference between Table 6-2. Most common plasma tools used in IC fabthe wafer surface and the plasma potential rication. are reduced by use of an internal metal Common Source type Used in shield (termed an “etch tunnel”) which name makes the wafer region electric field-free (and, incidentally, makes R F matching easL or C coupled strip is0 etch Barrel ier and more stable). Tunnels usually lower 13.56 M H z dielectric etch Plasma etch rates and increase across-the-chamber parallel plate nitride stripping. These processes are rela13.56 MHz metal, poly RIE tively insensitive to long overetches so 2456 M H z (typ) resist strip (hi P) Microwave poor across-the-chamber nonuniformities remote resonant poly, metal ECR are often acceptable. Even so, slow mass transfer between the edge and center of the wafers often requires that the space beTable 6-3. Comparison of different types of etch tools. tween wafers be increased to as much as Type P Range Miwmax (eV) Typical n , 10 mm (reducing the load size) in order to of tool (torr) (at surface) (~rn-~) maintain across-the-wafer uniformity. Thin nitride etch (isolation mask, for example) 0 1 10 Barrel 3 20 1012 1013 and even polysilicon gate etch processes Plasma 1 5 100 loo0 5 x 1012 RIE i00,iooo 1 0 ~ - 1 0 ~ ~ have been run in production with these 005 0 5 5011000 109 1011 Mag 001 o 1 tools. One 4 M b fab has used a barrel ECR 5 500 1011 1013 0001 0 2 etcher to clean poly gate lines after partial (at source) RIE etch: the reason for this is to avoid


gate oxide damage on their devices. The use of barrel etchers is in general not popular because these tools usually have high particle counts and because their capabilities can be duplicated by downstream single wafer tools like microwave etchers.

6.2.3.2 Plasma Etchers So called “plasma etchers” (Fig. 6-3 b) are a high pressure configuration of parallel plate RIE etchers with mechanical differences that permit their operation at high pressures (up to 10 torr) and high power densities (up to 3 W/cm2). The main mechanical difference between them and RIE tools are in the physical design of the electrodes and their use of a relatively small (about 10 mm) electrode gap. These tools have been used extensively for high speed single wafer dielectric etching and operate with a mix of chemical and physical processing. The utility of the design arises from the increase in etch rate that occurs as the electrode space is decreased below 10 mm in the few torr pressure range. The typical design trade-off is the balance between process stability and uniformity for larger gaps and high rate for smaller gaps. For certain layers, these tools are successful in 4 Mb DRAM production technology. They are characterized electrically by a nearly zero D C bias voltage, a relatively high plasma potential, and high power densities. They frequently use coolec‘ \!infer chucks and lower frequency (100-400 kHz) excitation for dielectric etch. Some have the capability to split the applied power between the two electrodes: this helps control geometric asymmetries inherent in any reactor and permits truly “anode” or “cathode” coupled operation. The control of damage that is achieved with these machines stems from their high pressure operation.

30 1

6.2.3.3 Reactive Ion Etchers Reactive ion etching (RIE) tools are characterized by a large ( > 2 : 1) area ratio between the anode and cathode (Coburn and Kay, 1972), operation in the 20400 mtorr range and have been designed in both single wafer and batch configurations. The schematics in Fig. 6-3 c show the important components of an RIE etch tool: a blocking capacitor is in series with the power supply (see Kohler et al., 1985, for capacitor discussion). The wafers are placed on the cathode (the smaller, powered electrode for this design). These are the tools which support virtually all high resolution pattern transfer etch processes in the industry. The low pressure operation provides good mass transfer which reduces microand marco-loading effects. The diode performance of the plasma provides high ion energy at the wafer surface for ion assisted etching and low ion energy at the anode for reduced sputtering of the chamber walls. The success of these tools stems from their ability to operate in physically dominated etch modes (oxide, nitride, and trench etching, for example), chemically dominated modes (aluminum etching) or mixed modes (poly/silicide, or A1-4% Cu etch). They also have the advantage of widespread acceptance and understanding of their mechanical and electrical components: that is, people know how to adjust setpoints to obtain different wafer results and how to keep the equipment operational in production. Most RIE tools currently available are evolutionary in that they represent continuously improved designs of a mature technology. One limitation of RIE tools has to do with the lowest pressure at which they can be usefully operated. Large R F voltages are required to maintain them at low ( 4 - 1 0 0 mtorr) pressure and typical

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,

(a)

r - - - - - - - -

I

I

I

' 3 56 MHZ

If* ANODE CATHODE

Figure 6-3. Schematic view of typical etchers: (a) barrel; (b) "plasma etcher"; (c) RIE ctcher: (d) microwave etcher; (e) ECR etcher; (f) "NTT" ECR design


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power densities (1 W/cm2). These high voltages result in large voltage drops across the cathode sheath and in ion damage on the wafers: lattice damage and etchant implantation (Current et al., 1989) can be a dominant process. Thus, the parallel plate RIE etcher has some limitation with respect to the lowest pressure at which it is useful, especially for sensitive etch steps like gate and contact etch. Note from Table 6-1 that the 4 M b process requirements are met with this technology. The operating voltages of RIE tools can be reduced by applying a magnetic field to the gas gap: a number of different configurations of such magnetically enhanced RIE (MERIE) or magnetron tools are used in industry.

6.2.3.4 Remote Plasma Generation: Microwave and ECR Microwave strippers (Fig. 6-3 d) are one type of remote source or downstream etch configurations. They consist of a microwave plasma source located upstream of the wafer, a method of distributing the source effluent uniformly to the wafer surface, and often include radiant heating and passive cooling for wafer temperature control. The temperature control is critical for resist strip applications which run at a few torr pressure and which have a temperature sensitive strip rate. External wafer biasing is common in lower pressure microwave systems (see Fig. 6-3e) which perform anisotropic etching: systems are currently available to preform resist strip, metal etch and gate etch. Most microwave etchers use closed loop temperature control of the RF biased wafer chuck to prevent overheating of the wafer. Finally, Fig. 6-3 f shows the “NTT” ECR (electron cyclotron resonance) design: here the effluent from the tubular resonant re-

gion reaches the wafer directly. The distance between the source and the wafer controls the balance between uniformity and rate. The rationale for this type of tool is that the process can run with very low ion energy (and low ion current to the wafer surface, if necessary): ion densities as low as 107/cm3have been measured in argon at 2 torr a few cm downstream of the microwave source (Cook, 1991). This is expected to reduce damage on the wafer and also reduce surface heating. In addition, the microwave plasma can be operated at pressures lower than an RIE parallel plate system: this is expected to provide better particle control by reducing deposition. Better loading performance is also expected since the pressure is lower. The ECR source is similar to a microwave source in that it uses a 2.45 GHz driving frequency. It also uses a localized magnetic field of 875 Gauss to generate a resonance between the electron gyro frequency and the frequency of the applied field. ECR plasma sources operate effciently at low pressure ( < 1 mtorr) and can generate high plasma densities (up to 1Ol2/ cm3). Operation at true resonance also generates a high energy tail on the electron energy distribution: these electrons can generate high energy radiation (soft X-rays) which is a new possible source of device damage (Buchanan and Fortuno-Wiltshire, 1991). ECR tools are of interest to many device manufacturers but have not yet matured to the point where they are in common production use. Other sources such a helical resonators show promise but are not currently available on production hardware. The attraction of the resonator design is that it is relatively simple mechanically, that is uses RF, not microwave frequencies, and that the plasma is inductively coupled so low plasma potentials are possible, even at low pressure.

6.3 Endpoint, Diagnostic and Control Techniques

6.3 Endpoint, Diagnostic and Control Techniques Metrology (the science of measurements) and communications are as critical to the success of a process module as any hardware component. The ability to known when a process is complete, and to avoid unnecessary exposure of underlying films to subsequent processes, is of utmost importance. Not only does endpoint detection reduce the propensity for damage to underlying films, but it can also enhance run-to-run uniformity. Hence, it is desirable to have an endpoint detector for any etch process. It is common for engineers today to use designed experiments, or response surface methodology (RSM) techniques to establish operating points and characteristics of their processes. A major drawback of these procedures is that, although they allow for multivariate input, they only provide optimization for a single output for control of the system, rather than providing for the optimization of several control outputs. Exceptions to this rule are neural networks, which are truly multivariate input and output, but techniques such as these are not commonly in use today. The absence of multivariate input and output techniques creates two problems. First, since all equipment fails at some point in time, the need for diagnostic tools in troubleshooting a failed process is a “must”. Also, it is important to realize that the purpose for using designed experiments is to identify a window of operation which is stable and meets specifications. As circuit designs become more complex these specifications get tighter and the need to maintain process optimization in a smaller window of operation becomes increasingly difficult. Add to this the problem of responding to the variability of incoming material (sometimes drastic and often in-

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tentional as in the case of ASIC design), and a second problem arises: the dynamic control of the process tool. In this section each of these three topics will be discussed with regard to current and future process requirements. It should be noted that due to the time frames of interest, emphasis will be given to technologies applicable to dry processes only. 6.3.1 Endpoint Monitors Due in part to the normal surface topography of IC designs, film thickness will vary over a wafer. This necessitates a certain amount of “overetching”, i.e., etching beyond the point where the top film has begun to clear. However, as mentioned above, it is important to minimize the exposure of sensitive underlying layers such as gate oxide. Often this means converting from a very fast anisotropic etch with poor selectivity to the underlying film, to a much slower less anisotropic process with higher selectivity. This conversion from high anisotropy can result in loss of dimensional control if not minimized. Therefore, endpoint detection is an important part of process control. Initially the concept of determining when a very thick film (a few thousand angstroms) clears seems difficult. However, inspection of the actual etching process reveals numerous opportunities for signal generation and monitoring. Flamm and Herb (1989) give an excellent account of film volatilization and the chemical makeup of the plasma throughout a dry etch. It is easy to conceive that if one could monitor a signal proportional to the chemical composition of the plasma, such as density of the etchant or a by-product of volatilization, that the level of this signal would change as the film is removed. This is the basic method of operation of most end-

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point detectors. Another type of monitor makes use of the optical properties of the film being etched. As the film is removed the optical properties of the wafer surface change and can be monitored to detect endpoint. The following subsections are a review of the most widely used endpoint monitors. 6.3.1.1 Optical Emission Spectroscopy (OES)

All plasmas emit light at some wavelength. The most common example of this is a man-made plasma contained in a fluorescent lamp. Plasmas used in dry processing of simiconductors also emit broadband radiation. Emissions can emanate from etchants, etch products or their fragments. There are numerous manufacturers of OES equipment. There are three basic types: a) multichannel analyzers with up to 1024 light sensitive pixels; b) scanning monochromator with typically only one light sensitive element; c) fixed wavelength. The most common is the scanning monochromator. Figure 6-4 contains an actual endpoint trace taken with a scanning monochromator type system. Table 6-4 lists characteristic emitter wavelengths for a variety of film/etch chemistry combinations. Endpoint detection by OES has been used quite successfully for many years. Systems can be cheaply constructed or purchased at a reasonable price. The most expensive and flexible is the multichannel analyzer with the capability to capture highly temporally resolved broadband snapshots of the process. The least expensive systems are the fixed wavelength variety. Functionally, these systems work as well as any of the three, however, the user must know in advance of purchase, exactly which wavelength will be monitored. For

Overetcp h

m

c ._

C

x .L

m

0,

-

c

Time

Figure 6-4. Typical optical emission endpoint signal taken from MERIE poly etch.

Table 6-4. Characteristic wavelengths for optical emission endpoint monitoring via selected species in various etch chemistries. Film

Etchant

Wavelength

Emitter

('4 AI cu Cr Resist

Si

Si,N,

SiO, (P-Doped)

w

2614 3962 3248 3579 2977 3089 6563 6156 7031 7770 2882 3370 7037 6740 1840 2535 7037

AlCl AI cu Cr

co

OH H 0 F SiF Si N2

F N

co P F

fabrication facilities with changing loading, multiple processes, resists or product designs this may not be practical. Therefore the most common unit found in use today is the scanning monochromator system, which allows for changing the monitored wavelength. As good as these sound, not everything is perfect with OES endpoint detection.


The first problem encountered in the normal fabrication environment is the availability of a port on the chamber with a good view of the discharge. Although some older machines may not have such access, most newer equipment does. The next obstacle which a process engineer must overcome is finding a relevant wavelength to monitor. Plasmas emit broadband, and there is much light available, but usually the intensities of only a few wavelengths correlate with what is happening at the wafer. Also most detectors are sensitive only in the very near IR through the very near UV portions of the spectrum (200800 nm) so much information relating the heavy molecules typical of a process plasma is lost. Even if the installation of an OES system is successful and a spectral feature which can serve as an endpoint detector can be identified, clouding of the window is one last problem which can never be solved. Most OES systems use a quartz window for optimum transmission, but the quartz is etched, or deposits form on it, just as they do on a wafer or on the chamber walls. So the window must be periodically cleaned. Cleaning is a major problem for very low pressure tools, such as ECR, or C1, based process systems which should be exposed to atmosphere as little as possible.

6.3.1.2 Laser Interferometry Another production proven endpoint technique is based on the reflection of monochromatic light from the various film surfaces on the front side of a wafer during process (Donnelly, 1989). Monochromatic light, usually from a laser, has a reflected intensity which depends on its wavelength, the index of refraction and thicknesses of the films in the stack. The reflected intensity depends on constructive and destructive interference of light reflected from the various

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interfaces. This phenomena is used to monitor the thickness of materials such as polysilicon, silicon oxide and silicon nitride. When a laser, such as He-Ne (632.8 nm) is directed at the wafer surface, interference maxima and minima occur when twice the thickness of the film, d, is a multiple of the wavelength, I,, divided by the refractive index, n

d = rz (142)

(6-1) The light intensity reflected from these silicon based films varies sinusoidally with film thickness. The etch rate can be monitored by determining the time interval between a maxima and minima on the signal trace. This technique permits real time monitoring of etch rate. Hence, changes caused by variations in the composition of the film with depth can be detected. Laser interferometry has been used in a wide variety of etch processes due to its adaptability. Even in metal etching where the film is reflective, interferometry can be applied. As the reflective metal film clears the optical characteristics of the underlying film become apparent in the amount of laser light reflected. Figure 6-5 shows representative laser interferograms for (a) metal etch clearing followed by polysilicon etch, and (b) silica being stripped from a silicon substrate. A major problem with laser interferometry is its lack of ability to deal with etch non-uniformity. Interferometric techniques by nature must operate with a very small spot size (IO-’ cm in diameter) in order to achieve a sharp interferogram. Therefore since endpoint determination is made from sensing a small area, variations in film thickness or across the wafer etch rate will produce an unrepresentative sample. This is especially serious with batch processes or with single wafer etches which sacrifice selectivity for rate and anisotropy. A sec-

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a

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io

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ELAPSED TIME (MINUTES)

.-PLASMA

END P O I N T 1

ON

I

t

4 40

30

20 t (min)

40

Figure 6-5. Typical laser interferometry traces for (a) metal over oxide. and (b) polysilicon over oxide.


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Figure 6-6. RGA output from CF, plasma. 4

14

24

34

44

54

64

74

a4

94

Mass

oridary issue, which may make the measurement impossible, is the requirement for normal incidence of the laser on the wafer surface.

6.3.1.3 Residual Gas Analysis/ Mass Spectroscopy As mentioned above, the plasma chemistry changes during the etch process from start to finish. This change is usually based on the consumption of either the etchant or the film being volatilized, their density should be inversely proportional to each other. Therefore, temporally resolved information relating to the density of various plasma constituents, should make endpoint determination trivial. This is the basic idea behind using mass spectroscopy or residual gas analysis (RGA) for endpoint detection. However, RGA and OES share the similar problem of identifying the critical peaks to monitor in the presence of an intense background. As a matter of fact, RGA is probably worse, since it looks at a much wider portion of its spectrum than OES. Figure 6-6 shows a typical RGA output. A more critical problem arises when the details of RGA sampling are examined. The most common mass spectroscopy systems in use today are based on the quadrupole mass analyzer which requires a low

operating pressure ( < torr). This low pressure is reached by placing a sampling orifice between the differentially pumped quadrupole region and the process gases. Depending on the RGA manufacturer, the sampling orifice may be a small bypass valve or a pin hole aperture. After being accepted into the differentially pumped region the sampled particles pass through an ionizer and then must travel some distance to traverse the quadrupole. The distance covered in exiting the plasma, passing through the sampling port and ionizer and then the quadrupole adds up to many, many mean free paths. The probability of any particles, especially a large charged particle, making such a trek without incurring a collision is small. Therefore it is safe to assume that for the most part what we see at the typical RGA display is a limited representation of the actual chemistry present near the wafer surface. A second problem arises for the use of RGA in newer magnetically enhanced machines. The principle of operation for quadrupoles is based on the interaction of a controlled electric and magnetic field with a charged particle. In the case of MERIE or ECR type tools, the externally imposed confinement fields may severely interfere with the quadrupole analysis field, even to the point of rendering the RGA useless.

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This is not to say that RGA is not a useful metrology tool. The problem of external magnetic field interference can be solved with special shielding. The problem of not truly sampling plasma at the wafer can be solved with special probes, although these may shadow the wafer. The dificulties do, however, tend to make RGA more of a development tool than a production sensor (Vasile and Dylla, 1989; Manos and Dylla, 1989 b). 6.3.1.4 RF and Bias Voltage

It is intuitive that as the plasma chemistry changes during the etch process so do the plasma impedance and the sheath characteristics. As the impedance and sheath change so do the RF voltage, current, phase and, providing the power is not controlled by the bias, so does the self-bias voltage. Monitoring of the RF network parameters is the most direct means of non-invasive plasma metrology because the signal-to-noise ratio is very favorable and, since the measurement is usually made at the wafer electrode, the discharge is sampled in a relevant area. There are no problems with shadowing the wafer or clouded windows involved in making RF measurements and implementation of voltage and current sensors can be almost trivial. As a potential endpoint monitor, RF analysis benefits from two different phenomena which complement one another. First, the constituents of the discharge change throughout the etch process which result in a changing impedance. Being able to measure the bias voltage, the current to the plasma, as well as the impedance of the plasma makes RF monitoring near the wafer surface a powerful endpoint detector. Second, since the wafer serves as an exposed electrode, and this entire surface changes (i.e., the electrical

properties of the powered electrode change), the entire wafer surface contributes to the endpoint monitor. This removes the problem of limited spot size associated with laser interferometry. Also with RF metrology, even though the spectrum may be broad there are only discrete frequencies contained within it (the fundamental and its harmonics). This makes identifying the proper endpoint signal much easier than with either OES or RGA. Figure 6-7 contains traces of the RF voltage, current, phase and the self-bias voltage. Of the relevant RF parameters, only self-bias is currently measured on a routine basis. Two problems exist with making self-bias voltage measurements. First, and most important, is that this is a DC voltage measurement which requires an ohmic path to the plasma exposed powered electrode surface. Many modern process tools use anodized electrodes which will stop the DC current flow to any resistive voltage divider set up to measure the self-bias voltage. This makes it impossible to obtain an accurate or even representative self-bias voltage measurement. The second problem is that several types of process tools use servo control of the power in order to keep the bias voltage constant. Therefore, as a film clears, the bias voltage does not change, since the power changes to keep the bias constant. It is anticipated that R F monitoring will find increasing use, since OES sensitivity is already at the limit of detection in some processes such as contact or via etching. OES is often not sufficiently sensitive for dependable endpoint determination, and it has been demonstrated that R F can detect endpoint in cases where OES cannot (Turner, 1991a). Systems for simultaneously monitoring the RF voltage, current, phase and harmonic content are becoming available and will probably

6.3 Endpoint, Diagnostic and Control Techniques 11s

31 1

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84.6 84.46 84.4 84.36 84.3 84.26 84.2 84.16 84.1 84.06

I

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4.36 4.3 4.26 4.2 4.16 4.1 4.06 0

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10

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-320 -326

-F

-330

E

-340 -346

I

8 I I

=

2

-336

-360 -366 -360

Figure 6-7. RF parameter endpoint signals: voltage, phase, current, self-bias.

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come into use as standard endpoint monitors because of their capability and because the monitoring system can be incorporated into the equipment needed for power control.

plasma or the incoming wafers. Proper metrology practices can remove all but the most catastrophic of these by providing timely information relating to the overall state of the process module. We will begin this discussion, as an etch begins, with the machine settings.

6.3.2 Diagnostic Tools/ Metrology for Process Control

The previous section dealt with stopping the process at the appropriate time to improve run-to-run uniformity and insure minimal damage to underlying films. This section deals with the metrology devices which can be used to correct a process either prior to going out of control, or after a control failure has occurred. Diagnostic tools and metrology for process control are based on both machine related and process related measurements. This is to say that etching can be viewed as having three components: a) the machine which is used to generate the plasma; b) the plasma used to generate the chemicals and kinetics; c) the wafer and etch results. This modular relationship can be best represented mathematically by the following three relations: etch parameters

=F

(time, plasma (6-2) parameters)

plasma parameters = F (time, machine (6-3) parameters) etch parameters = F (time, machine parameters) (6-4) The time has been included explicitly to emphasize that this entire process is dynamic and time dependent. The primary concept intended to be conveyed by these equations is that machine settings are used to generate a plasma with certain properties and these properties in turn determine how the wafer etches. Failures, drifts, or out of control situations arise from the variability of either the machine, the

6.3.2.1 Machine Related Metrology

All plasma process tools have some amount of machine related metrology. Even the very first machines had RF power meters and pressure gauges. Today’s equipment is much more complex with mass flow, temperature, one or more R F generators, pressure, electrodes gap, magnetic field, backside cooling pressure, all requiring sensory equipment to operate. But the real problem is not how many measurements to make, but how to make them correctly, i.e., where, when and at what frequency. It is also important to remember that production versions of plasma etchers have been in use for the last decade and made many valuable contributions to the fabrication capability of advanced circuit designs. The goal of this section is to point out methods and techniques for improving and extending the capabilities of plasma etching into the next decade. R F Poirser Metrologj,

Present R F measurement practice provides a good example of misplaced metrology. Plasmas are by nature nonlinear phenomena with highly variable impedances. This necessitates the use of an impedance matching network to effectively couple the RF energy from the 50R output on the generator to the powered electrode in the process chamber. These matching networks are made of real, not idealized resistive, inductive and capacitive components,


which create losses due to 12R heating and other radiative effects. Also, matching the variable impedance network to the plamas impedance most often results in tuning to a minimum reflected power, so that some of the incident R F energy is reflected back to the generator. Yet even today, with this understanding, RF power measurements are still made at the output of the generator rather than at the powered electrode. Figure 6-8 illustrates present, correct implementation of RF metrology. A second serious error is also being made routinely in the measurement of delivered RF energy. R F power process setpoints are typically specified in terms of watts. However, it is important to remember that power is the product of the instantaneous voltage and current. Assuming that the voltage and current are both sinusoidal, the average power is given by average power = voltage x current x x cos(phase) (6-5) Since plasmas are by nature nonlinear, the sine-wave assumption of Eq. (6-5) does not rigorously hold, but does serve as a good approximation. Since the etching behavior of a plasma depends on the voltage and current, as well as on the power, it is easy to see that simply specifying the forward power does not properly define the operating conditions. Better control can be obtained by installing proper voltage, current, and phase sensors as part of the RF generator control strategy.

Vucuum Metrology All plasma processing is done at a reduced pressure. Therefore requirements for creating and sustaining a vacuum, for gas handling and delivery, for pressure measurement and control, are all fundamental to dry etching. Lower pressures are used

313

Figure 6-8. Present, improved placement of RF metrology.

more in some types of process tools than others. ECR, for example, require a low operating pressure. The lower the operating pressure, the lower the base pressure which must be used to insure a clean starting chamber. Achieving a low base pressure is usually a function of the pumping capability and the size, type and number of leaks in the vacuum chamber. Pressure metrology has been available for the last century and many improvements have been made resulting in the present capabilities. However, it is important to realize that the chemicals used in most etching processes either attack or alter the measurement capabilities of modern pressure transducers. Similarly, the mass flow controllers (MFCs) used to deliver regulated amounts of process gas to the chamber are adversely affected by use. These MFCs are made from high quality materials but are still subject to the corrosive nature of process chemicals such as Cl,. There is no immediate cure for the degradation of pressure flow transducers. However, simple techniques and available calibration systems can make significant improvements in the reproducibility of transducer performance. Again the problem of making measurements in the wrong

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place jeopardizes the overall metrology process. An MFC, for example, can be set to control the gas flow based on a measurement of the flow and a conversion coefficient for the type of gas. This metrology process gives no information relating to the state of operation of the MFC. Gas is allowed to flow through the MFC by opening and closing an electrochemical valve. By simply measuring the drive current to this valve the time remaining before it fails can be monitored and appropriate actions taken to plan for the replacement of the unit prior to failure. Due to the corrosive nature of many process chemicals it is not practical to remove an MFC for calibration. Therefore, a volumetric technique is presently used to check MFC calibration. This “flow cal” technique is based on the assumption that the pressure transducer has not changed, however, as mentioned above, this is usually not the case. Presently there is a commercially available solution for this problem which makes use of a wellmaintained NIST traceable capacitance manometer (Chapman). This transfer standard calibration system is mounted onto the etcher under test and is used to develop a transfer function correlating the maintained manometer and the etcher’s transducer. Simple but effective techniques such as this will improve the reproducibility of the overall vacuum and gas handling system.

1”

Magnetics Metrology

Many modern “high density” etch systems make use of magnetic confinement techniques to create or sustain certain plasma characteristics. Response surface models generated on some machines indicate that the magnetic field is a prime independent variable. That is to say, it has a very strong influence on the resulting etch parameters. This is easy to understand with regard to uniformity. Figure 6-9 illustrates the establishment of a drift vector created by the interaction of an electric and magnetic field ( D = E x B). The drift phenomena affects all charged particles and can drive the uniformity of etch rate by causing the formation of etchant to be located off the wafer surface. The results of the etchant formation dislocation is that the etchant must diffuse an entire wafer radius to volatilize the exposed film in the center. For a more detailed descriptioin of the E x B drift effect see below. Often the magnetic fields are generated by electromagnetic coils rather than with permanent magnetics. Equipment such as this usually bases the magnetic field strength on a model which uses a measurement of the current flow through the coil as input. However, permeability of chamber components and field divergence are often difficult, if not impossible, to accommodate

Slit Valve

Figure 6-9. E x B drift field created in MERIE tool.


in a model. Therefore, use of a simple Hall effect probe or magneto-strictive fiber optic sensor would provide valuable information relating to one of the most important machine parameters. Presently, neither of these technologies is in routine use. However, providing that access to the chamber is available, either measurement is simple to make and the information generated readily made available.

Thermal Metrology

All etchers make use of thermal energy in some way. The range of temperatures used in etching varies widely from cryogenically cooled to heated well above ambient temperature. In each case the specific temperature aids or inhibits certain etch characteristics. Information relating to the temperature of the wafer can be important for use in overall process control. For example, the degree of anisotropy in the etching of certain films in a simple C1, plasma can be varied if the wafer temperature is known. There are numerous ways to measure wafer temperature. Phosphorus tipped probes have been developed to contact the wafer backside and make spot temperature measurements. Single point pyrometry is widely used in deposition processes and could be applied to etch as well. Spot or single location measurements work well and are a proven technique, however, suffer from the same lack of uniformity information that laser interferometry does for endpoint. Recently, there has been work on the use of two-dimensional CCD detectors for real time temperature analysis (Turner, 1991b). Based on the emission of IR radiation from the wafer surface, these CCD devices present a real time image of the wafer surface. As the wafer is etched the emissivity of the

31 5

top film changes. This makes absolute temperature measurement all but impossible. However, the effect creates two unique capabilities: first, the establishment of a whole wafer endpoint monitor; second, a monitor of thermal gradients caused by non-uniform ion bombardment or cooling (either can result in etch rate gradients).

6.3.2.2 Process Related Measurements As mentioned above the second type of etch module metrology deals with measurements of the chemical or kinetic properties of the discharge. Present process tools do little to exploit this type of metrology even though it is the plasma which actually defines the process results. For example, although it has been known for some time that electrons drive the creation of etchant, nothing has been done to incorporate a device for the routine monitoring of electron density and velocities. This fact alone illustrates the ability of equipment suppliers to empirically develop etch modules which have met industry needs. However, the development cycle for new equipment and processes as well as a significant reduction in yield loss could be achieved with the application of a few simple plasma metrology tools. For years the argument against the need for plasma metrology has been based on the ability to generate a repeatable discharge if the machine setpoints were correct. And, for years the required range in repeatability of the discharge was sufficiently large to support the argument. However, the present requirements being placed on dry etching require tighter overall control of the plasma. For example, due to the rising cost of processed silicon it is no longer practical to discard edge die simply because the process cannot be made uniformly across the entire wafer surface. This sort of uniformity informa-

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tion is often impossible to obtain without some type of dedicated plasma metrology device. Hence, the need for better understanding and control is creating a need for plasma metrology. The following sections detail the capabilities of several fundamental plasma metrology tools. Application of some, such as the RF metrology, in a production process control environment is very simple. Others may require special support which results in their use only as a troubleshooting or SPC type measurement. Residual Gas Anulj-six

The use of RGAs as endpoint monitors and for determining vacuum integrity has already been discussed. However, an RGA provides a unique capability which may be successfully exploited for plasma metrology. One of the simplest measurements to make with an RGA is a partial pressure analysis to determine the concentration of a certain plasma generated component. Partial pressure analysis of a neutral compound such as C1 or F can be done on a periodic basis to ensure optimized generation of etchant. In this application the desired signal is known (the mass of the etchant atom), and the signal to noise ratio should be sufficient for monitoring this primary plasma constituent. Implementation of an RGA can be done in various locations throughout the vacuum system. However, it is recommended that the quadrupole always be as close as possible to the actual discharge. Since only neutrals actually etch, information relating to the etchant concentration can be valuable in optimizing, controlling and troubleshooting dry etch processes.

Optical Emission Spectroscopy

Aside from its capabilities as an endpoint monitor, OES can provide insight into the chemical composition of the discharge. Even though the information gathered from an OES is basically a line integral, it can still be very useful in determining the presence and relative concentrations of compounds with too short a mean free path to make it into the RGA. The most common examples of short-lived constituents are film formers and ions, both essential to anisotropic etching. Although not all ions emit in the OES operating bandwidth, typically a sufficient number do to generate a process “fingerprint” which can serve as a “go-no-go” plasma sensor (Turner, 1991 c). Langmuir Probes

Langmuir probes are probably the bestknown and oldest plasma metrology tools, second only to the human eye. In implementation, they are very simple. One reviewer described a Langmuir probe as nothing more than a wire inserted into a plasma (Manos and Dylla, 1989a). There have been numerous reviews and articles published and these will not be reviewed here (Smits, 1960-62; Langmuir, 1929; Langmuir and Blodgett, 1923,1924; Langmuir and Mott-Smith, 1923, 1924, 1926). It has been shown for molecules such as those commonly found in plasma etching, that the dissociation which generates etchant is driven by the electron properties (Phelps and Van Brunt, 1988). The relationship between dissociation and etchant generation is driven by the dependency of electronic excitation cross sections on electron energy. By mounting the probe tip on a moveable platform with known spatial resolution, it is possible to generate radial profile maps of electron energy and density.

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\

C&

scree-

J

31 7

Since the electrons drive the etch chemistry, information relating to their properties is essential to a complete picture of the process and for improved control. Figure 6-10 contains a schematic representation of a Langmuir probe. Figure 6-11 shows the spatial variance in the probe I- I/ characteristic. In Fig. 6-11, position 1 is over the edge of a 150 mm wafer, position 2 is at 75 mm and position 3 at the center. When making probe measurements, care should be taken to insure a good ground plane is available. Also, in order to avoid excessive particle generation and possible vacuum failure, the use of welded bellows in the probe assembly should be avoided.

alumina sleewng

6.3.3 Control Techniques

-or

Figure 6-10. Schematic representation of a typical Langmuir probe circuit.

Original plasma etch tools had little or no sophisticated control. For the most part, machine settings were established and the operator manually turned the R F power on and off to start and then stop the

Field at 270 Degrees

-

0.06

0.06

4 I

0.04

-

0.03 0.02

0.01

+

~

Figure 6-11. Typical Langmuir probe I - V characteristic.

POS3

31 8


process. Soon the need for pressure control became apparent, to be followed by mass flow control, then temperature control. As mentioned above, R F power has always been a source-controlled parameter, rather than controlled at the load. For the most part, even with RF, the control strategy has been simple proportional-integral-derivative (PID) control. However, as the industry progresses into the 1990s, the need for improved machine control is becoming clear owing to the requirements of larger, more expensive, more complex wafers and in some cases, more complex etch tools. The following sections explore machine control from its present state to possible solutions for future needs.

6.3.3.1 Present Control Strategy Etch processes are presently controlled by a number of independent P I D loops. Each loop is based on some metrology (often misplaced) and a simple algorithm for modifying the drive signal to either a valve or other electromechanical device. A classic example of this form of control is seen in the pressure PID. The following sequence of events is typical of what would happen should a C1, M F C corrode and fail shut. A transducer generates a voltage proportional to the chamber pressure, which is sent to the controller as input for a decision. Suppose the pressure is determined to be low. Then the controller would in turn send a signal to the throttle valve instructing it to close, causing the pressure to rise. Without some sort of plasma or improved mass flow metrology the user would not know that there was a problem until the processed wafte was inspected and found to be scrap. Existing, independently operating PID loops create just such problems. This problem is compounded by the current lack of plasma metrology. Since there

is almost no information presently generated relating to the discharge characteristics, the plasma essentially runs open loop. By its very nature this condition induces run-to-run variability.

6.3.3.2 What is Needed? The most obvious answer to this question is improved metrology. From the point of its contribution to the success of an etch process, the availability of good information generated from the correct location in the system and relating to critical process parameters such as R F voltage, current, phase and the electron properties would have a huge impact. Figure 6-12 illustrates the difference in present and future control strategies. It should be pointed out that as yet the use of single wafer process tools has not been optimized due to the inability to detect an out of control situation during the processing of a lot of material. The proper addition of metrology fulfills the promise of single wafer tools. For some, this may seem like a large if not huge step. However, the payback for such efforts can be readily measured in terms of wafers saved or added and is found to be very fast. The payback of a $50 k investment in metrology equipment would be less than a single shift’s production of a typical 4 Mb DRAM product. Secondly, correlated information will make examples like the one above non-existent by allowing the pressure control PID to know that there is a problem with the MFC. Another significant improvement would come in the form of a true multivariate input/multivariate output optimization utility to replace existing RSM techniques. Since RSM is only a multivariate input,’ single response technique, it is difficult to apply to problems such as etching which has multiple responses (rate, uniformity, selectivity, anisotropy, and damage).


31 9

Present Plasma Process Control [LEiF]

[L+G-]

R+ ITCH ESIJLTS.

LOOP

m a

OPm LOOP

PLPSMP.

SBM Approach Completes the Promise of Single Wafer Processors

I

I

1

COPITROUB,

Figure 6-12. Present and future control strategies.

6.3.3.3 Possible Solutions Along with the obvious solution of adding metrology, improvements in control strategies must also be made. A simple extension of present statistical process control (SPC) techniques to use data in real time could make a significant improvement in the ability to detect and correct for out of control situations. This simple solution could also eliminate mis-processing the wafer in the example of the failed MFC described above. A real time SPC routine

could be used with either machine (power, pressure, flow,. . .), or plasma information. Embedded control could also consist of empirical models generated with multivariate optimization routines. These models should be capable of predicting correct machine settings for the generation of specific plasma characteristics necessary for various product wafers. It is most likely that the final advanced control package will be a hybrid of PID, SPC and model based. The SPC package could detect the out of control condition and pass control

320


to the model. The model package could then determine a proper response and relay these new machine settings to the PID controllers for each subassembly. At the present time efforts to define the next generation control system are underway at various university and manufacturing locations. It is difficult to predict the outcome of current efforts; however, it can be anticipated that over the next decade etch tools will undergo drastic changes in order to meet product design specifications.

6.4 Process Discussion: General Considerations 6.4.1 Isolation

Etch processes for different isolation techniques are, as expected, operated with different process requirements. The SWAMI (sidewall mask isolation) process, for example, requires an anisotropic nitride and oxide etch, followed by a silicon etch-todepth with a smooth etch front and profile control at the bottom of the silicon feature (similar to trench etch requirements). The SILO (sealed interface local oxidation) isolation requires a more complex structure and a self-aligned etch of nitride-pad oxide-thin nitride structure followed by a silicon etch to recess the field oxide. The issue of stress control of the silicon after field oxidation requires a tapered, round-bottomed silicon etch. Some of these problems and trade-offs involved in the etch process are discussed by Parrillo (1986) and Brassington et al. (1988). Trench isolation can be described in the context of shallow or deep trench isolation. In this context, shallow trench isolation is a LOCOS (local oxidation of silicon) replacement that gives more planar isolation. Shallow trenches ( < 1 pm) do not sig-

nificantly improve isolation performance and latch up resistance but can be considered a more planar LOCOS replacement. The processing cost is in the trench etch (usually a photoresist mask/nitride/pad ox stack is used), the mask removal, the CVD oxide deposition, and the planarization etchback of this oxide. This etchback may involve multiple resist layerings to achieve a suitably planar surface. Deep trench isolation has the advantages of potentially eliminating latchup and using less real estate than other techniques. The fabrication complexity of this structure is the reason why it is not in common use at the 4 M b level. Here, “deep” means deeper than 3--4 pm: the trench etch step itself takes some minutes in the etcher and requires multiple etch chambers to meet factory throughput demands. The etch requirements are severe: The sidewall and bottom profiles must be controlled and the process must be well centered in a wide process window since only destructive, time consuming SEM techniques can be used to inspect these etch results. The sidewalls must remain undamaged and a high quality thermal oxide must be capable of being grown on them. (A sacrificial oxide may be used first.) Typically, deep trenches are etched with chlorine or fluorinebromine based chemistry: a hard mask is required for this etch. Tachi and Okudaira (1986) have measured the silicon reaction rates with F’, Cl’, and Br’ and have shown that of the three, Br+ etching of silicon has the strongest dependence on ion energy. Table 6-5 summarizes the range of geometries that are commonly associated with different etch chemistries. The use of bromine-containing gases in this etch process has a number of advantages, most notably higher selectivity to oxide masks and increased capability to etch deep, narrow feature. Figure 6-13 shows a 21 : 1 aspect

6.4 Process Discussion: General Considerations

32 1

Fdble 6-5. Trench etch chemistries for different geometries.

Chemistry Mask Etch depth (1 pm mask) Etch profile

Fluorinated

Chlorinated

Brominated

photoresist 3 Pm depends on mask profile

oxide 10-15 pm always vertical

oxide/nitride >20 pm always vertical

ratio trench etched in Si using brominecontaining etch chemistry. The high selectivity to oxide obtained with this chemistry also means that care has to be taken to avoid black silicon formation. After the trench is etched, it must be filled, the fill planarized or at least etched back, and the isolation structure capped with (usually) a LOCOS oxidation. The fill process usually uses polysilicon which is easily oxidized to cap the trench (Silvestri, 1986) and can fill the trenches without voiding. Details of trench etch processing are found in literature: the ion energy dis-

Figure 6-13. Trench etched with bromine chemistry: the 0.2 x 4.2 pm trench demonstrated the usefulness of bromine chemistry for etching high-aspect-ratio trenches.

tribution and ion scattering effects on sidewall profiles are discussed by Sat0 and Arita (1984). Mechanisms and sidewall analyses are presented by Hirobe and Nojiri (1987) and Oehrlein et al. (1990).

6.4.2 Gate Definition Gate definition etch tolerances now require operation to extremely tight specifications of control, rate, uniformity and particle control as well as control of gate oxide integrity and sidewall profile. Furthermore, the gate electrode now consists of a doped polysilicon layer that is frequently covered with a refractory metal silicide to decrease the resistance of the electrode. The common use of an LDD (lightly doped drain) structure to control hot carrier effects on small ( E

W

-

0

-

Y

-1

SI

W -I

a

--

W

10-6

10'~

1 015

10'6

BACKGROUND DOPING NB ( ~ r n - ~ )

2

Figure 7-6. Depletion-layer width ( Wm), maximum field at breakdown (8,)and breakdown voltage (V,) for one-sided abrupt Si pn junctions (after Sze and Gibbons, 1966).

10-8

k

10-12 10-3

10-2

10-1100 101

plotted in Fig. 7-6 for a one-sided abrupt Si p-n junction at 300 K.

102

vR(v)

7.2.4 Bipolar Transistor

(b) Figure 7-5. The current-voltage characteristics of a Si pn diode at various temperatures. (a) Forward bias. (b) Rekerse bias.

tained from the maximum depletion-layer width W, and the maximum critical field 6,, 6 , = q NBW,/E,. The breakdown voltage V, is 2

, 6, v, = E__ NB-

(7-10)

2q

The breakdown voltage, the maximum field e,, and the maximum depletion-layer width at breakdown W, versus NB are

The bipolar transistor is an active threeterminal device that combines an n-p junction and a p-n junction by means of a common middle p layer (base) which is very narrow. This is the npn bipolar transistor. Its complementary type is the pnp bipolar transistor. The band diagram of an npn bipolar transistor is shown in Fig. 7-7a. The solid lines are for the normal bias condition (i.e., emitter-base forward biased and the base-collector reverse biased) and the dotted lines for the equilibrium condition. Figure 7-7 b shows the minority carrier distribution profiles. Note that due

7.2 Potential-Effect Devices

EMITTER

BASE

COLLECTOR

VF: *0.6V E

E Fn

(a) REVERSE

FORWARD

"

n

p

m

n

I

CB

- -

EMITTER

BASE

I R

IC

COLLECTOR

bJLL I LUX

35 1

tion current I , in the E-B junction and a generation current I, in the C-B junction as shown in Fig. 7-7 b. In Fig. 7-7c, the electron current In, is emitted from the E-B junction and diffuses through the base with partial leakage to the base due to electron-hole recombination InB.The remainder In, is collected by the collector electrode. Hole-diffusion current IpEand I, is injected from the base to the emitter. This current makes no contribution to the collector current. Therefore, to achieve a high current gain, the hole-diffusion current should be minimized. I , and I , are the leakage currents due to diffusion and generation, respectively, under a C-B reverse bias condition. The inverse of current gain h;' can be expressed (Yang, 1988) as

NdC

Applying the p-n junction current theory,

5v

0.6V

(C)

Figure 7-7. An npn transistor in equilibrium and in nonequilibrium. (a) Band diagram and quasi-Fermi levels under bias compared to a no-bias condition. (b) Minority-carrier concentrations under normal active bias. (c) Carrier flows in the respective regions.

to a reverse bias applied to the collectorbase (C-B) junction, nP(xB)% 0 while n, (0) = npoexp [q V&/k T ) ]due to forward bias in the emitter-base (E-B) junction. It is easy to apply the same principle, discussed in the previous section (7.2.3), to derive the current flows in the respective regions. In addition, there is a recombina-

+

NA 'B

'dE

e - e V e / ( 2 kT )

(7-12)

DnB ni ' 0

Subscripts E, B, C refer to the emitter, base, and collector respectively. From Eq. (7-12), hfe increases with decreasing base doping concentration NAB. This, in turn, decreases the high-frequency performance due to a large base spreading resistance R B B . The maximum unity-power-gain frequency f,,, is (Sze, 1990) (7-13) where f is the cutoff frequency at unity current iain due to total delay and transit time from E to C. A heterojunction bipolar

352

7 Silicon Device Structures

transistor can meet the requirements of both high gain and high-frequency response by having wider bandgap material in the emitter. This will be discussed in the following two sections. A modern high-frequency, doped polycrystalline emitter, bipolar transistor is shown in Fig. 7-8. The device was fabricated in a double-polysilicon self-aligned bipolar process (Chen et al., 1989). A schematic cross section is shown in Fig. 7-8 a. A p - substrate with an n+/n-epitaxial layer was used. Then, the device fabrication follows the polysilicon refilled-trench isolation process. An epitaxial p-type layer was grown on top of n-collector and isolationE

B

oxide layer. After p+-polysilicon delineation, oxidation, and n f -polydeposition at the emitter window, a thermal furnace and rapid thermal annealing were used to provide a shallow emitter-base junction. A representative device profile is shown in Fig. 7-8b. The estimated base widths range from 63 to 95 nm with an emitterbase junction depth of about 25 nm. Such devices exhibit gains ranging from around 100 to 200, depending on the base implant dose and the resulting base Gummel number. The cutoff frequency f, reaches 51 GHz at a current density of more than 1.0 mA/pm2 while maintaining an emittercollector breakdown of 3 V. The total transit time is less than 3.0 ps.

C 7.2.5 Heterojunction

n' - EPI

-.P

10'8

PY

i J

c

0.0

0.1

0.2 0.3 DEPTH ( p m )

0.4

0.5

(b)

Figure 7-8. The self-aligned poly-Si emitter npn bipolar transistor. ( a ) Schematic device cross section. (b) Representative secondary ion mass spectrometry (SIMS) profile of a device obtained from a monitor wafer (after Chen ct ai.. 1989).

In the early 1980s, a new unorthodox player emerged on the heterostructure scene, Ge,Si, - x on Si (Kasper and Bean, 1989).The lattice constant of germanium is about 4% larger than that of silicon. For a strained, but not relaxed, overgrowth layer that obeys a rule of equilibrium, the overgrowth thickness should not exceed a critical thickness L , as is shown in Fig. 7-9 with different germanium fractions x. The bandgap versus x is also shown and decreases with increasing x values. The epitaxial growth techniques involve the molecular beam epitaxy (People, 1985), UHV/CVD (Meyerson, 1986), limited reaction process (Gibbons et al., 1985), etc. The band alignment of Ge,Si ,on Si substrates for different x values is shown in Fig. 7-10. The bandgap discontinuity in the conduction band is always smaller than that in the valence band, e.g., AE, = 0.020 eV while AEv = 0.15 eV for x = 0.2, as shown in Fig. 7-loa. For x = 0.5, A E , = 0.15 eV and AEv = 0.30 eV on an unstrained (001) Geo,25Sio,,5buffer layer

353


(not shown), as illustrated in Fig. 7-lob. Figure 7-1Oc shows the band alignment of the Ge,,,5Sio,5/Si heterostructure on a (001) Si substrate (People and Bean, 1986). The heterostructure is the building block for various kinds of novel GeSi/Si devices such as the heterojunction bipolar transistor, MODFET, and resonant-tunneling devices, which will be discussed in more detail in the following sections.

7.2.6 Heterojunction Bipolar Transistor The heterojunction bipolar transistor (HBT) offers numerous advantages over conventional homojunction bipolar transistors for high-frequency and high-speed applications. The advantage is due to the HBT's higher emitter injection efficiency as a result of the bandgap of its emitter being larger than that of its base. Thus, higher base doping and lower emitter doping can be used to reduce the emitter-base delay time. The use of a graded base can further reduce the base transit time.

--

r

A E c = 0.020eV

t

t

STRAINED Eg (Geo.zSio.8 ) = l.OeV

CUBIC E9 (Si)=1.17eV

1

i

A Ev = 0.15 eV

'-7-

Ev

(a)

AEc= 0.150eV EC

t

t STRAINED

STRAINED Eg (Geo.sSio.5

)=

089eV

1

Eg (SiI = 1.04eV AEv

- -

Ev

= 0.30eV

(b)

AEc= 0.020eV --E-

'

Ec

CUBIC

t

STRAINED Ep (Geo.sSi0.s

= 0.78eV

E g ( S i ) = 1.17eV

I (C)

GexSi,., ON SI

1.3

s'

SUBSTRATE

Figure 7-10. Band alignments for (a) Ge,,,Si,,,/Si heterostructures on (001) Si substrates, (b) Ge,,,Si,,,/Si heterostructures on an unstrained (001) G e o , 2 ~ S i o , , ~ buffer layer, and (c) Ge,,,Si,,,/Si heterostructures on (001)Si substrates (after People and Bean, 1986).

1.2

0

v

a

3

1.1

Figure 7-11 a shows the band diagram of an HBT. Following the analysis of Eq. (7-12), the current gain, limited by emitter injection efficiency, is

1.0

>

g

0.9

W

2

w 0.8 0.7

0 Si

0.4 0.6 0.8 1.0 Ge FRACTION , x Ge

0.2

Figure 7-9. The critical thickness and bandgap energy versus Ge fraction of strained GeSi on a Si substrate (Bean, 1978).

where A E g is the bandgap difference of the emitter and the base. Representative doping concentrations in state-of-the-art HBTs fabricated in the Si/GeSi system are shown in Fig. 7-1 1 b,

354


-5 SiGe

E

-

m

C

B (a)

IO2'

1

1

(550 "C) epitaxial silicon deposition process known as ultra-high vacuum chemical-vapor deposition (UHV/CVD). Demonstrated in this work are the excellent quality of Si/GeSi junctions formed using this method, the advantages of GeSi for bipolar device design, and the integration of this technology into a polyemitter bipolar process. Figure 7-12 a shows the polyemitter bipolar structure with emitter dimensions of only 1.2 x 2.4 pm', that was used in this work. An example of the final doping profile of a GeSi-base device is shown in Fig. 7-12b. In the GeSi-base transistors, the Ge content was graded from 0 to 14% across the base (roughly 6 to 13% across

P EPI BASE 'N

x

I 1

0

0 0.2

1

0,4

5

0.6

0.8

5 1.0

EPI

P - SUBSTRATE

N'

I

(a)

DEPTH (urn) (b)

Figure 7-11. (a) Representative band diagram and (b) doping profile of an HBT.

which should be compared with those of Fig. 7-8 b for the homojunction transistor. In HBTs, doping levels of lo2' cm-3 have been used in the base. As a result, base sheet resistance can be greatly decreased, even with ultra-narrow base regions, and transistor f,,, can be greatly increased, (Eq. (7-12)). In recent work (Meyerson et al., 1990), Si and graded-GeSi-base bipolar transistors were fabricated in a standard polyemitter bipolar process using the low-temperature

DEPTH ( n m )

(b)

Figure 7-12. (a) Schematic cross section of the nonself-aligned bipolar structure with a base formed by UHV'CVD low-temperature epitaxy. (b) SIMS impurity profile of a 75 GHz (GeSi-base transistor (poly-Si emitter contact not shown) (after Meyerson et al., 1990).


the neutral base region), with the highest Ge percentage (largest bandgap reduction) occurring at the base-collector junction. The smaller bandgap in the base reduces the barrier for electron injection into that region, while the bandgap grading introduces a drift field (over 15 kV/cm) to aid the transport of electrons across the neutral base. The maximum cutoff frequency of the GeSi transistor increases from 75GHz at 298 K to 94 GHz at 85 K at a collector current of 28 mA. Equally significant, the peak cutoff frequency of the homojunction Si device increases from 52 to 57 GHz for a doubling of collector current, as illustrated in Fig. 7-13. The larger relative improvement for the graded-GeSi base transistor results from the quasi-field created by the bandgap grading in the base. This field is more effective at low temperatures, and it compensates the degradation in diffusivity of the base (Grabbe et al., 1990). A combination of the high density of ULSI and the high speed capability of GeSi-based HBT technology will have dramatic impact on future electronics system applications.

7.2.7 Thyristors The thyristor is a four-layer device that has an npnp or a pnpn structure. It can be treated as two transistors, one an npn and the other a pnp, connected in series. A schematic diagram of a thyristor is shown in Fig. 7-14a. Under forward conducting conditions, both p l -pl and n2-p2 are reverse biased while nl -p2 is forward biased. When the sum of current gains zl,a2 of the two transistors becomes unity, the device is turned on to a high-conduction state. The doping profile and the currentvoltage characteristics are shown in Fig. 7 -14 b and c, respectively (Yang, 1988). The

TEMPERATURE

0.004

0.006

0.008 1/T

(

355

K)

0.01

0.012

(K-')

Figure 7-13. Collector current dependence of iT at 298 K and 85 K for Si and SiGe devices. In both cases, the peak fT and the associated collector current increase at lower temperature (after Grabbe et al., 1990).

basis current-voltage characteristic of a p-n-p-n diode exhibits five distinct regions: 0 -+ 1: The device is in the forward-blocking or off state and has a very high impedance. Forward breakover (or switching) occurs where dVdZ = 0; at point 1 we define a forwardbreakover voltage V , and a switching current I,.

356


’A

REV

/\i~:c loL8 impurity atoms/cm3), field emission becomes dominant. For the classical metal-silicon contacts (e.g., Al), metals are deposited physically (e.g.,by evaporation) or chemically (e.g., by chemical vapor deposition) onto a silicon surface. One potential problem is the possible contamination of the interface between the metal layer and the silicon surface. Recently, there has been a significant emphasis on the use of silicide-silicon contacts instead of the classical metal-silicon contacts. The new contacts are of interest because (1) many silicides have relatively low resistivities and, (2) silicide is formed underneath the original silicon surface and the silicide-silicon interface is generally free of oxides, impurities, or defects. Therefore, the silicide-silicon contacts are more reproducible and highly reliable. A new model for the silicide-silicon intimate contacts has been proposed based on microphysical investigations that show the existence of an interphase layer between the silicide and the silicon surface. This transition layer is responsible for the grad-

359

ual shift from silicon to metal silicide. The equilibrium band diagram of the silicide/ transition layer/silicon is shown in Fig. 7-18. The barrier height for the electrons in the metal, 4n, is the Schottky barrier. From Fig. 7-18, we obtain

where 4Mis the metal work function, x is the electron affinity, (A4)M is the change in electrostatic potential at the metal surface, and p is given by (7-18) where d is the transition-layer thickness (about 30 8, for a CrSi,/n-Si contact), A is the penetration depth in silicide (0.5 8, for CrSi,), and E , and E , are the dielectric permittivities in silicon and metal, respectively. The new model can explain the bias and temperature dependence of the current-voltage characteristics using a fielddependent barrier height as given by Eq. (7-17) (Sze, 1991).

x:O

\SILICIDEON TII;:::\

x:d

\

n-Si

Figure 7-18. Thermal equilibrium energy diagram for the silicide/transition layer/n-Si system (after Sze, 1991).

360


7.3.2 Homogeneous Field-Effect Transistors

Homogeneous field-effect transistors include the JFET (junction FET), the MESFET (metal-semiconductor FET), and the PBT (permeable-base transistor). They employ homogeneous semiconductor materials instead of heterojunctions to offer greater simplicity and ease of fabrication, because they do not depend critically on the precise control of layer thicknesses and sharp interfaces. The JFET consists of a conductive channel for current flow and two ohmic contacts. It uses the depletion region of a reverse-biased p-n junction as the gate electrode to modulate the crosssectional area of the conductive channel. The operation of a MESFET is identical to that of a JFET. The MESFET, however, has a metal-semiconductor rectifying contact instead of a p-n junction for the gate electrode. Silicon JFETs have been used extensively in many discrete and IC applications. Si MESFETs are more difficult to make than Si MOSFETs due to the great care needed to prevent native oxide formation at the metal-silicon interface. Furthermore, Si MESFETs are relatively unpopular, because they are outperformed by Si MOSFET and bipolar transistors. The Si permeable-base transistor (PBT) is a high-speed device that can be used in analog applications at microwave frequencies. I n contrast to the planar homogeneous FETs such as JFET and MESFET, the PBT is a vertical device in which the current flow is normal to the Si waver surface rather than parallel to the surface. Because of lower effective electron velocity in Si, the frequency capabilities of the Si PBT are below that of its GaAs counterpart. However, the Si PBT provides a practical, high-performance microwave device that

Figure 7-19. Cutaway diagram of a Si permeablebase transistor (after Rathman and Niblack, 1988).

has advanced fabrication technology and superior thermal conductivity. A schematic diagram of a Si PBT is shown in Fig. 7-19. Grooves are etched into an n-type Si layer, a metal (e.g., Pt) is deposited on top of the ridges and in the bottom of the grooves and then sintered to form silicide (e.g., PtSi) emitter and base contacts. Selective ion implantation is used to dope the active region and to obtain device isolation. Si PBTs with a grating periodicity of 0.32 pm have demonstrated a maximum frequency of oscillation (fmax) of 30GHz and a cutoff frequency (f,) of 22 GHz. Si PBT has very low llfnoise and excellent performance in low-noise oscillators (Rathman and Niblack, 1988). 7.3.3 MOS Structure and Charge-Coupled Devices The MOS diode is the heart of the most important device for very-large-scale integration the MOSFET. It is also of paramount importance in semiconductor device physics. In recent years, MOS structures have been adopted for even wider applications. One example is the tactile imager for use in precision robotics applications where high packaging density and high resolution are required.

7.3 Field-Effect D e v i c e s

THIN SILICON SUPPORT BEAM

361

DEEP BORON DIFFUSION

GLASS SUBSTRATE

Si02

,< + -+ -A -,

........ ............................. .......... .......... ........ .......

Figure 7-20 shows the MOS structure of the imaging cell. The force-sensitive capacitor is formed between the lower metallic plate on the glass substrate and a thick Si center plate that is supported by two thinner Si beams. When a force is applied to the top surface of the center plate, it deflects the thin beams to change the capacitive gap and hence the cell capacitance. The dielectric film over the center plate prevents electric shorts and provides buildin over-range protection when excessive force causes the plates to touch. The fabrication sequence of the tactile imager is shown in Figs. 7-20b-e. The process starts with a p-type (100) Si wafer. The wafer is oxidized and oxide mask patterns aligned to (1 10) are formed by HF etching. The Si islands are then created by

Figure 7-20. Fabrication of an MOS tactile imaging cell: (a) device cross section, (b) KOH etch, (c) deep boron diffusion, (d) shallow boron diffusion and dielectric deposition, (e) electrostatic bonding and final wafer etching (after Suzuki et al., 1990).

anisotropic etching in KOH, Fig. 7-20 b. Next, a thick oxide is thermally grown and patterned, followed by a deep boron diffusion, which defines the thickness of the center plate and the bonding islands, Fig. 7-2Oc. All oxide is removed and a third oxide is grown and patterned, followed by a shallow boron diffusion to define the supporting beams. Finally, a thin oxide and a thin nitride layer are deposited and patterned to form the protective dielectric, Fig. 7-20d. A glass substrate is metallized and patterned. The Si structure is fused to the glass substrate by electrostatic bonding. The device is placed in an EDP (ethylene diamine-pyrocatechol-water) etchant, which etches the lightly doped silicon wafer and stops at the boron p t layer, Fig. 7-20e.

362


This MOS structure is rugged and has a high damage threshold against excessive force. It operates over a wide temperature range and has a low temperature sensitivity ( < 30 ppm/-C). A 32 x 32-element, capacitive Si tactile imager has been made; it can be read at a rate of 15 ps/element offering an effective frame rate of 5.1 ms (Suzuki et al., 1990). A charge-coupled device (CCD) is basically an array of closely spaced MOS diodes. Under the application of a proper sequence of clock-voltage pulses, the MOS diode array is biased into the deep surface depletion. By changing the potential across the array, the charge packet (representing the information) can be stored and transferred in a controlled manner across the Si substrate. To increase the clock rate and to reduce the clock voltage, an ultrafast, buriedchannel CCD with built-in drift field has been designed and fabricated. A schematic diagram of the C C D and the calculated

2.5

15.01 0

1

10

I

20

I

30

DISTANCE ( W r n )

Figure 7-21. Step-doped, charge-coupled device with the calculated potential distribution. The barrier gate is 4 prn and the storage gate is 7 pm (after Lattes et al., 1991).

potential profile are shown in Fig. 7-21. It has 4 pm barrier gates and 7 pm storage gates. The potential gradient is permanently built into the storage gate by a step implant to improve the charge-transfer efficiency (CTE) at high clock rates. The buried channel is defined by a uniform phosphorus implant, a second phosphorus implant is added to create the storage wells. The delay lines are operated with 5 V two-phase clocks. The CCD has been tested up to 325 MHz with no degradation in CTE ( > 0.99996). The equivalent C C D with uniformly doped storage wells degrades rapidly above 240 MHz (Lattes et al., 1991).

7.3.4 MOSFET 7.3.4.1 Submicrometer MOSFET The metal-oxide semiconductor fieldeffect transistor (MOSFET) is the most important device for very-large-scale integrated circuits ( > IO5 components/cm*) and ultra-large-scale integrated circuits ( > 10’ components/cm2). It is a four-terminal device as shown in Fig. 7-22a, consisting of a p-type Si substrate into which two n + regions, the source and drain, are formed. (This is called an n-channel device. One may consider a p-channel device by exchanging p for n.) The top metal contact is called the gate. Heavily-doped polysilicon or a combination of silicide and polysilicon can also be used as the gate electrode. Because the gate electrode is used as a mask to implant the source/drain regions, it self-aligns the source/drain with respect to the gate to minimize parasitic capacitance. The sidewall oxide spacer is used to bring the source/drain ohmic contacts as close as possible to the channel without shorting the source/drain to the gate electrode.

7.3 Field-Effect Devices GATE

P

n’

A

L

SIDEWALL OXIDE

h

n’

-1

p- Si

b SUBSTRATE (a1

SHALLOW n D- S i

SIDEWALL OXIDE

I

(b) Figure 7-22. (a) MOSFET with sidewall spacer. (b) MOSFET with sidewall spacer and lightly doped drain structure.

The basic device parameters are the channel length L, the oxide thickness d, the p-n junction depth rj, and the substrate doping N . To reduce the channel length to the submircometer ( < 1 pm) region, various approaches have been proposed. An empirical formula has been obtained to serve as a guide for MOSFET miniaturization:

Lmin= 0.4 [rj d (W, + WJ2]’I3 (pm) (7-19) where Lminis the minimum channel length to maintain proper device behavior, W, and W, are the depletion widths of source and drain, with rj, W,, W, in micrometers and d in angstroms. It is apparent that in order to reduce channel length, one must reduce rj, d, and the depletion widths (Sze, 1981). As the channel length moves into the submicrometer region, one key concern is

363

the hot-electron effect, i.e., the high-energy electrons near the drain can cause threshold-voltage shift and degradation of transconductance. To minimize the hot-electron effect, “drain engineering” has been proposed. One approach is the lightly doped drain (LDD) as shown in Fig. 7-22 b. The drain consists of a shallow lightly doped n region followed by a deeper n + region. By proper design of the doping and the extension of the shallow n region, one can substantially reduce the peak field near the drain, thus reducing the generation of hot carriers there (Brews, 1990). To place millions of devices in an IC package, we must reduce power dissipation. Because of its low power dissipation, CMOS (complementary MOS) technology becomes the dominant technology in which both n-channel and p-channel devices are constructed simultaneously on the same substrate. Two examples of submicrometer CMOS devices are shown in Fig. 7-23. The device shown in Fig. 7-23 a has twin wells on a p- substrate. Each well is 2 pm deep and of retrograde type formed by high-energy ion implantation. The 2.2 pm deep trenches isolate the wells. The wells are 1 pm wide and are filled with chemicalvapor-deposited SiO, on top of a 200A thick thermal oxidation layer of the trench surface. The active regions of each device are delineated with the LOCOS (local oxidation of silicon) process. The gate-oxide thickness is 35 A. Surface-channel nMOS and buried-channel PMOS are employed so that a phosphorus-doped n + single-gate process can be used. The use of retrograde wells and trench isolation gives the devices a high latch-up immunity. The transconductance of the 0.22 pm gate-length n- and p-MOSFETs are 450 and 330 mS/mm, and unloaded ring-oscillator delays are 36 ps at 2 V (Okazaki et al., 1990).

364

7 Silicon Device Structures P DOPED

J:-s:ocos

SI02 \

P-

(a)

PMOS

nMOS

LOW-IMPURITY-CHANNEL

EPITAXIALLY GROWN FILV

1

\t HIGHLY DOPED W E L L

(b) Figure 7-23. (a) Cross section of sub-0.25 pm CMOS device (after Oka7aki et al., 1990). (b) 0.1 pm CMOS device using low-impurity-channel transistors (after Aoki et al.. 1990).

improved by increasing the hole mobility. One novel approach is to place a buried Ge,Si, - - x layer under the gate of a pMOSFET as shown in Fig. 7-24a where a 100 8, Ge,Si - ,layer is grown on a Si substrate, followed by the growth of a Si spacer layer of 30-90 A, both by chemical vapor deposition. Figure 7-24b shows the band diagram at the flatband condition for a structure with a 75 8, Si spacer and a 100 8, Geo.4Sio,6 well. The quantum well for holes is created because the bandgap discontinuity between Si and Ge,Sil -,occurs predominantly in the valence band. When a negative gate voltage is applied, an inversion layer is formed in the Ge,Si, -,well as shown in Fig. 7-24c. Numerical simulations have indicated that it is desirable to employ a minium Si spacer thickness and a maximum Ge fraction to maximize the number of holes confined in the Ge,Si, -, well. Since the hole mobility in Ge,Si, -, is higher than that in Si, this MOS-gated Ge,Si -./Si heterostructure is expected to have higher transconductance, improving CMOS performance (Garone et al., 1990). A novel combination of CMOS and bipolar technology has recently been considered. This BiCMOS approach can combine the advantages of both technologies the speed and power-handling capability of bipolar devices with the ease of fabrication and high density of MOS devices. Figure 7-25 shows the cross section of a nonoverlapping, super self-aligned BiCMOS structure. The active areas of the bipolar transistor and MOSFETs are virtually identical. The structure allows complete silicidation of active polysilicon electrodes, reducing the parasitic resistances of the source, drain, and extrinsic base. The gate and emitter regions are protected from exposure and damage from reactive ion etching. All shallow p n junctions are con-

,

Figure 7-23 b shows a 0.1 pm CMOS using low-impurity channel transistors. The impurity concentrations in the low-impu~ , rity channels are 1016-1017~ m - which are about two orders of magnitude lower than those of the highly doped wells. The gate-oxide thickness is 50 8,. Ultra-shallow junctions are formed at 9W'C with rapid thermal annealing to give junctions of 500 8, for nMOS and 1000 8, for PMOS. By proper choice of the thickness of the low-impurity layer, we obtain low threshold voltage (due to low-impurity concentration in the channels) and high punchthrough voltage (due to the highly doped wells). The device shows a subthreshold swing of 40 m V at 77 K (Aoki et al., 1990). The performance of CMOS circuits is limited by the low transconductance of pMOSFET. This transconductance can be

7.3 Field-Effect D e v i c e s

365

ALUMINUM GATE p' BORON IMPLANT

-r

,

\

p + BORON IMPLANT

n - S i SUBSTRATE

I EC EF

Gex Sii-x WELL S i BUFFER

BULK Si

I

1

EV

GexSii.x WELL Si BUFFER

k

T

E

BULK S i

F

Ev

(C) Figure7-24. (a) Cross section of an MOS-gated Ge,Si, - x device. (b) Thermal equilibrium band diagram of the device with a 75 8, Si buffer and a 100 8, Ge,,,Sio,, well. (c) Band diagram of the device when the Ge,,,Si,,, well is inverted (after Garone et al., 1990).

GATE

NMOS

0 Si02 POLY

S/D

tacted by polysilicon electrodes that minimize silicide-induced leakage. An arsenic buried-collector layer minimizes collector resistance. Fully recessed oxide with a polysilicon buffer layer is used to achieve low defect-density isolation. CMOS with a channel length of 1.1 pm and a width of 10 pm exhibits ring oscillator delays of 128 ps/stage. The corresponding n-p-n transistor has a cutoff frequency of 14 GHz and a ring oscillator delay of 87 ps/stage. This BiCMOS structure is suitable for gigabits per second, digital VLSI applications. By scaling down the device dimensions, even higher speed operation is anticipated (Chiu et al., 1991). Another novel combination is the integration of Si devices with compound-semiconductor devices using heteroepitaxial technology. However, there are many difficulties in Si heteroepitaxy. These include lattice mismatch (the lattice of GaAs is 4% larger than that of Si), mismatch in thermal

GATE BASE EMITTER COLLECTOR

-

PMOS

ALUMINUM SILICIDE

BIPOLAR

N * - REGION P * - REGION

Figure 7-25. Cross-sectional view of a nonoverlapping, super self-aligned BiCMOS structure (after Chiu et al., 1991).

Next Page

366


expansion coefficient (2.6 times larger for GaAs), and antiphase disorder due to single atomic layer steps on a Si surface. Various approaches have been investigated to grow compound semiconductors heteroepitaxially on a Si substrate, and the viability of GaAs-based millimeter-wave integrated circuits on Si substrates has been established. Figure 7-26 depicts a cross section of a Si wafer showing GaAs MESFETs integrated with Si CMOS devices. The Si devices are fabricated first because they require higher temperatures for their formation than do the GaAs devices (Shichijo et al., 1988). It is conceivable that a monolithic integration of digital and analog devices, Si and non-Si devices, and electronic and photonic devices can be built on a Si substrate using heteroepitaxial technology. This technology will create novel system architectures and enhance overall system performance.

7.3.4.2 Silicon-on-Insulator Devices When devices are scaled down to submicron dimensions, they are also pushed closer together to increase the packing density. But close packing of devices places severe demands on isolation between devices. One solution to the isolation requirement is to build the circuit on an insulating substrate. A silicon-on-insulator (SOI) MOSFET is shown in Fig. 7-27 where a MOSFET is built on a silicon dioxide layer, so substrate isolation does not require buried n + regions as shown previously in Fig. 7-25. There are additional advantages of SO1 devices. Since there are no parasitic p-n-p-n's in SO1 devices, there is no latch-up in CMOS circuits. The volume of the p region under the gate is much smaller than that of the conventional device, there-

TiW/Au PLASMA LPCVD OXIDE NITRIDE

\ I

1

BORON lSOLATlON POLYSILICON 1

p-Si, 3' OFF

-

SCHOTTKY GATE

I

-

Figure7-26. Cross section of a Si wafer showing a GaAs MESFET integrated with Si CMOS devices (after Shichijo et al., 1988).

fore, only a limited number of electronhole pairs will be generated under radiation by high-energy particles. The SO1 devices can thus stand a much higher dose of radiation than a conventional MOSFET. When the silicon film (p region) is fully depleted, the device behavior will depend on both the top and bottom Si-SiO, interfaces. this two-sided behavior lowers the fields inside the device and tends to reduce hot-electron effects and short-channel effects. Furthermore, the subthreshold slope S can be improved in a fully depleted device. The slope S is proportioned to (1 + CJC,,), where C, is the capacitance between the silicon surface and ground and Coxis the gate-oxide capacitance, both per unit area. For a bulk or non-fully depleted MOSFET

c, = E,/W

(7-20)

,--SOURCE

,

TGATE

DRAIN

15,-02

p-

SUB ST RATE

urn

db-0.6)~rn

Figure 7-27. A MOSFET built on an insulating substrate (after Brews, 1990).

Previous Page

7 . 3 Field-Effect Devices

where E , is the permittivity of Si and Wis the surface depletion width. For a fully depleted device, the capacitance C, is a series combination of the capacitances of three layers:

c,= -+-+: d b ('si

/%

Lox

Kub\-' 6s

SILICON

367

SILICON

(7-21)

/

where tSi and d, are the depleted Si film thickness and the lower oxide-layer thickness, respectively (shown in Fig. 7-27), and Wsub is the depletion width in the supporting silicon substrate. If C, from eq. (7-21) is less than C, from Eq. (7-20), the SO1 device has a lower S than the bulk device for the same Cox(Brews, 1990). The major problem in SO1 technology is the relatively poor quality of the material, since it is difficult to produce a high-quality Si film on an insulating substrate. SO1 technologies include ZMR (zone-melting recrystallization of polysilicon by using a laser beam or a strip heater), FIPOS (full isolation by porous oxidized silicon), and SIMOX (separation by implanted oxygen, i.e., implantation of oxygen ions into Si followed by high-temperature annealing to form buried SiO,). These technologies are still evolving and their success depends on further improvements in the quality of Si film. A new SO1 method has been introduced to yield ultra-thin, defect-free silicon on silicon dioxide. This technique uses epitaxial okergrowth of Si and chemical-mechanical polishing. Figure 7-28 shows the fabrication sequence. A thermal oxide (0.3 pm) is grown and a polish-stop film is formed (Fig. 7-28a). Narrow lines are opened in the exposed oxide to act as a seed area for selective epitaxial silicon growth (Fig. 7-28 b). These lines are along (100) so that a defect-free film can be obtained by an epitaxial lateral overgrowth process, i.e., the growth initiates in the seed area and

(C)

(d 1

Figure 7-28. Fabrication sequence for producing Sion-insulator (SOI) structures using epitaxial lateral overgrowth and chemical-mechanical polishing (after Shahidi et al., 1990).

grows vertically and laterally over the oxide, as shown in Fig. 7-28c. Chemical-mechanical polishing is used to thin the film. The polishing process is stopped when the polish pad reaches the polish-stop film. This process produces a SO1 film thickness that is determined by the polish-stop film thickness (Fig. 7-28 d). The quality of the SO1 film is equivalent to bulk silicon, and the basic device characteristics are comparable to those resulting from fabrication on bulk. However, because SO1 devices have better isolation and lower parasitic capacitance, ring oscillator measurements on the SO1 film have shown significant speed improvement over the bulk devices (e.g., 30 ps versus 120 ps for 0.5 pm channel length devices operated at 2 V) (Shahidi et al., 1990).

7.3.4.3 Thin-Film Transistors Thin-film transistors (TFTs) are MOSFETs fabricated by depositing amorphous or polycrystalline semiconductors on largearea glass or other insulating substrates. Because of their lower costs, TFTs are potentially very useful for active-matrix liq-

368

7 Silicon D e v i c e S t r u c t u r e s

uid-crystal displays, printer heads, and image sensors. Figure 7-29a shows a cross section of a polysilicon TFT. The polysilicon films are deposited on an insulating substrate using standard low-pressure chemical vapor deposition techniques. Typically, they have a fine-grain structure of the order of 0.05 pm in diameter. To increase the grain size, lowtemperature seed selection is used by means of an ion-channeling technique. A Si ion implantation can make the deposited polysilicon film amorphous but a few (1 10) oriented grains survive the implant due to the ion channeling effect. When annealed at about 625 "C, the amorphized polysilicon film recrystallizes from the surviving grains via a solid-phase epitaxy process. Much larger grains, in excess of 1 pm, can be obtained. When the channel dimensions are reduced to the same size as the grain size, the TFT characteristics improve dramatically. A comparison of the mobilities for small and large grain sizes is shown in Fig. 7-29 b. Note the substantial increase in mobility for devices with large grains, especially with very small channel dimensions. Mobilities as high as 70 cm2 V - s and O N / O F F ratios larger than lo8 have been obtained in 2 pm devices (Yamauchi et al., 1991).

' '

7.3.4.4 Nonvolatile Memory

Nonvolatile memories are MOSFETs with modified gate electrodes to enable semipermanent charge storage inside the gate. At present, nonvolatile memories such as the EPROM (erasable programmable read-only memory) and the EEPROM (electrically erasable programmable read-only memory) constitute about 10% of all MOS IC scales. The first nonvolatile memory had a floating gate (not connected to external

AI-SI

I

n' POLY-Si

/

n'

AI-Si

I

\ ' n' SPUTTERED Si02

/

LPCVD POLY-SI

VD = 0.5V

*

E

100

m

P + V

50

W

SMALL GRAIN

LL LL

w

0 -I

E

07 -

0

5

10

-

CHANNEL DIMENSION

-1-

15 W:L

20

5

(pm)

(b) Figure 7-29. (a) Cross section of a polysilicon thinfilm transistor. (b) Field-effect mobility in large and small grain polysilicon film as a function of channel dimensions (channel length = channel width) (after Yamauchi et al., 1991).

voltage) sandwiched between two insulating layers, Fig. 7-30a. When an appropriately high field is applied through the outer control gate, charge carriers transport through insulator 1 and charge the floating gate, giving rise to a threshold voltage shift. Such a device can function as a bistable, nonvolatile memory, because the charges are stored even after the charging field is removed due to a much lower probability of back-transport. If avalanche injection of electrons (near the drain) is used to charge the floating gate, we have a FAMOS (floating-gate

7.3 F i e l d - E f f e c t D e v i c e s INSULATOR 2

369

CONTROL GATE

(a) 9 VG

A

AI

..

Si3N4

..

PoLYS'L'CoN sio2

n-Si

Figure 7-30. Nonvolatile memory devices. (a) Floating gate. (b) FAMOS. (c) MIOS. (d) Triple-dielectric structure (after Libsch and White, 1990).

(C)

avalanche injection MOS) nonvolatile memory (Fig. 7-30b). Since there is no outer gate electrode, the initial equilibrium condition can be restored by illuminating the device with ultraviolet light or exposing it to X-ray radiation. A MIOS (metal-insulator-oxide-semiconductor) memory device, shown in Fig. 7-3Oc, has a double-dielectric (AI-Si,N,Si0,-Si) structure. The charge carriers can tunnel through SiO, and are stored at the Si,N,-SiO, interface. Nonvolatile memories are now moving towards higher densities, faster access times, scaled-down cell sizes, lower power consumption, and lower voltage operation (e.g., 5 V for microcomputer systems). A triple-dielectric structure (Fig. 7-30d) has been proposed. Charge transport and storage can be modeled by using two-carrier (electrons and holes) injection simultaneously at both the Si-bulk and gate-electrode boundaries via Fowler-Nordheim or direct tunneling. In the case of low-voltage operations (f5 V), a projected 10 year lifespan and lo6 cycles are obtained for a device with dimensions of 20 8, for the tunnel oxide, 50 8, for the nitride, and 35 8, for the blocking oxide (Libsch and White, 1990).

A novel nonvolatile memory cell has been made based on microelectromechanics. A schematic diagram of the memory cell is shown in Fig. 7-31. The memory cell has a micromachined, conductive membrane in the form of a bridge. The bridge is longitudinally stressed so that it can buckle upward or downward and is therefore mechanically bistable. The cell is fabricated using a modified MOS process. Silicon substrate is covered with a thin, insulating thermal oxide and a spacer layer of 1.5 pm polysilicon. The polysilicon is selectively masked and the unmasked areas are implanted heavily with boron; the implanted

Figure 7-31. Schematic drawing of a rnicroelectromechanical, nonvolatile memory cell based on a bistable bridge (B), a spacer (S), and the substrate (SUB) with lateral electrodes (L) (after Holg, 1990).

370


areas are the etch-stop areas. The bridge material is a thermally grown SiO, layer covered by a 20 8, Cr layer, and the bridge is defined by photolithography and etching. The bridge is released by partly etching away the polysilicon spacer with EDP (ethylene diamine pyrocatechol solution). The etched channels are defined by the boron etch-stop mentioned above. The bistable bridge performs the memory function. The two logic levels are defined by the two stable states: the bridge bending upward or downward. The write function corresponds to the switching of the bridge between the two states. Switching to either state is done electrostatically by applying a voltage between the bridge and the substrate or the lateral electrodes. The read function is done by sensing the capacitance between bridge and substrate. Thus, the memory cell is nonvolatile and fully immune to an electromagnetic field, and the stored data can be retained permanently. Switching voltages around 30 V have been achieved; lower voltages are expected. Since the fabrication technology for the bridge is close to a standard MOS process, we expect that the microelectromechanical memory cells can be integrated monolithically with microelectronic read/ write circuits to form a full memory device (Holg, 1990).

We have used a Ge,Si - ,strained layer to fabricate the Si-based MODFET (modulation-doped FET) in which a two-dimensional electron gas is formed at the GeSi-Si heterojunction interface. The layers are grown at an epitaxy temperature of 600 "C on a (100) Si substrate using the Si MBE system. A schematic cross section of the layered structure is shown in Fig. 7-32a. A Geo,25Si,,,5 buffer layer is deposited on a high resistivity (IO4 cm) p-type Si substrate. The subsequent layers consist of an undoped Ge,Sil -,graded layer with x varying from 0.5 to 0 within the 100A width, and, finally, an undoped Si top layer of 100 8,. Source and drain ohmic contacts

SOURCE

DRAIN

(-

Geo.sSio.slOOA

I

Si

200A UNDOPED

Ge0.25S10.75

T

Sb DOPING SPIKE

0.2 bm

1 BUFFER LAYER

1OLn.crn

Sb DOPING SPIKE

7.3.5 MODFET In Sect. 7.2 we have considered the Ge,Si -,/Si system. A Ge,Si - ,layer can be grown epitaxially on a Si substrate as a strained layer without interfacial misfit dislocations as long as the thickness of the Ge,Si, -,layer is less than the critical thickness (e.g., for x = 0.2, the critical thickness L , is 1600 A, and for x = 0.5, L , is 140 A).

Ev

p o 8 +1ooA

--+-2oooA-

+1ooA+2ooA

I - S I Ge,SII.r G e d l a s GRADED LAYER

I-SI

Gea2sS10.75 BUFFER LAYER

(b) Figure 7-32. (a) Cross section of a GeSi/Si MODFET structure. (b) Band diagram of the n-channel MODFET at thermal equilibrium (after Daembkes et al., 1986).

7.3 Field-Effect Devices

are formed by thermal evaporation of AuSb. The gate is formed by electron-gun evaporation of a Pt/Ti/Au sandwich of 1000 A/IOOO A/1500 8, thickness. The gate length and width are 1.6 and 160 pm, respectively, and the drain-to-source spacing is 5 pm, A schematic band diagram of the nchannel MODFET is shown in Fig. 7-32 b. A 2 DEG is formed in the undoped Si layer adjacent to the Geo,,Sio,, layer. Because of the Ge,Si, --x graded layer we avoid the formation of a second quantum well near the surface. The device shows good FET characteristics with a transconductance of 70 mS/mm. The mobility is 1550 cm2 V - S- near the heterojunction interface. The cutoff frequency is 2.2 GHz. These values are all higher than those of a comparable Si MESFET, indicating the improved transport properties of electrons in the MODFET. Various device optimizations can be made so that the device can have substantially higher transconductance and higher cutoff frequencies. The Si n-channel MODFET can be combined with Si p-channel MODFET to form highperformance Si complementary-logic circuits (Daembkes et al., 1986). A MODFET consisting of p-Geo,,Sio,,/ Ge/Geo,,,Sio,2, with a strain-controlled Ge channel can be fabricated by MBE. A cross section of such a device is shown in Fig. 7-33. A 0.5 pm Geo,,5Sio,25buffer layer is grown on a (100) Ge substrate by MBE. A thin Ge film ( 2 0 0 4 and a thin Ge,,,Si,,, film (150 A) are commensurably grown on the buffer layer. For the doping, Ge atoms are adsorbed on the Geo,,Sio., surface. Finally, a Geo,,Sio., film (150 A) is deposited. The strain at the heterointerface between p-Geo,,Si,,, and Ge is controlled by the Ge,Si,-, buffer layer. By proper choice of x one can maximize the valence-band discontinuity at the heteroin-

' '

371

0.5 p m

Figure 7-33. Cross section of a strain-controlled Gechannel MODFET (after Murakami, 1991).

terface and enable sufficient confinement of the two-dimensional hole gas. The x value is chosen to be 0.75 to give maximum hole mobility. The p-channel MODFET has a ultra-high hole mobility of 9000cm2V-'s-' at 77 K (Murakami, 1991).

7.3.6 Microvacuum Field Emitter One of the major limitations of highspeed semiconductor devices is the carrier velocity saturation due to scattering effects. The carrier velocity in a vacuum, on the other hand, can be substantially higher and is only limited by relativistic effects. Therefore, a microvacuum devices become an important area of study. Figure 7-34a shows a microvacuum triode with molybdenum field-emission cathodes, and a close-spaced Si anode that is made by microfabrication technology. The anodes are fabricated from a (100) p + silicon wafer. A thermal oxide, 2 pm thick, is grown on the wafer. The oxide is then lithographically patterned with 1.25 mm wide lines on 2.5 mm centers parallel to the (1 11) plane. This pattern is transferred by anisotropic etching of Si using KOH to the depth required for emitter-to-anode spacing (up to 20 pm).After dicing, the silicon anode chip is positioned so that the SiO, straddles the emitting area. The anode is

372


,L

I

- 0

100

200 IVOLTS)

V,

(b) Figure 7-34. (a) Microvacuum triode with closespaced Si anode. (b) Current-voltage characteristics of the microvacuum triode (after Holland et al., 1990).

supported by a layer of SiO, resting on the gate electrode. Electrical contact is made to the back of the Si anode chip, which is coated with TiW. BUILT- ON -ANODE

II

I

II

n* C O N T A C ~ REGION

iI

Figure 7-34b shows a set of currentvoltage characteristics for a triode that has an emitter-to-anode spacing of 8 pm. The measured transconductance is 1 pS for a cathode with 2500 emitters. The average tip current is 4 nA per emitter. The transit time is 4 x s at 60 V. The advantage of the Si anode is that much lower anode voltage is required due to the small anodeto-emitter spacing. However, additional studies are needed to improve the transconductance and the emitter current (Holland et al., 1990). Figure 7-35 shows the cross section of a Si avalanche cold cathode. The device is fabricated on a (100) p-type Si epitaxial wafer (4 Q cm) grown on a p + substrate. The emission current is measured with a stainless steel anode at a distance of 1 mm from the cathode. Standard IC processing, including implantation of B, As, and P, is used to fabricate the cold cathode. The As peak is located at a depth of 120 A, and the junction depth is 300 A. When the device is reverse-biased to avalanche breakdown, the reverse current I increases linearly. The emission current I , also increases approximately linearly with increasing I,. The emission efficiency q is defined as lE/(ID + IE). For a single cathode with a 40 ym diameter, a reverse bias of 6.2 V, and an anode voltage of ..

-

/ -- 1

:'SHALLOW

' CHANNEL

II II

I / -

-

p EPILAYER

p'

p' SUBSTRATE

1

I

METAL

si02

0si

Figure 7-35. Cross section of a Si avalanche cold cathode device (after Ea, 1990).

7.4 Quantum-Effect Devices

500 V, is 2 x lo-’. The anode voltage can be lowered to 1 V and the emitter efficiency can be increased when the anode is replaced by cantilevered polysilicon beam to be constructed at a distance of 1-2 p from the emitting cathode as shown by the dashed line in Fig. 7.35. Because of the small area (2 x 20 pm2) of the proposed cantilevered polysilicon beam anode, the expected capacitance is a fraction of a picofarad, thus subpicosecond transit-time operation is posible (Ea, 1990).


well, quantum wire and even quantum dot. For example, a resonant tunneling device was fabricated (Takeda et al., 1990), and the multiple quantum-well structure revealed an excellent infrared detection capability (Kesan et al., 1990). A resonant hotelectron transistor has also been fabricated (Rhee et al, 1989). All these devices will be presented in the following sections.

7.4.2 Quantum Wells, Wires, and Dots In the three-dimensional case, the energy E versus wave vectors k , k can be expressed as

7.4.1 Introduction The quantization effect in field-effect transistors was first observed in a MOSFET in 1966 (Fowler et al., 1966). A twodimensional electron gas (2DEG) in nMOSFET and a two-dimensional hole gas (2DHG) in p-MOSFET are present in the triangular potential well right next to the SiO, -Si interface. Modern lithographic technology can fabricate a MOSFET with a channel length and width of 0.1 pm. For such a small channel, we can find only “one” interface state in the channel, if the interface state density is 10’’ states/cm2. Recently, single-electron trapping was observed. Employing the quantum wire as the channel of a MOSFET, e.g., a MOSFET with a channel length of 1 pm and a channel width of 10 nm, revealed many interesting physical insights (Pepper, 1990). In addition, using resonant tunneling phenomena, different kinds of structures can be made such as the effective-mass filter (Gennser et al., 1990), energy filter (Gennser et al., 1990), and the wave function filter (Rajakarunanayak, 1989), etc. Recent developments in GeSi technology can be employed to fabricate quantum

373

(7-22) where k is the wavevector perpendicular to k l l and m , and m i l are the effective masses in the corresponding directions. However, in a quantum well a standing electron wavefunction is formed. This implies a quantized energy in this direction ( z in real space and k l , in reciprocal space). The wavevector k l l is

kll

1l.t

=-

Lz

1=1,2,3, ...

(7-23)

The E - k relation in a band (conduction or valence band) is given by

The low dimensionality can be further reduced to one dimension and to zero dimensions, in which the transverse wavevector k is further quantized. Generally, the density of states (DOS)in d dimensions can be found. The number of states per unit volume in k-space is ( 2 ~ ) ~ , where d = dimensionality. The total number of states 2 in volume I/k(d) in k-space is

,

(7-25)

374


In a multivalley semiconductor, using 5 , for the valley degeneracy,

The energy-k relation is given by E = -h2(k:- + ” +k “2 2 m, my

k 2 ) =-h 2 k 2 m, 2m

for isotropic effective mass m. Therefore, the DOS per energy E to E+dEis d Z d Z IdE Q ( E )= - = - / dE d k / dk states/( V d *)energy) (7-26)

= 1.587 x

10l1( i ) ( S ) / ( c m ’ m e V )

for (100) Si z 2.8 x 1010/(cm2meV) for GaAs

In a one-dimensional system

For example, in a three-dimensional (3 D) system, a free-electron-like gas has spin

dZ 8nk2 dk ( 2 ~ ) ~ dE h 2 k dk m (2 m E)” h 21Zm32 E12 e 3 D (E) = h3

k

4 dZ _ dk 5 (7-29)

=

(7-27)

In 3D, the DOS is proportional to the square root of energy. In a two-dimensional (2 D) system,

E

h2 kfi =Eo + A 2mll

nzI - -m l (7-28) h2 k x h2 The DOS is independent of energy. ~

In a zero-dimensional (OD) system, the DOS becomes a delta function located at each quantized state. The DOSs of 3D, 2D, 1 D, and OD systems are shown in Fig. 7-36. Realizations of a 2 DEG or 2 D H G in a Si system have been shown previously. However, a quantum-wire-channel MOSFET, shown in Fig. 7-37a, has also been fabricated (Takeda et al., 1990). There are two gates, the first and the second, fabricated by electron-beam lithography. Their widths were both varied from 0.1 pm to 1.0 pm. The channel length from source to drain is approximately 2 km. The second gate, which has a 10 nm gate oxide, creates the narrow conducting channel. In Fig. 7-37 b, the transconductance g,( = aZ,,/aV,,) is found to show oscillatory behavior and negative differential resistance, which implies a resonant transport.

375

7.4 Quantum-Effect Devices FIRST GATE

Q2D

t

I

4 i = l

QUANTUM WELL

2

E,Ei

3

I

I

VS G

-3

v

-4 v -5v

L

QUANTUM DOT

(d

1

6

J

4.2 K

E, Ei

Figure 7-36. Density of states in (a) 3 D, (b) 2 D, (c) 1 D, and (d) OD systems.

Figure 7-37. Quantum wire channel MOSFET: (a) device structure; (b) transconductance oscillation in narrow Si inversion layers.

The quantum-dot structure can be fabricated by the following process steps. As shown in Fig. 7-38, thin layers of Si and GeSi are deposited on a Si substrate by MBE or a UHVjCVD process. After a mesa etching, an SiO, layer can be formed by a low-temperature oxidation step such as high-pressure oxidation (HIPOX) or plasma-enhanced chemical vapor deposition (PEVCD). Finally, a narrow metal gate strip is formed on the top oxide. If the dimensions L,, L,, L, are smaller than the

de Broglie wavelength (about 200 8, at 300 K), a quantum dot is formed.

7.4.3 Resonant-Tunneling Diode The quantized states in a double-barrier quantum well (DBQW) are shown at the left in Fig. 7-39. The resonant phenomenon is analogous to the resonant transmission of light through a Fabry-Perot etalon. In DBQW, an electron wave behaves like a light wave.

376


Figure 7-38. Structure of a quantum dot.

(QUANTUM W I R E S )

Consider an electron at energy E incident on the one-dimensional DBQW structure. When E matches one of the energy levels Ei in the QW, the amplitude of the electron de Broglie waves in the QW increases due to multiple scattering, and the waves leaking in both directions cancel the reflected waves and enhance the transmitted ones. Near resonance one has (Luryi, 1990) T ( E )%

.,2 4 TI T2 (7-1 TZ)’ ( E - E;)’

+

+ ;”

(7-30)

where Tl and T, are the transmission coefficients of the two barriers at the energy E = Ei and 7 z A/? is the lifetime width of the resonant state [quasi-classically, 7 z Ei

li

7

(Tl = T2)].In the absence of scattering, a system of two identical barriers ( Tl = T2)is completely transparent to electrons entering at resonant energies and the transmission coefficients, plotted against the incident energy, have a number of sharp peaks, as shown at the right in Fig. 7-39 b. A GeSi/Si double-barrier resonant-tunneling diode (DBRTD) was fabricated (Rhee et al., 1988). Figure 7-40a shows the energy barrier diagram in the valence band. Figure 7-40b is the current-voltage characteristic ( I - V ) in which a resonant tunneling peak can be clearly observed around 300 meV at both 4.2 K and 77 K. The peak is due to the transmission through the light-hole ground state Elhl (higher energy not shown).

0.8 0.6

0.4 w

z Y

El

c ---jp

0

t -I+

1

1ooA

SI

t w

L : - y 5 + ) * 2

GerSi1.x

SI

10-4

10-8

TRANSMISSION COEFFICIENT

5? u

z

Figure 7-39. Double-barrier resonant-tunneling diode (DBRID): (a) quantized states in the well; (b) transmission coefficient vs. energy E (after Luryi, 1990).

7 . 4 Quantum-Effect Devices

377

index confinement region that permits effective waveguiding in the silicon overlayer. A silicon ridge was used as the waveguide. A multiple quantum well (MQW)layer was imbedded in a p-i-n structure as shown in Fig. 7-41 a. The 40 8, Si,,,Ge,~,/210 8, Si, 28-period layer is equivalent to an average Ge composition of 10%. The response of the detector as a function of wavelength at 10 V reverse bias and at room temperature is shown in Fig. 7-41 b. A 50% internal quantum eficiency was obtained at 1.1 pm wavelength with an impulse response time of 100 ps (Kesan et al., 1990).

-U E

7.4.5 Resonant-Tunneling Hot-Electron Transistor V

n

DC VOLTAGE (mV)

(b) Figure 7-40. (a) Schematic band diagram of the double-barrier diode. For the structure used in this experiment, W, = W, = 50 A, W, = 40 A, and x = 0.4. (b) Observed current -voltage characteristics for the structure at three different temperatures (after Rhee et al., 1988).

The heavy-hole ground state Ehht can only be seen by dI/dV or d2Z/dV2 measurement because of the large tunneling effective mass. At higher bias a second peak occurred at 900meV in the dZ/dV measurement due to the first excited heavyhole state Ehhl(Rhee et al., 1988).

7.4.4 Multiple Quantum Well Detector The Si-Ge heterostructure makes the realization of a Si-based 1.3 pm long wavelength optoelectronic detector possible. Silicon-on-insulator (SOI) structures are used. The buried-oxide layer forms a low-

When a double-barrier resonant-tunneling diode (DBRTD) is imbedded in a structure, as in p + (Ge,,,Si,,,)-DBRTDP+ (Ge0.5Sio.A base-i (Ge,,,Si,, 8)p + (Geo.,Si0,,), a hot-electron transistor (HET) is formed. The HET exhibits negative differential resistance (NDR) in its current-voltage (I- V) characteristics (Rhee et al., 1989). Because of its high-speed tunneling capability and negative differential resistance, integration of such a device into Si-based circuits could find applications in high-speed digital circuits, frequency multipliers, multistate logic circuits and tunable oscillator/ amplifiers. The HET samples were grown on highly doped p-type (lO0)Si substrates in a Si MBE chamber. Detailed procedures for sample cleaning and growth can be found elsewhere (Rhee et al., 1990). Figure 7-42a shows the structure of the resonant-tunneling hot-electron transistor. A double-barrier structure, which consists of two 50 8, Si layers separated by a 43 8, Ge,,,Si,,, quantum well, is used as an emitter. A 1.2 pm Ge,,,Si,,, buffer layer acts as a collec-

378


I

UNDOPED Ge.2Si.g 100 nrn

P'-

n

Ge.4Si.s

1200 nm

COLLECTOR

DETECTOR RESPONSE ( LIGHT WAVEGUIDE) - l O V BIAS

--:: 50

n

I

VBC ( m V )

Figure 7-41. (a) Schematic view of a photodetector consisting of an M Q W absorber integrated into a rib waveguide--P--i - N structure showing both device geometry and epitaxial layer structure. (b) Internal quantum efficiency vs. well length for the structure in ( a ) (after Kesan et al.. 1990).

Figure 7-42. The resonant-tunneling hot-electron transistor: (a) cross-sectional view of the GeSi resonant-tunneling hot-hole transistor. (b) Schematic band diagram of the transistor under bias when resonant tunneling occurs through the light-hole ground state in the quantum well. (c) 1 V characteristics (after Rhee et al., 1989).


tor and the collector barrier consists of a 1000 8, Ge,,,Si,,, layer. A 1000 8, Ge,.,Si,,, base is inserted between the double-barrier quantum-well emitter and the collector barrier. The doping concentration is about 1 x lo1, cm-3 throughout the device except for the collector barrier and the double-barrier resonant-tunneling structure, which are undoped. Substrate temperature was held at about 530 "C during the growth. The emitter and base contacts were obtained using selective wet etching and standard photolithographic techniques. The valence-band offsets and boundstate energy of the light-hole ground state in the quantum well is shown schematically in Fig. 7-42 b. For convenience, the hole energy was taken to be positive. All the values are given with reference to the valence-band edge of the unstrained Ge,,,Si,,, layers. The collector barrier and the resonant-tunneling double barriers in the emitter are subjected to an in-plane tensile strain that causes the heavy-hole band edge to be above the light-hole band edge. In the base, the heavy-hole band edge is below the light-hole band edge due to the compressive strain. In the unstrained Ge,,,Si,., layers, the light-hole and heavyhole bands are degenerate. The light and heavy holes moving from the collector to the base have to overcome 106 meV and 155 meV barriers, respectively. On the other hand, the light and heavy holes see barrier heights of 137 meV and 208 meV, respectively, from the base to the collector. Due to the degenerate light- and heavyhole bands in the collector, the majority of the current from the collector to the base is from light holes because of the lower lighthole barrier height. The effective barrier height from the collector to the base is 106 meV as seen by the light hole and 208 meV from the base to

379

the collector as seen by the heavy hole. An asymmetric I - V characteristic between the base and the collector is evident as a result of the unequal barrier heights. In the double-barrier quantum-well emitter, the barrier heights for the light and heavy holes are 211 meV and 315 meV, respectively. There are three bound states for the heavy hole and one bound state for the light hole in the quantum well. The negative differential resistance of the device is due to the light-hole tunneling through the light-hole ground state located 61 meV from the bottom of the well. Figure 7-42 b shows the band diagram under an external bias. When the emitter is biased positively with respect to the base, holes are injected into the base through the double-barrier resonant-tunneling emitter with an excess hole energy relative to the valence-band maximum of the Ge,,,Si,,, base. The holes injected into the base are then transported near-ballistically to the collector. The 1000 8, Ge,,,Si,,, collector barrier prevents injection of the holes initiated from the valence band of the base to the collector when VB, is applied, but allows transport of the injected hot holes from the emitter to the collector if the hot holes have higher energies than the collector barrier height. In Fig. 7-42c, a set of collector currents (I,) is shown as a function of the base-collector voltage (V,,) at 77 K, with VEB as a parameter. The rightmost curve corresponds to V,, = 0 and the others are obtained for an incremental step of 0.2 V. At VEB= 0, no negative differential resistance (NDR) is observed because a large portion of the collector current comes from the base. As the emitter bias is increased, the injection current from the emitter becomes the dominant source of the collector current and he NDR increases with VEB.

380


7.5 Microwave and Photonic Diodes

ity of Si-based optical sources (Luryi and Sze, 1987). 7.5.1 IMPATT Diode

The most important Si microwave diodes are the IMPATT diode and the BARITT diode. They provide high-power, hight-efficiency, or low-noise operations from 1 GHz to the millimeter-wave band. Although Si tunnel diodes have been made, the device performance is inferior to that of GaAs tunnel diodes due to Si's relatively large effective mass for tunneling. There is no Si transferred-electron diode, because the satellite valley in the Si conduction band is located 1.1 eV above the bottom of the conduction band, too high for intervalley transfer of electrons. Si photonic devices include the Si photodetectors, which detect optical signals through electronic processes, and Si solar cells, which furnish the power for satellites and space vehicles as well as for terrestrial applications. No Si optical sources have been developed yet, because Si has an indirect bandgap. It is conceivable, however, that certain Si-based materials may have direct bandgaps, thus opening the possibil-

N

[-x

N, 0

b

N

0

W

2

The IMPATT (impact ionization avalanche transit time) diode is one of the most powerful solid state sources of microwave power. It can generate the highest CW (continuous wave) power at millimeter-wave frequencies, and is used most extensively in that frequency range (30 to 300 GHz). Si IMPATT diodes are superior to GaAs IMPATT diodes in the millimeterwave frequency range because Si has a smaller energy relaxation time, which results in faster response to impact ionization when an electric field is applied. In addition, Si has a higher thermal conductivity for better heat dissipation. The basic members of the IMPATT diode family are the single-drift devices and the double-drift devices. Figure 7-43 shows the single-drift IMPATT diodes in which only one type of charge carriers (ie., electrons) traverses the drift region. Figure 7-43a shows the doping profile and electric field distribution at the avalanche

1-

b n : 2

o b

W

w

E

em^^^,,^ Em\".k: i:(; x,

Q

XA

W

(a)

~~

0 XA

w

(b)

--c

0 XA

w

(C)

X

Figure 7-43. Doping profiles and electric-field distributions at the avalanche breakdown condition of three singledrift IMPATT diodes: (a) one-sided abrupt p-n junction, (b) hi- lo structure, and (c) lo-hi-lo structure (after Sze, 1990).

7.5 Microwave and Photonic Diodes

38 1

N. E

),,//IV

f

; /

0

W (C)

X

’ NA

\

0

W

X

Figure 7-44. Doping profiles and electricfield distribution of four double-drift IMPATT diodes: (a) flat profile, (b) hi-lo structure, (c) lo-hi-lo structure, and (d) hybrid structure (after Sze, 1990).

(d)

breakdown condition of a one-sided abrupt p -n junction. The avalanche multiplication process occurs in a narrow region near the highest field between 0 and x. Figure 7-43 b shows a hi-lo structure in which a high doping Nl region is followed by a lower doping N2 region. With proper choice of the doping Nl and its thickness b, the avalanche region can be confined within the Nl region. Figure 7-43c is the lo-hi-lo structure, in which a “clump” of donor atoms is located at x = b. Since a nearly uniform high-field region exists from x = 0 to x = b, the avalanche region is equal to b, and the maximum field can be much lower than that for the hi-lo structure. Figure 7-44 shows double-drift devices in which both electrons and holes participate in device operation over two separate drift regions. The double-drift devices have higher efficiency and higher output power than single-drift devices. Figure 7-44 a illustrates the doping profile and electricfield distribution of a two-sided abrupt p-n junction. The avalanche region is located near the center of the depletion layer. Fig-

ure 7-44 b shows a double-drift hi-lo structure that consists of a lo-hi structure on the p-side and a hi-lo structure on the n-side. Figure 7-44 c shows a double-drift lo-hi-lo structure, the avalanche region is given by the distance between the p + clump and the n + clump. Figure 7-44d shows the double-drift hybrid structure in which the p side has a flat doping profile but the n side has a hi-lo profile. The selection of a particular device structure depends on many factors, such as the operating frequency, the CD-to-AC conversion efficiency, power output, and ease of fabrication. The double-drift lo-hilo structure (Fig. 7-44c) is expected to have the highest efficiency, but it is also the most difficult to fabricate. The double-drift hybrid structure (Fig. 7-44d) is a good compromise, since it has good efficiency and is relatively easy to make. Of course, the simplest structure is the single-drift p-n junction (Fig. 7-43 a). For lower-frequency operation, Si IMPATT diodes are fabricated using diffusion, chemical vapor deposition, or ion implantation processes to form the n-type

382


and p-type layers. At higher frequencies, especially in the millimeter-wave region, the layer thickness becomes very small. At these frequencies, we must use molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD) to control the doping and layer thickness precisely. State-of-the-art Si IMPATT diodes have CW power output of about 10 W at 10 GHz, 1 W at 100 GHz, and about 0.1 W at 200 GHz. The conversion efficiency is a constant value of 15% up to 100GHz, then it decreases to 1 % at 200 GHz (Sze, 1990).

7.5.2 BARITT Diode The BARITT (barrier injection transit time) diode is also capable of operating in the millimeter-wave frequency region with substantially lower noise, but also with lower power output than the IMPATT diode. BARITT diodes are particularly useful for applications in self-mixing oscillators where the minimum detectable signal power level can be 30 dB below that of IMPATT diodes. The BARITT diode is basically a backto-back pair of p-n junctions or metalsemiconductor diodes biased into a reachthrough condition. Figure 7-45 a shows a Si p+-n-p+ structure. When a voltage is applied to the device, one junction is forward biased and the other is reverse biased. When the voltage is above the reachthrough condition, the BARITT diode has the electric field profile shown in Fig. 7-45 b. The point x R corresponds to the potential maximum for minority-carrier (holes in this case) injection; the point x, separates the low-field drift region from the saturation-velocity drift region as shown in Fig. 7-45c.

+

-

n

W

0

ELECTRIC FIELD

A

INJECTION REGION

DRIFT REGION

--I

(b) DRIFT VELOCITY

t u

s

0 LOW- F IE LD REGION

t

-

r

X R XS

--I

SATURATED +VELOCITY REGION

*

i

W

X

4

(C)

Figure 7-45. Device cross section, field distribution, and carrier drift velocity of a BARITT diode (after Sze, 1990).

State-of-the-art Si BARITT diodes have CW power output of 100 mW at 10 GHz, and about 1 mW at 60 GHz. Typical efficiencies are in the range of 0.5 to 2 % (Sze, 1990).

7.5.3 Photodetectors Si photodetectors include the p-i-n photodiode and the avalanche photodiode (e.g., hi-lo or lo-hi-lo structures similar to those shown in Fig. 7-43 b and c). The conventional Si photodetectors are useful in the wavelength range from 0.6 to 0.9 pm, where nearly 100% quantum efficiency (i.e., number of electron-hole pairs generated per incident photon) has been ob-

7.5 Microwave a n d Photonic Diodes

tained from devices with antireflection coatings (Sze, 1981). Recently, many novel Si photodetectors have been designed exhibiting excellent photoresponse from the near-ultraviolet to the far-infrared region In addition, heteroepitaxial technology has been used to form Si-based, monolithic optoelectronic integrated circuits that combine 111-V compound photodetectors and MESFET with Si integrated circuits on a Si substrate. Figure 7-46 a shows a cross-sectional view of a single pixel of a 160 x 244-element focal plane array in which a frontilluminated PtSi Schottky-barrier photodetector is connected with a charge-coupled device (CCD). The photodetector is fabricated on a p-type (100) Si wafer using electron-beam evaporation to deposit a

383

10 8, thick Pt film in an ultrahigh vacuum system and subsequent annealing in situ at 400 "C to form a 20 8, PtSi (the barrier height of PtSi/p-Si is 0.18 eV). An n-type guard ring surrounding the periphery of the silicide is utilized to suppress edge leakage. Electrons generated by illumination are accumulated on the PtSi electrode and are subsequently transferred to the CCD channel. The quantum efficiency, as a function of wavelength, of a photodetector reversebiased to 5 0 V and at 50K is shown in Fig. 7-46 b. For wavelengths 2 1 pm, corresponding to photon energies below the bandgap of Si, the photodetector response is produced by carriers generated by absorption of light in the PtSi film. The quantum efficiency is 3% at 1.5 pm and de-

uv CCD TRANSFER GATE

GUARD RING

BURIED CCD CHANNEL

(a)

-

100 10

u Z

w

u

1

L LL

w

I

0.1

3

t-

Z

Q

0.01

3

5

0.001

I

0

I

1

I

I

I

I

2 3 4 5 WAVELENGTH (urn 1

(b)

I

6

I

7

Figure 7-46. (a) Schematic diagram of a single pixel of a 160 x 244-element PtSi focal-plane array operated in the frontillumination mode. (b) Quantum e n ciency as a function of wavelength (after Tsaur et al., 1990).

384

7 Silicon D e v i c e Structures

creases to 0.01% at 6.3 pm. For shorter wavelengths, the quantum efficiency increases drastically, because the radiation can transmit through the 20A PtSi film and is absorbed by the Si substrate to generate carriers that contribute to the photoresponse. The quantum efficiency is 60% at 0.8 pm, remains essentially constant down to 0.4 pm, and then decreases to 35% at 0.3 pm. Using this photodetector and CCD readout circuitry, very large, highly uniform focal-plane arrays have been demonstrated. Such an array is useful for remote sensing and imaging applications (Tsaur et al., 1990). A Ge,Si -./Si heterojunction internal photoemission detector has been investigated. This Si-based far-infrared photodetector has a quantum efficiency of 3 - 5 % in the 8- 12 pm region. Figure 7-47 a shows the structure of a p+-GeSi/p-Si detector. The device is fabricated on a p-type (100) Si substrate. The p'-GeSi layer is grown in a MBE system with a base pressure of 3 x lo-" Torr. The substrate is heated to 500-600°C and Ge and Si are coevaporated from two electron-gun sources. The GeSi layer thickness ranges from 100 to 4000 A, the Ge composition ranges from 0.2 to 0.4, and the boron doping concentration ranges from i o i 9 to 4 x lozocm-3. The energy band diagram is shown in Fig. 7-47 b. Infrared radiation is absorbed in the p +-GeSi layer, the photoexcited holes are emitted over the GeSi/Si heterojunction barrier into the Si by internal photoemission. Strong infrared absorption is achieved in the p t GeSi layer due to free carrier absorption and intra-valence-band transitions. The heterojunction band alignment for the GeSi/Si system is essentially of type 111, that is, most of the band-edge difference appears at the valence band. By decreasing the Ge composition, we can reduce the valence band offsets AEv, which,

AI

G - e-5-i

i02

I

L

(a) Si GeSi VALENCE BAND ,jD IS CONT I NU I T Y

AB so R I N G LAYER

.mp

..................

00

-

PHOTO-EXC IT ED HOLES

(b)

::

-

400A

40008

-10' >. V

Z

LL LL

lo-' r

f 0

2

4

6

8 1 0 1 2

WAVELENGTH ( p m )

(C)

Figure 7-47. Device structure of a p+-GeSi/p-Si photodetector. (b) Energy band diagram of the photodetector. (c) Quantum efficiency of two GeSi/Si photodetectors as a function of wavelength (after Lin and Maseyian, 1990).

in turn, reduces the heterojunction barrier q # B given by qdB= AEv - (E,, - E ) (in eV) (7-31) The cutoff wavelength iC [1.24/(q #B)] will therefore increase. Figure 7-47c shows the quantum efficiencies of two GeSi/Si photodetectors as a function of wavelength. For both detec-

7.5 Microwave a n d Photonic D i o d e s

tors, the GeSi layers have the same Ge content of 0.3 and the same total quantity of boron, but for detector A, the layer thickness is 400 A, and for detector B, the layer is 10 times thicker. The thinner layer of detector A allows more photoexcited holes to reach the interface before undergoing inelastic scattering, resulting in higher quantum efficiency. In addition, the higher doping concentration of detector A reduces the effective potential barrier because its Fermi level moves further below the valence band, and thus extends the photoresponse to 10 pm. By optimizing the thickness, composition, and doping concentration of the GeSi layer, significantly improved quantum efficiencies are expected (Lin and Maseyian, 1990). Another Si-based photodetector is the InGaAs/InP detector for the 0.9- 1.7 pm wavelength. The detector is fabricated on a Si substrate by a heteroepitaxial process. This approach allows monolithic integration of photonic and electronic devices on a single Si substrate. Figure 7-48 shows the cross section of the photodetector. A Si wafer (4" off (100) orientation) with a GaAs layer grown by the MOCVD process serves as the starting material. The hydride vapor-phase epitaxial technique is used to deposit seven 1 pmthick In,Ga, -,As layers with x ranging from 0.07 to 0.49 in equal steps to accommodate the 3.8% mismatch with GaAs. A final 5 pm thick Ino,53Gao.47As layer is

deposited to serve as the optical absorption layer, followed by a 1 pm thick InP layer, which serves as the high-bandgap passivation "window" layer. Planar p-i-n photodetectors with 75 pm diameter are then fabricated by conventional processes using Zn diffusion. For a reverse bias of 5 V, the quantum efficiency at 1.3 pm is 85% and the capacitance is 1.1 pF. The detectors have been life-tested at 125 "C and - 5 V. No increase in room temperature dark current has been observed after 2000 h, indicating that the detectors are quite reliable (Olsen, 1990). 7.5.4 Solar Cells

There have been dramatic increases in the Si solar cells' conversion efficiency in the past few years. Most of these increases have originated from improved cell structures and processing techniques, rather than improved Si quality. Figure 7-49a shows a schematic diagram of a passivated emitter and rear cell, which shows a high efficiency of 23.1 YOunder AM 1.5 spectrum (i,e., an air mass 1.5 condition with the sun at 45" above the horizon; these conditions are an energy-weighted average for terrestrial applications). We note that the cell structure is quite different from that of the conventional solar cell. The front side has an invertedpyramid surface texture to trap the incident light. A heavy n + diffusion under-

Si3Nq DIELECTRIC (0.10 urn) n- PASSIVATION LAYER(lnP-1.0~lrn) Zn DIFFUSION n-OPTICAL ABSORPTION LAYER (ln0.53Go0.47Ar-5.0~m) STEP GRADED REGION 7- 1 urn THICK- InxGol-x As LAYERS ( XI

n+ < l o o > S i SUBSTRATE

385

0.07-0.49)

n+- BUFFER LAYER (GaAs-2.01~rnI n-SEED LAYER (GoAs-6OAl

Figure 7-48. In,,,Ga,,,,As/ InP compositionally graded photodetector on a Si substrate (after Olsen, 1990).

386

7 Silicon Device Structures "I NVE RTED " PYRAMIDS

FINGER

REAR CONTACT

OXIDE

(a) METAL

INVERTED PYRAMIDS

(b)

Figure 7-49. (a) Schematic diagram of a passivated emitter and rear cell (after Green, 1990).(b) Schematic diagram of a solar cell with 26% efficiency at the 90 sun, AM 1.5 condition (after Cuevas et al., 1990).

neath the top metal contact helps to minimize series resistance and increase opencircuit voltage. The top surface oxide is 250 A thick, and a MgFJZnS double-layer antireflection coating (not shown) is applied. O n the bottom surface, a thermally grown oxide passivates most of the surface. Nonalloyed ohmic contact is made at isolated contact holes through the passivating oxide. In order to have a low contact resistance, relatively low-resistivity Si should be used (e.g., e = 0.2 R cm). The cell thus incorporates a highly reflective planar rear surface. The calculated reflectance of this layer is above 97% (Green, 1990). Figure 7-49 b shows a similar cell with efficieny of 21.7% at 1 sun (AM 1.5 condi-

tion) and 26% at 90 suns concentrated light, 25"C, AM 1.5 condition. The cell consists of an undoped (or moderately doped n-type) substrate with imbedded point p f and n + islands. The SiO, used to mask the boron and phosphorus diffusions passivates the undoped surface and also acts as an antireflection coating. The percentage of silicon area that is contacted is 1 YOfor the p + and 2 % for the n + materials. The metal grid is arranged in a chevron pattern that aligns on the triangular ridges (Cuevas et al., 1990). Progress has also been made on a polycrystalline Si solar cell. Efficiency as high as 17.8% has been obtained under a 1 sun AM 1.5 condition. A passivated-emitter solar cell is shown in Fig. 7-50. The cell incorporates two novel treatments. The first is the phosphorus pretreatment in which phosphorus is diffused into the polycrystalline silicon. The enhanced diffusion of phosphorus along the crystallographically poor regions (grain boundaries) converts areas which would otherwise be minority carrier sinks into useful collection regions. The second is the rear aluminum treatment. Aluminum, like phosphorus, is also found to exhibit enhanced diffusion D O U B L E LAYER AR COATING TOP CONTACT ( T i / P d / A g 1

'REAR CONTACT Figure 7-50. A passivated-emitter polysilicon solar cell with anti-reflection (AR) coating (after Narayanan et al., 1990).

387

7.6 Outlook

along grain boundaries. The aluminum treatment can increase both the open-circuit voltage and short-circuit current. These treatments in gettering the substrate and nullifying the deleterious effects of grain boundaries have improved the performance of the less expensive polysilicon solar cell to nearly match that of singlecrystal devices. Using a surface-texturing approach similar to that shown in Fig. 7-49 may further increase the efficiency (Narayanan et al., 1990).

7.6 Outlook As the technology of microelectronics advances, the feature size becomes smaller. Figure 7-51 shows that, in the year 2000, the MOSFET’s gate length may be reduced to 0.2 pm, gate-oxide thickness to 4nm, and junction depth to 0.04pm. Simultaneously, bipolar transistors that have a base width of 50 nm in 1990 may be reduced to 30 nm in the year 2000 by using a heterojunction GeSi approach. Consequently, cost and performance improvement will be tremendous. In 2000,256 Mbit (- 3 x lo8 components/chip) DRAM will be available with a gate delay of only 30 ps,

E

=L

Y

Table 7-1. Peformance projection. Year

Minimum feature length (P) Component density (devices/cm2) Gate delay (ns) Power-delay product (pJ) Wafer size (mm)

1960

1991

2000

25

0.7

0.2

1

500 loo00 25

8 x 1 0 6 0.03

0.1 0.01

200

0.03 0.0003 250

compared to 500 ns in 1960. Power-delay products will also profoundly improve from 10000 pJ in 1960 to 0.0003 pJ by the year 2000. These projections are summarized in Table 7-1. Figure 7-52 shows the evolution of circuit complexity versus year. MOSFET has the highest complexity. Bipolar still maintains its momentum but levels off after 1990. MESFETs and MODFETs are still in their development stage, however, their momenta are extremely high - high enough to challenge MOSFETs in the future. A combination of the high complexity of Si-based devices with the high-speed capability of GaAs devices will create new system applications for the future computer,

30 10

ul

rn W

z s 0 I c-

’

1oooA

0.1

1

0

I

z z 5

L

0.01

-1 ( - 1 3 % R E DI U C T I O N

0.004 1960

1970

PER I 1980

YEAR

1008 L.-O 8

1990

2000

Figure 7-51. Dimension scaling of MOSFETs and bipolar junction transistors vs. time.

388


~

VLSI

BIPOLAR .... TRANSISTOR MESFET

MODFET U

I

10'

...:

1

1960

I 1970

I 1980

I 1990

I

2000

2010

YEAR Figure 7-52. Evolution of VLSI circuit complexity.

communication, and high-quality entertainment equipment such as high-definition television (HDTV), which may use heteroepitaxy of GaAs on Si technology. O n the other hand, work on GeSi strained layers on Si is attracting a lot of attention. Using narrower bandgap GeSi material for the base of bipolar transistors makes the device speed competitive with that of heteroepitaxy of GaAs on Si. A commensurate GeSi layer on Si is much more suitable to realize the heterojunction bipolar transistor, which will have an extraordinary impact on both Si and GaAs technologies. In order to mass produce these devices beyond the year 2000, low-temperature process technologies are required. Otherwise, the diffusion of the constituent materials will seriously affect device performance, especially when the channel length of MOSFETs is reduced to 0.1 pm and the base width of bipolar transistors is reduced to 30nm. The growth of Si or GeSi epitaxially at a temperature lower than 550 "C has already been achieved (Meyerson, 1986). Deposition temperatures for poly-Si or poly-SiGe,

oxide, nitride, and even the annealing temperature should be lowered accordingly, preferrably to below 800 "C. Table 7-2 presents the possible low-temperature processes for future ultra-large-scale integration (ULSI). Therefore, there are callenges to many professionals including the physicist, chemist, materials scientist, and electronics and device engineer to work together towards solutions. Advances in Si technology such as Si micromachining have created many new applications, which include microvacuum and micro-electromechanical systems (Fan et al., 1989). New sensors, transducers, actuators, and even new kinds of field-emission devices such as field-emission displays (Spindt, 1989) and high-power distributed microwave vacuum triode arrays using field-emission types have been developed (Kosmahl, 1989). We anticipate that Sibased devices will remain the dominant semiconductor devices in the foreseeable future.

Table 7-2. Possible low temperature technologies for future ULSI circuits.

Feature

Technology"

Epitaxial or poly Si. UHVjCVD, MBE, LRP, SiGe LPCVD Oxides and interfaces Plasma treatment, UV ozone, Hipox Nitrides CVD-PECVD, photo-CVD, LPCVD, Metals (and silicates) Sputtering CVD Contacts Non-alloy, LT-EPI, with RTA Junctions TRP, RTA, LT-EPI Abbreviations: UHV, ultra-high vacuum; CVD, chemical vapor deposition; MBE, molecular beam epitaxy; LPR, limited reaction process; LPCVD, low pressure chemical vapor deposition; UV, ultraviolet; HIPOX, high-pressure oxidation; PECVD, plasma-enhanced chemical vapor deposition; LT, low temperature; EPI, epitaxy; RTA, rapid thermal annealing; RTP, rapid thermal processing.

7.8 References

7.7 Acknowledgements This Chapter is dedicated to the memory of Mrs. Cheng-Hwei Wu Chang, C. Y. Chang's wife, who passed away during our writing of the manuscript. We wish to thank Mr. N. Erdos who did the technical editing of the Chapter, Ms. B. L. Huang who typed the initial draft and the final manuscript, and Mr. T. Z. Jung who furnished the technical illustrations.

7.8 References Allyn, C. L., Gossard, A. C., Bethea, C. G., Levine, B. E (1980), Appl. Phys. Lett. 36, 373. Aoki, M., Ishii, T., Yashimura, T. (1990), IEEE Int. Electron Device Mtg. Tech. Digest, pp. 939-941. Bean, J. C. (1978), Appl. Phys. Lett. 33, 654. Brews, J. R. (1990), in: High Speed Semiconductor Devices: Sze, S . M. (Ed.). New York: Wiley, pp. 139-210. Chang, C. Y, Luryi, S., Sze, S. M. (1986), IEEE Electron Device Lett. 7, 497. Chen, T. C., Toh, K. Y., Cressler, J. D. (1989), IEEE Electron Device Lett. 10, 344. Chiu, T. Y., Chin, G. M., Lan, M. Y (1991), IEEE Trans. Electron Devices 38, 141. Cuevas, A., Sinton, R. A., Midkiff, N. E. (1990), IEEE Electron Device Lett. 11, 6. Daembkes, H., Herzog, H. J., Jorke, H. (1986), IEEE Trans. Electron Devices 33, 633. Ea, J. Y (1990), IEEE Electron Device Lett. 11, 403. Fan, L. S . , Tai, Y. C., Muller, R. S. (1989), IEEE Trans. Electron Devices 35, 724. Fowler, A. B., Fang, E F., Howard, W. E., Stiles, P. J. (1966), Phys. Rev. Lett. 16, 901. Garone, P. M., Venkataraman, V., Sturm, J. C. (1990), IEEE Int. Electron Device Mtg Tech. Digest, pp. 383-386, 587-590. Gennser, U., Kesan, V. P., Iyer, S. S., Bucelot, T. J., Yang, E. S. (1990), .I Vac. Sci. Tech. B8, 210. Gibbons, J. F., Gronet, C. M., Williams, K. E. (1985), Appl. Phys. Lett. 47, 721. Grabbe, E. E, Patton, G. L., Stork, J. (1990), IEDM 17. Green, M. A. (1990), IEEE Trans. Electron Devices 37, 331. Grinberg, A. A., Luryi, S. (1981), Appl. Phys. Lett. 38, 810.

389

Holg, B. (1990), IEEE Trans. Electron Devices 37, 2230. Holland, C. E., Rosengreen, A., Spindt, C. A. (1990), IEEE Int. Electron Device Mtg. Tech. Digest, pp, 977-982. Jwo, S. C., Chang, C. Y (1986), IEEE Electron Device Lett. 7 , 689. Kasper, E. C., Bean, J. C. (1989), Silicon Molecular Beam Epitaxy. Boca Raton, FL: CRC Press, Chaps. 2, 4. Kazarinov, R. E, Luryi, S. (1982), Appl. Phys. A 38, 15. Kesan, V. P., May, P. G., Bassous, E., Iyer, S. S. (1990), IEDM. Kosmahl, H. G. (1989), IEEE Trans. Electron Devices 36, 2728. Laska, T., Miller, G. (1990), IEDM, 807. Lattes, A. L., Munroe, S. C., Seaver, M. M. (1991), IEEE Electron Device Lett. 12. 104. Libsch, E R., White M. H. (1990), Solid-State Electron 33, 105. Lin, T. L., Maseyian, J. (1990), Appl. Phys. Lett. 57, 1422. Liu, H. C., Landhear, M., Buchanan, M., Hougton, D. C. (1988), Appl. Phys. Lett. 52, 1809. Luryi, S. (1985), Physica 134B, 466. Luryi, S., (1990), in: High Speed Semiconductor Devices; Sze, S. M. (Ed.). New York: Wiley. Luryi, S., Sze, S. M. (1987), in: Silicon Molecular Beam Epitaxy: Kasper, E., Bean, J. C. (Eds.). CRC Uniscience, pp. 251 -288. Malik, R. J., Aucoin, T. R., Board, K., Wood, C. E. C., Eastman, L. E (1980), Electron. Lett. f0,836. Meindl, J. D. (1984), IEEE Trans. Electron Devices 31, 1555. Meyerson, B. S. (1986), Appl. Phys. Lett. 48, 797. Meyerson, B. S., et al. (1990), IEEE Int. Electron. Device Mtg. Tech. Digest. p. 21. Murakami, E. (1991), IEEE Electron Device Lett. 12, 71. Narayanan, S . , Wenham, S. R., Green, M . A. (1990), IEEE Trans. Electron Devices 37, 382. Okazaki, Y., Kobayashi, T., Miyake, M. ( I 990), IEEE Electron Device Lett. 11 ( 4 ) , 134. Olsen, G. H. (1990), IEEE Int. Electron. Device Mtg. Tech. Digest, pp. 145-147. Pearce, C. W. (1988), in: VLSI Technology: Sze, S. M. (Ed.). New York: McGraw-Hill, pp. 9-45. People, R (1985), Appl. Phys. Lett. 47, 322. People, R., Bean, J. C. (1986), Appl. Phys. Lett. 48, 538. Pepper, M. (1990), in: Proc. Int. Electron Devices Symp., EDMS '90. Hsinchu, Taiwan, R.O.C.: NCTU, p. 465. Rajakarunanayak, Y. (1989), Appl. Phys. Lett. 55, 1537. Rathman, D. D., Niblack, W. K. (1988), I E E E M T T S Intl. Microwave Symp. Digest, Vol. 1. Piscataway, NJ: IEEE, pp. 537-540.

390


Rhee. S. S., Park. J. S.. Karunasiri, R. P. G., Ye, Q., Wang. K . L. (1988). Appl. Phj,s. Lett. 53,204. Rhee. S. S.. Chang. G. K.. Carns. T. K., Wang, K. L. (1989). Int. Electron Deyice Mtg., p. 651. Rhee. S. S.. Chang. G. K.. Carns, T. K.. Wang, K. L. (1990). Appl. P/i.rs. Lett. 56. 1061. Shahidi. G.. Davari. B.. Taur. Y., Warnock, J. (1990), in: Proc. IEEE bit. Electron. Device Mtg. Shichijo. H.. Matyi. R. J.. Taddiken, A . H. (1988), IEEE Inrl. Electron Device Mtg. Tech. Digest, pp. 778 - 781. Smith, C. G., Pepper. M . (1989), J. Phys. Condens. Matter 1 , 9035. Spindt. C. A . (1989). IEEE Trans. Electron Devices 36, 225. Suzuki. K.. Najafi. K.. Wise, K . D. (1990). IEEE Truns. Electron. Deviws 37, 1852. Sze, S. M. (1981). Ph,rsics of Semiconductor Devices, 2nd ed.. New York: Wiley. Sze. S . M. (1985). Semiconductor Devices: Ph,rsics and Technologj~.New York: Wiley. Sze, S . M. (Ed.) (1990), High Speed Semiconductor Devices. New York: Wiley. p. 425, pp, 521-585. Sze. S. M . (Ed.) (1991). Semiconductor Devices: Pioneering Papers. Singapore: World Scientific. Sze. S . M.. Gibbons. G. (1966). Solid-State Electron, 9 , 831.

Taft. R. E., Plumer, J. D., Iyer, S. S. (1989), Int. Electron Dei'ice Mtg., p. 55. Takeda. E. (1990), IEEE Int. Electron. Device Mtg. Tech. Digest, p. 389. Tsaur. B. Y.. Chen, C . K., Mattia, J. P. (1990), IEEE Electron Dei,ice Lett. 11, 162. Turner,G. W.(1988). Proc. Mat. Res. Soc.Symp. 116. 179. Yamauchi. N., Hajjar, J. J., Reif, R. (1991), IEEE Truns. Electron Devices 38, 55. Yang. E. S. (1988), in: Microelectronic Devices. New York: McGraw-Hill.

General Reading Sze, S. M. (1981). Physics of Semiconductor Devices, 2nd ed. New York: Wiley Sze, S. M. (1985), Semiconductor Devices: Physics and Technology. New York: Wiley. Sze, S. M. (Ed.) (1990), High Speed Semiconductor Devices. New York: Wiley, p. 425, pp. 521-585. Sze, S. M. (Ed.) (1991), Semiconductor Devices: Pioneering Papers. Singapore: World Scientific. Yang, E. S. (1988), Microelectronic Devices. New York: McGraw-Hill.

8 Compound Semiconductor Device Structures William E. Stanchina and Juan E Lam Hughes Research Laboratories. Malibu. CA. U.S.A.

List of 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.5 8.6 8.6.1 8.6.2 8.6.3 8.7

Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key Material Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Group 111-V Materials Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Field-Effect Transistors (FETs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metal-Semiconductor FETs (MESFETs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Heterostructure FETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Electron Mobility Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Heterojunction Bipolar Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Novel Semiconductor Laser Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Cascade Semiconductor Laser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Blue-Green Semiconductor Diode Laser . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

392 394 394 396 397 398 400 400 402 404 404 405 405 406

392

8 Compound Semiconductor Device Structures

List of Symbols and Abbreviations channel depth baseicollector junction capacitance drain-to-channel capacitance drain-to-gate capacitance drain-to-source capacitance emitter/base junction capacitance gate-to-source capacitance electron/minority carrier diffusion coefficient band gap energy difference between band gaps difference in valence band energies frequency unity gain cutoff frequency; current gain-bandwidth product minimum noise figure transconductance current drain current channel electron current saturated drain current collector current density Boltzmann constant position in Brillouin zone gate length heavy-hole mass free-electron mass electron mass in r valley n-type doping concentration n-type doping concentration in HBT emitter effective density of states in the conduction band doping concentration in channel sheet charge in 2-DEG effective density of states in the valence band pressure p-type doping concentration in the narrow band gap base electronic charge collector resistance drain resistance emitter resistance gate resistance intrinsic resistance source resistance drain-to-source resistance temperature


V VP us

vb e VdS, VDS

VGS vnb

‘pe

W

wb

K Pmax

r

E EO

Pn ‘b ‘C ‘CC

‘e, ‘e,

BJT CW

2-DEG FET HB HBT HEMT HFET HIGFET IC JFET LEC LED LPE MBE MESFET M MIC MODFET MOVPE PHEMT rf SISFET

voltage pinch-off voltage saturated free carrier velocity base-to-emi tter voltage drain-to-source bias gate-to-source bias electron velocity across the base hole velocity across the emitter width of the channel base width space charge width in the collector maximum common emitter current gain center of Brillouin zone dielectric constant permittivity of free space free carrier mobility in the channel base transit time collector transit time collector charging time emitter-to-collector transit time emitter charging time bipolar junction transistor continuous wave two-dimensional electron gas field-effect transistor horizontal Bridgman heterojunction bipolar transistor high electron mobility transistor heterostructure FET heterostructure insulated gate FET integrated circuit junction field-effect transistor liquid encapsulated Czochralski light emitting diode liquid phase epitaxy molecular beam epitaxy metal-semiconductor field-effect transistor monolithic microwave-integrated circuit modulation-doped FET metal-organic vapor phase epitaxy pseudomorphic HEMT radiofrequency heterostructure FET

393

394


8.1 Introduction The vision of a 21st century society based on an information superhighway infrastructure is synergistic with an extensive, worldwide R&D effort in optoelectronic devices and systems. The future needs of commercial and military services for real-time access to information at a high data rate ( > 10 Gbs- ’) have pushed the semiconductor technology frontier towards devices that can accommodate faster and faster processing rates without deterioration of the quality and quantity of information. In view of the timeliness of this research and technology upsurge, this chapter provides a description of up-todate optoelectronic and electronic devices which may be of practical interest to researchers and engineers in the fields of optical communication, satellite communication, wireless communication, and information systems. Due to the limited scope of this review article, we will concentrate on some of the most recent developments in the field at the expense of other equally important contributions in optoelectronics and semiconductor technology. Compound semiconductors, while covering a very broad range of binary, ternary, and quaternary materials, will be limited in this discussion to the group III-V semiconducting compounds. These refer more specifically, and for the most part, to GaAs and InP and those compounds that can be grown on these binary semiconductor substrates. Compound semiconductor device structures developed to date have generally been intended for application in very high speed electronic systems (taking advantage of the superior electronic transport properties of III-V semiconductors over Si) and in optical or optoelectronic systems (taking advantage of the direct band gaps of these

semiconductors over a wavelength range of 0.6-3.5 pm). These devices have begun to dispel the common notion among their detractors that “they are the materials of the future and always will be”. Probably the most ubiquitous of these is the AlGaAsIGaAs red light emitting diode (LED), which is widely used in displays; however, the semiconductor laser, currently being utilized in long haul fiber optic communication links, pump sources for solid-state lasers, and digital audio discs, is a close second. The GaAs metal-semiconductor field-effect transistor (MESFET) is also gaining acceptance through commercially built integrated circuits that act as improved performance replacement parts for selected Si integrated circuits (ICs), and they have long held a highly regarded position in hybrid and monolithic microwave integrated circuit applications. As these and other III-V devices build a history in terms of reliability and diminishing cost and new improved versions become available, III-V compound semiconductors will inevitably grow in use.

8.2 Key Material Properties Group III-V compound semiconductors have excellent transport and optical

properties, and they include a wide range of crystallographically lattice-matched and strained compounds which enable the development of improved and new device structures through “band gap engineering”. Many of these compounds are shown graphically in Fig. 8-1 in terms of their crystallographic lattice constant vs. the energy band gap. While only the binary compounds are labeled, ternary and quaternary compounds lie on the solid and dotted lines with compositions proportional to

395

8.2 Key Material Properties

Figure &1. Energy band gap vs. lattice constant for major 111-V compound semiconductors. Shaded vertical bands highlight groups of compound semiconductors with approximately the same lattice constant. 5.4

5.6

5.8 6.0 6.2 LATTICE CONSTANT (A)

6.4

their locations relative to the binary compounds terminating those line segments. The solid lines represent compounds with direct band gaps, while the dotted lines correspond to indirect band gap compositions. Shown in Table 8-1 is a selection of generally accepted physical constants for some of the more common direct band gap 111-V semiconductors. Not shown, but of equal importance, are the bulk resistivities in

6.6

excess of 1 x 10' a-cm for semi-insulating GaAs and InP substrates. This property has been a key factor in the rise of high speed 111-V ICs, since it enables devices to be electrically isolated from one another in a simple fashion and since it allows the substrate to serve as a dielectric for stripline waveguides at microwave frequencies. While each material's physical properties show distinctly advantageous features, 111-V devices can obtain enhanced perfor-

Table 8-1. Physical constants of group 111-V semiconductors. Properties

Units

GaAs

Al,,,Ga,,,As

InP

Gao,,,In,,,,As

Al~,481no,5zAsInAs

GaSb

~~~~

Energy gap (25 "C) Conduction band energy (T-L)difference Electron effective mass

eV eV

1.35

0.73

0.40

0.55

0.092

0.077

0.044

0.62

0.66

0.51

0.45

4.1

6.9

6

2.3

9.7

8.2

1.44 0.31

1.81

0.067

1.45

0.35

0.72

1.35 0.075

0.023

0.042

(mr /ma 1

Hole effective mass

0.32

(mhhim,)

Conduction band density of states Valence band density of states Electron saturation velocity at 100 kVcm-' (25 "Cj Peak electron velocity Electron mobility (25 "C) Hole mobility (25 "Cj Static dielectric constant Thermal conductivity

14 0.83

15 0.86

2.7

6.6

8500

3000

4500

12000

1500

33000

4ooo

450

100

150

450

75

400

650

12.6

Wcm-I K-'

1.1

3

2.2

6.6

0.46

11.8 0.70

12.4

14.6

0.26

15.7 0.35

396


mance by combining two or more of these semiconductor compounds in the same device. This has led to the technique of “band gap engineering” - the utilization of two or more semiconductor materials (having different energy band gaps) in the same structure to create new devices, enhance, or adjust the performance of existing device types. The interface between any two differing semiconductors is called a heterointerface (or heterojunction if the interface also includes a change in the doping type). These multilayers are then called heterostrucrures.

8.3 Group 111-V Materials Preparation Heterostructure devices are possible due to the development and refinement over the past 20 years of various epitaxial growth techniques, which include molecular beam epitaxy (MBE), metal-organic vapor phase epitaxy (MOVPE), and liquid phase epitaxy (LPE). Homojunction devices, too, are quite often grown by these epitaxial techniques with the most notable exception being the ion-implanted metal-semiconductor field-effect transistor (MESFET). Epitaxial growth involves the deposition of semiconductor constituent atoms on a smooth, single crystal substrate under conditions such that the deposited material nucleates, coalesces, and grows into a smooth, single crystal layer lattice matched to the substrate. Semi-insulating substrates are commonly grown as bulk ingots by the liquid encapsulated Czochralski (LEC), horizontal Bridgman (HB), or gradient freeze techniques (AuCoin and Savage, 1985). The ingots are sawed, lapped, and polished to form 50mm, 75mm, 100mm, or even

150 mm diameter wafers with a final thickness of 400-700 pm. Molecular beam epitaxy (MBE) (Arthur, 1968) is a growth technique in an < 10-l’ Torr ultra-high vacuum [Pbackground (1.33 x Nm-2)andPg,o,,, 1100“C) N-well/P-well drive-in process also acts as an effective denudation step, causing oxygen out-diffusion. Following the well drive-in process is usually the field oxide isolation process at intermediate temperatures between 900 “C and 1000“C. This will also induce oxygen precipitation and growth in the bulk of the wafer, thereby

41 6

9 Silicon Device Processing

activating the IG process. For some other CMOS device processing lines, process induced IG may not be sufficient, so enhanced process induced IG is required. By adding a 700°C SiO, nucleation anneal step after the well drive-in step prior to the field oxide isolation step, one can increase the precipitate density and SiO, precipitation rate during the field oxidation step. In this way, the IG effectiveness is improved, especially for the critical gate oxidation step.

9.2.2 Gettering by Hydrogen Annealing As the design rules of MOS ULSI shrink to the quarter micron range, high quality and high reliable ultra-thin silicon oxides are required for gate oxide and tunnel oxide. In general, the failure of a thin oxide can be categorized by three modes (Yamabe, 1990): Mode A, Mode B, and Mode C. Mode C failures represent intrinsic oxide breakdown while mode A failures are related to surface foreign material such as unintentional contaminants. impurities and particles. Mode B failures on the other hand are related to silicon material crystallographic defects such as as-grown stacking faults and SiO, precipitates and process induced crystallographic defects. It has been shown that the crystal quality of the silicon wafer surface plays an important role for gate oxide integrity (GOI) (Yamabe et al., 1983; Ryuta et al., 1990; Yamagishi et al., 1992; Miyashita et al., 1991; Miyashita and Matsushita, 1993): crystal defects in the wafer surface region reduce the dielectric breakdown strength and long-term reliability of thin oxides (Miyashita and Matsushita, 1993). Silicon wafers typically used for ULSI fabrication are made of CZ grown crystal and have several types of as-grown defects, such as

oxygen precipitates and surface micro defects (SMD) (Yamabe, 1990; Yamabe et al., 1983; Ryuta et al., 1990; Yamagishi et al., 1992; Miyashita et al., 1991; Miyashita and Matsushita, 1993). To reduce these micro-defects near the silicon wafer surface extensive research has been done. One approach is to form a denuded zone (DZ) by annealing the silicon wafers at high temperatures in an oxygen-containing environment (Tsuya, 1991). Having a region free of defects and interstitial oxygen will result in the elimination of mode B failures. The use of an epitaxial layer as a DZ also significantly improves GOI. Another possibility to decrease the as-grown defects is to slowly grow the silicon crystal and control the thermal history of the crystal (Hizuki et al., 1990). These approaches have proved to be effective in reducing the as-grown defects to some extent, but insufficient for the improvement of time-dependent dielectric breakdown (TBBD) of oxides thinner than 10nm (Miyashita and Matsushita, 1993). Annealing of silicon wafers in a hydrogen environment at high temperatures to cause outward oxygen diffusion has been shown to be a very effective method to reduce the oxygen precipitates in the surface region. Improved GO1 has been reported in hydrogen annealed wafers (Matsushita et al., 1988; Adachi et al., 1992; Samato et al., 1993). A comparison of oxygen concentration and defect density for hydrogen-annealed CZ wafers, conventional CZ wafers, defect-free CZ wafers, and epitaxial wafers is shown in Fig. 9-2 (Nikkei, 1993). It is clearly seen that the hydrogen-annealed wafers are comparable to the more expensive epi wafers, but are superior to other wafers. On the other hand, however, Omar et al. (1992) observed a high density of micropits on the surface after annealing in H, at 1150 "C. Xu et al. (1993) also observed sur-

9.2 Gettering

41 7

Figure 9-2. Comparison of oxygen concentration and oxygen-extraction defects for hydrogen-annealed Cz wafers, conventional Cz wafers, defect-free Cz wafers and epi wafers.

face roughening during pre-annealing at 1050°C in H, which resulted in degraded dielectric breakdown. More fundamental understanding of the hydrogen annealing mechanism and process optimization is

needed before this technology can be incorporated in ULSI manufacturing. Deep submicrometer CMOS technology is switching from high-temperature diffused well to low-temperature MeV im-

41 8


plantation technology (Lee et al., 1993). A process sequence based on MeV implantation can eliminate two to three masking steps, eliminate up to 30 processing steps, improve surface topography, and reduce manufacturing cost by 5 to 15 YO,depending on the application. For MeV processing a denudation step must be added or incorporated into the process flow. An inert denuding environment is superior to an oxidizing environment and hydrogen has been reported to be the best (Borland and Koelsch, 1993; Borland, 1989). Recently a significant breakthrough in bulk Cz wafer quality was reported by using hydrogen annealing/denudation, resulting in the realization of surface properties similar to those on epi wafers without additional cost (Nikkei Microdevices, 1993). Under inert conditions such as hydrogen annealing at temperatures as high as 1200°C for 1 h, elimination of mode B failures has been reported (Samato et al., 1993). Gardner et al. (1994) reported significantly improved CMOS bulk Cz wafer quality on the use of hydrogen denudation processing (annealing). Superior device performance, thin tunnel/gate oxide quality and Cz wafer surface properties have been measured demonstrating the potential for epitaxial elimination. This is achieved by subjecting the wafers to a short hydrogen denudation pre-process between 1050“C and 1200“C for 15-30min. For thin oxides down to 8.2 nm up to 29% improvement was observed on two different QBD structures. Hydrogen denuding was also very effective in eliminating mode B oxide breakdown failures on bulk non-epitaxial Cz wafers, Additionally, an order of magnitude decrease in junction leakage was observed for the H 2 annealed wafers relative to the bulk non-epitaxial Cz wafers, resulting in bulk Cz wafers with surface properties similar to epi wafers without the added cost. These

results have immense potential cost savings for all CMOS fabrication areas today currently using epitaxial substrates, especially when applying MeV technology.

9.3 Device Isolation The electrical isolation of active devices in integrated circuit technology includes both general oxide isolation in the “field” regions between devices and special application structures. The most common isolation is the field region, which is typically implemented by partially or fully recessed thick oxide regions between active device regions. Complete oxide isolation with no parasitic leakage paths is possible only in silicon-on-insulator (SOI) technologies. Special isolation structures, such as deep trenches, have been developed to separate the n- and p-well regions of complementary MOS (CMOS). The basic desired properties for any isolation technology are: A small pattern transfer difference be-

tween mask layout dimensions and final device geometries. No downscaling of the field oxide thickness as other device geometries are scaled down. A planar surface topology. A defect-free process. 9.3.1 LOCOS-Based Isolation Almost all modern integrated circuits use LOCOS (local oxidation of silicon) for device isolation (Appels et al., 1970). A nitride/oxide stack is formed on the silicon substrate and is patterned and etched to remove the nitride layer in the field regions. Before the resist is stripped off, boron impurities are implanted into the field

9.3 Device Isolation

regions. The oxidation is then followed and the silicon is oxidized only locally in the field regions without nitride coverage. The thickness of the field oxide typically is between 700 and 1000 nm. A major drawback of LOCOS is the so-called “bird’s beak” transition between the field region and active device area (Bassous et al., 1976), caused by lateral diffusion of oxidizing species beneath the nitride oxidation mask. The transition length varies depending on the oxidation condition. This transition reduces the device packing density and, as the isolation area is scaled down for VLSI application, the problem becomes more serious. Scaling down the field oxide thickness can reduce the encroachment, but requires a heavier channel-stop implantation to maintain adequate isolation between the devices. The lateral diffusion of the channel-stop impurities during the oxidation and the subsequent high temperature processes can degrade junction capacitance, increase the junction leakage and reduce the “effective” electrical channel width associated with MOS current gain. An option in scaling LOCOS is a channel-stop implant done after the oxidation. This reduces the depletion of boron into the field oxide during the field oxidation, thus retains more boron impurities near the oxide/silicon interface in silicon. As a result, thinner oxide can be used to achieve appropriate isolation. However, the field oxide threshold voltage is very sensitive to the oxide thickness with through-field implant due to the variation of the field oxide thickness. Another problem associated with through-field implant is the increased junction capacitance and reduced junction breakdown voltage for N + / P junctions due to the increased substrate concentration under the junctions from the high energy, unmasked through-field implant.

41 9

Modifications of the LOCOS process have been investigated. SWAMI (sidewall mask isolation) is one of the best known LOCOS-based isolation techniques (Chiu et al., 1982) and was developed with the objective of retaining the advantages of LOCOS while drastically reducing the bird’s beak. Since the bird’s beak is due to oxygen lateral diffusion through thin oxide from the active area edges, an obvious solution is to block it with a nitride barrier (Teng et al., 1985). SILO’S (sealed-interface local oxidation) approach to bird’s beak reduction consists of reducing the thickness of the LOCOS pad oxide to zero in order to seal the silicon interface under the LOCOS stack (Hui et al., 1982). This eliminates the need for a perimeter nitride seal, as used in SWAMI, and allows for a simpler process. SILO uses an active area stack with two different nitride layers, one very thin ( x130 8, for interfacial seal) in direct contact to silicon and one much thicker (x1000 8, for oxidation mask) on top of the stack. Between them, the usual pad oxide is retained for stress relief purposes. The key to prevention of Si defects is the extremely small thickness of the sealing nitride, which limits the compressive stress induced in Si to values below the plastic deformation threshold (DerouxDauhphin et al., 1985). Another approach uses a stress relief poly-buffer layer between the nitride and the initial pad oxide (poly-buffer LOCOS, PBL), which absorbs stress produced during field oxidation (Nishihara et al., 1988; Havemann and Pollack). Although low bird’s beak was demonstrated, the resulting field oxide protrudes significantly above the original silicon surface, producing severe topography. Using the principle of a stress relief polysilicon layer and a reverse L-shaped sealed nitride spacer, the bird’s beak can be further reduced com-

420


pared to conventional PBL (Sung et al., 1990). The process flow for this reverse L-shape sealed poly-buffer LOCOS (RLSPBL) is shown in Fig. 9-3 (Sung et al., 1990). The pad oxide is selectively removed using the silicon nitride/polysilicon stack as a mask to form undercut portions. A new stress-buffer oxide film is then grown to cover the entire silicon surface. After LPCVD nitride deposition and RIE, a reverse L-shape sealed silicon nitride spacer is formed. Shimizu et al. (1992) developed a poly-buffer recessed LOCOS (PBR LOCOS) isolation for 256 Mbit DRAM cells. In this process, the low bird’s beak and defect-free isolation are achieved by using shallow silicon recess etch (25-200 nm), buffer polysilicon, and nitride sidewall sealing. The process flow of PBR LOCOS is shown in Fig. 9-4.

SI

\PAD

OXIDE

(a)

E

(C)

Figure 9-3. Reverse L-shape sealed PBL process flow: (a) formation of side etched portions of pad oxide; (b) sealed nitride film deposition; and (c) RIE nitride etching. The pad oxide (100 A), polysilicon film (500 A), nitride cap (2000 A), and regrown oxide (60 A) are not drawn to scale.

9.3.2 Advanced Isolation Techniques The scalability of LOCOS to deep submicrometer dimensions has been difficult due to the conflicting requirements for a small bird’s beak profile, defect-free substrate and adequate field oxide thickness to ensure good electrical isolation. Several isolation techniques have been investigated as replacements for standard LOCOS. Non-planar techniques are not favored because of the patterning difficulties associated with subsequent levels such as interconnect. Those that are sufficiently planar can be divided into the following categories : Modified LOCOS that use improved nitridation masking Shallow Trench Isolation (STI) Selective Epitaxial Growth (SEG) Trench isolation Silicon on insulator (SOI)

Figure 9-4. PBR LOCOS process sequence: (a) after recess etching; (b) after nitride sidewall formation; and (c) field oxidation.


Recessed sealed sidewall field oxidation (RESSFOX) (Lee et al., 1990) employs a consumable sidewall nitride to reduce bird’s beak. A thin consumable nitride film of about 200 8, thickness is deposited over a shallow trench (150 nm) in the Si substrate after the field implant. RIE is used to form the consumable nitride on the sidewall of the shallow trench prior to field oxide growth. This thin nitride must be thick enough to block the oxygen lateral diffusion, and thin enough not to add additional stress and to be consumed during field oxidation. This is the main difference between RESSFOX and SWAMI. The use of a self-aligned nitride-filled or polysilicon-filled cavity followed by nitride spacer formation to offset the bird’s beak from the nitride-1 edge has received much attention for 0.25 ym CMOS technology. Polysilicon encapsulated local oxidation (PELOX) controls the bird’s beak through the use of a polysilicon-filled cavity, selfaligned to the nitride edge (Roth et al., 1991). The process only involves simple modification of a standard LOCOS process flow. These modifications include an HF dip after nitride pattering to form a cavity self-aligned to the nitride edge, reoxidation of exposed silicon, and polysilicon deposition to fill the cavity, as shown in Fig. 9-5. Using nitride-filled cavity instead of polysilicon-filled cavity, Pfiester et al. (1993) have developed a ni tride-clad LOCOS (NCL) isolation which exhibits 600 A per side bird’s beak encroachment profiles with adequate field oxide thickness in narrow field regions. The process flow is shown in Fig. 9-6. A bird’s beak controlled poly-buffered LOCOS (BPBL) was developed by Huang et al. (1993). A schematic process sequence of BPBL isolation is shown in Fig. 9-7. The pad oxide was grown, followed by LPCVD polysilicon and nitride deposi-

42 1

tions. After nitride etching by RIE, isotropic plasma etching was used to partially remove the exposed polysilicon to form rounded thin polysilicon regions under the nitride layer. After nitride spacer formation, the remaining polysilicon is removed to increase the recess depth of a 4000 8, field oxide. The corner between the first nitride and polysilicon is rounded to diffuse stress impinging from the nitride spacer to the Si substrate during field oxide growth. The polysilicon is thinned to minimize the bird’s beak penetration. Results show that the surface morphology is quite planar, Le., the recessed portion of field oxide profile reaches almost 70% of total thickness. Isolation space up to 0.35 ,urn has been achieved with excellent junction characteristics and gate oxide integrity. For buried oxide (BOX) isolation (Kurosawa et al., 1981; Shibata et al., 1983) or shallow trench isolation (STI) (Fuse et al., 1987; Davari et al., 1988; Pierce et al., 1991; Yu et al., 1992; Shibahara et al., 1992; Fazan et al., 1993) shallow trench and advanced planarization techniques are used. For feature size of 0.25 ym or below, neither LOCOS nor its advanced modifications are expected to provide the required surface planarity, field-oxide thickness, edge contour, and channel-stop characteristics. On the other hand, BOX and STI isolations have the potential to fulfill these needs. Unlike the local oxidation process, in BOX a deposited oxide is used. Thermal oxidation depletes the channel stop boron impurities near the interface which degrade the isolation. Using deposited oxide can retain more boron under the field and can achieve sharper corners with more potential barrier enhancement. However, BOX isolation suffers from process control problems, such as field isolation uniformity at mesa corners, double-resist processing, and

422


Figure 9-5. PELOX process flow: (a) RIE nitride; (b) HF dip to undercut nitride and form cavity; (c) growth reoxidation; and (d) deposit polysilicon encapsulation layer.

Figure 9-6. NCL process flow: (a) HF etching of the first stress relief oxide (SRO-1) to form a 750 8, selfaligned cavity under Nitride-1; (b) a 5 5 8, thermal reoxidation (SRO-2) followed by a 100 8, Nitride-2 deposition; and (c) field oxidation.

Figure 9-7. Process flow of BPBL isolation.


I

423

I

Figure 9-8. STI process flow summary: (a) mask and trench definition, (b) trench oxidation and B doping, (c) CVD oxide and CMP planarization, (d) oxide spacer formation, (e) pad oxide wet etching, (f) gate oxide growth and gate deposition.

registration of the first-resist pattern. Moreover, the adoption of sloped sidewalls contrasts with the trend toward higher resolution. STI provides a planar surface and a fully recessed field oxide; it does not suffer from field oxide thinning and can easily be scaled down. Fazan and co-workers (1993) proposed a simple STI process suitable for 256Mb to 4Gb DRAMS. The process flow is summarized in Fig. 9-8. The features of this STI process are tapered trench sidewalls, a slight trench reoxidation, a vertical boron field implant, a CMP-only planarization, and disposable oxide spacers to smooth the trench corners. In addition to device isolation, STI has been employed to fabricate 0.25 pm CMOS devices with buried trench gate structures, as shown in Fig. 9-9 (Wen et ai., 1991). The entire poly gate is buried in both active and isolation areas and a fully planarized structure is achieved. The electrical Junction depth with respect to the channel surface is

Figure 9-9. Process sequence of the fully planarized CMOS technology.

424


about 50nm, which is much shallower than the conventional junction due to the recessed poly gate. Excellent short channel effects and device characteristics are achieved using this fully planarized CMOS technology. The highly planar topography of this technology also forms an excellent base for future planarized multilevel interconnect structures. SEG is conceptually the simplest method for achieving fully recessed oxide isolation. Active silicon layers are grown epitaxially between columns of oxide that serve as device isolation. At the leading edge of this technology, SEG demonstrated an incredibly short active area spacing across the well of only 1/4 pm (Kasai et al., 1987; Kamins et al., 1985). The rapid progress experienced by SEG has resulted in a growing number of publications and improvements in SEG fabrication equipment. indicating that this technique will play a major role in CMOS submicrometer isolation at 0.25 pm and below. The other 1. Oxide

2. Etch N-well windows

advantage of SEG is that the n-well and p-well can be formed independently, as shown in Fig. 9-10 (Borland, 1987). Independent n-well and p-well CMOS structures with retrograde wells can be realized through graded epitaxial growth without the use of ion implantation and high temperature annealing. This advantage can also be found in bipolar and BiCMOS structures. The selective doping is also very attractive for other applications such as shallow junction formation and contact refill as well as planarization for interconnect. Remaining issues to be resolved in SEG include the faceting and the defect generation in epi near the epi/oxide interface. Although defect-free structures have been reported for patterns oriented parallel to the (100) direction, they have yet to be determined for other orientations. The major objective of trenches is to achieve high density without suffering an increase of isolation leakage or having to reduce the supply voltage. This is achieved

3. N-Type SEG epi for N-well formation

4. Thin thermal

oxide

I 5. Etch P-well

windows

6. P-type SEG epi for P-well formation

Si

7. Strip thin oxide

Retrograde wells are possible by buried layer epitaxy or graded epitaxy techniques

Figure 9-10. Independent n-well and p-well formation by SEG.

I

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by folding the silicon surface across the isolation to form a deep, narrow barrier, which increases the current path many times with respect to the spacing. Moreover, by digging the trench so deep that its bottom lies in heavily doped silicon, such as the substrate of an epitaxial wafer, the isolation leakage suppression is virtually complete. Particularly for trench capacitors, the trench oxidation properties are important to ensure high dielectric strength, high breakdown voltage, and low leakage current of the capacitor dielectric. Fortunately, these properties were found to be only slightly inferior to those of planar surfaces (Baglee et al., 1985), with the weakest spot being at the corners, where the oxidation rate is smaller (Marcus and Sheng, 1982). However, using a sacrificial oxidation, these corners can be rounded off erasing any difference between the trench and the planar oxide properties (Yamabe and Imai, 1981). Conventional trench isolation results in stress induced defect generation. The problem can be overcome by a sealed sidewall trench (SST) process (Teng et al., 1984) containing an additional nitride layer in the trench, although this introduces process complexity. With the conventional trench process (either refilled with poly or deposited oxide), the leakage is about 2 to 3 orders of magnitude higher than without a trench (Teng et al., 1984). However, with SST the leakage is comparable. Although trench isolation can produce excellent lateral isolation, it does not address vertical isolation. The ideal situation for future isolation would be to suspend both device types in a dielectric layer (e.g., SiOJ. This would effectively eliminate latch-up and radiation induced error phenomena, as well as reduce performance limiting effects such as parasitic capacitnnmts. Furthermore, such a structure

425

would require less layout area for the same design rules than conventional, junctionisolated CMOS, because the deep p- and n-wells are eliminated and the area required to accommodate p-n junctions is significantly reduced.

9.3.3 Silicon-on-Insulator Silicon-on-insulator (SOI) technology is a major contender to provide the high performance, low voltage, low power capabilities required for future generations of integrated circuits. The performance advantages of this technology, as well as the potential yield advantages offered by the unique “all around” isolation in SO1 devices, have been discussed in several publications. During the past several years, unique problems in device performance in this technology have been identified and solved, but the long standing issues of quality, availability, and cost of SO1 substrates have prevented this technology from being commercial IC applications. FIPOS (full isolation by porous oxidized silicon) employs lateral anodic oxidation to form isolated silicon islands over a silicon substrate (Zorinsky et al., 1986; Kubota et al., 1986; Imai et al., 1984). In early developments, lateral oxidation could only be extended to a few micrometers without forming excessively thick porous oxide films, which would cause warpage and later interfere with the rest of the process. An improved FIPOS approach was developed. It is known as the ISLANDS method (Zorinsky et al., 1986) and its process sequence is illustrated in Fig. 9-11. A heavily doped n + layer is formed by epitaxy followed by a second n-epitaxial layer with the desired resistivity. Then, Si,N, and SiO, are deposited to form the masking stack. Trenches with a

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426


F== EPI LAVER

(*)

OXIDIZED POROUS SILICON LAVER

THERMAL OXIDE

SUBSTRATE

ANODIZABLE LAVER

FORM N+ ANODIUBLE LAYER QROW EPITAXIAL “TUB” LAYER ANODIZABLE LAVER \

FORM (POROUS) ANODIZED LAYER I) (P = FI [HF], J. Nd..

..

GROW ISOLATION OXIDE

(B)

HARD MASK LAVERS PATTERN TRENCH MASKETCH STACK, ETCH TRENCH

- -

REFILL TRENCH DEPOSITED OXIDE PLANARlZE RESIST EROSION DENSIFY TRENCH OXIDE

few micrometers are formed along the active area edges. The porous oxide is formed preferentially along the n + epitaxial layer, electrically isolating the top n-silicon layer from the substrate. Finally, the trenches are refilled with oxide and planarized. The maximum size of an isolated feature is 42 l m in width and unlimited in length. The minimum pitch is 2.8 pm and consists of a 1-pm line and a 1.8-pm gap. The porous oxide thickness is uniformly controlled to 4900 -t 300 A. Measured electron mobilities are equivalent to those of BULK. The subthreshold leakage current is low (a0.1pA/pm width at 5 V), demonstrating complete elimination of the back channel. Several significant contributions have been made recently to the two primary SO1 technologies being considered for volume VLSI device applications: separation by implantation of oxygen (SIMOX) and wafer bonding (as used here, “wafer bonding” includes all of the thinning techniques for producing SO1 which use bonded wafers as a basis). The SIMOX process is illustrated in Fig. 9-12. This process uses a high dose oxygen implantation (10’ oxygen atoms/cm2)into a silicon substrate, followed by high tem-

~i~~~~ 9-11. The ISLANDS process flow.

perature annealing to form a buried oxide. The structure after the implantation is composed of the silicon substrate, a buried oxide, and a single-crystal silicon film. If necessary, the single-crystal silicon thickness can be increased by conventional epitaxy. During oxygen implantation, the wafer is kept at an elevated temperature ( >400°C) in order to minimize the damage to the surface layer. The growth characteristics and physical structure of the buried oxide and the single-crystal silicon produced by the SIMOX process has been studied extensively over the past several years. During the implantation, the oxygen concentration first forms a skewed Gaussian profile, but once the oxygen dose is sufficiently high the distribution becomes flat-topped, with a peak oxygen concentration corresponding to stoichiometric SiO,. It has been found that al-

I

Figure 9-12. Scheme of SIMOX process.

I


though the SIMOX buried oxide is in many ways similar to thermal oxides, it differs significantly in both conduction characteristics and radiation response. High temperature annealing ( > 1300“C) is performed following the implantation to eliminate crystallographic damage in the surface silicon layer, and to allow oxygen from the tails of the implanted distribution to diffuse to and be incorporated in the SiO, layer. After annealing, the dislocation and stacking fault density in the top silicon layer was quite high, i.e., approximately IO4 to lo6 per cm’. Such high density of dislocations and stacking faults remaining in SIMOX wafers after annealing can cause emitter -collector shorts in bipolar devices, similar to the effects of these crystallographic defects on devices built in bulk material. As a result, SIMOX wafers cannot be used for ULSI bipolar applications. On the other hand, the effects of crystallographic defects in SIMOX material on CMOS devices can be minimized. The majority of applications of SIMOX SO1 technology are found in CMOS devices designed for operation in harsh environments. The typical SO1 materials needed for these applications have buried oxides with thicknesses in the range of 0.4 pm, and silicon layers with thicknesses of 0.3-0.5 pm. The SIMOX process is ideally suited to producing material with these layer thicknesses. Even with the device demonstrations, the major stumbling block for the use of SO1 technology in any large scale applications has been the credibility of supply of high quality SO1 at reasonable costs. A fundamental problem of buried oxide “pipes” are plagued SIMOX wafers. These buried oxide “pipes” are observed as conductive threads of silicon through the oxide. Measurements also showed that there are “partial pipes”, that is, areas which appear as thin oxide regions

427

in the SIMOX materials. The buried oxide pinhole problem has been correlated with particles on the wafers during the implantation step. The “pipes” are a result of the shadowing of specific areas from the oxygen implant by the particles. Eliminating these defects has not been a trivial task since particles can be generated in the clean-up before wafers are implanted as well as in the implanter itself. The wafer bonding process is illustrated in Fig. 9-13. In this process, two silicon wafers which have a very high degree of flatness are used. One, or both, of the wafers are oxidized. The surfaces are then mated, and the composite is annealed to form a single structure. One of the wafers is then used as a handle, and the other wafer is thinned from the back side until only a thin superficial silicon film is left. Several techniques for the thinning process have been used, including both physical and chemical techniques. In some methods, an etch stop is either implanted or diffused into the wafer to be thinned before the bonding process; initial thinning is accomplished by a mechanical process to produce a film in the range of several micrometers thickness. The final thinning is then accomplished by a chemical etch Two Flat Si Wafers

I

Wafer 1

I

I

Wafer 2

I Oxidize, Bond, Anneal

-

Oxide

Wafer 2

Grind, Polish or Preferential Etch

I

Wafer 2

I

Figure 9-13. Scheme of wafer bonding process.

428


back using a preferential etchant and an etch-stop layer. The structure of the superficial silicon films on bonded wafers are expected to be very similar to those of the bulk wafers used in the SO1 fabrication. This is generally found to be the case, at least for superficial silicon layers down to a thickness of a few micrometers. Typical crystal defect densities in bulk silicon are < 102/cm2. With the usual wafer grinding and polishing techniques used for silicon IC substrates, it is difficult to produce uniformities superior to f.0.5 pm. Although thinner superficial silicon layers can be produced with chemical etch stop techniques, this is at the expense of added process complexity and the possible introduction of defects due to the etch stop layer itself. Because it is relatively difficult to control the thickness of bonded wafers within very small ranges, these materials have been primarily applied to bipolar devices. In bipolar circuits, the superficial silicon layer must be essentially free of crystallographic defects, and is typically used to form a deep collector. This requires a thickness in the range of 2-4 pm, with tolerances of f0.5 pm. The wafer bonding approach is ideally suited for this application. Ultrathin bond and etch-back silicon on insulator (BESOI) in the thickness range of 75 to 100 nm offers the potential for performance enhancement in both CMOS and BiCMOS technology (Omura and Izumi, 1990; Shahidi et al., 1991). To be useful however, a very low total thickness variation (ttv) is desirable, typically below 10 nm. With the conventional grinding technology ttvs around 300 nm can be obtained, with ultra-precision grinders even better ttvs are possible (Abe et al., 1992). Nevertheless, conventional grinding technology may be incapable of achieving the ultra-low ttvs which are required by these

new applications. Recently, several polishing techniques have been reported that utilize polish stops to achieve high ttvs with selected patterns. While these techniques are useful, they are expensive and do not yield a generic wafer. A unique plasma thinning technology has been demonstrated to be able to thin the superficial silicon on bonded wafers to thicknesses of 0.3 pm or less, with thickness tolerances of less than fO.O1 pm (Mumola et al., 1992). This may allow bonded wafers to be used for both CMOS and bipolar devices. Bonding of an oxidized wafer to another wafer was proposed by Lasky and coworkers (1985). They developed an ion implanted etch stop technology to thin the device wafers. Mazara (1991) and Hunt et al. (1991) extended this technique to include a double etch stop. A potential high throughput BESOI process that is capable of achieving both intrinsic high quality (both silicon and oxide) and versatility as well as high uniformity was developed by Iyer et al. (1993) using a well-defined and highly uniform etch stop system. The Si-Ge etch stop layers are deposited by low temperature UHVCVD epitaxial techniques (Iyer et al., 1989). After a low temperature joining and bonding process, the device wafer is thinned by moderate ttv grinding, followed by a damage removal step. The device wafer is then selectively etched in high selectivity silicon etch with the etching stopping well within the etch stop system. The etch stop layers are then separately removed in another selective etch. After taking into consideration the uniformity of the epitaxial processes, grinding and etching processes, a ttv that is typically well below 10 nm is routinely achieved with minimal edge loss. Electrical characterization of SO1 films showed superior carrier lifetimes and FET devices characteristics.

429

9.4 Gate Dielectrics

The bonding interfaces must be free of bubbles. Bubbles are mainly caused by particles and adsorbed gases on silicon surfaces such as hydrocarbons. These particle-related bubbles can be eliminated by mating two wafers in an ultra-cleanroom (class 1 or better) or by using a micro-cleanroom set up (Mitani et al., 1991). Bubble generation caused by adsorbed gases can be prevented by degassing before wafer bonding (Mitani et al., 1991). Bonding strength is monotonically increased with increasing the annealing temperature due to atomic phase change at the bonding interface and the thermal flow of oxide at high temperature.


CMOS TECHNOLOGY TREND

-ol

0.25 I

As device dimensions continue to shrink, a commensurate reduction in the gate oxide thickness is required, as shown in Fig. 9-14 (Taur et al., 1993), primarily to prevent the short-channel effects. For example, an excessive reduction in channel length without an adequate thickness scaling can result in threshold voltage instabilities due to charge sharing effect as well as excessive subthreshold and off-state currents due to drain-induced barrier lowering and punchthrough. Thus, in order to minimize the undesirable short channel effects while ensuring high performance of the device, gate oxide thickness scaling is a very efficient approach. In other words, by scaling the oxide thickness, the behavior of a MOSFET can be made more long-channel-like. Thin gate oxides ( < l o 0 A) in ULSI MOS applications should meet the following crucial requirements : Low defect density Good barrier properties against impurity diffusion High quality Si/SiO, interface with low interface state density and fixed charge

0.5

I

0.1 1.0 MOSFET CHANNEL LENGTH (pm)

IO

Figure 9-14. CMOS technology trend.

Stability under hot carrier stress and irradiation Low thermal budget processing Low defect density in the oxide ensures that the number of catastrophic oxide failures at low electric fields is minimum. One method to characterize oxide integrity is breakdown histograms. This well-established method categorizes failure modes as either mode A, B, or C (Sanchez et al., 1989). Mode C failures represent intrinsic oxide breakdown while mode A failures are related to surface foreign material such as unintentional contaminants, impurities and particles. Mode B failures on the other hand are largely related to silicon material crystallographic defects such as as-grown stacking faults and SiO, precipitates and process induced crystallographic defects. Other causes for Mode B failures are listed in Table 9-2.

430


Table 9-2. Causes for B-mode failures in oxide. 1 . Local electric field intensification a. Local oxide thinning b. Residual nitrogen at surface (Kooi effect) 2. Charge trapping of oxide a. Electron trapping water related traps non-bridging oxygen defects dopant impurities b. Hole trapping oxygen vacancy

3. Crystal quality a. Metallic contamination b. Surface roughness c. Oxygen precipitates 4. Process-induced damage a. Reactive ion-etching b. Photoresist ashing

Improved barrier properties are particularly important for p+-polysilicon gated p-MOSFETs. Low interface state density ensures a sharp switching characteristic in MOSFETs. High lateral electric fields in the channel in the downscaled MOSFETs lead to significant heating of channel carriers, resulting in hot carrier effects such as oxide charge trapping and interface state generation. The use of a gate dielectric which suffers minimum damage under hot carrier stress is a promising option in aggressively scaled MOSFETs. Processing techniques such as reactive ion etching (RIE) and some of the future tools such as X-ray lithography can expose gate oxides

to high energy plasma and radiation, which are known to reduce the quality of gate oxides. This imposes the requirement of the radiation “hardness” on thin gate oxides. Finally, low thermal budget is necessary in ULSI in order to minimize the redistribution of dopants by diffusion. The main thrust in the gate dielectric research in recent years has been addressed to the above mentioned issues. Numerous techniques have been suggested to solve one or more of these problems. These techniques can be broadly divided into four categories. The first approach involves variations of pre-oxidation cleaning procedures. The second approach involves process variations of the oxidation process. The third approach, which has received considerable attention over the past decade, is to chemically modify the properties of gate oxides. The final approach is deposition of oxides or formation of stacked layers as gate dielectrics.

9.4.1 Preoxidation Cleaning The fundamental role of a silicon cleaning procedure is to remove from the surface (a) organics, (b) transition metal and alkali ions and (c) particulates. These contaminants, if not removed from the wafers prior to oxidation, can affect the quality of the gate oxide. Common wet cleans and their application are listed below :

etching native SiO, layers

o HF/H,O

removing heavy organics

0

H,SO,/H,O,

0

NH,OH/H ,O,/H,O (1 : 1 :5 ) (SC-1)

0

HCI/H,O,/H,O (SC-2)

0

Effects of NH,OH/H,O,

(5:l)

removing light organic residue and particles removing metallic species

(1 : 1:5 ) ratio:

High: good for particle removal Low: less surface roughening

431


The RCA cleaning procedure, proposed by Kern and Puotinen (1970), is still used widely in its original form or with minor modifications. The cleaning procedure consists of two steps. The first step involves cleaning in a hot, high pH H,O, SC1 solution (H20/H,0,/NH40H = 5 : 1: 1) in order to remove organic contaminants from the silicon surface by oxidation. The second step involves treatment of the silicon surface with a hot, low pH H,O, SC2 solution (H,O/H,O,/HCl= 5 : 1 : 1) to remove the metal contaminants via metal complex formation. An additional intermediate step of dilute H F dip is often used to remove the oxide grown during the first cleaning step. A detailed review of the chronological development of the cleaning processes has been published by Kern (1990). As the oxide thickness is scaled down to below 100 A, the requirements on the cleaning processes have become more stringent. Although RCA or modified RCA clean are adequate in effectively removing the surface contaminants, these cleaning treatments can also lead to surface microroughness due to the presence of alkaline N H 4 0 H solution used. Ohmi et al. (1992) investigated this phenomenon in detail and reported that microroughness causes lowering of breakdown electric field and charge-to-breakdown in gate oxides grown on these surfaces. They suggested the use of a 5 : 1 :0.25 H,O/H,O,/NH,OH solution, rather than the traditional 5 : 1 : 1 mixture in order to prevent the surface microroughness. Optimization of the NH40H/H20,/H,0 ratio in the SCIcleaning has been studied by Meuris et al. (1992). It was found that both metal contamination and particle densities were equal after the complete RCA cleaning for wafers processed using SC1 with different mixtures (NH,OH/H,O,/H,O = 0.1 - 1 : 1 :5).

From this, one would normally expect similar breakdown properties of subsequently grown gate oxides. However, large differences were found in yield. The 0.25:1:5 SC1 mixture results in much higher gate oxide integrity than the 1 :1 :5 mixture due to the Si-surface roughness caused by SC1 solutions. A qualitative model for the action of the SC1-cleaning helps to understand the observations (Meuris et al., 1992). When silicon is exposed to the SC1mixture, the peroxide will oxidize the silicon surface while the ammonia will disperse this chemical oxide; i.e. a chemical oxide layer will continually form and dissolve as a result of the compensating effect of the two chemical components. This process slowly etches the silicon. A high etching rate will increase the particle removal efficiency by undercutting the particles, but will cause a larger surface roughening during 10 min of cleaning. Consequently, it is important to find an optimum between particle removal efficiency and silicon surface roughening. An etching rate of 0.2 nm/ min was found to be the best. New cleaning solutions such as choline are also being used (Kao et al., 1989) with a reduction in defect density in oxides. The metallic contamination on Si wafers after various cleaning treatments is shown in Table 9-3 (Verhaverbeke et al., 1991). In general, a final cleaning step in H F results in lower metallic contamination compared with standard RCA cleaning. Surface metal Table 9-3. Typical metallic contamination after various final cleaning steps followed by DI water rinsing (10" at/cm2) (Verhaverbeke et al., 1992).

RCA HF HF/H,O, BHF

K

Ca Cr

Fe

Ni

Cu

Zn

0.3 0.1 0.6 0.2

8.6 3.8 1.6 1.4

5.1 0.3 2.2 2.6

3.3 0.1 0.2 0.3

0.3 0.06 0.09 3.7

0.4 0.1 1.2 0.7

0.2 0.05 0.3 0.4

432


contamination resulting from SC-1 solutions include the following: -

Fe will form non-soluble iron hydroxide under SC-1 conditions; Iron hydroxide can be removed during SC-2 cleaning; Electrochemical plating of noble metals (e.g..Cu) from HF.

The hydrogenated surface resulting from H F etching allows electrochemical reactions with noble metals to occur. The reaction product is mostly a silicide, a chemical substance very difficult to remove in a subsequent set of chemical cleaning steps. Cu is present in an acid HF-solution with a higher half-cell potential than hydrogen and, therefore, can be deposited on the Sisurface from an HF-solution (Kern et al., 1991). This can be avoided by using highly purified chemicals or by adding small amounts of H,O, to the HF-solution (Ohmi et al., 1991). Contaminants in the chemicals used in wet etching and DI water distribution system have been major sources of metallic impurities which reduce the gate oxide integrity. In a recent work (Verhaverbeke et al., 1991), roles of various metallic contaminants on the gate oxide breakdown properties were studied. Ca was found to interact strongly with the Si substrate, resulting in interface roughness and deterioration of breakdown properties. Whereas Fe was observed to degrade the oxide integrity by forming defect spots during oxidation, A1 was shown to cause damage under the polysilicon gate/SiO, interface. Unlike Fe and A1 contamination, Ca contamination is largely unaffected by the gettering cycle. This is consistent with the fact that Ca is mainly located in the thermal oxide. From these results it can be concluded that for gate oxide integrity, Ca is the most important contaminant. The Ca

contamination can be avoided by using ultra-pure chemicals, ultra-pure distilled (DI) water, a carefully designed DI-water distribution system and by final cleaning with H F (Verhaverbeke et al., 1992). After the last cleaning step with HF, the metallic contamination on the Si-surface is lower on the average than after an RCA-cleaning for the typical metals found after a stateof-the-art cleaning. Owing to their low metallic contamination, HF-dipped surfaces are well-suited for the growth of highlyreliable thin gate oxides. However, hydrophobic surfaces are well-known to be susceptible to particle deposition, particularly during subsequent DI-water rinsing (Table 9-4). These particles can be reduced significantly after oxidation. Table 9-4. Particles on a 5 inch wafer after HF-dip and rinse-dry (Verhaverbeke et al., 1992).

N, manual blow HF-dip/no rinse HF-dip/overflow rinse HG-dipiquick dump rinse

Spin Spin dryer rinsedryer

I

250 6900

400 3100

500 6100 1200 7600

By adding minute amounts of isopropyl alcohol (IPA) to the HF-solution (Verhaverbeke et al., 1992), the deposition of particles on the Si surface can be prevented during HF-dipping and subsequent rinsing and results in highly reliable oxide layers. By adding 200 ppm or more IPA to the 0.5 YOH F solution, the particle deposition is dramatically reduced. The IPA does not chemically react with the Si surface; it is only physically adsorbed and desorbs readily at moderate temperatures. As the devices become smaller and smaller, there are several serious concerns for wet chemical cleaning. These include:


- Particulates generated after cleaning; - Drying difficulties (watermarks) ; - Large amount of hazardous waste chemicals produced; - Inability to clean small contact holes with large aspect ratio; - Incompatibility with certain existing processes ; - Incompatibility with integrated processing. For these reasons, dry cleaning processes have attracted significant attention (Moslehi et al., 1992; Ruzyllo et al., 1989) over the past several years. Advantages of dry cleaning include : -

-

A "cleaner" process; Gas reactive species have easier access to the wafer surface, capable of penetrating minute, high aspect ratio trenches; Significant reduction in chemical waste disposal ; Can be incorporated in situ for integrated single wafer processing; Removal of metal and organics can be achieved by using UV-enhanced or plasma dry cleaning.

Ruzyllo et al. (1989) reported that the use of UV treatment on wafers in an 0, ambience to remove organic contaminants had no detrimental effect on mean time-tobreakdown ( t b d ) as well as t b d distribution. Kao et al. (1991) used a vapor phase HF/ HCl cleaning procedure and observed a ten-fold increase in tb, for the subsequently grown gate oxides compared to the oxides on RCA cleaned wafers. Kasi and Liehr (1992) concluded that a pre-oxidation high temperature UV/O, treatment can effectively remove the hydrocarbon contamination. Fukuda et al. (1992) adopted a rapid thermal cleaning approach in which the wafers, initially subjected to H,SO,-H,O, cleaning and 1 % H F dip were treated in

433

either H, or HCl/Ar ambience for various temperatures and durations. It was concluded that the HCl/Ar cleaning removes metallic impurities as well as the native oxide, whereas the H, cleaning is unable to remove the metallic impurities.

9.4.2 Process Dependence of Gate Oxide Quality The impact of gate oxide temperature on the quality of the gate oxides has been investigated by several researchers. For example, in an earlier work, Deal et al. (1967) reported that the fixed positive charge in the oxide decreased nearly linearly with increasing oxidation temperature. Hahn and Henzler (1984) studied the structural and electrical properties of the Si/SiO, interface as a function of oxidation temperature. They reported a strong correlation between the atomic steps at the interface, which were taken as a measure of roughness, and the electrical properties and concluded that high temperature oxidation results in a smoother interface with less interface states and less fixed charge. Fukuda et al. (1992) also indicated that high temperature (1200 "C) RTP oxidation results in a superior gate oxide with lower interface state density, longer tbd and tighter tbd distribution, as compared to low temperature (800 "C) furnace grown oxide. Walters and Reisman (1990) reported that the density of electron traps in the gate oxide decreased with an increase in oxidation temperature from 800 "C to 1000 "C. Joshi and Kwong (1992) reported that MOSFETs with gate oxides grown at high temperature show improved electron and hole mobility as well as suppressed degradation under radiation and hot-carrier stress, as shown in Fig. 9-15. The improved mobility was attributed to the formation of a smoother interface at elevated

434


-

Temperature ("C)

5 20

omL

800

.

' 900

'

'

1000

'

'

1100

'

1

b, v

0

12cv

TEMPERATURE ("C)

Figure 9-15. (a) Effective electron mobility (perf)for two values of effective electric field (Eeff)in MOSFETs with gate oxides grown at different temperatures. (b) Increase in off-state leakage current (AZd,) and transconductance degradation as a function of gate oxide growth temperature.

temperatures, while the improved reliability was attributed to interfacial strain relaxation by viscous oxide flow at temperatures above 960 "C (EerNisse, 1977). These studies suggest that high temperature oxidation is preferred in order to achieve good performance and reliability in gate oxides. Consequently, rapid thermal oxidation at high temperature appears to be a suitable approach for gate oxide growth in ULSI MOS devices. Apart from the higher growth rate, suppressed number of early breakdown as compared to dry oxides is an attractive feature of wet oxides (Irene, 1978). Wu et al. (1989) observed that wet oxides

show very sharp t b , distributions with 15 x larger t b , values as compared to dry oxides. Li and Chang (1988) used a two step approach to grow gate oxides, with a combination of dry-dry, wet-dry and wetwet processes. The wet-wet process resulted in the minimum defect density. A systematic decrease in the number of low field breakdowns was observed with an increase in wet oxygen partial pressure during oxidation. Recently, wet oxides have been implemented in a 0.8 pm technology and some attractive features have been reported (Wei et al., 1992). The comparison was made between 850°C wet oxide MOSFETs and 900°C dry oxide MOSFETs. The breakdown histograms were comparable in both the cases, unlike the significant improvement for wet oxides reported in earlier studies. A 10% increase in linear transconductance was observed in n-channel MOSFETs with wet gate oxides. However, in p-channel MOSFETs, where electron trapping during hot carrier stress is the dominant degradation mechanism (Koyanagi et al., 1984), wet oxide devices are somewhat worse than dry oxide devices. The use of high pressure oxidation was suggested for growing thick field oxides, e.g., in a LOCOS isolation (Baglee et al., 1984). The major advantage of high pressure oxidation is an enhanced growth rate as compared to atmospheric pressure oxidation. If atmospheric pressure oxidation is used to grow thick field oxide necessary to provide isolation between adjacent MOSFETs, high temperature/long duration processing is necessary. For example, a 3000 8, field oxide can be grown by wet oxidation at 1000°C in about 2 h. Such a high thermal budget is not desirable in ULSI processing due to redistribution of dopants by diffusion. For example, channel width narrowing due to the encroach-


ment of channel stop implants into the active regions has been reported by Baglee et al. (1984). Due to the enhanced oxide growth rate, high pressure oxidation can be performed within a considerably smaller thermal budget either by lowering the oxidation temperature or by reducing the growth time. Since thermal budget reduction is crucial in ULSI processing, Tay et al. (1987) applied high pressure oxidation to grow gate oxides. At a pressure of 10 atm, an 120 8, thick gate oxide was grown at as low a temperature as 700°C. The pressure ramp-up was performed in N, ambience in order to avoid nonuniform oxide growth on wafers due to temperature instabilities. These oxides shows low interface state densities in the 1010 eV-' cm-, range. In a more recent work (Tay et al., 1990), the same research group demonstrated that high pressure oxidation at 700 "C followed by nitrogen annealing at 900 "C results in gate oxide films (80 8,) with up to 15 MV/cm breakdown field and high quality Si/SiO, interface. In an earlier work, it has been indicated that high pressure oxides and conventional oxides grown at atmospheric pressure show similar radiation response (Gupta et al., 1980). Although the high pressure gate oxidation technique appears to be attractive due to its low thermal budget, a more detailed investigation is required to judge its applicability to ULSI MOS processing, especially regarding the MOSFET reliability.

-

9.4.3 Chemically Modified Gate Oxides

Over the past decade, a considerable amount of work has been reported on chemically modified gate oxides for MOS applications. The main goal of chemical modification is to introduce controlled quantities of impurities such as nitrogen or fluorine primarily at the Si/SiO, interface

435

to improve the interfacial properties that are critical to the performance and reliability of SiO, . The Si/SiO, interfacial region consists of a non-stoichiometric monolayer followed by a 10-40 8, thick strained SiO, (Grunthaner and Maserjian, 1978). The non-stoichiometric monolayer results from incomplete oxidation and the strained region is due to lattice mismatch between Si and SiO,, which causes a compressive strain in the interfacial SiO, . Relaxation of intrinsic strain at the Si/SiO, interface is an important technique to improve the reliability of MOS devices under electrical or radiation stresses. It is known that tensile strain exists in Si3N4 in the Si3N4/Si system. This led to an approach which involves incorporation of a small amount of nitrogen in the interfacial region so as to oppose the compressive strain (Vasquez and Madhukar, 1985). Strain relaxation in such nitrided oxides is probably due to the formation of Si,N,O (Vasquez and Madhukar, 1986). Triangular planer bonding in Si,N,O allows a smoother transition from the tetrahedral bonding in silicon to amorphous SiO,. In addition, since the Si-N bond strength is significantly higher than that of Si-H bonds, defect generation by hot carriers and ionizing radiation is suppressed. The other important advantage of introducing nitrogen into SiO, is the improved diffusion barrier properties to boron penetration, an extremely important requirement for p -polysilicon-gated surface-channel p-MOSFETs (Lo and Kwong, 1991). Incorporation of fluorine at the Si/ SiO, interface is another approach to modify the properties of MOS system. Fluorine has been suggested to satisfy some of the dangling bonds at the Si/SiO, interface (Wright and Saraswat, 1989). In a conventional process, the dangling bonds are satisfied by hydrogen during the sintering step. Since the bond strength of Si-F +

436


bonds (5.73 eV) is significantly higher than that of Si-H bonds (3.17 eV), defect generation by hot carriers and ionizing radiation is suppressed. Moreover, fluorine incorporation leads to strain relaxation at the interface (da Silva et al., 1987). Both these approaches to chemically modify thin oxides have been extensively studied. Annealing of gate oxides in NH, (It0 et al., 1982a; Lai et al., 1983) has been reported to achieve such desirable properties as good resistance against impurity diffusion (It0 et al., 1982a) and endurance against hot electron stress (Lai et al., 1983). Rapid thermal nitridation (RTN) is an attractive approach due to its low thermal budget requirement and good control over the resulting nitrogen profile (Mosleh and Saraswat, 1985). Reoxidation (Hori et al., 1989; Yang et al., 1988; Dunn and Scott, 1990; Joshi et al., 1992) or inert gas annealing (Wright et al., 1990) was proposed to reduce electron trap and fixed charge density in the nitrided oxides while still retaining the nitrogen-rich layer at the Si/SiO, interface. However, the electron traps induced by residual nitridation cannot be eliminated completely by reoxida-

tion or annealing, resulting in worse reliability in p-channel MOSFETs (Momose et al., 1991). The reoxidized nitrided oxides used in this case were prepared by rapid thermal processing after the conventional oxide growth. It turned out that reoxidized nitrided gate oxides are superior to pure oxides in numerous aspects. However, the presence of residual nitridation induced electron traps is a shortcoming in these dielectrics and, as a result, pMOSFET reliability is worse than that of the conventional gate oxide MOSFETs. The disadvantage can be avoided by using light N H ,-nitridation, but such light nitridation may not be sufficient to prevent boron penetration into the channel region. This trade-off is depicted in Fig. 9-16 (Momose et al., 1991). Compared to NH,-based processes, the N,O-based processes have an important advantage in addition to the process simplicity, Le., the elimination of any hydrogen-containing species during processing. Therefore, the hydrogen-related disadvantages can be avoided. Depending on process design, thermal budget limitation, and device applications, several processes have

Figure 9-16. Performance and reliability of RTN/ RTO S O , as a function of nitrogen concentration.


been developed to use the significant advantages offered by N,O process. These include

500

437

1 L

i?

Oxidation of Si in pure N,O (Lo et al., 1991); Nitridation of thermally grown SiO, in N,O (Ahn et al., 1992a); Densification and Nitridation of CVD SiO, in N,O (Ahn et al., 1992b); Nitridation of N,O oxides in NH, for p+-poly-Si gated P-MOSFETs (Yoon et al., 1993).

Figure 9-17. Comparison of the growth kinetics between N,O and 0, oxidation of Si.

The oxidation process is self-limiting compared with 0, oxidation, as shown in Fig. 9-17, allowing growth of ultrathin oxides with excellent thickness controllability. The process is simple, hydrogen-free and easy to integrate into modern ULSI processes. Because of nitrogen incorporation at the Si/SiO, interface during N,O oxidation, the resulting oxynitrides show lower hole trap density, reduced electron trap generation under high-field stressing, and reduced interface state and neutral trap generation under both hot-carrier stressing and X-ray irradiation in comparison to the control oxide. NH, nitridation of N,O-oxides does not reduce electrical and reliability properties of N,O-oxides, with the additional advantage of significantly improved resistance to boron penetration. Finally, study of hot-carrier related reliability in both n- and p-MOSFETs with N,O-based gate oxides under application specific stress conditions such as for SRAM-type pass transistors, CMOS logiccircuit transmission gates and CMOS analog devices shows that all the hot-carrier induced damages (Le., interface states, electron/hole trapping, and neutral electron traps) are greatly suppressed in N,Obased gate oxides compared with control oxide devices (Yoon et al., 1993). These results suggest that N,O-based gate oxides

are promising for numerous MOS ULSI applications. Fluorine incorporation in the gate oxide has been performed by different techniques, such as immersion of Si wafers in H F prior to gate oxidation (Nishioka et al., 1988), F ion implantation (Lo and Kwong, 1991 ; Nishioka et al., 1989) and NF, purge during or before gate oxidation (Lo et al., 1992). Different techniques produce different distributions of fluorine in the gate oxide, resulting in a wide variation of electrical properties. Since excessive fluorine incorporation in the oxide can lead to worse dielectric properties (Lo and Kwong, 1991; Nishioka et al., 1989), excellent control over the amount of incorporated fluorine is necessary which can be achieved by rapid thermal processing (RTP). Fluorination has been reported to increase fixed positive charge but suppress interface state density (Nishioka et al., 1989; Lo et al., 1992). Wright and Saraswat (1989), on the other hand, reported a negative charge in the fluorinated oxides. The reduction in interface state density has been attributed to passivation of dangling bonds at the Si/SiO, interface by fluorine (Wright and Saraswat, 1989; Nishioka

-

-

-

300 400

L

c

100 0

0

1

200

"

0

" " " ' " " ' " " ' " ' ' 1 " '

20

40

60

80

100 120 140 160

Oxidation Time (min)

438


et al., 1989: Lo et al., 1992). whereas the increase in positive charge is due to the formation of nonbridging oxygen defects by incorporation of fluorine in the oxide. Wright and Saraswat (1989) reported that the hot electron induced degradation in MOSFETs is considerably suppressed with an increase in the amount of fluorine incorporated in the gate dielectric. Lo et al. (1992), on the other hand, reported that both the amount and distribution of fluorine in the gate dielectric affect the hot carrier reliability of fluorinated oxides. Only a small process window was observed to result in improved hot carrier reliability as well as radiation hardness as compared to pure oxides. Moreover, the presence of fluorine at the Si,SiO, interface was found to be essential in order to realize a gate dielectric with superior reliability. The improvement in radiation and hot carrier immunity in fluorinated oxides has been mainly due to suppressed interface state generation. Interfacial fluorine incorporation has generally been accepted as a cause for the improvement (Ma and Dressendorfer. 1989). 9.4.4 CVD and Stacked Oxides

Deposition of gate oxide, rather than its growth from the substrate, is an attractive technique to suppress the density of defectrelated breakdowns in oxide films because the deposited oxides are less likely to be affected by the defects from the Si substrate. Another advantage of this technique is the feasibility of low temperature processing, which is an attractive feature from the viewpoint of stringent thermal budget requirements in ULSI MOS processing. Various CVD oxides such as TEOS, HTO, and LTO have been studied (Tseng et al., 1993). Ahn et al. (1992b) investigated hot-carrier reliability of MOSFETs with

z 65 8, LPCVD gate oxides (silane and oxygen reaction) annealed in presence of N, . The compressive stress in the films after post-deposition annealing was observed to be smaller than conventional thermal oxides, and was suggested to be the cause of improved current drive capability as well as hot-carrier reliability. In a recent report (Ahn and Kwong, 1992), N 2 0 post-deposition is used instead of the conventional N, annealing in order to incorporate a small amount of nitrogen at the Si/SiO, interface. The resulting films show superior hot carrier reliability due to nitrogen at the Si/SiO, interface as well as low defect density due to the deposition of oxides, rather than growth from substrate. Roy et al. (1988) studied oxide films containing a stack of a “pad” oxide and a CVD oxide on top of it. The dramatic reduction in defect density observed in this stack layer was mainly attributed to misalignment of defects in individual components of the stack. Moreover, the stress at the Si/Si02 interface is close to zero due to the stress compensation between component layers. Kawamoto et al. (1987) demonstrated stacked layers with performance comparable to thermal oxide films. 0 stacked Tseng et al. (1991) used ~ 1 4 8, CVD oxides (40 8, thermal oxide and 100 8, LPCVD/TEOS) for 0.5 pm CMOS process and demonstrated several advantages. Firstly, the number of low field breakdowns was significantly smaller than for the conventional thermal oxides. In addition, due to the smaller levels of stress at the SiiSiO, interface, a large reduction in process induced damage was observed. An optimum ratio of bottom thermal oxide thickness to the top CVD oxide thickness was reported to achieve longer time-tobreakdown and lower defect density. The optimum ratio is a consequence of the compensation between the intrinsic defect

9.5 Shallow Junction Formation

densities of the two layers and the mismatch mechanism. The use of oxide and Si,N, in a gate dielectric stack (ON (oxide/nitride) or O N 0 (oxide/nitride/oxide)) can yield two advantages. Firstly, as in the case of stacked CVD and thermal oxide, the misalignment of micropores in the individual components acts as an effective “seal” to prevent the early gate dielectric failures (Roy et al., 1988). Secondly, the use of Si,N, increases the effective dielectric constant of the film and serves as effective barrier against boron penetration. Iwai et al. (1990) studied the hot carrier immunity of MOSFETs with stacked ON gate dielectrics. It was observed that by reducing the top nitride thickness to about 3 0 & the charge trapping in stacked layers can be significantly reduced and can be comparable to a conventional thermal oxide film. Dori et al. (1987) used ON dielectrics for a dual gate process and demonstrated that the top nitride layer is an effective barrier against boron penetration, which facilitates the fabrication of p +-polysilicon gated p-MOSFETs. In addition, these dielectrics showed a tighter E,, distribution than the conventional thermal oxides. Reduction in electron trapping by reducing the top nitride layer thickness was reported, as also stated by Iwai et al. (1987).

439

9.5 Shallow Junction Formation A significant requirement in high-performance semiconductor technologies is CMOS source/drain junction depth reduction to suppress MOS punchthrough leakage and to minimize device short channel effects such as drain-induced barrier lowering (DIBL) in CMOS devices. Device junctions with relatively high surface dopant concentrations, ultra-shallow depths, low contact and sheet resistances, and low junction leakage currents will be critical for advanced CMOS technologies. It has been projected that ultra-shallow junctions with junction depth 2 : l), film conformality is a critical issue. Collimated sputtering technology has been developed to deposit low resistance Ti and TiN films to improve the contact coverage. A collimator, whose aspect ratio is 1.O, is placed between the sputter target and the wafer so that the wafer can collect the fraction of Ti clusters with normal incidence angle to the surface of the wafer. The problems with collimated sputtering have been shown to consist of no deposition on the side of the contacts, low deposition rate, and particles generation from the collimator. CVD TIN becomes a viable alternative, since these films can be almost 100% conformal. It is also possible to completely fill sub-micrometer contact holes. Traditional CVD TiN processes involve the reaction TiCl, + N, + H, at 1000°C or TiCl,+NH, (6 TiCl,+ 8 NH, --t 6 TIN +24 HCl S N , ) at lower

Several methods have been proposed for TiN deposition, including sputtering, reactive evaporation, thermal nitridation of pure titanium and CVD. Recent results have shown that high quality TiN/TiSi, bilayer can be formed using Ti-rich TIN films deposited from a single TIN,,, alloy target followed by rapid thermal nitridation. Excellent contact resistance and junction thermal stability as well as tight control over the stoichiometry of the sputtered films have been demonstrated, as shown in Fig. 9-23 (Nakamura, 1993). Reactive sputtering of Ti in the presence of N, results in films with low stress and high adhesion (Circelli and Hems, 1988; Stimmell, 1986). The metallization scheme typically included a 10 to 30 nm thick layer of pure titanium, 80 nm and 120 nm thick layers of TiN and 800 nm of aluminum-I YOsilicon. TIN can also be formed by thermal nitridation of titanium in the presence of NH3

@O

4 8 12 16 Breakdown Voltage [ V ]

20

( M .> l O b A )

'0

4

8

453

12

16

20

Breakdown Voltage [ V ]

(M: >IObA)

Figure 9-23. Breakdown voltage distributions of pure Ti and Ti(N0,J samples after (a) 450°C. (b) 525°C annealing.

454


temperatures (Price et al., 1986; Kurtz and Gordon, 1986). Since TiC1, and NH, react at room temperature to form a solid product, it is difficult to mix the gases and introduce them to the reactor without gas phase nucleation. I t has been found (Price et al., 1986: Kurtz and Gordon, 1986) that these two gases neither react in the gas phase nor deposit any TIN film on surfaces in the temperature range of ~ 2 5 0 - 3 5 0 ° C . Based on this fact, both a low-pressure, hot-tube system at 700°C and an atmospheric pressure. cold-wall tube reactor and deposited films at 500-650°C were developed. More recently, a number of studies have demonstrated that the TiCl, + NH, reaction could be carried out in a low-pressure, cold-wall. single-wafer reactor at similar temperatures and high deposition rates (500-1000 k m i n ) (Yokoyama et al,, 1989; Sherman. 1990; Smith, 1989; Buiting et al.. 1991). One group used a reactor with warm (rather than cold) walls ( Z250-350 "C) to prevent deposition on the walls (Smith, 1989). Although resistivity of these films is considerably higher than bulk TIN, it can be kept quite low when depositions are done at higher temperatures. Values from 100 to 300 pR cm are typical, with the lowest values observed at the highest temperatures. Excellent diffusion barrier properties have been demonstrated (Sherman, 1990; Reid et al., 1991; Travid et al., 1990) between silicon and aluminum. Contact resistance of = R cm were obtained for TiN deposited onto titanium silicide (salicide) contacts and p'-Si (Sherman, 1990; Travid et al.. 1990) with excellent leakage current. A number of studies have shown that conformality for TiN can be outstanding, even for sub-micrometer trenches (Yokoyama et al.. 1989; Sherman, 1990; Smith, 1989; Buiting et al., 1991). Rather than using TiC1, as the Ti precursor in

CVD TiN, one could use an organometallic molecule, thereby avoiding chlorine contamination. Two choices are available. One possibility would be the use of tetrakis (dimethylamido) titanium, Ti(N[CH,],), and pyrolize it to yield TIN, since the molecule already contains nitrogen. It has been shown that a more successful approach involves reduction with NH, (Fix et al., 1989). In this case, deposition in an atmospheric-pressure, cold-wall tube reactor at 200-400°C yielded reasonably pure stoichiometric films. Another approach would be to use biscyclopentadienyl titanium, (C,H,),Ti, again with NH, (Yokoyama et al., 1990). Here, reasonably pure films are reported at deposition temperatures of 450 "C in a low-pressure, coldwall reactor. If either film, when deposited at temperatures 400"C, can be shown to have properties similar to the higher temperature films deposited from TiCl,, they will be better choices than aluminum or silicon. Finally, the deposition temperature can be lowered using a glow discharge. Although a number of studies have shown that this is possible for TiCl,+ N, + H, or TiCl, + NH,, they all result in a large amount of chlorine incorporation. One exception has been reported where a TiCl, NH, mixture was excited at 13.45 MHz, and the chlorine content of the film was found to be quite low at 400°C (Hilton et al., 1986). The performance of MOS ICs depends on several parameters, of which the RC time constant is probably the most important. As the size of MOSFET devices decreases, the RC time delay due to the wiring (metal and polysilicon layers) that is used to contact the device gate, source, and drain, does not scale with the shrinking of the physical dimensions of the device. Therefore, for downscaled MOSFETs, the RC speed enhancement can be leveled by

+

+

455

9.6 Metallization

the time delay due to the wiring. Selfaligned silicides (SALICIDEs) including PtSi, TiSi,, CoSi,, MoSi,, and WSi,, have been reported to simultaneously form silicide on source/drain and diffused interconnections with the gate. The conventional SALICIDE process flow for n-channel MOSFETs fabrication consists of the following steps. The sidewall oxide spacers are formed after polysilicon gate patterning, lightly-doped source/drain ion implantation, and activation. A thin metal film chosen to form metal silicide is then deposited to cover the entire surface area. Metal silicide is thermally formed at both polysilicon gate regions and source/drain diffusion regions. A selective etching process removes the unreacted metal from the silicon dioxide surfaces but does not attack the metal silicide. A layer of doped glass (BPSG or PSG) is then deposited, followed by flow, contact window opening, reflow, and A1 metallization. For noble and near noble metal silicides, the metal is the dominant moving species during the reaction. This reduces the probability of bridging between gate and source/drain because of less lateral silicide formation. One major disadvantage of no-

ble and near noble metal silicides is the high temperature limitation. This temperature limitation can be relaxed by the use of refractory metal silicides, due to their high temperature stability. The use of TiSi, and CoSi, in SALICIDE technology has received considerably more attention than other metal silicides because of low resistivity, good adhesion, and high temperature stability. A comparison between CoSi, and TiSi, is shown in Table 9-9. Using the conventional TiSi, SALICIDE process for CMOS applications causes several problems, including the formation of native oxide at the metal/Si interface which slows down the reaction and results in a rough silicide surface, critical ambient control, lateral silicide growth, different amounts of Si consumption in p-channel and n-channel devices, and non-ohmic contacts due to significant dopant redistribution during silicide formation. The native oxides at the TijSi interface cause the reaction to proceed in a non-uniform fashion, resulting in a rough silicide surface. In addition, a high concentration of As at the Ti/% interface retards titanium silicide formation. Therefore, the growth rates of titanium silicides formed on n + (As doped)

Table 9-9. Comparison of the properties of CoSi, and TiSi,. Properties Resistivity (pR/cm) Metal-dopant compound formation Thermal stability on single crystal Si Thermal stability on polysilicon (undoped) Mechanical stress (dyneicm') Reaction temperature with SiO, ("C) Dominant diffusion species during silicide formation Sheet resistance control Resistivity to dry/wet etching Native oxide consumption Thermal stability in the Al/silicide/Si system Lattice match with Si

CoSi,

TiSi,

10-15 no good poor (8-10) x lo9 > 1000 "C

13-16 Yes good poor (2-2.25) x 10" 700 "C Si poor poor good poor poor

co good good poor poor good

456


and p + (B doped) regions are different, resulting in different amounts of silicon consumption in the diffusion regions of pand n-channel MOS devices. Furthermore, significant amounts of dopant redistribution in source and drain areas occurred during SALICIDE formation, which makes the ohmic contact resistance very difficult. The above mentioned problem is avoided in the source-drain extension structure (Taur et al., 1993). in which shallow p + (or n - ) source-drain extensions are used in conjunction with deeper p + (or n + ) source drain regions implanted after thick oxide spacer formation. as shown in Fig. 9-24. The shallow extension depth is decoupled from the deep junctions required for the SALICIDE process. A 600 8, deep p + source-drain extension has been fabricated by Sb pre-amorphization and low energy BF, implantation (Taur et al.. 1993). Another approach is to use selective silicon deposition to form raised sourcedrain structures (Mazure et al., 1992; Kotaki et al.. 1993). Issues with SEG elevated S:D structures and technologies are: capacitance increase, effects of faceting.

9.6.3 Interconnections The reduction in interconnection feature sizes has lead to reliability degradations

caused by electromigration and stress-induced migration. The increase in wiring resistance as a result of the increase in chip size has been solved by increasing the number of interconnection levels. To meet this requirement, the thicknesses of both conductors and inter-layer dielectrics have been kept constant to reduce parasitic resistances and capacitances, making contact- and via-hole aspect ratios greater than one. Therefore, new contact- and viahole filling technologies as well as highly reliable multilevel interconnection conductor systems will be required. An example of interconnection materials and technologies for 256 M D R A M is shown in Table 9-10 (Kikkawa, 1992). As traditional interconnection materials AI as well as various alloys of A1 have been used. Aluminum has a number of ideal properties: (1) low resistivity (eBulk = = 2 . 8 pi2 cm); (2) excellent adhesion to S O , : and (3) excellent wire bonding properties. However, because of its very low melting point (660 "C), electromigration occurs at relatively low temperatures and low current densities. Electromigration of A1 atoms takes place at the grain boundaries within the metallization line. The electron stream creates a flow of these atoms because they are less tightly bound than those within grains where the atoms are bound in lattice positions. Because the atom flow

n-WELL p - T Y P E SUBSTRATE

Figure 9-24. Schematic cross-section of 0 1 prn CMOS devices with source drain extension structure for sil!c ided J anctions

457

9.6 Metallization

Table 9-10. Interconnection materials and technologies for 256M DRAM (Kikkawa, 1992). Interconnection Word line Bit line Bit contact Capacitor contact Peripheral contact

Material

Process

Design rule

Aspect ratio

WSi,,poly-Si WSi, N * poly-Si N + poly-Si W/TiN/Ti

sputtering/LP-CVD sputtering doped LP-CVD doped LP-CVD blanket W-CVD collimated sputtering reflow sputtering (L. T.) collimated sputtering reflow sputtering (H. T.) collimated sputtering sputtering

0.25 0.25 0.25 0.25 0.3

1-1.4 0.5-1.0 2-4 3-6 3-4

0.3

3-4

0.3 0.25

3-4 1-2

0.25 0.6

1-2 1-1.5

0.6

1-1.5

AI-Ge/TiN/Ti

Metal line

Via-hole

Al-Si-Cu/ TiN/Ti TiN/Al-Si-Cu/ TiN/Al-Si-Cu/TiN cu W/TiN/Ti Al-Ge/TiN/Ti

sputtering blanket W-CVD reactive sputtering reflow sputtering (L. T.) reactive sputtering

occurs along the grain boundary in the direction of electron flow, a grain boundary that extends completely across the metallization pattern (“bamboo” structure) should have greater electromigration resistance. However, this type of structure is not manufacturable. The practical method of reducing grain electromigration is to introduce impurities, such as Si and Cu, that passivate the grain boundaries. The additions of high percentages of Cu make alloys difficult to etch and prone to corrosion problems; therefore, large numbers of circuits are still being made with A1 (1 ‘Yo Si) or A1 (1 YOSi) with a small percentage of Cu ( lo2’ cmW3have been created with carbon doping, although the use of the term “impurity” might be better replaced by “alloy component” at these levels. It should be noted that this is a doping tour-de-force since the electrical and physical properties of the GaAs degrade markedly for concentrations of carbon above 5x 1019 cm-’ (Georgeet al., 1991).Theminimum concentrations are highly dependent on the growth apparatus as the background impurity concentrations and native defect structures in the epitaxial layers determine the minimum detectable change in the doping level. Recently, using gas-source epitaxial (GSMBE) methods, carbon concentrations above lo2’ cm-3 have been realized in GaAs (Abernathy et al., 1989), although the same caveats exist for high doping levels independent of the crystal growth method. Epitaxial growth processes provide significantly better control of the depth distribution of impurities than ion implantation, but, until recently, have had limited selected-area control capabilities. CBEIGSMBE methods are actively being explored for selected area growth (Tu, 1995; Shiralagi et al., 1996). The issues which limit the selected area growth are nucleation and growth phenomena and contamination in the patterned areas, as well as control of the growth rates on the various crystal planes exposed by the

-

51 4

10 Compound Semiconductor Device Processing

patterning. Recent advances in MOCVD have also shown some capability for controlled selective area growth (Linden, 1991 ) . As was shown in Fig. 10-7, the device transfer characteristics are significantly better for epitaxy-based devices than for ion implanted structures. This is due to the tightly controlled charge distribution in a heterostructure device. Sidegating and backgating are also better controlled in heterostructure devices, as the charge distribution is readily isolated by etching or ion implantation processes. This latter point is illustrated in Fig. 10-l l . Principally, the performance improvements come from the significant differences i n the charge distributions, the ability to isolate devices (interaction of the chemical species as well as damage), the creation of atomic displacement damage, and the interaction of the substrate and the charge distribution during device operation [see D’Avanzo (1982), Vuong et al. (1990)l. When doping compound semiconductors, many factors must be considered. The

O h

process of ion implantation is of relatively low cost compared to epitaxial layer growth. This cost saving is due to a high wafer throughput relative to all other methods of creating an active layer, which is a significant point for fabrication costs. Also, the uniformity and reproducibility are adequate for most applications, the trade-off coming in the ability to create the tightly-controlled charge distributions required for ultra-high performance devices. However, as high volumes of epitaxial materials are being consumed and manufacturers add epitaxy capabilities, the material prices are falling, so reducing the offset in the final manufactured costs. The performance of epitaxy-based devices is typically far superior to that realized in ion implanted devices for a given set of design rules and circuit configuration. The performance advantage and yield improvements offered by epitaxial materials easily offset the higher costs of processing epitaxial materials for a number of applications. Furthermore, epitaxy-based heterostructures such as HBT, HEMT, VCSEL,

Ids 200rm

I

\

100

a0

51 7

L

Direction

Direction GaAs Substrate

cl oo>

t

Direction

Direction

GaAs Substrate

stand and control the etching process to produce the desired mesa or trench configuration. Etching characteristics, substrate crystallographic properties, and device implications were discussed, for example, by Lee (1982). Etch stop technology, as implemented in epitaxial materials, can be used very effectively to assist in the formation of isolation structures. An effective etch stop layer can provide precise location of the mesa ledge or trench bottom resulting from arresting the etch process, and provide extremely robust processes, for example, greater than 10000 to 1 selectivity in the InGaP-GaAs system (Ren et al., 1995). The ability to force the etchant into very fine features, i.e., liquid surface tension or gas pressure/density effects, limits the minimum spacing between devices and features. Similarly, to remove the reaction products or to dilute the etchant and arrest the etching process is particularly difficult for high aspect ratio, or closely spaced, features. (Details of etching chemistries and

Figure 10-14. Anisotropy of GaAs as revealed by chemical etchants. The limiting crystal planes are of [ 11 1 ] type, with arsenic or gallium planes exposed. This results from the nature of the zincblende crystal structure.

processes are presented in Sec. 10.5) As a result, devices must be separated to accommodate these process limitations at the expense of valuable semiconductor area. Thus the packing density and the integration level of the circuit are generally more limited when mesa isolation is used as opposed to ion implantation processes. Redeposition of the host materials or masking materials may occur during the etching process, which may inhibit the formation of well-controlled mesa morphologies, creating curved or corrugated surfaces, nonuniform mesa definition, leakage paths, etc. These effects must be avoided to successfully isolate devices with mesa technology.

10.3.2 Ion Implantation Isolation With ion implantation, the object is to render the material semi-insulating or highly resistive by the formation of deep levels and recombination centers resulting from the ion bombardment. Use of this

51 8


technique has the powerful advantage of maintaining surface planarity, which makes the definition of very fine features and multi-layer metallizations relatively straightforward. Thus better process integrity and greater complexity can be achieved with ion implantation as opposed to mesa etching methods. For successful isolation selection of the ion species. control of the ion flux, beam purity, and the ion energy are critical. The ion penetration depth is proportional to the ion energy, ion mass and host lattice atomic structure, molecular weights and composition. The concerns associated with ion implantation, as discussed in Sec. 10.2.1. are ion channeling, straggle, and tailing of the depth profile. However, for isolation processes it is usually desirable to extend the isolation as deeply into the substrate as possible, thus tailing may be a desirable feature

in this case, as shown in Fig. 10-15. The efficacy of the isolation is a function of the chemistry between the host and the implanted ions as well as the formation of defects. Some of the important ion implantation ranging data are summarized in Table 10-3 for a GaAs host crystal. Boron, hydrogen (protons), and oxygen are very effective species for ion implantation isolation. The isolation effect is created by the displacement of host-lattice atoms, the creation of a myriad of defect complexes, and the reactions of the host species with the implanted ions (e.g., A1-0 complexes in AlGaAs) (Donelly, 1981; Short and Pearton, 1988). Commonly used ions are oxygen, boron. and protons (H+) (Pearton et al., 1987; D’Avanzo, 1982). It is generally desirable to use heavier ions for the isolation implant, as greater atomic displacement occurs in the host. However, a significant com-

Figure 10-15. Ion implantation isolation schematic diagram. The peak of the ion range (R,) is the approximate position of maximum isolation. The displacement damage peak (maximum atomic displacement) will be some what shallower or deeper than R,. depending on the host and implanted species atomic numbers, the dose and the energy of the implantation. The approximate extent of the isolation is shown. Additional displacement occurs at the end-of-range. increasing the effective isolation depth.

519

10.3 Isolation Methods

Table 10-3. Ion-implantation ranging data for selected ion species in GaAs single crystal material Energy (keV)

20 50 100 1 so 200 300 380

Element

H

B

C

0

Si

0.21810.099 0.480/0.144 0.86610.181 1.233/0.205 1.60710.275 2,42310,262 3.16 110.292

0.04410.034 0.12410.070 0.25510.1 15 0.38210.145 0.50410.170 0.73310.207 0.90510.229

0.03910.030 0.101/0.060 0.20810.098 0.31310.125 0.41 510.147 0.60610. 182 0.75110.203

0.03010.022 0.07510.045 0.1.5410.076 0.23310.100 0.31610.121 0,46210.152 0.56710.172

0.018/0.013 0.04210.025 0.08510.044 0.12910.061 0.17410.074 0.26310.100 0.33310.117 ~~

a

Gibbons et al. (1975); data are in micrometers; data are presented as depthlstandard deviation.

promise in the achievable depth arises for heavy ions at practical ion energies. Light ions, particularly protons, can be used for very deep isolation requirements if relatively high doses are required. The implanted ions may create a variety of atomic displacements in the crystal lattice. It is desirable to create defects which act as recombination centers to prevent or inhibit the transport of charge between devices. As mentioned in Sec. 10.2.1, these defects consist of atomic displacements, vacancies, interstitials, a variety of defect complexes, and antistructure (resulting from atomic site exchanges). Each defect alters the electrical characteristics of the host material, and in the aggregate serve to create the insulating regions between devices. At very high doses the lattice may be disordered to the point of amorphization. This can occur in GaAs at fluxes greater than l O I 5 cm-* for oxygen or boron; protons require much larger doses (greater than 10l6 ~ m - ~ “Softer” ). materials such as InP amorphize at slightly lower doses; hard materials like GaP or S i c require higher doses. Excessive damage can create a conductive region instead of insulating characteristics. In this case, extensive annealing may be required to recover the damage. It should be

noted that there are significant tradeoffs in the dose-energy relationships in the implantation process: simply increasing the dose or energy may actually enhance the interaction and leakage between devices, and also increase surface leakage due to excessive damage. The large density of states created with high dose implants may permit hopping conduction and tunneling processes for charge transport. A light dose implant may not create sufficient recombination centers to be effective; a low energy may create insufficient displacement damage or too shallow an isolation region (current flows underneath the isolation region). Each ion species has a unique “signature” in the isolation process. For example, B+ ions remove up to 200 electrons per ion when implanted into GaAs at 1 MeV (Davies et al., 1973). Oxygen ions, while less effective than B at removing electrons on a per-ion basis, have proven to be extremely effective at isolating GaAs and particularly AlAs or AlGaAs-containing structures (Favennec, 1976; Pearton et al., 1987; Short and Pearton, 1988; Ren et al., 1990). Oxygen produces a deep level in GaAs (Fig. 10-3, Sze, 1981, Chap. l), which captures electrons and may create a high resistivity characteristic with sufficient dose. In the Al-

520


GaAs material A1-0 complexes are formed which are highly effective recombination centers (Pearton et al., 1987; Short and Pearton, 1988). Protons are the ion of choice for deep isolation schemes (D’Avanzo, 1982). Being of low mass, the proton may be injected deep into the lattice even at modest energies, e.g.. beyond 2 p m at an energy of 250 keV (Gibbons et al., 1975). It is interesting to note that the damage profiles do not generally coincide with the ion profiles due to the large mass differences between the host and most implanted species. This discrepancy is greater as the mass difference between the ion and the host atoms increases. Owing to the approximately Gaussian nature of the ion and damage distributions i n the lattice, multiple implant se-

quences are generally needed to achieve a relatively smooth, total ion damage profile into the depth. This is illustratedin Fig. 10-16. When properly placed within the host lattice, multiple implants create a quasi-uniform, high resistivity volume in the implanted region. The drawback with the use of multiple implants is that the surface damage can be extensive, particularly at high doses or high energies, as well as extending process times and increasing macroscopic surface defect densities. The surface damage can lead to surface leakage paths or nonstoichiometric surface regions. For example, surface resistivity has been observed to fall by more than three orders of magnitude when very high energy isolation implants are carried out in GaAs (Liu et al., 1980).

Figure 10-16. Multiple implant isolation profile. I n this case. ion implantation cycles are carried out at different energie5. The deeper implants are performed at higher energies. End-of-range damage increases the isolation effectiveness and helps to smooth the net damage profile. With a large ion flux some amorphization or damage of the surface region may occur. A mild thermal anneal may be required to recover the crystal structure and stabilize the displacement damage profile without recovering the isolation effects.


One very powerful advantage of ion implanted isolation is that selected areas with complex geometries can be readily formed by patterned masking. Use of the selected area ion implantation methods for active region and isolation region formation allows for optimizing layout compaction and device isolation in the integrated circuit. To withstand very high energy ion bombardment, very thick blocking layers must be deposited on the surface, which can limit fine feature definition. Suitable ion blocks are thick photoresist layers, or photoresists with combinations of dielectrics or thin metals. Photoresist layers of 2-4 ym in thickness are typically employed to block 0, B, or H implants at energies of 100 keV to - 800 keV. With lighter ions, such as protons, the displacement of lattice atoms is significantly less than that obtained with heavy ions. Therefore the recovery of lattice disorder may occur with lower driving forces. For example, the damage created by H' implantation in GaAs anneals out at temperatures above about 400 "C. Protons create only small lattice displacements, and hydrogen diffuses rapidly out of the host leaving few electrically active defects (Pearton et al., 1990), The behavior puts significant constraints on processing temperatures and the viability of proton isolation for all but the lowest thermal budget processes. For most isolation processes a minimal thermal anneal is desirable, typically below -500°C for relatively short times. This "gentle" anneal prevents complete relaxation of the lattice, but eliminates some of the marginally stable atomic displacements and potential leakage paths while maintaining the high resistivity of the isolated region. On the other hand, for ion implantation doping it is necessary to anneal at temperatures in the range of 750"C-9OO0C to permit site selection by the impurities (activation) and

-

521

to remove electrically compensating displacement damage. This raises a conflict between the processes required to form the active layers and the need for isolation. For example, isolating underneath ohmic contact pads is not possible with present ion accelerator technologies. It should be noted that as the implantation process involves charged species interactions and significant energy is transferred to the lattice, the possibility of radiation damage and heating of the lattice during bombardment exists. The energy impinging on the wafer is of the order of hundreds of watts per square centimeter in a high-current implanter. If the wafer temperature rises above - 150-200 "C, the effectiveness of the isolation process may be compromised as lattice displacements can anneal out during the implantation cycle. To minimize the self-heating, it is prudent to implant at the lowest practical beam current and ion energy, or control the substrate temperature during implantation. Electron bombardment can be used for isolation, but the damage created is subject to annealing out at very low temperatures. The annealing of electron-induced damage in GaAs has been observed to occur in two stages: 150-200°C and 200-300°C (Aukerman and Graft, 1967; Vook, 1964). This makes electron irradiation unsuitable for isolation as temperatures in wafer fabrication typically exceed these levels. Neutron damage is another method for isolating regions in compound semiconductors. The typical array of point defects and defect structures are produced by neutron irradiation. The damage induced by neutrons has been found to recover in two stages in a manner similar to electron-induced damage: at 200-300°C (minor displacements), and then recovers fully at 600-700°C (Lang, 1977). Thus the isolation created by neutron bombardment creates a stable isolation re-

522


gion only if processing temperatures are maintained below - 500°C. Beam blocking materials are generally transition metal layers in order to obtain sufficient stopping power for the neutron flux. One additional variation of ion implanted isolation is the creation of an isolation “box” for devices. For example, in devices utilizing n-type implants, a p-type implantation can be placed beneath the tail of the donor distribution. This buried-p layer creates a p-n junction isolation condition. By carefully selecting the dose and energy, the ptype layer can be nearly fully depleted, leading to minimal capacitance, a sharp n-type charge profile, and mitigation of short channel effects (Finchem et al., 1988; Matsunage et al., 1989; Onodera and Kithahara, 1989; Sadleret al., 1989).Typically, the buried p-type implant is used only under the channel region. However, it may be connected to an external bias to enhance the back-plane isolation with a depleted p-n

junction. An additional isolation implant or mesa processing may be used to create the “walls” of the box, thereby completely isolating each device, as illustrated in Fig. 10-17.

10.3.3 Sidegating and Backgating Sidegating and backgating are terms describing the interaction between devices in an integrated circuit laterally and from the back-plane region, respectively. These phenomena have plagued GaAs-based devices for many years (Vuong et al., 1990; D’Avanzo, 1982; Smith et al., 1988a; Lin et al., 1990), and arise from the electric fields induced in the material when the circuits are biased. The effects are realized as a modulation of the transistor channel current or the current flow in channel-resistors (Gray et al.. 1990; D’Avanzo, 1982; Goto, 1988). The problems associated with sidegating and backgating are greatly influenced by the circuit layout, and, in particular, the spacing

Figure 10-17. A cross section schematic diagram of an FET isolated by ion implantation processing (or mesa etching). The device has a buried-p layer connected electrically to the low potential of the device. This addition serves to mitigate sidegating effects. The buried-p layer must be contacted through an additional p-type ion implantation adjacent to the nc contact implant (or diffusion). The gate is offset in the channel to reduce source resistance.


and differential voltages between nearby devices and the condition of the back-plane (biased or grounded). Additional phenomena in sidegating and backgating effects are the transient charging and discharging of deep states. Electric fields, such as those created in p-n junctions, implanted isolation regions, ohmic contacts, depletion regions (e.g., Schottky barriers), etc., all lead to exposure of the various deep level states (traps), relative to the Fermi level, which lie in the semiconductor energy gap as shown in Fig. 10-18 (see also Milnes, 1973, and Sze, 1981, Chap. 1). As the electric fields are altered first by biasing, then modulated during device operation, the deep traps charge and discharge as the bands bend. This leads to a secondary modulation of the charge transport in the devices, with response transients of sub-microseconds to minutes in duration, and strong temperature dependences.

Semiconductor Surface

f

II

523

Several competing processes may arise from these deep levels in or near active device regions: l ) charge domains may be launched from a source (anode) contact under moderately high electric field conditions, and 2) DC and AC electric fields may modulate the deep state charge conditions (Milnes, 1973). In GaAs, for example, charge domains may be created and injected from ohmic contacts when electric fields exceed 500 V cm-' to 1000 V cm-' between nearby devices (Ridley and Watkins, 1961; Ridley and Pratt, 1965; Kaminska et al., 1982). These charge domains travel through the semi-insulating substrate or buffer layer to the collecting contact (cathode or drain in a FET). The motion of these charge packets induces a time-varying electric field under the gate and thereby upsets the channel charge distribution causing a modulation of the device operating conditions (see, for example, Fujisaki and Matsunaga (1988)).

Increasing reverse bias exposes additional deep states

-

Emitted Charges (Deep Levels Empty) Free charges may be recaptured by deep or shallow states Shallow Donor Level

Fermi Level

\

E3

N-type Semiconductor

Valence Band Edge

Figure 10-18. Schematic representation of the near-surface band bending in an n-type semiconductor. Shallow donors are partially ionized. Deep levels are occupied within 2 k T of the Fermi level, and filled below the Fermi level crossover points. When the state is lifted above E,, charges are emitted at rates proportional to their respective depths, the temperature, emission characteristics, and rate of band bending. The charges may be recaptured during relaxation processes and re-emitted, leading to an oscillatory condition.

-

524


In the case of field effects there are two main components. The DC contribution involves the equilibration of deep state capture and emission processes. This is typically a very slow process leading to long turn-on transients upon biasing, device latch-up, and an “improper” DC operating state. Depending on the material’s condition, these transients may be of the order of nanoseconds to minutes. The details of this quasi-equilibrium condition are affected by the operating temperature, and the temperature distribution in the device through the capture and emission rates and the concentrations of the deep states. The charge exchange processes can produce additional time constants in the temporal response as the device heats during operation. Localized anomalies may arise as different regions of the device may dissipate varying amounts of heat during operation. The AC effects are essentially resonances of the deep state capture and emission rates with the operating frequency of the devices. For example, i n GaAs there are at least 20 known deep levels of electron- and hole-like characteristics in the energy gap (Martin et al., 1977). Thus, for a given temperature, electric field strength (biasing condition and voltage swings), active layer configuration, and circuit layout, a number of traps may be exposed within a device as shown in Fig. 1018. As the device changes state in response to an input, the trap exposure about the Fermi level is altered, and the emission or capture of charges by the trap(s) may be stimulated. This leads to the “resonance” condition. The electrical manifestations of deep levels may be observed as long time constant effects, impaired transient responses, “ringing” in the device characteristics. or an apparent lack of device gain (Lin et al.. 1990; Vuong et al., 1990; Smith et al., 1988b). Similarly, the back-plane or substrate bias can modulate the channel charge distri-

bution in FETs through the electric field created between the back-plane and the channel, thus upsetting the threshold and current-carrying capability in the devices. Again, as the electric fields are modulated, the channel charge distribution responds with multiple time constants determined by the trapping behavior of the exposed deep levels, particularly those at the bufferinterface (epitaxial layers) or in the tailsubstrate of the implant profile. These effects are not subtle: sidegating and backgating phenomena, either static or dynamic, can lead to collapse of the transfer characteristics, or pinch-off resistors and transistors, as illustrated in Fig. 10-19. In extreme cases, sidegating can impact devices separated across an entire 3” (76 mm) wafer (Gray, 1989). The typical manifestations are devices operating well below expected performance levels, or the intermodulation effects as devices switch to different states and the electric fields are altered. These phenomena are well known and relatively well

10. 8-

SIDEGATE 2 pin

$

6.

v

-8

4

2

0

10.4 Diffusion

understood (D’Avanzo, 1982; Vuong et al., 1990; Smith et al., 1988a; Ridley and Watkins, 1961; Ridley and Pratt, 1965; Milnes, 1973). A highly effective method for isolation in GaAs devices has been discovered: a “lowtemperature buffer” (LTB) grown by MBE (Smith, 1988 a). This approach capitalizes on the extensive defect structure created by epitaxial crystal growth at low temperature under strongly nonequilibrium growth conditions. The material produced by this process is nearly completely inactive, both electrically and optically (Kaminska et al., 1989). Smith et al., 1988b, has found that the DC isolation and DC sidegating immunity are greatly improved: negligible interactions are found for DC electric fields in excess of 10 kV cm-’. However, unless other measures are taken to displace device active regions well away from the LTB, the high-frequency performance of circuits fabricated on these buffer layers is drastically affected. It has been found that integrated devices operating at - 1 GHz, as fabricated with “standard” processing methods, are slowed to the kilohertz regime when constructed with the LTB structure without having sufficient isolation from the LTB (Lin et al.. 1990). This effect was attributed to electron trap-related charge capture and emission with very long time constants. To circumvent these problems, a second relatively thick standard buffer layer must be grown on top of the LTB to minimize the effects on charge transport behavior in transistors (Smith et al.. 1988 a,). Subsequently, the devices must be laterally isolated to prevent or mitigate the normal sidegating effects. “Low temperature” buffer layers have been greatly improved in the latter part of the 1990s, and are commonly used in epitaxy-based fabrication processes (Wang et al., 1997). The importance of controlling or eliminating interactions in compound semicon-

525

ductor-based devices continues to drive investigations into the trap-related, semi-insulating characteristics of GaAs and analogous effects in other III-V semiconductors. At the present time, there are methods for mitigating the sidegating and backgating effects, but it appears unlikely given the nature of the compound semiconductor materials and their defect structures, and the desirability of the semi-insulating behavior, that these problems will be totally eliminated.

10.4 Diffusion Diffusion and impurity redistribution are of great importance and consequence in device fabrication processes. Diffusion has been the subject of extensive investigation (Tuck, 1988). The intentional diffusion of impurities is required in numerous fabrication steps. Often, however, the diffusion of impurities and the interactions amongst the various materials present on, and in, the wafer are highly undesirable. As examples, p-n junctions generally become less abrupt and the electrical and physical (chemical) junctions may shift when the impurity species diffuse, or when mixed chemical species interdiffuse, such as with a GaAs : AlGaAs heterointerface. In heterostructure bipolar transistor (HBT) structures, the “misalignment” of the electrical and physical junctions strongly compromises the device electrical characteristics and device performance (Ali and Gupta, 1991). Rapid in-diffusion of gold in an ohmic contact region may cause device failure via punch-through (“spiking”) or lateral migration (Zeng and Chung, 1982). Silicon donor redistribution in HFET devices will alter the channel charge distribution, shift the device threshold voltage, the transconductance (g,), and affect the current carrying ability of the

526


channel (see Daembkes, 1991 and references therein, and Schubert, 1990). The diffusion behavior is characterized by a parameter known as the diffusion coefficient, and is controlled principally by the chemical potentials of the host and impurity atoms in the lattice, and the impurity concentration distribution(s). Defects, such as vacancies, interstitials, impurities, and the relative physical sizes of the host lattice atoms and the impurity, the bond strengths and the dimensions of the lattice interstices all affect the atomic mobilities and the diffusivity of the impurity atoms. Diffusion processes are mathematically represented by several empirical relationships known as Fick’s laws. The first of these laws considers the flux of a diffusing species (in one dimension), J , through a plane in a direction x, at any time (f):

(IO- 1) where C is the concentration, dC/dr is the concentration gradient, and D is the diffusivity. Equation ( I O - 1 ) describes the driving force behind diffusion: a concentration gradient, i.e., a chemical potential difference which, from thermodynamic arguments, must become negligible as the system reaches equilibrium. Equation (10- 1) is illustrated schematically i n Fig. 10-20, The relative ease with which a given species moves in the lattice is embodied in the magnitude of the diffusivity. Fick’s second law relates the change of the concentration profile with time [taking the derivative of Eq. ( I O - l ) ] ( 10-2)

Equation (10-2) describes 1 ) how rapidly the material will redistribute in the host lattice, and 2) the concentration profile as a

I t

Characterized by:

Doe - EanT

\

\

Distance into Semiconductor Surface

Figure 10-20. Schematic diagram of a “erfc” diffusion profile, represented by a single-value diffusion coefficient, D o , and a unique activation energy, E,; k and T have their usual meanings.

function of time and distance. Using the grad operator, Eqs. (10-1) and (10-2) may be extended to accommodate the real threedimensional behavior of the diffusion process in the crystal lattice. Implicit in these descriptions is the temperature sensitivity of the diffusion process, which is accounted for in the diffusivity. The diffusivity is defined as

D = Do exp (- E , / k T )

(10-3)

where Do is the diffusion constant, E, is the activation energy for the diffusion process, k is the Boltzmann constant, and T is the temperature (K). In addition, the diffusivity of an impurity is sometimes dependent on the concentration, typically being enhanced at higher concentrations. Therefore to realize a high degree of stability against elevated temperature processing, it is desirable that an impurity species have a large activation energy, a small diffusion constant (see, for example, Tuck, 1988 or Shewmon, 1963, and be present in reasonably low concentra-

527

10.4 Diffusion

tions (- 100 ppb to 100 ppm) to minimize impurity-impurity interactions in the lattice. The segregation coefficient k for an impurity species is a measure of the tolerance of the host lattice for the impurity atom. It is defined from solidification processes as the ratio of the concentration of the impurity incorporated into the solid relative to that in the liquid phase during crystal growth. With respect to the solid state, the segregation coefficient can be interpreted in terms of the additional driving force for diffusion: A small value of k implies a relatively large energy for redistributing the impurity in the host. [n compound semiconductors most impurities have segregation coefficient values of less than one which represent an additional driving force for the out-diffusion behavior. The crystal lattice is distorted by the presence of the impurity atoms due to size and/or the chemical incompatibility. The extra energy available tends to drive the impurity species from the lattice. The free surfaces, or those surfaces and interfaces under strain due to mismatched physical properties (e.g., heterostructures, dielectric layers, metals, etc.), will also provide added energy for diffusion, and may act as sinks for the diffusing species. Also, the solid solubility limit places an upper limit on stable concentrations of impurities in the lattice: concentration above this level will increase the driving force for redistribution, precipitation, size exchange processes, and electrical compensation. In GaAs it has been observed that the diffusivities of the groups IV and VI donor type species are generally small, whereas the group I1 acceptor species tend to diffuse much more rapidly. Carbon, a group IV acceptor, is a notable exception, being extremely stable in most compound semiconductor lattices (Schubert, 1990; Schubert et al., 1990).

Two additional concerns for the processing of compound materials at elevated temperatures are the increased vibration frequency of the lattice atoms and the dissociation of the compound semiconductor material. The motion of the atoms in a compound semiconductor lattice can create a variety of electrically active point defects (Hurle, 1977; Van Vechten, 1975), and diffusion may cause an undesirable redistribution of the impurity atoms. As a result, the electrical properties of the material may be altered in an uncontrollable manner. For the compound semiconductor materials GaAs and InP, the dissociation rate is significant for temperatures above - 600 “C and 475 “ C , respectively (Panish, 1974), and similarly for GaP and some 11-VI compounds. This is due to the high partial pressure of the group V (or group VI) species over the host material, as illustrated in Fig. 10-21 [after Thurmond (1965)l. The key point in this figure is the region around the congruent decomposition pressure. By controlling partial pressures of the various species the decomposition may be suppressed. Without some mechanism for protecting the surface region during high temperature processing, either with a cap layer or an overpressure of the group V species, the surface rapidly decomposes creating a metal-rich surface, enhanced dissolution of the surface layers, and destruction of the semiconducting properties. It is therefore critical to maintain a minimalistic approach to the thermal processing of most compound semiconductor materials. RTA (rapid thermal annealing) cycles or “low thermal budget” (i.e., lowest possible temperatures and minimal times) processing are needed to maintain the impurity profile and materials integrity in the near-surface region. For successful device fabrication, knowledge of the stability of the donor and acceptor species in the lattice is critical. The dif-

-

528

10 Compound Semiconductor Device Processing 1200 1100 I

lo00

900

800

“C

I

lOVT, 1M

Figure 10-21. The equilibrium vapor pressure (in atm.) of As, Ga, As2 and As, over GaAs as a function of IO‘ T-’. The total arsenic pressure (referred to As,) is approximately 1 atm. (IO’ Nm-’) at the melting point, 1238°C. [Reproduced from Thurmond (1965). Reprinted with permission. 0 1965, Pergamon Press.]

fusion coefficient values for most usable impurities are in the range of 10-3-10-6 cm2 s-’ at the temperatures used for epitaxial crystal growth, ion implantation annealing, and wafer processing, and thus most species move quite rapidly in the lattice (Tuck, 1988, Chaps. 4,5;Shewmon, 1963). For example, one advantage of an epitaxial-grown MESFET device process sequence is the ability to minimize the thermal budget, leading to a limited redistribution of the donor impurities. In contrast, in a similar ion-implanted MESFET process, the thermal budget and maximum temperatures are extremely critical to the impurity distributions and activation. The resulting charge distribution, and the final device characteristics

are greatly affected by processing times of the order of seconds or tens of degrees, particularly for the ultra-thin, ion-implanted structures required for high-speed or low noise operation. On the other hand, high-temperature furnace or rapid thermal annealing of selfaligned MESFET and HFET devices is necessary and readily accomplished when refractory gate metals are used. The limited reactivity and stability of the refractory metals with most compound semiconductors permits the temperature to be raised above 800°C (for GaAs) sufficient to anneal the ion implantation damage, restore the lattice disorder, and activate the implanted species (Dautremont-Smith et al., 1990; Yamasaki et al., 1982; Shimura et al., 1992). At the same time, the impurities which provide charge to the channel may diffuse large distances (tens of nanometers), leading to uncontrolled device characteristics and poor performance, emphasizing the need for strict control and understanding of the timetemperature cycle impact. In other processes, if ion implantation is not used for doping, substantially lower thermal budgets may be used. Si redistribution during annealing processes was investigated in GaAs/AlGaAs heterostructure (HFET) materials (Schubert et al., 1988, 1990). It was found that the diffusivity of silicon was roughly ten times higher in AlGaAs than GaAs at 800°C. This places significant constraints on the device structures, particularly for HFET devices which may incorporate a “setback” (intentional spacing of the impurity species away from the channel region) to keep the ionized donors separated from the electrons that reside in the potential well (Sequeria et al., 1990; Baret al., 1993; Danzilio et al., 1992). In a typical annealing cycle the Si atoms may diffuse more then 5 - 15 nm, thereby placing a significant fraction of the Si atoms

529

10.4 Diffusion

in the channel region. This phenomenon will be realized as a reduced electron mobility and somewhat impaired electrical performance. One of the anomalies in the diffusion behavior of most acceptor species in compound semiconductors is the double diffusion front (Tuck, 1988; Gosele and Moorhead, 1981). In this case the impurity appears to have at least two distinct values for thc diffusivity. These phenomena have been explained in terms of interstitialcy and substitutionality of the diffusing species. Interstitials have significantly lower activation energies for motion in the lattice, and therefore larger diffusion coefficients since there is no requirement for atomic site-exchange to allow motion within the crystal lattice (Gosele and Moorhead, 1981; Small et al., 1982). The interstitial atoms may therefore move very rapidly in the host material. The substitutional impurity, on the other hand, requires the presence of a vacancy or the exchange of adjacent lattice atoms to permit motion of the impurity. Such an exchange process requires the addition of significant amounts of energy, and the cooperative motion of several atoms. The activation energy for such a process is relatively large, the probability of site exchange is small, and the substitutional diffusion process is slow. The double diffusion behavior is illustrated in Fig. 10-22 for zinc in GaAs (after Tuck, 1 9 8 8 ~ )It. is clear that there are at least two mechanisms operating in this case, with significant differences in diffusivity values as well as the relative concentrations of interstitial and substitutional impurities. Several investigations have been carried out to understand the behavior of anomalous diffusers such as Mg, Zn, and Be (Small et al., 1982; Cunnel and Gooch, 1960; Gosele and Moorhead, 1981). At the present time, although the mechanisms for explaining the double diffusion from behavior are well-ac-

I

50

100

150

Depth

200

250

300

(wm)

Figure 10-22. Experimental diffusion profiles for zinc in GaAs at 1000°C. A, B, C, and D represent the zinc concentration profiles after 10 min, 90 min, 3 h, and 9 h, respectively. Note the two unique regions for the concentration profiles in each case. [Reproduced from Tuck (1988). Reprinted by permission of Adam Hilger/ IOP, 0 1988.1 Note: Ordinate axis label corrected from the original publication.

cepted, the precise understanding of the processes by which the species simultaneously select both types of diffusion paths has yet to be elucidated. As device processing continues to improve, more stable species, such as carbon, are being utilized for acceptor doping. However, carbon is not a panacea as the effectiveness for doping in a number of ternary and quarternary compound semiconductors is very limited. As mentioned above uncontrolled impurity redistribution can seriously affect device performance. These effects are often seen in one of the moore promising device structures, i.e., the heterostructure bipolar transistor (HBT) based on GaAs/AlGaAs epitaxy (Ali and Gupta, 1991). Owing to “band gap engineering” (Capasso, 1987,1990)and the properties of GaAs-based and InP-based ternary compounds, an HBT device in these


530

It has been observed that the Be atoms redistribute so significantly in the lattice that this method of doping the p-base region is essentially impractical for use in controlled, reproducible HBT fabrication (Miller and Asbeck, 1985). Streit et al., (1992) claim to have solved the Be redistribution-related degradation problem by controlling certain growth parameters in the MBE growth of HBT structures, although these devices were operated at modest performance levels (Streit et al., 1992). Other p-type transition-metal species also behave in a manner similar to beryllium, but are not generally utilized for this reason. Accelerated device aging tests showed that Be doped base HBTs can be relatively stable to self-diffusion failure mechanisms under low to medium power conditions, as shown in Fig. 10-23 (Yamada et al., 1994). They found failures (under accelerated aging conditions) occurring at - 300 h, 230°C, and an apparent activation energy of - 1.4 eV, which translated to projected operating lifetimes of - lo6lo7 h at a junction temperature of 125°C. Carbon, however, has been found to be very stable in compound semiconductor crystal lattices, and therefore appears to be the practical alternative for p-type doping in

materials is capable of switching in the hundreds of gigahertz, many times faster than the fastest silicon-based counterpart (Nubling et al., 1989; Nottenberg et al., 1989). Many of these HBT devices have been fabricated in MBE-grown epitaxial materials. using Be for the base dopant species (Kim et al., 1988;Miller and Asbeck, 1985; Streit, 1992). Investigations into the performance of Be doped base HBTs and the fundamental processes of diffusion of beryllium in GaAs have shown that this impurity diffuses extremely rapidly (Hafizi et al.. 1990). This poses a difficult problem for the crystal grower and the process engineer, as significant impurity redistribution can occur during crystal growth. During even modest thermal processing, and subsequently during the device operation rapid diffusers can move in the crystal lattice, the latter effect being induced by elevated junction operating temperatures and the extremely high electric fields in the devices (Ah and Gupta, 1991). As a result of the Be redistribution at the emitter-base junction, the p-n junctions shift in an uncontrolled manner rendering the materials unsuitable for device applications (Hafizi et al.. 1990; Yin et al., 1990).

30 0

-30

-60

F

-90

E 2

-120

9 4

-150

-180 -210

I

-240

-

Z15"C/biased 215"C/no bias [hot controll e 25"C/nO bias (controll --t

-

100

I 200

I 300

I

I

400

500

Stress Time (Hour)

I

600

I

I

700

800

Figure 10-23. A plot of the change in output voltage of a HBT-based circuit as a function of stressing time at 215°C. Parts which have not been subjected to current stress are shown as open circles and open squares. Parts which have been biased are shown as closed circles. At 21S°C, the output of the circuit degrades substantially up to 800 h . This indicates a change in the bases emitter junction, or a modification of the emitter contact resistance due to impurity diffusion. (Reproduced from Yamada et al. (1994). Reprinted with permission. 0 1994 IEEE.)

10.5 Etching Techniques

many 111-V materials (Abernathy et al., 1989; Maliket al., 1989; Quinn, 1992- 1993).Carbon may be introduced into the lattice by ion implantation or during crystal growth when carried out with techniques such as metal -organic chemical vapor deposition (MOCVD) or gas-based molecular beam epitaxy methods (chemical beam epitaxy CBE or gas-source molecular beam epitaxy - GSMBE) (Abernathy et al., 1989; George et al., 1991). Several solid-phase carbon sources have been fabricated and used in standard MBE crystal growth (EPKhorus, 1994; Maliket al., 1989). Hole concentrations in HBT base layers exceeding lo2’ cm-3 have been realized without apparent problems with diffusion and redistribution. However, a significant lattice contraction occurs at these high carbon concentrations (above - 3-5x 1019 ~ m - George ~, et al., 1991), with strong reductions in the hole mobility due to scattering events (Quinn, 1992- 1993). The formation of large numbers of line defects in base regions for these high carbon concentrations raises significant questions of long-term device reliability. Owing to the issues outlined in this section, there are only a limited number of solely diffusion-based processes remaining in compound semiconductor technology. For example, the JFET fabrication sequences are hybrid processes using diffusion of the p-type species to create the junction or highly doped p-contact region in an n-type material formed by epitaxy or ion implantation (Zuleeg et al., 1984, 1990; Wada et al., 1989). These diffusion processes are similar to those employed in silicon-based process sequences with the notable exception that they require very sensitive control of the process conditions. This is due to the large diffusivity of zinc or beryllium acceptor species, and the need to prevent dissociation of the host material due to the high vapor pressure of the group V elements.

531

The concern for rapid diffusivities arises also when considering reliability issues significant redistribution of any impurities or defects in the active regions of the devices will degrade performance and lead to field failures (Hafizi et al., 1990; GaAs IC 1992, 1993a). This has been observed in HBT devices, for example, where the performance characteristics decay rapidly as the device is operated under moderate to high stress conditions (Yamada et al., 1994). As previously, noted, the deterioration has been assigned to the redistribution of beryllium atoms in the base region of the device caused by thermal and electric field-aided drift of beryllium ions (Miller and Asbeck, 1985; Hafizi et al., 1990)

10.5 Etching Techniques Material removal may be carried out by “wet” chemistry, or by “dry” (vapor or plasmdsputtering) techniques. Etching processes can be used to delineate the features of active and passive devices, form electrical contacts, gate recesses, and vias, and create isolation trenches. The most critical issue is the ability to create an etched feature which has an optimal morphology compatible with the subsequent processing steps. The choice of wet or dry chemical etching methods depends upon the processing sequence, the required degree of etching control, the materials compatibility, and the availability of a suitable etchant for the target material. In addition, the etchant must not affect the masking or etch stop materials, and the other materials exposed during the etching process. Additional considerations are the control of undercutting of the mask layer (dimensional variation), the creation of anisotropic features, and the permissible process latitude.

532


Various etchants and methods may be used in the process sequence for defining device features or general etching processes. Anisotropy and materials selectivity are critical and very useful features of etchants and the different etching processes. The crystallographic sensitivity of the etching chemistry can be utilized to form selectively sloped side walls for smooth metal coverage or to create a controlled undercut to prevent metal continuity where desired (see Sec. 10.9, liftoff processes). At the same time, the undercutting of photoresist layers or other masking materials by lateral dissolution of the semiconductor, dielectric layers, or metals can give rise to very undesirable expansion or contraction of etched features. Reaction products are important in all aspects of etching, i n both wet or dry methods. Such by-products may impede contact between the etchant species and the surface atoms. They can lead to anisotropic effects resulting from build-up on the various exposed crystallographic planes, or block the etching process entirely. Bonding of the reaction products to the surface may further alter the etching characteristics. In wet processes continual solvation of the reaction products into the solution alters the pH and therefore the chemical activity and the etching rates. In a similar manner, with dry etching, the poisoning of the plasma by reacted species may drastically alter the effectiveness of the etching process. Thus it is important to ensure adequate chemical flows in either wet or dry processes. The understanding of all of these competing effects is a critical element in developing a viable. controlled, and reproducible etching process. For both dry and wet etching processes, the main limitation (in typical compound semiconductor (CS) processing sequences) is the inability to readily etch gold, which is one of the principal metals in CS device fabrication. However, ion milling or liftoff pro-

cesses produce excellent results in gold metallizations, even with very fine geometries. It should be noted that significant efforts have been directed to creating aluminumbased metallization schemes for interconnects (Vitesse, 1990, 1995), and the use of titanium or tungsten-based metals to overcome the limitations of the liftoff processes needed for gold metallizations (GaAs IC, 1993b, Dautremont-Smith et al., 1990). Reactive ion etching or sputtering may also be used for the etching of various layers during processing. In this case, the rate(s) of sputtering the desired material(s) relative to that of the masking material(s) is crucial to the success of the process (Melliar-Smith and Mogab, 1978; Chapman, 1980). The chemical anisotropy of the compound semiconductor materials plays an important role in the formation of etched structures. The shape of an etched feature may be strongly influenced by the polar nature of the zincblende-type lattice and the anisotropic behavior of the etchant. For GaAs, anisotropic effects are further complicated by the existence of two standards for the substrate orientation. These two options are denoted “SEMI US” (wedge) and “SEMI E/J” (dovetail) (SEMI Standards, 1989). Both of these specifications adhere to the same electrical and physical characteristics as the SEMI standards, but they are rotated 90” about the (100) with respect to each other as shown in Fig. 10-24. As a result, the same chemical etchant may produce different (rotated 90”) etching features in the two wafer configurations. Thus, it is critical to understand the interactions of an etchant with the surface layers to ensure the formation of a desired morphology.

10.5.1 Wet Etching

To remove undesired material(s) from the surface region, solutions of appropriate


KOH ETCH PIT

533

1

OF WAF$

Figure 10-24. Crystallographic representations of the two standard configurations for gallium arsenide substrates. The etch pit configurations for each orientation are shown in (b) and (d) and on the central part of the crystal plane image. The etching response of the crystal with respect to the central axis is illustrated by the relative positions of the “V-groove” and “dovetail” etch figures. (a) V-groove option (known as the US standard); (c) dovetail option (known as the E/J standard). Note that the minor flats are 180” in opposition between the two orientations. (Figure courtesy of SEMI, Mt. View, CA, reprinted by permission.)

chemicals (acids or bases and diluents) may be used. The etchant solution must be constantly in contact with the target material, and must typically be stirred or sprayed onto the wafer surface to ensure the constant replenishment of the etchant at the surface and to remove by-product materials (Shaw, 1981; Stirland and Straughan, 1976; Iida and Ito, 1971; Mukherjee and Woodard, 1985). The effects of stirring are typically observed as significant increases in etching rates relative to stagnant solutions, as shown in Fig. 10.25. Without agitation or replenishment, the etchants may produce significant undesired topological changes in the surface. Some means of arresting the etching process rapidly and uniformly must be provided to neutralize the etchant and com-

pletely remove the reacted material(s) in order to ensure reproducibility and control. Wet etching occurs by an oxidation process followed by solvation of the reacted species. The etching solution generally contains both the oxidizer and a solvent, and the CS-oxide species and reactants are preferably readily soluble materials. A complexing or buffering agent may be added to stabilize the etchant chemistry, and deionized water is commonly used as the diluent. A key issue in wet etching control is the boundary layer at the interface between the solution and the semiconductor surface. The schematic representation of the boundary region is shown in Fig. 10-26. The boundary layer controls the etching process through the exchange rates of the oxida-

534


Temperature

10

20

30

40

Figure 10-25. Etch-rate dependence on temperature and forced convection. The etchant is H,SO,-H2O2-H20 (8 : 1 : I ) , with an addition of 50 wt.% citric acid. The ratio of HzOz (3070) to 50 wt.% citric acid is 1 : I by volume ( k = 1 in the figure). It can be seen that the effects of stirring are dramatic, as is the importance of temperature and therefore temperature control of the etchant and the etching rate. [Reprinted from Howes and Morgan ( 1 985). Reproduced with permission. 0 1985 John Wiley and Sons, Ltd. Figure caption modified by author (original data after Iida and Ito (1975). and Otsubo et al. (1976).]

("C)

\

100

Solution

*\.

j

x.\

Slirrinq

4 f

0

k =1

*\

CT

.-C

c V

c

W

I1

I

1

L

I

I

103/T ( K - ' )

Substrate

ConvectiveTransport Region

Material

Turbulent or Laminar Flow

I Msrokcd Specha into Solvent Bulk

I I I

I I

I

tion-dissolution cycle, i.e., the removal rate of the surface materials relative to the arrival rate of fresh reactants to the surface. For extremely critical etching processes such as gate etching (FETs) or the emitterbase junction (HBTs), a weak oxidizer may be applied first, followed by a solvent solution so as to remove only a very thin surface

Figure 10-26. Schematic representation of the region adjacent to a semiconductor interface during chemical etching. The diffusion boundary layer is the controlling region for the transport of species to: and out from, the interface. A similar diagram can be utilized for gas-phase chemistry, with varying mean-free-path lengths and very high convective velocities in the bulk gas phase.

layer rather than maintaining a constant etching process. Repetition of the process results in a step-wise approach to the final gate trough depth and shape. While timeconsuming, this approach can provide an extremely high level of control. Table 10-4 presents a number of liquid etchants suitable for compound semiconductor materials.


Table 10-4. Common etchant compositions for compound semiconductors. Chemical formulation NH4OH

H,02

: H,O

H>SO,: H,O,: H,O

HCI : HNO,

H3P04: H,02 : H,O

Br - MeOH

Ratio

Reference

I : 2 : 20 Shaw (1981) 3 : 1 :50 Gannon and Neuse (1974) Adachi and Oe 5 :1:1 (1983) Shaw (1981) 1:8:40 Adachi and Oe 1: 3 (1983) Adachi and Oe (1983) Adachi and Oe 5 : 1 : 20 (1983) Mori and 1.9.1 Watanabe ( 1 978) Adachi and Oe 1 : 100 (1983)

Choice of a specific chemistry depends on the morphology and degree of control desired in the fabrication sequence. There the two basic limiting mechanisms in wet etching: diffusion-controlled and reaction-rate-limited processes. In the diffusion-controlled case, the transport of reactant to the interface and the transport of the reacted products away from the interface are moderated by the diffusion boundary layer. Material transport limits the etching rate as diffusion coefficients in liquids are typically in the range of lop5cm2 s-’. Therefore it may take a significant time for materials to reach the bulk liquid where convective flows (- cm s-’ velocities) dominate. Additionally, there may also be an “incubation period” for etching initiation, Le., the time required to come to a steady-state etching condition due to impeding surface layers or interfacial chemical imbalances. Typical wet etching rates are in the range of a few nanometers per minute to tens of micrometers per minute depending on the etchant agitation and dilution factors. For example, in

535

a gate etch process where control is crucial, the etch rate employed should be very slow. In contrast, for a backside via-etch a very high rate is needed to etch through (25 p m (- 1 mil) to 350 pm (- 14 mil) of substrate, while at the same time, a high degree of anisotropy is important to prevent lateral spreading and undercutting. Diffusion-limited etchants are relatively isotropic in general, as the surface reaction rate is orders of magnitude shorter than the residence time in the diffusion boundary layer. Agitation greatly affects the etch rates of diffusion-limited processes, as the diffusion boundary layer thickness is easily modulated by forced convective flow (see Fig. 10-26). Thus care must be exercised in wet etching processes to ensure stable, uniform and reproducible etching conditions. In the reaction-rate-limited case, the dissolution rate is determined by the rate of chemical interactions at the interface. Typically, reaction-rate-controlled etchants are anisotropic since the surface reactions are modulated by the density of atoms on the surface planes, and the availability of free electrons at the surface. Etching is therefore dependent on the surface atom density, the electrons configuration, the doping concentration, and any surface reconstruction. Convective flow generally has a minimal effect on reaction-rate-limited etchants, as the transport rate of etchant to the surface does not generally affect the reactions unless the solutions are highly dilute. Reaction-ratecontrolled etchants may either preserve the morphology existing at the initiation of etching, or more often, develop anisotropic shapes as crystallographic effects influence the local etch rate (exposing planes of higher or lower atom density). Reaction-rate-controlled etchants that exhibit strong anisotropy are very desirable for defining gates, mesas, vias, troughs, or other high-aspect-ratio features, but are

536


highly unsuitable for planarizing the surface or pre-crystal-growth surface preparation. In either case the formation of a remanent oxide layer can inhibit the interfacial reactions and affect material transport, thereby affecting the etch rate in both diffusion and reaction-rate-limited processes. Wet chemical also generally very sensitive to temperature, as illustrated in Fig. 10-25, and may also be sensitive to above bandgap light exposure (electron-hole pair generation), Etchant reactivity is nearly always enhanced by an increase in temperature, although depletion or exhaustion of the etchant solution accelerates at higher temperatures (Otsubo et al., 1976). Reaction-ratelimited processes are much more temperature-sensitive than diffusion-limited solutions. During the etching process, the reactions at the surface involve the breaking of many chemical bonds, and therefore energy is evolved. The temperature rise associated with the etching process can upset the local as well as the global etch rate, depending on the etching rate and the net free energy liberated in the reaction. Therefore it is optimal to provide relatively large volumes of etchant, and to provide temperature control to ensure stable etching conditions. The sensitivity to light is manifest through the creation of electron- hole pairs in the surface region, which may affect the charge exchange processes at the semiconductor-etchant interface. The presence of near or above bandgap energy may increase etching rates or create anisotropic effects from surface charge density differences. Thus care must be taken to control illumination of the wafers, the light intensity, and the spectral content, to ensure reproducible etching processes; etching in the dark is preferable. A difficulty with wet chemical etchants is maintaining the reproducibility of the chemistry and reaction conditions. Several

problems can arise in wet chemical etching processes: sensitivity to the etchant, temperature, the pH of the solution, chemical depletion, the presence of light, passivating layers, and the methods of application, e.g., immersion, agitation, spray and spin, etc. The etchant solutions deplete with usage (buffering may slow this process) and age (chemical breakdown during storage, heat, or exposure to air). Recirculating solutions, while reducing some waste handling issues may be more troublesome to control, because the solution chemistry is constantly changing. During use, the chemical potentials may be altered (the pH changes) and diluent species (water and other contaminants) are formed during the reactions, thereby diluting the solution. Light of an appropriate wavelength can increase the etching rates may-fold by creating electron-hole pairs at the surface or assisting in the breaking of bonds. The presence of an increased charge density (dopant species) will nearly always increase the reaction rates at the surface. Wet etching solutions often produce gaseous by-products (e.g., H,, O,, Cl,, Br,, or other volatiles). The formation of bubbles and bubble streaks on the wafer may inhibit or accelerate the etch rate depending on the nature of the surface reactions. This bubbling phenomenon may lead to nonuniform etching across the wafer surface, and can damage the surface morphology. For example, spiking at mask edges and openings can occur due to stagnation of the etchant material (Shin and Economou, 1991). Agitation or stirring can alleviate some of these problems. The use of spray etching methods avoids the difficulties of immersion-type etching baths, and can produce vastly superior terms of reproducibility and control of the etching process (Grim, 1989, 1990). However, the application rates must be sufficient to prevent etchant depletion, and uni-


formity can be more difficult to control with diffusion-controlled etches. Anodic etching is another “wet” method for removing the surface layers in a controlled manner. Here the wafer is fitted with an electrical contact, immersed in an etchant solution, and then biased to create a depletion region of the surface. The anodic oxidation reaction creates an interface charge which balances the impressed electric field. As etching proceeds, the surface potential is gradually equalized over the wafer surface, i.e., a relatively uniform surface oxide is created. Subsequently, this oxide may be removed by a suitable solvent and the process repeated until the desired amount of material is removed. In principle this method is well-controlled. In practice, significant problems arise with localized variation in the surface potentials, nonuniform current distribution, effects of localized charge (e.g., n- or p-type regions, semi-insulating regions, etc.), the impact of residues and surface contamination, and the presence of metals, which greatly complicate control of the etching uniformity. The high resistivity substrates of GaAs and InP commonly used in IC fabrication also cause problems owing to the limited current flow permitted with reasonable bias voltages. Furthermore, the etching occurs in discrete steps which creates a “digital” thickness change with each step and protracts the etching cycle greatly. Some of the additional problems associated with wet etching are the undercutting of the surface layers or masks due to capillary effects and chemical anisotropy. Surface tension, viscosity, anisotropy, solubilities, and convective flows all conspire to reduce the control over the critical dimensions, the morphology, and the uniform arresting of the etching process. The capillary effects may be realized as “blow-out’’ or expansion of the feature peripheral dimen-

537

sions, and contraction (undercutting) of interior features. These phenomena also affect the control of the etching end-point when rinsing the etchant from the surface. Crystal lattice and etchant anisotropies, as well as flow-related effects and surface tension effects, can radically affect the shape of the etched feature. Some illustrations of different feature shapes are shown in Fig. 10-27. Once the desired chemistry is determined and understood, wafers may be routinely processed with wet etching methods. The etching of gates, vias, mesas, and channels are quite similar processes, the aim being to create a hole in, or a mesa on, the surface for the purpose of forming the gate trough, holes for interconnect vias, and isolation between devices, respectively. The selectivity of wet etchants can be exploited during fabrication by including etch stop layers in the epitaxial materials. With these materials, differential etch rates of 10000 to 1 can be realized (Ren et al., 1995). Wet etching may be used to subtractively define resistors or capacitor plates on or in the surface layers, although dry techniques are generally preferred for this process (see Sec. 10.5.2). In addition, wet chemical processes are typically used for the preparation of the substrate surfaces prior to crystal growth or processing. For additional information, see Williams (1990, Chap. 5 ) . 10.5.2 Dry Etching Dry etching of compound semiconductor materials encompasses the generic methods of plasma-based surface decomposition; sputtering, plasma etching (PE), reactive ion etching (RIE), reactive ion beam etching (RIBE), and electron-cyclotron resonance etching (ECRE). All of these etching technique involve the creation of excited or reactive chemical species which selectively

538


Figure 10-27. A schematic illustration of various etched shapes which can be created by wet or dry etching techniques. In a ) a strongly “undercut” shape is shown. This morphology would be ideal for a metal liftoff process. but undesirable for metal or dielectric coverage. In b), the crystal anisotropy has dominated the etching process, producing an etch morphology that has been limited along the [ 1 1 I ] crystal planes. Figure 10-27c illustrates a method by which very small features may be created: undercutting the masking material. Here a feature substantially smaller than the mask line is formed as material is removed from the exposed sides of the desired material. Depending on the etching conditions, anisotropy, and chemistry, vertical side walls, selectively curved side walls, or undercut features may be created, or highly selective etching may be carried out.

physically sputter, or react with, the target material(s) while minimally affecting the masking agent and those desirable materials that remain. Successful dry etching processes require careful selection of the reactive species, etching conditions, duration, control of the gas mixture. and the temperature Dry etching is typically carried out in a reduced pressure environment. High-volume vacuum pumps (for maintaining a low pressure), high-tension power supplies and field plates for developing a confined high electric field, controlled injection of the apnrnnriate gases. an ion source (if needed),

and monitoring of the process are required. Many configurations exist for this apparatus. but all systems contain the same basic components. A generalized system configuration is shown in Fig. 10-28. Dry methods are suitable for etching most of the materials present in a compound semiconductor integrated circuit process sequence. As with wet etching, gold is not etched by plasmas, although it can be sputter-etched, or ion-milled. Dry etching processes have excellent spatial resolution and the uniformity is typically very good, variation being of the order of a few percent across a 3” (76 mm)di-


539

Figure 10-28. A schematic illustration of a generic plasma etching system. The plasma, containing a strongly reactive ion, is generated by RF excitation, with optional DC biasing. The reactive gas is injected into the plasma region and maintained in a dynamic vacuum condition. In this configuration, ions may directly bombard the water surface and induce damage in the semiconductor. A carrier or ballasting gas may be used to modulate the reactivity and etching rates. Rotation may be used to enhance the uniformity ofthe etching process. Heating may be used to accelerate or control the etching rate. Exhaust treatment may be required to handle toxic by-products.

ameter wafer in a well-controlled process (O’Neill, 1991). Plasma etching processes have been used to define laser facets, gate troughs, and isolation mesas, as well as to form top or through-wafer via structures. These methods have been used to define submicrometer gates (Sauerer et al., 1992), large diameter through-wafer vias (Chen et al., 1992), and achieve etch rates of 50 pm per hour (Kofol et al., 1992; see also Sec. 10.12). There are several mechanisms that remove material during all types of plasma etching: physical sputtering, chemical etching, and reactive ion etching. Complicating the reactant removal and promoting continued surface reaction are problems associated with the formation of reaction byproducts, surface and gas-phase polymerization, and other reaction inhibitors. These by-product materials act as contaminants in the plasma, as diluents in the gas stream and may block access of the surface to new reactant species or tie-up the reactant species in the gas phase through the formation of

complex molecules or other polymeric species. Chlorine-, fluorine-, or bromine-containing compounds are preferred for the etching gas. Such species as CC14 (Sato and Nakamura, 1982; Inamura, 1979), C1, (Donelly and Flamm, 1981), HC1 (Smolinsky et al., 1981), SiC1, (Sato and Nakamura, 1982), CF, (Schwartz et al., 1979; Harada et al., 1981),CCl,F2 (Hosokawaet al., 1974; Smolinsky et al., 1981), and BCl, (Tokunaga et al., 198 1 ; Hess, I98 1) are commonly used in plasma or reactive ion etching systems. The etching rates of various materials can be balanced or controlled with additions of ballasting gases, such as argon or helium, and the total system pressure may be modulated to alter the plasma density and the impingement and interaction rates at the surface. A process utilizing these types of reactive chemical species is relatively hard on the apparatus, readily attacking the system components in the chamber, the gas control valves, feeds, injectors, pumping systems, pump fluids, and exhaust systems and waste

540


treatment facilities. The selection of system components and their exposure to the plasma or gas streams is critical for mitigating contamination of the semiconductors. Exhaust scrubbing and waste treatment is often required to prevent the polluting effects of the effluent gases. The excitation voltage and total RF and DC energy input to the plasma controls the ion creation rate and determines the ion energy distribution. There are frequency-dependent effects in the plasma, excitation being carried out typically at either -300455 kHz or 13.6 MHz (frequencies that do not interfere with communications bands) which alter the ionization efficiencies, ion densities, and energy distributions. The use of 13.6 MHz excitation results in minimal surface damage. while 300-455 kHz excitation tends to severely exacerbate the damage. This can be understood from the point of momentum transfer to the ions: at the lower frequency, ions can travel a significant distance during a cycle, readily impinging onto the surface, causing atomic displacements. At the high frequencies, however, the ions have substantially less time to accelerate into the surface region, and thus have a lower probability of damaging the surface atoms. In addition, the electric field strength and the geometry of the plasma excitation plates have a strong influence on the etching process by affecting the flow of ions to the wafer surface. The system pressure may be controlled over a moderate range which also changes the plasma density, the reactive ion density and formation rate, and thus the etching rate and selectivity (feature shape). Since the plasma contains a significant amount of energetic species, the temperature of the substrates rises typically to -200°C to -300°C during the etching cycle. Heating or cooling of the substrate may be required to control of etching proceqs.

For the various materials exposed to the plasma during etching, the selectivity for removal is determined predominantly by the plasma-materials interactions, but also affected by the system operating pressure (impingement rates). For example, the etching of heterostructure materials (e.g., GaAs/ AlGaAs materials) may be carried out selectively or nonselectively by plasma methods depending on the gas chemistry and relative etch rates. Typical dielectric materials (oxides and nitrides) are readily etched by dry techniques, as are photoresists, the latter are removed particularly well in oxygen containing plasma (“ashing” processes). Nitrides are generally more etch-resistant than oxides. Most metals, except gold, are also etched easily in plasma containing reactive species such as C1, F, or Br (see Williams, 1 9 9 0 ~ )One . major concern in plasma etching is ensuring that the protective coatings maintain their integrity during the etching cycle (etch-rate issues). One difficulty with the phosphorus-containing compounds such as InGaP, GaAsP, or quaternary materials is that these materials do not etch readily in the typical plasma chemistries (Ren et al., 1993, 1995). A key to the successful implementation of plasma etching is controlling the damage induced by energetic ion bombardment of the exposed surfaces. This is especially true for devices using “shallow” p-n junctions or lightly-doped layers in the materials structures. Damage created by the injection or recoil of energetic ions can produce atomic displacements and create donors, acceptors, and deep levels, thereby alterating the charge i n the surface region. The use of high frequency (13.6 MHz) excitation reduces there effects. To mitigate these effects there are parallel plate configurations with differing ratios between the upper and lower plate areas that control plasma confinement (density and impingement rate) and ion

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guiding effects, and “downstream” designs wherein the plasma region is confined “upstream” well away from the substrates (Pearton et al., 1991). This latter design approach attempts to minimize the direct ion bombardment of the surfaces. Here the active species formed in the plasma are swept through the chamber and across the wafers by a flowing carrier gas stream. A multitude of other competing variables exist in the plasma system and process: the gas-phase composition, chamber materials, biasing of the substrates, ion damage thresholds for the substrate materials, as well as sputtering of the chamber materials. All of these system variables contribute to variations in the etching rates. Etch rates and profiles are strongly influenced by the pressure of the chamber, the gas chemistry, and even the slightest trace of contaminants in the etching chamber. Sputtering is the process of physically “blasting” atoms from the surface by atomic interactions. Typical sputtering systems have a source of energetic ions created by a DC or AC plasma in a diode configuration. The sputtering rates are controlled by the pressure, gas mixture, current, and voltage in the system. Argon ions are a preferred species as the gas is available relatively pure, is readily ionized, and the ion is massive. Charge separation in the plasma causes the argon ions to be attracted to the negatively charged (wafer) electrode. The ion impact sputters away the surface layers. Sputtering is carried out in relatively small volume chambers with a small spacing between the plates (- 10 cm). These systems are operated at total pressures of to 1 Torr (0.13-133 N mP2). With a small chamber and close proximity of the plates, continuous redeposition may occur as it is difficult to extract the sputtered material rapidly from the center of the chamber. Contamination of the semiconductor material

-

-

541

can occur by redeposition and decomposition of the chamber materials, and by implantation by ion bombardment at the surface. “Passivation” of the surface or redeposition may slow the etching process by interfering with the sputtering rates of the desired species and create nonuniform etching profiles over the wafer surface. Etch masking must be quite robust to withstand the continuous ion bombardment in sputtering or plasma processes. Thick photoresist (PR) layers or multiple PR/metal layers may be used to resist the ion flux. A balance of etching rates between the mask materials and the semiconductor is generally the best achievable compromise in practice. Metal layers etch substantially more slowly than the semiconductor or photoresists. Thus relatively thin metal masking layers may be used to assist pattern definition, permitting very fine features to be created. Etch feature side wall definition is generally poorer with sputtering processes relative to other approaches. The high wall angles desired for deep trenching (isolation) cannot be achieved easily by sputtering, due to the limited interaction of the ions with the surface at high incident angles and the high probability of redeposition within the trench. RIE-type etching in much better suited to large-aspect-ratio etched structures. RIE/RIBE/PE processes operate at low pressures, in the range Torr (0.13-0.00 13 N m-*). RIE/RIBE chambers have relatively large electrode spacings, and lower energies (smaller potentials) are impressed, providing a cleaner environment for the etching process and somewhat reduced redeposition rates. The strongly enhanced etching comes from the reactivity of the ions rather than the energy imparted to the etchant species. Unlike plasma etching where the low-energy plasma consists of ions, radicals, and various electrons, pro-

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542


tons, etc., an ion source ( R E ) or directed ion beam (RIBE) creates a selected set of ionized species to affect the etching. These systems exhibit somewhat slower etching rates than those of sputtering processes, predominantly due to the limitations of the ion sources. Plasma etching tends to be isotropic, whereas RIE and RIBE can be used to control the etched morphology and have very limited sputter damage and redeposition. The latter two points are very critical i n device structures that incorporate field effects for charge modulation (FET-type devices and lightly-doped structures. for example). PE operates at higher pressures than RIE/RIBE, with relatively low power, and etches at moderately low rates. While there is less surface damage created than with sputtering, PE still embodies a significant amount of damage and contamination from the plasma and chamber components. Operating at higher potentials generally leads to greater anisotropy in the etching, but greater damage to the surface due to implantation processes. RIE/RIBE carried out at higher bias voltages can produce near-vertical side walls due to impingement near 90". In RIE/RIBE the etching is caused predominantly by the reactive species rather than all of the particles i n the plasma, as i n PE . The ion source in RIE/RIBE provides a reactive ionized species containing a group VI1 (chlorine. fluorine, or bromine) atom or molecule. For most 111-V materials, the chlorine and bromine compounds produce highly volatile reactants and are therefore preferred over the fluorine compounds (Burton et al.. 1983: Ibbotson et al., 1983). Polymer formation is a concern with any of these compounds, particularly in the presence of photoresists. The objective is to provide selected, low-energy, reactive ions to t h e surface of the wafer where upon they

form volatile complexes with the surface atoms. This volatility limits redeposition as the complexes and compounds do not readily decompose or attach themselves to the surface of the wafer. A variety of halogenated compounds have been used as reactive ion sources: CF,, CCl,, BCl,, CBr,, or other chloro-fluoro carbons. CBr,Cl,, CHCl,, and CJl, have been found to readily form polymeric compounds and by-products, and are generally unsuitable for RIE/RIBE. Construction materials (chamber walls, shields, electrodes, etc.) for RIE/RIBE systems are of critical importance as the reactive species may cause the system components to decompose and contaminate the wafers. RIBE is differentiated from RIE by the use of collimation to create a directed beam of extracted ions from a high-density plasma source. This beam-like ion stream permits variation of the angle of incidence to the surface, thereby affecting the etching rates and morphology (Ide et al., 1992). Surface reactivity is not dependent on the incident angle to the first order, and therefore the side wall angle can be affected through the angle of incidence. The ability to control the interaction of the ions with the surface mitigates the problems of morphology control independent of the ion energy. RIE/RIBE are carried out in a parallel plate system, selecting the reacting ions by gas injection or ion extraction, under appropriate bias conditions. Etching occurs by chemical reaction and subsequent desorption of the reactants. The ability to create nearly vertical side walls at moderate bias voltages is a distinct advantage of RIBE. As with all plasma systems, RIE/RIBE etch rates are influenced by pressure, gas mixture. ion density, and excitation power. Problems may occur with polymerization between certain etchant gases and the reactant species, which can inhibit the etching.

10.6 Ohmic Contacts

543

Figure 10-29. A schematic illustration of an ECR-plasma etching system. The ion plasma, containing a strongly reactive species, is generated by exciting electron-cyclotron resonance of the desired chemical species. The source is located “upstream” from the etching chamber to protect the wafer from direct ion bombardment. A carrier or ballasting gas flows through the ion source and the chamber, assisting in the transport of reactive ions to the wafer. Electronic extraction may be used to pull ions from the source. Rotation or heating may be used to enhance or control the uniformity and rate of the etching process. Exhaust treatment is generally required to handle toxic by-products in compound semiconductor processing.

RIE/RIBE are significantly better than sputtering techniques for most applications, having lower damage due to the lower ion energies and reduced contamination (with proper chamber construction). Electron-cyclotron resonance etching (ECRE) processes involve the selective excitation of an ionized species through a high frequency resonant coupling process (Pearton et al., 1991). Figure 10-29 schematically outlines an ECRE configuration. The excited ions are typically created well away (“upstream”) from the etching chamber to minimize direct ion bombardment damage to the wafer. Ions are extracted from the ECR source by the electric fields and the pressure gradient in the system: The etching processes occur in a manner similar to RIE/RIBE. ECRE has the advantages of “clean” etching as it is carried out in a high or ultra-high vacuum environment, gives very minimal surface damage (with low to moderate extraction/acclerationpotentials), negligible redeposition, and reasonable etch rates (Pearton et al., 1991).

Run-to-run reproducibility is somewhat difficult to control in plasma techniques as there is no convenient and accurate method for monitoring the etching rate. Control of the end point may be enhanced by the incorporation of etch-stop layers, monitoring of the reaction product generation rate, or the presence of specific reacted species (chemical indicators) in the plasma or exhaust gases. These techniques can provide adequate end point detection to determine the completion of the etching cycle. Presently, the best control parameter is tracking of the reactant species evolution by residual gas analysis, optical absorption, or similar methods to determine an end point indication. Further development and refinement of gas-phase sensors will result in greatly improved control of plasma type processes.

10.6 Ohmic Contacts Ohmic contacts provide low resistance current paths and interconnection between

544


devices. The creation of the ohmic behavior is, and has been, a source of perpetual investigation and development activity in compound semiconductor materials (Braslau et al., 1987; Matino and Tokunuga, 1969; Schwartz, 1969; Edwards et al., 1972; Ostubo et al., 1977; Kaumanns et al., 1987). The underlying difficulty in creating an “ohmic” contact is that Schottky barriers are formed when most metals are brought into initial contact with the semiconductor surface (Schottky barriers are considered in detail in Sec. 10.7). Therefore some means of eliminating this barrier must be developed. The details of the mechanisms behind the formation of ohmic contacts are not yet fully understood in spite of more than 50 years of work [see Sharma (1981)l. From a theoret-

ical and physical standpoint an ohmic contact begins as a Schottky barrier, as shown in Fig. 10-30. The work function of the metal and semiconductor are initially offset as the Fermi energy is constant across the interface. This band offset creates a barrier to charge flow from the semiconductor to the metal, as attributed to the investigations of Schottky [see Chap. 5 in Sze (1981)], giving rise to a diode transfer characteristic. The Schottky barrier height is defined as the difference of the metal and semiconductor work functions $m-$s=

( 10-4)

$B

As long as the quantity $B is significantly greater than zero, a barrier to charge transport exists, and the flow of charge will not

Figure 10-30. Initial formation of a Schottky barrier prior to annealing to create an ohmic contact. In a) &,is the metal work function, is the electron affinity of the semiconductor, E, is the semiconductor energy gap, and E, and E , are the conduction and valence band energies, respectively. EF is the Fermi energy and q V , is the difference between the Fermi level and relative to the vacuum level. b) As the metal is brought into contact with the semiconductor, charge is exchanged to maintain a constant Fermi energy. This creates a depletion region, W, in the semiconductor to balance the electrons in the metal. The semiconductor energy bands “bend” to reflect the charge distribution in the near-surface region. The Schottky barrier height is &, and the junction build-in potential is V,, at equilibrium (no applied bias).

x,

Metal

-

I

Semiconductor

x,

Schottky Barrier

EC EF

EE”

-I

Depletion Width

10.6 Ohmic Contacts

be linear with applied voltage (electric field strength), The formation of an “ohmic” contact to the semiconductor involves metallurgial reactions which create a transition from a Schottky barrier condition to a graded energy band structure with a negligible barrier height (Schwartz and Sarace, 1966; Schwartz, 1969; DiLorenzo et al., 1979). The initial formation of a depletion region (W) with the creation of a Schottky barrier is illustrated in Fig. 10-3 1. The width of this depletion region is proportional to the square root of the doping concentration (in the abrupt junction approximation) governed by the relation (Sze, 1981, Sec. 5.2)

545

conductor so that tunneling and/or field emission processes have a high probability. A model for this latter point was discussed in the light of the depletion width being substantially smaller than the depth of the degenerate layer. Thus tunneling and thermionic emission processes are facile, and the barrier to transport is negligible (Popovic, 1978). Conversely, as the doping density decreases, the depletion width increases and the metallurgical junction must be formed deeper into the semiconductor to affect an ohmic behavior. Also, since there are fewer charges available i n the semiconductor, the conductivity is reduced. All of these effects contribute to higher contact resistances for “lightly” doped materials, and make the formation of a high quality ohmic contact more difficult. There is no consensus on a precise model and understanding for the ohmic contact formation (see Sharma 1981, or Schwartz, 1969). Some investigators consider the interface to be a disordered alloy with “mobility gap” states (Peterson and Adler, 1976), while others interpret the interface as a transition from the metal through an amorphous region to the crystalline semiconductor material (Wey, 1976; Riben and Feucht, 1966). At present, resolution of these arguments remains unclear.

( 10-6)

As the doping level is increased the depletion width shrinks, the interfacial electric becomes greater, and field emisfield (Emax) sion, thermionic emission, and tunneling processes may readily occur. It is desirable to have: 1) a small @B such that k T / q is “large”, or 2) a degenerately-doped semi-

Semiconductor

c

-4

EV

Depletion Width

Figure 10-31. The creation of a depletion region of width W in the surface region of an n-type semiconductor. E , is the donor energy level relative to the conduction band edge, &, E,, E,, E,, and E , have their usual meanings. V,, is the built-in potential. The depletion width is inversely proportional to the carrier density as in Eq. (10-5).

546


Further investigations may some day shed light on the exact phenomena. For a more detailed theoretical development of ohmic contact electrical behavior see, for example, Chap. 5 in the book by Sze (1981). To eliminate the Schottky barrier and produce an ohmic behavior, a metal contact material must generally be alloyed into the semiconductor. The metal reacts with the semiconductor forming multiphase intermetallic compounds, lowering the barrier potential. and stretching the band-bending

into the semiconductor, as illustrated in Fig. 10-32. Electron (or hole) flow is impeded less and less as the alloying process advances. If the condition (10-7)

is met for an n-type semiconductor material, then the contact is considered to be ohmic in nature. For small positive values of @ B (a small Schottky barrier height), significant tunneling and thermionic emission can occur permitting significant current flow with

Figure 10-32. Creation of an "ohmic" contact to a semiconductor. In a ) the barrier height, &,, is very small, presenting a negligible barrier to electron flow. &,.E,, E,, E,, E,, and E, have their usual meanings. In b) the surface region of the semiconductor is doped to an n* degenerate condition (high electron density, Fermi level in the conduction band). The depletion width ia dramatically narrowed. Thus tunneling processes may readily occur Both of thehe processes may contribute to the ohmic behavior.

10.6 Ohmic Contacts

a small forward bias. Thus only a very small resistive component is realized. Surface states and surface charge may also affect the barrier height and charge distribution in the semiconductor, and therefore the I- V behavior (Spicer et al., 1989). This latter point is particularly important for devices which are lightly doped (“enhancement mode”) and therefore very sensitive to changes in near-surface depletion or the accumulation of charge. The contact resistance (R,) is derived from the thermionic I- V theory for an ideal Schottky contact. The definition of R, is

R,=- n k T

at V = O

( 10-8)

94at

A plot of log I vs. V should result in a straight line of slope q / ( n k T) where n is the ideality factor from Schottky junction theory, k is the Boltzmann constant, q is the elementary charge, Tis the temperature, and I,,, is the reverse bias saturation current. Typically, n is in the range 1.0-1.1 for a good ohmic contact; values very near 1.O are most desirable. Values of n greater than 1.1 indicate problems with the alloying cycle, the contact metallurgy, or highly resistive materials. A critical feature of the ohmic contact is the linearity of the I- V relationship: any diode-like characteristics are undesirable. Contact metals must be deposited on clean surfaces to prevent erratic intermixing of the metal and semiconductor during alloying, particularly with reactive species such as aluminum or titanium. Typically, at least one of the components of the metallization is a donor (e.g., Si, Ge, Sn,Se, or Te in ntype, III-V compounds) or an acceptor (e.g., Zn, Cd, Be, or Mg in p-type materials) species in the host semiconductor. This will greatly increase the ease of ohmic contact formation as the effective doping density can create a highly degenerate layer i n the

-

547

interfacial region of the metal and semiconductor. The alloying process causes intermixing of the metal, the doping species, and the semiconductor, as discussed above. However, many considerations arise in the process of alloying: chemical reactivity or inertness with the host semiconductor, diffusivity of the various species, the phase diagram for multi-component systems, surface tension, processing limitations (thermal and morphological) from previous steps, adhesion, defining geometry (masking), stability of the intermetallic phases, compatibility with the wire bonding metallurgy, etc. The phase diagram and the kinetics of the intermixing process determine, to a large extent, the achievable barrier reduction and thus the conductivities of the interfacial metallic region. It is desired that the contact resistance be as low as possible, typically in the range of 1o-’ to R cm2 for n-type materials, and about ten times larger for p-type materials principally due to mobility differences. The range of interactions generate a large number of compromises in the development of a viable, manufacturable, and stable ohmic contact formation process. The fabrication of ohmic contacts begins with careful surface preparation, followed by deposition of metal(s) and/or metal alloys. There are a multitude of methods and metallurgical systems suitable for the formation of ohmic contacts to III-V compounds (Sharma, 198 1; Schwartz, 1969; Palmstrom and Morgan, 1985). Table 10-5 highlights a number of these metals systems; numerous other alloys have been evaluated. Predominantly, metallurgical systems based on Au-Ge, and more typically Au-Ge-Ni, are the most studied and in general use. For additional information see Sharma (198 l), Howes and Morgans (1985, Chap. 6), Williams (1990, Chap. 1 I ) , and the associated references therein.

548


Table 10-5. Ohmic metallizations Metallization

Semiconductor tY Pe

Reference

In Sn

n

Au-In

n n

Wronski ( 1969) Schuartz and Sarace (1966) Paola (1970) Henshall (1977) Fukuta et al (1976) Shih dnd Blurn (19721, Kuan et al (1983) Matino and Tokunaga (1969) Shih and Blurn (1972) Ishihara et al (1967) Matino and Tokunaga (1969)

Au-Sn Au-Ge Au-Ge-Ni Ap-In AI Ag-Znn In-Zn

n

n n

n. P n

P P

Evaporation methods are particularly useful for multi-component metallizations. While heating of the substrate material must be carefully controlled through the deposition rate and intentional heating or cooling of the wafer, control of the thickness and deposition rate are very good. Compositions can be controlled either through multiple deposition steps, co-deposition, or the use of alloys as charge materials. Sputtering and plating-type processes can also be used to deposit the metal on the semiconductor, although plating is rarely implemented for top surface metallizations in practice. Sputtering methods generally have lower deposition rates, can generate substantial damage in the semiconductor, and thickness control is indirect and difficult. On the other hand, sputter damage to the interfacial region may lead to lower contact resistance through the creation of defect states and disorder at the surface. Plating processes rapidly build up layer thicknesses, but tend to be rather “dirty” from the chemical standpoint, and have problems in relation to control of the surface morphology and layer thicknesses. In some processes, such as backside ohmic metallization of bonding pad formation,

where metal thickness control is relaxed but thick layers are desired, plating processes are the method of choice. Ohmic contact topology may be defined by standard photolithographic patterning methods after deposition (see Chap. 4 of this Volume). Liftoff patterning, photoresist or dielectric assisted, is the most common method for the removal of unwanted metal (see Sec. 10.1 1.2), provided the deposition process has not created a completely uniform layer of metal over the photoresist or dielectric surface topology. Ion milling may be employed for patterning gold or goldbearing alloys, or tungsten-based contact materials. Aluminum and other non-gold bearing metallizations may be patterned by dry etching methods such as RIE (as discussed in Sec. 10.5.2). The annealing of most ohmic metallizations used in device fabrication is a very critical step. “Spiking” and other deviations from planarity can occur even with mild over-alloying (Le., excessively high temperatures of extended alloy time), making subsequent processing more difficult (Gyulai et al., 1971; Zeng and Chung, 1982; Palmstrom et al., 1978; Miller, 1980). Spiking of the contact metal in the compound semiconductor systems is quite similar to that observed in the A1 : Si system at edges of contact windows. Lateral spreading has a negative impact on electric field distributions and may cause short-circuiting in fine geometries [see Goronkin et al. (1989)l. Roughness or texturing in the contact region is apparent after alloying especially if “overalloying” has occurred. Even 20-30°C overtemperatures (in the range of -400°C for NiGeAu-based contacts to GaAs materials) or slightly extended cycle times can cause the metals to “punch through” active layers, as shown schematically in Fig. 10-33. Lateral spread of the contact materials may lead to uncontrolled electrical behavior in active

10.6 Ohmic Contacts

549

Figure 10-33. Schematic representation of annealing effects on Ni-Au-Ge contacts to GaAs. In a) the metal regions have been deposited and defined by lithography. I n b) the material has been annealed. The angular structure of the NiAs(Ge) crystal structure, represented by the shaded region, is characteristic of the metal-semiconductor interaction during annealing. This has been observed in several TEM investigations (Zeng and Chung, 1982; Parsey, 1990). Excessive annealing will produce punch-through of the metal below the n-layer. as shown.

and passive devices, such as low breakdown voltages or leaky characteristics. Roughness of the contact sites may also negatively impact subsequent mask alignment, photoresist depositions, and other processing steps. A minimal thermal budget is typically used for alloying processes employing a furnace, “hot plate”, or rapid thermal annealing (RTA) system. The objective is to minimize the metallurgical interaction while maximizing the conductivity of the alloyedcontact region. For n-type materials, using gold-based metallurgy, the alloying process is carried out at relatively low temperatures -400°C) and short times (of the order of tens of seconds to 10 min), or in RTA systems with somewhat higher temperatures (- 500 “ C ) but shorter durations (ca. 30 s) the contact metallurgy is controlled sufficiently to create a reproducible, low-re-

-

sistance contact to the n-type materials [see Sec. V in Sharma (1981)l. Similarly, the Au-In and Au-Zn alloy families are commonly used for contacts to p-type materials. Owing to the lower carrier mobility, and thus the higher resistivity of p-type materials, a higher doping level is required to achieve low contact resistance (doping levels are usually greater than cm-3) to achieve a highly degenerate region. Even with high doping concentrations, contacts to p-type semiconductors are always of higher resistance than those to n-type materials. It is possible to form “nonalloyed” ohmic contacts to GaAs and other compound semiconductors provided sufficiently high doping concentrations exist in the surface layers, Typically, electron densities greater than 3 - 5 x 1019 cm-3 are necessary for a low resistance, nonalloyed contact to n-type

550


ily via tunneling and thermalization processes, as well as requiring only minimal electric fields to drift the charges across the metallurgial junction. Detailed analyses of the ohmic contact and interfacial reactions have been made by numerous techniques, among them, X-ray diffraction (Ogawa, 1988), Auger electron spectroscopy (Robinson, 1975), transmission electron microscopy (Kuan et al., 1983), scanning electron microscopy (Robinson, 1975), and secondary ion mass spectroscopy (Palmstrom et al., 1978). The information obtained has led to a detailed understanding of the interactions and con-

material (Chang et al., 1971). If the semiconductor bandgap energy is small or can be reduced, for example, by the addition of an alloy component. e.g., In in In,Ga,As, the formation of nonalloyed contacts is facile. The use of In, sGa, ,As as a low resistance contact to HBT devices has attracted significant interest (Poulton et al., 1994; Huang et al., 1993). Keys to creating this type of contact are: 1) the relatively small bandgap of In, sGao ,As (approx. 0.8 eV): 2 ) the degeneracy of the semiconductor (high surface doping concentration); 3) the formation of an extremely thin depletion region (< 10 nm) at the surface. Charge flows eas-

Weight P e r c e n t Gallium 0

1208-1

.

. . ..

.., . . . . . . . . .,

IO

. .'. .

.

50

40

30

20

,

60

70

BO

90 100

, . .I

L

7'

8

0 ¶

4

; 0 0 2 -

m

0

Au

10

20

J--?0

40

50

60

Atomic P e r c e n t Gallium

70

ab

90

IO0

Ca

Figure 10-34. The Au-Ga phase diagram showing atomic percent (left figure) and weight percent (right figure) relationships. Numerous intermetallic phases can form in the temperature range -274°C to -491 "C, which can greatly affect the morphological and electrical behavior of annealed contacts (after Massalski, 1990, p. 370). Renrinted by permission of ASM International.

10.6 Ohmic Contacts

trol of the alloy process (see Howes and Morgan, 1985, Chap. 6). A number of investigators have studied the interaction of gold and gold-alloy materials with GaAs (Zeng and Chung, 1982; Vandenberg and Kingsborn, 1980) and InGaAsP (Vandenberg et al., 1982; Vandenberg and Temkin, 1984) and found that, as predicted from the phase diagrams, numerous intermetallic compounds form and evolve during the alloying process. For example, in the reaction of gold with GaAs, formation of the Au-Ga alloys occurs with the resulting loss of arsenic from the surface, and the creation of AuGa, and AuGa; p and y intermetallic phases are created, as shown in Fig. 10-34 (Massalski, 1986, pp. 258-261).

551

Contact resistance in most ohmic contact systems has been found to increase if undesirable (high resistivity) phases form. For example, in the Ni-Au-Ge contact, if aAu : Ge or Ni-Ge are created i n significant amounts, or if excess gold diffuses into the semiconductor surface region, the contact resistance will be increased. In contrast, the contact resistance will be lower if Ni-As and the in-diffusion of germanium occurs and Au : Gaforms. Schmid-Fetzer (1988) has recently reviewed the phase relationships and predicted interactions of a large number of metals for potential contacts to GaAs. Contacting thin layers (of the order of a few tens of nanometers) is a difficult task due to the necessity to consume some of the surface

Atomic Percent Gallium

Au Figure 10-34. (continued).

Weight P e r c e n t Gallium

Ga

552

10 Compound Semiconductor Device P r o c e s s i n g

material. to form the correct phase(s), and the complication of uncontrolled in-diffusion processes due to surface defect formation. The varied and rapid diffusivity of the various component metals also complicates control of the alloying to very thin layers. Optimum thicknesses of n+ or p+ contact layers appear to be in the range of 25-50 nm.

10.7 Schottky Barriers and Gates A Schottky barrier is the rectifying contact which forms when a metal is brought into contact with a semiconductor material. This structure is a charge dipole which creates a depletion region analogous to a p-n junction diode. Schottky barriers are the heart of most FET-type devices. The charge flow in the transistor is modulated by the bias applied to the Schottky barrier gate metal during device operation. The “barrier

height”, in conjunction with the available charge density, determines the threshold of the switching action and the conduction state of the device at a given bias condition. In Fig. 10-35 the formation of a Schottky barrier is illustrated. The semiconductor material and the metal possess different work functions relative to the vacuum energy levels, &, and @, , respectively. As the metal is brought into contact with the semiconductor, charge is exchanged between the materials so as to balance the chemical potential of the electrons and holes, i.e., the Fermi energy level is constant across the interface. The metal contributes - 1 electron per atom, and the semiconductor typically 1 O-‘ to electrons per atom. Charge exchange creates the dipole layer and charge equilibrium is established. As a result of the imbalance i n the charge density, a depletion region, “W”, is formed in the semiconductor.

Figure 10-35. Schematic energ) diagram of a Schottky barrier. d,,, is the metal work function, ,Y, is the electron affinity. V,, i j the built-in potential. E, is the energy gap, and E, and Ev are the conduction and valence band edges. respectibely. 6 , i s the Schottky barrier height. After a metal is placed on the semiconductor surface, charge is exchanged to equilibrate the Fermi energy ( E k ) .Since the semiconductor contains far less charge than the rneial. the donor state\ (E,) empty producing a depleted region of width W.

553

10.7 Schottky Barriers and Gates

From Fig. 10-35 the relationship

Table 10-6. Schottky barrier heights on selected compound semiconductor materials”,b.

( 10-9)

@rn-xs= 4 B

may be observed. The difference between the electron affinity of the semiconductor, and the metal work function, $,, is the In principle Schottky barrier height, each semiconductor-metal system should have a unique Schottky barrier height based upon the configuration of Fig. 10-35 (see Kahn et al., 1989). In reality, surface states, surface reconstruction, impurities, and defects may all act to “pin” the Fermi energy. Thus the barrier height values are confined to a relatively narrow range, as evident in Table 10-6. This phenomenon is the subject of intense investigation [see, for example, spicer et al. (1980), Brillson et al. (1983), and Williams (1982)], and remains unresolved at present. The current flow in a Schottky diode is described by the relationship

xs,

eB.

I = I , {exp[ q V / ( k T ) ]- 1 )

(10-10)

where q is the elementary charge, V is the applied voltage, k is the Boltzmann constant, and T is the absolute temperature. I , is the thermionic current z ~ = A *T~ exp 1-9

4B/(k~)]}

(10-1 1)

where A * is the Richardson constant, qB is the Schottky barrier height, and the other symbols have their usual meaning. From Eq. (10-9) if 4,>xS,then 4B>0 and the structure will be rectifying. Thus an ideal diode would have an infinitely large value of $ B . In practice the largest possible value for the barrier height would suffice. For further development of the Schottky barrier theory see Simmons and Taylor (1983). Typically, qB is in the range of 0.5 V to 1.4 V for most important compound semiconductor as shown in Table 10-6, clustering around 0.8 V for most metals on GaAs. The observed barrier height is related to the magnitude of the sem-

-

Metal

A1 Au Ag W Ti Ni Pt

Semiconductor material GaAs

AlAs

InP

GaP

ZnSe

0.80 0.90

1.20

0.52‘ 0.52 0.54 -

1.07 1.30 1.20 1.12 1.27 1.45

0.76 1.36 1.21 -

0.88

-

0.80 0.83d 0.77d 0.84

-

1.0

-

1.40

Values in electronvolts at 300 K; from Sze ( 1 98 I , p. 291); Sharma (1981); Waldrop (1984). a

iconductor band-gap, being about 0.5 -0.6 of E,, lower for materials with a small E,, and higher for wide gap ,materials such as Gap. For materials with small band gaps, such as InAs (0.42 eV), this factor places stringent requirements on device operation, necessitating cryogenic temperatures for viable transistor operation. The value of the Schottky barrier height does not appear to depend strongly on the metal work function, although from the physical description of the barrier formation [Eq. (10.9)] it should be directly tied to $, , The “pinning” of the Schottky barrier height noted above has been attributed to the existence of surface states at the level of -lo’* to 1013cm2. These states can arise from carbon, oxygen, surface defects, or other contaminants chemisorbed or physisorbed on the surface. Numerous interpretations have been put forth to explain these effects. Brillson et al. (1983) have considered that a finite amount of intermixing occurs during the metal deposition process rather than an idealized, atomically abrupt interface. An effective metal work function is defined which integrates the effects of defects, clusters of metal, or semiconductor

-

554


species, etc. This leads to a “pinned” value for the Schottky barrier height. Spicer has postulated a “unified defect model”, depending on surface states from defects (e.g., vacancies) which gives rise to the pinning states. This behavior is discussed further by Williams (1982) and numerous theories exist for these pinning phenomena. Many investigations of the Schottky barrier phenomena have been carried out in an attempt to understand and control the interfacial charge states and the metallurgy of the metal-semiconductor junction so as to provide a stable and reproducible barrier height (Spicer et al., 1980; Pan et al., 1983; Brillson et al., 1983: Waldrop et al., 1982; Williams, 1982). While the barrier heights obtained under near-ideal conditions (e.g., invacuo cleaved surfaces) are relatively wellcharacterized, in practice, the variation induced by the processing chemistry and the materials properties requires significant efforts to provide a “reproducible” Schottky barrier height. However, the precise physical relationship of the energy gap, work function, and q3B is not fully understood. as remarked by many investigators (see review by Schmid-Fetzer, 1988). To form the Schottky-barrier gate structure, a metal (e.g., gold or aluminum) or metalloid (e.g.,WSi, WN, TiWN, etc.) is deposited onto the CS surface and then patterned by standard photolithographic-etching processes. The demands of the fabrication process sequence place constraints on the formation of Schottky-barrier gates: the required thermal and patterning processes determine the permissible gate metallurgy. It is necessary to contend also with adhesion between the gate material and the semiconductor and the impact of subsequent processing steps on the chemical reactivity and stability of the metal-semiconductor system. Therefore the selection of suitable metals and metal alloys becomes relatively

limited (see Table 10-6). These materials may be used in combination to improve properties such as the electrical resistivity, but the barrier height is determined by the metal or metal alloy in contact with the semiconductor surface. The primary metal deposition methods are sputtering and evaporation. As in any deposition process, the surface and the material to be deposited must be extremely clean to prevent uncontrolled interfacial reactions or the creation of metal-insulator-semiconductor (MIS) structures. For most of the refractory metals, their melting points are sufficiently high that sputtering is the only viable deposition method; electron beam evaporation for these materials is either impractical or the deposition process will raise the temperature of semiconductor surface too high to prevent chemical interactions. On the other hand, sputtering readily creates surface damage and thus creates surface states (see Sec. 10.6). As previously noted, the formation of a Schottky barrier is extremely sensitive to the interfacial density-of-states. The corresponding variability in the barrier height, locally or globally, will affect the transistor threshold voltage, operating conditions, and reproducibility. Many of the metallurgical systems presented in Table 10-6, particularly in the case of refractory metals, may create significant stresses during deposition and fabrication, and also during device operation due to a mismatch in the lattice parameters, atomic configurations, and the existence of thermal expansion coefficient mismatch. These phenomena give rise to piezoelectric-type effects, and consequently, the transistor threshold voltage may shift. For example, the grain structure of a Schottky-barrier metallization, as deposited by various methods, is strongly dependent on the deposition rate and the deposition conditions (e.g., vacuum, plasma composition, target materials,


etc.). Thus variations in $B may be anticipated. The microscopic details of the grain structure may also affect the gate metal resistivity and the susceptibility to electromigration at high current densities or high temperatures. These issues must be carefully addressed to achieve a stable Schottky barrier process. If the device fabrication process is carried out at relatively low temperatures, gate materials such as Ti-Pt-Au may be utilized (Wadaetal., 1989; Brownetal., 1989).Gold suffers from relatively poor adhesion to most compound semiconductors and also rapidly diffuses in most compound materials, even at low temperatures (ca. 250400”C), as does platinum. Thus there is a need to capitalize on the conductivity of gold, while maintaining process integrity. The Ti-Pt-Au system is commonly used for gate metals on GaAs. In this case, the titanium is used as an “adhesion promoter”. The platinum layer serves as a diffusion barrier to prevent the gold from reacting with the titanium (see Massalski, 1986, pp. 298299) and subsequent gold-spiking into the GaAs (Goronkin et al., 1989). Palladium may be substituted for platinum with similar results. The gold provides a very low resistance path to support a high density current flow. As these metals are relatively compatible from a thermal expansion standpoint there are only small interlayer stresses, and little driving force for intermixing at

555

temperatures below ca. 600 “C, thereby producing a thermodynamically stable contact structure. For fabrication processes that employ nonalloyed or nonannealed contacts, aluminum, titanium, and tantalum have been found to be stable at temperatures up to 300°C. These materials can be used i n the gate structure provided temperatures in subsequent process steps do not exceed roughly 200-250°C and operating temperatures are limited to less than 125-200°C. For devices which utilize an ion implantation and anneal step subsequent to the gate metal deposition (see Secs. 10.3 and 10.1l ) , the gate material must be stable at temperatures at least as high as the annealing temperature, typically in the range of 800 “C to 1000 “C. Self-aligned processes, such as the generalized approach shown in Fig. 10-36, require the use of ion implantation and annealing for defining the gate and channel regions. Several approaches exist for creating the self-aligned gate, among them, the selfaligned implantation for n+ layer technology (SAINT) (Yamasaki et al., 1982) and the self-aligned refractory gate integrated circuit process (SARGIC) (DautremontSmith et al., 1990; Dick et al., 1989). Any variation on this type of technology relies on the existence of a stable Schottkybarrier gate metallurgy. Typically, for selfaligned structures the gate material is a refractory or noble metal such as tungsten (Sze, 1981, p. 290), platinum (Fontaine et

-

Figure 10-36. Schematic flow of a “self-aligned” process wherein the gate metal layer is used to protect the FET channel from ion implantation and processing damage. Steps 1 and 2 define the channel and gate, step 3 is the self-aligning step. Step 4 provides the device isolation. Steps 5 to 8 define the ohmic contacts, first and second level interconnections, and passivation protection.

556


2) Gate metal deposition, Photolithography,Etching or liftoff to define gate

3) N'ion implantation,Anneal

4) Photolithgraphy,Isolation ion implantation

5 ) Photolithography,Ohmic metal deposition, Littoff or etching, Alloying

Figure 10-36. (continued)

10.7 Schottky Barriers and Gates 6) Dielectric deposition,Via etch, Interconnect metal deposition, Patterning

7) Dielectric deposition, Via patterning,Metal 2 deposition, Patterning

8) Passivation and Contact pad via openings

Figure 10-36. (continued).

557

558


al., 1983; Sinha and Poate. 1974), Titanium (Matino), or an alloy or bi-layer such as WSi (Dautremont-Smith et al., 1990) W-N (Kikauraet al., 1988),Ti-W-N (Sadleret al., 1989). W-A1 (Inokuchi et al., 1987j, or other similar combinations. These types of Schottky barrier material are relatively stable at high temperatures and exhibit only very limited reactivity with the compound semiconductor surface. However, it has been observed that metals such as tungsten must be treated extremely carefully as layers tend to lift from the semiconductor surface at temperatures above 400-500°C due to thermal expansion mismatch (the ratio of thermal expansion coefficients is greater than 10: 1). Also. all Ti-based gate structures can exhibit “gate sinking” under high stress operation. In this case. the metallurgical junction diffuses into the semiconductor and alters the electrical performance over time. Multi-layer metal-metalloid structures may be deposited to significantly reduce the electrical resistivity of the gate structure. For example, gold over W-Si, gold over TaSi, or tungsten over w-Si. Use of these layered structures is particularly important for device performance as silicide or refractory materials have a much higher resistivity than gold or gold-based alloys. Thus the current carrying capabilities are significantly lower. Electromigration and thermally-induced grain modification may also occur if the current densities are driven above lo5 A cm-? depending on the metals system (Irvin and Loya 1978; Irvin, 1982; Oates and Barr, 1994). Localized heating can occur in a resistive gate structure. thereby upsetting the device operating characteristics and accelerating the degradation processes (see Irvin and Loya, 1978; Irvin, 1982. and references therein). The use of such “bi-layer” or T-gate structures substantially enhances the current car-

-

rying capability (Maeda et al., 1988) and increases the operating speed of a transistor by lowering the gate RC time constant (Brech et al., 1997). A low-resistance gate is crucial to the performance of devices with submicrometer gate lengths, as the advantages of the small transit time through the gate region can be completely offset by the performance losses incurred from the RC effects of a high resistivity gate stripe. A gate structure known as the “T-gate” or “mushroom-gate” (Yuen et al., 1988; Beaubien, 1992; Wada et al., 1997; Thiede et al., 1998; Pobanz et al., 1998) can be utilized to further reduce the resistance of the refractory of high-resistivity gate structure while maintaining a very small effective gate length. The T-gate configuration is formed by deliberately undercutting the Schottky barrier material beneath the top metallization layer, or by providing a photoresist or other sacrificial layer to shape the top metallization during deposition following the definition of the fine gate feature on the surface. This undercut structure is also useful for self-aligned ion implanted processes to prevent the implanted ions from encroaching on the channel region. In cross section the gate has a T-shape with the current being carried predominantly in the low-resistivity top metal layer, as shown schematically in Fig. 10-37. Here the large, low-resistance top metal extends over the higher resistance Schottky barrier material in a Tconfiguration. Figure 10-38 shows an SEM cross section of a T-gate structure. The physical gate length i n this figure is 100 nm, while the metal width of the cross is -0.5 pm. Wada et al. (1997) described a process for the fabrication of gates with dimensions of under 100 nm. Electron-beam or deep-UV lithography is required to achieve the sub-0.25 pm dimensions, whereas g-line or i-line photolithography is suitable for dimensions larger than -0.4 pm. Many “tricks”

-


559

Figure 10-37. Cross-section schematic diagram of a “T-gate” structure. Numerous combinations of compatible materials may be used for this gate configuration.

Figure 10-38. SEM micrograph of a T-gate structure. The physical gate length at the semiconductor surface is - 100 nm. The width of the body is -0.5 pm. (Micrograph courtesy of Beaubien (1992).)

of interference or multiple pass exposures, intentional misalignment, multilayer resists, shadowing, etc. can be used in either process to achieve very fine gate geometries (Wanget al., 1997).Trade-offs regarding the selection of a fine-line process must be determined vis-a-vis device and process complexity, yield, process cost, and reliability. Devices fabricated with these fine features show superior high frequency performance due to the small RC time constant and a short gate length. A variation on the T-gate was proposed by Tanaka et al. (1997). Herein

they formed a “spike-gate” structure, causing a buried extension of the T-gate to provide an extremely short gate length for power applications. The key to realizing successful device performance lies in the uniformity and reproducibility of the gate formation process, coupled intimately with the materials properties (thickness x doping product, charge profile, charge density, heterostructure etc.). Step and repeat lithographic systems can create minimum dimensions typically in the range of 0.25-0.5 pm in production environments. G-line (dimensions - 0.5 pm), I-line (dimensions -0.25 pm), deep U V (- 0.15 pm), image reversal processes, or Xray flood exposure can be used to photolithographically define the fine features. FiveX or ten-X projection systems permit the writing of finer features than one-to-one projectors or contact aligners. Electron beam methods are capable of achieving 0.1 pm line widths and can perform near this level in a low-to-modest volume production environment, the trade-off being that the systems are relatively slow, expensive, and limited to gate level exposures at the present time. As designers continue to push for higher frequency performance and device dimensions shrink, it should be recognized that processes must evolve that can work macroscopically at the near-atomic level: consider that a 0.1 pm gate stripe is only about 350 atoms wide, while GaAs sub-

-

560


strates are 100 mm in diameter, 150 mm substrates have entered production, and typical print fields i n a step-and-repeat camera are 15-20 rnm by 15-20 mrn.

10.8 Annealing Annealing processes are required for activating ion implanted species, passivating surfaces and electrically active defects, and relieving stresses between layers of dissimilar materials. The underlying principle is to induce controlled atomic exchange within the wafer by thermal excitation. There are two basic approaches to this process: fur-

Time(min.)

nace annealing (FA) and rapid thermal annealing (RTA). The two configurations are illustrated schematically in Figs. 10-39 and 10-40, respectively. Furnace annealing tends to be less stressful to the wafer as the rate of change of temperature is relatively slow, while the time at high temperature is relatively long. In RTA the object is to provide a rapidly changing, high peak temperature condition (typically hundreds of degrees higher than that in FA) to effect atomic level rearrangement in a very short time span. The drawback of RTA is the stress induced by rapid heating: the short time tends to preclude uniform heating and the exposure period is generally insufficient for ther-

______)

Figure 10-39. A schematic diagram of a furnace annealing system. In the upper section of the figure, the time-dependence sequence is illustrated. The key issues are a relatively slow temperature rise and fall, and a lengthy time at the peak temperature. The lower half of the figure shows wafers heating parallel to the gas stream to minimize stresses due to heat retention and radiativekonductive thermal exchanges. Safety systems are mandatory for handling effluent gases when processing most 111-V or 11-VI compound semiconductor materials.

10.8 Annealing

TMaX

56 1

Typical Maximum Temperatures -700-10OO0C 5-60 sec typical

Heating and cooling rates in the range -1 0 to 100’s of degrees per minute Room Temp Time(sec)

-

Figure 10-40. A schematic diagram of a rapid thermal annealing (RTA) system. In the upper section of the figure, the time-temperature sequence is illustrated. The key issues are a relatively rapid temperature rise and fall, and a relatively short time at the peak temperature. The lower half of the figure shows a wafer constrained between a graphite (or other material) susceptor. This configuration, typical of present commercial systems, can process one wafer at a time. The susceptor acts to supply heat uniformly to the wafer to prevent slip and s t r e w and to slow the actual rates of heating and cooling. Exhaust gases must be treated by combustion or scrubbing for safety.

mal equilibration. The primary difference between these approaches is the nature of diffusion and redistribution of the impurities and defects behavior) due to the different time- temperature cycles. Annealing may be used for repairing the minor atomic displacements associated with ion implantation without causing the recovery of the gross displacement damage, as required for isolation processes: or, with a larger thermal budget, cause the ion im-

(m

planted species to site select (activate) and occupy a substitutional position in the lattice while simultaneously recovering nearly all of the atomic displacement damage: and also, for strain-relieving multi-layer materials structures with dissimilar physical properties, as are found in all integrated circuit fabrication sequences. Passivation may be realized through the “healing” of surface defects, the consolidation of deposited films, and the in-/out-diffusion of mobile

562


species such as hydrogen (Pearton and Caruso, 1989). Annealing may be carried out using a variety of heat sources such as stripheaters (Banerjee and Bakar. 1985), furnace-based processes (Woodall et al., 1981; Shigetomi and Matsumaro, 1983; Hiramoto et al., 1985), and RTA methods using lasers (Tsukada et al., 1983), rapid-cycling high intensity heat lamps (various types of IR generators) (Chan and Lin, 1986; Crist and Look, 1990), or arc sources (TabatabaieAlavi et al.. 1983). The processes discussed here involve relatively high temperatures; low-temperature alloying and annealing processes are discussed relative to the formation of ohmic contacts i n Sec. 10.6. On comparing FA and RTA methods, one finds the net thermal budgets to be significantly different. As an example, a furnace anneal cycle at 850" C for 20 min is equivalent to a few seconds at 1000°C in terms of atomic diffusivities. In contrast, a typical RTA cycle may last only 5 or 10 s at 1000°C. During FA, the metastable defects and slightly displaced atoms relax during the heating cycle. While at temperature, longer range interactions take place, and site exchange and diffusion occur. During cooling, more active species continue to move slightly as the wafer returns to room temperature. The surface temperature achieved during RTA processes is not well-characterized as the heat sources (e.g., heat lamps) are operating many hundreds of degrees higher than the actual wafer temperature. Heat is being conducted and re-radiated from the surface region in a very dynamic condition. Also. the wafer topology may be very nonuniform: patterned layers of dielectric, metal, and semiconductor may be exposed, all of which have radically differing thermal and radiative properties. Thus strongly inhomogeneous thermal gradients are created in the wafer. It is the increased kinetic energy at

the higher temperature that allows for very rapid atomic exchange and thus for rapid recovery of lattice damage and impurity site selection. Since the time at elevated temperature is so short in the RTA process, typical dopant species diffuse distances of the order of a few nanometers rather than tens or hundreds of nanometers in the case of FA. When a substrate is annealed after ion implantation, the donor and acceptor impurities generally become substitutional in the lattice and charge is provided to the semiconductor. The net amount of charge depends on l ) the number of donor or acceptor species present; 2) site selection probabilities (interstitialcy, autocompensation effects, the ionization state in the lattice), and 3) the degree of lattice recovery (point defect concentrations). For example, n-type regions with electron densities as high as 5 x l O I 9 cm-3 have been created using very high dose implants (- 1015cmP2) and laser RTA techniques (Liu et al., 1980); p-type materials with hole densities up to 7 x lOI9 cm-3 have been formed using pulsed laser annealing (Kular et al., 1978). With furnace annealing processes, the peak charge densities achieved are somewhat lower than those obtained in RTA due to the quasi-equilibrium nature of the furnace anneal process. Typically, maximum n-type and p-type carrier concentrations of 3-5 x 1 0 ' ~cm-3, and 1-2 x l o i 9 cmP3,respectively, are realized i n GaAs with furnace annealing processes. Much effort has been expended in understanding and controlling the annealing process i n compound semiconductors, building on the experience developed in silicon wafer fabrication. Owing to the volatility of the group 11, V, and VI species, thermal annealing of the compound semiconductors poses significant challenges. The behavior of GaAs materials under various conditions of capping and/or arsenic overpressure have been

10.8 Annealing

studied at great length with widely varying results [see, for examples, Woodall et al. (198 l ) , Banerjee and Bakar (1985), Tsukada et al. (1983) Crist and Look (1990), Asom et al. (1988), Look et al. (1986), Parsey et al. (1987)l. Site selection of impurities is affected by 1 ) the statistical nature of the atomic displacements, 2) the exchange processes that must take place to create a substitutional impurity, 3) the competing formation of point defects and defect complexes, etc. Since, i n the compound semiconductors, there are two chemically and electrically distinct lattice sites, the charge state of an impurity can be either donor-like or acceptor-like, and in the case of interstitialcy the charge state may not be well-defined. Variations in activation have been attributed to inconsistencies in substrate properties (e.g., bulk and surface layer stoichiometry, impurities, out- and in-diffusion of both defects and impurities), the efficacy of “face-to-face” vapor exchange processes, and the interaction of the capping layers with the semiconductor surface layers (e.g., stresses, interdiffusion, contamination, etc.). The annealing of compound semiconductor materials may be carried out with or without a protective cap, or a group 11, V, or VI “quasi-equilibrium” overpressure atmosphere. In general, some method for maintaining the surface integrity is required to prevent decomposition of the surface regions due to the high vapor pressures of the group 11, V, and VI species, particularly with the phosphorus- or mercury-containing materials, The surface layers of compound semiconductors are subject to incongruent decomposition during heating due to the strongly mismatched vapor pressures of the respective components, as illustrated in Fig. 10-4 1 for GaAs, Gap, and InP (Panish, 1974). The vapor pressures of the group V species may be in the range of a few Pascal to many kilo Pascal at useable annealing

563

temperatures. Surface losses must be minimized lest the surface become conducting (more metallic) in nature as the surface becomes rich in the less volatile species. This latter effect will occur in the temperature regime about and above the congruent evaporation point. For GaAs-based materials, this is in the range of - 580-620°C (Panish, 1974), and similarly, for InP 480-500°C. The group VI species tend to have lower vapor pressures than the group V elements, and thus somewhat more relaxed annealing conditions prevail for most 11- VI materials, although the same phenomena must be considered. However, in materials such as HgCdTe, the vapor pressure of mercury is extremely high and the vapors are toxic. Great care must be taken to prevent decomposition of HgCdTe and related compound semiconductors. In furnace annealing of GaAs, the initial rate of free-surface decomposition is of the order of a few monolayers per second at 500-6OO0C, depending on the heating rate, temperature, and presence of an atmosphere. In an equivalent RTA process, an uncapped surface decomposes at initial rates of tens of nanometers per second in GaAs; these rates are higher for phosphorus-containing compounds. The use of an overpressure of As, or P, vapor can reduce or prevent the decomposition by balancing the surface dissociation rate, while a cap layer will completely suppress loss of the volatiles, although diffusion into the cap or wafer surface may become an issue. “Overpressures” may be generated by heating solid sources of the host material, from elemental or compound sources, or by injection of the volatile component vapor species. Open tube or closed ampul methods have been used: practical considerations i n the processing of large diameter wafers dictate the use of “open tube” methods, although significant safety measures must be

-

564

10 Compound Semiconductor Device Processing 104 K/T,(Ga- As, Xn- P

1

0

-1

-2

-3 c

-m

-4

0

-=

-6

- 1

-E

-
10” dyn cm-’ (1 O4 to > lo5 N), which is sufficient to alter the device electrical characteristics. This latter point is the result of the polar nature of compound semiconductor crystal lattices and resulting piezoelectric effects. The problem associated with such compositional variation is that the film properties are determined by the chemical make-up and may therefore be in conflict with the design requirements (e.g., the capacitance dielectric value or the isolation and standoff voltage capabilities). In the case of a dielectricover-gate stripe, stresses i n this critical area may shift the threshold voltage, which can lead to erratic circuit performance from thermal cycling effects. The metallization/ dielectric “sandwich” structures, e.g., capacitors or inductors, and multi-level metals, formed when passive components and interconnections are fabricated must also be stable to the thermal cycle. The respective materials properties and compatibility are very important if delamination or blistering resulting from excess stresses at the respective interface is to be avoided. In HBT devices, the breakdown voltage of the emitterbase or collector-base junctions may be reduced by improperly deposited dielectric layers. Interface and deep-level states may be passivated i n compound semiconductors by appropriate implantation processes (e.g., low energy protons), followed by a gentle, low-temperature annealing cycle (Pearton and Caruso, 1989). As hydrogen rapidly out-diffuses from compound semiconductors (Pearton et al., 1987), temperatures in the range of - 300-400°C must be used for the annealing process. Also, with this high diffusivity the thermal excursion and thermal budget of any subsequent process

567

steps are drastically limited if the effect of the hydrogen is to be maintained (see Sec. 10.3). Reproducibility of the annealing process in crucial in order to obtain reproducible device performance. The statistical nature of impurity site selection, and related compensation and defect formation processes, necessitates tight control of the annealing environment. If high temperature anneals are used, such as are necessary for ion implantation annealing, then considerations must be taken of the thermal history of the wafer from previous process steps, the impact on impurity and defect redistribution in subsequent processing, and the ability of the materials to withstand the additional thermal cycling. One of the conditions impressed on the fabrication sequence is that sequential steps must be carried out with continually lower thermal budgets to prevent uncontrolled reactions, undesirable phase formation, and additional in-diffusion and punch through of the junction and contact regions. Therefore, careful planning and a detailed understanding of the material’s properties and the thermodynamics and kinetics of the processes are required.

10.9 Dielectrics and Interlayer Isolation Electrical and mechanical isolation is required between the various layers of semiconductor and metals i n a device. For example, the formation of capacitors requires a dielectric material to isolate the electrode plates. In the case of an inductor the coil runners must be isolated from the substrate or any other metallizations. The formation of a capacitor is illustrated in Fig. 10-42. Typically, this structure is formed as either an n+ layer covered by a dielectric (Fig. 1042a), or as one of the first level metals cov-

568


Figure 10-42. Schematic cross sections of capacitor structures. In a) a channel-based capacitor is illustrated. In b) the capacitor is formed from the first and second level metals, with the dielectric between them. The thickness and perfection of the dielectric layer is critical to the leakage and breakdown properties of the structure in both cases. The effective areal dimensions of the capacitor are determined by the lengths of the upper level metal pad.

ered by a dielectric, followed by an upper level metal which defines the capacitor area (Fig. 10-42b). In this application, the properties and perfection of the dielectric layer are critical to the reproducibility and yield of the capacitors. An inductor may be formed as a spiral in a single layer of metal with a bridge or via to connect the center of the coil. Stacked inductors are also possible using multiple metal layers and vias. The complexity of modern circuit designs demands multiple metallization layers to interconnect the devices and the signal transmission lines, provide for power bus routing, and to permit adequate circuit comDaction. Each of these metal layers must be

isolated with a dielectric layer. The dielectric material must possess a suitable dielectric strength and dielectric constant, uniformity of thickness and physical properties, and be deposited with a high degree of layer integrity to minimize short circuits. The dielectric layers also play a critical role in controlling the density of surface states and pinning of the Fermi level at the semiconductor surface. These properties may affect the value and control of the device thresholds in MESFET, HFET (MODFET), and MISFET-type devices fabricated on GaAs, InP, and other compound semiconductor materials [see Daembkes (1991), and articles and references therein].

10.9 Dielectrics and Interlayer

The dielectric material serves to reduce surface leakage by “tying up” dangling bonds and passivating the surfaces. A dielectric layer may also be used to protect the compound semiconductor from chemical attack and contamination during processing, and to provide mechanical protection of the surfaces. An encapsulating dielectric film may be used to prevent surface decomposition during annealing procedures. This is a crucial application in most III-V and I1 -VI compounds due to the volatility of the component species. To assist in the formation of air bridge metallizations, dielectric layers may be used to form the post-andbridge structures. Thus understanding of the dielectric material, the deposition process, and potential interactions at the interfaces are critical for achieving reproducible device characteristics. It is an unfortunate fact that the compound semiconductor materials do not have the strong, stable native oxide available in silicon technology. For example, in GaAs the native oxides Ga20, and As20, ( y = 3.5) are very weak, being readily soluble in a variety of liquids. The suboxides (Ga,O and As,O) are quite volatile at common processing temperatures. These oxides, which form rapidly in air, are one source of interfacial states as the surface bond configuration and chemistry are strongly modified by the oxidation process. The native oxides also tend to be inhomogeneous in their properties due to strong local variation in the chemical composition and bonding (Watanabe et al., 1979). In part, this is due to the large difference in vapor pressure and reactivity of the constituent elements. Other oxide layers, for example those formed with glycol-based solutions, have been found to be electrically inferior to most deposited dielectric materials and have therefore received little attention (Hasegawa and Hartnagel, 1976). Dissolution of the group I11 and

569

group V oxides may readily be carried out with HCl- or NH,OH-based chemistries. This is convenient for surface preparation, but emphasizes the limited utility of the native species for integrated circuit applications. Thus alternative deposited dielectric materials must be used for CS device fabrication. For most applications, the suitable dielectric materials are SiO,N,, Si,N,., and SiO,. Device performance criteria dictate the optimum value of the dielectric constant. The dielectric constant depends strongly on the chemical composition; the composition of the materials is determined by the deposition chemistry and the apparatus configuration. It should be emphasized that these materials are rarely, if ever, stoichiometric. Therefore, care must be exercised i n deposition to achieve a homogeneous, uniform and low-stress film. The application of a dielectric layer embodies many compromises. Optimally, it is desirable to have a low dielectric constant for high-speed operation. The tradeoff in the use of SO,, Si,N,, and SiO,N, is the value of the dielectric constant: nitride films are best for capacitors, but the oxide is optimum for runners due to the lower dielectric constant and a resulting lower capacitance. Mixed oxy-nitride materials have dielectric constants intermediate between SiO, and Si,N,, which permits a compromise in the circuit fabrication-performance relationship. For example, the dielectric constant for SiO, ( x - 2 ) is significantly less than that of Si,N,. ( x - 3 , y-4) as shown in Table 10-7, along with other interesting dielectric materials. Alternative dielectrics have received some attention during the late 1990s for special applications. Circuit designers recognize certain advantages of “high k” dielectrics, but design and layout constraints may force impractically small dimensions, which obviate the advantages.

570


Table 10-7. Values of dielectric constants for selected dielectrics. Material

GaAs SiO? Si,N, Poly imide Ta20, TiO: SrTiO, Ah03

Dielectric con\tant (relati\e)

Reference

13.1 1-5 5 5-1 5 -3.5 20-25 1-1- I I O 50- IO0

Sze (1981. App. HI Williams (1990. p . 295) Williams (1990. p. 295) CRC (1978) William3 (1990. p. 295) CRC ( 1978) Nishitsuji et al. (1993) CRC ( 1986)

95

A lower capacitance may be realized with SiO.,, a highly desirable feature for highspeed circuits. However, much thinner SiO., dielectric layers must be deposited to achieve a given capacitance value (relative to materials with larger dielectric constants) or, alternatively, large areas of the circuit must be committed to these devices with the resulting cost increase and yield reduction. In the case of very thin layers, the integrity of the film becomes a yield-limiting factor. Most of these dielectric layers can be deposited with relatively low stresses, if the process is carried out under optimized conditions. Typical stress levels are in the range of 1O9--1O” dyn cm(10‘-106 N).Valuesof 10’ dyn cm ( 10‘ N ) or less are considered strain-free. while those above 10“’ dyn cm ( lo5 N ) can create problems with yield and reliability (layer adhesion. thermal cycling effects). Another issue with stress is the piezo-electric (PE) effects arising from the polar nature of the compound semiconductor lattice. Interlayer stresses may generate significant anisotropic threshold shifts due to the PE effects; thus the gate orientation with respect to the substrate crystallographic orientation becomes important. In Si.,N, films on GaAs, stress typically increases with increasing Si fraction. At the

same time, the dielectric film resistivity varies with the silane concentration in the deposition atmosphere, making the electrical isolation less effective, i.e., higher leakage currents may be observed. Hydrogen incorporation also increases with lower deposition temperatures. Excessive hydrogen content may cause dielectric “blistering” during subsequent high temperature processes. An optimum balance of the properties in silicon nitride materials has been obtained with “near-stoichiometric” film compositions (see Williams, 1990, Secs. 8.3.1, 13.3, and references therein). A caveat to the use of dielectric materials is the mechanical incompatibility between most such materials and the compound semiconductors. The thermal expansion coefficients of dielectric materials are typically quite different from metals or the host semiconductor. Thus deposition of the dielectric layer can increase the levels of stress during thermal excursions. Thermal cycling caused by device operation can produce failures in metallization lines and contacts from cyclic fatigue, particularly at steps and edges. This effect is illustrated schematically in Fig. 10-43. Cyclical stresses can also give rise to shifts in device characteristics arising from the PE effects in the compound semiconductor. The PE effects and the fabrication process-related phenomena. as they affect the device threshold and operation, must therefore be clearly understood to achieve proper and reliable circuit operation. The deposition of dielectric films may be carried out by a variety of techniques. Evaporation methods for dielectric material deposition are well understood but have limited applicability for compound semiconductor processing. This method suffers from exposure of the substrate to very high temperatures, dielectric composition control is very difficult. and variation in the film composi-

10.9 Dielectrics and Interlayer

571

Figure 10-43. Detail of a metal line over a dielectric step. With continued thermal cycling, the differential expansion may induce fractures and microcracking in the metal lines. Similarly, dielectric over-layers may crack due to expansion of the metals beneath. Steps and edges are most susceptible owing to the concentration of stresses.

tion occurs with time due to depletion of the various components from the source charge at varying rates. The control of stoichiometry and the materials properties are also complicated by the fact that elemental and molecular evaporation rates are very difficult to balance i n a high vacuum (HV or UHV) deposition environment. Sputtering methods may be used for deposition but surface damage can be significant unless great care is taken to optimize deposition processes. Stoichiometry is generally variable throughout the film on the microscale, which may affect the physical properties as well as the etching characteristics. Aging of the sputtering target(s) may also cause a gradual shift i n the dielectric composition and properties. Lattice damage can occur from ions and surface atoms being driven into the surface region: resputtering of surface atoms also occurs during deposition. It is critical that no low frequency (e.g., 455 kHz) excitation is implemented in these systems as the plasma will severely

damage any exposed semiconductor surface regions. Hydrogenation of the surface region is also a problem, especially with the use of silane, hydrogen, and/or ammonia feed gases. The incorporation of hydrogen in various forms alters the dielectric properties in an uncontrolled manner and produces a time-varying effect in the film, due to out-diffusion of the hydrogen species during subsequent processing, or even during device operation (Pearton et al., 1987). Standard CVD processes require relatively high deposition temperatures to drive the gas phase reactions. Typically, deposition takes place at temperatures greater than 500- 1000°C,which is incompatible with most metallizations used for ohmic contacts and interconnects. Temperatures in this range are also too high for most compound semiconductor materials: surface decomposition may occur during the deposition cycle, as the vapor pressures of the group V species, e.g., PA, and P,, for example, are significant at these processing temperatures

572


(see Fig. 10-4 1 , and Panish ( 1984), for example). The deposition method of choice appears to be plasma-enhanced chemical vapor deposition (PECVD). This is due to the relatively low temperatures (- 175-400 “C) developed in these processes, and the enhanced controllability of the reactor systems. The plasma serves to create energetic reactive species, with the energy imparted by electrical excitation rather than direct thermalization. The plasma may be generated with DC or AC fields, in a variety of system configurations: each approach has its proponents (Gupta et al.. 1983; Tsubaki et al., 1979). In PECVD processes the pressures are Torr (0.13 N typically of the order of m-2). The excitation in the plasma imparts energies in the range of a few hundred electronvolts or less. Thus there is only minimal surface damage due to free electron or ion bombardment (Meiners, 1982). The chemically reactive species are generated at low effective temperatures with the plasma. Only a very small fraction of the available molecules are ionized by these interactions: most of the plasma is neutral and therefore relatively “cool” and unreactive. The substrate may be heated or cooled, but it is necessary to raise the substrate surface temperature to only 150-300°C for high quality deposition. The self-heating effects during deposition can raise the substrates into this temperature range; active cooling may be desirable for process reproducibility. The low temperature of this process generally allows direct monitoring of the gas-phase reactions, reaction species, and by-products by the characteristic emission or absorption energies (Havrilla et al., 1990), or analysis of the exhaust stream by RGA techniques. These type of measurements can be readily adapted to process control or end-point detertinq.

The PECVD method offers great flexibility: the dielectric density, composition, refractive index, and dielectric constant can be varied by controlling the deposition conditions. The PECVD processes can be used to create layers of AlN, Si,N,. , SiO,, Ta,O,, TiO,, and other materials. AlN appears to be a promising new material for use in GaAs and related materials. It possesses a thermal expansion coefficient well matched to GaAs, but the deposition-related damage is presently significant and the material is rather hard to remove without creating additional damage to the surface (Gamo et al., 1977). Growth rates in PECVD tend to decrease with increasing operating pressure or higher deposition temperatures, while the refractive index generally increases with a higher deposition temperature. Suitable gases for deposition and etching are reactive species: chlorines, fluorines, ammonia, silane, hydrogen, oxygen, and nitrogen-containing compounds. Noble gases such as argon may be used as diluents to moderate the deposition process. The major drawback to utilizing PECVD processing is that the process has many variables: gas pressure, chamber and substrate temperatures, flow rates, gas compositions, etching rates, the evolution of by-product materials, the electrode geometry, the excitation method (DC or RF and excitation frequency), the input power, the plasma energy density, the system configuration, substrate rotation, etc. (Gupta et al., 1983). These variables present a formidable obstacle to process development, and complicate process control. For process consistency, contamination from pumps, leakage at vacuum seals (processes are not operated in UHV conditions), chamber materials, and residual species such as Si, 0, H, C, N, etc. must be considered. As a result, a stable, robust operating condition can be difficult to achieve and sustain. Another concern in the PECVD

10.9 Dielectrics and lnterlayer

method is that deposition occurs over the entire chamber, complicating the control and stability of the process. Careful maintenance and consistent cleaning are required to maintain process integrity refully designed experimental methods‘and the application of statistical process control monitoring, a robust and reproducible process may be obtained (Havrilla et al., 1990). Barrel (or plate-type) PECVD reactor designs can be used for deposition (or etching) processes (Fig. 10-44). In a barrel reactor the electrode plates in the chamber may be neutral or floating relative to the ground potential. Various susceptor and chamber configurations are possible. Biasing the wafer plate can enhance or retard the deposition process, or alter the selectivity of the deposition. A low energy ion flux is thus created between the upper plate and the wafer surface. Local perturbations in the electric field on the wafer surface can readily deflect the incoming ions. It is generally more difficult to control an etching process on a fine scale in this type of system, due to the low ion energy and small accelerating field strength. This makes a barrel-type reactor best suited for relatively coarse processes, e.g., deposi-

573

tion of thick, noncritical layers, etching of large features, or ashing of photoresist layers, due to problems associated with localized and nonuniform electric fields on the metallized and/or patterned wafers. Controlled gas flows, critical to achieving a uniform etching process, are also difficult to maintain uniform in a barrel design due to nonuniform and nonsymmetric heating effects, convection, and generally asymmetric injection and pumping of the effluent species in commercial systems. Radial flow, rotating susceptor reactor designs have proven quite good for achieving uniform film deposition. A generalized configuration is shown in Fig. 10-45. New commercial systems, such as those developed by ElectroTechTM,or PlasmaThermTM, are capable of 1?k control of thickness over a 3”(76 mm) diameter GaAs wafer (O’Neill, 1991). In this configuration the electrode temperature can be controlled, if desired, to enhance or retard the surface reaction rate. Reactant gases and ion species are much better distributed in the radial reactors relative to the barrel-type designs which leads to improved film characteristics and thickness uniformity. In a radial reactor the plasma is

Figure 10-44. A schematic illustration of a RF-excited, barrel-type configuration for PECVD of dielectric films. The plasma above the wafer creates the active species for deposition. The energy of the excited species may be quite high and cause damage to the semiconductor surface. Susceptor rotation may be incorporated to improve uniformity. Heating and bias may be supplied to the wafers to assist deposition

574


Figure 10-45. A Achematic illustration of a high-performance. radial flow configuration for PECVD of dielectric films. The p l a m a is generated above the wafers. creating the active species for deposition. A radial flow is set up by the injection and exhaust configuration. improving the uniformity of the deposition. As in most plasma-type sy5tems. the energy of the excited species may he quite high and cause damage to the semiconductor surface. Susceptor rotation may be incorporated to improve uniformity. Heating and bias may he supplied to the wafers to assist deposition

confined between the excitation plates, with a quenched region adjacent to the plate surfaces (space charge region). Ions are accelerated through the space charge region by the electric field and impinge on the wafer surface. Several investigators have introduced "downstream" ( indirect ) systems . wherein the plasma excitation and active species are generated "upstream" (with respect to the location of the substrates and the gas flow), well removed from the deposition region. The reactive materials are extracted from the source cell with the gas stream, and flow across the wafers. Deposition occurs on the wafer surface if the thermal conditions are appropriate. This configuration is shown in Fig. 10-46. It has been found that the use of such a downstream deposition process greatly reduces the plasma-induced ion damage in the surface regions (Meiners,

1982). A limitation to this approach is the total reactive ion current extractable from the source and the lifetime of the ionized species in the gas stream. Another approach to CVD deposition is photo-stimulated CVD. In this embodiment, a CVD chamber is fitted with windows to permit selected-wavelength light to impinge on the gases and/or the substrate. The added stimulation generates the desired species with reduced electrical energy input. The technique has advantages similar to PECVD: low deposition temperatures as well as a great selectivity for the excitation of specific molecular species by choice of the optical excitation energy (Peters, 1981). Photo-enhanced CVD induces less surface damage than the standard PECVD techniques, and by utilizing a downstream type configuration direct ion bombardment damage of the surface can be avoided.

10.9 Dielectrics and lnterlayer

575

Figure 10-46. A schematic illustration of an ECR-plasma CVD system. The plasma is generated by tuned electron-cyclotron resonance of the desired species in a cell well removed from the deposition region. A carrier gas flow or extraction potential transports the active species to the wafers. Minimal damage is imparted in the wafer in this configuration. Rotation of the wafers may be provided to improve the uniformity of the deposition. Heating or bias may be supplied to the wafers to assist deposition.

Electron-cyclotron resonance (ECR) is a relatively new method for creating a plasma while mitigating the damage induced by the ion and electron bombardment (Kondo and Nanishi, 1989; Takamori et al., 1987; Sugata et al., 1988). Here the plasma excitation is provided in the usual manner with the addition of a very high frequency RF excitation signal. Selective excitation is achieved by choosing the excitation frequency to resonate with the desired ion species cyclotron frequency. These selected ions absorb the energy and create the plasma for deposition. A relatively high excitation power is required in this approach, and therefore the downstream configuration is used for obvious reasons. Another class of dielectric materials are polyimides. These materials are polymeric organic films with relatively low dielectric constants: typical values are - 3.5. Polyimides are very stable dielectrics: some compositions are capable of tolerating exposure to temperatures greater than 500 "C (Dupont, 1976). These materials are best suited as an encapsulant or capacitor dielec-

tric, for inductor isolation, or for isolation of second (and higher) metal levels. These materials are also useable for the standoff of metal runners in air bridge configurations, although the large capacitances may present a problem at very high frequencies. Moisture absorption and swelling can be an issue with polyimide materials. Incorporation of those layers must take packaging integrity into account to ensure long term reliability. Polyimides may be deposited with dispensehpin systems, as are used for photoresist coating. The major drawbacks to the application of polyimides are: 1) the extended curing time required to drive off the solvents and crosslink the polymer chains (ca. 1 h or more at elevated temperatures), and 2) control of the thickness owing to the high viscosity of the liquid phase. Following the curing, the polyimide film can be patterned with standard photolithographic methods. However, only specific etchants and some plasmas will attack polyimide materials. They can be etched with oxygen plasmas (asher), or with strongly basic solutions. Appropriate solvents or alcohols

576


may also be used for pattern development, but care must be taken to minimize softening or other damage to the film. One great advantage of the polyimides is their dielectric strength: typical values are - IO6 V cm-'. This property, coupled with the high dielectric constant, makes these materials very attractive for use in high voltage circuits or for achieving very fine feature sizes. In PECVD and related deposition methods, film growth rates are i n the range of 10-50 nm min-', and useful films are typically 50- 1000 nm thick. The polyimide film thickness is controlled through the fluid viscosity and the spin speed and acceleration program i n the spinner system. Very thin films (< 100 nm) can be deposited, but integrity generally suffers. All types of dielectric films can be evaluated with standard ellipsometric instruments to determined thickness and the dielectric constants. Other instruments, such as interferometers, are used to determine the compressive or tensile stress conditions in the deposited films. Pinholes or failures in the film integrity are a continual problem resulting from wafer surface contamination, the formation of large clusters or particulates i n the plasma and on the chamber surfaces, or difficult surface topology. Multiple process cycles can be used to alleviate or minimize this problem. The impact of dielectric films and surface states on the channel saturation currents (J,,J, the device threshold voltage ( Vth), and reverse breakdown voltage ( Vbr) effects are poorly understood. Sputtering of PECVD typically produce ion damage depths less than 50- 100 nm, but can have a damage depth in GaAs up to twice the expected ion range under improper deposition conditions (Williams, 1990, Chap. 9). Significant surface depletion effects occur from this damage, and can result in erratic device behavior. The surface state effects are especially

important for enhancement mode or lowcurrent devices, where the charge is very close to the gate or of low density, and thus the conducting channel is more sensitive to local perturbations in the surface electric field strength. Post-growth annealing may help stabilize the dielectric film properties by equilibrating the interface charge balance and the interfacial chemistry, and also relaxing built-in stresses (Weiss et al., 1977). All of these issues are crucial to the fabrication of high-performance, high-reliability integrated circuits in compound semiconductors, and are the subject of continuous investigation and development.

10.10 Resistors Biasing networks, feedback control, voltage and current dividers, load terminators, and balancing applications all require the use of resistors. Resistors may be formed utilizing the conducting channels (active regions) in the surface of the wafer, or constructed as separate thin film layer structures. The channel-based resistor structures may be formed using the n-layer to the n/n+ layers (ion implanted or epitaxially grown layers), as illustrated in Fig. 10-47a. This approach demands tight control of the sheet resistances in the layer(s) for a controlled resistance value. A thin film resistor is typically deposited above the first dielectric layer, as shown in Fig. 10-47b, but may be placed in any convenient location within a multi-layer metal scheme. A resistor requires a conductive stripe and at least two contacts. A channel-type structure will require some form of peripheral isolation to define the resistor body dimensions. Thus the fabrication of resistors must be carefully considered when planning the process sequence. Either a trench, mesa, or ion implantation scheme must be used to

10.10 Resistors

577

Figure 10-47. In a) a cross section of a channel-based resistor is illustrated. The effective length of the resistor is “I”. Ohmic contacts define the effective length. The width is determined by perimeter isolation [mesa or implant (shown)]. A dielectric layer is used to protect the resistor body during subsequent processing steps. Figure IO-42b illustrates a resistor structure made with a thinfilm resistor material. The layer is deposited on a dielectric as shown, and patterned by photolithographic methods. Metal contact pads are deposited and patterned on the ends of the resistor. Taps may be placed along the resistor body, if required. The effective length of this resistor is I , with the width determined by the lithography. Controlling the thickness or the chemical constituents in the film provides a high degree of control over the resistor properties.

define the body of the resistor and to isolate the contact region for channel-type resistors; deposited film resistors may be defined by photolithography and etching or lift off processes. Greater latitude is permitted for the deposited film structures built on dielectric layers, as the resistor bodies can meander over the surface (with some restrictions) without consuming valuable active area. A larger range of resistivity values is accessible to the thin process relative to the channel-type structures. The processing asso-

ciated with the resistor fabrication must not exceed the thermal constraints of the preceding processing sequences. The resistance value ( R )achieved in a resistor is defined by the relationship (10-12)

where p is the resistivity of the conducting medium, L is the length, and W is the width of the resistor body; t is the layer thickness, implant thickness (- 2 A R J , or the total ac-

578


tive epitaxial layer thickness, 2 R, is the sum of the contact resistances, and W, is the effective contact width. A resistor structure is shown in detail i n Fig. 10-48. If multiple conducting layers are used in the resistor stripe, such as in an n+-n layer structure, Eq. (10-12) is modified to accommodate parallel conduction effects. For practical resistor structures, the contact resistance will be negligible (typically much less than one percent of the resistor value), and well within the resistor process variations. Resistors formed with the semiconductor conducting layers are relatively easy to implement. No additional mask levels are needed as the channel can be patterned with the process sequences of ohmic metallization and isolation. Typical resistivity values are in the range of 100- 1000 R/ 0 , but this range may easily be extended with additional ion implantation and annealing steps. If the resistor is isolated with a mesa etch, then additional process steps may be necessary. The topology and design rule limitations with a mesa configuration must be considered in light of subsequent process steps and consumption of semiconductor area (cost). The implementation of channel-type resistors has several drawbacks: surface depletion (surface states) can affect the charge in the resistor stripe, surface potential offsets may arise with dielectric deposition, a relatively large temperature coefficient of

-

resistivity exists (bandgap energy coefficient, impurity ionization, mobility effects) saturation of the current-carrying capability can occur, heating or cooling effects alter the charge density and carrier mobility, and slow domain oscillations and high frequency (Gunn-type) oscillations can arise from charge injection into the substrate. All of these effects, described below, compromise the performance of such a resistor structure. Careful layout (with respect to power distribution busses, proximity to critical nodes, etc.) is necessary to minimize interactions with the resistors and other circuit components. The realities of device fabrication manifest themselves in resistor structures in the following manner. Surface depletion can decrease the available charge in the resistor stripe, and generally leads to higher resistance values than expected. Owing to process-induced variations in the layer thicknesses, charge density, dimensional tolerances, surface states, and surface contamination effects (leakage currents), the resistance may actually increase or decrease in an uncontrolled manner. Layers of high sheet resistivity, with their correspondingly low-charge density, are more susceptible to these variations. The application of a dielectric film will tend to ameliorate the effects of surface states, but can aggravate control of the resistance owing to the generation of stress and piezoelectric effects.

Figure 10-48. Detail of a resistor structure showing the critical dimensions and features. The contact resistance is predominantly at the interface of the metal and the semiconductor. The bulk resistivity determines the dimensions of the resistor relative to the needs of the circuit design. W , is the effective contact width, W is the effective width of the resistor stripe, t is the effective thickness of the layer, and L is the effective length.

10.10 Resistors

The magnitude of these effects in subject to the dielectric film composition, surface preparation, and deposition conditions. Thermal effects must also be considered, as carrier mobilities decrease with heating (proportional to T-3’2). Thus the resistor value increases when significant power is dissipated in the circuit or the resistor. In addition, when temperatures are very high (> 100 “C), the effects of band-gap narrowing may also begin to influence the transport properties, again altering the resistivity. This behavior is of importance to the designers, as compensation networks may have to be build into the circuit to accommodate these changes in resistance. Since the resistor body in this configuration is essentially the transistor conducting channel, it is subject to the same current saturation limits as the transistors. For most compound semiconductor materials, channel saturation occurs at electric field strengths of - 1000-5000 V cm-I (Sze, 1981d, pp. 44, 325). While these effects can be mitigated by careful design and control of the voltage drop across the resistor, it presents an additional restriction for the device designer and process engineer. Attempts to exceed the saturation values will lead to excessive heating and accelerated failure. Critical field effects may arise from both DC and AC operating conditions when the resistors are biased. Above the critical field strength, charge may be injected into the regions surrounding the resistor (isolation regions or the semi-insulating substrate). Selfoscillations may then occur in the compound semiconductor material. These oscillations may be realized as “slow domains” (Ridley and Walkins, 1961; Ridley and Pratt, 1965; Kaminska et al., 1982, and Sec. 10.3.3) or high frequency, Gunn-type oscillations (Sze, 1981, Chap. 1 I). In GaAs slow domains can be created when the electric field strength exceeds roughly 500- 1000 V

579

cm-I (Kaminska et al., 1989); Gunn oscillation are created at a field strength in excess of roughly 3000 V cm-’ (see (Sze, 1981 d, Chap. 11). The oscillations will add to the dispersion in the device characteristics. A major consideration in the use of channel resistors is the heat dissipation. The thermal conductivity ( K ) of GaAs is only - 0.48 W cm-’ K-’ (EMIS, 1990, Sec. 1.8), and the thermal diffusivity is only -0.27 cm2 s (EMIS, 1990, Sec. 1.9). In InP these values are 0.56 W cm-’ K-I and - 0.4 cm2 s, respectively (EMIS, 1991, Sec. 1.8 and 1.9). Therefore care must be taken to avoid excessive local heating and thermal runaway conditions, particularly if a resistor body is adjacent to an active device. The last concern for channel-type resistors is the large distributed capacitance which arises from the depletion effects along the length of the resistor. The capacitance is of particular concern for “long” resistor stripes (high-resistance values), which can lead to intractable RC time constant problems and a significant reduction in device operating speeds. Inductive parasitics also arise with long meandering resistors, which again can limit high-frequency operation and create unexpected operating instabilities. Thin film resistors may be constructed on the semiconductor surface (with implant isolation beneath the resistor body and contact regions), or above the first or subsequent dielectric layer(s) by the deposition and patterning of thin layers of Cr, Ni-Cr (nichrome), TaN, or other materials (see Table 10-8). These resistor films have specific resistance values in the range of - 10-1000 R/O which provides a suitable range of resistor values. The deposition and patterning of these films on the semiconductor surface are subject to many of the effects that affect the channel-type structure de-

-

580


value. a trimming capability (laser trimming or focused ion beam (FIB) repair), reduction of the distributed capacitance, and design and layout flexibility at the expense of an additional masking level. The thin films are typically less than 100 nm thick, and therefore have a limited impact on the topology. Evaporation and sputtering processes are the deposition methods used for resistor fabrication: plating processes are insufficiently well controlled. A caveat with these thin film structures is that continuity is strongly affected by pinholes and inhomogeneities in the film. Therefore, a robust, high integrity film must be produced (slow deposition rates and multiple passes are recommended). High current densities in the thin film resistor can result in electromigration problems, localized heating, and catastrophic failure, particularly at the junction of the contact pad and the resistor body. These effects are similar to electromigration failures in drain/source or gate metallizations. This failure mechanism is illustrated schematically in Fig. 10-49 (see Magistrali et al.. 1992). The adhesion of the resistor film to the semiconductor or dielectric material is a critical issue. This problem is typically surmounted by the deposition of a dielectric layer over the resistor to protect the thin film layer from damage, stresses, and confine the film. Control of the resistance value is in-

Table 10-8. Thin film resistor materials". Metal

Resistivity range

(R/O 1

Temperature coefficient (ppm K-' )

~ _ _ _

Cr TI NiCr TaN

I? 55-135

60-600 280

3000 2500 200 - 180 to -300

From Willmrn5 (1990. p 306)

scribed above. The formation of a thin film structure involves depositing a uniform layer of the resistor material, then photolithographically defining the appropriate pattern. Etching of the exposed material is carried out using plasma-etching techniques. Lift-off methods may also be implemented, using photoresist or dielectric-assisted techniques. Contact metals are then deposited on the resistor stripe as desired, patterned, and annealed to alloy the contact to the resistor body. Tapped resistor structures can be readily fabricated. These tapped resistor structures may be used for tuning high-frequency response or circuit gain characteristics, using laser ablation or current pulses to break the film at a desired 10cation. By depositing the thin film layer on the dielectric, numerous advantages are gained: relatively easy control of the resistance

Region of Failure

-

Material Migration Material Pile-up

-

Current Crowding

Figure 10-49. A schematic picture of film resistor failure. The electromigration-induced transport of material ("electron wind") causes a high resistivity region to form near one contact. Some material is transported to the oooosite end of the resistor. The loss of material creates a "hot spot" which ultimately fails catastrophically.

10.11 Metallization and Liftoff Processes

fluenced by the variations in film thickness, defined width, and film composition. Film resistors may be trimmed by laser ablation methods to “fine tune” the resistance value at the time of testing. More recently, with the advent of the FIB techniques, the resistor stripes may be repaired, or built-up, albeit this approach is presently limited to very costly circuitry. Fringing capacitance effects are minimized by the use of deposited film resistors, as the charge in the semiconductor is well removed from the resistor stripe. The dielectric constant of the dielectric layer may be optimized and a minimized capacitive coupling may be effected with a thin film structure. This can lead to significantly reduced RC time constants relative to channel-type resistors. In principle, the limit to current flow in a thin film resistor is the maximum current density supported by the material. This is constrained practically by electromigration phenomena, the heating-related effects, the materials’ temperature coefficients, and the maximum power dissipation of the resistor and substrate materials. As the dielectric materials are well behaved, there is little concern for charge injection, oscillations, and nonlinearity in the thin film structures deposited on dielectric layers even when operated at high bias levels.

10.11 Metallization and Liftoff Processes A metallic conductor is required to provide the interconnection of devices, interlevel and back-plane connections (vias), and for electrical and thermal conduction paths to the external environment. The conductor material must have the following properties: a high electrical and thermal conductivity, be electrically and mechanically stable, be chemically inert yet paternable by fabrica-

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tion-compatible chemistries, possess good adhesion characteristics, be corrosion resistant, ductile, and compatible with the processing sequences which follow the deposition and definition steps. The key issue for metallization and interconnect processes is minimizing the electrical resistivity in runners and vias to prevent excessive power dissipation and the concomitant loss of signal, as well as the operating speed limitations due to RC time constants and heating effects, while utilizing minimal geometries. Au, Al, Ti, Ta, W, Ge, various silicides, and numerous gold-based alloy materials are compatible with most compound semiconductor processes (Howes and Morgan, 1985, Chap. 6; Williams, 1990, Chap. 11). However, to prevent undesired chemical and metallurgical reactions, many of these materials must be used i n a “multilayer” configuration, i.e., a barrier layer and high conductivity “bulk” metal(s). In addition, the interconnection metal must be stable to electromigration processes which arise at current densities above - lo5- lo6 A cm-2 (Davey and Christon, 1981; DiLorenzo and Khandelwal, 1982, p. 345; Williams, 1990, Chap. 20; Irvin, 1982). Furthermore, this stability must be maintained under highly stressful testing and operating conditions, e.g., accelerated aging, testing and operation at elevated temperatures, high bias, and high humidity. Only then can a material be called suitable for use i n compound semiconductor devices. Unlike the aluminum metallization common to silicon-based products, metallizations for CS devices must be stable for tens of thousands of hours at very high operating temperatures, ca. 200 - 250 “C. Metallization schemes are a major issue in IC interconnects. A “two level” process prevents minimal dimension devices from being fabricated due to the dominant problem of power routing. Thus lower perfor-

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mance, lower yields and higher cost circuits would be realized. Three-level (Lee et al., 1989) and four-level (Vitesse, 1990, 1995; TriQuint) interconnect schemes provide for flexibility in signal and power routing, and allow for significant circuit compaction and optimization of the signal and power distribution. In multi-layer metallization schemes, the control signals are typically carried in the lower layers, while the power distribution and ground connections are handled in the upper layer(s). Vias are used to complete the interlayer connections. A commercial four-layer metallization process is illustrated schematically in cross section i n Fig. 10-50. In this figure. the interconnection is made from an upper metal layer to a lower level metal directly. The multi-layer configuration shown i n Fig. 10-51 is a "post-andrunner" structure. The interconnect layers would be created by sequential metallization over dielectric, patterning, and some form of via-fillhelected-area metallization. The interconnect runners are formed by aluminum or gold-based metal deposition

I

v Passivation Dielectric

processes, and photolithographic patterning techniques. The posts may be formed during the interconnect metal deposition or, for example, selective-tungsten CVD processes (Wilson et al., 1993) as shown in Fig. 10-52. Each subsequent metal layer is generally printed with a slightly larger critical dimension as a result of circuit topology constraints. A substantial amount of planarization may be realized as a side benefit of the larger dimensions. However, as is evident in Fig. 10-52, this is not always required. So far. chemical-mechanical polishing has not been necessary in CS device processing. This is due partly to the greatly relaxed geometries necessary to obtain extremely high performance in CS devices, and the somewhat lower integration levels common to CS applications. The number of mask levels in CS processing rarely exceeds 13- 15 plates, even for highly complex circuits in the range of 100000 to 500000 gates (Brown et a1.,1998; Vitesse, 1995), whereas a bipolar silicon process might have 28-30 plates, or more, giving rise to very rough to-

Mask levels

1

w

Technology

4 Layers of Aluminum Interconnect

Conventional state-otthmrt Silicon Interconnect

GaAs

Proprietary to Vitesse

I

ij

MESFET

Figure 10-50. A schematic cross section of a four-layer interconnect metal scheme. Aluminum is utilized for the upper level metal layers i n these MESFET ICs. (Figure courtesy of C. Gardner, Vitesse Semiconductor Corooration. Camarillo. CA.)

10.1 1 Metallization a n d Liftoff Processes

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Figure 10-51. Details of a “post-and-runner” multi-level metallization scheme. Two levels of metal are shown above the ohmic contact. The via plug may be formed by selected area chemical vapor deposition or by blanket deposition and etching. A substantial amount of planarization may occur in this type of structure as the dielectric layer tends to smooth out height variations and steps. This structure may be continued above the two layers by successive depositions and patterning.

Figure 10-52. An SEM cross section micrograph illustrating the details of a four-layer “post-and-runner’’ metallization process. The via plugs are selected-area CVD tungsten, with a titanium adhesion layer and gold main metal on each tungsten plug. The magnification marker is 1 p m ; the via diameters are approximately 1 p m , and the interconnect metal layer thickness is approximately 400-500 nm. (Figure courtesy of Dr. M. Wilson, Cray Computer Co., Colorado Springs, CO.)

pology. In any case, the larger dimensions of the upper level metallizations have the distinct advantage of a higher current carrying capacity, ideal for low-loss power distribution busses. A four-level “post-andrunner” metal interconnect scheme is shown in a SEM micrograph (Fig. 10-53). This type of multi-layer process has proven to be reliable and manufacturable with high yields (Mickanin et al., 1989; Wilson, 1989). The circuit compaction permitted by multi-level metallization allows for significantly improved high-speed performance. This is achieved predominantly by optimizing the routing through various levels of interconnect and minimizing the distance between critical nodes in the circuit. At present, the use of fourth metal-level power

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Figure 10-53. An SEM micrograph of a four-layer "post-and-runner" metallization process with interlayer dielectric removed. This figure illustrates the beauty and utility of the multi-layer metallization process. The fine geometry lines are gate fingers of nominally I p m i n dimension. The increasingly larger metal lines are evident at higher levels. (Figure courtesy of Dr. W. Mickanin. TriQuint Semiconductor, Inc., Beaverton. OR. 1

routing with relaxed design rules can approach 50% surface area utilization for both power and ground distribution lines (Vitesse, 1990). Since adding an additional metallization layer only requires relaxing the critical dimensions (due to surface topology). a via process, and a dielectric layer, there is no theoretical limit to the number of levels of metal. The performance requirements of up to 50- 100 GHz and a million or more devices do not demand development above four or perhaps five metal levels. 10.11.1 Metallization

In the manufacture of compound semiconductor devices, the interconnect metallizations are still predominantly gold and gold alloy based. Aluminum-based metallization processes are being introduced to fabrication sequences (see Vitesse, 1990), but the use of aluminum and aluminum allow. while well understood i n the silicon in-

dustry, is subject to the same constraints as are found in silicon processing: e.g., the formation of Au-A1 intermetallic compounds with undesirable high resistivity (e.g., "purple plague", see Irvin and Loya, 1978; and Irvin, 1982), and concerns for long term reliability from alloying materials such as copper, modest current carrying capability, and wire-bonding issues. To minimize the metallurgical reactions and rapid in-diffusion of gold, barrier metals such as Pt, Pd, W, or Ti must be used between the contact layer (semiconductor or metal) and the gold interconnect layers. While there barriers perform the function of blocking the intermixing of the contact metals, they add complexity to the process sequence, and ultimately act only to slow the eventual intermixing process. Numerous metallizations have been tried in the compound semiconductor field. The reader is referred to Sec. 10.6, and Howes and Morgan (1985, Chap. 6), for additional supporting discussions. As the processing of compound semiconductor devices matures, aluminum alloys are being used in an increasing number of applications. Aluminum and aluminum alloys have the distinct advantage of being patterned readily by reactive ion etching, ion milling, or lift-off methods, as well as relatively low cost. Gold can be effectively patterned by lift-off or ion milling processes. Submicrometer features may be patterned readily in any of the common metallization systems used in compound semiconductor device fabrication. The aluminum layers are commonly alloyed with copper to stabilize the material against electromigration failure. In silicon devices, copper has not been found to affect device performance. For GaAs, copper is a deep acceptor with at least four deep levels in the lower half of the energy gap (see Fig. 10-3) (Kullendorf et al., 1983). This can give rise to slow transients and erratic de-


vice behavior under certain bias or operating conditions (strongly related to device design and structure). For GaAs digital applications, the AI-Cu system (with barrier layers) appears to be suitable. In the case of RF or mixed signal applications, the process sequences and device structures and operating points are significantly different, and may result in compromised device performance. In InP materials, copper has at least three deep acceptor states, and, in fact, high concentrations of copper give rise to a semiinsulating characteristic and copper precipitation (Leon et al., 1992). Thus great care must be exercised when using AI-Cu metallizations. Gold-based interconnects, on the other hand, are problematic in the silicon case (carrier lifetime-killer centers), but are highly effective for compound semiconductor devices, and have been field-proven as reliable for more than twenty-five years. Typically, gold-based gates and interconnections are utilized in processes that do not use ion implantation beyond the formation of the junction, isolation, and contact layers. This is due to the rapid diffusion and metallurgical reactions which occur at temperatures of - 350-500°C in most compound semiconductors. A common interconnect metallization used in GaAs device fabrication is the Au/Pt/Ti system (Niehaus et al, 1982). Here the titanium layer is used to enhance the adhesion. The platinum layer acts as a diffusion barrier against gold interdiffusion, and to mitigate the reaction of titanium and gold which occurs at -200°C. Since gold and platinum have high conductivity, this “sandwich” structure produces very low resistivity interconnects. An interconnect for higher temperature applications is based on Ti-W/Au. The Ti-W layers are used to contact the semiconductor and provide a diffusion barrier to the gold, while the gold layer carries the majority of the current. This contact has been found to be stable

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to - 50O-60O0C, although adhesion problems due to differential thermal expansion (stress), and degradation mechanisms are not yet completely controlled. In addition, sputter deposition must be carefully controlled to prevent leakage currents due to surface damage (Kohn, 1979; Day et al., 1977). Interdiffusion is a problem with a number of desirable materials due to the reactivity of GaAs and InP with a wide range of metals. These reactions are well understood through the phase relationships for these systems. For example, aluminum on GaAs interdiffusion has been observed at - 250°C andextended times (Mukherjee et al., 1979; Sealy and Surridge, 1975). It should be noted that for aluminum-based metallizations, 250°C is quite near the “2/3 melting point” criteria used in metallurgy for defining stability to interdiffusion, and thus such interactions are expected. For further understanding of potential intermetallic phase formations, see Massalski (1986). As previously discussed, barrier metals or alloying elements can be used to improve the stability and minimize interdiffusion in the contact regions. High temperature interconnects and metallization are used when the wafer may be subjected to high processing temperatures as required for ion-implantation annealing. These materials were discussed in Sec. 10.6 in the context of gate formation. Such interconnect configurations are typically constructed from refractory metals such as Ti-W, W-Si, Ti-W-Si, W-N, Ta-N, and Ta-Si (some of these materials may also be used for thin film resistor stripes). It has been found that these materials withstand temperatures well in excess of 850 “C without significant interdiffusion [see Dautremont-Smith et al. (1990)l. There are significant limitations in the metal line widths, achievable by different patterning methods. The electron beam

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(e-beam) writing system has achieved dimensions below 100 nm in the laboratory, but this is a very daunting proposition for the fabrication line where control. low cost, and reproducibility are required. An example of a -0.1 pm e-beam-exposed. T-gate structure was shown in Fig. 10-38. Typically. gate dimensions as small as 0.35 pm are printed by step-and-repeat systems (Williams, 1990; Wilson et al., 1993), whereas “0.25 pm” or smaller technology is implemented with e-beam methods (Danzilio et al., 1992). Smaller gate features require multi-layer offset photoresist patterning. electron beam, or other short wavelength processes such as deep ultraviolet exposure. Owing to instrument throughput constraints, the e-beam is only used to write the finest gate features. not the general metallization patterns. The step-and-repeat systems can control line widths down to 0.4 pm using the G-line, and 0.3 p m using the I-line, from high intensity mercury vapor light sources. Figure 10-54 shows a 0.36 pm gate feature defined by G-line exposure. Finer features can be produced by careful control of the photoresist thickness, exposure conditions. multi-layedmulti-exposure photoresist and metal thicknesses. Figure 10-55 schematically illustrates a method of offsetting multiple photoresist layers and implementing directional metal deposition to achieve finer metal line geometries. In the upper metallization levels there are fewer constraints in the metal line dimensions, but patterning and dimensional control may be complicated by the topology. Partial planarization by dielectric deposition can relieve these problems. Ion milling or sputtering methods may be used for metal pattern definition. This process requires a high vacuum system and appropriate high current ion sources or plasma excitation systems. In the ion milling process. a high flux ion source is used to sput-

-

-

ter the unwanted metal atoms from the exposed surface. In sputtering processes, an ion plasma is created above the wafer surface which removes metal atoms by physical sputtering processes. Argon, or chlorinecontaining compounds, are typically used for the source gases. Nitrogen gas may be added to ballast or control the ion milling rates. The patterning of fine features is limited by the spacing of adjacent metal runners due to shadowing of the ions by the topology of the metal and the pre-existing wafer surface. The photoresist or other defining layer (e.g.. a second metal, a dielectric layer, or a combination of photoresists and metals or dielectrics) add to the topological relief. Ion milling is relatively slow compared to liftoff processes, although it leaves a very smooth surface and is not subject to edge burring and adhesion-strength limitations. Sputtering is relatively rapid and can be used to etch fine features. One of the concerns in ion milling or sputtering is that in

Figure 10-54. A SEM micrograph showing a recessed gate opening. The magnification marker is I p m . The trench dimension is 0.356 p m at the bottom. printed by G-line photolithography. This dimension represents the limit to G-line lithography with single pass step-and-repeat exposure systems, and standard photoresists. (Micrograph courtesy of P. A. Grasso, S . E. Lengel. A . F. Williams, Lucent Technologies. Inc.. Reading, PA.)

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Figure 10-55. A schematic view of a method for creating fine features with process-limited photolithography. a) A layer of photoresist is deposited and exposed at a controllable dimension. A second layer of photoresist is deposited on the wafer and exposed with a specific offset to the original pattern. Clearing the exposed photoresist leaves a bilayer offset feature as shown in b). Subsequent metal deposition, preferably at a substantial angle. produces a fine metal feature of dimension much less than the photolithography limit, if desired.

the process of etching, residual ion damage and redeposition of sputtered species may occur, which can lead to surface-state-induced electrical effects or leakage paths in devices. In most process tools, only a single wafer or a few wafers can be etched at a time, leading to a limited throughput in the apparatus. The topic of ion etching was discussed in Sec. 10.5 in a more general context. The criteria and utilization presented therein are applicable to metallization patterning.

10.11.2 Liftoff Processes Liftoff procedures are implemented when metallizations are incompatible with chemical etchants, when rapid, high throughput processes are desired, or when ion-based patterning is undesirable. The as-deposited metal layers are required to be ductile and adherent in order to permit the selective separation of the unwanted metal from the wafer surface. In addition, the control of step, edge, and side-wall coverage is critical for

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providing a “weak link” to permit separation of the metal film. Metals that are deposited by evaporation or plating meet these criteria and are generally quite well suited for liftoff processes. These patterning methods are particularly effective for gold or gold-based materials. as deposited gold layers are nearly “dead soft”. Sputtered metal layers, and particularly refractory metals, are more difficult to liftoff successfully due to high adhesion to all surfaces, relatively good conformal coverage of steps and edges, and their tendency to be harder in the as-deposited state. Liftoff processes involve the creation of high aspect ratio trenches or undercut pattern features in the patterned photoresist or

dielectric layer(s), coupled with a “directional” type of metal deposition process. The metals are deposited over this patterned sacrificial film. Then the metal layer and sacrifical film is stripped off by mechanical, chemical, or chemo-mechanical means, so “lifting” the unwanted metal from the surface. To successfully carry out the liftoff process, complete, full thickness metal coverage at the edges of the photoresist or dielectric layers is highly undesirable. Electron beam or resistance-heated evaporation methods are best suited to the deposition of metal layers due to the highly directional nature of the evaporation process, resulting in “poor” edge/sidewall or corner coverage, as illustrated by Figure 10-56.

Figure 10.56. A schematic illustration of an optimal liftoff metal coverage. a) The key to a clean metal liftoff lies in the thin or nonexistent coverage of the side walls of the gate or metal trench feature. b) The thin lines of metal part readily form the main metal line when the photoresist of patterning material is removed from the wafer. leaving the desired metal line pattern.

10.1 1 Metallization and Liftoff Processes

Other methods of metallization, such as sputtering or plating, tend to provide a more uniform surface coverage, and thus are less well suited to liftoff techniques, unless the sacrificial layer is shaped to create a thin parting line in the metal. The thickness of the dielectric or photoresist, and the edge definition, play a critical role in the perfection of the liftoff procedure by influencing the thickness of the metal coverage during deposition. The metal at step edges and corners is typically much thinner than the bulk regions of the metal film. Therefore the edges are much weaker than the bulk and easily parted at these sites. Ideally, there is no metal film continuity and the undesired material will liftoff without residue. The thinning or lack of coverage at the feature edges is also important for the prevention of burring and the elimination of interlayer short circuits. However, great care must be exercised in lifting off the metal, as many desired metal traces have steps and edges in their topology. Several methods of “lifting” the undesired metal are available. All of the methods rely on a solvent (water or organic chemicals) or an etchant to dissolve the sacrificial layer. Typical photoresists are quite soluble in acetone or other organic solvents. Sacrificial dielectrics films may be dissolved with HF or other suitable acids or bases. This latter approach has been used for large area liftoff of epitaxial films (Fan, 1990; Yablonovich et al., 1990) by utilizing sacrificial AlAs or AlGaAs layers. Subsequently, the unwanted metal and the sacrificial layer are floated or “scrubbed” off the surface of the semiconductor wafer with agitation, a high pressure fluid spray, or other mechanical means. As uncontrolled physical/mechanical scrubbing can be quite damaging to the remaining metal, most processes use deionized water or other solvents at moderate pressures and flows to remove

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the metal and residual photoresist or dielectric materials. Metal recovery systems are used to reclaim precious metal wastes in these processes. Static electricity can be an issue with solvents or other chemistries flowing over a highly resistive substrate, leading to circuit damage. Surfactants or other materials may be added to the fluid streams to reduce static charge build-up. The adhesion of the metal to the desired surfaces must be strong in the as-deposited state or the metal layer may be removed from undesired areas during the liftoff. At the same time, poor adhesion of the metal to the sacrificial dielectric or photoresist layer is highly desirable. In addition, relatively thin metal layers must be used to prevent tearing of the metal or lifting off of the desired layer. Edge lifting and undercutting may occur if the adhesion to the desired contact region is insufficient. Burring can be a problem with liftoff processes owing to the ductility of the metals in the as-deposited state. The liftoff processes may tear the metal at the parting lines if there is incomplete separation of the deposited metal film. This result could be due to excessive metal coverage or thickness variations, grain structures anomalies, adhesion variations, particles, etc. Small burrs will be left along the edge of the metal line in this case. This problem is illustrated in Fig. 10-57. The burrs can protrude through the next level of dielectric causing short circuits between the metal layers. Careful preparation and wellcontrolled deposition conditions are required to ensure clean removal of the unwanted metal. Figure 10-58 illustrates a “clean” edge definition on a multi-fingered air bridge structure created with liftoff methods. The air bridge was constructed by a sacrificial layer post-and-runner process. At present there is no solution for complete amelioration of the problems of edge lifting and minor tearing/burring of the

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Figure 10-57. An illustration of a burr formed on a metal feature due to improper trench edge definition or excessive metal layer thickness. In this case the burr may extend along the metal line or be an isolated fine point. This may cause interlayer shorting due IO poor dielectric coverage in subsequent process steps.

metal layer. Good process methodology and process control can produce excellent. reproducible results with liftoff processes. A minor amount of yield reduction may occur from open circuits, electrical contact resistance variations. burring, and short circuits. While these drawbacks can be quite serious, many materials cannot be successfully etched or ion milled, thus liftoff processes are the only viable alternative. It should be noted that commercial liftoff-based processes are quite robust, and presently operate with high yields.

10.12 Backside Processing and Die Separation Backside processing is carried out when the wafer must be thinned or if a back-surface metallization layer is needed. It is highly desirable to thin a compound semiconductor wafer to improve device performance from both the thermal and electrical standpoint. For example, thin wafers and the use of backsurface ground planes are critical to the R F performance of microwave devices. The spacing of the top surface conductors to the ground plane (back surface), i.e., the wafer thickness, creates a controlled

59 1

10.12 Backside Processing a n d Die Separation

Figure 10-58. Secondary electron micrographs of air bridge structures formed by liftoff methods. The marker is 10 p m in both images; the span dimension is approximately 25 pm. In a) a “sea” of approximately 125 air bridges over interconnect metal lines is presented. I n b) a high magnification image of a few air bridges is presented. Note the moderate take-off angle of the bridge, leading to high strength and high reliability, and the elimination of electrical shorting. Bridge structures such as these readily withstand backside processing. (The micrographs are courtesy of P. A. Grasso, S . E. Lengle, A. F. Williams, Lucent Technologies, Inc., Reading, PA.)

impedance condition for transmission lines, which is required for stable microwave performance. It may be necessary to link the top surface ground lines to the back surface ground plane, Le., through-wafer vias are required. Source or emitter vias (for FET or HBT devices, respectively) provide low im-

pedance connections to the ground (Furukawa et al., 1998). In addition, thinner substrates and through-wafer vias permit vastly improved heat extraction from the devices. As the thermal conductivity of GaAs and InP is significantly less than that of silicon, this is a critical issue, as shown in Table 10-9. Thus by thinning the wafer, greater power may be dissipated per unit area for a given temperature rise, permitting compact, high-power devices without compromising performance. If no backside processing is required, the wafer would pass to die separation, as described in Sec. 10.12.2. One of the key issues in the backside process flow is attention to detail; the importance of this point cannot be over-emphasized. Since the front side process is now completed, it becomes an extremely expensive proposition to damage the active circuitry while thinning and metallizing the back surface. There is a great amount of handling in the backside process which can subject the wafer, in a relatively weak condition, to significant abuse. Breakage, contamination, and physical damage (e.g., scratches and chips) may occur at each of the mounting, grinding, polishing, cleaning, etching, metallization, and demounting steps, which encompass the backside process sequence (Fig. 10-59). In comparison to silicon fabrication, compound semiconductor materials are much “softer” (the hardness of GaAs is approximately one-tenth that of silicon), and have facile cleavage, which emphasizes the importance of careful handling to avoid Table 10-9. Thermal conductivity of selected semiconductors“. Silicon ISh

Gallium arsenide

Indium phosphide

0.48‘

0.56d

Values in W cm-’ K-’ at 300 K; Sze (1981, App. H ) ; ‘ E M I S ( I 9 9 0 , S e c . 1 . 8 ) ; d E M l S ( 1 9 9 1 , S e c .1.8).

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1 0 Compound Semiconductor Device Processing

Thickness I

1

-

I

Mount to Substrate

+

Grind (oneor two-step)

1

PhotdiTraphy Through-wafer IR Alignment

14

I

1 Scribe-and-Cleave

i Cleaning

inspection

t

1

Inspection

Polish (chemical or mechanical) Substrate

Figure 10-59. An example of process flow options for creating back surface metallizations, through-wafer vias, die separation, and the selection of viable devices

chips and breakage. Finished die costs are highly dependent on the success of this final process step. Very little information on the complete backside processing sequence has been made available in the public domain, as it is considered highly proprietary. The process flow description herein is drawn from the authors’ experience and discussions with other experts, and represents a “hybrid” view of the backside issues.

10.12.1 Backside Processing The process involves a multitude of steps to complete the wafer process flow as shown in Fig. 10-59. The principal tasks to be accomplished are: mounting, grinding, cleaning, polishing, and if required, masking, via etching and finally, metallization. Following these processes the wafers will be electrically tested and optically inspected, the useable die separated by various means, and the die passed to assembly and packaging.

Mounting involves fixing the wafer topface-down onto a supporting substrate to facilitate the grinding or lapping processes and subsequent handling in a thinned condition. This mount must be physically strong, stiff, extremely flat, and not damaged by the thinning processes. Sapphire or quartz mounts, ground and polished to optical flatness, are suitable for this task. Silicon wafers or other materials may be used if back-to-front alignment is not required. The wafers may be affixed to the mount by an IR-transparent adhesive (e.g., paraffin, beeswax, or other readily soluble, noncontaminating materials of low melting point). Adhesive tape products, such as NITTO tape are also suitable for mounting. It is critical to ensure that the mount is free of particulates and that the wafer is parallel to the mount surface. The wafer must not be subjected to excessive stress or pressure during the mounting procedure, and great care must be taken to prevent damage to the front side structures. This latter point is particularly

10.12 Backside Processing and Die Separation

important when air bridge technology is employed. Wafer thinning is a slow, labor-intensive process even with automated apparatus. The initial grinding or lapping of the back surface may remove up to - 95% of the original thickness, with an accuracy of a few micrometers (-0.1 mil). The wafer may be ground to a thickness slightly greater than the final target value, and then chemically polished or etched as desired. The etching step removes grinding damage and achieves the final thickness and surface quality suitable for via etching and/or metallization. High precision grinding apparatus is required for this task, with well controlled stock removal rates to prevent damage to the wafer and to ensure accurate thickness control. Fine diamond grit (1 - 10 pm nominal) grinding wheels can produce a good surface flatness at economical grinding rates without generating excessive damage to the substrate. Commercial vertical spindle/horizontal pass grinding units can achieve very good control and reproducibility of the thickness and surface quality (Lapinsky, 1991). Following the grinding procedures, the wafer and mount are carefully cleaned to remove grinding residues. This step involves a detailed inspection of the wafer to identify any surface damage, fractures, or chipping of the edge. The wafer may then be chemo-mechanically polished to the final thickness, removing the gross damage from the grinding and preparing the surface for metallization or masking and via definition. The final polish chemistry is typically based on NaOCl or NH,OH etching solutions as they are anisotropic and produce a superior surface finish (Stirland and Straughan, 1976). For InP substrates, mixtures of bromine and methyl alcohol are typically employed (Chin and Barlow, 1988). Chemomechanical etching tends to slightly round

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the wafer profile as polishing occurs. Therefore care must be taken to maintain the flatness and parallelism of the wafer surface. In addition, the polishing systems must be well-characterized to achieve an accurate final thickness as the material removal rates vary strongly with polishing pressure and solution pH. In a well-controlled process, variation can be maintained within 2.5 pm (0.1 mil) to 5 pm (0.2 mil) for a final thickness ranging from 100-250 pm (Lapinsky, 1991). Wafers for certain microwave or high power applications are thinned to as little as 25 pm (1 mil) (Niehaus et al., 1982). At this thickness the wafer will readily conform to corrugations in the NITTO mounting tape. The mounted wafer is now ready for backside metallization. As shown in Fig. 10-59, there are two paths: photoresist deposition and exposure of the via pattern to create the front-to-back contacts, or, if vias are not required, the mounted wafer is cleaned and passed to metallization. Typically, a 4 mil (100 pm) or thinner wafer will not be demounted as cleavage is quite facile in compound semiconductor materials; 250 pm (10 mil) thick wafers can be carefully handled without a carrier. Thorough cleaning is again critical to the success of the process, as adhesion of the photoresist and the initiation of etching are strongly influenced by the surface condition. The photoresist masking layer for backside processing must be significantly thicker that required for the front surface processing. Owing to the very extended etching times needed for opening vias through hundreds of micrometers of substrate, the masking layer must be much more robust, although the precision of the critical dimensions is more relaxed than for front side processes. Multi-layer masking techniques may be used to minimize via “blowout” (expansion significantly beyond the

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patterned dimensions) and damage to the substrate (edge lifting, pinhole leakage, etc.). For example, additional layers of photoresist, or metals such as Ni or Cr, could be applied on top of the base photoresist layer. In this case, the photoresist layer may be only a few hundred nanometers thick, and the metal layer of the order of 50 nm thick. Exposing a through-wafer via pattern requires a “front-to-back” infrared aligner system. In this apparatus the front surface metallization pattern is imaged through the carrier and wafer using sub-bandgap infrared light The alignment of the via mask pattern is referenced to the target contact pads on the front surface. Exposure is carried out as with normal photoresist techniques (see Chap. 4 of this Volume) with the exception that very extended or multiple exposure times may be required. In multi-layer processes several passes through this sequence are necessary. The through-wafer vias are etched in a manner described in Chap. 6 of this Volume and Sec. 10.5. Reactive ion etching is becoming the preferred method, as the morphology and aspect ratio of the via may be controlled through the etching conditions (pressure and gas compositions). With wet chemical methods, the vias tend to expand laterally as vertical etching proceeds even with highly anisotropic etchants, although very smooth via walls result with wet chemistry methods. It is difficult to control the final “over-etching” of the target areas and minimize the damage to the front surface if etchants leach around the metal contact pads. Also, the aspect ratio of the via and the side-wall structure is critical to the metallization process: severely undercut edges, re-entrant corners, or curved side walls (Fig. 10-60a), or vertical side walls and sharp corners (Fig. 10-60b), will prevent or complicate successful metallization coverage, leading to unsatisfactory continuity, high resistivity, and poor reliability.

Metallization steps are carried out after careful cleaning of the etched wafer. Residues are often left on the surface due to polymerization or overheating from the ion plasma during RIE, or residual by-products from the chemical etching procedures. It is crucial that any foreign materials are removed as the metallization quality may be affected or inhibited entirely. There are several approaches to backside metallization: 1) deposit a thin layer of metal(s), form a plug in the via hole, and then deposit a thick, full surface metal layer over the entire wafer: 2) deposit a thin metal layer for contacting, and then use a “solder” flow process to fill the vias and provide the full surface metal cover age. Many variations of these general approaches exist. Metallization may be carried out in two or three steps: the first to provide an intimate conformal seed metal layer to ensure ohmic contact to the exposed (back surface) metal pads on the front surface (Fig. 10-61), then to “plug” or “fill” the vias, and the third step to completely contact the surface and the vias creating the ground plane. The via may or may not be completely filled. The final process entails the addition of a planarization metal deposition or the application of a thick back surface metallization. The first metallization may be an adhesion promoting layer (e.g., titanium), or a layer of gold or gold alloy. The plug process should appropriately fill a via and be relatively planar. When the final metal layer is formed it must be adherent, uniform in thickness, and planar. Examples of the plug process are shown in Figs. 10-62 and 10-63. In Fig. 10-62 an SEM micrograph shows a view of a via hole. The morphology of the wall of the via is apparent. A series of via plugs with top surface contact pads is shown after etching away the substrate in Fig. 10-63. The surface morphology of the via perimeter is evident on the gold plugs. It is clear that the


595

Figure 10-60. Illustrations of undesirable via morphologies. In Fig. 10-60a, the effects of undercutting or re-entrant corners are evident. Metal coverage and continuity are compromised by these conditions. Figure 10-60b highlights the additional problems of sharp corners and vertical side walls. Here the filling of the via may be compromised by the vertical wall, and the sharp corners enhance stress localization.

Figure 10-61. Schematic illustration of a well-defined through-wafer via. The corners of the via are rounded to enhance continuity and minimize stresses. The seed plating is continuous and the filling metal shows only limited underfilling. A planarization metal layer is shown (optional). The final back surface metal layer provides the continuous back-plane conductor.

596


Figure 10-62. As SEM micrograph of a via hole after etching. The diameter of the via is approximately 100 pm. Note the gentle curvature of the top region of the via. (Figure courtesy of Dr. A . Colquhoun. Daimler-Benz Research Center, Ulrn, Germany.)

acteristics. Solder-fill approaches can provide a via fill at relatively low cost. The plug metallization must be compatible with plated or evaporated gold or gold alloys typically used for the ground plane formation, and subsequent die attachment processes. The back surface metal plate-up is normally many micrometers thick and uniform in coverage to ensure uniform electrical and thermal contact, low resistance, and to withstand the alloying and reaction that occurs during mounting of the finished die to the package. For this reason, plating methods (electro or electro-less) are optimal, although evaporated or sputtered metals may be used. The key issue during the metal deposition process is to keep the wafer temperature below the softening point of the adhesive material (the wafer is still mounted on a carrier). Plating may be carried out at temperatures below 100"C, which is compatible with most adhesives, whereas evaporation may expose the wafer to very high surface temperatures, and sputtering methods can raise the temperature to well above 200°C. To circumvent the heating problem, evaporation or sputtering may be carried out in steps, although there are penalties in system throughput, the metal film qualities, and the cost associated with this type of process sequence. Active cooling may be necessary to help control the temperature rise. As in front surface metallizations, an adhesion promoter such as nickel or titanium may be used to improve the adherence of the back surface metal. When using electroplating processes it is difficult to produce a uniformly thick metal layer owing to the high resistivity of semi-insulating substrates (GaAs or InP) and the finite electrical contacts. A metal seed layer is required to initiate the plating process. Current flow necessary to induce plating is inhibited in the substrate, and current spreads through the

-

Figure 10-63. An SEM micrograph of a series of through-wafer vias after removing the GaAs substrate. The top surface contact pads form a cap on the filled via metal. Via diameters are slightly larger than 100 pm. These vias are used to form a ground plane for 2 20 GHz device operation. (Figure courtesy of Dr. A . Colquhoun. Daimler-Benz Research Center, Ulm, Germany.)

-

shape of the via hole is critical for achieving continuity between the back plane and the front surface contacts. Plugs may be formed by selected area filling with gold, gold-based alloys, or other metal solders, or bv dating processes with good filling char-


seed layer from the electrical contacts. The metal build-up generally occurs more rapidly in areas close to the contact(s), especially if high plating currents are used. The use of highly conductive, adhesion-promoting layers and substantial seed metal thickness can greatly reduce this problem by increasing the in-plane conductivity. There is additional concern for interactions of gold with GaAs and InP with respect to long-term stability under severe operating conditions. Barrier metals such as nickel, platinum, or palladium may be incorporated in the back surface metal layers to reduce the interaction of gold or solder metals with the GaAs substrate (Parsey et al., 1996). However, it has been shown that gold-based metallurgy is very stable under high-stress reliability testing (Irvin, 1992). References such as Massalski (1986) should be consulted for further understanding of the relevant phase diagrams. At this point the wafer may be demounted from the supporting plate. The wafer is now quite fragile and easily damaged by mishandling. Several cleaning steps are required before the wafer may be passed to testing and evaluation. The adhesive materials and any undesired materials that were placed on the front surface as a protective coating must be removed. As before, no residues may be left on any surfaces as they will impede electrical contact to the back surface as well as the bonding pads on the front surface. The wafer may be transferred to a supporting carrier such as a NITTO tape handling system (Nitto). Here the wafer is gently pressed onto a polymer film which is supported by a tensioning ring carrier. The film and ring are capable of supporting the wafer mechanically during testing, die separation, and “pick and place”. As the polymeric film is plastic, separating the die is accommodated by expanding the film after the “streets and alleys” are cut or formed.

597

10.12.2 Die Separation The wafer must now be electrically tested to identify the good die. After testing and marking (ink dot or X - Y die location map) the die must be separated for mounting in packages. Several methods exist for separating the die: scribe-and-cleave (diamond scribe or laser ablation using varied mechanical stresses to cleave the wafer along the scribe lines) and sawing (typically with diamond blades). The first approach is best suited to wafers with thin or no backside metallization, although if the metal layer is less than a few micrometers thick this tends not to be an insurmountable problem. The latter method is required for very thick backside metallizations because of the malleable nature of gold. With diamond or laser scribing, a groove is scored or ablated, respectively, in the “streets and alleys” between adjacent die. The groove acts to focus the mechanical stresses when the wafer is flexed on a suitable pad by a roller-type device or impacted by a cleaving bar. The use of a roller-type method is not well suited for devices using air bridge metallizations unless great care is exercise in the scribing and the mechanical handling: the air bridges are easily crushed. Also, detritus from the diamond scribe or laser ablation processes may be lodged around the air bridges leading to short circuits or other damage, unless the surface is encapsulated. Recently, an apparatus for “scribe-andcleave” processes has been introduced to compound semiconductor technology (Dynatex). This instrument uses an automated diamond scribe system coupled to a precision impact bar which rides below the backside of the wafer is indexed in two dimensions while the impact bar is snapped up to the back surface at each scribe line The sharp impact breaks or cleaves the wafer

598


without excessive force, and has been found to be suitable for die separation when air bridge metallizations are used, although the cautions of contamination apply due to use of the diamond scribe. It is important to note that these processes perform best when photolithography is carried out aligned to the preferred (1 10) cleavage directions in the compound semiconductors. Attempting to die separate along other crystal directions generally leads to failure and low yields. The second method of separation is diamond sawing (AT, Disco). In this approach, the wafer is placed on a precision indexing table and then moved beneath a rotating diamond wheel to cut a groove in the “streets” on the wafer surface. The blade width is typically -10 pm (0.0004 in) to - 100 p m (0.004 in), creating a cut roughly 25% wider than the actual blade dimension. Diamond sawing is the “least clean” method to separate the die. As noted above, the wafers should be encapsulated to protect the surfaces from damage and contamination. However, this may be i n conflict with the testing and evaluation sequence. Use of the diamond blade, the coolant/lubricant fluid, and the generation of chips and other rubbish creates significant contamination of the wafer surface and necessitates careful cleaning procedures to remove the residual materials. After the “x” and “y” groove pattern is cut, the wafer may be mechanically stressed to cleave the substrate along the grooves, as noted above. The same constraints apply here to the use of the mechanical flexing approach for cleaving the wafer. In some cases the wafer may be sawn completely through the back surface metal. Great precision is demanded in the cutting process to avoid excessive damage to the substrate carrier film layer. Vibration imparted into the wafer during sawing is of substantial detriment to GaAs and InP materials, as they are quite brittle. Edge dam-

age, fractures, and undesired cleavage can readily occur during the sawing operation. One step remains before the die may be selected: physically separating the die. In the case of NITTO tape or similar materials, this step is effected by stretching the polymer film. The spacing between the separated die is expanded to allow mechanical chip handling devices to remove the chip from the film, or to permit human handling, without damage to adjacent die. Exposure to chemicals or UV light may be used to reduce adhesion between the wafer and the carrier to facilitate the removal of the die from the film. “Pick-and-place” is a process of selecting the good die and locating them in a chip carrier or package cavity. This is done either manually or with automated systems. Vacuum pickups are employed to avoid the damage and yield losses associated with tweezers or mechanical clamping devices. In the case of expanded film carriers either method may be used. Solid wafer carriers (e.g., sapphire or quartz) do not lend themselves to effective die separation, and therefore require manual chip selection in the latter case, further cleaning processes may be necessary to remove residues. The identity of the die and the location within the wafer are known from the testing sequence and may be maintained prior to assembly. Following completion of the pick- and-place operation, the die are subjected to additional visual inspection with the survivors passing to assembly and test.

10.13 References Abernathy, C. R., Pearton, S . J., Caruso, R., Ren, F., Kovalchick, J . (198Y), Appl. Phys. Lett., 55, 1750. Abrokwah, J., Huang, J. H., Ooms, W., Shurboff, C., Hallmark, J., Lucero, L. (1993), in: 15th Guns IC Symp., Tech. Diye.rr. New York: IEEE; pp. 127130.

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Wada, M., Kawasaki, H., Hida, Y., Okubora, A,, Kasahara, J. (19891, in: l l t h GaAs IC Symp., Tech. Digest. New York: IEEE, pp. 109-1 12. Wada, S . , Yamazaki, J., Ishikawa, M., Maeda, T. (1997), in: 19th GaAs ICSymp., Tech. Digest. New York: IEEE, pp. 70-73. Waldrop, J . R., Kowalczyk, S. P., Grant, R. W. (1982), J. Vac. Sci. Technol. 21, 607. Waldrop, J. R. (1984), J. Vac. Sci. Technol. B2, 445. Wang, J. G., Hur, K., Studebaker, L. G., Keppeler, B. C., Quach, A. T. (l997), in: 19th GaAs ICSymp., Tech. Digest., New York: IEEE, pp, 74-77. Watanabe, K., Hashiba, M., Hirohata, Y., Nishino, M., Yamashino, T. (1979) Thin Solid Films 56, 63. Weiss, B., Kohn, E., Bayraktaroglu, B., Hartnagel, H. L. (19771, in: Inst. of Phys. Cant Ser. 33, London: Institute of Physics; pp. 168- 176. Wey, H. Y. (1976), Phys. Rev. B 13, 3495. Williams, R. H. ( 1 982), Contemp. Phys. 23, 329. Williams, R. E. (1990), Gallium Arsenide Processin8 Techniques, 2nd. ed., Norwood, MA: Artech House. Wilson, M. R., Welch, B. M., Imboden, C., Krongard, B. S., Shah, N., Shen, Y., Venkataraman, R. ( 1 989), in: l l t h GaAJ IC Symp., Tech. Digest. New York: IEEE, pp. 23 1-234. Wilson, M. R., Chasson, D. E., Krongard, B. S., Rosenberry, R. w . , Shah, N. A,, Welch, B. M. (1993), in: 15th CaAs IC Symp., Tech. Digest. New York: IEEE, pp. 189-192. Woodall, J. M.,Rupprecht, H.,Chicotka,R. J., Wicks, G. (1981), Appl. Phys. Lett. 38, 639. Wronski, C . R. (1969), RCA Rev. 30, 314. Yablonovich, E., Hwang, D. M., Gmitter, T. J., Florez, L. T., Harbison, J. P. (1990), Appl. Phys. Lett. 56, 2419. Yamada, F. M., Oki, A. K., Streit, D. C., Saito, Y., Coulson, A. R., Atwood, W. C., Rezek, E. A. (1994), in: 16th GaAs IC Symp., Tech. Digest. New York: IEEE, pp. 27 1- 274. Yamasaki, K., Asai, K., Kurumada, K. (1982), IEEE Trans. Electron Devices 29, 1772. Yin, X., Pollak, F., Pawlowicz, L. M., O’Neill, T., Hafizi, M. ( l990), Appl. Phys. Lett. 56, 1278. Yu, M., Matloubian, M., Petre, P., Hamilton, L., Bowen, R., Lui, M., Sun, C., Ngo, C., Janke, P., Baker, D., Robertson, R. (1998), in: 20th GaAs IC Symp., Tech. Digest. New York: IEEE, pp. 37-40. Yuan, Y. R., Eda, K. Vawter, G. A,, Merz, J. L. (1 983), J . Appl. Phys. 54, 6044. Yuen,C., Nishimoto, C., Glenn, M., Pao, Y. C., Bandy, S., Zdasiuk, G. (1988), in: 10th GaAs IC Symp., Tech. Digest. New York: IEEE, pp. 105- 108.

605

Zeng, X . F., Chung, D. D. L. ( I982), Thin Solid Films 93, 207. Ziegler, J. F., Biersack, J. P. and Littmark, U. ( 1 9 8 3 , The Stopping and Range of Ions in Solids, New York: Pergamon. Zuleeg, R., Notthoff, J . K., Troeger, G. L. ( 1 9 8 4 ~ IEEE Electron Device Lett. 5, 2 1, Zuleeg, R., Notthoff, J. K., Troeger, G . L. ( I 990). Gullium Arsenide Technology, Vol. 2 , C a m e l : IN: SAMS, Chap. 3, pp. 95- 138.

General Reading List Ali, F., Gupta, A. (Eds.) (1991), HEMTs und HBTs: Devices, Fabrication, and Circuits. Norwood, MA: Artech House. Daembkes, H. (Ed.) ( 1 99 I ) , Modulation-Doped FieldEffect Transistors, Principles/Design/and Technology. New York: IEEE. DiLorenzo, J. V. (Editor-in-Chief), Khandelwal, D. D. (Associate Editor) (1982), GaAs FET Principles and Technology Dedham, MA: Artech House. EMIS Datareviews Series No. 2 (1990). Properties of Gallium Arsenide, 2nd ed. London: I N S P E W E E . EMIS Datareviews Series No. 6 ( 1 99 1 ), Properties of Indium Phosphide, 1 st ed. London: INSPEC/IEE. Howes, M. J., Morgan, D. V. (Eds.) (1981), Reliubility and Degradation. Chicester: Wiley. Howes, M. J., Morgan, D. V. (Eds.) (1985), Gallium Arsenide Materials, Devices, and Circuits. New York: Wiley-Interscience. Milnes, A. ( 1 9 7 3 ~Deep Levels in Semiconductors. New York: Wiley. Schwartz, B. (Ed.) (1969), Ohmic Contacts to Semiconductors. New York: The Electrochemical Society. Shewmon, P. G . (1963), Diffusion in So1id.r. New York: McGraw-Hill. Shur, M. (1987), GuAs Devices and Circuits. New York: Plenum. Sze, S. M. (1981), Physics of Semiconductors. New York: Wiley-Interscience. Tuck, B. (1988), Atomic Diffusion in 111- VSemiconductors. Bristol and London: Adam Hilger/Institute of Physics. Williams, R. E. (1990). Gallium Arsenide Processing Techniques, 2nd. ed Norwood, MA: Artech House.

11 Integrated Circuit Packaging

.

Daniel I Amey E . I . DuPont de Nemours Inc., Dupont Electronic Materials. Wilmington. DE. U.S.A.

List of Symbols and Abbreviations ........................................ 11.1 Introduction ..................................................... 11.2 Package Functions ................................................ 11.3 Integrated Circuit Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Die Attachment .................................................. 11.5 Microinterconnect Methods ........................................ 11.6 Wire Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.7 Tape Automated Bonding (TAB) .................................... Flip Chip or Solder Bump .......................................... 11.8 Package Sealing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.9 11.10 Rent’s Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.11 Thermal Management ............................................. 11.11.1 Thermal Resistance ............................................... 11.11.2 Cavity-Up/Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.12 Package Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.13 JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.13.1 Dual In-Line Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.13.2 Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.13.3 Chip Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.13.4 Small Outline Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.13.5 Grid Array Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.13.6 Hybrid Circuit Packages .......................................... 1 1.14 Package Attachment .............................................. 11.15 Electrical Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.16 Other Package Selection Considerations .............................. 11.17 Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.18 Multichip Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.18.1 Introduction ..................................................... 11.18.2 Multichip Packaging Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.19 Change and Repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.20 Change Bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.21 Repair Links ..................................................... 11.22 The Future ...................................................... 11.23 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

608 610 610 612 614 614 615 616 618 619 620 621 621 624 624 624 626 626 627 628 628 630 631 633 635 636 637 637 637 640 641 642 644 645

608


List of Symbols and Abbreviations 9

P P TI T2 E, QC,

QD

0, 0,) QJ2

QJ3 QJ.4

QJC

0, ATAB BGA

cc

c4 CERDIP CMOS CQFP DIP ECL EIA EIAJ FQFP FRU IC IEC IEEE

I10 ISHM JEDEC LCC LFPM LGA LIF LSI MCM MCP

number of logic gates number of pins dissipated power average die junction temperature ambient air temperature relative dielectric constant case-to-air thermal resistance thermal resistance of the die thermal resistance of the heat sink material thermal resistance of the die-to-package interface thermal resistance of the package-to-heat-sink surface thermal resistance of the heat-sink-to-air (film resistance) junction-to-air thermal resistance junction-to-case (exterior) thermal resistance thermal resistance of the package material TAB ball grid array ball grid array chip carrier controlled collapse chip connection ceramic dual in-line package complementary metal-oxide semiconductor ceramic quad flatpack dual in-line package emitter coupled logic Electronics Industries Associa tion Electronics Industry Association of Japan fine pitch quad flat pack field replaceable unit integrated circuit International Electrotechnical Commission Institute of Electrical and Electronics Engineers input - output International Society of Hybrid Microelectronics Joint Electron Devices Engineering Council leadless chip carrier linear feet per minute land or leadless grid array low insertion force large scale integration multichip module multichip packaging


Iv SI P-3GA Pc 3A PXC P‘bVB Q FP QUIP SI MM s1P S’vlTA S”k4TPGA Sc 1 SC >J sc >P S ( IT S‘>OP T. I B Ti :E TCM Tc )FP T‘jOP v LSI Z F Z P

medium scale integration plastic ball grid array pin grid array plastic leadless chip carrier printed wiring board quad flatpack quad in-line package single in-line memory module single in-line package Surface Mount Technology Association surface mount pin grid array small outline SOP with leads in a J configuration small outline package small outline transistor shrink small outline package tape automated bonding thermal coefficient of expansion thermal conduction module thin quad flatpack thin shrink small outline package very large scale integration zero insertion force zigzag in-line package

609

61 0


11.1 Introduction A package as defined in JEDEC Standard No. 99 is “An enclosure for one or more semiconductor chips that allows electrical connection and provides mechanical and environmental protection”. A wide variety of package types exist having different shapes, materials, styles, terminal forms, terminal pitch and terminal count. Terminal count is a general, generic term referring to pins, leads, pads, solder bumps, etc., and is often used interchangeably with the term which describes a specific configuration. Thousands of package variations exist, each meeting specific application requirements. Designers selecting an integrated circuit (IC) are faced with an “alphabet soup” of package types - BGA, PGA, LGA, LCC, TSOP, TSSOP, QFP, MQP, etc., etc., etc., - from which to choose; but it has not always been this way. In the 1960s the choices were few, with the dual in-line package (DIP) the most popular type. Since then, each decade has seen a doubling of the number of basic package types available to the designer, thus making the choice of a package type more difficult and critical to the success of the overall packaging approach. Packaging and interconnection has limited, and will continue to limit electronic system performance. It is rare for a package type to disappear from the scene. This is illustrated in Table 11-1. The DIP quickly replaced the TO5 style package for ICs; but after 30+ years, the DIP still remains in widespread use in electronics packaging. Package types and variations evolve without replacing existing types, resulting in the proliferation we have today. Some of this is due to the early identification of the potential or need for a new type, the long gestation period for a package to become widely applied due to the establishment of the infra-

structure to apply the package (asssembly equipment, test tools, etc.), and investment in both the factory and the field. But, due to rapid change, the required investment is not just the investment in the new approach but also that of the prior packaging approach. This investment drag on technology insertion is one of the major reasons the D I P has enjoyed such a long life. Packages have changed and will continue to change to develop denser, thinner, lighter single chip packages and proliferation of types will continue. As has long been the case, no one package type can suit the needs of the many and varied applications in the electronics industry.

11.2 Package Functions Semiconductor circuits continue to place new demands on circuit packages and interconnections for eficient circuit packaging. Package trends are toward increasingly higher terminal counts, higher thermal dissipation, higher packaging densities (more interconnections per square inch) and multichip packaging to improve electronic system performance with increased functionality and capabilities. In the 1950s and early 1960s discrete semiconductor devices and electronic components such as transistors, resistors, and capacitors with axial and radial lead terminals were predominant. As semiconductor technology improved, and more and more components could be put on a silicon chip, the number of pins on the TO-type semiconductor packages were not sufficient. ICs used circular TO5 packages with 10 and 12 leads in a circular pattern, the pin limit for the package and the printed circuit interconnect technology for that time (about 1963). This resulted in the need for, and introduction of, the D I P and the D I P has

61 1

11.2 Package Functions

Table 11-1. Integrated circuit package types. -

P ickage type

-

Dual in-line package Fidt pack C iip Carrier LLladless chip carrier Pldstic leaded chip carrier Grid array Pin grid array L(,adless (land) grid array Sriiall outline or small outline IC Sryiall outline J lead Ti,pe automated bonding

In -line packages Si,igle in-line package Zig-zag in-line package Q .lad in-line package Single in-line memory module

Q.iad flat pack Molded ring carrier Fine pitch quad flat pack Tliin quad flat pack SI-rink small outline package Tliin small outline package Tliin shrink small outline package

Acronym

1960s

1970s

1980s

19905

DIP FP

0 0

0 0

0 0

0

LCC PLCC

0

0 0

0 0

0 0

PGA LGA

0

0

0 0

0 0

SO or SOIC SOJ

0

0 0

0 0

TAB

0

0

0

0 0 0

0 0 0 0

0 0 0 0

0

0

0

0

0

cc

SIP ZIP QUIP SIMM (SIP)

0

QFP TAPEPAK * FQFP TQFP SSOP TSOP TSSOP

0 0 0 0 0

BGA PBGA ATAB SMTPGA

0 0 0 0 0

G,-idarray Bi.11 grid array

P1,istic ball grid array TtiB ball grid array SL.rface mount pin grid array Metric TAB M ultichip module MCM pin grid array MCM ceramic quad flat pack Shrink DIP Memory cards L; rge IjO SIMMs

TAB MCM MCM PGA MCM CQFP

SIMM (SIP)

served as the workhorse package for many years and will continue to be a primary semiconductor package type for many, many years to come. However, in the mid-I970s, as the semiconductor technology advanced into

0

0 0

0

0

0 0 0

0 0 0

0 0

0 0 0

medium scale integration (MSI) and large scale integration (LSI), more and more components and capabilities became possible on the silicon die or chip, but there were not enough pins or terminals in the DIP or other in-line styles to practically

61 2


support the logic that could be fabricated on a single die, This led to the need for different package types; the large pin (or terminal) count packages such as chip carriers and pin grid arrays (PGAs), the fine pitch QFPs and now ball grid arrays (BGAs) and multichip modules (MCMs). It is a fact of life that more pins can always be used. Multichip packaging is the latest direction for packages and modules. Multichip packaging is not new for it has been applied in both military and commercial applications for over 25 years. Ceramic hybrid technology, the original MCMs, provided the functional equivalent which the state-of-the-art semiconductor technology could not economically provide as a single die. As semiconductor technology advanced, those functions in the multichip package were, or were capable of being, replaced by single-chip functions with higher performance or capability. Yet, there was still the need/desire for capability beyond what single chip packaging could provide in the military and high performance markets which continued the growth of the hybrid industry and the same needs are now moving multichip packaging in ceramic, thin film and printed wiring technologies into the mainstream. More on that later. Single chip package types are still the basis for multichip packages and single chip packages will continue to be used in high volume. Multichip functions will become single chip functions or packages as semiconductor technology continues its relentless speed and density advancement. In the foreseeable future few barriers are predicted to limit this advancement. MCMs are another package technology evolving to further expand the packaging engineering toolbox. Proliferation of variations will continue and the complexity in choosing the “right” pack-

age will become greater and continue to drive interconnection technology. It must be emphasized that no one package or packaging technique can satisfy all applications. Each packaging approach has its advantages and disadvantages which must be considered in a system analysis of the complex technology, application requirements, manufacturability, maintainability, and cost tradeoffs typical of an electronic system as well as the unique, companyspecific practices (and biases) which exist in any company.

11.3 Integrated Circuit Processing It is important to understand the microinterconnect technology used in semiconductor packaging. Figure 11-1 depicts the major integrated circuit fabrication steps (for wire-bonded circuits) from the unprocessed wafer through the masking and wafer processing steps, also referred to as “front-end processing”, and the packaging steps from wafer mounting through sealing or encapsulation, the “back-end processi -.”. The wafer, with its hundreds or thousands of identical circuits, is mounted on a carrier with a heat releasable adhesive or wax. Wafer dicing is the sawing of the wafer to create the individual die,or chip, that will be packaged. Die attachment or die bonding is the physical attachment of the die to the package or substrate for mechanical attachment and heat conduction. Electrical contact is sometimes a function of the die attachment. The interconnection from the die to the package, leadframe, or substrate is shown as wire bonding (tape automated bonding steps are shown in Fig. 113) and interconnections at this stage are sometimes referred to as the “microinterconnect” to distinguish them from the interconnections external to a package. Note

11.3 Integrated Circuit Processing

61 3

AND LAYOUT

k4 MASK MAKING

& VERIFICATION

I

WAFER PRXESSING

4

I

PROBETEST

4 WAFER MOUWING

WAFER SAWlNODlClNG

DIE SEPARATION

OPTICAL INSPECTON

PACKAGES OR LEADFRAMES

u

DIE 83NDING

I

r

PRE-CAP OPTICAL INSPECTION

+

LOAD IN WAFFLE PACK

1

SEALING OR ENCAPSULATION

. IDS OR PLASTICS

i

FINALTEST

I

th it flip chip or solder bump microintercorinection does not use the die attach step fo the solder bumps serve to both attach and electrically interconnect the die. Sealing or encapsulation provides for the protecticln of the die from the environment. Note th 3 various points where test is performed. W tfers are tested in a probe test where eat:h individual die in the wafer is tested to

Figure 11-1. The major integrated circuit fabrication steps.

determine if it is functional. Typically only key DC characteristics are tested. Faulty circuits are identified with a spot of ink to indicate to subsequent assembly steps that the die is not functional. The final test, after all the packaging and assembly operations are complete, is the stage where full functional and AC testing and sorting for electrical and environmental performance is

614


accomplished. Testing at intermediate packaging stages is not practical so that a great deal of value is added between the last two test steps. The packaging represents a significant portion of the overall cost of a circuit.

11.4 Die Attachment There are four primary ways for the physical attachment of the die to the package or substrate: alloy or eutectic bonding, solder attachment, low temperature glass frits, and adhesive bonding. Dice that have been separated from the wafer may be in a “waffle pack” (a plastic case with a square array of pockets with a die in each pocket) for manual bonding to a package or substrate or they may be mounted on a releasable carrier that keeps the dice in a precise, uniform position (as they were fabricated) after the dicing operation for use in automated attachment equipment. Typically the equipment is pick-and-place style with a heated vacuum tip collet that picks up the die and moves it to the package or substrate which is on a heated platen. The collet has a mechanical action scrubbing the die on the package surface and a eutectic bond is formed between the silicon die and the gold plating in the package die attach area. For a larger die, a solder or gold alloy preform in the form of a thin (about 1 mil, i.e., -25 pm) wafer is placed between the package die attach area and the die. The back of the die is metallized with gold and the die attach area is also gold. The assembly is heated in the 300°C range where the preform flows and attaches the die to the package. Low temperature glass flowing in the 300-400 “C range is also applied with ceramic packages. Epoxies are also used, particularly in hybrid circuits and MCMs. When epoxies are

used there are organics present in the package that may be of concern for some applications where contamination may result. The epoxies are typically one-part materials and may be filled with metallic particles for good thermal and electrical conductivities. One criterion for acceptable die attachment has been established for the amount of material around the perimeter of the die. Typically military packaging requires a good fillet between a minimum of three sides of the die and the package base. This has been established for mechanical attachment but does not necessarily give an indication of the overall integrity of the die attachment, which is important in high dissipation circuits. X-rays and acoustic microimaging are means to examine the die attach to determine void free attachment for good thermal properties (DiGiacomo, 1989). Diodes with dedicated leads for thermal sensing and thermal resistance test equipment are also used. All of these test or analysis techniques can add significant cost to a circuit and should be carefully applied to any design or product specifications. Thermal performance is, however, an increasingly critical parameter that affects reliability and electrical performance, so the extra cost of insuring die attach integrity may be well justified in high performance, high price circuits. See the section on thermal management (Sec. 11.11).

11.5 Microinterconnect Methods Figure 11-2 shows three microinterconnect attachment or bonding methods: wire bonding, flip chip (also called solder bump or “C4” for controlled collapse chip connection), and tape automated bonding (TAB). The left side of the figure shows the orientation of the die with respect to the

11.6 Wire Bonding

61 5

r WIRE

‘-LEAD

FRAMEJ

METALLIZATION

SOLDER BUMP

I

f

COPPER (GOLD) BUMP

COPPER LEAD

r

-,-

I

1

BONDING

PLASTIC CARRIER

y

Figure 11-2. Integrated circuit die interconnection alternatives.

package mounting surface. In wire bonding the die is oriented “face-up”. The input/ o ~tput ! (I/O) terminals, and active surface of the die are up and away from the package mounting surface and are connected to th.: die and package by thermocompression, thermosonic, or ultrasonic bonding. The solder bump technology has a “facedown” orientation, where the active surface with its plated bumps is down and ad lacent to the mounting surface. A solder bL.mped die is attached by reflow soldering to interconnect the die to the package. IBM developed the technology in the 1960s for high volume automated assemblv, and the technology is used throughout their product line. They recently began licensing their technology and it has been licensed to a number of semiconductor mmufacturers. TAB technology is primarily a face-up technology with bumps plated on the die terminal pads. The bumps are thermocom-

pression bonded to copper leads supported by a plastic film carrier.

11.6 Wire Bonding In wire bonding, thin gold or aluminum wires typically 0.7-1.3 mils (18-33 pm) in diameter are bonded to connect from the die 1/0 terminals to the package, lead frame, or substrate metallization. This is a sequential operation forming one bond at a time. Automatic bonding machines operate at a rate of five to seven bonds per second, a significant increase over manual operations. Wire bonding is the most popular interconnect technology used in the merchant market. Table 11-2 shows some typical wire sizes. The most popular are 1.0 mil gold and 1.3-mil-diameter aluminum wire (1 mil N 25 pm). Note the length restrictions. The maximum wire lengths are a

616


Table 11-2. Wire bond mechanical and performance parameters. Material

Au Au AI SI A I SI

Wire diameter (in.)

Min. wire length (in.)

Max. wire length (in.)

Resistance per foot (a)

Max. current (A)

0.0010 0.0013 0.0010 0.001 3

0.040 0.040 0.020 0.020

0.080 0.1 10 0.120 0.150

13.5- 14.4 8.03-8.53 17.7- 19.5 1.3-1 2.5

0.200 0.500 0.125 0.250

Parameter

Wire bond a

TAB leadb

Aluminum

Gold

Copper

0.142 0.025 2.621

0.122 0.025 2.621

0.017 0.006 2.10

79.6 336.5

51.6 336.5

8.3 149.5

Electrical properties: Lead resistance (0) Lead to lead capacitance (pF; 0.008 spacing) Lead inductance (nH) Thermal resistance Lead conduction ( CjmW) Lead convection (free) ( C mW) a

0.001-in. dia. by 0.10-in. long wire bond.

0.001-in. by 0.004-in. by 0.100-in. long TAB lead (1 in. = 2.54 cm).

function of the ability of the wire to support itself, to maintain its integrity under shock and vibration, and to not short to adjacent wires. Also note the resistance values. Significant resistance (0.5 to 0.8 R is not unusual) and inductance (1-5 nH) can exist in the bond wires. This can affect electrical performance in current-carrying capabilities, signal propagation and circuit noise. Maximum-length considerations cause the package cavity size to vary based on die size, for if length exceeds acceptable limits, a smaller cavity size must be used. For power connections, internal bond sites and metallization may be wider to allow for multiple wire bonds and lower lead inductance and resistance. A variety of integrated circuit packages exist, which, from all external appearances, are the same; however, the internal details to accommodate different die sizes make them unique com-

ponents that the semiconductor manufacturers must stock. For power connections larger wire diameters (0.010 in = 0.25 mm diameter is not uncommon for power semiconductors) or multiple wire bonds and very wide internal package metallization are used to minimize resistance and increase current carrying capacity.

11.7 Tape Automated Bonding (TAB) In the early 1970s TAB was developed for automatic interconnection. Initially developed as a high-volume mass termination and production technique for small pin-count “jelly bean” (high-volume) circuits with 14-16 terminals, it is a technology that has become attractive for use with large-terminal-count die and for high performance circuits.

11.7 Tape Automated Bonding (TAB)

For TAB bonding the wafer must go through an additional processing step to “bump” the die 1/0 for thermocompression bonding and to avoid edge shorting. T! pically gold bumps or gold-over-copper bumps are used. The TAB process attaches a die to a tape or plastic film with an etched ccpper pattern, automatically taking it from the wafer and attaching it to the tape. Aatomated equipment makes the connections from the die to the tape, a process called “inner-lead bonding”. An advantage of this process is that the integrated circuits m.iy be tested or burned-in (subjected to te-nperature extremes that will cause those cixuits to fail that are not as reliable or prone to failure) prior to the expensive pitckaging and assembly steps. The “outerle,id bonding” process applies the tape-car-

ried integrated circuits (attached in the inner-lead bonding process) to the package or a multichip substrate, as would be done for hybrid technology or multichip modules. Figure 11-3 shows the basic process steps (Rima, 1985). Various types of lead formation can be employed. The term “spider bonding“ was used to describe this technology in its early development since the leads are formed away from the circuit in a spider-leg fashion where they can be attached by either solder or thermocompression bonding to a substrate. This lead form is now commonly referred to as “gull-wing’’ shaped leads. TAB is well-suited for high-performance multichip circuits for the advantages of high packaging density through the elimination of the individual IC package and

TAPE CARRIER WITH ETCHED LEAD PATTERN TEST IC WAFER WITH BUMPS ADDED TO BONDING PADS

INNER LEAD BOND TAPE CARRIER FABRICATION

..

I’

61 7

EXCISE, LEAD FORM, A N D OUTER LEAD UTEST AND BOND BURN I N HYBRID ASSEMBLY

Fixure 11-3. Tape automated bonding (TAB) process steps.

FINISHED HYBRID MICROCIRCUIT

61 8


package lead electrical degradation, with the ability to test and burn-in the IC prior to assembly. A related microinterconnect technology is “bumped tape”, where instead of bumping the wafer, bumps are formed on the tape. The bumps are needed for the bonding process and to ensure that the lead is above the surface of the die to minimize any possibility of edge shorting. Tape bumping eliminates the additional wafer plating steps required for TAB and the potential high-cost fallout, should damage occur at that process stage where all the value has been added to the wafer. Bumped tape uses a lower-cost wafer and less expensive tooling and has been successfully developed by some manufacturers, but is not a widely used technique. Another high density, fine pitch technique based on TAB technology is TapePack. Initial development was demonstrated with 20-min centerline terminal spacing, but the technology has the capability for finer pitches, to 10 mils (0.25 mm) or less. Tape-Pack uses TAB circuit fabrication, which is then overmolded with plastic to create a finished package. Leads may be formed in a number of configurations. This approach is an excellent example of high-density, fine-pitch packaging using TAB. It is significant to note that mechanical standards for testable metric TAB tape have been established by a joint activity of the EIA JEDEC committee in conjunction with their counterpart Japanese organization, the EIAJ EE13 committee. See Sec. 11.12, on package types, for information on the standards. There is more and more interest in chipon-board technology, particularly for MCMs with large-terminal-count TAB die, allowing testability, and by eliminating the IC package allowing circuits to be placed

much more closely together than packaged devices. Reliable, high-performance chipon-board technology becomes practical with TAB.

11.8 Flip Chip or Solder Bump IBM developed the controlled collapse chip connection (C4) process technology, more commonly refered to as flip chip or solder bump technology, in the early 1960s and has perfected this automated mass interconnection process. Of the total number of silicon interconnects used worldwide there are probably more solder bumps than any other type. Solder bumps have very short interconnections and the technique is more efficient in its use of silicon area because the full area of the chip can be used for 1/0 terminals. This is not possible with wire bonding or TAB because the pressures that are involved with the bonding process can change device characteristics if they are placed beneath 1/0 pads. Area array solder bumps are also more efficient for interconnection length and area, and all bonds are made in one reflow process step as opposed to the serial, one-at-atime, process with wire bonds. The process was not widely used outside of IBM, for the process controls are quite stringent, but IBM is now licensing the technology and it has significant advantages, particularly for high performance systems. Increasing use of solder bump interconnection is taking place and it is also being applied at the package level in ball grid array packages which will be discussed later. Tummala and Rymaszewski (1989) provide an excellent description of the solder bump technology.

61 9

11.9 Package Sealings

11.9 Package Sealing The last packaging process step is packape sealing. Ceramic packages use two basic processes: glass and solder sealing. Wzlding is used in very high reliability applrcations, typically with metal packages.

Figure 11-4 shows various ceramic package construction and sealing techniques. Glass may also be used to attach the package lid to the seal ring. Solder attachment of metal lids to a metallized seal ring is widely used in military applications. Metal or glass sealing results in a hermetic packKOVAR SEAL RING

ALUMINA

/

KOVAR

I

DIE

KOVAR OR OR ALUMINA

GLASS

(a 1

(b)

METAL (OR ALU .I1 IA)

t

METAL (OR ALUMINA) SOLDER

BRAZED

,(OR GLASS)

I

METALLIZATIO MULTILAYER E ALUMINA BRAZED LEADS

' METALLIZATION

(d)

(C)

DI'E

MULTILAYER ED ALUMINA

/

/

ALUMINA METALLiZATlON

Figure 11-4. Ceramic integrated circuit package alternatives: (a) CERDIP, (b) metal lid ceramic, (c) side brazed ceramic, (d) bottom brazed ceramic, (e) single layer chip carrier.

620


age, providing protection of the IC and its internal connections from the corrosioninducing moisture of the environment. Epoxy may also be used for cover or lid sealing and is used in some hybrid applications, however, while it makes it easier to repair/replace devices, this method does not reach the high degree of hermeticity of glass or solder sealing. In plastic packages, the die is attached to a lead frame, and plastic is molded to fully encapsulate the die. Plastic is molded around each die while in strip form and after molding, the package leads are formed, the packages separated and placed in tubes. Figure 11-5 shows a lead frame of a plastic package to which a die would be attached and wirebonded. Plastic packages are non-hermetic since the plastic materials allow the ingress of moisture. Some manufacturers use secondary protection materials such as silica gels or die coatings to protect the surface of the die from moisture. Although plastic packages have been continually improved and are very reliable due to improved plastics and die passivation (where the surface of the die is protected by glass or oxides or the gels, room temperature vulcanizing compounds, or other materials), plastic packages do not provide the long-term high-reliability of metal or ceramic packages. Some military applications are now using plastic packages in places they were

not previously permitted, and the military is moving toward much broader acceptance of plastic packaging due to economic pressure as well as improvements in materials and processes.

11.10 Rent’s Rule One of the primary driving forces of packaging technology is IC component density, not only in random logic but also in memory and microprocessors, and terminal counts have increased at a rapid rate and show no signs of slowing down. Increased IC component density, as measured by the number of components - logic gates per chip for random logic, storage cells for memory, transistors for microprocessors - will continue in the foreseeable future. As a result, the number of package I/O terminals has significantly increased to where microprocessor terminal counts are between 200 and 300 and moving into the 300 to 400 terminal range. (Current predictions are for a six million transistor microprocessor in 1995 and devices with terminal counts in the thousands.) Projections for general-purpose logic show terminal counts continuing to rapidly increase. Why is this? There is a relationship between the number of terminals and the number of logic gates in an electronic function. In the mid-1960s IBM studied their computer

Figure 11-5. DIP lead frame (front) and assembled, molded untrimmed lead frame (rear).

11.1 1 Thermal Management

lo$c packages on printed circuit boards ai-d developed a relationship called "Rent's rule" (Landman and Russo, 1971), a relationship between the number of pins p and th; number of logic gates g in the assembly. Tlie relationship has a proportionality fac.tor a multiplied by a number of gates raised to a power b (less than 1) in the form

p - = agb

(11-1)

Rvnt's rule was empirically derived for random logic on printed circuit boards but has also been shown to apply to individual serniconductor circuits. Bell Labs studies have shown the Rent's relationship that bejt fits their system designs to be p c z 4.5 go.5

(11-2)

Tliis is the number of signal pins needed to support the logic gate count and is typical of many others. The exponential relationship was also shown to apply to PWB routing density (Schmidt, 1981, 1982). Ujiisys studied some of their gate-array logic functions (Steele, 1981) and found the relationship that best fits their designs to be p

:=

2.2 9 0 . 6

(11-3)

again, one that best fits their component, pr ,duct and systems designs ut that time. The power pin relationship will vary wiih circuit technology. For the Bell Labs model the estimator for the number of power pins required was 25% of the number of signal pins. Another more practical ruie of thumb is to estimate the number of pc wer terminals as a function of the number of active outputs; for example, one gr iund terminal for every three switching outputs has been used for ECL circuitry. Aiiother consideration which must be tailen into account to determine the numbei- of power terminals is the total current foi the package to meet DC drop/noise

62 1

margins; with high-speed logic the larger the number of signal outputs the more power terminals are needed for a larger number of outputs that switch simultaneously. The increased number of power terminals reduces the overall lead inductance, an important parameter for simultaneous switching, to minimize noise and ensure signal integrity, and increase performance. Additional power terminals may also be used for impedance control, where the power terminals serve as an impedance reference for the signals and maintain a uniform impedance across the package or connector interface. Lastly, system noise immunity must be considered, and a sufficient number of power and ground terminals must be provided to minimize power distribution losses and keep the noise levels within system noise limits. All of these considerations result in an increasing number of pins for logic devices.

11.11 Thermal Management 11.11.1 Thermal Resistance

Thermal resistance is defined as

(11-4) where TI is the average die junction temperature ("C), T2 the ambient air temperature ("C), P the dissipated power (watts, W), and e,,., the junction-to-air thermal resistance ("C/W). OJA is the summation of the thermal resistances from the die to the airstream which is removing most of the heat. It comprises the thermal resistances of the die (silicon), the materials used to attach the die to the package and the package (its base material and metallization in the thermal path). The thermal resistance from the

622


junction to the case or exterior of the package is called ~ J C it; is a uniform characteristic of a package, or common reference point, for an integrated circuit manufacturer to specify thermal performance. Heat sinks and the means to remove heat external to the package are functions of individual designs and are difficult for an IC manufacturer to specify or control. 8 J C is what is typically characterized and specified by semiconductor manufacturers for a pack~ heatage. The user determines 6 , through sink and system-cooling design. If a heat sink is present this includes the material used to attach the heat sink to the package, the thermal resistance of the heat sink, and the effect of airflow over the package, so that

Junction-to-air thermal resistance is the summation of the individual thermal resistances of the elements that are in the thermal path of the package: 8jA=eD

+ 6jl +

+

6 p + 6 ~ 2 6H+853

where 8 j A is the junction-to-ambient thermal resistance of the assembly, 8, the thermal resistance of the die, Brl the thermal resistance of the die-to-package interface, 8, the thermal resistance of the package material, 8 J 2 the thermal resistance of the package-to-heat-sink surface, 6 , the thermal resistance of the heat sink material and 6j3 the thermal resistance of the heat sink to ambient air (film resistance). The thermal resistances are depicted in Fig. 11-6, a cross-sectional exploded view of a board-mounted package. Typical thermal resistance of DIP packages ranges

AMBIENT A I R

t HEAT SINK

EPOXY

\,

CHIP CARRIER.

f-'J2 'T

I

SUBSTRATE CLIPS

-

EPOXY

6,

THERMAL DIE

LID

(11-6)

I

PRINTED CIRCUIT BOARD

Figure 11-6. Integrated circuit package cross section and package component thermal resistances.

11.1 1 Thermal Management

623

30

25

20

z

,'3

15

0.128 X O 192 in DIE

42 m 10

5

0

I

I

I

I

I

I

I

I

250

500

750

1000

1250

1500

1750

2000

AIR VELOCITY, LINEAR FEET/MIN

Figure 11-7. Typical thermal resistance of a 0.950' square leadless multilayer ceramic chip carrier.

from 50 to 200 "C/W, depending on material , and construction. In Fig. 11-7 a plot of th 2 thermal resistance of a 0.950 in. (24 mm) square 68 1/0 chip carrier. Note that the e8ective thermal resistance, 8 J A , varies with th; airflow (air velocity is a measure of the ariount of air over the package measured in linear feet per minute, LFPM). For these chip carriers elAis about 25"C/W in still ail. At 1000 LFPM the thermal resistance is 'tbout 12"C/W. Keep in mind that each pa;kage type has a unique thermal resista ice. To determine thermal performance, one m 1st consider the package environment, nc't just the system environment. A piece of equipment might typically have a maxim im specified ambient operating temperature of 40°C. However, the air outlet temperature of the equipment will be subject to th: heat rise from devices beneath them,

and it is not unusual for an internal temperature rise to be 20°C so that the electronics near the air outlet will experience a 60°C maximum ambient temperature. If a package is dissipating 5 W (not unusual with today's circuits) and has a junctionto-air thermal resistance, 8 J A = 12 "C/W, the temperature difference from the junction to the ambient airstream will be 60°C ( 5 W x 12"C/W). The 60°C ambient air cooling the package is added to that of the junction temperature rise, resulting in a junction temperature of 120 "C. While this is within the limits of the operating temperature of most ICs, it is best to minimize the junction operating temperatures for improved reliability and performance. With higher temperatures and larger temperature differences, electrical parameters will degrade, and the non-uniformity of the thermal environment will cause wide differ-

624


ences in the electrical characteristics (e.g., threshold level, noise immunity) of the IC so it is best to have temperature differences minimized. Thermal performance of packages is a major concern with new highspeed circuits and MCMs. Keep in mind that the die attach process has a primary effect on the thermal resistance of an integrated circuit package. 11.11.2 Cavity-Up/Down

Another important package characteristic relating to thermal performance is the orientation of the internal package cavity which is referred to as “cavity-up’’and “cavity-down”. Most DIP packages are in a cavity-up configuration. This terminology was created when chip carriers became popular since they offer the opportunity for mounting in both the cavity-up and cavity-down orientation because they are leadless and can be metallized to allow them to be mounted with the die cavity adjacent to, or away from, the mounting surface (or package seating plane). For air-cooled systems, the cavity-down configuration, where the die cavity is down and adjacent to the mounting surface, was developed. This arrangement allows the primary heat-dissipating surface, the back side of the die and the back of the package, to have direct conduction from the die surface through the die through the back of the package to the heat sink, as shown in Fig. 11-6. The cavity-down construction has been used extensively in air-cooled systems. Figure 11-8 shows a cavity-down PGA package configuration. PGA packages also have the capability of both orientations but the maximum terminal count is reduced in the cavity-down configuration. This is shown in Fig. 11-9. The cavity-up construction is still quite popular for indirect cooling. such as cold bars or surface

pads, to remove the heat through the base of the package into, or through, the mounting substrate or printed circuit board. Packages now are becoming more and more complex to where they must package die dissipating 30-50 W in a single chip package. Thermal performance has always been important in electronic packaging, but it is now essential to consider thermal performance in the earliest stages of system and packaging design for successful system application. Thermal design and performance can no longer be an afterthought.

11.12 Package Types As defined in the introduction, a package is “an enclosure for one or more semiconductor chips that allows electrical connection and provides mechanical and environmental connection” and can be of many forms each having numerous variations. There are many package standards and there is an active effort in the worldwide industry to minimize the number of package variations. The primary standards organization for IC Packages in the U.S.A. is JEDEC.

11.13 JEDEC JEDEC, formerly the Joint Electron Devices Engineering Council, is a function of the Electronics Industry Association (EIA) and defines the microelectronic standards in the U.S.A. JEDEC currently has 15 committees that are involved in all aspects of microelectronics and semiconductor technology standardization, specializing in digital, bipolar, MOS, linear memory, gate arrays, mechanical standards and other areas. The EIA/JEDEC JC-1 1 Committee on Mechanical Standardization of

11.13 J E D E C

625

Figure 11-8. A cavity-up pin grid array package with a double bond shelf,

Figure 11-9. Pin grid array double bond shelf packages: cavity-up (center) and cavity-down (left and right).

Solid State Devices is responsible for micrc )electronic package outlines and has developed standards for all package types. This committee is the recognized U.S.standa rd organization for packages and represeIits the United States in the International Elt.ctrotechnica1Commission (IEC) (Freedm:.n, 1993). The JC-11 committee has an ongoing standardization effort for packages in both ceiamic and plastic construction and in 1938 pioneered international coordination to minimize package proliferation by estaldishing an ongoing relationship with its co Linterpart Electronics Industry Association of Japan, EIAJ EE-13 committee.

The JEDEC JC-11 committee has attempted to minimize the variations and has provided excellent documents defining the mechanical outlines of packages in Publication 95, JEDEC Registered and Standard Outlines for Semiconductor Devices, and package design guidelines in JEDEC Standard No. 95-1, Design Requirements f o r Outlines of Solid State and Related Products. The JEDEC JC-IO Committee on Terms and Definitions has developed a number of documents on symbols, terms and definitions for semiconductor and optoelectronic devices, two of which are of significance to packages: JEDEC Standard No. 99, Glossary of Microelectronic Terms,

626


Definitions and Symbols and JEDEC Standard No. 30, Descriptive Designation System for Semiconductor-Device Packages. JEDEC is moving toward full adoption of the alphanumeric package designations described in JESD-30, which includes in the designation details of design and construction. As they are not fully adopted, they have not been included herein (JEDEC Standard 95, JEDEC Standard 30). Another useful reference defining package types is the US. Military Standard MIL-STD-1835, Microcircuit Case Outlines and the Electronic Packaging, Microelectronics, and Interconnection Dictionary (Harper and Miller, 1993). The following descriptions are based on these references; however, in many cases there are minor differences in the “standard” definitions in these documents, in which case a description has been created from them or the most appropriate description selected and referenced. The following descriptions of package types are for the most popular existing and emerging types and do not cover all possible types and variations. They can be found in the JEDEC Standards.

11.13.1 Dual In-Line Package A dual in-line package is a rectangular package with two parallel rows of terminals, or leads, that are positioned in two straight rows on the sides of the package. The terminals are oriented perpendicular to the package seating plane for insertion into interconnecting holes in a substrate. Figure 11-10 shows a variety of DIPS in a printed wiring assembly.

11.13.2 Flatpack A flatpack is defined as “a low-profile

package whose leads project parallel to, and are designed primarily to be attached parallel to, the seating plane. The leads typically originate from either two or four sides of a package. The body of the flatpack is similar to that of a chip carrier. Leads may be formed generally away from the package body. If the leads are formed back towards the package body, the correct term is “chip carrier” (JEDEC Standard 95, JEDEC Standard 30). The flatpack was one of the earliest package types and a long-time military use package (with

Figure 11-10. Through-hole mounted integrated circuit packages.

11.13 JEDEC

627

leads on two sides). With the advent of high density surface mounting the quad flat pack (QFP)with leads on all four package sides, in both English and metric spacing. became popular for high lead count very fine pitch surface mounting for its ease of membly and inspectability. 11.13.3 Chip Carrier This term is sometimes used to describe an! package which contains a chip but is more properly used to define a specific Invented in the late 1960s in package cer

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