Device Applications of Silicon Nanocrystals and Nanostructures

Device Applications of Silicon Nanocrystals and Nanostructures Nanostructure Science and Technology Series Editor: Da...

Author: Nobuyoshi Koshida

77 downloads 993 Views 35MB Size Report

This content was uploaded by our users and we assume good faith they have the permission to share this book. If you own the copyright to this book and it is wrongfully on our website, we offer a simple DMCA procedure to remove your content from our site. Start by pressing the button below!
Report copyright / DMCA form

DOWNLOAD PDF

Device Applications of Silicon Nanocrystals and Nanostructures

Nanostructure Science and Technology Series Editor: David J. Lockwood, FRSC National Research Council of Canada Ottawa, Ontario, Canada

For other titles published in this series, go to www.springer.com/series/6331

Nobuyoshi Koshida Editor

Device Applications of Silicon Nanocrystals and Nanostructures

Editor Nobuyoshi Koshida Department of Electrical & Electronic Engineering Tokyo University of Agriculture and Technology Tokyo, Japan

ISBN: 978-0-387-78688-9 e-ISBN: 978-0-387-78689-6 DOI: 10.1007/978-0-387-78689-6 Library of Congress Control Number: 2008940837 © Springer Science+Business Media, LLC 2009 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper springer.com

Foreword

Silicon: Different people associate the word with different things. The general public will often correctly link it to electronics and sometimes confuse it with the compound that seals their bath or enlarges particular body parts. As scientists or technologists, we know the elemental semiconducting version to be one of, if not, the most studied materials known. But when we sculpt solid silicon structures below 10 nm, a variety of dramatic and often astonishing effects ensue. Indeed, this book on nanostructured silicon devices brings together two of the great endeavours of our generation. There has already been huge investment and human ingenuity in the pervasive silicon device – the integrated circuit. There is now also mounting excitement and investment in nanotechnology – our ability to design, fabricate, and use techniques and materials at the nanoscale. The book’s editor, Professor Nobuyoshi Koshida, is undoubtedly a great pioneer in this field, with more than 30 years of world-leading research on novel phenomena, characterization, and uses of nanoscale silicon. He has assembled a great team of authors, all established experts in their respective areas of specialization. The content of this book show a bias toward electronic chip-based uses of “nano-silicon” (Chaps. 5–8), and rightly so. Indeed many would argue that we are only interested in silicon nanostructures because of what the bulk material has achieved with its integrated circuits inside everyone’s PC, and what we hope MEMS technology might achieve. Nonetheless, within the book, one also will find significant progress toward using nano-silicon in scientific fields that might not be an obvious choice for this semiconductor. Examples are optics/photonics (Chaps. 1 and 3), optoelectronics and displays (Chaps. 2, 4, 9), biological diagnostics (Chap. 10), and ultrasonics (Chap. 11). The interest in nanoscale silicon grew dramatically in the early 1990s and continues almost 20 years later, but in a diversified manner. The wonderfully dramatic effects of quantum confinement have enriched what was already a fairly versatile material – the additional effects of nanoscale porosity allowing tunability of many of its properties over ranges that were thought impossible. v

vi

FOREWORD

In this book, you will discover how we now can manipulate current transport and charge in assemblies of nanocrystals at incredibly small dimensions, enabling various novel electronic devices to be realized. We can nanostructure pure silicon to be pink, green, red, or any color you like. It can be used to detect and distinguish biomolecules at very low concentrations. It can emit visible light at high efficiency. It can generate music from electrical signals. From my own studies, it can be biodegradable in the human body and thus used medically. It may even have nutritional uses in food. It is a material that continues to surprise us with its expanding potential. Malvern, UK

Leigh Canham

Preface

Semiconductors exhibit a critical size at which quantum confinement effects become apparent. A measure of this condition is the exciton Bohr radius. This value in single-crystalline silicon is below 5 nm, which is exceptionally small in comparison to most conventional semiconductors, and is one reason why the development of silicon-based logic and memory devices has followed an anticipated road map. In fact, however, silicon devices have evolved in all stages of the design, processing, and fabrication technologies. The scaling principle is the engine driving these advances in integrated circuitry. The scaling of advanced MOS technology is now entering the region of 10 nm. As the scaling extends to the region below the quantum-size criterion, it should be noted that the original optical, electrical, thermal, and chemical properties of bulk silicon are substantially modified. As a consequence, various useful functions are induced in quantum-sized nanocrystalline or nanostructured silicon materials. For instance, a significant band gap widening and delocalization of carriers in momentum space make the optical property free from the traditional direct or indirect-transition regime. Efficient visible luminescence is created and opens the door toward integrated silicon photonics. In addition, the range of possible applications in quantumsized silicon is extending to the field of electronics, acoustics, and biology. The main theme of this book is how widely the potential functions of silicon have been implemented as devices in the nanometer region, and that silicon devices in the quantum zone produce various technological values different from the scaling merits. The volume is composed of three main subjects: photonic devices (four chapters), electronic devices (five chapters), and functional devices (two chapters). In the first four chapters, basic characterization of silicon-rich dielectrics for photonic uses are addressed followed by the development of silicon electroluminescence devices as a key issue for monolithic integration. The succeeding two chapters describe fabrication and properties of periodic silicon nanostructures as an important photonic component as well as analyses of possible optical gain in silicon system leading to a breakthrough in this field. vii

viii

PREFACE

The next five chapters are devoted to state-of-the-art work on electronic devices based on nanostructures: single-electron device, spin transistor, specified electron transport in nanosilicon dot chains, nonvolatile information storage, and surface-emitting ballistic cold cathode. These topics suggest the range of forthcoming electronic device applications. The last two chapters concern the applicability of nanostructured silicon layers to functional biosensing scaffold and to thermally induced ultrasound emission. The former and the latter come from the biocompatible nontoxic features and complete thermal insulating properties of nanoscale silicon, respectively. As demonstrated in all chapters, the key word common to nanocrystalline or nanostructured silicon is functionality as a technology platform for next-generation devices. Hopefully, this book gives a perspective on the device image in the postscaling era, since silicon technology should be further amplified by functional integration in which photonic, electronic, acoustic, and biological functions are involved in conjunction with advanced ULSI devices. Tokyo, June 2008

Nobuyoshi Koshida

Acknowledgments

The editor thanks all coauthors of this book for the stimulated and careful preparation of their manuscript and artwork. It was great to have an opportunity of fruitful cooperation with many colleagues during this project. Thanks are due to Dr. D.J. Lockwood, the series editor of Nanostructure Science and Technology, for his encouraging suggestions in the progress of this work and to Prof. L.T. Canham for his continuing and invaluable communications. The production of this book is totally owing to patient, competent, and helpful support of Anushka Hosain, Lee Lubarsky, and Dr. David Packer at Springer.

ix

Contents

1

Si-Rich Dielectrics for Active Photonic Devices ...................................... L. C. Kimerling, L. Dal Negro, M. Stolfi, J. H. Yi, J. Michel, X. Duan, E. H. Sargent, T.-W. F. Chang, V. Sukhovatkin, J. Haavisto, and J. LeBlanc

1

2

Nanocrystalline Si EL Devices .................................................................. B. Gelloz and N. Koshida

25

3

Surface and Superlattice ............................................................................ Rabah Boukherroub

71

4

Optical Gain and Lasing in Low Dimensional Silicon: The Quest for an Injection Laser ............................................................... Lorenzo Pavesi

103

5

Silicon Single-Electron Devices ................................................................ Yasuo Takahashi, Yukinori Ono, Akira Fujiwara, Katsuhiko Nishiguchi, and Hiroshi Inokawa

125

6

Room Temperature Silicon Spin-Based Transistors .................................. M. Cahay and S. Bandyopadhyay

173

7

Electron Transport in Nanocrystalline Silicon .......................................... H. Mizuta, S. Uno, N. Mori, S. Oda, and N. Koshida

197

8

Silicon Nanocrystal Nonvolatile Memories ............................................... R. Muralidhar, M.A. Sadd, and B.E. White Jr.

223

xi

xii

CONTENTS

9

Nanocrystalline Silicon Ballistic Electron Emitter.................................. Takuya Komoda and N. Koshida

251

10

Porous Silicon Optical Label-Free Biosensors ........................................ Philippe M. Fauchet

293

11

Ultrasonic Emission from Nanocrystalline Porous Silicon ..................... Hiroyuki Shinoda and Nobuyoshi Koshida

325

Index ................................................................................................................

337

1 Si-Rich Dielectrics for Active Photonic Devices L. C. Kimerling*, L. Dal Negro†, M. Stolfi, J. H. Yi, J. Michel, X. Duan, E. H. Sargent, T.-W. F. Chang, V. Sukhovatkin, J. Haavisto, and J. LeBlanc Abstract The quest to develop an efficient Si-based light emitter has stimulated research worldwide. Among the several approaches being considered, enhancing the probability of light emission through the use of Si nanocrystals embedded in SiO2 shows considerable promise due to the demonstration of efficient room temperature light emission and optical gain. In this chapter, we compare the nucleation, light emission, and emission sensitization of Si nanocrystals embedded in Si-rich oxide and Si-rich nitride. Based on the results of our study, we identify Si nanocrystal emission from Si-rich nitride and Er doping of Si-rich oxide as materials systems that satisfy the requirements of CMOS compatible processing and high emission efficiency for integration with Si-based electronics. We also present PbS quantum dot emission sensitization through Si nanocrystals in Si-rich nitride, an alternative approach to achieving efficient infrared emission on a Si platform. The improved electrical properties and high refractive index of Si-rich nitride also allows for the fabrication of electroluminescent devices with small footprints and active, complex photonic crystal devices for multiwavelength applications.

1. INTRODUCTION

The trend of improving microprocessor performance through size scaling has revealed several challenges that threaten the microelectronics industry’s ability to follow Moore’s law. Large RC delays and heat dissipation produced by closely

* Massachusetts Institute of Technology, 77 Massachusetts Avenue, Cambridge, MA 02139-4307, USA, [email protected] † Department of Electrical and Computer Engineering, Boston University, Boston, Massachusetts 02215 and Materials Science Division, Boston University, Boston, Massachusetts 02215

N. Koshida (ed.), Device Applications of Silicon Nanocrystals and Nanostructures, DOI: 10.1007/978-0-387-78689-6_1, © Springer Science + Business Media, LLC 2009

1

2

KIMERLING ET AL.

spaced, small cross-sectional metal interconnects have replaced transistor gate delays as the primary limiting factor in improving performance and in stimulating the development of novel approaches for device interconnection. Si microphotonics, the monolithic integration of Si-based optics and electronics, is one approach to device interconnection that offers significantly improved bandwidth with negligible heat dissipation and cross-talk to achieve high clock speeds and low latency interconnection between microprocessors operating in parallel. Optical interconnection, when applied to the telecommunications industry, led to improvements of several orders of magnitude in information capacity. Several of the building blocks required to apply this technology to electrical integrated circuits have recently been demonstrated in Si including low loss optical waveguides for interconnection [1], optical modulation [2], and switching [3]. Missing is an efficient Si-based light emitter. It is well known that Si is an indirect bandgap material where photon emission originates from low-probability, phonon-mediated transitions that compete unfavorably with fast, nonradiative deexcitation paths, such as Auger recombination and free carrier absorption. As a result, the only reports of lasing in Si are based on stimulated Raman scattering, which suffers from a high threshold and low wall-plug efficiency [4, 5]. To overcome the limitations for light emission in Si several strategies have been recently developed to engineer Si into a more efficient light emitting material [6–10]. The approach of quantum confinement has led to a dramatic improvement of the light generation efficiency in Si nanostructures [9–12]. The high emission efficiencies of up to 23% under optical excitation reported in porous Si after high pressure water vapor annealing [12], integration of a porous Si light emitting diode and bipolar transistor [13], and sizeable optical gain recently demonstrated in Si nanocrystals embedded in SiO2 matrices [14–19] have opened the race toward the fabrication of an integrated, fully Si-based laser [9]. Moreover, it has been recently discovered that Si nanocrystals act as efficient emission sensitizers for rare-earth ions, particularly Er ions, allowing broad band pumping of 1.54 μm light emission with almost three orders of magnitude-enhanced pumping efficiency [20–25]. With sizes ranging from 1 to 10 nm Si nanocrystal systems possess high surface to volume ratios. Therefore, it is no surprise that the interface between the Si nanocrystal and the surrounding matrix plays a crucial role in determining the optical properties of Si nanocrystals. In particular, the presence of Si&dbond;O bonds [26–29] at the surface of small Si nanocrystals embedded in Si-rich oxide is believed to have a dramatic impact on the light emission properties of these systems. This opens the possibility of engineering the interface properties through the controlled addition of dopants or changing the surrounding dielectric matrix entirely. An intriguing possibility would be the nucleation of Si nanocrystals in dielectric matrices with smaller bandgaps than SiO2, and more favorable electrical properties compared to traditional devices based on porous Si and Si nanocrystals embedded in SiO2 matrices. Following this approach, visible and near-infrared light emitting Si nanocrystals embedded in Si3N4 matrices have been recently demonstrated [30, 31] and efficient visible electroluminescence has been reported [32, 33]. In this chapter, we report on a comparison between the formation and properties of Si nanocrystals fabricated in Si-rich oxide and Si-rich nitride. There are three

1. SI-RICH DIELECTRICS

3

objectives to our study (1) obtaining a deeper understanding of the processes leading to efficient light emission and emission sensitization, (2) optimizing the fabrication conditions with respect to performance, and (3) investigating novel applications and devices based on Si nanocrystals including energy transfer to PbS quantum dots and active photonic crystals. The standards we use to determine optimum performance are (1) CMOS compatibility, using standard CMOS processing techniques with a low thermal budget; (2) high emission efficiency; and (3) in the case of electrically driven devices, stable operation and high injection efficiency at low voltages.

2. NUCLEATION AND STRUCTURAL PROPERTIES OF SI NANOCRYSTALS

Si nanocrystals have been produced through several techniques including annealing of Si-rich oxide [34–39], electrochemical etching [6, 40], laser-assisted processing [41, 42], solution synthesis [43], and annealing of Si/SiO2 [44] or SiO/SiO2 superlattices [45]. In this chapter, we will focus on the fabrication of Si nanocrystal devices through annealing of Si-rich oxides and nitrides. Si-rich oxide can be fabricated through a variety of techniques such as ion implantation into stoichiometric SiO2 [35, 36], chemical vapor deposition [34, 37], sputtering [38], and thermal evaporation of SiO [39]. After deposition, the films are annealed to induce a precipitation transformation where the metastable Si-rich dielectric film decomposes into two stable phases: Si clusters and a matrix, which is closer in composition to the equilibrium (stoichiometric) composition. According to classical nucleation theory [46, 47] the driving force for the precipitation transformation is a volume free energy reduction, ΔGv(XSi,TA), which increases as the Si content is increased above the stoichiometric level (given by the mole fraction of Si, XSi) and the annealing temperature, TA, is increased. Opposing the volume free energy reduction is the energy required to create the interface between the Si cluster and the matrix, AgCM, where A is the surface area and gCM is the cluster–matrix interfacial energy. The total free energy passes through a maximum as a function of cluster radius where the maximum is associated with the free energy to form a critical nucleus, which is 3 given by the expression ΔG* = (16πg CM ) 3ΔGv2 for spherical clusters with a critical cluster radius of r* = 2gCM / ΔGv. In homogeneous nucleation, all of the energy required to form the cluster–matrix interface must be supplied by the chemical driving force, as described above. However, in most real systems the nucleation occurs through heterogeneous nucleation at pre-existing defect sites where the threshold for nucleation is reduced by the energy released through the annihilation of the defect. In either case, once nucleation occurs with the formation of critically sized nuclei, cluster growth is governed by the process of coarsening, which minimizes the overall surface energy of the system by promoting the growth of large clusters at the expense of smaller clusters. By considering these principles of nucleation and growth, the parameters of Si content, annealing temperature, and annealing time can be used to fabricate nanocrystal ensembles with the desired size and density. For example, the theory predicts the highest density of small Si nanocrystals for low annealing temperatures. We will describe in the following sections how the fabrication conditions of Si content, annealing temperature, and annealing time are

4

KIMERLING ET AL.

important for the fabrication of nanocrystal ensembles with high quantum efficiency, strong emission sensitization, and high electrical injection efficiency. To investigate the formation of Si nanocrystals we have prepared Si-rich nitride thin films through plasma-enhanced chemical vapor deposition (PECVD) and magnetron co-sputtering and Si-rich oxide thin films through reactive magnetron sputtering. The PECVD nitride films were fabricated using an Applied Materials Centura DxZ chamber with SiH4 and N2 as precursors and a substrate temperature of 400°C. The sputtering was performed, without substrate heating, in a Kurt J. Lesker Co. CMS-18 system. For the Si-rich nitride films, the sputter deposition was performed using Si and Si3N4 targets in an Ar atmosphere. For the Si-rich oxide films, the sputter deposition was performed reactively using a Si target in an O2/Ar atmosphere. We used Raman spectroscopy to examine the evolution of the Si-rich dielectric matrix with annealing conditions since amorphous and crystalline Si structures have unique Raman signatures [48]. Both unannealed Si-rich nitride and unannealed Si-rich oxide (Fig. 1a, b; dotted line) show a broad Raman band due to an amorphous Si network while an additional broadened, asymmetric, and shifted Raman peak (with respect to bulk Si) can be clearly observed for annealed samples (Fig. 2a, b; dashed line). For the annealed, PECVD-deposited Si-rich nitride sample, three peaks can be distinguished in Fig. 1a corresponding to the two-phonon acoustical (~300 cm−1) and optical (~900 cm−1) scattering bands as well as the one phonon band at 512 cm−1. We also note that for the PECVD Si-rich nitride sample after annealing, the two-phonon optical (~900 cm−1) and acoustical (~300 cm−1) scattering bands are strongly enhanced with respect to both the bulk Si and the unannealed sputtered Si-rich nitride sample. The presence of a significantly shifted (Δν ~ 15 cm−1) and asymmetrized one-phonon Raman peak for annealed, PECVD-deposited Si-rich nitride and annealed, sputtered

FIG. 1. (a) Micro-Raman spectra of crystalline Si (solid line), unannealed Si-rich nitride deposited by sputtering (dotted line), and PECVD deposited Si-rich nitride annealed at 700°C for 10 min (dashed line). (b) Micro-Raman spectra of crystalline silicon (solid line), unannealed Si-rich oxide deposited by sputtering (dotted line), and Si-rich oxide deposited by sputtering annealed at 1,100°C for 1 h (dashed line). (c) Micro-Raman spectrum of Si nanocrystals embedded in SiO2 annealed at 1,100°C for 1 h (solid line). Theoretical simulation assuming ~6 nm average crystal diameter (dotted line). (d) Micro-Raman spectrum of Si nanocrystals embedded in amorphous Si3N4 annealed at 700°C for 10 min (solid line). Theoretical simulation assuming 2-nm average crystal diameter (dotted line).


5

Si-rich oxide is the direct evidence of the formation of small Si clusters embedded in the amorphous dielectric matrix. The physical origin of the broadened Si peak is related to the uncertainty in the Si-cluster phonon momentum, q, that allows modes with q ≠ 0 to contribute in the Raman spectrum. This general physical picture, referred to as phonon bottleneck, can be quantitatively described within a phenomenological model that accounts for the line shape of the TO one-phonon modes of quantum-confined Si clusters [49]. The one-phonon Raman line shapes can be easily obtained by calculating the integral transform [50] e − qL / 4 a d 3 q, 0 [w − w (q )]2 + (G / 2)2 0 2

I (w ) = ∫

1

2

(1)

where L is the average Si nanocrystal radius, G0 is the linewidth of the LO bulk Si phonon, and a is the Si lattice constant. The phonon dispersion of the bulk material is given by the relation ω2(q) = A + Bcos(Pq / 2) with A = 1.714 × 105 cm−2 and B = 1.000 × 105 cm−2 [50, 51]. This phenomenological approach allows us to simulate the experimental Raman data and to estimate an average size for the quantum confined scattering particles. We have applied this procedure to the Si-rich oxide sample annealed at 1,100°C for 1 h and the Si-rich nitride sample annealed at 700°C for 10 min. In the case of annealed Si-rich oxide (Fig. 1c), we estimate an average diameter of ~6 nm, while in the case of annealed Si-rich nitride (Fig. 1d), the micro-Raman data are compatible with the presence of smaller Si clusters with an estimated diameter less than 2 nm, as fitted within the phonon confinement Raman model. To check the consistency of this analysis, the nanocrystal sizes were observed through transmission electron microscopy (Fig. 2). The average diameters determined from the

FIG. 2. (a) Plan view transmission electron microscope image of Si nanocrystals (dark spots) with an average diameter of 6 nm embedded in Si-rich oxide annealed at 1,100°C for 1 h. (b) Cross-section transmission electron microscope image of Si nanocrystals (dark spots) with an average diameter of ~1–2 nm embedded in Si-rich nitride annealed at 700°C for 10 min.

6

KIMERLING ET AL.

electron micrographs were 6 nm for Si-rich oxide and ~1–2 nm for Si-rich nitride in perfect agreement with the analysis of the Raman spectra.

3. OPTICAL PROPERTIES OF SI NANOCRYSTALS

Based on the different sizes, densities, and formation conditions for our Si nanocrystals in oxides and nitrides, we can expect that their optical properties and the optimization of those properties may also be different. This is generally true for Si nanocrystals that have been produced through a variety of techniques due to the sensitivity of the nanocrystal performance on the details of the sample preparation [52]. Before discussing the comparison of the optical properties of our nanocrystals, we will review the optical properties of Si nanocrystals in oxide systems which have been investigated extensively. Si nanocrystals possess several intriguing optical properties with application toward the fabrication of optoelectronic devices. Among these is a broad, near infrared emission spectrum, located above the band edge of bulk Si, with a peak emission wavelength that can be tuned over a few hundred nanometers by varying processing parameters [41, 53, 54]. Several studies have been conducted to understand the origin of this strong emission. Time-resolved photoluminescence experiments have revealed a stretched exponential decay of the nanocrystal emission with a decay time in the range of 10–100 μs [55]. The stretched exponential decay is caused by energy migration from small Si nanocrystals to large Si nanocrystals with the degree to which the exponential is stretched decreasing with increasing excitation wavelength (selectively exciting progressively larger nanocrystals) [56]. Emission experiments performed on single Si nanocrystals have revealed a homogeneous linewidth of 100–150 meV at room temperature; the typical spectral width, which can be as large as 500 meV, is therefore dominated by inhomogeneous broadening due to the broad size and shape distributions that exist in typical Si nanocrystal ensembles [57]. Despite the strong luminescence from Si nanocrystals, it has been shown through spectral hole burning experiments that the indirect bandgap properties of bulk Si are still retained in Si nanocrystals [58]. The effect of quantum confinement of excitons within the Si nanocrystal is to increase the energy gap leading to a decrease in the emission wavelength and enhance the probability of no-phonon radiative recombination. In general, the trend of emission energy vs. nanocrystal size follows a model consistent with quantum confinement for large nanocrystals. For small nanocrystals, it has been observed that the emission energy does not increase beyond 2 eV although the nanocrystal size is decreased. Wolkin et al. [26] attributed this pinning of the bandgap to exciton recombination via Si=O bonds located at the nanocrystal/oxide interface. The sensitivity of the optical properties to the nanocrystal surface chemistry was further examined by Pudzer et al. [28] revealing the complex interplay between size and surface effects. Co-doping of Er with Si nanocrystals can also have several positive consequences for the fabrication of Er light emitting devices. Conventional Er-doped waveguide amplifiers require intense optical pumping at discrete wavelengths due


7

to the small absorption cross sections corresponding to the atomic energy levels of Er. When co-doped with Si nanocrystals, Er excitation occurs via the nanocrystals with the nanocrystals absorbing the pump light and transferring the excitation to the Er with dramatic results [20–25]. The excitation cross section of Er is enhanced by as much as 1,000× with respect to Er in stoichiometric SiO2 (Er:SiO2) [24]. Additionally, since the excitation is occurring through the nanocrystals, any pump wavelength within the nanocrystal absorption band can be used to efficiently excite the Er ions allowing for optical pumping via white light or LED sources [59, 60]. Electroluminescent devices have also been demonstrated [61, 62]. In addition to investigating the sensitization properties of Si nanocrystals, several recent studies have been devoted to understanding the origin of enhanced emission sensitization from Si-rich oxide samples annealed at low temperatures (215 mA cm−2

10 kHz

750 nm

6V

–

–

~730 nm

800 nm

5–14 V

–

–

–

Stability

–

–

–

–

–

QE = 19% (single nc-Si)

–

–

–

Stable

–

Very stable

Stable

–

–

EQE < 0.02% Very stable EQE = 10−5% 2000

–

–

Efficiency

1 A cm−2

Bipolar injection Voltage-tunable: 800 nm–600 nm

800 nm

Impact excitation

600 nm

650 nm

5–15 V; 25–200 mA >8 V

–

Voltage, Current >4 V

Si+implantation; annealing Si+implantation; annealing Sol-gel; Si+implantation; annealing CVD; thermal oxidation

Si(p)/Si-rich SiO2/ Au Al/Si(p)/SiO2 + nc-Si/Au Si(p)/SiO2 + nc-Si/ poly-Si (n) Si(n)/SiO2 + nc-Si/ ITO Al/Si(p)/SiO2/nc-Si (single layer)/ SiO2/Al Si(p+)/SiO2 + nc-Si/ Metal

Injection

Bipolar injection

nc-Si synthesis

Sputtering; annealing

Structure

Table 6 Some characteristics of most devices discussed in Sect. 4, about LEDs based on Si-rich SiO2 Year

2005

2005

2005

2005

2004

2002 2003 2004 2003

2000

[133]

1999

1997

1995

Ref.

[138]

[138]

[148]

[135]

[136, 137] [131]

[140– 143]

[147]

[134]

[132]

[139]

2. NANOCRYSTALLINE SI EL DEVICES 47

48

GELLOZ AND KOSHIDA

The PL external QE efficiency of these structures was typically quite low (about 0.1–0.3%) until recently, when Wang et al. [1] reported an external QE of 12%. The trick used by the authors to get such a high value is to set the substrate temperature to RT during the film deposition, instead of heating it to above 200°C as usually accepted in PECVD. As a result, the Si nanocrystals were nearly strain-free and the Si–SiO2 interface was sharp. The quality of the interface between the Si nanocrystals and the surrounding matrix is indeed critical to get high luminescence efficiencies. This fact is also illustrated by the very high PL external QE (23%) obtained by Gelloz et al. [2, 3] in PS using HWA (see Sect. 2.6). In addition to the passivation role, the oxide surrounding the Si nanocrystals also plays a major role in the luminescence via interface states. On one hand, this is a major problem when one wants to obtain blue emission from the Si nanocrystals themselves since levels inside the gap induce red emission instead of blue [11]. On the other hand, these levels could be extremely important and desirable since they may be crucial to the observation of optical gain [118]. The PL [127–130] and EL[131] of single Si nanocrystals surrounded by SiO2 have been studied. The best PL quantum efficiency reached 35% (19% for the EL), which is encouraging for the application in EL devices. However, the blinking, and the long radiative lifetime (0.1 ms), consequence of the indirect band-gap structure, could be a major limitation for interconnect purposes, though display applications could still be considered. The EL introduces an addition challenge: efficient injection of the charge carriers into Si nanocrystals. Electron–hole pairs are usually generated either by bipolar injection from both electrodes of the diode or by impact excitation. In the latter case, only electrons flow through the device and holes are generated by impact processes. 4.2. Si-Implanted Si Oxide The approach consisting in Si implantation in a matrix such as SiO2 has lead to several reports. Among these, Song et al. [132] have studied the EL of Si+ implanted thermally formed SiO2. The oxide layer was 34 nm thick. Si was implanted (25 keV, 1016 cm−2) mainly in the bottom half of the oxide layer. Both PL and EL show three bands, around 470, 600, and 730 nm. However, the 600-nm band is the strongest in EL whereas it is weaker in PL. The relative contributions from different luminescence bands to EL depend on the annealing conditions. From the study of different annealing conditions, the authors conclude that the 470-nm band needs too high excitation energy to be electrically excitable. The 730-nm band depends on the existence of Si nanocrystals, which are not numerously produced until high temperature annealing. The 600-nm band is easy to excite electrically due to its low energy. Moreover, the presence of Si nanocrystals improves the EL from oxygen-related defects. Luterova et al. [133] have observed red EL from Si+-implanted sol–gel-derived SiO2 films on n-type Si. The oxide layer was 250 nm thick. Four different energies and ion doses have been used for the Si implantation in order to get a flat ion profile

2. NANOCRYSTALLINE SI EL DEVICES

49

across the oxide layer. Annealing was performed at 1,100°C for 1 h. EL was observed from 5 V and 1 A cm−2. The device showed no rectifying behavior but the EL could be obtained only at one bias polarity. EL at 295 K was emitted only from a small number of bright spots. The EL spectrum showed only a peak at 750 nm (attributed to Si nanocrystals) whereas the PL showed the same peak plus another one in the blue range attributed to the presence of defects. The EL was attributed to electron–hole recombination in Si nanocrystals as a result of carrier injection. Si nanocrystals are believed to create several conductive percolation paths across the oxide layer. The low efficiency (10−5%) was attributed to shunting current paths due to defects. The EL decay is 8 μs. Lalic et al. [134] have studied the fabrication and the electroluminescent properties of Si nanocrystals in SiO2. The Si nanocrystals were generated by ion implantation and further annealing at 1,100°C for 1 h. Both the Si dose and SiO2 thickness have been varied. The oxide thickness has been varied from 12 to 100 nm. The thermal oxide was grown on a p-type Si substrate. Then a 210-nm thick a-Si layer was deposited for use as a protective and contacting layer as well as to adjust the position of the implantation profile peak. A 160-nm thick highly phosphorous-doped poly-Si layer was then deposited and used to enhance the carrier injection into the Si nanocrystals. EL was observed from LEDs with oxide thickness less than 18 nm for bias voltages above 8 V. The EL spectrum shows a peak at about 1.55 eV. The EL efficiency is found more than one order of magnitude lower than that of their previously reported LED based on PS [42–44], which should be less than 2 × 10−2%. However, the EL of the new device shows no degradation (due to Si nanocrystal passivation by SiO2). This is very much better than the results they obtained with PS. Higher implantation doses lead to a higher level of interconnection between Si nanocrystals. More interconnected structures induce shorter EL time constants, larger leakage currents, and lower efficiency. The same group has studied the PL [127–130] and EL [131] of single Si nanocrystals in the same kind of devices. The EL was observed at voltages above 5 V. Its mechanism was impact excitation of electron–hole pairs in Si nanocrystals. The EL was stable and visible by naked eye. The best EL quantum efficiency was 19% for a single quantum dot. The effect of boron or phosphorous dopant incorporation in the structure has been studied [135]. Si+, P+, or B+ were implanted into p-type thermally oxidized Si. The samples were then annealed at 1,000–1,100°C. The EL was excited by impact by hot electrons. It was always improved by the doping, up to ten times. For many devices in this category, the injection mechanism is impact excitation. However, this mechanism leads to device degradation upon prolonged operation. The ideal injection scheme would involve bipolar injection from both electrodes of the diode. Such injection mechanism has been realized using a p+-Si/ SiO2 + nc-Si/Al device structure [136, 137]. Forty nanometers of thick SiO2 layers were twice Si-implanted in order to obtain a planar profile of the excess Si nanocrystals in the oxide. The SiO2 layers were then etched at different depth, from 10 to 30 nm. Finally the samples were annealed at 1,110°C. The current was found not thermally activated and the Fowler–Nordheim regime was not observed for electric fields below 5 MV cm−1. The transport mechanism was described as hopping, with

50

GELLOZ AND KOSHIDA V

OB18 (15% Si excess) PL Reference X4

Normalized luminescente intensity

1

PL

Al (15 nm) Implanted SiO2 (15nm)

EL (Eox=+4,7MV/cm)

p-type Si substrate

e− Vg < 0

hw

h+

1,2 1,4 1,6 1,8 2,0 2,2 2,4 2,6 2,8 3,0 Energy (eV) FIG. 9. PL and EL spectra for 15-nm thick implanted-oxide LED. The PL of a nonimplanted sample is shown for comparison. Reprinted from [137] © (2002) with permission from Elsevier.

an average trap distance between 1.4 and 1.9 nm. Figure 9 shows a schematic representation of the device, the EL model, and spectra of EL and PL. Stable red EL was observed at RT. Since the EL and PL exhibit the same energy peak, they relate to the same origin, recombination of carriers trapped by the surface states of the Si nanocrystals. The higher energy part of the EL spectrum was attributed to SiO2 radiative defects. Very recently, Lin et al. [138] studied the effect of the defects in SiOx on the EL characteristics. They built two devices, both consisting in Al/n-Si/SiO2 + nc-Si/ Ag structure. One included a multienergy Si-implanted SiO2 layer, whereas the other one included a substoichiometric SiOx layer. Both layers were annealed. The Si-implanted layer was including many defects which induced blue and green EL bands in addition to the conventional red band due to Si nanocrystals, leading to white EL. In this device, the threshold voltage, current, and electric field were 3.3 V, 0.15 A cm−2, and 66 kV cm−1, respectively. The transport mechanism was attributed in part to hopping and enhanced Fowler–Nordheim tunneling, and the EL mechanism to carrier injection and impact excitation of different defects in the oxide layer. The EL was only observed under reverse bias. Maximum optical output was 120 nW at 15 V. The device including the annealed SiOx layer exhibited a much higher voltage threshold (86 V) than the previous device. This was attributed to fewer nonradiative and irradiated defects within the PECVD-grown Si-rich SiOx material. The carriers in nc-Si were neither thermally activated nor field-enhanced Fowler–Nordheim tunneling injected, but possibly assisted by direct tunneling between Si nanocrystals. The device was emitting near-infrared light (600–800 nm).


51

4.3. Annealed Substoichiometric Si Oxide Qin et al. [139] have studied the visible EL from Au/extra thin Si-rich SiO2/p-type Si structures. The oxide thickness was 4 nm. It was grown by magnetron sputtering. The EL was observed at voltage above 4 V. The EL showed a peak at 1.9 eV with a FWHM of 0.5 eV when the Si-rich oxide film was not annealed. Annealing at 800°C induces a widening of the EL spectrum and the appearance of several shoulders at about 1.5, 2.2, and 2.4 eV. Furthermore, the EL peak energy blue shifts with increasing forward bias. The luminescence is believed to originate from several types of luminescent centers in the Si-rich Si oxide film. One group has produced several reports recently showing promising results of EL from Si quantum dots embedded in the oxide of MOS structures [140–143]. A 25-nm thick substoichiometric SiOx (x < 2) film was deposited on a p+-type Si substrate by PE-CVD and annealed at 1,100°C for 1 h in N2 in order to induce separation of the Si and SiO2 phases. The Si nanocrystals thus formed had a mean radius of about 1.0 nm. The excitation cross section of Si nanocrystals under electrical pumping (4.7 × 10−14 cm2) was found two orders of magnitude higher than under optical pumping [140]. This was also the case for Er excitation in their similar device including implanted Er ions [144]. The mechanism responsible for the light emission was the same under both optical and electrical pumping (self-trapped exciton recombination at a Si=O interfacial state). The charge carrier transport was Fowler–Nordheim tunneling and the injection mechanism was attributed to impact processes. Efficient EL was obtained at 4 V and 0.2 mA cm−2. The EL spectrum exhibited a peak at about 900 nm. EL response time could be lowered down to about 25 μs [140]. The effect of the Si concentration in the SiOx layer was studied [143]. Figure 10 (Fig. 4) shows the EL intensity as a function of voltage for devices based on active layers with different Si concentrations. It shows that the threshold for light emission increases by decreasing the Si concentration in the SiOx film. These devices are very stable. 4.4. nc-Si Single Layer Sandwiched Between Two SiO2 Layers Devices including a few nanometer thick amorphous Si layer sandwiched between two SiO2 layers have been investigated [145, 146]. A forward bias p-type Si/SiO2/ a-Si/SiO2/Au[145] and a reverse biased n+-type Si/SiO2/a-Si/SiO2/Au [146] have been studied. The thickness of the a-Si layer has been varied between 0 and 4 nm. The upper and lower SiO2 thicknesses were 3.0 and 1.5 nm, respectively. Room temperature EL is observed at about 5–7 V in the wavelength range from 600 to 700 nm depending on a-Si thickness. In both devices, EL peak intensity and peak wavelength synchronously swing with increasing the a-Si layer thickness [145]. The swing period is consistent with half the de Broglie wavelength of the carriers [146]. The EL is mainly attributed to luminescent centers in the oxide (excited by electrical breakdown), with a minor contribution of the a-Si layer as a result of quantum confinement. Photopoulos et al. [147] studied room- and low-temperature EL in the visible from a single layer of Si nanocrystals in between two thin (5 nm) SiO2 layers. The

52

GELLOZ AND KOSHIDA

FIG. 10. EL intensity at 850 nm as a function of the applied voltage under forward bias conditions for devices characterized by different active layers. Reprinted from [143] © (2004) with permission from Elsevier.

EL was attributed to quantum confinement. The effects of size and size distribution were demonstrated. The EL peak wavelength exhibited a voltage-tunability from the red (800 nm) to the yellow (600 nm). The authors suggest different possible mechanism to explain the voltage tunability of the peak wavelength: selective carrier injection in Si nanocrystals of different sizes, an enhanced Auger recombination rate at high voltages, Coulomb charging, and quantum-confined Stark effect. A new device operation has been proposed recently: field-effect light emission using a floating-gate transistor structure [148]. The gate oxide was the host of the Si nanocrystals. Figure 11 shows the device structure as well as the device operation mechanism. Electrons and holes tunnel sequentially from the channel under the influence of an alternating voltage applied to its gate (6 V). The sequential accumulation of electrons and then holes within the Si nanocrystals on each cycle thereby results in recombination and the emission of light (broad spectrum centered at 750 nm in the report of Walters et al. [148]). This injection scheme presents several advantages compared to the conventional diode structure. The field necessary to produce light is small compared to that in diodes because the carrier tunneling efficiency is governed only by the distance between the nanocrystals and the channel and not by their density or the total matrix thickness. In addition, the degradation of the oxide due to impact processes should be avoided, leading to long life operation. The device of Walters et al. [148] was indeed very stable. Finally, the fabrication techniques are that of conventional electronics, and thus fully compatible with VLSI. There is one negative point that still remains though. The speed of the device is still limited by the long luminescence lifetime of the Si nanocrystals (tens of


53

FIG. 11. Schematic of the field-effect EL mechanism in a Si nanocrystal floating-gate transistor structure. Inset band diagrams depict the relevant tunneling processes. (a–c), The array of Si nanocrystals embedded in the gate oxide of the transistor can be sequentially charged with electrons (a) by Fowler–Nordheim tunneling, and holes (b) via Coulomb field-enhanced Fowler–Nordheim tunneling to prepare excitons that radiatively recombine (c) [148]. Reprinted by permission from Macmillan Publishers Ltd, © (2005).

54

GELLOZ AND KOSHIDA

microseconds) due to their indirect bandgap. As a result, the potential application remains in the display arena rather than interconnects.

5 OTHER SINGLE LAYER NANOSTRUCTURES

The characteristics of a selection of devices discussed in this section can be found in Table 7. 5.1 nc-Si Embedded in SiNx Park et al. [149] have used a silicon nitride film as the host matrix for Si nanodots. Amorphous Si quantum dots were formed in SiNx by PE-CVD. Control of dot size led to red, green, and blue PL. An orange LED was fabricated using Si dots with a mean size of 2.0 nm. The turn-on voltage was below 5 V. The EQE was about 2 × 10−3%. A device also based on Si nanocrystals embedded in a SiNx matrix exhibited a relatively high external QE (1.6%) [5]. This is currently the highest value reported to date for a light-emitting device based on nanocrystalline Si. It is greater than the 1.1% that was earlier reported by Gelloz et al. [4] with a device based on PS. Figure 12 shows a schematic representation of the device as well as the evolution of the current density as a function of the voltage. The solid curve is a fit of the data using a Fowler–Nordheim equation. The EL was orange and was observed at current greater than 1 mA. An emitted power of 2 mW was obtained for a current of 70 mA. The n-type SiC semitransparent layer is crucial to inject electrons while allowing the EL to exit the device. Another configuration has been investigated by Chen et al. [150]. nc-Si/a-SiNx was grown by e-beam evaporation of Si into an inductively coupled plasma of nitrogen. Holes were injected by an ITO electrode whereas electrons were injected by an Ag electrode in one case or a Ca/Ag electrode in another case. The second configuration showed better results. It outperformed the configuration with a simple Ag electrode by increasing the current density, the maximal luminance, and the EL efficiency of the device. The turn-on voltage was 10 V, and the EL efficiency 0.16 Cd A−1. A maximum of 0.25 Cd m−2 was obtained, at 12 V. 5.2 Other Low-Dimensional Si Structures EL from Si nanopillars has been reported by Nassiopoulos et al. [151, 152]. Si nanopillars were fabricated by using deep UV lithography, highly anisotropic Si reactive ion etching, and high-temperature thermal oxidation for further thinning. The pillars (lying on and perpendicular to, the original Si substrate) were below 10 nm in diameter and 0.4–0.6 μm high. The space between pillars was filled with an isolating transparent polymer. The top contact was either gold or ITO. Weak and low efficiency EL peaking at about 675 nm was observed at voltages above 12–14 V. EL was stable for several hours [152]. The potential of visible EL from Si nanocrystals embedded in a-Si:H film has also been investigated. Tong et al. [153] produced such electroluminescent layers by

Bipolar injection

Spin-on doping; SiO2 nanoparticles; thermal diffusion

200–600 mA

7–10 V; 50–500 mA

–

Stimulated emission in ridge waveguide B or P implantation Bipolar injection 10 V; >100 mA cm−2 by tunneling CVD annealing Bipolar injection by 3–20 V; 0.18–12.7 mA F–N tunneling cm−2

Bipolar injection

Sputtering

1,150 nm

790 nm 650 nm

770 nm

Speed

– – –

600 nm

–

1,170 nm 440–500 nm

1,155 nm

–

1,060 nm or red – and blue 1,400 nm

Efficiency

– –

–

EQE = 10−4% EQE < 0.01% –

Hours

–

–

–

EQE = 1.6%

–

EQE = 0.013% in ridge waveguide IQE = 2% – 0.16 Cd A−1 –

IQE = 0.1%

–

–

Ref.

2005 [5]

2005 [161] 2005 [150]

2004 [163]

2002 2002 [159]

2001 [156, 157]

2001 [149]

2001 [160]

1998 [158] 1999 [154]

1997 1998 [155]

1996 [151, 152]

1996 [153]

Stability Year –

–

–

25 kHz EQE =0.02% – QE = 0.1% – EQE = 0.002% –

– –

–

–

–

EQE External quantum efficiency and IQE internal quantum efficiency. Stated voltage and current are the minimum values for EL detection, or the device operation conditions

n+ p diode Ca-Ag/a-SiNx + nc-Si/ ITO Si(p)/SiNx + nc-Si / SiC(n)/ITO

Si(p)/SiO2-doped Si/Metal In/Si(n)/nano-structured Si(p+)/In

Impact excitation

Si(p)/SiNx + nc-Si/NiO Pt/Si(p)/In2O3 + nc-Si/ITO Laser ablation; annealing

EL peak, λ 630 nm and 730 nm 650 nm

5–10 V; 0.7 V; >1 mA

Bipolar injection

–

5–10 V 4.5 V; 60 mA

7–30 V; 1–20 mA

10–40 V

6–22 V

Voltage, Current

Bipolar injection Impact excitation

Si(p)/SiNx + nc-Si/NiAu CVD

Glass/SnO2/nc-Si(p)/Al Ti-Au/Si(p+)/a-Si + nc-Si/Ti-Au AuSb/Si(n)/Si(p+)/Al

Impact excitation

Laser ablation; annealing CVD; anodization a-Si deposition; annealing B implantation

Si(p)/nc-Si/Pt

Bipolar injection

–

CVD

Si(n)/nc-Si/Au

Injection mechanism

Si(n)/Si nano-pillars/ITO Lithography; etching

Nanostructuration

Structure

Table 7 Some characteristics of most devices discussed in Sect. V, about LEDs based on various types of nanostructures excluding Si-rich SiO2


56

GELLOZ AND KOSHIDA

FIG. 12. Current density vs. applied voltage. Open circles and solid line denote the experimental data and the fitted data, respectively. The experimental data are best fitted by the expression for the Fowler–Nordheim tunneling process. The inset shows the schematic of the device. Reprinted with permission from [5] © 2005 American Institute of Physics [DOI: 10.1063/1.1866638].

CVD. The EL spectrum showed two peaks, at about 630–680 nm and 730 nm. EL detection threshold was about 6 V. This value increased when the film conductivity decreased. In addition, the EL intensity increased with the film conductivity. The EL mechanism was not clear. Fujita et al. [154] used an ultrathin a-Si layer containing Si nanocrystals. The device was a TiAu/p+-Si/a-Si + ncSi/TiAu structure. Orange EL could be seen at RT with the naked eye under reverse applied voltages of about 4.0–4.5 V. The EL spectrum included a major peak at 1.9 eV and a minor peak at 2.2 eV. The EL excitation mechanism was attributed to an impact process. One group has investigated the EL from Si nanocrystals prepared by laser ablation [155–157]. In the report of Yoshida et al. [155], the diode structure was Pt/closely packed Si nanocrystals/p-type Si/Pt. EL at 1.66 eV at room temperature was obtained. The EL energy peak was lower than the PL one (2.07 eV). The EL current and voltage threshold (photomultiplier detection) were 1 mA and 7 V, respectively. Detection threshold by the naked eye in the dark were 15 mA and 25 V for the current and voltage, respectively. The active area was 0.031 cm2. The estimated external QE was 10−4%. A strong superlinear dependence of the EL intensity on the current density was attributed to the EL generation mechanism, namely impact ionization by minority hot carriers. The effects of annealing on the structure and the optical properties of the luminescent layers were later reported [156]. A number of new emission bands appeared, which was explained by the enhanced crystallinity after annealing in N2. Annealing in O2 lead to the appearance of a blue EL band attributed to luminescence of neutral oxygen vacancy defects in SiO2. The same group also studied the effect of an In2O3 passivating layer on top of the nc-Si layer [157]. When this layer was deposited without breaking the vacuum, the EL spectrum had a narrow bandwidth of 0.15 eV peaked at 1.17 eV at RT. However, when the nc-Si layer was exposed to air before In2O3 deposition, a broad EL spectrum was obtained


57

(peak: 1.7 eV, bandwidth: 0.46 eV). The visible emission was attributed to various oxide-related emission centers. Toyama et al. [158] have observed EL from a glass/SnO2/p-type Si nanocrystals/ Al structure by applying positive bias voltage to the SnO2 electrode. P-type Si nanocrystals were first deposited onto SnO2-coated glass by PE-CVD. This Si layer is then anodized in HF. This anodization is likely to lead to a porous amorphous Si layer. Si nanocrystals sizes were estimated to be in the range of 3–5 nm. The EL showed a peak at 1.57 eV. The EL onset voltage was about 5 V. The EQE was below 10−2%. The EL was attributed to radiative recombination of electrons injected from the Al electrode and holes in the p-type Si nanocrystal film. The authors suggested that electron injection was a result of a tunneling process at the interface of Si nanocrystals/Al. Osaka et al. [159] reported EL at 1,400 nm from a p-type Si/SiO2-doped Si/Metal diode. SiO2-doped Si was deposited by RF magnetron sputtering technique on p-type Si at a substrate temperature of 400°C. The EL was attributed to hole injection from the substrate followed by optical transition between electron-bound states in the film and injected holes. The EL spectrum was much narrower (FWHM 125 nm) than the PL one (FWHM 400 nm). This behavior was attributed to the hole density of states being much broader than the electron-bound state distribution. The films showed optical absorption in the range 1.4–2.0 eV, comparable to that of undoped a-Si:H films. The SiO2-doped Si films may be useful for photovoltaic applications. 5.3. Confinement Induced by Local Strain or Doping Fluctuations Ng et al. [160] fabricated a device in which the non radiative recombination rate in bulk silicon is reduced as a result of carrier localization. Carrier localization is achieved by a three-dimensional local strain field induced by appropriately produced dislocation loops in the pn junction. These dislocation loops as well as the p part of the junction are produced in two simple steps: boron implantation at a dose of 1 × 1015 cm−2 at an energy of 30 keV, and subsequent annealing in nitrogen atmosphere for 20 min at 1,000°C. The dislocation loops form an array situated in a planar region parallel to, and around 100 nm from, the pn junction. They are about 80–100 nm in diameter and are spaced around 20 nm apart. These loops are said to induce a blocking potential that confines carriers close to the junction region. At 100 mA forward current, the emitted light was 19.8 μW and the external QE was about 2 × 10−2% at room temperature. The device response at room temperature was about 18 μs. At room temperature, the emission spectrum shows a peak at around 1,150 nm. This type of diodes has been studied by other research groups. An internal QE of 2% was reported at 300 K by Kittler et al. [161], whereas an external power efficiency of 0.12% was reached by Sun et al. [162]. An interesting feature of these diodes is that the EL and PL efficiencies increase with the temperature. This unusual property has been explained by thermal activation of carrier from bound excitons having low recombination rates [161, 162]. Enhanced EL from bulk Si p+n junctions has also been obtained by Chen et al. [163] by using spatial confinement of carriers induced by doping fluctuations. The

58

GELLOZ AND KOSHIDA

carrier localization nanostructure was made using nonuniform diffusion of dopant though SiO2 nanoparticles. EL peaked at 1,150 nm was measured at RT, with a maximum internal QE of about 0.1%. The incorporation of the pn junction into a ridge waveguide led to stimulated emission at 1,214 and 1,217 nm. The different emission wavelengths were attributed to the free and bound excitons.

6. SUPERLATTICES

Most devices discussed in this section have their main properties listed in Table 8. 6.1. Superlattices Based on SiOx Layers The first LEDs based on Si–SiO2 superlattices were fabricated by molecular beam epitaxy [164]. The basic period of the superlattice was formed by a monolayer of adsorbed oxygen and a thin deposited single crystal Si layer. Both EL and PL were observed. The luminescence was attributed to quantum confinement as well as Si/O binding regions. The EL was stable for more than a year. Poly-Si/SiO2 superlattices were formed by PE-CVD [165, 166]. The thickness of the Si layer was varied either from 1 to 3 nm (up to 60 periods) or from 75 to 150 nm (up to 4 periods) [165]. The oxide layer was around 1 or 2 nm. All structures were containing Si nanodots. At low current injection, the emission was red and the quantum efficiency was low (about 10−3%). The author latter suggested that this EL originates from defect levels on the oxide near the interface [166]. At larger injection current, the EL intensity was superlinear with respect to the current density and a blue shift occurred together with a narrowing of the FWHM down to about 5 nm. These phenomena are consistent with plasma emission in the intergrain regions. Nanocrystalline Si/SiO2 superlattices have been fabricated by alternate sequences of LP-CVD of thin Si layers and high temperature thermal oxidation [167]. The initially amorphous Si films were crystallized during the oxidation step used to make to top oxide layer. Multilayers with five or ten periods were fabricated, with nc-Si thickness between 1.5 and 5 nm, and SiO2 thickness between 5 and 101 nm. The EL spectrum showed several peaks at 550, 650, and 750 nm. Gaburro et al. [168] have also fabricated light-emitting Si/SiO2 superlattices by LP-CVD. The Si and SiO2 thicknesses were 2 and 5 nm, respectively. The fabrication process was CMOS compatible. The PL band shows a peak at 800 nm due to quantum confinement, whereas the EL shows two bands. One band in the infrared region was attributed to blackbody radiation. The other band was visible and was attributed to coupling of energetic electrons with surface plasmon-polaritons, or to hot-electron relaxation. EL was observed from 2 mA for a contact area of 5 × 10−5 cm2. The external QE was 2 × 10−4%. The same group also reported an external QE of 5 × 10−3% [169]. Heng et al. [170] fabricated a LED based on an amorphous Si/SiO2 superlattice deposited on a p-type Si substrate, by sputtering. The thickness of the a-Si layers was varied in a range 1.0–3.2 nm. The thickness of the SiO2 layer was 1.5 nm in all devices. EL was observed above about 5 V. Every EL spectrum could be decomposed

CVD

Sputtering

CVD

MBE

Sputtering

Si/SiO2

Si/CaF2 a-Si/SiO2

Poly-Si/SiO2

Si/CaF2

a-Si/SiO2

Injection mechanism

Bipolar injection by tunneling

Bipolar injection EL from centers in SiO2 Bipolar injection EL from centers in SiO2 –

–

Bipolar injection Hot-electron relaxation Bipolar injection

>5 V 4 A cm−2 >4 V >100 mA cm−2 5–11 V; 20–250 mA

>5 V

8 V pulsed

Stated voltage and current are the minimum values for EL detection, or the device operation conditions

470 nm After gamma irradiation 620 nm Voltage tunable (950–725 nm)

650 nm

700 nm

550–800 nm

550 nm; 650 nm; 750 nm 700 nm 680 nm; 560 nm

650 nm 650 nm White

Voltage, Current EL peak, λ >7 V >7 V 10 V; 2 mA

Si/SiO2 Sputtering EL from centers in SiO2 12 V pulsed SiO/SiO2, EL at 80 K e-Beam evaporation; – 2–4 V annealing

CVD; laser heating CVD MBE; RTA

a-Si:H/a-SiNx:H Si/SiO2 Si + CaF2/CaF2

Superlattice structure Main techniques

Table 8 Some characteristics of most devices discussed in Sect. 6, about LEDs based on superlattices

– –

–

–

–

–

–

– Low

–

–

–

–

–

– –

–

Hours

–

–

–

– Stable –

[167]

[174] [169] [180, 181]

Ref.

2002 [172] 2005 [173]

2001 [171]

2001 [182, 183]

2001 [166]

2000 [180] 2001 [170]

1999 1999 1999 2000 2000

Efficiency Stability Year

– Low >1 MHz 0.005% – –

Speed


60

GELLOZ AND KOSHIDA

into two Gaussian bands with peak energies of 1.82 and 2.22 eV. The EL intensity and current swings synchronously with increasing the Si layer thickness with a period being consistent with half the De Broglie wavelength of the carriers. The authors had already observed the same behavior with using only a single period instead of a superlattice [145, 146]. They attribute the EL emission to defect centers rather than levels in quantum dots. Ma [171] has studied the effects of gamma irradiation on the EL from Au/a-Si/ SiO2 superlattices/p-type structures. Different Si thicknesses were used. The EL peak was at 650 nm. After gamma irradiation, the EL peak intensity increased 2.5 times. Moreover, a new 470 nm blue peak emerged from the EL spectra. The EL was visible by naked eye. Its mechanism was attributed to the presence of luminescence centers in SiO2 rather than to the Si nanostructure. Averboukh et al. [172] have investigated Si/SiO2 superlattices prepared by magnetron sputtering on p-type Si. Four periods were used (Si: 1.8 nm; SiO2: 1.5 nm). The EL was excited by electrical pulses (12 V, 4 μs). Both the PL and the EL had their peak at about 2.06 eV. The luminescence was attributed to transitions between localized defect states at the Si/SiO2 interface. Jambois et al. [173] have studied SiO/SiO2 superlattices prepared by successive thermal evaporation of a SiO powder and evaporation of fused silica glass. The nc-Si size was controlled by the SiO thickness. The SiO2 thickness was 5 nm whereas the SiO thickness was varied from 2 to 6 nm. A clear continuous shift in PL peak energy was observed as a function of the nc-Si size, from 1.5 eV for 6 nm size to 1.68 eV for 2 nm size. EL was observed at 80 K with a threshold voltage of 2 V. The EL increased as the

FIG. 13. EL spectra for a sample containing nc-Si with a mean size equal to 2.8 nm as a function of the bias voltage. The PL spectrum of the sample is represented in dotted line. Reprinted with permission from [173] © 2005 American Institute of Physics [DOI: 10.1063/1.2034087].

Electroluminescence intensity (arb. un.)

90

3.2V

PL

80 70 3V

60 50

2.8V 40 2.6V

30

2.4V

20

2.2V

10

2V

0 600

700 800 900 Wavelength (nm)


61

voltage was varied from 2 to 4 V, with a blue shift, as seen in Fig. 13. However, beyond 4 V, the EL intensity decreases and was not reproducible any more. The EL mechanism was attributed to both defects in SiO2 and radiative recombination in nc-Si. 6.2. Superlattices Based on SiNx or CaF2 Layers In addition to Si–SiO2 superlattices, a-Si:H/a-SiNx:H multiquantum well structures have been studied for their EL properties [174]. The layers were deposited by PE-CVD, and subsequently annealed with an KrF excimer laser. The /a-SiNx:H layer was either 3 nm or 10 nm and the a-Si:H layer was varied from 2 to 4 nm. The LED structure was semitransparent electrode/crystallized a-Si:H/a-SiNx:H multiquantum wells/crystallized n+ – a-Si:H/SiO2/Si or quartz substrates. The EL spectrum showed multiple peaks around 600 and 700 nm. The onset of visible EL was 7 V in the best case. The EL mechanism was attributed to carrier injection into nanosized Si crystallites in the multiquantum wells, and radiative recombination via Si quantum well states. Another configuration, including CaF2/Si superlattices, has been investigated. PL [175–177] and EL [178–183] from these structures have been reported. A theoretical report attributes the EL emission from these structures to electron and hole tunneling through the CaF2 barriers, occurring via Wentzel–Kramers–Brillouin mechanism [179]. Maruyama et al. [181] studied the EL of such superlattices on p-type Si. The superlattice was grown by molecular beam epitaxy and was followed by a rapid thermal annealing treatment. The EL was white. The EL spectrum is such that the emission increases from below 400 nm to more than 700 nm, whereas the PL has a peak at about 575 nm. The authors published some improvements 1 year later [180]. The electrical transport in these superlattices has been studied [183]. One hundred periods were used. The Si thickness was ranging from 1.2 to 1.6 nm, and the CaF2 thickness was below 1 nm. At voltages higher than 4 V (both under forward and reverse conditions), a Poole–Frenkel-type mechanism accounted for the observed electric-field-assisted conduction through the layers. The same authors found that the EL spectra are slightly current tunable [182]. This was attributed to Auger quenching of the luminescence and size-dependent carrier injection.

7.

EL FROM RARE EARTH-DOPED SI NANOCLUSTERS

The main properties of most devices discussed in this section can be found in Table 9. The Er luminescence is greatly enhanced when incorporated into an SiO2 matrix containing Si nanocrystals [184, 185]. Nonradiative de-excitation may be reduced due to enhanced localization. The emitting Er ions are located in the SiO2 matrix or at the Si nanocrystal–SiO2 interface [185]. The Si nanocrystals act as efficient sensitizers for the rare-earth ions. The coupling between Si nanocrystals and Er is indeed very strong. Transfer of excitation from Si nanocrystals to neighboring rare-earth ions is very effective.

100 h 100 h Stable – 100 h Stable – –

IQE = 10% IQE = 3% 1% – EQE = 10% EQE = 1% EQE = 10% EQE = 0.1%

– – 1.4 kHz 1.15 kHz 333 Hz – – –

Ref.

2001 2001 2002 2003 2003 2003 2003 2003

[188] [188] [144] [189] [190] [190] [190] [190]

1997 [186] 1999 [187]

Stability Year

Er: 1.54 μm Tb: 540 nm Er: 1.54 μm Er: 1.54 μm Er: 1.54 μm Er: 1.54 μm Tb: 540 nm Yb: 980 nm

−3

Efficiency

10 V; >1 A cm >18 V; >1.4 mA

−2

Ion incorporation Injection mechanism Voltage, Current

Al/Si(p)/Si-rich SiO2:Er/poly-Si(n)/Al Er Electroplating Impact excitation Al/Si(p)/Si-rich SiO2:Er/poly-Si(n)/Au Er Electroplating Impact excitation (reverse bias) Er Implantation Impact excitation Si(p)/SiOx + nc-Si:Er/Metal Tb Implantation Impact excitation Si(p)/SiOx + nc-Si:Tb /Metal Er Implantation Impact excitation Si(p)/SiOx + nc-Si:Er/Metal Er Implantation – Si(p+)/SiOx + nc-Si:Er/Metal Er Implantation Impact excitation Si(p+)/SiOxi:Er/Metal Er Implantation Impact excitation Si(p+)/SiOx + nc-Si:Er/Metal Tb Implantation Impact excitation Si(p+)/SiOx:Tb/Metal Yb Implantation Impact excitation Si(p+)/SiOx:Yb/Metal

Device structure

Table 9 Some characteristics of most devices discussed in Sect. 7, about LEDs based on rare-earth doped Si nanostructures

62 GELLOZ AND KOSHIDA


63

Tsybescov et al. [186] have obtained room temperature PL and EL from so-called Er-doped silicon-rich silicon oxide. PS made from p+ type Si was the starting material. PS was first doped by Er ions by electroplating and later converted to silicon-rich silicon oxide by partial thermal oxidation at 900°C. The LED structure is a n–i–p bipolar device with a 350-nm thick n-type poly-Si top contact, a 0.5 μm Er-doped silicon-rich silicon oxide, and a p-type c-Si substrate. The EL was detected under forward bias above 10 V and current density near 1 A cm−2. The low efficiency (500 nm) when the forward bias exceeded 6 V. The intensity of the light (800 nm) increased with the forward current while an important increase of the visible light was obtained with the number of layer pairs. The origin of the EL in these structures was not well identified and it was believed that the lack of layer formation in the SLs was responsible for the light emission. The hot-electron mechanism (hot-electron relaxation in the substrate) was assigned to the EL origin in SLs deposited by LPCVD [81]. This assumption was supported by the comparison of EL vs. current and voltage characteristics. A high current was necessary to reach a fixed level of EL intensity, which suggests that the breakdown opens parasitic conduction channels, parallel to the electroluminescent

3. SURFACE AND SUPERLATTICE

89

ones. The proposed model based on hot-electron relaxation rather than electron– hole recombination was also supported by the observed low decay time constant of the EL (£0.7 ms). In fact, in Si nanostructures, electron–hole recombination, which gives rise to visible light emission at room temperature, is expected to decay with the time constant of the order of 10–100 ms [134]. A thickness and annealing temperature dependence of the PL and EL peak position was reported for a-Si:H/SiO2 grown using PECVD technique [55]. In contrary to the previous report [81], the EL spectrum shape was independent from current density, and the integrated intensity was proportional to current. The difference was attributed to thick SiO2 sublayer used in the present work that removes the local SiO2 breakdown and provides a homogeneous carrier transport through the SL. The luminescence mechanism was interpreted in terms of quantum and spatial confinement of carriers.

6. OPTICAL PROPERTIES OF RARE-EARTH DOPED SILICON NANOSTRUCTURES

Since the first demonstration of 1.54 mm Er3+ luminescence by Ennen et al. [135], erbium doping of silicon has been studied intensively as a promising way to realize silicon-based integrated optoelectronics [136]. Several approaches have been proposed to combine Er and Si technology [136]. Direct Er implantation into bulk crystalline silicon results in efficient Er luminescence at 5 K, but a severe PL quenching takes place when the temperature was raised to room temperature [137]. Another approach to overcome the bandgap limitation of silicon is to embed rareearth elements within silicon nanostructures and to exploit the QCE to modify the electronic structure of semiconductor hosts in such a way as to greatly enhance the radiative efficiency of the rare-earth dopant. In this part, a special focus is given on studies regarding efficient luminescence from rare-earth doped silicon microcavities and superlattices [138, 139]. 6.1. Silicon Resonating Quantum Structures By placing the erbium-doped silicon active layer within a microcavity, radiative transition probabilities may be greatly increased and thus an enhanced and tunable emission from erbium can be obtained [140]. The ability to control the emission from erbium was demonstrated by ion implantation of erbium in Si/SiO2 Fabry– Pérot microcavities prepared by radio frequency (RF)-magnetron sputtering [141, 142]. The erbium was incorporated in the SiO2 active regions within the microcavity. It was found that the cavity strongly affects the coupling of the optically excited Er3+ to the radiative and waveguiding modes of the system. Erbium can be introduced in PSi microcavities using electrochemical doping [143, 144]. The structures consist of two highly reflecting PSi Bragg reflectors sandwiching an active layer. The cavities are doped by cathodic electromigration of erbium ions into the PSi matrix, and the infiltrated erbium ions are activated by thermal annealing in oxygen or nitrogen to activate the erbium luminescence. Figure 4 displays a SEM image of

90

BOUKHERROUB

FIG. 4. Cross-sectional SEM micrograph of an erbium-doped porous silicon (PSi) microcavity activated at 900°C in oxygen and densified at 1,100°C in nitrogen. The top and bottom Bragg reflectors contain six pairs of low (43%) and high (62%) porosity layers sandwiching an active layer (68%). The porosities apply to the freshly anodized layers before oxidation. The first two top layers of the microcavity are difficult to see due to the way the sample was cleaved (from [143]).

an erbium-doped PSi microcavity after activation at 900°C in oxygen and densification at 1,100°C in nitrogen. The high and low porosity layers of the quarter-wave mirrors are observed by the dark and light regions, respectively. The thickness of the low and high porosity layers is ~200 nm and that of the active layer is ~800 nm. The periodic nature of the Bragg cavity constitutes a one-dimensional photonic bandgap structure, and yields enhanced and directional erbium emission. Emission through the Bragg stack is enhanced up to 38 times than that in plane, from the edge of the structure (Fig. 5), and is highly directional with a 20° emission cone around the normal axis [143]. Furthermore, the ability to tailor the cavity structure enables to tune the erbium emission to regions where the natural erbium emission is very weak. Similar multilayer PSi microcavities into which Er ions were doped electrochemically and activated through thermal annealing at 900°C under a nitrogen atmosphere were reported by Zhou et al. [145, 146]. The microcavity structure yielded a narrow PL at 1.436 mm with a full width at half maximum of ~6 nm. However, the observed luminescence from the resulting Bragg mirrors was not attributed to only erbium ions present in the cavity layer (active region), but occurred throughout the whole structure. The optical characteristics of a Fabry– Pérot microcavity with Er-doped hydrogenated amorphous silicon active layer were studied in detail by Sel’kin et al. [147, 148]. The multiple quarter-wave stack distributed Bragg reflectors and active layer of the microcavity were produced using PECVD technique. The erbium doping was realized during the deposition using a metal organic precursor. A PL intensity enhancement by two order of


91

FIG. 5. Erbium emission from a microcavity (a) taken at normal incidence and (b) from a cleaved edge. The emission from the edge is the normal erbium spectrum, while the emission from the top is enhanced by 38 times and centered at 1,562 nm as a result of modification from the cavity resonance. The inset shows a schematic of the collection directions (from [143]).

magnitude and selective narrowing of the erbium emission line at 1.54 mm were observed as compared to a single amorphous layer doped with erbium ions. The optical properties of Er3+ in Si/SiO2 microcavities were studied as a function of the degree of light confinement and Er3+ concentration [149–151]. In weak light confining microcavities, the Er3+ emission was strongly enhanced while in a strong light confining Si/SiO2 microcavity, Er3+-photon coupling with a spectral splitting of 0.1 THz around the erbium emission frequency was observed. 6.2. Si/SiO2 Superlattices Following these studies, the PL properties of erbium-doped Si/SiO2 superlattices were investigated in detail by Shin et al. [152]. Two superlattices films, one with erbium in Si layers (Si/Er) and the other with Er3+ in SiO2 layers (SiO2:Er), were synthesized using electron cyclotron resonance plasma-enhanced chemical vapor deposition of SiH4 and O2 with cosputtering of erbium followed by rapid thermal annealing. The resulting nanostructures display a good periodicity and well-defined interfaces and planar interfaces. The Si and SiO2 layer thicknesses are 5 nm and 9 nm, respectively, for the Si:Er film, and 4 nm and 8 nm, respectively, for the SiO2:Er film (Fig. 6). It is important to note that these thicknesses correspond to ~l/100 for the Er3+ luminescence wavelength and thus no resonant-cavity effect was observed. The SiO2:Eu films showed a PL peak centered at 1.533 mm while the Si:Eu displayed a PL peak at 1.536 mm. Furthermore, it was found that the Er3+ luminescence from superlattice films is independent of excitation wavelength and less temperature quenching was observed when erbium was in the SiO2 layer.

92

BOUKHERROUB

FIG. 6. Transmission electron microscope images of Si/SiO2 superlattices. On the right is the schematic drawing showing the composition of the layers (from [152]).

Next, the authors have studied Er3+ PL properties of erbium-doped Si/SiO2 superlattices by doping erbium into the SiO2 layers only and by depositing buffer layers of pure SiO2 between the erbium-doped SiO2 layers and the Si layers [153]. The superlattice structure consisted of a period of 30 layers of SiO2 and Si of thicknesses 3 nm and 4 nm, respectively, and a pure SiO2 buffer layer of thickness ~1.5 nm. The concentration of erbium was estimated using RBS to be 0.1 at% and thermal annealing of the structure did not induce any diffusion of Er atoms in the buffer layers. The authors demonstrated that Er3+ luminescence can be enhanced by a factor of 3, as the buffer layer thickness was increased, and the presence of the buffer layers suppressed the temperature PL quenching. The PL enhancement was explained in terms of asymmetry between the carrier-mediated excitation and de-excitation mechanisms of Er3+ and the suppression of de-excitation mechanisms using buffer layers during Er-carrier interactions. Furthermore, the authors have investigated Er3+ luminescence properties of erbium-doped Si/SiO2 superlattices with subnanometer-thin silicon layers where only the SiO2 layers were doped with erbium [154]. A Si/SiO2 superlattice of 20 periods with a fixed 9.6-nm SiO2 layer thickness and a variable Si layer thickness from 0.6 to 3.6 nm was prepared as previously [152]. The Er concentration in the SiO2 layers was estimated using RBS to be 0.5 at%. All the deposited films displayed the typical Er3+ luminescence around 1.54 mm due to the 4I13/2®4I15/2 intra-4f transition of Er3+. The erbium luminescence intensity increases monotonically more than an order of magnitude as the Si layer thickness decreases. All samples showed a similar PL intensity dependence with temperature. The Er3+ PL intensity decreased by ~50% as the temperature was raised


93

FIG. 7. Bright-field cross section TEM image of the SL with Er-doped SiO2 layer thickness of 2.5 nm after annealing. The thin, dark bands are a-Si layers and gray bands are SiO2 layers. On the right is a schematic drawing showing the composition of the layers (from [155]).

from 25 K to room temperature. Moreover, the excitation rate of Er3+ increased from 10 to 30 s−1 as the Si layer thickness decreased from 0.8 to 0.6 nm. Therefore, it is believed that only carriers generated near the Si/SiO2 interfaces are likely to contribute to Er3+ excitation significantly and suggests that the PL from erbium-doped nanostructures is dominated by Er3+ ions located near the Si/SiO2 interface. Interestingly, for understanding the physical mechanisms underlying the Er3+carrier interactions including the characteristic interaction distance in Er-doped a-Si/ SiO2 superlattices, Shin et al. [155] have synthesized a superlattice thin films consisting of 12 periods of a-Si/SiO2:Er/SiO2/SiO2:Er layers with different Er concentrations (Fig. 7). The thickness of a-Si layers was fixed at 1.2 nm while the thicknesses of the SiO2:Er (erbium-doped SiO2) and SiO2 (pure SiO2) layers were varied such the total thickness of SiO2 layer remains constant (9.5 nm). Figure 8 displays the changes of the Er3+ PL intensity from the sample with 0.27 at% Er (and 0.1 at% Er in the inset) as a function of SiO2:Er layer thickness. For both samples, the Er3+ PL intensity increases with increasing SiO2:Er layer thickness d, but saturates after 1.5 nm. However, the Er3+ luminescence lifetime was found independent of the SiO2:Er thickness. The increase of the Er3+ PL intensity with increasing SiO2:Er thickness was assigned to an increase of the number of available Er3+ ions in the matrix. The experimental results are well described by exponentially decaying carrier–Er interactions with a characteristic interaction distance of 0.5 ± 0.1 nm [155]. Another approach was adopted by Zacharias et al. [99, 156, 157] to prepare erbium-doped Si/SiO2 superlattices. The doping was carried out by direct implantation with various erbium doses (ranging from 1 × 1015 to 5 × 1016 cm−2). To prevent and limit implantation damage of amorphous Si/SiO2 lattice containing 15 periods of a-Si/a-SiO2 (10/3 nm) a top oxide layer of 80-nm thickness was deposited by PECVD. The resulting structures showed an enhanced room temperature PL at 1.54 mm compared to an amorphous SiO2 film implanted with the same erbium dose. Thermal annealing at 800°C led to silicon crystallization (formation of silicon nanocrystals with an average size of 5.7 nm) and room temperature luminescence

94

BOUKHERROUB

FIG. 8. The dependence of the Er3+ peak PL intensities on the SiO2:Er layer thickness in Er-doped a-Si/ SiO2 superlattices. The symbols are experimental data and the lines are the results of fits using different carrier–Er3+ interaction mechanisms. The inset shows the dependence of the Er3+ peak PL intensities on the SiO2:Er layer thickness in Er-doped a-Si/SiO2 superlattices containing 0.1 at% Er and the line is the result of fit (from [155]).

increases. These results confirm the effect of Si nanocrystals in the vicinity of the Er3+ center on the PL intensity. Furthermore, the PL intensity at 1.54 mm decreases with increasing the Eu content of the films, which is related to enhanced film damage. Another interesting feature observed in this study is the weak temperature quenching of the PL intensity from 7 to 300 K. Furthermore, the same authors have investigated the effect of size-controlled silicon nanocrystals on erbium luminescence from erbium-doped nanocrystalline Si/ SiO2 and SiO/SiO2 superlattice structures after thermal annealing [67]. Amorphous Si/SiO2 superlattices were prepared by RF sputtering and plasma oxidation. The Si layer thickness varies between 2.2 and 19 nm. Amorphous SiO/SiO2 superlattices were obtained by reactive evaporation of SiO and SiO2 alternately. The SiO layer thickness was varied between less than 1 and 3 nm. After thermal annealing, the Si/ SiO2 superlattices showed polycrystalline-like Si layers with a very weak defectrelated red room temperature luminescence with main maxima at 650 and 750 nm. There was no evident correlation between Si layer thickness and PL emission wavelength or intensity. However, SiO/SiO2 superlattices exhibited Si nanocrystals separation after annealing and a very strong red room temperature luminescence with a good correlation between crystal size and PL peak position. After Er doping, Si/SiO2 displayed a Er3+ luminescence at 1.54 mm with weak intensity, which is independent of Si layer thickness. However, SiO/SiO2 samples showed a 25 times enhanced Er3+ PL intensity. This behavior was attributed to the difference in the structure and the composition of the Si/SiO2 and SiO/SiO2 superlattices after thermal annealing.


95

The presence of separated and isolated nanocrystals in the latter due to thermalinduced phase separation is the key parameter for Er PL enhancement. The Er PL enhancement was studied in detail as a function of implantation dose and Si nanocrystals size [158, 159]. Dense arrays of silicon nanocrystals were produced as previously by using the Si/SiO2 superlattice approach. It was demonstrated that the energy of optically excited the silicon nanocrystals can be completely transferred to the Er3+ ions due to the Förster process. The high PL emission intensity of the Er3+ ions increased for higher photon energy excitation and for smaller nanocrystals sizes and can be explained by a strong coupling between excitons confined in the Si nanocrystals and neighboring Er3+ ions in their upper excited states. The field of rare-earth doped quantum confined structures is rapidly developing and will remain active in the future. It holds promise for potential applications in all-optical memories and optical computing. 6.3. Miscellaneous The effect of swift heavy-ion irradiation (Kr and Pb ions) on the optical properties of Si/SiO2 multilayers has been investigated by Gourbilleau et al. [160] with the aim to control the silicon grain size distribution. Irradiation of the superlattice with Kr or Pb ions with 9 MeV energy followed by thermal annealing at 1,100°C under nitrogen flow led to a PL blue shift. This blue shift was assigned to silicon grain size reduction or a decrease of the interface width between Si and SiO2 along the ion path.

7. OTHER SILICON-BASED SUPERLATTICES

Here, other Si-based semiconductor/insulator superlattices in addition to Si/SiO2 SLs are introduced. 7.1. Si/CaF2 SLs Si/CaF2(111) multiquantum wells were synthesized using molecular beam epitaxy (MBE) in ultra-high vacuum [161–167]. The growth of CaF2 on Si(111) is know to be epitaxial and two dimensional for a wide range of temperatures, because of the small lattice mismatch at room temperature between Si and CaF2 (~0.6%) and the fact that the CaF2 surface energy [sCaF2 (111) = 450 erg cm−2] is almost three times smaller than that of Si [sSi(111) = 1,240 erg cm−2]. The room temperature deposition was preferred to high temperature deposition to overcome silicon island formation occurred at elevated temperatures. Multiquantum wells containing 50–100 periods consist of CaF2 layer thickness held constant at 14 Å and a Si layer thickness varying between 3 and 50 Å (Table 1). Electrical measurements were used for the characterization of Si/CaF2 multiquantum wells (MQWs) of 50 periods with a nominal CaF2 thickness in the range of 1.4–2.8 nm and Si layer thickness of 1.6 nm [163, 164]. The device exhibited capacitive behavior, similar to that of a metal–insulator–semiconductor (MIS)

96

BOUKHERROUB

Table 1 Main growth characteristics of the Si/CaF2 samples. Sample number

Nominal Si thickness (Å)

Nominal CaF2 thickness (Å)

Number of periods

10 15 20

14 14 14

50 100 50

A B C

structure. It was found that the CaF2 barrier thickness plays the key role in vertical carrier transport and the interface between Si and MQWs is characterized by a moderate density of active electronic states. Furthermore, the current–voltage from and current–temperature characteristics of a MBE grown 100 Si/CaF2 periods superlattices with Si and CaF2 layers thicknesses in the range of 1.2–1.6 nm and below 1 nm, respectively, it was suggested that at gate voltages higher than ±4 V a Poole–Frenkeltype mechanism accounts for the carrier transport through the SL [165]. Transport under these conditions was mainly dominated by thermal emission from traps, which can be eliminated by reducing the CaF2 layer thickness (0.56 nm). The dependence of the luminescence from Si/CaF2 MQWs on the Si layer thickness was attributed to quantum confinement of the carriers within the nanocrystalline Si layers [161, 168]. It was demonstrated that samples were luminescent only if the silicon layer thickness was below 2.5 nm. However, the observed increase of the PL upon ageing of the superlattices in air shows the fundamental contribution of the surface on the luminescence properties of the structure. This phenomenon was further demonstrated during ITO deposition on the superlattices [162]. A blue shift of the PL peak accompanied with intensity enhancement was observed. This was attributed to the adsorption of oxygen during ITO deposition, which diffuses through the grain boundaries and reduces the silicon grain size, at the same time passivating the silicon nanocrystallites. These observations were corroborated by first-principle theoretical studies of the dielectric functions of Si/CaF2 SLs [169]. It was concluded that quantum confinement, good surface passivation, and the presence of localized states are key parameters to obtain PL in confined silicon based systems. EL with similar characteristics with PL was also observed from Si/CaF2 superlattices [162, 163, 166]. EL spectra exhibited voltage and laser power tunability, similar to that observed in silicon nanocrystals in SiO2, which was assigned to a combination of Auger quenching of radiative recombination and size-dependent carrier injection or ionization of nanocrystallites. 7.2. Si/SiNx SLs The preparation of a-Si:H/a-SiNx:H superlattices was first demonstrated by Abeles and Tiedje in 1983 [7]. The authors used a PECVD process involving decomposition of silane (SiH4) and silane/ammonia (SiH4/NH3) to deposit alternating layers of a-Si:H and a-SiNx:H. Since then, several research groups used the PECVD (or RF glow discharge) technique to grow a-Si:H/a-SiNx:H SLs on different substrates including glass slides, quartz, sapphire, GaAs, and crystalline silicon under various conditions [129, 170–187]. SiH2Cl2/H2 and SiH2Cl2/NH3 mixtures were also investigated for Si and SiNx layers growth, respectively, using the PECVD deposition technique [188].


97

a-Si/a-SiNx multilayers deposition using electron-gun Si evaporation and periodic electron resonance plasma nitridation was reported by Baribeau et al. [52]. A two-target alternation magnetron sputtering technique was also used for Si/Si oxynitride superlattices preparation [189]. The alternation targets used were n+-type silicon with a resistivity ~10−2 W cm and Si3N4. Amorphous Si/Si oxynitride SLs with Si and Si oxynitride layers thicknesses of 1.4 nm and 2.0 nm, respectively, were synthesized using the technique. The as-deposited Si layers are amorphous. The crystallization of the a-Si layers was obtained upon thermal annealing [52, 184–186] or laser irradiation [129, 179, 181–183, 187]. The crystallinity of the annealed samples and the structural changes induced upon thermal annealing were investigated using Raman spectroscopy in the backscattering geometry. Raman spectrum of as-deposited a-Si:H/a-SiNx:H display a broad peak located at 473 cm−1 due to TO phonons of a-Si sublayers. After thermal annealing at temperatures above 900°C, a sharp peak at 514 cm−1 ascribed to TO mode of nc-Si was observed in the Raman spectrum [186]. As for a-Si/SiO2 SLs, it was found that the crystallization temperature of the a-Si thin layers in a-Si/a-SiNx SLs requires higher temperatures than that of thick a-Si films (about 650°C). Furthermore, FTIR spectroscopy was used to examine the chemical changes occurred in a-Si:H/a-SiNx:H SLs upon thermal annealing [185, 188]. The FTIR spectrum of the as-deposited SLs displays three main bands at 800–900, 2,100– 2,240, and 2,800–3,000 cm−1 due Si–N, Si–H, and N–H stretching modes, respectively. Annealing at 400°C in vacuum or at 450°C in a N2 environment led to partial desorption of hydrogen (decrease of the Si–H and N–H bands intensity). Further annealing at 1,000°C for 70 s caused the disappearance of the H-related bonds. Both quantum confinement and defect-related PL was observed in a-Si/a-SiNx SLs [52, 179, 180, 187]. Steigmer et al. [187] reported that the as-deposited a-Si/a-SiNx SLs displayed two distinct PL spectral features at around 620 and 500 nm. The peak at around 620 nm was found extremely sensitive to the annealing conditions and was assigned to surface state radiative recombination while the peak in the range of 470–550 nm was attributed to QCE. Selective laser crystallization of the a-Si layers of a PECVD grown a-Si/a-SiNx SLs with a-Si layers of different layer thicknesses (2–4 nm) has a big impact on the PL properties. Indeed, a net increase of the PL intensity was observed upon crystallization of the silicon layers [179]. Slow annealing of a-Si/a-SiNx SLs (400°C anneal) resulted in a different behavior [188]. The high energy and strong PL component completely disappeared after 1 h annealing at 400°C. FTIR spectroscopy analysis showed a decrease of the peaks related to the Si–H and N–H stretching modes. Hydrogen effusion upon vacuum annealing creates nonradiative centers, which are responsible for the suppression of the luminescence. A similar PL behavior was reported by Wang et al. [184] for a-Si/a-SiNx superlattices with a-Si layer thickness of 4 nm annealed at temperatures below 800°C. The room-temperature PL peak at 800 nm observed in the as-deposited superlattice disappeared after rapid thermal annealing at 700 or 800°C for 50 s. Under these conditions, Raman analysis revealed that the Si sublayers remained amorphous and the disordered structure was caused most likely by

98

BOUKHERROUB

hydrogen evolution during the thermal treatment. The PL quenching was attributed to an increase of dangling bonds (nonradiative centers) generated during hydrogen evolution. However, the sample annealed at 900°C showed an intense PL peak centered at 710 nm. The PL peak was not sensitive to the annealing time although the PL intensity increased with increasing annealing time. The invariance of the PL peak position with annealing time was connected with the fact that the size of nc-Si was not sensitive to the annealing time. Thus, the PL band at 710 nm originated from nc-Si formed in a-Si:H sublayers. EL spectra from nanocrystalline silicon fabricated by KrF excimer laser annealing of hydrogenated a-Si:H/a-SiNx:H superlattices deposited by PECVD have been measured under different bias conditions [181, 182]. Visible and stable EL with an emission peak wavelength at 700 nm at room temperature was observed from laser-crystallized a-Si:H/a-SiNx:H SLs with a-Si:H and a-SiNx:H sublayer thicknesses of 4.0 and 3.0 nm, respectively. The visible light emission was attributed to radiative recombination within the nanocrystalline crystals. By varying the a-Si:H layer thickness from 4.0 to 1.0 nm while the a-SiN x:H sublayer thickness was kept at 3.5 nm, a significant blue shift of the EL peak from 780 to 600 nm and an enhancement of the luminescence efficiency were observed. This suggests that the EL results from QCE. Bai et al. [189] have studied EL emission from Si/Si:Nx SLs composed of three periods of Si (1.4 nm) and Si:Nx (2.0 nm) layers prepared using the two-target alternation magnetron sputtering technique. The EL spectrum was dominated by a peak around 640 nm, accompanied by a weak peak at 520 nm and a shoulder at 820 nm. The main EL peak at 640 nm was comparable to 660 nm EL peak observed for a semitransparent Au/Si:Nx film/p-Si structure, suggesting that the light emission originates mainly from the luminescence centers in the Si:Nx layers. Furthermore, the EL intensity was 2–4 times higher in the superlattice than that of the Au/Si:Nx film/p-Si structure.

8. CONCLUSIONS

Si/SiO2 nanostructures hold considerable promise from both fundamental and applied research aspects. In this chapter, the different aspects of Si/SiO2 superlattices ranging from fabrication and characterization to potential applications in the field of optoelectronics were reviewed. Several techniques compatible with standard Si wafer processing technology have been developed for SL deposition and both theoretical and experimental approaches have been used to better understand the influence of different parameters on the microstructural and optical properties of the structure. However, there are some limitations to overcome before reaching technologically relevant materials (1) achievement of controlled Si crystallite size, density, and crystallographic orientation is a prerequisite for improving the luminescent properties of the structures, (2) better understanding of the luminescence mechanism in order to prepare highly efficient and stable devices, (3) improving the quality


99

of Si/SiO2 interfaces by removing impurities and achieving an abrupt interface, and (4) good surface passivation. The field of Si/SiO2 superlattices will remain very active for the coming years. This will be driven mainly by fundamental physics questions concerning QCEs, but also by the potential applications of these structures in various fields including light-emitting devices, nonvolatile memories, and nanoscale devices. Acknowledgments The author is grateful for the permissions from Elsevier and AIP for providing useful material in this chapter. The Centre National de la Recherche Scientifique (CNRS) and the Nord-Pas-de Calais region are gratefully acknowledged for financial support.

REFERENCES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36.

S. Furukawa and T. Miyasato, Jpn. J. Appl. Phys. Part 2 27, L2207 (1988). L. T. Canham, Appl. Phys. Lett. 57, 1046 (1990). V. Lehmann and U. Gösele, Appl. Phys. Lett. 58, 856 (1991). A. G. Cullis, L. T. Canham, and P. D. J. Calcott, J. Appl. Phys. 82, 909 (1997). J. Heitmann, F. Müller, M. Zacharias, et al., Adv. Mater. 17, 795 (2005). Y. Peng, X. Zhao, and G. Fu, Chin. Sci. Bull. 47, 1233 (2002). B. Abeles and T. Tiedje, Phys. Rev. Lett. 51, 2003 (1983). T. Zheng and Z. Li, Superlattices Microstruct. 37, 227 (2005). D. J. Lockwood, Phase Trans. 68, 151 (1999). Z. H. Lu, D. J. Lockwood, and J.-M. Baribeau, Nature 378, 258 (1995). D. J. Lockwood, Z. H. Lu, and J.-M. Baribeau, Phys. Rev. Lett. 76, 539 (1996). Z. H. Lu, D. J. Lockwood, and J.-M. Baribeau, Solid State Electron. 40, 197 (1996). D. J. Lockwood, J.-M. Baribeau, M. Noël, et al., Mater. Res. Soc. Symp. Proc. 715, 49 (2002). D. J. Lockwood, J.-M. Baribeau, M. Noël, et al., Solid State Commun. 122, 271 (2002). S. V. Novikov, J. Sinkkonen, O. Kilpelä, et al., J. Cryst. Growth 175/176, 514 (1997). S. V. Novikov, J. Sinkkonen, O. Kilpelä, et al., J. Vac. Sci. Technol. B 15, 1471 (1997). J. Keränen, T. Lepistö, L. Ryen, et al., J. Appl. Phys. 84, 6827 (1998). L. Khriachtchev, M. Rasanen, S. Novikov, et al., J. Appl. Phys. 86, 5601 (1999). L. Khriachtchev, S. Novikov, and O. Kilpela, J. Appl. Phys. 87, 7805 (2000). L. Khriachtchev, O. Kilpelä, S. Karirinne, et al., Appl. Phys. Lett. 78, 323 (2001). L. Khriachtchev, S. Novikov, and J. Lahtinen, J. Appl. Phys. 92, 5856 (2002). L. Khriachtchev, S. Novikov, J. Lahtinen, et al., J. Phys.: Condens. Matter 16, 3219 (2004). L. Khriachtchev, M. Räsänen, and S. Novikov, Appl. Phys. Lett. 88, 013102 (2006). K. Dovidenko, J. C. Lofgren, F. de Freitas, et al., Phys. E 16, 509–516 (2003). R. Tsu, A. Filios, C. Lofgren, et al., Electrochem. Solid-State Lett. 1, 80 (1998). R. Tsu and J. C. Lofgren, J. Cryst. Growth 227–228, 21 (2001). Q. Zhang, A. Filios, J. C. Lofgren, et al., Phys. E 8, 365 (2000). L. Tsybeskov, K. D. Hirschman, S. P. Duttagupta, et al., Phys. Status Solidi (a) 165, 69 (1998). B. T. Sullivan, D. J. Lockwood, H. J. Labbé, et al., Appl. Phys. Lett. 69, 3149 (1996). L. Tsybeskov, K. D. Hirschman, S. P. Duttagupta, et al., Appl. Phys. Lett. 72, 43 (1998). M. Zacharias, L. Tsybeskov, K. D. Hirschman, et al., J. Non-Cryst. Solids 227–230, 1132 (1998). D. J. Lockwood, B. T. Sullivan, and H. J. Labbé, J. Lumin. 80, 75 (1999). L. Tsybeskov, G. F. Grom, M. Jungo, et al., Mater. Sci. Eng. B 69–70, 303 (2000). G. F. Grom, D. J. Lockwood, J. P. McCaffrey, et al., Nature 407, 358 (2000). S. Zollner, A. Konkar, R. Liu, et al., Mater. Res. Soc. Symp. Proc. 638, F5.1.1. (2001). J. Ruan, P. M. Fauchet, L. Dal Negro, et al., Appl. Phys. Lett. 83, 5479 (2003).

100

BOUKHERROUB

37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71.

N.-N. Liu, J.-M. Sun, S.-H. Pan, et al., Opt. Commun. 176, 239 (2000). M. Benyoucef, M. Kuball, J. M. Sun, et al., J. Appl. Phys. 89, 7903 (2001). G. G. Qin, S. Y. Ma, Z. C. Ma, et al., Solid State Commun. 106, 329 (1998). C. L. Heng, B. R. Zhang, Y. P. Qiao, et al., Phys. B 270, 104 (1999). C. L. Heng, Y. Chen, Z. C. Ma, et al., J. Appl. Phys. 89, 5682 (2001). B. Averboukh, R. Huber, K. W. Cheah, et al., J. Appl. Phys. 92, 3564 (2002). S. Y. Ma, G. G. Qin, Y. Y. Wang, et al., Surf. Interface Anal. 32, 98 (2001). F. Gourbilleau, X. Portier, C. Ternon, et al., Appl. Phys. Lett. 78, 3058 (2001). C. Ternon, F. Gourbilleau, X. Portier, et al., Thin Solid Films 419, 5 (2002). K. Nishimoto, D. Sotta, H. A. Durand, et al., J. Lumin. 80, 439 (1999). Y. Kanemitsu, M. Liboshi, and T. Kushida, Appl. Phys. Lett. 76, 2200 (2000). Y. Kanemitsu and T. Kushida, Appl. Phys. Lett. 77, 3550 (2000). S. Nihonyanagi, K. Nishimoto, and Y. Kanemitsu, J. Non-Cryst. Solids 299–302, 1095 (2002). M. Glover and A. Meldrum, Opt. Mater. 27, 977 (2005). O. Jambois, H. Rinnert, X. Devaux, et al., J. Appl. Phys. 98, 046105 (2005). J.-M. Baribeau, D. J. Lockwood, Z. H. Lu, et al., J. Lumin. 80, 417 (1999). F. Iacona, G. Franzo, and C. Spinella, J. Appl. Phys. 87, 1295 (2000). V. Vinciguerra, G. Franzo, F. Priolo, et al., J. Appl. Phys. 87, 8165 (2000). V. Ovchinnikov, A. Malinin, V. Sokolov, et al., Opt. Mater. 17, 103 (2001). O. Ovchinnikov, V. Sokolov, and S. Franssila, Microelectron. J. 34, 579 (2003). Z. Ma, L. Wang, K. Chen, et al., J. Non-Cryst. Solids 299–302, 648 (2002). Z. Ma, K. Chen, X. Huang, et al., J. Appl. Phys. 95, 2448 (2004). J. Mei, Y. Rui, Z. Ma, et al., Solid State Commun. 131, 701 (2004). K. Chen, Z. Ma, X. Huang, et al., J. Non-Cryst. Solids 338–340, 448 (2004). Z. Ma, K. Chen, X. Huang, et al., Appl. Phys. Lett. 85, 516 (2004). H. Zou, L. Wu, X. Huang, et al., Thin Solid Films 491, 212 (2005). D. Cha, J. H. Shin, I.-H. Song, et al., Appl. Phys. Lett. 84, 1287 (2004). H. J. Trodahl, M. Forbes, D. G. A. Nelson, et al., J. Appl. Phys. 62, 1274 (1987). U. Kahler and H. Hofmeister, Opt. Mater. 17, 83 (2001). J. Heitmann, R. Scholz, M. Schmidt, et al., J. Non-Cryst. Solids 299–302, 1075 (2002). M. Schmidt, J. Heitmann, R. Scholz, et al., J. Non-Cryst. Solids 299–302, 678 (2002). M. Zacharias, J. Heitmann, R. Scholz, et al., Appl. Phys. Lett. 80, 661 (2002). L. X. Yi, J. Heitmann, R. Scholz, et al., Appl. Phys. Lett. 81, 4248 (2002). L. X. Yi, J. Heitmann, R. Scholz, et al., J. Phys.: Condens. Matter 15, S2887 (2003). A. G. Nassiopoulou, V. Ioannou-Sougleridis, P. Photopoulos, et al., Phys. Status Solidi (a) 165, 79 (1998). P. Photopoulos, A. G. Nassiopoulou, D. N. Kouvatsos, et al , Mater. Sci. Eng. B 69–70, 345 (2000). P. Photopoulos, A. G. Nassiopoulou, D. N. Kouvatsos, et al., Appl. Phys. Lett. 76, 3588 (2000). D. N. Kouvatsos, V. Ioannou-Sougleridis, and A. G. Nassiopoulou, Mater. Sci. Eng. B 101, 270 (2003). Y. Hirano, F. Sato, N. Saito, et al., J. Non-Cryst. Solids 266–269, 1004 (2000). Y. Hirano, F. Sato, S. Aihara, et al., Appl. Phys. Lett. 79, 2255 (2001). S. Sato, N. Yamamoto, H. Yao, et al., Chem. Phys. Lett. 365, 421 (2002). G. Pucker, P. Bellutti, C. Spinella, et al., J. Appl. Phys. 88, 6044 (2000). G. Pucker, P. Bellutti, M. Cazzanelli, et al., Opt. Mater. 17, 27 (2001). M. Patrini, M. Galli, M. Belotti, et al., J. Appl. Phys. 92, 1816 (2002). Z. Gaburro, G. Pucker, P. Bellutti, et al., Solid State Commun. 114, 33 (2000). M. Modreanu, M. Gartner, E. Aperathitis, et al., Phys. E 16, 461 (2003). M. Modreanu, E. Aperathitis, M. Androulidaki, et al., Opt. Mater. 27, 1020 (2005). L. Heikkilä, T. Kuusela, H.-P. Hedman, et al., Appl. Surf. Sci. 133, 84 (1998). L. Heikkilä, T. Kuusela, and H.-P. Hedman, J. Appl. Phys. 89, 2179 (2001). N. Porjo, T. Kuusela, and L. Heikkilä, J. Appl. Phys. 89, 4902 (2001). S. Charvet, R. Madelon, R. Rizk, et al., J. Lumin. 80, 241 (1999). S. Charvet, R. Madelon, F. Gourbilleau, et al., J. Lumin. 80, 257 (1999).

72. 73. 74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86. 87. 88.

3. SURFACE AND SUPERLATTICE 89. 90. 91. 92. 93. 94. 95. 96. 97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. 112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. 124. 125. 126. 127. 128. 129. 130. 131. 132. 133. 134. 135. 136. 137. 138. 139. 140. 141. 142.

101

F. Gourbilleau, P. Voivenel, X. Portier, et al., Microelectron. Reliab. 40, 889 (2000). C. Ternon, F. Gourbilleau, R. Rizk, et al., Phys. E 16, 517 (2003). M. Bollani, S. Binetti, M. Acciarri, et al., Mater. Res. Soc. Symp. Proc. 762, A5.3. (2003). T. Akasaka and I. Shimizu, Appl. Phys. Lett. 66, 3441 (1995). A. Strass, W. Hansch, P. Bieringer, et al., Surf. Coat. Technol. 97, 158 (1997). J. E. Olsen and F. Shimura, J. Appl. Phys. 66, 1353 (1989). S. Chausserie, N. Khalfaoui, C. Dufour, et al., Opt. Mater. 27, 1026 (2005). M. Modreanu, M. Gartner, C. Cobianu, et al., Thin Solid Films 450, 105 (2004). T. Tagami, Y. Wakayama, and S.-I. Tanaka, Jpn. J. Appl. Phys. 36, L734 (1997). N. Daldosso, G. Das, G. Dalba, et al., Mater. Res. Soc. Symp. Proc. 770, I1.3.1 (2003). M. Zacharias, S. Richter, P. Fischer, et al., J. Non-Cryst. Solids 266–269, 608 (2000). D. J. Lockwood, G. F. Grom, L. Tsybeskov, et al., Phys. E 11, 99 (2001). M. Zacharias, J. Bläsing, K. D. Hirschman, et al., J. Non-Cryst. Solids 266–269, 640 (2000). M. Zacharias and P. Streitenberger, Phys. Rev. B 62, 8391 (2000). P. D. Persans, A. Ruppert, and B. Abeles, J. Non-Cryst. Solids 102, 130 (1988). M. Zacharias, J. Bläsing, P. Veit, et al., Appl. Phys. Lett. 74, 2614 (1999). J. S. d. Souza, G. A. Farias, V. N. Freire, et al., J. Appl. Phys. 84, 5369 (1998). M. Rosini, C. Jacoboni, and S. Ossicini, Phys. E 16, 455 (2003). B. K. Agrawal and S. Agrawal, Appl. Phys. Lett. 77, 3039 (2000). E. Degoli, S. Ossicini, D. Barbato, et al., Mater. Sci. Eng. B 69–70, 444 (2000). E. Degoli and S. Ossicini, Surf. Sci. 470, 32 (2000). E. Degoli and S. Ossicini, Opt. Mater. 17, 95 (2001). B. Delley and E. F. Steigmeier, Appl. Phys. Lett. 67, 2370 (1995). E. Degoli, S. Ossicini, M. Luppi, et al., Mater. Res. Soc. Symp. Proc. 770, I1.9.1 (2003). P. Carrier, Z. H. Lu, L. J. Lewis, et al., Appl. Surf. Sci. 212–213, 826 (2003). R. Tsu, Phys. Status Solidi (a) 180, 333 (2000). P. Carrier, L. J. Lewis, and M. W. C. Dharma-wardana, Phys. Rev. B 64, 195330 (2001). P. Carrier, L. J. Lewis, and M. W. C. Dharma-wardana, Phys. Rev. B 65, 165339 (2002). G. Allan, C. Delerue, and M. Lannoo, Appl. Phys. Lett. 71, 1189 (1997). N. Tit and M. W. C. Dharma-wardana, Solid State Commun. 106, 121 (1998). M. Nishida, Phys. Rev. B 59, 15789 (1999). D. J. Lockwood, M. W. C. Dharma-wardana, N. Tit, et al., Phys. E 6, 201 (2000). J. S. d. Souza, G. A. Farias, and V. N. Freire, Superlattices Microstruct. 25, 377 (1999). B. V. Kamenev, G. F. Grom, D. J. Lockwood, et al., Phys. Rev. B 69, 235306 (2004). X. L. Wu, S. Tong, X. N. Liu, et al., Appl. Phys. Lett. 70, 838 (1997). X. Portier, C. Ternon, F. Gourbilleau, et al., Phys. E 16, 439 (2003). A. Pérez-Rodriguez, A. Cornet, and J. R. Morante, Microelectron. Eng. 40, 223 (1998). P. X. Zhang, I. V. Mitchell, B. Y. Tong, et al., Phys. Rev. B 50, 17080 (1994). J.-M. Baribeau, D. J. Lockwood, and Z. H. Lu, Mater. Res. Soc. Symp. Proc. 382, 259 (1995). R. Sammynaiken, S. J. Naftel, T. K. Sham, et al., J. Appl. Phys. 92, 3000 (2002). L. Y. Zhu, X. F. Huang, W. B. Fan, et al., Superlattices Microstruct. 31, 285 (2002). L. Heikkilä, T. Kuusela, and H.-P. Hedman, Superlattices Microstruct. 26, 157 (1999). C. Delerue, G. Allan, and M. Lannoo, Phys. Rev. B 48, 11024 (1993). R. Rölver, O. Winkler, M. Först, et al., Microelectron. Reliab. 45, 915 (2005). S. Y. Ma, Thin Solid Films 402, 222 (2002). Y. Kanemitsu, Phys. Rev. B 53, 13515 (1996). H. Ennen, J. Schneider, G. Pomrenke, et al., Appl. Phys. Lett. 43, 943 (1983). S. Coffa, IEEE Spectrum 42, 44 (2005). P. G. Kik, M. J. A. de Dood, K. Kikoin, et al., Appl. Phys. Lett. 70, 1721 (1997). A. J. Kenyon, Curr. Opin. Solid-State Mater. Sci. 7, 143 (2003). A. J. Kenyon, Prog. Quantum Electron. 26, 225 (2002). E. F. Schubert, A. M. Vredenberg, N. E. J. Hunt, et al., Appl. Phys. Lett. 61, 1381 (1992). A. M. Vredenberg, N. E. J. Hunt, E. F. Schubert, et al., Phys. Rev. Lett. 71, 517 (1993). E. F. Schubert, N. E. J. Hunt, A. M. Vredenberg, et al., Appl. Phys. Lett. 63, 2603 (1993).

102 143. 144. 145. 146. 147. 148. 149. 150. 151. 152. 153. 154. 155. 156. 157. 158. 159. 160. 161. 162. 163. 164. 165. 166. 167. 168. 169. 170. 171. 172. 173. 174. 175. 176. 177. 178. 179. 180. 181. 182. 183. 184. 185. 186. 187. 188. 189.

BOUKHERROUB H. A. Lopez and P. M. Fauchet, Appl. Phys. Lett. 77, 3704 (2000). H. A. Lopez and P. M. Fauchet, Mater. Sci. Eng. B 81, 91 (2001). Y. Zhou, P. A. Snow, and P. S. J. Russel, Appl. Phys. Lett. 77, 2440 (2000). Y. Zhou, P. A. Snow, and P. S. J. Russel, Mater. Sci. Eng. B 81, 40 (2001). A. A. Dukin, N. A. Feoktistov, V. G. Golubev, et al., Appl. Phys. Lett. 77, 3009 (2000). A. A. Dukin, N. A. Feoktistov, V. G. Golubev, et al., J. Non-Cryst. Solids 299–302, 694 (2002). M. Lipson, T. D. Chen, D. R. Lim, et al., J. Lumin. 87–89, 323 (2000). M. Lipson and L. C. Kimerling, Appl. Phys. Lett. 77, 1150 (2000). M. Lipson, T. Chen, K. Chen, et al., Mater. Sci. Eng. B 81, 36 (2001). J. H. Shin, W.-H. Lee, and H.-S. Han, Appl. Phys. Lett. 74, 1573 (1999). J. H. Shin, J.-H. Jhe, S.-Y. Seo, et al., Appl. Phys. Lett. 76, 3567 (2000). Y. H. Ha, S. Kim, D. W. Moon, et al., Appl. Phys. Lett. 79, 287 (2001). J.-H. Jhe, J. H. Shin, K. J. Kim, et al., Appl. Phys. Lett. 82, 4489 (2003). M. Schmidt, M. Zacharias, S. Richter, et al., Thin Solid Films 397, 211 (2001). M. Zacharias, J. Heitmann, M. Schmidt, et al., Phys. E 11, 245 (2001). J. Heitmann, M. Schmidt, M. Zacharias, et al., Mater. Sci. Eng. B 105, 214 (2003). V. Y. Timoshenko, M. G. Lisachenko, B. V. Kamenev, et al., Appl. Phys. Lett. 84, 2512 (2004). F. Gourbilleau, C. Ternon, X. Portier, et al., Phys. E 16, 434 (2003). F. Bassani, L. Vervoort, I. Mihalcescu, et al., J. Appl. Phys. 79, 4066 (1996). V. Ioannou-Sougleridis, V. Tsakiri, A. G. Nassiopoulou, et al., Phys. Status Solidi (a) 165, 97 (1998). A. G. Nassiopoulou, V. Tsakiri, V. Ioannou-Sougleridis, et al., J. Lumin. 80, 81 (1999). V. Ioannou-Sougleridis, V. Tsakiri, A. G. Nassiopoulou, et al., Mater. Sci. Eng. B 69–70, 309 (2000). V. Ioannou-Sougleridis, T. Ouisse, A. G. Nassiopoulou, et al., J. Appl. Phys. 89, 610 (2001). V. Ioannou-Sougleridis, A. G. Nassiopoulou, T. Ouisse, et al., Appl. Phys. Lett. 79, 2076 (2001). F. Arnaud d’Avitaya, L. Vervoort, F. Bassani, et al., Europhys. Lett. 31, 25 (1995). F. Bassani, S. Menard, and F. Arnaud d’Avitaya, Phys. Status Solidi (a) 165, 49 (1998). E. Degoli and S. Ossicini, J. Lumin. 80, 411 (1999). N. Ibaraki and H. Fritzsche, Phys. Rev. B 30, 5791 (1984). B. Abeles, L. Yang, P. D. Persans, et al., Appl. Phys. Lett. 48, 168 (1986). P. Santos, M. Hundhausen, and L. Ley, Phys. Rev. B 33, 1516 (1986). L. Yang, B. Abeles, and P. D. Persans, Appl. Phys. Lett. 49, 631 (1986). O. Koblinger, J. Mebert, E. Dittrich, et al., Phys. Rev. B 35, 9372 (1987). S. Kalem, Phys. Rev. B 37, 8837 (1988). Y.-H. Song, C.-C. Eun, C. Lee, et al., Phys. Rev. B 42, 11862 (1990). M. Beaudoin, M. Meunier, and C. J. Arsenault, Phys. Rev. B 47, 2197 (1993). R.-Y. Tsai, L.-C. Kuo, and F. C. Ho, Appl. Opt. 32, 5561 (1993). J. Dutta, I. M. Reaney, P. Roca i Cabarrocas, et al., NanoStruct. Mater. 6, 843 (1995). K. Murayama, T. Toyama, S. Miyazaki, et al., Solid State Commun. 104, 119 (1997). M. Wang, X. Huang, W. Li, et al., Phys. Status Solidi (a) 167, 125 (1998). M. Wang, X. Huang, J. Xu, et al., Appl. Phys. Lett. 72, 722 (1998). X. Huang, L. Wang, J. Li, et al., J. Non-Cryst. Solids 266–269, 1015 (2000). L. Wang, Z. Ma, X. Huang, et al., Solid State Commun. 117, 239 (2001). L. Wang, X. Wang, X. Huang, et al., J. Phys.: Condens. Matter 13, 9857 (2001). L. Wang, X. Huang, Z. Ma, et al., Appl. Phys. A 74, 783 (2002). E. F. Steigmeier, D. Grützmacher, H. Auderset, et al., Thin Solid Films 225, 295 (1995). G. Santana, O. de Melo, J. Aguillar-Hernandez, et al., Phys. Status Solidi (c) 2, 3698 (2005). G. F. Bai, Y. P. Qiao, Z. C. Ma, et al., Appl. Phys. Lett. 72, 3408 (1998).

4 Optical Gain and Lasing in Low Dimensional Silicon: The Quest for an Injection Laser Lorenzo Pavesi Summary In this chapter, I review the various approaches to achieve an injection laser by using low dimensional or nanostructured silicon. After an initial discussion of the basic on light amplification and gain in semiconductor, I consider the limitations of silicon, in particular its band structure. Then, I present the experimental data about the observation of optical gain in silicon nanocrystals, in Er3+ ions coupled to silicon nanocrystals, in nanopatterned silicon on insulator and in nanoporous silicon impregnated by dyes. Finally I draw some conclusions on the perspectives to build a nano-silicon laser. Photonics and microelectronics convergence is propelled by the increase of the bit rate in-, within-, out of- a chip. An almost general consensus arises on 10 Gb s−1 as the bit rate at which electronics has to be replaced by photonics [1]. Nowadays, inside a lot of consumer electronics this bit rate is coming near: just as an example, novel generation play stations have data flow rates among the central unit and the peripherals (main memory, display, …) exceeding 20 Gb s−1. Thus, there is a serious need to implement optical interconnects inside electronics to allow faster communication. A key component in the optical link is the transmitter: a multi-chip component where light is generated and data streams are encoded into the light signal. Nowadays, transmitters are made by several distinct devices realized by using various materials: silicon for electronics, III–V semiconductors for laser, glasses or polymers for carrying the optical signal, etc. A breakthrough, which will allow cost reductions, performance improvements, increased availability, will be the monolithic integration of all the various devices into a single silicon chip. Most of these have been already demonstrated, the single one which is still laking is an injection silicon laser [2].

Laboratorio Nanoscience, Dipartimento di Fisica, Universita di Trento, via Sommarive 14, 38050 Povo (Trento), Italy, [email protected]


103

104

PAVESI

A first step to achieve a diode laser (LD) is to demonstrate a light emitting device (LED), where radiation is emitted incoherently. The market behind LED is enormous and people are thinking that it will be bigger than the whole DRAM market within ten years. In particular, the LED market is order of magnitude larger than the LD market. And LED are replacing LD in several applications due to their lower cost, robustness, and easy of use. For example, in printing LED-printers are more and more supplanting laser-printers. However, LD are essential for signal transmission in optical interconnects both at long and at short distances, because of their brightness, the easy of coupling in small fibers or waveguides, their monochromaticity, which allows reducing temporal dispersion and DWDM applications, and their high modulation speed. In this chapter, I will review the recent work performed to achieve an efficient LED or laser focusing to low dimensional silicon. Hence, I will not discuss approaches based on bulk silicon [3]. Very interesting results [4–6] and demonstration of CW laser action by using stimulated Raman scattering in bulk silicon [7, 8] have been published. I have already reviewed these in [1, 9]. Thus, in this chapter, I will shortly introduce the physics of gain, then I will review the limitation of silicon and then I will discuss various successful approaches based on silicon nanocrystals, Er coupled to silicon nanocrystals, and nanostructured silicon.

1. BASIC ON LIGHT AMPLIFICATION AND GAIN

A laser is based on three main components (Fig. 1): an active material that is able to generate and amplify light by stimulated emission of photons, an optical cavity that provides the optical feed-back to sustain the laser action, and a pumping mechanism that is able to excite the active material such that population inversion can be achieved [10]. In an injection diode laser, the optical feedback is provided by a Fabry-Perot cavity, and the pumping mechanism is usually provided by carrier injection via a p-n junction. The p-n junction allows achieving bipolar injection into the active material. Minority carriers are driven across the depletion layer into the other side of the junction to recombine there with majority carriers. High injection efficiency is thus achieved by injecting both electrons and holes. The use of electrical injection makes the device particularly interesting for integration with microelectronics. The light generation property of an active material is quantified by the internal quantum efficiency hint. hint gives the ratio between the number of photons generated and the number of electron-hole (e-h) pairs that recombine. This number is given by the ratio between the e-h radiative recombination probability and the total e-h recombination probability, i. e. by the fraction of all the excited e-h pairs that recombine radiatively. It easy to demonstrate that hint = tnr/(tnr + tr ), where tnr and tr are the nonradiative and radiative lifetimes, respectively. Thus to have an high hint either the radiative lifetime should be short (as in direct bang-gap semiconductors) or the nonradiative lifetime should be long (as in color center systems). The first essential property to be owned by the active material is the ability to emit and amplify light efficiently. Light amplification is quantified by the gain

4. OPTICAL GAIN AND LASING IN LOW DIMENSIONAL SILICON

105

FIG. 1. Basic components of a laser.

spectrum g(ħω) of the material. For a bulk semiconductor, it is related to the joint density of states ρ(ħω), the Fermi inversion factor fg(ħω), and the radiative lifetime: g (w ) dF (w ) = drstim (w ) − drabs (w ) =

l2 r (w ) fg (w ) F (w ) dz 8pt r

(1)

where dΦ the change in the photon flux, drstim or drabs the rate of stimulated emission or absorption at a given photon energy ħω, respectively, fg (w , EFe , EFh , T ) = [ fe (w , EFe , T ) − (1 − fh (w , EFh , T ))] , fe and fh are the thermal occupation functions for electrons and holes, and Φ the photon flux density. EFe and EFh are the quasi-Fermi level for electrons and holes, respectively. When no external pumping is present, the Fermi inversion factor reduces to the simple Fermi statistics for an empty conduction band and a filled valence band (fg w the condition of population inversion is verified and fg>0. This means that (1) is positive and hence the system shows positive net optical gain (g>0). Note that in (1) a critical role is played by the radiative lifetime: the shorter the lifetime the stronger the gain. For an atomic system, the expression of the gain coefficient reduces to g(w ) = s em (w ) N 2 − s abs (w ) N1 ,

(2)

where σem is the emission cross section, σabs the absorption cross section, N2 and N1 the density of active centers in the excited and ground states, respectively.

106

PAVESI

If σem = σabs, the condition to have positive optical gain is that N2 > N1, i.e., the condition of population inversion. The emission cross section is related to the radiative lifetime by the Einstein relation s em (v) =

l2 A(v), 8πt r

(3)

where n is the frequency, A(ν) the lineshape function associated to the optical transition. Also in (3) the radiative lifetime enters. If a piece of active material of length L is used to amplify light, one achieves light amplification whenever the material gain g is positive and larger than the propagation losses αp of the light trough the material, that is g > 0 and g > αp. If the system is forged as a waveguide L long, and we call IT and I0 the intensity of the transmitted and of the incident beams, the amplification factor G of the light is G = I T / I 0 = exp [(Gg − a p ) L ],

(4)

where G is the optical confinement factor of the optical mode in the active region. To have amplification G > 1. In a laser, optical feedback is usually provided by a Fabry-Peròt cavity so that the round trip gain (the overall gain experienced by a photon travelling back and forth across the cavity) can be larger than 1. This condition is expressed by the relation G2R1R2 > 1, where R1 and R2 are the back and front mirror reflectivities. For an injection laser, it is simple to demonstrate that the injection current density at threshold Jth is equal to J th =

a r + a el Δ nT , a hit T

(5)

where ar are the resonator losses experienced by light travelling in the cavity, which 1 1 includes also the mirror losses a m = 2 L ln R R , and l the active region thickness and 1 2 ΔnT the transparency excess free carrier density. ΔnT is related to the material properties, while the other parameters can be optimized by proper cavity design to reduce the threshold current. Note that in (5) the internal quantum efficiency is present. Recently high-Q resonators have been proposed to obtain gain in low efficient materials or to reduce significantly the laser threshold. Q = wE/P, where E is the energy stored in the cavity and P the total power lost by the cavity. When the linewidth of the cavity resonance is measured, Q can be approximated by Q = w/Δw, where Δw is the resonance linewidth. It is possible to demonstrate that the gain threshold for a resonator is related to Q by 2πng 1 (6) gth = , λG Q where ng is the group refractive index and λ the lasing wavelength. Several resonator architectures have been demonstrated in silicon, e.g. defects in photonic crystals


107

or microring resonator or microdisk resonators, with quality factors larger than 1 × 106 at λ = 1.55 μm [11].

2. LIMITATION OF SILICON FOR LIGHT AMPLIFICATION

Among the various semiconductor materials that have been used to form lasers, it is striking the absence of Silicon. Let us review why Si has not been used as a laser materials up to nowadays [2, 3, 12]. Si is an indirect band-gap semiconductor (Fig. 2). As a consequence, the probability for a radiative recombination is low, which in turn means that the e-h radiative lifetime is long, of the order of some milliseconds. An e-h pair has to wait in average a few milliseconds to recombine radiatively. During this time both the electron and the hole move around and cover a volume of the order of 10 μm3. If they encounter a defect or a trapping centre, the

FIG. 2. Simplified energy diagram of Si. The most relevant transitions are shown. Black: absorption of a photon via a phonon-assisted indirect transition; red: emission of a photon via a phonon-assisted indirect transition; orange: free carrier absorption; green: Auger recombination process.

108

PAVESI

carriers might recombine nonradiatively. Typical nonradiative recombination lifetimes in Si are of the order of some nanoseconds. Thus, in electronic grade silicon the internal quantum efficiency ηint is about 10−6. This is the reason why silicon is a poor luminescent material: the efficient nonradiative recombinations which deplete rapidly the excited carriers. Many strategies have been researched over the year to overcome this silicon limitation, some of which are based on the spatial confinement of the carriers, other on the introduction of impurities, other on the use of quantum confinement, others on the use of Si-Ge alloys or superlattices [3]. In addition, two other phenomena limit the use of Si for optical amplification (Fig. 2). The first is a nonradiative three-particles recombination mechanism where an excited electron (hole) recombines with an hole (electron) by releasing the excess energy to another electron (hole). This is called nonradiative Auger recombination mechanism (Fig. 3a). This recombination mechanism is active as soon as more than one carrier is excited. The probability of an Auger recombination is directly proportional to the number of excited carriers and inversely proportional to the band-gap energy [13]. For our discussion this is a very relevant mechanism because the more excited is the semiconductor the more the Auger recombination is effective. The probability for an Auger recombination in a bulk material is proportional to Δn3, we can thus write a nonradiative recombination lifetime due to Auger as τA = 1/CΔn2, where C is a constant, which depends on the doping of the material. For silicon C ∼ 10−30 cm6 s−1 [13]. For Δn∼ 1019 cm3, τA = 10 ns. The Auger recombination is the dominant recombination mechanism for high carrier injection rate in Si. The second phenomenon is related to free carrier absorption (Fig. 3b). Excited carriers might absorb photons and thus deplete the inverted population and, at the same time, increase the optical losses suffered by the signal beam. The free carrier absorption coefficient can be empirically related to the Si free carrier density nfc and to the light wavelength λ as αn ∼ 10−18 nfcλ2 at 300 K [14]. For nfc = 1019 cm−3 and λ=1.55 μm, αn = 24 cm−1. For heavily doped Si, this is the main limitations to lasing, while for intrinsic Si this contribution can be exceedingly small, unless nfc is very high as in a laser. In confined system, such as

FIG. 3. (a) Auger process; (b) free carrier absorption process. The wavy lines represent the band structure of silicon.


109

Si nanocrystals, this recombination mechanism is due to confined carriers and, hence, is called confined carrier absorption.

3. OPTICAL GAIN IN SILICON NANOCRYSTALS

Historically, the first successful material where optical gain was reported was based on Si nanoclusters (Si-nc) dispersed in a silica matrix [15]. Low dimensional silicon, where Si-nc are embedded into a silicon-based dielectrics, mostly Silicon dioxide but also Silicon nitride and their alloys, have been largely discussed in the literature [3]. With this approach one maximizes carrier confinement, improves the radiative probability by quantum confinement, shifts the emission wavelength to the visible, controls the emission wavelength by Si-nc dimension, decreases the confined carrier absorption due to the decreased emission wavelength, and increases the light extraction efficiency by reducing the dielectric mismatch between the source materials and the air. Various techniques are used to form Si-nc whose sizes can be tailored in the few nm range (Fig. 4). Starting by a silicon rich oxide, which can be formed by deposition, sputtering, ion implantation, cluster evaporation, etc., a partial phase separation is induced by thermal annealing. The excess silicon (excess with respect to the SiO2 stoichiometric quantity) clusterizes. The duration of the thermal treatment, the annealing temperature,

FIG. 4. Si nanocrystals formation, structure, and luminescence spectrum.

110

PAVESI

the starting excess Si content are all determining the final sizes of the clusters, their dispersion in size which can be significant and the Si-nc crystalline nature. It is worth noticing that the Si-nc density has been found in the 1017 cm−3 range for 10 % excess silicon. If one sums-up all the silicon contained in these Si-nc, one does not end-up with the amount of excess silicon deposited. Almost 70% of the Si atoms deposited still remains in the dielectric matrix after the annealing treatment. At the present, their influence on the optical properties is unclear. The large amount of Si in the matrix could explain the large value of optical losses measured in Si-nc based waveguides. The size dispersion is usually claimed as the source of the broad emission lineshape that at room temperature is typical of the Si-nc emission spectra. However, both size selected deposition [16] and single Si-nc luminescence experiments [17] demonstrate that most of the luminescence broadening is intrinsic in nature. The Si-nc have a core-shell structure with a crystalline Silicon core and a thin (∼5 Å) transition layer of a suboxide (Si-nc interface) [18]. The active role of the interface region in determining the optical properties of Si-nc has been highlighted in a joint theoretical and experimental paper [19]. The origin of the luminescence in Si-nc is still unclear, many authors believe that it comes from confined exciton recombination in the Si-nc [20], while others support a defect assisted recombination mechanism where luminescence is due to recombination of carriers trapped at radiative recombination centers, which form at the interface between Si-nc and the dielectric [21] or even in the dielectric [22]. One candidate for these centers is the silanone bond, which is formed by a double Si–O bonds [23]. The most probable nature of the luminescence in Si-nc is a mechanism, which involves both recombination paths: excitons at about 800 nm and trapped carriers on radiative interface state at about 700 nm. Indeed passivation experiments show that the intensity and lineshape of the emission can be influenced by exposition to hydrogen gas or by further oxidation [24]. A number of papers reported observation of optical gain in these systems [15, 25–32]. Gain was observed in many different experiments in Si-nc formed by many different techniques. Figure 5 reports a summary of the most relevant data taken on Si-nc formed by plasma enhanced chemical vapor deposition (PECVD) [25–27]. Two techniques are reported here: the variable stripe length method (VSL), which is sketched in the inset of Fig. 5 and is based on the one-dimensional amplifier model [26], and the pump-probe technique, which is based on the probe amplification in presence of an high energy and high intensity pump beam [27]. In the VSL method by varying the pumped region extent (whose length is z) one measures the amplified spontaneous emission (IASE) signal coming out from an edge of a waveguide whose core is rich in Si-nc: I ASE ( z ) =

J sp (Ω ) gmod

(e gmod z − 1),

(7)

where Jsp(W) is the spontaneous emission intensity emitted within the solid angle W and gmod is the net modal gain of the material, defined as gmod = Gg − α. Data reported in Fig. 5 shows that the ASE intensity increases sublinearly with the pumping length when the pumping power is lower than a threshold. For pumping


111

FIG. 5. Summary of various experimental proofs of gain in Si-nc. Top left panel, geometry used to measure the ASE, amplified spontaneous emission; top center panel, ASE vs. the pumping length for two pumping powers; top right, ASE time decay for the various pumping conditions indicated in the inset (1 is the pumping length); bottom left, luminescence, absorption and gain spectra at room temperature for a Si-nc rich waveguide; bottom right, transmission spectra for various pumping powers (the inset shows the experimental geometry used). Data have been redrawn from [25, 26, 27].

power higher than threshold the ASE signal increases more than exponentially. This is a consequence of the pump induced switching from absorption (gmod0). In addition if time resolved measurements are performed (Fig 5-right top panel) [27], the ASE decay lineshape shows two time regimes: a fast decay within the first nansecond and a slow time decay with typical time constant of few microseconds. It is well known that Si-nc have time decay constant of some microseconds, so the appearance of a nanosecond time decay is at first surprising. What is important is the fact that the fast decay appears only if the pumping power and the excitation volume are both large. If one decreases the excitation volume at high power or the pumping power at large excitation volume, the fast decay disappears. This can be understood if the fast decay is due to stimulated emissions. In fact, at high pumping rate three competitive paths open: stimulated emission, Auger recombination, and confined carrier absorption. All these could be the cause of the fast decay. In particular, the Auger lifetime and the confined carrier absorption lifetime can be modelled in a 1 I Si-nc by t A = and t CC = 2C N , where CA and CCC are coefficients and Nex is C A N ex CC ex the density of excited recombination centers. Nex is directly proportional to the pumping power and not to the pumping volume. Thus, decreasing the pumping length the ASE decay lineshape should be unchanged. On the one hand, the experiments show that the fast component disappears, this excludes Auger or confined carrier absorption as the origin of the fast component. On the other hand, by a simple

112

PAVESI

rate equation modelling [33], the stimulated emission lifetime turns out to be 4 1 3 t se = π RNS , where RNS is the average radius of the Si-nc, ξ their packing density, 3 ξσ g cnph σg the gain cross section and nph the photon flux density. Note that τse depends on the material properties (RNS,ξ, σg) but also on the photon flux density nph, which exists in the waveguide. nph depends, in turn, on the waveguide losses, the Si-nc quantum efficiency and the pumping rates. In addition, if the sample shows gain, by increasing the excitation volume, nph exponentially increases, i.e. τse decreases. τse shortens when either the pumping length or the pumping power are increased as both increase nph. It is important to notice that calculations show that the Auger lifetime in Si-nc are in the interval 0.1–10 ns [34], which means that Auger is a strong competitive process which should be always considered. In some Si-nc systems, due to either material problems or poor waveguide properties or both, Auger and confined carrier absorption might prevail and no optical gain could be observed. Figure 5 bottom left shows a summary of the wavelength dependence of the luminescence, absorption, and gain spectra in a sample with 4 nm wide Si-nc [25]. It is seen that the gain spectrum is on the high energy side of the emission band and that absorption is negligible in the region of gain and luminescence. These facts suggest a four level models to explain the gain where the levels can be associated to both different Si-nc populations or to a radiative state associated to a Si=O double bond for which optical excitation causes a large lattice relaxation of the Si=O bond [35] as in the silanone molecule (Fig. 6). Pump-probe measurements were attempted with contradictory results world wide [27, 36]. Our group was able to show probe amplification under pumping conditions (see Fig. 5-bottom right panel) [27], while another group reported pump-induced absorption probably associated with confined carrier absorption [36]. Literature results show that the confined carrier absorption cross section σfc in Si-nc is at least one order of magnitude reduced with respect to bulk Si [37]: σfc≈10−18 cm2 at 1.55 μm in P-doped Si-nc. This cross section should be further reduced at 700 nm due to the λ2 dependence of the confined carrier absorption. Transmission measurements of a probe beam through a Si-nc slab deposited on a quartz substrate show the typical interference fringes due to multiple reflection at the slab interfaces (Fig. 5). When the pump power is raised, the transmission is increased and, at the maximum power used, net probe amplification with respect to the input probe intensity in air is observed in a narrow wavelength interval. Note that the probe amplification spectrum overlaps the fast luminescence spectrum measured by time resolved technique. On the basis of these results, design of optical cavity for a Si-nc laser has been published [38] (Fig. 7) Figure 3 shows a summary of various experimental results measured at the University of Trento on various samples prepared with many different methods. It is interesting to note that in addition to the packing density another parameter rules the possibility and strength of the material gain: the Si-nc sizes. As the Si-nc size decreases the material gain increases, maximum gain values of 100 cm−1 under pulsed excitations are reported in the figure. Today, the challenge is related to carrier injection into the active region to electrically pump the population inversion and, thus, achieve an injection amplifier


113

FIG. 6. The four level model introduced to explain gain in Si-nc.

FIG. 7. Modal gain and material gain measured under pulsed conditions for various Si-nc waveguides as a function of the Si-nc diameters. Bottom plot is the net gain obtained by the measured gain coefficient gmod divided by the optical mode confinement factor Γ. Upper plot refers to the estimated material gain gmal, which takes into account the propagation losses α measured at the same wavelength as the gain measurements.

or laser. Very favorable results have been published with respect to Si-nc based LED where turn on voltages as low as few volts have been demonstrated by using thin Si-nc active layers [39]. The quantum efficiency of these LED was low because electroluminescence was due to impact excitation of electron-hole pairs in the Si-nc. The problem is related to the fact that the carriers have to cross a dielectric. Two mechanisms for current flow are possible (Fig. 8): tunnelling through the high energy triangular barrier formed across the dielectrics when the bias field is large

114

PAVESI

FIG. 8. The Fowler-Nordheim injection and the direct tunnelling injection. Courtesy of Z. Gaburro.

(named Fowler-Nordheim tunnelling) or direct tunnelling into the quantized electronic states of the Si-nc. The barrier height and the oxide thickness determine which one is the prevailing mechanism. The energy of the involved carriers in the two transport processes is significantly different. In the Fowler-Nordheim case, energetic hot electrons are injected into the oxide, which have a low probability to loose their energy by exciting an electron-hole pair in Si-nc. This process is called impact excitation and can lead to electroluminescence in presence of an unipolar current. An unwanted side-effect is the fact that the oxide is stressed by the current and could break which causes the failure of the LED. Usually LED based on this injection mechanism have low efficiencies, in the 10−5 range. Carrier direct tunnelling is more reliable despite is more difficult. Oxide thicknesses has low as a few nanometer are needed. The more difficult aspect is to achieve bipolar tunnelling, i.e., both electrons and holes have to tunnel into the same Si-nc to have electroluminescence. Once direct tunnelling is achieved, the radiative recombination efficiency of the Si-nc is quite high. A recent work [40] has shown that indeed bipolar direct tunnelling is possible and electroluminescence so excited is quite high. This device is based on a FET structure where the gate dielectric has a layer of Si-nc. Actually the device was designed to act as a memory device. By driving a current trough the channel, and changing the sign of the gate bias, separate injection of electrons and holes in the Si-nc is achieved. Luminescence is observed only when both electrons and holes have been charged into the Si-nc. By using this AC bias technique, unipolar injection of alternate sign charge carriers is achieved, which leads to high efficiency in the emission of the LED (an estimate gives few percent).


115

FIG. 9. Left: propagation losses at 1,620 nm of Si-nc based waveguides vs. the refractive index of the core layer measured at 632.8 nm. The inset shows the modal profile measured at the exit of the waveguide. Right: propagation losses measured vs. the wavelength for a rib-loaded waveguide with a core thickness and refractive index of 1.8 μm and 1.565 at 632.8 nm, respectively, and a rib width of 13 μm. The inset shows an image of a typical waveguide. Data from [41, 42].

Channel optical waveguides with a core layer rich of Si-nc have been characterized for their propagation losses [41, 42]. Various sources of loss are present: absorption losses due to the direct absorption of the Si-nc, scattering losses due to the composite nature of the core of the waveguide, which are usually described within the Mie formalism, scattering losses due to the roughnesses at the corecladding interface or at the channel edges. Figure 9-left shows optical losses of only a few dB/cm at 1.6 μm when low refractive index (i.e., low excess silicon content in the film) is used. These losses significantly increase when the wavelength is reduced (Fig. 9-right). This is mainly due to direct Si-nc absorption and Mie scattering due to the index mismatch among the Si-nc and the dielectric [43]. All these different experimental findings have still to be merged in a laser cavity structure to demonstrate a Si-nc based laser.

4. LIGHT AMPLIFICATION IN ER COUPLED TO SI NANOCLUSTERS

The radiative transitions in the internal 4 f shell of Erbium ions (Er3+) are exploited in the erbium-doped fiber amplifier (EDFA) [44]: an all optical amplifier that has revolutionized the optical communication technology. During the nineties several experimental efforts have been spent to develop an efficient and reliable light source by using Er3+ in Si [3]. The idea was to excite the Er3+, which emits 1.535 μm photons, by an energy transfer from the electrically injected e-h pairs in a p-n Si diode. The most successful results have been the demonstration of room temperature emission with an external quantum efficiency of 0.1 % in a MHz modulated Er3+-doped Si LED [45]. The main problem associated to Er3+ in Si is the back transfer of energy from the Er3+ ions to the Si host, which causes a lowering of the emission efficiency of the diode [41]. This is due to a resonant level, which appears in the Si band gap due to the Er3+ doping and which couples with the Er3+ levels. To reduce

116

PAVESI

FIG. 10. Schema of the distribution of Er3+ ions coupled to the Si-nc. The dashed ring around the Si-nc shows the coupling volume which contains Er3+ ions coupled to the Si-nc. The Er3+ ions outside these volumes are uncoupled.

this back-transfer process, it was proposed to enlarge the band-gap of the Er3+ host so that the resonance between the defect level and the internal Er3+ levels is lost [41]. Si-nc in a SiO2 dielectric were thus proposed as the host [47]. Indeed it turns out that Si-nc are very efficient sensitizers of the Er3+ luminescence with typical transfer efficiency as high as 70% and with a typical transfer time of 1 μs [48]. In addition, the Er3+ are dispersed in SiO2, where they found their most favorable chemical environment. Quite interestingly the transfer efficiency gets maximized when the Si-nc are not completely crystallized but still in the form of Si nanoclusters [49]. Some reports claim even that the Er3+ can be excited through defects in the matrix [50]. However, the segregation of Er3+ in SiO2 is so effective that they are not homogeneously distributed but tend to agglomerate in regions empty of Si-nc even when the Er3+ concentration is lower than the critical concentration for Er3+ clustering (>1 × 1020 cm−3) [51]. Since the Er3+–Si-nc characteristic interaction distance is lower than 1 nm. [52], less than 10% of the Er3+ ions are effectively coupled to the Si-nc (Fig. 10). Figure 11 summarizes the various mechanisms and defines the related cross-sections for this system. On the one hand, excitation of Er3+ occurs via an energy transfer mechanism (dipole–dipole interaction) among Er3+ and photoexcited Si-nc: the overall efficiency of light generation at 1.535 μm through direct absorption in the Si-nc is described by an effective Er3+ excitation cross section σexc. On the other hand, the direct absorption of the Er3+ ions, without the mediation of the Si-nc, and the emission from the Er ions are described by an absorption σabs and an emission σem cross sections, respectively. The typical radiative lifetime of Er3+ is 8–10 ms [53], which is similar to the one of Er3+ in pure SiO2 [54]. Figure 12-left reports the luminescence and the


117

σ fc

Auger

signal

up-conversion

tr ~1μs

650 nm

σexc pump

800 nm 980 nm

Er

3+

4F 9/ 2 4I 9/ 2 4I 11/ 2 4I 13/ 2 em ~9ms

Si-nc signal σabs

σ em 4I 15/ 2

FIG. 11. Diagram of the excitation process of Er3+ ions via a Si-nc, with the main related cross sections. On the left the main internal energy levels of the Er3+ are shown.

absorption spectra measured in an Er3+ coupled Si-nc ridge waveguide at room temperature [55]. When the excitation rate is large, other competing processes appear. In the Si-nc, Auger recombination or confined carrier absorption deplete the Si-nc excitation and, thus, act to reduce the Er3+ σexc by being competitive to the energy transfer from the Si-nc. Indeed σexc has been found to decrease as the pumping is increased [55]. Moreover, strongly excited Er3+ ions are affected by nonradiative recombination processes such as cooperative upconversion or excited state absorption [56]. Table 1 summarizes the best results for the various cross sections reported in the literature. It is important to notice the five order of magnitude increase in σexc and the high efficiency of Er3+ pumping by impact excitation via an electrical current [59]. In addition, it is striking that σem gets enhanced by one order of magnitude with respect to the value for Er3+ in pure SiO2 [60]. A cautious note should here drawn as measurements for σabs do not confirm this enhancement [55]. If one places the Er3+ ions in a Si-nc ridge waveguide (inset of Fig. 12-right), one can perform experiments on signal amplification at 1.535 μm with the aim to demonstrate an Er-doped waveguide amplifier (EDWA). The main advantage of an EDWA with respect to an EDFA is the reduced size, the decreased pump power to achieve the same gain, and the wide spectrum range to optically pump the system. A few groups have performed such an experiment [55, 61, 62]. The most successful result was reported in [61], see Fig. 12-right. In this work a very low Si-nc concentration has been used and an internal gain of 7 dB cm−1 has been deduced. A successful experiment of pumping the EDWA with LED was also reported [60]. In other experiments, with a large Si-nc concentration, no or weak signal enhancement has been observed [55, 62]. The reason is attributed to the presence of a strong confined carrier absorption, which introduces a loss mechanism at the signal wavelength and

118

PAVESI

Table 1 Summary of the various cross sections related to Er3+ in various materials Er in SiO2 (cm2) Er in Si (cm2) Effective excitation cross 1–8×10−21 section of luminescence at a pumping energy of 488 nm Effective excitation cross section of electroluminescence Emission cross section at 6×10−21 1.535 μm Absorption cross section at 4×10−21 1.535 μm

Er in Si-nc (cm2)

Reference for Er in Si-nc

3×10−15

1.1−0.7×10−16 [57, 58]

4×10−14

1×10−14 by [59] impact ionization 6×10−20 [60]

2×10−20

0.4–1.2×10−20 [53]

For Er3+ coupled to Si-nc, the best reported results are shown and are taken in the reference listed in the last column

FIG. 12. (left) Absorption and luminescence spectra of an Er3+ coupled Si-nc waveguide. Data after [51] (right) Signal enhancement at 1.535 μm in an Er3+ coupled Si-nc waveguide vs. the pumping power density by using top pumping as shown in the inset. Data after [55].

prevents the sensitizing action of the Si-nc. Indeed, the energy transfer is in competition with confined carrier absorption at the signal wavelength (Fig. 11). A confined carrier cross section of 10−18 cm2 is usually assumed [48]. The competing recombination channels for excited carriers in the Si-nc turn-off the energy transfer to the Er3+ ions: the signal enhancement observed in [55] is due to the direct absorption of the Er3+. Propagation losses, saturation of Er3+ excitation, up-conversion, excited state absorption and confined carrier absorption make difficult the proper design of EDWA where optical amplification can be observed. In addition, the design of the top-pumping configuration makes new challenges in terms of proper modal overlap and effective pumping: a detailed design study has shown some solutions to this when large rectangular waveguides are used [63]. Having got internal gain, electrically injected LED [59, 64] and optical cavities[65], a laser that uses the Er3+ coupled


119

Si-nc system as active material seems feasible. A very interesting design of an electrically driven laser, which uses a microring resonator and slot waveguides has been published [66]. It is worth noticing that toroidal microcavities formed in silica doped with Er3+ have demonstrated optically pumped lasing at room temperature [67].

5. OPTICAL GAIN IN NANOSTRUCTURED SILICON

5.1. Stimulated Emission by Nanocavities in Silicon Recently, evidence of stimulated emission in nanocavities formed in silicon has appeared [68]. A thin (80 nm) silicon on insulator (SOI) layer was patterned by forming a periodic (100 nm) network of cavities (diameter 60 nm), see Fig. 13. The SOI layer acts as a planar waveguide. Low temperature photoluminescence experiments show that the waveguided luminescence is dominated by a narrow and strong emission at 1,278 nm, see Fig. 13-left. This emission exhibits a nonlinear increase with the pumping rate with a threshold like behavior joined to a significant line narrowing, see Fig. 13-center. VSL-experiments on this line shows the typical switch from losses at low power to gain at high power due to amplified spontaneous emission, see Fig. 13-right. Other evidences support the stimulated emission nature of the 1,280 nm line: a fine structure of the line and a directionality of the emission. Measured gain coefficients are as high as 260 cm−1 at 10 K and decrease to 80 cm−1 at 70 K, while at higher temperatures no more stimulated emission is observed. To explain these observations, it was proposed in [68] that the nanopatterning allows to have a large effective silicon surface where a sizable density of A′ centers could pile-up. A′ centers are associated to silicon vacancies. Emission is due to phononless direct recombination between trapped electrons and free holes. These defect centers are believed to play the role of active optical centers, which can be optically inverted in these samples. Despite the impressive results, the major caveat is that the gain is vanishing as the temperature is raised. Another possible difficulty could be to obtain an effective electrical excitation of the defects.

FIG. 13. Left: edge emission luminescence spectrum at 10 K. Inset: Image of the samples. Center: evolution of the edge emission intensity of the 1,278 nm line as a function of the pump power at 10 K. A few high resolution luminescence lineshape of the 1,278 nm line are reported in the inset. Right: evolution of the edge-emission intensity as a function of the pumping length in a VSL experiment. Two pumping power are used. The fit to the data with (7) yields the absorption and gain coefficient reported. Data after [68].

120

PAVESI

5.2. Stimulated Emission by Dye Impregnation in Nanoporous Oxidized Silicon Another way to form nanocavities in silicon is to use porous silicon formation. A successful experiment of impregnation of nanoporous silicon with an optical active specie (dye molecules) is reported in [69]. By a suitable choice of etching parameters, two-layer planar waveguides were grown (a core with a refractive index of 1.75 and a cladding with a refractive index of 1.36). The waveguides were designed to be single mode with a core 500 nm thick and a cladding 10 μm thick. The waveguides were then annealed at 900°C in air for 3 h in order to completely oxidize the silicon, and convert the material into transparent porous silica. The refractive indices of the core and cladding decreased from 1.75 and 1.36 down to 1.25 and 1.15, respectively. The samples were subsequently impregnated with the dye NileBlue (LC 6900) by immersing them in an ethanoic dissolution. The guided emission from a waveguide impregnated in a 10−4 M Nile-Blue solution showed a strong nonlinear intensity increase with a significant line narrowing of the emission lineshape when the pump pulse energy was increased at room temperature, see Fig. 14-left. VSL experiments demonstrated that the increase and the line narrowing are due to optical gain. The gain coefficients as a function of the pump pulse energy are reported in Fig. 14-right for three significant wavelengths. Maximum gain values of 10 cm−1 were reported and associated to the saturation of the dyes. The main problems of this approach is the fact that laser dyes usually undergo bleaching after a certain number of pulses, especially when they are not circulated, as in this case. In fact, after 1,000 pump pulses the amplified signal started to decrease appreciably. After 104 pump pulses, the waveguide still showed amplification, but with four times higher pump threshold.

FIG. 14. Left: evolution of the room temperature emission intensity at 700 nm vs. the pump pulse energy from a dye impregnated porous silica waveguide. Various emission lineshape are reported at the pump pulse energy referred by the arrows. Right: gain coefficients at 680, 700, 720 nm vs. the pump pulse energy density. Data after [69].


121

6. CONCLUSIONS

After six years since the first observation of optical gain in Si nanocrystals, a first Si laser has been demonstrated, though not using Si-nc but the Raman effect. Raman laser are necessarily optically pumped so have limited applications. Thus the research to achieve an electrically pumped laser in silicon is still open and very active. I have reviewed in this chapter a few of the main research lines. These cover a wide spectral range spanning from visible to infrared. ●

●

●

Silicon bulk-based approaches [λ = 1.2 μm] aim to increase the nonradiative lifetimes and, hence, to increase the internal quantum efficiency by using passivation or carrier localization either in a small silicon region or on a point defect. The more successful approaches are based on the use of the nanopatterning of a pn junctions or of a thin silicon layer. Both stimulated emission by electrical injection or by optical pumping at cryogenic temperatures have been observed. Silicon nanocrystals-based approaches [λ = 0.7 μm] aim to beat the indirect band-gap of silicon by using quantum confinement. Both high external quantum efficiency in electroluminescence devices and optical gain under optical pumping have been reported. To achieve electrical pumped optical gain and, hence, lasing one has to control the injection in the silicon nanocrystals so that it becomes bipolar injection. At the same time electrons and holes have to tunnel into the nanocrystals so that efficient recombination is possible. A proper bandgap engineering by changing both the composition and the effective barrier strengths is needed. Er coupled to silicon nanocrystals approaches [λ = 1.535 μm] where several materials related issue have still to be mastered. Optimization of the deposition parameters, Er content and annealing processes has to be performed by using as figure of merit the waveguide optical gain and not the luminescence intensity as it has been done so far. Once optimization has been reached, the implementation of electrically injected amplifier could be achieved also by using the injection methods suggested for bare Si-nc.

In addition, the hybridization of silicon with III-V semiconductors is a viable way to add a laser on silicon. Many successful examples have been reported. One which seems very promising is based on the bonding of an active direct-band gap layer on top of a silicon rib-waveguide so that an evanescent coupling of the optical mode of the silicon rib-waveguide within the active layer of AlGaInAs occurs. Thus, light amplification is occurring in the direct band-gap AlGaInAs while light is propagating in the silicon waveguide. By including this structure within an optical cavity, optically pumped CW lasing at 1,568 nm and up to 60°C was reported [70]. Electrically injection should be easy in the direct band-gap layer. These facts show that the perspectives to achieve an injection laser in Si are nowadays more solids than ever. We are quite optimistic that a laser will be realized in the near future by using one of the various approaches here presented.

122

PAVESI

Acknowledgments It is a pleasure to thank the hard work of my coworkers and students. The support of EC through the SEMINANO (FP6-505285), PHOLOGIC (FP6-017158), and SINERGIA (FP529650)/LANCER (FP6-033574) projects and of the MIUR through the Italy-Spain linkage grant is acknowledged

REFERENCES 1. Optical interconnects, edited by L. Pavesi and G. Guillot, Springer series in Optical sciences Vol. 119 (Springer-Verlag, Berlin 2006). 2. Silicon Photonics, edited by Lorenzo Pavesi and David Lockwood, Topics in Applied Physics Vol. 94 (Springer-Verlag, Berlin 2004). 3. Ossicini Stefano, Pavesi Lorenzo, Priolo Francesco Light Emitting Silicon for Microphotonics, Springer Tracts in Modern Physics, Vol. 194 (Springer-Verlag, Berlin 2003) 4. M. A. Green, J. Zhao, A. Wang, P. J. Reece and M. Gal, Nature 412, 805 (2001) 5. W.L. Ng, M. A. Lourenço, R. M. Gwilliam, S. Ledain, G. Shao, and K. P. Homewood, Nature 410, 192 (2001) 6. M. J. Chen, J. L. Yen, J. Y. Li, J. F. Chang, S. C. Tsai, and C. S. Tsai, Appl. Phys. Lett. 84, 2163 (2004) 7. O. Boyraz and B. Jalali, Opt. Exp. 12, 5269 (2004); Opt. Exp. 11, 1731 (2003) 59; Opt. Exp. 13, 796 (2005) 8. A. Liu, H. Rong, M. Paniccia, O. Cohen, and D. Hak, Opt. Exp. 12, 4261 (2004); Nature 433, 292 (2005); Nature 433, 625 (2005) 9. L. Pavesi, Materials Today 8(1) (January 2005) pp. 18–25. 10. O. Svelto, D. C. Hanna, Principles of Lasers, Plenum Press, 1998. 11. M. Borselli, T. J. Johnson, and O. Painter, Appl. Phys. Lett. 88, 131114 (2006) 12. Towards the first silicon laser, edited by L. Pavesi, S. Gaponenko and L. Dal Negro, NATO Science Series (Kluwer Academic Publishers 2003) 13. P. Jonsson, H. Bleichner, M. Isberg, and E. Nordlander, J. Appl. Phys. 81, 2256 (1997) 14. Schroder, D. K., R. N. Thomos, and J. C. Swartz, IEEE Trans. Electron. Dev. ED-25, 254 (1978) 15. L. Pavesi, L. Dal Negro, C. Mazzoleni, G. Franzò, F. Priolo, Nature 408, 440 (2000) 16. M. Zacharias, J. Heitmann, R. Scholz, U. Kahler, M. Schmidt, and J. Bläsing, Appl. Phys. Lett. 80, 661 (2002) 17. J. Valenta, R. Juhasz, and J. Linnros, Appl. Phys. Lett. 80, 1070 (2002). 18. A. Zimina, S. Eisebitt, W. Eberhardt, J. Heitmann and M. Zacharias, Appl. Phys. Lett. 88, 163103 (2006) 19. N. Daldosso, M. Luppi, S. Ossicini, E. Degoli, R. Magri, G. Dalba, P. Fornasini, R. Grisenti, F. Rocca, L. Pavesi, S. Boninelli, F. Priolo, C. Bongiorno, and F. Iacona, Phys. Rev. B 68, 085327 (2003) 20. Johannes Heitmann, Frank Muller, Lixin Yi, Margit Zacharias, Dmitri Kovalev, Frank Eichhorn, Phys. Rev. B 69, 195309 (2004) 21. L. Khriachtchev, M. Räsänen, S. Novikov, O. Kilpelä, and J. Sinkkonen, J. Appl. Phys. 86, 5601 (1999) 22. Leonid Khriachtchev, Markku Räsänen, Sergei Novikov, Lorenzo Pavesi, Appl. Phys. Lett. 85, 1511 (2004) 23. Y. J. Chabal, Krishnan Raghavachari, X. Zhang, and E. Garfunkel Phys. Rev. B 66, 161315 (2002) 24. J. S. Biteen, N. S. Lewis, and H. A. Atwater A. Polman, Appl. Phys. Lett. 84, 5389 (2004) 25. L. Dal Negro, M. Cazzanelli, N. Daldosso, Z. Gaburro, L. Pavesi, F. Priolo, D. Pacifici, G. Franzò and F. Icona, Physica E 16, 297 (2003) 26. L. Dal Negro, M. Cazzanelli, L. Pavesi, S. Ossicini, D. Pacifici, G. Franzò, F. Priolo and F. Iacona, Appl. Phys. Lett. 82, 4636 (2003) 27. L. Dal Negro, M. Cazzanelli, B. Danese, L. Pavesi, F. Iacona, G. Franzò and F. Priolo, J. Appl. Phys. 96, 5467(2004) 28. Leonid Khriachtchev, Markku Rasanen, Sergei Novikov, and Juha Sinkkonen, Appl. Phys. Lett. 79, 1249 (2001) 29. J. Ruan, P. M. Fauchet, L. Dal Negro, M. Cazzanelli, and L. Pavesi, Appl. Phys. Lett. 83, 5479 (2003)


123

30. K. Lutcrova, K. Dohnalova, V. Svrcek, I. Pelant, J.-P. Likforman, O. Cregut, P. Gilliot, and B. Honerlage, Appl. Phys. Lett. 84, 3280 (2004) 31. M H Nayfeh, S Rao, N Barry, Appl. Phys. Lett. 80, 121 (2002) 32. Massimo Cazzanclli, Dmitri Kovalev, Luca Dal Negro, Zeno Gaburro, and Lorenzo Pavesi, Phys. Rev. Lett. 93, 207402 (2004) 33. VI.Klimov, A A. Mikhailovsky, S. Xu, A. Malko, J. A. Hollingsworth, et al., Science 290, 314, (2000) 34. C. Delerue, M. Lannoo, G. Allan, Phys. Rev. Lett. 75, 2228 (1995) 35. F. Zhou and J. D. Head, J. Phys. Chem. B 104, 981 (2000); A. B. Filonov, S. Ossicini, F. Bassani, F. Arnaud D’Avitaya, Phys. Rev. B 65, 195317 (2002) 36. R.G. Elliman, M J. Lederer, N. Smith, and B. Luther-Davies, Nucl. Instrum. Meth. B 206, 427 (2003) 37. A. Mimura, M. Fujii, S. Hayashi, D. Kovalev, and F. Koch, Phys. Rev. B 62, 12625 (2000) 38. S. L. Jaiswal et al., Appl. Phys. A77, 57 (2003). 39. G. Franzò, A. Irrera, E. C. Moreira, M. Miritello, F. Iacona, D. Sanfilippo, G. Di Stefano, P. G. Fallica, and F. Priolo, Appl. Phys. A 74, 1 (2002) 40. R. J. Walters, R. I. Bourianof, H. Atwater, Nat. Mat. 4, 143 (2005) 41. A.J. Kenyon, P.F. Trwoga, M. Federighi, and C.W. Pitt, J. Phys. Condens. Mat. 6, L319 (1994) 42. M. Melchiorri, N. Daldosso, D. Navarro-Urrios, L. Pavesi, G. Pucker, F. Gourbilleau, S. Chausserie, C. Dufour, Appl. Phys. Lett. (2006) 43. P. Pellegrino, B. Garrido, C. Garcia, J. Arbiol, J.R. Morante, M. Melchiorri, N. Daldosso, L. Pavesi, E. Schedi, and G. Sarrabayrouse, J. Appl. Phys. 97, 074312 (2005) 44. E. Desurvire, Erbium-Doped Fiber Amplifiers: Principles and Applications (Wiley, New York, 1994). 45. G. Franzò, S. Coffa, F. Priolo, and C. Spinella, J. Appl. Phys. 81, 2784 (1997) 46. F. Priolo, G. Franzò, S. Coffa, and A. Carnera, Phys. Rev. B 57, 4443 (1998) 47. M. Fujii, M. Yoshida, Y. Kanzawa, S. Hayashi, and K. Yamamoto, Appl. Phys. Lett. 71, 1198 (1997) 48. D. Pacifici, G. Franzò, F. Priolo, F. Iacona, and L. Dal Negro, Phys. Rev. B.67,245301 (2003) 49. G. Franzò et al., Appl. Phys. Lett. 82,3871(2003) 50. D. Kuritsyn, A. Kozanecki, and H. Przybylin’ska, W. Jantsch, Appl. Phys. Lett. 83, 4160 (2003) 51. P. Pellegrino, B. Garrido, J. Arbiol, C. Garcia, Y. Lebour, and J. R. Morante, Appl. Phys. Lett. 88, 121915 (2006) 52. F. Gourbilleau, R. Madilon, C. Dufour, and R. Rizk, Opt. Mat. 27, 868 (2005) 53. N. Daldosso, D. Navarro-Urrios, M. Melchiorri, L. Pavesi, C. Sada, F. Gourbilleau, and R. Rizk, Appl. Phys. Lett. 88, 161901 (2006) 54. M. Wojdak et al. Phys. Rev. B 69, 233315 (2004) 55. N. Daldosso, D. Navarro-Urrios, M. Melchiorri, L. Pavesi, F. Gorbilleau, M. Carrada, R. Rizk, C. Garcia, P. Pellegrino, B. Garrido, and L. Cognolato, Appl. Phys. Lett. 86, 231103 (2005) 56. W. Loh and A. J. Kenyon, IEEE Phot. Techn. Lett. 18, 289 (2006) 57. F. Priolo, G. Franzò, D. Pacifici, V. Vinciguerra, F. Iacona, and A. Irrera, J. Appl. Phys. 89, 264 (2001) 58. A. J. Kenyon, C. E. Chryssou, C. W. Pitt, T. Shimizu-Iwayama, D. E. Hole, N. Sharma, and C. J. Humphreys J. Appl. Phys. 91, 367 (2002) 59. F. Iacona, D. Pacifici, A. Irrera, M. Miritello, G. Franzó, F. Priolo, D. Sanfilippo, G. Di Stefano, and P. G. Fallica, Appl. Phys. Lett. 81, 3242 (2002) 60. J. Lee, J. Shin, N. Park, IEEE J. Lightwave Technol. 23, 19 (2005) 61. Hak-Seung Han, Se-Young Seo, Jung H. Shin, and Namkyoo Park, Appl. Phys. Lett. 81, 3720 (2002) 62. P. G. Kik and A. Polman, J. Appl. Phys. 91, 534 (2002) 63. H. Lee, J. H. Shin, and N. Park, Opt. Exp. 13, 9881 (2005) 64. Maria Eloisa Castagna., Salvatore Coffa, Mariantonietta Monaco, Anna Muscara, Liliana Caristia, Simona Lorenti, Alberto Messina, Materials Science and Engineering B105, 83 (2003). 65. F. Iacona, G. Franzò, E.C. Moreira, and F. Priolo: J. Appl. Phys. 89, 8354 (2001) 66. C. A. Barrios and M. Lipson, Opt. Exp. 13, 10092 (2005) 67. A. Polman, B. Min, J. Kalkman. T. J. Kippenberg, and K. J. Vahala, Appl. Phys. Lett. 84, 1037 (2004) 68. S. G. Cloutier, P. A. Kossyrev, and J. Xu, Nature Materials 4, 887 (2005) 69. C.J. Oton, D. Navarro-Urrios, M. Ghulinyan, N. E. Capuj, S. Gonzales-Peres, F. Lahoz, I. R. Martin, and L. Pavesi, Appl. Phys. Lett. (2006) 70. H. Park, A. W. Fang, S. Kodama, and J. E. Bowers, Optics Exp. 13, 9460 (2005); A. W. Fang, H. Park, R. Jones, O. Cohen, M. J. Paniccia, and J. E. Bowers, IEEE Photon. Technol. Lett. (2006)

5 Silicon Single-Electron Devices Yasuo Takahashi*, Yukinori Ono, Akira Fujiwara, Katsuhiko Nishiguchi, and Hiroshi Inokawa Abstract Single-electron devices (SEDs) are attracting a lot of attention because of their ability to manipulate just one electron. They operate using a Coulomb blockade, which occurs in tiny structures made of conductive material due to electrostatic interactions between confined electrons. Although any kind of conductive material can be used, silicon is preferable in terms of integrated circuit applications because, on a silicon substrate, SEDs can be used in combination with conventional complementary metal-oxide-semiconductor (CMOS) circuits. In addition, the well-established technologies used for fabricating CMOS large-scale integrated circuits can be employed to make these small structures. Silicon SEDs are employed in two fields: memory and logic. The simple operating principle of SEDs, i.e., capacitive coupling, has meant that many kinds of logic and memory applications have been proposed and tested. Another important issue with SEDs is the accurate control of a single electron, which is a challenge that must be met by ultimate electronics. The current status of silicon-based SEDs is introduced.

1. INTRODUCTION

Highly sophisticated nanotechnology enables us to fabricate nanometer scale metal-oxide-semiconductor field-effect transistors (MOSFETs). The smaller size increases both the transistor operating speed and the large-scale integrated circuit (LSI) integration level, and consequently improves the performance [1]. However, as the performance improves, the power dissipation in a small silicon chip increases up to the cooling limit. In addition, it is essential to reduce the power consumption if we are to establish a ubiquitous communication society and we must realize devices excellent levels of performance. In general terms, in order to achieve a lowpower LSI, we have to reduce the operating voltage and total capacitance of the circuit including wiring, which means that we have to reduce the total charges

Graduate School of Information Science and Technology, Hokkaido University, Sapporo 060-0814, Japan, [email protected]


125

126

TAKAHASHI ET AL.

participating for the circuit operation. The single-electron device (SED) is a major candidate in this respect because it can control the electron flow by means of oneby-one electron tunneling. The SED operating principle makes it possible to use any kind of conducting material. Initially, metals and III–V compound semiconductors were investigated to establish the basic physics of transport through zero-dimensional conductors and to explore possible applications. When we consider practical SED use, it is beneficial to employ Si as the base material. One of the great advantages is that we can use continuously advancing fabrication technologies developed for CMOS LSIs. As an example, we can make low-dimensional structures using a high-quality silicon-on-insulator (SOI) wafer, which has a very flat and highly controlled thin Si layer. In addition, the use of Si enables us to make SED-MOSFET combined circuits. This enables us to use established circuit technology and produce new useful functionality of SEDs. The great advantages of Si SEDs fabricated using such technologies have already been demonstrated. Here, we outline the SED operating principles and then describe the techniques used for fabricating Si single-electron transistors (SETs), which are the simplest type of SED. The fabrication of nanometer scale Si dots enables the devices to operate even at room temperature. Many kinds of applications have been proposed as a result of employing these techniques and the variety of SED operational features. Memory is the simplest application, because single-electron memory, where one electron is memorized as one bit, is the ultimate goal. Logic applications are also attractive in terms of low-power consumption. Memory and logic applications are described in Sects. 4 and 5, respectively. The final topic is single-electron transfer and detection, which will enable us to achieve perfect control of a single electron, the ultimate challenge for electronics.

2. OPERATING PRINCIPLE OF SINGLE-ELECTRON DEVICES

The basic principle with respect to manipulating a single electron involves a Coulomb blockade and single-electron tunneling, which requires small islands connected via a tunnel barrier or a tunnel capacitor. Since the physics of this approach has been well reviewed [2–4], we briefly describe only the basic operating principles of a SET, which is the simplest SED. SETs should have a small island that can be made using any material (metals, semiconductors, and even certain molecules) as long as it is conductive. When the island is sufficiently small, the charging energy Ec needed for adding one electron to the island becomes large. Ec corresponds to half of the energy gap between two energy levels, where the electron numbers in the island differ by unity. In such a case, no additional electron can enter the island through the tunnel capacitor unless the potential of the island is reduced by an external bias. This phenomenon is known as a Coulomb blockade. SETs use this phenomenon to control the electron flow through an island. A schematic cross section of a SET and the equivalent circuit is shown in Fig. 1. The electrode with the normal capacitor is the gate, and

5. SILICON SINGLE-ELECTRON DEVICES

127

FIG. 1. Schematic cross section of a SET (a), and equivalent circuit (b).

the other two electrodes are the source and drain. The Coulomb blockade of a SET is determined by two tunnel capacitances, Cs and Cd, and the gate capacitance, Cg. Figure 2 shows a “Coulomb diamond” when the source terminal is grounded. In the rhombic regions, electron transfer is prevented because the number of electrons in the island is a fixed integer. Outside the Coulomb diamonds, the number of electrons in the island fluctuates between certain numbers. If the drain voltage is low enough, the current flows by means of one-by-one electron tunneling, i.e., the electron number changes only between two adjacent integers. As shown in Fig. 2, the maximum drain voltage for a Coulomb blockade state is given by e/CΣ, where CΣ = Cg + Cs + Cd is the total capacitance of the island. If we scan the gate voltage with a fixed small source–drain voltage, the Coulomb blockade states and the single-electron tunneling states appear alternately and the drain current vs. gate voltage characteristics exhibit a multipeak structure, as shown in Fig. 3. This is called Coulomb blockade oscillation. As understood from the principle mentioned above, the drain current is determined by the CgVg/e value, which corresponds to the number of excess electrons in the gate electrode. The drain current has its minimum value when CgVg/e is an integer because the Coulomb blockade occurs. Conversely, when CgVg/e is a half integer, the current flows because the Coulomb blockade is lifted. There are two criteria for observing the above characteristics. One is that the resistance of the tunnel capacitor must be sufficiently larger than the quantum

128

TAKAHASHI ET AL.

FIG. 2. Diagram of Coulomb diamond.

FIG. 3. Schematic drain vs. current gate voltage characteristics of a SET.

resistance Rq = h/e2 (~25.8 kΩ). Otherwise, the number of electrons in the island fluctuates because of the uncertainty relationship even in the Coulomb blockade regions. The other is that the charging energy Ec must be larger than the thermal energy. Otherwise, heated electrons tunnel through the barriers and the Coulomb blockade does not occur. This means that the current peaks in Fig. 3 broaden and finally become indistinct as the temperature rises. This relation is expressed as Ec = e2/(2CΣ) > 3.5kT. When the island is assumed to be a sphere with a diameter d and embedded in a dielectric material with a dielectric constant ε, the selfcapacitance (nearly equal to CΣ) is given by 2pε0εd. Thus, a smaller island results in a higher Ec, and operates at a higher temperature. For room-temperature (T = 300 K or kT = 25.9 meV) operation, d should be less than 14 nm for SiO2 dielec-


129

FIG. 4. Single-electron box with one tunnel capacitor (a), and double tunnel junctions (b).

trics (e = 3.9). Controlling the size of such a small structure is a technological challenge in Si-based SETs. SEDs have two applications. One is a memory device called a “single-electron memory,” and the other is a single-electron logic device. The single-electron memory sometimes uses a single-electron box (SEB) structure, which has one tunnel capacitor as shown in Fig. 4a. If the device has only one island, it dose not act as an electron trap for a memory because the Coulomb blockade does not show hysteresis or bistable characteristics. We need at least two connected islands to stop the stored single electron escaping from the memory island as shown in Fig. 4b. We call the extra island a “barrier island.” Here, the Coulomb blockade state is effective in keeping a single electron in the memory node. As the number of islands connected in series increases, the single electron storage becomes very accurate due to the increase in the effective Coulomb blockade barrier as well as the reduction in the probability of co-tunneling, which is the higher-order tunneling against the Coulomb blockade effect.

3. FABRICATION OF SILICON SINGLE-ELECTRON DEVICES

The operating principle of SETs allows any conductive material to be used as an island. SETs were first demonstrated experimentally with a metal/oxide system in 1987 [5, 6]. The pioneering work on Si SETs was done in 1989 by Scott-Thomas et al. [7, 8], who also reported the first observation of Coulomb blockade oscillation in semiconductors. This oscillation in conductance was attributed to Si islands unintentionally formed in a narrow one-dimensional (1D) channel in a double-gate Si MOSFET. In 1991, similar characteristics were observed in a double-gate Si MOSFET with a point contact [9]. Previously, in 1990, Meirav et al. [10] reported on a SET fabricated with a GaAs/AlGaAs two-dimensional (2D) electron-gas system. The operating temperature of these early era SETs was below 1 K because the Coulomb islands were insufficiently small. The reason is that the minimum feature size of the lithography was employed to make two point contacts in order

130

TAKAHASHI ET AL.

to use them as tunnel capacitors, and this made the island much larger than the minimum feature size. Over the last 10 years, these devices have been effective in clarifying the mesoscopic physics of quantum dots formed in a 2D electron-gas system of compound semiconductors, because this temperature is sufficiently high for physics research. In terms of practical circuit applications, an operating temperature of less than 1 K is too low. To date various processes for fabricating Si-based SETs have been proposed and the characteristics of the fabricated devices have been examined. Most of these studies aimed at high-temperature SET operation, typically in the 4 K to room temperature range. The size of Si Coulomb islands must be of the order of 10 nm or less. Although it is not easy to fabricate such small sizes with good reproducibility, miniaturization has been the continuous strategy when developing conventional Si LSIs. In accordance with this strategy, many kinds of fabrication technologies designed to realize small sizes have been developed and put to use. Historically speaking, research on Si SETs has focused on achieving the high-temperature operation of SETs and this still remains the challenge. There are two ways to make a small island; lithographically or by using self-organized nanostructures. Lithography is the most direct way of forming miniaturized structures because it allows us to design the device structures and circuits. It also has the merit of compatibility with current LSI technology. Nevertheless, the minimum feature size even of sophisticated electron-beam (EB) lithography is of the order of 10 nm, which is too big for a tunnel junction. The use of self-organized nanodots makes it easy to obtain small islands. Small nanometer-scale conductors, such as C60, carbon nanotubes, and gold clusters, can be used as SET islands. The use of Si nanocrystals or small Si islands nucleated by the decomposition of SiH4 gas has been demonstrated. The tunnel current through a single Si nanocrystal on a substrate has been measured with an atomic force microscope with a conductive tip. The observation of negative differential conductance (NDC) [11] and Coulomb staircases [12] has been reported. SETs using Si nanocrystals can be made using the structure shown in Fig. 5. Dutta et al. [13, 14] reported a clear Coulomb diamond that they obtained by depositing Si nanocrystals about 8 nm in diameter on a substrate using VHF-plasma CVD, on which source and drain electrodes with a narrow gap had been formed. Several Si nanocrystals bridged the gap and acted as Coulomb islands. SET characteristics with an Ec of a few tens of meV were observed. The

FIG. 5. SET fabricated using Si nanocrystals.


131

most crucial issue when applying Si nanocrystals to SETs is to find a way of citing them in the desired location. Random deposition makes it difficult to fabricate SETs with the same parameters, for example tunnel capacitance and resistance, because the position of the Si island affects them strongly. Selective deposition techniques might allow the island position to be accurately controlled. One of the simplest ways to form islands without nanometer-scale lithography is to use multiple Si islands formed automatically in an ultra-thin layer. The pioneering work on this technique was performed by Yano et al. with a very thin polycrystalline silicon layer, in which some relatively large grains act as a current channel and some small grains act as single-electron islands or SETs. If we use the small islands as barrier islands, as shown in Fig. 4b, the device also works as a single-electron memory. Uchida et al. [15] adopted a similar approach to SET fabrication, but used a thin SOI layer. They used a chemical treatment to introduce a nanometer-scale undulation in a 3-nm-thick SOI layer. They ascribed their obtained Ec of 35 meV to Si islands that formed as a result of fluctuations in the quantum confinement energy due to SOI thickness variations. The merit of these methods based on natural and random formation is the ease with which they can provide nanometer-size Si islands. However, similar to Si nanocrystals, they are somewhat unsuitable for SET fabrication because the Si islands cannot be accurately positioned at a desired location. The methods are suitable for memory applications, which will be described in Sect. 4. With SET fabrication using the lithographic approach, in addition to tunnel barrier formation, one of the biggest problems is the realization of the three-dimensional (3D) confinement. In the first stages of semiconductor-based SET fabrication, the use of 2D electron gas was investigated. The first reported Si SET used a double-gate MOSFET [7]. The use of an inversion layer is the simplest way to achieve vertical confinement. In addition, tunnel barriers can be formed by the surface potential, which is controlled by the electric field from the gate electrodes. This method can form an SET island and tunnel barriers electrically. A promising way of further reducing the island size is to use a 2D SOI layer instead of bulk Si wafers. Since SiO2 has a much larger bandgap energy (9 eV) than Si (1.1 eV), strong physical confinement is possible. Recent progress on high-speed and low-power CMOS technology has produced high-quality SOI wafers, such as separation by implanted oxygen (SIMOX) or bonded SOI wafers. One possible structure is shown in Fig. 6. The lower narrow gates produce the tunnel barriers by applying a negative bias, and the positive bias of the top gates forms an island in the SOI layer between the two narrow gates. Kim et al. [16, 17] fabricated SETs with two narrow self-aligned gates on Si wire formed by using an SOI wafer, which exhibited clear SET characteristics. Lee et al. [18, 19] reported another device with a different arrangement of the lower narrow gates; side gates. The great advantage of these structures is that we can tune the tunnel barrier height by controlling the gate voltage, which enables us to control the tunnel resistance over a wide range. This can be employed for the accurate control of single-electron transfer from one electrode to the other, which will constitute the ultimate low-power electronics of the future. In fact, Fujiwara et al. [20] demonstrated control of island and tunnel barrier formation by using 1D Si wire with ultra-fine gates.

132

TAKAHASHI ET AL.

FIG. 6. Schematic bird’s-eye view of a SET formed electrically by using SOI and small gates (a) and schematic cross section (b). A SET island and tunnel barriers are formed by the electric field induced by the small gates. In some cases, top gates are used to generate electrons in the SOI layer.

FIG. 7. Schematic bird’s-eye view of a SET formed by the constrictions (a) and equivalent circuit (b). The potential barriers to confine the electrons in the island and to be tunnel barriers are formed in the constricted regions (point contacts) by the quantum size effect.

Another way to construct a semiconductor island and tunnel barriers involves the use of the quantum size effect in a physically formed constriction. When we form a narrow constriction or wire structures as shown in Fig. 7, the effective electrical potential increases due to the quantum size effect. This type of SET was first demonstrated by Ali and Ahmed using a 1D SOI wire, which has a vertically modulated structure [21]. They made a uniform 1D Si wire by EB lithography and dry etching. Then, two narrower parts were formed in the Si wire, again by using EB lithography and etching. These parts were expected to act as tunnel barriers as a result of the quantum size effect. The obtained Ec was 1.6 meV and not much


133

higher than that of SETs on bulk wafers since the island size was still limited by the lithography. The Coulomb blockade effect was observable up to a few K. The pattern-dependent oxidation (PADOX) method is a special approach for making small SETs using lithography. Takahashi et al. [22–25] demonstrated the first observation of Coulomb blockade oscillation at room temperature. The process is simple: it involves the thermal oxidation of a short Si wire, whose two ends are connected to wide Si layers. The thermal oxidation of Si is one of the most stable processes in the field of LSI technology. It is widely known that the oxidation of Si depends on mechanical stress that accumulates due to the volume expansion that occurs during the oxidation [26]. Since the influence of oxidation-induced stress becomes enormous when a nanometer-scale Si structure is oxidized [27, 28], the way in which the oxidation proceeds is strongly dependent on the initial Si pattern. Schematic diagrams of the device structure are shown in Fig. 8a. The initial Si wire was defined in an SOI layer by EB lithography and dry etching and was 30 nm wide, 30 nm high, and 30–100 nm long. Next, the Si wire was thermally oxidized in a dry oxygen ambient and then a polysilicon gate was formed over it. An electrical measurement of the device with the oxidized Si wire revealed that a Si island was effectively formed in the Si wire. The current–gate voltage characteristics are shown in Fig. 8b. Almost periodical current oscillations with relatively high conductance were observed. Ec was found to range from 10 to 50 meV, which was more than one order of magnitude larger than the previously obtained Ec value. The largest Ec corresponds to a 7-nm-diameter Si island with CΣ = 1.5 aF. Such a small dimension, which is below the lithographic limit, is possible because the size of the remaining Si is reduced as oxidation proceeds. This is one of the big advantages of thermal oxidation. Another important feature of PADOX is that the Cg value of the Si island had an almost linear relation with the designed length of the Si wire [23], which was the

FIG. 8. Schematic bird’s-eye view of initial structure of PADOX (a) and measured characteristics of a SET measured at 40 K and the drain voltage of 10 mV (b). A one-dimensional Si wire is formed between the two-dimensional Si source and drain layer. The Si wire is typically 30-nm thick and 40-nm wide. The length varied from 30 to 200 nm. The length of the measured wire is 70 nm.

134

TAKAHASHI ET AL.

FIG. 9. Relation between gate capacitance Cg and the designed length of the Si wire for SETs fabricated by PADOX.

first experimental result demonstrating the reproducibility of Si SET fabrication. The result is shown in Fig. 9. This strongly suggests that PADOX converts a Si wire to a Si island with a tunnel barrier at each end in a self-aligned manner. However, the result was surprising because the oxidized Si wire was still continuous between the Si pad layers and there was no constricted region in the Si wire. To explain the origin of the tunnel barriers, a model was proposed that takes account of the bandgap modulation of Si caused by quantum confinement and the oxidation-induced stress [29]. A schematic band diagram of the model is shown in Fig. 10. The model assumes that a single potential barrier (~50 meV high) is formed as a result of the quantum size effect in the Si quantum wire. The compressive stress (~20,000 atm.) [27] accumulates in the middle of the wire. This stress is expected to be lower around the ends of the Si wire because of the shear stress caused by the oxidation at the Si/buried oxide interface of the Si pad layers. Since the compressive stress reduces the Si-band gap, a potential well (~150 meV deep) is introduced at the middle of the barrier potential, resulting in double tunnel barrier potential. This model clearly indicated the importance of oxidation-induced stress when designing nanometer-scale Si devices. However, further experimental investigation is necessary to confirm the validity of the model. An asymmetric potential profile was suggested for the tunnel barrier from the bias dependence of the conductance of the fabricated SET [30]. PADOX led us to expect that various SETs could be fabricated by designing the Si pattern appropriately. Recently, with the development of an improved version of PADOX called vertical-PADOX (V-PADOX) [31, 32], this indeed proved to be true. V-PADOX utilizes the thermal oxidation of a relatively wide (>60 nm) Si wire with a modulated thickness. A diagram of the Si structure is shown in Fig. 11a. A thin region with a length of 10–60 nm is sandwiched between the thicker regions. Thermal oxidation affects this structure in two ways. First, the two edges of the thin region of the Si wire remain as twin 10-nm-size Si wires because the built-up stress suppresses their oxidation, whereas the center part is completely oxidized. Cross-sectional images of the thick and thin Si regions obtained with a transmission electron microscope


135

FIG. 10. Schematic top view of Si layer (a) and potential profile of the model of SET formation (b) by the oxidation-induced stress during the PADOX. Quantum size effect in the narrow Si wire increases the potential, but strong compressive stress reduces the band gap in the center of the wire. Experimental data show that the potential in the island is about 0.1 eV lower than that of the 2D layer when the wire is relatively long.

FIG. 11.Schematic bird’s-eye view of initial structure of V-PADOX (a) and cross-sectional TEM image of the relatively thick (b) and thin Si regions (c) after thermal oxidation at 900°C.

(TEM) are shown in Fig. 11b, c, respectively. Second, tunnel barriers are formed at both ends of the twin Si wires, probably due to the same mechanism by which SETs are produced by PADOX. Consequently, twin SETs are formed at the same time. A clear relation was observed between the Cg value of the Si island and the length of the thin Si region, which is evidence of the self-aligning formation of Si islands.

136

TAKAHASHI ET AL.

There have already been many reports on Si SETs with Ec values larger than a few tens of meV, which were fabricated based on 1D Si wires on a SOI wafer. Some of these reports focused on the effect of quantum confinement in the Si island because the size of the Si island is less than 20 nm. In several experiments, NDC was observed in the SET current [33–36] and its origin was discussed in terms of the nature of quantized energy levels. Leobandung et al. [37] reported a SET using a 1D Si wire with two lithographically defined constrictions. They observed Coulomb blockade oscillations with a gap energy of 40 meV, and estimated that about half of this energy resulted from the Coulomb blockade effect and the other half from the energy between the quantized levels caused by the confinement. They reported a single-hole transistor (SHT) with a similar structure [38]. Hiramoto and co-workers [39] reported a SET that employed 10-nm-wide and 100-nm-long triangular Si wires. Multiple island structures were formed due to some unknown randomness in the Si channel. They also reported a SET with Ec = 58 meV and discussed the quantum confinement effect in the Si island [33]. In their work, they employed a point contact defined by EB lithography and anisotropic etching as shown in Fig. 12. Since the device structure apparently did not include tunnel barriers, they suggested that the tunnel barrier formation is due to localized states or Si nanoparticles at interfaces, or PADOX. To obtain more information on the tunnel barrier, they investigated the characteristics of electron and hole currents in the same channel by using a SET with both n- and p-type source/drain contacts [40, 41]. They observed Coulomb blockade oscillations for both types of operation and concluded that tunnel barriers were formed for both electrons and holes. The p-type versions should be called SHTs. More recently, they reported a room temperature operated SHT and NDC in which they achieved smaller island sizes [42–44]. Although the mechanism of the SHT island formation is not clear, they insisted on the possibility of mechanisms other than oxidation-induced stress in PADOX. A great advantage of semiconductor SEDs is that we can use the quantum size effect. Since the energy separation caused by the quantum size effect is in inverse

FIG. 12. Schematic bird’s eye view of initial structure of Si SET proposed by Hiramoto and co-workers. Room temperature operated SHTs have been fabricated using the structure.


137

proportion to the square of the size, the effect will support an increase in the operating temperature in ultra-small semiconductor islands. However, this can be regarded as a problem from an application point of view because it is likely to introduce some complex irregularity in the Coulomb blockade oscillation, which is periodical with metal-based SETs. As described in Sect. 2, periodical oscillation characteristics are quite usable. One approach to avoiding such a complex feature might be the use of doped Si wires on SOI wafers. Rather periodical Coulomb blockade oscillations can thus be obtained similar to those of SETs with a single metal island [45–47]. This might indicate that doping is useful for obtaining a periodical Coulomb blockade oscillation, although the Ecs of these SETs were less than 15 meV and insufficiently large to be strongly affected by quantum confinement. It should be noted that an undoped SET with a similar Ec value also showed a rather periodic Coulomb blockade oscillation [22], except in the few-electron regime where the electron number in the Si island is small. It is important to investigate the quantized energy states in an ultra-small Si dot and the effect of doping. We should add that NDC, probably caused by the quantum confinement effect, might be useful for some circuit applications. When we use lithography to form SEDs it must be in a controlled way. It is widely recognized that SETs are formed in a small Si structure as a result of the formation of a tunnel barrier by certain fluctuations; such as potential modulation by quantum confinement, mechanical stress, and ionized impurities. Even if Coulomb blockade oscillation is successfully observed in a structure designed to produce tunnel barriers, this might be due to some unexpected mechanism. We emphasize the importance of clarifying the relationship between the electrical characteristics and the structural parameters, which will guarantee the controllability of the fabrication process. At present PADOX and V-PADOX are the most promising methods in this respect. Although they are reproducible to a certain extent, the tunnel barrier formation mechanism has not been completely determined and is still controversial. Further investigation is also needed to achieve size reduction. The most important feature of Si SETs is their stable operation. It has often been said that a SET is too sensitive to even a small charge to operate stably. This is sometimes called offset charge instability or background charge instability. It is widely known that metal-based SETs are strongly influenced by mobile offset charges even when the SETs are kept at temperatures lower than 4.2 K [48]. The Coulomb blockade oscillation originates from the one-by-one change in the stable electron number in the Coulomb blockade island. The offset charges probably add a random phase offset to this oscillatory characteristic. If the offset is a large fraction of 1e, the operation point of the SET changes significantly. This argument has led to a very pessimistic view regarding the practical use of SETs in electronic circuits [4]. Recently, the long-term stability of Si SETs fabricated by PADOX was investigated. The devices showed a drift of current characteristics less than 0.01e over some weeks [49]. This excellent stability is a very advantageous characteristic of Si SETs.

138

TAKAHASHI ET AL.

4. SINGLE-ELECTRON MEMORY

The small size of SEDs has led to their use as memory devices. If we can establish the technology for assigning one electron to one bit, this will provide us with the ultimate small and low power memory. Single-electron memories are believed to be devices with a small island or so-called SEB. Figure 4a shows the simplest structure, which an electron can enter and leave through a tunnel capacitor. If the tunnel capacitor is replaced with a MOSFET, the device is a conventional dynamic random access memory (DRAM) cell, in which we can regard a short-channel MOSFET as a tunnel capacitor with a tunable barrier height. As shown in Fig. 6, a tunnel barrier formed by an electric field is such a case. Consequently, there are no structural differences between single-electron and conventional memories. We should consider a single-electron memory to have a small memory node that contains only a small number of electrons. Another important demand as regards a single-electron memory is that it should have a highly sensitive electrometer in order to detect the small charges of stored electrons. SEDs, because of their high sensitivity to even a single electron, can also be used in charge sensing schemes. There are various types of single-electron memory in addition to that shown in Fig. 4b. Recent progress on MOS memory devices has increased the scale of DRAM integration beyond 1 Gbit. However, their complicated fabrication processes have contributed to the demand for new small memories. In terms of mobile applications, flash memory has become usable as a nonvolatile memory, because it can keep the electrons without the support of a voltage supply. However, the scaling limit as regards the tunnel oxide of a flash memory [50] is crucial if we are to increase the integration level. With the above as a basis, a great deal of attention has been concentrated on floating-node type approaches, where a limited number of electrons are stored in the floating memory node and the presence of a charge is detected with a charge-sensing device [4, 51]. 4.1. Multi-Nanodot Memory A crucial issue with the flash memory is tunnel oxide degradation. Since the memory node is a polysilicon sheet, even a small leak in part of the tunnel oxide layer enables all the stored electrons to escape. Tiwari et al. [52, 53] proposed and demonstrated the use of multisilicon nanocrystals as a memory node instead of a polysilicon sheet as shown in Fig. 13. Since the memory node is divided into small pieces, the leakage of stored electrons through a defect in the tunnel oxide does not propagate. The principle of the operating characteristics is the same with flash, i.e., there is a discrete threshold voltage shift corresponding to single and multiple electron storage in each dot. A thin tunnel oxide leads to a small write voltage, and is also expected to improve robustness [54, 55]. The unexpectedly long retention time (e.g., more than a week at room temperature for 1.6-nm tunnel oxide), which might result from the storage of injected electrons in the deep trapping centers [56, 57], also encourages use as a nonvolatile memory.


139

FIG. 13. Schematic cross-section of multidot or nanocrystal memory with a MOSFET as a chargesensing device.

Since the small size, small size distribution [58], and large density (total area) [59] of nanocrystals are important in achieving an effective Coulomb blockade, uniform charging, and a large threshold voltage shift, respectively, many nanocrystal fabrication techniques have been investigated. Low-pressure chemical vapor deposition (CVD) is the most common, but different underlayers, such as SiO2, HF-treated SiO2 [60], Si3N4 [61], oxynitride [62], and Al2O3 [63], have been examined. Other techniques include remote plasma-enhanced CVD [64], aerosol fabrication [65], annealing of silicon-rich oxide [66], ion implantation of Si, Ge, or Sn into SiO2 followed by annealing [67, 68], and Ge implantation into Si followed by oxidation [69]. One approach to relaxing the trade-off between write/erase and retention times is the use of a double or multiple tunnel junction electron box (Fig. 4b). Ohba et al. [70] fabricated doubly stacked dots in a self-aligned manner, and observed improved retention. But further optimization of the device structure is needed to confirm the overall merit of this scheme. A reduction in the nanocrystal memory device width has led to the single-dot memory [71–73], which is a combination of a single-junction electron box (Fig. 4a) and a narrow-channel MOSFET charge-sensing device. One refined example, which was reported by Guo et al. [71] and Nakajima et al. [72], is shown in Fig. 14. A small silicon dot is located just above a narrow (~10 nm) single-crystal MOSFET channel. A quantized shift in the threshold voltage, which can be attributed to single-electron charging, is clearly observed at room temperature. Yano et al. [74, 75] utilized an ultra-thin (~3 nm) polysilicon film to form a single-dot memory naturally. In such a thin film, there is a large fluctuation in thickness and also in electronic potential. As a positive bias is applied to the gate, a narrow percolation channel and an isolated island appear where the potential is low, and they work as a memory. A discrete threshold voltage shift caused by single-electron charging was observed at room temperature. They fabricated a 64-bit memory array to examine write/erase, retention, and endurance characteristics. The write/erase time was typically 10 μs, resulting in a data-transfer capability of two orders larger than that of typical flash memories. The retention time was typically 1 h to a month. Their memory showed excellent endurance in the face of repeated write/erase cycles, i.e., there were no obvious changes in the threshold

140

TAKAHASHI ET AL.

FIG. 14. Schematic bird’s-eye view (a) and cross-section (b) of single dot memory with a narrow-channel MOSFET as a charge-sensing device.

voltages in the write/erase states even after a 107-cycle operation. They also showed the usefulness of the verify operation in compensating for device-to-device variations in the naturally formed structure. Their work showed the feasibility of silicon-based SEDs operating at room temperature in the early 1990s, which stimulated other researches in this field. 4.2. Memories Using a Single-Electron Transistor as a Sensing Device A SET is a good choice as a detector for small stored charges as well as a MOSFET. Figure 15 shows a simple example of an equivalent circuit of an all SET-based single-electron memory. Double or multiple tunnel junctions are needed as an electron trap for a memory node, which is the same as seen in Fig. 4b. Stone and Ahmed [76] reported a memory device that had a memory node with a multitunneling junction (MTJ) formed in a narrow Si wire. The electrons stored in the memory node are detected by another MTJ SET. The Coulomb blockade of the MTJ keeps the electrons in the memory node at 4.2 K. A shrunken version of the memory with a double-tunnel-junction electron trap was fabricated by Fujiwara et al. using the PADOX process [77]. The equivalent circuit and measured characteristics are shown in Fig. 16a, b, respectively. It comprises a double-tunnel-junction electron trap and a SET charge sensing device, and one tunnel junction is shared by the trap and the SET. The oscillatory conductance vs. gate voltage characteristics of the SET when operating at 30 K showed the hysteresis associated with the multistability of the number of stored electrons. In addition, as shown in Fig. 16a, jumps in the detected current caused by the single-electron tunneling between the memory node (memory island) and the detector SET island were clearly observed on the timescale. A SET sensing device was fabricated together with a write/erase MOSFET by Takahashi et al. [78]. Figure 17a, b shows a SEM image of the device and the


141

FIG. 15. SET-based single-electron memory.

FIG. 16. Equivalent circuit (a) of shrunken version of SET-based single electron memory. Measured current vs. Vg characteristics, where Vg was scanned forward and then backward at 30 K show hysteresis together with some jumps due to single-electron tunneling (b).

FIG. 17. Scanning electron micrograph image of a memory with a write/erase MOSFET and SET sensing device (a) and simplified equivalent circuit.

142

TAKAHASHI ET AL.

FIG. 18 Measured characteristics of the SET current representing the “write” and “storage” action of the memory shown in Fig. 17.

corresponding circuit diagram, respectively. This particular device was also fabricated by the PADOX process. The wire region of the SET was initially 100-nm long and 40-nm wide, and the memory node also had the same dimensions. The gate length of the 1D-wire MOSFET was 50 nm. Figure 18 shows the hysteresis characteristics of the SET current representing the “write” and “storage” operations at 40 K. Initially, at the lower-gate voltage Vlg of −2.7 V, the MOSFET cuts off and the storage node is not charged. As Vlg increases, the SET current also increases due to the capacitive coupling between the lower gate and the SET island. When Vlg exceeds −2.4 V, the MOSFET channel becomes conductive and electrons flow into the memory node, lowering the potential of the Coulomb island and causing a drop in the SET current. Even after Vlg is swept back to its initial value of −2.7 V, electrons are kept in the memory node and the charged state is clearly distinguished from the discharged state by the reduced SET current. Even a narrow write/erase MOSFET channel is expected to operate quickly because the stored charge is small as a result of the high charge sensitivity of the SET. In addition, the sharp subthreshold characteristics of the wire MOSFET should result in a long retention time and low operating voltage. 4.3. Multiple-Value Memories Using a Single-Electron Transistor In the tradition of DRAM, a combination consisting of a write/erase MOSFET (Fig. 19) and a sense MOSFET (Fig. 13a) is called a “gain cell” [79, 80]. The concepts behind the memories shown in Figs. 17b and 19 are the same. Since the charges in a storage capacitor are not directly shared by the bit-line capacitance in the read operation, the difficulty of obtaining a large storage capacitance is avoided. Although the gain cell has been expected to provide a memory for future generations, it has been very difficult to make a write/erase transistor with a minimal leakage current and a small area.


143

FIG. 19. Circuit diagram of a DRAM cell with a gain cell.

FIG. 20. SEM image of revised version of memory shown in Fig. 17.

Now, SEDs offer a way to meet this challenge. One of the great advantages of single-electron memory, as shown in Fig. 20, is that we can add a new function of multiple values representing a number of stored electrons, which enables the memories to reduce their chip size. Nishiguchi et al. demonstrated a shrunken version of the memory device shown in Fig. 17 that allows single-electron storage and detection. When another wire MOSFET is added, as shown in Figs. 20 and 21, the device works as a multiple-valued memory as shown in Fig. 22 [81, 82]. The fourfold increase in the SET current indicates that three electrons are transferred one by one from the side electrode to the memory node by turning two wire-MOSFETs ON and OFF alternately. This single-electron transfer can be achieved by the Coulomb blockade in the small island formed electrically between “OFF”-state MOSFETs. The subsequent reduction in the SET current, namely electron emission from the memory node to the side electrode, can be achieved just by changing the voltage applied to the side electrode. This demonstration, which corresponds to the function of a four-level (2-bit) single-electron memory, promises to provide a memory with

144

TAKAHASHI ET AL.

FIG. 21. Equivalent circuit of a multivalue single-electron memory cell with a gain cell.

FIG. 22. Measured characteristics of electron storage and emission using a multivalue single-electron memory cell at 26 K. VF and VR were −0.7 and 2 V, respectively. The inset shows a schematic of single-electron transfer.

unique advantages, e.g., arbitrary control of memory information, thereby leading to the simple and quick operation of data-write/erase and -verify processes. The miniaturization of the electrically formed island using lithography and electron confinement with multigates allowed the room temperature operation of an 11-level (>3-bit) memory as shown in Fig. 23. Noteworthy features are fast transfer (104 s) (Fig. 23b), which had been conflicting features in flash-type single-electron memories owing to their constant tunnel resistance. The achievement of both fast transfer and long retention result from the variable resistance of the MOSFET’s channels; i.e., the channels become very transparent when electrons are transferred, while they become insulative when electrons are stored in the memory node. Moreover, the transferred single electrons were detected at room temperature because of high charge sensitivity caused by the SET island as well as careful cell design, e.g., the small self-capacitance of the memory node and the narrow gap between the memory node and the SET island. This multiple-valued memory promises not only a huge memory capacity but also


145

FIG. 23. Measured characteristics of (a) fast transfer and (b) long retention using a multivalue singleelectron memory cell at room temperature.

FIG. 24. Equivalent circuit of a multivalue SRAM cell.

ultra-low-power consumption because of a few orders of magnitude reduction in the number of stored electrons and the data-refresh process, compared with those of conventional DRAMs. Inokawa et al. proposed and demonstrated a different type of a multiple-valued memory [83, 84]. Figure 24 shows a static multiple-valued memory comprising a SET and a MOSFET. The operating principle is completely different from that of the above-mentioned single-electron memories, but can be easily understood by regarding the SET and MOSFET as circuit elements. A MOSFET with a fixed gate bias Vgg is used to keep the SET drain voltage nearly constant at Vgg−Vth, where Vth is the threshold voltage of the MOSFET. We can set the SET drain voltage (Vgg−Vth)

146

TAKAHASHI ET AL.

sufficiently low to maintain the Coulomb blockade condition. As a result, the current flowing through the circuit is determined only by the SET input voltage; it is unaffected by the output voltage. When the input and output terminals are shorted together, multipeak negative differential resistance is attained in the form of two-terminal characteristics. With a proper load device (a constant-current source in Fig. 24), many stability points appear and this circuit works as a multiple-valued memory. This particular device was fabricated by the PADOX process and operated at 27 K. The measured characteristics in Fig. 25 show six stability points each of which produce a corresponding output voltage. This is advantageous because the number of stored electrons is converted to some quantized voltage. The application field of static memories, which feature a fast and simple write operation and stable retention, will be different from that of floating-node-type memories. The combined SET-MOSFET circuit is advantageous for SET applications, because a MOSFET recovers the low drivability and low voltage gain of SETs. Other uses are described in Sect. 5.

5. SINGLE-ELECTRON LOGIC

There is a need for low-power logic LSIs due to the increase in the number of transistors that they incorporate. The biggest problem for future CMOS LSIs is the power that will be dissipated in their huge number of integrated transistors. Even in low-power CMOS circuits, where more than 1 billion transistors are integrated, a huge amount of power is consumed that approaches the cooling limit. In order to increase the operating speed for the massive transfer of information that will be required in the future and for wearable applications, we must find a way to reduce power consumption. SEDs constitute one candidate for such integrated logic devices.

FIG. 25. Measured characteristics of SET-MOSFET combined multiple-valued SRAM.


147

A SET, which can be controlled by a gate, can be used as a simple switch in the same way as a MOSFET. The highly sophisticated CMOS digital technology has become established through its use in personal computers and cellular phones. Great advantages can be realized if we can employ these accumulated full-fledged technologies developed for CMOS circuits to SET circuits [85–90]. From the viewpoint of single electronics, SET has novel features that conventional transistors do not have. Since the basic principle of SET operation is the Coulomb blockade, in which the gate capacitance controls the charging states of the island, the device can have many gates. This enables the device to have many inputs and to offer high functionalities. In addition, as shown in Fig. 3, SET has oscillatory characteristics corresponding to the number of electrons in the island. This is also difficult to obtain with other devices. Many methods for realizing single-electron logic have been proposed and analyzed for SEDs since it allows a large variety of system architectures and circuit designs. The basic operation of some of these approaches has been demonstrated using actually fabricated devices. Here, we focus mainly on these devices. 5.1. SET-Based Logic A SET acts as a three terminal device in the same way as a conventional transistor. When we connect a load resistance to a SET, we can define the voltage gain of the SET [8]. This parameter is explained using the electrical characteristics of a SET. As shown in Fig. 2, when the applied voltage increases, currents begin to flow at the edge of the Coulomb diamond. As a result, the output drain voltage Vd for a fixed input drain current Id exhibits a Coulomb diamond as a function of the gate voltage Vg. The measured characteristics for a SET using the V-PADOX method are shown in Fig. 26. The two slopes of the graph (Figs. 2 and 26a) correspond to the maximum inverting voltage gain GI and the noninverting gain GNI. These values are determined by the SET parameters shown in Fig. 1b as GI = Cg / Cd ,

(1)

GNI = Cg / (Cg + Cs ).

(2)

Although GNI is always smaller than unity, GI can exceed unity if Cg > Cd. Consequently, we can make logic circuits based on inverters, in the same way as that used for CMOS-type logic. Equation (1) makes it clear that a SET has to have larger Cg to obtain a higher inverting gain. This means that the total capacitance of the SET island tends to increase. Therefore, the voltage gain and the operating temperature are in a trade-off relationship and it is not easy to make SETs with a larger than unity gain that operate at high temperatures. Although a GI value larger than unity has been achieved in metal-based [91, 92], GaAs-based [93], and Si-based SETs [94], they operate at temperatures below 4 K. However, the V-PADOX process has enabled us to make SETs with voltage gains as high as 4 at around 30 K [95], and recently Harata et al. [96] reported a voltage gain of about 5 at room temperature by using the SHT shown in Fig. 12.

TAKAHASHI ET AL.

148

FIG. 26. Electrical characteristics of a SET fabricated by the V-PADOX process. The output drain voltage Vd for a fixed input drain current Id of ±10 pA (a), and the output drain current Id for a fixed drain voltage Vd of 10 mV (b) as a function of the gate voltage Vg measured at 27 K.

The current cutoff characteristics are determined by the subthreshold slope S in the Id−Vg characteristics that rise and fall nearly exponentially at the tails of the peaks. Figure 26b shows the output drain current Id for a fixed input drain voltage Vd plotted as a function of Vg on a logarithmic scale. At a sufficiently low temperature and high tunnel resistance, S is given by S = [d(ln I d ) / dVg ]−1 = (CS / Cg )kT / e.

(3)

This equation is very similar to that for a MOSFET. It also indicates that we need a high inverting voltage gain GI to obtain a steep subthreshold slope. If Cs is equal to Cd, a GI of 4, which is possible by using a PADOX SET, corresponds to a CΣ/Cg of 1.5, or S= 90 mV per decade, at room temperature. One different feature of SETs is that the low-current region is limited by the existence of the next peak, which may cause a relatively large off current. However, if we use the first-electron peak, an infinitely low current can be achieved as with a MOSFET. Another important drawback of SETs is that the drain current is limited by the tunnel resistance, which has to be larger than the quantum resistance h/e2 (25.8 kΩ) to maintain the Coulomb blockade condition. This makes the signal response very slow when the outputs are connected to a heavy load such as long wiring. The applicable drain voltage is also limited to a value smaller than e/CΣ. This is an


149

FIG. 27. Equivalent circuit of the combined SETMOSFET inverter.

obstacle to driving a series of SETs with a small voltage gain or external circuits that require a high input voltage. SET-MOSFET logic circuits have been proposed as a way to overcome this drawback [37, 38]. The combined SET-MOSFET circuit used as a multiple-valued memory (Fig. 24) can be employed. Figure 27 shows the equivalent circuit of the combined SET-MOSFET inverter with a constant current load I0. A MOSFET with a fixed gate bias Vgg is connected to the drain of a SET. The MOSFET keeps the SET drain voltage sufficiently low to maintain the Coulomb blockade. Since the drain voltage is almost independent of the output voltage Vout, a large output voltage and voltage gain can be obtained. The device operation was verified by employing the same SET-MOSFET circuit as that used for the multiple-valued memory demonstration shown in Fig. 25. Figure 28 shows the input–output characteristics of a combined SET-MOSFET inverter with a constant current load of 4.5 nA and a Vgg of 1.08 V. This is an n-type MOSFET with an effective channel width of 12 mm, a channel width of 14 mm and a gate oxide thickness of 90 nm. The threshold voltage Vth and the transconductance Gm(MOS) of the MOSFET at the drain voltage of 3 V is 1.07 V and151 mS, respectively. The output voltage Vout and output resistance of the combined SET-MOSFET inverter are given by [97] Vout = −Gm(SET) Rd(SET) (1 + Gm(MOS) Rd(MOS) )Vin ,

(4)

Rout = Rd(MOS) + (1 + Gm(MOS) Rd(MOS) ) Rd(SET) ,

(5)

where Gm(SET) is the transconductance of the SET and Rd(SET) and Rd(MOS) are the drain resistances of the SET and MOSFET, respectively. The voltage gain of the SET is

150

TAKAHASHI ET AL.

FIG. 28. Id−Vg characteristics of a combined SET-MOSFET inverter with a constant current load of 4.5 nA at 27 K.

multiplied by that of the MOSFET, which means that the voltage gain of the SET–MOSFET inverter becomes very large because of the large voltage gain of the MOSFET. In fact, the measured voltage gain of the SET–MOSFET inverter is about 40 as seen in Fig. 28. The important point is that a large voltage gain can be easily obtained while preserving the oscillatory I−Vg characteristics. A SET-based logic can be made by employing the voltage gain. The simplest SET-based logic is one that uses single-gate SETs and resistive loads [89, 98]. Nishiguchi and Oda [99] fabricated an inverter based on this logic on a SOI wafer. The SET consists of a small Al island made by evaporation using a self-alignment technique, and two leads made of the SOI layer. A larger than unity gain was achieved at 5 K, although the logic swing was small. A CMOS-type circuit is advantageous in terms of obtaining a higher voltage gain. If the oscillation phase of a SET is controllable, we can use the SET as both an n-switch and a p-switch [86]. Ono et al. [100] demonstrated a Si-based inverter fabricated using the V-PADOX process. Figure 29a, b shows an AFM image and the equivalent circuit of the inverter. The two SETs with a voltage gain of about 2 were packed in a very small (100 × 200 nm) area. As shown in Fig. 29c, the input and output transfer curve attains both a larger than unity gain and a full logic swing at 27 K. A NAND gate was also reported by Stone and Ahmed [101]. This was fabricated on an SOI wafer on which four MTJ-SETs were integrated. The fundamental operation was achieved at 1.6 K, although the voltage gain was lower than unity. The inverter shown in Fig. 29 needs control gate terminals, which sometimes complicate the circuit design. One proposed solution is to use a floating gate instead of the control gate as shown in Fig. 30 [15, 102]. The floating gate, which is sometimes a small island or a dot, is attached to the SET island so that it couples with the SET island capacitively. Charges are injected into the floating gate from the island [102] or other electrodes [15] and these shift the oscillation phase of the SET. Consequently, we have to control the amount of the injected charge so that the two SETs operate in a complementary manner. Another technique for controlling the oscillation phase of a SET uses the feedback of the output voltage to the control gate, which allows automatic phase control [103, 104]. The basic circuit is shown in Fig. 31. A small memory node coupled capacitively to the SET is connected to the MOSFET (MN-FET), which acts as a switch for charging


151

FIG. 29. AFM image of a Si CMOS-type inverter fabricated by the V-PADOX process (a), an equivalentcircuit (b), and input–output transfer curve measured at 27 K (c).

FIG. 30. Equivalent circuit of the quasi-CMOS inverter where a floating gate (dot) is attached to each SET.

or discharging the memory node. In the feedback cycle, the output terminal is connected to the gate of the MOSFET, and, at the same time, an appropriate voltage is applied to the input gate of the SET. When the output voltage is high, the MN-FET is turned ON, and charges are injected into the memory node. This changes the potential of the node, and the oscillation phase is shifted to turn the output OFF. When the output

152

TAKAHASHI ET AL.

FIG. 31. Equivalent circuit of the SET logic with a feedback loop, by which the oscillation phase is controlled automatically. The MN-FET gate is connected to the output terminal only when feedback is on, and it is connected to a low voltage source Voff to shut off the MN-FET.

signal is in the OFF state, the MN-FET is turned off automatically. This process controls the charges in the memory node so that the output signal is OFF. After that, the MN-FET gate is connected to a low voltage source Voff, which keeps the MN-FET OFF and also keeps the charges in the MN-FET. The precise phase of the oscillation is controlled by changing the input voltage applied to the gate of the SET. Nishiguchi et al. reported a further application of this scheme [104]. 5.2. Multigate SET and Pass Transistor Logic The principle of a SET means that the device inherently has multiple gates. We can use this characteristic to control the oscillation phase in the above-mentioned CMOS-type SET. Basically, SETs operate with a charge balance between the gate and SET island. The output current is determined by the sum of the product of the gate capacitance and the voltage applied to each gate, ΣCgiVgi, where Cgi and Vgi are the gate capacitance and the applied voltage of ith gate, respectively. We can exploit this special characteristic to construct multiinput devices [105]. In addition, we can employ another important feature of the oscillatory characteristics. The combination of the multigate configuration and the unique peak-and-valley structure in the Id−Vg characteristics makes the SETs highly functional. When one of the gates is positively biased by e/2Cgi, the Id−Vg curve shifts by 180° to a negative Vg, which makes the current state change from low to high, or from high to low. Provided that the many input-gate capacitances have the same value, Cg0, and the gate input amplitude is e/2Cg0, the SET is ON only when an even number of the input gates are biased HIGH (e/2Cg0), and the SET is OFF when an odd number of the input gates are biased HIGH. This logic function is an XOR gate. A dual-input XOR gate was experimentally demonstrated using PADOX [106]. Figure 32 shows a SEM image of a dual-gate SET fabricated by using the PADOX process. The equivalent circuit of the device is shown in Fig. 33a, where the two gates


153

FIG. 32. SEM image of a dual gate SET before (a) and after (b) formation of two input gates.

FIG. 33. Equivalent circuit of a dual gate SET (a), and its operating characteristics as an XOR gate (b).

are used as input gates biased at 0 and 0.2 V according to the ON and OFF states, respectively. The XOR function was confirmed in the output drain current at 40 K as shown in Fig. 33b. This SET XOR gate is a powerful component when we construct arithmetic units such as adders and multipliers because XOR is a half-sum, which is a lower order bit calculated by adding together two 1-bit binary numbers. Unless we use a combined SET-MOSFET circuit, it is impossible to obtain a high voltage gain in a multigate SET operated as an XOR. The CMOS-domino-type logic was proposed by Uchida et al. as a way of using SETs without a voltage gain [107]. A combinational logic circuit is built in a SET logic tree, where SETs are used as pull-down transistors. The point is that the tree is operated with a sufficiently small excitation voltage (or drain voltage) in order to make the Coulomb blockade effective. The output signal with such a small voltage is then amplified before being transferred to the next logic segment. The building block used to construct the logic is a directional current switch composed of two single-gate SETs. Such a current switch has been fabricated on SOI substrates and its function was confirmed at around 30 K [32,108, 109]. Also, basic logic operation, such as NAND, was performed using this scheme at 10 K [17].

154

TAKAHASHI ET AL.

FIG. 34. Equivalent circuit of one-bit sum (a) and carry-out (b) based on a pass-transistor logic scheme.

FIG. 35. Measured characteristics of one-bit sum (a) and carry-out (b) performed at 25 K.

A single-electron pass-transistor logic, where SETs are used both as pull-up and pull-down transistors, has also been studied. The fundamental circuit of the single-electron pass-transistor logic was fabricated using V-PADOX, and half-sum and carry-out for the half-adder has been demonstrated [110]. Figure 34 shows the equivalent circuits of half-sum and carry-out, and Fig. 35 shows their measurement data at 25 K. Both half-sum and carry-out are correctly output at 25 K. The significance is that the gate and total capacitances, and even the peak positions of the fabricated SETs, were well controlled for these operations. This is the first arithmetic operation performed by SET-based circuits. It was shown that the combination of multigate SETs and pass-transistor logic enables us to construct full and multibit adders in a very compact way [90], although circuits based on this idea have not yet been fabricated. 5.3. Multiple-Valued Logics Multiple-valued logics have potential advantages over binary logics with respect to the number of elements per function and operating speed [111, 112]. They are also expected to relax the interconnection complexity on the inside and outside


155

of LSIs. These are advantageous as they allow a further reduction in the power dissipation in LSIs and the chip sizes. However, their success has been limited, partially because the devices that were used (MOSFETs and negative differential resistance devices such as resonant tunneling diodes) are inherently single-threshold or single-peak, and are not fully suited for multiple-valued logic. The oscillatory behavior in the Id−Vg characteristics, in which the number of electrons in the SET island changes according to the oscillation cycles, suggests that SETs could be used in multiple-valued schemes. As described in Sect. 4.3, a quantized multistable voltage can be generated using the combined SET-MOSFET configuration. In fact, Inokawa et al. fabricated a literal gate and a quantizer using PADOX and demonstrated their operation at 27 K [113]. Figure 36a, b shows the measurement setup for the quantizer and its measured data, respectively. The triangular input VIN was successfully quantized into six levels. They also proposed the analog to digital converter (A–D converter) shown in Fig. 37, which uses a SET-based quantizer and literal gates. The simulation results predict that the operating speed is around 1 GHz and the power consumption is about 1/10,000 that of conventional high-speed CMOS A–D converters even when connected to a 1-mm-long wiring load [84]. Other circuit applications with highly sophisticated multiple-valued architecture have been reported by Degawa et al. They proposed highly flexible and compact multiple-valued logic circuits that can be used for carry-propagation free arithmetic [114, 115]. 5.4. Logic Applications Using Negative-Differential Conductance Another prominent feature of a SET made of a semiconductor nanodot is its NDC, which is a phenomenon provided by transport through quantized states in the small nanodot. Figure 38 shows the measured counter plot of differential conductance (dId/dVd) in a drain voltage (Vd)–gate voltage (Vg) plane for the device fabricated by V-PADOX [35]. NDC is observed in the dark regions. As shown in the figure, the quantized states appear at a slightly higher drain voltage at which the Coulomb blockade condition is lifted. Figure 39 shows the NDC characteristics observed in the drain current (Id)–Vd curve at a fixed gate voltage at 27 K. More recently room temperature NDC has been observed in small Si SETs as described in Sect 3 [42–44]. One significant feature of the NDC in the SETs is that the position of the peak (or valley) can be controlled by the gate voltage, which is easily predicted from the characteristics shown in Fig. 38. Many kinds of application have been proposed that use typical NDC devices represented as tunnel diodes. It is well known that one of the typical applications is static memory. Saitoh et al. [43] demonstrated a SET-NDC-based static memory in which the gate voltage is used to control the write/erase conditions. In addition, they also demonstrated an XOR gate for logic circuits that uses the peak drain-voltage shift of SET-NDC devices [116]. Another interesting use of the gate voltage-controlled NDC of a SET is that we can obtain hysteresis in the drain current when we scan the gate voltage back and forth with a constant current load. This phenomenon can be used as a Schmitt trigger circuit that will be useful for achieving wide noise immunity [35].

156

TAKAHASHI ET AL.

FIG. 36. Measurement setup for the quantizer made by using PADOX. The external MOSFET 2 is used as a FET probe for the output signal by oscilloscope (a), and measured data at 27 K (b).

6. SINGLE-ELECTRON TRANSFER AND SINGLE-ELECTRON DETECTION

Ultimate single electronics should be able to handle a single electron. As described in Sect. 4.3, we have treated a single electron as 1 bit and it was successfully memorized in a SET island. This constitutes an ultimate device because it will allow us to achieve the highest integration level and will consume very little power [117]. In this section, we describe clocked single-electron transfer and single-electron detection for such ultimate single-electronics applications.


157

FIG. 37. Circuit diagram of a 3-bit analog-to digital converter that consists of a quantizer and SETbased literal gates.

FIG. 38. Contour plots of the differential conductance of a SET in a drain voltage (Vd)-gate voltage (Vg) plane. The dark areas indicate NDC.

6.1. Development of Single-Charge Transfer Device Clocked single-electron transfer is defined as the transfer of just a single electron during one ac gate voltage cycle, or one gate clock. Unfortunately a SET does not have this ability. This is because we cannot control the time interval of each transfer in a SET due to the stochastic nature of electron tunneling. We need more

158

TAKAHASHI ET AL.

FIG. 39. Drain current vs. drain voltage characteristics of the SET in Fig. 38 for a fixed gate voltage of 1.34 V.

FIG. 40. Equivalent circuit of the single-electron pump (a), and single-electron turnstile (b). In (a), Cg, Ug, V1, and V2 are the gate capacitance, voltages to the gate, source, and drain, respectively. The number of electrons in the central island is represented by n. In (b), Cg1, Cg2, Ug1, Ug2, V1, and V2 are the gate capacitances, voltages to the gates, source, and drain, respectively. The number of electrons in the left and right islands is represented by n1 and n2, respectively.

sophisticated devices if we are to transfer single electrons that are synchronized with the gate clock. Sometimes called single-charge transfer devices, they include single-electron pumps and single-electron turnstiles shown in Fig. 40a, b, respectively. In these devices, an electron is conveyed from the source to the drain in one cycle of the gate clock. Thus, the generated current is equal to ef, where e is the elementary charge and f is the clock frequency. Research on the single-charge transfer devices started with Al-AlOx multiple junctions, and then expanded to GaAs and Si semiconductors. The first two single-charge transfer devices were reported in 1990 and 1991 and these are now known as the single-electron turnstile [118] and single-electron pump [119]. They were fabricated with Al-AlOx multiple junctions. The turnstile has three sequentially connected islands and the central island has a gate (Fig. 40b). The current characteristics exhibit a step-like structure as a function of the drain voltage, and the level of each


159

FIG. 41. Stability chart for the two-island single-electron pump. Cg1, Cg2, Ug1, and Ug2, are the gate capacitances, and voltages to the gates, respectively. The number of electrons in the left and right islands is represented by (n1, n2). The arrows indicate the gate-voltage trajectory for the pump operation.

plateau is equal to multiples of ef. The pump is composed of (at least) two islands and each island has a gate (Fig. 40a). In contrast to the turnstile, the single-electron transfer current ef is observed at around zero drain voltage as an offset current. Thus far, the single-electron pump has been the most intensively studied single-charge transfer device. As the name indicates, this device can convey single electrons from the source to the drain even when the drain is grounded or reversely biased. Figure 41 shows the stability chart for the two-island devices for the pump. The horizontal and vertical axes are the normalized gate voltages. The closed circles are the nonvanishing conductance points for a sufficiently small drain voltage. The pump operation corresponds to establishing a gate voltage trajectory that encircles one of these points, as shown by the arrows in the figure. This is accomplished by applying an ac bias to the gates with some phase shift as shown in Fig. 42. In 1996, Keller et al. fabricated a highly sophisticated pump using Al-AlOx junctions [120], which achieved a transfer accuracy of the order of 10−8 (the highest ever reported) at temperatures below 50 mK. A different approach to realizing single-charge transfer devices is used with semiconductors in that they use a two-junction device, i.e., a SET. As mentioned above, the time interval for the tunneling in ordinary SETs cannot be controlled. Thus, in order to make a SET transfer an electron with a time correlation, the resistance of the junctions is modulated with time [121, 122]. Such a SET with tunable barriers could provide a fairly attractive single-charge transfer device. A pioneering study was reported in 1991 in which a GaAs/AlGaAs heterostructure was used [121].

160

TAKAHASHI ET AL.

FIG. 42. Example gate voltage waveforms for the pump operation, (a) triangular shaped and (b) sinusoidal.

Split gates formed over the GaAs/AlGaAs heterostructure made an island and tunnel junctions in two-dimensional electron gas, and these gates were used to modulate the barrier resistance. They observed current characteristics are similar to those of a metal-based turnstile at 10 mK. Another approach using the GaAs/AlGaAs heterostructure employs surfaceacoustic waves (SAWs). Such a SAW-based charge-transfer device was demonstrated by Shilton et al. in 1996 at around 300 mK [123]. The operational frequency was in the GHz range, which has not yet been achieved with any other charge transfer devices. Since high-frequency operation results in a high level of current, the SAW device has been intensively studied, with a view to realizing dc standard applications in electrical metrology. However, it is very difficult to transfer a fixed number of electrons because the SAW cannot switch ON and OFF very quickly. Thus, it may not be suitable for circuit applications. Although metal-based and compound semiconductor-based devices have proved the feasibility of clocked single-charge transfer, the operating temperature was below 1 K and this must be raised. Si-based devices can operate at much higher temperatures because they possess a smaller island, which could be made owing to the state-of-the-art fabrication technology available for SETs and MOSFETs. 6.2. Si-Based Single-Charge Transfer Devices As described in Sect. 3, PADOX SETs are stable and can operate at high temperatures. The application of PADOX SETs to tunable barrier devices should make it possible to improve the operating temperature and stability greatly. Thus, Ono and Takahashi fabricated a charge-transfer device on an SOI wafer and demonstrated single-charge-transfer operation [124, 125]. To obtain tunable barriers, they exploited MOSFETs, the best devices with which to obtain a large on–off current ratio, i.e., to obtain a large dynamic range for barrier tuning. The MOSFET resistance was superimposed on the SET junction resistance.


161

FIG. 43. Equivalent circuit of the PADOXbased pump/turnstile.

FIG. 44. Stability chart for the PADOX-based pump/turnstile. U1 and U2, are the voltages to the gates. n is the number of electrons in the SET island. U1th and U2th are the threshold-voltage lines for MOSFET1 and MOSFET2, respectively.

Figure 43 shows the equivalent circuit. The device is in effect a dual-gate SET, where each gate is carefully positioned so that it can control not only the electrostatic potential of the island but also the electron density of the SET leads. The two leads of the SET are therefore the independently controllable electron channels of the ultra-small MOSFETs. This device can work both as a pump [124] and a turnstile [125]. This is one of the notable features of a two-junction device with tunable barriers, and distinguishes it from the metal-based multijunction devices, where the pump and the turnstile require their own structures. Figure 44 shows the stability chart for this device in the two gate voltage plane. This is basically the same as the chart for an ordinary SET, but the nonvanishing conductance regions, i.e., the Coulomb blockade peak regions, are terminated at the threshold voltages (indicated by lines U1th and U2th) of the MOSFETs. Similar to the metal-based pump, the pump operation can be achieved by making the gate-voltage trajectory encircle one of the nonvanishing conductance regions, as indicated by the oval in Fig. 44.

162

TAKAHASHI ET AL.

FIG. 45. SEM image of the PADOX-based pump/turnstile. The source and drain are made of SOI and the two fine gates (gate-1 and -2) are made of poly-Si.

FIG. 46. Pump operation (a) and frequency dependence of the pump current (b) for the PADOX-based pump/turnstile.

The device was fabricated using the V-PADOX process, which made it possible to operate the device at around 20 K, which is 102–103 higher than previous chargetransfer devices [124]. A scanning-electron microscope (SEM) image is shown in Fig. 45. The SET island was made of SOI, while the two fine gates were made of poly-Si. Figure 46a shows the drain current (ID) vs. drain voltage (VD) characteristics measured at 25 K with a frequency f of 1.0 MHz. The offset current at VD = 0 V is 160 fA, which is equal to ef with f = 1.0 MHz. Changing the polarity of the gate-voltage rotation resulted in a change in the polarity of the offset current, thus demonstrating the pump operation. As shown in Fig. 46b, the offset current is proportional to


163

FIG. 47. Device structure of a single-electron CCD. This test device demonstrated single-electron shuttling.

the frequency. We have also shown that this device can operate as a turnstile by applying an ac gate bias with a phase shift of π [125]. There is another type of Si single-charge transfer device. This is based on charge-coupled devices (CCDs), and is now called the single-electron CCD. Conventional CCDs consist of an array of MOS diodes and are widely used in image sensors. A suitable sequence of clock voltage pulses applied to the diodes traps and bundles electrons in a potential well and transfers them from one diode to another. We expect that the scaling-down of the CCD will finally lead to singleelectron manipulation. Despite its potential, very few researchers recognized the importance of this device until Fujiwara and Takahashi [126] demonstrated its primary operation in 2001. In fact, the single-electron CCD is the first Si singlecharge transfer device. Figure 47 shows a schematic view of the device used for demonstrating the primary operation. The device is a closely packed array of two Si-wire MOSFETs. The channels of the MOSFETs are defined by fine poly-Si gates. This first demonstration involved holes rather than electrons. Single holes can be stored under these gates and transferred back and forth between them. The T-shaped Si wire shared by the two MOSFETs is connected to three large electrodes (one source and two drains). These electrodes are used to make the electron current flow. These currents are important in terms of sensing the stored hole. Figure 48 shows the demonstration of single-hole transfer at 25 K. The transfer was performed by changing the bias voltage of each MOSFET, and the presence or absence of the hole was checked by monitoring the level of the sensing electron current flowing through each MOSFET.

164

TAKAHASHI ET AL.

FIG. 48. Demonstrated of the single-electron shuttling by the single-electron CCD.

FIG. 49. SEM image of the CCD-based turnstile. The source and drain are made of SOI and the fine gates are made of poly-Si. The rightmost gate was not used for the turnstile operation and its voltage was kept at a positive voltage.

A key aspect of this study was the development of a way to sense stored single holes. For this purpose, they created a flow of electrons near the stored holes. This sensing technique will be touched on later. Although the original work [126] on the single-electron CCD did not demonstrate the single-charge-transfer current ef, this was soon achieved in 2004 [127]. This CCD-based device is promising for high-frequency operation because it has no fixed barriers. The device is composed simply of two ultra-fine MOSFETs connected in sequence. Figure 49 shows a top-view SEM image of the device fabricated on an


165

SOI wafer, which consists of a Si-wire channel, an array of fine poly-Si gates, and a source and drain. We apply repetitive pulse voltages to two gates (VG1 and VG2), which modulate the barrier potential to turn the channel under G1 and G2 on and off alternately. The potential of the island between the two gates is controlled by an additional upper gate (not shown in Fig. 49) that covers the space between G1 and G2. Figure 50 outlines the turnstile operation: The island is isolated (1) and then connected to the source (2). The number of electrons (n) is then quantized due to the formation of an island with a low barrier resistance (3), and n increases as a function of the upper gate voltage. Finally, the electrons are captured (4) and extracted to the drain (5). Consequently, the drain-to-source current is quantized as I = nef. Figure 51 shows the frequency dependence of the current vs. upper gate voltage characteristics at 20 K. Clear plateaus are observed for frequencies up to 100 MHz.

FIG. 50. Potential profile showing the single-electron transfer sequence in the CCD-based turnstile.

FIG. 51. Demonstration of turnstile operation.

166

TAKAHASHI ET AL.

When we compare the CCD-based device with the former PADOX-based Si pump/turnstile, the difference is that this device does not contain fixed barriers: the barrier is the potential formed by the MOSFET itself. Therefore, the junction resistance is tunable over a wider range. As a result, the device has states in which there is almost no barrier. In other words, there are time intervals where the device has no islands. When we raise the potential barriers, the island is formed so that electrons are scooped up. Although we do not fully understand how the Coulomb blockade evolves in this case, we can expect high-frequency operation if it evolves at a significantly low resistance. To estimate the transfer accuracy, we have developed an analytical model that considers the dynamical response of electrons [128]. However, more detailed measurements and theoretical considerations are needed to clarify the maximum accuracy and speed of this device. Another advantage of this device is that it is much easier to fabricate because of its simple structure, and it can benefit fully from the evolution of Si nanotransistor fabrication technology. 6.3. Single-Electron Detection A straightforward way of detecting a very small amount of charge Q is to put the charge on a very small capacitance C, thus causing a change Q/C in the voltage, and then to measure the resultant change in the current level of an electrometer placed near the capacitor. The SEB is a good choice for single-charge storage because the Coulomb blockade effectively prevents excess electrons entering and escaping. In Sect. 3, we introduced a variety of SEDs that can detect charges at the singleelectron level. However, for an electrometer, a Coulomb blockade is not necessarily required as long as the charge sensitivity is high. Thus, in principle, a FET is applicable to single-electron detection, as well as SETs or other SEDs. We will hereafter describe such MOSFET-based single-electron detection. The detection of stored single electrons by MOSFETs has been observed by several groups. After the epoch-making study [74, 129] by Yano et al., who achieved the world’s first single-electron detection at room temperature in 1993, Guo et al. and Nakajima et al. made a Si wire-MOSFET with an SEB mounted on top. They observed clear steps in the MOSFET channel currents at room temperature [71, 72] which they ascribed to the charging of the SEB by single electrons. One unique approach to sensing single electrons is to exploit the electron–hole co-existence system in thin SOI [130–132]. This technique, which was originally developed for the demonstration of a single-electron CCD, uses a wire-MOS structure [131, 132]. Figure 52a shows schematic cross sections of the device. The electron–hole coexistence system can be formed by applying a large electric field in the vertical direction of the Si wire. If we apply a large negative voltage to the MOS gate, which we call the front gate, and a large positive voltage to the SOI substrate, which we call the back gate, then holes (if any) and electrons are separated from each other and attached to a different side of the wire interface. When, for example, the system is illuminated, holes are generated and this separation truly occurs. Since the concentrated electrons contribute to the MOS current, the trapped holes can be detected by monitoring the level of electron current. Fujiwara and Takahashi [131]


167

FIG. 52. Schematic cross-sectional view of the charge sensing device and the measurement results.

showed that the electron current level is very sensitive to the number of trapped holes and it is even possible to detect changes of one in this number. Figure 52b shows the measurement results. The horizontal axis is the voltage to the sense gate, which was placed over the front gate to modulate the electric field in the wire. When the sense-gate voltage is scanned in the positive direction, the electron channel starts to open and then the electron density increases, which enhances the recombination of the electrons and the holes. In this way, each recombination can be detected and it becomes possible to store only one hole. The advantage of this method is that it is not necessary to define the SEB lithographically for storage; it is formed electrically. We should also mention that this sensing technique is destructive. That is, the stored charge is erased during the sensing procedure by the recombination.

168

TAKAHASHI ET AL.

7. SUMMARY

Single electronics is expected to provide extremely LSIs with low-power consumption. Although the basic device is a single-gate SET, the operating principle of the device allows many kinds of variations. One of the great features of SETs is that these devices operate simply by employing a balance of charges between a small SET island and some electrodes or other islands. This makes the SET capable of supporting multiple gates. In addition, combinations of SET islands produce special transport characteristics such as single-electron transfer devices. We can use SETs to achieve a number of new functionalities as described above to suit the desired application. The greatest advantages of single electronics are small size and low-power operation. These characteristics provide good efficiency when SEDs are used in highly integrated circuits. As a result, SEDs fabricated with conventional silicon MOS processes are very important in terms of practical applications. The particular advantages of Si SEDs are summarized below: 1. A charging energy, Ec, of greater than several tens of meV is possible using the sophisticated fabrication processes available in Si technology. 2. The fabrication process can be highly compatible with conventional LSI technology, thus enabling us to integrate SETs in conventional CMOS circuits. 3. A Si SED can be used in combination with MOSFETs, thus counteracting the low drivability of SETs. 4. Si SETs are very stable against offset charges. There are basically two types of SET application: memory devices and logic devices. The small size is especially important for memory devices; memory cells have to be small to achieve a greater degree of integration. Many kinds of work have been undertaken using a small Si dot as a memory node. One special application is the multilevel memory in which every memory state corresponds to the number of electrons in the memory node. This is another way to increase the effective capacity of solid-state memories. These new concepts with respect to Si singleelectron memory will lead to new uses. An important issue as regards future logic LSIs is finding a way to suppress the power dissipating in a small silicon chip. The low-power dissipation nature of SEDs will be very useful for logic LSIs. A critical issue with the SET logic is low drivability that results from the operating principle of one-by-one electron tunneling. To deal with this problem, a pass-transistor logic and the combination of SETs and MOSFETs have been proposed. Very low power and relatively fast operation have been confirmed. An important aspect of SET-base logic is that active devices are used quite differently from conventional transistors. For the future ultimate application of SEDs, we must first succeed in the manipulation and the detection of a single electron. Basic demonstrations of single-electron transfer devices have been achieved at low temperatures, and some have even been realized at room temperature. This is important not only for establishing ultra-low-power LSIs but also for developing current standards which is important in terms of metrology.


169

Raising the operating temperature as high as room temperature means that we have to reduce the island size of the order of a few nanometers. Although this is a challenging issue, some devices have been demonstrated that clearly and conclusively operate at room temperature through the use of recent rapidly developing nanotechnologies. The results provide excellent prospects for the future practical application of SEDs.

REFERENCES 1. J. D. Meindl (ed), Proc. IEEE 89 (2001). 2. D. V. Averin and K. K. Likharev, Mesoscopic Phenomena in Solids, B. L. Altshuler, P. A. Lee and R. A. Webb (eds), Chapter 6 (Amsterdam: Elsevier, 1991). 3. H. Grabert and M. H. Devoret (eds), Single Charge Tunneling (New York: Plenum, 1992). 4. K. K. Likharev, Proc. IEEE 87 606 (1999). 5. L. S. Kuzmin and K. K. Likharev, JETP Lett. 45 495 (1987). 6. T. A. Fulton and G. J. Doran, Phys. Rev. Lett. 59 109 (1987). 7. J. H. F. Scott-Thomas, S. B. Field, M. A. Kastner, H. I. Smith and D. A. Antoniadis, Phys. Rev. Lett. 62 583 (1989). 8. S. B. Field, M. A. Kastner, U. Meirav, J. H. F. Scott-Thomas, D. A. Antoniadis, H. I. Smith and S. J. Wind, Phys. Rev. B 42 3523 (1990). 9. C. de Graaf, J. Caro, S. Radelaar, V. Lauer and K. Heyers, Phys. Rev. B 44 9072 (1991). 10. U. Meirav, M. A. Kastner and S. J. Wind, Phys. Rev. Lett. 65 771 (1990). 11. M. Fukuda, K. Nakagawa, S. Miyazaki and M. Hirose, Appl. Phys. Lett. 70 2291 (1997). 12. M. Otobe, H. Yajima and S. Oda, Appl. Phys. Lett. 72 1089 (1998). 13. A. Dutta, S. P. Lee, Y. Hayafune, S. Hatatani and S. Oda, Jpn. J. Appl. Phys. 39 264 (2000). 14. A. Dutta, S. Oda, Y. Fu and M. Willander, Jpn. J. Appl. Phys. 39 4647 (2000). 15. K. Uchida, J. Koga, R. Ohba, S. Takagi and A. Toriumi J. Appl. Phys. 90 3551 (2001). 16. D. H. Kim, J. D. Lee and B. G. Park, Jpn. J. Appl. Phys. 39 2329 (2000). 17. D. H. Kim, S. K. Sung, K. R. Kim, J. D. Lee, B. G. Park, B. H. Choi, S. W. Hwang and D. Ahn, IEEE Trans. Electron. Devices 49 627 (2002). 18. S. D. Lee, K. S. Park, J. W. Park, J. B. Choi, S-R. E. Yang, K. H. Yoo, J. Kim, S. I. Park and K. T. Kim, Phys. Rev. B 62 7735 (2000). 19. S. D. Lee, K. S. Park, J. W. Park, Y. M. Moon, J. B. Choi, K. H. Yoo and J. Kim Appl. Phys. Lett 77 2355 (2000). 20. A. Fujiwara, H. Inokawa, K. Yamazaki, H. Namatsu, Y. Takahashi, N. M. Zimmerman and S. B. Martin, Appl. Phys. Lett, 88, 053121 (2006). 21. D. Ali and H. Ahmed, Appl. Phys. Lett. 64 2119 (1994). 22. Y. Takahashi, M. Nagase, H. Namatsu, K. Kurihara, K. Iwadate, Y. Nakajima, S. Horiguchi, K. Murase and M. Tabe, Electron. Lett. 31 136 (1995). 23. Y. Takahashi, H. Namatsu, K. Kurihara, K. Iwadate, M. Nagase, and K. Murase, IEEE Trans. Electron. Devices 43 1213 (1996). 24. A. Fujiwara, Y. Takahashi, H. Namatsu, K. Kurihara and K. Murase, Jpn. J. Appl. Phys. 37 3257 (1998). 25. Y. Takahashi, A. Fujiwara, M. Nagase, H. Namatsu, K. Kurihara, K. Iwadate and K. Murase, Int. J. Electron. 86 605 (1999). 26. D. B. Kao, J. P. McVittie, W. D. Nix and K. C. Saraswat, IEEE Trans. Electron. Devices 35 25 (1988). 27. H. I. Liu, D. K. Biegelsen, F. A. Ponce, N. M. Johnson and R. F. W. Pease, Appl. Phys. Lett. 64 1383 (1994). 28. M. Nagase, A. Fujiwara, K. Yamazaki, Y. Takahashi, K. Murase and K. Kurihara, Microelectron. Eng. 41/42 527 (1998).

170

TAKAHASHI ET AL.

29. S. Horiguchi, M. Nagase, K. Shiraishi, H. Kageshima, Y. Takahashi and K. Murase, Jpn. J. Appl. Phys. 40 L29 (2001). 30. A. Fujiwara, Y. Takahashi and K. Murase, Microelectron. Eng. 47 197 (1999). 31. Y. Ono, Y. Takahashi, K. Yamazaki, M. Nagase, H. Namatsu, K. Kurihara and K. Murase, IEEE Trans. Electron. Devices 47 147 (2000). 32. Y. Ono, Y. Takahashi, K. Yamazaki, M. Nagase, H. Namatsu, K. Kurihara and K. Murase, Jpn. J. Appl. Phys. 39 2325 (2000). 33. H. Ishikuro and T. Hiramoto, Appl. Phys. Lett. 71 3691 (1997). 34. M. Saitoh, T. Saito, T. Inukai and T. Hiramoto, Appl. Phys. Lett. 79 2025 (2001). 35. Y. Ono and Y. Takahashi, Jpn. J. Appl. Phys. 41 2569 (2002). 36. M. Saitoh and T. Hiramoto, Jpn. J. Appl. Phys. 43 L210 (2004). 37. E. Leobandung, L. Guo, Y. Wang and S. Y. Chou, Appl. Phys. Lett. 67 938 (1995). 38. E. Leobandung, L. Guo and S. Y. Chou, Appl. Phys. Lett. 67 2338 (1995). 39. H. Ishikuro, T. Fujii, T. Saraya, G. Hashiguchi, T. Hiramoto and T. Ikoma, Appl. Phys. Lett. 68 3585 (1996). 40. H. Ishikuro and T. Hiramoto, Appl. Phys. Lett. 74 1126 (1999). 41. M. Saitoh, H. Majima and T. Hiramoto, Jpn. J. Appl. Phys. 42 2426 (2003). 42. M. Saitoh and T. Hiramoto, Appl. Phys. Lett. 84 3172 (2004). 43. M. Saitoh, H. Harata and T. Hiramoto, Appl. Phys. Lett. 85 6233 (2004). 44. M. Saitoh, H. Harata and T. Hiramoto, Jpn. J. Appl. Phys. 44 L338 (2005). 45. T. Sakamoto, H. Kawaura and T. Baba, Appl. Phys. Lett. 72 795 (1998). 46. A. Tilke, R. H. Blick, H. Lorenz, J. P. Kotthaus and D. A. Wharam, Appl. Phys. Lett. 75 3704 (1999). 47. R. Augke, W. Eberhardt, C. Single, F. E. Prins, D. A. Wharam and D. P. Kern, Appl. Phys. Lett. 76 2065 (2000). 48. W. H. Huber, S. B. Martin and N. M. Zimmerman, Experimental Implementation Quantum Computation (IQC’01), p. 176 (Princeton, NJ: Rinton, 2001). 49. N. M. Zimmerman, W. H. Huber, A. Fujiwara and Y. Takahashi, Appl. Phys. Lett. 79 3188 (2001). 50. S. Lai, International Electron Devices Meeting, Technical Digest, p.971 (Piscataway, NJ: IEEE, 1998). 51. K. Nakazato, R. J. Blaikie, J. R. A. Cleaver and H. Ahmed, Electron. Lett. 29 384 (1993). 52. S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan and D. Buchanan, International Electron Devices Meeting, Technical Digest, p. 521 (Piscataway, NJ: IEEE, 1995). 53. S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe and K. Chan, Appl. Phys. Lett. 68 1377 (1996). 54. K. R. Farmer, M. O. Andersson and O. Engström, Appl. Phys. Lett. 60 730 (1992). 55. H. Hanafi, S. Tiwari, S. Burns, W. Kocon, A. Thomas, N. Garg and K. Matsushita, International Electron Devices Meeting, Technical Digest, p. 657 (Piscataway, NJ: IEEE, 1995). 56. Y. Shi, K. Saito, H. Ishikuro and T. Hiramoto, Jpn. J. Appl. Phys. 38 425 (1999). 57. J. A. Wahl, H. Silva, A. Gokirmak, A. Kumar, J. J. Welser and S. Tiwari, International Electron Devices Meeting, Technical Digest, p. 375 (Piscataway, NJ: IEEE, 1999). 58. H. Wang, N. Takahashi, H. Majima, T. Inukai, M. Saitoh and T. Hiramoto, Jpn. J. Appl. Phys. 40 2038 (2001). 59. T. Ishii, T. Osabe, T. Mine, F. Murai and K. Yano, International Electron Devices Meeting, Technical Digest, p. 305 (Piscataway, NJ: IEEE, 2000) 60. A. Ohata, H. Niiyama, T. Shibata, K. Nakajima and A. Toriumi, Jpn. J. Appl. Phys. 34 4485 (1995). 61. B. DeSalvo, G. Ghibaudo, G. Pananakakis, P. Masson, T. Baron, N. Buffet, A. Fernandes and B. Guillaumot, IEEE Trans. Electron. Devices 48 1789 (2001). 62. I. Kim, S. Han, H. Kim, J. Lee, B. Choi, S. Hwang, D. Ahn and H. Shin, International Electron Devices Meeting, Technical Digest, p. 111 (Piscataway, NJ: IEEE, 1998). 63. A. Fernandes, B. DeSalvo, T. Baron, J. F. Damlencourt, A. M. Papon, D. Lafond, D. Mariolle, B. Guillaumot, P. Besson, P. Masson, G. Ghibaudo, G. Pananakakis, F. Martin and S. Haukka, International Electron Devices Meeting, Technical Digest, p. 155 (Piscataway, NJ: IEEE, 2001).


171

64. B. J. Hinds, K. Nishiguchi, A. Dutta, T. Yamanaka, S. Hatanani and S. Oda, Jpn. J. Appl. Phys. 39 4637 (2000). 65. J. DeBlauwe, M. Ostraat, M. L. Green, G. Weber, T. Sorsch, A. Kerber, F. Klemens, R. Cirelli, E. Ferry, J. L. Grazul, F. Baumann, Y. Kim, W. Mansfield, J. Bude, J. T. C. Lee, S. J. Hillenius, R. C. Flagan and H. A. Atwater, International Electron Devices Meeting, Technical Digest, p. 683 (Piscataway, NJ: IEEE, 2000). 66. F. Yun, B. J. Hinds, S. Hatatani and S. Oda, Jpn. J. Appl. Phys. 39 L792 (2000). 67. H. I. Hanafi, S. Tiwari and I. Khan, IEEE Trans. Electron. Devices 43 1553 (1996). 68. A. Nakajima, T. Futatsugi, N. Horiguchi, H. Nakao and N. Yokoyama, International Electron Devices Meeting, Technical Digest, p. 159 (Piscataway, NJ: IEEE, 1997). 69. Y. C. King, T. J. King, and C. Hu, IEEE Trans. Electron. Devices 48 696 (2001). 70. R. Ohba, N. Sugiyama, K. Uchida, J. Koga and A. Toriumi, International Electron Devices Meeting, Technical Digest, p. 313 (Piscataway, NJ: IEEE, 2000). 71. L. Guo, E. Leobandung and S. Y. Chou, Science 275 649 (1997). 72. A. Nakajima, T. Futatsugi, K. Kosemura, T. Fukano and N. Yokoyama, Appl. Phys. Lett. 70 1742 (1997). 73. J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee and Y. Lee, IEEE Electron. Device Lett. 18 278 (1997). 74. K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi, F. Murai and K. Seki, International Electron Devices Meeting, Technical Digest, p.541 (Piscataway, NJ: IEEE, 1993). 75. K. Yano, T. Ishii, T. Sana, T. Mine, F. Murai, T. Hashimoto, T. Kobayashi, T. Kure and K. Seki, Proc. IEEE 87 633 (1999). 76. N. J. Stone and H. Ahmed, Appl. Phys. Lett. 73 2134 (1998). 77. A. Fujiwara, Y. Takahashi, K. Murase and M. Tabe, Appl. Phys. Lett. 67 2957 (1995). 78. Y. Takahashi, A. Fujiwara, K. Yamazaki, H. Namatsu, K. Kurihara and K. Murase, Jpn. J. Appl. Phys. 38 2457 (1999). 79. S. Shukuri, T. Kure and T. Nishida, International Electron Devices Meeting, Technical Digest, p. 1006 (Piscataway, NJ: IEEE, 1992). 80. H. Ikeda, T. Terano, H. Moriya, T. Emori and T. Kobayashi, Symposium on VLSI Technology, Digest of Technical Papers, p. 168 (Piscataway, NJ: IEEE, 2000). 81. K. Nishiguchi, H. Inokawa, Y. Ono, A. Fujiwara and Y. Takahashi, Appl. Phys. Lett. 85 1277–1279 (2004). 82. K. Nishiguchi, H. Inokawa, Y. Ono, A. Fujiwara and Y. Takahashi, Electron. Lett. 40 229–230 (2004). 83. H. Inokawa, A. Fujiwara and Y. Takahashi, Appl. Phys. Lett. 97 3618 (2001). 84. H. Inokawa, A. Fujiwara and Y. Takahashi, IEEE Trans. Electron. Devices, 50 462 (2003). 85. K. K. Likharev, IEEE Trans. Mag. 23 1142 (1987). 86. J. R. Tucker, J. Appl. Phys. 72 4399 (1992). 87. K. Uchida, K. Matsuzawa, J. Koga, R. Ohba, S. Takagi and A. Toriumi, Jpn. J. Appl. Phys. 39 2321 (2000). 88. K. Uchida, J. Koga, R. Ohba and A. Toriumi, IEICE Trans. Electron. E84-C 1066 (2001). 89. K.-T. Liu, A. Fujiwara, Y. Takahashi, K. Murase and Y. Horikoshi, Jpn. J. Appl. Phys. 41 458 (2002). 90. Y. Ono, H. Inokawa and Y. Takahashi, IEEE Trans. Nanotechnol. 01 93 (2002). 91. G. Zimmerli, R. L. Kautz and J. M. Martinis, Appl. Phys. Lett. 61 2616 (1992). 92. E. H. Visscher, S. M. Verbrugh, J. Lindeman, P. Hadley and J. E. Mooij, Appl. Phys. Lett. 66 305 (1995). 93. Y. Satoh, H. Okada, K. Jinushi, H. Fujikura and H. Hasegawa, Jpn. J. Appl. Phys. 38 410 (1999). 94. R. A. Smith and H. Ahmed, Appl. Phys. Lett. 71 3838 (1997). 95. Y. Ono, K. Yamazaki and Y. Takahashi, IEICE Trans. Electron. E84-C 1061 (2001). 96. H. Harata, M. Saitoh and T. Hiramoto, Jpn. J. Appl. Phys. 44 L640 (2005). 97. H. Inokawa, A. Fujiwara and Y. Takahashi, Jpn. J. Appl. Phys. 41 2566 (2002). 98. A. N. Korotkov, R. H. Chen and K. K. Likharev, J. Appl. Phys. 78 2520 (1995). 99. K. Nishiguchi and S. Oda, Appl. Phys. Lett. 78 2070 (2001). 100. Y. Ono, Y. Takahashi, K. Yamazaki, M. Nagase, H. Namatsu, K. Kurihara and K. Murase, Appl. Phys. Lett. 76 3121 (2000). 101. N. J. Stone and H. Ahmed, Electron. Lett. 35 1883 (1999).

172

TAKAHASHI ET AL.

102. N. Takahashi, H. Ishikuro and T. Hiramoto, Appl. Phys. Lett. 76 209 (2000). 103. K. Nishiguchi, H. Inokawa, Y. Ono, A. Fujiwara and Y. Takahashi, IEEE Electron. Device Lett. 25 31 (2004). 104. K. Nishiguchi, H. Inokawa, Y. Ono, A. Fujiwara and Y. Takahashi, IEICE Trans. Electron. E87-C 1809 (2004). 105. R. H. Chen, A. N. Korotkov and K. K. Likharev, Appl. Phys. Lett. 68 1954 (1996). 106. Y. Takahashi, A. Fujiwara, K. Yamazaki, H. Namatsu, K. Kurihara and K. Murase, Appl. Phys. Lett. 76 637 (2000). 107. K. Uchida, K. Matsuzawa and A. Toriumi, Jpn. J. Appl. Phys. 38 4027 (1999). 108. A. Fujiwara, Y. Takahashi, K. Yamazaki, H. Namatsu, M. Nagase, K. Kurihara and K. Murase, IEEE Trans. Electron. Devices 46 954 (1999). 109. N. Takahashi, H. Ishikuro and T. Hiramoto, International Electron Devices Meeting, Technical Digest, p. 371 (Piscataway, NJ: IEEE, 1999) 110. Y. Ono and Y. Takahashi, International Electron Devices Meeting, Technical Digest, p. 297 (Piscataway, NJ: IEEE, 2000). 111. T. Hanyu, M. Kameyama and T. Higuchi, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, p. 134 (Piscataway, NJ: IEEE, 1993). 112. H. C. Lin, Proc. 24th IEEE Int. Symp. on Multiple-Valued Logic, p. 188 (Los Alamitos, CA: IEEE, 1994). 113. H. Inokawa, A. Fujiwara and Y. Takahashi, International Electron Devices Meeting, Technical Digest, p. 147 (Piscataway, NJ: IEEE, 2001). 114. H. Inokawa, Y. Takahashi, K. Degawa, T. Aoki, and T. Higuchi, IEICE Trans. Electron. E87-C 1818 (2004). 115. K. Degawa, T. Aoki, T. Higuchi, H. Inokawa, and Y. Takahashi, IEICE Trans. Electron. E87-C 1827 (2004). 116. M. Saitoh and T. Hiramoto, International Electron Devices Meeting, Technical Digest, p. 753 (Piscataway, NJ: IEEE, 2003). 117. N. Asahi, M. Akazawa and Y. Amemiya IEEE Trans. Electron. Devices 44 1109 1997. 118. L. J. Geerligs, V. F. Anderegg, P. A. M. Holweg and J. E. Mooij, Phys. Rev. Lett. 64 2691 (1990). 119. H. Pothier, P. Lafarge, P. F. Orfila, C. Urbina, D. Esteve and M. H. Devoret, Phys. B 169 573 (1991). 120. M. W. Keller, J. M. Martinis, N. M. Zimmerman and A. H. Steinbach, Appl. Phys. Lett. 69 1804 (1996). 121. L. P. Kouwenhoven, A. T. Johnson, N. C. van der Vaart, C. J. P. M. Harmans and C. T. Foxon, Phys. Rev. Lett. 67 1626 (1991). 122. A. A. Odintsov, Appl. Phys. Lett. 58 2695 (1991). 123. J. M. Shilton, V. I. Talyanskii, M. Pepper, D. A. Ritchie, J. E. F. Frost, C. J. B. Foad, C. G. Smith and G. A. C. Jones, J. Phys.: Condens. Matter 8 L531 (1996). 124. Y. Ono and Y. Takahashi, Appl. Phys. Lett. 82 1221 (2003). 125. Y. Ono, N. M. Zimmerman, K. Yamazaki and Y. Takahashi, Jpn. J. Appl. Phys. 42 L1109 (2003). 126. A. Fujiwara and Y. Takahashi, Nature 410 560 (2001). 127. A. Fujiwara, N. M. Zimmerman, Y. Ono and Y. Takahashi, Appl. Phys. Lett. 84 1323 (2004). 128. N. M. Zimmerman, E. Hourdakis, Y. Ono, A. Fujiwara and Y. Takahashi, J. Appl. Phys. 96 5254 (2004). 129. K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi, F. Murai and K. Seki, IEEE Trans. Electron. Devices 41 1628 (1994). 130. A. Fujiwara, Y. Takahashi and K. Murase, Phys. Rev. Lett. 78 1532 (1997). 131. A. Fujiwara and Y. Takahashi, Jpn. J. Appl. Phys. 41 1209 (2002). 132. A. Fujiwara, K. Yamazaki and Y. Takahashi, Appl. Phys. Lett. 80 4567 (2002).

6 Room Temperature Silicon Spin-Based Transistors M. Cahay* and S. Bandyopadhyay Abstract In this review article, we provide a brief overview of current research in the field of silicon spin-based transistors operating at room temperature. This field has branched into two distinct efforts: the first aimed at developing new types of silicon transistors where spin transport, in conjunction with charge transport, is utilized to realize or augment device operation, and the second focused on improving the performance and functionality of complementary metal oxide silicon devices. In this work, we provide a synopsis of these ideas and conclude with a short term prognosis.

1. INTRODUCTION

“Spintronics” is the science and technology of manipulating the spin degree of freedom of a single charge carrier (electron or hole), or an ensemble of such carriers, to encode, store, process, and/or deliver information [1, 2]. This new field is an outgrowth of the older and more established field of magnetoelectronics that traditionally dealt with magnetic or magnetoresistive effects for sensing and storing information. Early successes in spintronics include the development of “passive devices” such as read heads for reading data stored in massively dense magnetic storage media, and nonvolatile magnetic random access memory (MRAM) [3]. The application of spintronics in “active devices” is a relatively new field. Research in this area initially focused on developing “spin-enhanced” transistors, where the performance of a conventional transistor was to be improved or augmented by utilizing spin effects. The spin field effect transistor and the spin lifetime transistor [4, 5] are examples of such devices. These devices are identical to a conventional field effect transistor with one difference: the gate voltage does not change the carrier concentration in the channel; instead, it changes the spin–orbit

ECECS Department, Universitfy of Cincinnati, Cincinnati, OH 45221, USA, [email protected]


173

174

CAHAY AND BANDYOPADHYAY

interaction in the channel to modulate the source-to-drain current. Since the current modulation could be achieved without changing carrier concentration, it was initially thought that these devices could be switched by expending less energy than conventional field effect transistors. However, this conjecture turned out to be incorrect. Because there is current flow in the device, there is still charge motion that consumes energy. Therefore, there is no fundamental advantage and ultimately what matters is whether it takes less energy to change the carrier concentration or less energy to change the spin–orbit interaction. A detailed study of this issue can be found in [6]. The spin unipolar junction transistor and the spin bipolar junction transistor [7, 8] are “spin-enhanced” junction transistors fashioned after the conventional bipolar junction transistor. The idea here is to exploit spin transport across junctions of dissimilar (ferromagnetic) materials to implement three-terminal devices that can amplify signals. These devices have also been recently compared with conventional silicon bipolar junction transistors and no significant advantage was found [9]. The unipolar junction transistor may not even be capable of signal amplification [9]. It therefore appears that as long as spin devices remain mere “clones” of conventional electronic devices, radical advances are not likely. Remarkable improvements can only accrue from paradigm shifts that exploit special properties of “spin,” that are absent in “charge.” This article is organized as follows. In Sect. 2, we give a brief description of the phenomenon of giant magnetoresistance discovered in the late 1980s which triggered a flurry of activity in the field of spintronics. In Sect. 3, we describe the spin-valve transistor, which was inspired by the metal base transistor but was aimed at capitalizing on the newly discovered giant magnetoresistance (GMR) phenomenon. In Sect. 4, we describe the spin diffusion transistor which is the only silicon spin-based transistor to date that has yielded a current gain greater than unity along with reasonable output current. Section 5 presents a brief introduction to a new class of silicon spin metal-oxide-semiconductor field-effect transistors (spin-MOSFETs), which offer increased functionality within traditional MOSFET technologies. Finally, Sect. 6 presents our conclusions and a short-term prognosis.

2. SPIN-BASED TRANSISTORS: THE EARLY HISTORY

The first three-terminal spin transistor was proposed by Johnson [10, 11]. It was not a silicon transistor, but we discuss it nevertheless since it is a pioneer in the world of spin transistors and it is a trivial step to replace the metal base of this transistor with silicon. The Johnson device was based on the phenomenon of GMR which was discovered independently by Baibich et al. [12] and Binasch et al. [13] in the late 1980s. Since this phenomenon is at the heart of many spin transistor concepts, we summarize its salient features and refer the reader to comprehensive reviews on the subject [14]. The electrical resistance of magnetic metallic multilayers can drop substantially in a magnetic field (close to 50% at tens of kG in the pioneering work of [12, 13]). This magnetoresistance (MR) of multilayers is referred to as GMR because it is much larger than the MR of the constituent bulk materials. The discovery of the GMR effect in Fe/Cr

6. ROOM TEMPERATURE SILICON SPIN-BASED TRANSISTORS

175

magnetic multilayers spawned voluminous research on layered magnetic systems. The origin of the resistance reduction due to applied field can be explained qualitatively as illustrated in Fig. 1 below starting with Mott’s model for the transport properties of transition metals. This model was developed by Mott as early as 1936 [15]. Mott postulated that electrical current through bulk ferromagnets is carried by two distinct types of carriers, one with spin parallel to the magnetization of the magnet and the other antiparallel to it. These two channels are relatively independent because the spin flip processes, eventually leading to their mixing in bulk samples, typically occur on a timescale much larger than the time it takes for both carriers to cross thin samples used in the multilayered structures. Mott’s original hypothesis was confirmed several decades later by current transport measurements in selectively doped ferromagnets [16, 17]. The GMR effect is a consequence of the nonequivalence of the majority and the minority spin channels and the fact that the magnetic state of a ferromagnetic sample can be changed with an external magnetic field. Figure 1a, b shows a multilayered sample composed of ferromagnetic (F) and normal (N) metal layers. In Fig. 1a an external magnetic field forces the magnetizations of the F-layers (indicated by arrows) to be oriented in parallel. Figure 1b shows the situation at zero field, when the magnetizations of the F-layers are antiparallel. This antiparallel alignment happens spontaneously at certain critical layer thickness of the paramagnetic spacer due to nonlocal exchange coupling. Spin-dependent scattering takes place in a ferromagnetic layer. Electrons with spin antiparallel to the magnetization of an F-layer are scattered more effectively than electrons with parallel spin. Figure 1a, b shows that each magnetic layer acts as a spin-selective valve: its magnetization direction determines whether it transmits predominantly spin-up or spin-down electrons. In the case of parallel-aligned magnetic layers, the resistance of the spin-up channel 2R↑ is relatively small, whereas the resistance of the spin-down channel 2R↓ is relatively large (Fig. 1c). The total resistance of the multilayer structure is RP = 2R↓R↑/(R↑ + R↓) which is less than 2R↑, or less than twice the

a

F

N

F

b

spin

c

spin

F

N

F

spin

R↑

R↑

R↓

R↓

d

spin

R↑

R↓

R↓

R↑

FIG. 1. Basic two spin-channel model of spin-valve effect leading to the phenomenon of giant magnetoresistance (from [14]). Reproduced with permission from IEEE.

176


smaller resistance. The antiparallel alignment of alternate magnetic layers leads to appreciable scattering of electrons in both spin channels. The total resistance of the multilayered structure is now RAP = R↑ + R↓ (Fig. 1d) which is larger than RP. Since the magnetic field aligns magnetizations of the F-layers to the parallel configuration, it changes the total resistance from RAP to RP. Therefore, we expect to see the resistance drop in a magnetic field, giving rise to a negative magnetoresistance. The larger the difference between RAP and RP, the larger is the magnetoresistance. The difference in the resistance between RP and RAP is also the cause of the spin-valve effect. The structure acts like a “valve,” passing a large current only when the ferromagnets have parallel magnetizations, and not otherwise. Note that the low resistance channel can correspond either to the majority spin, as in the Co/ Cu combination, or to the minority spin, as in the Fe/Cr combination. This difference accrues from the difference in the respective band structures. Most of the GMR experiments were originally carried out with the current flowing in the plane of the multilayers, a geometry referred to as current-in-plane (CIP) geometry. This configuration leads to fairly large resistance values since the sample length is typically orders of magnitude larger than the film thicknesses used in the multilayers. On the other hand, in the so-called current-perpendicular-toplane (CPP) geometry (which is the case shown in Fig. 1), the length of the sample is just the film thickness which is typically much thinner than the film’s lateral dimensions. Hence, this configuration leads to ultra-low resistances which can only be measured with extremely sensitive techniques. Johnson’s original idea for an all-metal spin-based transistor was to capitalize on the first successful reports of GMR measurements in the CPP geometry by Pratt et al. [18] at low temperature using superconducting electronics and later extended to room temperature by Gijs et al. using microstructure samples [19]. As depicted in Fig. 2, Johnson’s all-metal spin transistor consists of a spin-valve structure with a third terminal connected to the nonmagnetic spacer layer. The Johnson spin transistor device requires that the thickness of the layers be comparable to or smaller than the spin diffusion length of the material, which is of the order of a few nm in impure metallic samples [20]. An elementary description of the basic principle of operation of this device has been given by Johnson in [10, 11]. Preliminary experimental results of this all-metal spin transistor were reported by Johnson himself [21], leading only to small voltage output changes and no power or current gain. If such a device could generate a current gain, it could potentially be used to make logic devices. Furthermore, since the electrical characteristics of this purely ohmic device are magnetically tunable, it can potentially be used as a field sensor or as a nonvolatile MRAM.

3. THE SPIN-VALVE TRANSISTOR

Soon after the proposal by Johnson, Monsma et al. [22] fabricated the first hybrid spintronic device in which ferromagnets and semiconductors were closely integrated (see Fig. 3). This device is now usually referred to as the spin-valve transistor


177

FIG. 2. Schematic of the Johnson spin transistor.

FIG. 3. (Left) Schematic of the spin-valve transistor (SVT) (from [22]); (Right) Schematic energy band diagram of the SVT in forward active mode of operation. The emitter Schottky barrier height at the emitter–base junction is slightly larger than the collector Schottky barrier height at the base–collector junction. Some hot electrons injected from the emitter still have enough energy to emit over the top of the collector Schottky barrier. Reproduced with permission from the American Physical Society.

(SVT) and is basically a reincarnation of the well-known metal base transistor proposed in the 1960s [23]. First fabricated in 1995, the SVT consists of the typical emitter/ base/collector configuration of a bipolar junction transistor in which the thin base region is formed of a spin CPP multilayer containing at least two magnetic layers separated by a normal metal spacer. The two magnetic layers act as spin polarizer

178


and analyzer for electrons injected from the n-type emitter. The relative orientation of the magnetic layers in the base region, which can be altered with a magnetic field in the plane parallel to the emitter–base and base–collector interfaces, determines the amount of injected current transmitted across the base and reaching the collector contact. In the active mode of operation, the collector Schottky barrier is reverse biased and the emitter Schottky is forward biased. As a result, in the SVT, the collector current depends strongly on the magnetic configuration of the base region. In the first SVT report by Monsma et al. [22], a 215% change in the collector current was observed with an applied magnetic field of 500 Oe at low temperature (77 K), with the typical hysteresis characteristic of the spin-valve effect (see Fig. 4). The SVT is a hot-electron device as a result of the injection of electrons from the emitter across the forward-biased emitter–base junction. Even if the total base thickness is rather thin (a few hundred angstroms), the hot electrons will lose some energy when crossing the base depending on the bulk (or volume) scattering in each layer and the amount of scattering at the various interfaces bordering the base. This hot-electron scattering depends strongly on the magnetic configuration of the magnetic multilayer. In the case of antiferromagnetic alignment of adjacent magnetic layers in the GMR base, both spin-up and spin-down carriers experience heavy scattering in one of the magnetic layers. As a result, the average kinetic energy of both spin types injected from the emitter decays exponentially with distance in the base region. On the other hand, for the case of ferromagnetic alignment of adjacent ferromagnetic layers in the base, only one type of spin will get scattered heavily whereas the other will reach the base–collector interface without much scattering. In the SVT, the number of hot electrons retaining enough energy to surmount the

FIG. 4. Magnetocurrent of first spin-valve transistor reported by Monsma et al. [22], as a function of applied magnetic field, with a base composed of four (Cu 2 nm)/(Co 1.5 nm) bilayers recorded at 77 K. There is a large (390%) change in the collector current at fairly small value of the external magnetic field. Reproduced with permission from the American Physical Society.


179

collector Schottky barrier and contributing to the collector current is therefore strongly dependent on the magnetic configuration of the base. In the case of parallel magnetic alignment, more carriers will be emitted over the collector barrier and the collected current will be larger. The challenge of SVT technology is to design the transistor such that the magnetocurrent ratio γMC defined as

(

γ MC = I CP − I CAP

)I

AP C

,

where ICP and ICAP refer to the collector currents for the parallel (P) and antiparallel (AP) configurations, is the largest for a given magnetic field applied to switch between the two configurations. Efforts to meet this challenge have led to various modifications of the emitter–base junction design so as to increase the hot-electron emitter injection efficiency, and the collector–base junction design to increase the amount of hot-carrier collection. In the original SVT proposed by Monsma et al. [22], the injection energy of hot electrons incident from the emitter is fixed by the height of the Schottky barrier between the emitter and the base. In a related device based on a metal(emitter)/thin insulator/ metal(GMR base)/semiconductor(collector) structure proposed by Mizushima et al. [24] (referred to as the magnetic tunnel transistor (MTT) ), this limitation was overcome by using a tunnel junction as the emitter. The thin insulator acts as a tunnel barrier, injecting hot electrons into the metal base at an energy given by the tunnel bias voltage between the metal emitter and the base. This provides additional tunability of the hot-electron energy, allowing more detailed spectroscopic studies of spin transport across the base. One major point of concern in MTT structures is the reliability of the ultra-thin insulator (oxide barrier) which is subjected to a large bias (1–2 V) and a large current density. To mitigate this problem, LeMinh et al. [25] proposed an MTT device in which the metal emitter is replaced by silicon. As a result, the voltage drop across the emitter–base region is dropped partly across the semiconductor emitter depletion region and partly across the tunnel oxide, thus reducing the voltage stress across the latter. However, the energy of the hot electrons injected into the base is still tunable as the portion of the emitter–base bias dropped across the tunnel insulator raises the conduction band at the semiconductor/tunnel barrier interface with respect to the Fermi level of the base metal. Compared to a MTT with a metal emitter, the voltage drop over the thin tunnel oxide is reduced enabling stable device operation at higher bias voltages. LeMinh et al. [25] recently fabricated such a device with a magnetocurrent ratio up to 166% and a steep enhanced transfer ratio reaching 6 × 10−4 at an emitter current of 200 mA. In SVT technology, the poor transfer ratio has been the limiting factor leading to current transfer ratio a (ratio of the collector current IC divided by the emitter current IE) much smaller than unity. This was a major drawback encountered in the earlier development of the metal base transistor, as well. Despite this shortcoming, the Monsma transistor represents a very important step in the evolution of silicon spintronics because it is an active device whose electrical characteristics are magnetically tunable. As pointed out in the recent review article by Jansen on SVT technology [26], the

180


most influential aspect of the Monsma transistor and its derivatives is that it showed the value of functional integration of semiconductor and ferromagnetic materials into hybrid electronic devices. Room temperature magnetocurrent ratio as large as 400% in small magnetic field (typically a few tens of Oe) are now routinely obtained [27]. More recently, the investigation of MTT structures has been successfully extended to GaAs-based devices [28]. Much progress has been made in optimizing the device performance focusing on the output current level and noise sources. Further improvements are still required in order to capitalize on the huge magnetic sensitivity of these structures which make them very attractive candidates for future generations of magnetic sensors or magnetic memories. In that context, MTT structures, scaled to submicron dimension, will be relevant [26]. SVT and MTT technologies have opened up a new route to the systematic study of the fundamental physics of spin-dependent transport of hot electron at energies of the order of 1 eV. New insights into the fundamental physics of spindependent hot-electron scattering have been obtained, including the dominance of the volume effects over interface effects in the spin-dependent transmission across the base, the effects of thermal spin waves, and the surprisingly important role of elastic scattering processes. For instance, it has been realized that hot-electron spin filtering may have some attractive features for spin injection into a semiconductor, in particular the ability to reach a spin polarization close to 100% with conventional ferromagnets. Furthermore, the development of SVT and MTT technologies have led to a detailed study of hot-electron spin transport through half-metallic ferromagnets and oxides which will undoubtedly lead to future proposals of new types of hybrid electronic devices combining ferromagnets and semiconductors.

4. THE SPIN DIFFUSION TRANSISTOR

The Johnson spin transistor and SVT discussed above are based on all-metal and hybrid metal–semiconductor combinations with the common feature that the spin selective transport is limited to the metallic components of the device. A siliconbased spin transistor design trying to take advantage of spin transport through the semiconductor itself has been reported recently based on an original concept proposed by Gregg and Spark [29]. To date, this is the only silicon spin transistor with a current gain greater than unity and with reasonable output current. The basic operation of this device (referred to as the spin diffusion transistor) is similar to a bipolar junction transistor (although it is most closely related to the classical tunnel transistor) [30]. An energy band diagram for this device, as well as a schematic of the first reported experimental prototype, is shown in Figs. 5 and 6, respectively [31]. In this device, a spin polarized current is injected from the emitter into the electric field-screened base region through a tunnel barrier [32]. The current which diffuses across the base is driven primarily by a carrier concentration gradient which forces the carriers injected by the emitter to wander towards the base along the top of a second tunnel barrier, above which lies the collector (see Fig. 6). This second tunnel barrier is also spin selective (according to the magnetic


181

FIG. 5. Band structure of the spin diffusion transistor (from [34]). Reproduced with permission from IEE.

FIG. 6. Schematic cross section of the first fabricated spin diffusion transistor (from [34]). Reproduced with permission from IEE.

orientation of the collector) and determines if the polarized carriers injected from the emitter are allowed to fall into the collector or not. Preliminary experimental realizations of the spin diffusion transistors [31, 33, 34] have produced devices with current gain slightly larger than unity, which is three orders of magnitude larger than what any other spin transistor (such as the SVT discussed earlier) has reported to date. This is still far from the typical current gain of 100 for regular bipolar transistors. However, one interesting feature of spin diffusion transistor is that its current–voltage characteristic can be magnetically tuned by manipulating the spin selectivity of the energy barrier via an externally applied magnetic field of just a few hundred Oersteds. Figure 7 shows some of the IC–VEC characteristics of n-type and p-type spin diffusion transistors recorded in the common-collector configuration and zero applied magnetic field [34]. The devices with the structure depicted in Fig. 6 were

182


FIG. 7. IC–VEC characteristics of spin diffusion transistors in common-collector configuration and zero applied external magnetic field (a) p-type and (b) n-type spin diffusion transistor. The step size of IB is 0.2 μA with the starting and ending currents as indicated in the boxes (from [34]). Reproduced with permission from IEE.

fabricated using standard photolithography on n- and p-type silicon-on-insulator (SOI) wafers with a measured resistivity between 2 and 1,000 Ω cm. First, an insulating layer of 600 nm of SiO2 was grown on the front (active silicon) side of the wafer. This layer was then removed in selected areas to make the base contacts, which were doped to form ohmic contacts. Next, the emitter contacts were etched through the insulating SiO2. On the back (handle silicon) side of the wafer, another layer of insulating SiO2 is deposited, which is then removed in selected areas to form the collector contacts. A pit is etched through the handle Si to the buried oxide layer, and then through the buried oxide layer to the active Si. Tunneling barriers of Si3N4 were deposited on the collector and emitter contacts by low-pressure epitaxy,


183

followed by sputtering on both sides of the wafers of 30 nm of Co and 1 μm of Al (for the electrical contacts). When biased in the common collector configuration, the transistor exhibits characteristics (see Fig. 7) similar to that of a conventional bipolar transistor. The difference in the I−V characteristics between the n- and p-type transistors can be explained by either different doping in the silicon resulting in different minority carriers traversing the base, or electron domination of the tunneling process (due to the difference in effective masses for electrons and holes) causing one device to be a majority carrier device and the other to be a minority carrier device [34]. The emitter current as a function of base current and emitter–collector voltage is as high as −1.56 μA (−3.09 μA) for p-type (n-type) spin diffusion transistor, which occurs at VEC = −1 V and IB = −1.0 μA. Not only is this a higher output current than what can be achieved in an SVT (by three orders of magnitude), but it also occurs at a lower voltage. At a slightly higher base current of −0.6 μA (see Fig. 8), the current gain b is 1.03 ± 0.03 (0.96 ± 0.03) for p-type (n-type). At a base current of −0.8 μA, the current gain β is 1.06 ± 0.05 for the p-type transistor. Furthermore, the base transport factor a = IE/IC is calculated to be 1 (within experimental accuracy) for positive and negative μEC for both the p-type and n-type transistor at IB = 0 μA. This means that virtually all of the emitter current is reaching the collector. Since the current gain is not identically equal to 1, the base current must be modifying either the amount of recombination in the Si, or the current injected into the Si from the emitter. Application of a magnetic field is expected to affect the I–V characteristics in two ways. First, the magnetization of the emitter and the collector Co contacts can be differentially manipulated, thereby introducing a spin-selective tunneling magnetoresistance effect that modulates the collector current. Second, the applied magnetic field decreases the mean free path in the silicon base via the Lorentz magnetoresistance effect thereby also affecting the collector current. Both of these are observed in these devices [34]. The transistor was again operated in common-collector mode with the magnetic field applied in the plane of the transistor (perpendicular to the current). The results in Fig. 9 are typical and plot the emitter current as a function of applied emitter–collector voltage and magnetic field at IB = −0.6 μA. These results show a variation in the emitter current as a function of the magnetic field indicating that the transistor behaves as a magnetically tunable device with a field-dependent gain. The maximum variation of the average current gain (where b was averaged for all VEC > 0.4 V and for each base current) relative to the current gain at H = 0 Oe, was −11 ± 3% (−15 ± 2%) for p-type (n-type) and occurred at 75 Oe (110 Oe) for IB = −0.6 μA. Spin diffusion transistors still have several shortcomings, which, if eliminated, may provide improved performance. There is a need for a better choice of tunnel barriers to replace the suboptimal Si3N4 barriers, which conduct initially via hopping conduction, a process well known to partially destroy the spin polarization of the carriers. In a second generation of spin diffusion transistors, Dennis et al. used Al2O3 tunnel barriers. However, this approach still needs significant work since the deposition of Al directly onto Si results in the formation of AlSi,

184


FIG. 8. Calculated current gain at zero field as a function of emitter–collector voltage for (a) p-type and (b) n-type spin diffusion transistor in zero applied magnetic field. The step size of IB is 0.2 mA with the starting and the ending currents as indicated in the boxes. The current gain is determined by calculating the change in collector current for unit change in base current. The gain was determined between adjacent pairs of base currents (as shown in the legend) at all voltages (from [34]). Reproduced with permission from IEE.

which is a metal, leading to a destruction of the spin polarization of the current injected from the emitter as well as an increase of the emitter contact resistance. The spin diffusion transistor would probably benefit from the use of different magnetic materials in the emitter and the collector contacts since the current devices are characterized by insufficient magnetic switching differential (where each contact switches quickly at a particular field) between the three contacts. In addition, shrinking the device to submicron dimensions in all directions will result in a single domain magnetic contact that should sharpen up the magnetic


185

FIG. 9. IE–VEC characteristics as a function of applied magnetic field for the n-type spin diffusion transistor in common-collector configuration with IB= −0.6 μA (a) Full I–V characteristics and (b) blow-up of the black boxes from (a) for detail (from [34]). Reproduced with permission from IEE.

switching behavior of the device. A reduction of the contact resistances should improve the magnitude of current gain as well as the magnetic characteristics of the transistor. Moreover, the doping profile in these spin diffusion transistors is not optimal since the dopant changes polarity in the middle of the silicon base, which creates a weak p–n junction that in turn dilutes the spin polarization of the carriers as they diffuse across the base. This, in turn, reduces the maximum magnetic sensitivity. Additional improvements and changes in the design are discussed in more detail in the recent review article of Dennis et al. [34].

5. SPIN-MOSFETS

Over the last few years, Sugahara and Tanaka [35–37] have proposed a new class of spin transistors referred to as spin-MOSFETs and some of these devices are depicted in Fig. 10. These spin-MOSFETs can be classified according to the structure


186

a

Gate

Gate oxide

FM source

FM drain Si Schottky

b

junction

Gate Gate oxide HMF drain

HMF source Si Schottky

c

junction

Gate

Gate oxide FM(HMF) drain

FM(HMF) source

Schottky junction

d

Gate

FS channel

Gate oxide FS drain

FS source Si pn

junction

FIG. 10. New class of spin-MOSFETs proposed by Sugahara and Tanaka [37]. The source and drain contacts can be either a ferromagnetic metal (FM) or half-metallic ferromagnet (HFM). Alternatively, p–n junctions with a ferromagnetic semiconductor in the source and the drain regions can be used. The semiconductor channel can either be a nonmagnetic semiconductor (Si or Si-based alloys) or a ferromagnetic semiconductor. Reproduced with permission from IEE.

(Schottky or p–n junctions) of the source/drain and the source and drain materials (ferromagnetic metal, half-metallic ferromagnet, or ferromagnetic semiconductor). The attractiveness of the proposed spin-MOSFETs is their compatibility with present silicon technology and also their high degree of scalability as ordinary MOSFETs. As will be discussed below for the specific spin-MOSFET shown in Fig. 10a, each of these devices not only exhibit significant magnetocurrent ratios but also a high transconductance, a low power-delay product, and a low OFFcurrent (leakage current in the OFF state). These features make this family of spinbased devices certainly worth pursuing as attractive building blocks for future VLSI


187

applications, including very high-density nonvolatile memory cells and reconfigurable logic gates. Work is actually under way at IMEC in Belgium and other places around the world to produce some of the spin-MOSFETs depicted in Fig. 10. This approach could greatly benefit from the SOI technology currently emerging as a serious contender for implementation of future generation of microelectronics circuits [38, 39]. Furthermore, there has been recent progress in identifying possible channel materials following the theoretical prediction that Si1−xMnx and Ge1−xMnx should behave as ferromagnetic semiconductors [40–42]. Investigations of possible materials for source and drain ferromagnetic contacts with a large spin polarization, such as CoFe, CoFeB, and Fe3Si [43–45], are also under way. As in ordinary MOSFETs, the basic design of Spin-MOSFETs consists of a MOS capacitor and ferromagnetic contacts for the source and the drain. To maintain the large ON-current (high gm) and small OFF-current (low power) of ordinary MOSFETs, the source and the drain in spin-MOSFETS must have an ohmic character when the transistor is in the ON-state and must have a blocking effect of the current (low leakage current between source and drain) when the transistor is in the OFF-state. An additional functionality is expected when using ferromagnetic contacts since the amount of drain current should be affected by the magnetization configuration (parallel or antiparallel magnetization) of the source and the drain contacts. Actually, if spin-MOSFETs are expected to become the basic component of future generations of high-density integrated circuits, one of the important challenges will be the magnetization reversal mentioned above. In fact, if the magnetic field needed for magnetization reversal of the contacts is induced by current variation through typical interconnects, then it would lead to intolerable power dissipation because the current required for magnetization reversal increases when devices have nanoscale dimensions. Fortunately, two more power efficient schemes have been identified recently, including the current-induced magnetization reversal (CIMR) via spin transfer torque [46] and the electrical manipulation of magnetization reversal (EMMR) of a ferromagnetic semiconductor [47]. Both of these schemes could be used for fast and reliable switching in spin-MOSFET integrated circuits with nanoscale components. The easiest way to fabricate a spin-MOSFET would be to replace the metallic source and drain contacts in a Schottky barrier MOSFET [48] with ferromagnetic Schottky junctions to the Si channel (Fig. 10a). This device could work with n-type or p-type channel operating in the accumulation or depletion mode. Hereafter, the principle of operation of the device is discussed assuming an n-channel accumulation type spin-MOSFET. The band diagram from source to drain in such a spinMOSFET is illustrated in Fig. 10a under a common source bias condition with and without a gate–source bias VGS for the case of parallel magnetization of the source and drain contacts. In Fig. 11a, ΦSB is the Schottky barrier height for spin-up and spin-down electrons at the source–channel interface. When a drain–source bias VDS (>0) is applied at VGS = 0, neither spin-up nor spin-down electrons are injected from the ferromagnetic source into the channel since this Schottky barrier contact is reverse biased. In that case, the conduction band profile in the channel is as shown by the upper dotted curve in Fig. 11a. With VGS > 0, the width of the source


188 E

a

fSB k

k

VGS=0 VGS>0

EF

E

EF↓

eVDS

EF↑

k k EF↓

FM source

EF↑

Si channel FM drain

b

VGS=0

E

fSB k

VGS>0

EF

E

k EF↓

eVDS

EF↑

k k

FM source

EF↑

EF↓

Si channel FM drain

FIG. 11. Schematic band diagram for the spin-MOSFET shown in Fig.10a as a function of the gate bias. Also shown are the Fermi levels of the two spin bands in the contacts used to model the ferromagnetic source and drain contacts. FSB is the Schottky barrier height for spin-up and spin-down electrons at the source–channel interface (from [37]). Reproduced with permission from IEE.

Schottky barrier is reduced due to the field effect induced by the gate and the new conduction band profile in the channel is shown qualitatively as the upper solid curve for that biasing configuration. As a result, both spin-up and spin-down electrons are injected from the ferromagnetic source into the channel via tunneling through the Schottky barrier which is now much thinner owing to the applied positive gate voltage. The electrons injected in the channel are therefore spin polarized and the spin-injection efficiency depends on VGS and the spin polarization of the ferromagnetic source (due to the difference in populations of the spin bands in the contact). In this spin-MOSFET, the Schottky barrier at the source acts not only as a blocking contact (controlling the OFF-current of the device) when VGS = 0 but also as a gate voltage-controlled spin injector into the channel when VGS > 0. Under the realistic assumption of ballistic transport through the channel for nanoscale spin-MOSFETs, the drain current is expected to depend on the relative magnetization configurations of the ferromagnetic contacts. In the parallel configuration, electrons injected from the majority spin band from the source can be transported to the majority band of the FM through the channel and the device will have a large


189

drain current. As shown in Fig. 11b, the antiparallel magnetization can then be established by flipping the magnetization of the drain contact. The drain current should then decrease since the transport of majority spin electrons from the source is restricted only to the minority spin band of the drain when the source and drain have antiparallel magnetizations. Sugahara carried out an analysis of the spin-MOSFET described above based on a two-current model similar to the one used to describe the GMR effect. The drain current, magnetocurrent ratio, spin injection efficiency, and transconductance of the device were calculated under the assumption of ballistic transport starting with the Tsu–Esaki formula [49] for a device with a thin-film-geometry shown in Fig. 10a. Spin–orbit interaction in the channel was ignored, but it is not a serious oversight since spin–orbit interaction in silicon is weak (only the Rashba interaction will be operative and the Dresselhaus interaction will be absent since silicon has bulk inversion symmetry). The gate oxide (SiO2) thickness tox is assumed to be 1 nm, the channel region thickness tCH is set to 3 nm, and the channel length LCH is set to 10 nm. The source and drain regions were assumed to be made of transition metal alloys and the Fermi levels of the majority and minority spin bands are set to 2 eV and 50 meV. The Schottky barrier height FSB is equal to 200 meV. We first focus on the spin injection efficiency η defined as η = (ID↑P − ID↓P)/(ID↑P + ID↓P), where ID↑P and ID↓P are the drain current due to the majority and minority spin bands incident from the source, respectively. Figure 12 is a plot of the spin injection efficiency from the source contact into the channel of the spin-MOSFET described above for a drain to source bias of 0.5 V. The latter is large enough so that the drain current through the device becomes independent of the magnetization configuration of the two contacts (parallel or antiparallel), as shown in Fig. 13 . This is because the Fermi levels for the two spin bands in the drain contact are low enough compared to the placement in the source contact. As a result, the drain current

100

η(%) 50

V DS =0.5V 0 0.2

0.4

0.6 BiasVGS(V)

0.8

1.0

FIG. 12. Spin injection efficiency h from the ferromagnetic source into the channel as a function of VGS at VDS = 0.5 V for the case of parallel magnetization of the source and drain contacts. The spin injection efficiency is defined as (ID↑P − ID↓P)/(ID↑P + ID↓P) where ID↑P and ID↓P are the drain currents due to the majority and minority spin carriers incident from the source, respectively (from [37]). Reproduced with permission from IEE.


190

P AP

Current ID,ID (μA/μm)

2000

V GS =1.0V

P ID AP ID

1000

0.8V 0.6V

0.2V 0

0

0.25 Bias VDS(V)

0.4V 0.5

FIG. 13. Output characteristics of the spin-MOSFET with ferromagnetic source and drain contacts. IDP and IDAP are the drain currents when the magnetizations of the source and drain contacts are parallel and antiparallel, respectively. The current–voltage characteristics are plotted as a function of VDS with VGS varied in step of 0.2 V up to 1 V. The threshold voltage for this spin-MOSFET is 0.2 V (from [37]). Reproduced with permission from IEE.

is limited by the supply functions of the two spin bands in the source and the amount of tunneling through the source Schottky barrier rather than by the availability of electronic states in the drain for the electrons incident from the source to tunnel into. In this case, the magnetoresistive effect of the drain is negligible. As the Schottky barrier at the source/channel contact is “thinned down” by the application of a positive gate potential, more electrons from the contact with energies below their respective Fermi level can tunnel through the barrier at the source contact but eventually the drain current saturates when the limit provided by the supply function of the contact is reached. As shown in Fig. 12, the spin injection efficiency eventually reaches a very high value (in excess of the 73% value of the spin polarization of the source contact for the selection of the contact Fermi levels above). In this spin-MOSFET, the gate-controlled Schottky barrier at the source/channel junction therefore acts as a spin injector with variable spin injection efficiency. The latter will be closer to 100% if ferromagnetic contacts can be found with Fermi energy for the minority spin band much smaller than the Fermi energy for the majority spin band. The ideal case would be to use half-metallic ferromagnetic source for which only the majority spin band is occupied. The main challenge is to find such materials working at room temperature [50]. Figure 13 also shows that the value of drain current is similar to those reached in sub-100 nm scale MOSFETs [38] even for VGS less than 1.0 V. The drain current could even be increased further by appropriate selection of the ferromagnetic contact such that the Schottky barrier height FSB would be reduced, or by decreasing the gate oxide thickness (while keeping the leakage current through the gate oxide under control). Figure 14a is a plot of the magnetocurrent ratio γMC = (IDP − IDAP)/IDAP as a function of VDS with VGS = 1.0 V showing that gMC is close to 100% for VDS = 50 mV and


MC

(%)

100

50

γ

Magnetocurrent ratio

a

191

V GS =1.0V 0 0

0.25

0.5

Bias VDS (V)

MC

(%)

100

50

γ

Magnetocurrent ratio

b

VDS =50mV 0

0.2

0.6

1.0

Bias VGS (V) FIG. 14. Magnetocurrent ratio γMC = (IDP − IDAP)/IDAP (a) as a function of VDS when VGS = 1.0 V and (b) as a function of VGS when VDS = 50 mV (from [37]). Reproduced with permission from IEE.

decreases sharply as VDS increases. The latter results from the fact that the difference between IDP and IDAP is smaller at larger VDS, as shown in Fig. 13. The dependence of gMC on VGS for VDS = 50 mV is illustrated in Fig. 14b. In this case, γMC increases VGS as a result of the larger difference between IDP and IDAP at larger gate potential as illustrated in Fig. 13. The results discussed above show that the spin-MOSFET exhibits magnetization-configuration-dependent current–voltage characteristics. Additionally, the transconductance and output current of the device also reach values comparable to the values recorded with state-of-the-art sub-100 nm ordinary MOSFETs as illustrated in Fig. 15. The large transconductance gm (solid curve) of the spin-MOSFET leads to a small propagation delay time tpd = CL/gm, where CL is the load capacitance, and a large voltage gain GV = gm/gD, where gD is the channel conductance given by


192

102

P

gm (mS/mm)

Transconductance

3000

Current ID (μA/μm)

104

4000

2000

1000

100 V DS = 0.5V

0

0

0.5

1

BiasVGS (V) FIG. 15. Transconductance gm (solid curve) and drain current IDP (dashed curve) as a function of VGS when VDS = 0.5 V (from [37]). Reproduced with permission from IEE.

∂IDP/∂VDS (dashed curve). Furthermore, as a result of its large gm value, the spinMOSFET can be operated with a low voltage swing, leading to a small power-delay product or switching energy. Sugahara has calculated the subthreshold swing of the spin-MOSFET to be as small as 100 mV per decade (60 mV per decade is the theoretical limit for MOSFETs at room temperature), implying a relatively small OFFcurrent necessary to obtain a good enough ON/OFF ratio for logic applications of the device [37]. Sugahara and Tanaka [35, 36] have shown that the multifunctionality and figures of merit of other types of spin-MOSFETs make them equally good candidates for future generations of microelectronics circuits. For instance, one advantage of the spin-MOSFET family based on a ferromagnetic semiconductor (FS) channel shown in Fig. 10d is that they can be used to implement a nonvolatile cell memory using the circuit shown in Fig. 16. When the device size is pushed from the submicron to the nanoscale regime, each cell size in the storage array, made up of a single spinMOSFET, will ultimately occupy a miniscule area leading to an extremely high degree of device integration. The storage array is designed so that each cell shares a gate connection (word-line; WL) and a source connection (source line; SL) with the other cells in the same column, whereas the drain connection (bit-line; BL) is shared by the cells in the same row. This allows a memory access in a random order. Each spin-MOSFET can store 1 bit of binary information, which can be varied by the relative magnetization configuration of the FS channel and ferromagnetic source and drain contacts. The readout operation is performed by applying a bias to the selected cell. The amount of the drain current reveals the stored information, i.e., large and small drain currents correspond to the parallel and antiparallel magnetizations, respectively. For writing operation, EMMR is used for the magnetization reversal of the FS channel. During the writing process, the selected source line and bit line must be connected to a high bias in order for the carrier density of the FS channel to


193

FIG. 16. Nonvolatile memory cell using spin-MOSFETs as building blocks (from [36]). Reproduced with permission from the American Institute of Physics.

be significantly reduced or depleted by the widened depletion layers of reverse biased source/drain junctions. The magnetization reversal of the FS channel is performed by a magnetic field induced by the current through the word line. Once the ferromagnetic ordering of the FS channel is changed to a paramagnetic character due to the reduction of the carrier density in the FS channel, the magnetization reversal can then be accomplished via a very small magnetic field, much less than the coercivity of the FS channel. After the source and the drain biases and then the current in the word line are removed, the ferromagnetic ordering is returned in the FS channel with newly stored information depending on the magnetization direction. During this process, the other cells in the memory array hold their own data since the channel region of these cells is only partially depleted and thus their ferromagnetic ordering and large coercivity still remain intact in the FS channel. The proposed readout/writing

194


schemes present other advantages, including a fast readout time, an excellent fault tolerance for readout, and low power dissipation during the writing process.

6. OUTLOOK

This chapter has presented a bird’s eye view of the current state-of-the-art in the field of spin-based transistors employing silicon technology. Ultimately, as enunciated by Sugahara and Tanaka [35], the following five important criteria should be kept in mind when designing and fabricating spin-based silicon transistors in order for them to have a chance to be competitive (1) spin-based transistors should have a large magnetocurrent ratio for nonvolatile memory and reconfigurable logic functions, (2) a high transconductance for high-speed operation, (3) a high amplification capability (voltage, current, and power gains) to restore signal levels at logic nodes and the potential to achieve large fan-out, (4) a small power-delay product and small OFF-current for low-power dissipation, and (5) a simple device structure for high degree of integration and high production yield. Only then spin-based devices will offer an improvement over the currently developed VLSI technologies [38, 39]. Meanwhile, spintronics is poised to make important contributions to a number of passive and active devices and systems distinct from “transistors.” They include very low current monitors [51], extremely sensitive magnetic field sensors [52], very low power single spin logic switches [53], programmable spintronic logic devices based on magnetic tunnel junction elements [54], rotational speed control systems [55], positioning control devices in robotics [56], perimeter defense systems, and magnetic biosensing platform based on the on-chip manipulation of magnetically labeled biomolecules [57], among others. Also, the emerging field of “organic spintronics” can usher in revolutionary advances [58]. Organic semiconductors, particularly π-conjugated polymers are optically active. They are a likely platform to merge spintronics and optics, leading possibly to multifunctional “opto-spintronic” chips compatible with silicon manufacturing. Such chips, where optics and spintronics are integrated to perform seamless signal processing and communication, will be versatile and extremely valuable in terms of speed and performance. Acknowledgments The authors thank C.L. Dennis for Figs. 5–9, S. Sugahara and M. Tanaka for Figs. 10–16, and Junjun Wan for Fig. 3. S. Bandyopadhyay acknowledges support from the Air Force Office of Scientific Research grant FA9550-04-1-0261.

REFERENCES 1. D.D. Awschalom, M.E. Flatte, and N. Samarth, Scientific Am., 286(6), 66 (2002). 2. S.A. Wolf and D.M. Treger, Proc. IEEE, 91, 647 (2003). 3. P.P. Freitas, F. Silva, N.J. Oliveira, L.V. Melo, L. Costa, and N. Almeida, Sensors Actuators A, 81, 2 (2000).


195

4. S. Datta and B. Das, Appl. Phys. Lett., 56, 665 (1990). 5. J. Schliemann, J.C. Egues, and D. Loss, Phys. Rev. Lett., 90, 146801 (2003); X. Cartoixa, Z.Y. Ting, and Y.C. Chang, Appl. Phys. Lett., 83, 1462 (2003); K.C. Hall, K. Gundogdu, J.L. Hicks, A.N. Kocbay, M.E. Flatte, T.F. Boggess, K. Holabird, A. Hunter, D.H. Chow, and J.J. Zink, Appl. Phys. Lett., 86, 202114 (2005). 6. S. Bandyopadhyay and M. Cahay, Appl. Phys. Lett., 85, 1433 (2004). 7. J. Fabian, I Zutic, and S. Das Sarma, Appl. Phys. Lett., 84, 85 (2004). 8. M.E. Flatte and G. Vignale, Appl. Phys. Lett., 78, 1273 (2001); M.E. Flatte, Z.G. Yu, E. JohnstonHalperin, and D.D. Awschalom, Appl. Phys. Lett., 82, 4740 (2003); M.E. Flatte and G. Vignale, J. Appl. Phys., 97, 104508 (2005). 9. S. Bandyopadhyay and M. Cahay, Appl. Phys. Lett., 86, 133502 (2005). 10. M. Johnson, Science, 260, 320 (1993). 11. M. Johnson, IEEE Spectrum, 31(5), 47 (1994). 12. M.N. Baibich, J.M. Broto, A. Fert, F. Nguyen Van Dau, F. Petroff, P. Eitenne, G. Creuzet, A. Friederich, and J. Chazelas, Phys. Rev. Lett., 61, 2472 (1988). 13. G. Binasch, P. Grenberg, F. Saurenbach, and W. Zinn, Phys. Rev. B, 39, 4828 (1989). 14. A detailed review of the work on giant magnetoresistance using magnetic multilayers is given by M.A.M Gijs and G.E.W. Bauer, Adv. Phys., 46, 285 (1997). 15. N.F. Mott, Proc. R. Soc., 153, 699 (1936). 16. A. Fert and I.A. Campbell, Phys. Rev. Lett., 21, 1190 (1968). 17. A. Fert and I.A. Campbell, J. Phys. F: Metal. Phys., 6, 849 (1975). 18. W.P. Pratt, Jr., S.-F. Lee, J.M. Slaughter, R. Loloee, P.A. Schroeder, and J. Bass, Phys. Rev. Lett., 66, 3060 (1991). 19. M.A.M. Gijs, S.K.J. Lenczowski, and J.B. Giesbers, Phys. Rev. Lett., 70, 3343 (1993). 20. I. Zutic, J. Fabian, and S. Das Sarma, Rev. Mod. Phys., 76, 351 (2004). 21. M. Johnson, J. Appl. Phys., 75, 6714 (1994). 22. D.J. Monsma, J.C. Lodder, Th.J.A. Popma, and B. Dieny, Phys. Rev. Lett., 74, 5260 (1995). 23. S.M. Sze, Physics of Semiconductor Devices (Wiley, New York, NY, 1969), Chapter 11. 24. K. Mizushima, T. Kinno, T. Yamauchi, and K. Tanaka, IEEE Trans. Magn., 33, 3500 (1997). 25. P. Leminh, H. Gokcan, J.C. Lodder, and R. Jansen, J. Appl. Phys., 98, 076111 (2005). 26. For a recent review of the basic science and technology of the spin-valve transistor, see R. Jansen, J. Phys. D: Appl. Phys., 36, R289 (2003). 27. R. Jansen, H. Gokcan, O.M.J. van’t Erve, F.M. Postma, and J.C. Lodder, J. Appl. Phys., 95, 6927 (2004). 28. G. Salis, R. Wang, X. Jiang, R.M. Shelby, S.S.P. Parkin, S.R. Bank, and J.S. Harris, Appl. Phys. Lett., 87, 262503 (2005). 29. J.F. Gregg and P.D. Sparks, US Patent # 6218718 (2001). 30. C.A. Mead, Proc. IRE, 48, 359 (1960); H. Kisaki, Proc. IEEE, 61, 1053 (1973). 31. C.L. Dennis, C. Siristhatikul, G.J. Ensell, J.F. Gregg, and S.M. Thompson, J. Phys. D: Appl. Phys., 36, 81 (2003). 32. As described in [29], a wide variety of spin diffusion transistor designs are possible based on p–n junctions, Schottky barriers, or spin tunnel junctions. 33. C.L. Dennis, PhD Thesis, The University of Oxford (2004). 34. C.L. Dennis, C.V Tiusan, J.F. Gregg, G.J. Ensell, and S.M. Thompson, IEE Proc.-Circuits Dev. Syst., 152, 340 (2005). 35. S. Sugahara and M. Tanaka, Appl. Phys. Lett., 84, 2307 (2004). 36. S. Sugahara and M. Tanaka, J. Appl. Phys., 97, 10D503 (2005). 37. S. Sugahara, IEE Proc.-Circuits Dev. Syst., 152, 355 (2005). 38. L.Chang, Y. Choi, D. Ha, P. Ranade, S. Xiong, J. Bokor, C. Hu, and T. King, Proc. IEEE, 91, 1860 (2003). 39. G.K. Celler and S. Cristoloveanu, J. Appl. Phys., 93, 4955 (2003). 40. A. Stroppa, S. Picozzi, A. Continenza, and A.J. Freeman, Phys. Rev. B, 68, 155203 (2003). 41. Y.D. Park et al., Science, 295, 651 (2002).

196


42. F. Tsui, L. He, L. Ma, A. Tkachuk, K. Nakajima, and T. Chikyow, Phys. Rev. Lett., 91, 177203 (2003). 43. X. Han, M. Oogane, H. Kubota, Y. Ando, and T. Miyazaka, Appl. Phys. Lett., 77, 283 (2004). 44. D. Wang, C. Nordman, J.M. Daughton, Z. Qian, and J. Fink, IEEE Trans. Magn., 40, 2269 (2004). 45. A. Kawaharazuka, M. Ramsteiner, J. Herfort, H.-P. Schonherr, H. Kostial, and K.H. Ploog, Appl. Phys. Lett., 85, 3492 (2004). 46. F.J. Albert, J.A. Katine, R.A. Buhrman, and D.C. Ralph, Appl. Phys. Lett., 77, 3809 (2000); D. Chiba, Y. Sato, T. Kita, F. Matsukura, and H. Ohno, Phys. Rev. Lett., 93, 216602 (2004). 47. D. Chiba, M. Yamanouchi, F. Matsukura, and H. Ohno, Science, 301, 943 (2003). 48. T. Lepselter and S.M. Sze, Proc. IEEE, 56, 1400 (1968). 49. R. Tsu and L. Esaki, Appl. Phys. Lett., 22, 562 (1973). 50. S.A. Wolf, A.Y. Chtchelkanova, and D.M. Treger, IBM J. Res. Dev., 50, 101–116 (2006). 51. C. Reig, D. Ramirez, H.H. Li, and P.P. Freitas, IEE Proc.-Circuits Dev. Syst., 152, 307 (2005). 52. S. Bandyopadhyay and M. Cahay, Phys. E, 27, 98 (2005). 53. J. Wang, H. Meng, and J.P. Wang, J. Appl. Phys., 97, 100509 (2005). 54. P.P. Freitas, L. Costa, N. Almeida, L.V. Melo, F. Silva, J. Bernardo, and C. Santos, J. Appl. Phys., 85, 5459 (1999). 55. W.J. Ku, P.P. Freitas, P. Compadrinho, and J. Barata, IEEE Trans. Magn., 36, 2782 (2000). 56. J. Pelegri, J.B. Egea, D. Ramirez, and P.P. Freitas, Sensors Actuators A, 105, 132 (2003). 57. L. Lagae, R. Wirix-Speetjens, C.-X. Liu, W. Laureyn, G. Borghs, S. Harvey, P. Galvin, H.A. Ferreira, D.L. Graham, P.P. Freitas, L.A. Clarke, and M.D. Amaral, IEE Proc.-Circuits Dev. Syst., 152, 393 (2005). 58. S. Sanvito, Nature Materials, 6, 803 (2007).

7 Electron Transport in Nanocrystalline Silicon H. Mizuta*, S. Uno, N. Mori, S. Oda, and N. Koshida 1. INTRODUCTION TO ELECTRON TRANSPORT IN NANOCRYSTALLINE SILICON

In recent years, electron transport properties of nanocrystalline Si (nc-Si) have attracted increasing interests along with the remarkable progress of nc-Si material control technologies. The nanometer-scale size of individual Si nanocrystals leads to various electronic and photonic properties associated with quantum confinement, single-electron tunneling, and charge quantization. These unique properties have been exploited for fabricating experimental single-electron transistors and memories [1, 2], ballistic electron emitters [3], and silicon light emitting devices [4]. Strong tunnel coupling between double nc-Si dots via ultra thin interface layers may also be utilized to realize a charge quantum bit (qubit), based on the molecular states formed in the structure [5]. It has also been pointed out very recently that the phonon states and electron–phonon interactions in the nc-Si differ very much from those for bulk Si because of a high contrast in acoustic properties between the nc-Si dots and the interface oxides. The nc-Si may enable the realization of artificial acoustic superstructures and the engineering of electron–phonon interaction. To date, only limited studies have been done on the microscopic electron transport in the nc-Si. Nevertheless, this chapter intends to review recent experimental and theoretical studies on novel transport properties of the nc-Si. Most of nc-Si materials available so far for are still fairly disorder system consisting of a random network of crystalline Si nanodots and their boundaries that are usually formed by amourphous silicon, silicon suboxide SiOx, or SiO2. Figure 1a, b show the scanning electron micrograph (SEM) images of two types of nc-Si materials fabricated by using different techniques. The nc-Si film (Fig. 1a) can be formed either from an amorphous Si film with solid phase crystallization [6] or by using a very high frequency (VHF) plasmaenhanced CVD (PECVD) at a low temperature [7]. In the nc-Si films, the mean size School of Electronics and Computer Science, University of Southampton, Southampton, UK, [email protected]


197

MIZUTA ET AL.

198

of the Si nanodots can be controlled via the film thickness and crystallization temperature, although the size and shape of individual dots are varying. Figure 1b shows the assembled nc-Si dots formed by using a VHF plasma enhanced decomposition of silane with a hydrogen gas pulse sequence (Fig. 2) [8]. This technique facilitates in separating the nucleation and crystal growth process and forms individual nc-Si dots (Fig. 1c) of less than 10 nm in diameter with dispersion of only ± 1 nm [9]. The inter-dot tunnel barriers can be formed by in situ oxidation or nitridation in a controlled manner. Integration of the fabricated nc-Si dots is a challenging issue, and various attempts are currently conducted. In particular, the self-assembly method based on the dispersion solution of nc-Si dots has been studied intensively. Assembly of the nc-Si dots was conducted by Tanaka et al. [10] on the hydrophilic SiO2 surface via the lateral capillary meniscus force between the adjacent dots, and densely packed structures (Fig. 1b) were formed with areal dot density as high as approximately 1012

FIG. 1. (a) A scanning electron micrograph (SEM) image of a 50-nm-thick nc-Si film fabricated by using low-pressure chemical vapor deposition (LPCVD). The film contains the nc-Si dots with size ranging from 30 nm down to 5 nm. (b) A SEM image of the assembled nc-Si dots and (c) a HR-TEM image of a single nc-Si dot fabricated by the very high frequency (VHF) plasma CVD. Substrate To TMP

UHV Chamber

Orifice ( φ ∼ 5 mm )

b.p. ~10−9 Torr r.p. ~ 1 m Torr

SiH4 gas

H2 or Ar gas

PC control

VHF (144MHz) Plasma Cell (r.p. ~ 1 Torr)

FIG. 2. (a) A SEM image of a 50-nm-thick nc-Si film fabricated by using LPCVD. The film contains the nc-Si dots with size ranging from 30 nm down to 5 nm. (b) A SEM image of the assembled nc-Si dots and (c) a HR-TEM image of a single nc-Si dot fabricated by the VHF plasma CVD.

7. ELECTRON TRANSPORT IN NANOCRYSTALLINE SILICON

199

dots cm−2. Local-area assembly has also been demonstrated on the silicon-on-insulator (SOI) substrates with prepatterned nanoelectrodes. Nanometer-scale transistors have successfully been fabricated with the nc-Si cluster channel formed in a gap of as small as 20 nm (Fig. 3) [11]. Such nc-Si dot integration techniques are expected to develop rapidly combined with top-down nanofabrication techniques and to provide a new powerful method of fabricating nanoscale Si devices in the near future. In general, electron transport in the nc-Si is complex mixture of macroscopic percolation transport [12] and nanoscopic transport such as resonant tunneling (RT) [13] and Coulomb blockade (CB) [14]. If the nc-Si consists of the Si nanodots and boundaries with various dimensions (Fig. 4a), the electrons in the percolation process may take the conduction pathways with the lowest tunnel resistance. Extremely small Si nanodots contained in the material also influence on determining the conduction pathways as they give rise to energy quantization and CB of the electrons, resulting

FIG. 3. A nanoscale transistor with a channel composed of the Si nanodots assembled in the nanogap between the n+-Si source and drain electrodes.

a

b

S

c

S

D

d

D

e S

D

S

D

FIG. 4. Various nc-Si structures as a conduction channel for electron devices: (a) macroscopic disorder networks of nc-Si dots and boundaries with varying dimensions and (b) those with uniform dimensions, and (c) two-dimensional and (d) one-dimensional Si nanodot array with uniform dimensions, and (e) a nanoscopic structure with double nc-Si dots.

200

MIZUTA ET AL.

in creation of high resistance locally on the network. The transport properties of macroscale nc-Si are expected not to show the quantization effects of charge (CB) and energy (RT) as the materials contain uncountable pathways and the electrons bypass such high resistance regions. Large-area devices formed by using the nc-Si shown in Fig. 1a are a typical example. In the macroscale nc-Si composed of the Si nanodots, which are distributed randomly but have uniform dimensions (Fig. 4b), the electrons are expected to take the shortest pathways as the single-electron charging energy and tunnel resistance are virtually the same for all the dots and boundaries. This is the case for the macroscopic nc-Si materials shown in Fig. 1b. The nanoscopic transport mechanisms play a main role in the nc-Si structures, which contain only a limited number of Si nanodots and boundaries (Fig. 4e). This is also the case for the one-dimensional Si nanodot array (Fig. 4d) as only one conduction path is available and electrons cannot avoid the region where CB and/ or RT are dominant. Although it is still technically challenging to fabricate the macroscale nc-Si materials with a long-range periodic structure (Figs. 4c, d), theoretical investigations have been opened to predict their electronic properties. Electron transport may be described by using the minibands in the same manner as that in the GaAs/AlGaAs superlattice. Another phenomenon expected to occur in such periodic nc-Si structures is formation of phononic bands. It is theoretically predicted that phonons show intriguing properties such as spatial confinement and depletion, leading to the phononic bandgaps, as the result of a large acoustic impedance gap between Si and oxide. Investigations of electron transport in the nc-Si are still at the early stage, and no systematic study has been done. In the following sections, we intend to present the recent progress of the experimental and theoretical studies on microscopic transport mechanisms for the nc-Si by taking account of their novel device applications. We do not discuss the macroscopic percolation transport due to the limitation of space available for this chapter. In Sect. 2, we focus on the nanoscale transport phononema: CB, RT and coherent electron coupling. Section 3 is devoted to discussion on the electron–phonon interactions and the associated electron transport in the periodic nc-Si structures.

2. ELECTRON TRANSPORT IN NANOSCALE NC-SI STRUCTURES

2.1. Coulomb Blockade CB in the nc-Si has been investigated by Dutta et al. by using the nanoscopic devices shown in Fig. 5a [15]. In-plane source and drain electrodes with a nanogap of only 15 nm were fabricated on a heavily-doped (5 × 1019 cm−3) SOI of 25 nm in thickness by using electron beam direct writing. nc-Si dots 8 nm in diameter were then deposited sparsely on the nanoelectrode pattern. Density of Si nanodots was approximately 1011 cm−2, which corresponds to surface coverage of 5%. Dry oxidation was carried out at 800°C for 10 min to form a thin oxide tunnel barrier on the Si nanodot surface. A 40-nm-thick gate oxide film was then deposited over the Si


201

FIG. 5. (a) A schematic Si nanodot transistor structure formed on the silicon-on-insulator (SOI) substrate with a nanoscale souce-drain separation. Silicon nanodots are deposited sparsely on the nanoelectrodes. (b) A tunneling current contour plot in the source–drain voltage and gate voltage plane.

nanodots using VHF plasma-enhanced CVD. Aluminum source and drain Ohmic contact pads and gate electrode were finally fabricated using a lift-off process. Electrical conductance has successfully been measured for the devices with a one-dimensional array of Si nanodots formed between the source and drain electrodes. As the Si nanodot diameter is about 8 nm, either two or three nanodots are likely to form the bridge. The source–drain current–voltage characteristics showed the Coulomb gap as large as 1.4 V at 20 K. When the gate bias is varied with the source–drain voltage fixed, the Coulomb oscillations have clearly been observed. Figure 5b shows the source–drain current contour plot measured at 20 K as a function of the source–drain voltage and gate voltage. The Coulomb diamond pattern is clearly seen with almost the same oscillation period. This indicates that a single Si nanodot works as a charging island. Among three Si nanodots involved, the central nanodot with two tunnel junctions is supposed to play a role since the other two nanodots connected to the electrodes have a larger junction capacitance and hence their single-electron charging energies are expected to be smaller than that for the central nanodot. This scenario is consistent with the fact that the individual oscillation peaks break into multiple subpeaks at lower temperatures. It was found that the Coulomb oscillations persist up to above 77 K, and the remaining oscillations were observed for the transconductance (dIds/dVg) even at room temperature. Nishiguchi et al. has attempted to study the single-electron tunneling via solely a single Si nanodot by adopted a vertical transistor structure (Fig. 6a). The vertical structure was fabricated on a SiO2(30 nm)/poly-Si(25 nm)/SiO2(20 nm)/Si(100) substrate where the middle poly-Si layer was phosphorous doped by 1018 cm−3 and acts as a surrounding-gate electrode. A lateral two-dimensional array of nanoscale pores of approximately 30 nm in diameter were patterned by using electron-beam lithography. By combining anisotropic and isotropic dray etchings, pores penetrating to the bottom Si substrate were formed. The shape of the pores was carefully designed to taper down toward the substrate, and the lateral dimension of the pore at the bottom is only about 10 nm. Silicon nanodots of about 10 nm in diameter were then deposited on the pore array. Some of the pores are expected to

202

MIZUTA ET AL.

FIG. 6. (a) A cross-sectional view of a vertical Si nanodot transistor and (b) Coulomb oscillation observed at temperature of 5 K as a function of the surrounding-gate voltage.

accommodate a single Si nanodot, which sits stably at the bottom of the pore. The pores were finally filled with the doped poly-Si, which was formed from the CVD deposited a-Si using solid-phase crystallization. Gold films were deposited both on the top poly-Si and the bottom Si substrate after an isolation process for the devices for obtaining the ohmic contacts. Figure 6b shows the Coulomb oscillation observed for the fabricated vertical device at 5 K. The oscillation period was found virtually the same, and this proves that a single Si nanodot is responsible for the CB. The Coulomb oscillation has been observed at temperature up to 77 K. It is apparent that the size of Si nanodots should be decreased further for achieving room temperature operation of the single-electron transistors. For this purpose, CB was studied intensively also for the nc-Si films (Fig. 1a). Tan et al. [16] has adopted a thin nc-Si film prepared by a low-temperature PECVD, which contains Si nanodots with the size down to 4 nm. The quantum point-contact transistor (QPC-Tr; see the inset to Fig. 7a) was fabricated on the nc-Si film. The QPC-Ts features a channel with both the length and width as short as 20 nm. The QPC-Trs with double side gates were patterned by high-resolution electron beam lithography and electrically isolated by reactive ion etching. The electric characteristics for the QPC-Trs, therefore, reflect the properties of only few Si nanodots and boundaries contained in the extremely small QPC channel area. After defining the QPC-Trs, a multiple step oxidation process was applied, which was proposed to oxidize the boundaries between the Si nanodots selectively and to convert them to SiOx (x < 2) without increasing the Si nanodot size [17, 18]. This is low-temperature oxidation (650–750°C) followed by high-temperature (1,000°C) annealing. A clear CB oscillation was observed for the fabricated QPC-Trs as shown in Fig. 7a when the common bias was applied to the double side gates [19, 20]. The Coulomb oscillation persists up to room temperature, although the P/V current ratio gradually decreases as the temperature is raised. A well-defined oscillation period indicates that a single Si nanodot in the QPC channel is responsible for the Coulomb oscillation. The P/V current ratio of the CB oscillation observed at room temperature is still too small for considering any immediate device applications. Apparently further


203

FIG. 7. Ids − Vgs characteristics observed for the Si nanodot quantum point-contact transistor (QPC-Tr). The temperature increases from 50 to 300 K in 25 K steps. (Inset) An SEM image of the fabricated QPC-Tr. (b) Si nanodot diameter dependence of the charging energy EC. Two broken lines show the energy of 10 kBT at the temperature of 77 K and 300 K.

reduction of the Si nanodot size is needed for achieving “real” room temperature operation. Figure 7b shows the single-electron charging energy EC calculated for a single spherical Si nanodot embedded in oxide by taking account of both the selfcapacitance and tunnel capacitance [21]. As a rough guideline for the operation temperature, two horizontal broken lines show the energy of 10kBT with T = 300 K and T = 77 K. The results indicate that ddot ⲏ 2 nm is needed to meet EC ⲏ10kBT at room temperature and to secure the SET operation at room temperature. It is, however, worth exploring the Si nanodot-based devices by combining the available CB effects with other switching mechanisms, i.e., the external electrostatic potential, tailored energy potential barriers [22], and energy quantization. It should finally be noted that Si nanodots with diameter as small as 1 nm have been reported very recently. Tilley et al. [23] succeeded to form 1.6-nm crystalline Si nanodots in inverse micelles by the solution reduction of SiCl4 with strong hydride reducing agent. Mitas et al. [24] reported a novel hydrogen terminated Si nanodot, Si29H24, which is electrochemically dispersed from crystalline Si in a mixture of HF/ H2O2 and the diameter is as small as 1.0 nm. These extremely small Si nanodots may be used as a building block for achieving “real” room-temperature CB operation. 2.2. Resonant Tunneling In contrast to the numerous reports on CB, RT [25] has been studied much less for nanocrystallie Si. This is presumably because the quantization energy is relatively smaller in the Si-based nanostructures due to a larger electron effective mass compared with that in GaAs-based nanostructures. In addition, the atomic layer growth techniques, represented by molecular beam epitaxy (MBE) technique, have been developed for GaAs-based compound semiconductors, and have enabled to fabricate well-controlled multiple-barrier structures suitable for exploring RT. However, the recent advance of Si-based bottom-up techniques is certainly boosting the interest in RT in Si structures. A very thin SOI has been first used for studying RT in Si,

204

MIZUTA ET AL.

and negative differential conductance (NDC) was observed at low temperature [26]. RT through a two-dimensionally confined structure has also been reported by using a disk-shaped silicon nanodot by using a contact-mode atomic force microscopy (AFM), and the NDC has been observed at room temperature [27]. Silicon-based RT devices have a great advantage of being compatible with present VLSI technologies and, therefore, would have a significant impact on the complementary metal oxide semiconductor (CMOS) technology. Combined with the CMOS, Si-based RT devices may lead to various functional devices such as low power tunneling static random access memory (TSRAM) [28, 29], and multivalued logic circuit [30]. Quantum dot based IC technology is predicted to become the most basic component of ultra-scaled semiconductor device [31]. Nanocrystalline based RT diode can be used for local refresh in dynamic random access memory (DRAM) with extremely low power dissipation [32]. Very recently Surawijaya et al. [33] has studied RT via a spherical single Si nanodot by using the contact-mode AFM. nc-Si dots were deposited by using the VHF plasma CVD on a uniform 1.5-nm-thick SiO2 formed on the n-type (100) Si substrate. The Si nanodots were then exposed to ambient air for several hours at room temperature to oxidize the nc-Si dots naturally, forming the natural oxide of around 1–2 nm in thickness. A single Si nanodot isolated well from the others was chosen beforehand with the topographical scanning over the area of 1 × 1 μm2 on the sample. Afterwards the tunneling current was measured by contacting the Au coated AFM tip to the chosen Si nanodot (Fig. 8a). Figure 8b shows typical current–voltage characteristics obtained at room temperature when the voltage was applied between the AFM tip and substrate. The peak-tovalley (P/V) current ratio is approximately 17 for the first current peak. Large P/V ratios observed at room temperature certainly encourage the future applications of Si nanodot RT devices. However, the peak voltages and peak currents observed in this measurement differed depending on the Si nanodot chosen for measurement. In addition, the peak voltages were found much larger than those expected from the resonant energies

FIG. 8. (a) A schematic configuration of the contact-mode atomic force microscopy (AFM) measurement for a single Si nanodot. (b) Typical current–voltage characteristics observed at room temperature.


205

FIG. 9. (a) A three-dimensional model structure of a single Si nanodot embedded in SiO2 matrix and sandwiched between source and drain n + -Si contact regions.(b) Four lowest resonant energies calculated for the structure shown in (a) as a function of the Si nanodot diameter.

calculated by using a three-dimensional scattering matrix (S-Matrix) theory [34] for the RT diode structure with a spherical single Si nanodot (Fig. 9a, b). A gap between the experiment and theory is attributable to the large tip-to-dot contact resistance, which is difficult to control under the current measurement circumstances as well as the built-in potential between Au and Si. Fabrication of the single Si nanodot RT diode and characterization of temperature dependence of RT current are indispensable for clarifying the phenomenon fully. 2.3. Electron Interaction in Strongly Coupled Double Nc-Si Dots It is widely known that quantum bits (qubits) – two-level quantum systems – are the elementary units for realizing quantum information processing circuits. There are a number of potential candidates as a physical implementation of a qubit, either a native or artificial entity, for example, charge states or spin states in semiconductor quantum dots, superconducting charge states or flux states, nuclear spins, photons, excitons, and so forth. Among them, the electron charge states in double Si quantum dots are particularly interested for various reasons such as inherent scalability, existence of a variety of initialization and readout methods, and compatibility with conventional VLSI technologies. On the one hand, when the double Si nanodots are coupled strongly through a thin tunnel barrier, the molecular states are expected to be formed in the same manner as a hydrogen molecule. On the other hand, it was also anticipated that inevitable interaction processes with phonons and photons may corrupt the evolution of the coherent states of the charge qubits and make the decoherence time very short. However, Gorman et al. have successfully demonstrated the Rabi oscillation with the decoherence time longer than 200 ns by using double Si nanodots of about 100 nm in diameter fabricated by using the electron beam lithog-


207

sweeping revealed existence of four conductance peaks: two main peaks with two small peaks (Fig. 12c). a

Vg1

b

Gate1

Vg2 (V)

Drain

Cf

-0.7

(-2,- 3)

-0.8 (-4,-4) -1.0 -1.0

Vg2

(-1,-2)

(-3,-3)

-0.6

-0.9

dot2 Gate2

(-2,-2)

-0.5

dot1 Source

-0.4

TP1

TP2

(-1,-3)

(-3,-4) (-2,-4) -0.8

-0.6 -0.4 Vg1 (V)

-0.2

0.0

FIG. 11. (a) An equivalent circuit for the QPC-Tr with two capacitively-coupled parallel Si nanodots. (b) Tunnel current calculated as a function of two side gate bias superposed on the charge stability diagram for the double dot system. Thick grey lines show peak tunnel currents. Indices in parentheses show excess charge on the double dots; minus sign means excess electrons. Two solid dots indicate charge triple points.

2 Vg2 (V)

b

Conductance (nS)

a 1 0

−1 −2

0 −1 −2

0.3

c

Conductance (10−6 e2/h)

−3 −4 −3 −2 −1 0 1 2 Vg1 (V)

6.0

3

4

Vg2 (V) 1

−3 −4 −3 −2 −1 0 Vg1 (V)

0.0

1

Bonding Anti-bonding

5.0

Anti-bonding

4.0

ΔEsplit

3.0

Bonding

2.0 1.0

Vg2=−0.65 V

0 −2.0 −1.5 −1.0 Vg1 (V)

−0.5

FIG. 12. Experimental line plot (a) and (b) grey scale plot (b) of the conductance, dIds/dVds vs. the gate voltages, Vg1 and Vg2, at source–drain bias Vds = −2 mV and at T = 4.2 K. (c) Fine plot of drain-source conductance as a function of Vg1 at Vg2 = −0.65 V, Vds = −2 mV, and T = 4.2 K measured near two charge triple points indicated by a broken circle in (b). The observed curve is decomposed into two main peaks and two sub peaks.

MIZUTA ET AL.

Logic operations/qubit [times]

208

108 107

ΔEsplit

106 105 104 103 102 101 100 0.1

100ns 10ns 1ns 0.1ns

Decoherence Time T2[s] 1

10 Esplit[meV]

100

1000

FIG. 13. Maximum logic operation per qubit as a function of two-level splitting calculated for various values of decoherence time T2.

Identified four conductance peaks are associated with electron tunneling through the delocalised coherent states near the two triple points. Formation of these levels may be attributed to the coherent coupling across the 1-nm-thick grain boundary tunnel barrier between two Si nanodots with sizes smaller than or equal to the electron mean inelastic scattering path of approximately 10 nm at 300 K [38], and may be longer at 4.2 K. Tunnel splitting ΔEsplit between the bonding-like and anti-bonding-like levels was evaluated to be about 0.4 meV from the observed conductance peak separation. This is a few times larger than those reported for the GaAs/AlGaAs double dots at temperature less than 50 mK [39]. Larger ΔEsplit between the quantum two-levels gives a higher fundamental qubit frequency and hence leads to an increase in the maximum logic operations per qubit (Fig. 13).

3. PHONONIC STATES AND BALLISTIC ELECTRON TRANSPORT IN PERIODIC NC-SI STRUCTURES

As mentioned in Sect. 1, the integrated Si nanodots provide an intriguing system to study unique electronic and phononic states in periodic Si nanostructures. Experimental realization of the array of Si nanodots with long range periodicity still needs further progress of assembly technologies for Si nanodots along with their surface modification techniques. However, growing attentions have recently been paid to electron transport properties of such Si nanodot arrays associated with the experimental observation of ballistic electron emission from the integrated Si nanodot structures. This section intends to present theoretical investigation of phononic states and electron–phonon interactions in the Si nanodot array structures. To date, phonons and associated electron–phonon interactions have been studied intensively for GaAs-based nanostructures. For example, the effects of polar optical phonon (POP) scatterings on electron transport have been investigated for


209

GaAs/AlGaAs superlattices [40–45]. Acoustic phonons and their interactions with electrons have also been studied for GaAs-based nanostructures [46, 47], and some reports have shown the ways to tailor phonon conductivity and electron–phonon scattering rate [48–50]. These efforts demonstrate what “phonon engineering” can do to functionalize semiconductor nanostructures right to the edge of the envelope. Although such efforts showed significance of phonon modification in GaAs-based nanostructures, there is limited number of studies addressing Si-based systems. This is actually quite surprising considering how widely Si-based nanostructures are used in today’s electronic devices such as processors, sensors, memories, and displays. The present section is devoted to investigate the acoustic phonons and electron–phonon interactions in one-dimensional Si nanodot arrays interconnected with thin oxide layers (1DSiNDA). Theoretical outcomes described in the following can be applied for other Si-based nanostructures such as a very thin SOI structure or a Si nanowire wrapped by SiO2 and would give bases of phonon-engineering in Si nano devices. 3.1. Electronic States in One-Dimensional Si Nanodot Arrays (1DSiNDA) Interconnected with Thin Oxide Layers Figure 14 shows schematic diagram of 1DSiNDA. nc-Si dots are hereafter modeled as cubes with Lx, Ly, and Lz, and they are connected with thin oxide layers of thickness Tox. As we assume perfect periodicity in the x direction, the period of the translational symmetry is given by d = L x + Tox .

Si

(7.1)

Oxide

d = 5nm Tox =1nm Lx

z

Ly Lz

y

0 x

nc-Si Oxide

Lx=Ly=Lz= 4nm

FIG. 14. Schematic diagram of the one-dimensional Si nanodot arrays interconnected with thin SiO2 layers (1DSiNDA). Parameters were set close to those of the nc-Si for electron emission devices [51–53].

MIZUTA ET AL.

210

To make the following calculations and arguments as realistic as possible, the structural parameters are set close to those of the nc-Si used for the electron emission devices [51–53], that is, Tox = 1.0 nm, Lx = Ly = Lz = 4.0 nm. This model can be viewed as a simplification of realistic Si nanodot array fabricated by various techniques. In addition, for simplicity, further assumptions are set as follows: • 1DSiNDA is standing free in vacuum • Single electron charging is neglected • Electric field applied across 1DSiNDA (that is, x direction) is low Silicon has six equivalent energy minima in k space at X points. At room temperature, these minima are filled with conduction electrons, and they contribute to electric conduction. In 1DSiNDA, these six minima are squashed into single energy minimum at k = 0 due to loss of translational symmetry. Low field electron transport in 1DSiNDA can be suitably treated using effective mass approximation in this Γ-like valley. Electron wave functions in the y and z directions are easily obtained by assuming infinite potential barrier outside the Si nanodots, and they are written using sine functions. As we consider low filed transport, the potential in the x direction can be viewed as the Krönig-Penny potential, and the electron wave functions are written in terms of Bloch functions. Therefore, electron wave functions read ⎧ 1 ⎪ x k x be = uk ,b (x )e i kx x L x e ⎪ ⎪ ⎡ ny p ⎤ 2 ⎪ sin ⎢ y⎥ , ⎨ y ny = Ly ⎪ ⎣⎢ L y ⎦⎥ ⎪ ⎪ z n = 2 sin ⎡ nz p z ⎤ ⎢ ⎥ z ⎪ Lz ⎣ Lz ⎦ ⎩

(7.2)

where nx, ny, and nz are positive integers, be is the energy branch index, and L is the total length of 1DSiNDA in the x direction, which eventually vanishes during electron–phonon interaction formulation. Figure 15 shows electron energy in the x direction as a function of wave vector in the x direction, kx. In the calculation, oxide barrier height denoted by the dashed line was set at 1.0 eV based on the fact that such thin oxide layers are often not fully oxidized in real Si nanodot systems. Electrons can take energies only in allowed ranges (minibands), and the forbidden energy ranges (minibandgaps) appear. These are typical characteristics of electronic states in periodic potential. Dispersion curves are flatter than those of free electrons, so that the energy density of states are larger compared with those in Si nanowire. Especially, minibands well below the oxide barrier height are almost dispersionless, and therefore electrons are localized in Si nanodots, as expected.


211

Electron Energy inx [eV]

3

2

1

0 −π/d

0 Electron Wave Vector

π/d

FIG. 15. One-dimensional electron energy dispersion relations in 1DSiNDA. Parameters used are shown in [53].

3.2. Phononic States and Reduction of Acoustic Phonon Scattering Potential due to Phonon Modulation Acoustic phonons in Si nanowires can be approximated as one-dimensional phonon wave along the x direction multiplied by two-dimensional waves in the y and z directions [54]. For free-standing wires, these two-dimensional waves are often taken as plane waves having antinodes at the side walls of the nanowire. Therefore, three-dimensional acoustic waves in 1DSiNDA can be written as

(

)

S (r ) = ∑ Cq aq + a−+q e i Q⋅R Sqx ( x )s q , q

(7.3)

where q is the phonon wave vector, a−q+ and aq are the creation and annihilation operators, Sqx (x) is a one-dimensional phonon wave, sq is the unit vector in the direction of atomic vibrations, and R and Q are coordinate and phonon wave vector in the y–z plane, respectively. The constant Cq is defined as Cq ≡

1 , 2w q N y N z

(7.4)

where ωq is the frequency of the phonon vibration, and NyNz is the total number of atoms on a cross section in y–z plane. The one-dimensional phonon wave function Sqx(x) is obtained using the linear atomic chain model shown in Fig. 16. Nc-Si

MIZUTA ET AL.

212

regions are modeled as a linear chain of Si atoms, and the oxide layers are assumed to contain both silicon and oxygen atoms alternating with each other. The neighboring atoms are interconnected by atomic bonds, and the spring constants for Si–Si and Si–O bonds were determined based on the Young’s modulus of Si and SiO2. The one-dimensional phonon waves are obtained by solving Newton’s equations for all atoms under periodic boundary condition. For simplicity, only interactions between neighboring atoms are considered. Figure 17 shows calculated phonon dispersion relations for (a) Si nanowire (b) oxide nanowire, and (c) 1DSiNDA. The curves in Fig. 17a were obtained by setting all the atoms and spring constants in the linear chain as those of Si. The dispersion curves are basically composed of optical and acoustic branches observed in bulk Si (100) direction, folded into smaller first Brillouin zone. The curves in Fig. 17b were

Oxygen atom

Silicon atom

FIG. 16. Schematic diagram of linear atomic chain model for obtaining one-dimensional acoustic phonon wave function.

a

Silicon 60

b

c

Oxide

1DSiNDA

Phonon Energy [meV]

50 40 30 20 10 0 −π/d

0

π/d −π/d

0

π/d −π/d

0

π/d

Phonon Wave Vector FIG. 17. One-dimensional phonon energy dispersions for (a) Si nanowire, (b) oxide nanowire, (c) 1DSiNDA.


213

|Displacement|2 [a.u.]

Re[Displacement] [a.u.]

obtained by assuming that all the region is composed of oxide, so that the Si and O atoms reside side by side, and the spring constant was calculated from Young’s modulus of SiO2. As the unit cell of this system contains two different kinds of atoms, there is a phonon energy gap between the optical and acoustic branches. The dispersion relations for 1DSiNDA shown in Fig. 17c are easily explained, based on the results in Figs. 17a, b. In Fig. 17a, the phonon dispersion is continuous in energy, while that in Fig. 17b clearly shows the phonon energy gap at 27 meV < E < 37 meV. In 1DSiNDA, phonon vibration can exist both in the Si dots and the oxide layers, only when the phonon energy is within E < 27 meV or 37 meV < E < 45 meV. Such phonon normal modes should be dependent on a parameter of translational symmetry, that is, the phonon wave vector, and therefore the phonon branches in Fig. 17c show certain dispersion. The phonon dispersion is then a “mixture” of those in Figs. 17a, b. The small phonon energy gaps appeared because of the mismatch of the spring constants in the Si dot region and the oxide layers. When phonon energy lies within 27 meV < E < 37 meV or 45 meV < E, such phonon vibration cannot exist in the oxide layers, and therefore it is localized only in the Si dots. Such localized phonons are not affected by the phonon wave vector, and hence the phonon branches are dispersionless. This argument is confirmed by plotting the phonon waves as a function of position. Figure 18a, b show real parts of the phonon wave functions chosen from a branch with and without dispersion. As expected, the phonon wave is delocalized when it belongs to a branch with dispersion, and it is localized for dispersionless branch. Figure 18c, d show the squared phonon amplitude of such phonon waves, demonstrating the localization/delocalization of phonon vibration more clearly. a

1

b

Delocalized Phonon

Localized Phonon

0

-1 c 10

Oxide Si

Oxide Si

d

Delocalized Phonon

Localized Phonon

5

0 0

10

20

30

40

0

10

20

30

40

Position in x [nm] FIG. 18. Simulation results of phonon wave functions obtained from the linear atomic chain model. (a) Real part of phonon displacement for delocalized phonon, (b) that of localized phonon, (c) Squared displacement (amplitude) for delocalized, and (d) localized phonons.

MIZUTA ET AL.

214

The delocalized phonon in Figs. 18a, c was taken from the lowest phonon dispersion branch, so that it is an acoustic phonon. Now, note that the phonon displacement in Fig. 18a indicates that the distance between two neighboring atoms are large in the oxide layers. As a result, strain caused by the acoustic phonon vibration might be larger in the oxide layers than in nc-Si regions. This is confirmed in Fig. 19. Figure 19a shows phonon displacement for an acoustic phonon in 1DSiNDA, and Fig. 19b shows the absolute value of the strain (strain amplitude) caused by this acoustic phonon vibration. Note that the strain is larger in the oxide layers than in the Si dots. The dashed line shows the result obtained from Si quantum wire for comparison. Note that the strain in the Si dots is weaker compared with that in the Si nanowire. This indicates that the strain in the Si dots is “absorbed” by the oxide

Displacement [a.u.]

a

2 Phonon Displacement

1 0 -1 -2

b 20 |Strain| [a.u.]

Strain Amplitude

c

10

0 10 ADP Scattering Hamiltonian

|HADP| [a.u.]

8 6 4 2 0 0

10

20 Position [nm]

30

40

FIG. 19. (a) Phonon displacement as a function of position plotted for an acoustic phonon in 1DSiNDA; (b) Absolute value of strain caused by the acoustic phonon vibration; (c) Acoustic deformation potential (ADP) scattering potential.


215

layers inserted between these dots. This is quite reasonable because oxide layers are softer than Si dots, and therefore they act as buffers of vibration energy. This observation is important because the strain amplitude is related to the amount of electron–phonon interactions. In Si-based devices, major electron–phonon scattering events are mediated by acoustic phonons, and its scattering potential is written in one-dimensional form as H ADP (x ) = Daco

d Sq (x ), dx x

(7.5)

where the derivative of phonon displacement Sqx (x) in terms of position x is the strain caused by the acoustic phonon vibration, and the coefficient Daco is the acoustic deformation potential (ADP) coefficient, which has values of 9.0 eV in Si and 3.5 eV in SiO2. Note that the coefficient Daco is larger in Si than in SiO2, while the strain amplitude shown in Fig. 19b is smaller in Si than in SiO2. This indicates that the scattering potential (7.5) may be reduced all over the device because of the strain redistribution. This actually occurs as shown in Fig. 19c, where the ADP scattering potential for 1DSiNDA (solid curve with open circles) is smaller than that of Si nanowire (dashed line) all along 1DSiNDA. Thus, the phonon wave modulation due to mechanical mismatch between Si and SiO2 causes reduction of ADP scattering potential. More details can be found in [55]. 3.3 Intra- and Inter-Miniband Scattering The electron and phonon wave functions are now substituted into Fermi’s golden rule to calculate electron–phonon interactions. Exploiting the fact that electrons and phonons are strongly confined in one-dimension, three-dimensional formula for transition probability of an electron in a state k at a miniband be to another state k’ at a miniband be’ can be approximated in one-dimensional form as T (k → k ′ )=

2p 1 2w ± qx N y N z

⎪⎧ nqx ⎪⎫ ⎛ 1 ⎞⎛ 1 ⎞ ⎨ ⎬ ⎜ 1 + d ny ny′ ⎟ ⎜ 1 + d nz nz′ ⎟ ⎝ 2 ⎠⎝ 2 ⎠ ⎩n− qx + 1⎭

k x′be′ H el-ph (x ) k x be

2

d ⎡⎣ E (k ′ ) − E (k )∓ w ± qx ⎤⎦ ,

(7.6)

where Hel-ph(x) is the scattering potential, and n is the phonon occupation number [56]. This formula is valid for scattering events mediated by both acoustic and optical phonons. Assuming that the electronic states in the y and z direction does not change during the scattering, the scattering rate for an electron in a state kx at miniband be is written as ⎡ d W (k x , be ) = ∑ ⎢ ⎢ 2p bp ⎣

∑ j

T (k x be → k x′be′ )⎤ ⎥, F ′ k x′ = k j′ ⎥ ⎦

(

)

(7.7)

MIZUTA ET AL.

216

∼ where bp denotes the phonon branch index, and T and F are defined as ⎧ T (k x be → k x′be′ ) ⎪⎪T (k x be → k x′be′ ) ≡ d ⎡⎣ E (k x′ , be′ )− E (k x , be )∓ w ± qx ⎤⎦ ⎨ ⎪ ⎪⎩ F (k x′ , be′ ) ≡ E (k x′ , be′ )− E (k x , be )∓ w ± qx

(7.8)

and the kj′ is the jth root of F(kx′,be′) = 0. Figure 20 shows the scattering rates as a function of initial electron energy in the x direction calculated using (7.7). In this calculation, electrons are assumed to reside at ground state in the y and z directions, and therefore transitions occur only in the x direction. The numbers from 2 to 6 in the figure denote the miniband indices where electrons initially reside. The solid curves show scattering rates for phonon emission processes, and the dashed curves denote phonon absorption processes. Note that there are sharp spikes at near the bottom/top of the minibands. These spikes occur when electron final state is near the top or bottom of the minibands, where the density of state diverges (that is, the function F’(kx′,be′) approaches to zero). Also note that the scattering rates rapidly decrease at near the bottom/top of the minibands for emission/absorption processes. This is because the scattering events mediated by high energy phonon branches do not occur because the electron final state falls into a minibandgap. The dotted dash curve shows the phonon emission rate for Si nanowire, which was obtained by calculating electronic and phononic states by replacing all the oxide layers by Si. The dotted curve shows the phonon absorption rate obtained in the same way. Note that the scattering rates calculated for 1DSiNDA are eventually

1014

Scattering Rate [s−1]

#2 1013

T = 300K

#3

#4

Emission Absorption #5 #6

1012

1011

1010

0

1 2 Initial Electron Energy in the x direction [eV]

FIG. 20. Total scattering rate as a function of initial electron energy in the x direction. All the phonon branches (acoustic and optical) are taken into account. Solid curves: phonon emission processes for 1DSiNDA; dashed curves: phonon absorption processes for 1DSiNDA; dotted dash curve: phonon emission process for Si nanowire; and dotted curve: phonon absorption process for Si nanowire. Calculations were done for T = 300 K.


217

larger than those of Si nanowire, although, in the previous discussion, acoustic deformation potential was shown to decrease in 1DSiNDA! This unpleasing result occurred because the existence of oxide layers alters electronic states as well as phononic states. The electron dispersion relations show miniband structures as shown in Fig. 20, which leads to the increase of density of states and hence scattering rate at any given energy. This increase eventually dominates the reduction of ADP scattering potential. However, in future, we may be able to engineer the device structures, so that the reduction of scattering rate occurs due to that of ADP scattering potential. Finally let us take a quick look at the interminiband scattering in 1DSiNDA. As is always the case for systems having periodic potential, interminiband scattering processes in 1DSiNDA can be suppressed due to the existence of minibandgaps. As the transverse energy can change during the interminiband scattering processes, now we remove the assumption that the electronic states in the y and z directions do not change during scattering processes. Then the electron energy in the x direction is added by that in the y and z direction, and the minibands are redefined in terms of total electron energy. Interminiband scattering is not allowed when the minibandgap lying between the two minibands is larger than the maximum phonon energy, which can be transferred to/from electrons. Figure 21 shows the minibandgaps as a function of minibandgap number, defined in the way that nth minibandgap is the energy gap between nth and n + 1st miniband. The broken line denotes the maximum phonon energy in 1DSiNDA, that is, 62 meV. Three curves were plotted for Si nanodot size of 3.0, 5.0, and 7.0 nm. Note that, for Lx = 4.0 nm, minibandgaps 1, 3, 6, 9, and 12 are above the maximum phonon energy denoted by the broken line. Interminiband scatterings over such minibands are not allowed, and therefore interminiband scatterings are suppressed in this system. The curve plotted 250

1DSiNDA Minibandgaps [meV]

200

Lx=3.0nm Lx=4.0nm Lx=7.0nm

150 100 50 0

0

5

10

15

Minibandgap Number

FIG. 21. Minibandgaps as a function of minibandgap number. Minibandgaps were re-defined in terms of total electron energy, that is, electron energy in the x direction added by that in the y and z directions. The nth minibandgap is defined as energy gap between nth and n + 1st miniband. The broken line denotes the maximum phonon energy in the 1DSiNDA, that is, 62 meV.


EMAX (eV)

# of emitted electrons (a.u.)

100 80 60 40

22 20 18 16 14 12 10 10 12 14 16 18 20 22 eVdiode –WAu (eV) EMAX

20 0

219

0

5

10 15 Electron energy (eV)

20

25

FIG. 23. Distribution of electrons emitted from Si nanodot BSD as a function of electron energy. (Inset) Maximum electron energy virtually equals to the applied voltage minus the Au work function.

and that the peak becomes much narrower at low temperatures with a peak shift toward higher energy. The most striking feature is that the following relationship holds among EMAX (the maximum energy of the distribution shown with an arrow in Fig. 23), Vdiode and WAu (see the inset to Fig. 23): EMAX ≅ eVdiode − WAu

(7.9)

These facts indicate that electrons in the high energy region of the distribution travel through the Si nanodot layer in a quasi-ballistic manner and are then launched into vacuum with a high initial energy. Thanks to this unique property the BSDs have various technical advantages compared with other field emission display devices. For example, the BSDs need neither high vacuum nor an electron focusing lens because of highly directional emission of ballistic electrons. The experimental BSDs have already been developed, based on porous Si [51–53] as a promising candidate for the future flat panel display technology. From the stand-point of transport physics, there still remain lots to do for clarifying the mechanism behind the ballistic electron transport in Si nanodot array. Modification of electron–phonon scattering shown for 1DSiNDA in the previous sections may contribute to such ballistic electron transport. However, for quantitative description of the anomalously low energy loss in the Si nanodot array, further analysis must be done in future by extending the theory in the previous sections to high electric field conditions. Acknowledgments The authors are very grateful to Dr. Y. Tsuchiya, Dr. K. Usami, Dr. M. Khalafalla, Dr. S. Huang, Dr. K. Nishiguchi (now of NTT Basic Res. Lab.), Dr. A. Dutta, Mr. T. Nakatsukasa (now of Toppan Printing Co. Ltd.), Mr. A. Surawijaya, Dr. Y. Kawata, Dr. A. Tanaka, Mr. N. Momo, Mr. T. Nagami, Mr. S. Higashijima, Mr. G. Yamahata, Mr. J. Ogi of Tokyo Institute of Technology, and Dr. Z.A.K. Durrani, Mr. A. Rafiq and Dr. J. Gorman of University of Cambridge for their valuable technical contributions. The authors also gratefully acknowledge Dr. D.A. Williams of Hitachi Cambridge Laboratory, Dr. S. Saito, Dr. T. Arai of Hitachi Central Research Laboratory, Dr. T. Shimada of Quantum 14 Co. Ltd., Prof. K. Nakazato of Nagoya University for very useful discussions.

220

MIZUTA ET AL.

REFERENCES 1. K. Yano, T. Ishii, T. Hashimoto, T. Kobauashi, F. Murai, and K. Seki, Appl. Phys. Lett. 67, 828 (1995) 2. Y. T. Tan, T. Kamiya, Z. A. K. Durrani, and H. Ahmed, J. Appl. Phys. 94, 633 (2003) 3. K. Nishiguchi, X. Zhao, and S. Oda, J. Appl. Phys. 92, 2748 (2002) 4. Y. Kanemitsu, S. Okamoto, M. Otobe, and S. Oda, Phys. Rev. B 55, R7375 (1997) 5. M. Khalafallah, H. Mizuta, and Z.A.K. Durrani, Appl. Phys. Lett. 85, 2262 (2004) 6. Y. Furuta, H. Mizuta, K. Nakazato, Y. T. Tan, T. Kamiya, Z. A. K. Durrani, H. Ahmed, and K. Taniguchi, Jpn. J. Appl. Phys, 40, L615 (2001) 7. T. Kamiya, K. Nakahata, Y. T. Tan, Z.A.K Durrani, and I. Shimizu, J. Appl. Phys. 89, 6265 (2001) 8. S. Oda and M. Otabe, Mater. Res. Soc. Proc. 358, 721 (1995) 9. T. Ifuku, M. Otabe, A. Itoh, and S. Oda, Jpn. J. Appl. Phys. 36, 4031 (1997) 10. A. Tanaka, G. Yamahata, Y. Tsuchiya, K. Usami, H. Mizuta, and S. Oda, Current Applied Physics 6, 344 (2006) 11. A. Tanaka, G.Yamahata, Y.Tsuchiya, K.Usami, H.Mizuta, and S.Oda, Proc. 5th IEEE Conference on Nanotechnology, Nagoya, July (2005) 12. B. I. Shlovskii and A. L. Efros, Electronic Properties of Doped Semiconductors, Springer, Berlin (1984) 13. H. Mizuta and T. Tanoue, The Physics and Applications of Resonant Tunneling Diodes, Carnbridge University Press, Cambridge (1995) 14. H. Grabert and M. H. Devoret, Eds., Single Charge Tunneling – Coulomb Blockade Phenomena in Nanostructures, NATO ASI Series B, Plenum; New York (1991) 15. A. Dutta, S. Oda, Y. Fu, and M. Willandar, Jpn. J. Appl. Phys. 39, 4647 (2000) 16. Y. T. Tan, T. Kamiya, Z. A. K. Durrani, and H. Ahmed, J. Appl. Phys. 94, 633 (2003) 17. T. Kamiya, Z.A.K. Durrani, and H. Ahmed, Appl. Phys. Lett. 81, 2388 (2002) 18. T. Kamiya, Y.-T. Tan, Z.A.K. Durrani, and H. Ahmed: J. Non-Cryst. Solids 299–302, 405 (2002) 19. Z.A.K. Durrani, T. Kamiya, Y.T. Tan, H. Ahmed and N. Lloyd, Microelectronic Engineering 63, 267 (2002) 20. H. Mizuta, Y. Furuta, T. Kamiya, Y. T. Tan, Z. A. K. Durrani, K. Nakazato, and H. Ahmed, Polycrystalline Semiconductors VII – Bulk Materials, Thin Films, and Devices, T. Sameshima, T. Fuyuki, H.P. Strunk, J.H. Werner eds., in Series ‘Solid State Phenomena’, Scitech Publ., Uettikon am See, Switzerland, 419 (2003) 21. K.K. Likharev, Proc. IEEE 87, 606 (1999) 22. K.K. Likharev, Appl. Phys. Lett. 73, 2137 (1998) 23. R D. Tilley, J.H. Warner, K. Yamamoto, I. Matsuib, and H. Fujimori, Chem. Commun., 1833 (2005) 24. L. Mitas, J. Therrien, R. Twesten, G. Belomoin, and M. H. Nayfeh, Appl. Phys. Lett. 78, 1918 (2001) 25. R.T Su and L. Esaki, Appl. Phys. Lett. 22, 562 (1973) 26. Y. Ishikawa, T. Ishihara, M. Iwasaki, and M. Tabe, Electron. Lett. 37, 1456 (2003) 27. M. Fukuda, K.Nakagawa, S. Miyazaki, and M. Hirose, Appl. Phys. Lett. 70, 2291 (1997) 28. J. P. A. van der Wagt, Nanotechnology 10, 174 (1999) 29. J. P. A. van der Wagt, A. C. Seabaugh, and E. A. Beam, III, IEEE Electron. Device Lett. 19, 7 (1998) 30. A. C. Seabaugh, Y. C. Kao, J. Randall, W. Frensley, and A. Khatibzadeh, Jpn. J. Appl. Phys. 30, 3413 (1991) 31. J. Randall, G. Frazier, A. Seabaugh, and T. Boerkaert, Microelectron. Eng. 32, 15 (1996) 32. J. Berg, S. Bengtsson, and P. Lundgren, Solid-State Electron. 44, 2247 (2000) 33. A. Surawijaya, H. Mizuta, and S. Oda, Jpn. J. Appl. Phys. 45, 3638 (2006) 34. H. Mizuta, C. J. Goodings, M. Wagner, and S. Ho, J. Phys.: Condens. Matter 4, 8783, (1992) 35. J. Gorman, D. Hasko, and D. Williams, Phys. Rev. Lett. 95, 090502 (2005) 36. W. G. van der Wiel, S. De Franceschi, J. M. Elzerman, L. P. Kouwenhoven, T. Fujisawa, and S. Tarucha, Rev. Mod. Phys. 75, 1 (2003) 37. M. Khalafalla, H. Mizuta, and Z. A. K. Durrani, IEEE Trans. Nanotechnol. 2, 271 (2003) 38. M. V. Fischetti and S. E. Laux, Phys. Rev. B, 38, 9721 (1988)

7. ELECTRON TRANSPORT IN NANOCRYSTALLINE SILICON 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58.

221

R. H. Blick, D. Pfannkuche, R. J. Haug, K.v. Klitzing, and K. Eberl, Phys. Rev. Lett. 80, 4032 (1998) I. Lee, S. M. Goodnick, M. Gulia, E. Molinari, and P. Lugli, Phys. Rev. B51, 7046 (1995) R. Lassnig, Phys. Rev. B30, 7132 (1984) N. Sawaki, Surf. Sci. 170, 537 (1986) N. Mori and T. Ando, Phys. Rev. B40, 6175 (1989) K. Hirakawa, Phys. Rev. B40, 3451 (1989) N. Mori and C. Hamaguchi, Semicond.Sci. Technol. 8, 197 (1993) N. Bannov, V. Mitin, and M. Stroscio, Physica Stat. Solidi B, 183, 131 (1994) N. Bannov, V. Aristov, V. Mitin, and M. Stroscio, Phys. Rev, B51, 9930 (1995) E. P. Pokatilov, D. L. Nika, and A. Balandin, Appl. Phys. Lett. 85, 825 (2004) E. P. Pokatilov, D. L. Nika, and A. Balandin, J. Appl. Phys. 95, 5626 (2004) E. P. Pokatilov, D. L. Nika, and A. Balandin, Superlatt. Microstruct. 33, 155 (2003) N. Koshida, T. Ozaki, X. Sheng, and H. Koyama, Jpn. J. Appl. Phys.34,. L705 (1995) N. Koshida, X. Sheng, and T. Komoda, Appl. Surf. Sci. 146, 371 (1999) T. Komoda, X. Sheng, and N. Koshida, J. Vac. Sci. Technol. B 17, 1076 (1999) R. W. Morse, J. Acoust. Soc. Am., 22, 219 (1950) S. Uno, N. Mori, K. Nakazato, N. Koshida, and H. Mizuta, J. Appl. Phys 97, 113506 (2005) S. Uno, N. Mori, K. Nakazato, N. Koshida, and H. Mizuta, Phys. Rev. B72, 035337 (2005) S. Huang, K. Arai, K. Usami and S. Oda, IEEE Trans Nanotechnol. 3, 210 (2004) Y. Tsuchiya, K. Takai, N. Momo, T. Nagami, S. Yamaguchi, T. Shimada, H. Mizuta, and S. Oda, J. Appl. Phys. 100, 094306 (2006) 59. S. Uno, K. Nakazato, S. Yamaguchi, A. Kojima, N. Koshida, and H. Mizuta, IEEE Trans. Nanotechnol. 2, 301 (2003)

8 Silicon Nanocrystal Nonvolatile Memories R. Muralidhar1, M.A. Sadd1, and B.E. White Jr2. 1. INTRODUCTION

In 1959, physicist Richard Feynman delivered his “There’s Plenty of Room Left at the Bottom” lecture [1] to the American Physical Society that spawned the field of nanotechnology. In that lecture, Feynman discussed two themes that are critical to the work presented here. The first was the recognition of the tremendous opportunities associated with the ability to miniaturize computers. At the time of his lecture, the most powerful computers consumed entire rooms, and Feynman realized the tremendous gains that could be realized in performance if the technology could be reduced to the size of one’s thumbnail. The second important area Feynman touched on was the unique opportunities that surround the manipulation of matter at the atomic level to create materials with unique and, hopefully, useful properties. Both of these ideas have now been realized as evidenced by the exponential growth of the semiconductor industry over the last 40 years and the tremendous explosion in nanotechnology research, development, and product introduction over the last decade. In this chapter, we discuss how these two themes are impacting the ability to scale memory technology in the semiconductor industry with a particular emphasis on nonvolatile memory. In particular, we will discuss how the self assembly of silicon nanocrystals on an oxide surface can be used to create an artificial charge trapping layer. This layer, when placed between the gate and channel of a metal oxide semiconductor field effect transistor (MOSFET) provides a means for storing charge that can dramatically change the current flowing from the source to drain of a MOSFET, thus creating a memory bit. The properties of this technology are such that a substantial reduction in the operating voltage of conventional nonvolatile memory can be obtained and this, in turn, enables continued scaling of the technology to higher memory densities.

1

Freescale Semiconductor, US

2

Binghamton University, [email protected]


223

224

MURALIDHAR ET AL.

2. TRADITIONAL NONVOLATILE MEMORY SCALING

The scaling of traditional nonvolatile memories is rapidly reaching an impasse because of the high voltages required to operate the memory arrays. The high voltages are a direct result of the structure, or bitcell, used to form the memory element. A schematic representation of this element is shown in Fig. 1. This bitcell is composed of a MOSFET containing a source of carriers, a drain to remove carriers from the device, a gate used to modulate the injection of carriers from the source of the device, and a substrate used to form the barrier between carriers in the source and the drain. When a voltage above a critical value known as the threshold voltage, Vt, is applied to the gate, carriers from the source traverse the body of the device resulting in a current from source to drain. The memory element also contains an additional gate that is electrically isolated from its surroundings, and is known as the floating gate. Charge can be injected onto this floating gate using a variety of techniques [2] and the presence of charge shifts the threshold voltage of the memory bit, which can be sensed by a change in the current flowing from source to drain as charge is either added to or removed from the floating gate. At a high level, this memory bit possesses wonderful properties. It provides a large signal in the form of drive current from a MOSFET. The threshold voltage shift of the device is proportional to the density of charge stored on the floating gate (see later) and thus does not face the limitations associated with the requirements of maintaining an absolute quantity of stored charge that exists in the case of dynamic random access memories (DRAM) [3]. However, upon closer examination, the flaws in the memory bit become apparent. In order for this memory element to be nonvolatile, the floating gate must be capable of retaining the charge placed on it for the lifetime of the memory. This causes the dielectrics that electrically isolate the floating gate from its surroundings to have thicknesses on the order of 10 nm. The thickness and dielectric constant of these dielectrics are such that a voltage difference on the order of 18 V between the gate and body of the memory

FIG. 1. A conventional floating gate nonvolatile memory bit. The presence of charge stored on the floating gate of the memory bit causes the threshold voltage of the bit to change resulting in different currents flowing from source to drain at a given control gate voltage. Thus the presence or lack of charge on the floating gate can be used to create a memory.

8. SILICON NANOCRYSTAL NONVOLATILE MEMORIES

225

element are required to remove charge from the floating gate in a reasonable amount of time. Scaling of the voltage required to operate these memories is limited by the inability to reduce the thickness of the dielectrics that isolate the floating gate. In Fig. 2, a plot of a typical thickness of the dielectric that separates the floating gate from the body of the memory element (the tunnel oxide), taken from the 2003 International Technology Roadmap for Semiconductors [4], is shown for several generations of Flash memory technology. The size of a typical bitcell is also shown in the plot. As can be seen, despite the fact that the bitcell size has been reduced by over an order of magnitude during the time shown, the tunnel oxide thickness has remained relatively constant. For a given memory size, this has resulted in a larger fraction of the memory array being occupied by the large devices required to switch these high voltages. These high voltage transistors cannot be reduced in size without a voltage reduction. If taken to an extreme, one can imagine a situation where, for a given memory size, the memory array is no longer reduced in size as the semiconductor industry moves from one technology node to the next, violating one of the fundamental premises behind developing new technologies for this industry. Simple calculations would suggest that the thickness required to retain charge on the floating gate of a nonvolatile memory bitcell is approximately a factor of two smaller than current tunnel oxide thicknesses [5]. In fact, the ability to reduce the tunnel oxide thickness is limited not by fundamental properties of the dielectric but rather by defects that exist in the dielectric. Thus, if a technology could be developed that was immune to defects in the dielectrics used to isolate the floating gates of a nonvolatile memory bitcell, the operating voltages of these memories could be reduced to enable continued scaling of the technology.

FIG. 2. The scaling of NOR bit cell size and tunnel oxide thickness over several technology nodes as predicted by the International Technology Roadmap for Semiconductors. The lack of tunnel oxide scaling limits voltage scaling in this memory devices, ultimately leading to an inability to scale the memory module size.

226

MURALIDHAR ET AL.

Nonvolatile memories based on silicon nanocrystals fall precisely into this category. The properties of these memories will be discussed in the following sections with careful attention being paid to the ideal properties of the silicon nanocrystal-based charge trapping medium, device architectures and modes of operating the memory, processes for creating silicon nanocrystals, discussion of the impact of fluctuations in the spatial location of nanocrystals on these memories, and experimental results on memory arrays.

3. SILICON NANOCRYSTAL MEMORIES AND IDEAL NANOCRYSTAL PROPERTIES

The silicon nanocrystal nonvolatile memories discussed in this chapter are memory bits in which the floating gate of a conventional nonvolatile memory cell is replaced with an artificially created charge trapping layer formed with silicon nanocrystals and silicon dioxide. Because the silicon nanocrystals in this silicon dioxide matrix can store charge, the presence or lack of charge in the nanocrystals can form the basis of a memory element with the charge being sensed through a change in the threshold voltage of a MOSFET in which the artificially created charge trapping medium is inserted between the gate and channel of the device (Fig. 3). In this memory element, the nanocrystals are separated from the channel or body of the MOSFET by a dielectric, or tunnel oxide, typically composed of silicon dioxide. Reduction of the tunnel oxide thickness over that conventionally found in traditional floating gate nonvolatile memories is enabled due to the isolated nature of the silicon nanocrystals. This isolation results in isolated charge storage thus resulting in only local charge loss if a nanocrystal is near a tunnel oxide defect, with the majority of nanocrystals retaining their stored charge. In contrast, for the electrically continuous floating gate found in conventional non-volatile memories, this same tunnel oxide defect would result in complete charge loss from the floating gate. As mentioned earlier, this allows a reduction in the tunnel oxide thickness to near ideal values.

FIG. 3. A silicon nanocrystal nonvolatile memory bitcell. In its simplest incarnation, the silicon nanocrystal memory replaces the conventional floating gate of a nonvolatile memory bitcell with an artificial charge trapping layer created by placing silicon nanocrystals in a silicon dioxide matrix.


227

To better quantify the impact of nanocrystal charge storage on the memory device, a simple one-dimensional argument can be constructed in which one evaluates the impact of a silicon layer with uniform charge density on the threshold voltage of a MOSFET. This type of analysis shows that the threshold voltage shift, ΔVt, from the presence of charge in the silicon nanocrystals is given by: DVt =

qnd ⎛ 2e Si tox ⎞ 1+ , 2e Si ⎜⎝ e ox d ⎟⎠

(1)

where n is the number density of nanocrystals, q is the charge of an electron, eSi is the dielectric constant of silicon, d is the diameter of the silicon nanocrystal, and eox and tox are the dielectric constant and thickness, respectively, of the dielectric between the silicon nanocrystal and the gate. Also, note that for silicon nanocrystals, the first term in the expression is approximately an order of magnitude smaller than the second term. Thus, within this model, it is a good approximation to treat the charge stored in the nanocrystals as an ideal sheet of charge located a distance tox from the gate of the device. In this simplified case, the threshold voltage shift reduces to: DVt =

qntox . e ox

(2)

From this equation, it is clear that the maximum threshold voltage shift, which is a measure of the available memory window, is directly proportional to the number density of nanocrystals. With this in mind, it would seem plausible that the nanocrystals should be made as small as possible with a minimum separation. After all, the number density of the nanocrystal layer, n, if the nanocrystals are placed on a square lattice, is simply given by: n = 1/(s + d)2 where s is the spacing between nanocrystals. Thus one would obviously maximize n by making s and d as small as possible. However, there are two negative consequences associated with such a strategy. First, in creating the nanocrystal based memory for nonvolatile memory purposes, it is key that charge migration from one nanocrystal to a neighboring nanocrystal be eliminated to avoid susceptibility to defects in the oxide. To sufficiently eliminate this lateral charge migration, the nanocrystals must be separated by a distance of approximately 5 nm. This places a lower limit on s. Second, the reduction of the nanocrystal diameter, results in enhanced coulomb blockade effects due to the reduction in nanocrystal capacitance and increased confinement effects on the single particle energy levels of the nanocrystal. These effects reduce the maximum number of electrons that a nanocrystal can hold before data retention becomes an issue. Although the many body problem represented by coulomb blockade is complex, if we ignore quantum mechanical confinement effects and focus only on the electrostatic impact of charging a nanocrystal, we can estimate the change in the energy of the single particle levels of the nanocrystal in going from N − 1 electrons to N electrons by calculating the work required to bring an electron from infinity to the surface of a sphere containing N-1 electrons. In doing this, the change in the single particle energy levels of the nanocrystal, ΔE, is found to be:

228

MURALIDHAR ET AL.

q 2 (N − 1) q 2 (N − 1) q 2 (N − 1) d r = = , 4peR C 4per 2 ∞ R

DE ≈ ∫

(3)

where q is the fundamental electron charge, N is the number of electrons stored in the nanocrystal, R is the radius of the nanocrystal, e is the dielectric constant of the medium in which the nanocrystal is embedded, and C is the capacitance of an isolated nanocrystal. As the energy of the electron energy levels increases with the addition of each electron, the barrier height to emission or tunneling out of the nanocrystal is reduced. Thus, requiring an electron to remain in the nanocrystal for a period of time that represents the data retention specification of the memory bit corresponds to setting an allowable ΔE. If one solves this equation for the maximum number of electrons a nanocrystal can hold for the lifetime of the memory and combines this with the expression for threshold voltage shift, one finds that the threshold voltage shift or memory window can be given approximately by: DVt ≈

DE 4ped 1 d =A , 2q 2Ccontrol (s + d )2 (s + d )2

(4)

where A is a constant introduced to simplify the expression. Figure 4 shows a simple plot of this function. Differentiating this expression with respect to the nanocrystal diameter indicates that the maximum nanocrystal window occurs when the nanocrystal diameter is equal to the spacing between nanocrystals. Given the materials properties of silicon and silicon dioxide, this implies that a nanocrystal process that can produce a nanocrystal with a diameter of 5 nm and a spacing of 5 nm should yield optimum memory performance for this materials system. More discussion of

threshold voltage shirt / volts

2.5 silicon nanocrystals

2 1.5 1 0.5 0

d

0

8 10 2 4 6 nanocrystal diameter / nm

s

12

FIG. 4. The available threshold voltage shift in a nanocrystal memory is dependent on both the density of nanocrystals and the size of the nanocrystal. A simple argument (see text) shows that an optimum threshold voltage shift exists when the nanocrystal diameter, d, is equal to the spacing between nanocrystals, s.


229

the process technology that can deliver such sizes and spacing for the silicon/silicon dioxide materials system is presented in Sect. 6.

4. DIRECT TUNNELING MEMORIES

In 1995, Tiwari et al. [6] introduced the concept of a dense memory element based on the storage of charge in silicon quantum dots formed above the channel of a MOSFET. The thickness of the tunnel oxide in this memory element is such that it enables the use of direct tunneling to add or remove electrons or holes from the silicon nanocrystals. This provides a low power, single transistor bit cell in which one can trade off program and erase speed with degrees of nonvolatility, with the tradeoff being accomplished through changes in the tunnel oxide thickness. The use of direct tunneling to program and erase the nanocrystals also offers the hope of a limitless number of program and erase operations with the memory, since direct tunneling should not result in the degraded tunnel oxide and trapped charge typically observed in traditional floating gate memories programmed by hot-carrier injection or Fowler-Nordheim tunneling [2]. Well separated energy levels found in the small silicon nanocrystals also offer the promise of unique device properties that include well controlled multi-memory state per bit devices. The use of common materials such as silicon and silicon dioxide promise a more rapid introduction of the technology into mainstream semiconductor manufacturing due to the relatively mature process technology that exists for these materials. Figure 5 shows a device cross section of a silicon nanocrystal memory with a 3.8 nm tunnel oxide (note that the thickness appears larger in the cross section due to the fact that the cross section does not go through the exact center of the nanocrystal).

FIG. 5. A TEM cross section of a nanocrystal memory device with 3.8 nm tunnel oxide. The thickness of the tunnel oxide in this device allows the program and erase operations for the memory bit to be carried out with direct tunneling.

230

MURALIDHAR ET AL.

The nanocrystals in this device were produced using a chemical vapor deposition process (Sect. 6) that resulted in nanocrystals with an average diameter of 5 nm and a number density of approximately 1 × 1012 cm−2. The thickness of the tunnel oxide was chosen based on models developed to predict the long term charge retention behavior of silicon nanocrystals [7]. These particular devices were designed so that the silicon nanocrystals would retain stored charge for times of ten years at temperatures of 150°C. The expected charge retention of the silicon nanocrystal memory device as a function of tunnel oxide thickness is shown in Fig. 6. The cases are calculated for the range of the likely effective mass in the oxide. The oxide barrier height is 3.15 eV. Figure 7 shows the shift in threshold voltage as a function of programming. As can be seen, threshold voltage shifts of approximately 0.5–0.6 V, corresponding to approximately one electron per nanocrystal can be achieved in times of 40 ms with voltages of 6–7 V on the gate. Erase times, shown in Fig. 8, with −7 V on the gate are approximately 1 s. The results shown here represent reasonable performance for a nonvolatile memory replacement. Although the properties of a single bitcell look promising from the data shown thus far, there are several issues with the direct tunneling bitcell that limit its usefulness as a conventional Flash nonvolatile memory replacement. One of the key issues is that of read disturb. In many applications, a memory bit is read almost continuously over the lifetime of the memory array. In memories based on direct tunneling, there is a small but finite probability of a charge carrier in the channel of the device tunneling through the tunnel oxide into the charge storage medium

106

Lifetime (Year)

104

102

100

10−2

30

35

40

45

Tunnel Oxida Thickness (Å) FIG. 6. The calculated lifetime as a function of tunnel oxide thickness for charge decay from a nanocrystal assuming one electron stored per nanocrystal in the conduction band, a nanocrystal density of 9 × 1011 cm−2, and an equivalent control oxide thickness of 7 nm.


231

FIG. 7. Threshold voltage shift as a function of time for a silicon nanocrystal memory bit programmed by direct tunneling. A schematic band diagram is also shown in the figure. Threshold voltage shifts on the order of 0.5 V can be obtained at programming times of approximately 40 ms with a programming gate voltage of 7 V.

FIG. 8. Threshold voltage shift as a function of time for a silicon nanocrystal memory bit erased by direct tunneling. A schematic band diagram is also shown in the figure. These data show that a 0.5 V threshold voltage shift can be erase by direct tunneling in approximately 1 s at an erase gate voltage of −7 V.

formed by the nanocrystals and silicon dioxide. Although the time to read a bit is generally much smaller than the time typically required to program the bit, if the time between read operations is much smaller than the retention time of a charge in the nanocrystal (typically this is desired!), then the probability of an electron being trapped in the nanocrystal approaches one as the number of read operations becomes very large. Mathematically, if we define the probability of an electron tunneling through the tunnel barrier during a read operation as, p, then the probability of the nanocrystal remaining free of a tunneling charge carrier will be 1 − p. If k read operations occur in a time much smaller than the retention time of the charge carrier in the nanocrystal, then the probability of the nanocrystal remaining free of a charge carrier, P, is P = (1 − p)k. For small p, we can rewrite this expression as

232

MURALIDHAR ET AL.

P = 1 − kp which indicates the programming of a nanocrystal during a read operation will occur in approximately 1/p read operations. In Fig. 9, this phenomenon is shown by plotting the threshold voltage of an erased bit as a function of time under read conditions. A one volt shift in the threshold voltage of the memory bit is seen to occur on time scales on the order of 1,000 s. This corresponds to approximately 1011 read operations, a value that is far below the 1015 to 1016 read operations a memory bit may experience over the life of the part. Circuit techniques (for example, periodic erasing of the memory array) can alleviate these issues but make the implementation of the technology somewhat more difficult as a direct Flash nonvolatile memory replacement. The second issue that must be overcome with direct tunneling memories is the relatively small threshold voltage shift present in these memories. In Fig. 10, a fictitious threshold voltage distribution of memory bits in the programmed and erased states is shown for illustrative purposes. In any real memory, slight variations in the individual bit properties lead to a distribution in threshold voltage for both the erased and the programmed state. At the very least, to maintain an ability to differentiate a programmed bit from an erased bit, the threshold voltage shift in a memory bit must be larger than the width of the erased state distribution. Threshold voltage variations due to intrinsic random dopant fluctuations alone in a direct tunneling memory are estimated to be on the order of 0.5 V in a 150 nm gatelength

FIG. 9. Threshold voltage of a silicon nanocrystal memory bit as a function of time under a constant gate voltage designed to simulate a read operation. As can be seen, in devices with a thin tunnel oxide, uncharged nanocrystals will eventually be programmed resulting in an erased bit becoming a programmed bit. This effect, known as erased state read disturb can be mitigated through the use of a thick tunnel oxide.


233

108 107

erased state

programmed state

number of bits

106 gate voltage during read

105 104 103 102 101 −1

0

1 2 3 threshold voltage / (volts)

4

5

FIG. 10. The threshold voltage distribution of the erased state and programmed state. The gate voltage during a read operation is typically set at a value between the least erased memory bit and the least programmed memory bit. In addition, the gate voltage during read must be large enough to guarantee that the least erased memory bit meets the required memory access time.

bitcell [8]. Thus a minimum threshold voltage shift of at least 0.5 V is required for this type of memory technology. In reality, to meet required memory access times and build margin for other sources of variation, a threshold voltage shift at least a factor of three larger than this value is required for memory functionality, with the exact value of the shift depending on the particular memory operating specifications.

5. HCI PROGRAMMING/FOWLER-NORDHEIM ERASE SI NANOCRYSTAL MEMORIES

Given some of the difficulties associated with implementing a silicon nanocrystal bitcell that utilizes direct tunneling for program and erase operations, it is natural to explore the advantages of a bitcell that eliminates the read disturb issue associated with the thin tunnel dielectric-based nanocrystal memories. To accomplish this, it is easiest to simply increase the thickness of the tunnel oxide to value of approximately 5 nm. However, this effectively eliminates the possibility of programming and erasing the memory through direct tunneling and forces one into a method of programming and erasing the bitcell with techniques typically found in conventional Flash technology: Hot carrier injection (HCI) for programming and Fowler-Nordheim Tunneling for erasing the bitcell [2]. Interestingly, memories that utilized silicon clusters for charge storage and programming by these techniques were contemplated in the early 1970s [9]!

234

MURALIDHAR ET AL.

In Fig. 11, a plot of the programming time of a thick tunnel oxide silicon nanocrystal-based bitcell under HCI conditions is shown. In this mode of operation, high electric fields are generated in the channel of the bitcell through appropriate source, drain, substrate, and gate biases. The high fields create carriers with sufficient energy to surmount the silicon/silicon dioxide barrier that exists at the substrate/tunnel oxide interface. Once carriers are injected into the silicon dioxide conduction band using this technique, they are able to drift through the charge trapping medium until they are either captured by a nanocrystal or emitted to the gate of the bitcell. It is important to note that the generation of hot electrons using this technique is a local phenomenon that typically occurs in proximity to the drain of the bitcell. The charging of nanocrystals also occurs only near these high field regions thus resulting in nonuniform charge distribution in the nanocrystal charge trapping layer. This can been advantageous in creating mutli-bit per bitcell memories [10]. The programming time of a silicon nanocrystal bitcell under HCI operation can be quite fast with threshold voltage shifts of approximately 2 V obtained in times of approximately 10 ms. The time required to program a particular threshold voltage shift in the device can be modulated with programming bias as is also shown in Fig. 11 where sub 1 ms programming times for a 2 V threshold voltage shift can be obtained with a gate voltage of 9 V, drain voltage of 4.5 V, and with the source and substrate grounded.

5.5

gate = 6V, drain=3.5V

threshold voltage / volts

5

substrate= −2.0V, source=0V

4.5 4

gate = 9V, drain=4.5V substrate=0V, source=0V

3.5 3 2.5

gate = −12V, drain=0V

2

substrate=0V, source=0V 1.5 10-7

10-6

10-5

10-4

10-3

10-2

10-1

time / sec FIG. 11. The threshold voltage as a function of time for a silicon nanocrystal nonvolatile memory bit when programmed by hot carrier injection (HCI) and erased by Fowler-Nordheim tunneling.


235

It is interesting to look at the programming curve of the bitcell as a function of time. As programming begins, the threshold voltage of the bitcell increases monotonically and then saturates at a value that is a function of the programming conditions. This saturation is believed to represent the point at which the rate of charge injection from the channel of the bitcell into a nanocrystal is balanced by the rate of charge emission out of a nanocrystal. The value of threshold voltage shift at which the saturation occurs is a function of the gate bias with the saturation threshold voltage shift decreasing as the gate bias increases. This can be understood from the impact the gate bias has on the two current injection mechanisms associated with the bitcell. In the case of injection of charge from the channel of the bitcell, increasing the gate bias for a given source, drain, and substrate bias tends to decrease HCI. With a decrease in this injection current, the balance between charge injection into the nanocrystal and charge emission from the nanocrystal can be reached at a lower level of nanocrystal charge storage, which translates directly to a lower threshold voltage shift. For the case of charge emission from the nanocrystal, the increased gate bias during programming results in a higher electric field in the control gate dielectric over the nanocrystal and thus allows increased emission from Fowler-Nordheim tunneling. The amount of charge required to balance the injection current is thus reduced, also resulting in a lower threshold voltage shift. The erase characteristics of the bitcell when using Fowler-Nordheim tunneling are also shown in Fig. 11. The application of −12 V to the gate results in the tunneling of charge carriers from the filled nanocrystals to the substrate of the bitcell. The time required to erase the device is seen to be around 100 ms with a 10 nm SiO2 control gate dielectric. This is very competitive with conventional Flash technology but represents a substantial reduction in the voltage required for erase from values of approximately −18 V in Flash to the −12 V needed for the nanocrystal bitcell. The data retention of electrons stored in the silicon nanocrystal bitcell is shown in Fig. 12. At temperatures of 150°C, the results indicate very little in the way of 4 temperature = 150 C

FIG. 12. The threshold voltage as a function of time for a silicon nanocrystal memory bit programmed to a 2 V threshold voltage shift. The threshold voltage for the memory bit is measured at room temperature but the bit is held at 150°C between measurements.

threshold voltage / volts

3.5

programmed state

3 2.5 2 1.5 erased state 1 10−3

10−2

10−1

100 101 time / hours

102

103

104

236

MURALIDHAR ET AL.

charge loss when the bitcell is programmed to a greater than 2 V threshold voltage shift. These data are again taken for a bitcell with a tunnel oxide thickness of approximately 5 nm and a control gate dielectric thickness of approximately 10 nm. However, although unbiased data retention in this type of memory is typically very good, the memory is susceptible to long-term charge loss from the nanocrystals while the memory is being read. To illustrate this effect, Fig. 13 shows the data retention of both the programmed and erased states of a bitcell when subjected to a constant positive gate bias of 6 V. Under these conditions, carriers can be removed from the nanocrystal and emitted into the gate through either a tunneling or trapassisted tunneling process. Note, this phenomenon is somewhat unique to nanocrystal-based memories and can be turned into an advantage: the ability to erase the memory by Fowler-Nordheim tunneling of charge from the nanocrystal through the control gate dielectric [11]. In Fig. 13, one can also see the impact of nanocrystal size on this phenomenon. In this experiment, memory bits with approximately the same nanocrystal density but different nanocrystal sizes were subjected to the 6 V gate bias discussed above. As the size of a nanocrystal is reduced, the maximum amount of charge that can be held for a given amount of time is also reduced. This is clearly seen in the figure where the bitcell with an average nanocrystal size of 6.2 nm is able to hold a given amount of charge several orders of magnitude longer than the bitcell with an average nanocrystal size of 3.6 nm. Another key attribute of nonvolatile memory technology is the ability to program and erase the memory bits without degradation of their properties. In traditional floating gate nonvolatile memory, this property, known as endurance, is typically limited by charge trapping in the tunnel oxide because of either preexisting

FIG. 13. The threshold voltage as a function of time for a silicon nanocrystal memory bit subjected to a positive gate bias of 6 V and a substrate bias of −2 V. These data show that electrons from the nanocrystals can be removed by tunneling through the control gate dielectric into the gate of the memory bit. The degree of this disturb is a function of both the number of electrons stored in the nanocrystal and the size of the nanocrystal.


237

6

Threshold Voltage (V)

5

4 ~1.5V increase in threshold voltage 3

2

1 10−1

100

101 102 103 104 Program/Erase Cycling

105

106

FIG. 14. The change in threshold voltage of a silicon nanocrystal memory bit as a function of the number of times a program and erase operation has been performed on the memory bit. The change in threshold voltage is due to charge trapping the dielectrics that surround the nanocrystal.

defects or defects created during the program and erase operation. In the ideal case of spherical nanocrystals deposited on a silicon dioxide surface in a square lattice, the area fraction of the surface occupied nanocrystals is 25%. With 75% of silicon dioxide surface being free of a trapping medium, the majority of hot electrons injected over the silicon dioxide/silicon barrier during the programming operation pass through both the tunnel dielectric and the control gate dielectric, emerging at the gate. Because of this, silicon nanocrystal memories are more susceptible to charge traps present in the deposited control gate dielectric, which can have trap densities in the 1018 cm−3−1019 cm−3 range [12]. The presence of these traps leads to a systematic increase in the threshold voltage of the bitcell as the bitcell is programmed and erased. In Fig. 14, an example of this phenomenon is shown where the threshold voltage of an erased bit is seen to increase by approximately 1.5 V after 105 program and erase operations. Thus, for this type of memory, it is critical to develop deposited dielectrics, which have inherently low trap densities to serve as control gate dielectrics

6. SILICON NANOCRYSTAL DEPOSITION PROCESSES

As discussed earlier, crucial to the making a nanocrystal memory is the ability to form nanocrystals with an average size of approximately 5 nm, separated by an average distance of approximately 5 nm. On a square lattice, this corresponds to a nanocrystal density of 1012 cm−2. In addition, processes that allow control of the location of the nanocrystals relative to the substrate and gate of the memory bit are desirable. Numerous efforts in the literature have focused on obtaining a high density

238

MURALIDHAR ET AL.

of silicon nanocrystals through techniques such as chemical vapor deposition (CVD) [13], aerosol deposition [14], ion-implantation of silicon into silicon dioxide [15], and recrystallization of amorphous-Si [16]. In this chapter, we focus on the CVD process given the degree to which similar processes are used in the semiconductor industry. In addition, the other methods have either not demonstrated the required densities in a single layer of nanocrystals (e.g., recrystallization) or result in multilayered nanocrystals without a fixed tunnel oxide thickness (e.g., aerosol deposition or ion implantation). Furthermore, as will be shown, nucleation and growth by CVD provides appropriate processing controls for manipulating both the size of and spacing between nanocrystals. Si nanocrystals with number densities between 1011 and 1012 cm−2 have been deposited on various amorphous dielectrics such as SiO2, Si3N4, and Al2O3 using CVD [17–19]. Si island growth during CVD on these amorphous dielectrics is believed to proceed by atomistic nucleation, with a critical size of between 1 and 4 atoms [20]. Figure 15a shows a typical nucleation and growth curve for Si nanocrystal formation during CVD along with plan view SEM images of the surface during various stages of nucleation and growth. During the initial incubation phase, there are not enough adatoms formed on the surface for nucleation to occur and the surface adatom concentration increases with time. Once a sufficient surface concentration of adatoms is attained, nucleation occurs as adatoms diffusively encounter each other to form critical nuclei. During this nucleation phase, the number of nanocrystals increases rapidly as new nuclei are formed. The nanocrystals formed by nucleation grow by adatom attachment through surface diffusion and direct epitaxy. Initially, the growth phase overlaps with the nucleation phase. However, once a certain saturation nanocrystal density is attained, new nucleation is shut off as all incoming adatoms are captured by existing nanocrystals. This results in a saturation of the nanocrystal density in time, which can be advantageous for process stability given that the nanocrystal density in this region is not a strong function of the deposition time. Eventually, the growing nanocrystals merge with adjacent ones by coalescence, and the nanocrystal density decreases as a continuous network of clusters is formed. Figure 15b depicts the major processes occurring a

b

SiH4(gas)

Evaporation Stable cluster

* Desorption SiH4 adatom + H2

Nucleation

FIG. 15. (a) Typical nucleation and growth curve along with SEM images showing the evolution of nanocrystals on SiO2 surface during CVD of Si and (b) major processes – including SiH4 adsorption, adatom re-evaporation and diffusion as well as H2 desorption – during atomistic nucleation of Si nanocrystals.


239

on the dielectric surface during atomistic nucleation of Si nanocrystals by CVD, using SiH4 as an example precursor. In this process, an incoming SiH4 molecule from the gas phase is adsorbed on the surface at a physisorption site of surface energy minima and dissociates to form a Si adatom accompanied with H2 desorption. The formed Si adatom then either contributes to the formation of a new nanocrystal through atomistic nucleation or is consumed by an existing nanocrystal through surface diffusion. H2 desorption at a high rate is desired to optimize silicon adatom formation on the surface. To obtain a high nanocrystal density, a high adatom flux is desired to insure a high probability of forming critical nuclei by control of the adatom surface concentration. In addition, low adatom surface diffusivity is preferred to insure that stable nanocrystals already present on the surface do not deplete the adatom source of to be formed nanocrystals. To gain a better understanding of the physics behind nanocrystal formation by CVD, we can consider the process as that of molecular beam epitaxy deposition. For this process, the saturation nanocrystal density, ns, is given by Venables [21] for initially incomplete condensation and 3d island growth as: ⎛ 2 ( Ei + iEa ) ⎞ ns ~ F 2i/5 exp ⎜ ⎟⎠ , ⎝5 kT

(5)

where F is the flux of adatoms, i is the critical size, and Ei, and Ea are the binding energy of a cluster of i atoms and the adsorption energy, respectively. From this expression, it is clear that the saturation density increases with adatom flux and decreasing temperature (which typically equates to reduced surface diffusivity). In a CVD process, the presence of chemical reaction determines the adatom flux and as such the dependencies on temperature can be more complicated. Although the model presented by Venables allows prediction of the maximum nanocrystal density as a function of process conditions, it does not explain the temporal evolution of the average nanocrystal size or the distribution of nanocrystal sizes found in a typical CVD reactor. This knowledge is critical because the temporal evolution determines the ultimate spacing between nanocrystals as well as their size, the two key parameters that must be optimized for the devices discussed in this chapter. Stoker et al. [22] have developed a model capable of predicting the temporal evolution of nanocrystal nucleation and growth by taking into account most of the elementary processes that occur in a CVD process. This model is now summarized here. To simplify the model, it is assumed that all nanocrystals are hemispherical in shape and that stable nanocrystals are immobile. Precursor adsorption and dissociation are assumed to occur in a two-step process, which for SiH4, as an example, is given below SiH 4 (g) + * → SiH 2 (s) + H 2 (g)

(6)

SiH 2 (s) → Si(s) + H 2 (g), where “*” indicates a vacant adsorption site on the SiO2 surface. Both processes are assumed to be first-order with respect to the concentration of the reacting surface species.

240

MURALIDHAR ET AL.

The critical size is assumed to be 1 atom and as such the nucleation rate is described by the simple rate equation: dN = knq Si2 , dt

(7)

where qSi corresponds to the silicon adatom coverage and kn is a rate constant for the nucleation process. As discussed earlier, nanocrystals grow by surface adatom diffusion and direct epitaxy. The solid line in Fig. 16 shows the expected evolution of nanocrystal size with time based on a solution of the steady-state diffusion equation for the adatom flux to the nanocrystal and including the contribution from direct epitaxy. To simplify the calculations, the model approximates this evolution as two linear growth regimes. These are shown as dotted lines in Fig. 16 along with experimental data. Nanocrystal coalescence, the merging of two adjacent nanocrystals into a single nanocrystal, becomes increasingly important as the nanocrystal surface coverage increases. Coalescence is assumed to occur whenever growth causes two nanocrystals to intersect, and the size of the resulting nanocrystal is determined by mass conservation. Model predictions and experimental measurements of the nanocrystal density as a function of deposition time are shown in Fig. 17. Both the model and experimental data indicate that the density initially increases very rapidly to a maximum value and then decays. The maximum in the model prediction occurs at roughly the same time as the peak in the experimental data, although the model underestimates the maximum density by about 20%.

average nanocrystal size / nm

5

4 model Data

3

2 steady state diffusion equation 1

0 0

0.2

0.4 0.6 normalized time

0.8

1

FIG. 16. Average nanocrystal size as a function of time for the nanocrystal nucleation and growth model of Stoker et al [22]. The ability to predict the temporal evolution of silicon nanocrystal size is critical for nanocrystal memories given the dependence of the memories critical properties on both nanocrystal size and density.


241

nanocrystal density x cm2

2 x1012

1.5 x1012

1 x1012

5 x1011

0

0

0.2

0.4

0.6

0.8

1

normalized time FIG. 17. A comparison of the experimentally determined silicon nanocrystal density as a function of time with the nanocrystal nucleation and growth model of Stoker et al. [22]. The ability to predict the temporal evolution of nanocrystal density is critical to establishing a viable silicon nanocrystal memory technology.

The above model has been shown to provide reasonable predictive capability in determining both the size and density of silicon nanocrystals as a function of process conditions and time. The model shows that the optimum nanocrystal layer property of having a nanocrystal diameter equal to the spacing between nanocrystals can be achieved by proper control of adatom surface diffusivity and the surface flux of adatoms through proper precursor selection. Although the development of processes for the deposition of silicon nanocrystals is critical to creating a viable memory technology, other issues associated with construction of the bitcells discussed in this chapter are equally important. One of the key problems that must be overcome in developing a silicon nanocrystal memory technology is the ability to integrate the nanocrystals into a typical MOSFET integration flow. In particular, the silicon nanocrystals, once deposited, are often subjected to various oxidizing ambients during the memory device formation process. This can occur during the deposition of the control gate dielectric, for example, or during the gate reoxidation processes that often occur following the patterning of the gate electrode when constructing a MOSFET. The oxidation of silicon nanocrystals has been studied [23], and the results show that stress effects are known to limit the oxidation of silicon in these geometries, especially at low temperatures. However, at the high temperatures that may be encountered during memory bit processing, stress relaxation can occur at the silicon/ silicon dioxide interface resulting in the complete oxidation of the nanocrystal or a reduction in the diameter of the nanocrystal to values much less than optimum. The reduction in nanocrystal size is especially a concern given the sensitivity of the end of life threshold voltage shift in a nanocrystal memory to nanocrystal size that is shown in Fig. 4.

242

MURALIDHAR ET AL.

FIG. 18. (a) An energy filtered transmission electron microscope image of a silicon nanocrystal after being subjected to strong oxidizing conditions. This nanocrystal remains is free from oxidation due to appropriate passivationof the nanocrystal surface. (b) A similar image as an (a) except that the nanocrystal was not passivated. This resulted in substantial oxidation of the nanocrystal.

To prevent this issue, techniques for passivating the surfaces of nanocrystals have been developed. In particular, annealing the nanocrystals at temperatures of 850°C in a NO ambient has been shown to passivate the nanocrystals by forming a thin shell of SiOxNy [23]. Given the relatively low temperature of this process, this passivation also has the added advantage that it can reduce variations in nanocrystal size that will naturally exist in a CVD by taking advantage of the self-limiting oxidation effects in nanocrystals. Figure 18 shows the ability of passivated nanocrystals to withstand an aggressive oxidizing ambient such as a 1,000°C anneal in oxygen for times of 30 min. The unpassivated nanocrystals oxidize partially forming a thick oxide shell around a Si core, whereas the passivated nanocrystals do not show any signs of oxidation [23].

7 EFFECTS OF NANOCRYSTAL FLUCTUATIONS

As nanocrystals are self-assemled by island growth during CVD, a concern for nanocrystal memories is the impact of nanocrystal density and size fluctuations from device to device. It turns out that the physics of nucleation and growth in CVD can be used to minimize fluctuations. Furthermore, the nonlocal nature of the influence of a charge located in the nanocrystal mitigates the effect of nanocrystal spatial variations. In this section, we discuss these two ideas. Silicon nanocrystal nucleation and growth during CVD is not completely random in space but rather benefits from the self-ordering inherent in the formation process. This self-assembly characteristic arises from the formation of nucleation exclusion zones around each stable nanocrystal (Fig. 19). The exclusion zones are the result of adatoms being lost to stable nanocrystals, thus resulting in a depletion


243

FIG. 19. The deposition of silicon nanocrystals using a CVD process results in a partially-ordered arrangement of nanocrystals due the nucleation exclusions zones that form between stable nuclei. In these regions, additional nanocrystal nucleation is suppressed since adatoms present in these regions are more likely to be captured by the existing stable nuclei. The TEM image on the right shows that the location of silicon nanocrystals on an oxide surface is far from random.

of adatoms in the vicinity of nanocrystals. Within this adatom depletion zone, the probability of a nucleation event occurring is greatly suppressed given that this probability is at least proportional to the square of the adatom concentration. This necessarily implies that neighboring stable nanocrystal nuclei are well separated from one another at the outset, and the resulting nanocrystals are well separated unless they are allowed to grow to coalescence. Within the framework of the model of Stoker et al. discussed above, the radius of this exclusion zone can be derived by solving the adatom diffusion equation around a nanocrystal including appropriate source (surface adatom generation) and sink terms (attachment to other clusters). Mathematically, the resulting expression for the exclusion zone radius, rex, is:

rex2 = rk2 + 2rk

⎛ r ⎞ K1 ⎜ k ⎟ ⎝ Dt ⎠ 8 Dt Dt − 2 p ⎛ rk ⎞ K0 ⎜ ⎟ ⎝ Dt ⎠

∫

∞

0

e

− ( m 2 +1) t

t

dm , (8) ⎡ 2 2 ⎛ mrk ⎞ 2 ⎛ mrk ⎞ ⎤ m(m + 1) ⎢ J 0 ⎜ ⎟ + Y0 ⎜⎝ ⎟⎥ Dt ⎠ ⎦ ⎣ ⎝ Dt ⎠

where rk is the nanocrystal radius, D is the adatom diffusivity, t is the time constant of adatom attachment to other nuclei, desorption and other processes, and J0, Y0, K0, and K1 are Bessel functions. The third term on the right-hand side of (8) corresponds to the transient solution and is important for short times (relative to t) given that the exclusion zone radius as a function of time ultimately determines the nanocrystal size and the spacing between nanocrystals. Figure 19 also shows a plan view energy filtered transmission electron microscope image of silicon nanocrystals produced with a CVD process. From this image, the nanocrystal size and separation distributions were obtained and are shown in Fig. 20. Notice that the distribution of separations exhibits a peak indicating

244

MURALIDHAR ET AL.

FIG. 20. The measured nanocrystal size distribution (a) and edge to edge separation (b) extracted from experimental data such as the plan view TEM image shown in FIG. 19. The solid curve in both figures represents simulation based on a random nucleation model. The peak in the nanocrystal separation distribution function (b) cannot be explained by a random nucleation model.

a spatially nonrandom nucleation process and cannot be explained by a simulation based on a random nucleation model [24]. Although the CVD process used for silicon nanocrystal deposition results in a partially organized growth process, variability in both the size and local density of nanocrystals still remains. Given this, it is important to try and assess the impact of this variability on memory array operation. In particular, it is critical to understand how the MOSFET used to sense the presence of charge in nanocrystals performs in averaging over these fluctuations. To do this, one can adopt an approach similar to that used to analyze the impact of dopant fluctuations on MOSFET device performance [24–26] by considering the effect of the presence of a localized charge in a nanocrystal on the electrostatic surface potential in the substrate of the device. Using an approximate equation for the substrate potential, we can derive [27] an analytical expression for the surface potential, Yx,y. as a function of the local threshold voltage shift, ΔVt(x, y), due to trapped charge, s(x, y), near x and y, sinh( y / ) y ( x, y) = V 0 ( x, y) + [V + V − V 0 ( x, L )] bi ds eff sinh( L / ) eff sinh(( L − y ) / ) eff +[V − V 0 ( x,0)] , bi sinh( L / ) eff

(9)

where for a device wide in comparison to variations in ΔVt(x, y), V 0 ( x, y) = Vgs − VT0 + 2fF − DVave ( x, y), DVave ( x, y) =

∞

1 dx ′ ∫ dk e ik ( x − x ′ ) × 4p 2 ∫ −∞

Leff

∫ dy ′ d (k )e

−| y − y ′| / d ( k )

(10) DVt ( x ′, y ′ ). (11)

0

Equation (9) is a Green’s function solution in the length direction of the MOSFET for each Fourier component of ΔVt(x,y) in the width direction. In the above expressions, Leff is the length scale that characterizes the impact of the drain potential on the substrate potential near the source of the device, x is the depth


245

direction of the device, y is the direction from source to drain, 2φf is the Fermi potential and Vto is the long channel threshold voltage of an uncharged device. Equation (9) suggests that the effect of trapped charge on the surface potential in the substrate is determined through ΔVave that averages over the trapped charge distribution with a Green’s function that decays with a length of l, which is a measure of the substrate debye length. This result implies that as long as the charged nanocrystal separation is less than the debye length of the doped substrate, fluctuations in the substrate potential due to the location of the charge will be small. The typical doping concentrations found in the substrate of the memory devices discussed in this chapter have corresponding debye lengths of approximately 10 nm, and thus the MOSFET is quite effective at averaging over any fluctuations that might occur in nanocrystal location, size, and spacing. To illustrate the impact of this averaging, consider the case in which a device shown in Fig. 21, with charges located in the nanocrystals shown in green, loses charge in such a way that the center row of nanocrystals becomes uncharged (Fig. 22). If the device were to behave as if each line of nanocrystals formed a separate transistor (corresponding to the substrate debye length being much smaller than the nanocrystal to nanocrystal spacing), this configuration would represent a worstcase situation. As shown in Fig. 23, device simulations of this case show that loss of threshold voltage shift is much less than what would be obtained by simply treat-

FIG. 21. A silicon nanocrystal memory device in which all nanocrystals near the drain of the device are storing charge.

FIG. 22. A silicon nanocrystal memory device in which a row of nanocrystals near the drain of the device in FIG. 16, becomes uncharged.

246

MURALIDHAR ET AL. 10−2 10−3

Drain Current (A/μm)

10−4 10−5 10−6 10−7 10−8 Uncharged

10−9

Parallel Transistors Charged

10−10

Charge Averaging

10−11 10−12 0

1

2 Vgate (V)

3

4

FIG. 23. Estimate of threshold voltage shift for the uncharged case, the charged case in FIG. 21, and two models for the case of FIG. 22. The “parallel transistor” model assumes that each line of nanocrystals forms an independent parallel transistor, while the “charge averaging” model uses the calculations presented in the text.

ing each portion as a parallel-connected transistor. For the particular device simulated here, the cased where all nanocrystals are charged results in a threshold voltage shift of approximately 1.1 V. The loss of charge from the central column of nanocrystals reduces the threshold voltage shift to a value of approximately 0.9 V. This 200 mV difference in threshold voltage shift is much smaller than would be estimated if the structure were treated as a set of transistors in parallel where the threshold voltage shift would decrease from 1.1 V to approximately 0.25 V. Thus the fact that the length scale associated with the surface potential impact of a charge stored in a nanocrystal is much larger than the nanocrystal to nanocrystal spacing, a small variation in trap charge distribution may not have a disproportionate effect on the device characteristics. Such a property may become critical to controlling threshold voltage distributions as the memory device dimension scales from technology node to technology node and the number of charged nanocrystals in each transistor falls below 100.

8 MEMORY ARRAY RESULTS

Given the process control of nanocrystal size and density offered by the CVD process for silicon nanocrystal deposition, one can build large memory arrays to assess the impact of nanocrystal process fluctuations on memory array performance. In 2003,


247

Freescale Semiconductor (at that point, the Semiconductor Products Sector of Motorola) demonstrated the first 4 Mb silicon nanocrystal based nonvolatile memory array [11]. In 2005, through further modifications and improvements to the bitcell processes, Freescale demonstrated a 24 Mb memory array using a 90 nm CMOS process technology. A die photo of this memory is shown in Fig. 24. In Fig. 24, the threshold voltage distributions for a typical memory array are also plotted for the erased state. As can be seen in the figure, two distributions exist for the erased state. One represents the threshold voltage distribution of bits before being erased, and is very close to that expected for memory bits with no charge in the nanocrystals. Following an erase of the memory array, the entire “erased state” distribution shows an increase in threshold voltage by approximately 250 mV. This is caused by the need to balance electron capture and electron emission in the nanocrystals when current flows through the surrounding dielectrics during the erase process (at steady state, current injected from the gate of the device is exactly balanced by current emitted from the nanocrystals to the substrate). Slight differences in the barrier heights between the gate electrode and the control gate dielectric, and the silicon nanocrystal and the tunnel oxide can cause this current balance to be achieved with some net charge in the nanocrystals. In addition, the widths of the threshold voltage distributions are seen to be fairly tight with a width of approximately 750 mV. The majority of this variation is believed to be due variations in threshold voltage induced by the random dopant atom placement used to construct the memory array.

FIG. 24. The distribution of threshold voltages from a 24 Mb silicon nanocrystal memory array. The distributions shown are for the case of charge neutral nanocrystals and the nanocrystals following an erase pulse. The erase pulse actually results in a slight programming of the nanocrystals, increasing the threshold voltage of the memory bits.

248

MURALIDHAR ET AL.

The results also indicate that variations in the nanocrystal density and size are not significantly impacting the threshold voltage distributions, as explained earlier. Although this result would not be surprising for nanocrystals with no charge storage (the threshold voltage variation in this case would be due to small variations in the capacitance between the gate and the substrate), the fact that erased state memory bits actually contain approximately one electron per nanocrystal indicates that the bitcell itself is relatively insensitive to local fluctuations in the nanocrystal properties.

9 SUMMARY

The vision laid out by Richard Feynman in his 1959 lecture that spawned the field of nanotechnology is becoming more real with each passing year. The semiconductor industry, which represents perhaps the best example of “top down” nanotechnology commercialization (state-of-the-art MOSFETs have dimensions as small as the smallest virus!), is facing tremendous challenges as it works to stay on the exponential growth path experienced over the last 40 years. This is especially true in the area of nonvolatile memory technology. In this chapter, we have shown the promise of a technology that is based on a combination of both “tops down” and “bottoms up” nanotechnology to alleviate some of these scaling challenges in the memory area. In particular, the use of self-assembled silicon nanocrystals in a matrix of silicon dioxide to create an engineered charge trapping layer has been shown to be an excellent solution for reducing the operating voltages of Flash nonvolatile memory.

REFERENCES 1. R.P. Feynman, Ann. Meet. APS, Cal. Inst. Tech., Pasadena, 1959 2. See for example, ‘Nonvolatile Semiconductor Memory Technology: A Comprehensive Guide to Understanding and Using NVSM Devices’ William D. Brown and Joe E.Brewer, IEEE Press, New York, 1998 3. A.F. Tasch and L.H. Parker, Proc. of the IEEE, 77 374 (1989) 4. Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 2003 5. K. Naruke, S. Taguchi, and M. Wada, Tech. Digest International electron Devices Meeting, pp. 424–427, (1988) 6. S. Tiwari, F. Rana, K. Chan, H. Hanafi, Chan Wei, and D. Buchanan, Tech. Digest of International Electron Devices Meeting, 521, 1995. 7. M. Sadd, R. Muralidhar, S. Madhukar, K. Scheer, D. Gentile, B. Hradsky, M. Rossow, R. Rao, M. Ramon, A. Konkar, J. Conner, S. Bagchi, and B. E. White, NVSMW (2000) 8. D. Burnett, J. Higman, A. Hoefler, Chi-Nan Li, and P. Kuhn, IEDM Tech. Digest, 529 (2002) 9. S. Yamazaki, K. Hatakeyama, I. Kagawa, and Y. Yamashita, 1973 Int. Electron Devices Meeting Tech. Digest, 355 (1973) 10. B. Hradsky, R. Rao, R.F. Steimle, M. Sadd, S. Straub, R. Muralidhar, and B. White, NVSMW 99 (2003). 11. R. Muralidhar, R.F. Steimle, M. Sadd, R. Rao, C.T. Swift, E.J. Prinz, J. Yater, L. Grieve, K. Harber, B. Hradsky, S. Straub, B. Acred, W. Paulson, W. Chen, L. Parker, S.G.H. Anderson, M. Rossow, T.


12.

13. 14. 15. 16. 17. 18.

19. 20. 21. 22.

23. 24. 25. 26. 27.

249

Merchant, M. Paransky, T. Huynh, D. Hadad, Ko-min Chang, and B.E. White Jr, Tech. Digest of International Electron Device Meeting, 26.2.1–26.2.4, (2003). F.B. McClean, H.E. Boesch, Jr., and T.R. Oldham, “Electron-Hole Generation, Transport, and Trapping in SiO2” in “Ionizing Radiation Effects in MOS Devices and Circuits” edited by T.P. Ma and Paul V. Dressendorfer, Wiley-IEEE, 1989, p. 87–192. F. Mazen, T. Baron, G. Bremond, N. Buffet, N. Rochat, P. Mur, and M.N. Semeria, J. Electrochem. Soc. 150, G203, (2003). M.L. Ostraat, J.W. De Blauwe, M.L. Green, L.D. Bell, M.L. Brongersma, J. Casperson, R.C. Flagan, and H.A. Atwater, Appl. Phys. Lett., 79, p.433–435 (2001). C.Y. Ng, T.P. Chen, L. Ding, and S. Fung, IEEE Elect. Dev. Lett., vol 27, 231–233 (2006) L. Tsybeskov, K. D. Hirschman, S. P. Duttagupta, M. Zacharias, P. M. Fauchet, J. McCaffrey, and D. J. Lockwood, Appl. Phys. Lett. 72, 43–45 (1998). F. Mazen, T. Baron, G. Bremond, N. Buffet, N. Rochat, P. Mur and M.N. Semeria, J. Electrochem. Soc. 150, G203, (2003). R.A. Rao, R.F. Steimle, M. Sadd, C.T. Swift, B. Hradsky, S. Straub, T. Merchant, M. Stoker, S.G.H. Anderson, M. Rossow, J. Yater, B. Acred, K. Harber, E.J. Prinz, B.E. White Jr., R. Muralidhar, Solid State Electron., 48, 1463 (2004). T. Baron, A. Fernandes, J.F. Damlencourt, B. De Salvo, F. Martin, F. Mazen, F. S. Haukka, Appl. Phys. Lett., 82, 4151 (2003). T. Kamins, Polycrystalline Silicon for Integrated Circuits and Displays, (Kluwer Academic Publishers, Dordrecht, 1998). J.A. Venables, Introduction to Surface and Thin Film Processes, (Cambridge University, Cambridge, 2000). M.W. Stoker, T.P. Merchant, R. Rao, R. Muralidhar, S. Straub, and B.E. White Jr., in Materials and Processes for Nonvolatile Memories, edited by A. Claverie, D. Tsoukalas, T-J. King, and J.M. Slaughter (Mater. Res. Soc. Symp. Proc. 830, Warrendale, PA, 2005) p. D5.7. K.C. Scheer, R.A. Rao, R. Muralidhar, S. Bagchi, J. Conner, L. Lozano, C. Perez, M. Sadd, B.E. White Jr.,. J. Appl. Phys., 93, 5637, (2003). L. Perniola, S. Bernardini, G. Iannaccone, B. De Salvo, G. Ghibaudo, P. Masson, and C. Gerardi, Proc. 34th ESSDERC 249 (2004). Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, M.-C. Jeng, P.K. Ko, and Y.C. Cheng, IEEE Trans. Elec. Dev., 40 86 (1993). L. Perniola, S. Bernardini, G. Iannaccone, P. Masson, B. De Salvo, G. Ghibaudo, and C. Gerardi, IEEE Trans. Nanotech., 4 360 (2005). M.Sadd, S.G.H. Anderson, B. Hradsky, R. Muralidhar, E.J. Prinz, R. Rao, S. Straub, R.F. Steimle, C.T. Swift, B.E. White, and J.A. Yater, Solid State Electron., 49 1754 (2005).

9 Nanocrystalline Silicon Ballistic Electron Emitter Takuya Komoda* and N. Koshida Abstract The finding of visible photoluminescence from nanocrystalline silicon (NS) at room temperature and the development of light-emission device was important step toward silicon-based optoelectronics technology. Subsequent research revealed that these light emission may occur due to silicon nanostructure and intensive research and development to achieve high-efficient, high-intensity, and tunable visible light-emitting devices based on NS was conducted all over the world. In 1998, a novel cold cathode technology based on nanocrystallised polysilicon (NPS) layer was reported by the authors. Its electron emission characteristics strongly suggest that electrons injected to the NPS layer are transported quasiballistically. It showed various excellent characteristics as compared with the conventional FEDs and it was termed ballistic electron surface-emitting display (BSD). In order to demonstrate the possibility of the realisation of large panel FPD, we firstly developed quartz glass-based BSD. We also developed low temperature process to fabricate the BSD on a TFT and a PDP glass substrate. Electrochemical oxidation technique was one of the key process concepts to reduce process temperature. It was also shown that the BSD had excellent thermal stability and a frit-sealed model was fabricated. In this section, we first overview the characteristics of the BSD cold cathode and discuss the mechanism of ballistic electron emission model from the NPS nanostructure. Subsequently, we discuss the relationship between emission efficiency and nanostructure. Finally, w e demonstrate the BSD on glass substrate. We describe the 2.6- and 7.6-in. diagonal full-colour BSD fabricated on a glass substrate with low temperature process and demonstrate strong possibility of the process compatibility for a large panel BSD.

Advanced Technologies Development Laboratory, Panasonic Electric Works, Ltd, Japan, [email protected]


251

252

KOMODA AND KOSHIDA

1. INTRODUCTION

The finding of visible photoluminescence from nanocrystalline silicon (NS) at room temperature [1] and the development of light-emission device [2] was an important step toward silicon-based optoelectronics technology. Subsequent research revealed that these light emission may occur due to silicon nanostructure [3] and intensive research and development to achieve high efficient, high intensity, and tunable visible light-emitting devices based on NS was conducted all over the world [4]. On the course of investigating the electrical excitation process in NS in order to clarify the mechanism of electroluminescence, electron emission from a NS diode with a structure of Au/NS/Si substrate was reported by Koshida et al. in 1995 [5]. It triggered another possibility of an application of nanocrystalline silicon to a novel cold cathode. Until that time, cold cathode was always based on the mechanism of field emission from metals or dielectric materials under a high electric field, such as so called Spindt type cathode or metal–insulator–metal (MIM) type cold cathode [6, 7]. Although intensive research has been done with those cathodes, there was still room for improvement for the practical application. For example, those cold cathodes only worked well under a high vacuum condition and normally need focus electrodes in order to gather emitted electrons to the target. In 1998, a novel cold cathode technology based on nanocrystallised polysilicon (NPS) layer was reported by the authors [8]. Its electron emission characteristics strongly suggest that electrons injected to the NPS layer are transported quasiballistically [9]. It showed various excellent characteristics as compared with the conventional FEDs [10] and it was termed as ballistic electron surface-emitting display (BSD) [11]. In order to demonstrate the possibility of the realisation of large panel FPD, we firstly developed quartz glass-based BSD [12]. We also developed low temperature process to fabricate the BSD on a TFT and a PDP glass substrate [13]. Electrochemical oxidation (ECO) technique was one of the key process concepts to reduce process temperature. It was also shown that the BSD had excellent thermal stability and a frit-sealed model was fabricated [14, 15]. Although BSD exhibits various excellent characteristics as a novel cold cathode, there are still a lot of points to clarify such as mechanism and implication of the electron emission from the structure. In this section, we first overview the characteristics of the BSD cold cathode and discuss the mechanism of ballistic electron emission model from the NPS nanostructure. Subsequently, we discuss the relationship between emission efficiency and nanostructure. Finally, we demonstrate the BSD on glass substrate. We describe the 2.6- and 7.6– in. diagonal full-colour BSD fabricated on a glass substrate with low temperature process and demonstrate strong possibility of the process compatibility for a large panel BSD. 2. FABRICATION AND BASIC CHARACTERISTICS OF THE BSD

2.1. BSD on Silicon Wafers The BSD samples were prepared by the anodisation of polysilicon layer grown on (100) n-type 0.01–0.02 Ω cm silicon wafer. Non-doped polysilicon layers were

9. NANOCRYSTALLINE SILICON BALLISTIC ELECTRON EMITTER

253

grown by low-pressure chemical vapour deposition (LPCVD) on the silicon substrate at a temperature of 650°C to a thickness of 1.5 μm. Subsequently, in order to form nanocrystalline polysilicon (NPS) layer, polysilicon layers were anodised in a solution of HF (50%):ethanol = 1:1 at a current density of 30 mA cm−2 for 12 s under the illumination of 500 W tungsten lamp from a distance of 20 cm. The thickness of NPS layer was about the same as that of polysilicon layer. NPS layers were oxidised by rapid thermal oxidation (RTO) in dry oxygen atmosphere. Samples were put into the quartz furnace of the lamp annealing system and heated up at the various rate up to a temperature of 900°C and oxidised for 60 min. Finally, semitransparent 15-nm gold film was deposited onto the NPS layers by sputtering technique. An ohmic electrode was formed at the back of the silicon wafer. 2.2. BSD on Glass Substrates With regard to glass substrate, 0.7 mm thickness of Corning 1737 TFT and 2.8 mm thickness of Saint-Gobain CS77 glass substrate were used as a starting material. Figure 1 shows the process flow of the BSD on glass substrate. First, a 3,000-Å of tungsten metal layer was deposited onto the surface of the glass substrate as a bottom electrode by a sputtering technique. Subsequently, polysilicon was deposited by a plasma-enhanced chemical vapor deposition (PECVD) technique at a temperature of below 400°C at a thickness of 1.5 μm. After forming polysilicon layer onto the metal bottom electrode, samples were anodised by the same method as that employed with Si substrate. After anodisation, samples were oxidised by an ECO technique. Samples were put into an aqueous solution containing 1 M sulphuric acid (H2SO4) and a current source of 20 mA cm−2 was applied for 20 s to the NPS layer with respect to the solution. Finally, semitransparent 15-nm gold film was deposited as a surface electrode onto the NPS layers by a sputtering technique. 2.3. Measurements and Analyses The prepared samples were characterised electrically and optically. Electrical characterisation was carried out in a high vacuum system. Vacuum level in the chamber was about 10−5 Pa. Among the emission properties, particular interests were paid into the static relationship between diode current Ips and emission current Ie, the emission current fluctuation as a function of time, the emission current stability in a low vacuum level, and energy distribution of the emitted electrons. Static relationship Tungsten film Glass Substrate Deposition of bottom electriode

Anodisation and subsequent oxidation Polysilicon film Surface electrode

Deposition of polysilicon by PECVD

Formation of Surface electrode

FIG. 1. The process flow of the NPS layer on glass substrates.

254

KOMODA AND KOSHIDA

Emitted electrons collector e− e− e− e− e− e− e− e− e− e− e−

Ie vc

Emission current

vps BSD

Ips

Vacuum chamber

Vacuum pump FIG. 2. Schematic of the measurement system of static characteristics.

between Ips and Ie and the emission current fluctuation as a function of time were measured in the conventional measurement system shown in Fig. 2. A dc bias voltage Vps was applied to the top Au electrode with respect to the bottom electrode. The anode electrode was set above the Au electrode and kept at a positive potential Vc of 100 V in order to collect the emitted electrons. The distance between the top Au electrode and the anode electrode was 10 mm. Ie and Ips were measured as a function of Vps. In order to investigate the emission stability to the ambient gas pressure, emission characteristics were measured under various gas pressures with different gas species. Samples on silicon substrate were set up in a high vacuum chamber shown in Fig. 2. Subsequently, a N2 gas was introduced into the chamber and the ambient pressure maintained at a certain level by adjusting leaking valve. Then Vps was applied to the samples and emission current Ie was measured. The applied voltage between the anode electrode and the top Au electrode of the cold cathode was 100 V. The electron energy distributions were measured using a conventional ac-retardingfield analyzer consisting of three parallel flat electrodes. Figure 3 shows the configuration of the system. G1 and G2 are grids, which have a transmission rate of 50% each, and C is a collector electrode. G1 was kept at a positive potential in order to obtain a constant emission. On the other hand, G2 was connected to the ground so that G2 was kept at the same potential as the Au electrode of the samples. The collector electrode C was kept slightly positive with respect to G2 to prevent electrons from backscattering. Retarding voltage VR, which is the slow dc sweeping voltage, was modulated with ac signal of 0.2–0.5Vp-p and 123 Hz. The corresponding ac component of the collector current was detected by a lock-in amplifier and was recorded as a function of VR by a computer. All the electrodes were coated with


255

VACUUM CHAMBER 105Pa n-Si

G0 G1 G2 NPS METAL

C

e−

LOCK-IN AMPLIFIER

COMPUTER

Vps

RETARDING VOLTAGE

Ref. Signal 123Hz 0.2~0.5Vp-p

FIG. 3. Schematic of the measurement system of emitted electrons energy distribution.

lampblack to suppress the secondary electrons emission from them. A variable capacitance Cv was set to eliminate the capacitance between the Au electrode and the anode electrode. 2.4. Emission Characteristics of the BSD Figure 4a shows typical electron emission characteristics of the BSD fabricated on a TFT glass substrate using ECO technique. A high electron emission current density (Je) of 2.43 mA cm−2 was obtained at bias voltage of 18 V. Electron emission efficiency η defined as the ratio of emission current to diode current was about 2.6%. This means that the low temperature process was successfully introduced to the glass compatible process. Figure 4b shows Fowler–Nordheim (FN) plot calculated from the result of Fig. 4a. The FN plot shows linear behaviour suggesting that the electrons injected into the NPS layer are transported via multiple tunnelling through SiO2 thin films formed at the surface of silicon nanocrystallites. Figure 5 shows the emission current stability at Vps = 16 V as a function of time, including the behaviour of Ips. Although both the diode and the emission current slightly change in the initial stage of operation, they have been significantly stabilised. Especially of importance is that there is no spike-like fluctuation in emission current, in contrast to the conventional field emission arrays [6, 7]. It is assumed that anodisation progresses faster at the boundary of the grain of the polycrystalline silicon and the rate of the anodisation in polycrystalline silicon is generally higher than that in bulk crystalline silicon. Therefore, it is a reasonable assumption that the silicon nanocrystallites are created mainly at the surface of the silicon grains.

FIG. 4. (a) Electron emission characteristics of the BSD fabricated on a glass substrate. ECO process was employed. (b) Fowler–Nordheim plot calculated from the result of Fig. 4a.

FIG. 5. The emission current (Ie) stability at Vps = 16 V as a function of time, including the behaviour of Ips.


257

FIG. 6. Emission stability of the BSD against ambient pressure.

Subsequently many crystalline silicon grains remain in the nanocrystalline polysilicon system. Thus, rather large crystalline silicon grains as compared with nanocrystallites can contribute to the better control of the conductivity and the thermal stability of the diode and, as a result, fluctuation-free electron emission can be achieved. The emission current at a higher value was also investigated in terms of the stability against the ambient pressure. Figure 6 shows the N2 gas pressure dependence of the emission current at Vps = 16 V. It is evident that the emission current of about 1 mA cm−2 remains almost constant even at an ambient pressure of 10 Pa. This is consistent with the hypothesis that the emission mechanism is based on generation of energetic electrons under high electric field in NPS layer. 2.5. Energy Distribution of Emitted Electrons Figure 7 shows the energy distribution of emission electrons obtained from the sample at different Vps. X-axis indicates the electron energy and Y-axis indicates the number of emitted electrons (arbitrary unit). Unlike the conventional cold cathode device [16], the distributions are not Maxwellian and strongly depend on Vps. The peak energy and maximum energy shift toward higher energy side in accordance with an increase in Vps. For example, a high peak energy of about 6 eV is shown at Vps = 16 V. The original point of the measured energy distribution corresponds to the vacuum level. Taking the work function of Au, ΦAu, which can be assumed about 6 eV [17], into account, it can be seen that the significant amount of electrons have an energy of about 60% of the value corresponding to e(Vps−ΦAu). The important thing is that the peaks of the energy at the maximum number of emitted electrons Ep and the maximum energy of emitted electrons Emax change fairly with Vps. According to the result of time-of-flight measurement by Sedlacik et al. [18], the drift length of the carriers under strong electric field (about 105 V cm−1) within the PS layer reaches 1 μm. This value is much larger than the size of the average silicon nanocrystallites. It indicates that conduction electrons can easily become hot electrons. It can be assumed that major potential drop is produced at the boundaries such as surface skin of the nanocrystalline silicon or a thin oxide layer between nanocrystallites,

258

KOMODA AND KOSHIDA Level of thermal electron emission (0.1 ˜ 0.3eV)

1

Vps=16 V

N(E) [a.u]

0.8 Vps=14 V

0.6

0.4

0.2

0

Vps=12 V

0

2 4 6 8 Emitted Electron Energy [eV]

10

12

FIG. 7. Characteristics of emitted electron energy distribution.

but not at the bulk. This assumption can be applied to the NPS and the drift length within the NPS under similar electric field is much longer than the grain size (typically 200–300 nm) and, therefore, electrons become hot electrons at the surface area. 2.6. Emission Uniformity and Angular Dispersion It is assumed that the electron emission direction from the samples is normal to the surface of the diode because the energy of the emitted electrons is high enough to ignore the repelling force between emitted electrons. It is also considered that the electron emission uniformity is remarkably high because of many emission sites. To confirm this performance, a monochrome display panel consisting of 4 × 4 addressable pixels was fabricated on a silicon wafer as described in Sect. 2.2. An anode electrode was coated with phosphors (ZnO:Zn;P-15) on Indium Tin Oxide (ITO) glass plate by screen printing technique. The anode plate was set up at a distance of 5 mm from the cathode by quartz spacer. No focusing electrode was set between the anode electrode and the cathode. The display panel was pumped at a pressure of 10−4 Pa and sealed by adhesive for keeping vacuum level. Light emission pattern on the anode phosphor was observed and light emitting sizes were compared with fabricated cathode area. Also, emitted pattern was magnified up to 20 times with a conventional electrostatic lens system shown in Fig. 8. Figure 9a shows the light emission pattern on the anode phosphor. Pixel size was patterned by 4 mm2 and it was confirmed that light-emitting sizes seemed as almost the same as a cathode pattern size. It was also demonstrated their good emission uniformity within each pixel. Figure 9b shows the enlarged emission site of the sample. It is apparent that emission pattern after the magnification of 20 is so uniform that emission sites seem very small and uniform in distribution. It is the complete different results from the conventional Spindt type cathode [6] as shown in Fig. 9c [19].


259

FIG. 8. Schematic of electrostatic lens system.

FIG. 9. (a) The light emission pattern on the anode phosphor, (b) the enlarged emission site of the PPS sample, and (c) the emission sites pattern of Spindt type cathode [19].

3. BALLISTIC EMISSION MODEL

A typical example of the measured energy distribution of emitted electrons is shown in Fig. 7. We can see the characteristic feature of ballistic emission in both the shape of the energy distribution curves and the voltage dependence of the peak energy. One possible model is generation of ballistic electrons in the NPS layer via multiple-tunnelling transport through interfacial barriers between interconnected Si nanocrystallites (NS) as illustrated in Fig. 10. The key issue of this effect is spikelike concentrated high electric field at the NPS interfaces. To confirm the model mentioned above, the electron transport in the NPS layer was analysed by time-of-flight (TOF) measurements for a self-standing NPS layer [20] using a picosecond-width UV laser pulse as shown in Fig. 11.

260

KOMODA AND KOSHIDA

n-Si

e−

NPS

Au

Vacuum

Low Temp.

RT VPS Evac Thin Oxide Si Crystallite

FIG. 10. Ballistic electron emission model.

FIG. 11. Experimental apparatus for TOF analyses of electron transport in NPS layer.


261

Figure 12 shows the transient photocurrent after 35 ps light pulse incidence for a free-standing NPS layer at 300 K. In all cases, we have observed a “plateau” in the initial stage of the transient photocurrent during 20–50 ps just after the UV laser pulse incidence. The period of plateau becomes shorter at higher electric field. After the plateau, the transient photocurrent curves exhibit a simple exponential decay. These results are different from the transient TOF signals of both singlecrystalline silicon and hydrogenated amorphous silicon. The observed plateau and its field dependence are strong indications that some photoexcited electrons are accelerated in the NPS layer ballistically and reach the counter-electrode without suffering significant scattering losses. The simple exponential decay appeared after the plateau, on the other hand, suggests that there is a certain trapping rate for electrons possibly due to interfacial states between interconnected Si nanocrystallites. The drift velocity values derived from the TOF data of Fig. 12. In contrast to the behaviour in single-crystalline silicon, the drift velocity in NPS shows a steady increase with no saturation for increasing field strength. It reaches over 108 cm s−1 at a high electric field even at room temperature. This is considerably

FIG. 12. The observed transient TOF signals for an NPS layer for different electric field.

262

KOMODA AND KOSHIDA

higher than those of both thermalised electrons and hot electrons generated during conventional transport in solids. The corresponding mean free path exceeds 1.5 μm. This value is two orders of magnitude larger than that in crystalline bulk Si. It appears that electrons travel through several hundreds of Si nanocrystallites with little scattering losses. The field-induced enlargement of mean free path is caused by an enhanced tunnelling probability between Si nanocrystallites. The mean kinetic energy gain during the ballistic transport exceeds over 4 eV at a high electric field. It is consistent with the measured mean energy of emitted electrons from NPS diode [21, 22].

4. CORRELATION BETWEEN NANOSTRUCTURES AND EMISSION PERFORMANCE

4.1. Nanocrystallisation of LPCVD-Deposited Polysilicon In this section, the nanocrystallisation mechanism of a columnar structured polysilicon (poly-Si) film is investigated. The poly-Si film was deposited by LPCVD on a crystalline silicon (c-Si) substrate. Figure 13 shows a cross-sectional SEM photograph of the nanocrystallised poly-Si (NPS) layer after anodisation and subsequent RTO treatment. Columnar grains with diameters of 100–500 nm were clearly observed. Brighter areas, corresponding to the oxidized areas, were observed along grain boundaries of columnar Si grains. On the other hand, the central parts of the grains were not oxidized. An etch pit was also observed in the area where the oxidized part reached the c-Si substrate. These results suggest that oxidation proceeds at different rates depending on the location in the NPS layer. The oxidation rate changes with the surface-to-volume ratio. It is known that the surface-to-volume ratio of the nanocrystallised silicon is three orders of magnitude higher than that of c-Si [23]. Accordingly, one can suppose

NPS layer etch pit poly-Si

c-Si substrate

FIG. 13. The cross-sectional SEM photograph of an NPS using high temperature poly-Si formed by the LPCVD technique.


263

that the oxidized part along a grain boundary is the nanocrystallised part, and that nanocrystallisation proceeds preferentially from the grain boundary. The existence of the etch pit further proves the penetration of the ethanoic HF solution along grain boundaries in the anodisation process. This non-uniform penetration into the polySi film may result in preferential nanocrystallisation from the grain boundaries. The reason for the difference in penetration rates of the ethanoic HF solution can be explained as follows. At the grain boundary, the potential energy is lower than that of the bulk part because the Si–Si bond network is disconnected and terminated by hydrogen. When a columnar poly-Si film is dipped in the ethanoic HF solution, the solution penetrates along grain boundaries and nanocrystallisation proceeds from the surface of each grain. As a result, nc-Si is formed at the surface of each crystal grain, while the central parts of the columnar grains are not nanocrystallised. Thus, the intermingled structure of nc-Si and bulk columnar crystal grains is formed. 4.2. Ballistic Transport Channel in the NPS Layer In order to investigate the electric current path in the NPS layer, wherein nc-Si and bulk columnar grains are intermingled, the current path profiles were measured by conductive atomic force microscopy (conductive AFM). In the conductive AFM measurement, a dc-biased conductive probe is scanned over the sample surface. The local conductivity and topography images are simultaneously obtained. The observed current can be used as a measure for the local conductivity of the sample. Figure 14a, b shows the topography and current path images of the NPS layer, respectively. The dark part in Fig. 14b corresponds to the current path. The grain size of the poly-Si is distributed in the range of 200–500 nm, which is in agreement with the SEM result shown in Fig. 13. Although a distribution of grain sizes is observed, the grains are densely formed and no bulky defects are observed. The profile of the dark part in Fig. 14b corresponds to the grain boundaries in Fig. 14a. Electric current does not pass at the centre of the bulk grains, but it passes along the nanocrystallized part formed along the grain boundaries.

FIG. 14. Measurement by conductive AFM (a) topography of the NPS layer (b) current path image.

264

KOMODA AND KOSHIDA

In order to understand the reason why electrons are not effectively injected into the bulk part, one can consider a thick oxide film formed at a bulk grain. In the case of nanometre-sized silicon, oxidation is regulated by a self-limiting mechanism [24] when the thin oxide film was formed on the surface of nc-Si. On the other hand, when oxidation proceeds in bulk silicon, a thick oxide film is formed and it is believed to prevent electron injection into the bulk silicon. In conclusion, the sample fabrication and electron emission models are shown in Fig. 15. Columnar poly-Si is deposited by LPCVD. In the anodisation process Columnar poly-Si grain Columnar poly-Si is deposited by LPCVD.

CVD

nc-Si

HF/ethanol

The ethanoic HF solution promotes preferential local dissolution at the poly-Si grain boundaries.

Anodization

h

h

O 2

Only the surface is oxidized as for nc-Si. Thick oxide film is formed on the surface of each grains.

Oxidation by RTO treatment

e -e Thin surface electrode deposition

Operation

SiO2

e -e -e -e -

e - e - Surface electrode The electrons injected from the substrate drift in the nanocrystallized part, tunnel through the surface electrode and are emitted into vacuum.

FIG. 15. A model of nanocrystallisation, oxidation by RTO treatment and operation as an electron source.


265

the ethanoic HF solution promotes preferential local dissolution at the poly-Si grain boundaries. Here, holes (h) are supplied through columnar crystal grains from the substrate. The sample is oxidized by RTO treatment. As for nc-Si, only the surface is oxidized according to the self-limiting mechanism of oxidation. However, a thick oxide film is formed on the surface of each columnar grain. Finally, thin-film top electrodes are formed on the NPS layer. When a bias is applied between the top electrode formed on top of the NPS layer and the substrate so that the top electrode is positive, the electrons injected from the substrate drift in the nanocrystallized part toward the top electrode, tunnel through the top electrode and are emitted into vacuum. 4.3. Optical Characterisation of Silicon Nanostructures To clarify the effect of the silicon nanostructure on the electron emission process, the emission properties were studied in relation to the optical and surface properties of the NPS layer [25]. Two NPS samples prepared under the same conditions were treated by RTO with two different heating rates: 90°C s−1 (sample A) and 30°C s−1 (sample B). The oxidation temperature and time were 900°C and 1 h, respectively. Then, a thin gold (Au) electrode (15 nm) was deposited onto the RTO-treated NPS layer as a top electrode. The diode current density Jd and the corresponding emission current density Je for the two samples are shown in Fig. 16 as a function of the bias voltage Vd.

FIG. 16. Electron emission current density vs. voltage curves for samples A and B. The emission current at 16 V of sample A is higher by a factor 300 than that of sample B.

266

KOMODA AND KOSHIDA

The characteristics of samples A and B are shown by closed and open symbols, respectively. In sample A, electron emission begins at about 6 V and increases rapidly with increasing Vd up to 60 μA cm−2 at 16 V. The emission efficiency η reaches 1.9% at 16 V. In sample B, on the other hand, the onset voltage Vth, Je, and η at 16 V are 9 V, 0.21 μA cm−2, and 0.01%, respectively. In addition, the slope of Je in sample B decreases with increasing Vd. Obviously, the emission performance of sample A is considerably better than that of sample B. These results suggest that in sample A the electrons injected into the NPS layer are more efficiently accelerated toward the outer surface with fewer scattering losses in comparison to the situation in sample B. To investigate the difference in the energy scattering processes between the two samples, the respective energy distributions of emitted electrons were measured. As suggested from the experimental results shown in Fig. 17, non-thermalized hot electrons are emitted ballistically. The peak energy Ep and maximum energy Emax show a shift toward the higher-energy side in fair accordance with the increase in Vd. In sample A, the value of Ep−Emax, which is a measure of scattering energy loss inside the NPS layer [26], is 2.0 eV at Vd = 14 V. This value is significantly smaller than that for sample B (3.2 eV). A comparatively large scattering loss during transport in sample B is implicated. Assuming that the only difference between the two samples is the heating rate during RTO, some effects must be induced in the PL characteristics due to differences in surface properties. The measured PL spectra for samples A

FIG. 17. Energy distribution curves of output electrons emitted from samples A and B. Note that the ballistic behaviour is more apparent in sample A, and that scattering energy losses in sample A are less than those in sample B.


267

FIG. 18. Measured PL spectra of samples A and B. In sample A, the red emission due to silicon nanocrystallites remains with a significant intensity, while it is quenched in sample B.

and B are shown in Fig. 18. Solid line and broken line show PL spectra in sample A and B, respectively. In samples A with higher electron emission efficiency, the PL spectrum consists of two emission bands: red emission due to silicon nanocrystallites [1, 2] and blue emission related to the surface oxide [27, 28]. The red PL band is the same as that observed in as-anodized NPS. It appears that the nanocrystalline silicon phase remains in sample A, oxidized at a high heating rate. In sample B, in contrast, only blue PL is observed and the peak intensity of the blue PL is much higher than that of sample A, while the red PL is almost completely quenched. It can be assumed that silicon nanocrystallites at the outer surface of the NPS layer in sample B are fully oxidized during the RTO procedure due to the slow heating rate. In fact, TEM observation shows that there are no silicon nanocrystallites in the surface region of sample B. This was further confirmed by the XPS depth profile analyses of Si, SiOx, and SiO2 signals as shown in Fig. 19. The thickness of the fully oxidized layer in sample B was about 180 nm, and the degree of oxidation is decreasing gradually to the depth direction. In the case of sample A which is oxidized at a high heating rate, silicon nanocrystallites are oxidized only in the surface region because further oxygen diffusion is suppressed by a self-limiting mechanism as described in Sect. 4.2. On the contrary, in sample B, which is processed under a slow heating rate, the silicon nanocrystallites are fully oxidized by annealing effects by diffusion of the oxygen supplied from a gaseous phase [29].

268

KOMODA AND KOSHIDA

FIG. 19. XPS depth profile analyses of Si, SiOx, and SiO2 signals.

This causes an increase of electron scattering losses and a consequent reduction in the electron emission efficiency [25]. The difference in the electron emission mode between the two samples can be seen in FN plots as well. Figure 20 shows the FN plots obtained from the emission characteristics in Fig. 16. Field-induced tunnelling is apparent in the high-voltage region for sample A. In contrast, the field effect for sample B is reduced when the voltage is increased, presumably due to field distortion along the depth direction in oxide film because of trapping effects [30, 31]. One important requirement for efficient ballistic electron emission from NPS diodes has been clarified in terms of the luminescence properties of silicon nanostructures. Appropriate combination of silicon nanocrystallites with interfacial thin oxide films promotes efficient generation of ballistic electrons and subsequent emission into vacuum. Microscopic control of the formation of interfacial oxides between interconnected silicon nanocrystallites is a key factor for enhancing the ballistic emission performance. 5. OPTIMISATION OF PROCESS AND DEVICE PARAMETERS

5.1. Low-Temperature Processing As already shown in Sect. 4, the intermingled structure of nc-Si chains, which develop perpendicular to the substrate, is formed after anodisation of columnar poly-Si deposited by a high temperature LPCVD process. Although it is presumed


269

FIG. 20. Fowler–Nordheim plots obtained from the data for samples A and B shown in Fig. 16. A distinct difference in the field effects between the two samples can be seen in the high-voltage region.

that the columnar bulk Si promotes heat dissipation of the Joule heat generated in the electron conduction of NPS layer to the substrate [32], it does not contribute to electron emission at all. In order to improve the electron emission efficiency, applying poly-Si with narrower column width might be effective. The size of the crystal grains of poly-Si is strongly affected by the deposition temperature. As the deposition temperature decreases, the grain size becomes small [33]. In order to obtain narrower crystal grains, poly-Si films were deposited by low temperature plasma enhanced CVD (PECVD) on top of a 250-nm-thick tungsten (W) electrode, which was sputtered on a glass substrate. Cross-sectional TEM observation clearly showed that the columnar grain size of the low temperature PECVD deposited poly-Si was distributed in the range of 20–50 nm, about one order of magnitude smaller than that of the LPCVD deposited poly-Si. 5.2. Analysis of Annealing Effect on Electrochemically Treated NPS by TDS In the previous section 4.3, we described that avoiding thermal damage in the oxidation process after anodisation is essential. As a low temperature oxidation process, the ECO technique was introduced to replace the RTO technique. Since ECO is a wet process performed at room temperature, oxide films can be formed without causing thermal damage to nc-Si. However, the dielectric properties of low-temperature formed oxide films are worse than those of high-temperature oxide films. In order to obtain an efficient electric field effect, the dielectric properties of the ECOoxide layer should be improved compared to those of the RTO-treated samples.

270

KOMODA AND KOSHIDA

It is well known that the H2O molecules degrade the dielectric strength of SiO2 films [34]. We can suppose that the observed poor emission stability of as-deposited ECO samples is closely related to H2O molecules incorporated in the NPS layer during processing. To improve the film quality of ECO-formed oxide films, thermal annealing effects have been studied [35]. The ECO-treated sample is annealed at a temperature of 550°C for 1 h in vacuum or in forming gas ambient (N2 including 3% H2). Annealing effects on the physicochemical properties of NPS layers are also evaluated separately by thermal desorption spectrometry (TDS). The electron emission characteristics of the fabricated diodes are measured. The stability of both the electron emission current and efficiency of the samples are compared under pulsed operation mode in which the pulse width and the duty ratio are 1 ms and 1:9, respectively. Figure 21a shows the diode current density Jd and the corresponding emission current density Je for three different samples as a function of applied voltages Vd. Plots of open circle, triangle, and square denote the Jd curves of as-ECO processed, vacuum annealed, and forming-gas annealed samples, respectively. Closed circles, triangles, and squares denote the respective Je curves. After annealing, the threshold voltage Vth defined as the onset Vd value of electron emission decreased from 7to 6 V. The electron emission efficiency η (=Je/Jd) at Vd = 14 V was improved from 0.3 to 1.0%. Although the Je values of annealed samples (closed triangles, closed squares) increase rapidly with increasing Vd, that of as-ECO samples (closed circles) tends to saturate at relatively low applied voltages. The Je of annealed samples at Vd = 14 V are over two orders of magnitude higher than that of the as-ECO sample at the same bias. Obviously post-ECO annealing is effective to improve electron emission characteristics. Both the Jd and the Je of the sample annealed in forming gas are considerably higher than those annealed in vacuum, while their emission efficiencies are comparable to each other independent of the annealing ambient. In Fig. 21b are shown Fowler–Nordheim plots obtained from the emission characteristics in Fig. 21a. In the annealed samples, field-induced tunnelling mode is seen in the low-voltage region. It should be noted that the linear behaviour appears at lower voltages. No apparent tunnelling behaviour can be seen for the as-ECO sample in the whole range of applied voltage. Post-ECO annealing makes field effect more effective on the electron transport followed by the emission. Associated with the enhancement of field effect, a desirable feature is induced in the electron emission stability. Figure 22 shows the stability of diode and emission currents of the sample annealed in vacuum. The Jd shows a gradual increase and correspondingly both the Je and η values show a gradual decrease during pulsed operation for 200 h (the duty ratio is 1:9) at Vd = 13 V. This is different from the poor stability of as-ECO sample prepared without annealing, in which the Jd increases rapidly and the corresponding Je significantly degrades within only a few minutes of operation. Two possible causes for the increase in Jd are leakage-path generation and thermal effects, which should result in an irreversible or a reversible changes of the emission characteristics, respectively. To determine which cause is the case, the sample operated for 200 h was turned off for a long period, and then the emission characteristics were measured again. According to the experimental result, no recovery from the degradation was seen in the Jd, Je, nor η values. Thus, the


271

FIG. 21. (a) The electron emission characteristics of three samples differently treated after ECO processing. Circle, triangle, and square plots denote the characteristics of as-ECO, vacuum-annealed, and forminggas-annealed samples, respectively. (b) Fowler–Nordheim plots obtained from the results of Fig. 21a.

observed continuous increase in Jd associated with a decrease in both the Je and η is presumably caused by irreversible degradation of the interfacial SiO2 films in the NPS layer. Figure 23 shows emission stability of the sample annealed in forming gas. Unlike the other two samples, the Jd in this sample is enhanced and kept almost

272

KOMODA AND KOSHIDA

FIG. 22. Time evolution of diode current, electron emission current, and efficiency for vacuum annealed sample.

FIG. 23. Time evolution of diode current, electron emission current, and efficiency for the sample annealed in forming gas. The stability of Jd, Je, and η has been significantly improved.

completely constant during pulsed operation for 200 h under the same conditions. The corresponding time evolutions of Je and η become more stable compared to those in Fig. 22. These results suggest that annealing in forming gas effectively suppresses degradation of interfacial SiO2 films, and that the transport channel for ballistic emission remains almost unchanged. To investigate the microscopic properties of the NPS layers more in detail, three samples were characterized by TDS measurements. Figure 24 shows measured TDS spectra of H2O molecules (M = 18) of each samples as a function of temperature. Three peaks are observed in as-ECO sample at around 170, 200, and 220°C, which are due to physically bonded H2O molecules in SiO2 films [36].


273

FIG. 24. Measured TDS signals of water molecules for three samples as a function of temperature.

For annealed samples, in contrast, all peak intensities of H2O molecules are significantly reduced to a similar level. Annealing in either vacuum or forming gas is very effective to remove H2O molecules. The definite difference in the emission stability between the annealed samples shown in Figs. 22 and 23, however, suggests that there might be some species relating more closely to the degradation of the emission performance besides H2O molecules. To investigate this suggestion, TDS spectra analyses were made for the three samples in terms of hydrogen related species (M = 2). Results are shown in Fig. 25. As indicated in Fig. 25, the TDS spectra of as-ECO sample and vacuum-annealed one show two peaks at around 350 and 600°C, which originate from Si–H2 and Si–H bonds, respectively [37]. In the TDS spectrum of the sample annealed in forming gas, in contrast, the peak at 350°C completely disappears. Hydrogen species of Si–H2 bonding configurations inside the SiO2 layers have been effectively evacuated by forming gas anneal, though some Si–H bonds remain there. Removing hydrogen by anneal in forming gas is desirable in order to improve the stability of electron emission. In conclusion, annealing ECO-treated NPS in forming gas is effective to improve the dielectric properties of the SiO2 layers processed at low temperature in aqueous solution, which results in improving electron emission stability. This is consistent with our ballistic transport model in which the interfacial oxides between nc-Si play a key role for multiple-tunnelling cascade. 5.3. Analysis of ECO-Treated nc-Si by TEM To clarify the ballistic emission mechanism and to improve the emission characteristics further, it is important to investigate the emission characteristics closely in relation to nanostructure in anodized poly-Si films including the interfacial oxides. Based on

274

KOMODA AND KOSHIDA

FIG. 25. Measured TDS signals of hydrogen molecules for three samples as a function of temperature.

the optical analyses of anodized nc-Si samples in terms of PL [25] shown in Sect. 4.3, direct observation of the nanostructure has been pursued by high-resolution field emission transmission electron microscopy (FE-TEM) [38]. A confirmed definite correlation between nc-Si structures and electron emission characteristics is shown in this section. Two NPS samples were prepared under the same conditions except poly-Si deposition conditions by PECVD as a base material. The devices formed on poly-Si layers deposited at RF powers of 1.8 kW and 1.4 kW are termed here as sample C and D, respectively. The cross-sectional TEM image of sample C is shown in Fig. 26a. The diameters of the columnar poly-Si grains and nc-Si were about 30 nm and 5 nm, respectively. The lattice image of nc-Si clearly appears in registry with that of the adjacent part of the poly-Si grain, suggesting that nc-Si was a part of the nearby columnar crystal grain. An amorphous-like image is also observed between each nc-Si and poly-Si grain. These results strongly indicate that during the anodisation process the ethanoic HF solution promotes preferential local dissolution at the poly-Si grain boundaries. As a result, a chain-like interconnected nc-Si structure is formed in the depth direction along the poly-Si grain boundaries. It has been confirmed from the results of pinpointed EDX measurements (Fig. 26b) that the oxidation takes place at the interface between nc-Si and poly-Si grains. From the spectrum at positions (1) and (3), signal at 0.2–0.3 eV and 1.76 eV, originate from carbon and Si, respectively, were observed. Here, signal from carbon is considered to be the effect of surface contamination. On the other hand, from the spectrum at positions (2) and (4), the signal at 0.54 eV, originates from oxygen, was also observed in addition to the above-mentioned signals, suggesting the existence of extremely thin surface oxides at nc-Si surfaces. A chain-like nc-Si structure is clearly observed in which the respective interfaces are interconnected via thin SiO2 layers.

276

KOMODA AND KOSHIDA

FIG. 26. (Continued).

columnar crystal grains are comparatively large, thick SiO2 films are formed because there is no such mechanism of self-control in providing the holes. Finally, thin-film top electrodes are formed on the NPS layer. When bias is applied between the top and bottom electrodes so that the top electrode is positive, the electrons injected from the bottom electrode drift in the NPS layer toward the top electrode, tunnel through the top electrode and are emitted into vacuum. 5.4. Existence of nc-Si and Electron Emission Characteristics The effect of the difference in microstructure, shown in the previous section 5.3, on the electron transport process is investigated. The electron emission current density (Je) and efficiency (η) of the sample C are 1.30 mA cm−2 and 2.1%, respectively at a bias of 16 V (Fig. 29a). The η value increases with increasing bias voltage.


277

FIG. 27. Cross-sectional TEM image for sample D.

Moreover, the diode current density (Jd) and the Je are one order of magnitude higher than those from the high-temperature poly-Si-based electron source shown in Fig. 16. As shown in Fig. 28, current does not flow through the remaining polySi columnar grains. Thus, the diameters of the columnar poly-Si grains should be reduced in order to increase the current flow through the diode. On the contrary, Je and η of sample D are 0.59 mA cm−2 and 0.4%, respectively, at the same bias voltage (Fig. 30a), and the η value tends to saturate at a bias voltage of about 12 V. It is apparent that the enhancement effect is small in the case of sample D. The results of FN plots calculated from Figs. 29a and 30a are shown in Figs. 29b and 30b, respectively. An enhanced field effect can be seen in sample C, where the slope in the high-field region is larger than that for sample D. Obviously an electric field effect enhanced by the existence of nc-Si improves the electron emission characteristics. Figures 31 and 32 show the operation life performance of samples C and D, respectively. Solid lines and dashed lines denote emission current density (Je) and efficiency (η), respectively. In the case of sample C, both of Je and η decreased slightly with time to about half of the initial values after 5 h operation in the dc

278

KOMODA AND KOSHIDA Columnar poly-Si grain Columnar poly-Si is deposited by PECVD.

CVD

nc-Si

HF/ethanol

The ethanoic HF solution promotes preferential local dissolution at the poly-Si grain boundaries.

Anodization

h

h

H 2SO4

SiO2 Only the surface is oxidized as for nc-Si. Thick oxide film is formed on the surface of each grains.

Oxidation by ECO treatment

h

h

e -e Thin surface electrode deposition

Operation

e -e -e -e -

e -e - Surface electrode The electrons injected from the substrate drift in the nanocrystallized part, tunnel through the surface electrode and are emitted into vacuum.

FIG. 28. A model of nanocrystallisation, oxidation by ECO treatment, and operation as an electron source.

mode. The diode current density (Jd) was almost constant. In the case of sample D, in contrast, the Je and η rapidly decreased more than one order of magnitude lower than the initial values. Whereas, the Jd increased gradually in the same period. Insufficient field effect in sample D can be linked with significant interfacial electron scattering. Induced energy losses cause an increase in trapping defects and accelerate the decrease in electron emission efficiency. The existence of oxidized nc-Si chains is a critical requirement for preventing scattering event.


279

FIG. 29. (a) J–V characteristics of sample C. (b) The corresponding F–N plot for sample C.

To confirm this hypothesis further, the nanostructure of sample C was evaluated again by TEM and EDX observation after dc operation for 20 h. Figure 33a shows the cross-sectional FE-TEM photograph of sample C after operation. A chain-like nc-Si structure along columnar poly-Si grain boundaries is observed similarly to the results of the TEM observation of the sample before operation (Fig. 26a). There are no signs of changes in sizes of neither columnar poly-Si grains nor nc-Si particles

280

KOMODA AND KOSHIDA

FIG. 30. (a) J–V characteristics of sample D. (b) The corresponding F–N plot for sample D.

even after a long-term dc operation. The results of EDX measurements (Fig. 33b) also indicate that the situation of the surface and interfacial oxidation of both nc-Si particles and poly-Si grains remains unchanged. All the original nanostructures are retained. Similarly, no significant structural changes were observed in sample D even after degradation. Appropriate arrangements of nc-Si chains and improvement


281

FIG. 31. Time evolution of Je for sample C.

FIG. 32. Time evolution of Je for sample D.

in the quality of SiO2 barriers at the interfaces of chain-like nc-Si should further enhance the efficiency and stability of ballistic emission.

6. EFFECTS OF SURFACE ELECTRODE ON ELECTRON EMISSION

6.1. Effect of UV/O3 Treatment in Electron Emission Efficiency Based on our ballistic electron conduction model, it may be considered that the electrons, which have reached the surface of the NPS layer, are hot electrons so that they easily tunnel through the surface electrode, and then are emitted into vacuum. Meanwhile, in order to improve the electron emission efficiency, it is necessary to prevent the electrons from scattering in the surface electrode. Therefore, the surface


283

FIG. 33. (Continued)

lower than that of the first material. A Cr film deposited on top of the NPS layer exhibits high adhesion and sublimation enthalpy. However, the electron emission current density decreases one order of magnitude compared to a sample with an Au surface electrode, suggesting that electron scattering in the Cr layer severely limits device performance. In order to improve the electron emission efficiency, a double-layer structure of Au/Cr was treated under ultraviolet (UV) light exposure in ozone (O3) atmosphere at 150°C. Figure 34 shows the J–V characteristics before and after the treatment. The electron emission current increased almost one order of magnitude higher compared to an untreated sample. By applying UV/O3 treatment, high electron emission characteristics, specifically adhesion and temperature durability, were obtained. There are two possible explanations for the improved electron emission current after applying UV/O3 treatment, namely, a structural changing of the double-layered structure of Au/Cr or elimination effect of organic substances (contamination) from the surface of the electrode. In order to clarify the reason for the improved electron emission current, a diode with a Pt (single layer) electrode was fabricated as a reference without

284

KOMODA AND KOSHIDA

FIG. 34. Emission current for the device with a bilayer Au/Cr surface electrode before and after UV/O3 treatment.

alloying effect. Figure 35 shows the J–V characteristics of the Pt electrode sample. The increase in electron emission current was less than that of the Au/Cr electrode sample (Fig. 34). The effect of removing organic substances on the surface turned out to be relatively small. These results strongly suggest that the electron–electron scattering probability of the Au/Cr electrode was reduced by the UV/O3 treatment. In order to investigate the structural change of the Au/Cr electrode caused by UV/O3 treatment, elemental analysis was conducted using an X-ray micro analyzer (XMA). Measurement points are shown in the Fig. 36 as (a)–(c). After UV/O3 treatment, both Au and Cr were detected from all the points of (a)–(c). The result demonstrated that Au and Cr coexisted in the same region, making the alloyed structure. 6.2. Effect of Carbon Layer on Heat Durability In employing the nc-Si-based cold cathode to an electron source for a flat panel display it must be sealed in vacuum by frit glass sealing process (typically at 420°C). First, the heat durability of the top electrode of the UV/O3-treated Au/Cr was evaluated. The top-views of the SEM photographs are shown in Fig. 37. Figure 37a shows the surface profile before heat treatment. An 8-nm-thick Au film formed a layered structure. However, after annealing at 200°C for 20 min, no electron emission was observed because Au migrated to form island structures as shown in Fig. 37b. In the sample treated at 420°C for 20 min, as shown in Fig. 37c, it turned out that each Au island was completely isolated. These results indicate that the stable operation temperature of the alloyed Au/Cr electrode was lower than 420°C.


285

FIG. 35. Emission current for the device with a Pt surface electrode before and after UV/O3 treatment.

In order to suppress the aggregation of Au, the effect of a carbon layer was investigated. Figure 38 shows SEM photographs of a multi-layered electrode of Au(8 nm)/Cr(2 nm)/C(1 nm) pre- and post-heat treatment. The Au in the sample without heat treatment formed a layered structure as shown in Fig. 38a. Figure 38b shows the surface of the heat-treated sample after 20 min at 420°C. The J–V characteristics of the sample with Au/Cr/C electrode are shown in Fig. 39. No change in the electron emission characteristics was observed after heat treatment. The application of 1-nm-thick carbon layer improved the heat durability of the nc-Si based cold cathode up to at least 420°C. The improved heat durability was demonstrated by fabricating frit glass sealed samples. The cold cathode was vacuum-sealed with a phosphor-coated face plate. Figure 40 shows the luminous pattern on phosphor on face plates of the samples with and without frit glass sealing at 420°C for 10 min using Au/Cr/C electrode. The part, which appeared black in the right-hand-side figure is the frame glass sealed with frit glass. The size of the luminous pattern corresponding to the region, which the electron flux reached is about 1 mm2. This is considered to be an excellent result, a foresight for a promising commercialisation of such devices.

7. FABRICATED BSD MODEL

Figure 41 shows schematic cross-sectional structure of the vacuum encapsulated BSD model. A matrix BSD was directly fabricated on a thin TFT or PDP glass substrate as a base plate. Supporting glass plate of 2.8-mm thick was attached to the

FIG. 37. Agglomeration of Au/Cr electrode films caused by annealing.

FIG. 38. Mitigation of the thermal agglomeration problem by using a Au/Cr/C electrode structure.

FIG. 39. Improved heat durability by using Au/Cr/C surface electrode.

FIG. 40. Light emission pattern before and after frit sealing for the device using a Au/Cr/C electrode structure.

FIG. 41. Schematic cross section of the vacuum encapsulated BSD model.

FIG. 42. Perspective view of the fabricated BSD base plate.

290

KOMODA AND KOSHIDA

FIG. 43. Perspective view of the fabricated 7.6–in. diagonal prototype model.

electrode of the BSD and anode voltage of 5 kV was applied between ITO of the faceplate and the surface electrode of the BSD. Figure 42 shows the fabricated BSD base plate. It was fabricated on the glass substrate and the size of it was 200 × 200 mm. Figure 43 shows perspective view of the encapsulated 7.6-in. diagonal prototype model. Base plate shown in Fig. 42 and the faceplate were successfully combined and encapsulated in a vacuum with simple structure of cathode plate and faceplate shown in Fig. 41. Active pixel area shown in Fig. 43 is 154 × 116 mm2.

8. CONCLUSIONS

A prototype 7.6-in. diagonal BSD model was successfully fabricated with a low temperature process on TFT or PDP glass substrates. Excellent electron emission characteristics such as emission current density, efficiency of the emission current, and stable emission characteristics under low vacuum, which are comparable to 2.6-in. diagonal BSD model proposed earlier, were clearly observed. Electron emission mechanism was carefully investigated using time-of-flight analysis and we discovered the mean free path of the electron in the NPS system exceeds 1.5 μm. Consequently, BSD provides a promising possibility to realize large size FPDs for the near future. Acknowledgments The authors would like to thank the colleagues of the Advanced Technology Research Laboratory at Matsushita Electric Works, Ltd. and the Tokyo University of Agriculture and Technology for their useful discussion and sample measurement support. Also, the authors would like to thank various companies for their effort to development of the materials and equipments for BSD technology.


291

REFERENCES 1. L.T. Canham, Appl. Phys. Lett. 57, 1046 (1990). 2. N. Koshida and H. Koyama, Jpn. J. Appl. Phys. 30, L1221 (1991). 3. Y.H. Xie, W.L. Wilson, F.M. Ross, J.A. Mucha, E.A. Fitzgerald, J.M. Macaulay and T.D. Harris, J. Appl. Phys. 71, 2403 (1992). 4. B. Gelloz and N. Koshida, Jpn. J. Appl. Phys. 43, 1981 (2004). 5. N. Koshida, T. Ozaki, X. Sheng and H. Koyama, Jpn. J. Appl. Phys., Part 2 34, L705 (1995). 6. C.A. Spindt, J. Appl. Phys. 39, 3504 (1968). 7. M. Suzuki, T. Kusunoki, H. Shinada and T. Yaguchi, J. Vac. Sci. Technol. B 13, 2201 (1995). 8. T. Komoda, X. Sheng and N. Koshida, Mat. Res. Soc. Symp. Proc. 509, 187 (1998). 9. T. Komoda, X. Sheng and N. Koshida, J. Vac. Sci. Technol. B 17, 1076 (1999). 10. T. Komoda, Y. Honda, T. Hatai, Y. Watabe, T. Ichihara, K. Aizawa, Y. Kondo and N. Koshida, IDW’99, Technical Digest FED3-2, 939 (1999). 11. T. Komoda, Y. Honda, T. Hatai, Y. Watabe, T. Ichihara, K. Aizawa, Y. Kondo and N. Koshida, SID’00, Digest of Technical Papers 28.4, 428 (2000). 12. T. Komoda, Y. Honda, T. Hatai, Y. Watabe, T. Ichihara, K. Aizawa and N. Koshida, SID’01, Digest of Technical Papers 14.1(Invited), 188 (2001). 13. T. Komoda, Y. Honda, T. Ichihara, T. Hatai, T. Takegawa, Y. Watabe, K. Aizawa, V. Vezin and N. Koshida, SID’02, Digest of Technical Papers 39.3, 1128 (2002). 14. T. Ichihara, Y. Honda, K. Aizawa, T. Komoda and N. Koshida, J. Cryst. Growth, 237, 1915 (2002). 15. T. Ichihara, Y. Honda, T. Baba, Y. Takegawa, T. Watabe, T. Hatai, K. Aizawa, T. Komoda, V. Vezin and N. Koshida, IDW’02, Technical Digest FED1–4, 1033 (2002). 16. C.A. Spindt, C.E. Holland, A. Rosengreen and I. Brodie, J. Vac. Sci. Technol. B 11, 468 (1993). 17. H. B. Michaelson, J. Appl. Phys. 48, 4729 (1977). 18. R. Sedlacik, F. Karel, J. Oswald, A. Fejfa, I. Pelant and J. Kocka, Thin Solid Films 255, 269 (1995). 19. T. Matsukawa, S. Kanemaru, M. Nagao and J. Itoh, IDW’99, Technical Digest FED3–3, 943 (1999). 20. A. Kojima and N. Koshida, Jpn. J. Appl. Phys. 42, 2395 (2003). 21. N. Koshida, X. Sheng and T. Komoda, Appl. Surf. Sci. 146, 371 (1999). 22. X. Sheng, A. Kojima, T. Komoda and N. Koshida, J. Vac. Sci. Technol. B 19, 64 (2001). 23. L. E. Brus, P. F. Szajowski, W. L. Wilson, T. D. Wilson, T. D. Harris, S. Schuppler and P. H. Citrin, J. Am. Chem. Soc. 117, 2915 (1995). 24. H. Fukuda, J. L. Hoyt, M. A. McCord and R. F. W. Pease, Appl. Phys. Lett. 70, 333 (1997). 25. T. Ichihara, T. Hatai, K. Aizawa, T. Komoda and N. Koshida, J. Vac. Sci. Technol. B 22, 57 (2004). 26. S. Uno, K. Nakazato, S. Yamaguchi, A. Kojima, N. Koshida and H. Mizuta, IEEE Trans. Nanotechnol. 1, 1 (2003). 27. A. J. Kontkiewicz, A. M. Kontkiewicz, J. Siejka, S. Sen, G. Nowak, A. M. Hoff, P. Sakthivel, K. Ahmed, P. Mukherjee, S. Witanachchi and J. Lagowski, Appl. Phys. Lett. 65, 1436 (1994). 28. D. I. Kovalev, I. D. Yaroshetzkii, T. Muschik, V. Petrova-Koch and F. Koch, Appl. Phys. Lett. 64, 214 (1994). 29. B. E. Deal and A. S. Grove, J. Appl. Phys. 36, 3770 (1965). 30. N. Xu, J. Chen and S. Deng, Appl. Phys. Lett. 76, 2463 (2000). 31. Y. Lau, Y. Liu and R. Parker, Phys. Plasmas, 1, 2082 (1994). 32. T. Komoda, X. Sheng and N. Koshida, J. Vac. Sci. Technol. B 17, 1076 (1999). 33. A. C. Adams, VLSI Technology, ed. S. M. Sze, p. 103 (McGraw Hill, New York, NY, 1983). 34. E. H. Nicollian, C. N. Berglund, P. F. Schmidt and J. M. Andrews, J. Appl. Phys. 42, 5654 (1971). 35. T. Ichihara, Y. Honda, T. Baba, T. Komoda and N. Koshida, J. Vac. Sci. Technol. B 22, 1784 (2004). 36. H. Okumura and T. Takahagi, TRC News 49, 30 (1994) (in Japanese). 37. D.K. Biegelsen, R.A. Street, C.C. Tsai and J.C. Knights, Phys. Rev. B 20, 4839 (1979). 38. T. Ichihara, T. Baba, T. Komoda and N. Koshida, J. Vac. Sci. Technol. B 22, 1372 (2004). 39. M. Cardona and L. Ley, Photoemission in Solids 1 (Springer, Berlin, 1978).

10 Porous Silicon Optical Label-Free Biosensors Philippe M. Fauchet Abstract Because of its large internal surface area, porous silicon (PSi) is an attractive material for chemical and biological sensing applications. This chapter describes label-free optical biosensors consisting of PSi photonic bandgap structures. After a brief review of the material science and key properties of PSi, the design, fabrication, and sensitivity of various PSi photonic bandgap structures is discussed. The properties of one type of these structures, namely PSi microcavities, are discussed in detail. The sensitivity of these structures is then verified experimentally via the detection of a single monolayer of silane and glutaraldehyde. Examples of biosensing are then discussed. They include the detection of DNA segments, Gram negative bacteria, IgG, and pathogenic E. coli.

1. BACKGROUND

1.1. The Need for Label-Free Biosensors Technology for early detection and recognition of biological substances is urgently needed in many fields such as food safety, environmental protection, drug delivery, and medical diagnostics. Labeling methods are the major technique in biological research protocols and molecule detection technology. They typically involve radioisotopes or the use of molecular tags conjugated to one or several interacting molecules. For example, the “gene chip” systems based on fluorescent labeling are now used daily in hundreds of biomedical research labs throughout the world [1]. However, molecular tagging has drawbacks such as chemical modification in the assay and inability to acquire continuous recording of binding events. In addition it is labor intensive. Label-free methods have received considerable attention lately because of their ease of sample preparation. The development and applications of label-free biosensors have been pursued with great interest by researchers. Various label-free University of Rochester, Rochester, New York, USA, fauchet@ece rochester.edu


293

294

FAUCHET

biosensors that do not use the traditional fluorescence and radioactivity labeling methods have been developed to provide quick and simple methods for biomolecular detection by converting the molecular recognition events into easily detectable optical [2, 3], electrical [4, 5], calorimetric [6], or acoustic [7] signals. A typical label-free biosensor can be generally defined as a device that consists of a biological recognition system (bioreceptor) and a transducer that can measure the effect generated by interaction of the analyte with the bioreceptor. Figure 1 illustrates the conceptual principle of the biosensing process. Biosensors can be classified by either their bioreceptors or their transducers type. Bioreceptors are biological molecular species or living biological systems that utilize biochemical mechanisms for recognition. They are the key to specificity for biosensor technologies. Numerous forms of bioreceptors can be used. On the basis of the bioreceptor type, biosensors generally can be classified into the following categories [8]: Nucleic acid/DNA, antibody/antigent, enzyme and cells. On the basis of the transducer type, biosensors generally can be classified as: Optical sensors (i.e., luminescence, reflectance, absorption, surface plasmon resonance, etc.), electrical and electrochemical sensors and mass-sensitive sensors (i.e., surface acoustic wave, microbalance, etc.) New types of transducers are still constantly being developed for use in biosensors. Among all the transducer classes, optical detection offers the largest number of possible subcategories. This is because optical biosensors can be used for many different types of spectroscopy such as absorption, fluorescence, Raman, SERS, refraction, dispersion, etc. The properties of light that can be measured include amplitude, energy, polarization, phase, etc. Each sensing technology has

Analyte

Recognition system

Transducer

Signal (light, current, frequency) FIG. 1. A biosensor consists of a recognition system and a transducer.

10. POROUS SILICON OPTICAL LABEL-FREE BIOSENSORS

295

its own benefits and drawbacks. Sensitivity, selectivity, response time, ease of integration, and cost are all factors in determining the most suitable device for each specific application. 1.2. Material Science of Porous Silicon Porous silicon (PSi) is a form of silicon with unique properties, distinct from those of crystalline, microcrystalline, or amorphous silicon. It was first prepared in 1956 [9] and much later was identified as etched silicon [10]. A strong research focus into porous silicon properties and applications began only after Canham’s report of visible photoluminescence in 1990 [11]. For more than a decade, porous silicon has been investigated as the basis for devices such as LEDs [12], filters [13], waveguides [14], and sensors [15]. Applications of porous silicon in biosensing have attracted great attention over the past several years because of its large surface area (ranging from a few to hundreds of square meters per gram) and the wide range of morphologies [16]. Furthermore, advances in techniques for chemical functionalization of porous silicon have increased the stability of the material and allowed the immobilization of organic molecules, such as bioreceptors, to silicon via stable, covalent bonds [17]. In general, porous silicon can be classified into three categories based on the pore diameter: (1) Microporous silicon with pore diameters and pore-to-pore distances smaller than 10 nm; (2) Mesoporous silicon with pores in the 10–50 nm range; (3) Macroporous silicon with pores larger than 50 nm. The morphology of porous silicon is important in sensing applications, because the pore diameter limits the size of the species that can be captured. Figure 2 shows the top view SEM images of typical microporous, mesoporous, and macroporous silicon samples. The most common fabrication technique to produce PSi is electrochemical etching of a crystalline silicon wafer in a hydrofluoric (HF) acid-based solution [22]. The dissolution of silicon requires the presence of fluorine ions (F−) and holes (h+). The pore initiation and growth mechanisms are qualitatively understood. Pore growth can be explained by several models, each one of which is more relevant in a specific regime of porosity and pore size [23–25]. If the silicon/electrolyte interface becomes irregular shortly after etching starts, the surface fluctuations of the silicon/electrolyte interface may either grow (PSi formation) or disappear (electropolishing). A depletion region is formed in the thin porous silicon layer itself and also in a region of the Si wafer near the PSi/c-Si interface. In forward bias for p-type substrates, the holes Micropores

50 nm

Mesopores

40 nm

Macropores

Macropores

200nm

2 mm

FIG. 2. Top view SEM images of typical micropores (50 nm) [20, 21]. Each morphology was obtained using different fabrication conditions such as wafer doping type and level.

296

FAUCHET

Hydrofluoric Acid

F

F

FF-

F-

F-

F-

F

FF-

FF+ ++

FF-

+ + + + +

FF+ +

++

FF+ ++ +

++ + +

Crystalline Silicon

++

FIG. 3. Porous silicon formation. Etching occurs only at the pore tips where the holes (h+) are focused by the electric field.

can still reach the silicon/electrolyte interface as the electric field lines are focused at the tip of the pores. Thus, holes will preferentially reach the silicon/electrolyte interface deep in the pores, where etching will proceed rapidly (Fig. 3). In contrast, no holes will reach the end of the silicon rods, effectively stopping the etching there. In addition, if this electrostatic effect is not strong enough, the random walk of the holes toward the silicon/electrolyte interface makes it more likely that they reach it at or near the pore’s tip, resulting in an effect similar to the electrostatic one. When an n-type substrate is used, porous silicon formation takes place in reverse bias since holes are required for etching to proceed. Another important mechanism becomes predominant if the silicon rods are narrow enough (typically much less than 10 nm). In this size regime, the electronic states start to differ from those of bulk silicon. When the motion of carriers is restricted in one or more dimensions, the holes in the valence band are pushed to lower energy by quantum confinement, which produces a potential barrier to hole transport from the wafer to the silicon rods. The holes can no longer drift or diffuse into the silicon rods and further etching stops. The electrochemical process allows for precise control of the structural properties of porous silicon such as thickness of the porous layer, porosity, and average pore diameter. Pore formation occurs when the fluorine ions are delivered faster than the holes, the inter-pore regions of porous silicon are depleted of holes, and further etching occurs only at the pore tips. When the current density decreases, the number of holes at the pore tips drops, which leads to smaller pore sizes. Thus the porosity (defined as the percentage of void space in the material) can be precisely controlled by the etching current density [22, 25]. The thickness of a porous silicon layer is linearly related to the etching time. In practice, maintaining a constant HF concentration at the tip of very deep pores is very difficult [26], which may lead to


297

Mesoporous silicon multilayer

Meso-Macroporous silicon multilayer

Macroporous silicon multilayer

2 μm

500 nm

20 mm

FIG. 4. Cross-sectional SEM images of mesoporous and macroporous silicon multilayer structures [19, 20, 28]. Layers with different morphology/pore size were formed by modulating the etching current density.

a change in the layers properties. Thus, there is a limitation of the maximum thickness that can be etched. One unique property of porous silicon is that multilayer structures with different porosities can be formed on the same substrate simply by modulating the etching current density. This is because silicon dissolution occurs preferentially at the bulk crystalline silicon/electrolyte interface, which is the pore tip [27]. The SEM images of porous silicon multilayer structures in Fig. 4 shows their periodic morphology in depth. This property of porous silicon makes it possible to form complex optical devices such as mirrors, waveguides, and photonic crystals. 1.3. Porous Silicon for Label-Free Biosensing: Principle, Advantages, and Achievement The high surface area, wide range of morphology, ease of fabrication, and ability for easy integration make porous silicon an ideal host for sensing applications. Porous silicon sensors based on several different transductions have been investigated including interferometric-based, photoluminescence-based, and electricalbased transduction [15]. The most extensively developed and most robust transduction of a porous silicon sensor is the interferometric method. It has a simple and well understood sensing principle. Our understanding of the other two transductions is still not complete, which limits the use of the sensors. In this section, only the interferometric sensing method is discussed. The interferometric transduction is based on the optical thickness of a structure. The optical thickness is defined as the product of the refractive index (n) and the physical thickness (L) of the structure. The effective refractive index of a porous silicon layer nPSi = e PSi can be related to its porosity by the Bruggeman effective medium model [29]: (1 − P )

e si − e PSi e − e PSi + P void =0 e si + 2e PSi e void + 2e PSi

(1)

where P is porosity, esi is the dielectric constant of silicon, ePSi is the effective dielectric constant of porous silicon, and evoid is the dielectric constant of the medium

298

FAUCHET

inside the pores. The Bruggeman effective medium model shows that the effective refractive index of the porous structure increases as the porosity decreases, and the dielectric constant of the medium inside the pores evoid increases. In porous silicon sensing applications, when biological objects are infiltrated into the pores, evoid is increased due to the binding of the objects to the internal surface of the pores. Thus, ePSi, the overall effective dielectric constant of the porous structure is increased. As shown in Fig. 5, for a given increase of evoid, the effective refractive index change is larger for higher porosity layers. The reflectance spectra of porous silicon structures (single layer or multilayer) are determined by the effective optical thickness of the entire structure. As ePSi increases, the effective optical thickness of the structure increases, and a red shift in the optical reflectance spectrum of the structure can be detected. Thus, by monitoring the optical spectra of the sensors, one can detect the capture of other species inside the pores. To selectively detect targets of interest, the internal surface of porous silicon needs to be functionalized. Highly selective elements, such as DNA segments and antibodies, can be immobilized on the internal surface of the pores as the bioreceptors or probe molecules. When the sensors are exposed to the target, the probe molecules selectively capture the target molecules. The molecular recognition events are then converted into optical signals via the increase of the refractive index. The first chemical sensor that utilized the interferometric transduction involved a single layer thin film [30]. The exposure of silicon-hydride terminated surfaces to solvent vapors led to a reversible shift in the fringe patterns. A few years later, porous silicon single layer sensors capable of detecting biomolecular interactions (DNA–cDNA, Protein A–human IgG) were demonstrated [31, 32]. The internal surface of porous silicon was functionalized with DNA or proteins for the molecular recognition. However, the method used to create macropores for sensing large

4 n-void =1

3.5

n-void =1.3

neff

3 2.5 2 1.5 1 0

20

40 60 Porosity (%)

80

100

FIG. 5. Effective refractive index of porous silicon as a function of the porosity at the wavelength of 800 nm. The black curve corresponds to nvoid = 1 and the grey curve to nvoid = 1.3.


299

size molecules has been problematic [33]. Most of the sensors reported were then based on mesoporous silicon. Complex mesoporous silicon device such as photonic bandgap microcavities, rugate filters were also employed for sensitive detection of DNA [34, 35], bacteria [36], and chemicals [37, 38]. Lately, a new type of macroporous silicon morphology was reported and macroporous silicon photonic bandgap microcavity sensors were demonstrated for large size molecules detection [20]. Porous silicon thin films can also be released from the silicon substrate. Sensors based on freestanding porous silicon membranes have been investigated and used for in vivo applications such as a “smart bandage” [39] and “smart dust” [40]. For photoluminescence-based and electrical-based transduction, interesting results have been reported by several groups. It was observed that the photoluminescence emission from mesoporous silicon is quenched upon exposure to certain solvent vapors and gases [41–43]. Quenching of the photoluminescence may be due to the binding of gas or vapor molecules to a surface site on the nanocrystalline silicon. The reversible quenching can be quantified to measure the concentration of the gaseous analyte of interest and may serve as an optical sensor. Large percentage changes in photoluminescence intensity were also observed with porous silicon sensors functionalized with antibodies, which is capable of binding to human myoglobin [44]. However, the change of photoluminescence intensity was not observed with other porous silicon biological sensors, such as DNA and lipid sensors [35, 36]. Porous silicon electrical and electrochemical sensors have also been demonstrated for chemical and biological sensing applications. These sensors carried out a deposition step to fill the pores with metallic [45], dielectric or semiconducting oxide [4, 46], enzyme [47] or molecular receptor films [5, 48]. Porous silicon served as the basis structure for sensors capable of detecting gas, metal ions, humidity, chemicals, and biological molecules. 2. POROUS SILICON PHOTONIC BANDGAP STRUCTURE BIOSENSORS: DESIGN AND FABRICATION

2.1. Introduction to Photonic Bandgap Structures Photonic band gaps were first predicted in 1987 by two physicists, Eli Yablonovitch then at Bell Communications Research and Sajeev John then at Princeton University. In semiconductors, the periodic arrangement of ions on a lattice gives rise to the energy band structure, which controls the motion of charge carriers through the crystal. Similarly, photonic bandgap (PBG) structures are periodic dielectric structures that control the propagation of electromagnetic waves through the photonic crystal. The interaction between the photons and the refractive index contrast results in a range of allowed energies and a band structure characterized by photonic band gap. A band gap forms when the photon wavelength is comparable to the periodicity of the dielectric structures. Figure 6 illustrates the 1D, 2D, and 3D photonic crystal structures. The interest in these artificial photonic bandgap structures has been growing tremendously because of the deep implications from both a fundamental and a


a

Incident light

301

Reflected light n=air

b

nH= high index

1

nL= low index nH= high index nL= low index ns= substrate

Reflectivity

nL= low index nH= high index

1.2

0.8 0.6 0.4 0.2 0 0.6

0.7

0.8 0.9 1 Wavelength (nm)

1.1

FIG. 7. (a) A Bragg mirror consists of a multilayer-stack of alternate high and low-index films. A part of the incident beam is reflected at every interface in the stack. All reflected beams interfere constructively if the optical thickness of each layer is designed properly. (b) Simulated reflectance spectrum of a Bragg mirror. The stopband of high reflectance is centered at the wavelength satisfying the Bragg condition.

If the relative phase difference of all reflected beams is 0° or a multiple of 360°, constructive interference occurs [57]. As shown in Fig. 7, the reflectance spectrum of a Bragg mirror is characterized by a stopband. The reflectance and the full width half maximum (FWHM) of the stopband of the Bragg mirror are determined by the refractive index contrast (or porosity contrast) between mirror layers and the number of periods of the stack. The reflectivity of the Bragg mirror increases with the number of periods. The stopband also becomes sharper as the number of periods in the Bragg mirrors is increased. The practical limits to form a porous silicon Bragg mirror are the porosity contrast that can be achieved in a given wafer substrate and the number of periods that can be formed. The longer the etch proceeds, the more likely the etch rate will change and a porosity gradient will appear. 2.2.2. Microcavity A microcavity consists of two Bragg mirrors (top and bottom) and one of several half-wavelength optical thickness “defect” layer that breaks the periodicity. As a result, light reflecting from the top Bragg mirror destructively interferes with the light reflecting from the bottom mirror at the center wavelength. This wavelength is also called the resonance wavelength for which there is low reflectance (high transmission). Hence, a microcavity is a one-dimensional PBG structure with a defect that introduces an allowed mode into the photonic bandgap. Figure 8 is the schematic drawing of a microcavity and its reflectance spectrum. l The quality factor (Q-factor) of a microcavity is defined as Q = , where l Δl is the resonant wavelength and Δl is the full width half maximum of the resonance.

302

FAUCHET

b 1.2

a

1 Reflectivity

Bragg mirror

Defect layer

Bragg mirror

0.8 0.6 0.4 0.2 0 0.6

Si high index

low index

0.7 0.8 0.9 1 Wavelength (mm)

1.1

FIG. 8. Microcavity structure with two Bragg mirrors sandwiching a half-wave length optical thickness defect layer. The Bragg mirrors consist of alternating layers of high and low refractive index quarterwave length optical thickness layers. (b) Calculated reflectance spectrum of microcavity. The defect layer introduces a narrow resonance in the middle of the high reflectance stopband.

The higher the Q value, the sharper the resonant dip and the more efficiently light is confined inside the cavity. Q increases as the reflectivity of the Bragg mirrors increase. 2.2.3. Rugate Filter Rugate filters are structures in which the refractive index varies sinusoidally. These arrangements also show bandgaps, which are slightly narrower than the bandwidth of a Bragg mirror. To produce a stop band centered at l0 one has to use a sinusoidal index profile of the following form: n(t ) = n0 +

⎛ 4pt ⎞ Δn sin ⎜ , 2 ⎝ l0 ⎟⎠

(2)

where t is the optical path, n0 is the average of the high and low indices, and Δn is the index contrast. Figure 9 is the schematic drawing of a rugate filter with a center wavelength of 800 nm and its simulated reflectance spectrum. The reflectance spectrum is characterized by a stopband with very small sidelobes. The FWHM of the stopband increases and the reflectivity are determined by the total thickness of the rugate filter and the porosity contrast in a similar way as Bragg mirrors. 2.3. Sensitivity of Porous Silicon Optical Sensors 2.3.1. Sensitivity Definition Sensitivity is one of the most important issues to evaluate the performance of the sensors. However in the literature, the sensitivity of the sensors is often reported in terms of molarity [58], grams/area [59], cells/milliliter [60], grams/milliliter [61], etc. The variety in reporting detection limits are due to the different sensing nature of the sensors or different applications. However, this inconsistency sometimes does make the comparative evaluation difficult.


a

b

303

1.2

Reflectivity

1

Rugate filter

0.8 0.6 0.4 0.2

Si

0 0.6

0.7

0.8

0.9

1

1.1

Wavelength (mm) FIG. 9. A rugate filter with refractive index varying sinusoidally in depth. (b) Simulated reflectance spectrum of a rugate filter with maximum and minimum porosity of 80% and 60%, total thickness of 4 μm. The reflectance spectrum is characterized by a stopband with very small sidelobes.

b Reflectivity

a

neff

neff + Δneff

0.8 npore = 1 0.7 npore = 1.03 0.6 0.5 0.4 0.3 0.2 0.1 0 0.6 0.7 0.8 0.9 1 1.1 1.2 Wavelength (μm)

FIG. 10. (a) Single layer porous silicon Fabry-Perot interferometer sensor. When the pores are infiltrated with other materials, the effective refractive index of the porous silicon layer increases from neff to neff+ Δneff. (b) Simulation of the reflectance spectrum of the structure in (a). The blue curve is the spectrum of the porous silicon layer with 70% porosity, 2.5 μm thickness and npore = 1. The red curve is the reflectance spectrum of the porous silicon layer when npore = 1.03. A red shift can be detected in the reflectance spectrum as the effective refractive index of the porous silicon layer increases.

The most wildly accepted figure of merit describing the sensitivity of the affinity sensors is Δl/Δn, where Δl is the wavelength shift and Δn is the change of the ambient refractive index. For a detection system capable of resolving a given wavelength shift, Δl/Δn indicates the minimum detectable index change of the device. In this section, Δl/Δn is used in the discussion of the ultimate sensitivity of the PSi sensors. 2.3.2. Porous Silicon Single Layer Biosensor The first porous silicon affinity biosensor reported was a single layer Fabry-Perot interferometer [62]. As shown in Fig. 10a, light reflected from the top interface (air-PSi) and the bottom interface (PSi-Si substrate) interfere with each other and

304

FAUCHET

form the typical Fabry-perot fringes in the reflectance spectrum. The peak position of the fringes are determined by the following equation: ml = 2 neff d ,

(3)

where m is an integer, l is the peak wavelength, neff is the effective index of the layer and d is the thickness of the layer. When the effective refractive index of this layer increases by Δneff (as a result of infiltration other materials into the pores), l shifts to a longer wavelength. The sensitivity of a porous silicon sensor is defined as Δl/Δnpore, where Δnpore is the change of refractive index of the pores. Δnpore can be related to Δneff through (1). For a porous silicon layer with 70% porosity and a measurement wavelength of 800 nm, the sensitivity of the sensor Δl/Δnpore ~430. The thickness of the layer determines the sharpness of the fringes. Increasing the thickness of the layer increases the sharpness of the fringes. With sharper fringes, it should be possible to resolve a smaller shift of the spectrum. However, thicker layers require a larger amount reagent to reach the same Δnpore. Furthermore, uniform infiltration of the reagent through out the entire layer is more difficult for thicker layers. 2.3.3. Rugate Filter Biosensor For complicated structures, such as one-dimensional photonic bandgap structures, increasing the effective refractive index of the structure will also cause a red shift of the spectrum. For a rugate filter with center wavelength at 800 nm, highest porosity of 80%, lowest porosity of 60%, and total thickness of 4 μm, simulation shows that the sensitivity of the sensor Δl/Δnpore ~ 450 (Fig. 11). Similar to single layer 1.2 1

npore = 1

npore = 1.03

Reflectivity

0.8 0.6 0.4 0.2 0 0.6

0.7

0.8 0.9 Wavelength (μm)

1

1.1

FIG. 11. Reflectance spectra of a rugate filter with 80%–60% porosity and 4 μm thickness. The blue curve is the reflectance spectrum with npore = 1; the red curve is the reflectance spectrum with the npore = 1.03. When the effective index of the structure increases, the stopband shifts to longer wavelength.


305

sensor, the sensitivity of the rugate filter is independent on the structure thickness. A thicker rugate filter leads to a sharper stopband, which increases the ability of the sensor to resolve small shift in the spectrum, thus increase the sensor sensitivity. However, uniform infiltration of the reagent through out the entire layer is more challenging for thicker layers. 2.3.4. Microcavity Biosensor A microcavity is a PBG structure with a defect that introduces a sharp resonant dip into the reflectance spectrum stop band. The entire reflectance spectrum of a microcavity also depends on the effective refractive index of the entire structure. Simulations show that the sensitivity of a microcavity with 6-period Bragg mirrors (80% and 60% porosity) and a resonant wavelength at 800 nm is Δl/Δnpore~ 480 (Fig. 12). 2.4. Advantages of Porous Silicon PBG Microcavity Structures in Sensing Applications Simulations show that as the refractive index of the pores (npore) increases from 1.00 to 1.03, red shift of approximately 14 nm is observed at 800 nm in all three cases described above. Thus, in the ideal case, the performance of the sensors with different configurations is the same. However, in practice, the microcavities have several advantages over single PSi layers and rugate filters. First, it is much easier to resolve a small shift in the spectrum of a microcavity, because of the sharp resonance dip. In another words, a microcavity sensor requires less refractive index change in the pores than a single layer and a rugate filter to produce a detectable optical shift. In the presence of noise, a small shift in the optical

1.2 1

Reflectivity

0.8 npore = 1

npore = 1.03

0.6 0.4 0.2 0 0.6

0.7

0.8

0.9

1

1.1

Wavelength (μm) FIG. 12. Simulated reflectance spectra of a microcavity with 6-period Bragg mirrors (80% and 60% porosity). The blue curve is the spectrum with npore = 1 and the red curve is the spectrum with npore = 1.03.

306 0.6

b

0.4 0.3 0.2 0.1 0 0.6 0.7 0.8 0.9 1 1.1 1.2 Wavelength (μm)

c

1.2 1

Reflectivity

Reflectivity

0.5

1.2 1

Reflectivity

a

FAUCHET

0.8 0.6 0.4 0.2

0.8 0.6 0.4 0.2

0

0 0.6

0.7 0.8 0.9 Wavelength (μm)

1

0.6

0.7 0.8 0.9 Wavelength (μm)

1

FIG. 13. Simulations of reflectance spectra of (a) single layer, (b) rugate filter and (c) microcavity with (red curve) and without (blue curve) a thin layer on the top of the structure. The position of the resonance is not affected by the refractive index changes on the top of the microcavity.

spectrum is easier to detect for a microcavity than a single layer and a rugate filter, because the microcavity spectrum has a sharp resonance. Thus a microcavity is a more sensitive platform. Second, for biosensing applications, the sensor needs to operate in complex environments. Simulations show that a thin layer of material covering the single PSi layer and rugate filter will cause a red shift in the spectrum similar to that caused by a change of refractive index inside the pores (Fig. 13). However for a microcavity, a thin layer on top of the structure only causes changes to the side lobes in the spectrum but not to the resonance dip. This property makes microcavity sensors more reliable and enables the sensors to perform in “dirty” environments. 2.5. Design of Porous Silicon 1-D PBG Microcavity Biosensors The optical spectrum of the microcavity is strongly influenced by the device configuration such as the Bragg mirror periods, porosity contrast, etc. [63, 64]. This section examines how the Q-factor and the pore size affect the sensitivity and how to design a sensor for optimum performance. 2.5.1. Q-Factor The Q-factor of a microcavity is used to evaluate how effectively light is confined within a PBG structure. The larger the Q, the more efficiently light is confined inside the cavity. In sensing applications where the shift of the spectrum is monitored, increasing the Q of the microcavity will increase the ability to resolve a small wavelength shift. Thus, the Q of the sensor should be as high as possible to increase the sensitivity. The highest Q reported in a PSi 1-D microcavity is ~8,000 [65]. The Q value is related to the number of periods of the Bragg mirrors and the refractive index contrast between the layers. Figure 14 shows the simulated Q values for PSi microcavities with different porosities and different numbers of periods in the Bragg mirror. It can be seen from Fig. 14 that for higher porosity contrasts and thicker Bragg mirrors, larger Q values can be obtained. Although a larger Q value will increase the sensitivity of the sensor, there are limitations that need to be considered when designing a microcavity. The porosity


307

9000 80% vs. 50% 8000

80% vs. 60% 80% vs. 70%

7000 6000

Q

5000 4000 3000 2000 1000 0 3

5 7 Periods of Bragg mirror

9

FIG. 14. Simulation of Q values of 1-D PBG microcavities with different porosities and different number of periods.

j1= 40mA/cm2 j2= 30mA/cm2

a


b


c

FIG. 15. Cross sectional SEM images of two layers PSi structures formed using different current densities. The top layers of each sample were etched with a current density of 40 mA cm−2. The bottom layers were formed with different current densities ranging from 30 to 10 mA cm−2. The pore size decreases as the current density decreases.

is controlled by the etching current density. A lower current density results in a lower porosity corresponding to smaller pores (Fig. 15) [20, 66]. Smaller pores may not be favorable for biosensing applications when the size of the target is comparable to the pore size. Thus the highest Q value is limited by the maximum porosity contrast. In practice, the number of periods of the Bragg mirror cannot be increased arbitrarily because uniform infiltration of the molecules becomes more difficult for thicker devices. In particular, using a thick top Bragg mirror makes it difficult for the analyte to reach the defect layer where the field is confined.

308

2.5.2.

FAUCHET

Influence of the Pore Size and Nanomorpholgy on Sensitivity

When the refractive index inside the pores is increased homogenously, Δl/Δn is the same for sensors with different pore sizes but the same porosity. However, in biosensing applications, the sensing species are attached only to the internal surfaces (pore walls) instead of completely filling the pores. In this case, the pore size becomes an important parameter, because for a PSi layer of a given porosity, the internal surface area (or the total number of available binding sites) decreases as the pore size increases. In this section, we quantitatively characterize the performance of PSi microcavity biosensors by modeling the wavelength shift resulting from binding events in sensors with different pore sizes. To quantitatively analyze Δnpore (the increase of refractive index of the pores due to the binding of a thin layer of molecules on the pore wall) a simplified effective medium approximation based on volume ratios is used. The change in refractive index of the cylindrical pore after infiltration of a uniform layer coating is estimated by ⎡ Vlayer ⎛ Vlayer ⎞ before ⎤ before after before Δnpore = npore − npore =⎢ nlayer + ⎜ 1 − ⎟ npore ⎥ − npore ⎝ Vpore ⎠ ⎢⎣ Vpore ⎥⎦

(4)

and 2

Vlayer Vpore

=

⎛ D⎞ ⎛D ⎞ p ⎜ ⎟ − p ⎜ − t⎟ ⎝ 2⎠ ⎝2 ⎠ ⎛ D⎞ p⎜ ⎟ ⎝ 2⎠

2

2

⎛ t t2 ⎞ = 4⎜ − 2 ⎟ , ⎝D D ⎠

(5)

after before where npore and npore are the refractive indices of the pore before and after binding, nlayer is the refractive index of the binding layer, Vlayer is the volume of the coating layer, Vpore is the volume of the pore, D is the diameter of the pores, and t is the thickness of the layer binding on the pore wall. Thus,

⎛ t t2 ⎞ before Δnpore = 4 ⎜ − 2 ⎟ nlayer − npore ⎝D D ⎠

(

)≈

t

Device Applications of Silicon Nanocrystals and Nanostructures

Device Applications of Silicon Nanocrystals and Nanostructures (Nanostructure Science and Technology)

Silicon Nanocrystals: Fundamentals, Synthesis and Applications

Silicon-Germanium (SiGe) Nanostructures: Production, Properties and Applications in Electronics

Nanocrystals:: Synthesis, Properties and Applications

Nanocrystals: synthesis, properties and applications

Ordered porous nanostructures and applications

Device Applications of Nonlinear Dynamics

Device applications of nonlinear dynamics

Semiconductor and metal nanocrystals

Nanostructures and Nanomaterials: Synthesis, Properties & Applications

Semiconductor Nanostructures for Optoelectronic Applications

Semiconductor Nanostructures for Optoelectronic Applications

Biological Nanostructures and Applications of Nanostructures in Biology: Electrical, Mechanical, and Optical Properties

Biological Nanostructures and Applications of Nanostructures in Biology : Electrical, Mechanical, and Optical Properties (Bioelectric Engineering)

Advances in Silicon Carbide Processing and Applications

Advances in Silicon Carbide Processing and Applications

Quantum Materials, Lateral Semiconductor Nanostructures, Hybrid Systems and Nanocrystals (NanoScience and Technology)

Advances in Silicon Carbide Processing and Applications

Semiconductors and Semimetals, Volume 21 Hydrogenated Amorphous Silicon, Part D Device Applications

Applications of silicon-germanium heterostructure devices

Optical properties of semiconductor nanocrystals

Biological Nanostructures and Applications of Nanostructures in Biology: Electrical, Mechanical, and Optical Properties

Biological nanostructures and applications of nanostructures in biology : electrical, mechanical, and optical properties

Semiconductor Nanocrystals and Silicate Nanoparticles

Electrochemistry of Silicon: Instrumentation, Science, Materials and Applications

Semiconductor Nanocrystals and Silicate Nanoparticles

Silicon

Electrochemistry of Silicon: Instrumentation, Science, Materials and Applications

Electrochemistry of Silicon: Instrumentation, Science, Materials and Applications

Electrochemistry of Silicon: Instrumentation, Science, Materials and Applications

Device Applications of Silicon Nanocrystals and Nanostructures