Applications of silicon-germanium heterostructure devices

Applications of Silicon–Germanium Heterostructure Devices

Series in Optics and Optoelectronics Series Editors: R G W Brown, University of Nottingham, UK E R Pike, Kings College, London, UK

Other titles in the series The Optical Transfer Function of Imaging Systems T L Williams Super-Radiance M G Benedict, A M Ermolaev, U A Malyshev, I V Sokolov and E D Trifonov Solar Cells and Optics for Photovoltaic Concentration A Luque

Forthcoming titles in the series Optical Fibre Devices J P Goure and I Verrier Diode Lasers D Sands High Aperture Focussing of Electromagnetic Waves and Applications in Optical Microscopy C J R Sheppard and P Torok Power and Energy Handling Capabilities of Optical Materials, Components and Systems R M Wood The Practical Application of the Moire Fringe Method C A Walker (ed) Transparent Conductive Coatings C I Bright XUV Optics: Fundamentals and Applications A V Vinogradov

Other titles of interest Thin-Film Optical Filters (Third Edition) H Angus Macleod

Series in Optics and Optoelectronics

Applications of Silicon–Germanium Heterostructure Devices C K Maiti and G A Armstrong Indian Institute of Technology, Kharagpur 721302, India and The Queen’s University of Belfast, Belfast, Northern Ireland, UK

Institute of Physics Publishing Bristol and Philadelphia

c IOP Publishing Ltd 2001
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior permission of the publisher. Multiple copying is permitted in accordance with the terms of licences issued by the Copyright Licensing Agency under the terms of its agreement with the Committee of ViceChancellors and Principals. British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library. ISBN 0 7503 0723 4 Library of Congress Cataloging-in-Publication Data are available

Consultant Editor: S C Jain Commissioning Editor: Tom Spicer Production Editor: Simon Laurenson Production Control: Sarah Plenty Cover Design: Victoria Le Billon Marketing Executive: Colin Fenton Published by Institute of Physics Publishing, wholly owned by The Institute of Physics, London Institute of Physics Publishing, Dirac House, Temple Back, Bristol BS1 6BE, UK US Office: Institute of Physics Publishing, The Public Ledger Building, Suite 1035, 150 South Independence Mall West, Philadelphia, PA 19106, USA Typeset in LATEX using the IOP Bookmaker Macros Printed in the UK by J W Arrowsmith Ltd, Bristol

In memory of Dr Suva Maiti

CONTENTS

PREFACE

xiii

1 INTRODUCTION 1.1 Evolution of bipolar technology 1.2 Heterojunction bipolar transistors 1.3 Development of SiGe/SiGeC HBT technology 1.4 Heterostructure field-effect transistors 1.5 Vertical heterostructure FETs 1.6 Optoelectronic devices 1.7 Applications of SiGe HBTs 1.8 Summary Bibliography

1 5 9 13 16 18 20 21 25 25

2 FILM GROWTH AND MATERIAL PARAMETERS 2.1 Strained layer epitaxy 2.2 Deposition techniques 2.2.1 Wafer cleaning 2.2.2 Molecular beam epitaxy 2.2.3 UHVCVD 2.2.4 LRPCVD and RTCVD 2.2.5 Very low pressure CVD 2.2.6 Remote plasma CVD 2.2.7 Atmospheric pressure CVD 2.2.8 Solid phase epitaxy 2.2.9 SiGeC film growth 2.2.10 Strained-Si film growth 2.3 Thermal stability of alloy layers 2.4 Bandgap and band discontinuity 2.4.1 Si/SiGe 2.4.2 Si/SiGeC 2.4.3 Strained-Si 2.5 Mobility 2.5.1 Si/SiGe 2.5.2 Si/SiGeC

32 33 42 43 44 46 47 48 48 48 49 49 50 51 52 54 56 58 59 59 59

viii

Contents 2.6

2.5.3 Strained-Si Summary Bibliography

63 64 65

3 PRINCIPLE OF SIGE HBTS 3.1 Energy band 3.2 Terminal currents in a SiGe HBT 3.3 Transit time 3.4 Early voltage 3.5 Heterojunction barrier effects 3.5.1 Effect of undoped spacer layers 3.6 High level injection 3.7 High-frequency figures-of-merit 3.7.1 Unity gain cut-off frequency, fT 3.7.2 Maximum oscillation frequency, fmax 3.8 Breakdown voltage, BVceo 3.9 Summary Bibliography

73 75 77 83 85 90 92 94 96 96 98 99 100 100

4 DESIGN OF SIGE HBTS 4.1 Device modelling 4.2 Numerical methods 4.3 Material parameters for simulation 4.3.1 SiGe: hole mobility 4.3.2 SiGe: electron mobility 4.3.3 SiGe: bandgap 4.3.4 Recombination and carrier lifetime 4.4 History of simulation of SiGe HBTs 4.5 Experimental SiGe HBTs 4.6 Device design issues 4.6.1 Base design 4.6.2 Emitter design 4.6.3 Collector design 4.7 Small-signal ac analysis 4.7.1 Small-signal equivalent circuit 4.7.2 Evaluation of transit time 4.7.3 ECL gate delay 4.8 Summary Bibliography

104 106 108 110 112 113 115 117 118 119 121 122 126 129 134 134 139 141 145 145

5 SIMULATION OF SIGE HBTS 5.1 Epitaxial-base SiGe HBT (1995) 5.2 Double polysilicon self-aligned SiGe HBT (1998) 5.3 Energy balance simulation 5.4 SiGe HBTs on SOI substrates

152 155 159 162 166

Contents 5.5 5.6 5.7 5.8 5.9

Low-temperature simulation 5.5.1 Low-temperature SiGe HBTs 5.5.2 Low-temperature simulation using ATLAS I2 L circuits using SiGe HBTs Noise performance Radiation effects on SiGe HBTs 5.8.1 Low dose-rate effects 5.8.2 Simulation of radiation hardness Summary Bibliography

ix 172 173 175 180 182 186 189 190 192 192

6 STRAINED-SI HETEROSTRUCTURE FETS 6.1 Mobility in strained-Si 6.1.1 Theoretical mobility 6.1.2 Experimental mobility 6.2 Band structure of strained-Si 6.3 Device applications 6.3.1 Strained-Si n-MOSFETs 6.3.2 Strained-Si p-MOSFETs 6.4 Simulation of strained-Si HFETs 6.5 MODFETs 6.6 Heterojunction Si/SiGe CMOS 6.7 Summary Bibliography

196 198 198 200 203 204 206 209 213 217 226 231 232

7 SIGE HETEROSTRUCTURE FETS 7.1 HFETs: structures and operation 7.1.1 Experimental HFETs 7.2 Design of SiGe p-HFETs 7.2.1 SiGe: MOS capacitor simulation 7.2.2 Si-cap/oxide thickness variation 7.2.3 Germanium mole fraction 7.2.4 Choice of gate material 7.2.5 Current–voltage characteristics 7.2.6 δ-doped p-HFETs 7.3 SiGe p-HFETs on SOI 7.4 SiGeC p-HFETs 7.5 Devices using poly-SiGe 7.5.1 Poly-SiGe gate MOSFETs 7.5.2 Poly-SiGe thin-film transistors 7.6 Vertical FETs 7.6.1 Vertical SiGe HFETs 7.7 Noise in p-HFETs 7.8 Summary Bibliography

238 241 242 245 245 246 247 249 250 252 254 257 259 260 261 263 263 265 267 268

x

Contents

8 METALLIZATION AND HETEROSTRUCTURE SCHOTTKY DIODES 8.1 Deposition of metal films 8.2 Fabrication of Schottky diodes 8.3 Silicidation of group IV alloy films 8.4 Silicidation with titanium 8.4.1 Rutherford backscattering characterization 8.4.2 Auger electron spectroscopy characterization 8.4.3 Sheet resistivity 8.5 Silicidation using Pt and Pd 8.6 Heterostructure Schottky diodes 8.7 Schottky diodes on strained-Si1−x Gex 8.7.1 Barrier height and ideality factor 8.7.2 Interface state density distribution 8.8 Schottky diodes on strained-Si 8.9 Summary Bibliography

272 274 276 276 278 279 282 284 285 287 291 293 300 303 305 307

9 SIGE OPTOELECTRONIC DEVICES 9.1 Optoelectronic devices in silicon 9.1.1 p–n junction photodiode 9.1.2 Schottky barrier photodiode 9.1.3 p–i–n photodetectors 9.1.4 Metal–semiconductor–metal photodetectors 9.2 Optical properties of SiGe and SiGeC films 9.3 Optical devices using SiGe alloys 9.4 Optical devices with SiGeC and GeC alloys 9.5 Simulation of optoelectronic devices 9.5.1 PtSi/SiGe Schottky photodetectors 9.5.2 SiGe p–i–n photodetectors 9.5.3 MSM photodetectors 9.5.4 SiGe/Si waveguide photodetectors 9.6 Summary Bibliography

310 315 316 317 318 318 321 325 334 336 338 341 345 350 352 353

10 RF APPLICATIONS OF SIGE HBTS 10.1 SiGe: perspective for wireless communication 10.2 Technology comparison 10.3 MOS versus bipolar 10.4 SiGe BiCMOS technology 10.5 RF circuits 10.5.1 Low-noise amplifiers 10.5.2 Power amplifiers 10.5.3 VCOs and frequency synthesizers 10.6 Passive components

359 363 367 369 375 378 378 381 384 386

Contents

xi

10.7 Commercially available products 10.7.1 TEMIC Semiconductors 10.7.2 IBM 10.8 Summary Bibliography

388 388 390 392 392

INDEX

397

PREFACE

Since the first report of SiGe heterostructure bipolar transistors (HBTs) in 1987, there has been tremendous progress in SiGe research. The successful demonstrations of SiGe HBT technology, in both high-performance digital and analogue circuit applications, are the results of over 15 years of steady research progress from initial material preparations in 1984, through device demonstrations from 1987–1992 to large scale circuit fabrication in 1994 and commercial products in 1998. With the development of the ultrahigh vacuum chemical vapour deposition (UHVCVD) system, which produces highly uniform SiGe heterostructures more rapidly than other methods, such as molecular beam epitaxy (MBE) or low-pressure CVD, only minor modifications to the process flow are required to incorporate the manufacture of SiGe HBTs into a conventional bipolar or complementary metal–oxide-semiconductor (BiCMOS) line. Indeed, SiGe HBTs integrated with CMOS (BiCMOS) circuits have been shown to be substantially cheaper than III–V technology. Qualified full-scale production devices (with cut-off frequencies in the 50–60 GHz range) and circuits using 200 mm wafers in a standard 0.5 µm CMOS line are now available. SiGe HBTs are superior to Si bipolar junction transistors (BJTs) and comparable to the best GaAs transistors, in that they are ideally suited for low-voltage, low-power wireless communication applications. Promising research results, combined with recent commercialization announcements, have generated considerable optimism. Silicon has been pushed to the 1–2 GHz frequency domain. However, many new RF applications, such as handheld and personal communication systems (PCS), direct broadcast TV, local multipoint distribution systems and wireless LANs, require circuit operation at frequencies up to 30 GHz. High-speed digital communications (up to 40 Gbps) such as synchronous optical network (SONET) applications also require highspeed devices—typically with a maximum oscillation frequency, fmax in excess of 100 GHz. It is now believed that, in many of these markets, SiGe will provide direct competition for GaAs on the grounds of cost and design flexibility. Indeed, it is possible that SiGe technology may xiii

xiv

Preface

eventually be applicable in the frequency range above 30 GHz, where GaAs is currently well established, in projects requiring wireless technology for traffic management and control, such as global positioning systems (GPS), sensor collision avoidance systems, road speed monitors and side airbag triggers. The application of strained-SiGe to heterostructure field-effect transistors (FETs) is not as well developed as that of HBTs. In MOS technology, scaling the gate length is impeded by lithographic techniques and scaling device width is limited by the relatively low hole mobility of a silicon p-channel metal–oxide-semiconductor field-effect transistor (p-MOSFET). When used in a heterojunction FET, strained-SiGe enhances the mobility of holes but not of electrons. Thus, the current drive of the p-MOSFET is improved, but not that of the n-MOSFET. However, strained-Si grown on a relaxed-SiGe buffer layer improves the electron mobility and current drive of an n-MOSFET. Other important research topics include synthesis of SiGeC, a carbon-containing alloy of SiGe and Si, and quantum-confined structures, which may ultimately offer an alternative to lithographic techniques or serve as single-electron devices. Integrated optoelectronics is another promising research field for SiGe devices, although development is hindered by the lack of a SiGe light emitter. Detectors and waveguides have been demonstrated, and integrated SiGe and Si devices are possible. Work is underway on a graded buffer layer—a virtual substrate—of SiGe that would permit III–V/SiGe/Si integration. Possible photonic devices are under development including: low-loss optical waveguides, photodetectors for 1.3–1.6 µm, light emitters, long-wave infrared detectors, optical switches and photonic integrated circuits. In this textbook, we discuss the relevance of SiGe technology to all the above application areas. The main focus of the book is on device applications, backed up by an extensive survey of the literature. Chapter 1 reviews the key developments in SiGe technology from the earliest research to the present day, leading to a brief summary of the current status of SiGe products in the marketplace. Chapter 2 describes key technology issues for the growth of stable strained-SiGe layers using different types of reactors. The effect of the Ge composition on strain and the consequent effect on bandgap and mobility is described. Chapter 3 gives the background theory of the HBT. Chapter 4 describes issues relating to optimal design of SiGe HBTs and considers how device simulation can be used to determine key indicators of device performance. Chapter 5 extends the concepts of chapter 4 to give a number of examples of the use of device simulation to study a wide range of device structures involving application of SiGe. Chapter 6 describes how growth of a strained silicon (strained-Si) layer on a relaxed-SiGe buffer layer has led to higher values of electron mobility with the resultant enhancement in the high-frequency performance

Preface

xv

of heterojunction field-effect transistors (HFETs). Strategies for the enhancement of hole mobility using either MOSFET or modulation-doped field-effect transistor (MODFET) structures are given. The impact of both strained-Si MODFETs and MOSFETs as a basis for future deep submicron CMOS is considered. In chapter 7, an alternative approach to the formation of a p-HFET is described, involving growth of a strained-SiGe epitaxial layer on a silicon substrate. Once again, the overall objective is a higher mobility, in this case hole mobility, to improve both the transconductance and bandwidth associated with the p-channel MOSFET. Chapter 8 discusses design, characterization and application of Schottky diodes, while chapter 9 considers the design and application of optoelectronic devices. Finally, chapter 10 assesses how SiGe technology competes with other alternative technologies in the wireless telecommunications marketplace. It also focuses on how SiGe technology has rapidly matured, allowing its integration into a mixed signal BiCMOS process. In summary, this book fills a gap in the literature in a rapidly evolving field, as it blends together wide ranging descriptions of SiGe technology, device physics and circuit applications. Where possible, the theoretical material is backed up by computer simulation. An extensive bibliography is provided for each chapter, which helps the reader identify the key stages in the development of SiGe from early research through to its integration in high-performance BiCMOS. We wish to extend special thanks to Professor S C Jain, Consultant Editor, Institute of Physics Publishing, for his keen interest and valuable comments. We are grateful to Tom Spicer, Commissioning Editor, for his personal support for this project. It was due to the skill and efforts of his colleagues, Simon Laurenson, Production Editor, and Sarah Plenty, Production Controller, that the project could be completed in a relatively short time. They deserve our sincere thanks. The help of the Production Department in removing the deficiencies in several figures is gratefully acknowledged. Finally, we must thank sincerely our families for their support and help during the preparation of this book. C K Maiti G A Armstrong 26 October 2000

Chapter 1 INTRODUCTION

Silicon is by far the most widely used semiconductor material and is likely to remain so for the foreseeable future, although from the perspective of an integrated circuit (IC) designer silicon is hardly a perfect semiconductor. Compared with other semiconductors, it is relatively poor in terms of how fast the charge carriers can move through the crystal lattice, which limits the speed at which silicon devices can operate. ‘Why is silicon still dominant?’ The answer to this question is economics. Silicon is abundant in nature, non-toxic, strong and an excellent conductor of heat. It can be grown to a very high purity and very large diameter (with 12 inch now being contemplated) wafers, and it readily forms a stable insulating film (SiO2 or Si3 N4 ) of high quality. Properties of this kind make silicon a natural choice for IC manufacturing and, in fact, over the past 40 years or so, the performance of silicon ICs and the density of devices per unit area have soared, while the cost per function has plunged (see figure 1.1). ICs are more difficult and more expensive to fabricate from III–V compound semiconductors such as GaAs/AlGaAs or InP. High-quality oxides are scarce in the III–V semiconductors, impeding device integration. Highpurity, large diameter crystals are difficult to grow and yield is poor because of more defect density. For decades, miniaturization has been the key to faster performance of ICs. As the size of a transistor, whether field effect or bipolar, influences its speed of operation, designers have focused on creating ever smaller transistors. The strategy for enhancing the function of an electronic device by reducing its critical dimensions is commonly referred to as scaling. Although scaling has led to improvement in the speed and flexibility of silicon-based electronics, the trend cannot continue indefinitely. Researchers are actively pursuing alternative approaches to boost the speed of electronic devices by introducing ‘bandgap engineering’. In silicon technology, two materials may be used in bandgap-engineered transistors: silicon carbide (SiC) and silicon–germanium (SiGe). Silicon 1

2

Introduction

Figure 1.1. Moore’s law: the gate length and cost of production lines as a function of time. Source: National Technology Roadmap for Semiconductors, Semiconductor Industry Association, San Jose, USA, 1997. (After Paul D J 1999 Adv. Mater. 11 191–204.)

carbide is a suitable emitter material, since it has a wider bandgap of 2.2 eV, while SiGe is a suitable base material with a lower bandgap which is dependent on the Ge content. The evolution of SiGe technology has been very rapid. It has gone from laboratory research in less than eight years to a commercial reality. As an example, a 12-bit digital-to-analogue converter (DAC) has been developed jointly by IBM and Analog Devices that processes data at 1.0 Gbit s−1 , which matches the speed of the best such circuits built using GaAs technology and it operates on a fraction of the power they require. At present, aggressively designed SiGe transistors have cut-off frequencies in excess of 130 GHz. In recent years, SiGe transistors, and other devices based on SiGe alloys, have been evident in an increasing number of products. SiGe heterojunction bipolar transistor (HBT) technology has the advantage of relatively simple integration with conventional complementary metal–oxide semiconductor (CMOS) silicon circuits to form a SiGe BiCMOS technology, in which the Si bipolar devices and SiGe HBTs can be integrated for critical high-speed analogue or digital functions. Silicon CMOS can serve for very high density memory or compact on-chip signal processing functions, which cannot be realized in other technologies. The two most important devices used in silicon technology are the bipolar and field-effect transistors, each having their strengths and

Introduction

3

Figure 1.2. Capacity of backbone network. (After Nakamura M 1998 IEEE ISSCC Tech. Dig. pp 16–21.)

weaknesses. Bipolar transistors with their high transconductance have predominantly been used in analogue applications, such as small-signal amplification, and in high-speed digital circuits, such as emitter coupled logic (ECL). For digital circuit applications, CMOS technology dominates because of its low power dissipation and high density of integration. The variety of bipolar transistors can, in general, be grouped into those optimized to satisfy the requirements of two major industries: communications and computers. As all activities of modern society have become information oriented, the need for high-speed and large capacity telecommunications systems is rapidly increasing. The rapid growth in data transmission has also created an urgent demand for increasing transmission capacity in backbone networks. Today, 10 Gb s−1 systems are in commercial use. Figure 1.2 shows the predicted trend for optical fibre transmission capacity. Two methods exist for achieving a higher transmission capacity: (i) time division multiplexing (TDM), and (ii) wavelength division multiplexing (WDM). Figure 1.3 shows the relationship between the bit rate and the required cut-off frequency (fT ) of devices from differing technologies. A 10 Gb s−1 system with fT in the range 25–50 GHz can be satisfied using Si bipolar technology, while a 40 Gb s−1 system, with corresponding fT in the range 100–200 GHz, will require SiGe, GaAs or InP HBTs. In communication applications, the increased importance of transmitting, receiving and interpreting data transmissions at high speeds has generated a need for high-frequency precision analogue circuitry. With

4

Introduction

Figure 1.3. Electron devices for backbone network. (After Nakamura M 1998 IEEE ISSCC Tech. Dig. pp 16–21).

internet host counts doubling every five to seven months, there is a pressing need for high-speed interconnect circuits [1]. In these circuits, the high operating frequency, high transconductance, close matching of the device parameters and bandgap voltage referencing capabilities of bipolar transistors make them invaluable to the design of analogue circuits. In the computer industry, the high-frequency performance and high current drive capabilities of bipolar transistors enable the realization of digital circuits with very low gate delay and high fan-out compatibility. The switching delay of a bipolar circuit is made up of three major components. The importance of these two characteristics can be best illustrated by a graph of the ECL gate delay time versus the collector current of the bipolar transistors, as shown in figure 1.4. In the low collector current range, the gate delay is a function of the load resistance, RL , and the input capacitance of the gate, Cin , which is determined by the capacitance of the bipolar transistors as seen from the gate input. In the high collector current range, the gate delay decreases, approaching a minimum set by the total forward transit time of the transistor, τF . At higher currents, the product of the combination of extrinsic and intrinsic base resistance and the diffusion capacitance begins to dominate the propagation delay. As is evident from figure 1.4, the realization of low gate delays requires the use of increased collector currents. Thus, if the operating current per gate is a limiting factor, the design should be focused on the reduction of parasitic capacitances. The delay contributed by each part of the transistor is different, depending on the type of circuit used.

Evolution of bipolar technology

5

Figure 1.4. Variation of delay components of a bipolar circuit versus collector current. At low currents, the gate delay is determined by the charging of the junction capacitances. At high currents, the minority carrier storage associated with high-level injection prevails.

However, power consumption and dissipation restrictions in digital bipolar circuits limit the collector current of the densely packed transistors. For high-speed digital applications, the challenges for designers of bipolar junction transistors (BJTs) include an increased level of integration, lower operating currents, reduction in base resistance and lower minimum gate delays. 1.1.

EVOLUTION OF BIPOLAR TECHNOLOGY

The design and study of a new semiconductor device structure hold promise at both the device level, where the transistor’s electrical behaviour may lead to novel effects, and the circuit level, where the device characteristics may be exploited to enhance functional performance. Since the revolutionary invention of the point-contact transistor at Bell Laboratories in 1947, numerous new transistor structures have been proposed and demonstrated. Of the many transistors demonstrated in the last fifty years, however, the IC market is dominated by just two devices: the BJT with a market share of about 20%, and the metal–oxide semiconductor field-effect transistor (MOSFET) with 75%. BJTs and MOSFETs are the dominant highperformance devices in silicon technology. In this section, we shall present an overview of the high-performance transistors in silicon.

6

Introduction

Figure 1.5. (a)–(g) The evolutionary continuum between bipolar and field-effect transistors. A conventional FET is shrunk in lateral dimension (a), then converting to a stacking configuration (b). Rotating the structure by 90◦ produces (c). Reducing the vertical dimensions from (c) to (e) yields a permeable base transistor. Replacing the grid with a sheet of metal produces a metal-base transistor (f ). Finally, replacing the metal base with a p-doped layer results in the conventional bipolar transistor (g). (After Stoneham E B 1982 Microwaves 55–60.)

Evolution of bipolar technology

7

The FET represents a class of devices (including MOSFETs, metal– semiconductor field-effect transistors (MESFETs) and junction field-effect transistors (JFETs)) which operate on a principle substantially different from that of the class of devices represented by the BJT. FETs represent lateral geometries and spatial charge control (via depletion regions), while BJTs represent vertical geometries and charge control. An ideal threeterminal device may be considered to move the charge within a finite time, when stimulated by some input voltage or current. Stoneham [2] has shown that most new devices lie somewhere between the extreme cases of BJTs and FETs. By manipulating the geometries and translating lateral and vertical properties, the evolution of one device into the other is possible as shown in figure 1.5. Although MOSFETs have constantly challenged the BJTs for performance superiority, bipolar devices have consistently kept their advantage by evolving new and/or improved process and design. The historical advantage of the bipolar device is the fact that its vertical dimensions are easier to control than the lateral MOS structure. Current gain in a homojunction npn bipolar transistor is mainly determined by the ratio of the density of electrons injected from the emitter into the base and the density of holes reinjected from the base into the emitter, and results in a finite dc current gain. Many attempts have been made to design improved emitter structures to minimize the disadvantages of the homojunction Si BJT with a heavily-doped emitter. Among these, polysilicon technology is by far the most advanced but problems with contact resistance still exist. Techniques to reduce contact resistance lead to reduced emitter efficiency [3, 4]. In a circuit environment, however, parasitics tend to dominate. The base–collector extrinsic junction and the base resistance prevent input signals from reaching the appropriate internal junctions until sufficient charge has filled the depletion regions (in the case of the base–collector capacitance), while the base resistance reduces the voltage seen by the internal emitter–base junction, lowering the effective transconductance. The steady improvement in performance of the BJT is the result of technology maturing sufficiently to build these scaled optimal structures. The evolution of new process technologies, such as silicon-on-insulator (SOI), trench isolation and epitaxial regrowth, provide techniques to drastically reduce the junction capacitances. These techniques have pushed the evolution of the transistor to its technical limits. As lateral geometries continue to shrink, devices require vertical design modifications in order to maintain higher performance. Several alternative structures have been proposed in the literature to extend the performance of silicon bipolar devices. The metal-base transistor at one time held the most promise of all hot electron devices [5]. The injection of electrons from the emitter occurs as in a BJT, but electrons

8

Introduction

entering the base from the emitter see a large band discontinuity. This accelerates them to a large momentum in the vertical direction. The base being very narrow, electrons remain hot throughout the base region, resulting in a reduction in the base transit time. In addition, the use of a metal for the base reduces the base resistance. In principle, the metal-base transistor should have a significant performance advantage over the BJT. Unfortunately, no metal-base transistor has yet achieved even unity current gain. Nishizawa [6] proposed a high-speed switching device known as the bipolar static induction transistor (BSIT) which may be thought of as a bipolar transistor with the intrinsic base region missing. Control of collector current in this device is only possible because the extrinsic p+ base regions are physically close together and current is controlled by forward biasing the base–emitter junction. A high transconductance is obtained compared to FETs of comparable dimensions and also leads to faster switching times. Indeed, several types of circuits have been successfully fabricated with the BSIT device [6, 7]. However, due to its extreme sensitivity to process variations, the BSIT could hardly be useful for high levels of circuit integration. Another interesting structure, a tunnel transistor, which is identical to that of a p-channel MOSFET with a very thin (20 ˚ A) gate oxide layer has also been proposed [8]. The thin oxide layer allows substantial electron tunnelling currents in the vertical direction. The gate can thus act as an emitter, the substrate as a collector and the source/drain regions as extrinsic base regions. The intrinsic base is replaced with a mobile hole layer or ‘inversion channel’ whose charge density modulates the electric field strength across the oxide, and thus controls the electron tunnelling currents in the vertical direction. This hole charge density is controlled by the extrinsic base potential. Using this concept, Simmons and Taylor [8] have theoretically and experimentally studied tunnel transistors built in the Alx Ga1−x As/GaAs material system. GaAs was used as the emitter and the collector semiconductors and AlAs was used as a wide bandgap semiconductor replacing the insulator. However, limited current density and transconductance resulted in a much slower device. Despite much research on alternative technologies, silicon integrated circuits dominate mainstream electronics. Impressive improvements in high-speed Si bipolar technology have been made in the last few years. Self-aligned bipolar transistors having polySi base electrodes have been effective in reducing base resistance through their small resistance in the base electrode and short length between the emitter and the base. Si homojunction transistors with a maximum oscillation frequency, fmax above 80 GHz have been obtained using low base resistance selfaligned metal/IDP (SMI) technology. The base resistance is reduced to a half compared to conventional polySi technology and a 12.2 ps gate delay

Heterojunction bipolar transistors

9

Figure 1.6. Si and SiGe device performance over the past several years. In terms of device speed, SiGe has maintained about 50% advantage over Si devices.

time in an ECL ring oscillator at a voltage swing of 250 mV has been achieved [9]. In 1999, Bopp et al [10] reported a near production, standard implanted base silicon bipolar technology for mixed-signal applications. Applicability for mobile communications up to at least 6 GHz, and for high-speed data links in the range 10–40 Gbits s−1 , was demonstrated. Transistors exhibited an fmax of 65 GHz, a minimum noise figure of 1.3 dB at 6 GHz and a 12 ps ECL gate delay. Summarized in figure 1.6 are some of the reported results obtained with high-performance Si homojunction transistors. Although the data for Si are only plotted up to 1997, the trend line shows that SiGe offers approximately 50% advantage in overall device performance. By way of comparison, back in 1991, AlGaAs/GaAs MODFETs achieved an fT of over 250 GHz [11] and exceeded the 400 GHz barrier for fmax . In an effort to improve single chip functionality, it is not surprising that, despite increased process complexity, BiCMOS processes have been developed to combine the advantages of CMOS and bipolar devices [12]. 1.2.

HETEROJUNCTION BIPOLAR TRANSISTORS

The idea of varying the bandgap in a bipolar transistor structure to increase the emitter injection efficiency is almost as old as the bipolar junction transistor itself. Shockley described the idea in his application for a patent on the junction bipolar transistor [13]. The inherent performance advantages of HBTs over conventional bipolar junction transistors have been recognized and Kroemer [14] first explained the underlying principle

10

Introduction

of the heterojunctions. The heterojunction offers a larger set of device configurations and has become the basis for the so-called field of bandgap engineering [15]. The principle of operation of an HBT is identical to that of the BJT, except that the bandgap of the emitter region exceeds that of the base region by ∆Eg , typically of the order of 0.1–0.2 eV. The resultant e∆Eg /kT exponential increase in current gain permits scaling of the base region to smaller thicknesses and higher doping levels. Conceptually, the simplest way to incorporate a heterojunction into a silicon bipolar transistor process is to replace the polySi emitter of a standard bipolar process with a wide bandgap material having a high-quality interface to the silicon base, thereby combining the minimized parasitic capacitances and resistances of the device structure with the increased emitter injection efficiency of the wide bandgap emitter HBT. Several wide bandgap materials have been investigated, such as GaP [16–18], semi-insulating polycrystalline silicon (SIPOS) [19–21], oxygen-doped silicon epitaxial films [22], epitaxial β-SiC [23], polycrystalline β-SiC [24], amorphous silicon (α-Si) and microcrystalline (µc-Si) silicon [25–27]. Major problems encountered were antiphase domains and cross doping (GaP), high bulk or contact resistance (α-Si and poly-β-SiC), and high processing temperature (single crystalline β-SiC). Moreover, it seems difficult to realize ideal, or at least reproducible, base currents with these materials [26, 28]. β-SiC can now be grown at 750 ◦ C, greatly improving its prospects for integration into Si HBTs with narrow and heavily-doped bases. A key point concerning wide bandgap emitter silicon HBTs is that the shape of the conduction band barrier in the base is identical to that of an Si homojunction transistor. It is therefore impossible to obtain improvements in transit time and output resistance associated with a bandgap grading between the emitter and collector sides of the base leading to a built-in drift field for the minority carriers in the base. Some of these structures may prove useful for special applications. However, in general, these have not been accepted by the semiconductor industry due to the difficulties in process optimization and reproducibility. Although the performance advantages of HBTs over BJTs were well understood, no fabrication technologies were available to produce highquality heterojunctions until the 1970s. The emergence of two new growth techniques, namely molecular beam epitaxy (MBE) [29] and metal–organic chemical vapour deposition (MOCVD) [30], sparked a thrust in the research of high-speed HBTs. Most research has been on the AlGaAs/GaAs system and related compound semiconductors. The high performance demonstrated by HBTs is a result of not only the inherent advantages of heterojunctions, but also the use of semiconductor materials with higher mobilities and saturated drift velocities. For instance, implementation of an Alx Ga1−x As/GaAs HBT has yielded the lowest demonstrated gate delay of

Heterojunction bipolar transistors

11

1.9 ps, and an AlInAs/InGaAs HBT has given a unity current gain cut-off frequency exceeding 200 GHz. Despite the advances in HBT fabrication techniques, mostly using group III–V and II–VI materials, silicon devices continue to dominate due to the low cost and ease of manufacturability. Silicon readily forms a high-quality oxide which can be used to mask implants, diffusion and metallization. The isolation technique, chemical vapour deposition, diffusion, ion implantation, contact technology and etching methods are highly developed in Si technology. GaAs and the other III–V semiconductors lack this important property. It is well known that GaAs or InP technologies exhibit superior fT and fmax , compared to a SiGe device, for a specified geometry. An excellent comparison of the technologies has been presented by Konig and Gruhle [31]. Plots from [31] of both fT and fmax as a function of base width are shown in figures 1.7 and 1.8. A further performance comparison of a III–V material HBT with a SiGe HBT has been presented by Larson [32]. Clearly, if maximum bandwidth or speed is the only criterion, then

Figure 1.7. Comparison of cut-off frequency, fT , as a function of base width for SiGe HBTs and devices from III–V technologies. (After Konig U and Gruhle A 1997 Proc. IEEE Cornell Conf. on Advanced Concepts in High Speed Semiconductor Devices and Circuits pp 14–23.)

12

Introduction

Figure 1.8. Comparison of maximum frequency of oscillation as a function of base width for SiGe HBTs and devices from III–V technologies. (After Konig U and Gruhle A 1997 Proc. IEEE Cornell Conf. on Advanced Concepts in High Speed Semiconductor Devices and Circuits pp 14–23.)

III–V technology is a superior option. In overall radio frequency (RF) system performance, including antenna interfacing, low noise and low power amplifier performance and relatively high levels of integration, SiGe HBT technology offers significant advantages, as summarized in table 1.1. Table 1.1. Technology comparison in the frequency range of 1–10 GHz. (After Temic Semiconductors, Germany.)

Low-frequency noise Low RF noise Low voltage High gain High power High efficiency Analogue capability Integration level Power supply

Si BJT

SiGe HBT

GaAs FET

+ O + − − − O + +

+ + + + + + + + +

− + O + + + + O −

Development of SiGe/SiGeC HBT technology 1.3.

13

DEVELOPMENT OF SIGE/SIGEC HBT TECHNOLOGY

As silicon BJTs reach their fundamental limits on speed because of the physical properties of the semiconductor material, advanced high-speed devices require heterojunction technology, as has been demonstrated in the previous section. Although Ge had made its mark as the point-contact electrode on the first transistor, Si eventually became the semiconductor of choice for its material properties. In 1957, Kroemer patented the first heterojunction Si bipolar transistor and eighteen years later, Erich Kasper at Daimler–Benz (now Daimler–Chrysler) made the first SiGe strained layer [33]. With the advent of heteroepitaxy, the concept of strained layers has been extended to include other elemental semiconductors. These developments set the stage for IBM’s development of SiGe HBTs in 1987 using MBE. The use of the ultrahigh vacuum chemical vapour deposition (UHVCVD) tool for HBT and BiCMOS devices followed. SiGe HBTs are particularly exciting because of their ability to take immediate advantage of highly developed silicon processing techniques. Impressive improvements in high-speed SiGe bipolar technology have been made through the growth of device quality strained-Si1−x Gex layers. This strain, which occurs because of a ∼4% difference in the lattice constants of Si and Ge, is used to vary the bandgap energy, band discontinuities and other properties of the material. For any given Ge content, there is a critical thickness of SiGe, above which dislocations cause severe performance degradation, as discussed more fully in chapter 2. The thin base layer of Si1−x Gex , sandwiched between the Si collector and emitter, must be thin enough to prevent the formation of these dislocations. Of additional significance is the enhanced mobility in a strained layer which offers the possibility of improved performance in SiGe-based FET devices, as discussed in chapters 6 and 7, although much of this work is still in the research stage. Higher mobility in digital circuits permits a smaller voltage swing to switch between states, leading to both faster switching times and reduced power consumption. Although the introduction of Ge in the base increases process integration complexity, it offers an additional degree of freedom which relaxes a series of trade-offs affecting device design. Several key advantages over conventional bipolar transistors include: • • • •

reduction in base transit time—resulting in higher frequency performance; increase in collector current density and hence current gain; lower intrinsic base resistance; and increase in Early voltage.

The design of a SiGe HBT, for a particular technology generation, is optimized by appropriate scaling of the emitter, base and collector regions

14

Introduction

and their associated doping profiles. A SiGe HBT offers additional design flexibility in that the bandgap of the base may be tailored by grading the Ge concentration. Reducing the width of the base region reduces the base transit time with associated improvement in cut-off frequency, but inevitably increases overall base resistance with possible reduction in fmax . For effective design, it is thus essential to use an appropriate simulation tool. Many of the significant issues have been published in a number of reports dealing with aspects of both numerical and analytical modelling of SiGe HBTs [34–41]. In chapters 4 and 5 of this book, we discuss the design considerations for SiGe HBTs in terms of the following: • • • •

optimization of base, emitter and collector doping profiles; effect of Ge profile on the transit times; prediction of cut-off frequencies, fT and fmax ; and design issues at low temperature.

Since the first report of SiGe HBTs in 1987, there have been numerous demonstrations (see figure 1.6) of its impressive potential. For example, an early theoretical study [42] predicted a unity gain cut-off frequency in excess of 300 GHz. Since then there have been a number of significant milestones in the measured performance of SiGe HBTs, including fT in excess of 130 GHz [43], fmax values of 160 GHz [44], ECL and current model logic (CML) gate delay of less than 10 ps [45–47]. Recently, an Si/Si0.65 Ge0.35 abrupt SiGe HBT with an fT of 213 GHz and fmax of 115 GHz at 77 K has been reported [48]. Summarized in table 1.2 are some of the reported results obtained with high-performance SiGe HBTs, which relate to state-of-the-art performance in commercially available devices. The addition of substitutional carbon to silicon–germanium thin films

Table 1.2. Some of the commercially available (as of 1998) device results from various SiGe research groups. Group parameter

IBM (1996)

IBM (BiCMOS)

NEC

HP

Daimler–Benz

fT /fmax (GHz)

48/60

48/60

60/50

40/–

59/90 113/65

Rbi /Rb (Ohms/square)

7–9 k

7–9 k

–

40k

380–780

Wb (˚ A)

700–1000

700–1000

–

500–600

150 w/spacers

Ge Profile

0–15% various shapes

0–15% various shapes

15% graded

16% graded

30% uniform

Development of SiGe/SiGeC HBT technology

15

leads to a new class of semiconducting materials (SiGeC) [49, 50]. This new material can remove some of the constraints (such as the critical layer thickness) on strained-Si1−x Gex and may help to open up new fields of device applications for heteroepitaxial Si-based systems. The incorporation of carbon [51] can be used: • • •

to enhance the SiGe layer properties; to obtain layers with new properties; and to control dopant diffusion.

A summary of possible applications of C-containing Si and SiGe films are shown in table 1.3. The incorporation of a low concentration of carbon (0 dB gain @ +3 dBm LO, 100 KHz IF BW, 30 dB isolation >6 dB gain, 19 dBm output 6.4–23 GHz, 1.5 W 5 GHz, 1.5 V, 89 mW Bandwidth 12 GHz GBW >22 GHz 1.2 Gsps, 750 mW

24

Introduction

RF applications require circuit operation at frequencies up to 30 GHz, a regime well out of the realm of devices based solely on Si. A number of circuit designs have been fabricated in SiGe technology in order to demonstrate its capability in the RF marketplace. Among the circuits that have been reported are: voltage controlled oscillators (VCOs), lownoise amplifiers (LNAs), power amplifiers (PAs), mixers and digital delay lines. Several reported circuit results are presented in table 1.4, and a more comprehensive survey is included in chapter 10. An exciting example of a communications application is the 10 Gbps data transmission system designed by Alcatel using advanced IBM SiGe technology [94]. In this system, SiGe technology has made a significant contribution toward the implementation of a cost effective transmission on a standard optical fibre, offering operators the advantage of upgrading their existing networks to terabit speed, without the time and cost of laying new cables. Table 1.5. List of devices available in the SiGe BiCMOS technology. The main characteristics are provided for each device which are available to the designers to make a full custom design. (After Brenner et al 1999 IBM MicroNews 5 1–4.) Device 1 npn 2 npn 3 n-FET 4 p-FET 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Gated lateral pnp Spiral inductor Varactor Schottky barrier diode Substrate contact Polysilicon resistor (RP) Polysilicon resistor (XN) Reach-through implant resistor (RN) n+ -subcollector resistor (RS) Ion implanted resistor (RI) Metal–insulator–metal capacitor Decoupling capacitor p–i–n diode ESD protective device

Parameter SiGe HBT fT = 47 GHz fmax = 65 GHz Higher breakdown SiGe HBT fT = 27 GHz, fmax = 55 GHz ID,sat = 485µA/µm Leff min=0.39 µm ID,sat = 213µA/µm Leff min=0.39 µm β = 107, VA = 67 V L = 10 nH, Q = 6 at 1 GHz 1.4 fF µm−2 Vf = 0.31 V @ 100 µA for 5 × 5 µm 330 Ωs (p+ subs.) for 2 × 10 µm 220 Ω/square 340 Ω/square 23.5 Ω/square 8 Ω/square 1750 Ω/square 0.7 fF µm−2 1.5 fF µm−2 6 Ω for a 2 × 10 µm 2000 V HBM

Summary

25

An excellent review of the application-driven origins of SiGe technology, how it has evolved and how the limitations of conventional silicon bipolar scaling have enhanced its adoption in the semiconductor industry, has been written by Meyerson [95]. This review demonstrates that SiGe HBTs are superior to Si BJTs and comparable to the best GaAs transistors and ideally suited for low-voltage and low-power wireless communication applications. In some aspects, such as low noise and low power consumption, SiGe HBTs have advantages over III–V HBTs, and approach the performance of some HEMTs, at least below 10 GHz. So far, Si BJT performance has been the main barrier for silicon to penetrate wireless RF front-ends. While SiGe HBTs have removed the barrier, RF isolation and system cost issues still remain. Since silicon substrates are conductive, it is not practical to build high-quality passive elements on-chip. However, much of the cost in current RF systems using discrete components comes from the passive elements. In addition to the SiGe HBT, recent progress in passive component design on silicon substrates, listed in table 1.5, now gives the RF designers a rich environment to realize applications for the wireless marketplace. 1.8.

SUMMARY

This introductory chapter has described the evolution of SiGe technology from early materials research to its current established position in the marketplace. The evolution of bipolar technology has led to the development and application of a SiGe transistor through utilization of strained layers. SiGe HBT technology has the potential to revolutionize high-frequency transceiver design in a way comparable to the revolution in digital integrated circuit technology brought about by CMOS. Its unique combination of outstanding high-frequency performance, low manufacturing cost and high yield will provide abundant opportunities for new architectures and new systems in the near future. Subsequent chapters in this book describe the basis of SiGe technology in much more detail. BIBLIOGRAPHY [1] Walker R C, Hsieh K-C, Knotts T A and Yen C-S 1998 A 10 Gb/s Si-bipolar TX/RX chipset for computer data transmission IEEE ISSCC Tech. Dig. pp 302–3 [2] Stoneham E B 1982 The search for the fastest three-terminal device Microwaves 55–60 [3] Ashburn P 1988 Design and Realization of Bipolar Transistors (Chichester: Wiley) [4] Patton G L, Bravman J C and Plummer J D 1986 Physics, technology

26

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28

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[43] Oda K, Ohue E, Tanabe M, Shimamoto H, Onai T and Washio K 1997 130 GHz fT SiGe HBT technology IEEE IEDM Tech. Dig. pp 791–4 [44] Schuppen A, Erben U, Gruhle A, Kibbel H, Schumacher H and Konig U 1995 Enhanced SiGe heterojunction bipolar transistors with 160 GHz fmax IEEE IEDM Tech. Dig. pp 743–6 [45] Washio K, Kondo M, Ohue E, Oda K, Hayami R, Tanabe M, Shimamoto H and Harada T 1999 A 0.2 µm self-aligned SiGe HBT featuring 107 GHz fmax and 6.7 ps ECL IEEE IEDM Tech. Dig. pp 557–60 [46] Oda K, Ohue E, Tanabe M, Shimamoto H and Washio K 1999 DC and AC performances in selectively grown SiGe-base HBTs IEICE Trans. Electron. E82-C 2013–20 [47] Meister T F, Schafer H, Franosch M, Molzer W, Aufinger K, Scheler U, Walz C, Stolz M, Boguth S and Bock J 1995 SiGe-base bipolar technology with 74 GHz fmax and 11 ps gate delay IEEE IEDM Tech. Dig. pp 739–42 [48] Zerounian N, Aniel F, Adde R and Gruhle A 2000 SiGe heterojunction bipolar transistor with 213 GHz fT at 77 K Electron. Lett. 36 1076–8 [49] Lanzerotti L D, Sturm J C, Stach E, Hull R, Buyuklimanli T and Magee C 1997 Suppression of boron transient enhanced diffusion in SiGe heterojunction bipolar transistors by carbon incorporation Appl. Phys. Lett. 70 3125–7 [50] Osten H J, Heinemann B, Knoll D, Lippert G and Rucker H 1998 Effects of carbon on boron diffusion in SiGe: principles and impact on bipolar devices J. Vac. Sci. Technol. B 16 1750–3 [51] Osten H J, Barth R, Fischer G, Heinemann B, Knoll D, Lippert G, R¨ ucker H, Schley P and R¨ opke W 1998 Carbon-containing group IV heterostructures on Si: properties and device applications Thin Solid Films 321 11–4 [52] Anteney I M, Lippert G, Ashburn P, Osten H J, Heinemann B, Parker G J and Knoll D 1998 Characterization of the effectiveness of carbon incorporation in SiGe for the elimination of parasitic energy barriers in SiGe HBTs IEEE Electron Device Lett. 20 116–8 [53] Osten H J, Knoll D, Heinemann B, Rucker H and Tillack B 1999 Carbon-doped SiGe heterojunction bipolar transistors for high-frequency applications IEEE BCTM Tech. Dig. pp 109–16 [54] Lanzerotti L D, St Amour A, Liu C W, Sturm J C, Watanabe J K and Theodore N D 1996 Si/Si1−x−y Gex Cy /Si heterojunction bipolar transistors IEEE Electron Device Lett. 17 334–7 [55] Osten H J, Knoll D, Heinemann B and Tillack B 1998 Carbon doping of SiGe heterobipolar transistors Proc. Silicon Monolithic Integrated Circuits in RF Systems pp 19–23 [56] Osten H J, Knoll D, Heinemann B and Schley P 1999 Increasing process margin in SiGe heterojunction bipolar technology by adding carbon IEEE Trans. Electron Devices 46 1910–2 [57] Osten H J 1999 Carbon-Containing Layers on Silicon—Growth, Properties and Applications (Switzerland: Trans-Tech Publications) [58] Sadek A, Ismail K, Armstrong M A, Antoniadis D A and Stern F 1996 Design of Si/SiGe heterojunction complementary metal–oxide semiconductor transistors IEEE Trans. Electron Devices 43 1224–32 [59] Ismail K 1995 Si/SiGe high-speed field-effect transistors IEEE IEDM Tech.

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30

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[77] Samavedam S B, Currie M T, Langdo T A and Fitzgerald E A 1998 Highquality germanium photodiodes integrated on silicon substrates using optimized relaxed graded buffers Appl. Phys. Lett. 73 2125–7 [78] Sieg R M, Ringel S A, Ting S M, Samavedam S B, Currie M, Langdo T and Fitzgerald E A 1998 Toward device-quality GaAs growth by molecular beam epitaxy on offcut Ge/Si1−x Gex /Si substrates J. Vac. Sci. Technol. B 16 1471–4 [79] Larson L E 1998 Integrated circuit technology options for RFICs—present status and future directions IEEE J. Solid-State Circuits 33 387–99 [80] Abidi A A 1995 Direct-conversion radio transceivers for digital communications IEEE J. Solid-State Circuits 30 1399–410 [81] Rudell J C, Ou J-J, Cho T B, Chien G, Brianti F, Weldon J A and Gray P 1997 A 1.9 GHz wide-band IF double conversion CMOS receiver for cordless telephone applications IEEE J. Solid-State Circuits 32 2071–87 [82] Greshishchev Y M and Schvan P 1999 A 60 dB gain 55 dB dynamic range 10 Gb/s broadband SiGe HBT limiting amplifier IEEE ISSCC Tech. Dig. pp 382–3 [83] Masuda T, Ohhata K, Oda K, Tanabe M, Shimamoto H, Onai T and Washio K 1998 40 Gb/s analog IC chipset for optical receiver using SiGe HBTs IEEE ISSCC Tech. Dig. pp 314–15 [84] Strohm K M, Luy J-F, Hackbarth T and Kosslowski S 1998 MOTT SiGe SIMMWICs IEEE MTT-S Dig. pp 1691–4 [85] Sevenhans J, Verstraeten B, Fletcher G, Dietrich H, Rabe W, Bacq J L, Varin J and Dulongpont J 1998 Silicon germanium and silicon bipolar RF circuits for 2.7 V single chip radio transceiver integration IEEE CICC Proc. pp 409–12 [86] Ainspan H, Soyuer M, Plouchart J-O and Burghartz J 1997 A 6.25 GHz low DC power low-noise amplifier in SiGe IEEE CICC Proc. pp 177–80 [87] Henderson G N, O’Keefe M F, Boles T E, Noonan P, Sledziewski J M and Brown B M 1997 SiGe bipolar junction transistors for microwave power applications IEEE MTT-S Dig. pp 1299–1302 [88] Long J R, Copeland M A, Kovacic S J, Malhi D S and Harame D L 1996 RF analogue and digital circuits in SiGe technology IEEE ISSCC Tech. Dig. pp 82–3 [89] Larson L, Case M, Rosenbaum S, Rensch D, Macdonald P, Matloubian M, Chen M, Harame D, Malinowski J, Meyerson B, Gilbert M and Maas S 1996 Si/SiGe HBT technology for low-cost monolithic microwave integrated circuits IEEE ISSCC Tech. Dig. pp 80–1 [90] Case M, Knorr S, Larson L, Rensch D, Harame D, Meyerson B and Rosenbaum S 1995 A 23 GHz static 1/128 frequency divider implemented in a manufacturable Si/SiGe HBT process IEEE BCTM Proc. pp 121–4 [91] Gao W, Snelgrove W M, Varelas T, Kovacic S J and Harame D L 1995 A 5 GHz SiGe HBT return-to-zero comparator IEEE BCTM Proc. pp 166–9 [92] Glenn J, Case M, Harame D and Meyerson B 1995 12 GHz Gilbert mixers using a manufacturable Si/SiGe epitaxial-base bipolar technology IEEE BCTM Proc. pp 186–9 [93] Harame D L, Schonenberg K, Gilbert M, Nguyen-Ngoc D, Malinowski J, Jeng S-J, Meyerson B S, Cressler J D, Groves R, Berg G, Tallman K,

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Chapter 2 FILM GROWTH AND MATERIAL PARAMETERS

Silicon-based heterostructures have come a long way from the use of strain as a parameter for bandgap engineering, to the present state of devices/circuits with enhanced performance compared to those obtained in bulk-Si and competing III–V compound semiconductors. Apart from the inherent performance enhancement, undoubtedly the main attraction of high mobility Si/SiGe, SiGe/strained-Si and Si/SiGeC heterostructures is their basic compatibility with standard Si processing. For any material, issues important to the device designer include bandgap difference, band alignments and mobility. The first two properties determine the class of devices that can be fabricated. For example, quantum confinement of electrons cannot occur without a conduction band discontinuity. It is the purpose of this chapter to consider the recent developments in growth techniques and the performance levels achieved to date in group IV alloy systems, to address the problems related with film development and process integration and to discuss alternative routes that could circumvent the use of strain adjusting epilayers, which are presently the bottleneck for an introduction of these promising materials (such as strained-Si and SiGeC) into a production environment. We shall discuss various growth and doping techniques and strain-induced material properties of different group IV alloy layers. The electronic properties of Si/SiGe, Si/SiGeC and strained-Si films will be presented. Semiconductor heterostructure devices rely on the differences in the electronic bandstructure of the two semiconductors used to fabricate a device. In the beginning of heterostructure devices, the emphasis was on finding a pair of semiconductors with different bandgaps but with nearly the same lattice constants. This was necessary so that a good epilayer of one semiconductor could be grown on the other. In lattice matched heterostructures, one can obtain an interface of high quality without 32

Strained layer epitaxy

33

defects, so that as a free carrier approaches a heterostructure boundary, it would be influenced only by the potential gradients and is not trapped or artificially scattered at the heterostructure boundary. Heterostructures based on column III–V and II–VI compound semiconductors, such as AlAs and GaAs, can be easily fabricated since there are direct structural and chemical matches among these semiconductors. On the other hand, for silicon-based heterostructures this is not the case as silicon has no natural semiconductor partner with respect to the configuration of its atomic lattice and chemistry, although silicon and germanium are completely miscible over the entire compositional range and give rise to alloys with a diamond crystal structure. At room temperature, the lattice constants for silicon and germanium are 5.43 ˚ A and 5.65 ˚ A, respectively, leading to a 4.2% lattice mismatch. Clearly, the large mismatch between silicon and germanium precludes depositing epitaxial germanium directly on silicon. The miscibility of silicon and germanium, however, allows deposition of epitaxial Si1−x Gex , without adhering to stoichiometric ratios, on silicon. As a result, the lattice mismatch between silicon and Si1−x Gex is lessened. Because a significant lattice mismatch still exists, Si1−x Gex on silicon can range from a fully strained to a fully relaxed state. Normal heterostructures of Si and Ge thus grow with high dislocation densities that were believed to be incompatible with most device applications. In the early 1980s, however, the situation changed when it was demonstrated that by utilizing strained layer epitaxy, defects could be eliminated in thin silicon-based heterostructures. In strained alloys of Si and Ge, Si1−x Gex , it was found that heterostructure effects were much stronger than expected, making them very attractive for device applications. 2.1.

STRAINED LAYER EPITAXY

Before we discuss the deposition and properties of strained layers, we briefly discuss the properties of the relevant bulk materials as given in table 2.1. Ge has been known to be produced with extremely poor impurity concentrations and large mobilities with both p- and n-type conductivity. Both the n- and p-type high-quality Ge samples exhibit mobilities of about 2 000 000 cm2 V−1 s−1 at about 4 K. On the other hand, high-purity Si exhibits electron mobilities slightly in excess of 500 000 cm2 V−1 s−1 at 4 K. As the atomic spacing of germanium is 4.2% larger than that of silicon, when the first few atomic layers of Ge are deposited, it is energetically desirable that they maintain full bonding with the silicon by compressing together. In the fully strained case, the larger Si1−x Gex horizontal lattice compresses to match the silicon substrate and the Si1−x Gex vertical lattice constant expands to accommodate the horizontal compression as shown

34

Film growth and material parameters

Table 2.1. Room-temperature materials data of selected group IV elements. Element Lattice Lattice constant, ao (˚ A) Density, g cm−3 TCE, α (10−6 K−1 ) Bandgap, Eg (eV) Dielectric constant,  Electron mobility, µe (cm2 V−1 s−1 ) Hole mobility, µh (cm2 V−1 s−1 ) Effective mass m∗ Electron, m∗e (⊥) Electron, m∗e () Light-hole, m∗h (l) Heavy-hole, m∗h (h)

C Diamond 3.5668 3.515 1.0 5.48 5.7

Si Diamond 5.431 2.329 2.56 1.11 11.9

Ge Diamond 5.657 5.323 5.9 0.664 16.2

α–Sn Diamond 6.489 7.285 4.7 – 24

1800

1450

3900

1400

1600

450

1900

1200

– – 0.7 2.18

0.19 0.92 0.15 0.54

0.08 0.64 0.043 0.28–0.38

0.024 0.2–0.45 – –

Figure 2.1. A schematic diagram of strained-Si1−x Gex crystal lattices illustrating two types of strain. In both cases, the epitaxial film is constrained by the substrate along two axes, as indicated by the arrows.

in figure 2.1. The higher energy state of strained-Si1−x Gex is sustained because the activation energy for the dislocation formation has not been reached. Since the Si substrate lattice is both much thicker and stiffer, it remains essentially undistorted. The growth of Si1−x Gex on silicon begins as a strained layer, but when the thickness or germanium concentration of the layer exceeds a critical value, the layer relaxes. Since the lattice

Strained layer epitaxy

35

Figure 2.2. Lattice constant for an Si1−x Gex alloy as a function of x. Vegard’s law is a linear interpolation between aSi and aGe .

constants of Si1−x Gex alloys are larger than that of Si, pseudomorphic Si1−x Gex layers grown on silicon have biaxial in-plane compression of the alloy and an extension normal to the interface. If layers are grown on a germanium substrate the reverse is the case. In both cases the layers suffer a tetragonal distortion. In fully relaxed Si1−x Gex on silicon, the lattice constant returns to the bulk value. The lattice constants of bulk-Si1−x Gex alloys have been measured and the results obey Vegard’s law to a very good approximation. Assuming Vegard’s law applies, the bulk-Si1−x Gex lattice constant (aSi1−x Gex ) is a function of the silicon and germanium lattice constants (aSi and aGe ) and the mole fraction of germanium, x in equation (2.1). The lattice constant of Si1−x Gex alloys varies linearly, as shown in figure 2.2 obeying Vegard’s rule: a(Si1−x Gex ) = aSi + x(aGe − aSi ).

(2.1)

Due to the relatively large lattice mismatch between SiGe and silicon, commensurate (defect-free) SiGe alloy films cannot be grown on silicon substrates without introducing large amounts of strain. As the thickness of the SiGe layer increases, so does the integrated strain energy and at some point this configuration will reach a thickness, which is known as the ‘critical layer thickness’, beyond which the total energy becomes larger and results in ‘misfit dislocations’ or periodic arrays of incompletely bonded atom rows. Misfit or threading dislocations appear at the interface in both the relaxed and partially relaxed cases. Threading dislocations affect the heterojunction by acting as a pathway for enhanced

36

Film growth and material parameters

dopant diffusion. This leads to increased junction leakage current. Misfit dislocations located inside a heterojunction depletion region result in an increased space-charge layer recombination and generation current. For most device applications, dislocations are deleterious and should be avoided. Since the dangling bond can become a trap or leakage site, such dislocations must be avoided within the active volume of a heterostructure device. This implies that active device areas must not lie at the interface of the Si1−x Gex and Si layers. This is possible in certain devices but, unfortunately, there are also segments of dislocations that thread from the heterostructure interface up to the surface of the crystal. A number of strategies have been suggested to minimize the impact of such threading dislocations [1]. The first possibility is extending the dislocation plane either to the edge of the wafer or at least to the boundary of a device die where threading dislocations would be irrelevant. Alternating thin layers can also be grown so that dislocations do not form and instead the atomic spacings of one or both materials shift to accommodate one another. This occurs naturally in very thin layers (e.g., 10–100 atoms thick) and can persist in much thicker layers (100–1000 layers) if a low-temperature growth technique is used, where dislocations do not have enough energy to form and grow. In some recent applications, however, the use of thick relaxed-Si1−x Gex layers as a starting substrate for strained silicon (strained-Si) deposition has been made. Relaxed-Si1−x Gex layers can be grown thick enough to cause threading dislocations to loop around. As a result, the surface is nearly defect-free. Alternating layers of silicon and Si1−x Gex may also be used to filter out threading dislocations. Contrary to the simplistic view given above, the transition from the strained to the relaxed case is not abrupt and is not clearly defined. Varying degrees of strain relaxation can exist [2]. Figure 2.3 shows three regimes (stable, metastable and relaxed) in the plot of Si1−x Gex layer thickness on silicon versus germanium mole fraction. The germanium concentration is directly related to the lattice mismatch according to Vegard’s law. The term ‘critical thickness’ was initially defined to denote the transition from a strained to a relaxed-Si1−x Gex layer. Van der Merwe [3, 4] calculated the critical thickness as a function of increased lattice mismatch, by minimizing the sum of the interfacial and strain energy. However, most of the published literature accepted the mechanical equilibrium theory of Matthews and Blakeslee [5, 6] as defining the transition from the stable to metastable regimes. Mechanical equilibrium theory assumes the existence of a threading dislocation. The energy required to glide a threading dislocation into a misfit dislocation is balanced with the strain energy from the lattice mismatch to define the critical thickness as a function of lattice mismatch. When the strain energy exceeds the misfit dislocation forms to

Strained layer epitaxy

37

Figure 2.3. Critical layer thickness versus Ge content showing stable, metastable and relaxed ranges of Si1−x Gex layers on Si. (After Schuppen A et al 1995 J. Mater. Sci., Mater. Electron. 6 298–305.)

relieve the strain energy. A simplified Matthews–Blakeslee critical thickness calculation (hc ) where angular dependences have been ignored [7], is given by equation (2.2)
 b hc 1 ln +1 (2.2) hc  f 4π(1 + ν) b where ν is Poisson’s ratio (0.3), b is the slip distance (0.4 nm), f is the mismatch between the film and substrate and for Si1−x Gex on silicon, f is 0.042x. For a detailed derivation of the critical thickness, the reader may refer to an excellent review by Jain and Hayes [8]. Although the Matthews–Blakeslee equilibrium theory is widely cited, strained-Si1−x Gex layers have been deposited much thicker than the theory predicts. Bean et al [9] deposited strained layers by molecular beam epitaxy at 550 ◦ C with the thickness an order of magnitude or more above the Matthews–Blakeslee curve, as shown by the solid curve in figure 2.3. The dashed curve demarcates the metastable and dislocation regimes. Above the dashed curve, strained-Si1−x Gex layers were impossible to deposit. Between the solid mechanical equilibrium curve and the dashed curve, the layers are labelled metastable. Layers in the metastable regime are

38

Film growth and material parameters

strained, even though the layers are above the Matthews–Blakeslee critical thickness. However, metastable layers relax with subsequent annealing. People and Bean sought to reconcile these differences by including the kinetics of relaxation in their calculation [10]. Their critical thickness prediction fits their data, but their theory has not been widely accepted by other researchers. Many other researchers have also contributed with critical thickness theories based on energy, mechanical equilibrium and kinetics of dislocations [11–13]. The critical thickness theories based on dislocation formation are disputed by some researchers because other factors, such as wafer preparation and particulate contamination, may play a much larger role in determining misfit dislocations [14]. Furthermore, methods for determining whether a layer is strained or relaxed may not have enough sensitivity to detect the onset of dislocation formation [15]. As a result, dislocation techniques with poor resolution overestimate the critical thickness. Determination of the critical thickness curve depends on the deposition methods and characterization methods used. Nonetheless, most researchers concur that the Matthews–Blakeslee equilibrium curve distinguishes the point where strained-Si1−x Gex layers cannot sustain extended thermal processing. When a thin film with a larger lattice constant (e.g., Si1−x Gex ) is grown on a smaller lattice constant substrate (e.g., silicon), the film maintains an in-plane lattice constant of the substrate and is under a biaxially compressive strain. Since layer sequences with well-defined electrical and optical properties require coherence of the in-plane lattice constant, biaxial strain is always present in such heterostructures. This asymmetry of the strain with respect to the (001) growth direction leads to a splitting of the sixfold degenerate conduction band and also of the heavy-hole/light-hole valence band degeneracy. The band ordering in this heterosystem is therefore strongly strain dependent, and a type I band alignment is obtained where the entire band offset occurs in the valence band (figure 2.4(a)) while the band offset in the conduction band is very small. This type of structure is favourable for hole confinement and has been exploited in several novel heterostructure devices, namely buried channel p-MOSFETs, p-MODFETs and HBTs (see for example, a review by Konig and Daembkes [16]). Similarly, a smaller lattice constant silicon epilayer (strained-Si) will be under biaxial tension when grown on a larger lattice constant relaxedSi1−x Gex substrate. In this case, type II band offset occurs (figure 2.4(b)) and the structure has several advantages over the more common type I band alignment. A large band offset is obtained in both the conduction and valence bands, relative to the relaxed-Si1−x Gex layer [7]. This allows both electron and hole confinements in the strained-Si layer, making it useful for both n- and p-type devices for strained-Si/SiGe-based CMOS technology. The ability to achieve both n-MOS and p-MOS devices

Strained layer epitaxy

39

Figure 2.4. Band alignments for (a) Si0.8 Ge0.2 on (001)Si, (b) strained-Si on (100)Si0.8 Ge0.2 and (c) Si0.6 Ge0.4 /Si heterostructure on (001)Si0.8 Ge0.2 substrates.

using strained-Si provides a promising alternative for next generation high-performance SiGe CMOS technology (see for example, reviews by Maiti et al [17] and Schaffler [18] and references therein). Since strainedSi provides both larger conduction and valence band offsets and does not suffer from alloy scattering, a significant improvement in carrier mobility can be achieved. However, strained-Si is more difficult to grow compared to strained-Si1−x Gex , as the growth of thick relaxed-Si1−x Gex is difficult without forming a large concentration of defects due to dislocation, and a total thickness of several microns leads to non-planarity, high defect density and surface roughness.

40

Film growth and material parameters

To fully exploit strain as an additional parameter for bandgap engineering, it is necessary to have substrates available that provide the desired in-plane lattice constant for the subsequent pseudomorphic layers. For this purpose, strain-relaxed SiGe buffer layers on an Si substrate are used. In an effort to extend the Si1−x Gex strained layer technology and to search for new materials, experimental work on Si1−x Cx and Si1−x−y Gex Cy alloys was started in the early 1990s and recently on Ge1−y Cy alloys. A different concept for strain adjustment has been suggested by adding carbon into the Si/SiGe material system [19, 20] indicating that the addition of carbon is a promising way for new relaxed buffer concepts with low threading dislocation densities. As the lattice parameter of carbon (3.546 ˚ A) is much smaller than that of Si and Ge, C may be used as a substitutional impurity in the SiGe to decrease the lattice mismatch of the SiGe system. In the case of a ternary alloy such as Si1−x−y Gex Cy , assuming Vegard’s law and for a fully relaxed film, the lattice parameter can be written as aSiGeC = aSi + x (aGe − aSi ) + y(aC − aSi )

(2.3)

where ai is the lattice parameter of the ith component. The third term being negative, it is possible to adjust composition of the alloy to cancel the second and third term leading to an alloy with exactly the Si lattice parameter (i.e., zero net strain). According to equation (2.3), for about 12% Ge in Si and 1% C in silicon, the mismatch is equal and opposite and a strain symmetrized structure with average zero strain may be obtained. Addition of substitutional carbon to the Si1−x Gex material system can provide an additional design parameter in band structure engineering on Si substrates. Since large bandgap variations from 5.5 eV (diamond) to 0.66 eV (Ge) exist, the Si1−x−y Gex Cy system may result in an increase in the bandgap to values greater than those of SiGe and Si, in addition to other interesting properties such as the highest known thermal conductivity (diamond), high hole mobility (Ge) and matured processing technology (Si). The incorporation of C, however, presents difficult challenges due to the large lattice mismatch between C and Si, low solubility of carbon in Si and silicon carbide precipitation. Attempts have been made to form strained layers on Si or Ge substrates containing Sn as a constituent. Synthesis of dislocation-free Siy (Snx C1−x )1−y [21] and growth of quaternary Si1−x−y−z Gex Cy Snz alloy have also been announced [22]. For the last few years, experimental studies on strained-SiGe materials have resulted in a significant progress in the understanding of strain relaxation kinetics and optimization of graded buffer layers with respect to relaxation and surface morphology [23–27]. These parameters are of crucial importance as they are interdependent and are affected by growth temperature, grading rate and composition. It appears that the competition between dislocation nucleation and propagation determines

Strained layer epitaxy

41

Figure 2.5. Cross-sectional transmission electron micrograph and secondary ion mass spectrometry profile of a graded SiGe buffer layer on an Si substrate. (After Schaffler F 1998 Thin Solid Films 321 1–10.)

the final threading dislocation density in the film. The compositional grading is believed to promote propagation while suppressing nucleation of dislocations and leading to reduced amounts of surface strain, thus allowing higher growth temperature [28,29]. Figure 2.5 shows the secondary ion mass spectrometry (SIMS) profile together with a cross-sectional transmission electron micrograph (TEM) micrograph of a graded SiGe buffer layer grown at 750 ◦ C by MBE. It is interesting to note that, close to the substrate interface, the misfit dislocation segments appear quite irregular with respect to spacing and length, whereas long-stretched misfits can be observed in the upper part of B1. B2 remains free of misfit dislocations, as expected, because once B1 is fully relaxed, B2 becomes

42

Film growth and material parameters

strain-free. In fact, the use of a compositionally graded, relaxed, Si1−x Gex buffer layer has been advocated as ‘virtual substrate’ and allows the strain in the film to be tailored at will. (For a detailed discussion on strain adjustment in SiGe buffer layers see, for example, excellent reviews by Schaffler [18, 30].) In the following sections, we discuss the technology of growth of SiGe, SiGeC and strained-Si films. Only a brief review is given for wellestablished results, and readers are referred to the original publications for more detail. We shall examine the deposition of heteroepitaxial films using various reactors in greater depth. As the reactor configurations differ substantially, the advantages and disadvantages of each system are also compared. For a detailed discussion, the reader may refer to a review by Maiti et al [31]. 2.2.

DEPOSITION TECHNIQUES

Many methods exist for depositing low-temperature silicon and Si1−x Gex on silicon. These can be broadly categorized into physical deposition and chemical vapour deposition (CVD) methods. To cope with the difficulties of growing SiGe alloys, molecular beam epitaxy was used at first to produce thin, device quality films. MBE is a physical vapour deposition method and is mostly used for the deposition of III–V compound semiconductors because of the excellent control of layers. Pioneering studies in the mid1980s at AT&T Bell Laboratories, IBM Thomas J Watson Research Center and Daimler–Benz Research Laboratories, Germany, British Telecom, UK, Hitachi and NEC, Japan, among others, used molecular beam epitaxy to show that SiGe alloys could be bandgap-engineered controllably and successfully used to realize a host of novel electronic and photonic devices. MBE allows the fabrication of moderately defect-free heterojunctions. However, MBE not being a production tool, they are only used for demonstration devices. On the CVD side, Gibbons et al [32] at Stanford were one of the first groups to demonstrate high-quality Si1−x Gex on silicon. Towards commercialization of SiGe technology, the development of UHVCVD by Meyerson et al [33] at IBM has been a key step forward which appeared at nearly the same time in the mid-1980s as limited reaction processing CVD (LRPCVD). The UHVCVD reactor combines a standard diffusion furnace with an ultrahigh vacuum and has made the most significant impact in the fabrication of Si/Si1−x Gex HBTs. An excellent review of this technique, and of the devices fabricated using this method of growth, has been published [34]. Other CVD techniques have also been used to grow device quality SiGe layers [35]. Results of Si1−x Gex film depositions at atmospheric pressure CVD by ASM, the only commercial entry in the late 1980s, have been published. These atmospheric CVD results may

Deposition techniques

43

be the most promising for widespread application of Si1−x Gex on silicon heterostructures in a production environment. In the following, we briefly discuss several reactors, the wafer cleaning method, reactor kinetics such as Ge incorporation control, dopant control and selective deposition, and compare the performances of various reactors. Focus is placed on systems that have successfully demonstrated devices and the discussion of the reactors proceeds in order of increasing base pressure. 2.2.1.

Wafer cleaning

Perhaps the most important issue in silicon-based heteroepitaxy is wafer preparation and in situ cleaning prior to epitaxial growth. Poor surface cleaning results in defects at the epitaxial interface that are independent of the lattice mismatch between Si and Si1−x Gex . Conventional silicon homoepitaxial reactors use an in situ high-temperature hydrogen or hydrogen chloride (HCl) ambient to ensure that the surface is free of oxide prior to epitaxial growth. Several approaches to the cleaning problem have been made in the low-temperature deposition of Si1−x Gex on silicon: retaining the high-temperature step and using an ultrahigh vacuum to desorb oxide; using a lamp-heated system to rapidly change from the cleaning temperature to the deposition temperature; using ion bombardment to physically remove the oxide; or using the unique properties of silicon wafers after dipping in liquid hydrofluoric (HF) acid for an H2 -terminated surface. Carbon and oxygen contamination is a common problem in epitaxy. Having a very low base pressure reduces the oxygen and carbon contamination and prevents the formation of a native oxide. Using a load-lock during the wafer load and unload is an additional method of keeping the deposition chamber free of oxygen and carbon from the atmosphere. In silicon homoepitaxy, emphasis is placed on obtaining a high growth rate for high throughput and reducing the autodoping from deposition. In low-temperature silicon and Si1−x Gex epitaxy, autodoping is not a problem and desired layer thicknesses are of the order of 100 nm or less. Precise control of the germanium and dopant concentration profiles becomes more important than high growth rates. Certain device applications need bandgap grading, so Ge incorporation control down to 1–2% is desirable. High and moderate levels of dopants of both types are needed to form different device structures. Quick transitions from high to low and low to high dopant and Ge concentrations are also desired for the formation of lightly-doped spacers for modulation-doped structures. Control of in situ doping profiles down to 50 nm and formation of dopant profiles with peaks below the surface are extremely important for precise vertical dopant profiles and lower junction capacitance. As ion implantation cannot produce these types of profiles, in situ doping is a necessity.

44

Film growth and material parameters

For CVD techniques, gas chemistry and gas purity are very important issues. Silane (SiH4 ) is more reactive than dichlorosilane (SiH2 Cl2 ), so a lower deposition temperature is possible. Even lower deposition temperatures can be achieved by using disilane (Si2 H6 ). 2.2.2.

Molecular beam epitaxy

Molecular beam epitaxy is the growth technique most widely used to grow pseudomorphic Si1−x Gex layers on Si. This is a growth technique where the thermally evaporated molecules of the desired species impinge on an atomically clean heated substrate to form a crystalline solid. The growth technique is intrinsically clean due to UHV growth environment (base pressure ∼10−11 Torr). Cryopumps provide an oil-free evacuation system. MBE is specially suited for the growth of heterostructures requiring precise control of alloy composition, layer thickness and doping. The main characteristics of the MBE growth technique are as follows: • • • • •

very low growth pressure (∼10−9 Torr) allowing atomic layer by layer growth on a atomically clean surface; low growth temperature (350–600 ◦ C) which minimizes solid state diffusion and autodoping; slow growth rate (0.1–5 ˚ A s−1 ) which permits atomically thin-layer growth and better uniformity; multilayer growth capability that allows growth of quantum well and superlattice structures; in situ surface analysis capability such as high-energy electron diffraction (RHEED), Auger electron spectroscopy (AES) and x-ray photoelectron spectroscopy (XPS).

Most MBE systems retain some type of high-temperature cleaning or anneal cycle. The resistively heated substrate can be lowered to the deposition temperature without worry of surface recontamination because of the very low partial pressures of oxygen and carbon in the process chamber. Argon sputter cleaning has been used to etch 10 nm from the surface of the wafer. The etch is followed by a 850 ◦ C anneal before lowering down to the deposition temperature, between 500–750 ◦ C. But sputter cleaning leads to degradation in the minority carrier lifetime by heavy metal contamination sputtered from the chamber onto the surface of the wafer [36]. Because of the UHV conditions, medium temperature (125 mm) may present an insurmountable problem from a uniformity stand point. The inability to in situ dope n-type dopants and to deposit selective layers has been surmounted by using gas source MBE (GSMBE) [37, 40–42]. In GSMBE, Si2 H6 , germane (GeH4 ), diborane (B2 H6 ) and phosphine (PH3 ) are introduced into the deposition chamber instead of evaporating elemental sources. The deposition is controlled by the chemical reaction of the gaseous radicals at the surface of a heated wafer. GSMBE may be described as a hybrid MBE/CVD system, but the deposition pressure is an order of magnitude or more below other CVD systems. At these deposition pressures, gas phase equilibrium may not be achieved, so standard CVD kinetics may not apply. 2.2.3.

UHVCVD

Chemical vapour deposition systems utilize precursor gases that incorporate the desired atoms to the substrate surface. This technique, which has been well known for decades, is in many ways simpler than MBE. CVD is the most advantageous process because it is a high throughput process and also it has in situ doping capabilities. An ultrahigh vacuum chemical vapour deposition reactor consists of a diffusion furnace under ultrahigh vacuum, as shown in figure 2.7. Since the base pressure is comparable to MBE at 10−9 Torr, the advantages of low contamination

Figure 2.7. A schematic cross section of a UHVCVD reactor.

Deposition techniques

47

and prevention of native oxide after loading are similar to MBE. UHVCVD does not use an in situ cleaning step, but relies on the passivation of the surface immediately after an HF dip [43]. A load-lock is also used to prevent exposing the deposition chamber to the atmosphere. The gases SiH4 , GeH4 , B2 H6 and PH3 provide the sources for CVD of p-type and n-type silicon and Si1−x Gex . The deposition pressure is about 1–2 mTorr, with deposition rates around 1–2 nm min−1 . The control of the wafer temperature in a diffusion furnace is extremely good. As a result, a surface rate-limited reaction results in a very uniform layer.

2.2.4.

LRPCVD and RTCVD

Limited reaction processing CVD for silicon homoepitaxy and Si1−x Gex heteroepitaxy was first developed at Stanford University. The unique feature of this system is that the surface reaction is temperature driven, and the temperature of the substrate acts as a switch either to initiate a reaction, terminate a reaction or to change the reaction rate. This technique employs rapid isothermal processing, and the temperature of the substrate (hence the reaction rate) can be rapidly varied (as fast as 350 ◦ C s−1 ). In this system, the base pressure is about 1 mTorr and the gas flows are established at low temperature. Typical gases used include SiH2 Cl2 , GeH4 , B2 H6 , AsH3 and PH3 as source gases. The lamps are turned on to raise the substrate temperature and initiate the deposition, hence the terminology limited reaction processing. As a result of the rapid temperature transitions, the high-temperature in situ cleaning step occurs with hydrogen or hydrogen chloride in a short time, thus reducing the total thermal budget compared to commercial epitaxial deposition systems. Many other research groups have used similar configurations and have adopted the name rapid thermal chemical vapour deposition (RTCVD) instead of LRPCVD because they use gas switching rather than lamp heating to control the reaction. However, rapid doping and compositional transitions are possible by using the lamps as a thermal switch to control the reaction. In situ doping and selective silicon and Si1−x Gex heteroepitaxy have been demonstrated. Si1−x Gex layers need to be deposited at a lower temperature to avoid relaxation and three-dimensional growth problems. The deposition temperature used for Si1−x Gex is about 625 ◦ C and is increased to 850 ◦ C for silicon cap layer deposition, if required. One of the major problems with reducing the temperature, however, is increased oxygen incorporation in the Si1−x Gex layers. The oxygen incorporation problem may be reduced with the use of a load-lock and point-of-use filtration of SiH2 Cl2 .

48 2.2.5.

Film growth and material parameters Very low pressure CVD

The very low pressure CVD (VLPCVD) deposition tool follows the more conventional CVD method with some differences and was first developed at MIT. The deposition chamber is a quartz tube evacuated by a turbopump to a base pressure of 10−8 Torr when cold. The susceptor and wafer are heated by a bank of quartz halogen infrared lamps up to a temperature of 800 ◦ C. The base pressure increases to about 10−7 Torr when the chamber is heated to 800 ◦ C. Process gases during deposition include silane (SiH4 ), germane (GeH4 ), diborane (B2 H6 ), arsine (AsH3 ) and phosphine (PH3 ) as the semiconductor and dopant gas sources. Unlike MBE or UHVCVD, the base pressure in VLPCVD is not low enough to prevent the formation of oxide in the reaction chamber. Therefore, in situ plasma cleaning techniques are needed to prepare the surface for epitaxial deposition. The VLPCVD reactor resembles the UHVCVD deposition kinetics because of the mTorr deposition pressure and SiH4 gas chemistry. Deposition of in situ doped n- and p-type layers of up to 1020 cm−3 dopant concentrations and the deposition of selective epitaxial layers using VLPCVD have been demonstrated [44–46]. 2.2.6.

Remote plasma CVD

Remote plasma enhanced CVD (RPCVD) has also been used for the Si and Si1−x Gex epitaxy [47]. It is a low-temperature process and has been successfully employed for silicon homoepitaxy and Si1−x Gex heteroepitaxy in the temperature range of 150–450 ◦ C. The epitaxial process employs an ex situ wet chemical clean, an in situ remote hydrogen plasma clean, followed by a remote argon plasma dissociation of silane and germane to generate the precursors for epitaxial growth. Boron doping concentration as high as 1021 cm−3 has been achieved in the low-temperature epitaxial films by introducing B2 H6 /He during growth. The growth rate of epitaxial Si can be varied from 0.4–50 ˚ A min−1 by controlling the RF power. The wide range of controllable growth rates makes RPCVD an excellent tool for applications ranging from superlattice structures to more conventional Si epitaxy. Defect densities below the detection limits of TEM (∼105 cm−2 or less) have been reported. The RPCVD process also exploits the hydrogen passivation effect at a temperature below 500 ◦ C to minimize the adsorption of C and O during growth. Low oxygen content ∼ 3 × 1018 cm−3 has been achieved by RPCVD. Silicon and Si/Si1−x Gex films with boron concentrations ranging from 1017 to 1019 have been achieved. 2.2.7.

Atmospheric pressure CVD

Atmospheric pressure reactors hold the greatest promise for widespread commercial use of Si1−x Gex heteroepitaxy of silicon. CVD of epitaxial SiGe

Deposition techniques

49

films from SiH4 –GeH4 –HCl–H2 gas mixtures in an atmospheric pressure CVD process has been reported [48]. IBM [49,50] and ASM [51–53] deposit silicon and Si1−x Gex at atmospheric pressure using SiH2 Cl2 and GeH4 . Layer depositions are carried out in a horizontally arranged, inductionheated and air-cooled conventional epitaxy reactor. RCA precleaned silicon wafers were treated in situ in hydrogen at 1070 ◦ C for 10 min and then HCl gas-etched for a further 10 min. Gas purifiers and load locks are essential in both cases to reduce the oxygen and carbon incorporation. The IBM system uses a silicon carbide susceptor, whereas the ASM system uses a quartz support plate. The deposition kinetics appear similar to the LRPCVD or RTCVD systems since SiH2 Cl2 and GeH4 are used. The IBM system deposited smooth Si1−x Gex layers with up to 44% germanium at 550 ◦ C; they speculate that the chlorine-based gas chemistry suppresses islanding at high germanium concentrations. Unfortunately, no in situ doping data or Si1−x Gex device results have been reported using atmospheric CVD. 2.2.8.

Solid phase epitaxy

From the viewpoint of the compatibility with conventional silicon processing, it may be difficult and extremely costly to merge MBE techniques within a standard bipolar/BiCMOS process. An alternative approach to forming the SiGe layer, is to implant high-dose Ge ions on the silicon substrate using solid phase epitaxy (SPE) [54–56]. This produces an amorphous SiGe layer on the silicon substrate and subsequent thermal annealing is required to induce crystallization. Residual implantation defects due to high-dose germanium implantation may be removed by sequential RTA. This method is fully compatible with the conventional silicon IC manufacturing process and is relatively simple. SPE growth of a SiGe alloy using Ge ion implantation and prolonged furnace anneal has been reported [57–60]. Carbon has a very low bulk solubility in Si and Ge. It is known that the incorporation of elements into Si at concentrations far in excess of their bulk solubility limit is possible by SPE. Thus, SPE provides another possible synthesis route for forming metastable Si1−y Gey or Si1−x−y Gex Cy layers. 2.2.9.

SiGeC film growth

SiGe grown on Si(001) is compressively strained due to the larger lattice constant of germanium compared to silicon. This causes limitations such as a critical thickness for planar pseudomorphic growth. Adding a small amount of carbon into the SiGe material system allows strain adjustment due to the small lattice constant of carbon. Exactly strain compensated SiGeC structures have been shown to exhibit a smaller bandgap than silicon with a considerable valence band offset [61–64]. Si1−y Cy and

50

Film growth and material parameters

Si1−x−y Gex Cy alloys in which C is incorporated substitutionally offer considerably greater flexibility compared to that available in Si/Si1−x Gex heterostructures. In particular, the growth of Si1−x−y Gex Cy alloys with a Ge:C ratio of about 8:1 offers the possibility of fabricating group IV heterostructure devices lattice matched to Si. Due to the smaller lattice constant of carbon, synthesis of carboncontaining alloys with high electronic quality is challenging in part because of the low equilibrium solubility of carbon on the Si lattice. A number of research groups have investigated the maximum amount of carbon that can be incorporated in Si1−x−y Gex Cy by MBE and CVD [62, 65, 66] and also studies have been carried out to determine the fraction of the total carbon concentration that is substitutional on the lattice. An MBE system, equipped with an electron beam evaporator for silicon, a pyrolytic graphite filament for carbon and effusion cells for germanium and boron, has been used for the growth of Si1−x−y Gex Cy samples with Ge contents up to 6% and carbon concentrations up to 0.55% at 450 ◦ C on a thick Si buffer layer. High-quality Si/Si1−x−y Gex Cy heterojunctions have been grown [67] by RTCVD using dichlorosilane (Si2 H2 Cl2 ), germane (GeH4 ) and methylsilane (SiCH6 ) as the precursors of Si, Ge and C, respectively. Using a cold-wall, ultrahigh vacuum, stainless steel chamber with single-wafer-processing capability, epitaxial SiGeC films have been grown at 550 ◦ C with 1–20 sccm of Si2 H6 , 0.1–2 sccm of GeH4 and 0.8– 1.6 sccm of CH3 SiH3 . Carbon incorporations of 2.6 atomic wt.% in Si and 1.4 atomic wt.% in SiGe were obtained [68]. Photoluminescence studies of Si1−x−y Gex Cy and electrical measurements on the Si1−x−y Gex Cy -based bipolar transistors [69] indicate that the incorporation of substitutional C increases the bandgap of Si1−x−y Gex Cy pseudomorphically grown on an Si(100) substrate, with the bandgap increasing by 21–25 meV when 1% C is added. 2.2.10.

Strained-Si film growth

High-quality completely lattice-relaxed SiGe buffer layers have been grown on Si(001) using MBE in the temperature range of 750 and 900 ◦ C and compositional grading of the order of 10% µm−1 or less with final Ge concentrations of about 30%. Xie et al [1] have grown compositionally graded relaxed-Si1−x Gex buffer layers on Si with various composition gradients and temperatures. The authors reported a threading dislocation density in fully relaxed-SiGe buffer layers grown using both MBE and RTCVD in the range of 105 –106 cm−2 [70]. GSMBE [71, 72] has also been successfully employed for the growth of high-quality completely latticerelaxed step-graded SiGe buffer layers on Si(001) in the temperature range of 750 and 800 ◦ C. A more abrupt compositional transience of the SiGe/Si interface is expected in GSMBE-grown QWs, owing to reduced Ge

Thermal stability of alloy layers

51

segregation at the heterointerface [73], than in those grown by solid source MBE where Ge segregation has been recognized as an important issue [74]. Another advantage of GSMBE is that uniform thickness and composition can be obtained without sample rotation. However, GSMBE is associated with autodoping of doping gas impurities, which would affect the device characteristics. 2.3.

THERMAL STABILITY OF ALLOY LAYERS

Since most of the low-temperature grown strained layers are metastable in nature, at a high processing temperature these coherently strained layers can relax by forming misfit dislocations. Even for sub-critically strained (i.e., thermodynamically stable) epilayers, interdiffusion can be important at a high temperature. Since standard silicon processing steps, such as implantation annealing and thermal oxidation, typically exceed the strained layer deposition temperature, thermal stability of strained layers is of utmost importance. The Matthews–Blakeslee curve imposes severe limitations on stable strained-Si1−x Gex layer thickness and germanium concentration. Understanding the relaxation processes of metastable layers is imperative if thicknesses and germanium concentrations greater than the equilibrium curve are needed. Relaxation processes from thermal cycling can be categorized into three mechanisms: temperature dependence of the threading dislocation glide force [75]; dislocation multiplication [76]; and germanium diffusion [77]. In an advanced very large scale integration (VLSI) process, there are two high-temperature steps: (i) thermal oxidation to grow gate oxide and (ii) post implant anneal after ion implantation. For gate oxidation, a temperature between 850–950 ◦ C is typically used, whereas for rapid thermal implant anneal a temperature as high as 1050 ◦ C is used depending on the dopant and dose. These high-temperature process steps impose serious limitations on the thermal budget that can be used to fabricate a device based on these metastable films. The characterization methods used vary due to the detection limits of each technique. Detection methods include plan-view TEM, in situ plan-view TEM, Raman spectroscopy, double crystal diffractometry (DCD) and defect etching. X-ray diffraction analysis is not very sensitive to study dislocation defect densities device grade materials. Capacitance–voltage (C–V ) measurements can be employed to study the carrier confinement in the QW. The SiO2 /Si/SiGe/Si MOS low-frequency capacitance shows a plateau region in inversion. This property of the low-frequency capacitance can be used to qualitatively study the degradation of the material properties due to high-temperature process steps. The plateau in the C–V curve is sensitive to the band offset in the valence band at the Si/SiGe interface [78]. This band offset in the valence band is reduced if the quality of the

52

Film growth and material parameters

heterointerface is degraded either due to the creation of misfit dislocation defects or due to interdiffusion. A few general trends may be established from the published literature on thermal stability of the strained layers: • • • •

2.4.

layers below the Matthews–Blakeslee equilibrium curve appear stable; relaxation of uncapped layers ranges from 600–700 ◦ C; unstrained silicon cap layers improve the thermal stability by extending the point of relaxation to 800 ◦ C. A silicon cap suppresses dislocation nucleation and propagation; and interfacial contaminants play a major role in the number of asdeposited dislocations.

BANDGAP AND BAND DISCONTINUITY

Theoretical calculations based on the electronic structure of heterointerfaces, involving a variety of SiGe layers on Si and Ge substrates, have been employed to predict the band offset [7, 79]. Computations are generally based on local density functional theory, [80], phenomenological deformation potential theory [81] and self-consistent ab initio pseudopotential [82]. Experimental determination of the valence band offset between strained-Si1−x Gex and Si (type I band alignment) has been reported by several workers using different techniques such as x-ray photoelectron spectroscopy (XPS) [83], admittance spectroscopy [84], deep-level transient spectroscopy (DLTS) [85], capacitance–voltage and temperature-dependent current–voltage (I–V ) characteristics [86–88]. In the case of a p-type Si/Si1−x Gex MOS capacitor, as the gate bias is swept negative, holes will accumulate first in the buried Si1−x Gex potential well formed by the valence band offset ∆Ev , rather than at the silicon/oxide interface. Carrier accumulation in the buried well produces a bias region over which there is little change in the capacitance as a function of gate bias. As the gate bias continues to be swept to negative voltage, holes will eventually begin accumulating at the silicon/oxide interface. The capacitance then rises towards the maximum value of Cox , as is usual for an Si MOS capacitor. Band offsets can be extracted by fitting the shape of simulated MOS capacitance–voltage curves in the plateau region to measurements at different temperatures, typically ranging from 100– 300 K [87]. To extract band offsets from C–V measurements of p-MOSFETs, threshold voltages at heterointerface (VTH ) and SiGe/SiO2 interface (VTS ) √ are measured both from the ID –VG characteristics and a plot of ID / gm versus VG curve of a MOS device [89]. The relationship between threshold

Bandgap and band discontinuity

53

voltages and valence band offset (∆Ev ) is given by [90]
VTH = VFB + φTH − qNB xdm and VTS = VFB + φTS −

tSi tox + Si ox

 (2.4)

qNB xdm  1 + H(φH ) Cox

(2.5)

where ∆Ev q 
φTH − φH H(φH ) = ho exp kT /q φTH = 2φF +

(2.6) (2.7)

where 2

ho = 2Si NB kT / (qNB xdm )

(2.8)

where VFB is the flatband voltage, φTH is the potential at threshold at the top Si/Si1−x Gex interface, φTS is the potential at Si/Si1−x Gex interface, φF is the Fermi potential, q is electronic charge, NB is the effective doping concentration in the bulk of the semiconductor, xdm is the maximum depletion layer width in strong inversion, tSi is the Si cap layer thickness, tox is oxide thickness, ox is the oxide permittivity, k is the Boltzmann constant, T is temperature and ∆VT = VTH − VTS . By subtracting equation (2.5) from equation (2.4) and rearranging, a system of two nonlinear equations (2.9) and (2.10) with ∆Ev and φH as unknown is obtained:  2  tSi kT Cox (∆VT − ∆Ev ) −1 ln 1 + Cox ∆Ev = φH −2φF + + −1 (ho ) q Si qNB xdm (2.9) and φH is given by kT φH = φTH − ln q



Si (φH − 2φF ) qNB xdm tSi

2



 −1

− 1 (ho )

.

(2.10)

For an Si/SiGe heterostructure, an experimental valence band offset (∆Ev ) is obtained by iterating equations (2.9) and (2.10) using the values of doping concentration and threshold voltages obtained from the experimental high-frequency apparent doping versus gate voltage characteristics [89], as shown in figure 2.8.

54

Film growth and material parameters

Figure 2.8. Apparent doping versus distance from the Si/SiO2 interface. Data obtained from the high-frequency C–V measurements.

2.4.1.

Si/SiGe

The electronic properties of SiGe materials depend on the substrate material on which they are grown, the germanium mole fraction in the film, and the quality of the film and interface. Although SiGe can be grown on silicon, germanium or even SiGe substrates, the fabrication of SiGe HBTs requires SiGe growth on silicon substrates. When a thin film with a larger lattice constant (e.g., Si1−x Gex ) is grown on a smaller lattice constant substrate (e.g., silicon), the film maintains the in-plane lattice constant of the substrate and is under a biaxially compressive strain. Figure 2.4, described earlier, shows the band offset between a strained-Si0.8 Ge0.2 film grown on silicon and strained-Si on a relaxed-SiGe layer. A discussion of strain-induced splittings within the framework of deformation potential theory has been given by van de Walle and Martin for strained-SiGe [79]. Depending on the composition, the bandgap of Si1−x Gex alloy varies from 1.1–0.7 eV, corresponding to the wavelength range of about 1–1.5 µm. This is a very useful range for discrete optoelectronic devices and for integrated optoelectronics on silicon. Figure 2.9 shows the bandgap difference compared to bulk-Si of unstrained Si1−x Gex [91] and the calculated values of strained-Si1−x Gex [92] at room temperature. The strained-Si1−x Gex curve splits into two lines because of uncertainty in some of the parameters used in the calculations. The

Bandgap and band discontinuity

55

Figure 2.9. Germanium mole fraction and strain-dependent bandgap of Si1−x Gex . The bandgap reduction for compressive (strained-SiGe), tensile (strained-Si) and relaxed cases are shown. (After People R 1986 IEEE J. Quantum Electron. 22 1696–710.)

calculated strained value lies in between the two dotted curves. The calculations for the bandgap of strained-Si1−x Gex were confirmed by Lang [93] using photocurrent spectroscopy. The bandgap depends on the germanium fraction in both cases, but strained-Si1−x Gex experiences a faster drop in bandgap than the unstrained case due to splitting of the valence band degeneracies. Figure 2.9 indicates that strained-Si1−x Gex layers need less germanium to achieve the desired bandgap difference. The bandgap alignment for strained-Si0.8 Ge0.2 on silicon appears in figure 2.9 based on pseudopotential and deformation potential calculations by van de Walle [82] and People [81]. Since the conduction band discontinuity is much smaller than the valence band discontinuity, researchers often ignore the conduction band discontinuity. Quantum confinement of electrons at the Si–strained-Si1−x Gex heterointerface is difficult because of the small conduction band discontinuity. However, the

56

Film growth and material parameters

state of the initial substrate plays a major role in determining the band offsets, as shown in figure 2.9. In fact, calculations show virtually any bandgap alignment is possible [14]. 2.4.2.

Si/SiGeC

Present knowledge about the band structure of tensilely strained-SiGeC ternary alloys on Si001 is limited. Assuming an average band structure for Si1−x−y Gex Cy alloys, Soref [94] has suggested an empirical interpolation between Si, Ge and diamond (C) for the bandgap which increases in the fundamental gap of Si1−x−y Gex Cy layers with increasing y. This result has been contradicted by Demkov and Sankey [95] who have shown that the fundamental gap is reduced when a small percentage of carbon is added to the silicon lattice. This reduction in bangap is in agreement with the photoluminescence measurement data. To describe adequately the observed energy shifts for pseudomorphic carbon-containing layers, strain-induced effects and effects due to alloying should be considered [96]. An estimation for the band offsets and the fundamental bandgap for Si1−x−y Gex Cy alloys (containing up to 3% carbon and 30% Ge concentration) tensile or compressive strained has been reported by Osten [97]. This estimation considers both the band alignment at the interface of two different materials, as well as strain effects. Figure 2.10 summarizes the results for the highest valence band for different tensile and compressive strained-Si1−x−y Gex Cy layers on Si001. The plot shows ∆Ev as a function of the effective Ge or C

Figure 2.10. Valence band offsets for compressively strained Si1−x Gex and Si1−x−y Gex Cy (x = 10%, 20% and 30%, y varies between 0% and 3%) and tensile strained Si1−y Cy and Si1−x−y Gex Cy (y = 1%, 2% and 3%, x varies between 0% and 30%) plotted as a function of the effective lattice mismatch—expressed in ‘effective’ Ge or C concentrations, respectively. (After Osten H J 1998 J. Appl. Phys. 84 2716–21.)

Bandgap and band discontinuity

57

concentration for the compressive or tensile strained layers, respectively. The effective concentration corresponds to the concentration needed for identically strained binary layers. The valence band offset between compressive strained layers and Si is generally much larger than that at the tensile strained layer/Si interface. Photoluminescence studies of Si1−x−y Gex Cy sandwiched between Si layers [62, 63] and electrical measurements on the Si1−x−y Gex Cy -based bipolar transistors [69] indicate that the incorporation of substitutional C increases the bandgap of Si1−x−y Gex Cy pseudomorphically grown on an Si(100) substrate, with the bandgap increasing by 21–25 meV when 1% C is added. Analysis of n- and p-type MOS capacitors indicates that most of the band offset is in the valence band for Si/Si1−x−y Gex Cy heterojunctions with carbon contents less than or equal to 0.8 at.%, i.e., no capacitance plateau region is observed for n-type Si/Si1−x−y Gex Cy /Si capacitors. Figure 2.11 summarizes the extracted valence band offsets as a function of the mismatch to Si for Si/Si1−x−y Gex Cy capacitors with Ge contents of 20 and 30% and carbon contents up to roughly 1 at.%. From the data it is seen that the extracted valence band offset decreases as carbon is added to Si1−x−y Gex Cy . This is consistent with the widening of the Si1−x−y Gex Cy bandgap with the increasing carbon content that has been

Figure 2.11. Summary of valence band offsets extracted from MOS capacitance–voltage characteristics for p-type Si/Si1−x−y Gex Cy capacitors. The offset is extracted by fitting C–V simulations to the measured data. (After Hoyt J L et al 1998 Thin Solid Films 321 41–6.)

58

Film growth and material parameters

observed by photoluminescence measurements [63, 98]. It is also observed from figure 2.11 that, for a given mismatch to Si, the valence band offsets appear to be slightly higher for Si/Si1−x−y Gex Cy than for Si/Si1−x Gex heterojunctions. XPS has been used to measure the conduction and valence band offsets in thick, relaxed Ge-rich Si1−x−y Gex Cy alloys grown by solid source molecular beam epitaxy on (100) Si substrates [99]. It was shown that addition of C increased the valence band maximum of SiGeC by +48 meV %C−1 . The bandgap energies were obtained from optical absorption, and were combined with the valence band offsets to yield the conduction band offsets. For SiGeC/Si heterojunctions, the offsets were typically 0.6 eV for the valence band and 0.38 eV for the conduction band, with a staggered type II alignment. These offsets provide significant electron and hole confinement for device applications. Admittance spectroscopy has been used to measure valence band offsets in Si/Si1−x Gex and Si/Si1−x−y Gex Cy heterostructures grown by MBE. The Si/Si1−x Gex and Si/Si1−x−y Gex Cy samples consisted of 250 ˚ A Si1−x Gex or Si0.796 Ge0.20 C0.004 alternating with 350 ˚ A Si for ten periods, and both layers were doped p-type with dopant concentrations of 7.4 × 1016 cm−3 and 1 × 1017 cm−3 , respectively. These heterostructures were grown on a 2000 ˚ A Si buffer on Si substrates and capped with 2000 ˚ A Si. Measurements of conductance and capacitance as functions of temperature at various frequencies were used to determine the activation energy for thermal excitation over the Si barriers in the p-type multiple quantum well (MQW) structures; band offsets were then obtained from the measured activation energies. For Si/Si0.75 Ge0.25 and Si/Si0.80 Ge0.20 heterostructures coherently strained to Si, valence band offsets of 198 ± 12 and 160 ± 20 meV, respectively, were obtained. For a Si0.796 Ge0.20 C0.004 heterostructure, the valence band offset was 118 ± 10 meV. This value is slightly lower than the valence band offset of approximately 135 meV expected in a Si/Si0.833 Ge0.167 heterojunction, for which the lattice mismatch is the same as in the Si/Si0.796 Ge0.20 C0.004 heterojunction. 2.4.3.

Strained-Si

The heterojunction band offsets (∆Ec , ∆Ev ) in a strained-Si/SiGe heterostructure have been determined from the measurement of threshold voltages of surface channel strained-Si p-MOSFET structures [89, 100]. The extracted experimental valence band offset ∆Ev was found to be 160 meV. Using the valence band offset value, the conduction band offset was obtained from the following equation ∆Ec = Eg (Si1−x Gex ) + ∆Ev (Si1−x Gex /Si) − Eg (strained-Si)

(2.11)

Mobility

59

where Eg (strained-Si) is given by [7, 101] Eg = 1.11 − 0.4x

(2.12)

where x is the Ge concentration in the top part of a completely relaxed SiGe buffer cap. The conduction band offset ∆Ec was found to be 126 meV for a Ge concentration of 0.2 at the top of the relaxed-SiGe layer. 2.5.

MOBILITY

Strain not only modifies the bandgap energy and band alignments but also lowers the effective mass at the band edges and higher mobilities may be expected [102]. In the following, we discuss some experimental work used to determine mobility in strained layers. A more comprehensive discussion of the electron and hole mobility on strain level and the band structure will be given in chapter 4. 2.5.1.

Si/SiGe

Calculations have been made for strained and unstrained Si1−x Gex that have shown an increased electron mobility perpendicular to the growth interface and increased hole mobility parallel to the growth interface for strained layers with increasing Ge content. If an Si1−x Gex strained epilayer is grown on (100) Si, the splitting of the conduction band minimum due to strain reduces the effective mass and improves the electron mobility in a direction perpendicular to the interface by about 50% [103, 104]. These results, however, have been contradicted by other simulations showing that the mobility peaked and then decreased with increasing Ge concentration [105, 106]. If the epilayer is grown on a thick relaxed-Si1−x Gex buffer layer with a higher Ge concentration than in the epilayer, the mobility perpendicular to the layer is reduced while the mobility parallel to the interface increases [107]. As the doping concentration in the semiconductor increases, the strict periodicity of the lattice is disturbed by the existence of the impurity atoms, and various heavy doping effects occur. Besides the dependence of carrier mobilities on the doping concentration and electric field, in alloy semiconductors, mobilities also depend on the composition. It is well known that heavy doping of a semiconductor can reduce the bandgap. In SiGe alloys and strained layers, the combined effect of strain and heavy doping on the bandgap and bandgap narrowing have been reported [8, 108]. 2.5.2.

Si/SiGeC

Given the potential of Si/Si1−x−y Gex Cy , it is imperative to know its carrier transport properties and compare them with those in the Si/Si1−x Gex

60

Film growth and material parameters

system. Two-dimensional modulation-doped hole gases can in principle be fabricated since the band offset at the Si/Si1−x−y Gex Cy interface is predominately in the valence band [109, 110]. To date, however, there are very few reports on the transport properties of holes in the Si/Si1−x−y Gex Cy interface and reports of transport properties are limited to the temperature range of 77–300 K. In the following, we discuss the transport properties of a two-dimensional hole gas in an Si/Si1−x−y Gex Cy modulation-doped structure. Using modulation-doped p-type Si1−x−y Gex Cy QWs, transport properties of boron-doped tensile strained, perfectly strain compensated and compressively strained-Si1−x−y Gex Cy alloy layers on Si(001) substrates have been studied by Duschl et al [111]. The layer sequence of the p-type modulation-doped Si0.85−y Ge0.5 Cy QWs is 200 nm undoped silicon, 20 nm Si0.85−y Ge0.5 Cy , 10 nm Si spacer, a 30 nm thick 2×1018 cm−3 boron-doped Si layer and a 30 nm Si cap. The mobility and charge carrier density were determined in a temperature range 40–300 K using the standard van der Pauw technique at a magnetic field of 0.3 T. At room temperature, acoustic and optical phonon scattering is dominant. However, with the freeze-out of phonons at cryogenic temperatures, ionized impurity scattering becomes dominant in moderately doped semiconductors. In Si1−x−y Gex Cy layers, alloy scattering contributes as a further mechanism. The carrier mobility also depends on the amount of ionized impurities, the germanium and carbon contents. In the following, we discuss the effect of the addition of carbon and germanium on the hole mobility of strained and exact strain compensated Si1−x−y Gex Cy layers. Figure 2.12 shows the room temperature mobility and hole density data. Besides a silicon reference layer (solid square), the first (open squares) starts with the compressively strained Si0.94 Ge0.06 . By adding carbon, while leaving the germanium content constant, the strain is subsequently reduced until exact strain compensation is reached (C = 0.55%). Then the amount of Ge is reduced leading to tensile strained Si0.995−x Gex C0.0055 and finally to Si0.995 C0.0053 . The second sequence (open circles) starts with Si0.96 Ge0.04 and ends at Si0.996 C0.0037 . Considering the Hall mobility (figure 2.12(a)) it is quite evident that additional germanium and carbon reduces the mobility as compared to pure silicon. A general trend is that the room temperature mobility on the compressive strain side is nearly independent of the carbon content. On the other hand, the hole density (figure 2.12(b)) decreases from compressive to tensile strain. Figure 2.13 shows the temperature dependence of the Hall mobility. The reduced mobility of the Si1−x−y Gex Cy alloys compared to pure silicon at room temperature agrees well with the results published in the literature [18, 112, 113]. The reasons for the drop in mobility are the

Mobility

61

Figure 2.12. Room temperature mobility (a) and hole density (b) of pure Si (solid square) and two sample sequences. The first sequence (open squares) starts with Si0.94 Ge0.06 . By adding carbon, while leaving the germanium content constant, the strain is subsequently reduced until strain relaxation is reached Si0.935 Ge0.06 C0.055 then the amount of germanium is reduced leading finally to Si0.995 C0.0053 . The second sequence starts with Si0.96 Ge0.04 and ends with Si0.996 C0.004 . (After Duschl R et al 1998 Thin Solid Films 336 336–9.)

alloy scattering and the enhancement of optical phonon scattering with increasing germanium incorporation due to the smaller optical phonon energy of germanium compared to silicon. But the theoretically predicted and experimentally observed small decrease of the effective mass due to the germanium incorporation, which should lead to a higher mobility, cannot compensate these effects. However, at a low temperature, the Si1−x−y Gex Cy layers show a higher mobility than the silicon due to the lower carrier concentration which leads to a lower effective mass and minor role of the optical phonon scattering at a low temperature. It is seen that

62

Film growth and material parameters

Figure 2.13. Temperature dependence of the hole mobility for the compressively strained Si0.94 Ge0.06 , exact strain compensated Si0.935 Ge0.06 C0.055 and tensile strained Si0.995 C0.053 layers. (After Duschl R et al 1998 Thin Solid Films 336 336–9.)

the room temperature mobility decreases with C and Ge alloy concentration compared to pure Si from 180 to 120 cm2 V−1 s−1 , which is due to the increasing alloy scattering and enhanced scattering at optical phonons. At temperatures below 100 K, a higher mobility is measured for the samples containing C, due to the lower carrier concentration and because ionized impurity scattering becomes dominant. Figure 2.14 shows the mobility and carrier density of a two-dimensional hole gas in the Si1−x−y Gex Cy channel from room temperature to 10 K. The initial decreasing and eventual saturation of hole density indicate the freeze-out of parallel conduction paths and the gradual transfer of holes to the Si1−x−y Gex Cy channels as temperature is decreased. In contrast, the hole mobility increases with decreasing temperature. This is evidence of the formation of two-dimensional hole gas in the Si1−x−y Gex Cy channels. The hole mobility at a low temperature decreases as C is incorporated. For example, at 10 K the mobility with no C is 1800 cm2 V−1 s−1 compared to 1500 and 800 cm2 V−1 s−1 with C levels of 0.3% and 0.6%, respectively. It is not clear if the decrease in hole mobility is due to enhanced alloy scattering with the addition of C, or other factors, such as increased interface roughness or C-related defects. The carrier density saturates at ∼1012 cm−2 at a low temperature, suggesting a complete hole transfer, as intended, from the Si dopant layer to Si1−x−y Gex Cy channels. The variation in the carrier density may be due to imperfect doping control during growth and is not thought to result from a change in the valence band.

Mobility

63

Figure 2.14. Hole density and mobility as a function of temperature for Si/Si1−x−y Gex Cy modulation-doped heterostructures. (After Chang C L et al 1998 Thin Solid Films 321 51–4.)

2.5.3.

Strained-Si

Low-temperature Hall mobility measurements are commonly used to determine the overall quality of a heterostructure and are used to optimize the growth parameters. At low temperature, where the thermal effects and scattering by phonons are dramatically reduced, the electron mobility becomes very sensitive to residual scattering mechanisms due to background charge impurities, roughness and dislocation. Experimental electron mobility data from strained-Si/SiGe modulation-doped structures may be divided into two categories: (i) data from devices with the uniform composition buffer and (ii) devices with the compositionally graded buffer. A detailed discussion on the mobility of electrons and holes in strained-Si may be found in [17]. At room temperature, strained-Si electron mobility values are between 2000 and 2800 cm2 V−1 s−1 for n-channels [118,119], which exceed those in bulk-Si MOSFETs by a factor of four to six. High hole mobilities in excess of 9300 cm2 V−1 s−1 at 4 K in p-type modulation-doped Si/Si0.87 Ge0.13 /Si heterostructures have been reported by Whall et al [120]. For p-MOSFETs, room temperature values between 1400 and 1800 cm2 V−1 s−1 have been reported [121], a factor of six to nine above those of conventional Si pMOSFETs. The dependence of low-field electron and hole mobility on strain level is shown in table 2.2. A more comprehensive discussion of the dependence of low-field electron and hole mobility on strain level and the band structure will be given in chapter 6.

64

Film growth and material parameters

Table 2.2. Experimental low-field electron and hole mobility: dependence on strain level. Ge concentration in the buffer (%) Electron

Strain in Si (%)

Temperature (K)

Mobility enhancement factor

10 20 29 29

0.4 0.8 1.3 1.3

300

[114]

77

1.45 1.67 1.75 1.35

1.33 0.8 0.8 1.0

300 300 77 300

1.2 1.4 2.0 1.5

[115] [116]

Ref.

Hole 29 18 18 25

2.6.

[117]

SUMMARY

In this chapter we have given the background for growing different strained layers using various types of reactors. Basic Si1−x Gex properties and deposition systems have been briefly covered. A variety of methods exist to deposit high-quality alloy layers. In addition to depositing layers with germanium concentrations of at least 15%, control of the germanium profile to within 1% is desirable for bandgap grading. The use of Si/Si1−x Gex heteroepitaxial structures for heterojunction devices is hindered by the lattice mismatch between the two materials. However, strained-Si1−x Gex layers can be deposited on silicon at or above the Matthews–Blakeslee critical thickness curve without interfacial dislocations. Typical bandgap engineering applications may require up to 150 meV bandgap difference. Therefore, the deposition technique must be able to deposit Si1−x Gex layers with germanium concentrations of at least 20%. Layers deposited above the Matthews–Blakeslee curve must contend with thermal relaxation during thermal processing. Unfortunately, the Matthews–Blakeslee critical thickness at 20% germanium is only about 20 nm, and is a limitation for applications requiring higher Ge mole fractions. Partially straincompensated or fully strain-compensated SiGeC films may extend the application areas. Differences in the reactor design, base pressure, gas chemistry and deposition temperature do not appear to limit the ability to deposit device quality group IV alloy layers. MBE is commonly used as a research tool due to its low wafer throughput. UHVCVD appears to have the

Bibliography

65

most advantages in terms of material quality and throughput. Research using LRP/RTCVD reactors have demonstrated device quality material. Extension of the LRP/RTCVD reactor concept to commercial atmospheric CVD reactors holds promise, but additional work in characterizing atmospheric reactors is needed. Furthermore, the throughput of these single wafer atmospheric CVD reactors needs to be examined. The experimental determination of valence band and conduction band offsets (∆Ev , ∆Ec ) in a heterostructure, from the measured threshold voltages (VTH and VTS ) of a p-MOSFET have been discussed. A review of experimental work to determine the variation of mobility in SiGe, SiGeC and strained-Si layers on strain, doping and temperature has also been described.

BIBLIOGRAPHY [1] Xie Y-H, Fitzgerald E A, Monroe D, Watson G P and Silverman P J 1994 From relaxed GeSi buffers to field effect transistors: current status and future prospects Japan. J. Appl. Phys. 33 2372–7 [2] Eaglesham D, Kvam E, Maher D, Humphreys C, Green G, Tanner B and Bean J 1988 X-ray topography of the coherency breakdown in Gex Si1−x /Si(100) Appl. Phys. Lett. 53 2083–5 [3] Van der Merwe J H 1963 Crystal Interfaces. Part II. Finite Overgrowths J. Appl. Phys. 34 123–7 (see also erratum 1963 p 3420) [4] Van der Merwe J H 1972 Structure of epitaxial crystal interfaces Surf. Sci. 31 198–228 [5] Matthews J W and Blakeslee A E 1974 Defects in epitaxial multilayers: I. Misfit dislocations in layers J. Cryst. Growth 27 118–25 [6] Matthews J W 1975 Defects associated with the accommodation of misfit between crystals J. Vac. Sci. Technol. 12 126–33 [7] People R 1986 Physics and applications of Gex Si1−x /Si strained layer heterostructures IEEE J. Quantum Electron. 22 1696–710 [8] Jain S C and Hayes W 1991 Structure, properties and applications of Gex Si1−x strained layers and superlattices Semicond. Sci. Technol. 6 547–76 [9] Bean J C, Feldman L C, Fiory A T, Nakahara S and Robinson I K 1984 Gex Si1−x /Si strained layer superlattice growth by molecular beam epitaxy J. Vac. Sci. Technol. A 2 436–40 [10] People R and Bean J C 1985 Calculation of critical layer thickness versus lattice mismatch for Gex Si1−x /Si strained layer heterostructures Appl. Phys. Lett. 47 322–4 [11] Van de Leur R, Schellingerhout A, Tuinstra F and Mooij J 1988 Critical thickness for pseudomorphic growth of Si/Ge alloys and superlattices J. Appl. Phys. 64 3043–50 [12] Chidambarrao D, Srinivasan G, Cunningham B and Murthy C S 1990 Effects of peierls barrier and epithreading dislocation orientation on

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Chapter 3 PRINCIPLE OF SIGE HBTS

In chapter 2, the technologies involved in SiGe layer growth and the electronic properties of strained-Si1−x Gex layers have been described with special emphasis on those properties which are related to their use as a narrow bandgap material in the base of a heterojunction bipolar transistor (HBT). In this chapter, we examine the underlying physics of the npn SiGe HBT, with particular emphasis on the fundamental differences between the operations of the SiGe HBT and the Si BJT. The concept of a bipolar transistor in which the emitter has a greater bandwidth than the base dates back to the time of Shockley’s original patent on the junction bipolar transistor [1]. A detailed theoretical analysis of the potential performance advantages of this type of device, commonly known as a heterojunction bipolar transistor, was presented by Kroemer in 1957 [2]. However, it was not until 1987 that a functional HBT employing a base layer was demonstrated. The introduction of Ge into the base of an npn Si BJT reduces the bandgap of the SiGe alloy in the p-doped base, relative to Si in the n-doped emitter and collector regions. This bandgap discontinuity creates the heterojunctions needed for the enhanced performance of a SiGe HBT. Before discussing heterojunction action in a bipolar transistor we start by recapping well-established Si BJT fundamentals [3]. If the effect of carrier recombination is initially ignored, the electron and hole injection currents in a forward biased pn junction can be expressed as  


qVbe qADnb In = −1 (3.1) np0 exp Lnb kT  


qVbe qADpe Ip = −1 (3.2) pn0 exp Lpe kT where Vbe is the applied bias, A is the area of the junction, Dnb and Dpe are the minority carrier diffusion constants, Lnb and Lpe are minority carrier 73

74

Principle of SiGe HBTs

diffusion lengths, and np0 and pn0 are the equilibrium minority carrier concentrations in the neutral base and emitter, respectively. In conventional homojunction transistors, the doping concentration in the emitter is considerably higher than in the base, in order to obtain a high injection efficiency. For a typical gain of 100, the emitter must be doped 100 times more heavily than the base. As the doping concentration increases to more than 1018 cm−3 , bandgap narrowing due to heavy doping becomes significant [4]. The following substitutions can be made in equations (3.1) and (3.2) np0 =

n2io Nb

(3.3)

pn0 =

n2ie Ne

(3.4)

∆Ebgn (3.5) kT where nio is the intrinsic carrier concentration and ∆Ebgn represents the bandgap reduction in the emitter due to heavy doping. When bandgap narrowing is included, the current gain β becomes 
Ne Lpe Dnb −∆Ebgn . (3.6) βSi = exp Nb Lnb Dpe kT n2ie = n2io exp

In an HBT with a narrow bandgap base, the bandgap of the emitter is larger than the base and therefore the injection efficiency can be made very high, even if the base is doped more heavily than the emitter [2, 5]. In a SiGe HBT, a narrow bandgap SiGe base is used and the bandgap difference between the emitter and base is ∆Eg (x) = Eg,Si − Eg,SiGe (x). Due to its smaller bandgap, the intrinsic carrier concentration in the SiGe base increases. The difference between the HBT and BJT is that the concentration of the injected electrons is much higher (several orders of magnitude) into the base due to lower conduction band barrier. The current gain for a SiGe HBT becomes 
∆Eg (x) βSiGe = βSi exp . (3.7) kT This means that the collector current will be much higher than in a similarly doped BJT, by a factor of exp(∆Eg (x)/kT ), while the base current is not affected. In a SiGe HBT, the bandgap difference ∆Eg (x) can be made much larger than kT . For example, a Ge fraction x = 0.2 in the base yields a bandgap difference of more than 170 meV. Therefore, the current gain of the HBT can be made large, irrespective of the doping ratio in the emitter and the base. However, the real advantage of the HBT

Energy band

75

is not to achieve a very high current gain, but to trade it against a high base doping, necessary to reduce the base resistance. High values of maximum oscillation frequency and low values of gate delay τd (for digital switching applications) can be obtained in HBTs [6,7]. Base resistance is an important parameter in determining fmax . In a welldesigned HBT, a value of 50 for β is usually sufficient, so emitter injection efficiency can be traded for increased doping in the base. Increased base doping gives rise to reduced base resistance which is also desirable in helping to avoid punch-through as the base–collector voltage is increased. High base doping may contribute to the onset of tunnelling current at the emitter–base junction. This can be avoided by deliberately reducing the doping concentration in the emitter. Indeed, in the HBT, it is in principle feasible to consider the possibility of interchanging collector and emitter, providing additional advantage in some digital circuits. Many of the specific issues involved in transistor design are more fully covered in chapter 4. For the remainder of this chapter, we focus in more detail on device physics, showing how the incorporation of germanium significantly changes the physics of the base region and the emitter–base and base– collector junctions. 3.1.

ENERGY BAND

The first step in understanding how a heterostructure device will operate is to consider the energy band diagram. For homostructures, the electron affinity and bandgap are position independent, and there is no need to worry about the reference level. But for heterostructures, a reference level is essential, normally taken to be the field-free vacuum level. To draw energy band diagrams for devices with a position-dependent alloy composition, it is essential to know how the bandgap varies with position and also the band line up at compositional junctions. Figure 3.1 shows the band diagram of an npn bipolar transistor. In forward active mode, the emitter–base junction is forward biased by the input voltage Vbe , and the base–collector junction is reverse biased by the output voltage Vbc . The collector current Ic consists of electrons which are injected from the n-emitter into the thin p-base, move through the base by drift and diffusion, and are collected in the n-collector layer (a drift field in the base can be caused by either a doping or a bandgap gradient). The number of electrons injected into the emitter side of the base is determined by the height of the potential barrier, ∆Vn , in the conduction band between the emitter and the base, which can be controlled by the input voltage Vbe . The dominant component of the base current Ib consists of holes which are injected from the p-base into the n-emitter (no holes are injected into the n-collector in forward active mode because the base–collector junction is reverse biased). The number of holes injected into the emitter is determined

76

Principle of SiGe HBTs

Figure 3.1. Simulated band diagram of an npn bipolar transistor. (After Prinz E J 1992 Base transport and vertical profile engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton University.)

Figure 3.2. Simulated band diagram of a narrow bandgap base npn heterojunction bipolar transistor. (After Prinz E J 1992 Base transport and vertical profile engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton University.)

Terminal currents in a SiGe HBT

77

by the potential barrier ∆Vp in the valence band between base and emitter, which is also controlled by the input voltage Vbe . The key idea of an HBT is to lower the potential barrier seen by the carriers responsible for the output current (electrons in npn devices) compared with the one seen by the carriers constituting the input current (holes in npn devices), thereby increasing the ratio of output to input current, the common emitter current gain of the HBT [5]. This is done by fabricating the emitter and the base using materials having different bandgaps. Depending on the layer in which the bandgap is changed compared to a homojunction device, two HBT configurations can be distinguished: (i)

in a narrow bandgap base HBT, the bandgap in the base is lowered thereby increasing the collector current, whereas (ii) in a wide bandgap emitter HBT, the bandgap in the emitter is increased compared to the base, resulting in a lower base current. In both cases, the common emitter current gain is increased by a factor proportional to exp(∆Eg /kT ) if spike and notch effects at the heterojunctions are neglected. Note that in an HBT, where the emitter bandgap is larger than that in the base, the current gain β should increase when the temperature is lowered, making it possible to operate the transistors more effectively at cryogenic temperature. 3.2.

TERMINAL CURRENTS IN A SIGE HBT

In this section we consider a comparison of a SiGe HBT with the equivalent Si BJT. For the purpose of comparison, it is assumed that both the silicon bipolar and the SiGe HBT are identical, other than the fact that germanium is present in the SiGe HBT. Figure 3.3 shows how the base bandgap changes are brought about by the incorporation of Ge into the base. In thermal equilibrium, the Fermi level, EF , is constant across the junction. Therefore, for an abrupt Si/SiGe interface, the difference in bandgap between the emitter and base causes discontinuities to exist at the conduction and valence bands, shown in figure 3.3 as ∆Ec and ∆Ev , respectively. Also, the total discontinuity, ∆Ec + ∆Ev , is equal to the base bandgap difference between the silicon emitter and SiGe base, ∆Egc−b . In SiGe, the valence band discontinuity, ∆Ev , tends to be considerably larger than the conduction band discontinuity, ∆Ec . Figure 3.4 shows the band diagram in forward active mode, where in this more general case, the germanium concentration is graded linearly across the base, increasing from emitter towards the collector. With the presence of germanium, the electron injection barrier from emitter to base, ψn , is reduced and there will be greater electron injection from emitter to base. This means an increase in the collector current. However, the hole

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Principle of SiGe HBTs

Figure 3.3. Effect of strained-SiGe layer on the bandgap of emitter–base junction for an abrupt Si/SiGe interface. (After Tang Y T 2000 Advanced characteristics and modelling of SiGe HBTs PhD Thesis University of Southampton.)

injection barrier from base to emitter, ψp , remains the same as in a silicon bipolar transistor. Therefore, the hole current from base to emitter, which is the main contributor to base current, remains the same. Hence, silicon bipolar transistors and SiGe HBTs tend to have approximately the same base current. The following derivations [8], used to show enhancements resulting from Ge incorporation in the base, closely follow derivations contained in [9]. We consider the most general case of germanium grading and show how constant grading may be treated as a particular case for which the theoretical treatment is still valid. The collector current of a graded SiGe HBT can be obtained by altering the collector current equation of a silicon bipolar transistor. Assuming uniform base doping for the device, the silicon bipolar collector current density, Jc,Si , for uniformly-doped base can be

Terminal currents in a SiGe HBT

79

Figure 3.4. Bandgap energy diagram across a graded SiGe HBT in forward active mode of operation. Of and Wf are the electrical boundaries of the neutral base region on the emitter and collector sides of the base, respectively. (After Tang Y T 2000 Advanced characteristics and modelling of SiGe HBTs PhD Thesis University of Southampton.)

written using the Moll–Ross relation [10]  Jc,Si = q (exp (qVbe /kT ) − 1) =

Wf

Of

Nb (x)dx Dnb (x)n2ie (x)

−1

 qDnb n2io app exp ∆Egb /kT [exp (qVbe /kT ) − 1] Wb Nb

(3.8) (3.9)

where q is the charge on an electron, Vbe is the forward biased emitter– base voltage, k is the Boltzmann constant, T is temperature, Of and Wf are the base electrical junction positions at the emitter and collector side of the neutral base, in forward active mode, Wb is the neutral base width, Nb (x) is the positional-dependent base doping concentration, Dnb (x) and nie (x) are the positional-dependent base electron diffusion coefficient and effective intrinsic carrier concentration, respectively, nio is the intrinsic

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Principle of SiGe HBTs

carrier concentration in the absence of heavy doping effects, Nb is the app base doping, and ∆Egb is the base apparent bandgap narrowing due to the heavy doping effect. In equation (3.8), nie (x) accounts for the effective intrinsic carrier concentration across the base and is a function of the bandgap. For a graded SiGe HBT, bandgap changes across the base, as depicted in figure 3.4, can be accounted for [9]   app ∆Egb ∆Eg,SiGe (grade)(x/Wb ) ∆Eg,SiGe (Of ) 2 2 nie (x) = γnio exp + + kT kT kT (3.10) where [11] (Nc Nv )SiGe γ= ≈ 0.4 (3.11) (Nc Nv )Si and neutral base width, Wb = Wf −Of . The term Eg,SiGe (grade) represents the bandgap difference across the neutral base. The term ∆Eg,SiGe (Of ) represents the bandgap difference at the emitter side of the neutral base, Nc and Nv are the density of states in the conduction and valence bands, respectively. Putting equations (3.8) and (3.10) together and integrating, the most general form for the SiGe HBT collector current density, Jc,SiGe , incorporating both bandgap offset and grading, can be written as [9]    app 2 ∆Egb qV n qD nb be io + −1 exp Jc,SiGe = ζ¯γ¯ Wb Nb kT kT (3.12)   exp ∆Eg,SiGe (Of )/kT ∆Eg,SiGe (grade)   × kT 1 − exp − ∆Eg,SiGe (grade)/kT where ζ=

(Dnb )SiGe >1 (Dnb )Si

(3.13)

where the symbol ‘–’ refers to a position averaged quantity. The ratio of (Dnb )SiGe to (Dnb )Si accounts for the strain enhancement of the minority carrier electron mobility with increasing germanium content [12]. Taking the ratio of Jc,SiGe to Jc,Si , the collector current enhancement due to bandgap engineering can be estimated by, exp (∆Eg,SiGe (Of )/kT ) Jc,SiGe ∆Eg,SiGe (grade) ≈ ζ¯γ¯ kT 1 − exp (−∆Eg,SiGe (grade)/kT ) Jc,Si

(3.14)

where we can draw important conclusions by considering the magnitudes of the terms in the above equation in giving rise to collector current enhancement, i.e.,

Terminal currents in a SiGe HBT • • •

81

ζ¯ > 1 defines the effect of the difference in diffusivity/mobility between SiGe and  Si;

∆Eg,SiGe (Of ) > 1 defines the effect of basic heterojunction action exp kT due to bandgap shrinkage in the base; and ∆Eg,SiGe (grade)/kT   > 1 defines the effect of bandgap grading 1−exp −∆Eg,SiGe (grade)/kT across the base.

It should be pointed out that equation (3.12) applies in the general case. In the limiting case, where there is no grading, the latter term tends to unity as ∆Eg,SiGe (grade) tends to zero, and the overall expression for collector current is still valid in a much simplified form. Even though γ¯ < 1 [11], exp(∆Eg,SiGe (Of )/kT ) increases the SiGe HBTs collector current exponentially for a finite germanium content. For a SiGe HBT having a germanium concentration varying from 4% at the emitter–base junction to 12% with a trapezoidal shape across the base (see figure 3.5), a collector current enhancement by a factor of 4.5 has been reported [9]. The base current in a bipolar transistor, consists of several components. In the emitter, holes can recombine with electrons at the

Figure 3.5. Uniform (flat), triangle, and trapezoid Ge profiles in the base of a SiGe HBT. (After Harame D L et al 1995 IEEE Trans. Electron Devices 42 455–68.)

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Principle of SiGe HBTs

emitter surface, in the neutral emitter, or in the wide bandgap part of the emitter–base space-charge region. In the narrow bandgap base, electrons can recombine with holes in the narrow bandgap part of the emitter– base space-charge region, or in the neutral base. An additional source of collector and base current consists of electron–hole pairs created by avalanche multiplication or thermal generation in the base–collector spacecharge region. The various base current components can be distinguished by their dependence on emitter–base voltage, base–collector voltage, and temperature. If both base and emitter material have a high minority carrier lifetime, which is usually the case in SiGe HBTs, the base current is dominated by emitter surface recombination current or the current in the neutral emitter. Since the boundary conditions for the injected minority carriers into the emitter remain the same as in the homojunction, the reverse injected hole current can be written as Jp =

 qDpe n2ie,Si qVbe /kT e −1 . Nde We

(3.15)

Equation (3.15) assumes a short, uniformly-doped emitter. For emitters with a short  minority carrier lifetime, We is replaced by the diffusion length Lpe = Dpe τp where Dpe and τp are the respective minority carrier diffusivity and lifetime in the emitter region, giving Jp =

qDpe n2ie qVbe /kT e Nde Lpe

(3.16)

where Nde and Lpe are the emitter doping density and hole diffusion length, respectively. Equation (3.16) implies that Jp has an ideality factor of unity. The potential barrier for hole injection into the emitter is the same for both the homojunction and the narrow bandgap heterojunction device, which implies that this component of the base current should be identical in the two devices, if they have similar emitters. This has indeed been observed in experimental SiGe HBTs and is evident from figure 3.6. Auger recombination deals with the heavy doping effects. This bandto-band recombination mechanism occurs at dopant concentrations beyond 1019 cm−3 [13]. One of the main objectives in SiGe HBT design is to lower the base resistance by increasing the base doping concentration. The lower base resistance improves high-frequency performance. In the highly-doped emitter of a BJT, the net effect of Auger recombination is a lower effective lifetime in the emitter, leading to a shortened diffusion length and increased base current. In a device simulator this effect is easily included as an extra term in the current continuity equations. Figure 3.6 shows the collector and base currents of a flat-base SiGe HBT (x = 0.2) compared to the corresponding Si homojunction device.

Transit time

83

Figure 3.6. Room temperature Gummel plots of a flat-base SiGe HBT and silicon control device with similar base sheet resistances, and emitter areas, showing the increased collector current due to the narrow bandgap base. (After Prinz E J 1992 Base transport and vertical profile engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton University.)

In the Gummel plot, the collector current of an ideal bipolar transistor should be proportional to eqVbe /kT , corresponding to an inverse slope of approximately 60 mV per decade of collector current at room temperature. The ∼50× increase in the collector current (and the current gain) of the HBT compared to the homojunction transistor is due to the narrower bandgap in the base, since both the devices have the same integrated base dopant concentration. Since the base current of silicon and SiGe HBTs are virtually identical, the current gain enhancement due to germanium incorporation is similar to the collector current enhancement. Therefore, the superior current gain potential of a SiGe HBT can be traded off for an increased fmax and reduced base resistance, leading to higher power gain, faster switching speed and a lower noise figure. 3.3.

TRANSIT TIME

Bandgap grading across the base creates a drift electric field that accelerates the electron minority carriers through the base. The graded electric field reduces the amount of base stored charge per unit collector current. This reduces the energy and time required to move charge in and out of the base during transients. As a result, the base transit time, τb , decreases.

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Principle of SiGe HBTs

In any bipolar transistor, the base transit time for constant base doping can be written as [10]  Wf 2 Wf nie (z) Nb (y)dy Qb τb = dz (3.17) = Ic Dnb (y)n2ie (y) Of Nb (z) z where Qb is the total base stored charge and Ic is the collector current. Putting equation (3.10) into (3.17) and integrating, τb,Si [13,14] and τb,SiGe [9] become: Wb2 τb,Si = (3.18) 2Dnb kT W2 τb,SiGe = ¯ b (3.19) ζDnb ∆Eg,SiGe (grade)

  −∆Eg,SiGe (grade) kT 1 − exp . × 1− ∆Eg,SiGe (grade) kT Taking the ratio of τb,SiGe /τb,Si gives: kT 2 τb,SiGe (3.20) = ¯ τb,Si ζ ∆Eg,SiGe (grade)

  −∆Eg,SiGe (grade) kT 1 − exp . × 1− ∆Eg,SiGe (grade) kT For a finite germanium grading of more than 1% at room temperature, τb,SiGe /τb,Si will be less than 1 and therefore the SiGe HBT base transit time will be shorter than the silicon bipolar. The cut-off frequency, fT of a bipolar device, as explained in section 3.7, is a function of base transit time, implying that bandgap grading will also increase the usable frequency of operation of the device. An additional benefit of incorporating Ge into the base is a reduction in emitter transit time τe , compared to a silicon BJT. Since τe is inversely proportional to the collector current, for a given base doping profile, the enhancement in τe , is obtained from the inverse of (3.14) as τe,SiGe Jc,Si 1 − e−∆Eg,SiGe (grade)/kT ≈ = . ∆E (grade) ∆Eg,SiGe (0)/kT τe,Si Jc,SiGe e ζ¯γ¯ g,SiGe kT

(3.21)

The emitter transit time can potentially be a limiting factor in HBTs which include a low-doped emitter region to avoid tunnelling current from base to emitter. Such structures are discussed in chapter 4. The effect of base and emitter transit times on ac performance is more fully discussed in section 3.7.

Early voltage 3.4.

85

EARLY VOLTAGE

For analogue circuit applications, a high value of the product of current gain and Early voltage (βVA ) is desirable. There are several physical effects which cause the collector current to increase with collector–emitter voltage for a constant base current. The most important of these is the increase of the collector current caused by a decrease of the width of the neutral base with base–collector reverse bias [15]. Output conductance is a measure of collector current variation with base–collector reverse bias. In figure 3.8, the base–collector depletion region widens and reduces the neutral base width as the reverse biased base–collector voltage increases, while keeping a fixed emitter–base voltage. Reduction of the neutral base width leads to an increase in the gradient of the injected electron distribution in the p-type base. Since the electron diffusion current across the base is directly proportional to this gradient, the collector current will increase. A low output conductance is desirable to achieve invariant output current in low-frequency analogue applications. The Early voltage, VA , an indicator of the extent of base width modulation, can be obtained by extrapolation of the output characteristics. With reference to figure 3.7, the Early voltage (ignoring recombination in the base) is given by 
 ∂Vce ∂Wb ∂Vce VA ≈ Jc . (3.22) = Jc ∂Jc ∂Wb ∂Jc The rate of change of the neutral base width Wb with respect to the

Figure 3.7. Definition of the Early voltage VA . The linear parts of the output characteristics of a bipolar transistor are extrapolated to zero collector current.

86

Principle of SiGe HBTs

Figure 3.8. Minority carrier distribution in an npn transistor for increasing base–collector reverse bias voltage in forward active mode. np (x) is the electron concentration in the p-type base. (After Tang Y T 2000 Advanced characteristics and modelling of SiGe HBTs PhD Thesis University of Southampton.)

base–collector voltage, for constant emitter–base voltage, is given by ∂Wb Cjc =− ∂Vbc qNb (Wb )

(3.23)

and the change of the collector current density with respect to the base width is   Nb (Wb )/ n2ie (Wb )Dnb (Wb ) ∂Jc (3.24) = −Jc  Wb   . ∂Wb Nb (x)/ (n2 (x)Dnb (x)) dx 0

ie

For a constant base profile, combining equations (3.23) and (3.24) one gets   qn2 (Wb )Dnb (Wb ) Wb  VA = ie Nb (x)/ n2ie (x)Dnb (x) dx (3.25) Cjc 0 where n2ie (Wb ) denotes the intrinsic carrier density at the end of the neutral base on the collector side. Combining equation (3.25) with the standard equation for bipolar current gain  −1 Wb  2  q p(x)/ nie (x)Dn (x) dx (3.26) β= Jb0 0

Early voltage

87

and assuming p(x) = Nb (x) yields an important figure-of-merit for bipolar transistors, βVA , given by βVA =

 q2  2 nie (Wb )Dn (Wb ) . Jb0 Cjc

(3.27)

The following three points are significant: • • •

βVA is a strong function of Ge concentration at the end of the neutral base (base–collector junction); βVA is larger in SiGe than in silicon due to the larger n2io (Wb ) value in SiGe; and to maximize βVA , the base–collector junction capacitance should be as low as possible.

Harame et al [9] showed that Early voltage enhancement of a graded SiGe HBT can be expressed as  
1 − exp (−∆Eg,SiGe (grade)/kT ) ∆Eg,SiGe (grade) VA,SiGe . ≈ exp VA,Si kT ∆Eg,SiGe (grade)/kT (3.28) Combining equations (3.28) and (3.14), the enhancement in βVA at constant emitter–base voltage can be shown as βVA,SiGe ≈ γζe∆Eg,SiGe (Of )/kT e∆Eg,SiGe (grade)/kT βVA,Si

(3.29)

which is significantly greater than unity for a profile with finite Ge content. For finite germanium grading, ∆Eg,SiGe (grade), of more than 1% across the base, τb,SiGe /τb,Si , ratio will be larger than 1. Therefore, grading Ge across the neutral base improves not only base transit time, but also Early voltage. Furthermore, since current gain is essentially enhanced by the difference in bandgap at the emitter–base junction and Early voltage by Ge grading across the base, respectively, the composite product βVA is significantly enhanced by up to two orders of magnitude. Figure 3.9 shows the SiGe/Si ratio for the three parameters of interest—current gain, Early voltage, and the product of current gain times Early voltage [9]. This figure needs to be interpreted with some care, as the integrated Ge dose across the base has been kept constant in order to provide a meaningful comparison. In this figure, when ∆Eg,Ge (grade) = 0, a pure Ge box profile of 8.4% Ge is implied, while ∆Eg,Ge (grade) = 125 meV, (the x-axis limit in figure 3.5), implies a purely triangular profile from 0–18.6% Ge. Any other grading between these limits indicates the corresponding trapezoidal Ge profile. The triangular profile has the largest Early voltage and gain–Early voltage product. The Ge box profile has an

88

Principle of SiGe HBTs

Figure 3.9. Early voltage and current gain Early voltage products. (After Harame et al 1995 IEEE Trans. Electron Devices 42 455–68.)

exponentially increased current gain, by the factor exp(∆Eg,SiGe (Of )/kT ), but the same Early voltage. The βVA product is strongly influenced by base–collector capacitance Cbc , but there is always a trade-off between the separate terms. If β is increased, by reducing the base doping, VA will decrease, so it is therefore not desirable to have excessively high current gain. In a SiGe HBT with a box Ge profile, the improvement in βVA is limited by critical thickness considerations. For example, for a base width of about 500 ˚ A, the Matthews–Blakeslee theory predicts a maximum Ge concentration of about 7% corresponding to a bandgap difference of 55 meV compared to Si. This bandgap difference translates into ∼5× improvement in the βVA product. In a graded base SiGe HBT, insertion of a very thin Si1−x Gex region between base and collector will reduce base–collector capacitance and increase Early voltage, while leaving the current gain virtually unchanged [16]. The thickness of this Si1−x Gex layer has to be sufficient to include the base edge of the base–collector depletion region even at maximum reverse bias Vbc . Since the equilibrium critical thickness decreases with increasing Ge concentration in a strained-Si1−x Gex layer, the improvement possible in the βVA product of a graded-base HBT is greater compared to that of β alone in a box profile HBT. A simple structure to investigate the β versus VA trade-off in graded base HBTs is a stepped base transistor, where the base consists of two separate p-doped layers with constant bandgap in each layer. Figure 3.10 shows the calculated band diagrams and measured collector current

Early voltage

89

Figure 3.10. Calculated band diagrams and measured collector current characteristics showing the effect of the position of the biggest bandgap region in the base on the output resistance of SiGe HBTs. The devices had an emitter area of 62 × 62 µm. (After Prinz E J 1992 Base transport and vertical profile engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton University.)

characteristics for two stepped-base devices. Both devices had similar current gains because of the similar width and height of the highest barrier for electrons in the base. The output resistance of device in which the narrow gap layer was located at the base–collector junction, however, was vastly increased compared to device which had its narrow gap layer at the emitter–base junction. Prinz and Sturm [16] have experimentally demonstrated βVA products of 168 000 using a two step 14–28% germanium base. State-of-the-art silicon bipolar processes have a βVA product of 6000. The effects of base dopant out-diffusion leading to a base–collector

90

Principle of SiGe HBTs

heterojunction barrier on the Early voltage have also been reported [17]. A more complete discussion on the effects of parasitic barriers is given in the following section. 3.5.

HETEROJUNCTION BARRIER EFFECTS

The computed conduction band offset in the silicon to strained-Si1−x Gex heterojunction is small (typically 20 meV) [18]. If a significant conduction band offset exists, a reduction in the gain may result. In a heterostructure, compositional grading across the heterojunction may be used to eliminate the conduction band spike. In the case of an Si/SiGe/Si system, the conduction band spike is not a severe problem if the emitter dopant concentration is larger than the base doping concentration, as the band bending appears on the side with lower doping. In an npn transistor any small conduction band spike may be disregarded. However, it is not true for the pnp transistor, as the spike will be large in this case because valence band offsets are much larger than the conduction band offsets. At high current densities or high forward bias, the transport of carriers is strongly influenced by the potential barrier that develops due to alloy grading potential of the heterojunction. A retrograde Ge profile near the collector junction also creates a barrier to the flow of the minority carriers [19]. Another type of parasitic barrier arises due to the boron out-diffusion from the base. Extension of base dopant beyond the Si1−x Gex region occurs during thermal cycling, or improper control of the as-deposited profile [20, 21]. Even small amounts of boron out-diffusion from a heavilydoped Si1−x Gex base into the Si emitter and collector cause parasitic barriers in the conduction band which can drastically reduce the collector current enhancement. Shafi et al [22] fabricated a SiGe HBT with a very narrow base width of 214 ˚ A, doped with a boron concentration of 5 × 1019 cm−3 and a Ge concentration of 15%. The width of emitter was 0.3 µm doped with a uniform As concentration 1018 cm−3 , while the doping in the collector was 3 × 1016 cm−3 . The collector current enhancement factor was 13, while the base current was also found to increase sixfold. The authors attributed this increase in base current to a either very low lifetime near the collector region in the base, or a parasitic barrier at the base–collector junction. Shafi et al [23] have also reported the collector current degradation due to out-diffusion of boron and creation of parasitic barriers. The minority carrier concentration in the base increases due to the barriers and this will increase the recombination and base current, irrespective of the value of the lifetime of the minority carriers. Out-diffusion of boron into the collector results in the formation of a parasitic conduction band barrier, as illustrated in figure 3.11, where an exponential out-diffusion tail region of varying diffusion length, LD ,

Heterojunction barrier effects

91

Figure 3.11. Simulation of band diagram and electron concentration for a SiGe HBT with the doping profile of (a). Note the exponential dopant out-diffusion tail (diffusion length LD ) into the Si collector region. The band diagram (b) shows the parasitic conduction band barrier at the Si1−x Gex /Si interface. (c) and (d) show conduction and valence bands, respectively, at the base–collector junction for various diffusion lengths LD . (e) The parasitic conduction band barrier causes a deviation from the triangular electron profile in the base leading to increased minority carrier charge storage in the base even as Ic decreases. (After Prinz E J 1992 Base transport and vertical profile engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton University.)

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Principle of SiGe HBTs

Figure 3.12. Simulation of normalized collector current enhancement versus inverse temperature for various values of LD . (After Prinz E J 1992 Base transport and vertical profile engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton University.)

extending into the Si collector region, has been superimposed upon an Si0.8 Ge0.2 base with a constant doping of 1019 cm−3 . Even a small amount of boron out-diffusion (LD ∼ 30 ˚ A) causes a large parasitic barrier for electrons at the base–collector junction (barrier height ∼85 meV), as shown in figure 3.11(c). This barrier leads to increased minority carrier storage in the base significantly impeding electron diffusion through the base, increasing neutral base recombination and degrading the collector current, as shown in figure 3.11(e). The parasitic barriers thereby reduce the potential enhancement in current gain once the diffusion length exceeds 11 ˚ A, as shown in figure 3.12. With increased minority carrier charge storage in the base, as shown in figure 3.11(e), the parasitic barriers increase the base transit time, τb , because of the increase in electron charge and the decrease in collector current Ic , as the ideal triangular electron profile for electron concentration in the base is replaced by a trapezoidal profile. This effect, demonstrated by simulation, was experimentally observed by Pruijmboom et al [24] in high-frequency measurements of SiGe HBTs. 3.5.1.

Effect of undoped spacer layers

The deleterious effect of base dopant out-diffusion from the Si1−x Gex base into silicon emitter and collector can be limited by inserting thin undoped Si1−x Gex layers on both sides of the base [20, 21]. These

Heterojunction barrier effects

93

Figure 3.13. Doping profile of HBT structure with undoped SiGe spacer layers. (After Prinz E J 1992 Base transport and vertical profile engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton University.)

Figure 3.14. Simulated boron doping profile (SUPREM III) for various anneals. If the Si1−x Gex layer thickness is increased by adding 150 ˚ A thick intrinsic Si1−x Gex spacer layers on both sides of the base, the diffused boron profile is still contained inside the Si1−x Gex layer for a temperature below 800 ◦ C. (After Prinz E J 1992 Base transport and vertical profile engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton University.)

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Principle of SiGe HBTs

spacers have to be wide enough to contain the tail regions of the boron out-diffusion. Inevitably, this change increases the overall width of the strained-Si1−x Gex layer, making the structure more likely to relax by forming misfit dislocations at the interface. To demonstrate the effect of thermal cycle on SiGe HBT performance, consider the device structure shown in figure 3.13 with a base doping of 5×1019 cm−3 , a base width of 300 ˚ A and box Ge profile (x = 0.18), leading to a base sheet resistance of ∼800 Ω/square. The 1017 cm−3 collector doping represents a trade-off between breakdown voltage BVceo and the onset of high level injection in the collector (Kirk effect) [25, 26]. If the base is doped above 2 × 1018 cm−3 a lightly-doped n-Si spacer has to be inserted between base and emitter to prevent tunnelling leakage in the emitter–base junction [27]. Figure 3.14 shows calculated doping profiles for a 10 min anneal at various temperatures and figure 3.15 the corresponding band diagrams for a structure (a) without and (b) with 150 ˚ A thick spacers. Note the absence of parasitic barriers in the device with spacers up to an annealing temperature of 850 ◦ C. However, increase in the thermal budget of the process leads to a strong degradation of the collector current. The intrinsic spacers, therefore, substantially improve the tolerance of the device structure for the thermal budget of the process. These simulations show that in the design of a SiGe HBT process, intrinsic Si1−x Gex spacer layers on both sides of the base, should be considered according to the thermal budget of the process. The critical thickness limitation of the strained-Si1−x Gex layer, however, limits the total permissible thickness of the base including the spacer layers. 3.6.

HIGH LEVEL INJECTION

In a bipolar transistor, two different type of high level injection (HLI) can occur. The first occurs in the base region from the large number of electrons injected at high emitter–base voltage. The effect was analysed for Si BJTs by Webster [28]. Since the reverse injected base current retains an eqVbe /kT dependence, the current gain falls off inversely proportional to Ic [3]. In general, this effect does not appear in HBTs if the base dopant concentration is high. The other HLI effect occuring in the collector region is the Kirk effect [25] which arises as the base–collector depletion width spreads into the collector at high current levels due to electron velocity saturation. The effect of velocity saturation at large collector current densities depends on the relative base and collector doping concentrations. Forward bias of the internal base–collector junction increases the base current due to hole injection into the collector and results in a rapid drop in dc current gain. In a SiGe HBT, the valence band offset prevents the injection of holes into the collector and subsequently the collector current saturates at densities

High level injection

95

Figure 3.15. Simulated band diagrams for a structure (a) without and (b) with 150 ˚ A thick spacers for a 10 min anneal at different temperatures. (After Prinz E J 1992 Base transport and vertical profile engineering in Si/Si1−x Gex /Si heterojunction bipolar transistors PhD Dissertation Princeton University.)

less than the classical Kirk effect. In addition, excess charge is stored in the base, which results in decreased current gain and fT . Cottrell and Yu [29] and Yu et al [30] attempted to model the valence band barrier effects at high collector current densities for a SiGe HBT. The authors noted that the valence band barrier effect appears at high current densities for npn and at all current densities for pnp devices. Other researchers [31, 32] examined the effect of two-dimensional lateral carrier diffusion on the gain. In this case, the electrons accumulating in the

96

Principle of SiGe HBTs

base–collector space-charge layer (SCL) diffuse laterally before collection, resulting in an increased effective collector area. Recently, a comprehensive investigation of the impact of the Ge profile shape as well as the scaling of base and collector doping on high injection heterojunction barrier effects has been described [33] over a wide temperature range. The onset of the Kirk effect in a SiGe HBT was shown to expose the Si/SiGe heterojunction which blocks the flow of holes into the collector under the Kirk effect and hence induces an electron barrier in the conduction band. The combined effect reduces collector current, increases base current and rapidly degrades fT . Various strategies to simultaneously reduce the impact of the conduction band barrier, and increase fmax and BVceo were discussed. Experimental evidence of the valence band barrier in a pnp SiGe HBT has been confirmed [19, 34, 35]. The knee current (at which Ic × β is maximum) which increases with applied base–collector bias, is found to be much stronger than can be explained by the Kirk effect. Similarly, the graph of unity gain cut-off frequency fT versus collector current density also shows a strong dependence on the base–collector bias. From the experiments, the knee current density was found to be much less than the current density calculated by accounting solely for velocity saturation. 3.7.

HIGH-FREQUENCY FIGURES-OF-MERIT

For high-frequency ac operation, bipolar transistors are often assessed according to two figures-of-merit. The first is known as the unity gain cut-off or transition frequency, fT . The second is known as the maximum oscillation frequency. While both figures-of-merit may not necessarily be suitable for all applications of SiGe HBTs, both are still widely quoted, particularly in device research publications. 3.7.1.

Unity gain cut-off frequency, fT

fT is defined as the frequency at which the common emitter short circuit ac current gain is unity [13]. It is related physically to the bipolar device, as the total delay for the minority carrier across the device from emitter to collector, τec [3]. The total delay consists of the minority carrier stored charge delay and the junction capacitance charging delay, and is often related to fT through the equation: fT =

1 2πτec

(3.30)

where the total transit time τec comprises of a number of components: τec = τe + τeb + τb + τbc + τje + τc .

(3.31)

High-frequency figures-of-merit

97

The major components, due to minority carrier stored charge, are τe for the neutral emitter and τb for the neutral base region (as previously discussed in section 3.3). The term τeb represents minority carrier transit time in the emitter–base depletion region, and is often small enough to be included in the emitter transit time term. The transit time τb , the delay due to the excess minority carrier storage in the base, is generally the most significant term in equation (3.31) and the relevant expressions for a SiGe HBT and the effect of Ge grading have been given in equations (3.19)–(3.20). The delay term τbc is known as the collector depletion layer transit time. It can be approximated as [13, 36] τbc =

Wjc 2vscl

(3.32)

where Wjc is the base–collector depletion layer width, vscl is the carrier scattering limited velocity which is approximately equal to 1×107 cm s−1 at room temperature for silicon [37]. For high-speed devices, as the base width is consistently scaled down, τb reduces, and τe and τbc become progressively more significant. The delay term τje is the total charging time associated with emitter– base and base–collector depletion layers and is given by [3] τje =

kT (Cje + Cjc ) qIc

(3.33)

where Cje and Cjc are the emitter–base and the base–collector depletion capacitances. As the collector current increases, it is often assumed that this transit time component becomes negligible. However, for low power devices, the effect of low Ic on τje becomes more significant, emphasizing very clearly the importance of minimizing the junction capacitances Cje and Cjc . The delay term τc is the collector charging time [3] τc = Rc Cjc .

(3.34)

In a well-designed transistor, Rc is usually quite small and therefore τc is usually not very significant. By combining all equations, fT can be conveniently formulated as 1 fT = 2π




kT Wb2 Wjc (Cje + Cjc ) + + τe + τeb + + Rc Cjc qIc αDnb 2vscl

−1 .

(3.35) Figure 3.16 shows the typical variation of fT with collector current. From equation (3.33), it is clear that τje is dominant at low collector current, and therefore fT tends to increase with increase in Ic . However, the influence of τje reduces drastically as the collector current continues to increase. At

98

Principle of SiGe HBTs

Figure 3.16. Variation of fT with collector current in a SiGe HBT.

peak fT , τe , τb and τbc are usually the dominant terms for an optimal transistor design [13]. Therefore, to improve the peak value of fT , all three terms need to be minimized. Eventually high injection occurs and the base transit time increases at high collector current, causing the reduction in fT as shown in figure 3.16. 3.7.2.

Maximum oscillation frequency, fmax

The unity gain cut-off frequency provides a good indication of the intrinsic delay associated with a bipolar transistor. However, it is not a realistic parameter for a circuit environment, as it assumes that the output is short circuited. In addition, it is independent of base resistance and hence does not take the base resistance base–collector depletion capacitance time constant into account. These are important parameters for determining the transient behaviour of bipolar circuits. Therefore, another more practical and widely accepted figure-of-merit, fmax , is commonly used, which characterizes the power transfer in and out of the bipolar device. fmax is defined as the frequency at which the unilateral power gain becomes unity. Here the output is essentially isolated from the input by an appropriate external matching circuit comprising reactive and resistive components. The load that it drives is also assumed to be conjugately matched to the transistor output impedance. It can be shown [38] that:  fmax =

fT 8πCjc Rb

(3.36)

Breakdown voltage, BVceo

99

where Rb is the base resistance. Equation (3.36) shows that it is not sufficient to obtain a high value of fT , by decreasing base width, but that base resistance and base–collector capacitance must also be minimized. However, as base width decreases rapidly to achieve high fT , Rb will increase unless the doping is increased. To counter that effect, the base needs to be more highly doped, which means that emitter doping has to be lowered to prevent emitter–base junction tunnelling for very high base doping levels. The increased current gain capability of a SiGe base enables lowering of emitter doping without jeopardizing sufficient current gain. An alternative figure-of-merit, the ECL gate delay (see section 4.7.3) has been used to characterize the effects of transistor parameters at high frequency [39]. Unlike the frequencies fT and fmax , there is no standard expression for the switching time or the propagation delay. The gate delay depends not only on the intrinsic characteristics of the transistor but also the circuit configuration and the values of load resistance and capacitance. In all cases, base resistance and base–collector capacitance appear in the expressions. Even though fmax does not accurately represent the device performance at high frequencies, the qualitative effect of reducing base resistance and base–collector capacitance is apparent. A further discussion on the computational aspects of determining the various components of fT from device simulations will be presented in chapter 5. 3.8.

BREAKDOWN VOLTAGE, BVCEO

Although several breakdown voltages are defined for a bipolar transistor, the most important is the collector–emitter breakdown voltage, BVceo , as it determines the maximum supply voltage that can be applied. The collector–emitter breakdown is limited by two different reverse bias junction breakdown mechanisms: Zener and avalanche. Zener breakdown occurs when both sides of a junction have high dopant concentrations. Avalanche breakdown occurs when a large electric field appears across the depletion region causing an impact ionization and generation of electron–hole pairs. BVceo , limited by avalanche breakdown, occurs when the product of the avalanche multiplication factor and dc current gain approaches unity. For design purposes it is often approximated by [40] BVceo 

BVcbo √ m β

(3.37)

where BVcbo is the base–collector breakdown voltage with emitter opencircuited and m ranges from 2–3 for silicon [41]. In general, the optimization of breakdown voltages for a homojunction transistor and an HBT does not differ. However, extension of the Ge profile into the collector region to avoid the parasitic heterojunction barriers may lead to increased impact ionization. But simulations of carrier energy

100

Principle of SiGe HBTs

seem to indicate that impact ionization is more likely to occur deeper into the collector than originally thought [42]. Therefore, a narrow bandgap Si1−x Gex -base may not affect the breakdown voltage. A trade-off exists between the breakdown voltage and the collector velocity saturation effects. Increases in breakdown voltage for both emitter–base and base–collector junctions have been obtained by placing lightly-doped spacers on both sides of the heavily-doped base without incurring collector velocity saturation effects [43–45]. 3.9.

SUMMARY

The objective of this chapter has been to describe the basic physics of SiGe HBTs. Use was made of energy band diagrams in deriving the expression for collector current in the most general case of a graded base SiGe HBT. It was evident that significant enhancement in current gain, base transit time and Early voltage is possible with the incorporation of germanium in the base region. The way in which the resultant reduction of emitter and base transit times leads to a corresponding enhancement in high-frequency performance measures such as fT and fmax was clearly indicated. The onset of a parasitic conduction band barrier at the base– collector junction through out-diffusion of boron from the base was shown to be undesirable, since it increases minority carrier storage in the base, and reduces both collector current and fT . Consequently, the advantage in use of thin undoped SiGe spacer layers between base and emitter and base and collector was discussed.

BIBLIOGRAPHY [1] Shockley W 1951 US Patent Specification 2569347 [2] Kroemer H 1957 Theory of a wide-gap emitter for transistors Proc. IRE 45 1535–7 [3] Sze S M 1981 Physics of Semiconductor Devices 2nd edn (New York: Wiley) [4] Slotboom J W and de Graaff H C 1976 Measurement of bandgap narrowing in Si bipolar transistors Solid-State Electron. 19 857–62 [5] Kroemer H 1982 Heterojunction bipolar transistors and integrated circuits Proc. IEEE 70 13–25 [6] Vaidyanathan M and Roulston D J 1995 Effective base–collector time constants for calculating the maximum oscillation frequency of bipolar transistors Solid-State Electron. 38 509–16 [7] Vaidyanathan M and Pulfrey D L 1999 Extrapolated fmax of heterojunction bipolar transistors IEEE Trans. Electron Devices 46 301–9 [8] Tang Y T 2000 Advanced characteristics and modelling of SiGe HBTs PhD Thesis University of Southampton

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[9] Harame D L, Comfort J H, Cressler J D, Crabbe E F, Sun J Y-C, Meyerson B S and Tice T 1995 Si/SiGe epitaxial-base transistors—part I: materials, physics and circuits IEEE Trans. Electron Devices 42 455–68 [10] Kroemer H 1985 Two integral relations pertaining to the electron transport through a bipolar transistor with a nonuniform energy gap in the base region Solid-State Electron. 28 1101–3 [11] Slotboom J W, Streutker G, Pruijmboom A and Gravesteijn D J 1991 Parasitic energy barriers in SiGe HBTs IEEE Electron Device Lett. 12 486–8 [12] Kay L E and Tang T-W 1991 Monte Carlo calculation of strained and unstrained electron mobilities in Si1−x Gex using an improved ionizedimpurity model J. Appl. Phys. 70 1483–1488, 1991. [13] Ashburn P 1988 Design and Realization of Bipolar Transistors (Chichester: Wiley) [14] Lindmayer J and Wrigley C 1961 The high injection level operation of drift transistors Solid-State Electron. 2 79–84 [15] Early J M 1952 Effects of space-charge layer widening in junction transistors Proc. IRE 40 1401–6 [16] Prinz E J and Sturm J C 1991 Current gain-Early voltage products in heterojunction bipolar transistors with nonuniform base bandgaps IEEE Electron Device Lett. 12 691–3 [17] Prinz E J and Sturm J C 1991 Analytical modelling of current gain-Early voltage products in Si/Si1−x Gex /Si heterojunction bipolar transistors IEEE IEDM Tech. Dig. pp 853–6 [18] People R 1986 Physics and applications of Gex Si1−x /Si strained layer heterostructures IEEE J. Quantum Electron. 22 1696–710 [19] Harame D L, Stork J M C, Meyerson B S, Crabbe E F, Scilla G J, de Fresart E, Megdanis A C, Stanis C L, Patton G L, Comfort J H, Bright A A, Johnson J B and Furkay S S 1990 30 GHz polysilicon-emitter and single-crystal-emitter graded SiGe-base pnp transistors IEEE IEDM Tech. Dig. 33–6 [20] Prinz E J, Garone P M, Schwartz P V, Xiao X and Sturm J C 1989 The effect of base-emitter spacers and strain-dependent densities of states in Si/Si1−x Gex /Si heterojunction bipolar transistors IEEE IEDM Tech. Dig. pp 639–42 [21] Prinz E J, Garone P, Schwartz P, Xiao X and Sturm J 1991 The effects of base dopant out-diffusion and undoped Si1−x Gex junction space layers in Si/Si1−x Gex /Si heterojunction bipolar transistors IEEE Electron Device Lett. 12 42–4 [22] Shafi Z A, Gibbings C J, Ashburn P, Post I R C, Tuppen C G and Godfrey D J 1991 The importance of neutral base recombination in compromising the gain of Si/SiGe heterojunction bipolar transistors IEEE Trans. Electron Devices 38 1973–6 [23] Shafi Z A, Ashburn P, Post I R C, Robbins D J, Leong W Y, Gibbings C J and Nigrin S 1995 Analysis and modelling of base currents of Si/Si1−x Gex heterojunction bipolar transistors fabricated in high and low oxygen content material J. Appl. Phys. 78 2823–9 [24] Pruijmboom A, Slotboom J W, Gravesteijn D J, Fredriksz C W,

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[25] [26] [27]

[28] [29] [30] [31] [32] [33] [34]

[35]

[36] [37] [38] [39] [40]

Principle of SiGe HBTs van Gorkum A A, van de Heuvel R A, van Rooij-Mulder J M L, Streutker G and van de Walle G F A 1991 Heterojunction bipolar transistors with SiGe base grown by molecular beam epitaxy IEEE Electron Device Lett. 12 357–9 Kirk C T 1962 A theory of transistor cut-off frequency fT falloff at high current densities IRE Trans. Electron Devices 9 164–74 Poon H C, Gummel H K and Scharfetter D L 1969 High injection in epitaxial transistors IEEE Trans. Electron Devices 16 455–8 Matutinovic-Krstelj Z, Prinz E J, Schwartz P V and Sturm J C 1991 Reduction of p+ –n+ junction tunnelling current for base current improvement in Si/SiGe/Si heterojunction bipolar transistors IEEE Electron Device Lett. 12 163–5 Webster W M 1954 On the variation of junction-transistor current amplification with emitter current Proc. IRE 42 914–20 Cottrell P and Yu Z 1990 Velocity saturation in the collector of Si/Gex Si1−x /Si HBTs IEEE Electron Device Lett. 11 431–3 Yu Z, Cottrell P E and Dutton R 1990 Modelling and simulation of high-level injection behaviour in double heterojunction bipolar transistors IEEE BCTM Proc. pp 192–4 Gao G-B, Fan Z-F and Morkoc H 1991 Analysis of cut-off frequency roll-off at high currents in SiGe double-heterojunction bipolar transistors Appl. Phys. Lett. 58 2951–3 Mazhari B and Morkoc H 1991 Effect of collector-base valence-band discontinuity on Kirk effect in double-heterojunction bipolar transistors Appl. Phys. Lett. 59 2162–4 Joseph A J, Cressler J D, Richey D M and Niu G 1999 Optimization of SiGe HBTs for operation at high current densities IEEE Trans. Electron Devices 46 1347–54 Harame D L, Stork J M C, Meyerson B S, Crabbe E F, Patton G L, Scilla G J, de Fresart E, Bright A A, Stanis C, Megdanis A C, Manny M P, Petrillo E J, Dimeo M, McIntosh R C and Chan K K 1990 SiGe-base pnp transistors fabricated with n-type UHV/CVD LTE in a ‘No Dt ’ process Dig. Symp. on VLSI Technol. pp 47–8 Harame D L, Meyerson B S, Crabbe E F, Stanis C L, Cotte J, Stork J M C, Megdanis A C, Patton G L, Stiffler S, Johnson J B, Warnok J, Comfort J H and Sun J-C 1991 55 GHz polysilicon-emitter graded SiGe-base pnp transistor Proc. Symp. VLSI Tech. pp 71–2 Meyer R G and Muller R S 1987 Charge-control analysis of the collector-base space-charge-region contribution to bipolar transistor time constant τt IEEE Trans. Electron Devices 34 450–2 Smith P, Inoue M and Frey J 1980 Electron velocity in Si and GaAs at very high electric fields Appl. Phys. Lett. 37 797–8 Pritchard R L 1955 High-frequency power gain of junction transistors Proc. IRE 43 1075–85 Asbeck P M 1990 Bipolar transistors High Speed Semiconductor Devices ed S M Sze (New York: Wiley) pp 335–97 Werner Jr R M and Grung B 1983 Transistors: Fundamentals for the Integrated-Circuit Engineering (New York: Wiley)

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[41] Roulston D J 1990 Bipolar Semiconductor Devices (Singapore: McGrawHill) [42] Patton G L, Stork J M C, Comfort J H, Crabbe E F, Meyerson B S, Harame D L and Sun J Y-C 1990 SiGe-base heterojunction bipolar transistors: physics and design issues IEEE IEDM Tech. Dig. pp 13–16 [43] Comfort J H, Patton G L, Cressler J D, Lee W, Crabbe E F, Meyerson B S, Sun J Y-C, Stork J M C, Lu P-F, Burghartz J N, Warnock J, Scilla G, Toh K-Y, D’Agostino M, Stanis C and Jenkins K 1990 Profile leverage in self-aligned epitaxial Si or SiGe base bipolar technology IEEE IEDM Tech. Dig. pp 21–4 [44] Tang D D and Lu P F 1989 A reduced-field design concept for high performance bipolar transistors IEEE Electron Device Lett. 10 67–9 [45] Lu P F, Comfort J H, Tang D D, Meyerson B and Sun J Y-C 1990 The implementation of a reduced-field profile design for high-performance bipolar transistors IEEE Electron Device Lett. 11 336–8

Chapter 4 DESIGN OF SIGE HBTS

As semiconductor technology continues to evolve, numerical modelling of the electrical behaviour of advanced devices has become vital. Numerical device modelling based on the self-consistent solution of the fundamental semiconductor equations dates back to the famous work of Gummel in 1964 [1]. In Gummel’s one-dimensional (1D) discretization, the Poisson equation and the current continuity equations are decoupled and solved sequentially until convergence. Gummel’s approach was later extended by de Mari [2] and applied to transient simulations of a 1D p–n junction. A very important breakthrough in the discretization of the current transport equations was reported by Scharfetter and Gummel in 1969 [3]. The Scharfetter–Gummel (SG) discretization scheme has since been used by all important device simulation programs. During the 1970s and 1980s, several 1D and 2D programs were developed, and made freely available to the research community. Examples include SEDAN [4] for 1D simulations, MINIMOS [5] for 2D MOS transistor simulations, BAMBI [6] for arbitrary semiconductor structures and PISCES [7], a 2D finite-element simulator, which rapidly became an industry standard and formed the basis of future commercial products such as Silvaco–ATLAS [8], Avant–Medici [9] and PISCES–2ET [10]. In 1977, Sutherland and Hauser [11] were the first to use numerical techniques to analyse heterojunction devices. They showed that the basic formulation for homojunction devices could easily be generalized to include the effects of a position-dependent band structure. The formulation was further developed [12] to include field-dependent mobility to fit the steadystate velocity field characteristics, and later expanded to treat degenerate semiconductors via Fermi–Dirac statistics [13–15]. HQUPETS [16] was an early 2D simulation tool developed for SiGe HBTs, and has been extensively used for device design [17]. Several advanced 1D simulators, specific to SiGe HBTs, such as a simulator for cryogenic research and silicon–germanium bipolar device optimization 104

Design of SiGe HBTs

105

(SCORPIO) [18] and PROSA [19], have been reported. Although the drift–diffusion (DD) model is the most widely used and understood tool for semiconductor device simulation, it unfortunately fails to predict non-stationary transport effects. As a derivative of the Boltzmann transport equation (BTE), it also fails to reflect the quantum mechanical nature of carrier transport. The continuous push toward smaller devices has led to a need to address these shortcomings, and to the development of more sophisticated physical models, such as the hydrodynamic and energy transport models [20, 21], the spherical harmonics expansion method [22] and the Monte Carlo technique [23–27]. Unfortunately, since the Monte Carlo method involves keeping statistics on a large number carriers undergoing random collisions, it is very expensive in terms of computer time. The simulation of a complete transistor requires tracking a prohibitive number of carriers in order to attain statistical significance. This typically limits the Monte Carlo technique to use an aid in studying only part of the transistor, for instance the emitter–base junction. In the hydrodynamic or energy transport model, the first three moments of the BTE are taken, yielding the particle, momentum and energy conservation equations [20]. To solve these equations, it is generally necessary to make many assumptions (for instance invocation of the relaxation time approximation). As the drift–diffusion model is pushed to its limits, more people are trying the hydrodynamic method of solution. A complete hierarchy of approaches and analyses has been reviewed by Ravaioli [28]. However, the increased rigour of such models comes at the expense of increased CPU time, so for the simulations reported in this book we confine our discussion almost exclusively to the drift–diffusion model. Regardless of the modelling methodology used, the ultimate responsibility will always rest on the user of the simulator to intelligently interpret the results and know when the assumptions inherent to the method are being violated. Otherwise, as was pointed out by Tang and Laux [29], ‘. . . computationally sophisticated 2D or even 3D device simulations are rendered merely expensive, and perhaps misleading, curvefitting programs’. The aim of this chapter is to give some insight into the formulation of a physical device model for a SiGe HBT and to show how it can be applied for HBT transistor design. The model equations account for the position-dependent variation of energy bandgap, the dependence of mobility on different scattering mechanisms, carrier velocity saturation, doping-dependent carrier lifetime and heavy doping effects. The resulting HBT model corresponds closely to that implemented in the Silvaco–ATLAS device simulator [8], which has been used in a number of the examples considered. A number of studies are presented where model prediction is compared to measured data.

106 4.1.

Design of SiGe HBTs DEVICE MODELLING

Physically based device simulation predicts the electrical characteristics associated with a specified physical structure and bias conditions. This is achieved by mapping the structure onto a two-dimensional or threedimensional grid consisting of a number of grid points called nodes. By applying a set of partial differential equations, derived from Maxwell’s equations to this grid, the transport of carriers can be simulated. By specification of appropriate boundary conditions, dc, ac and transient modes of operation can be modelled. Physical simulation has two important characteristics. It is much quicker and cheaper than performing experiments. In addition it provides information that is difficult or impossible to measure. The main drawback is that all the relevant physics must be incorporated into the simulator. The user must specify the problem to be solved by defining: • • •

the physical structure; the physical models; and the bias conditions for which electrical characteristics are required.

A basic requirement for a successful physical simulation of a semiconductor device is a mathematical model describing its operation. The model is characterized by a set of fundamental equations which link the electrostatic potential and the carrier densities within some predefined simulation domain. These equations are derived from Maxwell’s laws and consist of Poisson’s equation and the continuity equations for electrons and holes. Poisson’s equation relates variations in electrostatic potential to the space-charge density and is given by,   ∇ · (∇ψ) = −q p − n + ND+ − NA− − ρs (4.1) where ψ is the electrostatic potential,  is the local dielectric permittivity, q is the charge of an electron, p and n are the hole and electron concentrations, ND and NA are the ionized donor and acceptor impurity concentrations and ρs is the surface charge density. The continuity equations, which describe the way that electron and hole carrier densities evolve as a result of transport processes, generation and recombination processes, are given by, 1 ∂n = ∇ · J5n + (G − R) ∂t q

(4.2)

1 ∂p = − ∇ · J5p + (G − R) ∂t q

(4.3)

where Jn and Jp are the electron and hole current densities, and G and R are the generation and the recombination rates, respectively. The above

Device modelling

107

equations provide the general framework for device simulation. However, further secondary equations are necessary to specify particular physical models for current density, generation recombination rates. The current density equations are usually obtained by applying approximations and simplification to the BTEs. These assumptions can result in a number of possible transport models such as the drift–diffusion model [30], the energy balance and the hydrodynamic models [20]. The choice of transport model can impact on the choice of generation and recombination model. By far the simplest and most commonly used model in device simulation is the drift–diffusion model. Until recently this model was adequate for nearly all semiconductor devices but it tends to become less accurate for small feature sizes [28]. In the drift–diffusion model, the current densities are expressed in terms of quasi-Fermi levels Φn and Φp as J5n = −qµn n∇φn

(4.4)

J5p = −qµp p∇φp

(4.5)

where µn and µp are the electron and hole mobilities. Using Boltzmann approximations, the quasi-Fermi levels may be related to the carrier concentrations and the potential as given by   q (Ψ − φn ) n = nie exp (4.6) kTL   −q (Ψ − φp ) p = nie exp (4.7) kTL where nie is the effective intrinsic carrier concentration and TL is the lattice temperature. These two equations may then be rewritten as Φn = ψ −

n kTL ln q nie

(4.8)

p kTL ln . (4.9) q nie By substituting these equations into the current density expressions, one obtains Φp = ψ +

J5n = qDn ∇n − qnµn ∇Ψ − µn nkTL ∇ (ln(nie ))

(4.10)

J5p = −qDp ∇p − qpµp ∇Ψ + µp pkTL ∇ (ln(nie ))

(4.11)

where the last term accounts for the gradient in the effective intrinsic carrier concentration, taking into account bandgap narrowing effects. Effective electric fields are given by 
kTL 5 En = −∇ ψ + (4.12) ln nie q

108

Design of SiGe HBTs


kTL ln nie . E5p = −∇ ψ − q

(4.13)

From the above and using Einstein relationships, the familiar drift–diffusion expressions are as follows: J5n = qµn E5n + qDn ∇n

(4.14)

J5p = qµp E5p − qDp ∇p.

(4.15)

In the case of Boltzmann statistics, Dn and Dp are given by Dn =

kTL µn q

(4.16)

Dp =

kTL µp . q

(4.17)

In the case of the energy balance (EB) model, a higher-order solution to the generalized BTE is necessary to include an additional coupling of the current density to the carrier temperature (energy). Then the current density and energy flux densities are expressed as J5n = qDn ∇n − µn n∇Ψ + qnDnT ∇Tn 
kδn 5 Jn Tn S5n = −Kn ∇Tn − q

(4.18)

J5p = qDp ∇p − µp p∇Ψ + qpDpT ∇Tp 
kδp 5 Jp Tp S5p = −Kp ∇Tp − q

(4.20)

(4.19)

(4.21)

where Kn,p and δn,p are respective transport coefficients for electrons and holes that depend on the corresponding carrier temperatures Tn and Tp . Sn and Sp are the flux of energy (or heat) from the carrier to the lattice. Full details of the formulation are given in [31]. 4.2.

NUMERICAL METHODS

Several different numerical methods can be used to solve the semiconductor equations. In general, there are three approaches: decoupled (Gummel method), fully coupled (Newton method) or a combination method. The decoupled method will solve for each unknown in turn keeping other variables constant, repeating the process until a stable unchanging solution is achieved. Fully coupled techniques, such as the Newton method, solve the total system of unknowns together. The combined method will only solve some of the equations fully coupled. The Newton method is the preferred

Numerical methods

109

method as it offers quadratic convergence, provided a suitable initial guess can be estimated. Because of this constraint, it is always advisable to use small incremental changes to the applied voltage. In performing a simulation, the device starts with zero bias on all electrodes. Solutions are obtained by stepping the bias on electrodes from this initial equilibrium condition, using small steps in voltage. Once a solution is obtained, the current flowing through each electrode is calculated by numerical integration. Internal quantities, such as carrier distributions and electric field throughout the device, can then be computed or presented graphically. There are several ways to predict the small-signal and large-signal high-frequency properties of semiconductor devices. A review of these different techniques has been given by Laux et al [32]. Frequency domain perturbation analysis is used to calculate the small-signal characteristics, while Fourier analysis is required for a large-signal response. In ATLAS, frequency domain perturbation of a dc solution can be used to calculate small-signal characteristics at any frequency. Variables are represented as the sum of a known dc component and an unknown sinusoidal ac component. The semiconductor equations are expanded with differentiation in time becoming equivalent to multiplication by jω. The dc solution is subtracted, and what remains is a complex linear system whose unknowns are the ac components. Solving this linear system gives the small-signal y-parameters. If the Newton method is used for the dc solution, then the Jacobian matrix associated with the dc operating point can be used directly in the small-signal analysis without recomputation. If the semiconductor device is treated as a two port network, with defined input and output ports, then knowledge of the y-parameters permits all other small-signal parameters to be calculated. The advantage of this approach is that the determination of y-parameters is based solely on the physical structure, and hence does not rely on any predefined lumped element equivalent circuit model. These y-parameters can then be used to find different power gains [33]. Among the various power gains described so far in the literature several, such as maximum available gain (MAG), maximum stable gain (MSG) and maximum available unilateral gain (MAUG), have found widespread use. Additionally, a figure-of-merit that has been used extensively for microwave characterization is Mason’s invariant U (or Mason’s gain). These quantities are calculated from the measured small-signal scattering parameters because of the ease of measurement at high frequencies. All the above mentioned gains can be conveniently expressed in y-parameters as follows:    y21    M SG =  (4.22) y12 

110

Design of SiGe HBTs      y21   k − k2 − 1 MAG =  y12 

(4.23)

where 2Re(y11 )Re(y22 ) − Re(y12 y21 ) |y12 y21 |

(4.24)

|y21 − y12 |2 4[Re(y11 )Re(y22 ) − Re(y12 )Re(y21 )]

(4.25)

k= U=

MAU G =

|y21 |2 . 4Re(y11 )Re(y22 )

(4.26)

Maximum available gain is obtained when both input and output are simultaneously conjugately matched. MAG exists only when the device is unconditionally stable when k > 1. As can be seen from equations (4.25) and (4.26), U equals MAUG only if the device is unilateral, i.e., y12 = 0. MAG and MSG are equal to each other once the device is unconditionally stable. The frequency at which MAG becomes unity is often defined as fmax . However, a full discussion on the interpretation of fmax is given in [34]. Since common-emitter microwave transistors may have power gain with no impedance transformation, they can have useful gain when inserted into a 50 Ω system. This gain is identical to |s21 |2 . ATLAS has an option to easily convert y-parameters obtained from ac analysis, to s-, z- or h-parameters. The unity gain cut-off frequency is extracted from extrapolation of the high-frequency asymptote of a plot of the magnitude of h21 in dB versus log (frequency). Most BJT devices at a sufficiently low frequency can be represented as single pole devices. This assumption is equivalent to a high-frequency asymptote with a slope of −20 dB per decade. However, both Cbe and Cbc capacitances are bias dependent, and so is the cut-off frequency. From the MAG (in dB) versus log (frequency) plot, fmax is extracted at the point where MAG becomes 0 dB. 4.3.

MATERIAL PARAMETERS FOR SIMULATION

Electrons and holes in a device are accelerated by electric fields but lose momentum as a result of various scattering processes. These scattering mechanisms include lattice vibrations, impurity ions, other carriers, interfaces and material imperfection. To simplify these mechanisms for modelling purposes, mobility is usually defined as a function of lattice temperature, local electric field and doping concentration. In a device simulator, a mobility model is further subdivided into •

low-field behaviour,

Material parameters for simulation • • •

111

high-field behaviour, bulk semiconductor regions, and inversion layers.

In the low-field region, mobility is principally dependent on phonon and impurity scattering, both of which tend to decrease the low-field mobility. High-field behaviour shows that carrier mobility decreases with electric field. The mean drift velocity no longer increases linearly with increasing electric field, but rises more slowly. Eventually the velocity saturates at a constant velocity commonly denoted by the symbol vsat which is principally a function of lattice temperature. Modelling mobility in bulk material involves characterizing µn0 and µp0 as a function of doping and lattice temperature and describing the transition between low-field and high-field regions. Modelling carrier mobility in inversion layers presents additional complications due to surface scattering and quantum mechanical effects. These effects are important for accurate simulation of MOS devices. The transverse electric field is often used to characterize mobility variation within inversion layers. In ATLAS, a wide (and somewhat baffling) range of different silicon mobility models is available. Full details are given in the ATLAS manual [8]. The low-field mobility can be characterized in five different ways: user defined; a lookup table as a function of doping; an analytic function of doping and temperature [35]; a carrier scattering model relating mobility to carrier concentration and temperature; or a unified model dependent on impurity, lattice and carrier–carrier scattering and temperature [36,37]. For bipolar device simulation, the latter model is recommended as it applies a unified description of minority and majority carrier mobilities. The model shows excellent agreement with available experimental data. As carriers are accelerated in an electric field, their velocity will begin to saturate at a high electric field. This effect has to be accounted for by a reduction of effective mobility, since the drift velocity is the product of mobility and electric field in the direction of current flow. The following expression [38] is used to implement a field-dependent mobility for both holes and electrons, that provides a smooth transition between low-field and high-field behaviour,  µ(E) = µo

 1 1+




µo E vsat

β β1 (4.27)

where µo is the low-field mobility, E is the electric field parallel to the direction of current flow, β is a constant, and vsat is the saturation velocity. The coefficient β is one for holes and two for electrons. The saturation velocity vsat is calculated by default from the temperature-dependent

112

Design of SiGe HBTs

model, vsat (T ) =

2.4 × 107 1 + 0.8 exp (T /600)

(4.28)

but specific values for holes and electrons can be specified, if required. The incorporation of germanium significantly changes the properties of the base region and the emitter–base and base–collector junctions in a SiGe HBT. While silicon has been well characterized over the past 40 years, still not nearly as much is known about strained-SiGe. Many simplifying assumptions are made in the SiGe material parameters. The addition of Ge reduces the bandgap of Si, leading to the narrow bandgap SiGe base of the HBT, as discussed in chapter 3. The lattice constant of the strainedSi1−x Gex alloy differs considerably from that of Si. The incorporation of Ge also modifies the energy band structure, and density of states in the conduction and valence bands. In addition, carrier mobilities and diffusivities change owing to changes in the effective masses and alloy scattering. Finally, the dielectric constant, built-in potentials and depletion widths in the p–n heterojunctions depend on the Ge concentration. As all the device simulations reported in this book have been carried out using the Silvaco–ATLAS simulator [8], we consider in the following section, the material parameters used in the simulations. 4.3.1.

SiGe: hole mobility

There have been few reports on the measurements of mobility in strainedSi1−x Gex alloys. Mansevit et al [39] reported enhanced electron mobilities at room temperature, but the Ge mole fraction of the samples was not accurately known. Monte Carlo simulations of electron mobility heavilydoped SiGe at room temperature indicate that µn will be almost 50% higher than for silicon due to the smaller effective mass in SiGe [40]. Enhanced low-temperature mobilities have been also observed for both holes and electrons [41]. In addition to phonon, impurity and alloy scattering mechanisms, strain is expected to play a major role in determining carrier mobility. Due to strain effects, mobilities in SiGe are different for carriers travelling parallel and perpendicular to the direction of growth. In ATLAS version 5.0, there is no specific SiGe mobility model incorporated, but a separate user specified model can be created by writing specific functions in the C programming language, which are then interpreted when running the simulation. For this purpose, a hole mobility model may be based on a model developed by Mau [42] originating from an empirical fit to experimental data. The electron mobility model may be based on theoretical computations by Manku and Nathan [43]. The composition, temperature and doping dependent hole mobility is given by:

Material parameters for simulation

113

(i) for majority carriers
µp = 49.0

T 300

−0.45

+

−2.2

−0.45

− 49.0 (T /300)  (4.29) −2.4 0.74 1.0 + (T /300) (Ntot /1.7 × 1017 ) 480.0 (T /300)

(ii) for minority carriers   −0.45
T 480.0(T /300)−2.2 − 122.3(T /300)−0.45 µp = 122.3 + 0.7 ρ 300 (1.0 + (T /300)−2.4 ) (Ntot /1.4 × 1017 )  −1 1.0 × 1.0 + (4.30) 2 0.5 + (7.2 × 1020 /Ntot ) where


ρ=

µmin (x) +


(µmax (x) − µmin (x)) 1 + (Ntot /2.35 × 1017 )0.88



µmax (0) − µmin (0) × µmin (0) + 1 + (Ntot /2.35 × 1017 )0.88 where and

4.3.2.

−1 (4.31)

  µmin (x) = 68.7 exp 51.2x3 − 34.2x2 + 8.7x

(4.32)

  µmax (x) = 461.9 exp 32.5x3 − 22.2x2 + 6.4x .

(4.33)

SiGe: electron mobility

The alloy scattering limited electron mobility components for coherently strained Si1−x Gex , along directions perpendicular and parallel to the growth direction are given by [43] µalloy = ⊥

5.5 × 1018 T 22.0Nc x(1 − x)m2t

(4.34)

µalloy = 

5.5 × 1018 T 4.0Nc x(1 − x)m2l

(4.35)

where Nc is the effective density of states for silicon. It may be noted that the alloy mobility decreases with increasing Ge content. At low doping levels, alloy scattering and phonon scattering predominate, both of which have an E 1/2 dependence. At high doping levels, impurity scattering becomes important, and it too has the same energy dependence. Since the conduction band of SiGe for x < 0.3 is similar to that of silicon, and all the predominant scattering rates have an

114

Design of SiGe HBTs

E 1/2 dependence, the individual parallel and perpendicular components may be defined. The parallel component of electron mobility in SiGe can thus be obtained by using Mathiessen’s rule 1 1 1 = Si + alloy µSiGe µ µ  

(4.36)

and the corresponding perpendicular component becomes 1 µSiGe ⊥

=

1 1 + alloy Si µ⊥ µ⊥

(4.37)

where the mobility of silicon for parallel and perpendicular to the growth plane is expressed as [43] 3.0µSi (mt /ml + 2.0)

(4.38)

3.0µSi 2.0(ml /mt ) + 1.0

(4.39)

µSi ⊥ = µSi  =

where ml and mt are longitudinal and transverse density of state masses in silicon. At very high concentrations, the Caughey–Thomas relationship [38] no longer suffices to describe the carrier mobility. The effect of ultrahigh concentrations on mobility have been analysed by Klaassen [36], and the modified expression for majority and minority mobility for electron in silicon is given by: (i) for majority carriers   −0.45
T 1430.0(T /300)−2.3 − 74.5(T /300)−0.45 Si Z µ = 74.5 + 300 (1.0 + (T /300)−2.6 (Ntot /8.6 × 1016 )0.77 (4.40) (ii) for minority carriers  −0.45
T 1430.0(T /300)−2.3 ) − 200.0(T /300)−0.45 Si µ = 200.0 + 300 (1.0 + (T /300)−2.6 )(Ntot /5.3 × 1016 )0.68 ) (4.41) where 1.0 Z = 1.0 + (4.42) 0.21 + (4.0 × 1020 /Ntot )2 where Ntot is the total doping and the ‘clustering’ function Z(N ) is fitted analytically.

Material parameters for simulation

115

To evaluate the mobility of strained-SiGe, alloy scattering as well as energy shifts in the conduction band have to be included. The shifts are taken into account through the electron concentration, since the total mobility is given by a weighted average of the unstrained electron concentration of the ith conduction band, with the corresponding strained electron concentration. The components of the total electron mobility of strained-SiGe, for the growth plane µxx , and plane parallel to the growth direction µzz , can be represented as [43] 

SiGe exp(−∆Ex /kT ) + µSiGe + µ exp(−∆Ez /kT ) µSiGe ⊥ ⊥  µxx = (4.43) 2.0 exp(−∆Ex /kT ) + exp(−∆Ez /kT ) µzz =

exp(−∆Ex /kT ) + µSiGe exp(−∆Ez /kT ) 2.0µSiGe ⊥  2.0 exp(−∆Ex /kT ) + exp(−∆Ez /kT )

(4.44)

where ∆Ex = −0.21x and ∆Ez = 0.42x are the splitting energies due to the shift in the [001], [010] and [100] bands. Despite the apparent complexities of the latter model, a more straightforward model has been proposed in the 1D SCORPIO simulator [18], which describes the mobility enhancement of both carriers in SiGe as a linear function (4.45) µSiGe (x) = (1 + K.x)µSi where K is a fitting constant taken to be 10. Although there are conflicting reports concerning the degree of SiGe mobility enhancement which occurs in a HBT, Richey et al [18] conclude that their much simpler model gives excellent agreement with measured data. 4.3.3.

SiGe: bandgap

The most significant material parameter to be specified in the simulation of SiGe HBTs is the bandgap narrowing induced by incorporation of a Ge fraction x. A number of different models have been put forward. Polynomial fits by Bludau et al [44] describe the temperature dependence of the energy bandgap of pure silicon at or below room temperature. The high-temperature model from Sze [45] is slightly modified to match the room temperature value and is given by Eg (T ) = 1.170 + 1.059 × 10−5 T − 6.05 × 10−7 T 2

0 ≤ T ≤ 170 K (4.46)

Eg (T ) = 1.1785 − 9.025 × 10−5 T − 3.05 × 10−7 T 2 Eg (T ) = 1.170 −

4.73 × 10−4 T 2 T + 624.93

170 ≤ T ≤ 300 K (4.47)

T ≥ 300 K.

(4.48)

116

Design of SiGe HBTs

An empirical a fit to the data provided by People [46] for the bandgap of strained-Si1−x Gex alloys on Si(100) substrates is given by Eg (x) = 1.124 − 1.22x + 0.88x2

x ≤ 0.6.

(4.49)

A linear fit is used for 0.6 < x < 1.0, which assumes that the bandgap of strained pure Ge on (100) Si is 0.6 eV. Note that the bandgap of strainedSiGe is considerably smaller than that of bulk-SiGe. In ATLAS, to give increased accuracy, the SiGe bandgap is modelled by a complex piecewise linear function of x, as defined in full in the ATLAS manual. For values of x likely to be encountered in a SiGe HBT (x < 0.245), the following equation applies Eg (x) = 1.08 + x(0.945 − 1.08)/0.245.

(4.50)

In ATLAS, an alternative temperature dependence of the bandgap Eg (T ) for SiGe is given as   T2 αT 2 3002 Eg (T ) = Eg (0) − = Eg (300) + α − (4.51) T +β 300 + β T +β where the composition dependences of α and β are given by: α = (4.73(1 − x) + 4.77x)10−4 β = 636.0(1 − x) + 235.0x. The electron affinity of SiGe is assumed to be independent of the composition x and equal to 4.07 eV, identical to that of Si. In a BJT model, the intrinsic carrier concentration nio , which depends on the effective density of states in the conduction and valence bands and the bandgap, plays an important role. The effective conduction and valence band density of states in silicon are given by the well-known expressions:
Nc = 2

2πm∗n kT h2

3/2


Nv = 2

2πm∗p kT h2

3/2 (4.52)

where h is Planck’s constant, and m∗n and m∗p are the effective masses of the electron and hole density of states. The effective density of states decreases with increasing Ge content, because the amount of degeneracy in both the valence and conduction band decreases [43, 47]. In ATLAS, an empirical function used to give the composition dependence of densities of states for SiGe is given by: Nc = 2.8 × 1019 + x(1.04 × 1019 − 2.8 × 1019 )

(4.53)

Nv = 1.04 × 1019 + x(6.0 × 1018 − 1.04 × 1019 ).

(4.54)

Material parameters for simulation

117

By using equations (4.53) and (4.54), one can calculate the intrinsic carrier concentration as a function of the Ge content 
Eg (x, T ) 2 . (4.55) nio (x) = Nc Nv exp − kT In addition to the Ge-induced bandgap narrowing, the high doping in the base induces additional bandgap narrowing, similar to that observed in silicon. Although several bandgap narrowing and mobility models have been proposed for silicon [48–50], little information is available in the literature for Si1−x Gex [51]. The default model in ATLAS version 5.0 assumes that the bandgap narrowing due to heavy doping is the same as that in silicon. This approach has the advantage that any differences in the simulation of Si BJT and SiGe HBTs can then be unambiguously attributed to heterojunction action (due to Ge incorporation), rather than differences in model parameters. This assumption of equal values of dopinginduced bandgap narrowing in silicon and Si1−x Gex is reasonably good for base doping concentrations up to approximately 1 × 1019 cm−3 [51], but for higher concentrations there is some evidence [52] to suggest that the bandgap narrowing in Si1−x Gex is lower than that in silicon. Bandgap narrowing effects due to heavy doping are modelled by replacing the intrinsic carrier concentration nio with an effective carrier concentration nie (x, y) where   1/2  
2  N (x, y)  qa N (x, y) 1  ln + ln + a3 nie (x, y) = nio exp   2kT  a2 a2 (4.56) where a1 = 0.00692, a2 = 1.3 × 1017 cm−3 and a3 = 0.5 are model parameters. In ATLAS, the dielectric constant of SiGe as a function of composition is given by  = 11.9 + 4.1x. (4.57) 4.3.4.

Recombination and carrier lifetime

The dominant recombination processes in bulk-Si are Shockley–Read–Hall (SRH) and Auger recombination. Radiative recombination is negligible since silicon is an indirect bandgap semiconductor, and recombination involving excitons and shallow-level traps is only important at low temperature. The total recombination rate due to Auger and SRH recombination can be written as:     1 R = An n + Ap p + np − n2ie . (4.58) τn (p + p1 ) + τp (n + n1 )

118

Design of SiGe HBTs

In equation (4.58), An and Ap are the electron and hole Auger recombination coefficients and nie is the effective intrinsic carrier concentration including bandgap narrowing effects. τn and τp are the minority carrier SRH lifetimes and n1 and p1 are constants which depend on the energy of the deep-level traps. Commonly used (default) values for the radiative and Auger recombination coefficients are An = 5.0×10−32 and Ap = 9.9 × 10−32 for silicon [53]. Since strained-SiGe is similar to silicon in band structure, exactly the same recombination model is assumed for SiGe. The minority carrier lifetimes in silicon are doping-dependent. For doping concentrations up to 1019 cm−3 , an empirical fit to experimental data gives τ (0) (4.59) τ (N ) = 1 + N/N0 for both electrons and holes. τ (0) is the minority carrier lifetime in lightlydoped silicon and N0 is the reference doping. A good fit to experimental data is achieved by setting N0 = 7.1 × 1017 cm−3 for both n- and ptype silicon, τ (0) = 3.95 × 10−4 s for holes and τ (0) = 1.70 × 10−5 s for electrons [54]. However, τ (0) is very much process dependent. Studies on the determination of minority carrier lifetime in SiGe have shown that the lifetimes are believed to be somewhat shorter than silicon minority carrier lifetimes (in the nanosecond range), due to the large number of misfit dislocations. 4.4.

HISTORY OF SIMULATION OF SIGE HBTS

Numerous papers have appeared in the literature on both the numerical and analytical modelling of the SiGe HBTs [40, 55–61]. Much of the early work on simulation of SiGe HBTs was carried out over a decade ago and significant improvements in performance have since been achieved. Smith and Welbourn [40] reported that for a SiGe transistor with a 0.15 µm thick strained layer base (with 15% Ge, ∆Ev = 170 meV and 50% enhancement of electron mobility due to strain) an fT of 20 GHz should be realizable before the onset of base widening. The value of fmax was estimated to be 40 GHz. This represented a threefold increase of speed over the homojunction devices at that time. Pejcinovic et al [56] simulated numerically the small-signal performance of a SiGe HBT. The heavy doping effect in SiGe was assumed to be the same as in Si, and effects of strain and alloy scattering on the mobility were included in the model. The doping concentrations in the emitter, base and collector were 7×1019 , 2×1019 and 4.5 × 1017 cm−3 , respectively. The authors found that for the Ge fraction x = 0.2, the turn-on voltage of the HBT was smaller by 0.12 V as compared to an otherwise identical Si homojunction transistor. The frequency fT was twice as large as in the Si transistor and fmax was even larger.

Experimental SiGe HBTs

119

In early 1989, Won and Morkoc [60] examined theoretically the highspeed capability of the SiGe HBTs. They included alloy scattering and strain effects on the mobility in the model. Several doping concentrations were considered. The collector and base doping concentrations were optimized by making a compromise between speed and breakdown voltage. If the parameters are optimized to obtain an fT of 75 GHz, the estimated fmax value is 35 GHz at a current density of 1×105 A cm−2 and Vbc = 5 V. The theoretical work done during this period showed that the HBTs had great promise, once technological problems encountered in their fabrication were resolved. Hueting et al [61] have optimized a SiGe HBT design for highfrequency performance and claimed that a box type Ge profile with the leading edge approximately in the middle of the base is optimal. The doping concentrations in the emitter, base and collector were 2 × 1021 , 2.2 × 1018 and 1 × 1017 cm−3 , respectively, while the Ge concentration in A the base was 11.5%. An fT value of 45 GHz for a base thickness of 600 ˚ was obtained. Hueting et al studied the effect of grading the Ge profile in the base and concluded that (in their opinion) the grading of Ge in the base is of minor importance. Several other simulation techniques such as Monte Carlo [62–64], energy transport [19, 65] have also been employed for the simulation studies of SiGe HBTs. 4.5.

EXPERIMENTAL SIGE HBTS

Since the introduction of SiGe into conventional Si technology, various research groups have demonstrated high-performance SiGe base HBTs with differing approaches to forming the Ge profile in the base. While the IBM group uses graded Ge profiles, the Daimler–Benz group focuses on SiGe HBTs with a uniform Ge box profile. The epitaxial growth of active device regions in Si-based technology is a significant departure from past device fabrication, where epitaxy had been used solely for the controlled substrate formation. Epitaxial base technology has many advantages over an ionimplanted technology. A box-like profile provides independent control over base width and doping concentration. Thus, a base width as small as 30 nm, with a very high doping concentration, can be obtained. Even for these small thicknesses, the base resistance is acceptable and punch-through is avoided. This allows reduction of charge storage in the emitter and independent control of base resistance and base transit time. By tailoring the base profile, low values of emitter–base and base–collector capacitance, Cbe and Cbc , can be obtained. The design can also be tailored for optimum ECL performance in a digital circuit by obtaining high fT at low base resistance. Epitaxial base technology provides the opportunity to independently control each of the delays defined in equation (3.31). Transit time is

120

Design of SiGe HBTs

reduced by both vertical scaling and Ge grading in the base. Self-aligned epitaxial base technology also allows reduction of extrinsic capacitances and resistance to reduce the gate delays [66, 67]. Harame et al [68] have developed a high-performance SiGe BiCMOS HBT process. During the emitter formation, considerable out-diffusion of boron takes place as the diffusion coefficient of boron is considerably larger than that of arsenic. The problem of boron out-diffusion can be avoided, and narrow bases can be formed, if arsenic is replaced by phosphorus for doping the emitter [69]. The diffusivity of phosphorus is much larger than that of arsenic and is close to that of boron. In the devices designed and fabricated by Crabbe et al [69], phosphorus-doped emitters were used. The epitaxial SiGe bases were grown by UHVCVD [70] at 550 ◦ C. The Ge profile was graded from 0% at the emitter–base junction to 15% at the base–collector junction. The collector doping was 4 × 1017 cm−3 to avoid base widening at high current densities. Lightly-doped spacers were placed in the emitter–base and base–collector junctions to maintain reasonable values of BVebo and BVceo . The narrow base width reduced the intrinsic transit time from 2.1 ps to 1.9 ps [71]. The cut-off frequency was 73 GHz at a collector current density of 2 mA µm−2 . The peak fmax was only 26 GHz, due to high extrinsic base resistance caused by insufficient activation of boron because of low emitter anneal temperature. Gruhle et al [72] fabricated a high-performance MBE-grown SiGe transistor. Ge concentrations of 21–28% and boron concentrations of up to 2 × 1020 cm−3 were used to obtain simultaneously high current gains and low base resistance. The SiGe HBT with the highest fmax (in 1995) was reported by Schuppen et al [73]. This transistor used a relatively thick (60 nm) base and heavy doping to minimize the intrinsic base resistance. The base transit time was reduced by a strong electric field with 0–15% Ge grading. The SiGe base was grown selectively by using a self-aligned CVD technology. The performance achieved was an fmax of 160 GHz and a gate delay of 19 ps in an ECL circuit. In the same year, Meister et al [74] reported a SiGe HBT with a 74 GHz fmax , resulting in a record CML gate delay (at that time) of 11 ps. Recently, a 0.2 µm self-aligned selective epitaxial growth (SEG) SiGe HBT, with shallow-trench and dual deep-trench isolations and Ti–salicide electrodes, has been developed. The process, except for the SEG, is almost completely compatible with well-established silicon BiCMOS technology. The SiGe HBTs exhibited a peak fmax of 107 GHz and a record minimum ECL gate delay of 6.7 ps [75]. An Si/Si0.65 Ge0.35 abrupt HBT with transit frequencies fT of 133 and 213 GHz at 300 and 77 K, respectively, has been announced recently [76]. The corresponding maximum oscillation frequencies are 81 and 115 GHz. A detailed analysis of the intrinsic delay times has shown that the base transit time plays the dominant role.

Device design issues 4.6.

121

DEVICE DESIGN ISSUES

In the following sections, important parameters of SiGe HBTs (fT , fmax and VA ) will be considered in detail and attempts are made to illustrate how simulation has been used to optimize the device design for circuit applications. Base, emitter and collector profile design issues at room temperature will be discussed. All the simulations have been performed using the Silvaco–ATLAS device simulator as described in sections 4.1 and 4.2, using default material parameters.

Figure 4.1. Doping profile and Ge profile (flat or box) of a SiGe HBT.

122 4.6.1.

Design of SiGe HBTs Base design

We consider a uniform (flat or box) Ge profile (x = 0.12) in the base. The device structure and the doping concentration used for simulation is shown in figure 4.1. A simulated band diagram comparing SiGe and Si transistors is shown in figure 4.2. As can be seen in figure 4.3, the uniform Ge box profile produces the sevenfold increase in β for 12% Ge at 300 K, since the enhancement depends exponentially on the bandgap reduction at the emitter–base junction. In the conventional Si BJT, β is inversely

Figure 4.2. Schematic band diagrams of a homojunction (Si BJT) and a heterojunction (SiGe HBT) bipolar transistor.

Device design issues

123

Figure 4.3. Comparison of dc current gain of an Si BJT and a flat base SiGe HBT.

proportional to the integrated base charge. Since base doping cannot be increased indefinitely while maintaining adequate β, the flat Ge profile is particularly useful in realizing a transistor with either a very high β, or a moderate β with lower intrinsic base resistance. However, any significant enhancement in peak fT of a SiGe HBT over an Si BJT, depends principally on the utilization of Ge grading across the base. The simulated peak cut-off frequency of 42 GHz for a uniform Ge profile is shown in figure 4.4. Now we consider a graded Ge profile (defined for reference purposes as triangular) having 0% Ge at the emitter–base junction and 12% Ge

124

Design of SiGe HBTs

Figure 4.4. Simulated cut-off frequency of an Si BJT and a flat base SiGe HBT.

at the collector–base junction, as shown in figure 4.5. The Ge grading (0–12%), is effective for reducing τb , and thus increasing fT . In this type of Ge profile design, there is no Ge-induced bandgap reduction at the emitter–base junction, and the β is reduced compared to the flat Ge profile. However, as the β enhancement depends approximately linearly on the Ge grading when there is no bandgap reduction at the emitter–base junction, an enhancement in β of approximately 5 has been simulated. In high-speed analogue applications, which require a high βVA product, the triangular Ge profile would appear to offer a superior design [77]. Because β is still enhanced for the triangular Ge profile, it is still possible to trade β

Device design issues

125

Figure 4.5. Doping profile and Ge profile (triangular) of a SiGe HBT.

for lower base resistance. Using this approach, both fT and base resistance can be tailored to significantly increase fmax . It is seen from figure 4.6 that for a graded Ge profile in the base, fT has increased from 42 GHz (Ge box profile) to 63 GHz, but the gain has dropped from 360 to 200, as shown in figure 4.7. A trapezoidal profile would appear to be a logical compromise between the two previous Ge profiles. This type of profile was used successfully to realize the first 1.0 Gb s−1 12-bit digital-to-analogue converter [77]. Figures 4.8 and 4.9 show a simulation of a trapezoidal profile where the Ge mole fraction at the emitter–base edge is 5% and it has been graded to reach a maximum Ge concentration of 15% at the base–collector junction. It is seen that the trapezoidal grading results in a good compromise between peak current gain of 200, and fT of 50 GHz.

126

Design of SiGe HBTs

Figure 4.6. Comparison of peak cut-off frequency of a graded base versus a flat base SiGe HBT.

4.6.2.

Emitter design

An ideal emitter should provide low emitter saturation current density, low emitter resistance, low charge storage, low emitter–base depletion capacitance, and good passivation at the perimeter of the emitter. The polysilicon emitter contact used in conventional Si technology meets most of these requirements. The polysilicon–silicon interface also provides a barrier-to-hole injection into the emitter. An alternative approach to the polysilicon emitter contact is to use single-crystal emitter. Such a structure

Device design issues

127

Figure 4.7. Comparison of dc current gain of a graded base and a flat base SiGe HBT.

is ideal to decouple the base from the emitter, thereby allowing arbitrarily high base dopant concentrations. Furthermore, it allows a reduction in emitter–base capacitance, leading to higher fT at lower collector current density, as long as the delay associated with minority carrier charge storage in the quasi-neutral emitter can be minimized by maintaining sufficient current gain. A high–low emitter profile, consisting of a heavily-doped polysilicon contact on top of a thin epitaxial emitter cap addresses both requirements [78]. The emitter cap thickness should be small to minimize charge storage and is typically 200–300 ˚ A. The highly-doped polysilicon contact ensures low total emitter resistance.

128

Design of SiGe HBTs

Figure 4.8. Comparison of dc current gains of flat, graded (triangle and trapezoid) base SiGe HBTs.

Three different thicknesses of low-doped emitter, namely 100, 200 and 300 ˚ A, have been used for simulation as shown in figure 4.10. The peak value of Ge fraction x is 0.08. As expected, fT decreases marginally from 30 GHz as the emitter cap thickness is increased from 100 to 300 ˚ A. The location of the Ge profile with respect to the metallurgical emitter–base junction plays a key role in the dc and ac characteristics of the HBT. For an HBT with a linearly graded Ge profile and with a poly emitter contact, locating the emitter–base metallurgical junction right at the bottom of the Ge ramp is a good compromise to ensure moderate current gain while

Device design issues

129

Figure 4.9. Comparison of cut-off frequency of flat base, graded trapezoidal base SiGe HBTs.

taking full advantage of the Ge grading to minimize the base transit time. The slope of the Ge profile at the edge of the emitter–base space-charge region on the base side can affect the ideality of the collector current [79]. 4.6.3.

Collector design

The design of the collector is dictated by conflicting requirements to simultaneously achieve high breakdown voltage BVceo , low base–collector capacitance, low base–collector signal delay τbc , and a high value of

130

Design of SiGe HBTs

Figure 4.10. Emitter with different low-doped spacer layers. Ge and Boron profiles in the base are also shown.

the knee current density at which fT decreases. The collector doping profile determines two critical performance parameters of the transistor: the base–collector delay time τbc , which is a significant component of the total intrinsic delay τec , and the intrinsic base–collector capacitance which governs circuit performance. A conventional approach to suppress base widening is simply to utilize a thin highly-doped epitaxial collector layer. Consequently, base widening is suppressed at the expense of BVceo degradation. One of the methods to increase BVceo , while suppressing base widening, is to introduce a retrograde collector profile [80]. In determining HBT performance, it should be recalled that the collector–emitter breakdown voltage BVceo is directly related to the

Device design issues

131

Figure 4.11. Different collector doping profile and Ge profile (triangular) of a SiGe HBT.

cut-off frequency, according to the theoretical ‘Johnson limit’, and falls monotonically for increasing values of fT [81]. A 50 GHz transistor corresponds to a breakdown voltage of 3.3 V. In general, therefore, some degree of optimization is always required to yield the appropriate higher fT for a lower BVceo . Increasing the peak collector doping density (Ncoll ) above 1 × 1017 cm−3 improves the frequency performance in two ways: (i) a reduction in transit time τbc giving increase in fT ; and (ii) a delay onset of Kirk effect permitting operation at higher collector current density since the Kirk (knee) current density (Jk ) is proportional to the collector doping.

132

Design of SiGe HBTs

In simulations, as a compromise, we have assumed a minimum collector concentration of 5 × 1016 cm−3 at the base–collector junction, and have ramped the doping as shown in figure 4.11. Profiles 1, 2, and 3 correspond to peak values of 1.5 × 1017 cm−3 , 2 × 1017 cm−3 and 4 × 1017 cm−3 at a depth of 0.4 µm. The effects of the different collector profiles on fT are shown in figure 4.12. As expected, profile 3 (highest doping) produces the highest fT of 49 GHz. Early work on achieving high fT with SiGe HBTs utilized collector concentrations in the range 2 to 6 × 1017 cm−3 [82, 83]. These higher collector dopings led to unacceptably high values of Cbc for most circuit

Figure 4.12. Effect of collector doping (ramping) on cut-off frequency.

Device design issues

133

applications, as they increase the input capacitance of the device via the Miller effect. Optimizing the collector profile consists therefore in trading an increased transit time τec , arising from an increase in τbc with reduced collector doping, for a reduction in the base–collector capacitance. This point is considered again in chapter 5 where two variants of a process are considered: one to achieve very short ECL gate delay by using a relatively low collector doping and the other using a much higher collector doping to achieve fT of more than 100 GHz. Figure 4.13 shows the effect of collector doping on the simulated output characteristics. It is evident that the profile with the highest fT yields the lowest BVceo .

Figure 4.13. Effect of collector doping on BVceo .

134 4.7.

Design of SiGe HBTs SMALL-SIGNAL AC ANALYSIS

A useful outcome of physical device simulation is the opportunity to use the results to extract parameters which can be used in a compact model for circuit simulation. The particular virtue of device simulation in this context is the ability to visualize how changes to a particular process or structure affect the overall circuit performance. The whole field of compact modelling for bipolar transistors is extensive, with the Gummel–Poon model, and recently the vertical bipolar inter-company (VBIC) model, widely used [84, 85]. A detailed consideration of these models is beyond the scope of this book. However, by way of illustration, we present an example showing how device simulation can yield component values for a rudimentary small-signal lumped element model. In addition, a method of determining the different components of the transit time by integration of the carrier distribution is also discussed. 4.7.1.

Small-signal equivalent circuit

By treating the bipolar transistor as a two port network, it has been explained in section 4.2 that a device simulator such as ATLAS has the capability to determine all small-signal parameters. It is therefore possible to use these parameters to extract the components of the hybridπ small-signal equivalent circuit as shown in figure 4.14. This equivalent circuit represents a somewhat idealized representation of the transistor and neglects distributed effects of minority carrier storage in the quasi-neutral emitter and base regions [86]. It assumes that all parasitic components associated with resistance, inductance and capacitance of probes, pads and

Figure 4.14. Simplified hybrid-π model of a SiGe HBT.

Small-signal ac analysis

135

interconnects have been successfully de-embedded. In this model, Cbe is the emitter–base capacitance (representing the sum of diffusion and depletion capacitance), rbe is the dynamic emitter resistance, Cbc is the base– collector capacitance, rbb is the base resistance, rcc the collector resistance and ree the emitter resistance. The small-signal transconductance is expressed as [87] gm = gmo exp (−jωτd ) (4.60) where gmo is the low-frequency intrinsic transconductance and τd is the transit time phase delay of transconductance. To determine series resistance, it is most convenient to use small-signal z-parameters, where it can be shown [87] Z11 = rbb + ree +

Zπ 1 + gm Zπ

Zπ 1 + gm Zπ   gm Zπ 1− = ree + 1 + gm Zπ jωCbc Z12 = ree +

Z21

Z22 = rcc + ree + where

1 1 Zπ + jωCbc 1 + gm Zπ 1 + gm Zπ

Zπ =

rbe . 1 + jωrbe Cbe

(4.61) (4.62) (4.63) (4.64) (4.65)

If small-signal ac simulations are carried out at relatively high frequency (typically in the range 0.02–0.1 fT ), then since gmo ≥ 1/|Zπ | 1 gmo

(4.66)

rbb = Re (Z11 − Z12 )

(4.67)

ree = Re (Z12 ) −

rcc = Re (Z22 − Z21 ) −

Cbe . gmo Cbc

(4.68)

The method of extraction of rbb and ree appears to work well, but extraction of rcc is problematic, because rcc is expressed as the small difference between the real parts of Z22 and Z21 , and a further term representing the high-frequency ac output resistance. This latter term, involving a ratio of capacitance, tends to be much larger than the unknown value of rcc , so it proves very difficult to obtain a consistent value of rcc which is independent of the frequency at which it is evaluated. In addition, the accuracy of the second term is dependent on the accuracy of the evaluation of the other three parameters Cbe , Cbc and gmo . None

136

Design of SiGe HBTs

of these parameters are known with absolute certainty and have to be extracted using either y- or h-parameters using Cbc = − Cbe =

Im(y12 ) ω

Im(y11 ) (rbb + rbe )2 − Cbc 2 ω rbe

(4.69) (4.70)

and rbe can be reliably obtained from rbe =

1 − Re(y11 )(rbb + ree ) Re(y11 )

(4.71)

at a frequency low enough that the reactance of Cbe does not affect Re(y11 ). Figure 4.15 shows how the value of base resistance, extracted using equation (4.67), varies with frequency, as collector current is increased. The well-established mechanism of reduction in base resistance at higher collector current due to current crowding is evident in this figure. The choice of frequency is important in so far as one would like to evaluate the base resistance at a frequency where the extracted value is relatively insensitive to the choice of frequency. Based on the pattern of variation seen in figure 4.15, it would appear that extraction of rbb at a frequency of around 1 GHz, significantly below fT would appear to be a reasonable choice.

Figure 4.15. Variation of rbb = Re(Z11 − Z12 ) with frequency.

Small-signal ac analysis

137

Figure 4.16. Extraction of input resistance using (a) h-parameters and (b) z-parameters.

Figure 4.17. Extraction of output resistance using (a) h-parameters and (b) z-parameters.

138

Design of SiGe HBTs

Figure 4.16 shows that the equations (4.67) and (4.68) for rbb and rcc based on z-parameters are relatively independent of frequency in the range 1–8 GHz and it is clear that while rbb can be relatively accurately determined from z-parameters (rather than h-parameters), the small value of rcc , believed to be of the order of 20 ohms from sheet resistance calculations, is masked by the much higher value of more than 200 ohms of the additional term involving the ratio of capacitance. This point is further illustrated in figure 4.17, which shows that the total output resistance can be estimated by two methods: one using z-parameters, the other using h-parameters. As indicated on the figure, both expressions nominally give the same value. Neither equation however, is exact. Both involve a degree of approximation, and the expected value of rcc is of the same order as the likely error in using either of the two expressions. This example highlights the difficulty which can occur in determining collector series resistance from small-signal parameters. To evaluate gm , it transpires that the most appropriate method is to use h-parameters, rather than y-parameters. It has been shown that for the small-signal equivalent circuit shown [34] gm =

Re(h21 ) . Re(h11 )

(4.72)

Figure 4.18 shows that the above equation involving the ratio of

Figure 4.18. Extraction of gm using (a) y-parameters and (b) h-parameters.

Small-signal ac analysis

139

h-parameters is more reliable in estimating the transconductance, gm . Use of Re(y21 )/ω always underestimates gm , because it takes no account of the effect of the voltage divider ratio due to rbb and rbe . This correction of course requires accurate values of rbb and rbe so the computation using h-parameters is always liable to be more reliable. 4.7.2.

Evaluation of transit time

While small-signal analysis is useful in extracting fT from |h21 |, it does not permit insight into the magnitude of the individual components that comprise the total transit time τec . To find the individual components of τec from device simulation, it is necessary to integrate the carrier concentration within defined regions of the transistor, according to the analysis given in [88]. When the semiconductor equations are solved numerically, the carrier concentration is known at every node in the structure. Hence, it is relatively straightforward to integrate the carrier concentration numerically to give the individual components of transit time. The total transit time is given by  xbc L xeb q τec = ∆n(x)dx + ∆n(x)dx + ∆n(x)dx . (4.73) ∆Jc 0 xbc xeb Here we define the individual components by the incremental relationships: •

•

•

•

•

emitter–base depletion charging time xeb q (∆n(x) − ∆p(x)) dx τeb = ∆Jc 0 base–collector depletion charging time L q τbc = (∆n(x) − ∆p(x)) dx ∆Jc xbc emitter transit time τe =

q ∆Jc

τb =

q ∆Jc

base transit time

collector transit time q τc = ∆Jc



xeb

(4.76)

∆n(x)dx

(4.77)

∆p(x)dx.

(4.78)

xbc

xeb



L

xbc

(4.75)

∆p(x)dx

0



(4.74)

140

Design of SiGe HBTs

In the formulation given, the integration is implicitly defined as onedimensional through the active transistor region, where x = 0 defines the emitter contact, and x = L the collector contact. In this analysis, for simplicity, the parameters xeb and xbc define the respective positions of emitter–base and base–collector metallurgical junctions. A more rigorous definition of these two points, as the points of intersection of dp/dJc and dn/dJc , is given in [88]. This definition is, however, difficult to implement in a 2D device simulator and has not been used. The values of differential carrier densities ∆n(x) and ∆p(x) can be computed by perturbing the dc bias by a small amount, to induce a small change in collector current density ∆Jc . The value of emitter– collector transit time τec , computed using this method, is comparable (but not exactly identical) to the value of the SPICE parameter τF obtained from the y-intercept of the graph of 1/(2πfT ) versus 1/Ic as defined in equation (3.31) [89]. However, it should be borne in mind that all components of τec will vary to some extent with bias condition, whereas τF is an absolute value defined as 1/Ic → 0. Both emitter and base transit times are relatively insensitive to collector current but increase as expected at the onset of high injection leading to a fall in fT [90]. Figure 4.19 shows the relative magnitudes of the components of transit time based on a simulation of a state-of-the-art HBT with a base width of 40 nm, a Gaussian base doping profile with peak 1.5 × 1019 cm−3 and a low-doped emitter of 1018 cm−3 . The transit times were evaluated as a function of bias condition using equations (4.74)–(4.78). The simulated maximum unity gain cut-off frequency for this transistor based on h21 is 38 GHz, while the corresponding value of τF from figure 4.20 is 3.6 ps. For comparison, if transit times are computed directly the

Figure 4.19. Variation of transit time components with collector current.

Small-signal ac analysis

141

Figure 4.20. Extraction of SPICE parameter, τF from variation of fT with collector current.

minimum value of τec before onset of high injection is 3.75 ps at a collector current of 7 mA. It should also be pointed out that, while the y-intercept of the extrapolated straight line in figure 4.20 gives τF , its slope represents the sum of the depletion capacitance Cje + Cjc as defined in equation (3.35). This represents an alternative method for the determination of parasitic capacitance to the use of y-parameters. 4.7.3.

ECL gate delay

Unlike the frequencies fT and fmax , there is no standard analytical expression universally accepted for the propagation delay of an ECL gate. This gate delay, which normally represents a performance measure for digital circuits, depends not only on the intrinsic characteristics of the transistor, but also on the circuit configuration and the values of load resistance and capacitance. The unloaded ECL gate delay exhibits a similar sensitivity to intrinsic device transit time, parasitic resistance and capacitance as fmax . At low switching current levels, the gate delay is dominated by the base–collector capacitance, which is dependent on the device structure and layout geometry, whereas at high current levels the delay is more strongly coupled to the total base resistance and the transit time of the device. Approximate expressions for the gate delay for specific circuits have been used by Kroemer [91] and by Shafi et al [92] for the ECL circuits employing SiGe HBTs. The expression used by Kroemer is given by τdel =

5 rbb τF + (3Cbc + CL ) RL rbb Cbc + 2 RL

(4.79)

142

Design of SiGe HBTs

where RL is the load resistance and CL is the load capacitance of the circuit. The importance of reducing the base resistance to improve the speed is obvious from this equation (4.79). It is clear that a reduction in rbb will improve the switching time until the first two terms become small and the final term involving RL dominates. Further improvement can only be obtained by reducing base–collector capacitance. The importance of the above result lies not in the actual numerical values of different terms but in that it demonstrates the relative importance of the various transistor parameters in determining its speed. Shafi et al [92] have used a different approach to calculate the gate delay in an ECL circuit. Their calculations are based on the weighting factors developed by Fang [93]. The calculations using this method were compared with direct SPICE simulations and the two results agreed within 5% for the specific technology considered. The propagation delay is expressed as a sum of RC time constants and stored charge elements: τdel =

Ki Ri Ci + Kj τec

(4.80)

i

where summation over i includes all the resistances and capacitances of the logic gate and those associated with the emitter, base and collector of all the transistors in the circuit. Shafi et al [92] calculated the numerical values of gate delay for SiGe HBTs and compared these with similar computations for homojunction devices. A Ge concentration of 12% was shown to be required in the SiGe base to provide sufficient gain enhancement to allow the reversal of the usual emitter and base doping concentrations. This results in a transistor with a low base resistance and low emitter–base depletion capacitance. For a fully optimized device, predicted propagation delays were 15 ps for the SiGe HBT and 29 ps for the Si BJT. Subsequently, as SiGe technology has developed over the last decade, bipolar scaling to ultrathin base and 0.2 µm self-aligned technology has given rise to a propagation delay as low as 6.7 ps by a research group from Hitachi [75]. In order to simulate ECL delay, circuit simulation using SPICE must be used. If the two-dimensional structure of the transistor is known, device simulation can be used to extract key SPICE parameters such as τF , Cje , Cjc and rbb from small-signal ac analysis, as illustrated in the previous section. These SPICE parameters can then be used in a circuit simulation to predict variation in ECL gate delay with collector current. The advantage of this approach is that it provides insight into how the process can affect the circuit performance. Table 4.1 presents a representative sample of key SPICE parameters extracted for a scaled SiGe HBT process based on silicon-on-insulator (SOI) technology [94]. The technology, outlined more fully in chapter 5, utilizes an epitaxial base and lightly-doped emitter. To allow for effects of boron

Small-signal ac analysis

143

out-diffusion the base profile is assumed to be Gaussian. In table 4.1, two sets of process parameters are considered. In the set labelled (a) the emitter doping is 1018 cm−3 , while in the set labelled (b), the emitter doping is reduced to 1016 cm−3 . The key issue illustrated by table 4.1 is to examine whether use of a lower doping density in the emitter spacer layer can improve ECL gate delay. A more lightly-doped emitter will of course degrade the overall transit time and hence fT , but does yield a significantly lower emitter– base junction capacitance. This lower junction capacitance gives a marked improvement in ECL gate delay particularly at lower collector currents,

Table 4.1. SPICE parameters for a SiGe HBT. Transistor parameters

(a)

(b)

Base dose Emitter doping (n-type) Collector doping Mask alignment tolerances Ge fraction x Low-doped emitter width Wepi Base width Wb

1.2 × 1013 cm−2 1 × 1018 cm−3 1 × 1017 cm−3 0.25 µm 0.1 0.05 µm 0.038 µm

1.2 × 1013 cm−2 1 × 1016 cm−3 5 × 1016 cm−3 0.25 µm 0.1 0.03 µm 0.045 µm

356 3.0 ps 81 Ω 42 Ω 50.8 fF 13.5 fF 2.2 fF 75 V

190 4.2 ps 68 Ω 63 Ω 14.7 fF 10.0 fF 2.2 fF 101 V

38 GHz

29 GHz

48 GHz

56 GHz

36.2 35.1 29.8 39.0 21.7 18.4

31.0 38.3 30.6 24.3 16.7 15.5

Extracted SPICE parameters Forward current gain (β) Transit time τF Base resistance rbb at 1 mA Collector resistance rcc Emitter junction capacitance Cje Collector junction capacitance Cjc Collector substrate capacitance Cjs Early voltage VA Extracted small-signal parameters Cut-off frequency fT from h21 Maximum oscillation frequency fmax (MAG) SPICE circuit simulations Cut-off frequency fT at Ic = 5 mA Maximum oscillation frequency fmax SOI Maximum oscillation frequency fmax Si ECL gate delay at 0.5 mA ECL gate delay at 1 mA ECL gate delay at 5 mA

GHz GHz GHz ps ps ps

GHz GHz GHz ps ps ps

144

Design of SiGe HBTs

Figure 4.21. Dependence of fmax on emitter–polySi length.

well below the current level at which peak fT is predicted. In addition, the creation of the bipolar transistor in an SOI rather than a silicon substrate yields approximately 20% improvement in fmax due to lower collector– substrate capacitance in the SOI substrate, as shown in figure 4.21. In this figure, circuit simulation using SPICE parameters extracted from ATLAS has been used to determine fmax . With the simulated values of base resistance as an input parameter for SPICE, ECL gate delays have been computed as a function of base resistance and are tabulated in table 4.2. It is seen that, as expected, the ECL gate delay decreases with the decrease in rbb and the minimum value is comparable to the experimentally reported values for a SiGe HBT of comparable dimensions [95]. Table 4.2. The dependence of ECL gate delay on base resistance. SPICE parameters used: VAF = 130 V, Cje = 7.5 pF, Cjs = 13 pF, Cjc = 5.5 pF. Base resistance

Gate delay (ps)

200 100 50 25

17.1 14.7 13.3 12.5

Summary 4.8.

145

SUMMARY

This chapter has considered how a SiGe HBT can be modelled in a device simulator. The relevant equations, relating to current flow in a structure where the bandgap is varying, were considered. Basic concepts employed in a simulation program were given. Key material parameters for SiGe, in so far as they differ from silicon, were outlined. A more accurate strained layer SiGe mobility model should be used to take into account the different mobilities (parallel and perpendicular to the growth direction) of the strained-SiGe layer. The way in which ac simulation can be utilized to determine smallsignal y-parameters was considered. Knowledge of y-parameters then permits any other small-signal parameter to be evaluated. In this way, both fT and fmax can be determined. A specific study of the design of an HBT with a base width of approximately 60 nm was fully described. Base, emitter and collector profile design issues were discussed in detail. High βVA product necessary for analogue applications is of special interest, as it is achievable using SiGe HBTs. Devices with three different Ge profiles (flat, triangular and trapezoid) were considered. The optimum Ge profile in the base was shown to be a trapezoidal profile. A retrograde collector profile allowed the condition fT = fmax to be optimized, whilst still achieving acceptable BVceo . The significance of the ECL gate delay and the way in which device simulation can be used to predict ECL gate delay was outlined. Gate delays of ECL circuits involving SiGe HBTs were computed using SPICE parameters extracted using small-signal analysis. BIBLIOGRAPHY [1] Gummel H K 1964 A self-consistent iterative scheme for one-dimensional steady-state transistor calculations IEEE Trans. Electron Devices 11 455– 65 [2] DeMari A 1968 An accurate numerical steady-state one-dimensional solution of the P–N junction Solid-State Electron. 11 33–58 [3] Scharfetter D L and Gummel H K 1969 Large-signal analysis of a silicon read diode oscillator IEEE Trans. Electron Devices 16 64–77 [4] D’Avanzo D C, Vanzi M and Dutton R W 1979 One-dimensional semiconductor device analysis (SEDAN) Report G-201-5 Stanford University [5] Selberherr S, Schutz A and Potzl H W 1980 MINIMOS—a Two-Dimensional MOST Transistor Analyser IEEE Trans. Electron Devices 27 1540–50 [6] Franz A F and Franz G A 1985 BAMBI—a design model for power MOSFETs IEEE Trans. Comput.-Aided Des. 4 177–89 [7] Pinto M R 1985 PISCES-IIB Manual (Stanford, CA: Stanford University) [8] Silvaco International 1997 Silvaco–ATLAS Manual, Ver 4.0

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Design of SiGe HBTs

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heterostructures IEEE J. Quantum Electron. 22 1696–710 [47] Manku T, McGregor J M, Nathan A, Roulston D J, Noel J-P and Houghton D C 1993 Drift hole mobility in strained and unstrained doped Si1−x Gex alloys IEEE Trans. Electron Devices 40 1990–6 [48] del Alamo J A, Swirhun S and Swanson R M 1985 Simultaneous measurement of hole lifetime, hole mobility and bandgap narrowing in heavily-doped n-type silicon IEEE IEDM Tech. Dig. pp 290–3 [49] Swirhun S E, Kwark Y H and Swanson R M 1986 Measurement of electron lifetime, electron mobility and bandgap narrowing in heavily-doped p-type silicon IEEE IEDM Tech. Dig. pp 24–7 [50] Klaassen D B M, Slotboom J W and de Graaff H C 1992 Unified apparent bandgap narrowing in n- and p-type silicon Solid-State Electron. 35 125–9 [51] Poortmans J, Jain S C, Totterdell D H J, Caymax M, Nijs J F, Mertens R P and van Overstraeten R 1993 Theoretical calculations and experimental evidence of the real and apparent bandgap narrowing due to heavy doping in p-type Si and strained Si1−x Gex layers Solid-State Electron. 36 1763–71 [52] Jain S C and Roulston D J 1991 A simple expression for band gap narrowing (BGN) in heavily-doped Si, Ge, GaAs and Gex Si1−x strained layers SolidState Electron. 34 453–65 [53] Dziewior J and Schmid W 1977 Auger coefficients for highly-doped and highly excited silicon Appl. Phys. Lett. 31 346–8 [54] Fossum J G 1976 Computer-aided numerical analysis of solar cells SolidState Electron. 19 269–77 [55] McGregor J M, Roulston D J, Hamel J S, Vaidyanathan M, Jain S C and Bulk P 1993 A simple expression for ECL propagation delay including non-quasi-static effects Solid-State Electron. 36 391–6 [56] Pejcinovic B, Kay L E, Tang T W and Navon D H 1989 Numerical simulation and comparison of Si BJTs and Si1−x Gex HBTs IEEE Trans. Electron Devices 36 2129–37 [57] Chen J, Gao G B and Morkoc H 1992 Comparative analysis of the highfrequency performance of Si/Si1−x Gex heterojunction bipolar and Si bipolar transistors Solid-State Electron. 35 1037–44 [58] Roulston D J and McGregor J M 1992 Effect of bandgap gradient in the base region of SiGe heterojunction bipolar transistors Solid-State Electron. 35 1019–20 [59] Gao G-B and Morkoc H 1991 Base transit time for SiGe-base heterojunction bipolar transistors Electron. Lett. 27 1408–10 [60] Won T and Morkoc H 1989 High speed performance of Si/Si1−x Gex heterojunction bipolar transistors IEEE Electron Device Lett. 10 33–5 [61] Hueting R J E, Slotboom J W, Pruijmboom A, de Boer W B, Timmering E C and Cowern N E B 1996 On the optimization of SiGe-base bipolar transistors IEEE Trans. Electron Devices 43 1518–24 [62] Nuernbergk D M, Forster H, Schwierz F, Yuan J S and Paasch G 1997 Comparison of Monte Carlo, energy transport, and drift–diffusion simulations for an Si/SiGe/Si HBT High Performance Electron Devices for Microwave and Optoelectronic Applications, EDMO pp 19–24 [63] Jungemann C, Bartels M, Keith S and Meinerzhagen B 1998 Efficient methods for Hall factor and transport coefficient evaluation for electrons

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and holes in Si and SiGe based on a full-band structure Extd. Abstr. Sixth Int. Workshop on Computational Electronics, IWCE-6 pp 104–7 Keith S, Jungemann C, Decker S, Neinhus B, Bartels M and Meinerzhagen B 1999 Full-band Monte Carlo device simulation of an Si/SiGe HBT with a realistic Ge profile Int. Conf. on Simulation of Semiconductor Processes and Devices, SISPAD’99 pp 219–22 Bartels M, Decker S, Neinhus B, Bacht K H, Schuppen A and Meillerzhagen B 1999 Comprehensive hydrodynamic simulation of an industrial SiGe heterobipolar transistor IEEE BCTM Proc. pp 105–8 Comfort J H, Patton G L, Cressler J D, Lee W, Crabbe E F, Meyerson B S, Sun J Y-C, Stork J M C, Lu P-F, Burghartz J N, Warnock J, Scilla G, Toh K-Y, D’Agostino M, Stanis C and Jenkins K 1990 Profile leverage in self-aligned epitaxial Si or SiGe base bipolar technology IEEE IEDM Tech. Dig. pp 21–4 Burghartz J N, Comfort J H, Patton G L, Meyerson B S, Sun J Y-C, Stork J M C, Mader S R, Stanis C L, Scilla G J and Ginsberg B J 1990 Self-aligned SiGe-base heterojunction bipolar transistor by selective epitaxy emitter window (SEEW) technology IEEE Electron Device Lett. 11 288–90 Harame D, Nguyen-Ngoc D, Stern K, Larson L, Case M, Kovacic S, Voinigescu S, Cressler J, Tewksburg T, Gorves R, Eld E, Sunderland D, Rensch D, Jeng S, Malinowski J, Gilbert M, Schonenberg K, Ahlgren D and Meyerson B 1995 SiGe HBT technology: device and application issues IEEE IEDM Tech. Dig. pp 731–4 Crabbe E F, Comfort J H, Lee W, Cressler J D, Meyerson B S, Megdanis A C, Sun J Y-C and Stork J M C 1992 73 GHz self-aligned SiGe-base bipolar transistors with phosphorus-doped polysilicon emitters IEEE Electron Device Lett. 13 259–61 Meyerson B S 1986 Low temperature silicon epitaxy by ultrahigh vacuum/chemical vapor deposition Appl. Phys. Lett. 48 797–9 Patton G L, Stork J M C, Comfort J H, Crabbe E F, Meyerson B S, Harame D L and Sun J Y-C 1990 SiGe-base heterojunction bipolar transistors: physics and design issues IEEE IEDM Tech. Dig. pp 13–16 Gruhle A, Kibbel H, Konig U, Erben U and Kasper E 1992 MBE-grown Si/SiGe HBTs with high β, fT and fmax IEEE Electron Device Lett. 13 206–8 Schuppen A, Erben U, Gruhle A, Kibbel H, Schumacher H and Konig U 1995 Enhanced SiGe heterojunction bipolar transistors with 160 GHz fmax IEEE IEDM Tech. Dig. pp 743–6 Meister T F, Schafer H, Franosch M, Molzer W, Aufinger K, Scheler U, Walz C, Stolz M, Boguth S and Bock J 1995 SiGe base bipolar technology with 74 GHz fmax and 11 ps gate delay IEEE IEDM Tech. Dig. pp 739–42 Washio K, Kondo M, Ohue E, Oda K, Hayami R, Tanabe M, Shimamoto H and Harada T 1999 A 0.2 µm self-aligned SiGe HBT featuring 107 GHz fmax and 6.7 ps ECL IEEE IEDM Tech. Dig. pp 557–60 Zerounian N, Aniel F, Adde R and Gruhle A 2000 SiGe heterojunction bipolar transistor with 213 GHz fT at 77 K Electron. Lett. 36 1076–8 Harame D L, Stork J M C, Meyerson B S, Hsu K Y J, Cotte J, Jenkins K A,

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Design of SiGe HBTs Cressler J D, Restle P, Crabbe E F, Subbanna S, Tice T, Scharf B W and Yasaitis J A 1993 Optimization of SiGe HBT technology for high speed analog and mixed-signal applications IEEE IEDM Tech. Dig. pp 874–6 Crabbe E F, Comfort J H, Cressler J D, Sun J Y-C and Stork J M C 1993 High-low polysilicon-emitter SiGe-base bipolar transistors IEEE Electron Device Lett. 14 478–80 Crabbe E F, Cressler J D, Patton G L, Stork J M C, Comfort J H and Sun J Y-C 1993 Current gain rolloff in graded-base SiGe heterojunction bipolar transistors IEEE Electron Device Lett. 14 193–5 Lu P-F, Comfort J H, Tang D D, Meyerson B and Sun J Y-C 1990 The implementation of a reduced-field profile design for high-performance bipolar transistors IEEE Electron Device Lett. 11 336–8 Johnson E O 1965 Physical limitation on frequency and power parameters of transistors RCA Rev. pp 163–77 Patton G L, Comfort J H, Meyerson B S, Crabbe E F, Scilla G J, de Fresart E, Stork J M C, Sun J Y-C, Harame D L and Burghartz J 1990 63–75 GHz fT SiGe-base heterojunction bipolar technology Dig. of Symp. on VLSI Technol. pp 49–50 Patton G L, Comfort J H, Meyerson B S, Crabbe E F, Scilla G J, De Fresart E, Stork J M C, Sun J Y-C, Harame D L and Burghartz J N 1990 75 GHz fT SiGe-base heterojunction bipolar transistors IEEE Electron Device Lett. 11 171–3 Antognetti P and Massobrio G 1987 Semiconductor Device Modeling with SPICE (New York: McGraw-Hill) McAndrew C C, Seitchik J A, Bowers D F, Dunn M, Foisy M, Getreu I, McSwain M, Moinian S, Parker J, Roulston D J, Schroter M, van Wijnen P and Wagner L F 1996 VBIC95, the vertical bipolar inter-company model IEEE J. Solid-State Circuits 31 1476–83 Hamel J S 1996 An accurate charge control approach for modelling excess phase shift in the base region of bipolar transistors IEEE Trans. Electron Devices 43 1092–8 Lee S, Ryum B R and Kang S W 1994 A new parameter extraction technique for small-signal equivalent circuit of polysilicon emitter bipolar transistors IEEE Trans. Electron Devices 41 233–8 Van den Biesen J J H 1986 A simple regional analysis of transit times in bipolar transistors Solid-State Electron. 29 529–34 Ashburn P 1988 Design and Realization of Bipolar Transistors (Chichester: Wiley) Roulston D J 1990 Bipolar Semiconductor Devices (Singapore: McGrawHill) Kroemer H 1982 Heterojunction bipolar transistors and integrated circuits Proc. IEEE 70 13–25 Shafi Z A, Ashburn P and Parker G J 1990 Predicted propagation delay of Si/SiGe heterojunction bipolar ECL circuits IEEE J. Solid-State Circuits 25 1268–76 Fang W 1990 Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits IEEE J. Solid-State Circuits 25 572–83

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Chapter 5 SIMULATION OF SIGE HBTS

In chapter 3, we discussed the operating principle of a SiGe HBT, while in chapter 4 we focused on the basics of physical device simulation and gave some examples of its application. In particular, it has been shown that 2D simulations may be used with confidence for an accurate prediction of device performance. In this chapter, we develop this concept further by considering the simulation of some state-of-the-art SiGe HBTs, concentrating on those that have given particularly noteworthy performance. As SiGe technology continues to develop with device scaling, performance will naturally tend to improve, so we are only endeavouring to present particular examples in some detail. In section 5.2, we consider the device described by Meister et al [1]. This device was noteworthy in 1995 as the epitaxial-base (epi-base) bipolar technology was extended to SiGe technology, leading to a maximum oscillation frequency of 74 GHz and a CML gate delay time of 11 ps. In section 5.3, a later generation device [2] is simulated. In this device, particular attention has been paid to reproducing the two-dimensional structure. Excellent agreement in both fT and fmax has been achieved. In section 5.4, we show how, in a transistor with a very thin base, conventional drift–diffusion simulation tends to overestimate the transit time and a hydrodynamic simulation can in principle give a more accurate result for a transistor when fT exceeds 100 GHz. If SOI material is used as a substrate in a bipolar transistor, significant reduction in collector–substrate capacitance can be achieved with consequent improvement in fmax [3]. However, self-heating of the silicon island in which the HBT is formed can be problematic [4, 5]. In section 5.5, a thermal simulation of a SiGe HBT fabricated in an SOI substrate is presented. Problems encountered for the low-temperature operation of Si BJTs can be solved effectively by using heterojunction technology. Section 5.6 describes examples of low-temperature simulation. Because of its bandgap152

Simulation of SiGe HBTs

153

engineered base, the SiGe HBT is particularly suitable for operation at cryogenic temperature [6–12]. Since the bandgap of the emitter is larger than that of the base, therefore the current gain increases at low temperature. Since doping in the base of an HBT can be very high, carriers do not freeze at low temperature. While most digital applications involve the use of ECL technology, SiGe technology offers the potential for reducing the delay of an integrated injection logic (I2 L) gate. I2 L is a low-power bipolar technology suitable for VLSI which traditionally has suffered from a relatively poor dynamic performance. There has been renewed interest in I2 L, motivated by the impressive performance reported for SiGe HBTs [13,14]. The gate delay of I2 L circuits is primarily determined by stored charge in parasitic diodes

Figure 5.1. Doping profile and Ge profile (graded base) of a SiGe HBT.

154

Simulation of SiGe HBTs

associated with the extrinsic base region [15]. The lower bandgap of SiGe therefore has a great impact on the propagation delay of integrated injection logic. It is shown by simulation in section 5.7 that that SiGe I2 L may be a useful technology in high-performance and low-power applications, such as portable electronic systems [16]. As SiGe HBT technology appears to be exceptionally promising for RF and microwave analogue applications, the low-frequency noise performance, a key figure-of-merit, needs to be studied in detail. Section 5.8 presents a comprehensive study on the noise performance of SiGe HBTs with

Figure 5.2. Gummel plot of a graded base SiGe HBT.

Epitaxial-base SiGe HBT (1995)

155

comparison to AlGaAs/GaAs HBTs and conventional Si BJTs fabricated in different technologies. Finally, in section 5.9, the potential for SiGe technology in a radiation intensive environment is considered. 5.1.

EPITAXIAL-BASE SIGE HBT (1995)

In chapter 4, we established that, to design a high-performance HBT, it was desirable to use a low-doped emitter, thin base with a graded Ge profile and retrograde collector profile. In this section, the accuracy of the simulation is assessed, by comparison with devices recently reported in the literature. To optimize the high-frequency performance of a device, a nominal target of fT ∼ fmax was used.

Figure 5.3. The dc current gain of a graded base SiGe HBT.

156

Simulation of SiGe HBTs

Epi-base technology has many advantages over ion-implanted technology. An implantation tail can be avoided and the resultant box-like doping profile provides independent control over base width and doping concentration. Using epi-base technology, Meister et al [1] have reported an experimental SiGe HBT. A base width of about 500 ˚ A and a peak base doping concentration (6 × 1018 cm−3 ) were used. The structure, including the Ge and doping profiles used in simulation, is shown in figure 5.1. The Ge concentration in the base has been graded from 0% at the emitter–base junction to 12% at the centre of the base.

Figure 5.4. Typical output characteristics of a graded base SiGe HBT as a function of collector doping.

Epitaxial-base SiGe HBT (1995)

157

Figure 5.2 shows the simulated Gummel plot and it is seen that almost ideal base current characteristics are observed, with a peak dc current gain of approximately 210, as shown in figure 5.3. A unilateral power gain of 22 dB at 10 GHz was achieved at a base–collector voltage of 2 V. Even for a base width of about 500 ˚ A, a high base doping (> 6 × 1018 cm−3 ) maintains a low base resistance and avoids punch-through. In particular, the high fmax of 74 GHz originates from the integration of the SiGe base, providing high cut-off frequency at low intrinsic base resistance. The design can be tailored for optimum ECL or CML performance by obtaining high fT at low base resistance leading to a CML gate delay time of 11 ps. The effect of collector doping on the Early voltage obtained from the simulated output characteristics is shown in figure 5.4. These characteristics are obtained by utilizing a constant base current, (Ib = 15 nA), as opposed to the more usual fixed base voltage boundary conditions. It is seen that as the collector doping concentration increases, the Early voltage decreases. This reduction in Early voltage with the increase in collector doping density is expected from the consideration of equation (3.25) in chapter 3, as a higher collector concentration gives a higher base–collector capacitance and hence lower Early voltage. The Early voltage for the lowest collector doping of 5 × 1016 cm−3 is 110 V, leading to a βVA product of 22 000. A Ge fraction of 12% at the base–collector junction has helped to provide a high Early voltage. The dependence of cut-off frequency on the collector current is shown in figure 5.5 for two different base–collector voltages, while figure 5.6 shows

Figure 5.5. Effect of base–collector reverse bias voltage on the cut-off frequency of a graded base SiGe HBT.

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Simulation of SiGe HBTs

Figure 5.6. Cut-off frequency versus Ic of a graded base SiGe HBT.

a comparison of simulated and measured fT with collector current. It is evident that while the overall match is good, indicating good agreement of emitter–base and base–collector capacitance, the simulated values are slightly below the measured values. It is believed that this may be due to a small inaccuracy in the drift–diffusion model in predicting base transit time in thin base transistors. This point is more fully discussed in section 5.3. A direct comparison of major experimental and simulated figures-of-merit is shown in table 5.1. While excellent agreement has been obtained for fT , the simulation overestimates fmax , possibly due to an underestimate of base resistance.

Table 5.1. Comparison of simulated device parameters. Parameter

Experimental [1]

Simulation

Emitter size, Ae Current gain, β Breakdown voltage, BVceo Early voltage, VA Cut-off frequency, fT Maximum frequency oscillation, fmax

0.27 × 2.5 µm 220 3.0 130 V 61 GHz 74 GHz

210 3.0 120 V 57 GHz 105 GHz

Double polysilicon self-aligned SiGe HBT (1998) 5.2.

159

DOUBLE POLYSILICON SELF-ALIGNED SIGE HBT (1998)

In this section we consider an alternative SiGe HBT, discussed by Kondo et al [2]. The device structure is illustrated in detail in figure 5.7. It has the same structure as a conventional double polysilicon bipolar transistor. A borophosphosilicate (BPSG) refilled trench is used for isolation. Since the dielectric constant of BPSG is about one third that of silicon, substrate capacitance is therefore minimized. A wedge-shaped CVD silicon dioxide isolation structure below the p+ -polySi base electrode helps reduce base– collector capacitance. Both SiGe base and polySi SiGe contact are selfaligned on the n-collector and p+ -polySi SiGe sidewall inside the window. Hence, the width of the base–collector junction has been reduced to that of the 0.5 µm emitter window. The intrinsic base consists of a 200 ˚ A undoped SiGe layer, a 300 ˚ A − ˚ p -type graded SiGe layer and a 150 A undoped silicon layer. A SIMS plot is shown in figure 5.8. For ATLAS simulation, the peak emitter doping of 1020 cm−3 (n+ -type), the peak base doping of 5 × 1018 cm−3 (p-type) and the collector doping of 5×1016 cm−3 (n-type) were considered. The characteristic length of the Gaussian base profile is 0.0145 µm. The germanium fraction x is graded linearly, from a peak value of 0.145, down to zero at the emitter–base junction. Full details of the simulation are given in [17].

Figure 5.7. Schematic cross section of the ultra low-power SiGe base bipolar transistor with a wedge-shaped CVD-SiO2 isolation and a BPSG-refilled trench. (After Kondo M et al 1998 IEEE Trans. Electron Devices 45 1287–94.)

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Simulation of SiGe HBTs

Figure 5.8. A SIMS impurity profile of the emitter and the base in the intrinsic region. (After Kondo M et al 1998 IEEE Trans. Electron Devices 45 1287–94.)

Figure 5.9. Comparison of Gummel plot for a SiGe HBT. (After Hamel J S and Tang Y T 2000 Proc. ESSDERC pp 620–3.)

The Gummel plot simulated by ATLAS is shown in figure 5.9, along with the published result for comparison. Since great care has been taken to model both the doping profile and two-dimensional structure, excellent agreement has been achieved for the collector current. The higher

Double polysilicon self-aligned SiGe HBT (1998)

161

Figure 5.10. Comparison of simulated and experimental fmax and fT as a function of collector current. (After Hamel J S and Tang Y T 2000 Proc. ESSDERC pp 620–3.)

base current simulated by ATLAS could be due to lower hole lifetime in the emitter, but insufficient detail regarding the polysilicon interface is available in the original paper [2] to enable more precise modelling. The respective simulated and published values of fT and fmax have been compared in figure 5.10. The agreement is excellent with the simulation showing a peak fmax of 70 GHz and a peak fT of 40 GHz at around 200 µA. It would appear therefore that inaccuracy in the simulated base current does not affect the accuracy of the high-frequency modelling. Subsequently, this transistor has been used as the basis of a simulation study which offers a comparison between vertical and lateral HBTs [18]. The simulation predicts a potential twofold improvement in fmax , and at significantly lower bias current compared to the vertical SiGe HBT, for a given minimum lithography. The relevant comparison is shown in figure 5.11. The improved fmax is attributed to an order of magnitude improvement in the rbb Cbc time constant in the lateral HBT. Although specific device structures were utilized, the same active region profiles and identical minimum lithography ensured a meaningful comparison. The factor of two improvement predicted for lateral SiGe HBT on SOI technology gives a general indication as to how bipolar technology is likely to evolve over the next decade. As minimum lithography decreases, the SOI layer thickness in the lateral HBT can be made thinner to continue to provide improvement in performance.

162

Simulation of SiGe HBTs

Figure 5.11. Comparison of frequency performance versus dc collector current between vertical and lateral SiGe HBTs. (After Hamel J S and Tang Y T 2000 Proc. ESSDERC pp 620–3.)

5.3.

ENERGY BALANCE SIMULATION

As discussed in chapter 4, the drift–diffusion approximation can lead to inaccuracy in the prediction of device characteristics, particularly when the width of the base is reduced below 30 nm. In this instance, it is necessary to perform a simulation involving energy balance [19], where the equations for current flow must be modified as given in equations (4.18)–(4.21). The conventional drift–diffusion model of charge transport neglects non-local transport effects such as velocity overshoot, diffusion associated with carrier temperature gradients and dependence of ionization rates on carrier energy distribution. The drift–diffusion approximation is a low-order approximation of the Boltzmann transport equation (BTE). Device simulation based on the solution of the full BTE is possible but requires significant computing resources. A simpler intermediate level approximation, which offers potential for improved accuracy, is therefore attractive. Essentially, the energy balance model predicts velocity overshoot relative to the carrier saturation velocity defined in equation (4.28). Velocity peaks occur in regions of the device where carrier temperature is a maximum e.g., base–collector junction. High velocity gives rise to reduced transit time compared to the drift–diffusion model. The device considered for simulation [20] is a state-of-the-art SiGe HBT, designed to give a very high fT by incorporating a high dose selective collector implant of peak concentration of the order of 1018 cm−3 . The

Energy balance simulation

163

Figure 5.12. Germanium and doping profile for a SiGe HBT with 15% Ge content. (After Oda K et al 1997 IEEE IEDM Tech. Dig. pp 791–4.)

SIMS profile of the transistor, with a 15% graded Ge profile is shown in figure 5.12. This profile has been accurately reproduced in the input datafile for ATLAS simulation. This transistor is very similar to that described in the previous section. It only differs in two respects: a much higher doping density in the collector and the location of the peak collector doping lying closer to the base–collector. It was reported that the measured peak fT ranges from 110 GHz for a peak Ge content (x = 0.1) to 130 GHz (x = 0.25), as shown in figure 5.13. The simulated maximum cut-off frequency has been plotted as a function of peak collector doping in figure 5.14. It is clear that the drift– diffusion model predicts a maximum fT of less than 100 GHz, irrespective of the value of peak collector doping. It seems that in order to predict an fT of more than 100 GHz to match the measured value, the energy balance model appears to be required. This conclusion is in line with the observations in figure 5.6, where once again the simulated fT is less than the measured value. The differences between the energy balance and drift–diffusion models on emitter and base transit times are shown in figure 5.15. It is clear that the EB model predicts significantly lower values of base transit times, sufficient to account for the higher measured values of fT . A comparison of extracted carrier velocity for the DD and EB models,

164

Simulation of SiGe HBTs

Figure 5.13. Maximum cut-off frequency as a function of Ge content. (After Oda K et al 1997 IEEE IEDM Tech. Dig. pp 791–4.)

Figure 5.14. Cut-off frequency versus peak collector doping in a graded base SiGe HBT.

Energy balance simulation

165

Figure 5.15. Simulated emitter and base transit time of a SiGe HBT, as a function of collector current for both drift–diffusion and energy balance models for Ge mole fraction x = 0.1.

Figure 5.16. Extracted carrier velocity using drift–diffusion and energy balance models.

166

Simulation of SiGe HBTs

Figure 5.17. Simulated electron temperature in a SiGe HBT.

as a function of base bias, for two Ge fractions (x = 0.1 and 0.2), is shown in figure 5.16. The EB model shows a significant overshoot in the saturation velocity, sufficient to account for the lower base transit time in figure 5.15, while the maximum velocity possible with the DD model is limited by the saturation velocity, vsat = 8 × 106 cm s−1 . A plot of the simulated electron temperature in figure 5.17, taken as a one-dimensional section through the active device, shows the expected carrier heating associated with the high-field region at the base–collector junction. The maximum of the temperature profile is, however, shifted into the collector region, as the carriers are accelerated through the high-field region to reach the maximum temperature. Velocity overshoot occurs in the base region, where the electric field is high and the temperature is only beginning to rise. 5.4.

SIGE HBTS ON SOI SUBSTRATES

In Si bipolar technology, the two well-known disadvantages are: high power dissipation and low density. High power dissipation is a result of the high parasitic junction capacitance associated with using silicon as the substrate. Previously, silicon-on-insulator has been used for high-performance deep submicron CMOS, as discussed more fully in section 10.3. The advantages of utilizing a composite substrate comprising a monocrystalline semiconductor layer, such as silicon, epitaxially deposited

SiGe HBTs on SOI substrates

167

on a supporting insulating substrate, are well recognized. Major advantages include the substantial reduction of parasitic capacitance between charged active regions and the substrate, and the effective elimination of leakage currents flowing between adjacent active devices. Modern communication devices also present greater difficulties in high level integration because they require digital computing capability (logic and memory) along with analogue and RF circuitry. The need to reduce power consumption in battery powered wireless communication systems is a need which has not previously been met. While bipolar transistors fabricated on SOI substrates have been shown to offer lower parasitic capacitance [21], they do have a greater susceptibility to self-heating [4, 5]. Investigations on the impact of self-heating on transistor performance and effect of introduction of thermal vias to reduce temperature rise have been performed by Armstrong and Gamble [22]. Lattice heating in the SiGe HBT has been simulated by coupling the solution of the heat flow equation along with the semiconductor equations: C

∂TL = ∇ (κ∇TL ) + H ∂t

(5.1)

where TL represents the lattice temperature, C the heat capacitance per unit volume and κ the thermal conductivity. The Joule heating term H, which provides the coupling between the heat flow equation and the semiconductor equations, is given by H=

Jp2 Jn2 + qµn n qµp p

(5.2)

where Jn,p and µn,p represent current density and carrier mobility of electrons and holes, respectively. The temperature dependence of κ in the semiconductor is modelled by [23] κ=

1 a + bTL + cTL2

(5.3)

where for silicon and polysilicon, a = 0.03, b = 1.56×10−3 , c = 1.65×10−6 , while for silicon dioxide κ = 0.014. The SiGe HBT transistor considered for simulation (see figure 5.18) is based on SiGe technology developed at Southampton University [24]. The novel feature of this technology is selective growth of a silicon collector in an anisotropically etched oxide window, followed by non-selective growth of a SiGe base and low-doped SiGe emitter in the same growth sequence. A key aspect of the technology is the very low junction capacitance at both emitter–base and base–collector junctions. In addition, the fabrication of the transistor in a bonded substrate offers the possibility of including a buried silicide layer to reduce collector resistance. Simulations indicate

168

Simulation of SiGe HBTs

Figure 5.18. Structure of a SiGe HBT on SOI used for simulation.

Figure 5.19. SiGe HBT doping profile used for simulation.

SiGe HBTs on SOI substrates

169

Figure 5.20. A schematic diagram of a SiGe HBT showing different regions. (After Armstrong G A and Gamble H S 1999 Silicon-on-Insulator Technology and Devices IX, Electrochemical Society Proceedings Series vol 99-3, ed P L Hemment (Pennington, NJ: Electrochemical Society) pp 249–54.)

that the predicted performance of an optimized Si0.9 Ge0.1 heterojunction transistor produced in SOI material utilizing minimum lithography is fmax in excess of 100 GHz and ECL gate delay of less than 10 ps. To achieve this level of performance, a minimal feature size with an emitter polysilicon width of 0.25 µm and 0.125 µm mask alignment is required. A typical base doping considered for simulation is shown in figure 5.19. Figure 5.20 illustrates a simplified structure, representative of the oxide isolated technology, with extended base and collector regions. The buried collector is shown to be thinner than would normally be used, to emphasize any potential heating effect due to collector resistance. Electrical boundary conditions are applied at the emitter, base and collector contacts in the normal way. The substrate (not shown below the oxide) is assumed to be held at a fixed ambient temperature. Figure 5.20 also shows the inclusion of a thermal via through the buried oxide. This via, which is created prior to bonding, acts as a heat conduction path. A thermal boundary condition

170

Simulation of SiGe HBTs

Figure 5.21. Simulated Gummel plot with and without inclusion of the heat equation. (After Armstrong G A and Gamble H S 1999 Silicon-on-Insulator Technology and Devices IX, Electrochemical Society Proceedings Series vol 99-3, ed P L Hemment (Pennington, NJ: Electrochemical Society) pp 249–54.)

is defined at all three electrical contacts such that −κ

∂TL 1 (TL − Text ) = ∂n Rth

(5.4)

where Rth represents thermal resistance in K mW−1 . Figure 5.21 shows the Gummel plots, with and without the inclusion of the heat equation for the lattice heating modelling. Due to poor thermal conductivity in the buried oxide, the junction temperature rises, leading to a deviation from linearity. In the lower curve, heating has caused a 25 K rise in temperature above the ambient. The consequent increase in collector current is consistent with that value of collector current, which would occur for the same increase in ambient temperature. A comparison between the maximum temperature rise in a transistor on an SOI substrate, with two different thicknesses of buried oxide, and the maximum temperature rise on a silicon substrate is shown in figure 5.22. For different thermal boundary conditions (Rth ranging from 2–20 K mW−1 ), the sensitivity of the maximum temperature rise to thermal resistance, for a buried oxide of 0.4 µm, and a collector voltage of 3 V, is shown in figure 5.23. The impact of the thermal via in providing a heat conduction path through the buried oxide is shown in figure 5.24.

SiGe HBTs on SOI substrates

171

Figure 5.22. Comparison of heating effect between SOI and silicon substrates. (After Armstrong G A and Gamble H S 1999 Silicon-on-Insulator Technology and Devices IX, Electrochemical Society Proceedings Series vol 99-3, ed P L Hemment (Pennington, NJ: Electrochemical Society) pp 249–54.)

Figure 5.23. Dependence of maximum temperature rise on thermal resistance in a SiGe HBT fabricated in a bonded SOI substrate. (After Armstrong G A and Gamble H S 1999 Silicon-on-Insulator Technology and Devices IX, Electrochemical Society Proceedings Series vol 99-3, ed P L Hemment (Pennington, NJ: Electrochemical Society) pp 249–54.)

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Simulation of SiGe HBTs

Figure 5.24. Contour plots of temperature in a SiGe HBT. (After Armstrong G A and Gamble H S 1999 Silicon-on-Insulator Technology and Devices IX, Electrochemical Society Proceedings Series vol 99-3, ed P L Hemment (Pennington, NJ: Electrochemical Society) pp 249–54.)

The peak temperature occurs, as expected, within the active area of the transistor. However, it is clear that the thermal via is effective in providing a heat conduction path to the silicon substrate. Although an attempt has been made to predict the thermal behaviour of HBT transistors fabricated on SOI substrates, absolute accuracy is difficult to achieve because of the error in estimating the degree of external heat loss, which has been approximated using a thermal resistance boundary condition at the electrical contacts. The variation in temperature within the transistor and the dependence of the maximum temperature rise on thermal resistance have been demonstrated. The reduction in temperature, which occurs if a thermal via is included, depends on its alignment relative to the active area. 5.5.

LOW-TEMPERATURE SIMULATION

The outstanding performance advantages of a SiGe HBT for lowtemperature operation have been demonstrated experimentally in a stateof-the-art silicon bipolar process [7–10]. However, the design and optimization issues associated with the low-temperature operation of SiGe

Low-temperature simulation

173

HBTs remain unclear. Because of its bandgap-engineered base, a SiGe HBT is particularly suitable for operation at cryogenic temperature, where the exponential gain enhancement factor becomes very large. In addition, the built-in drift field in the base is more effective at low temperature, compensating for the degradation in base diffusivity, resulting in improvement in the cut-off frequency. It has been demonstrated [7] that present SiGe technology is capable of providing transistors with higher current gain at 77 K than at room temperature, and unloaded ECL circuits which are as fast at 77 K as they are at room temperature. The key design issues for the low operation of SiGe HBTs may be identified as follows [25]: • • • •

minimization of carrier freeze-out in the base; control of increased parasitic emitter–base tunnelling current at low temperature; design of collector profile to leverage the increase in Kirk knee current density with cooling; and effect of Ge grading on current gain and cut-off frequency.

Low-temperature semiconductor device simulation is a difficult task because parameters, often assumed constant in conventional simulators, may actually be complex functions of temperature. Phenomena unique to low-temperature operation, such as carrier freeze-out, are typically not accounted for in simulators designed for room temperature use. In addition, the system of equations to be solved for low temperature is much more illconditioned numerically than at room temperature, due to terms having stronger exponential temperature dependency. For these reasons, available simulation programs can have difficulty in converging to a solution at 77 K [26, 27]. 5.5.1.

Low-temperature SiGe HBTs

Patton et al [28] studied the low-temperature operation of a SiGe HBT fabricated in a poly-emitter bipolar process. The devices showed improved low-temperature behaviour with extremely high current gains of 1600 at 77 K for devices having 7.5 kΩ/square base resistivity. Crabbe et al [6] investigated the low-temperature behaviour of Si BJTs and SiGe HBTs fabricated and optimized for room temperature operation. The authors demonstrated that introducing a spacer layer in the emitter–base junction reduced the low level parasitic emitter–base tunnelling (leakage current) at low temperature, but gave rise to carrier freeze-out and increase of base resistance at 77 K. The respective current gains were 20–40 for an Si BJT, and 100–140 for a SiGe HBT for the temperature range from 77–300 K. The graded Ge profile in the base improved both the low-temperature current gain and base transit time, resulting in a peak cut-off frequency of 94 GHz at 85 K, compared to 75 GHz at 298 K.

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Simulation of SiGe HBTs

A much improved low-temperature SiGe HBT [29], specifically designed for low-temperature operation, was fabricated using self-aligned epi-base technology [30]. Lightly-doped spacers were used at both the junctions to reduce the electric field. The base width was approximately 59 nm and the peak concentration of the graded Ge profile was 9%. For a high-power design (about 10 mW), the ECL gate delay at 84 K was 28.1 ps, roughly the same as at 310 K, yet a factor of two better than the best value obtained at that time with a low-temperature Si BJT. Low power ECL circuits showed a power delay product of 112 fJ at 84 K. The measured gate delays were in reasonable agreement with the theoretical predictions [31]. At that time, these results represented a significant advance in performance of silicon-based bipolar technology at 77 K. During the 1990s, the research group at IBM [7, 9, 10] reported progressive further improvements in the low-temperature performance of SiGe HBTs. A low thermal budget allowed a sharp transition from a lowdoped emitter to a heavily-doped base, making the base immune to carrier freeze-out at 77 K. At 84 K, transistors showed a current gain of 500, fT of 61 GHz and ECL gate delay of 21.9 ps, 3.5 ps faster than at room temperature. Typical parameters and performance of the transistors at 310 and 84 K for the epitaxial emitter-cap (no spacer) design and an i–p–i (with spacers) design, are given in table 5.2. The effect of introducing lightly-doped spacer layers at both the emitter–base and base–collector junctions was studied in detail [9]. The

Table 5.2. Typical SiGe HBT parameters at 310 and 84 K at the wafer level. (After Cressler et al 1994 IEEE Electron Device Lett. 15 472–4.) Temperature SiGe profile βmax β at 1.0 mA Peak gm (mS) Rbi (kΩ/square) Re (Ω) Ieb (nA) BVceo (V) BVcbo (V) Cbe (fF µm−2 ) Cbc (fF µm−2 ) Peak fT (GHz) Peak fmax (GHz) ECL delay (ps)

310 K

84 K

Emitter-cap design 102 94 62 7.7 14.3 8.44 × 104 3.1 10.8 5.47 0.46 43 40 25.4

498 99 113 11.0 11.0 1.91 × 103 2.1 9.6 5.13 0.40 61 50 21.9

310 K

84 K

i–p–i design 105 96 74 8.2 82 2.89 3.2 10.8 6.30 1.04 53 37 26.0

82 34 83 15.9 15.9 1.11 3.2 9.5 5.90 0.93 59 48 30.4

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spacer layer reduced the low level parasitic base leakage but gave rise to carrier freeze-out and an increase of base resistance at 77 K. However, it was shown that a thin abrupt base profile attainable with epitaxial processing is particularly useful for low-temperature operation since the resultant profile is less sensitive to base freeze-out than ion-implanted profiles. The authors also fabricated homojunction Si BJTs and showed that properly designed homojunction transistors also have sufficient current gain and switching speed at 77 K for many digital applications. In several applications, however, the flexibility offered by using SiGe for base layer yields great benefits. Gruhle et al [12] have reported a high-performance SiGe HBT, fabricated using MBE, having a base doping of 2 × 1019 cm−3 , largely exceeding the emitter impurity level and a base sheet resistance of about 1 kΩ/square. The device exhibited an Early voltage of 500 V, a maximum room temperature current gain of 550 rising to 13 000 at 77 K. Devices built on buried-layer substrates exhibited an fmax of 40 GHz and an fT of 42 GHz. Sturm et al [32] also fabricated high-quality SiGe HBTs using rapid thermal chemical vapour deposition. Both graded-base and uniform Ge profiles in the base were considered. In a transistor with 20% uniform Ge concentration in the base, currents gain of about 2000 at room temperature and 11 000 at 133 K were observed. The performance of SiGe HBTs at liquid helium temperature has been reported by Joseph et al [8]. The current gain of a self-aligned, UHVCVD-grown SiGe HBT showed an increase in current gain from 110 at 300 K to 1045 at 5.85 K, although parasitic base current leakage limits the useful operating current to above about 1.0 µA at 5.84 K. A very high base doping (peak at 8 × 1018 cm−3 ) was used to suppress the base freeze-out at 4.48 K and resulted in a base sheet resistance of 18.3 kΩ/square. 5.5.2.

Low-temperature simulation using ATLAS

In order to understand the impact of the Ge profile and base doping in the design of a low-temperature SiGe HBT, simulations were performed using ATLAS 2D device simulator on two separate base doping profiles, and two different Ge profile shapes: (i) a box Ge profile (uniform Ge content, x = 0.20, not shown) (ii) a graded Ge profile (see figure 5.25). Figure 5.26 shows Gummel plots at 300 and 100 K, respectively, for constant Ge concentration. The simulated collector current characteristic is ideal over more than ten decades of current. As the temperature is lowered, the intrinsic carrier concentration decreases exponentially, and for an observable current to flow at low temperature, the emitter–base voltage

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Simulation of SiGe HBTs

Figure 5.25. Doping profile and Ge profile (graded case) in a SiGe HBT.

must be increased substantially, as may be seen from figure 5.26. As the dc current gain depends exponentially on the bandgap narrowing present at the emitter edge of the neutral base [33], the box Ge profile (x = 0.2) produces a larger enhancement in β, in figure 5.27, than the graded profile in figure 5.25. In the former diagram, a peak dc current gain as high as 11 000 is predicted at 100 K, compared to the more moderate enhancement for the graded Ge. In the latter case, the predicted current gain at 150 K of 900 is more than adequate for successful circuit operation at such a low temperature. A contributory factor to the high current gain at low temperature is the low level of bandgap narrowing in the relatively lightlydoped 5 × 1018 cm−3 single-crystal emitter. Richey et al [34] have shown close agreement with measurements for low-temperature SiGe HBT simulations, using a calibrated doping profile based on SIMS data. The authors have used the 1D simulator SCORPIO to examine the effects of Ge profile shape and base profile scaling on temperature. Some of these results are presented below. It has been

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177

Figure 5.26. Gummel plots of a SiGe HBT (flat base) at 300 and 100 K.

shown in chapter 4 that a triangular Ge profile in the base produces more enhancement in cut-off frequency and βVA product than a box Ge profile. The bandgap grading associated with the triangular Ge profile induces a drift field that helps accelerate electrons across the base, decreasing the base transit time. Figures 5.28–5.30 show dependence of cut-off frequency fT , relative improvement in fmax and βVA product on temperature, for box and graded Ge profiles, at different dc bias points. Three separate sets of base doping profile are used and, for each set, two Ge profiles—a box profile and a linearly graded profile—are considered. Each Ge profile has the same stability point as defined by Matthews and Blakeslee [35, 36], i.e. the integrated Ge concentration is held constant. Three stability points are referenced. Stability point 1 refers to a state-of-the-art device, with an effective Ge thickness of 120 nm and a base width of 90 nm. For the second stability point, the base profile has been scaled by one half while base

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Simulation of SiGe HBTs

Figure 5.27. The dc current gain of a flat base SiGe HBT at different temperatures. For comparison, dc current gain at 150 K for a graded base transistor is shown.

Figure 5.28. Cut-off frequency comparisons over temperature. Richey D M et al 1997 IEEE Trans. Electron Devices 44 431–40.)

(After

Low-temperature simulation

179

Figure 5.29. Enhancements in maximum oscillation frequency. Richey D M et al 1997 IEEE Trans. Electron Devices 44 431–40.)

(After

Figure 5.30. Current gain–Early voltage product enhancements. Richey D M et al 1997 IEEE Trans. Electron Devices 44 431–40.)

(After

180

Simulation of SiGe HBTs

doping is increased to maintain the same pinched base resistance. Stability point 3 is identical to the previous case, except that the Ge content is doubled. For all three scaled profiles, both the collector profile and emitter depth are unaltered. For all parameters, the enhancement factor increases significantly as the temperature is reduced. The relative improvement for the graded Ge profile at low temperature is due to the greater effectiveness of the drift field in compensating for degradation in diffusivity. The simulation suggests that for low-temperature operation, a box Ge profile may be used for maximizing dc current gain and fT , but this is a more sensitive function of temperature than the triangular profile. In conclusion, the box Ge profile produces the greatest enhancement in β, fT and fmax over temperature, while the triangular Ge profile produces the greatest enhancement in βVA product. 5.6.

I2 L CIRCUITS USING SIGE HBTS

High-performance bipolar logic circuits are usually realized using emitter coupled logic (ECL) which has a relatively low packing density and high power dissipation. The gate delay of I2 L circuits is primarily determined by stored charge in parasitic diodes associated with the extrinsic base regions of the I2 L gate [15]. SiGe technology offers the prospect of using bandgap engineering to minimize the stored charge in the parasitic diodes associated with the I2 L gate. Hence, the use of a heterojunction can add high speed to the other well-known advantages of I2 L technology, namely high packing density, low voltage and low power dissipation. Experimental results on SiGe integrated injection logic circuits (surface-fed and substratefed variants) have been reported [16]. Figure 5.31(a) shows the cross section of an I2 L gate and figure 5.31(b) a circuit diagram. The cross section shows the merged structure of the I2 L gate, with the SiGe layer used both as the base of the npn transistor and the collector of the pnp transistor. The npn switching transistor operates

Figure 5.31. Schematic cross-section (a) and circuit diagram (b) of an I2 L. (After Wainwright S P et al 1996 Proc. ESSDERC pp 649–52.)

I2 L circuits using SiGe HBTs

181

in the inverse mode, which allows multiple collectors to be produced using n+ -polySi contacts to the top n-type silicon layer. A polysilicon contact is also used to connect to the base of the pnp injector transistor. The emitter (injector) of the pnp transistor is formed in the top 300 nm n-type silicon layer using a BF2 implant through a 50 nm screen oxide. This SiGe I2 L technology therefore uses a vertical pnp transistor in contrast to the lateral pnp transistor used in conventional silicon I2 L technologies. A Gummel plot of a 3 µm npn switching transistor, operated in upward mode in an I2 L gate with three collectors, gave a maximum current gain of 14. The collector current characteristic was ideal over several decades of current, while the ideality factor of the base current was 1.28. The measured output characteristic is shown in figure 5.32 and indicates a breakdown voltage BVceo of about 2.9 V. A low gain of 1.4 for the pnp transistor was not deemed to be important for the operation of the I2 L gate, provided that the ratio of saturation currents for the pnp and the npn transistors was much greater than unity. Figure 5.33 compares the measured and modelled [37] switching time as a function of injector current per gate. The measured and modelled values agree quite closely, with the measured values being about 40% faster. For optimization of SiGe integrated injection logic (I2 L) circuits, a quasi two-dimensional stored charge model has been developed [16]. It has

Figure 5.32. Output characteristics (upward mode) of the npn SiGe HBT. (After Wainwright S P et al 1996 Proc. ESSDERC pp 649–52.)

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Simulation of SiGe HBTs

Figure 5.33. Comparison of measured and modelled I2 L gate delay. (After Wainwright S P et al 1996 Proc. ESSDERC pp 649–52.)

been shown that at low injector currents, the use of SiGe offers only a marginal benefit, since the switching speed is dominated by depletion region charge. However, at high injection currents, where the switching speed is dominated by stored minority carrier charge, the use of SiGe in I2 L technology has been shown to have important benefits. The inclusion of 16% Ge in the substrate-fed I2 L gate leads to a decrease in the dominant stored charge by a factor of more than ten, which suggests that gate delays well below 100 ps should be achievable, even at a geometry of 3 µm. The model has also been applied to predictions of the performance of a self-aligned structure, specifically optimized for SiGe I2 L. For a Ge concentration of 16% in the base, a maximum delay of 34 ps was predicted using 1.4 µm design rules. 5.7.

NOISE PERFORMANCE

Different types of noise mechanisms are found to be present in semiconductors [38]. Among them the low-frequency noise, typically observed to exhibit a dependence on frequency, is very important for analogue and mixed-signal applications. Low-frequency noise is known to degrade the spectral purity of nonlinear radio frequency (RF) and

Noise performance

183

microwave circuits, such as oscillators and mixers, where the low-frequency, baseband noise generates noise sidebands around the RF or microwave carrier signal [39]. Low-frequency noise in UHVCVD-grown Si and SiGe bipolar transistors has been studied by Vempati et al [40]. The authors have made a comprehensive study by comparing different technologies and have demonstrated that the SiGe devices have excellent noise properties compared to AlGaAs/GaAs HBTs and conventional Si bipolar junction transistors. Low-frequency noise has been characterized as a function of bias, geometry and temperature [41, 42]. The transistors used were fully integrated, self-aligned devices, with shallow and deep trench isolation, silicided extrinsic base and contacts, two levels of metallization and a conventional poly-emitter contact. Two different bias configurations were used to distinguish the various noise sources contributing to noise in the Si and SiGe bipolar transistors. The devices were biased in low injection (Ib ∼ 2.25 µA) in order to eliminate any second-order parasitic resistance effects and spurious noise due to weak impact ionization. The collector current was also limited to several milliamps, so that the shot noise due to the collector current was negligible compared to the base current shot noise. Common-emitter configuration with high input impedance was used for measuring the base noise. In order to determine the collector noise and the contributions, if any, of the parasitic series resistances, the devices were biased in the common-collector configuration. Typical curves of the equivalent input-referred base current noise spectra for Si and SiGe devices are shown in figure 5.34. At low frequencies, the noise rises over the shot noise and thermal noise background and exhibits an expected spectrum for frequencies below 1 kHz. Within the scatter of data (approximately 50 devices for both Si and SiGe combined were measured) the slope of the spectrum varies as 1/f . The roll-off of the spectra above 10 kHz is due to the Miller capacitance associated with the device and packaging. As temperature excursions are important in analogue applications, noise measurements were made over the range of −55 ◦ C to 85 ◦ C. Figure 5.35 shows the temperature dependence of the noise spectra of Si and SiGe transistors at a fixed base current of 2.25 µA. It is observed that the noise spectral density exhibits a clear 1/f behaviour without any anomalous behaviour in the slope across this temperature range. The noise spectra for Si and SiGe devices are similar, and have no significant temperature dependence. The authors concluded that the combination of an inverse of area dependence on geometry and nearquadratic dependence on base current suggests that the noise sources are homogeneously distributed over the entire emitter area and not restricted only to the emitter periphery. Comparisons with different technologies

184

Simulation of SiGe HBTs

Figure 5.34. Equivalent input-referred base noise current spectral density at a base current of 2.25 µA for multi-stripe Si and SiGe transistors with an emitter area 3 × 0.5 µm and comparable doping profiles. The inferred 1/f to shot noise corner frequencies are 480 Hz and 373 Hz for Si and SiGe transistors, respectively. (After Vempati L S et al 1996 IEEE J. Solid-State Circuits 31 1458–67.)

Figure 5.35. Noise spectral density at two different temperature points (358 and 218 K) of Si and SiGe devices of an emitter area of 3 × 0.5 µm. (After Vempati L S et al 1996 IEEE J. Solid-State Circuits 31 1458–67.)

Noise performance

185

demonstrate that the Ge incorporated in the base does not degrade the noise performance and that SiGe HBTs have better noise performance than AlGaAs/GaAs HBTs and conventional ion-implanted Si BJTs. Even though SiGe HBTs have demonstrated better noise performance over Si BJTs at low frequency, even better high-frequency noise characteristics may be expected if the Ge profile is optimized specifically to address this issue. The SiGe HBT design issues associated with minimization of broadband noise have been considered by Ansley et al [43]. Using the 1D simulator SCORPIO, the effect of the Ge profile in the base on the minimum noise figure at high frequency was theoretically investigated. The analysis was based on an equivalent circuit noise model originally formulated by Hawkins [44], as shown in figure 5.36. The model accounts for thermal noise in the source (vs ), base resistance (vb ), shot noise in the emitter (ve ) and collector partition noise (icp ). The resulting expression for noise factor may be approximated with sufficient accuracy by    Rb Re (1 − (2πf )Cje Xs )2  2 F 1+ + + (2πf )Cje Rs Rs 2 Rs
 
1 + (2πf )2 τb2 Rs Xs2 + (5.5) −1 + α0 2Re 2Re Rs where Rs is the source resistance, Xs is the source reactance, Re is the dynamic emitter resistance (thermal voltage divided by emitter current) and Cje is the emitter–base depletion capacitance, α0 is the common base dc current gain and f is the frequency at which the noise factor is evaluated. This formulation helps in determining the relative contribution of each of the terms which control the noise factor. As a guide, the presence of Ge

Figure 5.36. Equivalent circuit schematic of Hawkin’s noise model for bipolar transistors. (After Hawkins R J 1977 Solid-State Electron. 20 191–6.)

186

Simulation of SiGe HBTs

reduces the noise factor by decreasing τb , decreasing base resistance Rb and allowing the possibility of increased current gain. The minimum noise figure, NFmin is given by 10 log(F) when Rs is set to the optimum source resistance Ropt which may be approximated as  Ropt ≈

2Rb Re + a




Re2 2 − Xopt 2

 (5.6)

and the optimum source reactance Xopt is given by Xopt ≈ where a≈

(2πf )2 Cje Re2 a 2

(5.7) 2

((2πf )τje ) 1 ((2πf )τb ) + . + β α0 α0

(5.8)

When considering the Ge profile, the best noise performance is achieved with the greatest amount of Ge in the neutral base region, subject to the maximum acceptable β and the strained layer stability constraints. In what was essentially a theoretical study, a novel optimized Ge profile to achieve minimum noise figure was developed, as shown in figure 5.37, which compares the new profile with a traditional trapezoidal profile of the same average Ge content. Simulations using this profile at 10 GHz indicated an improvement of almost 1 dB in the minimum noise figure over an equivalent Si BJT control, and 0.4 dB over the equivalent SiGe HBT with the traditional profile. Base doping has a direct impact on β, intrinsic base resistance Rbi and fT , with all values decreasing as doping increases. The decrease in β and fT (with increases in both base and emitter transit time) would give the impression that NFmin will increase. However, the decrease in the base resistance suggests there may be a decrease in NFmin . Figure 5.38 shows the effect of increasing base doping on the major components of noise factor, as a function of collector current, for a 90 nm base HBT with the calibrated Ge profile of figure 5.37. An additional extrinsic base sheet resistance of 500 ohms/square has been included in the calculation. It is apparent that an increase in base doping increases NFmin because β decreases and τb increases. Even though an increase in doping reduces Rb , Ropt also decreases which partially offsets the impact of reduction in base thermal noise. 5.8.

RADIATION EFFECTS ON SIGE HBTS

In the following, we describe briefly the effects of proton and gamma radiation on SiGe HBTs fabricated in IBM SiGe BiCMOS technology.

Radiation effects on SiGe HBTs

187

Figure 5.37. Ge profile which allows optimization for NFmin compared to the conventional graded Ge profile. Emitter and base carrier concentrations are shown for reference from polySi interface in emitter to base–collector junction (at right edge). (After Ansley W E et al 1998 IEEE Trans. Microw. Theory Tech. 46 653–60.)

Figure 5.38. Effect of base doping level on the noise factor sources for the scaled base profile using a base link sheet resistance of 500 ohms/square. (After Ansley W E et al 1998 IEEE Trans. Microw. Theory Tech. 46 653–60.)

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Simulation of SiGe HBTs

Dose-rate effects and proton energy effects have been studied in detail for this technology, mainly by Cressler and his group [45–47]. Characteristics of proton and gamma irradiated SiGe HBTs and gated lateral pnp transistors (GLPNPs) have been reported [48]. MOS devices respond to ionizing radiation in several ways, depending on whether the damage occurs in silicon or in the oxide. In the oxide, charge-generation in the gate/oxide interface or the oxide/silicon interface causes changes in the threshold voltage (VT ), transconductance (gm ), and the leakage current. Two kinds of charges are observed: oxide trapped charge and interface trapped charge, each having different effects on device parameters. The major effects of radiation-induced interface states on MOS devices are lowering of transconductance and distortion of I–V characteristics. The generation of electron–hole pairs after a radiation burst is not a long-lived phenomenon because the electrons tunnel into the bulk of the device and the trapped hole charge can lead to significant device degradation. For most bipolar devices, the effects of radiation and subsequent performance degradation due to surface states are not as catastrophic as for MOSFETs. Bipolar transistors are, in general, more radiation tolerant than CMOS as they depend on junctions for operation, while MOSFETs depend on surface effects and the interfaces. Also, bipolar transistors are doped up to three orders of magnitude higher than MOSFETs. When irradiated, degradation of current gain and an increase in leakage current are found to occur in the case of bipolar devices. Gain degradation occurs mainly due to the atomic displacement in the bulk of the device. The displacement results in an increase in the number of recombination centres, which reduces the minority-carrier lifetime, and therefore an increase in the base current takes place. The other cause of gain degradation is due to the ionization of the oxide passivation layer, mainly in the emitter–base junction region where charge trapping and the generation of new interface traps occur. The trapped surface charge and the interface states cause an increase in minority-carrier surface recombination velocity, which reduces the gain. Another important effect in bipolar transistors is the increase in the junction leakage currents resulting from ionization in the surface oxide, mainly the region over the base–collector junction. This increase in base– collector leakage current (typically ∼1 nA) is usually due to charge build-up in the oxide layer over the junction producing a surface channel which conducts strongly. Figure 5.39 shows a schematic device cross section of a SiGe HBT and sources of degradation. The SiGe HBT has been successfully integrated with conventional Si CMOS technology to realize a SiGe BiCMOS technology. This technology is more fully discussed in chapter 10.

Radiation effects on SiGe HBTs

189

Figure 5.39. Schematic cross section of a self-aligned UHVCVD SiGe HBT. Sources of degradation are shown in the structure. (After Banerjee G 1999 Master’s Thesis Auburn University.)

5.8.1.

Low dose-rate effects

Low dose-rate (LDR) effects have been investigated in the state-of-the-art SiGe HBTs (see figure 5.39) which were fabricated using a self-aligned, planar structure with deep and shallow trench isolation and a conventional poly-emitter contact. These SiGe HBTs have 70 GHz fmax frequency response and have been fully integrated into a 0.35 µm SiGe BiCMOS technology for system-on-a-chip applications [49]. The LDR effects on these vertical SiGe HBTs were contrasted with high dose-rate (HDR) data, as well as data from gated lateral pnp transistors from this SiGe BiCMOS process, in order to shed light on the damage mechanisms. In contrast to reports of strongly enhanced LDR degradation in conventional Si bipolar transistors, LDR effects in the SiGe HBTs were found to be nearly non-existent [50]. Figure 5.40 shows the dependence of dc current gain on the energy of protons. A peak β of about 105 is observed which degrades to 100 for 44 MeV and 95 for 196 MeV. Clearly, the β degradation is much larger for the higher energy. It has been observed that an increase in the base current occurs when collector current is more or less independent of radiation. However, the degradation in current gain is not as large in the high current region of the transistor, where it will be biased for most of the high-frequency and high-power RF applications. The LDR effects have been found to be very technologydependent.

190

Simulation of SiGe HBTs

Figure 5.40. Current gain degradation as a function of energy. Banerjee G 1999 Master’s Thesis Auburn University.)

5.8.2.

(After

Simulation of radiation hardness

The effects of proton radiation in a gate-assisted lateral pnp (GLPNP) in an advanced SiGe BiCMOS technology have been studied by Niu et al [48]. The GLPNP is essentially a p-MOSFET whose source and drain serve as the emitter and collector of the lateral bipolar transistor. These transistors avoid the current gain limitation by combining both MOSFET and bipolar operational modes, and thus are commonly used in BiCMOS circuits [51]. Radiation-induced surface and bulk traps were electrically probed using a combination of dc measurements and 2D simulation. Figure 5.41 shows the schematic top view and cross section of a GLPNP, along with the SiGe HBT in the BiCMOS process studied. To understand the physics underlying radiation degradation, extensive 2D simulations using MEDICI [52] were performed by the authors, by placing positive charges in the oxide and introducing a thin surface layer of traps. The simulations show that the radiation-induced threshold voltage increases and the carrier lifetime at the surface decreases. Different combinations of trap density and spatial distributions of traps were used, and only those with higher surface trap densities can reproduce the experimentally observed data. Figure 5.42 shows the evolution of the simulated electron and hole densities versus depth with VGB change at Vbe = 0.45 V.

Radiation effects on SiGe HBTs

191

Figure 5.41. Device cross section for the gated lateral pnp transistor and SiGe HBT. (After Niu G et al 1998 IEEE Trans. Nucl. Sci. 45 2361–5.)

Figure 5.42. Simulated electron (solid curve) and hole (dashed curve) densities versus depth with VGB (gate-to-base bias) change at Vbe = 0.45 V. (After Niu G et al 1998 IEEE Trans. Nucl. Sci. 45 2361–5.

192 5.9.

Simulation of SiGe HBTs SUMMARY

In this chapter, further examples of device simulation employing SiGe HBT technology have been considered. Attention has been given to simulation of various advanced technologies leading to high cut-off frequency and/or low transit time. Good agreement between simulation and measurement provides confidence in the use of device simulation for future development. Simulation of the low-temperature operation of a SiGe HBT has been shown to be applicable for a wide range of applications in low-temperature electronics. Other more specialist applications of SiGe technology in I2 L circuits and radiation hard environment have been considered. BIBLIOGRAPHY [1] Meister T F, Schafer H, Franosch M, Molzer W, Aufinger K, Scheler U, Walz C, Stolz M, Boguth S and Bock J 1995 SiGe base bipolar technology with 74 GHz fmax and 11 ps gate delay IEEE IEDM Tech. Dig. pp 739–42 [2] Kondo M, Oda K, Ohue E, Shimamoto H, Tanabe M, Onai T and Washio K 1998 Ultra-low-power and high-speed SiGe base bipolar transistors for wireless telecommunication systems IEEE Trans. Electron Devices 45 1287–94 [3] Armstrong G A and French W D 1995 A model for dependence of maximum oscillation frequency on collector to substrate capacitance in bipolar transistors Solid-State Electron. 38 1505–10 [4] Jomaah J, Ghibaudo G and Balestra F 1995 Analysis and modelling of self-heating in thin film SOI MOSFETS as a function of temperature Solid-State Electron. 38 615–8 [5] Dallmann D and Shenai K 1995 Scaling constraints imposed by self-heating in SOI MOSFETs IEEE Trans. Electron Devices 42 489–96 [6] Crabbe E F, Patton G L, Stork J M C, Comfort J H, Meyerson B S and Sun J Y-C 1990 Low-temperature operation of Si and SiGe bipolar transistors IEEE IEDM Tech. Dig. pp 17–20 [7] Cressler J D, Crabbe E F, Comfort J H, Sun J Y-C and Stork J M C 1994 An epitaxial emitter-cap SiGe-base bipolar technology optimized for liquidnitrogen temperature operation IEEE Electron Device Lett. 15 472–4 [8] Joseph A J, Cressler J D and Richey D M 1995 Operation of SiGe heterojunction bipolar transistors in the liquid-helium temperature regime IEEE Electron Device Lett. 16 268–70 [9] Cressler J D, Comfort J H, Crabbe E F, Patton G L, Stork J M C, Sun J Y-C and Meyerson B S 1993 On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications— part I: Transistor dc design considerations IEEE Trans. Electron Devices 40 525–41 [10] Cressler J D, Comfort J H, Crabbe E F, Patton G L, Stork J M C, Sun J Y-C and Meyerson B S 1993 On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications—part II: circuit performance issues IEEE Trans. Electron Devices 40 542–56

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[11] Joseph A J, Cressler J D, Richey D M, Jaeger R C and Harame D L 1997 neutral base recombination and its influence on the temperature dependence of Early voltage and current gain–Early voltage product in UHV/CVD SiGe heterojunction bipolar transistors IEEE Trans. Electron Devices 44 404–13 [12] Gruhle A, Kibbel H, Konig U, Erben U and Kasper E 1992 MBE-grown Si/SiGe HBTs with high β, fT and fmax IEEE Electron Device Lett. 13 206–8 [13] Mazhari B and Morkoc H 1995 Intrinsic gate delay of Si/SiGe integrated injection logic circuits Solid-State Electron. 38 189–96 [14] Karlsteen M and Willander M 1995 Improved switch time of I2 L at low power consumption by using an SiGe heterojunction bipolar transistor Solid-State Electron. 38 1401–7 [15] Berger H H and Helwig K 1979 An investigation of the intrinsic delay (speed limit) in MTL/I2 L IEEE J. Solid-State Circuits 14 327–37 [16] Wainwright S P, Hall S, Ashburn P and Lamb A C 1998 Analysis of Si:Ge heterojunction integrated injection logic (I2 L) structures using a stored charge model IEEE Trans. Electron Devices 45 2437–47 [17] Tang Y T 2000 Advanced characteristics and modelling of SiGe HBTs PhD Thesis University of Southampton [18] Hamel J S and Tang Y T 2000 Numerical simulation and comparison of vertical and lateral SiGe HBTs for RF/microwave applications Proc. ESSDERC 2000 (Cork, Ireland, 12–14 September 2000) [19] Apanovich Y, Lyumkis E, Polsky B, Shur A and Blakey P 1994 Steadystate and transient analysis of submicron devices using energy balance and simplified hydrodynamic models IEEE Trans. Comput.-Aided Des. 13 702–7 [20] Oda K, Ohue E, Tanabe M, Shimamoto H, Onai T and Washio K 1997 130 GHz fT SiGe HBT technology IEEE IEDM Tech. Dig. pp 791–4 [21] Brodsky J S, Fox R M and Zweidinger D T 1999 A physics-based dynamic thermal impedance model for vertical bipolar transistors on SOI substrates IEEE Trans. Electron Devices 46 2333–9 [22] Armstrong G A and Gamble H S 1999 Simulation of self-heating effects in heterojunction bipolar transistors fabricated in wafer bonded SOI substrates Silicon-on-Insulator Technology and Devices IX, Electrochemical Society Proceedings Series vol 99-3, ed P L Hemment (Pennington, NJ: Electrochemical Society) pp 249–54 [23] Selberherr S 1984 Analysis and Simulation of Semiconductor Devices (Vienna: Springer-Verlag) [24] Schiz J 1999 The effect of fluorine in low thermal budget polysilicon emitters for SiGe heterojunction bipolar transistors PhD Thesis University of Southampton [25] Maiti C K and Armstrong G A 1998 Ge profile on dc current gain of Si1−x Gex HBTs at low temperature Proc. Int. Conf. on Computers and Devices for Communication (CODEC-98) pp 264–7 [26] Selberherr S 1989 MOS device modelling at 77 K IEEE Trans. Electron Devices 36 1464–74 [27] Chrzanowska-Jeske M and Jaeger R C 1989 BILOW-simulation of low-

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[33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43]

Simulation of SiGe HBTs temperature bipolar device behaviour IEEE Trans. Electron Devices 36 1475–88 Patton G L, Harame B L, Stork J M C, Meyerson B S, Scilla G J and Ganin E 1989 Graded SiGe-base, poly-emitter heterojunction bipolar transistors IEEE Electron Device Lett. 10 534–6 Cressler J D, Comfort J H, Crabbe E F, Patton G L, Lee W, Sun J Y-C, Stork J M C and Meyerson B S 1991 Sub-30 ps ECL circuit operation at liquid-nitrogen temperature using self-aligned epitaxial SiGe-base bipolar transistors IEEE Electron Device Lett. 12 166–8 Comfort J H, Patton G L, Cressler J D, Lee W, Crabbe E F, Meyerson B S, Sun J Y-C, Stork J M C, Lu P-F, Burghartz J N, Warnock J, Scilla G, Toh K-Y, D’Agostino M, Stanis C and Jenkins K 1990 Profile leverage in self-aligned epitaxial Si or SiGe base bipolar technology IEEE IEDM Tech. Dig. pp 21–24 Yuan J S 1992 Modelling Si/Si1−x Gex heterojunction bipolar transistors Solid-State Electron. 35 921–6 Sturm J C, Prinz E J and Magee C W 1991 Graded-base Si/Si1−x Gex /Si heterojunction bipolar transistors grown by rapid thermal chemical vapour deposition with near-ideal electrical characteristics IEEE Electron Device Lett. 12 303–5 Jain S C 1994 Germanium–Silicon Strained Layers and Heterostructures (New York: Academic) Richey D M, Cressler J D and Joseph A J 1997 Scaling issues and Ge profile optimization in advanced UHV/CVD SiGe HBTs IEEE Trans. Electron Devices 44 431–40 Matthews J W and Blakeslee A E 1974 Defects in epitaxial multilayers—I. Misfit dislocations in layers J. Cryst. Growth 27 118–25 Matthews J W and Blakeslee A E 1975 Defects in epitaxial multilayers—II. Dislocation pile-ups, threading dislocations, slip lines and cracks J. Cryst. Growth 29 273–80 Wainwright S P, Hall S and Ashburn P 1996 Analysis of SiGe heterojunction injection logic structures using a stored charge model Proc. ESSDERC’96 pp 649–52 Van der Ziel A 1986 Noise in Solid-State Devices and Circuits (New York: Wiley) Hughes B, Fernandez N G and Gladstone J M 1987 GaAs FETs with a flicker-noise corner below 1 MHz IEEE Trans. Electron Devices 34 733– 74 Vempati L S, Cressler J D, Babcock J A, Jaeger R C and Harame D 1996 Low-frequency noise in UHV/CVD epitaxial Si and SiGe bipolar transistors IEEE J. Solid-State Circuits 31 1458–67 Cressler J D, Vempati L, Babcock J A, Jaeger R C and Harame D L 1996 Low-frequency noise characteristics of UHV/CVD epitaxial Si- and SiGebase bipolar transistors IEEE Electron Device Lett. 17 13–15 Vempati L S, Cressler J D, Babcock J A, Jaeger R C and Harame D 1995 Low-frequency noise in UHV/CVD Si- and SiGe-base bipolar transistors IEEE BCTM Proc. pp 129–32 Ansley W E, Cressler J D and Richey D M 1998 Base-profile optimization for

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minimum noise figure in advanced UHV/CVD SiGe HBTs IEEE Trans. Microw. Theory Tech. 46 653–60 Hawkins R J 1977 Limitations of Nielsen’s and related noise equations applied to microwave bipolar transistors, and a new expression for the frequency and current dependent noise figure Solid-State Electron. 20 191–6 Roldan J M, Niu G, Ansley W E, Cressler J D, Clark S D and Ahlgren D C 1998 An investigation of the spatial location of proton-induced traps in SiGe HBTs IEEE Trans. Nucl. Sci. 45 2424–9 Roldan J M, Ansley W E, Cressler J D, Clark S D and Nguyen-Ngoc D 1997 Neutron radiation tolerance of advanced UHV/CVD SiGe HBT BiCMOS technology IEEE Trans. Nucl. Sci. 44 1965–73 Babcock J A, Cressler J D, Vempati L S, Clark S D, Jaeger R C and Harame D L 1995 Ionizing radiation tolerance of high-performance SiGe HBTs grown by UHV/CVD IEEE Trans. Nucl. Sci. 42 1558–66 Niu G, Banerjee G, Cressler J D, Roldan J M, Clark S D and Ahlgren D C 1998 Electrical probing of surface and bulk traps in proton-irradiated gate-assisted lateral pnp transistors IEEE Trans. Nucl. Sci. 45 2361–5 Subbanna S, Ahlgren D, Harame D and Meyerson B 1999 How SiGe evolved into a manufacturable semiconductor production process IEEE ISSCC Tech. Dig. pp 66–67 Banerjee G 1999 Ionizing radiation effects in silicon–germanium BiCMOS technology Master’s Thesis Auburn University Sunderland D A, Jeng S J, Nguyen-Ngoc D, Martin Jr B, Eld E C, Tewksbury T, Ahlgren D C, Gilbert M M, Malinowski J C, Schonenberg K T, Stein K J, Meyerson B S and Harame D L 1996 Gateassisted lateral pnp active load for analog SiGe-HBT technology IEEE BCTM Proc. pp 23–26 Technology Modelling Associates 1997 MEDICI, 2D Semiconductor Device Simulator, Version 4.0

Chapter 6 STRAINED-SI HETEROSTRUCTURE FETS

In conventional Si technology, the complementary metal–oxide semiconductor dominates the integrated circuit market. Its popularity comes from the simplicity in processing, as well as high input impedance. However, p-channel devices are inferior to n-channel ones in terms of current drive capability and speed performance. This is a consequence of the lower mobility of holes compared to electrons in Si. In order to match the current drive capability of n-channel (n-MOS), p-channel (p-MOS) devices are designed to be about 2–3 times larger than that of n-MOS. This adversely affects the level of integration and device speed. In order to improve the speed of VLSI/ULSI circuits, new materials and device structures are being proposed. The advances in the growth of strained silicon (strained-Si) layers on relaxed-SiGe buffer layers, combined with higher values of both the hole and electron mobilities in strained-Si, have led to increased interest in silicon-based heterojunction field-effect transistors (HFETs) using conventional Si-processing technology. Heteroepitaxy of semiconductor materials has been an active area of research for the last two decades. Interest is driven by the possibility of creating novel electronic and optical devices, as well as integrating existing devices in different material systems, leading to the production of integrated circuits with increased functionality and lower cost. The foundation of heteroepitaxy was laid by two important contributions. The first, by Frank and van der Merwe in 1949 [1], showed theoretically that if a lattice mismatched layer is grown on a thick substrate, the layer will be pseudomorphic, provided that the mismatch is small and thickness of the layer is not large. The second by Shockley [2] suggested the use of semiconductors of different bandgaps for fabrication of heterostructure devices. The lattice mismatch in the SiGe material system is 4.2%, resulting in a very high misfit and threading dislocation density. Most of the research 196

Strained-Si heterostructure FETs

197

Figure 6.1. Band alignments between Si and Si0.70 Ge0.30 on two substrates: (a) Si and (b) Si0.70 Ge0.30 .

has concentrated on devices having strained layers with thicknesses below the critical thickness. Si1−x Gex strained layer heterostructure devices were fabricated on an Si substrate only in the late 1980s. The key features of the growth and electronic properties of the strained-SiGe alloy system and their applications have been described in chapter 2 of this book, and also in more detail in several excellent reviews [3–7]. When a thin film with a larger lattice constant (e.g., Si1−x Gex ) is grown on a substrate with a smaller lattice constant (e.g. silicon), the film maintains the in-plane lattice constant of the substrate and is under a biaxially compressive strain. Figure 6.1 shows the band offset between a strained-Si0.7 Ge0.3 film grown on silicon. This is known as the type I band alignment where virtually all the entire band offset occurs in the valence band (figure 6.1(a)) with minimal band offset in the conduction band. This type of structure, favourable for hole confinement, has been exploited in several novel heterostructure devices, namely buried channel p-MOSFETs, p-MODFETs and HBTs (see, for example, excellent reviews by Paul [8] and Konig and Daembkes [9]). Similarly, a smaller lattice constant silicon epilayer will be under biaxial tension when grown on a larger lattice constant relaxed-Si1−x Gex substrate. Figure 6.1(b) shows the band offset for a strained-Si epilayer grown on a relaxed Si0.70 Ge0.30 . In this case, type II band offset occurs and the structure has several advantages over the more common type I band alignment, as a large band offset is obtained in both the conduction and valence bands, relative to the relaxed-Si1−x Gex layer [10]. This allows both electron and hole confinements, making it useful for both n- and p-type devices for strained-Si/SiGe based CMOS technology. Since strained-Si provides both larger conduction and valence band offsets and does not suffer from alloy scattering (mobility degradation) [11], a significant improvement in carrier mobility can be achieved. Strained-Si is more difficult to grow as compared to strained-Si1−x Gex , since an Si1−x Gex substrate is currently not available and, until recently, the growth of relaxed-Si1−x Gex without forming a large concentration of defects due to dislocation was difficult.

198

Strained-Si heterostructure FETs

Studies of the incorporation of a small amount of C atoms into the Si/SiGe material system to develop new types of buffer layers with reduced misfit dislocations may be useful [12]. However, the ability to achieve both n-MOS and p-MOS devices using strained-Si provides a promising alternative for next generation highperformance SiGe CMOS technology (see, for example, reviews [5, 13] and references therein). Strained-SiGe channel p-MOSFET designs are more fully covered in chapter 7. In this chapter, we discuss the present trends and applications of strained-Si films in SiGe-based CMOS technology. Indepth discussion will cover the film growth, electronic properties of the strained-Si layers on virtual substrates, design and simulation of strainedSi channel HFETs and MODFETs. Recent progress made in integration issues and the future prospects of strained-Si/SiGe-based high-performance HFETs, which may be integrated into Si VLSI/ULSI production, are also discussed. 6.1.

MOBILITY IN STRAINED-SI

Optimum semiconductor device design is ultimately based upon a full understanding and accurate modelling of charge-carrier transport in semiconductors. Due to their relevance for both basic understanding and for device applications, there has always been a strong interest in accurate model descriptions of the mobility as a function of strain, temperature and dopant concentration. For the estimation of maximum theoretical mobilities that can be achieved in strained-Si/SiGe heterostructures, several theoretical studies incorporating various scattering mechanisms have been reported [14–16]. The main scattering mechanisms to be considered in the strained-Si/SiGe material system are [17]: (i) (ii) (iii) (iv)

lattice scattering; ionized impurity scattering; neutral impurity scattering; and alloy scattering.

In addition, the strain distribution in the lattice mismatched SiGe layer affects the relative importance of intra- and inter-valley scattering, due to strain-induced changes in the conduction and valence bands. 6.1.1.

Theoretical mobility

Stern and Laux [14] considered the dependence of electron mobility on remote doping and background doping in the channel, as well as the contribution of interface roughness and interface charges. Their results are in good agreement with the experimental data when realistic background acceptor densities between 1014 and 1015 cm−3 were

Mobility in strained-Si

199

considered [18–20]. Monroe et al [21] have studied the limitations of various parameters including scattering from remote dopants, background impurities, interface roughness, alloy fluctuations, strain, morphology and threading dislocations on the mobility. Considering all potential scattering mechanisms which are reasonable, the authors predicted a low-temperature electron mobility over 1 000 000 cm2 V−1 s−1 , which is comparable to those reached in GaAs/AlGaAs heterostructures. Several other workers have calculated the expected electron mobility enhancements in strained-Si layers relative to bulk-Si [22–24, 26, 27]. Vogelsang and Hofmann [23] have calculated the in-plane electron drift velocities and mobilities in strained-Si for 300 and 77 K. High-field drift velocities were calculated by Monte Carlo (MC) simulations and low-field mobilities by the numerical solution of Boltzmann’s equation including intra- and inter-valley phonon and impurity scattering mechanisms. A mobility enhancement of 74% was obtained at 300 K, compared to 36% at 77 K, and a significant improvement of the drift velocity relative to bulk-Si was reported. Yamada et al [27] have reported a Monte Carlo study of the low-temperature mobility of electrons. For a device structure having 2×1018 cm−3 doping, mobility values of 2.5×105 cm2 V−1 s−1 at 4.2 K and 3.1 × 105 cm2 V−1 s−1 at 1.5 K for an electron density of 7.5 × 1011 cm−2 were obtained. Peak mobility values of 5.0 × 105 cm2 V−1 s−1 at 4.2 K and 7.6 × 105 cm2 V−1 s−1 at 1.5 K were predicted for a lower channel electron density. Rashed et al [22] have studied electron transport in the inversion layer of strained-Si channel n-MOSFETs using an MC tool, taking into account scattering mechanisms, namely phonon, surface roughness and alloy scattering. Table 6.1 shows the computed low-field electron mobility enhancement factors for strained-Si, along with some reported experimental device data. For a low level of strain at low electric field, the electron mobility increases with increasing strain. High-field velocity saturation and overshoot of electrons in strainedSi [24] show only a slight increase in the saturation velocity at both room temperature and 77 K. As the electric field parallel to the current flow is increased, the drift velocity of the electron increases and approaches the saturation velocity. These high electric fields are common in short-channel devices, and thus the saturation velocity, rather than low-field mobility, may ultimately limit the performance of scaled devices [23, 28]. Electron velocity overshoot in strained-Si/Si1−x Gex MOSFETs has also been studied using an MC simulator by Gamiz et al [29] for steadystate and non-steady-state for high longitudinal field transport regimes. It was concluded that at high longitudinal fields, the electron velocity overshoot effects, due mainly to the reduction of the inter-valley scattering rates as the Ge mole fraction increases, improve MOSFET drain current and transconductance.

200

Strained-Si heterostructure FETs

Table 6.1. Low-field electron mobility: dependence on strain level in Si. Ge concentration in the buffer (%)

Strain in Si (%)

Temperature (K)

Computed mobility enhancement factor

10 20 30

0.4 0.8 1.33

300

1.6 1.8 1.9

[22]

2.5 5 10 15 20 25 2.5 5 10

0.1 0.2 0.4 0.6 0.8 1 0.1 0.2 0.4

300

1.14 1.27 1.5 1.65 1.73 1.74 1.28 1.36 1.36

[23]

16.6 33.3 16.6 33.3

0.66 1.33 0.66 1.33

300

2.67 2.67 1.35 1.35

[24]

77

77

Ref

Experimental mobility enhancement factor 10 20 29 29

0.4 0.8 1.3 1.3

300 77

1.45 1.67 1.75 1.35

[25]

However, the progress in the study of hole mobility in strained-Si has been relatively slow. Nayak and Chun [11] have calculated the low-field hole mobility of strained-Si. At room temperature, in-plane hole mobilities were found to be 1103 and 2747 cm2 V−1 s−1 for Ge content of 10% and 20%, several times higher than that of bulk-Si. Table 6.2 shows the computed low-field hole mobility for strained-Si, along with some reported experimental hole mobility enhancement factors obtained from device data. 6.1.2.

Experimental mobility

Low-temperature Hall mobility measurements are commonly determine the overall quality of a heterostructure and are optimize the growth parameters. At low temperature, where effects and scattering by phonons are dramatically reduced, the

used to used to thermal electron

Mobility in strained-Si

201

Table 6.2. Low-field hole mobility: dependence on strain level in Si. Ge concentration in the buffer (%)

Strain in Si (%)

10 15 20 25

0.4 0.6 0.8 1

Temperature (K) 300

Computed mobility cm2 V−1 s−1 1100 1950 2700 3500

Ref [11]

Experimental mobility enhancement factor 29

1.33

300

1.2

[30]

18 18

0.8 0.8

300 77

1.4 2.0

[31]

25

1.0

300

1.5

[32]

mobility becomes very sensitive to residual scattering mechanisms due to background charge impurities, roughness and dislocation. Experimental electron mobility data from strained-Si/SiGe modulationdoped structures may be divided into two categories: (i) data from devices with the uniform composition buffer, and (ii) devices with the compositionally graded buffer. Figure 6.2 shows the range of values for Hall mobility [18, 28, 33–38] using both uniform composition and graded buffer layers. In the case of the uniform composition buffer [33, 36, 38], strain relief is a function of buffer layer thickness. In order to achieve a strain level of 1% in Si, a partially relaxed 0.2 µm Si0.68 Ge0.32 uniform composition buffer is required [39]. For an effective strain level of 1% in Si on a uniform composition buffer, record high electron mobilities of 1280 cm2 V−1 s−1 at 300 K [38] and 17 000 cm2 V−1 s−1 at 1.5 K [36] have been reported. In this type of buffer, mobility is limited by the presence of a large number of defects (109 –1010 cm−2 ) in the buffer layer. The effect of dislocations on electron mobility has been reported by Ismail [40]. It has been found that electron mobility is sensitive to threading dislocations when their density exceeds 3×108 cm−2 , and decreases by two orders of magnitude when the threading dislocation density is 1 × 1011 cm−2 . The introduction of graded buffer layers has made a great impact on the electron mobility enhancement. The upper curve in figure 6.2 represents very high (around 200 000 cm2 V−1 s−1 ) low-temperature mobilities but underestimates the two-dimensional electron gas mobility

202

Strained-Si heterostructure FETs

Figure 6.2. Measured electron Hall mobility versus temperature in modulation-doped strained-Si. The solid symbols are for strained-Si grown on high-quality, graded Si1−x Gex buffer layers, while the open symbols refer to films with constant Ge content. (After Maiti C K et al 1998 Semicond. Sci. Technol. 13 1225–46.)

at room temperature. This is due to parasitic parallel channels of low mobility and an unknown carrier concentration, which freeze out at a low temperature, but lead to a reduced average value of the Hall mobility at a higher temperature. By carefully designing the doping concentration in a series of samples, Nelson et al [41] could separate the contribution of the 2DEG at room temperature, and extracted room temperature mobility in excess of 2500 cm2 V−1 s−1 for the limiting case of a vanishing parasitic channel. The room temperature mobility enhancement factor is almost twice that of bulk-Si, and a factor of more than three greater than that of an Si-MOSFET. The extremely high electron mobility obtained in modulation-doped layered structures, grown using MBE and UHVCVD, indicates that a similar buffer layer quality has been obtained. By optimizing the modulation-doped layer sequence and thickness of strained-Si well [42], the highest mobility values between 300 000 and 400 000 cm2 V−1 s−1 have been

Band structure of strained-Si

203

obtained. Additional wave functioning by front and back gating of some of the structures led to a record low-temperature (0.4 K) electron channel mobility beyond 500 000 cm2 V−1 s−1 [43, 44], which is an improvement of more than a factor of ten compared to the best Si MOSFETs reported. Typical values of room temperature mobility, however, are between 2000 and 2800 cm2 V−1 s−1 for n-channels [28,45], which exceed those in bulk-Si MOSFETs by a factor of four to six. A high hole mobility in excess of 9300 cm2 V−1 s−1 at 4 K in a p-type modulation-doped Si/Si0.87 Ge0.13 /Si heterostructure has been reported by Whall [46]. At room temperature, values between 1400 and 1800 cm2 V−1 s−1 are more typical, still a factor of at least six to nine above that of a bulk-Si p-MOSFET [47].

6.2.

BAND STRUCTURE OF STRAINED-SI

The effect of both strain and alloying on the bandgap of the strainedSi/SiGe material system has been reported in detail by People [10]. In particular, the computed conduction and valence band discontinuities have been based on the calculations of van de Walle and Martin [48]. The extracted valence and conduction band offsets between the strained-Si and relaxed-Si1−x Gex layers [49] are plotted against theoretically estimated values in figure 6.3, showing a good match, particularly at low Ge concentration. Substituting the extracted conduction and valence band offset values, the overall bandgap of the strained-Si can be obtained and is shown in figure 6.4, along with the theoretical calculations of People [10]. The heterojunction band offsets (∆Ec , ∆Ev ) in a strained-Si/SiGe heterostructure have also been determined from measurement of the threshold voltages of a surface channel strained-Si p-MOSFET structure (see figure 6.5(a)) [50]. To determine the threshold voltage at the strainedSi/SiGe interface (VTH ) and the threshold voltage at the strained-Si/SiO2 √ interface (VTS ), the zero current intercept of the IDS –VGS and IDS / gm characteristics were used. The measured values of threshold voltages VTH and VTS were −1.0 V and −1.7 V, respectively [50, 51]. The extracted experimental valence band offset ∆Ev was found to be 160 meV. Using the valence band offset value, conduction band offset was obtained from equations (2.11) and (2.12) where x is the Ge concentration in the top part of a completely relaxed-SiGe buffer cap. The conduction band offset ∆Ec was found to be about 126 meV for a Ge mole fraction x = 0.18 in the relaxed-SiGe layer, and agreement with reported results was found to be good [10, 33].

204

Strained-Si heterostructure FETs

Figure 6.3. Band offsets: (a) valence band and (b) conduction band for strained-Si to relaxed Si1−x Gex . Calculated curves are from People R 1986 IEEE J. Quantum Electron. 22 1696–710 and the data are from Braunstein et al 1958 Phys. Rev. 109 695–710.

6.3.

DEVICE APPLICATIONS

Silicon complementary metal–oxide semiconductor transistors are the most important building blocks in digital integrated circuits due to low power consumption and mature technology. The use of strained-Si/SiGe materials promises to improve the speed-power performance of CMOS by offering higher electron and hole mobilities. Device applications of strained-Si/SiGe with special emphasis on heterostructure metal–oxide semiconductor fieldeffect transistors are described in this section, while the alternative approach of a Schottky gate modulation-doped field-effect transistor is discussed in section 6.5.

Device applications

205

Figure 6.4. Bandgap of strained-Si grown on a relaxed-Si1−x Gex buffer layer. Calculated curves are from People R 1986 IEEE J. Quantum Electron. 22 1696–710 and the data are from Braunstein et al 1958 Phys. Rev. 109 695–710.

Figure 6.5. Device structures for strained-Si MOSFETs with (a) Si on the surface, (b) Si buried and (c) dual strained-Si channels.

206 6.3.1.

Strained-Si heterostructure FETs Strained-Si n-MOSFETs

Very high electron mobilities demonstrated in strained-Si layer suggest a great potential for this material in high transconductance n-MOSFETs. To date, in-plane electron mobilities approaching 3000 cm2 V−1 s−1 have been reported in long-channel MOSFETs with both surface and buried channels [52]. Figure 6.5 shows the schematic diagrams of several possible configurations of strained-Si MOSFETs. All the structures have thick, relaxed-Si1−x Gex buffer layers, consisting of a layer with linearlygraded Ge, followed by a constant Ge layer. The surface channel device (figure 6.5(a)) has a single layer of thin strained-Si grown on top of the relaxed buffer layer. This layer is oxidized to form a gate oxide. The buried strained-Si channel device (figure 6.5(b)) has a layer of strained-Si buried beneath a thin layer of relaxed Si1−x Gex . An additional layer of strained-Si is necessary to form a gate oxide on top of the Si1−x Gex , but ideally this additional Si layer (sacrificial layer) should be consumed during oxidation. If this sacrificial layer is not consumed fully, then a very thin layer of Si, left between the gate oxide and the Si1−x Gex barrier layer (figure 6.5c) can act as a parallel conducting channel, strongly affecting device performance. Depending on the dopant type in the layers, these structures can be used for n- or p-MOSFETs. Welser et al [52, 53] have fabricated both p- and n-MOSFETs using all these device structures and some of their results on n-MOSFETs are presented below. Long-channel (L × W = 10 µm × 168 µm) surface and buried n-MOSFET devices fabricated on relaxed-Si0.7 Ge0.3 buffer layers have shown well-behaved output characteristics. The effective low-field mobilities for these device structures are shown in figure 6.6. For the surface-channel strained-Si device µeff is enhanced compared to the bulk-Si control device and has a similar dependence on the effective electric field. The peak mobility is 1000 cm2 V−1 s−1 , which shows an 80% enhancement over Si-control (550 cm2 V−1 s−1 ). The peak mobility value for the buried channel device is over 1600 cm2 V−1 s−1 , which is almost three times that of Si-control device. Room temperature effective mobility versus electric field curves of surface-channel, strained-Si n-MOSFETs with different Ge content in the buffer layer are shown in figure 6.7, along with the mobility extracted from a bulk-Si control device. Strained-Si mobility increases with increasing strain (more Ge content in the relaxed buffer layer) and has little dependence on the effective electric field. Rim et al [54] have reported measurements on deep submicron (0.1 µm) strained-Si n-MOSFETs. An electron mobility enhancement by 75%, compared to typical Si MOSFET mobilities, has been reported in spite of the high channel doping and vertical effective field present in the device. The ac measurements, used to reduce self-heating effects, have shown an extrinsic transconductance increase by 45% for a channel length

Device applications

207

Figure 6.6. Effective low-field mobility versus effective field for different n-MOSFETs. The surface channel strained-Si mobility shows a fairly constant mobility enhancement compared to that of the control-Si device, while the buried strained-Si mobility peaks at low fields, but decreases rapidly at higher fields. (After Welser J J 1994 The application of strained-silicon/relaxed-silicon germanium heterostructures to metal–oxide semiconductor field-effect transistors (Stanford University).)

Figure 6.7. Effective mobility of surface-channel, strained-Si n-MOSFETs at room temperature. Strained-Si mobility increases with increasing strain (more Ge content in the relaxed buffer layer). (After Welser J J 1994 The application of strained-silicon/relaxed-silicon germanium heterostructures to metal–oxide-semiconductor field-effect transistors (Stanford University).)

208

Strained-Si heterostructure FETs

Figure 6.8. Effective mobility, µeff versus vertical effective field, Eeff . For high Eeff , µeff is enhanced by 75% for strained-Si compared to the epi control-Si device and state-of-the-art universal MOSFET mobility. Data from Welser J et al 1994 IEEE IEDM Tech. Dig. pp 373–6, Takagi S et al 1994 IEEE Trans. Electron Devices 41 2357–62. (After Rim K et al 1998 IEEE IEDM Tech. Dig. pp 707–10.)

of 0.1 µm. In figure 6.8, the effective mobility µeff , measured on large devices, is shown as a function of vertical effective field Eeff . Even for high Eeff (>0.5 MV cm−1 ), the effective mobility µeff for the strained-Si device is enhanced by ∼75% compared to the epi control-Si. Electron mobility enhancements observed at lower Eeff [25] are thus sustained at higher effective fields, as predicted theoretically for the phonon-limited mobility in strained-Si MOS inversion layers [16]. The measured µeff for strained-Si (peak µeff ∼ 575 cm2 V−1 s−1 ) is also enhanced over the state-of-the-art n-MOSFET mobility [55]. These results demonstrate that, unlike conventional Si which is constrained to the universal MOSFET mobility curve (figure 6.8, dotted curve), strained-Si provides mobility improvement at a given Eeff . Such an enhancement in µeff at high channel doping and Eeff enables fabrication of high mobility, deep submicron devices with channel doping suitable to counter short-channel effects (SCE).

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6.3.2. Strained-Si p-MOSFETs Exploiting the demonstrated higher mobility for holes, efforts have been made to fabricate strained-Si p-MOSFETs. Various research groups working on the problem were able to achieve better performance with strained-Si compared to control-Si devices. The tensile strain in silicon grown on a relaxed-SiGe buffer raises the light-hole band and lowers the heavy-hole band, leading to a significant increase in the low-field hole mobility. Observation of hole mobility enhancement in strained-Si pMOSFETs was demonstrated by Nayak et al [32]. The initial devices were fabricated on a 1 µm uniform composition partially relaxed-SiGe buffer, which is known to have a very high defect density [56] and this resulted in a limited performance (subthreshold slope 111 mV/decade). An improved device structure and process to fabricate high performance strained-Si p-MOSFETs has been reported, with a highquality (defect density Eg , the photon flux penetrates through the semitransparent metal layer and gets absorbed in the semiconductor. The photogenerated electron–hole (e–h) pairs move in opposite directions due to the existing electric field with their respective saturation velocities and are collected at the electrodes. This is a very efficient mode of operation of Schottky diodes and is similar to that of a highspeed p–i–n diode. The fabrication of a Schottky barrier photodiode is also easy and lends itself for integrated applications. 9.1.3.

p–i–n photodetectors

p–i–n photodetectors are finding extensive applications in long haul and high bit rate optical communication systems and in local area networks for operation in the infrared region (0.8–1.6 µm). In addition to optical communication, these devices are also useful for sensing applications as they have superior electro-optical characteristics, namely low dark current, high quantum efficiency, greater sensitivity and high speed of response [33–35]. An important mode of operation of a p–i–n photodiode under the exposure of photon flux is the reverse biased configuration. In order to maximize the quantum efficiency of the diode, an intrinsic layer (i-layer) is inserted between two heavily-doped p+ - and n+ -layers and the resulting structure is a p–i–n diode. When a reverse bias is applied across the device, entire i-region becomes depleted. Due to high resistivity and total depletion of the i-layer, almost all the electric field appears across it. The applied reverse bias should not be so high that breakdown can take place. The dark current is independent of applied reverse bias. As light impinges from the top surface, most of the photon flux passes through the relatively thin top layer. The absorbed photons generate electron–hole pairs which drift towards the electrodes due to the existing electric field to give rise to a photocurrent in the external circuit. One of the advantages of heterojunction p–i–n photodiodes is that the device characteristics are tunable by changing the composition of the i-layer. Another is the resonant–cavity effect, due to the refractive index change at the heterojunction, which increases the photoresponsivity of the diode without affecting the transit-time-limited bandwidth [36]. 9.1.4.

Metal–semiconductor–metal photodetectors

Metal–semiconductor–metal photodetectors (MSM-PDs) are made up of interdigitated metal fingers forming back-to-back Schottky diodes on an undoped semiconductor surface (see figure 9.1). These detectors

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Figure 9.1. (a) Schematic structure of an MSM photodiode and (b) analysing area. (After Chattopadhyay S and Maiti C K, unpublished data.)

are very attractive for many optoelectronic applications, particularly for high-frequency wideband operation and are used in multi-gigabit optical communication with high sensitivity. MSM devices can be integrated in conventional IC-processing technology. On application of the bias, one junction becomes forward-biased while the other becomes reverse-biased. It can be designed so that the region between the two electrodes is almost depleted. When the incident photon flux impinges on the photo-active area (interdigitated area), the diode responds as a Schottky photodetector discussed above. Some of the important design parameters for MSM-PDs

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are responsivity, dark current and capacitance, which are discussed below. The dark current (which decides the minimum detectable power) of a photodetector significantly contributes to the noise at the input of an optical receiver, which in turn plays a crucial role in deciding the sensitivity of a receiver. Excess carriers responsible for dark current increase the capacitance and decrease the response speed of a detector. The detector noise associated with its dark current is a shot noise and its mean square value is given by i2d  = 2qId ∆f. (9.7) Furthermore, the minimum optical power required to achieve a photocurrent equal to the noise current id is usually regarded as the minimum detectable power of a detector. In an MSM structure, the dark current is a metal/semiconductor interface phenomenon and is attributed to thermionic emission of the carriers across the Schottky barriers [37]. Usually, thermionic emission of the carriers across a reverse-biased Schottky junction accounts for the dark current in MSM photodiodes [38] and the dark current density is given by J = A∗n T 2 e−q(φb −∆φb )/kT .

(9.8)

It is noted that a low Schottky barrier height would result in excess carrier injection in the semiconductor from the cathode and would lead to a large dark current. It has been proposed that equation (9.8) is valid until the conduction band profile of an MSM photodiode does not reach the flat band condition at the forward-biased contact [39]. When the conduction band at the anode reaches the flat band condition, thermionic emission of holes across the barrier at anode starts and is accounted for the dark current which is given by J = A∗n T 2 e−q(φb −∆φb )/kT + A∗p T 2 e−q(φb −∆φb )/kT

(9.9)

where A∗ are the respective Richardson constants and ∆φ are the respective barrier height lowering due to image force. The flatband voltage VFB can be expressed as [37] qNd S 2 VFB = (9.10) 2s 0 where S is the electrode spacing and Nd is the donor concentration in the layer. The dark capacitance of an MSM photodetector is contributed by the electrostatic field around the alternatively charged parallel metal fingers. The speed of an MSM detector is limited by RL C time constant if it is longer than the transit time or recombination time. Here, RL consists of the load resistance and series resistance of the metal fingers. The detector capacitance can be estimated by using a model based on conformal

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mapping [40]. If W is the finger width and P is the finger pitch (sum of width and spacing, i.e., P = W +S), the total detector capacitance is given by C0 A (9.11) Ctotal = P where A is active area of the detector. 9.2.

OPTICAL PROPERTIES OF SIGE AND SIGEC FILMS

It has been shown that quantum efficiency is determined mainly by the absorption coefficient of the semiconductor. The measured optical absorption coefficient, α, and refractive indices of Si and Si1−x Gex for different values of the Ge fraction, x, are shown in figures 9.2 and 9.3. The

Figure 9.2. Optical absorption coefficients of Si, Ge and undoped SiGe alloys.

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Figure 9.3. Refractive indices of Si, Ge and undoped SiGe alloys.

data are taken from [41]. It is seen from figure 9.2 that Si is transparent in the wavelength region 1.20–1.60 µm, while the SiGe absorption edge shifts towards the red with increasing Ge concentration in the alloy. The shift offers a means for absorbing 1.3–1.6 µm light, by choosing x > 0.3 for 1.3 µm and x > 0.85 for 1.55 µm. From figure 9.3, it may be noted that the refractive index increases with the increase in Ge concentration. While intrinsic Si and Ge are transparent from near-infrared up to 20 µm and beyond, the optical transmission of group IV alloys is found to reduce by heavy doping [2]. For unstrained (bulk) SiGe alloys, the absorption data have been provided by Braunstein et al [42]. Orner et al [43] have measured the optical absorption at phonon energies near the bandgap of a Ge-rich SiGeC (x ≈ 0.90, y ≤ 0.02) film by employing Fourier transform infrared (FTIR) spectroscopy. As the film

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Figure 9.4. Optical absorption coefficient (α) of a Ge-rich Si0.11 Ge0.88 C0.01 film: (a) C is primarily substitutional and (b) C is primarily interstitial. (After Orner B A et al 1996 Appl. Phys. Lett. 69 2557–9.)

was Ge-rich, their bandgap energies are less than that of Si. Absorption data and the best fit curves are as shown in figure 9.4. Figure 9.4(b) shows a comparison between two films with carbon at the interstitial and substitutional sites. In both cases the infrared absorption edge of the alloy shifts towards the red. Figure 9.5 shows the refractive index of the epitaxial Ge1−x Cx as a function of donor concentration and compares it to Ge epitaxial layers grown under identical conditions. Introducing carbon into epitaxial Ge films doped with P decreases the refractive index near the absorption edge. Figure 9.6 illustrates the absorption coefficient, α, of phosphorus-

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Figure 9.5. Refractive index versus donor concentration for Ge1−y Cy and Ge epitaxial films on Si(100). (After Dashiell M W et al 1998 Thin Solid Films 321 47–50.)

Figure 9.6. Absorption coefficient versus photon energy of Ge1−y Cy layers on Si(100) for ND = 7 × 1019 cm−3 , ND = 2 × 1018 cm−3 and undoped. Included are values for intrinsic bulk-Ge. (After Dashiell M W et al 1998 Thin Solid Films 321 47–50.)

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doped Ge1−y Cy films grown epitaxially on Si(100) for α > 100 cm−1 . The absorption edge experiences a redshift with increasing phosphorus concentrations for both Ge1−y Cy and Ge films. High-purity Ge data are also included in the figure. Note that undoped Ge1−y Cy epitaxial layers exhibit the same absorption coefficient as does intrinsic bulk germanium for α > 100 cm−1 . Thus, a significant band structure modification was not observed by optical absorption for these C concentrations. 9.3.

OPTICAL DEVICES USING SIGE ALLOYS

The main aims of SiGe optoelectronics are: high responsivity, low noise, fast response and integration with the conventional Si-processing technology. Most of the reported studies include: (i)

p–i–n diode for 1.3 µm wavelength with 50% internal quantum efficiency, 200 ps impulse response and 10 pA µm−2 dark current at 15 V bias [2, 44–46]; (ii) waveguided p–i–n photodetectors with 50% internal quantum efficiency at 1.3 µm and 200 nA dark current at −15 V in a 10×750 µm device [25, 47]; and (iii) a waveguided metal–semiconductor–metal photodiode [48].

A responsivity of 0.2 A W−1 was measured at 1.3 µm over a 1 nm detector length with a 500 pA µm−2 dark current at 5 V bias. Si1−x Gex rib waveguide avalanche photodetectors for operation at 1.3 µm and strained layer superlattice waveguide photodetectors have also been reported [49–52]. Silicide/Si1−x Gex Schottky diodes have been proposed for detecting far-infrared radiation, taking advantage of the controllable bandgap of SiGe. For such diodes, the general requirement is to adjust the parameters such as the barrier height and ideality factor. PtSi/Si1−x Gex Schottky photodetectors have been proposed for detection of infrared radiation of wavelengths up to 10 µm [19]. Xiao et al [53] have demonstrated Pd2 Si/Si1−x Gex and PtSi/Si1−x Gex Schottky-barrier long-wavelength infrared detectors The cut-off wavelength is found to be dependent on the amount of Ge present in the strained layer. Figure 9.7(a) shows the measured Fowler plots for three Pd2 Si/Si1−x Gex (x = 0, 0.20 and 0.35) detectors using an FTIR spectrometer at 77 K. As expected, the cut-off wavelength clearly increases with the increasing Ge fraction, x, for the Pd2 Si/Si1−x Gex detectors. The spectral response of a PtSi/Si0.85 Ge0.15 detector is shown in figure 9.7(b) along with that of a PtSi/Si control device. The cut-off wavelength is extended from 5.2 to 8.8 µm with only 15% Ge in the alloy, corresponding to a barrier height reduction of 100 meV. By extrapolation, a cut-off wavelength beyond 10 µm is expected for a PtSi/Si1−x Gex detector

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Figure 9.7. Infrared photoresponse at 77 K of (a) Pd2 Si/Si1−x Gex and (b) PtSi/Si1−x Gex Schottky barrier detectors. (After Xiao X et al 1993 IEEE Electron Device Lett. 14 199–201.)

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Figure 9.8. Comparison of measured external responsivities of PtSi/Si0.80 Ge0.15 and PtSi/Si infrared detectors. The points represent data obtained with a calibrated infrared monochromator (40 K), while the lines are scaled results from FTIR measurements. (After Xiao X et al 1993 IEEE Electron Device Lett. 14 199–201.)

with as little as 18% Ge in the alloy. The measured external responsivities (40 K) of the PtSi/Si0.85 Ge0.15 detector and the PtSi/Si control device are shown in figure 9.8. Although the actual measurement was limited to 4 µm, extrapolated full responsivity curves for the PtSi/Si0.85 Ge0.15 detector showed superior responsivity to the conventional PtSi/Si detector over the whole wavelength range. Low-loss waveguides have been proposed using group IV alloy films. Light can propagate in four types of group IV waveguides: lightlydoped silicon on heavily-doped silicon [54–57], epitaxial Si1−x Gex on Si [58–62], silicon-on-sapphire [63] and silicon-on-insulator [64–68]. In addition to epitaxial SiGe, SiC or SiGeC can be used as waveguide cores. Crystallographic defects such as threading dislocations need to be kept below 104 defects/cm2 in order to keep losses below 1 dB cm−1 in silicon-oninsulator and SiGe/Si waveguides [68]. A loss of 0.5 dB cm−1 for transverse electric (TE) and 0.6 dB cm−1 for transverse magnetic (TM) modes at 1.32 µm have been reported in chemical vapour deposited Si0.99 Ge0.01 ribs on Si [60]. The propagation loss in a polarization independent single-mode rib made from Ge-diffused Si has been found to be 0.3 dB/cm at 1.3 and

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Figure 9.9. Schematic view of integrated SiGe/Si planar photodetector with trench for optical fibre guide. The optical fibre is attached to the trench and the core of optical fibre is coupled to the photodetector with alignment-free. (After Tashiro T et al 1997 IEEE Trans. Electron Devices 44 545–50.)

1.55 µm. In a single-mode SOI/SIMOX rib, the reported propagation loss is about 0.4 dB cm−1 for polarization independent 1.3 and 1.55 µm infrared radiations [65]. An integrated p–i–n SiGe/Si-superlattice photodetector (as shown in figure 9.9) with a planar structure has been developed on a bonded siliconon-insulator for Si-based optoelectronic integrated circuits [69, 70]. An Si, 30 periods, superlattice absorption layer, a 0.1 µm p-Si buffer layer and a 0.2 p+ –Si contact layer were deposited on a bonded SOI. The bonded SOI is used to increase the external quantum efficiency, ηext of the photodetector. Moreover, to achieve simple and stable coupling of an optical fibre to the photodetector, a 63 µm deep and 128 µm wide trench is formed in the silicon chip. The p–i–n planar photodetector exhibits a high ηext of 25–29% with a low dark current of 0.5 pA m−2 and a high-frequency photoresponse of 10.5 GHz (3 dB bandwidth) at a wavelength of 0.98 µm. A vertical-cavity p–i–n SiGe/Si photodetector in bonded SOI substrate has been reported to exhibit a high external quantum efficiency of 60% with a low dark current of 0.5 pA µm−2 and a high photoresponse of 7.8 Gbit s−1 at λ = 980 nm as shown in figure 9.10. Light emission has been observed in various structures, such as rare earth metal-doped Si, strained-SiGe quantum wells, porous-Si, quasi-direct gap short period SiGe superlattices and Si quantum wires [71,72]. Si1−x Gex quantum well structures exhibit type I band alignment, where most of the band offset occurs in the valence band when the Ge concentration is low. This type of structure allows for only holes to be effectively confined in

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Figure 9.10. Frequency response of a photodetector at an area of 5000 µm2 . A 3 dB bandwidth of 7.8 GHz is confirmed at 5 V reverse bias at λ = 980 nm. (After Morikawa T et al 1996 IEEE IEDM Tech. Dig. pp 661–4.)

the quantum wells, whereas to form a light emitter, it is necessary to have an asymmetric type II structure which confines electrons in the conduction band. Neighbouring confinement structures (NCS) using Si1−x Gex have been developed [73]. NCS structures consist of a thick (>3 µm) Si0.82 Ge0.18 buffer in which a step-graded Si1−x Gex layer with x ranging from 0 to 0.18 is grown, and then capped with a uniform 2.5 µm Si0.82 Ge0.18 layer. The NCS structure is then grown on Si0.82 Ge0.18 in which a tensile strained 10 ˚ A Si-only QW is grown for electron confinement, and a 10 ˚ A Si0.64 Ge0.36 QW is grown for hole confinement. This structure allows for a nearly ‘direct’ transition as evidenced by orders of magnitude enhancement of no-phonon low-temperature PL, as compared to SiGe QWs using type I and symmetric type II QWs. The NCS technique, when coupled with growth on relaxedSiGe buffers, is a promising approach in the production of Si-based light emitters [71]. Some reports on Si1−x Gex /Si quantum well infrared photodetectors (QWIP) have appeared [1, 74]. An integrated waveguide photodetector, as shown in figure 9.11, deposited on a SIMOX substrate, has been fabricated and an external quantum efficiency of 11% with an impulse response time of 400 ps has been observed. For the mid-IR range (3–5 µm) highly p-doped

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Figure 9.11. Schematic layout of a waveguide/detector device on a SIMOX substrate. (After Presting H 1998 Thin Solid Films 321 186–95.)

Si/SiGe QW detectors have been deposited on an undoped, double-sided polished Si substrate based on hetero-internal photoemission (HIP) over the Si/SiGe barrier. The absorption and photocurrent spectra have been measured from fabricated mesa detectors at 77 K. The photoresponse spectrum of the HIP detectors is found to be widely tunable in the technological important wavelength band of 3–5 µm by choice of Ge content, well thickness and doping level. Quantum efficiencies of 1% at 4 µm and 77 K have been achieved from SiGe HIP structures, dark currents as low as 10 × 10−8 A cm−2 can be obtained by modulation doping. The key features of a p-Si1−x Gex /Si QWIP are shown in figure 9.12. The alloy layers are grown pseudomorphically on an Si substrate, and are compressively strained. The alloy bandgap is smaller than that of Si for a fully strained layer [75]. The higher density of states in SiGe subbands suggests that SiGe QWIPs are inherently superior to AlGaAs QWIPs. Valence band technology is preferred for 8–14 µm SiGe/Si QWIPs because it allows normal incidence of light on the detectors. The polarization of normal light is always perpendicular to the growth direction of the QW layers. Although low noise and good responsivity have been realized, a

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Figure 9.12. Energy band diagram showing the shift of the absorption edges in a symmetrically strained-Si1−x Gex /Si multiple quantum wells (MQWs). Electrons are confined in the wider bandgap of Si layers and holes are confined in the narrower bandgap of Si1−x Gex layers. E1 and HH1 are the minimum electron and hole energy levels in the quantum wells. L is the width of the quantum well.

long length in the waveguided diode is needed due to a low absorption coefficient. This long length tends to raise the parasitic capacitance of the distributed diodes. It becomes difficult to obtain better responsivity at higher wavelengths as the stability of strained-SiGe QWs decreases rapidly as the Ge fraction increases. Photocurrent and absorption characteristics of SiGe QWs and Sim Gen SLS have been measured at room temperature by Presting [1]. The wavelength-dependent photocurrent spectrum has been measured using a grating monochromator illuminated by a tungsten lamp, and the electrical signal has been detected by a lock-in amplifier technique. When comparing the absorption characteristics of the SLS and QW structures, it is evident that substantial absorption at 1.3 µm occurs for both structures. The different long wavelength absorption limits between the two were explained

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Figure 9.13. Circuit diagram of a SiGe–Si p–i–n HBT photoreceiver. (After Rieh J-S et al 1997 IEEE Photonics Technol. Lett. 10 415–7.)

by taking into account the different buffer layer thicknesses and Ge content in the structures. A monolithic SiGe/Si p–i–n HBT front-end transimpedance photoreceiver circuit, as shown in figure 9.13, has been fabricated by Rieh et al [76]. Figure 9.13 shows the circuit diagram with a transimpedance amplifier which consists of a photodiode, common-emitter gain stages, two emitter follower buffers and a resistive feedback loop. For fabrication, a mesa-type SiGe/Si p–i–n HBT technology was used. Fabricated HBTs showed an fmax of 34 GHz with dc gain of 25. SiGe/Si p–i–n photodiodes, which share base and collector layers of HBTs, demonstrated a responsivity of 0.3 A W−1 at λ = 850 nm (incident optical power of 22 mW) at a reverse bias of 5 V, and steadily increased as the reverse bias was increased. The corresponding external quantum efficiency was 43%. The bandwidth of the photodiode was about 450 MHz (see figure 9.14(a)). The frequency response of the monolithically integrated single-feedback p–i–n HBT photoreceiver, excited with λ = 850 nm light, is shown in figure 9.14(b) and exhibited a bandwidth of about 460 MHz, which is limited by the bandwidth of p–i–n photodiode. The integration of Ge photodetectors on silicon substrates is also advantageous for various Si-based optoelectronics applications [77]. Figure 9.15 shows the schematic diagram of an integrated p–n mesa

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Figure 9.14. (a) Measured frequency response of the SiGe p–i–n photodiode and (b) measured frequency response of the SiGe photoreceiver. The solid curves show the fit to the measured response. (After Rieh J-S et al 1997 IEEE Photonics Technol. Lett. 10 415–7.)

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Figure 9.15. A schematic diagram showing the optimized relaxed graded buffer growth sequence with the Ge mesa photodiode on top. (After Samavedam S B et al 1998 Appl. Phys. Lett. 73 2125–7.)

photodiode. Integrated mesa Ge photodiodes on an optimized graded relaxed-SiGe buffer on Si showed a very low dark current of 0.15 mA cm−2 . Capacitance measurements indicate that the detectors are capable of operating at high frequencies (2.35 GHz). The photodiodes showed an external quantum efficiency of 12.6% at 1.3 µm wavelength laser excitation in the photodiodes. 9.4.

OPTICAL DEVICES WITH SIGEC AND GEC ALLOYS

Conventional Si Schottky photodiodes and MSM photodetectors operate at wavelengths in the UV and visible region (0 dB gain @ +3 dBm LO ECL ring oscillator 6.7 ps, 0.25 V swing at 1.3 mA, 400 mV swing ECL ring oscillator 13.7 ps, 8 mA/stage, 200 mV swing LNA 2.4 GHz, 10.5 dB gain, 0.95 dB NF PCS CDMA, 12 dB gain, 13 dB NF, 3 V/5 mA, IIP3 > +10 dBm DECT, 1.8 GHz, 20 dB gain, 1.8 dB NF Broadband amplifier 8 dB gain, 17 GHz BW, 16.8 mA @ 2.5 V 35 GHz BW, 270 mW Timing circuit 10 Gb s−1 , 150 mA @ 5 V Power transmitter 2.4 GHz, 1W Pout , 48% PAE, 3.5 V, @ 1.5 V 150 mW Pout W, 47% PAE

Technology comparison

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Table 10.2. (continued) Circuit type Performance

Year

Process

1997 1999 1998

IBM IBM TEMIC

1998

IBM

1998

Hitachi

1997

Siemens

1998

IBM

1999

IBM

Power amplifier Tx, 900 MHz, 70%PAE, 16 dB gain 30 dBm, 16 dB gain, 75% PAE, 3.5 V 27 dBm, 26 dB gain, 45% PAE, 3.6 V, 1.9 GHz CMOS ASIC chip Multiplexer 2:1, 40 Gb s−1 output Demultiplexer 1:2, 60 Gb s−1 output 5.5 GHz LNA 14.1 dB gain, 2 dB NF Mixer, VCO Mixer: 16.4 dB Power conversion gain, IIP3 11.1 dBm, NF 6.6 dB, 20 Ω cm−1 ) of the substrate lead to severe processing problems associated with such wafers (specifically slip dislocations and warpage). 10.7.

COMMERCIALLY AVAILABLE PRODUCTS

IBM and Daimler–Chrysler have been involved in the SiGe area for a long time. Corporations such as Lucent, Motorola, ST-Microelectronics, Philips, Infineon, Maxim, Temic, Hitachi and many others have recently begun development or deployment of SiGe-based HBT processes, and are likely to make the transition from present efforts in discrete technology to integrated SiGe BiCMOS technology. SiGe-based mixed-signal technology is rapidly making its way into the consumer mainstream, at the high end of the telecommunications market. Present trends indicate that SiGe technology will find applications in the frequency range 2–30 GHz, above which GaAs is well established. Components for personal communication services devices operating between 1.8–2.2 GHz are a fast growing market segment, along with pagers and wireless local area networks. Other wireless opportunities might include direct-broadcast satellite TV and local multipoint distribution services (LMDS). Devices based on SiGe technology will be able to move data across networks at speeds traditionally considered beyond the reach of silicon technology. This will bring better performance at low costs to fibre transport networks, high-speed cellular voice/data phones and wireless devices such as global positioning satellite (GPS) receivers. Another application is a differential global positioning system (DGPS) satellite receiver that uses several GPS channels centred on 1.5 GHz. A related product is targeted for the automobile industry, which has significant potential to use wireless technology for traffic management and control, and collision avoidance systems. Inexpensive 24 GHz collision warning radar systems for mainstream automobiles are also needed. 10.7.1.

TEMIC Semiconductors

Temic Semiconductors supplies integrated circuits to the communications, automotive, data processing and aerospace markets. As a leader in SiGe technology, it provides high-performance SiGe solutions in highvolume production. Its SiGe process is a suitable technology for RF chip applications. It provides significant cost benefits on the component and system level side versus GaAs and, in a market where prices are falling, this will be the key issue for manufacturers. The SiGe process for high-

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volume production was set up on a well-proven ultrahigh-frequency (UHF) process. The wafer fabrication uses a progressive and widely automated 6 in wafer line, high-volume quantities can be provided reliably. Temic Semiconductors replaced the usual GaAs PA and LNA devices by SiGe integrated solutions in the frequency range of 400–2400 MHz. Thanks to SiGe, the U7004B, U7006B, T7024 and T0980 provide extremely low noise figures (e.g., 1.6 dB at 1.9 GHz in 50 Ω systems) and high integration. Figure 10.12 shows a typical application circuit using the U7004B SiGe front-end IC. As the LNA, PA and transmit–receive switch driver are included, a large number of external components, and thus system cost, can be saved. They also provide very efficient power amplifiers. The PAE of the T0980 front-end for 400 MHz reaches a typical value of 60%.

Figure 10.12. Application circuit using U7004B SiGe front-end IC. (After Temic Semiconductors, Germany.)

390

RF applications of SiGe HBTs

Solutions using GaAs devices are expensive and normally require a negative auxiliary voltage. The front-end ICs U7004B, U7006B, T7024 and T0980 manufactured in SiGe technology need only a single, positive 3 V supply voltage. This results in lower system and production costs as well as extended talk and standby times due to the low current consumption. The TST091x family members enable the cost-effective production of a new mobile phone generation. End products are expected to be smaller and lighter as 3 V operation makes use of a single battery cell. The high PAE and low-power operation of SiGe PAs allow for longer talk times. Since SiGe does not require negative supply voltage or a battery disconnect switch as needed by competing devices using GaAs technology, both system and production costs will be reduced. Temic Semiconductors offers SiGe PAs for single-band operation in the 900 MHz frequency range (GSM 900) and GSM 1800/1900, as well as for dual-band operation (GSM 900 and 1800/1900). With the CW capable T0930, Temic provides a high-performance, SiGe integrated solution with maximum efficiency for two-way pagers. A power amplifier, RF power control and a standby circuit are included. With SiGe, the current consumption in power-down mode is significantly reduced, eliminating the need for a high-side switch. This results in less external components—board space, and thus overall size can be reduced dramatically. The LNAs TST095x with a two-stage amplifier and switchable gain provide the perfect combination of low noise (NF = 2.2 dB in high gain mode), large signal capability (IIP 3 = −7 dBm in low gain mode) and high reverse isolation (minimum −40 dB). Both the low current consumption and power-down function help to extend battery lifetime. 10.7.2.

IBM

The mainstream SiGe chips introduced by IBM include basic building blocks—low noise amplifiers, voltage controlled oscillators, power amplifiers and discrete transistors. SiGe is well suited to realize innovative highfrequency products, e.g. antenna switches for the transmit/receive path, satellite communication applications or wireless local area networks. Several of the chips are designed as low-cost, highly-reliable direct replacements for gallium arsenide parts for a broad spectrum of communications applications and are listed below. Several system-level hardware and software products [66] are now in production and a brief list is given in table 10.7: • • • •

SiGe SiGe SiGe SiGe

3 V GSM tri-band low-noise amplifier 3 V tri-band image reject mixer with low-noise amplifier 3 V GSM tri-band voltage controlled oscillator PDC linear power amplifier

Commercially available products • • •

391

SiGe high dynamic range 1900 MHz low-noise amplifier SiGe high dynamic 900 MHz low-noise amplifier SiGe high dynamic range low-noise transistor

IBM has also been a partner in a number of collaborative ventures, involving application of their SiGe technology to other companies products. Alcatel has developed several 40 Gb s−1 SONET optical data transmission systems operating with the bit decision circuit based upon the IBM 50 GHz SiGe technology. A Harris Prism II chip set, a low-cost wireless local area network (WLAN) product operating on the IEEE 802.11 standard at 2.4 GHz, has been converted to SiGe technology. A factor of two reduction in chip count and cost, a factor of four improvement in range and a fivefold increase in bit rate have been achieved. A recent announcement by Siemens revealed the use of the IBM SiGe technology in developing third-generation (3G) cellular base station electronics. As 3G is a wideband CDMA protocol, the combination of high linearity at low power makes SiGe technology extremely well suited to this application.

Table 10.7. A brief listing of mixed-signal SiGe-based product offerings and their market status. (After Meyerson B S 2000 IBM Res. Dev. J. 44 391–420.) Company

Product category

Description

AMCC

Wired

Alcatel

Wired

Harris Intersil

Wireless

IBM Leica Siemens

Wireless

3.2 Gb s−1 17 × 17 differential crosspoint switch OC-192 SONET/SDH transimpedance amplifier OC-48 multi-rate clock and data recovery solution multi-rate OC-48 transceiver 2.5 Gb s−1 multi-rate clock recovery and limiting amplifier device 3.3 V OC-48 transimpedance amplifier for WDM and TDM applications Complete 10 Gb s−1 SONET system with all electronics PRISM II chip set 11 Mb s−1 (5 ICs 5 complete data comm radio operating at 2.4 GHz bands up to 11 Mb s−1 ) Power amplifier and detector (SiGe) RF-to-IF converter (SiGe) I/Q modulator/demodulator and synthesizer (SiGe) Direct-conversion digital GPS receiver and GPS engine Third-generation mobile cellular base station

Wireless

392 10.8.

RF applications of SiGe HBTs SUMMARY

In applications, SiGe-based devices and circuits represent an outstanding extension of conventional Si technologies, opening up frequency ranges which have previously only been the domain of III/IV compound semiconductors such as GaAs. SiGe HBT technology has the potential to revolutionize high-frequency transceiver design in a way comparable to the revolution in digital integrated circuit technology brought about by CMOS in the 1970s. Its unique combination of outstanding high-frequency performance, low manufacturing cost and high yield will provide abundant opportunities for new architectures and new systems in the near future. Many semiconductor companies, other than IBM and TEMIC, have recently begun development or deployment of SiGe-based technology and are likely to make the transition from discrete technology, particularly in BiCMOS applications. In the longer term, heterostructure CMOS technology may well take over at even higher frequencies. For mobile applications, the recent announcement of commercially viable implementation of silicon-on-insulator technology will have far reaching consequences in the semiconductor industry. The harnessing of SOI technology will result in faster chips that also require less power—a key requirement for extending the battery life of small handheld devices that will be pervasive in the future. Research on fabricating SiGe devices in a thin layer of silicon on top of an insulator (such as silicon oxide) has been initiated. If it becomes successful, this breakthrough may advance the microelectronics technology one or two years ahead of where it would have been with conventional bulk-Si technology. As early as 1995, IBM reported at the Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) that they believed an important application of SiGe technology will be a ‘single chip solution’ for wireless applications. Such a chip which will handle both RF and digital functions is now a reality! BIBLIOGRAPHY [1] Larson L E 1998 High-speed Si/SiGe technology for next generation wireless system applications J. Vac. Sci. Technol. B 16 1541–8 [2] Abidi A A 1995 Direct-conversion radio transceivers for digital communications IEEE J. Solid-State Circuits 30 1399–410 [3] Gray P and Meyer R 1995 Future directions of silicon ICs for RF personal communications IEEE CICC Proc. pp 83–90 [4] Rudell J C, Ou J-J, Cho T B, Chien G, Brianti F, Weldon J A and Gray P 1997 A 1.9 GHz wide-band IF double conversion CMOS receiver for cordless telephone applications IEEE J. Solid-State Circuits 32 2071–87 [5] Arnold R G and Pedder D J 1992 Microwave characterization of microstrip lines and spiral inductors in MCM-D technology IEEE Trans. Compon. Hybrids Manuf. Technol. 15 1038–45

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396

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[52] Narayanaswami R S 1998 The design of a 1.9 GHz 250 mW CMOS power amplifier for DECT Master’s Thesis University of California, Berkeley [53] Cripps S 1999 RF Power Amplifiers for Wireless Communications (Norwood, MA: Artech House) [54] Nelson B, Cripps S, Kenney J and Podell A 1996 A high-efficiency singlesupply RFIC PHS linear power amplifier with low adjacent channel power leakage IEEE MTT-S Dig. pp 49–52 [55] Greenberg D R, Rivier M, Girard P, Bergeault E, Moniz J, Ahlgren D, Freeman G, Subbanna S, Jeng S J, Stein K, Nguyen-Ngoc D, Schonenberg K, Malinowski J, Colavito D, Harame D L and Meyerson B 1997 Large-signal performance of high-BVCEO graded epi-base SiGe HBTs at wireless frequencies IEEE IEDM Tech. Dig. pp 799–802 [56] Ahlgren D, Gilbert M, Greenberg D, Jeng S-J, Malinowski J, NguyenNgoc D, Schonenberg K, Stein K, Sunderland D, Groves R, Walter K, Hueckel G, Colavito D, Freeman G, Harame D and Meyerson B 1996 Manufacturability demonstration of an integrated SiGe HBT technology for the analogue and wireless marketplace IEEE IEDM Tech. Dig. pp 859–62 [57] Jansen B, Negus K and Lee D 1997 Silicon bipolar VCO family for 1.1 to 2.2 GHz with fully integrated tank and tuning circuit IEEE ISSCC Tech. Dig. pp 392–3 [58] Soyuer M, Jenkins K, Burghartz J and Hulvey M 1996 A 3 V 4 GHz nMOS voltage-controlled oscillator with integrated resonator IEEE ISSCC Tech. Dig. pp 394–5 [59] Leeson D 1996 A simple model of feedback oscillator noise spectrum Proc. IEEE 54 329–30 [60] Gruhle A, Schuppen A, Konig U, Erben U and Schumacher H 1995 Monolithic 26 GHz and 40 GHz VCOs with SiGe heterojunction bipolar transistor IEEE IEDM Tech. Dig. pp 725–8 [61] Cho D H, Ryum B R, Han T-H, Lee S M, Yeom K W and Shin S C 1997 Low power consumption and low phase noise 2.4 GHz VCO using SiGe HBT for WLL application Electron. Lett. 33 1089–90 [62] Soyuer M, Burghartz J, Ainspan H, Jenkins K, Xiao P, Shahani A, Dolan M and Harame D 1996 An 11 GHz 3 V SiGe voltage-controlled oscillator with integrated resonator IEEE BCTM Proc. pp 169–72 [63] Soyuer M, Ainspan H A, Burghartz J N, Plouchart J-O, Gaucher B P, Beukema T J, Canora F J, Pilmanis E and Oprysko M M 1998 A costeffective approach to a short-range, high-speed radio design in the U-NII 5.x GHz band Radio and Wireless Conf. (RAWCON’98) pp 133–6 [64] Burghartz J N, Soyuer M and Jenkins K A 1996 Microwave inductors and capacitors in standard multilevel interconnect silicon technology IEEE Trans. Microw. Theory Tech. 44 100–4 [65] Senapati B, Maiti C K and Chakrabarti N B 2000 Silicon heterostructure devices for RF wireless communication Proc. 13th IEEE VLSI Design Conf. pp 488–91 [66] Meyerson B S 2000 Silicon:germanium-based mixed-signal technology for optimization of wired and wireless telecommunications IBM J. Res. Dev. 44 391–407

Index

Acoustic scattering, 60 Activation energy, 34, 58 Alloy scattering, 39, 60–62, 112, 197, 214 Atmospheric pressure CVD, 48 Auger electron spectroscopy, 44, 274, 282 Auger recombination, 82, 117, 337 Avalanche breakdown, 99, 316 multiplication, 82, 317 photodiode, 316, 317 Band offset, 38, 51, 52, 54, 56, 58, 60, 90, 197, 203, 328 Bandgap narrowing, 59, 74, 115, 117, 118, 176 Barrier effect, 90, 95 Base design, 122 Base resistance, 4, 5, 7, 8, 13, 75, 82, 99, 119, 120, 125, 135, 136, 142, 144, 157, 185, 186 Base transit time, 8, 13, 14, 83, 84, 92, 100, 120, 129, 139, 140, 158, 165, 177 Base width modulation effect, 85 BICFET, 20 BiCMOS technology, 2, 9, 24, 120, 186, 188–190, 260, 364, 365, 368, 375, 377, 387, 388 Bipolar technology, 3, 5, 8, 9, 13,

18, 25, 153, 161, 166, 174, 370 Boltzmann statistics, 108 Boltzmann transport equation, 105, 108, 162 Breakdown voltage, 99 Buffer layer, xiv, 17, 18, 21, 40, 41, 50, 198, 201, 206, 213, 219 Bulk recombination, 117 Carrier freeze-out, 173 Chemical vapour deposition, 11, 42, 46, 48 CMOS, 2, 16, 18, 196, 204, 226, 228, 238, 245, 367, 370, 372, 375 Collector breakdown voltage, 130 design, 129 Transit time, 97, 139 Conduction band discontinuity, 32, 55, 77 Critical thickness, 13, 35–38, 64, 88, 197, 276, 314, 351 Cross section TEM, 41 Current crowding, 136 Current gain, 7, 10, 11, 13, 74, 77, 83, 87, 89, 94, 120, 158, 173–175, 365 Cut-off frequency, 3, 14, 84, 96, 110, 120, 123, 131, 140, 143, 157, 163, 177, 222, 364 397

398

Index

δ-doping, 252 Density of states, 80, 113, 116 Deposition techniques, 42, 274 Dielectric constant, 34, 112, 117, 159, 288, 289, 311 Direct bandgap, 311, 337 Drift–diffusion equation, 108 model, 105, 107, 158, 162, 163 simulation, 152, 336 Early voltage, 13, 85, 87, 143, 157, 158, 175 ECL gate delay, 9, 99, 133, 141– 144, 174 Effective mass, 34, 59, 61, 116 Electron gas, 213 Emitter design, 126 transit time, 84, 97, 139, 163 Energy balance equation, 216 model, 162, 163 simulation, 162 Epi-base technology, 152, 156, 174 Fermi–Dirac statistics, 104, 250 Field-effect transistor, xiv, 2, 6, 16, 263, 361, 380 Figure-of-merit, 87, 96, 98, 99, 109, 154, 316, 365, 380 Flicker noise, 385 Forward active mode, 75, 77 Freeze-out effect, 60, 62, 175 Gas source MBE, 46, 50 GeC, 314, 315, 334 Gummel method, 104, 108 Gummel–Poon model, 134 HCMOS, 17, 227, 231 Heavy doping effect, 59, 80, 82, 118

Heterojunction, 10, 13, 19, 35, 42, 50, 57, 58, 90, 96, 152, 180, 226, 232, 318 Heterojunction bipolar transistor, 2, 9, 73, 76, 77, 119, 120 HFET, xv, 17, 196, 198, 213, 227, 238–242, 245, 250, 252, 254, 257, 263, 265, 268 High electron mobility transistor, 17, 25, 220 High level injection effect, 94 Hole gas, 60, 62, 217 Hot carrier, 239, 242, 314 Hot electron, 7, 20 Hydrodynamic model, 105, 107, 216, 227 Ideality factor, 274, 276, 277, 288, 293, 296–298, 306 Impact ionization, 99, 183, 314, 317 Impurity scattering, 111, 113, 199 Inductors, 361, 363, 364, 368, 385–387 Infrared detector, 305, 325, 327, 329 Injection efficiency, 9, 10, 74, 75 Input impedance, 183, 196, 369 Inter-valley scattering, 198, 199 Interface state density, 241, 274, 291, 293, 300–302 Interface traps, 188 Intermodulation distortion, 380 Ionized impurity scattering, 60, 62, 198, 221, 230, 252 Ionizing radiation, 188, 336 Kirk effect, 94–96, 131 Lattice constant, 13, 32–35, 38, 49, 50, 54, 112, 197, 314 Lattice scattering, 198 Limited reaction processing, 47

Index Limited reaction processing CVD, 42, 47 Low-noise amplifier, 360, 363, 378–380 Low-temperature simulation, 152, 172, 175 Mason’s gain, 109 Maximum available gain, 109, 110 Maximum oscillation frequency, xiii, 8, 75, 96, 98, 143, 152, 220, 221 Metal–organic CVD, 10 Metallization, 11, 183, 272, 277, 363 Metastable layer, 38, 49, 51 Misfit dislocation, 35, 36, 38, 41, 51, 52, 94, 118, 314 Mobility, 59, 63, 112, 113, 198, 200 MODFET, xv, 17, 217, 219–222, 224, 374 Modulation-doped heterostructures, 63, 201, 203, 218 Molecular beam epitaxy, xiii, 10, 37, 42, 44 Moll–Ross current relation, 79 Monolithic microwave integrated circuit, 361, 362, 388 Monte Carlo method, 105 Monte Carlo simulation, 112, 199 MOS capacitor, 52, 57, 245 MOSFET, xiv, xv, 5, 7, 17, 18, 188, 190, 199, 206, 209, 212, 214, 238, 249, 251, 257, 260, 263–265, 374 MSM, 315, 316, 318, 320, 334, 345–348 Multiple quantum well, 58, 331 Neutral base recombination, 92 Noise figure, 185, 186, 365, 368, 369, 372, 378, 379

399

Numerical methods, 108 Ohmic contact, 272, 276, 278 Optical absorption, 58, 321–323, 325 Optical detectors, 325 Optoelectronic devices, 20 Optoelectronic integrated circuits, 310, 311, 315, 328 Out-diffusion effects, 90, 92, 120 Oxidation, 51, 241, 264, 276 p–i–n diode, 315, 318, 325, 332, 334, 335, 341, 343, 363 Parasitic channel, 202, 212, 213, 216, 228 Passive component, 25, 363, 386, 387 Phase noise, 23, 265, 365, 372, 384–386 Phonon scattering, 60, 61, 63, 111, 113, 199, 200, 213 Photoconductor, 315 Photodetector, 306, 310, 315, 317–320, 325, 328, 329, 332, 334, 336–338, 341, 345, 346, 350 Photodiodes, 315, 318, 320, 332, 334, 335, 342 Photoluminescence, 50, 57, 312 Phototransistor, 314 Plasma processing, 48, 241 Poly-SiGe, 259–261 Power added efficiency, 364, 365, 382, 383 Power amplifier, 12, 23, 24, 363, 367, 377, 381–384 Power delay product, 174, 228, 231 Propagation delay, 4, 99, 141, 142, 154 Quality factor, 385 Quantum device, 20, 239

400

Index

Quantum efficiency, 316–318, 321, 328, 329, 332, 334, 337, 338, 350 Quantum well, 17, 44, 218, 222, 239, 242, 245, 247, 255, 328 Radiation effect, 186 Radiation hardness, 190, 256 Raman spectroscopy, 51 Rapid thermal CVD, 47, 175 Remote plasma CVD, 48 Responsivity, 320, 325, 327, 331, 332, 338, 343, 345, 347, 348, 353 RF communication, xiii, 21, 359, 387 RFIC, 360, 367, 383 Rutherford backscattering spectrometry, 279 Scattering mechanisms, 105, 110, 198, 199 Scattering parameters, 109 Schottky barrier diode, 293, 317 Schottky barrier height, 293 Schottky gate FET, 204, 221, 222, 228 Secondary ion mass spectrometry, 41 Self-aligned technology, 8, 120, 142, 159, 221 Self-heating effect, 152, 167, 206, 371 Setback layer, 230 Shockley–Read–Hall recombination, 117, 337 Shot noise, 183, 185, 320 SiC, 1, 10, 241, 314, 327 SiGe, xiii, 1, 2, 9, 13–15, 35, 40, 42, 54, 59, 77, 115, 254, 263, 321, 325 SiGeC, xiv, 13, 15, 18, 32, 42, 49, 50, 56, 59, 241, 257, 260,

264, 277, 310, 314, 321, 327, 334 SiGeSnC, 314, 352 Silicides, 272, 274, 276–278 SIMOX, 242, 250, 255, 256, 329, 362, 371 Small-signal analysis, 109, 134, 139, 338 SOI, 7, 142, 152, 161, 166, 172, 241, 254, 328, 370–372, 392 Solid phase epitaxy, 49 Space-charge recombination, 36 Spacer layer, 92, 94, 100, 143, 173, 174, 221 SPICE parameter, 140, 142–144 Strain compensation, 60, 259 Strain relaxation, 36, 40, 258, 276, 277, 286, 375 Strained layer epitaxy, 33 Strained silicon, 36, 196 Superlattice, 311, 313, 328, 351 Surface passivation, 47 Surface recombination velocity, 188, 288 Surface scattering, 111, 242, 256 Technology comparison, 367 Tensile strain, 60, 209 Thermal noise, 183, 185 stability, 52, 257 Thermal oxidation, 51 Thermal stability, 51 Thermionic emission, 276, 288, 292, 297, 317, 320 Thermionic field emission, 288, 292, 297 Thin-film technology, 261, 274 Third-order intermodulation, 380 Transmission electron microscope, 285 Transport, 60, 105, 107, 217 Tunnelling, 94, 99, 290, 336

Index Tunnelling current, 8, 75, 173, 260 ULSI, 196, 241 Ultrahigh vacuum CVD, 13, 46 Valence band, 58, 330 discontinuity, 55, 77, 203, 216, 291 Valence band offset, 39, 49, 52, 53, 57, 58, 90, 94, 197, 203 Velocity overshoot, 162, 199, 216

401

Velocity saturation, 94, 100, 111, 199, 217 Vertical transistor, 181, 241, 263, 264 Very low pressure CVD, 48 Voltage controlled oscillator, 24, 366, 384, 386 Wireless communication, 363 X-ray diffraction, 51, 274