Measurement and Modeling of Silicon Heterostructure Devices

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Cressler / Measurement and Modeling of Silicon Heterostructure Devices

66927_C000 Final Proof page i 5.11.2007 12:14pm Compositor Name: JGanesan

Measurement and Modeling of Silicon Heterostructure Devices

Cressler / Measurement and Modeling of Silicon Heterostructure Devices 66927_C000 Final Proof

page ii

5.11.2007 12:14pm Compositor Name: JGanesan


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Edited by

John D. Cressler

Boca Raton London New York

CRC Press is an imprint of the Taylor & Francis Group, an informa business


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The material was previously published in Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits and Applications of SiGe and Si Strained-Layer Epitaxy © Taylor and Francis 2005.

CRC Press Taylor & Francis Group 6000 Broken Sound Parkway NW, Suite 300 Boca Raton, FL 33487-2742 © 2008 by Taylor & Francis Group, LLC CRC Press is an imprint of Taylor & Francis Group, an Informa business No claim to original U.S. Government works Printed in the United States of America on acid-free paper 10 9 8 7 6 5 4 3 2 1 International Standard Book Number-13: 978-1-4200-6692-0 (Hardcover) This book contains information obtained from authentic and highly regarded sources. Reprinted material is quoted with permission, and sources are indicated. A wide variety of references are listed. Reasonable efforts have been made to publish reliable data and information, but the author and the publisher cannot assume responsibility for the validity of all materials or for the consequences of their use. Except as permitted under U.S. Copyright Law, no part of this book may be reprinted, reproduced, transmitted, or utilized in any form by any electronic, mechanical, or other means, now known or hereafter invented, including photocopying, microfilming, and recording, or in any information storage or retrieval system, without written permission from the publishers. For permission to photocopy or use material electronically from this work, please access www.copyright.com (http:// www.copyright.com/) or contact the Copyright Clearance Center, Inc. (CCC) 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400. CCC is a not-for-profit organization that provides licenses and registration for a variety of users. For organizations that have been granted a photocopy license by the CCC, a separate system of payment has been arranged. Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used only for identification and explanation without intent to infringe. Library of Congress Cataloging-in-Publication Data Measurement and modeling of silicon heterostructure devices / editor, John D. Cressler. p. cm. Includes bibliographical references and index. ISBN 978-1-4200-6692-0 (alk. paper) 1. Bipolar transistors--Mathematical models. 2. Bipolar transistors. 3. Heterostructures. 4. Integrated circuits--Design and construction. I. Cressler, John D. TK7871.96.B55M33 2008 621.3815’2--dc22 Visit the Taylor & Francis Web site at http://www.taylorandfrancis.com and the CRC Press Web site at http://www.crcpress.com

2007030737

Cressler / Measurement and Modeling of Silicon Heterostructure Devices 66927_C000 Final Proof page v 5.11.2007 12:14pm Compositor Name: JGanesan

For the tireless efforts Of the many dedicated scientists and engineers Who helped create this field and make it a success. I tip my hat, and offer sincere thanks from all of us Who have benefitted from your keen insights and imaginings. And . . . For Maria: My beautiful wife, best friend, and soul mate for these 25 years. For Matthew John, Christina Elizabeth, and Joanna Marie: God’s awesome creations, and our precious gifts. May your journey of discovery never end.


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He Whose Heart Has Been Set On The Love Of Learning And True Wisdom And Has Exercised This Part of Himself, That Man Must Without Fail Have Thoughts That Are Immortal And Divine, If He Lay Hold On Truth. Plato ¯Œ ı Ø Ø łı ı `ª ªØÆ Ł ŒÆØ `º ŁØ Æ, ŒÆØ Ø `Œ Ł ªØÆ , ‚Æ Ø ¢ æÆ æ ø ºº Æ ŒØ ŒłØ `ŁÆ ŒÆØ ¨, ¯ æØŁ `ºŁØÆ. Pl atvna§

Cressler / Measurement and Modeling of Silicon Heterostructure Devices 66927_C000 Final Proof page vii 5.11.2007 12:14pm Compositor Name: JGanesan

Foreword

Progress in a given field of technology is both desired and expected to follow a stable and predictable long-term trajectory. Semilog plots of technology trends spanning decades in time and orders of magnitude in value abound. Perhaps the most famous exemplar of such a technology trajectory is the trend line associated with Moore’s law, where technology density has doubled every 12 to 18 months for several decades. One must not, however, be lulled into extrapolating such predictability to other aspects of semiconductor technology, such as device performance, or even to the long-term prospects for the continuance of device density scaling itself. New physical phenomena assert themselves as one approaches the limits of a physical system, as when device layers approach atomic dimensions, and thus, no extrapolation goes on indefinitely. Technology density and performance trends, though individually constant over many years, are the result of an enormously complex interaction between a series of decisions made as to the layout of a given device, the physics behind its operation, manufacturability considerations, and its extensibility into the future. This complexity poses a fundamental challenge to the device physics and engineering community, which must delve as far forward into the future as possible to understand when physical law precludes further progress down a given technology path. The early identification of such impending technological discontinuities, thus providing time to ameliorate their consequences, is in fact vital to the health of the semiconductor industry. Recently disrupted trends in CMOS microprocessor performance, where the ‘‘value’’ of processor-operating frequency was suddenly subordinated to that of integration, demonstrate the challenges remaining in accurately assessing the behavior of future technologies. However, current challenges faced in scaling deep submicron CMOS technology are far from unique in the history of semiconductors. Bipolar junction transistor (BJT) technology, dominant in high-end computing applications during the mid-1980s, was being aggressively scaled to provide the requisite performance for future systems. By the virtue of bipolar transistors being vertical devices rather than lateral (as CMOS is), the length scale of bipolar transistors is set by the ability to control layer thicknesses rather than lateral dimensions. This allowed the definition of critical device dimensions, such as base width, to values far below the limits of optical lithography of the day. Although great strides in device performance had been made by 1985, with unity gain cutoff frequencies (fT ) in the range 20–30 GHz seemingly feasible, device scaling was approaching limits at which new physical phenomena became significant. Highly scaled silicon BJTs, having base widths below 1000 A˚, demonstrated inordinately high reverse junction leakage. This was due to the onset of band-to-band tunneling between heavily doped emitter and base regions, rendering such devices unreliable. This and other observations presaged one of the seminal technology discontinuities of the past decade, silicon–germanium (SiGe) heterojunction bipolar transistor (HBT) technology being the direct consequence. Begun as a program to develop bipolar technology with performance capabilities well beyond those possible via the continued scaling of conventional Si BJTs, SiGe HBT technology has found a wealth of applications beyond the realm of computing. A revolution in bipolar fabrication methodology, moving vii


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from device definition by implantation to device deposition and definition by epitaxy, accompanied by the exploitation of bandgap tailoring, took silicon-based bipolar transistor performance to levels never anticipated. It is now common to find SiGe HBTs with performance figures in excess of 300 GHz for both fT and fmax , and circuits operable at frequencies in excess of 100 GHz. A key observation is that none of this progress occurred in a vacuum, other than perhaps in the field of materials deposition. The creation of a generation of transistor technology having tenfold improved performance would of itself have produced far less ultimate value in the absence of an adequate ecosystem to enable its effective creation and utilization. This text is meant to describe the eco-system that developed around SiGe technology as context for the extraordinary achievement its commercial rollout represented. Early SiGe materials, of excellent quality in the context of fundamental physical studies, proved near useless in later device endeavors, forcing dramatic improvements in layer control and quality to then enable further development. Rapid device progress that followed drove silicon-based technology (recall that SiGe technology is still a silicon-based derivative) to unanticipated performance levels, demanding the development of new characterization and device modeling techniques. As materials work was further proven SiGe applications expanded to leverage newly available structural and chemical control. Devices employing ever more sophisticated extensions of SiGe HBT bandgap tailoring have emerged, utilizing band offsets and the tailoring thereof to create SiGe-based HEMTs, tunneling devices, mobilityenhanced CMOS, optical detectors, and more to come. Progress in these diverse areas of device design is timely, as I have already noted the now asymptotic nature of performance gains to be had from continued classical device scaling, leading to a new industry focus on innovation rather than pure scaling. Devices now emerging in SiGe are not only to be valued for their performance, but rather their variety of functionality, where, for example, optically active components open up the prospect of the seamless integration of broadband communication functionality at the chip level. Access to high-performance SiGe technology has spurred a rich diversity of exploratory and commercial circuit applications, many elaborated in this text. Communications applications have been most significantly impacted from a commercial perspective, leveraging the ability of SiGe technologies to produce extremely high-performance circuits while using back level, and thus far less costly, fabricators than alternative materials such as InP, GaAs, or in some instances advanced CMOS. These achievements did not occur without tremendous effort on the part of many workers in the field, and the chapters in this volume represent examples of such contributions. In its transition from scientific curiosity to pervasive technology, SiGe-based device work has matured greatly, and I hope you find this text illuminating as to the path that maturation followed.

Bernard S. Meyerson IBM Systems and Technology Group


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Preface

While the idea of cleverly using silicon–germanium (SiGe) and silicon (Si) strained-layer epitaxy to practice bandgap engineering of semiconductor devices in the highly manufacturable Si material system is an old one, only in the past decade has this concept become a practical reality. The final success of creating novel Si heterostructure transistors with performance far superior to their Si-only homojunction cousins, while maintaining strict compatibility with the massive economy-of-scale of conventional Si integrated circuit manufacturing, proved challenging and represents the sustained efforts of literally thousands of physicists, electrical engineers, material scientists, chemists, and technicians across the world. In the electronics domain, the fruit of that global effort is SiGe heterojunction bipolar transistor (SiGe HBT) BiCMOS technology, and strained Si/SiGe CMOS technology, both of which are at present in commercial manufacturing worldwide and are rapidly finding a number of important circuit and system applications. As with any new integrated circuit technology, the industry is still actively exploring device performance and scaling limits (at present well above 300 GHz in frequency response, and rising), new circuit applications and potential new markets, as well as a host of novel device and structural innovations. This commercial success in the electronics arena is also spawning successful forays into the optoelectronics and even nanoelectronics fields. The Si heterostructure field is both exciting and dynamic in its scope. The implications of the Si heterostructure success story contained in this book are far-ranging and will be both lasting and influential in determining the future course of the electronics and optoelectronics infrastructure, fueling the miraculous communications explosion of the twenty-first century. While several excellent books on specific aspects of the Si heterostructures field currently exist (for example, on SiGe HBTs), this is the first reference book of its kind that ‘‘brings-it-all-together,’’ effectively presenting a comprehensive perspective by providing very broad topical coverage ranging from materials, to fabrication, to devices (HBT, FET, optoelectronic, and nanostructure), to CAD, to circuits, to applications. Each chapter is written by a leading international expert, ensuring adequate depth of coverage, upto-date research results, and a comprehensive list of seminal references. A novel aspect of this book is that it also contains ‘‘snap-shot’’ views of the industrial ‘‘state-of-the-art,’’ for both devices and circuits, and is designed to provide the reader with a useful basis of comparison for the current status and future course of the global Si heterostructure industry. This book is intended for a number of different audiences and venues. It should prove to be a useful resource as: 1. A hands-on reference for practicing engineers and scientists working on various aspects of Si heterostructure integrated circuit technology (both HBT, FET, and optoelectronic), including materials, fabrication, device physics, transistor optimization, measurement, compact modeling and device simulation, circuit design, and applications 2. A hands-on research resource for graduate students in electrical and computer engineering, physics, or materials science who require information on cutting-edge integrated circuit technologies ix


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3. A textbook for use in graduate-level instruction in this field 4. A reference for technical managers and even technical support/technical sales personnel in the semiconductor industry It is assumed that the reader has some modest background in semiconductor physics and semiconductor devices (at the advanced undergraduate level), but each chapter is self-contained in its treatment. In this age of extreme activity, in which we are all seriously pressed for time and overworked, my success in getting such a large collection of rather famous people to commit their precious time to my vision for this project was immensely satisfying. I am happy to say that my authors made the process quite painless, and I am extremely grateful for their help. The list of contributors to this book actually reads like a global ‘‘who’s who’’ of the silicon heterostructure field, and is impressive by any standard. I would like to formally thank each of my colleagues for their hard work and dedication to executing my vision of producing a lasting Si heterostructure ‘‘bible.’’ In order of appearance, the ‘‘gurus’’ of our field include: Robert A. Groves, IBM Microelectronics, USA David C. Sheridan, IBM Microelectronics, USA Jeffrey B. Johnson, IBM Microelectronics, USA Rajendran Krishnasamy, IBM Microelectronics, USA Michael Schro¨ter, University of California at San Diego, USA Slobodan Mijalkovic´, Delft University of Technology, The Netherlands Sue E. Strang, IBM Microelectronics, USA Raminderpal Singh, IBM Systems and Technology Group, USA Youri V. Tretiakov, RF Micro Devices, USA Qingqing Liang, Georgia Institute of Technology, USA Ramana M. Malladi, IBM Microelectronics, USA I would also like to thank my graduate students and post-docs, past and present, for their dedication and tireless work in this fascinating field. I rest on their shoulders. They include: David Richey, Alvin Joseph, Bill Ansley, Juan Roldań, Stacey Salmon, Lakshmi Vempati, Jeff Babcock, Suraj Mathew, Kartik Jayanaraynan, Greg Bradford, Usha Gogineni, Gaurab Banerjee, Shiming Zhang, Krish Shivaram, Dave Sheridan, Gang Zhang, Ying Li, Zhenrong Jin, Qingqing Liang, Ram Krithivasan, Yun Luo, Tianbing Chen, Enhai Zhao, Yuan Lu, Chendong Zhu, Jon Comeau, Jarle Johansen, Joel Andrews, Lance Kuo, Xiangtao Li, Bhaskar Banerjee, Curtis Grens, Akil Sutton, Adnan Ahmed, Becca Haugerud, Mustayeen Nayeem, Mustansir Pratapgarhwala, Guofu Niu, Emery Chen, Jongsoo Lee, and Gnana Prakash. Finally, I am grateful to Tai Soda at Taylor & Francis for talking me into this project, and supporting me along the way. I would also like to thank the production team at Taylor & Francis for their able assistance (and patience!), especially Jessica Vakili. The many nuances of the Si heterostructure field make for some fascinating subject matter, but this is no mere academic pursuit. In the grand scheme of things, the Si heterostructure industry is already reshaping the global communications infrastructure, which is in turn dramatically reshaping the way life on planet Earth will transpire in the twenty-first century and beyond. The world would do well to pay attention. It has been immensely satisfying to see both the dream of Si/SiGe bandgap engineering, and this book, come to fruition. I hope our efforts please you. Enjoy!

John D. Cressler Editor


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Editor

John D. Cressler received a B.S. in physics from the Georgia Institute of Technology (Georgia Tech), Atlanta, Georgia, in 1984, and an M.S. and Ph.D. in applied physics from Columbia University, New York, in 1987 and 1990. From 1984 to 1992 he was on the research staff at the IBM Thomas J. Watson Research Center in Yorktown Heights, New York, working on high-speed Si and SiGe bipolar devices and technology. In 1992 he left IBM Research to join the faculty at Auburn University, Auburn, Alabama, where he served until 2002. When he left Auburn University, he was Philpott–Westpoint Stevens Distinguished Professor of Electrical and Computer Engineering and director of the Alabama Microelectronics Science and Technology Center. In 2002, Dr. Cressler joined the faculty at Georgia Tech, where he is currently Ken Byers Professor of Electrical and Computer Engineering. His research interests include SiGe devices and technology; Si-based RF/microwave/millimeter-wave mixed-signal devices and circuits; radiation effects; device-circuit interactions; noise and linearity; reliability physics; extreme environment electronics, 2-D/3-D device-level simulation; and compact circuit modeling. He has published more than 350 technical papers related to his research, and is author of the books Silicon-Germanium Heterojunction Bipolar Transistors, Artech House, 2003 (with Guofu Niu), and Reinventing Teenagers: The Gentle Art of Instilling Character in Our Young People, Xlibris, 2004 (a slightly different genre!). Dr. Cressler was Associate Editor of the IEEE Journal of Solid-State Circuits (1998–2001), Guest Editor of the IEEE Transactions on Nuclear Science (2003–2006), and Associate Editor of the IEEE Transactions on Electron Devices (2005–present). He served on the technical program committees of the IEEE International Solid-State Circuits Conference (1992–1998, 1999–2001), the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (1995–1999, 2005–present), the IEEE International Electron Devices Meeting (1996–1997), and the IEEE Nuclear and Space Radiation Effects Conference (1999–2000, 2002– 2007). He currently serves on the executive steering committee for the IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, as international program advisor for the IEEE European Workshop on Low-Temperature Electronics, on the technical program committee for the IEEE International SiGe Technology and Device Meeting, and as subcommittee chair of the 2004 Electrochemical Society Symposium of SiGe: Materials, Processing, and Devices. He was the Technical Program Chair of the 1998 IEEE International Solid-State Circuits Conference, the Conference Co-Chair of the 2004 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, and the Technical Program Chair of the 2007 IEEE Nuclear and Space Radiation Effects Conference. Dr. Cressler was appointed an IEEE Electron Device Society Distinguished Lecturer in 1994, an IEEE Nuclear and Plasma Sciences Distinguished Lecturer in 2006, and was awarded the 1994 Office of Naval Research Young Investigator Award for his SiGe research program. He received the 1996 C. Holmes xi

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MacDonald National Outstanding Teacher Award by Eta Kappa Nu, the 1996 Auburn University Alumni Engineering Council Research Award, the 1998 Auburn University Birdsong Merit Teaching Award, the 1999 Auburn University Alumni Undergraduate Teaching Excellence Award, an IEEE Third Millennium Medal in 2000, and the 2007 Georgia Tech Outstanding Faculty Leadership in the Development of Graduate Students Award. He is an IEEE Fellow. On a more personal note, John’s hobbies include hiking, gardening, bonsai, all things Italian, collecting (and drinking!) fine wines, cooking, history, and carving walking sticks, not necessarily in that order. He considers teaching to be his vocation. John has been married to Maria, his best friend and soul-mate, for 25 years, and is the proud father of three budding scholars: Matt, Christina, and Jo-Jo. Dr. Cressler can be reached at School of Electrical and Computer Engineering, 777 Atlantic Drive, N.W., Georgia Institute of Technology, Atlanta, GA 30332-0250 U.S.A. or [email protected] http://users.ece.gatech.edu/cressler/


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Contents

1 The Big Picture ............................................................................................................................ 1-1 John D. Cressler 2 A Brief History of the Field ........................................................................................................ 2-1 John D. Cressler 3 Overview: Measurement and Modeling ..................................................................................... 3-1 John D. Cressler 4 Best-Practice AC Measurement Techniques............................................................................... 4-1 Robert A. Groves 5 Industrial Application of TCAD for SiGe Development .......................................................... 5-1 David C. Sheridan, Jeffrey B. Johnson, and Rajendran Krishnasamy 6 Compact Modeling of SiGe HBTs: HICUM ............................................................................... 6-1 Michael Schro¨ter 7 Compact Modeling of SiGe HBTs: Mextram ............................................................................. 7-1 Slobodan Mijalkovic´ 8 CAD Tools and Design Kits ........................................................................................................ 8-1 Sue E. Strang 9 Parasitic Modeling and Noise Mitigation Approaches in Silicon Germanium RF Designs .... 9-1 Raminderpal Singh 10 Transmission Lines on Si........................................................................................................... 10-1 Youri V. Tretiakov 11 Improved De-Embedding Techniques ...................................................................................... 11-1 Qingqing Liang A.1 Properties of Silicon and Germanium ................................................................................... A.1-1 John D. Cressler A.2 The Generalized Moll–Ross Relations .................................................................................... A.2-1 John D. Cressler A.3 Integral Charge-Control Relations ......................................................................................... A.3-1 Michael Schro¨ter A.4 Sample SiGe HBT Compact Model Parameters..................................................................... A.4-1 Ramana M. Malladi Index ....................................................................................................................................................... I-1

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1 The Big Picture 1.1 1.2

John D. Cressler Georgia Institute of Technology

1.1

1.3 1.4 1.5

The Communications Revolution...................................... Bandgap Engineering in the Silicon Material System ................................................................... Terminology and Definitions ............................................. The Application Space ........................................................ Performance Limits and Future Directions ......................

1-1 1-3 1-4 1-5 1-9

The Communications Revolution

We are at a unique juncture in the history of humankind, a juncture that amazingly we engineers and scientists have dreamed up and essentially created on our own. This pivotal event can be aptly termed the ‘‘Communications Revolution,’’ and the twenty-first century, our century, will be the era of human history in which this revolution plays itself out. This communications revolution can be functionally defined and characterized by the pervasive acquisition, manipulation, storage, transformation, and transmission of ‘‘information’’ on a global scale. This information, or more generally, knowledge, in its infinitely varied forms and levels of complexity, is gathered from our analog sensory world, transformed in very clever ways into logical ‘‘1’’s and ‘‘0’’s for ease of manipulation, storage, and transmission, and subsequently regenerated into analog sensory output for our use and appreciation. In 2005, this planetary communication of information is occurring at a truly mind-numbing rate, estimates of which are on the order of 80 Tera-bits/sec (1012) of data transfer across the globe in 2005 solely in wired and wireless voice and data transmission, 24 hours a day, 7 days a week, and growing exponentially. The world is quite literally abuzz with information flow—communication.* It is for the birth of the Communications Revolution that we humans likely will be remembered for 1000 years hence. Given that this revolution is happening during the working careers of most of us, I find it a wonderful time to be alive, a fact of which I remind my students often. Here is my point. No matter how one slices it, at the most fundamental level, it is semiconductor devices that are powering this communications revolution. Skeptical? Imagine for a moment that one could flip a switch and instantly remove all of the integrated circuits (ICs) from planet Earth. A moment’s reflection will convince you that there is not a single field of human endeavor that would not come to a grinding halt, be it commerce, or agriculture, or education, or medicine, or entertainment. Life as we in the first world know it in 2005 would simply cease to exist. And yet, remarkably, the same result would not have been true 50 years ago; even 20 years ago. Given the fact that we humans have been on planet Earth in our present form for at least 1 million years, and within communities

* I have often joked with my students that it would be truly entertaining if the human retina was sensitive to longer wavelengths of electromagnetic radiation, such that we could ‘‘see’’ all the wireless communications signals constantly bathing the planet (say, in greens and blues!). It might change our feelings regarding our ubiquitous cell phones!

1-1


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having entrenched cultural traditions for at least 15,000 years, this is truly a remarkable fact of history. A unique juncture indeed. Okay, hold on tight. It is an easy case to make that the semiconductor silicon (Si) has single-handedly enabled this communications revolution.* I have previously extolled at length the remarkable virtues of this rather unglamorous looking silver-grey element [1], and I will not repeat that discussion here, but suffice it to say that Si represents an extremely unique material system that has, almost on its own, enabled the conception and evolving execution of this communications revolution. The most compelling attribute, by far, of Si lies in the economy-of-scale it facilitates, culminating in the modern IC fabrication facility, effectively enabling the production of gazillions of low-cost, very highly integrated, remarkably powerful ICs, each containing millions of transistors; ICs that can then be affordably placed into widgets of remarkably varied form and function.y So what does this have to do with the book you hold in your hands? To feed the emerging infrastructure required to support this communications revolution, IC designers must work tirelessly to support increasingly higher data rates, at increasingly higher carrier frequencies, all in the design space of decreasing form factor, exponentially increasing functionality, and at ever-decreasing cost. And by the way, the world is going portable and wireless, using the same old wimpy batteries. Clearly, satisfying the near-insatiable appetite of the requisite communications infrastructure is no small task. Think of it as job security! For long-term success, this quest for more powerful ICs must be conducted within the confines of conventional Si IC fabrication, so that the massive economy-of-scale of the global Si IC industry can be brought to bear. Therein lies the fundamental motivation for the field of Si heterostructures, and thus this book. Can one use clever nanoscale engineering techniques to custom-tailor the energy bandgap of fairly conventional Si-based transistors to: (a) improve their performance dramatically and thereby ease the circuit and system design constraints facing IC designers, while (b) performing this feat without throwing away all the compelling economy-of-scale virtues of Si manufacturing? The answer to this important question is a resounding ‘‘YES!’’ That said, getting there took time, vision, as well as dedication and hard work of literally thousands of scientists and engineers across the globe. In the electronics domain, the fruit of that global effort is silicon–germanium heterojunction bipolar transistor (SiGe HBT) bipolar complementary metal oxide semiconductor (BiCMOS) technology, and is in commercial manufacturing worldwide and is rapidly finding a number of important circuit and system applications. In 2004, the SiGe ICs, by themselves, are expected to generate US$1 billion in revenue globally, with perhaps US$30 billion in downstream products. This US$1 billion figure is projected to rise to US$2.09 billion by 2006 [2], representing a growth rate of roughly 42% per year, a remarkable figure by any economic standard. The biggest single market driver remains the cellular industry, but applications in optical networking, hard disk drives for storage, and automotive collisionavoidance radar systems are expected to represent future high growth areas for SiGe. And yet, in the beginning of 1987, only 18 years ago, there was no such thing as a SiGe HBT. It had not been demonstrated as a viable concept. An amazing fact. In parallel with the highly successful development of SiGe HBT technology, a wide class of ‘‘transport enhanced’’ field effect transistor topologies (e.g., strained Si CMOS) have been developed as a means to boost the performance of the CMOS side of Si IC coin, and such technologies have also recently begun *The lone exception to this bold claim lies in the generation and detection of coherent light, which requires direct bandgap III–V semiconductor devices (e.g., GaAs of InP), and without which long-haul fiber communications systems would not be viable, at least for the moment. y Consider: it has been estimated that in 2005 there are roughly 20,000,000,000,000,000,000 (2 1019) transistors on planet Earth. While this sounds like a large number, let us compare it to some other large numbers: (1) the universe is roughly 4.2 1017sec old (13.7 billion years), (2) there are about 1 1021 stars in the universe, and (3) the universe is about 4 1023 miles across (15 billion light-years)! Given the fact that all 2 1020 of these transistors have been produced since December 23, 1947 (following the invention of the point-contact transistor by Bardeen, Brattain, and Shockley), this is a truly remarkable feat of human ingenuity.




The Big Picture

1-3

to enter the marketplace as enhancements to conventional core CMOS technologies. The commercial success enjoyed in the electronics arena has very naturally also spawned successful forays into the optoelectronics and even nanoelectronics fields, with potential for a host of important downstream applications. The Si heterostructure field is both exciting and dynamic in its scope. The implications of the Si heterostructure success story contained in this book are far-ranging and will be both lasting and influential in determining the future course of the electronics and optoelectronics infrastructure, fueling the miraculous communications explosion of our twenty-first century. The many nuances of the Si heterostructure field make for some fascinating subject matter, but this is no mere academic pursuit. As I have argued, in the grand scheme of things, the Si heterostructure industry is already reshaping the global communications infrastructure, which is in turn dramatically reshaping the way life of planet Earth will transpire in the twenty-first century and beyond. The world would do well to pay close attention.

1.2

Bandgap Engineering in the Silicon Material System

As wonderful as Si is from a fabrication viewpoint, from a device or circuit designer’s perspective, it is hardly the ideal semiconductor. The carrier mobility for both electrons and holes in Si is comparatively small compared to their III–V cousins, and the maximum velocity that these carriers can attain under high electric fields is limited to about 1 107 cm/sec under normal conditions, relatively ‘‘slow.’’ Since the speed of a transistor ultimately depends on how fast the carriers can be transported through the device under sustainable operating voltages, Si can thus be regarded as a somewhat ‘‘meager’’ semiconductor. In addition, because Si is an indirect gap semiconductor, light emission is fairly inefficient, making active optical devices such as diode lasers impractical (at least for the present). Many of the III–V compound semiconductors (e.g., GaAs or InP), on the other hand, enjoy far higher mobilities and saturation velocities, and because of their direct gap nature, generally make efficient optical generation and detection devices. In addition, III–V devices, by virtue of the way they are grown, can be compositionally altered for a specific need or application (e.g., to tune the light output of a diode laser to a specific wavelength). This atomic-level custom tailoring of a semiconductor is called bandgap engineering, and yields a large performance advantage for III–V technologies over Si [3]. Unfortunately, these benefits commonly associated with III–V semiconductors pale in comparison to the practical deficiencies associated with making highly integrated, low-cost ICs from these materials. There is no robust thermally grown oxide for GaAs or InP, for instance, and wafers are smaller with much higher defect densities, are more prone to breakage, and are poorer heat conductors (the list could go on). These deficiencies translate into generally lower levels of integration, more difficult fabrication, lower yield, and ultimately higher cost. In truth, of course, III–V materials such as GaAs and InP fill important niche markets today (e.g., GaAs metal semiconductor field effect transistor (MESFETs) and HBTs for cell phone power amplifiers, AlGaAs- or InP-based lasers, efficient long wavelength photodetectors, etc.), and will for the foreseeable future, but III–V semiconductor technologies will never become mainstream in the infrastructure of the communications revolution if Si-based technologies can do the job. While Si ICs are well suited to high-transistor-count, high-volume microprocessors and memory applications, RF, microwave, and even millimeter-wave (mm-wave) electronic circuit applications, which by definition operate at significantly higher frequencies, generally place much more restrictive performance demands on the transistor building blocks. In this regime, the poorer intrinsic speed of Si devices becomes problematic. That is, even if Si ICs are cheap, they must deliver the required device and circuit performance to produce a competitive system at a given frequency. If not, the higher-priced but faster III–V technologies will dominate (as they indeed have until very recently in the RF and microwave markets). The fundamental question then becomes simple and eminently practical: is it possible to improve the performance of Si transistors enough to be competitive with III–V devices for high-performance applications, while preserving the enormous yield, cost, and manufacturing advantages associated with conventional Si fabrication? The answer is clearly ‘‘yes,’’ and this book addresses the many nuances


1-4




associated with using SiGe and Si-strained layer epitaxy to practice bandgap engineering in the Si material system, a process culminating in, among other things, the SiGe HBT and strained Si CMOS, as well as a variety of other interesting electronic and optoelectronic devices built from these materials. This totality can be termed the ‘‘Si heterostructures’’ field.

1.3

Terminology and Definitions

A few notes on modern usage and pronunciation in this field are in order (really!). It is technically correct to refer to silicon–germanium alloys according to their chemical composition, Si1xGex , where x is the Ge mole fraction. Following standard usage, such alloys are generally referred to as ‘‘SiGe’’ alloys. Note, however, that it is common in the material science community to also refer to such materials as ‘‘Ge:Si’’ alloys. A SiGe film that is carbon doped (e.g., less than 0.20% C) in an attempt to suppress subsequent boron out-diffusion (e.g., in HBTs) is properly referred to as a SiGe:C alloy, or simply SiGeC (pronounced ‘‘silicon germanium carbon,’’ not ‘‘silicon germanium carbide’’). This class of SiGe alloys should be viewed as optimized SiGe alloys, and are distinct from SiGe films with a much higher C content (e.g., 2% to 3% C) that might be used, for instance, to lattice-match SiGeC alloys to Si. Believe it or not, this field also has its own set of slang pronunciations. The colloquial usage of the pronunciation \’sig-ee\ to refer to ‘‘silicon–germanium’’ (begun at IBM in the late 1990s) has come into vogue (heck, it may make it to the dictionary soon!), and has even entered the mainstream IC engineers’s slang; pervasively.* In the electronics domain, it is important to be able to distinguish between the various SiGe technologies as they evolve, both for CMOS (strained Si) and bipolar (SiGe HBT). Relevant questions in this context include: Is company X’s SiGe technology more advanced than company Y’s SiGe technology? For physical as well as historical reasons, one almost universally defines CMOS technology (Si, strained Si, or SiGe), a lateral transport device, by the drawn lithographic gate length (the CMOS technology ‘‘node’’), regardless of the resultant intrinsic device performance. Thus, a ‘‘90-nm’’ CMOS node has a drawn gate length of roughly 90 nm. For bipolar devices (i.e., the SiGe HBT), however, this is not so straightforward, since it is a vertical transport device whose speed is not nearly as closely linked to lithographic dimensions. In the case of the SiGe HBT it is useful to distinguish between different technology generations according to their resultant ac performance (e.g., peak common-emitter, unity gain cutoff frequency (fT), which is (a) easily measured and unambiguously compared technology to technology, and yet is (b) a very strong function of the transistor vertical doping and Ge profile and hence nicely reflects the degree of sophistication in device structural design, overall thermal cycle, epi growth, etc.) [1]. The peak fT generally nicely reflects the ‘‘aggressiveness,’’ if you will, of the transistor scaling which has been applied to a given SiGe technology. A higher level of comparative sophistication can be attained by also invoking the maximum oscillation frequency ( fmax), a parameter which is well correlated to both intrinsic profile and device parasitics, and hence a bit higher on the ladder of device performance metrics, and thus more representative of actual large-scale circuit performance. The difficulty in this case is that fmax is far more ambiguous than fT , in the sense that it can be inferred from various gain definitions (e.g., U vs. MAG), and in practice power gain data are often far less ideal in its behavior over frequency, more sensitive to accurate deembedding, and ripe with extraction ‘‘issues.’’ We thus term a SiGe technology having a SiGe HBT with a peak fT in the range of 50 GHz as ‘‘first generation;’’ that with a peak fT in the range of 100 GHz as ‘‘second generation;’’ that with a peak fT in the range of 200 GHz as ‘‘third generation;’’ and that with a peak fT in the range of 300 GHz as ‘‘fourth generation.’’ These are loose definitions to be sure, but nonetheless useful for comparison purposes.

*I remain a stalwart holdout against this snowballing trend and stubbornly cling to the longer but far more satisfying ‘‘silicon–germanium.’’




1-5

The Big Picture

SiGe HBT BiCMOS technology evolution by generation

CMOS gate length

90 nm

3rd

0.12 µm

0.18 µm

0.25 µm

4th

2nd

1st 50 GHz

100 GHz

200 GHz

300 GHz

SiGe HBT peak cutoff frequency FIGURE 1.1 Evolution of SiGe HBT BiCMOS technology generations, as measured by the peak cutoff frequency of the SiGe HBT, and the CMOS gate length.

A complicating factor in SiGe technology terminology results from the fact that most, if not all, commercial SiGe HBT technologies today also contain standard Si CMOS devices (i.e., SiGe HBT BiCMOS technology) to realize high levels of integration and functionality on a single die (e.g., singlechip radios complete with RF front-end, data converters, and DSP). One can then speak of a given generation of SiGe HBT BiCMOS technology as the most appropriate intersection of both the SiGe HBT peak fT and the CMOS technology node (Figure 1.1). For example, for several commercially important SiGe HBT technologies available via foundry services, we have: . . . . . .

IBM SiGe 5HP—50 GHz peak fT SiGe HBT þ 0.35 mm Si CMOS (first generation) IBM SiGe 7HP—120 GHz peak fT SiGe HBT þ 0.18 mm Si CMOS (second generation) IBM SiGe 8HP—200 GHz peak fT SiGe HBT þ 0.13 mm Si CMOS (third generation) Jazz SiGe 60—60 GHz peak fT SiGe HBT þ 0.35 mm Si CMOS (first generation) Jazz SiGe 120—150 GHz peak fT SiGe HBT þ 0.18 mm Si CMOS (second generation) IHP SiGe SGC25B—120 GHz peak fT SiGe HBT þ 0.25 mm Si CMOS (second generation)

All SiGe HBT BiCMOS technologies can thus be roughly classified in this manner. It should also be understood that multiple transistor design points typically exist in such BiCMOS technologies (multiple breakdown voltages for the SiGe HBT and multiple threshold or breakdown voltages for the CMOS), and hence the reference to a given technology generation implicitly refers to the most aggressively scaled device within that specific technology platform.

1.4

The Application Space

It goes without saying in our field of semiconductor IC technology that no matter how clever or cool a new idea appears at first glance, its long-term impact will ultimately be judged by its marketplace ‘‘legs’’ (sad, but true). That is, was the idea good for a few journal papers and an award or two, or did someone actually build something and sell some useful derivative products from it? The sad reality is that the semiconductor field (and we are by no means exceptional) is rife with examples of cool new devices that


1-6




never made it past the pages of the IEDM digest! The ultimate test, then, is one of stamina. And sweat. Did the idea make it out of the research laboratory and into the hands of the manufacturing lines? Did it pass the qualification-checkered flag, have design kits built around it, and get delivered to real circuit designers who built ICs, fabricated them, and tested them? Ultimately, were the derivative ICs inserted into real systems—widgets—to garner leverage in this or that system metric, and hence make the products more appealing in the marketplace? Given the extremely wide scope of the semiconductor infrastructure fueling the communications revolution, and the sheer volume of widget possibilities, electronic to photonic to optoelectronic, it is useful here to briefly explore the intended application space of Si heterostructure technologies as we peer out into the future. Clearly I possess no crystal ball, but nevertheless some interesting and likely lasting themes are beginning to emerge from the fog. SiGe HBT BiCMOS is the obvious ground-breaker of the Si heterostructures application space in terms of moving the ideas of our field into viable products for the marketplace. The field is young, but the signs are very encouraging. As can be seen in Figure 1.2, there are at present count 25 þ SiGe HBT industrial fabrication facilities on line in 2005 around the world, and growing steadily. This trend points to an obvious recognition that SiGe technology will play an important role in the emerging electronics infrastructure of the twenty-first century. Indeed, as I often point out, the fact that virtually every major player in the communications electronics field either: (a) has SiGe up and running in-house, or (b) is using someone else’s SiGe fab as foundry for their designers, is a remarkable fact, and very encouraging in the grand scheme of things. As indicated above, projections put SiGe ICs at a US$2.0 billion level by 2006, small by percentage perhaps compared to the near trillion dollar global electronics market, but growing rapidly. The intended application target? That obviously depends on the company, but the simple answer is, gulp, a little bit of everything! As depicted in Figure 1.3 and Figure 1.4, the global communications landscape is exceptionally diverse, ranging from low-frequency wireless (2.4 GHz cellular) to the fastest high-speed wireline systems (10 and 40 Gbit/sec synchronous optical network (SONET)). Core CMOS technologies are increasingly being pushed into the lower frequency wireless space, but the compelling drive to higher carrier frequencies over time will increasingly favor SiGe technologies. At present, SiGe ICs are making inroads into: the cellular industry for handsets [global system for mobile communications—GSM, code division multiple access (CDMA), wideband CDMA (W-CDMA), etc.], even for power amplifiers; various wireless local area networks (WLAN) building blocks, from components to fully integrated systems ranging from 2.4 to 60 GHz and up; ultrawide band (UWB) components; global positioning systems (GPS); wireless base stations; a variety of wireline networking products, from 2.5 to 40 Gbit/sec (and higher); data converters (D/A and A/D); highspeed memories; a variety of instrumentation electronics; read-channel memory storage products; core analog functions (op amps, etc.); high-speed digital circuits of various flavors; radiation detector

Industrial fabrication facilities

25 20 15 10 5 0 1993

FIGURE 1.2

SiGe HBT BiCMOS Strained–Si CMOS

1995

1997

1999 Year

2001

2003

Number of industrial SiGe and strained Si fabrication facilities.

2005




1-7

The Big Picture

FIGURE 1.3 The global communications landscape, broken down by the various communications standards, and spanning the range of: wireless to wireline; fixed to mobile; copper to fiber; low data rate to broadband; and local area to wide area networks. WAN is wide area network, MAN is metropolitan area network, the so-called ‘‘last mile’’ access network, LAN is local area network, and PAN is personal area network, the emerging in-home network. (Used with the permission of Kyutae Lim.) Some application bands for SiGe ICs Defense Radar

Radar Navigation

GPS

Radar Automotive Collision avoidance

Polling

Cellular / PCS / Satellite / UWB

Communications WLAN

Bands: L 1

2

S

C

3

5

ISM W

Ka

X

Ku

10

20 30

50

100

Frequency (GHz)

FIGURE 1.4

Some application frequency bands for SiGe integrated circuits.

electronics; radar systems (from 3 to 77 GHz and up); a variety space-based electronics components; and various niche extreme environment components (e.g., cryogenic (77 K) hybrid superconductor–semiconductor systems). The list is long and exceptionally varied—this is encouraging. Clearly, however, some of these components of ‘‘everything’’ are more important than others, and this will take time to shake out. The strength of the BiCMOS twist to SiGe ICs cannot be overemphasized. Having both the high-speed SiGe HBT together on-chip with aggressively scaled CMOS allows one great flexibility in system design, the depths of which is just beginning to be plumbed. While debates still rage with respect to the most cost-effective partitioning at the chip and package level (system-on-a-chip versus system-in-a-package,


1-8




etc.), clearly increased integration is viewed as a good thing in most camps (it is just a question of how much), and SiGe HBT BiCMOS is well positioned to address such needs across a broad market sector. The envisioned high-growth areas for SiGe ICs over the new few years include: the cellular industry, optical networking, disk drives, and radar systems. In addition, potential high-payoff market areas span the emerging mm-wave space (e.g., the 60 GHz ISM band WLAN) for short range, but very high data rate (Gbit/sec) wireless systems. A SiGe 60 GHz single-chip/package transceiver (see Figure 1.5 for IBM’s vision of such a beast) could prove to be the ‘‘killer app’’ for the emerging broadband multimedia market. Laughable? No. The building blocks for such systems have already been demonstrated using third-generation SiGe technology [4], and fully integrated transceivers are under development. The rest of the potential market opportunities within the Si heterostructures field can be leveraged by successes in the SiGe IC field, both directly and indirectly. On the strained Si CMOS front, there are existent proofs now that strained Si is likely to become a mainstream component of conventional CMOS scaling at the 90-nm node and beyond (witness the early success of Intel’s 90-nm logic technology built around uniaxially strained Si CMOS; other companies are close behind). Strained Si would seem to represent yet another clever technology twist that CMOS device technologists are pulling from their bag of tricks to keep the industry on a Moore’s law growth path. This was not an obvious development (to me anyway) even a couple of years back. A wide variety of ‘‘transport enhanced’’ Si-heterostructure-based FETs have been demonstrated (SiGe-channel FETs, Si-based high electron mobility transistors (HEMTs), as well as both uniaxially and biaxially strained FETs, etc). Most of these devices, however, require complex substrate engineering that would have seemed to preclude giga-scale integration level needs for microprocessor-level integration. Apparently not so. The notion of using Si heterostructures (either

Radiation

Vision of a 60 GHz SiGe wireless transceiver Package mold

Wirebond pad

Wirebond C4-Balls

Tx/Rx flip-Antenna

Mix

Filter structure

Q-signal

90 VCO I-signal

Underfill

Su

bs

tra

te

Mix Mix Q-signal LNA

I/Q

90 VCO I-signal

PLL

Mix

I/Q

QFN-package Package pin

FIGURE 1.5 Pfeiffer.)

Vision for a single-chip SiGe mm-wave transceiver system. (Used with the permission of Ullrich




1-9

The Big Picture

uniaxial or biaxial strain or both) to boost conventional CMOS performance appears to be an appealing path for the future, a natural merging point I suspect for SiGe strained layers found in SiGe HBT BiCMOS (which to date contains only conventional Si CMOS) and strained Si CMOS. From the optoelectronics camp, things are clearly far less evolved, but no less interesting. A number of functional optoelectronic devices have been demonstrated in research laboratories. Near-term successes in the short wavelength detector arena and light emitting diodes (LEDs) are beginning to be realized. The achievement of successful coherent light emission in the Si heterostructure system (e.g., via quantum cascade techniques perhaps) would appear to be the ‘‘killer app’’ in this arena, and research in this area is in progress. More work is needed.

1.5

Performance Limits and Future Directions

We begin with device performance limits. Just how fast will SiGe HBTs be 5 years from now? Transistorlevel performance in SiGe HBTs continues to rise at a truly dizzying pace, and each major conference seems to bear witness to a new performance record (Figure 1.6). Both first- and second-generation SiGe HBT BiCMOS technology is widely available in 2005 (who would have thought even 3 years ago that fully integrated 100þ GHz Si-based devices would be ‘‘routine’’ on 200 mm wafers?), and even at the 200 GHz (third-generation) performance level, six companies (at last count) have achieved initial technology demonstrations, including IBM (Chapter 7), Jazz (Chapter 8), IHP (Chapter 11), ST Microelectronics (Chapter 12), Hitachi (Chapter 9), and Infineon (Chapter 10). (See Fabrication of SiGe HBT BiCMOS Technology for these chapters.) Several are now either available in manufacturing, or are very close (e.g., [5]). At press time, the most impressive new stake-in-the-ground is the report (June 2004) of the newly optimized ‘‘SiGe 9T’’ technology, which simultaneously achieves 302 GHz peak fT and 306 GHz peak fmax, a clear record for any Si-based transistor, from IBM (Figure 1.7) [6]. This level of ac performance was achieved at a BVCEO of 1.6 V, a BVCBO of 5.5 V, and a current gain of 660. Noise measurements on these devices yielded NFmin/Gassoc of 0.45 dB/14 dB and 1.4 dB/8 dB at 10 and 25 GHz, respectively. Measurements of earlier (unoptimized) fourth-generation IBM SiGe HBTs have yielded record values of 375 GHz peak fT [7] at 300 K and above 500 GHz peak fT at 85 K. Simulations suggest that THz-level (1000 GHz) intrinsic transistor performance is not a laughable proposition in SiGe HBTs (Chapter 16, see Silicon Heterostructure Devices). This fact still amazes even me, the eternal optimist of SiGe performance! I, for one, firmly believe that we will see SiGe HBTs above-500 GHz peak 400 4th

Cutoff frequency (GHz)

350 300 250 3rd 200 150

2nd

100 50 0 0.1

1st

1.0 10 Collector current density (mA/mm2)

100

FIGURE 1.6 Measured cutoff frequency as a function of bias current density for four different SiGe HBT technology generations.


1-10

page 10 17.10.2007

7:54am Compositor Name: JGanesan


400 f T + f max = 400 GHz

Peak f max (GHz)

350

600 GHz f T = f max

300 250 200 GHz

200 150 100

SiGe+SiGe: C HBT 300 K

50 0

0

50

100

150

200

250

300

350

400

Peak f T (GHz)

FIGURE 1.7 Measured maximum oscillation frequency versus cutoff frequency for a variety of generations of SiGe HBT BiCMOS technology shown in Figure 1.1.

fT and fmax fully integrated with nanometer-scale (90 nm and below) Si CMOS (possibly strained Si CMOS) within the next 3 to 5 years. One might logically ask, particularly within the confines of the above discussion on ultimate market relevance, why one would even attempt to build 500 GHz SiGe HBTs, other than to win a best-paper award, or to trumpet that ‘‘because-it’s-there’’ Mount Everest mentality we engineers and scientists love so dearly. This said, if the future ‘‘killer app’’ turns out to be single-chip mm-wave transceiver systems with on-board DSP for broadband multimedia, radar, etc., then the ability of highly scaled, highly integrated, very high performance SiGe HBTs to dramatically enlarge the circuit/system design space of the requisite mm-wave building blocks may well prove to be a fruitful (and marketable) path. Other interesting themes are emerging in the SiGe HBT BiCMOS technology space. One is the very recent emergence of complementary SiGe (C-SiGe) HBT processes (npn þ pnp SiGe HBTs). While very early pnp SiGe HBT prototypes were demonstrated in the early 1990s, only in the last 2 years or so have fully complementary SiGe processes been developed, the most mature of which to date is the IHP SGC25C process, which has 200 GHz npn SiGe HBTs and 80 GHz pnp SiGe HBTs (Chapter 11, see Fabrication of SiGe HBT BiCMOS Technology). Having very high-speed pnp SiGe HBTs on-board presents a fascinating array of design opportunities aimed particularly at the analog/mixed-signal circuit space. In fact, an additional emerging trend in the SiGe field, particularly for companies with historical pure analog circuit roots, is to target lower peak fT , but higher breakdown voltages, while simultaneously optimizing the device for core analog applications (e.g., op amps, line drivers, data converters, etc.), designs which might, for instance, target better noise performance, and higher current gain-Early voltage product than mainstream SiGe technologies. One might even choose to park that SiGe HBT platform on top of thick film SOI for better isolation properties (Chapter 13, see Fabrication of SiGe HBT BiCMOS Technology). Another interesting option is the migration of high-speed vertical SiGe HBTs with very thin film CMOS-compatible SOI (Chapter 5, see Fabrication of SiGe HBT BiCMOS Technology). This technology path would clearly favor the eventual integration of SiGe HBTs with strained Si CMOS, all on SOI, a seemingly natural migratory path. If one accepts the tenet that integration is a good thing from a system-level perspective, the Holy Grail in the Si heterostructure field would, in the end, appear to be the integration of SiGe HBTs for RF through mm-wave circuitry (e.g., single-chip mm-wave transceivers complete with on-chip antennae), strained Si CMOS for all DSP and memory functionality, both perhaps on SOI, Si-based light emitters, SiGe HBT modulator electronics, and detectors for such light sources, together with on-chip waveguides to steer the light, realized all on one Si wafer to produce a ‘‘Si-based optoelectronic superchip’’ [8], that could do-it-all. These diverse blocks would be optional plug-in modules around a core SiGe


The Big Picture

page 11 17.10.2007


1-11

HBT þ strained Si CMOS IC technology platform, perhaps with flip-chip (or other) packaging techniques to join different sub-die to the main superchip (e.g., for a Si-based detector or laser). I know, I know. It is not obvious that even if each of these blocks could be realized, that it would make economic sense to do so for real systems. I have no quarrel with that. I think such a Si-based superchip is a useful paradigm, however, to bind together all of the clever objects we wish to ultimately build with Si heterostructures, from electronic to photonic, and maintain the vision of the one overarching constraint that guides us as we look forward — keep whatever you do compatible with high-volume manufacturing in Si fabrication facilities if you want to shape the path of the ensuing communications revolution. This Si-based superchip clearly remains a dream at present. A realizable dream? And if realizable, commercially viable? Who knows? Only time will tell. But it is fun to think about. As you peruse this book you hold in your hands, which spans the whole Si heterostructure research and development space, from materials, to devices, to circuit and system applications, I think you will be amazed at both the vision, cleverness, and smashing successes of the many scientists and engineers who make up our field. Do not count us out! We are the new architects of an oh-so-very-interesting future.

References 1. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 2. ‘‘SiGe devices market to hit $2 billion in 2006,’’ article featured on CompoundSemicoductor.net, http://compoundsemiconductor.net/articles/news/8/3/22/1. 3. F Capasso. Band-gap engineering: from physics and materials to new semiconductor devices. Science, 235:172–176, 1987. 4. S Reynolds, B Floyd, U Pfeiffer, and T. Zwick. 60 GHz transciever circuits in SiGe bipolar technology. Technical Digest of the IEEE International Solid-State Circuits Conference, San Francisco, 2004, pp 442–443. 5. AJ Joseph, D Coolbaugh, D Harame, G Freeman, S Subbanna, M Doherty, J Dunn, C Dickey, D Greenberg, R Groves, M Meghelli, A Rylyakov, M Sorna, O Schreiber, D Herman, and T Tanji. 0.13 mm 210 GHz fT SiGe HBTs — expanding the horizons of SiGe BiCMOS. Technical Digest of the IEEE International Solid-State Circuits Conference, San Francisco, 2002, pp 180–182. 6. J-S Rieh, D Greenberg, M Khater, KT Schonenberg, J-J Jeng, F Pagette, T Adam, A Chinthakindi, J Florkey, B Jagannathan, J Johnson, R Krishnasamy, D Sanderson, C Schnabel, P Smith, A Stricker, S Sweeney, K Vaed, T Yanagisawa, D Ahlgren, K Stein, and G Freeman. SiGe HBTs for millimeter-wave applications with simultaneously optimized fT and fmax. Proceedings of the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Fort Worth, 2004, pp 395–398. 7. JS Rieh, B Jagannathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, S-J Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freeman, K Stein, and S Subbanna. SiGe HBTs with cutoff frequency of 350 GHz. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp 771–774. 8. R Soref. Silicon-based photonic devices. Technical Digest of the IEEE International Solid-State Circuits Conference, 1995, pp 66–67.


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2 A Brief History of the Field John D. Cressler Georgia Institute of Technology

2.1 2.2 2.3

Si–SiGe Strained Layer Epitaxy.......................................... 2-1 SiGe HBTs ............................................................................ 2-3 SiGe–Strained Si FETs and Other SiGe Devices ............... 2-6

In the historical record of any field of human endeavor, being ‘‘first’’ is everything. It is often said that ‘‘hindsight is 20–20,’’ and it is tempting in many cases to ascribe this or that pivotal event as ‘‘obvious’’ or ‘‘easy’’ once the answer is known. Anyone intimately involved in a creative enterprise knows, however, that it is never easy being first, and often requires more than a little luck and maneuvering. Thus the triumphs of human creativity, the ‘‘firsts,’’ should be appropriately celebrated. Still, later chroniclers often gloss over, and then eventually ignore, important (and sometimes very interesting) twists and turns, starts and stops, of the winners as well as the second and third place finishers, who in the end may in fact have influenced the paths of the winners, sometimes dramatically. The history of our field, for instance, is replete with interesting competitive battles, unusual personalities and egos, no small amount of luck, and various other fascinating historical nuances. There is no concise history of our field available, and while the present chapter is not intended to be either exhaustive or definitive, it represents my firm conviction that the history of any field is both instructive and important for those who follow in the footsteps of the pioneers. Hopefully this brief history does not contain too many oversights or errors, and is offered as a step in the right direction for a history of pivotal events that helped shape the Si heterostructures field.

2.1

Si–SiGe Strained Layer Epitaxy

The field of Si-based heterostructures solidly rests on the shoulders of materials scientists and crystal growers, those purveyors of the semiconductor ‘‘black arts’’ associated with the deposition of pristine films of nanoscale dimensionality onto enormous Si wafers with near infinite precision. What may seem routine today was not always so. The Si heterostructure story necessarily begins with materials, and circuit designers would do well to remember that much of what they take for granted in transistor performance owes a great debt to the smelters of the crystalline world. Table 2.1 summarizes the key steps in the development of SiGe–Si strained layer epitaxy. Given that Ge was the earliest and predominant semiconductor pursued by the Bell Laboratories transistor team, with a focus on the more difficult to purify Si to come slightly later, it is perhaps not surprising that the first study of SiGe alloys, albeit unstrained bulk alloys, occurred as early as 1958 [1]. It was recognized around 1960 [2] that semiconductor epitaxy* would enable more robust and controllable transistor fabrication. Once the move to Si-based processing occurred, the field of Si epitaxy was

*The word ‘‘epitaxy’’ (or just ‘‘epi’’) is derived from the Greek word epi, meaning ‘‘upon’’ or ‘‘over.’’

2-1


2-2



Measurement and Modeling of Silicon Heterostructure Devices TABLE 2.1

Milestones in the Development of SiGe–Si Strained Layer Epitaxy

Historical Event

Year

Ref.

First investigation of the bandgap of unstrained SiGe alloys First epitaxially grown layer to be used in a transistor First investigation of high-temperature Si epitaxy Concept of critical thickness for epitaxial strained layers Energy minimization approach for critical thickness Force-balance approach for critical thickness First growth of SiGe strained layers First growth of SiGe epitaxy by MBE First stability calculations of SiGe strained layers First measurements of energy bandgap in SiGe strained layers First growth of Si epitaxy by LRP-CVD First 2D electron gas in the SiGe system First growth of Si epitaxy by UHV/CVD First measurements of band alignments in SiGe–Si First growth of SiGe epitaxy by UHV/CVD First step-graded relaxed SiGe substrate First growth of SiGe epitaxy by LRP-CVD First growth of Si epitaxy by AP-CVD First 2D hole gas in the SiGe system First growth of SiGe epitaxy by AP-CVD First majority hole mobility measurements in SiGe First minority electron mobility measurements in SiGe First growth of lattice-matched SiGeC alloys First growth of SiGe layers with carbon doping First stability calculations to include a Si cap layer

1958 1960 1963 1963 1963 1974 1975 1984 1985 1985 1985 1985 1986 1986 1988 1988 1989 1989 1989 1991 1991 1992 1992 1994 2000

[1] [2] [3] [4] [5] [6] [7] [8] [9] [10,11] [12] [13] [14] [15] [16] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25]

launched, the first serious investigation of which was reported in 1963 [3]. Early Si epitaxy was exclusively conducted under high-temperature processing conditions, in the range of 11008C, a temperature required to obtain a chemically pure and pristine growth interface on the Si host substrate for the soon-to-be-grown crystalline Si epi. High-temperature Si epi has been routinely used in basically this same form for over 40 years now, and represents a mature fabrication technique that is still widely practiced for many types of Si devices (e.g., high-speed bipolar transistors and various power devices). Device engineers have long recognized the benefits of marrying the many virtues of Si as a host material for manufacturing electronic devices, with the bandgap engineering principles routinely practiced in the III–V system. Ultimately this requires a means by which one can perform epitaxial deposition of thin Si layers on large Si substrates, for both p- and n-type doping of arbitrary abruptness, with very high precision, across large wafers, and doping control at high dynamic range. Only a moment’s reflection is required to appreciate that this means the deposition of the Si epi must occur at very low growth temperatures, say 5008C to 6008C (not ‘‘low’’ per se, but low compared to the requisite temperatures needed for solid-state diffusion of dopants in Si). Such a low-temperature Si epi would then facilitate the effective marriage of Si and Ge, two chemically compatible elements with differing bandgaps, and enable the doping of such layers with high precision, just what is needed for device realizations. Clearly the key to Si-based bandgap engineering, Si-heterostructures, our field, is the realization of device quality, low-temperature Si epi (and hence SiGe epi), grown pseudomorphically* on large Si host substrates. Conquering this task proved to be remarkably elusive and time consuming. In the III–V semiconductor world, where very low processing temperatures are much easier to attain, and hence more common than for Si, the deposition of multiple semiconductors on top of one another proved quite feasible (e.g., GaAs on InP), as needed to practice bandgap engineering, for instance, *The word ‘‘pseudo’’ is derived from the Greek word pseude¯s, meaning ‘‘false,’’ and the word ‘‘morphic’’ is derived from the Greek word morphe¯, meaning ‘‘form.’’ Hence, pseudomorphic literally means false-form.


A Brief History of the Field



2-3

resulting in complex material composites having differing lattice constants in intimate physical contact. To accommodate the differing lattice constants while maintaining the crystallinity of the underlying films, strain is necessarily induced in the composite film, and the notion of a film ‘‘critical thickness,’’ beyond which strain relaxation occurs via fundamental thermodynamic driving forces, was defined as early as 1963 [4], as were the energy minimization techniques needed for calculating such critical thicknesses [5]. Alternative ‘‘force-balance’’ techniques for addressing the so-called stability issues in strained layer epitaxy came from the III–V world in 1974, and were applied to SiGe strained layer epitaxy in 1985 [9]. Interestingly, however, research continues today on stability in complicated (e.g., compositionally graded) SiGe films, and only very recently have reasonably complete theories been offered which seem to match well with experiment [25]. The first reported growth of SiGe strained layers was in 1975 in Germany [7], but the field did not begin to seriously heat up until the early 1980s, when several teams pioneered the application of molecular beam epitaxy (MBE) to facilitate materials studies of device-quality strained SiGe on Si in 1984 [8]. Optical studies on these films resulted in encouraging findings concerning the beneficial effects of strain on the band-edge properties of SiGe [10,11], paving the way for serious contemplation of devices built from such materials. Parallel paths toward other low-temperature Si epi growth techniques centered on the ubiquitous chemical vapor deposition (CVD) approach were simultaneously pursued, culminating in the so-called limited-reaction-processing CVD (LRP-CVD) technique (Si epi in 1985 [12], and SiGe epi in 1989 [17]), the ultrahigh-vacuum CVD (UHV/CVD) technique (Si epi in 1986 [14] and SiGe epi in 1988 [16]), and various atmospheric pressure CVD (AP-CVD) techniques (e.g., Si epi in 1989 [18], and SiGe epi in 1991 [20]). These latter two techniques, in particular, survive to this day, and are widely used in the SiGe heterojunction bipolar transistor (HBT) industry. Device-quality SiGe–Si films enabled a host of important discoveries to occur, which have important bearing on device derivatives, including the demonstration of both two-dimensional electron and hole gases [13,19], and the fortuitous observation that step-graded SiGe buffer layers could be used to produce device-quality strained Si on SiGe, with its consequent conduction band offsets [16]. This latter discovery proved important in the development of SiGe–Si heterostructure-based FETs. Both majority and minority carrier mobility measurements occurred in the early 1990s [21,22], although reliable data, particularly involving minority carriers, remain sparse in the literature. Also in the early 1990s, experiments using high C content as a means to relieve strain in SiGe and potentially broaden the bandgap engineering space by lattice-matching SiGe:C materials to Si substrates (a path that has to date not borne much fruit, unfortunately), while others began studying efficacy of C-doping of SiGe, a result that ultimately culminated in the wide use today of C-doping for dopant diffusion suppression in SiGe:C HBTs [23,24]. The Si–SiGe materials field continues to evolve. Commercial single wafer (AP-CVD) and batch wafer (UHV/CVD) Si–SiGe epi growth tools compatible with 200 mm (and soon 300 mm) Si wafers exist in literally dozens of industrial fabrication facilities around the world, and SiGe growth can almost be considered routine today in the ease in which it can be integrated into CMOS-compatible fabrication processes. It was clearly of paramount importance in the ultimate success of our field that some of the ‘‘black magic’’ associated with robust SiGe film growth be removed, and this, thankfully, is the case in 2005.

2.2

SiGe HBTs

Transistor action was first demonstrated by Bardeen and Brattain in late December of 1947 using a point contact device [26]. Given all that has transpired since, culminating in the Communications Revolution, which defines our modern world (refer to the discussion in Chapter 1), this pivotal event surely ranks as one of the most significant in the course of human history—bold words, but nevertheless true. This demonstration of a solid-state device exhibiting the key property of amplification (power gain) is also unique in the historical record for the precision with which we can locate it in time—December 23,


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1947, at about 5 p.m. Not to be outdone, Shockley rapidly developed a theoretical basis for explaining how this clever object worked, and went on to demonstrate the first true bipolar junction transistor (BJT) in 1951 [27]. The first BJT was made, ironically in the present context, from Ge. The first silicon BJT was made by Teal in 1954 using grown junction techniques. The first diffused silicon BJT was demonstrated in 1956 [28], and the first epitaxially grown silicon BJT was reported in 1960, see Ref. [2]. The concept of the HBT is surprisingly an old one, dating in fact to the fundamental BJT patents filed by Shockley in 1948 [29]. Given that the first bipolar transistor was built from Ge, and III–V semiconductors were not yet on the scene, it seems clear that Shockley envisioned the combination of Si (wide bandgap emitter) and Ge (narrow bandgap base) to form a SiGe HBT. The basic formulation and operational theory of the HBT, for both the traditional wide bandgap emitter plus narrow bandgap base approach found in most III–V HBTs, as well as the drift-base (graded) approach used in SiGe HBTs today, was pioneered by Kroemer, and was largely in place by 1957 [30–32]. It is ironic that Kroemer in fact worked hard early on to realize a SiGe HBT, without success, ultimately pushing him toward the III–V material systems for his heterostructure studies, a path that proved in the end to be quite fruitful for him, since he shared the Nobel Prize in physics in 2000 for his work in (III–V) bandgap engineering for electronic and photonic applications [33]. While III–V HBT (e.g., AlGaAs–GaAs) demonstrations began appearing in the 1970s, driven largely by the needs for active microwave components in the defense industry, reducing the SiGe HBT to practical reality took 30 years after the basic theory was in place due to material growth limitations. As pointed out [34] the semiconductor device field is quite unique in the scope of human history because ‘‘science’’ (theoretical understanding) preceded the ‘‘art’’ (engineering and subsequent technological advancement). Once device-quality SiGe films were finally achieved in the mid-1980s, however, progress was quite rapid. Table 2.2 summarizes the key steps in the evolution of SiGe HBTs. The first functional SiGe HBT was demonstrated by an IBM team in December 1987 at the IEDM [35]. The pioneering result showed a SiGe HBT with functional, albeit leaky, dc characteristics; but it was a SiGe HBT, it worked (barely), and it was the first.* It is an often overlooked historical point, however, that at least four independent groups were simultaneously racing to demonstrate the first functional SiGe HBT, all using the MBE growth technique: the IBM team [35], a Japanese team [62], a Bell Laboratories team [63], and a Linko¨ping University team [64]. The IBM team is fairly credited with the victory, since it presented (and published) its results in early December of 1987 at the IEDM (it would have been submitted to the conference for review in the summer 1987) [35]. Even for the published journal articles, the IBM team was the first to submit its paper for review (on November 17, 1987) [65]. All four papers appeared in print in the spring of 1988. Other groups soon followed with more SiGe HBT demonstrations. The first SiGe HBT demonstrated using (the ultimately more manufacturable) CVD growth technique followed shortly thereafter, in 1989, first using LRP-CVD [17], and then with UHV/CVD [36]. Worldwide attention became squarely focused on SiGe technology, however, in June 1990 at the IEEE VLSI Technology Symposium with the demonstration of a non-self-aligned UHV/CVD SiGe HBT with a peak cutoff frequency of 75 GHz [37,38]. At that time, this SiGe HBT result was roughly twice the performance of state-of-the-art Si BJTs, and clearly demonstrated the future performance potential of the technology (doubling of transistor performance is a rare enough event that it does not escape significant attention!). Eyebrows were raised, and work to develop SiGe HBTs for practical circuit applications began in earnest in a large number of industrial and university laboratories around the world.y The feasibility of implementing pnp SiGe HBTs was also demonstrated in June 1990 [40]. In December 1990, the simplest digital circuit, an emitter-coupled-logic (ECL) ring oscillator, using *An interesting historical perspective of early SiGe HBT development at IBM is contained in Ref. [61]. y A variety of zero-Dt, mesa-isolated, III–V-like high-speed SiGe HBTs were reported in the early 1990s (e.g., Ref. [66]), but we focus here on fully integrated, CMOS-compatible SiGe HBT technologies, because they are inherently more manufacturable, and hence they are the only ones left standing today, for obvious reasons.




2-5

A Brief History of the Field TABLE 2.2

Milestones in the Development of SiGe HBTs

Historical Event

Year

Ref.

First demonstration of transistor action Basic HBT concept First demonstration of a bipolar junction transistor First demonstration of a silicon bipolar transistor Drift-base HBT concept Fundamental HBT theory First epitaxial silicon transistors First SiGe HBT First ideal SiGe HBT grown by CVD First SiGe HBT grown by UHV/CVD First high-performance SiGe HBT First self-aligned SiGe HBT First SiGe HBT ECL ring oscillator First pnp SiGe HBT First operation of SiGe HBTs at cryogenic temperatures First SiGe HBT BiCMOS technology First LSI SiGe HBT integrated circuit First SiGe HBT with peak fT above 100 GHz First SiGe HBT technology in 200-mm manufacturing First SiGe HBT technology optimized for 77 K First radiation tolerance investigation of SiGe HBTs First report of low-frequency noise in SiGe HBTs First SiGe:C HBT First high-power SiGe HBTs First sub-10 psec SiGe HBT ECL circuits First high-performance SiGe:C HBT technology First SiGe HBT with peak fT above 200 GHz First SiGe HBT with peak fT above 300 GHz First complementary (npn þ pnp) SiGe HBT technology First C-SiGe technology with npn and pnp fT above 100 GHz First vertical SiGe HBT on thin film (CMOS compatible) SOI First SiGe HBT with both fT and fmax above 300 GHz

1947 1948 1951 1956 1954 1957 1960 1987 1989 1989 1990 1990 1990 1990 1990 1992 1993 1993 1994 1994 1995 1995 1996 1996 1997 1999 2001 2002 2003 2003 2003 2004

[26] [29] [27] [28] [30] [31,32] [2] [35] [17] [36] [37,38] [39] [39] [40] [41] [42] [43] [44,45] [46] [47] [48] [49] [50] [51,52] [53] [54] [55] [56] [57] [58] [59] [60]

self-aligned, fully integrated SiGe HBTs was produced [39]. The first SiGe BiCMOS technology (SiGe HBT þ Si CMOS) was reported in December 1992 [42]. Theoretical predictions of the inherent ability of SiGe HBTs to operate successfully at cryogenic temperatures (in contrast to Si BJTs) were first confirmed in 1990 [41], and SiGe HBT profiles optimized for the liquid nitrogen temperature environment (77 K) were reported in 1994 [48]. The first LSI SiGe HBT circuit (a 1.2 Gsample/sec 12-bit digital-to-analog converter—DAC) was demonstrated in December 1993 [43]. The first SiGe HBTs with frequency response greater than 100 GHz were described in December 1993 by two independent teams [44,45], and the first SiGe HBT technology entered commercial production on 200-mm wafers in December 1994 [46]. The first report of the effects of ionizing radiation on advanced SiGe HBTs was made in 1995 [48]. Due to the natural tolerance of epitaxial-base bipolar structures to conventional radiation-induced damage mechanisms without any additional radiation-hardening process changes, SiGe HBTs are potentially very important for space-based and planetary communication systems applications, spawning an important new sub-discipline for SiGe technology. The first demonstration that epitaxial SiGe strained layers do not degrade the superior low-frequency noise performance of bipolar transistors occurred in 1995, opening the way for very low-phase noise frequency sources [49]. Carbon-doping of epitaxial SiGe layers as a means to effectively suppress boron out-diffusion during fabrication has rapidly become the preferred approach for commercial SiGe technologies, particularly those above first-generation performance levels. Carbon-doping of SiGe HBTs has its own interesting


2-6




history, dating back to the serendipitous discovery [50] in 1996 that incorporating small amounts of C into a SiGe epi layer strongly retards (by an order of magnitude) the diffusion of the boron (B) base layer during subsequent thermal cycles. Given that maintaining a thin base profile during fabrication is perhaps the most challenging aspect of building a manufacturable SiGe technology, it is somewhat surprising that it took so long for the general adoption of C-doping as a key technology element. I think it is fair to say that most SiGe practitioners at that time viewed C-doping with more than a small amount of skepticism, given that C can act as a deep trap in Si, and C contamination is generally avoided at all costs in Si epi processes, particularly for minority carrier devices such as the HBT. At the time of the discovery of C-doping of SiGe in 1996, most companies were focused on simply bringing up a SiGe process and qualifying it, relegating the potential use of C to the back burner. In fairness, most felt that C-doping was not necessary to achieve first-generation SiGe HBT performance levels. The lone visionary group to solidly embrace C-doping of SiGe HBTs at the onset was the IHP team in Germany, whose pioneering work eventually paid off and began to convince the skeptics of the merits of C-doping. The minimum required C concentration for effective out-diffusion suppression of B was empirically established to be in the vicinity of 0.1% to 0.2% C (i.e., around 1 1020 cm3). Early on, much debate ensued on the physical mechanism of how C impedes the B diffusion process, but general agreement for the most part now exists and is discussed in Chapter 11 (see SiGe and Si Strained-Layer Epitaxy for Silicon Heterostructure Devices). The first high-performance, fully integrated SiGe:C HBT technology was reported in 1999 [54]. The first ‘‘high-power’’ SiGe HBTs (S band, with multiwatt output power) were reported in 1996 using thick collector doping profiles [51,52]. The 10-psec ECL circuit performance barrier was broken in 1997 [53]. The 200-GHz peak fT performance barrier was broken in November 2001 for a nonself-aligned device [55], and for a self-aligned device in February 2002 [67]. By 2004, a total of six industrial laboratories had achieved 200 GHz performance levels. A SiGe HBT technology with a peak fT of 350 GHz (375 GHz values were reported in the IEDM presentation) was presented in December 2002 [56], and this 375 GHz fT value remains a record for room temperature operation (it is above 500 GHz at cryogenic temperatures), and an optimized version with both fT and fmax above 300 GHz was achieved in June 2004 [60]. This combined level of 300þ GHz for both fT and fmax remains a solid record for any Si-based semiconductor device. Other recent and interesting developments in the SiGe HBT field include the first report of a complementary (npn þ pnp) SiGe HBT (C-SiGe) technology in 2003 [57], rapidly followed by a C–SiGe technology with fT for both the npn and pnp SiGe HBTs above 100 GHz [58]. In addition, a novel vertical npn SiGe HBT has been implemented in thin-film (120 nm) CMOS-compatible SOI [59]. Besides further transistor performance enhancements, other logical developments to anticipate in this field include the integration of SiGe HBTs with strained-Si CMOS for a true all-Si-heterostructure technology. Not surprisingly, research and development activity involving SiGe HBTs, circuits built from these devices, and various SiGe HBT technologies, in both industry and at universities worldwide, has grown very rapidly since the first demonstration of a functional SiGe HBT in 1987, only 18 years in the past.

2.3

SiGe–Strained Si FETs and Other SiGe Devices

The basic idea of using an electric field to modify the surface properties of materials, and hence construct a ‘‘field-effect’’ device, is remarkably old (1926 and 1935), predating even the quest for a solid-state amplifier [68]. Given the sweeping dominance of CMOS technology in the grand scheme of the electronics industry today, it is ironic that the practical demonstration of the BJT preceded that of the MOSFET by 9 years. This time lag from idea to realization was largely a matter of dealing with the many perils associated with obtaining decent dielectric materials in the Si system—doubly ironic given that Si has such a huge natural advantage over all other semiconductors in this regard. Bread-and-butter notions of ionic contamination, de-ionized water, fixed oxide charge, surface state passivation, and cleanroom techniques in semiconductor fabrication had to be learned the hard way. Once device- quality




2-7


SiO2 was obtained in the late 1950s, and a robust gate dielectric could thus be fabricated, it was not long until the first functional MOSFET was demonstrated in 1960 [69]. The seemingly trivial (remember, however, that hindsight is 20–20!) connection of n-channel and p-channel MOSFETs to form low-power CMOS in 1963 [70] paved the way (eventually) to the high-volume, low-cost, highly integrated microprocessor, and the enormous variety of computational engines that exist today as a result. Like their cousin, the SiGe HBT, SiGe–strained Si FETs did not get off the ground until the means for accomplishing the low-temperature growth of Si epitaxy could be realized. Once that occurred in the mid-1980s the field literally exploded. Table 2.3 summarizes the milestones in the evolution of SiGe– strained Si FETs, as well as a veritable menagerie of other electronic and optoelectronic components built from SiGe–strained Si epitaxy. It was discovered as early as 1971 that direct oxidation of SiGe was a bad idea for building gate dielectrics [71]. Given that gate oxide quality, low-temperature deposited oxides, did not exist in the mid-1980s, the earliest FET demonstrations were modulation-doped, Schottky-gated, FETs, and both n-channel and p-channel SiGe MODFETs were pioneered as early as 1986 using MBE-grown material [72,73]. Before the SiGe MOSFET field got into high gear in the 1990s, a variety of other novel device demonstrations occurred, including: the first SiGe superlattice photodetector [74], the first SiGe Schottky barrier diodes (SBD) in 1988 [75], the first SiGe hole-transport resonant tunneling diode (RTD) in 1988 [76], and the first SiGe bipolar inversion channel FET (BiCFET) in 1989, a now-extinct dinosaur [77]. Meanwhile, early studies using SiGe in conventional CMOS gate stacks to minimize dopant depletion effects and tailor work functions, a fairly common practice in CMOS today, occurred in 1990 [78], and the first SiGe waveguides on Si substrates were produced in 1990 [79]. The first functional SiGe channel pMOSFET was published in 1991, and shortly thereafter, a wide variety of other approaches aimed at obtaining the best SiGe pMOSFETs (see, for instance, Refs. [93–95]). The first electron-transport RTD was demonstrated in 1991 [81], and the first LED in SiGe

TABLE 2.3

Milestones in the Development of SiGe–Strained Si FETs and Other Devices

Historical Event

Year

Ref.

Field effect device concept First Si MOSFET First Si CMOS First oxidation study of SiGe First SiGe nMODFET First SiGe pMODFET First SiGe photodetector First SiGe SBD First SiGe hole RTD First SiGe BiCFET First SiGe gate CMOS technology First SiGe waveguide First SiGe pMOSFET First SiGe electron RTD First SiGe LED First SiGe solar cell First a-SiGe phototransistor First SiGe pMOSFET on SOI First strained Si pMOSFET First strained Si nMOSFET First SiGe:C pMOSFET First SiGe pFET on SOS First submicron strained Si MOSFET First vertical SiGe pFET First strained Si CMOS technology

1926 1960 1963 1971 1986 1986 1986 1988 1988 1989 1990 1990 1991 1991 1991 1992 1993 1993 1993 1994 1996 1997 1998 1998 2002

[68] [69] [70] [71] [72] [73] [74] [75] [76] [77] [78] [79] [80] [81] [82] [83] [84] [85] [86] [87] [88] [89] [90] [91] [92]


2-8




also in 1991 (a busy year for our field). In 1992, the first a-SiGe solar cell was discussed [83], and in 1993, the first high-gain a-SiGe phototransistor [84]. The first SiGe pMOSFETs using alternate substrate materials were demonstrated, first in SOI in 1993 [85], and then on sapphire in 1997 [88], the first SiGe:C channel pMOSFET was demonstrated in 1996 [89], and the first vertical SiGe FET was published in 1998 [92]. Because of the desire to use Si-based bandgap engineering to improve not only the p-channel MOSFET, but also the n-channel MOSFET, research in the early- to mid-1990s in the FET field began to focus on strained Si MOSFETs on relaxed SiGe layers, with its consequent improvement in both electron and hole transport properties. This work culminated in the first strained Si pMOSFET in 1993 [87], and the first stained Si nMOSFET in 1994 [88], and remains an intensely active research field today. Key to the eventual success of strained Si CMOS approaches was that significant mobility enhancement could be achieved in both nFETs and pFETs down to very short (sub-micron) gate lengths, and this was first demonstrated in 1998 [90]. Strained Si CMOS at the 90-nm node and below is rapidly becoming mainstream for most serious CMOS companies, and the first commercial 90 nm strained Si CMOS technology platform was demonstrated by Intel in 2002 [91]. At last count, there were upwards of a halfdozen companies (e.g., Texas Instruments and IBM) also rapidly pushing toward 90 nm (and below) strained Si CMOS technologies, utilizing a variety of straining techniques, and thus it would appear that strained Si CMOS will be a mainstream IC technology in the near future, joining SiGe HBT BiCMOS technology. This is clearly outstanding news for our field. The merger of SiGe HBTs with strained Si CMOS would be a near-term logical extension.

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15. R People and JC Bean. Band alignments of coherently strained GexSi1x/Si heterostructures on h0 0 1i GeySi1y substrates. Applied Physics Letters 48:538–540, 1986. 16. BS Meyerson, KJ Uram, and FK LeGoues. Cooperative phenomena is silicon/germanium low temperature epitaxy. Applied Physics Letters 53:2555–2557, 1988. 17. CA King, JL Hoyt, CM Gronet, JF Gibbons, MP Scott, and J Turner. Si/Si1x/Gex heterojunction bipolar transistors produced by limited reaction processing. IEEE Electron Device Letters 10:52–54, 1989. 18. TO Sedgwick, M Berkenbilt, and TS Kuan. Low-temperature selective epitaxial growth of silicon at atmospheric pressure. Applied Physics Letters 54:2689–2691, 1989. 19. PJ Wang, FF Fang, BS Meyerson, J Mocera, and B Parker. Two-dimensional hole gas in Si/Si0.85Ge0.15 modulation doped heterostructures. Applied Physics Letters 54:2701–2703, 1989. 20. P Agnello, TO Sedgwick, MS Goorsky, J Ott, TS Kuan, and G Scilla. Selective growth of silicon– germanium alloys by atmospheric-pressure chemical vapor deposition at low temperatures. Applied Physics Letters 59:1479–1481, 1991. 21. T Manku and A Nathan. Lattice mobility of holes in strained and unstrained Si1xGex alloys. IEEE Electron Device Letters 12:704–706, 1991. 22. T Manku and A Nathan. Electron drift mobility model for devices based on unstrained and coherently strained Si1xGex grown on h0 0 1i silicon subtrate. IEEE Transactions on Electron Devices 39:2082–2089, 1992. 23. K Erbel, SS Iyer, S Zollner, JC Tsang, and FK LeGoues. Growth and strain compensation effects in the ternary Si1xyGexCy alloy system. Applied Physics Letters 60:3033–3035, 1992. 24. HJ Osten, E Bugiel, and P Zaumseil. Growth of inverse tetragonal distorted SiGe layer on Si(0 0 1) by adding small amounts of carbon. Applied Physics Letters 64:3440–3442, 1994. 25. A Fischer, H-J Osten, and H Richter. An equilibrium model for buried SiGe strained layers. SolidState Electronics 44:869–873, 2000. 26. J Bardeen and WH Brattain. The transistor, a semi-conductor triode. Physical Review 71:230–231, 1947. 27. W Shockley, M Sparks, and GK Teal. p–n junction transistors. Physical Review 83:151–162, 1951. 28. M Tanenbaum and DE Thomas. Diffused emitter and base silicon transistors. Bell System Technical Journal 35:23–34, 1956. 29. See, for instance, W Shockley. U.S. Patents 2,502,488, 2,524,035, and 2,569,347. 30. H Kroemer. Zur theorie des diffusions und des drifttransistors. Part III. Archiv der Elektrischen Ubertragungstechnik 8:499–504, 1954. 31. H Kroemer. Quasielectric and quasimagnetic fields in nonuniform semiconductors. RCA Review 18:332–342, 1957. 32. H Kroemer. Theory of a wide-gap emitter for transistors. Proceedings of the IRE 45:1535–1537, 1957. 33. B Brar, GJ Sullivan, and PM Asbeck. Herb’s bipolar transistors. IEEE Transactions on Electron Devices 48:2473–2476, 2001. 34. RM Warner. Microelectronics: Its unusual origin and personality. IEEE Transactions on Electron Devices 48:2457–2467, 2001. 35. SS Iyer, GL Patton, SL Delage, S Tiwari, and J.M.C. Stork. Silicon–germanium base heterojunction bipolar transistors by molecular beam epitaxy. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1987, pp. 874–876. 36. GL Patton, DL Harame, JMC Stork, BS Meyerson, GJ Scilla, and E Ganin. Graded-SiGe-base, polyemitter heterojunction bipolar transistors. IEEE Electron Device Letters 10:534–536, 1989. 37. GL Patton, JH Comfort, BS Meyerson, EF Crabbe´, E de Fre´sart, JMC Stork, JY-C Sun, DL Harame, and J Burghartz. 63-75 GHz fT SiGe-base heterojunction-bipolar technology. Technical Digest IEEE Symposium on VLSI Technology, Honolulu, 1990, pp. 49–50. 38. GL Patton, JH Comfort, BS Meyerson, EF Crabbe´, GJ Scilla, E de Fre´sart, JMC Stork, JY-C Sun, DL Harame, and J Burghartz. 75 GHz fT SiGe base heterojunction bipolar transistors. IEEE Electron Device Letters 11:171–173, 1990.


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39. JH Comfort, GL Patton, JD Cressler, W Lee, EF Crabbe´, BS Meyerson, JY-C Sun, JMC Stork, P-F Lu, JN Burghartz, J Warnock, K Kenkins, K-Y Toh, M D’Agostino, and G Scilla. Profile leverage in a selfaligned epitaxial Si or SiGe-base bipolar technology. Technical Digest IEEE International Electron Devices Meeting, Washington, 1990, pp. 21–24. 40. DL Harame, JMC Stork, BS Meyerson, EF Crabbe´, GL Patton, GJ Scilla, E de Fre´sart, AA Bright, C Stanis, AC Megdanis, MP Manny, EJ Petrillo, M Dimeo, RC Mclntosh, and KK Chan. SiGe-base PNP transistors fabrication with n-type UHV/CVD LTE in a ‘‘NO DT’’ process. Technical Digest IEEE Symposium on VLSI Technology, Honolulu, 1990, pp. 47–48. 41. EF Crabbee´, GL Patton, JMC Stork, BS Meyerson, and JY-C Sun. Low temperature operation of Si and SiGe bipolar transistors. Technical Digest IEEE International Electron Devices Meeting, Washington, 1990, pp. 17–20. 42. DL Harame, EF Crabbe´, JD Cressler, JH Comfort, JY-C Sun, SR Stiffler, E Kobeda, JN Burghartz, MM Gilbert, J Malinowski, and AJ Dally. A high-performance epitaxial SiGe-base ECL BiCMOS technology. Technical Digest IEEE International Electron Devices Meeting, Washington, 1992, pp. 19–22. 43. DL Harame, JMC Stork, BS Meyerson, KY-J Hsu, J Cotte, KA Jenkins, JD Cressler, P Restle, EF Crabbe´, S Subbanna, TE Tice, BW Scharf, and JA Yasaitis. Optimization of SiGe HBT technology for high speed analog and mixed-signal applications. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 1993, pp. 71–74. 44. E Kasper, A Gruhle, and H Kibbel. High speed SiGe-HBT with very low base sheet resistivity. Techncial Digest IEEE International Electron Devices Meeting, San Francisco, 1993, pp. 79–81. 45. EF Crabbe´, BS Meyerson, JMC Stork, and DL Harame. Vertical profile optimization of very high frequency epitaxial Si- and SiGe-base bipolar transistors. Technical Digest IEEE International Electron Devices Meeting, Washington, 1993, pp. 83–86. 46. DL Harame, K Schonenberg, M Gilbert, D Nguyen-Ngoc, J Malinowski, S-J Jeng, BS Meyerson, JD Cressler, R Groves, G Berg, K Tallman, K Stein, G Hueckel, C Kermarrec, T Tice, G Fitzgibbons, K Walter, D Colavito, T Houghton, N Greco, T Kebede, B Cunningham, S Subbanna, JH Comfort, and EF Crabbe´. A 200 mm SiGe-HBT technology for wireless and mixed-signal applications. Technical Digest IEEE International Electron Devices Meeting, Washington, 1994, pp. 437–440. 47. JD Cressler, EF Crabbe´, JH Comfort, JY-C Sun, and JMC Stork. An epitaxial emitter cap SiGebase bipolar technology for liquid nitrogen temperature operation. IEEE Electron Device Letters 15:472–474, 1994. 48. JA Babcock, JD Cressler, LS Vempati, SD Clark, RC Jaeger, and DL Harame. Ionizing radiation tolerance of high performance SiGe HBTs grown by UHV/CVD. IEEE Transactions on Nuclear Science 42:1558–1566, 1995. 49. LS Vempati, JD Cressler, RC Jaeger, and DL Harame. Low-frequency noise in UHV/CVD Si- and SiGe-base bipolar transistors. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minnneapolis, 1995, pp. 129–132. 50. L Lanzerotti, A St Amour, CW Liu, JC Sturm, JK Watanabe, and ND Theodore. Si/Si1xyGexCy /Si heterojunction bipolar transistors. IEEE Electron Device Letters 17:334–337, 1996. 51. A Schu¨ppen, S Gerlach, H Dietrich, D Wandrei, U Seiler, and U Ko¨nig. 1-W SiGe power HBTs for mobile communications. IEEE Microwave and Guided Wave Letters 6:341–343, 1996. 52. PA Potyraj, KJ Petrosky, KD Hobart, FJ Kub, and PE Thompson. A 230-Watt S-band SiGe heterojunction junction bipolar transistor. IEEE Transactions on Microwave Theory and Techniques 44:2392–2397, 1996. 53. K Washio, E Ohue, K Oda, M Tanabe, H Shimamoto, and T Onai. A selective-epitaxial SiGe HBT with SMI electrodes featuring 9.3-ps ECL-Gate Delay. Technical Digest IEEE International Electron Devices Meeting, San Francisco, 1997, pp. 795–798. 54. HJ Osten, D Knoll, B Heinemann, H Ru¨cker, and B Tillack. Carbon doped SiGe heterojunction bipolar transistors for high frequency applications. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 109–116.



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55. SJ Jeng, B Jagannathan, J-S Rieh, J Johnson, KT Schonenberg, D Greenberg, A Stricker, H Chen, M Khater, D Ahlgren, G Freeman, K Stein, and S Subbanna. A 210-GHz fT SiGe HBT with nonself-aligned structure. IEEE Electron Device Letters 22:542–544, 2001. 56. JS Rieh, B Jagannathan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D Greenberg, S-J Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D Ahlgren, G Freeman, K Stein, and S Subbanna. SiGe HBTs with cut-off frequency of 350 GHz.Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 2002, pp. 771–774. 57. B El-Kareh, S Balster, W Leitz, P Steinmann, H Yasuda, M Corsi, K Dawoodi, C Dirnecker, P Foglietti, A Haeusler, P Menz, M Ramin, T Scharnagl, M Schiekofer, M Schober, U Schulz, L Swanson, D Tatman, M. Waitschull, JW Weijtmans, and C Willis. A 5V complementary SiGe BiCMOS technology for high-speed precision analog circuits. Proceedings of the IEEE Bipolar/ BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 211–214. 58. B Heinemann, R Barth, D Bolze, J Drews, P Formanek, O Fursenko, M Glante, K Glowatzki, A Gregor, U Haak, W Ho¨ppner, D Knoll, R Kurps, S Marschmeyer, S Orlowski, H Ru¨cker, P Schley, D Schmidt, R Scholz, W Winkler, and Y Yamamoto. A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2003, pp. 117–120. 59. J Cai, M Kumar, M Steigerwalt, H Ko, K Schonenberg, K Stein, H Chen, K Jenkins, Q Ouyang, P Oldiges, and T Ning. Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Toulouse, 2003, pp. 215–218. 60. J-S Rieh, D Greenberg, M Khater, KT Schonenberg, J-J Jeng, F Pagette, T Adam, A Chinthakindi, J Florkey, B Jagannathan, J Johnson, R Krishnasamy, D Sanderson, C Schnabel, P Smith, A Stricker, S Sweeney, K Vaed, T Yanagisawa, D Ahlgren, K Stein, and G Freeman. SiGe HBTs for millimeterwave applications with simultaneously optimized fT and fmax. Proceedings of the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Fort Worth, 2004, pp. 395–398. 61. DL Harame and BS Meyerson. The early history of IBM’s SiGe mixed signal technology. IEEE Transactions on Electron Devices 48:2555–2567, 2001. 62. T Tatsumi, H Hirayama, and N Aizaki. Si/Ge0.3Si0.7 heterojunction bipolar transistor made with Si molecular beam epitaxy. Applied Physics Letters 52:895–897, 1988. 63. H Temkin, JC Bean, A Antreasyan, and R Leibenguth. GexSi1x strained-layer heterostructure bipolar transistors. Applied Physics Letters 52:1089–1091, 1988. 64. D-X Xu, G-D Shen, M Willander, W-X Ni, and GV Hansson. n-Si/p-Si1x /n-Si double-heterojunction bipolar transistors. Applied Physics Letters 52:2239–2241, 1988. 65. GL Patton, SS Iyer, SL Delage, S Tiwari, and JMC Stork. Silicon–germanium-base heterojunction bipolar transistors by molecular beam epitaxy. IEEE Electron Device Letters 9:165–167, 1988. 66. A Gruhle, H Kibbel, U Ko¨nig, U Erben, and E Kasper. MBE-Grown Si/SiGe HBTs with high b, fT, and fmax. IEEE Electron Device Letters 13:206–208, 1992. 67. AJ Joseph, D Coolbaugh, D Harame, G Freeman, S Subbanna, M Doherty, J Dunn, C Dickey, D Greenberg, R Groves, M Meghelli, A Rylyakov, M Sorna, O Schreiber, D Herman, and T Tanji. 0.13 mm 210 GHz fT SiGe HBTs—expanding the horizons of SiGe BiCMOS. Technical Digest IEEE International Solid-State Circuits Conference, San Francisco, 2002, pp. 180–182. 68. H. Lilienfeld Patent, 1926; O. Heil, British patent number 439,457, 1935. 69. D Khang and MM Atalla. Silicon–silicon dioxide field induced surface devices. Solid State Research Conference, Pittsburgh, 1960. 70. FM Wanlass and CT Sah. Nanowatt logic using field-effect metal-oxide-semiconductor triodes (MOSTs). IEEE International Solid-State Circuits Conference, Philadelphia, 1963, pp. 32–33. 71. P Balk. Surface properties of oxidized germanium-doped silicon. Journal of the Electrochemical Society 118:494–495, 1971. 72. H Daembkes, H-J Herzog, H Jorke, H. Kibbel, and E Kasper. The n-channel SiGe/Si modulation doped field-effect transistor. IEEE Transactions on Electron Devices 33:633–638, 1986.


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73. TP Pearsall and JC Bean. Enhancement and depletion-mode p-channel GexSi1x modulation-doped field effect transistor. IEEE Electron Device Letters 7:308–310, 1986. 74. H Temkin, TP Pearsall, JC Bean, RA Logan, and S. Luryi. GexSi1x strained-layer superlattice waveguide photodetectors operating near 1.3 mm. Applied Physics Letters 48:963–965, 1986. 75. RD Thompson, KN Tu, J Angillelo, S Delage, and SS Iyer. Interfacial reaction between Ni and MBE grown SiGe alloys. Journal of the Electrochemical Society 135:3161–3163, 1988. 76. HC Liu, D Landheer, M Buchmann, and DC Houghton. Resonant tunneling diode in the Si1xGex system. Applied Physics Letters 52:1809–1811, 1988. 77. RC Taft, JD Plummer, and SS Iyer. Demonstration of a p-channel BiCFET in the GexSi1x /Si system. IEEE Electron Device Letters 10:14 –16, 1989. 78. TJ King, JR Pfriester, JD Scott, JP McVittie, and KC Saraswat. A polycrystalline SiGe gate CMOS technology. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1990, pp. 253–256. 79. RA Soref, F Namavar, and JP Lorenzo. Optical waveguiding in a single-crystal layer of germanium– silicon grown on silicon. Optics Letters 15:270–272, 1990. 80. DK Nayak, JCS Woo, JS Park, KL Wang, and KP MacWilliams. Enhancement-mode quantum-well GexSi1x PMOS. IEEE Electron Device Letters 12:154–156, 1991. 81. K Ismail, BS Meyerson, and PJ Wang. Electron resonant tunneling in Si/SiGe double barrier diodes. Applied Physics Letters 59:973–975, 1991. 82. DC Houghton, JP Noel, and NL Rowell. Electroluminescence and photoluminesence from SiGe alloys grown on (1 0 0) silicon by MBE. Materials Science and Engineering B 9:237–244, 1991. 83. DS Chen, JP Conde, V Chu, S Aljishi, JZ Liu, and S Wagner. Amorphous silicon–germanium thinfilm photodetector array. IEEE Electron Device Letters 13:5–7, 1992. 84. S-B Hwang, YK Fang, K-H Chen, C-R Liu, J-D Hwang, and M-H Chou. An a-Si:H/a-Si, Ge:H bulk barrier phototransistor with a-SiC:H barrier enhancement layer for high-gain IR optical detector. IEEE Transactions on Electron Devices 40:721–726, 1993. 85. DK Nayak, JCS Woo, GK Yabiku, KP MacWilliams, JS Park, and KL Wang. High mobility GeSi PMOS on SIMOX. IEEE Electron Device Letters 14:520–522, 1993. 86. DK Nayak, JCS Woo, JS Park, KL Wang, and KP MacWilliams. High-mobility p-channel metal-oxide semiconductor field-effect transistor on strained Si. Applied Physics Letters 62:2853–2855, 1993. 87. J Welser, JL Hoyt, and JF Gibbons. Electron mobility enhancement in strained-Si n-type metal-oxide semiconductor field-effect transistors. IEEE Electron Device Letters 15:100–102, 1994. 88. SK Ray, S John, S Oswal, and SK Banerjee. Novel SiGeC channel heterojunction pMOSFET. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1996, pp. 261–264. 89. SJ Mathew, WE Ansley, WB Dubbelday, JD Cressler, JA Ott, JO Chu, PM Mooney, KL Vavanagh, BS Meyerson, and I Lagnado. Effect of Ge profile on the frequency response of a SiGe pFET on sapphire technology. Technical Digest of the IEEE Device Research Conference, Boulder, 1997, pp. 130–131. 90. K Rim, JL Hoyt, and JF Gibbons. Transconductance enhancement in deep submicron strained-Si n-MOSFETs. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 1998, pp. 707–710. 91. KC Liu, SK Ray, SK Oswal, and SK Banerjee. Si1xGex /Si vertical pMOSFET fabricated by Ge ion implantation. IEEE Electron Device Letters 19:13–15, 1998. 92. S Thompson, N. Anand, M Armstrong, C Auth, B Arcot, M Alavi, P Bai, J Bielefeld, R Bigwood, J Brandenburg, M Buehler, S Cea, V Chikarmane, C Choi, R Frankovic, T Ghani, G Glass, W Han, T Hoffmann, M Hussein, P Jacob, A Jain, C Jan, S Joshi, C Kenyon, J Klaus, S Klopcic, J Luce, Z Ma, B McIntyre, K Mistry, A Murthy, P Nguyen, H Pearson, T Sandford, R Schweinfurth, R Shaheed, S Sivakumar, M Taylor, B Tufts, C Wallace, P Wang, C Weber, and M Bohr. A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 mm2 SRAM Cell. Technical Digest of the IEEE International Electron Devices Meeting, Washington, 2002, pp. 61–64.



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93. VP Kesan, S Subbanna, PJ Restle, MJ Tejwani, JM Aitken, SS Iyer, and JA Ott. High performance 0.25 mm p-MOSFETs with silicon–germanium channels for 300 K and 77 K operation. Technical Digest of the IEEE International Electron Devices Meeting, San Francisco, 1991, pp. 25–28, 1991. 94. S Verdonckt-Vanderbroek, E Crabbe´, BS Meyerson, DL Harame, PJ Restle, JMC Stork, AC Megdanis, CL Stanis, AA Bright, GMW Kroesen, and AC Warren. High-mobility modulation-doped, graded SiGe-channel p-MOSFETs. IEEE Electron Device Letters 12:447–449, 1991. 95. S Verdonckt-Vanderbroek, E Crabbe´, BS Meyerson, DL Harame, PJ Restle, JMC Stork, and JB Johnson. SiGe-channel heterojunction p-MOSFETs. IEEE Transactions on Electron Devices 41:90–102, 1994.


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3 Overview: Measurement and Modeling


Measurement and modeling of high-speed semiconductor devices is something that, unfortunately, is rarely discussed in a meaningful manner in the technical literature. This is a shame. In my experience, robust measurement and modeling, particularly at the extreme levels of performance found in modern SiGe devices, is a fine art, requires extreme dexterity in the laboratory, and getting reliable data, and importantly, a model to fit the data, is often two thirds of the battle for success (that may be an understatement)! One inevitably sees a nicely presented set of data, and the natural response is ‘‘How did they do that? What tricks did they use? How can I do that for myself ?’’ Alas, often times, one must simply keep on wondering, since such ‘‘tricks-of-the-trade’’ are held close to the vest and rarely divulged. One of the unique features of this handbook is that I have attempted to buck this trend and get some experts to talk about the subtle nuances of the measurement and modeling trade. It is something I am quite proud of, and I suspect will prove to be very useful to practioners. Chapter 4, ‘‘Best-Practice AC Measurement Techniques,’’ by R. Groves of IBM Microelectronics shows how one accurately obtains ac data off of advanced SiGe HBTs. In Chapter 5, ‘‘Industrial Application of TCAD for SiGe Development,’’ by D. Sheridan of IBM Microelectronics, the use of TCAD in device design is addressed. In Chapter 6, ‘‘Compact Modeling of SiGe HBTs: HICUM,’’ by M. Schro¨ter of the University of Dresden, and Chapter 7, ‘‘Compact Modeling of SiGe HBTs: MEXTRAM,’’ by S. Mijalkovic of Delft University of Technology, two of the most sophisticated SiGe HBT compact models are described in detail, and importantly, also address how one should intelligently use them! Integrated circuit design kits are amazingly sophisticated these days, and S. Strang of IBM Microelectronics covers ‘‘CAD Tools and Design Kits,’’ in Chapter 8. Noise coupling and the modeling of such complex effects is often key to success at the circuit level in conductive-substrate silicon-based technologies, and is discussed at length in Chapter 9, ‘‘Parasitic Modeling and Noise Mitigation Approaches in Silicon Germanium RF Designs,’’ by R. Singh of IBM Microelectronics. Given that the frequency response of state-of-the-art SiGe HBTs has reached unprecedented levels, designers are now beginning to seriously attack microwave and even mm-wave applications in SiGe. Key to success in this endeavor is the realization of robust transmission lines in Si, as discussed in Chapter 10, ‘‘Transmission Lines on Si,’’ by Y. Tretiakov of RF Micro Devices. Finally, accurate on-wafer de-embedding of parasitics to mm-wave frequencies is covered in Chapter 11, ‘‘Improved De-embedding Techniques,’’ by Q. Liang of Georgia Tech.

3-1




Cressler / Measurement and Modeling of Silicon Heterostructure Devices 66927_C004 Final Proof page 1 18.10.2007 1:19pm Compositor Name: JGanesan

4 Best-Practice AC Measurement Techniques 4.1 4.2

AC Device Measurement Techniques: Overview .............................................................................. 4-1 AC Measurement Techniques............................................. 4-2

4.3

Summary ............................................................................ 4-11

Robert A. Groves IBM Microelectronics

4.1

S-Parameter Measurement . C–V

AC Device Measurement Techniques: Overview

Development of high-quality device models is an essential ingredient in the design of successful analog and mixed-signal applications. Accurate device characterization plays a critical role in model development and circuit benchmarking. Model behavior must be verified against device measurements in order to validate the model and to define regions outside which the model may be inaccurate. The characterization of high-performance silicon heterostructures, and associated passives, requires care due to the demanding requirements associated with these devices: high frequencies, low leakage currents, low resistances, wide temperature ranges, etc. An area of particular concern and interest to device modelers and circuit designers is the improvement of the S-parameter measurement methodology as the measurement frequency extends to 100 GHz and beyond. Traditional calibration and de-embedding techniques need to be re-examined to determine if the underlying assumptions remain valid [1,2]. In addition to characterization in support of model development, circuits must be measured and compared to design predictions and requirements. Circuit measurement is particularly demanding for applications utilizing SiGe devices due to the high-frequency and low-noise characteristics of these designs [3,4]. Frequently, off-the-shelf measurement solutions do not exist to satisfy the characterization requirements for these cutting-edge circuits, requiring circuit designers to assume the role of test system developer. Preceding all these requirements is the necessity to create carefully controlled device measurement test structures that allow for accurate extraction of the desired device and circuit parametrics. Careful thought must be given to the limitations inherent in creating low parasitic test structures in a wafer-probing environment. This includes the creation of additional test structures that allow for the accurate characterization of the test structure parasitics, so that the device characteristics can be accurately de-embedded from the measured data [5,6].

4-1


4-2

4.2


AC Measurement Techniques

S-Parameter Measurement Why S-Parameters The demands of high-frequency device modeling and characterization of device under test (DUT) behavior require a test system that is able to provide detailed information about DUT performance characteristics over a broad range of frequencies (DC to 100 GHzþ). Often the linear behavior of the DUT to a test signal is needed in order to characterize or model its behavior. A test system that is able to accurately report the network parameters of an unknown linear network to an applied signal is required for these high-frequency measurements. Some network parameters appropriate to characterization and modeling of silicon heterostructures, passives, and circuits are H-parameters (hybrid parameters), Y-parameters (admittance parameters), Z-parameters (impedance parameters), S-parameters (scattering parameters), and T-parameters (transmission parameters). Each of these network parameter sets describes the response of the DUT to a defined set of input conditions. H-parameters, for instance, are widely used to determine HBT device characteristics. They are useful for this purpose because the equations describing the H-parameters can naturally be used to determine short-circuit current gain or b (in addition to other useful device parametrics). Network parameters are applicable generally to N-port networks. Most applications of network parameters are limited to between two- and four-port networks. Since many circuits and devices have two well-defined ports, two-port networks are quite often the most useful in determining DUT characteristics. The two-port network shown in Figure 4.1 is labeled as is customary, with the upper terminals at positive potential with respect to the lower terminals and the currents defined as flowing into the two upper terminals and out of the two lower terminals. Under conditions of applied stimulus to one of the ports and defined termination of the other port, the response of the network can be characterized in terms of the voltage and current relationships observed at the ports. For a two-port network, two equations completely define the network characteristics as a function of the applied stimuli and measured voltages and currents and some constants of proportionality (simply the network parameters themselves). For H-parameters, the following relationships define the interaction between the voltages, currents, and H-parameters [7]: V 1 ¼ h11 I 1 þ h12 V 2 I 2 ¼ h21 I 1 þ h22 V 2 V 1 V1 h11 ¼ h12 ¼ I 1 v2 ¼0 V2 I1 ¼0 I2 I2 h21 ¼ h22 ¼ I 1 v2 ¼0 V 2 I1 ¼0 I1

(4:1)

I2

+

+

V1 −

Linear network

V2 −

FIGURE 4.1 Two-port network representation of a linear-time-invariant (LTI) system with conventional representation of applied voltages and measured currents.


4-3

Best-Practice AC Measurement Techniques

These H-parameters can be derived directly through measurement of the two-port network, by applying the appropriate terminal conditions and monitoring the voltages and currents. H11, for instance, can be directly measured by applying a voltage (V1) to port 1, shorting port 2 to ground (V2 ¼ 0) and measuring the current flowing into port 1 (I1). Similarly, the other three H-parameters can be derived from physical measurements by simply applying the appropriate voltages and currents and setting one of the ports to either an open- or short-circuit condition as required by the definitions in Equation 4.1. A problem arises in applying this direct measurement technique at high frequencies. It is difficult to achieve perfect short or open circuits at the device terminals due to the parasitics associated with the connections between the measurement instruments and the device. These parasitic capacitances, resistances, and inductances combine to make the characteristics of open- and short-circuit connections strong functions of frequency. Therefore, a short circuit at one frequency may appear to be an open circuit at another, etc. This makes the broadband, direct measurement of many of the network parameters difficult. Another difficulty comes into play with active devices. Even if perfect broadband open and short circuits were achievable, silicon heterostructures may not be stable under conditions of open- and short-circuit termination of their terminals due to high gain and low parasitic resistances. The solution to this dilemma is to make device measurements using a set of network parameters that make use of applied bias and termination conditions that are easily achievable at high frequencies and that lend themselves to stable device operation. S-parameters satisfy these requirements. S-parameters are defined similarly to the previously described network parameters except that the applied bias conditions are defined in terms of traveling voltage waves, rather than total voltages and currents, and the termination conditions are defined in terms of the characteristic impedance of the transmission lines supplying these traveling waves, rather than open and short circuits. Figure 4.2 shows a two-port network with loss-less transmission lines supplying a traveling wave from a generator to port 1 and connecting a terminating impedance to port 2. The traveling voltage wave incident on port 1 will generate a reflected wave traveling back toward the source due to impedance mismatch between port 1 of the DUT and the transmission line. In addition, some of the energy will be transmitted through the network to port 2 and travel down the transmission line toward the load impedance. A voltage wave will then be reflected from the load toward port 2 (assuming that the load impedance is not equal to the characteristic impedance of the line), some of which will be transmitted back through the network and travel down the port 1 transmission line toward the generator where it will be either reflected or absorbed. Further reflections occur as each of these reflected voltage waves encounter an impedance mismatch or discontinuity. This complex combination of forward and reflected waves on the transmission lines connected to ports one and two will generate standing voltage waves.

a1 =

E1i

a2 =

√Z0 E1i

Z0

Z0

b1 =

E1r √Z0 E1i

E2i √Z0 E1i

Z0

Linear network s

ZL

b2 =

E2r √Z0 E1i

FIGURE 4.2 Two-port network representation used to describe S-parameters of a DUT. Loss-less transmission lines connect the DUT to the applied signal and load termination.


4-4


The relationships equating these voltage waves at the two DUT pffiffiffiffi ports and the S-parameters are indicated here [7] (the voltage waves are normalized by dividing by Z 0 for computational convenience): b1 ¼ s11 a1 þ s12 a2 b2 ¼ s21 a1 þ s22 a2 E1i E1r a1 ¼ pffiffiffiffiffi b1 ¼ pffiffiffiffiffi Z0 Z0 E2i E2r a2 ¼ pffiffiffiffiffi b2 ¼ pffiffiffiffiffi Z Z0 0 b1 b1 s11 ¼ s12 ¼ a1 a2 ¼0 a2 a1 ¼0 b2 b2 s21 ¼ s22 ¼ a1 a2 ¼0 a2 a1 ¼0

(4:2)

The constraining conditions that describe each individual S-parameter (i.e. a2 ¼ 0 for S11 and S21) are achieved by setting the appropriate reflection coefficient (G ¼ Ereflected / Eincident) to zero. This implies that the voltage wave is totally absorbed by a load impedance that is equal to the characteristic impedance of the transmission line. Thus, the two load conditions that must be achieved in order to directly measure the four S-parameters are as follows: 1. A load has been put in place of the generator of Figure 4.2 and a generator is applying a signal to port 2 through the transmission line. The condition a1 ¼ 0 implies that the load impedance on the port 1 transmission line is equal to the Z0 of that line, fully absorbing the voltage wave traveling toward the port 1 load. 2. The circuit of Figure 4.2 is achieved, with the load impedance on port 2 equal to the Z0 of the transmission line connected to port 2, absorbing the voltage wave incident on the load and setting the reflected wave to zero (a2 ¼ 0). These load conditions in a typical S-parameter measurement system are equal to 50 V, since the transmission lines connecting the measurement instrument and the DUT are generally 50 V transmission lines. This condition is much easier to achieve over a broad range of very high frequencies and contributes to a more stable measurement environment for high gain devices. Measuring the S-parameters of a DUT, then, consists of measuring the complex voltage waves present at the DUT ports under the conditions of an applied voltage wave transmitted through a loss-less transmission line toward one port and the termination of the other ports with a 50 V load (for a 50 V measurement system). While this is simpler than achieving the requirements for directly measuring a set of network parameters defined in terms of total voltages and currents (implying that perfect open- and short-termination conditions must be realized), there are still difficulties in achieving accurate measurements representative of the conditions at the DUT ports due to nonideal measurement conditions. For example, the transmission line connecting the measurement instrument and DUT has losses and may not have a Z0 of exactly 50 V, making it nonideal; reflections occur where cables, waveguides, or wafer probes connect to the measurement system and the DUT due to impedance mismatches; the 50 V load termination has frequency-dependent behavior and is not exactly 50 V; the generator does not have a perfect 50 V impedance; the equipment required to sample and measure the incident and reflected voltage waves causes additional losses and distortions; when making on-wafer measurements, the probe pads and transmission line launches introduce further errors. The procedures used to extract the DUT port characteristics from the raw measured S-parameters are called calibration and de-embedding. Instrumentation The measurement of S-parameters is most commonly performed using a test instrument called a vector network analyzer (VNA). These are typically configured to measure one-, two-, or four-port



4-5

S-parameters. Fully automated VNAs, able to measure more than one-port S-parameters, typically contain switching elements that allow for either a signal or load to be applied to each port in turn enabling the measurement of the multiport S-parameters with no manual intervention. In addition, a means of calibrating out the parasitics associated with connecting the VNA to a DUT is generally provided as an internal procedure that can be implemented from the instrument front panel or through a network connection by a host computer. Figure 4.3 shows an on-wafer, semi-automated S-parameter measurement system capable of measuring S-parameters up to 110 GHz. Calibration Since all voltage-wave measurements must, of necessity, be made in the VNA itself, a means of accounting for the effects of the nonideal transmission lines and other parasitics, present between the VNA measurement transducers and the DUT ports is required. In the simplest sense, VNA calibration makes use of the concept of a shifted reference plane to enable the direct measurement of the DUT port characteristics. Figure 4.4 shows the measurement setup of Figure 4.2 with the addition of a four-port S-parameter matrix (S 0 ) representing the actual transmission lines, and their associated loss and coupling parasitics, connecting the VNA to the DUT measurement ports. The measurement reference plane defines the actual ports of the uncalibrated, measured S-parameters and exists somewhere in the interior of the VNA itself. The DUT reference plane represents the desired location of the DUT ports such that the measured S-parameters, shifted to the DUT reference plane, represent the desired terminal characteristics of the DUT. This implies that 16 error terms (the S-parameters of the four-port matrix S 0 ) must be determined during calibration in order to fully describe the four-port error network. Once the 16 error terms are known, the DUT S-parameters can be extracted from the measured S-parameters using matrix manipulation. This removal of the effects of the S 0 network is known as ‘‘shifting the reference plane to the DUT ports.’’ In practice, the error network is passive implying that it is reciprocal and that S 0 ¼ S 0 T. This means that the eight S-parameters representing signal transmission through the network are equal in both the forward and reverse directions (i.e., S13 ¼ S31, etc.). A reciprocal fourport network, then, can be fully qualified with 12 error terms, since four of them will be redundant. This is, in essence, how the standard VNA 12-term error model is derived [8]. Calibration consists of measuring known standards located at the DUT reference plane and then applying algorithms to determine the 12 error terms. For wafer-level calibration, there are two main techniques:

FIGURE 4.3 Agilent N5250A 110 GHz VNA measurement system connected to a Cascade Microtech Summit semi-automated wafer probing system for characterizing on-wafer devices to 110 GHz. (Copyright 2004, Agilent Technologies, Inc. Reproduced with permission of Agilent Technologies.)


4-6


S9 (4-port)

Measurement reference plane

Linear network S

DUT reference plane

DUT reference plane

Measurement reference plane

Z0

ZL

S meas

FIGURE 4.4 Representation of desired DUT network (S) embedded in a four-port error network (S 0 ) representing the nonideal measurement environment present between the VNA and the DUT.

1. Let the four-port error network represent the environment between the VNA and the probe tips.

a. Shift the reference plane to the probe tips followed by an additional step called deembedding that is designed to characterize and remove any additional parasitics that might exist between the probe pads and the DUT. 2. Let the four-port error network represent the environment between the VNA and the actual DUT ports. a. Shift the reference plane directly to the DUT ports by measuring standards at the end of the signal launches that exist between the probe pads and the DUT. Each approach requires that the 12 unknown error terms be determined to a great degree of accuracy. The first approach requires the additional determination of the parasitic behavior of the probe pads and transmission line launches connecting the probes to the DUT. Determination of the error terms is done in a similar manner regardless of the desired location of the corrected reference plane. If the reference plane is desired to be at the probe tips (method 1), then the calibration standards may be realized either on-wafer or on a separate calibration substrate. In order to shift the reference plane directly to the DUT ports (method 2), the calibration standards must be realized on-wafer, in close proximity to the DUT. There are several different techniques that can be used to achieve the desired reference plane shift, generally named according to the calibration standards required to achieve the calibrations [9,10]: .

.

SOLT (Short-Open-Load-Thru) a. Requires accurate knowledge of actual characteristics (parasitic inductance and capacitance) of cal standards up to the highest frequency of operation.

b. Used successfully to 50 GHz and beyond, but sensitive to probe placement at higher frequencies, making measurement repeatability a problem. SOLR (Short-Open-Load-Reciprocal) a. Same requirements as SOLT, but only constraint on Reciprocal standard is that S12 ¼ S21. Typically used in applications where probes cannot be placed such that they are 1808 opposed



.

.

4-7

(i.e., both probes in the same plane, or one port rotated 908 with respect to the other), requiring that the Thru standard have a bend. b. Accuracy suffers in relation to SOLT cals [11]. TRL (Thru-Reflect-Line) a. Multiple different line lengths (probe spacing variable) required to provide broadband calibration (i.e., three line lengths required to cover 2 to 18 GHz range). b. Characteristic impedance of lines defines reference impedance of resulting S-parameters. c. Extending frequency range below 5 GHz requires excessively long transmission lines as cal standards and may sacrifice accuracy. d. Dispersion effects on the transmission line Z0 can limit effectiveness [12]. e. NIST-TRL technique provides high accuracy over valid frequency range. LRM/LRRM (Line-Reflect-Match, Line-Reflect-Reflect-Match) a. Thru delay and Match resistance must be known. b. Match reactance adjusted to achieve best-calibrated open response. c. Match resistance defines reference impedance of resulting S-parameters. d. Less sensitive to probe placement.

While shifting the measurement reference plane directly to the DUT terminals in one step is desirable, in practice this technique is difficult to implement due to problems associated with achieving acceptable calibration standards on-wafer. Match standards (typically 50 V resistors) are difficult to achieve with sufficient tolerance and low parasitics. Off-wafer match standards are laser trimmed to within 0.5% of 50 V, while on-wafer resistors with tolerances better than 10% are very difficult to realize and usually have significant capacitive parasitics. Transmission lines realized on Si wafers display excessive dispersion and loss effects for characteristic impedances near 50 V and for lines long enough to allow for reasonably low-frequency measurements. Additionally, transmission line standards, with sufficient length to allow measurement as low as 5 GHz, require large chip areas due to their excessive length. For these reasons, the first approach mentioned above (calibration to probe tips followed by on-wafer de-embedding) is the de facto standard for calibrating on-wafer S-parameter measurements. Utilizing this ‘‘probe-tip’’ cal approach has a drawback to achieving high accuracy in the final calibrated DUT S-parameters. The parasitic capacitance to ground and probe-to-probe coupling (primarily through the substrate) experienced by the probe when measuring the cal standards of the off-wafer cal substrate (typically an insulating alumina substrate) will be different than those seen when probing the DUT on-wafer (typically lossy Si substrate). This difference will result in systematic errors that will not be accounted for in the probe-tip cal. This systematic error can be minimized through careful measurement structure design. The most common two approaches used for probe-tip calibrations are LRRM and SOLT. TRL and SOLR calibrations have drawbacks in bandwidth and accuracy that generally preclude their use except in special circumstances. Proper choice of calibration and de-embedding techniques, then, is a major factor in achieving accurate S-parameter measurements to 100 GHz and beyond. De-Embedding The procedure used most frequently for on-wafer de-embedding of DUT characteristics from probe-tip calibrated measurements makes use of on-wafer standards designed to represent the parasitic environment around the DUT [13–18]. Figure 4.5a shows a typical on-wafer S-parameter probe-pad environment used to measure silicon heterostructures. This layout is optimized for two-port probing with ground-signal-ground (GSG) microwave probes. The GSG probes provide a means of launching a coplanar voltage wave onto the probe pads from the primarily coaxial transmission environment that exists between the VNA and the probes [19]. The S-parameter padset is designed to minimize the parasitic capacitance, resistance, and inductance that will need to be de-embedded from the measured S-parameters. The signal pad is made as small as possible while still providing enough metal landing area to completely land the microwave probe tip without overhanging the sides of the pad, as an overhanging probe provides additional parasitic capacitance that must be de-embedded. A conductive groundplane


4-8


(running from the top ground strap to the bottom ground strap at each port) is often provided underneath the signal pad, providing a well defined, low impedance return path for the parasitic electric field of the pad. This ground return path can be constructed of any material with reasonable conductivity, such as silicided polysilicon or a metal layer, such as M1. The various parasitic elements associated with the padset are added to the padset of Figure 4.5a and represented in Figure 4.5b. The schematic representation of the padset parasitics alone can be seen in Figure 4.5c. As can be seen from Figure 4.5c, the parasitic network represented by the elements labeled G1 and G2 (pad to groundplane capacitive and resistive parasitics), and G3 (port 1-to-port 2 capacitive and resistive parasitics) is connected in parallel with the DUT. On the other hand, the network consisting of Z1 and Z2 (port-to-DUT series resistive and inductive parasitics), and the network represented by Z3 (DUT third terminal-to-ground resistive and inductive parasitics) are in a series connection with the DUT terminals. This grouping of the padset parasitics into two networks, Z representing the combined series connected parasitics and G representing those parasitics that show up in parallel with the DUT, allows us to effectively remove (or minimize) the effects of the parasitics through the procedure called deembedding. The standards used to facilitate the de-embedding process are designed to represent either the parallel (G) parasitics, called the ‘‘Open Standard’’, or the series (Z) parasitics, called the ‘‘Short Standard.’’ The basic procedure is called Open-Short de-embedding. The Open standard is created by simply removing the DUT from the complete padset of Figure 4.5a, while the Short standard is created by replacing the DUT with a metal shorting piece that shorts the port 1 and port 2 connections to each other and to ground. Proper design of these standards is crucial to achieving accurate de-embedding of the padset parasitics up to very high frequencies. In order for OpenShort de-embedding to provide valid results, the padset must be designed to have an electrical behavior that closely mimics the schematic of Figure 4.5c. Any series or parallel paths not accounted for in the schematic should be minimized as much as possible (i.e., the impedance of the ground straps separating ports one and two should be made as small as possible, since this is represented as a zero impedance node in the schematic). If the padset is made to mimic the schematic as closely as possible and the parasitics are reduced to as low a value as possible, Open-Short de-embedding can provide valid results to 100 GHz. Above 100 GHz and for padsets that, due to their larger than normal size (as in spiral inductors) do not adhere to the schematic, further de-embedding methods may be required [1,2]. The de-embedding procedure consists of the following steps: 1. Measure the S-parameters of the DUT embedded in the padset (Smeas). 2. Measure the S-parameters of the Open and Short de-embedding standards (Sopen and Sshort, respectively). 3. Convert Sopen and Sshort to Y-parameters (Yopen and Yshort, respectively). Subtract Yopen from 0 (the Y-parameters of the short standard with the parallel capacitive and Yshort to yield Yshort resistive contribution from the pads and substrate removed). 0 0 0 to Zshort . Zshort now represents the combined network consisting of the three 4. Convert Yshort series impedances (Z1, Z2, and Z3). 0 (the Y-parameters of the DUT 5. Convert Smeas to Ymeas and subtract Yopen from it. This yields Ymeas with the parallel capacitive and resistive contribution from the pads and substrate removed). 0 0 to Zmeas which still contains the series impedances associated with Z1, Z2, and Z3 Convert Ymeas in addition to the desired DUT terminal characteristics. 0 0 00 from Zmeas to yield Zmeas (the Z-parameters of the DUT in the absence of all 6. Subtract Zshort 00 00 back into fully padset corrected S-parameters (Smeas ) padset parasitics) and finally, convert Zmeas for analysis of the DUT terminal characteristics. In addition to creating an ideal padset structure, another condition must be satisfied in order to be able to achieve valid results from Open-Short de-embedding. The network parameters representing the Open, Short, and DUT measurements must be linear and time invariant (LTI) in nature. This is not a problem for the Open and Short standards, as they are passive networks and, therefore, satisfy the LTI requirements. The DUT network parameters are LTI only under certain conditions, the most important


4-9


nd ou Gr lane p

nd ou Gr lane p

M3 M2 M1

(a)

nd ou Gr ane pl

M3 M2 M1

nd ou Gr ane pl

(b)

G3 Z1

Z2 DUT

G1

Z3

G2

(c)

FIGURE 4.5 (a) S-parameter measurement padset showing probe landing pads and connections between the probe pads and the DUT. (b) S-parameter measurement padset of (a) with schematic symbols representing padset parasitics and their general physical location. (c) Schematic representation of S-parameter padset parasitics with the physical structure removed for clarity.


4-10

page 10



of which is that the DUT is behaving linearly with applied input power (i.e., the network parameters are not dependent on input power level). This condition holds true when the input power level is low enough to ensure that the device gain remains linear with input power. Above this threshold input power level, the device no longer behaves as an LTI system, and the de-embedding procedures are no longer valid. Power-Level Selection Recall that the network parameters for a DUT are defined with the condition that the DUT behaves as a linear system. For example, if the device cannot linearly translate the input to the output (i.e., experiences gain compression), then the resulting S-parameters will no longer be valid. This concept applies to all four S-parameters, not just S21. If a particular S-parameter changes significantly with varying power level, the device can be said to be operating nonlinearly, negating the validity of the Sparameters. A simple test for this is to display the S-parameter of interest while the device is biased in its operational region. Divide the display data, using the VNA display math functions, by itself to yield a flat curve with a value of 0 dB across the frequency range of interest. Next change the power level in stages and observe the resulting curve. At some point the curve will begin to deviate from a flat 0 dB line. The magnitude of this deviation in dB is a measure of the nonlinearity of the device at that power level. For a range of power levels, there will exist a power level below which the S-parameters will no longer change. This is the highest power level that should be applied to the device while still assuring linear behavior. Power levels significantly below this level should be avoided for a different reason. The VNA has a noise floor that is a function of various settings and the internal instrumentation itself, the dynamic range of the VNA measurement is the difference between the measured power level and the noise floor. A high dynamic range is desired as it implies less noise present in the measured results. One further caution should be observed with regard to power levels. DUTs with high gain (many silicon heterostructures) may raise the output power level enough to overload the receiver on the input of the VNA. Judicious choice of input power levels, and possibly attenuation on the output, should be used to avoid this overload condition, which will affect the accuracy of the measured results. Therefore, appropriate choice of measurement power level is critical to achieving accurate S-parameters for silicon heterostructures. Some incorrect power conditions will be obvious (i.e., VNA receiver overload), while others will not (i.e., nonlinear behavior of the DUT or excessive noise in the data due to reduced dynamic range).

C–V For certain measurement situations, determination of device capacitance or inductance through S-parameter measurements is not required. Capacitance and inductance characteristics versus voltage or current bias can be achieved through the use of an impedance measurement system. This method is only suitable for measuring device characteristics that can be well described by a simple model consisting of resistors, capacitors, and inductors in various series and parallel configurations. The instrument essentially measures the magnitude and phase response of the DUT to an applied AC and DC bias (frequencies typically less than 10 MHz) and then applies a model (i.e., a capacitor in parallel with a conductance) to the data to report element values for the model (capacitance and conductance in this example). Different models will be appropriate for different device characteristics. For example a large capacitor with a nonnegligible series resistance might benefit from extracting the capacitance and resistance from a series R-C model. The model is typically chosen such that the reactive component characteristics can be extracted from the imaginary part of the measured impedance without having a strong variation in value over a certain range of frequencies. Different models may be appropriate for the same device at different measurement frequencies. Proper selection of the measurement model and frequency of measurement is crucial to getting meaningful data from an impedance measurement system [20].



4.3

page 11


4-11

Summary

Accurate high-frequency measurement capabilities and practices are crucial to the development and modeling of silicon heterostructures and their associated circuits. A basic understanding of S-parameters and the role they play in determining device and circuit characteristics is important for the laboratory technician, device development engineer, device modeler, and circuit designer. Proper interpretation of S-parameter and low-frequency C–V measurement data provides the engineer with the information needed to make informed decisions in the technology development and product design processes. An understanding of the assumptions used in the calibration, de-embedding and reporting of high-frequency data allows the engineer to use the information wisely, discarding information that may be based on invalid assumptions. This chapter has attempted to lay the groundwork for interpreting high-frequency data acquired in the RF laboratory. In addition some effort has been made to describe the requirements for creating effective on-wafer measurement pad structures that minimize the parasitics that must be de-embedded from measured data. Properly designed pad structures allow for more accurate de-embedding of measured device characteristics, resulting in data that accurately represent the DUT terminal characteristics.

References 1. Q. Liang, J.D. Cressler, G. Niu, Y. Lu, G. Freeman, D. Ahlgren, R.M. Malladi, K. Newton, and D.L.Harame. A simple 4-port parasitic de-embedding methodology for high-frequency characterization of SiGe HBTs. IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, June 2003, pp. 357–360. 2. L.F. Tiemeijer, J. Ramon, and Havens. A calibrated lumped-element de-embedding technique for on-wafer RF characterization of high-quality inductors and high-speed transistors. IEEE Transactions on Electron Devices 50(3), 2003, 822–829. 3. J. Kim, J.-O. Plouchart, N. Zamdmer, N. Fong, M. Sheronv, Y. Tan, M. Talbi, R. Trzcinski, J. Safran, K. Wu, S. Womack, J. Sleight, C. Sheraw, A. Ray, and L. Wagner. Highly manufacturable 40–50 GHz VCOs in a 120 nm system-on-chip SOI technology. IEEE International Electron Devices Meeting, December, 2003, pp. 15.3.1–15.3.4. 4. G. Freeman, M. Meghelli, Y. Kwark, S. Zier, A. Rvlyakov, M.A. Sorna, T. Tanji, O.M. Schreiber, K. Walter, J.-S. Rieh, B. Jagannathan, A. Joseph, and S. Subbanna. 40-Gb/s circuits built from 120 GHz f.sub T/SiGe technology. IEEE Journal of Solid State Circuits 37(9), 2002, 1106–1114. 5. T.E. Kolding. Shield-based microwave on-wafer device measurements. IEEE Transactions on Microwave Theory and Techniques 49(6), 2001, 1039–1044. 6. T.E. Kolding, O.K. Jensen, and T. Larsen. Ground-shielded measuring technique for accurate onwafer characterization of RF CMOS devices. Proceedings of the International Conference on Microelectronic Test Structures, Monterey, CA, 2000, pp. 246–251. 7. Agilent Technologies, Inc. Agilent AN 154 S-Parameter Design. Agilent Technologies, Inc. Application Note, 2000. 8. Agilent Technologies, Inc. Agilent AN 1364-1 De-Embedding and Embedding S-Parameter Networks Using a Vector Network Analyzer. Agilent Technologies, Inc. Application Note, 2001. 9. Cascade Microtech, Inc. On-Wafer Vector Network Analyzer Calibration and Measurements. Cascade Microtech, Inc. Application Note, 1997. 10. A.M.E. Safwat and L. Hayden. Sensitivity analysis of calibration standards for fixed probe spacing on-wafer calibration techniques. IEEE Microwave Theory and Techniques Symposium Digest, 2002, pp. 2257–2260. 11. S. Basu and L. Hayden. An SOLR calibration for accurate measurement of orthogonal on-wafer DUTs. IEEE Microwave Theory and Techniques Symposium Digest, Denver, CO, January 1997. 12. P.C. Walters, R.D. Pollard, J.R. Richardson, and B.M. Byzery. The effects of process variations on microstrip wafer calibration. Proceedings of IEEE Instrument and Measurement Technology Conference, May 1993, pp. 118–122.


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13. M.C.A.M. Koolen, J.A.M. Geelen, and M.P.J.G. Versleijen. An improved de-embedding technique for on-wafer high-frequency characterization. Proceedings of the Bipolar Circuits and Technology Meeting, Minneapolis, MN, September 1991, pp. 188–191. 14. H. Cho and D.E. Burk. A three-step method for the de-embedding of high-frequency S-parameter Measurements. IEEE Transactions on Electron Devices 38(6), 1991, 1371–1375. 15. S. Bousnina, C. Falt, P. Mandeville, A.B. Kouki, and F.M. Ghannouchi. An accurate on-wafer deembedding technique with application to HBT devices characterization. IEEE Transactions on Microwave Theory and Techniques 50(2), 2002, 420–424. 16. T.E. Kolding. General accuracy considerations of microwave on-wafer silicon device measurements. IEEE Microwave Theory and Techniques Symposium Digest, 2000, pp. 1839–1842. 17. T.E. Kolding. On-wafer calibration techniques for giga-Hertz CMOS measurements. IEEE International Conference on Microelectronic Test Structures 12, 1999, 105–110. 18. T.E. Kolding. A four-step method for de-embedding gigahertz on-wafer CMOS measurements. IEEE Transactions on Electronic Devices 47(4), 2000, pp. 734–740. 19. S.A. Wartenberg. Selected topics in RF coplanar probing. IEEE Transactions on Microwave Theory and Techniques 51(4), 2003, 1413–1421. 20. Agilent Technologies, Inc. Agilent Technologies, The Impedance Measurement Handbook. Agilent Technologies, Inc. Application Note, 2003.


5 Industrial Application of TCAD for SiGe Development 5.1 5.2

Introduction......................................................................... 5-1 SiGe Process Simulation ..................................................... 5-2 Emitter Out-Diffusion . Boron Diffusion in SiGe Epitaxial Layer Base

5.3

David C. Sheridan, Jeffrey B. Johnson, and Rajendran Krishnasamy IBM Microelectronics

5.1

SiGe Device Simulation ...................................................... 5-6 DC Calibration . AC Extraction and Calibration . Advanced RF Simulations

5.4 5.5 5.6

Application Examples ......................................................... 5-8 Predictive Model Extraction............................................. 5-10 Summary ............................................................................ 5-12

Introduction

Due to rapid evolution of semiconductor technologies, the use of technology computer-aided design (TCAD) has become a critical enablement path in the industrial development cycle. The capability to perform numerical process and device simulation that is able to accurately predict device performance under various process conditions can significantly reduce the time and cost of technology development. With experimental wafer processing costs increasing dramatically for advanced generation technologies, the economic necessity for accurate predictive TCAD is apparent. But it is not only the wafer cost and device complexity that is continuing to drive the need for accurate predictive SiGe TCAD. Unlike the high-performance CMOS logic that can have years between products, the analog and mixed-signal market that encompasses the majority of SiGe applications demands significantly reduced product cycle time. This aggressive development schedule is generating a new paradigm for the relationship between TCAD, process development, and circuit designers. The traditional relationship of TCAD with technology development (Figure 5.1) consisted of having SIMS profiles, TEMs, and various other physical and electrical measurements provided to the TCAD engineer to calibrate the process and device models in parallel to the process development effort. The flow is then iterated until target device characteristics are achieved and representative hardware can be furnished to the compact modeling team. The compact modeling team must then fully characterize the devices to generate a physically based model parameter set, which is then combined with the complete technology design kit. Even if the process of record is known, circuit designers cannot begin to design for a significant period of time before the processing, characterization, and design kit cycle is complete. It is in this regard that TCAD can be used to impact the product design cycle time independent of the benefits contributed by increased process development time (Figure 5.1). With accurate process and device simulation early in the development cycle the TCAD engineer can create the electrical device 5-1


5-2

TCAD flow

Technology definition

Calibration

Process experiments

Process simulations

Evaluate experiments

Device simulations

TARGETS?

TARGETS?

Qualification hardware

Model creation

Model creation

Designer lead time

}

3−8 months

Design kit to designers

Models to designers

Traditional TCAD role

1 month

3−6 months

Technology flow

1 WEEK

1− 4 months


FIGURE 5.1 Flow diagram showing the traditional TCAD relationship with technology development and the new extended paradigm.

characteristics to derive a initial predictive compact model. A compact model can then be provided to circuit designers in substantially earlier timeframe than traditionally available, based on calibrated physical simulations. As the technology development progresses, updates to the compact models can be provided to ensure the designers will have minimal design impact from the initial models to the final hardware-based models. The following sections demonstrate this new methodology with an overview of the TCAD process, device, and compact modeling strategy successfully employed in developing state-ofthe-art SiGe technologies.

5.2

SiGe Process Simulation

Bipolar technologies dominated the early years of the microelectronics industry, and significant industrial and academic effort was focused on impurity diffusion characteristics that affected the vertical emitter–base–collector profiles of the bipolar transistor structures [1]. The incorporation of models that account for the co-diffusion of point defects (interstitials and vacancies) with dopant impurities addressed the important physical effects of oxidation-enhanced diffusion and transient-enhanced diffusion, forming the basis for the impurity diffusion models used in modern silicon process simulation programs. Such programs combine many different physical modeling capabilities including oxidation, diffusion of various dopants and their interactions, etching, deposition, and various approaches to simulating ion implantation.


Industrial Application of TCAD for SiGe Development

5-3

The emergence of SiGe BiCMOS technologies has again made bipolar transistor simulation an important part of the demand for state-of-the-art process simulation capability. SiGe BiCMOS technologies utilize many of the same process operations as CMOS devices, and therefore, benefit directly from the accrual of simulation expertise gained from years of detailed submicron CMOS process modeling research. In the following discussion, it is assumed that the goal is not merely to generate an idealized SiGe HBT structure, for which task-detailed process simulation is not required, but rather to address the issue that dominates practical industrial applications of process and device simulation for SiGe BiCMOS technologies. Issues related to lateral diffusion of impurities generally dominate CMOS process simulation development, and the resultant physical models are equally applicable to issues related to vertical impurity diffusion profiles critical to SiGe HBT simulation. However, process simulation for SiGe HBTs is distinguished from CMOS process simulation by its critical dependence on Si–Si1x GexSi epitaxy and the interaction of polysilicon on silicon in the formation of the emitter and base structures. The challenge for SiGe HBT process simulation is to accurately simulate SiGe epitaxy and heavily doped polysilicon–silicon systems and combine this capability with the CMOS-specific process operations that dominate a modern SiGe BiCMOS technology.

Emitter Out-Diffusion Polysilicon is generally used to form the emitter region of modern high-speed SiGe HBTs as the polysilicon has a significantly lower surface recombination velocity to maintain high current gain with the continually scaled emitter diffusion depths. The emitter polysilicon is generally formed by a lowtemperature epitaxial process to reduce thermal effects on existing CMOS components, with impurities added either in situ during epitaxy or by ion implantation. The subsequent annealing and out-diffusion of the emitter dopants into the SiGe epitaxy creates the HBT emitter–base region. This positioning of the intersection of the emitter diffusion with germanium profile and both intrinsic and extrinsic base regions is fundamental in determining the transistors DC and AC characteristics. This annealing and out-diffusion of the emitter dopants, and their impact on the other dopant profiles under the emitter, is a complex combination of physical phenomena. Process-dependent physical effects such as arsenic (As) or phosphorus (P) deactivation mechanisms between As or P and vacancies, diffusion of dopants through interfacial oxide layers between the polyemitter and silicon, As or P clustering mechanisms, and diffusion differences of As or P in Si and strained or relaxed SiGe must be considered in the process simulation modeling to predictively fit the As or P emitter out-diffused profiles. Because of this complexity, TCAD cannot expect to be predictive over wide variations in process conditions by assuming diffusion models characteristic of CMOS technology development. Figure 5.2 illustrates this by plotting the profile generated by SIMS analysis of the emitter–base region in a modern SiGe BiCMOS technology. The arsenic distribution in the emitter can be divided into four distinct regions. In the first region a relatively uniform distribution of arsenic in deposited polycrystalline emitter, which can be calibrated based on process knowledge or testing of emitter sheet resistance structures. Second, the region where there is an As dopant segregation at the polysilicon–Si interface is calibrated using SIMS information and tuning the segregation and transport coefficients between polycrystalline emitter and single crystalline silicon. The third and fourth regions consist of the As diffusion regions in the pure Si cap and the strained SiGe epitaxial layers, respectively. The As (or P) deactivation mechanism with vacancy is modeled as [2]: nAs þ Si , AsnV þ I

(5:1)

where AsnV is an arsenic–vacancy cluster. The diffusion coefficients for As and P in strained SiGe epitaxial layer are modeled as [3]:


5-4


Arsenic concentrations (cm−3)

10 22 10 21 10 20 1019 SIMS Simple Model Full Model

1018 1017 −0.05

0

0.05 Depth (µm)

0.1

0.15

FIGURE 5.2 Simple model is simulated As out-diffused profile from polysilicon emitter not considering all the physical effects. Full model is the simulated As out-diffused profile from polysilicon emitter considering As diffusion difference in Si and strained SiGe epitaxial layers and clustering between and As and B atoms.

DAs (SiGe) ¼ DoAs fi Di0 þ Di

n ni (SiGe)

" P

D (SiGe) ¼

DoP Di0

þ

Di

þ fv Dv0 þ Dv

n ni (SiGe)

2 # n n þ Di ni (SiGe) ni (SiGe)

(5:2)

(5:3)

where DoAs and DoP are the prefactor, fi and fv are the fraction of interstitial and vacancy mediated diffusion, Di0, Di, Dv0, Dv, Di ¼ represent the contributions from neutral, single-negatively charged interstitials, vacancies, and double-negative charged interstitials defects, n is the electron concentration, and ni(SiGe) is the intrinsic carrier concentration for SiGe. The individual contributions may require significant tuning of the large number of various parameters during process simulations in order to be predictive over a wide range of processing conditions. Figure 5.2 also shows a better prediction of the simulated profile with SIMS by carefully calibrating all the necessary physical models in each region (Equation 5.1 to Equation 5.3).

Boron Diffusion in SiGe Epitaxial Layer Base Recently, the diffusion of the epitaxially deposited boron in modern SiGe HBTs has rivaled that of CMOS short-channel effects as a subject for research in silicon impurity diffusion. The epitaxial base in SiGe HBTs is a complex region in which B, Ge, and recently carbon (C) atoms are deposited. Point defects flow through the base as a result of P and As out-diffused from the subcollector, emitter diffusions, extrinsic base implants, and selectively implanted collector (SIC) implants, all of which influence the boron diffusion in the intrinsic base. Although point defect interaction with boron is typically considered in CMOS process simulation, in the SiGe or SiGeC base both the Ge and C concentrations have a strong influence in the base diffusion mechanics, and must be considered if a useful range of predictive simulation is expected. Two approaches to simulating the HBT vertical profile are typically used. The first approach illustrated in Figure 5.3 is to calibrate the B diffusion using only two physical factors that influence the diffusion of B in strained SiGe epitaxial layers. These two effects include the B diffusion coefficient that is modified by strain introduced by Ge mole fractions and GeB clustering reactions using [4], DB ¼ D0 exp ( EA =kT ) exp ( fS=kT )

(5:4)


5-5


14.0

------- Model O O SIMS

12.0

1019 1000⬚C & 20 sec

10.0

1050⬚C & 20 sec

1018

8.0

SIMS initial profile

Ge (%)

B concentrations (cm−3)

1020

6.0 1017 4.0 1016 0

0.03

0.06 0.09 Depth (µm)

0.12

2.0 0.15

FIGURE 5.3 Simulated B profiles compared with SIMS for B doping in strained SiGe base by taking into considerations strain from Ge and GeB clustering mechanisms on B diffusions. (From K Rajendran, D Villaneuva, P Moens, and W Schoenmaker. Solid State Electron. 47: 835–839, 2003. With permission.)

and the effect of B atoms that are trapped by Ge atoms by forming a clustering or chemical reaction G þ B , GeB [5] with DBeff ¼ DB

1 1 þ (CGe =Cch )

(5:5)

where EA is the activation energy of the boron in silicon, S is the local strain due to the presence of Ge, f is the activation energy per unit strain, CGe and Cch are the Ge and characteristic concentrations, respectively. Coefficients f and Cch are the fitting parameters used to fit the SIMS profiles for the B diffusion in strained SiGe epitaxial layers. For SiGe:C profiles, the more complex, yet potentially more predictive approach, is to individually treat both the Ge and C influence on the B diffusivity. It is well known that C controls the B diffusivity in SiGe:C base by trapping the interstitials [6], while the Ge concentration affects the B diffusion by both strain and Ge:B clustering mechanisms [5]. For modeling purposes, difficulties arise in separating the individual contributions from the Ge and C on the B diffusion, especially since the effects contain the forward and reverse GeB clustering reactions and the forward and reverse C trapping of interstitials. Apart from these two major competitive physical effects, still more complex problems relating to calibration and predictability arise from clustering reactions of B þ As and B þ P, as well as nonuniform point-defect distributions from various adjacent regions of the SiGe base. The interstitial concentrations trapped by substitutional carbon (Cs) (to control the B diffusion) are modeled by both kick-out (KO) mechanism and Frank–Turnbull reactions (FT) [8]: Cs þ I , Ci

(5:6)

Ci þ V , Cs

(5:7)

where I and V are interstitial and vacancy concentrations and CCi is the interstitial carbon concentration. Careful tuning of both forward and reverse reaction coefficients with the previous B diffusivity variables is required for predictive models. Figure 5.4 shows the simulated B profile by taking into consideration all the physical models compared to experimental B SIMS profiles. These final process variables consist of a careful balance between the Ge and C impact on the base B diffusion.


5-6


Boron concentrations (cm−3)

10 20

SIMS Model

1019

1018

1017

1016 0.15

0.2 0.25 Depth (µm)

0.3

FIGURE 5.4 Simulated B profile compared with SIMS in a strained SiGeC base with calibration of the percentage C and Ge contributions on B diffusion.

5.3

SiGe Device Simulation

A final two-dimensional SiGe HBT process simulation structure is shown in Figure 5.5 showing considerable parallel to the experimental SEM. This simulated device structure can either be directly used as input for device simulation, or translated through a regridding procedure, resulting in a more robust device simulation grid. The SiGe HBT grid generation benefits from the central role played by epitaxy in the process simulation. Since epitaxy models typically consist of repeated depositions of thin layers of material, the mesh arising from the process simulation will contain a smooth, finely graded grid point distribution in the device active areas. Experience has shown that such grids can serve as excellent device simulation platforms with minimal adjustment. For HBT device simulation, the fundamental electrical and material properties of the SiGe layers must also be accurately captured through the physical device models in the device simulator. For SiGe devices, the most fundamental changes to the default Si models pertain to the rigid bandgap narrowing and the mobility models for the minority and majority carriers. In the device simulator the Ge content at each node is known from the process simulation and the relative valence and conduction bands for can then be modified by DEc , Si1x Gex ¼ ( 0:04X)

(5:8)

DEv , Si1x Gex ¼ (0:740X)

(5:9)

to determine the total bandgap change due to Ge (DEg,Ge). Distortion of the band structure due to the Ge-induced stress causes a change in the effective mass and consequently carrier mobilities. Low-field mobilities for both electrons and holes are equally important in bipolar device operation and must be accurately modeled in the device simulator. Experimental measurements, analytical models, and Monte Carlo simulations given in Refs. [9,10] confirm an increase in hole mobility of up to 2.4 in strained Si1xGex layers compared to the unstrained Si values, while electron mobilities are generally reduced. The mobility model given in Ref. [11] shows excellent agreement with both published experimental data and Monte Carlo simulation data across Ge content and impurity concentration. Inclusion of the permittivity changes with Ge content is important for internal electric field and capacitance calculations. Since the fractional Ge percentage is known at each node, the effective permittivity can be calculated using linear interpolation between the pure Si and Ge values as



5-7

FIGURE 5.5 Experimental SEM and simulated cross section of a SiGe HBT demonstrating full two-dimensional process simulation capabilities.

«Si1x Gex ¼ 11:9(1 x) þ 16x

(5:10)

Similarly, the critical electric field dependence on Ge fraction can be approximated by EcritSi1x Gex 3 105 (1 x) þ 1 105 x

(5:11)

DC Calibration DC calibration logically starts with comparison of the HBT forward Gummel curves. The collector current calibration is predominantly dependent on the accuracy of the process emitter diffusion into the Ge and base profiles in combination with the bandgap narrowing models. Since the carrier properties at the emitter–base interface are strongly dependent on the interface processing conditions, polysilicon grain size, and impurity concentration, liberal adjustment to the emitter minority carrier polysilicon lifetimes are used to accurately match the experimental base currents. Extrinsic resistances that account for contact resistances and technology-dependent polysilicon resistances must be added only as needed depending on the comprehensiveness of the process simulation. Optimizations of layout variables such as collector contact configuration and isolation trench design require full twodimensional process and device simulation of both the intrinsic and extrinsic device regions. For full predictive capability, all HBT breakdown modes must be able to be simulated accurately including BVcbo, BVceo, and BVcer . Reliable numerical simulation of such events is challenging, especially for modern high-performance HBTs, which rely on very nonuniform and relatively heavily doped collector and base regions to achieve performance targets. For HBT breakdown simulations, local-field models can perform adequately for high-power transistors with wide, low-doped collector regions. For more complex devices, experience has shown that hydrodynamic models [12] can reliably simulate HBT breakdown modes. The simulation user should expect to be prepared to tune critical parameters for such models, such as energy relaxation times and impact ionization thresholds, in the calibration phase of such modeling.


5-8


AC Extraction and Calibration Small-signal Y- or S-parameters can be determined from device simulations performed using a wellknown 50 V terminated simulation method [13]. For high-speed devices, it is usually required to perform only a single small-signal solution at a predetermined ‘‘corner’’ frequency to extract the maximum operating frequency and maximum unilateral gain curves versus Ic. From this frequency point (usually between 5 and 30 GHz depending on the technology), 20 log10jH21j is calculated and straight line with a slope of 20 db/dec and extrapolated from this value to 0 db to give the ft value at each dc bias point. The unilateral gain fmax can be determined in a similar way by calculating U U¼

jy21 y12 j 4Re[y11 ]Re[Y22 ] 4Re[y21 ]Re[Y12 ]

(5:12)

at the simulation frequency and again extrapolating at a constant 20 dB/dec slope. Example simulation versus hardware plots of both ft and fmax are shown in Figure 5.7. The simulated S-parameters can not only be used to extract ac performance metrics such as ft and fmax, but also used to extract important information on the accuracy of individual calibration parameters such as rb, Ccb, Cbe, etc. Practical ac experimental characterization methods, such as extraction of base and emitter resistance using the impedance circle method and extraction of total junction capacitances using cold S-parameter simulations, can be applied to simulated data for a direct calibration of intrinsic components. Figure 5.6 shows the simulated and experimental S-parameter curves showing an excellent fit over a wide frequency range.

Advanced RF Simulations For RF applications, advanced simulations of high-frequency noise as well as intermodulation characteristics may be useful in the intrinsic device design phase but are often not considered necessary for predictive modeling. RF noise simulations are possible using impedance field methods [14] or hierarchal DD and HD methods from Monte Carlo simulations [15], but with results that are generally useful for only qualitative investigation of gross noise source phenomenon. Similarly, simulation of distortion through harmonic balance based methods [16] can prove to be informative for device design in determining the major components of nonlinearities that can affect important RF power metrics such as IIP3. However, these performance metrics can also be much more easily obtained through circuit simulation of the extracted compact model parameters from the simulated device characteristics.

5.4

Application Examples

In self-aligned emitter–base SiGe HBT structures, the extrinsic emitter spacer determines the position of the extrinsic base implant in relation to the intrinsic emitter diffusion. The thickness of this spacer is critical in determining the inherent tradeoff between the fT and fmax of the device. If the spacer is too thin, extrinsic base implants will diffuse far into the intrinsic base region resulting in an increased base transit time, and lowering fT, but also favorably decreasing base resistance and increasing fmax. On the other hand, increasing the spacer has a positive effect on fT, but ultimately increases the base link resistance and lowers the peak fmax. Through full two-dimensional calibrated process simulation experiments and device simulations, an optimal spacer thickness was determined and resulted in a fT increase of 10 GHz through the extrinsic base process redesign. The simulations were used not only to maximize fT, but also to establish the sensitivity of fT to potential process variances. Figure 5.8 shows the excellent agreement of the device simulations with the subsequent process experiments. In order to increase the 90 GHz device to 120 GHz, an extensive device redesign that targeted the entire intrinsic device including the trapezoidal germanium profile as well as the as-deposited intrinsic


5-9


0.2

1 Re(S11) experiment Im(S11) experiment

Re(S11) simulation Im(S11) simulation

Re(S12) experiment Im(S12) experiment


0.15

S12

S11

0.5 0.1

0 0.05

−0.5

0 0

20

40

60

80

100

120

0

20

Frequency (GHz)

40

60

80

100

120

Frequency (GHz)

2

1

1 0.5


S22

S21

0


−1 0 −2



−3

−0.5 0

20

40

60

80

100

120

0

20

Frequency (GHz)

FIGURE 5.6 SiGe HBT.

40

60

80

100

120

Frequency (GHz)

Comparison of experimental and simulated S-parameter characteristics of a high-performance

140

fT, fmax (GHz)

120 100

Exp. fT Exp. fmax TCAD fT TCAD fmax

80

120 GHz

60

40 20 0.0001

90 GHz

0.001

0.01

0.1

Ic (A)

FIGURE 5.7 Comparison of experimental and simulated fT and fmax characteristics for 90 and 120 GHz SiGe HBT design points.


5-10

page 10



95 90

Experiment TCAD

fT (GHz)

85 80 75

Emitter Pedestal

Spacer

70 65 −30

−20

−100

0

10

20

30

% Change in EB spacer

FIGURE 5.8 Simulated prediction and experimental results for fT changes due to emitter–base spacer process modifications.

base was needed. These modifications in turn drove changes to the collector design to maximize the transit-time reduction offered by the redesign of the intrinsic base, since without modifications to the collector, reduced the reduced base transit-time benefits may be negated by corresponding increases in collector transit times with an earlier onset of Kirk effect. Experimental fT and fmax results, shown in Figure 5.7, validated the process changes ultimately recommended by the concurrent process and device simulation study. The new fT ¼ 120 GHz device design was compatible with the existing 0.18 mm CMOS technology in which it was embedded, as the process simulations used to define it contained all the CMOS etch, depositions, and thermal budget characteristic of the base CMOS technology [17]. This calibrated TCAD capability was then used to define the first fT ¼ 200 GHz and 300 GHz SiGe HBTs [18,19]. These optimizations of peak device performance have always been the main object of TCAD, but for manufacturing purposes, sensitivity of the design point to process changes can be of equal priority. If the targeted design point is too sensitive to process variation, product yield and profitability can suffer, but it is often expensive and time consuming to produce large amounts of process window hardware during the development process. These tasks can be efficiently handled by well-calibrated two-dimensional device simulations. Figure 5.9 shows a simulated ‘‘sweet spot’’ plot of the targeted fT, fmax, and BVceo for a given technology. The central contour of the plot exhibits all possible processing conditions that still meet the device targets, emphasizing that design point ‘‘B’’ is considerably less sensitive to implant dose and energy than design point ‘‘A.’’ Such simulations can also be used to produce predictive process statistics for TCAD based compact models.

5.5

Predictive Model Extraction

Traditionally, the information provided by the TCAD process and device experiments had only direct impact on the process and device development cycle time, but did not have an immediate benefit to the design cycle time. But since the previously described approach to TCAD simulation encompasses the complete process and device simulation, it is elementary to produce the entire suite of ac and dc device characteristics that are needed to extract a suitable model for circuit design. Generating the compact model can be difficult and time consuming due to the amount of required data and number of modeling parameters. A genetic algorithm (GA) model generation methodology has been developed [20] that uses only a minimal set of extracted parameters together with the use of a physically bounded genetic algorithm


page 11


5-11


8⫻1013 7⫻1013 6⫻1013 Dose

Design Point B

SweetSpot Criterias met 2 Criterias met 1 Nothing

5⫻1013 4⫻1013

Design Point A

3⫻1013 2⫻1013 1⫻1013 160

180

200

220

240

260

280

300

Energy

FIGURE 5.9 points.

Results of a simulated design of experiments showing process sensitivity of two optimized design

0.005 T = 25⬚C forced Ib experiment VBIC95 fit to experiment VBIC95 fit to simulation

0.004

Ic (A)

0.003 0.002 0.001 0.000 0

1

2 Vcb (V) SiGe npn modeling

3

4

FIGURE 5.10 Comparison of simulated forced-Ib output characteristics, VBIC model extracted from the simulated data, and a VBIC model extracted from experimental hardware demonstrating excellent predictive modeling capability.

to efficiently optimize a model parameter set. Genetic algorithms have many advantages over more familiar optimization approaches, in particular robustness to getting caught in local minima, no requirements on calculation of functional derivatives or solution of large sets of linear equations, and easy specification of variable constraints. The simulated electrical characteristics are compiled and used as part of the genetic fitness function, allowing the algorithm to mutate the model variables until a predetermined number of generations or ‘‘fitness’’ is achieved. This significantly reduces the extraction and optimization effort as well as eliminating inaccuracies resulting from commonly used fitting methods to approximate model equations, allowing designers early access to technology models. Figure 5.10 shows the genetically fit output curves derived from the TCAD-simulated results, and the experimentally derived VBIC model, demonstrating excellent predictive TCAD and model extraction process.


5-12

5.6

page 12



Summary

This chapter intended to demonstrate the impact that TCAD can have in industrial SiGe technology development, with emphasis on the ability to simulate the full development cycle from the most sensitive process variation to the development of predictive compact models. As developmental wafer costs and process cycle are driven to more aggressive schedules, industry will continue to leverage TCAD as a core component of SiGe technology development.

References 1. RB Fair. Explanation of anomalous base regions in transistors. Appl. Phys. Lett. 22:186, 1973. 2. PM Rousseau, SW Crowder, PB Griffin, and JD Plummer. Arsenic deactivation enhanced diffusion: a time, temperature, and concentration study. J. Appl. Phys. 84:3593–3601,1998. 3. S Eguchi, JL Hoyt, CW Leitz, and EA Fitzgerald. Comparison of arsenic and phosphorus diffusion behavior in silicon–germanium alloys. Appl. Phys. Lett. 80:1743–1745, 2002. 4. NEB Cowern, PC Zalm, P Vander Swis, DJ Gravesteijm, and WB de Boer. Diffusion in strained Si(Ge). Phys. Rev. Lett. 72: 2585–2588, 1994. 5. K Rajendran and W Schoenmaker. Studies of boron diffusivity in strained Si1xGex epitaxial layers. J. Appl. Phys. 89:980–987, 2001. 6. H Rucker, B Heinemann, W Ropke, R Kurps, D Kruger, G Lippert, and HJ Osten. Suppressed diffusion of boron and carbon in carbon-rich silicon. Appl. Phys. Lett. 44:1682–1684, 2000. 7. K Rajendran, D Villaneuva, P Moens, and W Schoenmaker. Modeling of clustering reaction and diffusion of boron in strained Si1xGex epitaxial layers. Solid State Electron. 47:835–839, 2003. 8. JL Ngau, PB Griffin, and JD Plummer. Modeling the suppression of boron transient enhanced diffusion in silicon by subtitutional carbon incorportation. J. Appl. Phys. 90:1768–1778, 2001. 9. T Manku, JM McGregor, A Nathan, DJ Roulston, JP Noel, and DC Houghton. Drift hole mobility in strained and unstrained doped Si1xGex alloys. IEEE Trans. Electron Dev. 40:1990–1996, 1993. 10. LE Kay and TW Tang. Monte Carlo calculation of strained and unstrained electron mobilities in Si1xGex using an improved ionized-impurity model. J. Appl. Phys. 70:1483–1488, 1991. 11. V Palankovski and S. Selberherr. Critical modeling issues of SiGe semiconductor devices. Proceedings of the 6th Symposium Diagnostics and Yield: Advanced Silicon Devices and Technologies for ULSI Era, Warsaw, 2003, pp. 1–11. 12. M Bartels, S Decker, B Neinhus, KH Bach, A Schuppen, and B Meinerzhagen. Comprehensive hydrodynamic simulation of an industrial SiGe heterobipolar transistor. Proceedings Bipolar/ BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 105–108. 13. S. Laux. Techniques for small-signal analysis of semiconductor devices. IEEE Trans. Electron Dev. 32:2028–2037, 1985. 14. W Shockley, JA Copeland, and RP James. The impedance field method of noise calculation in active semiconductor devices. Quantum Theory of Atoms, Molecules, and the Solid-State. New York: Academic Press, 1966. 15. C Jungermann, B Neinhus, and B Meinerzhagen. Hierarchical 2-D DD and HD noise simulations of Si and SiGe devices—Part I: Theory. IEEE Trans. Electron Dev. 49:1250–1257, 2002. 16. B Troyanovsky, Z Yu, L So, and RW Dutton. Relaxation-based harmonic balance technique for semiconductor device simulation. Technical Digest ICCAD, San Jose, 1995, pp. 700–703. 17. A Joseph, D Coolbaugh, M Zierak, R Wurthrich, P Giess, Z He, X Liu, B Orner, J Johnson, G Freeman, D Alghren, B Jagannathan, L Lanzerotte, V Ramachandran, J Malinowski, H Chen, J Chu, P Gray, R Johnson, J Dunn, S Subbanna, K Schonenberg, D Harame, R Groves, K Watson, D Jadus, M Meghelli, and A Rylyakov. A 0.18 mm BiCMOS technology featuring 120/100 GHz (fT/ fmax) HBT and ASIC-compatible CMOS using copper interconnect. Proceedings Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 143–146.



page 13


5-13

18. JB Johnson, A Stricker, AJ Joseph, and JA Slinkman. A technology simulation methodology for ACperformance optimization of SiGe HBTs. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2001, pp 21.4.1–21.4.4. 19. JS Rieh, B Jagannahan, H Chen, KT Schonenberg, D Angell, A Chinthakindi, J Florkey, F Golan, D. Greenberg, SJ Jeng, M Khater, F Pagette, C Schnabel, P Smith, A Stricker, K Vaed, R Volant, D. Ahlgren, G Freeman, K Stein, and S Subbanna. SiGe HBTs with cut-off frequency of 350 GHz. Technical Digest IEEE International Electron Devices Meeting, Washington, DC, 2002, pp. 771–774. 20. DC Sheridan, JB Johnson, and J Watts. Use of genetic algorithm optimization techniques for bipolar compact modeling. Presented at the Workshop on Compact Modeling for RF/Microwave Applications, Toulouse, France, 2003.


page 14





6 Compact Modeling of SiGe HBTs: HICUM 6.1 6.2

Introduction......................................................................... 6-1 HICUM Basics..................................................................... 6-2 Internal Transistor . External Base–Emitter Region . External Base–Collector Region . Collector–Substrate Region . Other Effects

Michael Schro¨ter University of California at San Diego

6.1

6.3 6.4 6.5 6.6 6.7

Geometry Effects and Scaling............................................. 6-8 Parameter Determination Methodology ......................... 6-10 Model Hierarchy................................................................ 6-13 Trends ................................................................................. 6-13 Summary ............................................................................ 6-15

Introduction

The demand for high-speed wireless and fiber-optic communications has pushed the development of SiGe and SiGeC epitaxial base processes into the flow of CMOS mainstream technologies. This combination of narrow base width, due to epitaxial growth techniques, and lateral footprint reduction, due to the utilization of advanced CMOS lithography, has resulted in a tremendous performance boost of Si-based bipolar transistors (e.g., Chapter 3, see Fabrication of SiGe HBT BiCMOS Technology and Ref. [1]). In order to capture the resulting new electrical and physical effects occurring in such technologies, improved compact models have been developed such as the HIgh-CUrrent Model (HICUM) [2–4], that provide the capability of accurately predicting circuit performance. This capability has become extremely important due to the soaring mask cost, which can run as high as US$ 1 million for a 0.1 mmBiCMOS process. Thus, saving just one design cycle and its associated mask cost quickly pays off any model development and support cost. The development of sophisticated compact models takes 10 to 20 years before they actually become suitable for production circuit design. HICUM development started in the early 1980s [5,6], originally targeting the design of high-speed fiber-optic circuits using geometry scaling for circuit optimization [7,8]. Later on, the model was extended to accurately simulate high-frequency small-signal operation [9]. Over time, many effects occurring in advanced Si–SiGe heterojunction bipolar transistors (HBTs) have been added [10–13], and further developments still ongoing following the advancements in bipolar transistor technology and design [36,37]. A detailed documentation of HICUM model equations can be found in Ref. [3]. It should be emphasized that a successful production compact model and its development have to satisfy many requirements from different directions (as visualized in Figure 6.1). Since such a model embraces a major portion of the respective transistor theory, completely presenting its physical background and the 6-1


6-2




Process development Include all physical effects Model parameters without wafers Rapid et al. of process variations "Debugging" of process issues

Simulator

Param. extraction Well-defined, fast, reliable Using standard equipment Min. parameter interaction

Compact model

EC topology, equations to fit in different interfaces I, Q contin. differentiable Modular, easily extendable

Circuit design Accurate, valid over wide range Smooth geometry scaling (for optim.) Computationally fast and reliable Easy to understand

FIGURE 6.1

Requirements for compact model development.

derivation of its equations cannot be accomplished with the limited available space here. Therefore, the goal of this chapter is to provide an overview on HICUM and its associated infrastructure that needs to be in place to deploy the model for production design purposes. This includes: (i) the basic operating principle of HICUM, (ii) how the physical effects in advanced transistors are covered, (iii) the geometry scaling methods used, (iv) the parameter determination methodology, (v) how a hierarchy of models can be generated in an efficient way, and (vi) new research directions. For all the above topics, the reader is guided through the related literature that contains more detailed explanations and background material.

6.2

HICUM Basics

This section contains a concise overview on the operating principle of HICUM, with the focus on its equivalent circuit (EC) and the most important bias-dependent equations. Geometry scaling, although required for a model, will be discussed in Section 6.3. Usually, model construction is described in a ‘‘bottom–up’’ approach, starting with a one-dimensional (intrinsic) formulation and then extending step by step to the external transistor [2,3]. In contrast, this section provides a complementary view at HICUM, following a ‘‘top–down’’ approach, in which the overall structure of the transistor is considered first and then broken down into separate physical regions and their associated ECs. If not otherwise specified, an npn transistor and forward operation is assumed. (Note that proper modeling of inverse biasing is still necessary from a simulator point of view.) Figure 6.2 shows a schematic cross section of a Si–SiGe bipolar transistor fabricated in a nonselective epitaxial growth process. (Please refer to Chapter 3 of Fabrication of SiGe HBT BiCMOS Technology and further literature therein for a more detailed description of SiGe-HBT technologies.) The cross section is partitioned into various regions, indicated by the different line styles. Each of the subdivision is represented by a respective EC, resulting in a physics-based EC. In order to enhance the correspondence between EC and cross section, the internal nodes are inserted into the cross section. The portion determining the fundamental transistor characteristics is the internal transistor under the emitter with the corresponding EC elements following nonlinear bias dependences. In contrast, most elements of the external (parasitic) EC portions—except for the junction capacitances—have simple linear bias-dependent equations.

Internal Transistor Bipolar transistors are mostly employed due to their speed advantage. Speed is closely related though to the charges stored in the transistor. Hence, HICUM is based on an accurate large- and small-signal description of the charge-storage elements, which are discussed below first.




6-3

Compact Modeling of SiGe HBTs: HICUM

Base

Emitter

Base

Collector

External BE region

l b

BE spacer

n+

w, x Silicide p+ poly

E' SiGe

P+

B*

External BC region

External BC region

SiO2

n+ sinker

n-epi p+

n-SIC C' Internal transistor n+ buried layer

Collector−substrate region

p− substrate

External BC region S'

rSu

Collector-substrate region

S

Q jS CSu

iTS ijSC Q'BCx

Q"BCx

ijBCx

rBx

Q jEp

B

Q dS

CrBi

ijBCi

B*

ijBEp C'Eox

rCx

C' QjCi

iAVL

Qr

B' QjEi

r*bi iBEt

C

iT Qf

ijBEi E

C"Eox External BE region

rE

∆Tj

Internal transistor

P

R th

C th

E

FIGURE 6.2 Upper figure: schematic deep trench-isolated SiGe-HBT cross section with main regions identified by surrounding lines. Lower figure: large-signal HICUM/Level2 equivalent circuit with parasitic substrate transistor and self-heating network; network portions related to the main regions in the cross section are identified by the same line style.

A large-signal model for the charge elements starts with a bias-dependent description of the smallsignal quantities. The depletion capacitances CjEi and CjCi, which dominate the charge storage at low current densities, are nonlinear functions of the voltages across the respective internal junctions. Their integration yields the large-signal bias-dependent internal BE and BC depletion charges:


6-4




QjEi ¼

Z

VB0 E0

CjEi (v)dv

and

QjCi ¼

0

Z

VB0 C0

CjCi (v)dv

(6:1)

0

The respective analytical expressions for CjEi(VB0 E0 ) and CjCi(VB0 C0 ) have been extended beyond the classical equation found in textbooks in order to not only avoid numerical instabilities but also to increase the model accuracy. For instance, CjCi includes the punch-through of the BC space–charge layer to the buried layer which, beyond a certain reverse voltage, can lead to a significantly larger (feedback) capacitance than the classical equation predicts; also, both capacitances contain a smooth limitation to their maximum value at high forward bias. Toward high current densities, the minority charge becomes important, which starts to significantly exceed the depletion charge around the peak transit frequency. The minority charge is spatially distributed over the whole internal transistor and is partitioned into a forward and reverse component, Qf ¼

Z

iTf

t f (i)di

and

Qr ¼ t r iTr

(6:2)

0

with tf and tr as forward and reverse transit time, which include contributions from the base, emitter, and collector region. The bias dependent tf can be partitioned into a low-current component tf0 that depends on VB0 C0 (or VC0 E0 ) only, and a high-current component Dtf that depends on both the voltage VC0 E0 and forward component ITf of the (quasi-static) transfer current IT [13]. Variation in both base width (Early effect) and BC space–charge region width is included in the description of tf0, allowing to model transistors with a wide range of collector-doping profiles. The increase of tf at high current densities (via Dtf ) is determined by the mobile (electron) charge in the collector, which compensates the fixed space–charge. As a result, the electric field in the collector becomes bias dependent as shown in Figure 6.3, and its value Ejc starts decreasing with IT. Once Ejc approaches the critical field, the carrier velocity in the BC SCR starts to drop, leading to an increase in minority charge storage both in the base and—for a BC homojunction—also in the collector and to a decrease of fT. The current, at which the critical field occurs, is designated as ICK and can be calculated analytically as a function of VB0 C0 as well as doping and width of the collector region [14,29]. This has been one of the central equations in the minority charge storage formulation of HICUM due to its physics-based nature. Note that ICK is also related to circuit design since it can often be used during optimization for sizing transistors of certain

20

Eϕ Eψ

10 0

ICK

E (kV/cm)

−10 −20 −30 −40 −50 −60 −70 −80 −90

IC Ejc VBC = 0 V

xjc

IC/(mA)=0.074,0.155,0.225,0.3,0.37,0.45,0.51

0.05

0.1

0.15 x (µm)

0.2

0.25

FIGURE 6.3 Spatial dependence of the electric field in the collector of a SiGe HBT with the collector current density ( ¼ IT) as parameter [36]. xjc is the BC junction depth, Ew and Ec, respectively, is the field derived from electron quasi-Fermi potential and electrostatic potential, respectively.




6-5


circuit types, such as differential pair switches in CML and mixers. The bias dependence of the transit time is composed by the components in the various transistor regions, which are described in a physicsbased approach [13,36]. The transfer current of Si BJTs and SiGe HBTs can be expressed in a compact form by the GICCR (cf. Appendix A.3 and [10]) exp iT ¼ iTf iTr ¼ Is

VB0 E0 VT

exp VVB0TC0

Qp,T =Qp0

(6:3)

All nonideal effects and their bias dependence are taken into account in the weighted hole charge Qp,T ¼ Qp0 þ hjEi QjEi þ hjCi QjCi þ Qf ,T þ Qr

(6:4)

with transfer current ‘‘related’’ minority charge Qf,T ¼ QnB þ QpE, low þ hfE DQpE þ hfCQpC. The ‘‘D’’ indicates the difference (increase) of charge in addition to the low-current density component. With respect to the original one-dimensional GICCR given in the appendix, a few modifications are required to make it work for actual (three-dimensional) transistor structures: (i) only the high-current portion of the emitter minority charge is multiplied with the weighting factor, because the lowcurrent portion is calculated as QnB þ QpE,low ¼ tf0iTf via the low-current transit time tf0, which is very difficult to partition into its components by measurements. (ii) Qp0 assumes a modified value compared to the one-dimensional zero-bias charge due to the actual three-dimensional structure. In addition, the names of the weighting factors, which are HICUM parameters, are slightly different to better indicate their application: e.g., the index ‘‘i’’ in hjEi and hjCi indicates that the factors are applied only to the charges of the internal transistor. The weighting factors, their dependence on the Ge profile shape, and their impact on the transfer current are discussed in Appendix A.3. Since the charges are based on a continuous formulation of the respective small-signal quantities, iT is continuously differentiable. The current gain in a bipolar transistor is a derived quantity defined by the physically independent mechanisms governing base and collector current; hence, the base currents in HICUM are modeled independently of the transfer (collector) current. This allows to approximate realistic shapes of the measured forward current gain as a function of collector current using two components for ijBEi in Figure 6.2, representing back injection into the emitter, iBEi, and recombination within the BE space– charge region, iREi, vB0 E0 vB0 E0 DQfB 1 þ IREiS exp 1 þ ijBEi ¼ IBEiS exp mBEi VT mREi VT tBrec

(6:5)

The last term in the above equation takes into account excess recombination (with the lifetime tBrec) at the BC barrier that forms at high collector current densities due to the Ge concentration drop [15]. The current flowing across the (forward biased) internal BC junction, ijBCi(vB0 C0 ), can be described analogously to Equation 6.5, but with the last term omitted. One of the most difficult elements to describe in a compact analytical form is the internal base resistance rBi, which depends on geometry, temperature, and transistor operating mode. It represents the (time- or frequency-dependent) distributed voltage drop caused by the internal base current flowing in perpendicular direction of the transfer current. This leads to a current crowding at the perimeter edge for sufficiently high current densities. Note though that in advanced transistors with narrow emitter stripes and fairly low internal base sheet resistance, the effect of dc emitter current crowding is negligible while dynamic (ac or transient) current crowding can be very significant. Only for power transistors, the effect of dc current crowding sometimes may become relevant. HICUM contains an accurate compact analytical formulation for the bias dependence of rBi that includes emitter current crowding and is valid up to very high current densities [17,18]. The


6-6




frequency-dependent current crowding for small-signal operation is also explicitly accounted for (to first order) through the shunt capacitance CrBi in Figure 6.2 [9]. Unfortunately, a similar calculation as for the small-signal case is not possible for the general case of (high-speed) large-signal switching. Therefore, using CrBi in the latter case can lead to incorrect results and is not recommended. The only known accurate solution here is a multi- or (at least) two-transistor model as suggested in Ref. [19]. Investigations have shown though that at least for the class of high-speed current-mode circuits the different values of rBi during switching-off and switching-on tend to compensate each other [11], giving fairly accurate results using the dc value. The avalanche current iAVL can become a quite complicated function of bias toward high current densities. However, investigations have shown [16] that for circuits that are sensitive to breakdown, the three-dimensional pinch-in effect (caused by the voltage drop across the internal base resistance) is the dominant failure mechanism compared to one-dimensional breakdown at high current densities. Thus, rather than offering a computationally expensive one-dimensional breakdown model, HICUM contains only a weak avalanche model with the main purpose of indicating the onset of avalanche in order to avoid biasing or operation in this region. In addition though the formulation can still be used to construct a distributed three-dimensional model to properly capture the onset of the three-dimensional pinch-in effect.

External Base–Emitter Region The lateral extension of the emitter doping underneath the spacer region (cf. cross section in Figure 6.2) creates the emitter perimeter junction. Together with the BC junction under the spacer, this forms a periphery transistor with an associated transfer current iTp and corresponding charge elements [9]. For practical applications, i.e., circuit design and model parameter extraction, such a complicated twotransistor model is not attractive and needs to be simplified. This can be done by combining the transfer current components of the perimeter and internal transistor into a single transfer current source with iT ¼ iTi þ iTp as shown in the EC of Figure 6.2. Since so far Equation 6.3 is only applied to iTi, the GICCR needs to be extended to the two- and three-dimensional case as described in the appendix to retain a consistent description of the impact of nonideal effects on the total transfer current. This results in enlarged values for also the saturation current and hole charge components. The consequence of this transformation is a one-transistor model with an effective internal transistor, which includes portions of the currents and charges of the physical perimeter transistor in a consistent way. The leftover portions of the perimeter transistor elements in Figure 6.2, ijBEp, QjEp and part of 00 00 QjCx (included in QBCx ) are then kept at the respective (perimeter) nodes and, together with the 00 emitter resistance rE and part of the parasitic spacer capacitance, QEox , form the EC of the external BE region.

External Base–Collector Region This region consists of a resistive layer on top of the external BC junction and (shallow trench) oxide. Fundamentally, this structure corresponds to a transmission line, which is quite lossy though and can be treated as a distributed RC network. Up to not too high frequencies typical for high-speed circuit applications, the electrical behavior can be represented by a simple p equivalent circuit consisting of 0 00 0 QBCx rBx QBCx as shown in Figure 6.2. Note that QBCx also contains the bias-independent parasitic capacitance of the oxide underneath the base polysilicon layer and contact. Furthermore, the diode current ijBCx of the (effective) external BC junction is included in the EC; notice that this current is only relevant under hard-saturation condition.

Collector–Substrate Region Figure 6.4 shows a magnified view of this region. Fundamentally, at high frequencies the electrical behavior of the CS junction also needs to be represented by a distributed RC network.




6-7


C

S

SiGe SiO2 n+ sinker

n-epi

p+ CSp

n+ buried layer CjSb

DTI

p− substrate Bottom

Periphery

FIGURE 6.4 Enlarged schematic cross section of the collector substrate region with corresponding physics-based equivalent circuit (DTI ¼ deep trench isolation).

The latter consists of the CS depletion and isolation capacitance as well as the resistive regions of the external collector (i.e., buried layer, collector sinker) and the substrate. A simplified lumped EC that is still physics-based and sufficiently accurate for circuit applications [1,3,20] is shown in Figure 6.4. The signal path consists mainly of a bottom portion, indicated by the respective depletion capacitance CjSb, and a perimeter portion, indicated by the DTI capacitance CSp. If the DTI is replaced by pn-junction isolation—like in more cost-conscious process technologies—CSp has to be replaced by the respective perimeter depletion capacitance. Depending on the process and layout, the EC for the collector–substrate region can be even more complicated than that in Figure 6.4 [3,20]. For SOI technologies, there is still a bottom capacitance, which is to first-order bias independent though. Since in general, the substrate contact can be anywhere and be of any layout shape, calculating the substrate resistance components is a three-dimensional geometry-dependent problem, for which no general analytical solution exists that is suitable for compact models. Therefore, for modeling it is recommended to have a fixed substrate contact layout (i.e., a transistor p-cell), which is also used in circuit applications. This allows at least a direct characterization of the substrate impedance and resistance for given (critical) transistor layouts. In the built-in version of HICUM in simulators (cf. Figure 6.2), the nonlinear CS depletion charge QjS and the external collector resistance rCx are represented by lumped elements in order to keep the model as simple as possible. The substrate-coupling network also consists of a lumped substrate resistance, rSu, and the associated dielectric capacitance CSu. If a more sophisticated substrate-coupling network is required, the built-in network can be interpreted as the bottom path, and any desired network can be easily added via a subcircuit. Note again that the determination of the substrate coupling resistance remains the responsibility of backend parasitics extraction, unless the transistor layouts employed in circuits are identical to those used for parameter extraction regarding the location and shape of the substrate contact. The EC in Figure 6.2 also contains a simple substrate transistor model, consisting of the transfer current iTS, the base current elements ijSC and ijBCx, the charge storage elements QdS and QjS, and the series resistances rBx, rCx, rSu, which are partially shared with the regular transistor EC. Because operation in the substrate current regime is generally not preferred and can usually be avoided with a proper layout, the purpose of the substrate transistor element in HICUM is mostly to indicate the turn-on of its operation in a circuit with a minimum of modeling effort.


6-8




Other Effects The temperature-dependent description in HICUM is physics-based, with smooth extensions toward very low and very high temperatures for those expressions that otherwise would become numerically unstable [3]. The respective equations are based on TCs of material parameters such as mobility, intrinsic carrier density, and saturation velocity, allowing even reasonably accurate predictions of the transistor temperature behavior without extracting the parameters [4,8,14]. To achieve maximum speed, modern bipolar transistors have to be operated at fairly high current densities. This leads to significant self-heating, which is most pronounced for larger transistors used in driver applications and is taken into account by the separate network consisting of Rth and Cth in Figure 6.2. Although heat transfer is a distributed process, with usually at least a fast (nanosecond scale) and a slow (microsecond scale) characteristic time constant [21], only a simple single-pole network has been implemented to maintain a reasonable model complexity for most applications. If modeling of distributed effects is required, such as for power amplifier design, the thermal node DTj in Figure 6.2 is accessible in circuit simulators and allows adding a sophisticated thermal (coupling) network [22]. Since the temperature increase at node DTj requires the re-calculation of all temperature-dependent model parameters and bias-dependent equations, simulations with self-heating tend to be much more time-consuming than if the effect is neglected. Also, convergence problems in circuit simulators can occur if the transistor is operated such that it becomes thermally unstable (thermal runaway). For communication circuit design, the prediction of noise and distortion behavior as a function of bias, geometry, and frequency is important. Noise simulation is accomplished in HICUM by adding the physical description of noise sources to the dissipative equivalent circuit elements [3,23,24]. For lf (flicker) noise, a simple 1/f behavior is included in the model the corner frequency of which as a function of bias can be adjusted with two parameters. For describing hf noise and distortion behavior, which are both given by the EC and bias-dependent description of its elements [23–27], no separate model parameters are required.

6.3

Geometry Effects and Scaling

It cannot be emphasized enough that compact model development has to keep the application, i.e., mainly circuit design, in mind. Therefore, priority should be assigned to modeling those effects that matter most for circuit design. One important requirement in this regard is transistor sizing, which for a circuit designer is usually more important than detailed modeling of second-order physical effects. From a design point of view, it is desirable to be able to vary the transistor configuration, defined by the emitter width and length together with the number of contacts (or stripes) for base, emitter, and collector as well as their spatial arrangement. For example, when designing a low-noise amplifier, usually specifications for bandwidth and noise have to be met simultaneously. Unfortunately, maximum speed and minimum noise in a transistor do generally not occur at the same bias point. Thus, a compromise needs to be found by properly selecting the transistor size that gives the best overall circuit performance. There are many other examples [7], where transistor sizing is essential to achieving the circuit specifications for a given process technology. To speed up the design job, numerical optimizers have become available which, however, require continuously differentiable geometry scaling for (compact) models. A geometry scalable compact model requires that all of its EC elements are described as a function of layout dimensions. While this is fairly simple for some elements it can become very complicated for other elements in a given process as will be shown later. Note that geometry effects can not only depend on the device dimensions but also, for given dimensions, on bias and frequency (cf. tf and rBi). Also, sometimes certain vertical dimensions are allowed to be changed if requested by a foundry customer. Below, the presently most important geometry scaling effects from a hf point of view and their modeling in HICUM are briefly reviewed.




6-9


All elements of the internal transistor, except rBi, are scaled proportional to the effective emitter area AE which—according to section ‘‘Internal Transistor’’—is given by lumping together the bottom and perimeter components of the transfer current: LE0 iT ¼ iTi þ iTp ¼ jTi AE0 þ jTp LE0 ¼ jTi AE0 1 þ gC ¼ jTi AE , AE0

(6:6)

LE0 is the emitter perimeter length and gC ( ¼ jTp/jTi) is a process constant [28,29]. Hence, the effective electrical emitter area AE can be used to scale the transfer current iT correctly for arbitrary emitter sizes. This also applies to the associated (total) minority charge. With smaller emitter size, the peak of fT not only broadens but also shifts toward higher current densities. This three-dimensional effect is caused by collector current spreading and is taken into account analytically in the expressions for the critical current ICK and the minority charge Qf [29], that influence the transfer current via the GICCR. Since for the BE depletion charge and the base current flowing across the BE junction the ratio of perimeter to internal portion is usually different from iTp/iTi, the ‘‘leftover’’ portions are included as effective periphery elements QjEp and iBEp in Figure 6.2, preserving their total values. Also, the impact of the perimeter minority charge, which is included now in the effective internal transistor, on the input impedance of the internal transistor is taken into account by an effective internal base resistance rBi* [9]. HICUM contains an accurate compact formulation for the geometry dependence of the base resistance components rBi* and rBx [18,19]. The equation takes into account different contact configurations, such transistors with single-base contacts, which have become quite common due to the use of low-ohmic silicides and in which part of the current has to flow around the emitter as shown in Figure 6.5.

B

E

p+ SiO2 (a)

bo

bp

bl

b

bl

bp

6

5

4 contact

l/2 3

2 bl

1 lp (b)

0 0

1

2

3

4

5

6

FIGURE 6.5 Base resistance considerations for a single-base transistor: (a) schematic cross section with conducting plane through base and (b) current flow and equipotential lines in the base plane.


6-10

page 10 17.10.2007



The two-dimensional current distribution, including dc current crowding effects, is captured by explicit analytical equations that are based on simple physics-based considerations. The elements of the external transistor portions are scaled with the respective dimensions as described in Refs. [3,8,18]. For instance, the total external BC depletion capacitance scales with an expression similar to Equation 6.6, but with the external BC junction area, ABCx ¼ ABC AE, and perimeter length LBCx, where ABC is the total BC junction area. With increasing frequency and reduced device dimensions various parasitics become important. This includes the isolation capacitances, especially the portion CEox resulting from the BE spacer region, the spatial topology of which can be quite complicated. Further, parasitics that may need to be included are the capacitances between the metal studs as well as the self-inductances of the fingers, which are not covered by backend extraction. All these parasitics belong to the transistor itself and have to be dealt with already during parameter extraction. Scaling becomes even more complicated for the elements of the substrate and the thermal network due to the large variety of layouts and device designs (e.g., junction isolation, deep trench, SOI, metallization). Basically, different sets of scaling equations or even (fast) numerical methods have to be used for those cases. All these scaling equations further extend the physics-based formulation of HICUM toward addressing challenging circuit design and simulation tasks, including statistical modeling. Since a complete description of the scaling equations for bipolar transistors is beyond the scope of this paper, the reader is referred to, e.g., Refs. [3,8] and the references therein. It has been mentioned several times that the large variety of bipolar transistor fabrication processes and device designs require quite a sophisticated set of suitable scaling equations. Therefore, implementing those equations into circuit simulators along with the bias and temperature-dependent equations makes the model code messy, difficult to understand, and to maintain. The latter holds especially because geometry equations usually need to be improved or adapted to a particular process often at different times than the other equations. The result would be a large burden for the model developer to coordinate the respective code changes, tests, and releases in the many-circuit simulators the model is available in. As a consequence, accurate geometry scaling equations for (so far) five different BJT and HBT process technologies have been implemented in a separate tool. The program, TRADICA [8], enables a flexible model and parameter generation for practically relevant configurations, spanning from minimum size single-base over large multifinger transistors to coupled transistor cells, and including all important physical effects. Figure 6.6 provides an overview on the operating principle of the program. The input data consist of process-related parameters such as sheet resistances and per area capacitances, which are obtained from parameter extraction, and of device-relevant dimensions, that are obtained from design rules and SEMs of actually fabricated transistors (cf. Section 6.4). The initial program development started out in the early 1980s as sizing aid for circuit designers, a feature that has been expanded in the recent past. This origin underlines the close relationship of HICUM development with circuit design. Note though, that HICUM and TRADICA are independent tools, i.e., using HICUM does not depend on the availability of TRADICA. More recently, a set of analytical equations for calculating the transistor parameters and electrical performance as a function of process variations (in both vertical and lateral direction) have been added, enabling the generation of ‘‘skewed’’ model parameters. This capability can be used together with a design-of-experiment-based response-surface method, for statistical modeling and predicting the impact of process changes on electrical device behavior in a computationally efficient way. In fact, since physicsbased models for passive devices are also available in TRADICA, the parameter correlation between devices on the same chip can even be taken into account. Thus, the modular integration into a design system enables the simulation of parametric yield and device matching.

6.4

Parameter Determination Methodology

The typical methodology for model parameter determination relies on adjusting the parameters to fit a set of measured electrical characteristics of a transistor with given geometry. Unfortunately, this


page 11 17.10.2007


6-11


Design rules

Process specific parameters Process control monitor (PCM) data

sheet resistances, capacitances per area, sat, current per area, ...

Transistor configurations E width and length, number of E, B, C stripes, location

Critical bias points TRADICA

⇒

transistor sizing

Model characteristics Model parameters device libraries

(fT, fmax, NFmin ... as function of geometry and bias)

for specified bias points

FIGURE 6.6

Overview on the TRADICA program operation principle.

generally does not lead to physics-based model parameters and, thus, prohibits any predictive or statistical modeling. Most importantly though, every transistor configuration that is required for circuit design, has to be available on a test chip and to be fitted. Since test chip space and measurement time and, hence, transistor configurations are quite limited, such a methodology severely limits circuit design. In contrast, HICUM parameter extraction is based on a well-defined and small set of test structures, which then enables parameter generation also for any other configuration that is not available on a test chip. The parameter determination methodology is described in more detail in Refs. [3,30–32]. Also, a GUI-based extraction tool is available in Ref. [33]. ‘‘Production’’ HICUM parameters have been delivered for a variety of process technologies from foundries such as Atmel, IBM, Jazz, ST, TSMC; for publicly available results see Refs. [1,3,4,12,13,24–27,31]. Due to the lack of space, only a few selected examples can be presented here, which are key results related to the high-frequency transistor behavior and are typical for the accuracy achievable with HICUM in an industrial environment. The transit frequency fT shown in Figure 6.7 is an important figure-of-merit characterizing the performance of a technology. It also includes the information on how accurately the charge storage (connected to the base terminal) of a transistor is described by a compact model. As Figure 6.7 demonstrates, the experimental results for a SiGe(C) process are quite well described by HICUM. Noise figure NFmin and equivalent noise resistance Rn versus frequency are shown in Figure 6.8 for a 150 GHz production process. The bias point is typical for low-noise applications. HICUM gives good agreement for Rn over the whole frequency range and for NFmin at high frequencies. The observable deviation at lower frequencies is caused by the missing correlation between collector and base noise, which has not yet been implemented in circuit simulators. This is confirmed by the thin line that results from a HICUM-generated small-signal model (SSM) with added correlation. Figure 6.9 contains for a two-tone distortion measurement the output power both at the fundamental frequencies (f01 ¼ 5 GHz, f02 ¼ 5.01 GHz) and the third-order intermodulation frequencies (2f1 f2 ¼ 4.99 GHz, 2f2 f1 ¼ 5.02 GHz). Despite a bias point at a fairly high current density and the


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0.1

140

1

JC (mA/µm2)

10

120

fT (GHz)

100 80 60 40 20 0 0.1

1

10

IC (mA)

100

FIGURE 6.7 Transit frequency fT versus collector current (density) for STs 120 GHz SiGeC BiCMOS process: comparison between measurement (symbols) and HICUM (lines). VBC/V ¼ 0.6, 0.4, 0.2, 0, 0.25, 0.5; AE0 ¼ 0.25 12.65 mm2.

NFmin(dB), Rn /50Ω

3 NFmin 2

HICUM Rn/50Ω SSM & corr

1

HICUM SSM & corr

0 1

5

9

13 17 Frequency (GHz)

21

25

28

FIGURE 6.8 Minimum noise figure and equivalent noise resistance versus frequency for JazzSemi’s 150 GHz SiGeC-BiCMOS process: comparison between measurements (symbols) and HICUM (lines); IC ¼ 0.52 mA, VCE ¼ 1 V, AE0 ¼ 0.2 10.16 mm2. 20 0

Pout (dBn)

−20

Pout(f1,1)

f1,1 = 5.00 GHz f1,2 = 5.00 GHz

−40 IMD3

−60 −80

−100 −120 −140 −160 −50

−40

−30

−20 Pin (dBm)

−10

0

5

FIGURE 6.9 Output power versus input power for a high-voltage transistor of Atmel’s SIGE1 process: comparison between measurement (symbols) and HICUM (lines) for two-tone intermodulation distortion (IMD). IC ¼ 25 mA ( fT,peak), VCE ¼ 2.5 V; AE0 ¼ 2 1.3 49.7 mm2.



page 13 17.10.2007


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relatively high frequencies for the considered power transistor with 22 GHz peak fT, the model shows excellent agreement. At lower input power, even better results were obtained [27].

6.5

Model Hierarchy

For design tasks often (at least initially), a fairly simple model is sufficient. However, driven by the increasing number of physical effects to be accounted for, most of the present developments seem to be moving toward more complicated models, less and less understood by circuit designers. Model complexity is defined by number of nodes and elements in the EC along with the element equations and number of parameters. For final verification and some other cases though, more complicated models (even more than in Figure 6.2) are required. Thus, providing a model hierarchy is very attractive for meeting the very different design needs. As discussed in Ref. [34], it is most suitable to choose a medium complexity model as reference, from which both simple and more sophisticated models can be generated without any additional parameter extraction effort. Using TRADICA, such an approach has been realized with reasonable coding and maintenance effort, resulting in the (presently existing) hierarchy shown in Figure 6.10. The standard HICUM form (Level2) serves as reference model, from which—by adequately simplifying both EC and equations—HICUM/Level0 [35] and the standard SPICE Gummel–Poon model (SGPM/Level0) can be generated. Since all model parameters are calculated from process-specific parameters and layout dimensions, distributed models (HICUM/Level4, SGPM/Level4) can be generated at the same time. Notice that parameter extraction is performed only once for HICUM/Level2, ensuring a consistent set of models. Within each of the complexity levels, the model user can still create intermediate levels by turning off certain effects independently (without the necessity of reformulating equations).

6.6

Trends

Considering recent SiGe(C) technology development with HBTs exceeding even 300 GHz transit frequency, applications are increasingly becoming limited by ‘‘parasitic’’ effects rather than by the intrinsic transistor. Examples for important parasitic effects to be modeled more accurately include BC breakdown, intra- and inter-device substrate and electrothermal coupling as well as the metal contact studs and the connections between, e.g., amplifier cells. Reliable modeling of extreme cases such as power amplifiers is still a challenge, also for circuit simulators when dealing with self-heating and interdevice coupling. Fast, preferably compact, solutions are developed to account for the abovementioned effects during model generation. Providing an efficient statistical design capability is a demand from circuit designers that has been existing for a long time. There has also been an increasing interest by both foundries and designers to have this feature available already at the early stage of process development. To address these needs, physics-based statistical models for the complete device portfolio are developed and implemented in TRADICA [38,39]. This allows to include the correlations between parameters of different devices and to offer an integrated modular solution within a design system. For predictive modeling, TRADICA is coupled to a device simulator and an automated parameter extractor, enabling fast investigations of the impact of intentional process changes in electrical characteristics of devices and circuits. Improving the equations of the internal transistor toward a more compact HICUM formulation with more features is presently pursued. One of the goals is to model the bias dependence of the electric field in the BC region, which controls the transistor behavior at higher current densities, namely the voltage and current-dependent transit time, base–collector capacitance, avalanche breakdown and even nonlocal effects in the collector region. First versions of such an approach were presented in Refs. [36,37]. Coding in circuit simulators has been a major bottleneck to deploy improved compact models and keep pace with process development. Most recently, model compilers have been developed and become


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HICUM/Level0 ijSC

C’ CCox

CjCx

IjBC

CjCi

Cdc

CjE

CdE

SGPM/Level0

S CjS

rCx

S CjS

C

rB

CEox

ijBE

iAVL

CCox

ijBC

CjCx rD

CEox

rE

Cth

B

QdS

C’

B* rBx QEox

QdC

rBi

QjEi

QdE

iBEt

C

iTS

ijSC

iAVL

iBCx

B’

QjEp ijBEp

rCx

QjCi

B

iT

QdS

QEox

E’

ijBEp

E

Rth

rCx

QjCi

QdC

QjEi

QdE

B’ rBi iBEt

C

iT

ijBEi E’

∆Tj

rE

Qsu

C’ ijBCi

B* QjEP

rBx

ijBEi

P

S

QjS

Qsu ijBCi

TSU

S’

S

CrBi

CdE

E’

SGPM/Level2

rsu S’

ijSC

CjE

C

E

HICUM/Level2

ijSC

CdC

rE

Rth

P

iTS

ijBE

∆Tj

QjS

CjCi

B’ B

E’

E

gjSC r Cx

C’

B’ B


rE Cth E

HICUM/Level4, SGPM/Level4

C’

C’ T2n

Tkn

T1n

E’

E’

rsu S Tk3

T23

B*

C’ n C’ Tk2

T22

Tn E’

E’

C’ cK ∆rCx

S’

C’ w

S’

Tcl

TcK

rCxI

C

S’ Tw

E

C’

C’ Tk1

C’ cl ∆rCx

S’

B

T12

∆rCx

Csu

T31

T21

T11 z

E’

E’

E’

E’ y

Symmetry lines

FIGURE 6.10 Model hierarchy generated by TRADICA. HICUM/Level2 is the reference model, while ‘‘Level0’’ indicates simplified and ‘‘Level4’’ indicates distributed models with various types of partitioning.

available [40,41], that can transfer a Verilog-A model description into C code suitable for the compiled interfaces of various mainstream simulators. This capability will not only tremendously speed-up model deployment, but will also allow users to adapt existing models much quicker to their needs, such as special process features and design applications, than in the past.


Compact Modeling of SiGe HBTs: HICUM TABLE 6.1

page 15 17.10.2007


6-15

Summary of HICUM Features

High accuracy . Over wide bias range including the high-current region . For high-speed nonlinear large-signal (switching) operation . Up to very high frequencies in small-signal operation . Over wide geometry (transistor configuration) and temperature range Physical effects . Two-dimensional and three-dimensional effects such as emitter periphery injection, emitter current crowding, collector current spreading, distributed external base–collector region . (Weak) avalanche breakdown and BE tunneling . Temperature dependence (including parasitics and self-heating effects) . Parasitic substrate transistor and simple substrate coupling network . Non-quasi-static effects for both charge and current . Impact of bandgap variation in (SiGe) HBTs . All standard noise mechanisms Parameter determination . Well-defined set of test structures . Well-defined methodology and procedures . Commercial tools Simulator availability: ADS, SPECTRE, ELDO, HSPICE, MWO (cf. website in Ref. [3])

6.7

Summary

The basic operation principle of the advanced physics-based compact bipolar transistor model HICUM has been reviewed. The accurate description of small-signal quantities, such as depletion capacitance and transit time, as a (nonlinear) function of bias, temperature, and geometry results ‘‘by construction’’ not only in continuously differentiable relations for charges and transfer current but also in accurate modeling of the large-signal switching behavior, including harmonic distortion at high frequencies. Moreover, the small-signal quantities can be measured via the terminals using standard methods and equipment. The main features of the model are summarized in Table 6.1. HICUM development follows an integrated approach that is oriented toward circuit design and process development. Necessary infrastructure and CAD tools for flexible geometry scaling, parameter determination, and generating a model hierarchy, have been discussed in Sections 6.3 to 6.5. ‘‘Production’’ HICUM parameters have been delivered for a variety of foundry technologies; additional experimental results can be found in many publications, such as those listed below.

Acknowledgments Many individuals have contributed to the development of HICUM and related tools. In addition to those individuals mentioned already in Ref. [2], the author would like to thank Dr. B. Ardouin (XMOD), Dr. H. Jiang (JazzSemi), Dr. P. Zampardi (Skyworks Inc.), and Dr. P. Sakalas, S. Lehmann, H. Tran, Y. Zimmermann, H. Wittkopf, K. Moebus (all with the Chair for Electron Devices and Integrated Circuits, Dresden University of Technology), for their feedback and help with model and tool development. Financial and in-kind support are gratefully acknowledged from Atmel, JazzSemi, ST, IBM, Agilent, AWR, Cadence, Mentor, XMOD, and IHP.

References 1. M. Schroter. Compact device modeling for RF circuit design. Invited Tutorial at the IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, December 2002. 2. M. Schroter. Staying current with HICUM. IEEE Circuits and Devices Magazine 18(3), 16–25, 2002. 3. M. Schroter. ‘‘HICUM—a scalable physics-based compact bipolar transistor model. Documentation at www.iee.tu-dresden.de/iee/eb/ or www.xmodtech.com.


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4. H.-M. Rein and M. Schroter. A compact physical large-signal model for high-speed bipolar transistors at high current densities—Part II: Two-dimensional model and experimental results. IEEE Trans. Electron Dev. 34, 1752–1761, 1987. 5. H.-M. Rein, H. Stu¨bing, and M. Schroter. Verification of the integral charge-control relation for highspeed bipolar transistors at high current densities. IEEE Trans. Electron Dev. 32, 1070–1076, 1985. 6. M. Schroter and H.-M. Rein. A compact physical large-signal model for high-speed bipolar transistors including the high-current region. NTG meeting, Wu¨rzburg, May 1986. 7. H.-M. Rein. Very-high-speed Si and SiGe bipolar ICs. Proc. ESSDERC, 1995, pp. 45–56. 8. M. Schroter, H.-M. Rein, W. Rabe, R. Reimann, H.-J. Wassener, and A. Koldehoff. Physics and process-based bipolar transistor modeling for integrated circuit design. IEEE J. Solid-State Circuits 34, 1136–1149, 1999. See also: TRADICA User’s Guide and www.xmodtech.com. 9. A. Koldehoff, M. Schroter, and H.-M. Rein. A compact bipolar transistor model for very highfrequency applications with special regard to narrow stripes and high current densities. Solid-State Electron. 36, 1035–1048, 1993. 10. M. Schroter, M. Friedrich, and H.-M. Rein. A generalized integral charge-control relation and its application to compact models for silicon based HBTs. IEEE Trans. Electron Dev. 40, 2036–2046,1993. 11. M. Schroter and H.-M. Rein. Investigation of very fast and high-current transients in digital bipolar circuits by using a new compact model and a device simulator. IEEE J. Solid-State Circuits 30, 551–562, 1995. 12. M. Schroter, Z. Yan, T.-Y Lee, and W. Shi. A compact tunneling current and collector breakdown model. Proc. IEEE Bipolar Circuits and Technology Meeting, Minneapolis, 1998, pp. 203–206. 13. M. Schroter and T.-Y. Lee. A physics-based minority charge and transit time model for bipolar transistors. IEEE Trans. Electron Dev. 46, 288–300, 1999. 14. M. Schroter and H.-M. Rein. Transit time of high-speed bipolar transistors in dependence on operating point, technological parameters, and temperature. Proc. IEEE Bipolar Circuits and Technology Meeting, Minneapolis, 1989, pp. 85–88. 15. S. Tiwari. A new effect at high currents in heterostructure bipolar transistors. IEEE Electron Dev. Lett. 9, 142–144, 1988. 16. M. Rickelt and H.-M. Rein. A novel transistor model for simulating avalanche-breakdown effects in Si bipolar circuits. IEEE J. Solid-State Circuits 37, 1184–1197, 2002. 17. H.-M. Rein and M. Schroter. Experimental determination of the internal base sheet resistance of bipolar transistors under forward-bias conditions. Solid-State Electron. 34, 301–308, 1991. 18. M. Schroter. Simulation and modeling of the low-frequency base resistance of bipolar transistors in dependence on current and geometry. IEEE Trans. Electron Dev. 38, 538–544, 1991. Also, M. Schroter. Modeling of the low-frequency base resistance of single base contact bipolar transistors. IEEE Trans. Electron Dev. 39, 1966–1968, 1992. 19. H.-M. Rein. Improving the large-signal models of bipolar transistors by dividing the intrinsic base into two lateral sections. Electron. Lett. 13, 1977, S.40–S.41. 20. M. Pfost, H.-M. Rein, and T. Holzwarth. Modelling substrate effects in the design of high-speed Sibipolar ICs. IEEE J. Solid-State Circuits 31, 1493–1497, 1996. 21. D.J. Walkey, T.J. Smy, D. Marchesan, H. Tran, C. Reimer, T.C. Kleckner, M.K. Jackson, M. Schroter, and J.R. Long. Extraction and modeling of thermal behavior in trench isolated bipolar structures. IEEE Bipolar and BiCMOS Circuits and Technology Meeting, Minneapolis, 1999, pp. 97–100. 22. D.J. Walkey et al. Equivalent circuit modeling of static substrate thermal coupling using VCVS representation. IEEE J. Solid-State Circuits 37, 1198–1206, 2002. 23. S. Voinigescu et al. A scalable high-frequency noise model for bipolar transistors and its application to optimal transistor sizing for low-noise amplifier design. IEEE J. Solid-State Circuits 32, 1430–1439, 1997. 24. P. Sakalas et al. Analysis of microwave noise sources in 150 GHz SiGe HBTs. RFIC Symp., Tech. Dig., 2004.



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25. P. Sakalas, M. Schroter, P. Zampardi, and M. Racanelli. Microwave noise in III–V and SiGe-based HBTs: Comparison, trends, numbers (Invited paper). 18th Int. Conf. on Noise and Fluctuations, Canary Islands (Spain), 2004. 26. M. Schroter, D.R. Pehlke, and T.-Y. Lee. Compact modeling of high-frequency distortion in Si integrated bipolar transistors. IEEE Trans. Electron Dev. 47, 1529–1539, 2000. 27. P. Sakalas, M. Schroter, W. Kraus, and L. Kornau. Modeling of SiGe power HBT intermodulation distortion using HICUM. Proc. ESSDERC, Lisboa, 2003, pp. 311–314. 28. H.-M. Rein. A simple method for separation of the internal and external (peripheral) currents of bipolar transistors. Solid-State Electron. 27, 1984, S.625–S.632. 29. M. Schroter and D.J. Walkey. Physical modeling of lateral scaling in bipolar transistors. IEEE J. SolidState Circuits 31, 1484–1491, 1996; 33, 171, 1998. 30. T.-Y. Lee and M. Schroter. Methodology for bipolar compact model parameter extraction. At www.iee.tu-dresden.de/iee/eb/ or www.eigroup.org/cmc. 31. T.-Y. Lee, M. Schroter, and M. Racanelli. A scalable model generation methodology for bipolar transistors for RF IC design. IEEE Bipolar and BiCMOS Circuits and Technology Meeting, Minneapolis, 2001, pp. 171–174. 32. D. Berger, D. Celi, M. Schroter, M. Malorny, T. Zimmer, and B. Ardouin. HICUM parameter extraction flow for a single transistor geometry. IEEE BCTM, Monterey, CA, 2002, pp. 116–119. 33. XMOD Technologies. The HICUM Aperitif Toolkit. User Manual, 2002. www.xmod-tech.com. 34. M. Schroter. Compact bipolar transistor modeling—issues and possible solutions. Invited paper at WCM, Proc. International NanoTech Meeting, San Francisco, CA, 2003, pp. 282–285. 35. M. Schroter, H. Jiang, S. Lehmann, and S. Komarow. HICUM/Level0—a simplified compact bipolar transistor model. IEEE BCTM, Monterey, CA, 2002, pp. 112–115. 36. M. Schroter and H. Tran. Modeling of base–collector junction related effects in heterojunction bipolar transistors. Proc. Compact Modeling Workshop at the International NanoTech Meeting, Boston, MA, Vol. II, March 2004, pp. 102–107. 37. S. Wilms and H.-M. Rein. Analytical high-current model for the transit time of SiGe HBTs. Proc. Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, 1998, pp. 199–202. 38. M. Schroter, H. Tran, and W. Kraus. Germanium profile design options for LEC-SiGe HBTs. SolidState Electron. 48, 1133–1146, 2004. 39. M. Schroter. Modeling of high-speed bipolar transistors for predictive circuit design and optimization. Natural Sciences and Engineering Research Council of Canada, Project Report 1996. 40. See www.tiburon-da.com. 41. L. Lemaitre, C. McAndrew, and S. Hamm. ADMS—automatic device model synthesizer. Proc. Custom Integrated Circuits Conf., 2002, pp. 27–30.


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7 Compact Modeling of SiGe HBTs: Mextram 7.1 7.2

Introduction......................................................................... 7-1 Transfer Current .................................................................. 7-3 Quasi-Neutral Base . Epilayer

7.3

Recombination Currents..................................................... 7-7 Intrinsic Transistor Region . Extrinsic Quasi-Neutral Regions . Weak Avalanche Current

7.4 7.5

Substrate Current .............................................................. 7-10 Charges and Capacitances ................................................ 7-11 Depletion Capacitances . Diffusion Charges . Distributed and Non-Quasi-Static Charges

Slobodan Mijalkovic´ Delft University of Technology

7.1

7.6 7.7

Thermal Phenomena......................................................... 7-14 Parameter Extraction ........................................................ 7-16

Introduction

The worldwide interest in SiGe heterojunction bipolar transistors (HBTs) as a commercial IC technology is growing rapidly [1]. The corresponding circuit design activities essentially depend on accurate compact models of SiGe HBTs in all relevant modes of the transistor operation. This chapter gives an overview of the vertical bipolar transistor compact model Mextram (the acronym of the ‘‘most exquisite transistor model’’) and its capabilities to meet SiGe HBT circuit design challenges. The Mextram has been introduced by De Graaff and Kloosterman at Royal Philips Electronics in 1985 [2]. Appearing to be the fifth existing bipolar transistor model (after the previous four described in Ref. [3]), the first Mextram release was introduced as Level 501. Following the requirements of the continuous technology development, Mextram has appeared later in several update releases: Level 502 in 1987 [4], Level 503 in 1994, and Level 504 in 2000 [5]. Figure 7.1 shows the equivalent circuit of the Mextram model as it is specified in its latest release (Level 504). The branches representing model currents and charges are schematically associated with different physical regions of a bipolar transistor separated by the base–emitter (BE), base–collector (BC), and substrate–collector (SC) junctions. All current and charge branches in Mextram are given as explicit functions of external and internal nodal potentials and there are no implicit modeling variables that require internal iterations. The governing Mextram equations are formulated having in mind NPN transistors, but the model can be equally well used for PNP transistors by simple change of the current and charge polarity. The main transfer current IN in Mextram, as in the Gummel–Poon model [6], is evaluated in the quasi-neutral base (QNB). However, the mathematical appearance of the equations governing the transfer current is quite different in comparison to the Gummel–Poon model. The principle novelty was to abandon the classical Gummel–Poon charge control relationship between the transfer current and charges [7]. The integral base charge (at high injection) is evaluated in Mextram directly from the 7-1


7-2


C

C 0BE

p-type base

Q StE

RCC B1

RE E1

QtE

Qtex Iex + IB3

Isub

B2 Iavl

Qex

Qepi n-type epilayer n+ buried layer

ISF QtS

IN

IB2

QBC QtC

XIsub XIex

n + emitter QE

IB1 QBE

IB1B2

XQex

S I B1

QB1B2

RBC XQtex

E

C0 BC

B

C2 Iepi C1

p-type substrate

S

FIGURE 7.1

Mextram equivalent circuit.

junction low at QNB boundaries. Moreover, the effects of a graded Ge profile in QNB [8] are physically addressed in the transfer current description. A distinguishing feature of the Mextram model is the description of the epilayer transfer current Iepi. It is employed for intensive physical modeling of the quasi-saturation phenomena including the base widening, Kirk effect [9], hot-carrier behavior in the epilayer, and advance modeling of the distortion effects [10]. S , IB2, IB3, Iex, and XIex in the Mextram equivalent circuit The diode-like injection currents IB1, IB1 describe various recombination currents in the quasi-neutral and depletion transistor regions. The recombination in the modulated QNB, which is particularly important for SiGe HBT applications [11], is also included. The effect of a distributed hole injection across BE junction is described by an additional current branch IB1B2. Mextram provides also a sophisticated model for the weak avalanche current in the branch Iavl. The contribution of the parasitic PNP transistor transfer current to the substrate current, represented by the current sources Isub and XIsub, is implemented using a simplified Gummel–Poon integral charge control relationship. S , QtC, Qtex, The dynamic currents are accounted for by the depletion capacitances (charges) QtE, QtE XQtex, and QtS as well as diffusion charges (capacitances) QBE, QBC, QE, Qepi, Qex, and XQex in the intrinsic and extrinsic transistor regions as shown in Figure 7.1. The BC depletion capacitance is particularly equipped to account for the full depletion of the epilayer and the charge current modulation. An additional charge branch QB1B2 accounts for the distributed high-frequency effects in the intrinsic transistor base. Thermal phenomena are addressed in Mextram by a simple thermal impedance (thermal resistance and capacitance in parallel) and a power dissipation source. Moreover, the model is equipped with the physical temperature-scaling rules. A set of temperature-scaling parameters is extracted along with the corresponding electrical model parameters in the straightforward procedure. The physical background of the Mextram parameters also provides an excellent framework for the geometrical [12] and configurational scaling [13]. Mextram has been already used intensively in various SiGe HBTs applications including highperformance SiGe HBT integration [14], low-noise amplifiers [15,16], and SiGe HBTs phototransistors [17]. As an additional illustration of Mextram capabilities, some results of the Mextram parameter extraction for an IBM SiGe HBT test sample device are given at the end of this chapter.


7-3

Compact Modeling of SiGe HBTs: Mextram

7.2

Transfer Current

The transfer current is maintained by the electron flow in vertical direction from the emitter contact to the collector buried layer and further up to the collector contact. The pure ohmic regions on that way are represented by the constant emitter resistance RE ¼ RE and collector resistance RCC ¼ RCC. The electron current density Jn in QNB and epilayer is assumed to obey the one-dimensional drift-diffusion equation Jn ¼ qmn n(x)

dfn (x) dx

(7:1)

where n is the electron concentration, fn is the electron quasi-Fermi potential, mn is the electron mobility, q is the elementary charge, and the x-axis is directed from the emitter toward the epilayer region. Moreover, in the model derivation the electron and hole concentrations are related by the pn product p(x)n(x) ¼

n2ie (x) exp

fpB fn (x) VT

(7:2)

where p is the hole concentration, nie is the position-dependent effective intrinsic carrier concentration, fpB is the constant hole quasi-Fermi level in the QNB, and VT is the thermal voltage.

Quasi-Neutral Base The electron current density (7.1), and transfer current IN, can be expressed in QNB with the help of the pn product (7.2) as fpB fn (x) IN n2ie (x) d exp Jn ¼ ¼ qVT mn (x) p(x) dx AE VT

(7:3)

where AE is the effective emitter area. Integrating (7.3) for constant Jn in the interval (xBE, xBC), where xBE and xBC denote the edges of the QNB, we have [7] IN ¼

fpB fn (xBE ) fpB fn (xBC ) qn2i AE exp exp G(p;xBE ,xBC ) VT VT

(7:4)

where ni is the intrinsic carrier concentration and the functional G(p;x1 ,x2 ) ¼

ð x2 x1

2 p(x) ni dx mn VT nie (x)

(7:5)

is well known as the Gummel number. The transfer current (7.4) is implemented in Mextram as IN ¼

IS VB2 VE1 VB2 VC2 exp exp gB VT VT

(7:6)

G(p; xBE , xBC ) 0 0 G(NA ; xBE , xBC )

(7:7)

where gB ¼


7-4


0 0 is the relative change of the Gummel number in QNB with BE and BC junction biases, xBE and xBC denote the edges of the QNB at zero bias, NA is the acceptor-doping concentration in the base and 0 0 ,xBC ) is transfer saturation current. The quasi-Fermi potentials in Equation 7.4 are IS ¼ qn 2i AE /G(NA;xBE replaced in Equation 7.6 by the corresponding Mextram nodal biases. Notice that the value of the electron quasi-Fermi potential fn(xBC) in Equation 7.4 is not directly associated with the nodal bias VC2. * Instead an effective value VC2 is used in Mextram (Level 504) as provided by the epilayer model description. The relative Gummel number gB in Equation 7.7 is further expressed in Mextram as product gB ¼ gBWgBH where

gBW ¼ 1 þ

0 0 G(NA ; xBE ,xBE ) G(NA ; xBC ,xBC ) þ 0 0 0 0 G(NA ; xBE ,xBC ) G(NA ; xBE ,xBC )

(7:8)

G(n; xBE ,xBC ) : G(NA ; xBE ,xBC )

(7:9)

and gBH ¼ 1 þ

The role of gBW is to describe the relative change of the Gummel number in QNB with the modulation of BE and BC depletion widths (Early effect). On the other hand, the term gBH accounts for the relative change of the Gummel number in QNB due to the minority electron concentration at high injection currents. Assuming a linear graded Ge profile (and bandgap Eg) in QNB, as shown in Figure 7.2, for the spatial dependence of (ni/nie)2 in Equation 7.5 holds:

ni nie

2

DEG / exp x qVT wB0

(7:10)

0 0 0 0 where wB0 ¼ xBC xBE is the width of QNB and DEG ¼ Eg(xBE ) Eg(xBC ) is the bandgap difference over the base (in eV), both evaluated at zero bias. Integrating Gummel numbers in Equation 7.8 for constant NA and mn using Equation 7.10, the term gBW becomes [18]

gBW

DEG wBE DEG wBC 1 exp 1 exp VT wB0 VT wB0 þ ¼1þ DEG DEG 1 exp 1 exp VT VT

(7:11)

0 0 xBE and wBC ¼ xBC xBC define the modulation of BE and BC depletion regions. Notice where wBE ¼ xBE that in the limiting case DEG ¼ 0, the term gBW is reduced to

NA = const QtC DEG

Eg

QtE xBE

FIGURE 7.2

0 xBE

Doping and bandgap distribution in the QNB.

0 xBC

xBC


7-5


0 gBW ¼1þ

wBE wBC þ wB0 wB0

(7:12)

representing the relative change of QNB width or Early factor [3]. The relative variation of the depletion widths in Equation 7.12 is implemented in Mextram in terms of the BE and BC depletion charges QtE and QtC as wBE(C) QtE(C) ¼ wB0 VER(F) CJE(C)

(7:13)

where CJE and CJC are zero-bias BE and BC depletion capacitances while VER and VEF are reverse and 0 becomes identical to the Early factor proposed in Ref. [19] for forward Early voltages. In that way, gBW silicon bipolar transistors. The model parameters VER and VEF may be interpreted for SiGe HBTs as the effective Early voltages that define the modulation rate of QNB width instead of the Gummel number. For an alternative way to account for the Early effect in SiGe HBTs, see Ref. [20]. The high-injection therm gBH is implemented in Mextram in terms of minority electron concentration as gBH ¼ 1 þ

1 n(xBE ) n(xBC ) þ 2 NA NA

(7:14)

which for simplicity assumes uniform nie and linear distribution of n in QNB. The required normalized electron concentrations in Equation 7.14 are evaluated solving the system of electroneutrality equation p ¼ n þ NA and pn product (7.2) at xBE and xBC as 2 n(x) nie VB2 fn (x) ¼F exp NA VT NA2 2z pffiffiffiffiffiffiffiffiffiffiffiffiffi F(z) ¼ 1 þ 1 þ 4z

(7:15)

* where fn(xBE) ¼ VE1 and fn(xBC) ¼ VC2 . This is also the place where the forward knee current IK is introduced in Mextram using

n2ie IS ¼ NA2 IK

(7:16)

but in principle it has the same physical role in the description of the high-current effects as the corresponding knee current parameter of the Gummel–Poon model [21].

Epilayer The drop of the electron quasi-Fermi potential over epilayer is essential for the correct evaluation of fn(xBC) and the transfer current IN if the transistor is operating in quasi-saturation [22]. In that case, the epilayer region, between 0 and wepi having uniform donor doping concentration ND, can be split into quasi-neutral injection region 0 < x < xi and drift region xi < x < wepi as shown in Figure 7.3. From the pn product (7.2) we have n(x)

dfn (x) VT d(p(x)n(x)) ¼ dx dx p(x)

(7:17)


7-6

Concentration


n (x) p (x) ND

0

wepi

Electric field

xi

FIGURE 7.3

x

E (xi)

Distribution of the carrier concentrations and electric field in the epilayer.

which together with the quasi-neutrality condition n ¼ ND þ p allows to express the electron current density (7.1) in the injection epilayer region as [23] Iepi 2 1 dp : Jn ¼ ¼ qmn ND VT þ ND p dx AE

(7:18)

Integrating Equation 7.18 in the injection region for constant Jn and introducing the epilayer resistance RCV ¼ wepi/(qmnNDAE), we have xi p(0) p(xi ) p(0) RCV Iepi ¼ VT 2 þ ln ND p(xi ) wepi

(7:19)

as an integral control relationship for the electron transport through the injection epilayer region. The normalized minority hole concentrations p(0)/ND and p(xi)/ND in Equation 7.19 are obtained similar to the electron normalized concentrations in Equation 7.15 as 2 p(x) nie VB2 fn (x) ¼F exp , ND VT ND2

(7:20)

but this time the doping related term nie2/ND2 is implemented as n2ie VDC ¼ exp VT ND2

(7:21)

where VDC is the BC built-in voltage. The drift epilayer region is neutral and has ohmic behavior as long as Iepi is significantly smaller than the critical current for velocity saturation IHC ¼ qAENDvsat, where vsat is the electron saturation velocity. Otherwise, the electron concentration becomes current dependent as n ¼ NDIepi/IHC and the electric field E(x) has slope defined by the Poisson equation Iepi dE(x) qND ¼ 1 dx « IHC

(7:22)


7-7


where « is the permittivity of the epilayer. It should be emphasized that for the drift electron transport holds E(x) ¼ dfn(x)/dx, which allows to directly evaluate the drop of fn over the drift epilayer region integrating the Poisson Equation 7.22 twice in the interval (xi, wepi). The result is

VC1 fn (xi ) ¼ E(xi )wepi dR þ

2 qND wepi

2«

Iepi 1 dR2 IHC

(7:23)

where dR ¼ 1 xi/wepi is the relative depth of the drift epilayer region. Using the interface condition E(xi ) ¼

vs IHC RCV ¼ wepi mn

(7:24)

2 /(2« IHC), Equation (7.23) and introducing the epilayer space charge resistance SCRCV ¼ qNDwepi becomes

VC1 fn (xi ) ¼ IHC RCV dR þ Iepi IHC SCRCV dR2

(7:25)

and represents the governing equation for the electron transport through the drift epilayer region if Iepi > IHC. The validity of Equation 7.25 could be extended to the ohmic case after transformation IHC IV IHC þ IV

(7:26)

VC1 fn (xi ) RCV dR

(7:27)

IHC ! where IV ¼

is the ohmic current in the drift epilayer region. The integral relationships (7.19) and (7.25) for the injection and drift epilayer regions still require an additional condition to close the system of equations for unknown Iepi, xi/wepi and fn(xi). It may be the continuation of the electric field as proposed in Ref. [22]. In order to avoid implicit model variables and to improve smoothness of the modeling equations, the present Mextram release (Level 504) implements the above epilayer physics in a qualitatively different way. Namely, the epilayer current Iepi, as seen from the circuit simulator, is evaluated only from Equation 7.19 applied to the whole epilayer. The governing Equations 7.19 and 7.25 are then employed in the evaluation of the effective electron quasi-Fermi * ¼ fn(xBC) that substitutes the nodal bias VC2 in all subsequent calculations. The detailed potential VC2 implementation procedure is given in Refs. [21,24].

7.3

Recombination Currents

The recombination currents in the intrinsic transistor region, due to the hole injection into quasineutral emitter (QNE) and BE space–charge region as well as recombination in QNB, actually serve to model the transistor forward base current. The ohmic part of the base region is represented by the constant base resistance RBC ¼ RBC. The electron and hole injection across BC junction, in the reverse transistor operation, is addressed in Mextram in the extrinsic transistor area. The carrier generation due to the weak avalanche effects is introduced separately as a controlled current source.


7-8


Intrinsic Transistor Region The carrier recombination in the intrinsic transistor region is indirectly evaluated in terms of the currents injected into quasi-neutral or space–charge regions. These currents are typically given in the form of a diode-like characteristics Vj ID (Vj ,I0 ,m) ¼ I0 exp 1 mVT

(7:28)

where Vj is the junction voltage, I0 is the diode saturation current, and m is the nonideality factor. The most important contribution to the static base current is the recombination (injection) in QNE. It is expressed in terms of the diode current (7.28) as IBE ¼ ID

IS ,1 VB2E1 , BF

(7:29)

where BF is the ideal forward current gain. The recombination in the QNB may produce significant impact on the performance of SiGe HBTs [11]. It could be physically evaluated as an additional current component IBB ¼ qAE

ð xBC xBE

Dn dx tn

(7:30)

where Dn is the excess minority carrier concentration and tn is the minority carrier lifetime in the QNB. Assuming that the excess minority concentrations at the QNB boundaries are proportional to the injection currents as [25] IS ,1 and Dn(xBE ) / ID VB2E1 , BF

IS Dn(xBC ) / ID VB2C2 ,1 , BF

(7:31)

the QNB recombination current (7.30) is implemented in Mextram as [18] IS IS wBC IBB ¼ XREC ID VB2E1 , , 1 þ ID VB2C2 ,1 1þ , BF BF w0

(7:32)

where XREC is the EB recombination current prefactor. Notice that the width modulation of QNB, especially that due to the BC depletion capacitance, produces an Early-like effect in the forward base current. The hole injection into QNE is essentially a two-dimensional phenomenon. Namely, part of the holes are injected along the sidewalls of the BE junction. Moreover, the hole injection is laterally nonuniform along the intrinsic base below the emitter due to the variations of the internal BE junction bias. The sidewall base current component is introduced by splitting the injection current into the vertical IB1 ¼ (1 XIBI)½(1 XREC)IBE þ IBB

(7:33)

and sidewall S IB1

IS ,1 ¼ XIBI ID VB1E1 , BF

(7:34)


7-9


components using diode partition factor XIBI. The distributed injection along the pinched transistor base below the emitter is emulated using a nonlinear current branch IB1B2 ¼

0 gBW VB1B2 VB1B2 þ 2VT exp 1 3 RBV VT

(7:35)

where RBV is the resistance of pinched base under the emitter at low injection and it may be approximately evaluated as RBV ¼

rWE 3LE

(7:36)

for the given pinched base sheet resistance r as well as emitter width and length WE and LE, respectively. The Shockley–Read–Hall (SRH) recombination in the BE space–charge region is implemented in Mextram as a nonideal diode current IB2 ¼ ID ðVB2E1 , IBF, MLFÞ þ Gmin VB2E1

(7:37)

where IBF is the saturation current and MLF is the emission coefficient of the BE leakage diode. Small conductance Gmin ¼ 1013 V1 in Equation 7.37 is introduced for numerical stability.

Extrinsic Quasi-Neutral Regions The current Iex describes the recombination of carriers injected into a quasi-neutral region of the extrinsic BC junction. It is evaluated by

Iex ¼

exp VVB1C1 1 T

IS ext BRI 1 þ 12 (n(xBC )=(NA ))

(7:38)

where BRI is the ideal reverse current gain, ext n(xBC ) IS VB1C1 ¼F exp NA IK VT

(7:39)

is the normalized electron concentration at the edge of extrinsic QNB, which is obtained in the same way as n(xBE) but for the bias VB1C1. In principle, Iex represents the ideal component of the reverse base current taking also high-injection effects into account. An additional extrinsic current component XIex, similar to Equation 7.38 but evaluated for internal bias VBC1, is introduced if the model flag EXMOD is set to 1. It is also assumed that SRH recombination in the BC space region contributes dominantly to the extrinsic base current component. This current component is derived from maximum value of the net SRH recombination in the space charge region as [4] IB3 ¼ IBR

expðVB1C1 =VT Þ 1 þ Gmin VB1C1 expðVB1C1 =VT Þ þ expðVLR=2VT Þ

where IBR is saturation current and VLR is the crossover voltage of the BC leakage diode.

(7:40)


7-10

page 10



Weak Avalanche Current The avalanche current Iavl is evaluated in Mextram as [26,27] Iavl ¼ Iepi

ð WAVL

an ðE(x)Þdx

(7:41)

0

where WAVL the effective width of the epilayer, the ionization rate an is given by [28] Bn an (E(x) ) ¼ An exp E(x)

(7:42)

and An and Bn are predefined model constants. Assuming the linear electric field distribution x EM E(x) ¼ EM 1 lD 1 þ x=lD

(7:43)

with the slope 1/lD around the maximum electric field value EM, Equation 7.41 may be integrated to express the weak avalanche current as Iavl

An Bn Bn WAVL exp : ¼ Iepi lD EM exp 1þ lD Bn EM EM

(7:44)

The maximum electric field value EM and lD are obtained from the Poisson Equation 7.22 in the epilayer. To this end, it is rewritten as Iepi dE(x) VAVL ¼2 1 dx WAVL2 IHC

(7:45)

where VAVL ¼ qND WAVL2/(2«) is the avalanche curvature voltage. If the model flag EXAVL is set to 1, the weak avalanche model handles also the electric field distribution in quasi-saturation due to the Kirk effect [21].

7.4

Substrate Current

Substrate current is implemented in Mextram using a simplified Gummel–Poon integral charge control relationship for parasitic PNP transistor:

Isub

VB1C1 1 2 ISS exp VT sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ ffi IS VB1C1 exp 1þ 1þ4 IKS VT

(7:46)

where ISS is PNP transistor saturation current and IKS is the substrate knee current. Notice that the effects of the base width modulation by depletion capacitances are neglected and VSC1 ¼ 0 is assumed. Moreover, the high-injection effects are expressed in terms of IS/IKS instead of ISS/IKS to simplify parameter extraction. An additional extrinsic substrate current component XIsub, similar to Equation 7.46, but evaluated for internal bias VBC1, is introduced if the model flag EXMOD is set to 1. A diodelike current ISF is added between the substrate and collector nodes, S and C1, to serve as an indicator of wrongly polarized SC junction.


page 11


7-11


It should be emphasized that Mextram equivalent circuit is deliberately left without any circuit elements connecting intrinsic substrate node S and the substrate contact. In that way, external substrate network of arbitrary complexity could be easily attached to the intrinsic substrate node [29].

7.5

Charges and Capacitances

The temporal variation of the electric field results in the displacement current components across the space–charge regions. These dynamic current components are represented by the depletion capacitances (charges). On the other hand, the temporal variation of the compensated (diffusion) charges, produces an effective dynamic recombination current along the transistor transfer current flow, which is implemented by the diffusion charges (capacitances). Mextram (Level 504) also takes account of the BE and BC parasitic overlap capacitances C0BE ¼ CBEO and C0BC ¼ CBCO as shown in Figure 7.1.

Depletion Capacitances The bias dependence of the depletion capacitances is in Mextram generally considered as Ct (Vj ) ¼ (1 Xp )

C0 fI 1

Vjeff (Vj )=Vbi

P þ Xp C0

(7:47)

where C0 is the zero bias depletion capacitance, Vj is the internal p–n junction bias, Vbi is the junction built-in voltage, and P is the grading coefficient. The expression (7.47) is inspired by the simple empirical description for depletion capacitance of abrupt (or linear) p–n junctions but also enhanced, with quantities Xp and fI as well as function Vjeff(Vj), to increase the physical and computational range of the model validity. In order to avoid singular capacitance behavior at the forward bias, an effective junction bias Vjeff(Vj) is employed in the denominator of Equation 7.47. It is related to the real junction bias Vj as Vjeff (Vj )

Vj VF ¼ Vj Vch ln 1 þ exp Vch

(7:48)

where the control voltage

1=P VF ¼ Vbi 1 aj

(7:49)

forces the capacitance to asymptotically approach the constant value ajC0 for Vj > VF (see Figure 7.4). The smoothness of this transition is defined by Vch. The quantity Xp in Equation 7.47 limits the decrease

C t (Vj)

a jC0

VF

FIGURE 7.4

Implementation of the Mextram depletion capacitances.

Vbi

Vj


7-12

page 12



of the capacitance under the reverse bias. It is of particular importance for BC depletion capacitance having a fully depleted epilayer region. Finally, the term fI accounts for the modulation of the BC depletion capacitance by the transfer epilayer current. It is defined as fI ¼

Iepi 1 Iepi þ IHC

MC (7:50)

where MC is the current-modulation coefficient. Table 7.1 provides the corresponding model parameters in Mextram for the BE, BC, and SC junctions. For compact modeling purpose, it is more convenient to consider corresponding depletion charges Qt (Vj ) ¼

ð Vj 0

Ct Vjeff (Vj ) dV

(7:51)

instead of the depletion capacitances. The Mextram depletion charges (see Figure 7.1) are implemented as QtE (VB2E1 ) ¼ ð1 XCJEÞQt ðVB2E1 Þ

(7:52)

S QtE (VB1E1 ) ¼ XCJE Qt ðVB1E1 Þ QtC (VB2C2 ) ¼ XCJC Qt VjC (VB2C2 )

(7:53)

Qtex (VB1C1 ) ¼ ð1 XCJCÞð1 XEXTÞQt ðVB1C1 Þ

(7:55)

XQtex (VBC1 ) ¼ ð1 XCJCÞXEXT Qt ðVBC1 Þ

(7:56)

QtS (VSC1 ) ¼ Qt ðVSC1 Þ

(7:57)

(7:54)

where XCJE, XCJC, and XEXT are geometry partitioning factors splitting the depletion capacitances into vertical and sidewall components as well as between intrinsic and extrinsic parts of the transistor. Notice that the internal BC junction bias VjC in Equation 7.54 has to be evaluated implicitly as a function of bias VB2C2 in order to correctly take into account the effects of quasi-saturation in the epilayer [21].

Diffusion Charges The diffusion charges are evaluated in Mextram independently for the QNB, QNE, and epilayer as well as for the extrinsic transistor region. For the linear distribution of electrons in QNB, the total base diffusion charge is 0 QB ¼ QB0 gBW

1 n(xBE ) n(xBC ) þ 2 NA NA

(7:58)

where QB0 ¼ qAEwB0NA. In the quasi-static approximation, the base diffusion charge (7.58) is split into BE and BC components QBE and QBC as TABLE 7.1

BE BC SC

Parameters for the Depletion Capacitances Vbi

C0

P

Xp

fI

VDE VDC VDS

CJE CJC CJS

PE PC PS

— XP —

— MC —


page 13


7-13


1 0 n(xBE(C) ) QBE(C) ¼ TAUB IK gW 2 NA

(7:59)

and associated with Mextram nodes E1 and C2. The model parameter TAUB ¼ QB0/IK is introduced as base transit time. The diffusion charge in the QNE (including the compensated charge in the BE space–charge region) is expressed as VB2E1 1 QE ¼ QE0 exp MTAU VT

(7:60)

where MTAU is the emitter diffusion charge coefficient. The emitter transit time can be approximately expressed from Equation 7.60 as t E (IN )

QE0 IN 1=MTAU : IN IS

(7:61)

Introducing a emitter transit time as TAUE ¼ tE(IK), the prefactor QE0 in Equation 7.60 becomes 1=MTAU IS QE0 ¼ TAUE IK IK

(7:62)

as it is implemented in Mextram. The epilayer diffusion charge Qepi ¼ qAE

ð xi p(x)dx

(7:63)

0

actually represents the hole (minority carrier) charge in the injection epilayer region. This charge can be related to the epilayer current by the Gummel integral charge relationship Iepi ¼

q2 n2i A2E Dn V VB2 fn (xi ) : exp B2C2 exp VT Qepi VT

(7:64)

2 Introducing the epilayer transit time TEPI ¼ Wepi /(4Dn) and with the help of pn product (7.2), the epilayer diffusion charge can be expressed also as

Qepi ¼

2 Qepi0

4 TEPI Iepi

p(0) p(0) p(xi ) p(xi ) þ1 þ1 ND ND ND ND

(7:65)

4 TEPI VT : RCV

(7:66)

where Qepi0 ¼ qAE Wepi ND ¼

For practical implementation in Mextram, expression for Qepi is combined with the expression for the epilayer current Iepi and further simplified [21,30]. The extrinsic diffusion charge is evaluated combining expression for the injection in QNB and epilayer in extrinsic part of the transistor:


7-14

page 14



Qex ¼

ext ext TAUR 1 n(xBC ) p(xW ) QB0 þ Qepi TAUB þ TEPI 2 NA ND

(7:67)

where TAUR is the reverse base transit time, ext p(xW ) VB1C1 VDC ¼ F exp ND VT

(7:68)

ext while n(xBC )/NA is given in Equation 7.39. Further partition of the extrinsic diffusion charge, similar to that of the extrinsic injection currents, is possible if the model flag EXMOD is set to 1. In that case, the similar expression to Equation 7.67 is used to evaluate the extrinsic charge XQext in terms of junction bias VBC1 and the BC diode partition factor XEXT is used to split their contributions.

Distributed and Non-Quasi-Static Charges In high-frequency and high-speed applications, the quasi-static assumption is no longer valid. Moreover, the effects of the distributed capacitances along the BE junction should be taken into account. The high-frequency current-crowding effects are modeled introducing an effective charge branch QB1B2 ¼

1 dQB2E1 VB1B2 5 dVB2E1

(7:69)

where QB2E1 ¼ QtE þ QBE þ QE The non-quasi-static effects in QNB base are accounted for in Mextram introducing charge partitioning: QBC ! 1=3QBE þ QBC

and

QBE ! 2=3QBE

(7:70)

Both modeling options require the flag EXPHI to be set to 1.

7.6

Thermal Phenomena

The electrical characteristics of bipolar transistors are particularly susceptible to temperature variations due to the self-heating or thermal interaction with other devices. The electrothermal effects are implemented in Mextram as a combination of the electrical model (current and charge branches), with temperature-dependent parameters, and thermal model, that links the device average temperature to the dissipated electrical power. The temperature-scaling parameters are based on strong physical background of the electrical parameters. The default Mextram thermal model is one-pole linear thermal impedance (parallel thermal resistance RTH and thermal capacitance CTH of the device surrounding) connected between the external thermal node dT and zero bias (ambient) device temperature. If it is necessary, the default thermal impedance may be suspended and bypassed by a more advanced thermal network via external thermal node. In order to correctly take into account the time delays of the internal biases, the total dissipated power in the device is evaluated as a sum of the power dissipated in all nonreactive circuit elements separately. Most of the Mextram current and charge-modeling expressions have explicit temperature dependence. The actual device temperature is expressed as T ¼ TA þ DTA þ VdT þ 273:15

ðKÞ

(7:71)

where TA is the ambient (simulation) temperature in 8C, parameter DTA specifies constant temperature shift to ambient temperature and VdT is the temperature at the thermal node dT. The electrical potential


page 15


7-15


at the thermal node dT actually represents the excess device temperature. The temperature at which the electrical parameters are extracted is the reference temperature TREF in 8C or Tref ¼ TREF þ 273.15 in kelvin. The model parameters depend implicitly on temperature via intrinsic carrier concentration and carrier mobility temperature dependence. The temperature dependence of the intrinsic carrier concentration is VG n2i / tN3 exp VDT

(7:72)

where tN ¼

T Tref

1 q 1 1 ¼ VDT k T Tref

(7:73) (7:74)

k is the Boltzmann constant and * may be B, C, S, and J for the bandgap in base, collector, substrate, and BE depletion region, respectively. This approach is particularly suitable for HBTs with varying bandgap across the device. The carrier mobility is scaled with temperature as m / tNA

(7:75)

where * may be E, B, EX EPI, C, and S for the emitter, base, extrinsic base, epilayer, collector, and substrate region, respectively. A few temperature-scaling parameters, that could be particularly important for SiGe HBT applications, are introduced separately for certain electrical parameters. The forward and reverse current gain parameters BF and BRI depend on the difference of bandgaps at BE and BC junctions. Their temperature dependence is additionally expanded by DVGBF(R) BF(RI) / exp VDT

(7:76)

where DVGBF and DVGBR are the bandgap voltage differences. It is well known that the compensated charge in the BE space–charge region could have significant effect on the dynamic performance of SiGe HBTs [25]. This charge also has different temperature dependence then the base diffusion charge. In Mextram, it may be easily taken into account by the temperature dependence DVGTE TAUE / exp VDT

(7:77)

where DVGTE is the emitter transit time bandgap voltage difference. Finally, the base zero-bias charge QB0 has a separate temperature-scaling coefficient AQBO. Since it accounts also for the temperature dependence of wB0, it is crucial for the temperature scaling of Early voltages VER and VEF but also Gerelated parameter DEG as DEG / tNAQBO :

(7:78)

Figure 7.5 shows the complete set of Mextram temperature-scaling parameters associated with the different bandgap or doping areas along the transistor structure.


7-16

page 16



VGB

DVGBR

DVGBF

VGC

VGJ DVGTE

VGS

AEX

AE

AC AB

AQBO

FIGURE 7.5

7.7

AEPI

AS

Temperature-scaling parameters.

Parameter Extraction

The accuracy of compact models in circuit simulation depends not only on the correct physical description of various physical phenomena in the device but also on a reliable, robust, and unambiguous parameter extraction methodology. It should be emphasized that a general and fully automatic parameter extraction procedure is not currently available. The unambiguous determination of individual parameter values in the parameter extraction procedure could be seriously hampered by the correlation among the parameters. In order to minimize the correlation among electrical and temperature-scaling Mextram parameters, the electrical parameters may be split into parameters extracted at low-injection- (not affected by the self-heating) and high-injection-related parameters. Moreover, in order to further reduce the parameter correlation, the electrical and temperature-scaling parameters could be further split into small groups that are extracted subsequently, in the direction of their dominant dependence, from the measured data sensitive to the selected parameters. An example of such slitting for Mextram parameter extraction is given in Table 7.2 for low and Table 7.3 for high-injection extraction step, respectively. The more detailed discussion on Mextram parameter extraction is given in Ref. [31]. As a practical example of the full Mextram (Level 504) parameter extraction, we present here the results for the IBM self-aligned high-breakdown 0.32 mm BiCMOS SiGe graded-base test technology. It has been offered by IBM as a nonproduction test vehicle for free data exchange in compact model evaluation and standardization effort [32]. The measurement data have been provided for five different temperatures. The comparisons between measured data and Mextram characteristics for a single device, having emitter length of 16.7 mm, are shown in Figure 7.6 to Figure 7.11. The characteristics of the static current gain, reverse Gummel plot, output characteristics, and cutoff frequency at reference temperature of Tref ¼ 258C are shown in Figure 7.6 to Figure 7.9, respectively. Figure 7.10 and Figure 7.11 show the result of the collector current and cutoff frequency temperature scaling.


page 17


7-17


TABLE 7.2

Extraction of the Low-Injection Parameters

Characteristics

Electrical Parameters

Scaling Parameters

BE depletion capacitance BC depletion capacitance SC depletion capacitance Forward–Early Reverse-Early Forward-Early Forward-Gummel (Ic) Forward-Gummel (Ib) Re-flyback Rc-active Reverse-Gummel (Is) Reverse-Gummel (Ib)

CJE, PE, VDE CJC, PC, XP CJS, PS, VDS WAVL, VAVL, XREC VER VEF IS BF, IBF, MLF RE RCC ISS, IKS BRI, IBR, VLR

VGB VGC VGS

TABLE 7.3

AQBO AQBO VGB, AB DVGBF, VGJ AE AC VGS, AS DVGBR, VGC

Extraction of the High-Injection Parameters

Characteristics

Electrical Parameters

Output-characteristic Forward-Gummel Cutoff frequency Reverse-Gummel

RTH, IK RCV, VDC SCRCV, IHC, TAUE, TEPI TAUB XEXT

Scaling Parameters

DVGTE, AEPI

70 60

Ic /Ib

50 40 30 20 10 0 10−11 10−10 10−9 10−8 10−7 10−6 10−5 10−4 10−3 10−2 10−1 Ic (A)

FIGURE 7.6

The static current gain versus collector current.


7-18

page 18



10−2 10−3 10−4

Ie,Ib (A)

10−5 10−6 10−7 10−8 10−9 10−10 10−11 0.4

FIGURE 7.7

0.5

0.6

0.7 0.8 Vbc (V)

0.9

1

1.1

The reverse Gummel plot. 10 Ib = 0.12 µA Ib = 1.2 µA Ib = 6 µA Ib = 15 µA Ib = 30 µA Ib = 45 µA Ib = 60 µA

I c (mA)

8

6

4

2

0 0

FIGURE 7.8

1

2

3 Vce (V)

4

5

Output characteristics. 30 25

Ft (GHz)

20 15 10 0 0 10−4

Vcb = −0.3 V Vcb = 0 V Vcb = 1V Vcb = 2 V Vcb = 3 V 10−3

10−2 Ic (A)

FIGURE 7.9

Cutoff frequency versus collector current.

6


page 19


7-19


10−1 10−2 10−3 10−4

Ic (A)

10−5 10−6

T = 25⬚C T = 125⬚C T = 85⬚C T = 55⬚C T = −15⬚C

10−7 10−8 10−9 10−10 10−11

0.4

FIGURE 7.10

0.5

0.6

0.7

0.8 0.9 Vbe (V)

1

1.1

1.2

Gummel plot of the collector current at different temperatures.

30 25

Ft (GHz)

20 15 10 5 0 10−4

T = 25⬚C T = 125⬚C T = 85⬚C T = 55⬚C T = −15⬚C 10−3

10−2 I c (A)

FIGURE 7.11

Cutoff frequency versus collector current at different temperatures.

Acknowledgments The author would like to thank IBM for providing the measurement data for Mextram parameter extraction and Philips Research Laboratories for continuous support of the compact modeling activities at Laboratory of High-frequency Technology and Components, Delft University of Technology, The Netherlands.

References 1. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston: Artech House, 2003. 2. HC Graaff and WJ Kloosterman. New formulation of the current and charge relations in bipolar transistor modeling for CACD purposes. Trans Electron Dev 32:2415–2419, 1985. 3. IE Getreu. Modeling the Bipolar Transistor. Amsterdam: Elsevier, 1978.


7-20

page 20



4. HC de Graaff and FM Klaassen. Compact Transistor Modeling for Circuit Design. New York: SpringerVerlag, 1990. 5. JCJ Paasschens and WJ Kloosterman. The Mextram Bipolar Transistor Model—Level 504. Nat Lab Unclassified Report, NL-UR 2000/811, Koninklijke Philips Electronics, 2001. 6. HK Gummel and HC Poon. An integral charge control model of bipolar transistors. Bell Syst Tech J 49:827–852, 1970. 7. HK Gummel. An charge control relation for bipolar transistors. Bell Syst Tech J 49:115–120, 1970. 8. SL Salmon, D Cressler, RC Jaeger, and DL Harame. The influence of Ge grading on the bias and temperature characteristics of SiGe HBTs for precision analog circuits. IEEE Trans Electron Dev 47:292–298, 2000. 9. CT Kirk. A theory of transistor cutoff frequency (fT) falloff at high current densities. IRE Trans Electron Dev 9:164–174, 1962. 10. LCN de Vreede, HC de Graaff, K Mouthaan, M de Kok, JL Tauritz, and RGF Baets. Advanced modeling of distorsion effects in bipolar transistors using the Mextram model. IEEE J Solid-State Circuits 31:114–121, 1996. 11. G Niu, JD Cressler, and AJ Joseph. Quantifying neutral base recombination and the effects of collector–base junction traps in UHV/CVD HBTs. IEEE Trans Electron Dev 45:2499–2504, 1998. 12. HC Wu, S Mijalkovic´, and JN Burghartz. Parameter extraction of scalable Mextram model for highspeed SiGe HBTs. Proc 2004 Bipolar/BiCMOS Circuits and Technology Meeting, Montreal, 2004, pp. 140–143. 13. E So¨nmez, A Trasser, P Abele, KB Schad, and H Schumacher. Integrated receiver components for low-cost 26 GHz LMDS applications using an 0.8 mm SiGe HBT technology. 33rd European Microwave Conference, 2003, pp. 399–402. 14. P Deixler, HGA Huizing, JJTM Donkers, JH Klootwijk, D Hartskeerl, WB de Boer, RJ Havens, R van der Torn, JCJ Paasschens, WJ Kloosterman, JGM van Berkum, D Terpstra, and JW Slotboom. Exploration for high perfomance SiGe-heterojunction bipolar transistor integration. Proc 2001 Bipolar/BiCMOS Circuit and Technology Meeting, 2001, pp. 30–33. 15. U Erben and E So¨nmez. Fully differential 5 to 6 GHz low noise amplifier using SiGe HBT technnology. Electron Lett 40:39–40, 2004. 16. WC Hua, TY yang, and CW Liu. The comparison of isolation technologies and device models on SiGe bipolar low noise amplifier. Appl Surf Sci 224:425–428, 2004. 17. F Yuan, Z Pei, JW Shi, ST Chang, and CW Liu. Mextram modeling of Si/SiGe heterojunction phototransistors. Proc 2003 International Semiconductor Device Research Symposium, 2003, pp. 92–93. 18. JCJ Paasschens, WJ Kloosterman, and RJ Havens. Modeling two SiGe HBT specific features for circuit simulation. Proc 2001 Bipolar/BiCMOS Circuit and Technology Meeting (BCTM), Minneapolis, 2001, pp. 38–41. 19. CC McAndrew and LW Nagel. Early effect modeling in SPICE. IEEE J Solid-State Circuits 31:136– 138, 1996. 20. S Mijalkovic´. Generalized Early factor for compact modeling of bipolar transistors with nonuniform base. Electron Lett 39:1757–1758, 2003. 21. JCJ Paasschens, WJ Kloosterman, and R vd Toon. Model Derivation of Mextram 504. Nat Lab Unclassified Report, NL-UR 2002/806, Koninklijke Philips Electronics, 2002. 22. HC de Graaff and WJ Kloosterman, Modeling of the collector epilayer of a bipolar transistor in the Mextram model. IEEE Trans Electron Dev 42:274–282, 1995. 23. GM Kull, LW Nagel, S Lee, P Lloyd, EJ Prendergast, and H Dirks. A unified circuit model for bipolar transistors including quasi-saturation effects. IEEE Trans Electron Dev 32:1103–1113, 1985. 24. JCJ Paasschens, WJ Kloosterman, RJ Havens, and HC de Graaff. Improved compact modeling of output conductance and cutoff frequency of bipolar transistors. IEEE J Solid-State Circuits 36:1390– 1398, 2001. 25. M Reisch. High-Frequency Bipolar Transistors. Berlin: Springer-Verlag, 2003.



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26. WJ Kloosterman and HC de Graaff. Avalanche multiplication in compact bipolar transistor model for circuit simulation. IEEE Trans Electron Dev 36:1376–1380, 1989. 27. WJ Kloosterman, JCJ Paasschens, and RJ Havens. A comprehensive bipolar avalanche multiplication compact model for circuit simulation. Proc 2000 Bipolar/BiCMOS Circuit and Technology Meeting, 2000, pp. 172–175. 28. AG Chynoweth. Ionization rates for electron and holes in silicon. Phys Rev 109:1537–1540, 1958. 29. M Kleeme and E Barke. An extended transistor model for substrate crosstalk analysis. Proc IEEE 1999 Custom Integrated Circuit Conference, 1999, pp. 579–582. 30. LCN de Vreede, HC de Graaff, JL Tauritz, and RGF Baets. Extension of the collector charge description for compact bipolar epilayer models. IEEE Trans Electron Dev 45:277–285, 1998. 31. JCJ Paasschens and WJ Kloosterman. Parameter Extraction for the Bipolar Transistor Model Mextram—Level 504. Nat Lab Unclassified Report, NL-UR 2001/801, Koninklijke Philips Electronics, 2001. 32. D Sheridan, MR Murty, W Ansley, and D Harame. IBM Bipolar Model Standardization: VBICMEXTRAM-HICUM. Compact Model Counsil (CMC), Puerto Rico, April 2002.


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8 CAD Tools and Design Kits 8.1 8.2 8.3 8.4 8.5

Introduction......................................................................... Schematic Capture .............................................................. Design Simulation ............................................................... Physical Design .................................................................... Physical Verification ............................................................

8-1 8-2 8-4 8-5 8-6

Layout versus Schematic . Parasitic Extraction (PEX)

Sue E. Strang IBM Microelectronics

8.1

8.6 8.7

Chip Assembly ................................................................... 8-10 Chip Finishing ................................................................... 8-11

Introduction

Design projects are comprised of several phases, specification definition, design, and manufacture. The design phase spans the flow inputting information from the specification phase and outputting information to the manufacturing phase (Figure 8.1). To facilitate a design, computer-aided design (CAD) tools are integrated into the flow and customized to aid the designer. A process design kit (PDK) is a complete set of building blocks that are critical for any custom-integrated circuit design. The fundamental elements of a PDK consist of documentation, models for device and macros, schematic symbols, simulation support, physical design elements for device and routing options, technology files and physical verification rule decks for manufacturability and signal integrity. PDK development and support integrated into pure play foundry have proven an essential edge for foundries and customer-owned tooling (COT) vendors. A proven design methodology flow can take years to develop and is continuously improving to address the rapid transitions of technologies to tighter lithography and broader frequencies. Silicon germanium allows for integration of large digital content with high-frequency analog components (Figure 8.2) requiring a mixture of tools for system-level verification [1]. System and circuitlevel design methodologies are integrated within a CAD framework of tools. This framework links the various design stages, design entry, simulation, physical layout, and verification with multiple point tools. The design framework provides a high-level extension language, which can access the design database and provide a means for data translation between different tools as well as a mechanism for developing custom software. The design cycle is a highly iterative process, successive simulations are performed to optimize a circuit, layouts are optimized for matching, form factor and parasitic reduction, recursive verifications are run and layouts altered to match design rules, connectivity checks and simulations from layout data may cause updates to the original schematic placing the designer back to the electrical design stage. A framework of tools enables easy flow between tools allowing for a more efficient design process, especially when a single design database is shared. A discussion of the tools used in design phase of a custom and semi-custom design follows. The supporting PDK is developed to optimize the available CAD tools within each stage to reduce design cycles and to reduce or eliminate hardware fabrication errors. 8-1


8-2


Manufacture

Design

Specification

Phases of IC Design Phase Techology definition Testsite design Device characterization Circuitry design Simulation Physical design Design verification

Schematic capture Design simulation RF − Analog − Mixed Mode − Digital Physical design Polygon-cell block layout, Place and Route Design verification DRC, ERC, LVS, PEX, Resimulation

Foundry verification Fill and level Generation Mask generation

Chip assembly and verification Pads, block placement, Routing, DRC Chip finishing GDS2, Tape out for manufacture

FIGURE 8.1

Design framework flow.

FIGURE 8.2

Integrated analog and digital PRML design with 1200 SiGe HBT and >1,000,000 gates.

8.2

Schematic Capture

Design entry begins with the placement of devices or circuits from a library. A library is a collection of devices and circuits with symbolic and physical representations. Devices developed for RF custom libraries include DC MOSFETs, RF MOSFETs, BJTs, polysilicon, diffusion and metal resistors, MOS, metal–insulator–metal and vertically stacked capacitors, hyper-abrupt, MOS and collector–base varactors, Schottky Barrier and forward-biased diodes, ESD devices, symmetric spiral inductors, stacked inductors, programmable fuses, bondpads, transmission lines, and transformers. These devices are modeled primitives characterized in a technology and optimized for design use. Artwork for these


8-3

CAD Tools and Design Kits

devices is provided in the library for placement in schematics to form an electrical representation of a circuit. While many devices have industry standard artwork associated with them, custom changes such as color or text may be used to describe layout characteristics or design usage. These devices are used as building blocks to create an electrical representation of a circuit. Figure 8.3 shows a schematic representation of a differential amplifier. For each primitive a set of parameters are defined for use within circuit simulation and physical representation of the device as well as informational applications such as device current ratings. These parameters are used within the model to adjust the intrinsic model parameters per design dimensions and usage. Parameters such as self-heating and impact ionization and simulation frequencies describe design usage. The physical parameters describe the geometry and characteristics of the device. For MOSFETs parameters such as the length, width, number of channels, gate extensions, contact location, and bulk guard ring inclusion are defined. For passive devices like an inductor, parameters such as outer dimension, number of turns, line width, spiral spacing, underpass characteristics, metal stacking, groundshield pattern, and inductance are defined. For BJTs reliability parameters may be defined to determine the rated current for the device and the base wiring. Each parameter describes a physical characteristic of the device, which is used to build the layout (Figure 8.4). For optimization, device parameters may be defined as variables or expressions for variation within circuit simulation. A series of simulations is launched based on these parameters, initiating an iterative loop within the simulation. A family plot from the simulation results may be analyzed to select the optimal value of the parameter.

vdd

W=4.5U l=180n nf=2 m=1

vdd

pfet

pfet W=4.5U l=180n nf=2 m=1

out

enl=3U performance=Low fT nstripe=1

inp

enl=3U performance=Low fT nstripe=1 npn reff-169.83 W-8U l=5.06U

npn

inn

Polyres

nfet

nref

W=7.2U l=180n nf=1 m=1 gnda

FIGURE 8.3

Device library symbols used in a differential amplifier circuit.

nfet W=7.2U l=180n nf=1 m=1 gnda


8-4


drain

gate

bulk

source

Model subcircuit

FIGURE 8.4

Device symbol

Device layout

RF MOSFET model subcircuit, symbol, and layout representations.

For nonphysical, calculated parameters such as resistance, capacitance, and inductance, these values must be calculated within the model or preprocessor when a variable is defined. Linking CAD tools that require electrical or schematic input, such as circuit simulators and layout versus schematic (LVS) tools, requires a netlist of the circuit. The netlist is a text file defining the component name, device ports, connectivity, and the device parameters. Each device is prefixed by a character describing its type and may be defined as hierarchical. This information is unique for each simulator, and custom procedures can be written to adjust the information based on technology or application. For example, to pass a nonphysical parameter to LVS such as multiplicity, the component name may be altered or an additional parameter may be listed to group-like devices and verify multiplicity.

8.3

Design Simulation

A large-scale complex IC design may comprise of RF, analog, and digital elements requiring different simulation methods for each section. RF analysis is required for predicting RF and microwave behavior, transient and frequency analysis for analog circuitry, and high-level behavioral for logic applications. Several circuit simulations are available for these specific design types. Two types of algorithms are available for simulating RF characters in circuits such as power amplifiers, low-noise amplifiers, mixers, and voltage-controlled oscillators (VCOs) [2]. These are periodic steadystate (PSS) and harmonic balance (HB). The PSS algorithm is an RF simulation extension to a transient simulation engine, which assumes that a periodic signal exists in the system [3]. The HB engine is a pure frequency-domain approach. If the input signal is small enough that nonlinear elements in the circuit do not significantly distort the signal output, then the small-signal simulation gives valid results. However, as the input signal becomes increasingly large, new frequencies appear at the output. Harmonic balance solves for each of these new frequencies. Analog circuit simulation provides transistor-level analysis and net connectivity using compact models in multiple domains including time and frequency. Manufacturing and yield analysis can be done through statistical Monte Carlo simulations and corner analysis to emulate process variations. Nonuniformity in semiconductor processing produces differences in like devices due to lithography and etch processes, conductivity gradients, thickness differences due to polish differences, and thermal distribution across the chip. These differences cause mismatches in device behavior, which can be analyzed in statistical simulation runs. Digital macros can be modeled as top-level behavioral models at the system level. A mixed-mode simulation system analyzes both analog and digital.



8-5

Safe operating areas (SOA) are set by a technology and determined based on simulation results. A simulation can be augmented by additional analysis to show instantaneous voltage and currents and dynamically warn about any violations in the transistors if the SOA is exceeded ensuring reliability. Other simulation enhancement tools are defined to input manufacturing process bias and variability to specific model parameters to target device performance after fabrication. A post-circuit-simulation analysis determines critical operating range for the specifications and indicates the need to adjust device dimensions to tolerate circuit conditions based on current, voltage, or temperature. Circuit performance is affected by the physical layout of the circuit, therefore specific layout techniques such as device matching or bulk connection proximity must be passed to the physical stage.

8.4

Physical Design

Physical layout and interconnect in RF designs requires customization in order to control parasitic effects and match circuits for optimal performance. Physical representations of devices may be drawn custom by manually placing each layer to construct a unique device or interconnect. While this allows for highly specialized devices, this is tedious and prone to design rule errors. Another method is to use predrawn devices that are highly characterized. These, however, may not suit the design needs by limiting the possible configurations and form factors. To this end, programmable devices are developed within a library. These devices may be varied in shape by geometry inputs and optionally add in wiring, contacts, extensions, or repetition of shapes specified by designer input. These programs take the device parameters and create design rule correct device layouts to produce designs ready for manufacture. Figure 8.5 shows a graphical representation of a symmetric inductor and the same device after processing. Stretching of geometric shapes and conditional inclusions of device options allows for flexibility in layout. This methodology can be extended hierarchically to create programmable circuits in which design points are entered and a layout is generated. In reality, all described methods custom, fixed, and programmable are used for a design to meet the design criteria. In addition to device design, programmable cells may be created to assist in sound layout practices for silicon germanium technologies. These include the formation and properties of noise-isolating moat structures, guard rings, substrate contact techniques to achieve optimum device matching, and prevention of electromigration failure and voltage drops through proper metallization. Isolation moats place a

FIGURE 8.5

Inductor layout in CAD tool and manufactured inductor.


8-6


region of high resistance between two circuits, or separate areas of the chip, to reduce noise or signal coupling through the substrate. Guard rings form a barrier to the input of ionic contaminants, which are highly mobile in silicon dioxide, by surrounding the device or the die with a wall of metal. The contacts of the isolation guard ring may be switched off or sections may be removed for chaining of devices. Substrate contacts maintain the substrate potential to the desired voltage levels and assure that local potential variations are minimized to prevent latch-up, especially in highly resistive substrates. In the layout, good matching can be attained by keeping like devices close together or adjacent, placing groups of devices around a common center, orienting devices in the same direction, or using identical layouts. Abutment of MOSFET devices allows for devices to be merged into a single diffusion. The use of schematic-driven-layout streamlines the physical design process. The schematic is used to drive the placement within the physical design and assist in routing. Placement aids allow for predefinition of topology and routing aids guide interconnect for design constructs using recommended wiring layers and widths according to electromigration guidelines. Devices should be constructed with terminals with a predefined permutation rule for autorouting.

8.5

Physical Verification

Design rule requirements are imposed to ensure a variety of quality metrics, including area, timing, power, and yield. Each process step requires mask-layer design for fabrication. Analysis is required on the physical shapes generated by the physical design phase to verify the process steps for manufacturing and tool requirements. Design rule checking (DRC) is a requirement for fabrication and assures manufacturability. Process layers are checked for interaction between layers, metallization vias, overlay tolerances, width and separation limits, shape integrity (Figure 8.6). CAD tools are available to measure physical shapes hierarchically or for flat shapes for specified design rules and report design rule violations to the designer. Some process and design techniques checked in the DRC are discussed in the following sections. Antenna rules are introduced to identify process-induced gate oxide damage caused when exposed polysilicon and metal structures, connected to a thin oxide transistor, collect charge from the processing environment such as reactive ion etch. When a sufficiently large potential is developed, a current may propagate through the thin oxide. Unchecked occurrences may result in reduced performance or nonfunctional devices when exposed to process-induced damage. Gate oxide damage due to charging may be avoided by providing an alternate discharge path from the gate node to the substrate. A diode to substrate is an effective means to prevent charge build up across the gate dielectric. At wafer processing temperatures, the diode is sufficiently conductive to prevent any charge build up, and the potential is at maximum the junction breakdown voltage. At normal circuit operation temperatures, the diode is in a low-leakage reverse biased state. The manufacturing process utilizes chemical–mechanical polishing (CMP) to achieve planarity on a wafer. This process feature requires that the variations in density on a layer be restricted and must be

Spacing error FIGURE 8.6

Example of design rule checks.

Width violation

Overlap error



8-7

verified on a global and local area of the wafer. When densities are not sufficient, automatic placement of fill shapes may be added to a design in sparse regions to increase density or densities may be decreased by slotting or cutting holes in a layer. Copper lines are desirable for low resistance in the line, however, due to the soft structure of the material dishing may occur [4]. To achieve planarity slots may be required to be drawn in the conductor layers. Lines may be auto-filled or auto-slotted using CAD tools or devices may contain the fill techniques within the cell design. For sensitive circuitry such as transmission lines, fill shapes may be introduced in the library device to channel the signal current in the line for better modeling (Figure 8.7). Motion of electrons of a metal conductor, such as aluminum, in response to the passage of high current through it, may lead to the formation of voids within the conductor. These voids can grow to a size where the conductor is unable to pass current. Electromigration is aggravated at high temperature and high current density, and therefore, is a reliability concern. Electromigration is minimized by limiting current densities and by adding metal impurities such as copper or titanium to the aluminum. These conditions can be highlighted through CAD tools by overlaying the simulation results of current flow through the physical dimensions as designed in the layout and determining the current density of the conducting material. This electrical rule check (ERC) will highlight these conditions to the designer that may result in malfunctioning designs. The design for manufacturing (DFM) approach identifies trouble spots in a design and provides the important data that allow the designer to determine a cost–yield analysis. DFM checks are sets of recommended rules in which the tolerance is set to a statistically altered value to increase the chip yield. Separate DRC checks for DFM rules are used and results may be analyzed to determine concentrations of shapes, which exceed the DFM limits.

Layout versus Schematic When physical design is completed, a verification check is necessary to compare the generated physical design to the simulated electrical design. This is the LVS process. Physical shapes are analyzed and matched to predetermined devices. Correctly formed devices as determined by the manufacturer are extracted. The device design and the extraction code must be developed such that the device can be

FIGURE 8.7

Manual fill lines channel the current for better modeling, auto-generated fill inhibits current flow.


8-8


recognized by the extraction code as the device is built. These devices are checked for net connectivity and compared to that simulated in the schematic representation. Physical dimensions for these devices, which are used in the device model are compared with those which were simulated in the schematic. Standard comparison routines may be used for simple well-known devices and design styles, but many devices include unique parameterization, especially RF-type circuitry. These elements require custom comparison procedures. Inconsistencies are reported to the designer. Design practices involving connectivity are also checked during the LVS process. A common design practice for MOSFET layout is to interdigitate the devices in a common centroid layout for matching purposes. Such a practice takes the multiple schematic devices and merges them through abutment to form a single multichanneled device in the layout (Figure 8.8). For multichanneled devices in a single diffusion, each channel is extracted as a separate device then combined to ensure proper connection and matching to the schematic. Butted junctions, where a well contact and the source of a MOSFET are

FIGURE 8.8

Cell representations for interdigitated MOSFETs.



8-9

formed in the same diffusion active shape, are permitted in most silicide technologies and are a common layout practice. Contacts are required on the source side of the junction, and are optional on the well side of the diffusion. The source side must be contacted because of electrical and reliability concerns with the current-carrying capability of the silicide when it bridges both n- and p-type diffusions. Digital circuits generate high-frequency switching noise that is coupled into the substrate through the source–drain junction capacitances, bulk connections, and wiring. This noise signal can travel through the substrate where it may be introduced to sensitive analog circuits through wiring paths or substrate to bottom plate capacitance of MIM capacitors. The substrate network can be complex and specific regions must be designated. Substrate regions within a design for identifying different bulk areas within a chip must be extracted separately. These regions are necessary to isolate circuitry for noise and usually have physical barriers such as trenches or resistive moats. Separate regions allow the designer to study the effects of isolation versus coupled regions. CAD tools specific to substrate analysis are available to simulate the substrate effects due to integrating devices in local proximity with a common bulk material. These tools produce large simulation netlists, which are difficult to analyze for large chip areas. Firstorder effects, however, may be identified within LVS and simulated in a post-layout methodology. Process characteristics are checked during the LVS verification. Shallow-trench isolation (STI) induced stress and well proximity effects are two issues requiring explicit device parameter extraction to identify MOSFET model parameters to characterize device alterations within the process. The basic STI process sequence involves several sources of process strain, which can significantly increase the stress levels in the enclosed silicon area. This stress influences junction leakage and MOS electrical characteristics and must be extracted then passed to the device model. Proximity effects are caused by the erosion of the gate area caused by the scattering of ions during deposition that causes a change in Vth (threshold voltage) a device simulation parameter. The effects apply to both n-well and p-well devices. The effect is measured as a function of the distance between the gate and the well, weighted by the area of the gate affected. The erosion of the gate increases with decreasing distance.

Parasitic Extraction (PEX) Device interconnect introduces coupling effects to the device circuitry. These effects must be modeled for inclusion in design simulation. Estimation of the parasitic effects is critical for IC design and may alter the design point significantly. A typical IC design may contain thousands of devices with a broad frequency range and significantly more interconnect lines. During the PEX phase, each interconnect line is extracted based on the dimensions of the line, the vertical profiles of the process stack distance to adjacent conductors and the frequency of the signals traveling through the line. Parasitics include area and fringe capacitance of parallel plates of different conductors, parasitic diodes from diffusion, substrate or well, coupled capacitance for non-polarized capacitors, distributed resistance of conductors, and fringe capacitance of separation (non-overlapping) of like conductors (Figure 8.9). Skin resistance causes significant change in impedance for changing frequencies making inductance significant for gigabit frequencies. To this end, various extraction techniques must be employed in a given design. For designs below the 20 GHz range, parasitic RLC tools for estimation of parasitic effects may be used. Integrated mixed-signal designs often contain considerable metal density variation requiring a specific technology profile to define the stack heights and dielectric constants. Many parasitic extraction tools, however, produce large errors for sparsely packed wide metal geometries as in RF designs and in dense digital designs, large parasitic netlists remain a problem for resimulation. For critical interconnect estimation, a transmission line may be specifically modeled for accuracy. Transmission lines distribute the frequency and time-domain effects. For high-frequency designs, a three-dimensional field solver may be required for accurate investigation of key circuitry. It is necessary to identify the parasitics associated with the device model and that of the interconnect such that the coupling is not double counted. Identification shapes are useful for device boundaries so that the parasitic tool can couple internal parasitics to the shape and discard them in analysis as they are part of the modeled device.


8-10

page 10



Wi+1 Li+1 = 20 µm

Mi+1

C2

C1

C3

Si,1-2

Li,# = 18 µm

Si,2-3

Mi,1

Mi,2

Wi,1

C5

C4

Mi,3

Wi,2 C9

Li-1 = 20 µm

C10

C7 C6

Wi,3 C8

Mi-1 Wi-1 Wi+1 = Wi-1 = Wi,1 + Wi,2 + Wi,3 + Si,1-2 + Si,2-3 + 6 µm

FIGURE 8.9

Parasitic capacitance for a metal stack.

Postlayout simulation stitching all parasitic analysis may be produced including all parasitic components and extracted devices with measured parameters. Nonphysical model parameters, such as substrate resistance and temperature variability, must be overlayed onto the extracted data for accurate simulations.

8.6

Chip Assembly

Simulated and verified design blocks for both analog and logic circuitry are combined at the chip level. Combining the cell blocks and assembling the chip require unique tools and design practices. Full chip simulation for large designs is difficult and most times not possible due to too many devices, simulator performance, nonconvergence, and debugging concerns. Behavioral modeling becomes useful to characterize blocks of the design. Parameterized models promote cell reuse and are much faster than device-level simulation. System-level models promote top–down design techniques. Behavioral models are written in a high-level design language (HDL) to describe the functionality of the circuit in a mathematical equation. Mixed-signal languages require interaction between analog and digital sections, transferring the signal through some interface connect modules. Electrostatic discharge (ESD) protection is an important consideration in chip design and should be architected from the start of the design process [5]. All pins need a protection strategy, and ESD circuitry for a specific application must be designed according to the manufacturing design rules for chip protection. The three most common ESD test specifications are the human body model, the charged device model, and the machine model. The human body model (HBT) is intended to represent a discharge from a person touching one of the package leads. The human body has a large resistance, and the pulse is characterized by a decaying exponential function. The charged device model (CDM) represents a discharge that would be caused by chip or packaging handling equipment. The CDM is a brief discharge, with higher peak current and lower overall energy than that of the HBT and is distributed throughout the chip. The machine model (MM) represents a discharge to a pin by a charged piece of equipment. Current is more localized as in HBM, but peak current is high as in CDM.


page 11


8-11


Each of these events requires circuitry to dissipate the charge and protect the design circuitry. ESD protection circuitry can be built from common elements in the design kits to build a hierarchical circuit based on protection strategy. This circuitry consists of strings of diodes, RC-triggered power clamps, and Darlington clamps using varactors, HBTs, MOSFETs, and diodes. No new device characterization or modeling is required.

8.7

Chip Finishing

Designs are delivered to the foundry by translating the layout data from the physical design database to an industry standard binary format such as GDS2 or CIF. It is a common practice to verify the data to be released to the foundry and the physical layout database by performing an exclusive or (XOR) check which will overlay the input GDS2 and the native database and run a shape check to determine any dropped or shifted shapes. A complete DRC verification and density check is required prior to manufacture. Many foundries run postlayout checks and alterations to input design data for yield and reliability improvements. Automated fill and slotting techniques for designs, which do not meet the density requirements, may be run at the foundry. These will introduce shapes to increase or decrease the density. These algorithms are programmed to include the design rules and look for design features such as RF sensitive circuitry and via farms. Layers used in manufacturing such as implant halos are auto-generated from design build shapes. Automatic generation of fill and design layers simplifies the layout for the end designer. To print manufacturable features on silicon, the physical design data must be modified post-tapeout (Figure 8.10). Optical proximity correction (OPC), phase shift mask (PSM) design, and scattering bar (SB) may be required. These techniques are grouped as reticle enhancement technology (RET). OPC introduces design rules on physical layout provide allowances for the effects of sub-wavelength lithography and process distortions not present in the design data. These rules produce better yield and reliability by introducing shapes or cut-outs such as hammerheads, inner–outer serifs, assist bars, biasing, and line-end serifs to produce the actual shapes designed by using the process tolerances and biases [6]. Many CAD tools are readily available in the industry to solve many of the design challenges, which highly integrated RF–mixed-signal chips face. It is essential, however, to customize the tools for optimal performance for a given technology given the requirements from the foundry and the design specifications established.

Conventional (no OPC)

Silicon image w/o OPC

Original layout 0.18 µm OPC layout

FIGURE 8.10

Silicon image with OPC

OPC rules force alterations to a conductor in order to manufacture corners.


8-12

page 12



Acknowledgment The author would like to thank Don Jordan for contributions, editing, and general knowledge.

References 1. DL Harame, KM Newton, R Singh, S Sweeney, S Strang, J Johnson, SM Parker, CE Dickey, M Erturk, G Shulberg, D Jordan, D Sheridan, MP Keene, J Boquet, R Groves, M Kumar, DA Herman, and BS Meyerson. Design automation methodology and RF/analog modeling for RF CMOS and SiGe BiCMOS technologies. IBM Journal of Research and Development 47(2/3), 2003. 2. R Singh, C Dickey, and M Keene. RF-simulation algorithms: Which one is better for IC design? EDN, 8/22/2004. 3. Kundert. The Designer’s Guide to SPICE & SPECTRE. Kluwer Academic Publishers, New York, 1995. 4. D Jordan and S Strang. Custom verification using DIVA and DFII. Transactions of the International Cadence Usergoup Conference, September 2001. 5. S Voldman et al. Electrostatic discharge and high current pulse characterization of epitaxial base silicon germanium heterojunction bipolar transistors. International Reliability Physics Symposium, March 2000. 6. L Thenie. Implementing OPC correction in a mask data preparation flow. Transactions of the International Cadence Usergroup Conference, September 2000.


9 Parasitic Modeling and Noise Mitigation Approaches in Silicon Germanium RF Designs 9.1 9.2

Introduction......................................................................... 9-1 Substrate Noise Isolation and Coupling ........................... 9-2 Substrate Noise Coupling . Modeling Substrate Noise . Substrate Isolation: Predicting Isolation through TCAD and Test-Site Structures

9.3

Interconnect Modeling and Loss ....................................... 9-6 Modeling versus Extracting the Interconnect Parasitics . Parasitic Interconnect Inductance

9.4

General Noise Mitigation Guidelines . Substrate Noise Mitigation Guidelines

Raminderpal Singh IBM Systems and Technology Group

9.1

Mitigating Circuit Parasitic Noise Effects ......................... 9-9

9.5

Summary ............................................................................ 9-10

Introduction

As SiGe processes migrate and lower in cost, opportunities for higher levels of circuit integration and faster signal frequencies arise. In addition, as signal voltage headroom has dropped (due to technology scaling) and circuit ‘‘noise activity’’ has risen (due to higher digital and oscillator frequencies and higher levels of integration), an urgent need has arisen for accurate understanding and modeling of the coupling paths to and from each sensitive part of the circuitry. A key challenge has become the modeling and design of the parasitic effects of the passive devices, IC package, interconnect, and substrate. Figure 9.1 abstractly shows the resistive, capacitive, and inductive parasitics that affect the circuit performance. These effects cover most (probably not all) coupling and leakage paths possible, and are very significant and complex, often gating first pass design and product success. In this chapter, we focus on the topics of interconnect and substrate parasitic modeling and noise mitigation. Not all noise concerns are covered in this chapter, as SiGe offers design potential of integrated on-chip circuits with frequencies up to 100 GHz today [1]. Effects such as electromagnetic (EM) coupling also need thought, at millimeter-wave frequencies (40 GHzþ). There needs to be an integrated design methodology to allow the designer to probe and measure how the design performance is affected by the parasitics. Additionally, no single modeling methodology is 9-1


9-2


Package, RLC

Interconnect coupling, C (RL)

Bond pad and bond wire, RLC

Interconnect, RCL and transmission line models

Substrate model, R (C)

Guard ring, with very low R

FIGURE 9.1 SiGe integrated circuits today involve a combination of circuits, with different characteristics, building for a complex parasitic modeling problem.

sufficient to model and design with all these complex effects, throughout the RF IC design flow. Figure 9.2 shows a high-level view of an RF–analog custom IC design flow typically used by designers. Transmission line models are included here, as a needed but not yet prolific part of the design community. Additionally, it is very important that the SiGe designer includes the effects of the IC package, as shown in the figure. Ideally, co-design of the package with the silicon circuit is needed. But, this is not always possible, especially when the package and IC are coming from different design groups or companies. In these cases, careful hand-off and early specifications are critical. Finally, there is a need for guidelines to mitigate these parasitic effects in the circuit design. This discussion is qualitative and directional, but helps guide designers on some of the key nuances in trying to balance the parasitic effects against the design specifications and schedule.

9.2

Substrate Noise Isolation and Coupling

Substrate noise has emerged as a real parasitic effect since the mid-1990s. The noise itself has existed in the silicon substrate for far longer, due to digital circuit switching and on-chip oscillators. The difference is that the coupling effects are now significant and more acute, and designers are observing performance degradation due to them. Figure 9.3 shows the effect of oscillator signal self-mixing to create an effect called DC Offset, in direct conversion receivers. This effect is caused by the oscillator signal coupling through the substrate, and has caused complex design techniques to be used to avoid the self-mixing to the DC frequency range. Notably, design techniques [2] are very commonly used to avoid the problem. However, finding a solution requires more than design experience—i.e., modeling and estimation tools have a critical role to play in aiding the designer’s decisions.

Substrate Noise Coupling Figure 9.4 describes the mechanisms for substrate noise injection into the silicon substrate. Simply, electrons in the circuit follow lower AC impedance paths to the circuit ground. The chip substrate often


9-3

Parasitic Modeling and Noise Mitigation

RF-AMS IC

Package Schematic Capture

Device-level Transient Simulation

Transmission Lines Substrate Isolation estimation

Mixed-Signal Simulation

Simulation Environment

Electrical package design & modeling

Frequency Domain Simulation

Layout Transmission Line PCells

Resimulation Physical Verification

Parasitic Extraction Interconnect RLC Substrate Modeling

Package design

GDS II Tape-out

FIGURE 9.2 The RF-AMS IC design flow is complex, including several different point tools. There is also a need to carefully co-design the package, as illustrated here.

Self-mixing of interferer

LNA

Mixer

LO signal selfmixing through substrate VCO

FIGURE 9.3

Substrate coupling leading to LO feedthrough, in a Direct Conversion Receiver.

offers impedance paths to other points of the circuit and current noise in the substrate results. The mechanisms can be summarized as: .

.

Substrate noise current injections from active devices, such as rail-to-rail and high-frequency switching HBTs (e.g., in local oscillators) and switching FETs (i.e., digital switching circuitry). Capacitive coupling effects from lower level interconnects (e.g., M1) and passive devices. This mechanism has had little focus on by modeling, tool, and design teams. But, it is a


9-4


p+

Digital FET/ switching HBT n+ n+

Interconnect/ passives analog/rf n+ n+

p+

Current noise flow, based on substrate voltage bounce

FIGURE 9.4

There are several mechanisms for substrate noise injection into the substrate.

TABLE 9.1 Comparison between Substrate-Doping Levels (p-Type Substrate) and the Effective Cutoff Frequency, When the Capacitive Effects of the Substrate Become Significant Doping Level (cm3) 1014 1015 1016 1018

.

Resistivity (V cm)

fc (GHz)

125.6 12.7 1.4 0.035

1.2 12.0 >100 >1000

contributing factor, even with capacitive shielding (i.e., oxide) between the interconnects and the substrate. Native resistive connection to the substrate of substrate contacts and connected ground rails. This effect is often the dominant mechanism—i.e., large ground planes in digital circuitry virtually control the substrate voltage bounce in the region and sometimes the whole chip—depending on the chip floor plan and nature of the other on-chip circuitry.

As the frequency of the signal rises, the nature of the substrate impedance moves from ‘‘real’’ (i.e., resistance) to complex (i.e., resistive and capacitive) [3]. This ‘‘cutoff ’’ or transition frequency for the substrate depends on the doping level. Table 9.1 lists out a few data points mapping the doping level, to the cutoff frequency. These data are used by substrate modeling tools, but can also be used by designers when thinking about substrate effects due to different circuit blocks (with different frequencies).

Modeling Substrate Noise In recent years, there have been numerous papers published [4] attempting to offer practical and usable approaches to model substrate coupling. This realization has arisen from the adoption of single IC solutions, where smaller gate lengths have led to higher frequencies of circuit operations and to high levels of integration. Given these trends, it is somewhat surprising that substrate-modeling methodologies are not yet common in commercial verification design flows. This is partly because substrate modeling requires complex breakdown of the three-dimensional silicon body and methodology inefficiencies often lead to impractical extraction and simulation times as well as large memory requirements. Several algorithms [4] attempt to model the full nature of the silicon and interface to the circuitry, to a high level of detail. This may include three-dimensional numerical modeling techniques and close linkage to the device modeling methodology used. Some of the key difficulties with this approach include: 1. The size of the netlists extracted are large—approximately n2/2 for n substrate ports connecting to the design—and need reduction for any practical circuit analysis. This leads to heuristic assumptions in the reduction, which dilutes the value of the original algorithm.



9-5

2. The methodology implementation is dependent on a close tie to the silicon process technology used, which requires much work in integrating the device models and device layout extraction code. This is a risky process, given the margin for error in the complexity of the device models and device layout extraction code. 3. This methodology does not handshake well with the interconnect extraction–modeling methodologies used. So, the effect of the interconnects and even the substrate contacts can be easily missed or inaccurately modeled. 4. For most designers, there is a need for estimation of the substrate effects early in the design flow, for floor planning–layout design purposes. The silicon extraction approach assumes layout is complete or near to complete, and are hence used in a circuit sign-off mode not a circuit design mode—where it is needed. Another set of algorithms exists [4] with estimation of the substrate effects as a starting point. These approaches typically try to capture the dominant activity in the noise injection circuitry (e.g., switching activity of digital circuit blocks) and map them to sensitivity analyses of the sensitive (e.g., RF) circuit blocks. Macromodeling of the different circuit blocks is often tried, to try and reduce the size of the problem. Some comments on this general approach include: 1. The approaches have the general benefit of looking to at the design trade-offs based on limited available data—e.g., block-level floor plan. The effectiveness of this methodology has not yet been proven, but the impact is earlier in the design flow. 2. Because limited data are used, these algorithms sometimes follow the ‘‘junk in, junk out’’ approach. This problem is hard to avoid, with designers and CAD engineers often conflicting about the ultimate value of the results. 3. There is no leading commercial implementation of this approach, available today—although there have been many ideas and several prototypes in universities. Without proliferation and broad usage, it is difficult to prove the value for the common design space—especially as the effects vary depending on the application design.

Substrate Isolation: Predicting Isolation through TCAD and Test-Site Structures From the designer’s perspective, the most commonly understood and apparent need for substrate modeling is in the prediction of block-to-block isolation or impedance. Given this, there are a couple of focused and useful methodologies that could be used to aid the designer, which avoid the need for complex substrate modeling tools and methodologies. 1. TCAD predictive modeling—TCAD tools have been used for several years to understand the effects of coupling between active and passive devices. TCAD can also be effectively used to verify substrate isolation in chip floor plans (SiGe book), providing for value and impact early in the design flow. The capabilities also improve as the algorithms move from two-dimensional to three-dimensional modeling, with some results shown in Figure 9.5 and Table 9.2. This work has been done in IBM’s 0.25 mm SiGe 6HP process technology, where digital circuits are often integrated. The results compare the three-dimensional TCAD simulation data with measured data for a range of test structures. As can be seen, the results are very close, demonstrating the value of the TCAD tools. One still has to be careful with these data, as real circuit designs have numerous devices and have complex ground and parasitic paths that TCAD simulations cannot adequately capture—due to memory and CPU limitations. Nevertheless, this methodology is useful for high-level first-order analysis. 2. Substrate isolation test site structures—the use of test-sites to verify accuracies of substrate modeling tools is common. However, there has been a stream of papers that have brought forward useful methodologies for developing fitted equations to predict the impedance between points and even circuit blocks [3]. In many senses, this is a ‘‘home run’’ for the designer, as the


9-6


FIGURE 9.5 IBM 0.25 mm 6HP SiGe test site structures used to verify accuracy of IBM’s three-dimensional TCAD modeling methodology and tool. Each structure has a noise transmitter point and a receiver point.

TABLE 9.2

Measured and TCAD Simulated Results from Test Structures Shown in Figure 9.5

Device

W W W W W

¼ ¼ ¼ ¼ ¼

10u; D ¼ 50u 10u; D ¼ 100u 10u; D ¼ 100u 50u; D ¼ 50u 100u; D ¼ 50u

0.6 23 27 32 16 13

Measurement

Simulation Data

jS21j (db) at

jS21j (db) at F

23 27 32.7 16.1 13.5

2 23 27 32.8 16.6 13.8

0.6 23.25 26.10 31.44 16.5 12.96

2 23.25 26.27 31.43 16.5 12.95

10 23.10 25.84 31.29 17.06 12.82

30 22.06 23.62 30.25 14.88 11.86

results are specific to a process technology and hardware derived. In addition, through the use of TCAD simulations, the test-site fitted equations can be broadened to include different isolation structures and dimensions.

9.3

Interconnect Modeling and Loss

Interconnect extraction is a very common, and almost an assumed part of the SiGe IC design flow today (see Figure 9.2). However, as signal frequencies and levels of integration have risen, there is a need for a deeper understanding of key challenges faced by the designer.

Modeling versus Extracting the Interconnect Parasitics There are two ways to predict the effect of the interconnect parasitic impedances—modeling and shapebased extraction. Which approach to use depends on the types of signals on the interconnect and the level of accuracy required. Modeling: This involves the development of fitted equivalent circuit models, from experimental (using hardware and software methods) data. These models are typically distributed in nature (e.g., RLC ladder



9-7

networks) parameterized. For interconnects with RF signals—i.e., analog signals at 1 GHzþ frequencies—there is a need for S-parameter characterization and modeling, as well as modeling of any impedance mismatches and losses. Full-wave EM tools are needed to model the effects, as well as testsites allowing RF measurements (S-parameters) to be taken. This methodology has been described in detail in Chapter 10 on transmission line modeling. This methodology enables a growing field of interconnect-aware design, where the transmission line parasitics are designed as part of the circuit performance from the early stages of the design [5]. Extraction: This involves commercial software integrated into the design flow. The software breaks down the interconnect structures into small polygons, and uses precalculated look-up tables and coefficients to extract the RLC for each polygon. For interconnects carrying time-domain signals—i.e., digital—the accuracy is best modeled by comparing the extracted parasitic resistances (R), capacitances (C), and inductances (L) from the chosen interconnect extraction tool to a golden standard extractor. For hardware verification, the methodology required is to look at the measured delay from ring oscillators and other circuits. Extraction algorithms are typically shape-based—i.e., they calculate the parasitic R, L, and Cs from the physical dimensions of the interconnect. The advantage of this is that any shape can be analyzed. Conversely, analyzing complex structures with shape-based extractors leads to stray parasitics being netlisted, especially where discontinuities in the metal occur. Each of these methods has certain advantages and disadvantages. For example, if S-parameters are used in the accuracy verification (using full-wave EM modeling tools or RF measured data) for interconnects carrying digital signals, then there is room for error in the setup of the measurement– modeling structures. Conversely, if the models are aimed to be broadband and are applied to narrowband high-frequency signals, then the accuracy at a particular frequency may not be sufficient. Hence, there needs to be sufficient knowledge and expertise of the application and signal type. In SiGe designs, there is sufficient mix of both analog–RF and digital signals that both types of modeling and extraction are needed in the design flow. This leads to a more complex design environment.

Parasitic Interconnect Inductance Parasitic inductance effects are regularly discussed in literature [4,6,7], both for RF and digital designs. .

.

For RF designs, the effect of inductance is more prominent as the frequencies are higher. RF designers have for many years needed to predict and back-of-the-envelope estimate the transmission line effects in their designs, in order to meet circuit performance. As SiGe technologies have advanced, the situation has become more acute and a need has arisen for more integrated and proven transmission line structures (see Figure 9.6) to accurately model the frequency-dependent parasitic inductance, as well as resistance and capacitance. – Another concern for modeling RF signals is the effect of the substrate leakage path [3]. The silicon substrate is effectively a resistive and capacitive load on the interconnect. As the signal frequency rises to the cutoff point of the substrate (see Table 9.1), the substrate becomes more capacitive in nature and can provide a lower AC impedance path to ground for the signal. Hence, signal loss from the interconnect to the substrate may occur. The simplest method to avoid this effect is to use microstrip structures, which control the loss (see Figure 9.6) using physical ground shields. In designs where the RF interconnect routing is dense—e.g., highspeed integrated data converters—space is not always available for ground shields. In such cases, the interconnect to substrate effects needs to be modeled using novel hardware-correlated techniques as part of the RF IC design flow [3]. For digital designers, the impact of the parasitic inductance is dependent on several issues—such as switching activity and the net resistance. Previous publications have discussed the key guidelines for when digital designers should take inductance seriously in their design flow [4]. Determination of when to take inductance into account is complex, but simple guidelines can


9-8


FIGURE 9.6 Parasitic extraction tools are not always sufficient for SiGe communication designs, and microstrip line models are needed in integrated design flow.

Partial equivalent inductance

Loop inductance

V V

FIGURE 9.7 Inductance extraction of metal interconnects is often done using either PEEC or loop inductance. Each approach has its benefits and drawbacks, for the analog–RF designer.

be used to the first order—based on the net impedance, switching activity, return path. Some algorithms have already started to use this. Inductance extraction algorithms have (and continue to) advanced over the years, but are fundamentally tied to one of two methodologies [7] (see Figure 9.7): 1. Loop-based inductance—this methodology assumes a known dominant return path, and provides a reduced netlist comparable in size of the transmission line models. Inherently, this approach is useful for simpler routing patterns. 2. Partial equivalent electrical circuit (PEEC)—this methodology is very commonly used today for interconnect modeling, as it allows for complex interconnect structures and return paths. The netlist generated is, however, significantly larger than that of the transmission line model or extraction using loop-based algorithms. Another consideration to be aware of, is the assumption that the substrate makes a good return path [6]. The validity of this assumption is tied to the conductive nature of the substrate, which is proportional to the doping concentration level. The doping varies from foundry to foundry (typically, between 1 and 15 V cm), and even between processes, and sometimes low doping is used to raise the substrate impedance—for device design benefits and for higher inherent substrate isolation. The designer should always make some back-of-the-envelope calculations to check whether the substrate is a valid return path.



9.4

9-9

Mitigating Circuit Parasitic Noise Effects

General Noise Mitigation Guidelines SiGe RF–mixed-signal designers are often faced with a complex set of trade-offs and noise paths that cannot be precisely modeled or quantitively reduced. To help provide some insight and direction, some general mitigation techniques that circuits designers often use to preserve the quiet of mixed-signal ICs, include [8]: .

.

.

.

.

. .

Use smallest possible output driver to reduce switching noise. Output drivers are high contributors to overall substrate and power grid noise. Shut down switching functions of the rarely used logic circuits to reduce loading capacitance, and hence switching noise. Avoid long traces, long parallel runs near known noise sources, changing layers when possible. This will lead to less net-to-net coupling. Not to let Spice simulations that indicate no problems lull designers into a false sense of security. Many times, inaccurate modeling or incomplete simulation strategies lead to speculative results, which may not capture key noise-coupling issues. Pick the quietest portion of the clock cycle for sampling. In this way, less noise is picked up during sampling. Distribute the bias signal as a current to improve the resistance to noise. Use parallel supply connection instead of a series daisy chain of power connections. This leads to lower impedance paths, improving the tie down to AC ground.

Substrate Noise Mitigation Guidelines Substrate noise components can be broken down to RF and DC for the most. RF substrate noise is typically based on the clock or the VCO frequency and is typically higher for the rest of the circuit. This noise can be easily identified and partially protected against, from sensitive circuitry, using frequency planning and substrate-isolation techniques. DC substrate noise is typically generated from lowfrequency ground bounce effects, and as such is much harder to protect against—as the ground routing can cover a large portion of the design layout area. A handful of cost-effective structures and techniques [3] specific to reducing substrate noise coupling, include: .

.

. .

.

.

Guard ring structures around the noisy and sensitive circuitry, usually tied to dedicated package pins for closer AC grounding. Note that, in RF designs, a dedicated pin is not always available. NWELL trenches and deep trenches (DT) between the noisy and sensitive circuitry to block the substrate current flowing near the surface of the substrate. Differential circuitry—a favorite for RF designers. Lower package parasitic inductance (for the pins), causing stronger AC grounding of the substrate. This is a very effective but sometimes expensive approach due to the extra package costs. Lower inductance is also accomplished through multiple or shorter bond wire connections, or flip-chip area I/O packages. Note that corner pins have higher parasitic values than center pins. Careful floor planning can also be used. The idea is that the farther the sensitive and noisy circuits are, the less the substrate coupling will affect the circuit’s performance. Figure 9.8 shows an abstract view of the common approach to sensible floor planning. Use of an exposed paddle structure, to which the IC bondpads are downbonded, connected effectively to the PCB ground. This is another common technique, and is very effective. One has to be careful to realize that the analog and digital grounds are now common in the system.


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page 10



Low amplitude analog circuits

Medium amplitude analog circuits

High amplitude analog circuits

P+ Guard Rings Low speed digital circuits

High speed digital circuits

Digital output buffers

FIGURE 9.8 Careful floor planning should be used to reduce the effect of substrate coupling between different circuit blocks. In this example, the primary noise sources are the digital output buffers.

9.5

Summary

In this chapter, we have covered numerous relevant and significant topics to aid SiGe RF–mixed-signal IC designers. There are no absolute solutions to accurate modeling and noise mitigation, but—with a combination of experienced designers, good modeling algorithms and methodologies, and useful and practical guidelines for noise mitigation—there is ‘‘light at the end of the tunnel.’’

Acknowledgments The author would like to thank Wayne Woods, Youri Tretiakov, Nick Lam, Bob Barry, Mukesh Kumar, and Rajendran Krishnaswamy for their help in pulling together the needed data and content for this chapter. Special thanks also goes to Ramana Malladi, for his help in reviewing this chapter.

References 1. J. Robert Lineback. IBM Claims Proof of SiGe Beating InP and GaAs Chips in Future. http:// www.siliconstrategies.com/story/OEG20020225S0010, 2002. 2. W. Namgoong and T. Meng. Direct-conversion RF receiver design. IEEE Trans. Commun. 49:518–529, 2001. 3. R. Singh, D.L. Harame, and M. Oprysko. Silicon Germanium—Technology, Modeling, and Design. New York, NY: John Wiley & Sons, 2003. 4. R. Singh. Signal Integrity Effects in Custom IC and ASIC Designs. New York, NY: John Wiley & Sons, 2001. 5. D. Goren, M. Zelikson, T.C. Galambos, R. Gordin, B. Livshitz, A. Amir, A. Sherman, and I.A. Wagner. An interconnect-aware methodology for analog and mixed-signal design, based on high bandwidth (over 40 GHz) on-chip transmission line approach. Design Automation and Test in Europe Conference and Exhibition, Paris, 2002, pp. 804–811.



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6. C.K. Cheng, J. Lillis, S. Lin, and N. Chang. Interconnect Analysis and Synthesis, Chapter 5. New York, NY: John Wiley & Sons, 2000. 7. K. Gala, D. Blaauw, J. Wang, V. Zolotov, and M. Zhao. Inductance 101: analysis and design issues. Design Automation Conference, Las Vegas, 2001, pp. 329–334. 8. C. Falcon. Preserve the Quiet in your Mixed-Signal ASIC. Electronic Design Magazine, March 18, 2004, pp. 81–86.


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10 Transmission Lines on Si 10.1 10.2 10.3 10.4 10.5

Youri V. Tretiakov RF Micro Devices

10.1

10.6

Introduction..................................................................... 10-1 Transmission Line Technology ....................................... 10-1 Modeling Aspects ............................................................ 10-2 Transmission Line Measurements.................................. 10-5 Transmission Line Examples and Applications ..................................................................... 10-6 Summary .......................................................................... 10-8

Introduction

Microstrip, strip transmission lines, and coplanar waveguides are often utilized in high-speed radiofrequency (RF) integrated circuits (IC), digital and mixed-signal applications [1–6] to avoid signal integrity problems for critical transmission line interconnects. These transmission lines can range from narrow digital clock nets over a wide common ground plane to wide analog interconnects in power amplifiers. Traditionally, transmission line interconnects are employed to control high-frequency distributed impedance effects that become important as the wavelength approaches a fraction of the interconnect line length. Increasingly, transmission line structures are also employed to isolate critical interconnects from the lossy substrate either through reference ground plane shielding signal lines from below or field containment in coplanar-like structures. They can also serve as the open and short stubs [4] or as the input, output, and interstage interconnects [5] for matching purposes. Essential to transmission line capability is both the technology in which it is implemented, and also an accurate and flexible design system. The transmission line technology establishes structural constraints. The design system enables the designer to understand these trade-offs and establish the design first-pass success.

10.2

Transmission Line Technology

From a technology point of view, the design of the metal interconnect stack takes into account many issues that are not obvious at first glance. Compatibility with high-performance CMOS, integration with low-cost metal–insulator–metal capacitors as well as low-cost wire-bond need to be taken into account. The most simple transmission line structures to design and manufacture are microstrip lines [1] and coplanar waveguides [7,8] shown in Figure 10.1. The microstrip line interconnects with possible side shielding are effectively shielded from the substrate below to eliminate the silicon substrate losses and minimize coupling to other circuit elements. Optional side shielding is usually made of stacked vias. They work well as the side electromagnetic shield walls. Usually, top thick metal layers are used as signal 10-1


10-2


Signal ground

Single wire with bottom shield

Single wire with bottom and side shields

Coupled wires with bottom shield

Vias

Coupled wires with bottom and side shields

Signal ground

FIGURE 10.1

Silicon substrate

Silicon substrate

Single wire coplanar waveguide

Coupled wires coplanar waveguide

Transmission line interconnects: microstrip lines and coplanar waveguides.

wires with a thinner ground shield on the lower copper layers. This enables the use of microstrip lines for the most critical interconnects including power lines in RF power amplifiers. At the same time, the coplanar waveguide interconnects (see Figure 10.1) do not have bottom metal shield. The possible losses in the silicon substrate below are minimized by introducing the side shield lines at the same metal layer as signal ones. To enable the high-performance CMOS on the same chip, the tight-pitch thin-wire metal system nearest to the silicon must be established in the same way as the digital technology. On top of these thin metal layers, thick metal layers with thick interlevel dielectrics create low resistance films and low unit area capacitance. This combination is favorable for the low loss and high impedance required by designers. An alternative way to the low interconnect resistance, inductance, and losses is to use the stacked interconnect structures. The example of such a vertically stacked interconnect can be found in Ref. [8]. The major technology requirement for stacked interconnects to exist on a chip is the good manufacturability of long (a few hundreds of mm) via bars. If they can be manufactured, vertical coplanar waveguide devices have more flexibility in terms of impedance matching and loss control rather than single layer coplanar waveguides [8].

10.3

Modeling Aspects

A key element to design of transmission lines is the ability to rapidly optimize transmission line geometry during the IC design stage. Device component equations are calculated in the component description form (CDF) as well as the model files, including compatible interconnect libraries for a broad range of industry-leading Spice-compatible tools.


10-3

Transmission Lines on Si

A suitable interconnect modeling methodology is through the development of Spice-compatible lumped element models [9], preferably passive by construction. The models are usually parameterized (with respect to IC technology process metal stack and geometrical dimensions) frequency-dependent RLC lumped circuits that have been correlated using hardware, RLC extraction, and full-wave electromagnetic (EM) solver software. If the constructed model uses only frequency-independent RLCelements, then it can be used easily for both time and frequency-domain simulations. Therefore, the transmission line interconnect modeling sometimes is challenging due to the presence of frequencydependent skin and proximity effects. The frequency-dependent losses in the silicon substrate also have their significant impact on major interconnect electrical parameters (especially in coplanar waveguide structures). The general transmission line network representation is shown in Figure 10.2. The rule here is to have at least a few (usually 10) basic ZY-segments per minimum signal wavelength in a particular IC design. We should mention here that the simple lumped element network representation shown in Figure 10.2 is valid only when the explicit current return path is a part of a transmission line interconnect at all frequencies (from DC and up to RF). In real-life designs, this condition is difficult to satisfy since at low frequencies return current flows where the resistance is the lowest and at high frequencies current flows in a way that it minimizes the total loop inductance (and hence total loop impedance). Therefore, in general case the current return paths at DC and high frequencies can be different, especially if there is an alternative current return path (such as power grid) in the vicinity of a transmission line interconnect. In that case, the network shown in Figure 10.2 is not valid anymore. This results in the fact that each piece of metal (signal lines, ground return paths) should be treated in the same way. Each metal shape has selfresistance, capacitance, and inductance. In addition to that, all pieces of metal also have mutual coupling (inductive and capacitive). As a result, the developed interconnect model can be very complicated so it models properly the DC interconnect behavior (low-frequency IR drop for instance) as well as its highfrequency characteristics (impedance, loop inductance, S-parameters, and time delay). In the case of a well-defined transmission line interconnect (where the current return path is known), the Z-elements in Figure 10.2 describe longitudinal currents in metal and silicon substrate. At the same time, the Y-elements are responsible for modeling of transverse currents in metal and a substrate. Therefore, all lumped RLCG-elements in Figure 10.2 can be frequency dependent. Figure 10.3 shows their most common frequency behavior. The transition frequency for the L-element in Figure 10.3 is

Several segment per wavelength

Z

Z Y

Z Y

Z Y

Y

T-line segment Z-element: longitudinal current in metal and substrate

R(f)

L(f)

G(f) T-line segment FIGURE 10.2

Transmission line network representation.

C(f)

Y-element: transverse current in metal and substrate


10-4


L0 L(f) L⬁

ftr

R(f)~f0.5

R(f) R0

f

0 G⬁

C0 G(f) frel

C(f)

C⬁

f

0

FIGURE 10.3

f

0

frel

f

0

Frequency behavior of the RLCG elements.

L(f )

R(f )

L⬁

∆L

∆G

∆L

∆G

∆L

∆G

One basic element for each freq. decade ∆L1 L⬁

R0 ∆R1

FIGURE 10.4

∆Ln ∆Rn

Modeling of the Z-elements.

when the skin depth is comparable with the relevant interconnect cross-section dimension (thickness or width). For the GC-elements, the relaxation frequency depends on silicon substrate properties [10]. As we mentioned before, it is desirable that transmission line equivalent models use only series of lumped and frequency-independent RLC-segments. To model frequency-dependent effects (skin and proximity effects, silicon substrate losses) from DC till the given chip technology transistor cutoff frequency, so-called ladder networks have been developed and used extensively in the past [1,10,11]. Most popular examples of such ladder networks are shown in Figure 10.4 for LR-elements and in Figure 10.5 for GC-parameters. More details on the proper ladder network design can be found in Refs. [1,10,11].We just mention here that in the case of a microstrip transmission line the capacitance is usually constant over the whole range of interest. The G-element can also be neglected. Therefore, microstrip line models usually have in their network only ladder networks shown in Figure 10.4. At the same time, for coplanar waveguide all RLCG-elements are frequency dependent. That makes models to be more complicated since now they have ladder networks to describe the frequency behavior of RL and CG elements. We should also stress here that all elements in Figure 10.4 and Figure 10.5 are frequency independent. They are passive by construction and easy to netlist in commercial Spice-like simulators. All ladder network-building elements depend only on an interconnect geometry, IC technology backend-of-the-line (BEOL) stack and derived based on low- and high-frequency interconnect behavior.


10-5


Cox

Cside G(f )

C(f ) Gs

Cs

Signal to metal ground

∆Cox1

Coxo ∆Gs1

FIGURE 10.5

∆Cs1

∆Coxn ∆Gs1

∆Csn

Modeling of the Y-elements.

As far as basic RLC blocks are concerned, C and L parameters must be calculated carefully to take into account mutual electromagnetic coupling. As it can be seen from Figure 10.3 and Figure 10.4, it is required to know only their low- and high-frequency limits to finish building an interconnect lumped element network. That can be accomplished using quasi-static transverse electromagnetic (TEM) approximation to calculate low-frequency capacitance and inductance [12] of an interconnect. The quasi-static approach has a good accuracy because the cross section dimensions of on-chip interconnects are usually very small in comparison with the shortest on-chip wavelength even for high frequencies of operation. After low-frequency capacitance is estimated, it is used to calculate high-frequency inductance limit. The next step combines low- and high-frequency inductance values to construct ladder networks. The final transmission line models have strong frequency dependencies of resistance and inductance for microstrip line.

10.4

Transmission Line Measurements

The accurate simulation and modeling of on-chip passive devices such as transmission line interconnects are critical for the design to be successful. The increasing operating frequency of integrated circuits has enhanced the need to accurately model standard transmission line components over a wide frequency range (DC to 100 GHz). To develop accurate models, measured test site S-parameter data (with subtracted pad parasitics) need to be available. Major interconnect electrical parameters such as inductance (L), resistance (R), capacitance (C), and characteristic impedance (Z) can then be extracted and compared versus device model prediction. Before designing an interconnect test site, there is the need for proper measuring padset. The main advantage of a well-defined transmission line interconnect is its explicit current return path, which is a part of an interconnect device. As a result, there is no need to create the on-wafer ground ring around an interconnect under study. The ground contacts of probe tips at both interconnect ends will have a good on-wafer electric connection through the interconnect current return path. Therefore, the designer has only to shield effectively measuring padset from the silicon substrate below to create the padset device, which have well-defined (preferably frequency independent) parasitics. This allows the accurate deembedding of padset parasitics during the analysis of measurement data. We mention here the design described in Ref. [13] as a good example of the properly shielded measuring padset.


10-6


A number of simple and accurate de-embedding techniques have been developed in the past for onwafer active and passive device characterization. Although these methods have been already employed to study on-chip transmission line interconnects [14,15], we will briefly review them here. Here, the focus will be on methods that model the measuring padset structure to be de-embedded by the series impedance and shunt admittance [13,15–19]. Among on-wafer de-embedding techniques is the well-known ‘‘open-short’’ method [16], which is given by Ydut ¼

Ymeas Yopen

1

Yshort Yopen

1 1

,

(10:1)

where Yopen, Yshort denote the two-port admittance parameters measured on the ‘‘open’’ and ‘‘short’’ devices, Ymeas is the measured two-port admittance of the device, and Ydut is the de-embedded Y-parameters of the device under study. A second de-embedding technique based on the same ‘‘open’’ and ‘‘short’’ dummy structures has been proposed in Ref. [17], which switches the order of the series impedance and parallel admittance compared to the ‘‘open-short’’ method in Ref. [16]: Ydut ¼ ðZmeas Zshort Þ1 Zopen Zshort

1

:

(10:2)

Based on the assumption that the structures to be de-embedded on both ends are identical, another very powerful method (especially for on-wafer transmission lines) is the simplified ‘‘thru’’ de-embedding algorithm [15], which uses only two devices: the device under question with attached measurement pads and a simple dummy ‘‘thru’’ structure. This facilitates the whole de-embedding procedure and saves test site chip space. A detailed description of the ‘‘thru’’ method can be found in Ref. [15]. For most practical cases though it is difficult to adequately design a good ‘‘thru’’ structure where left and right pads are effectively uncoupled. Increasing distance between pads and measurement frequency cause the interconnect line connecting left and right pads of the ‘‘thru’’ device to behave as true transmission lines, which would have to be described by a distributed topology. Therefore, the easiest way would be to treat that connecting line to be also a true transmission line. Based on this, the use of only two devices has been proposed in Ref. [19]. The new de-embedding method uses only L1 ¼ L and L2 ¼ NL (N, the discrete number) long interconnects with attached pads. As a result of measuring only these two devices, they can be both de-embedded. The immediate advantage of the proposed in Ref. [19] technique is that left and right pads can be separated far enough to minimize mutual coupling between them. In that case, the new method treats the interconnect connecting pads as a true transmission line device, which improves the overall deembedding accuracy. The proposed method also eliminates the need for dummy ‘‘open,’’ ‘‘short,’’ and ‘‘thru’’ devices, which sometimes impose an additional challenge to the designer.

10.5

Transmission Line Examples and Applications

As the first example, we simulated a single wire transmission line without side shielding (see Figure 10.1) using the same lumped element model as the one adopted in Ref. [1]. The industry standard Spectre tool has been employed as the simulation engine. Figure 10.6 represents S-parameter correlation results (model versus EM solver) over a wide frequency range of 0.1 to 40 GHz. We also compared the above test case with on-wafer measurement results. They can be found in Figure 10.6, and are accurate to within acceptable levels with S21 magnitude differing by less than 1 dB across the whole frequency range of interest. The transmission line characteristics, shown in Figure 10.6, are quite accurate, and tools, at the center of which is an interconnect-aware design methodology [1], enable the designers to design critical nets in complex metal systems of silicon technologies with great accuracy and the design first-pass success.



FIGURE 10.6

10-7

Test site versus lumped element model and EM solver: S-parameters, microstrip line interconnect.

As the second example, we simulated (using developed Spectre model) and compared two 50 V single-wire microstrip lines (see Figure 10.1) made of 4-mm thick aluminum (width of 12.5 mm and 9.25 mm distance from a finite width metal ground plane below) and a 1.25-mm thick aluminum (width of 5.9 mm and distance 4 mm from a finite width metal ground plane below). Both lines have the same length of 1000 mm. It can be clearly seen from Figure 10.7 that the thicker interconnect has the lowest losses (parameter S21). Figure 10.8 also shows extracted RLCZ parameters for the above lines. The simple equations from Ref. [20] have been used to perform RLCZ extraction procedure from the twoport S-parameter data. Again, thicker line has lower resistance and inductance. Its characteristic impedance is more close to the 50 V value across the whole frequency range of interest. Figure 10.9 and Figure 10.10 show the 77 GHz SiGe power amplifier (PA), which is described in Ref. [5]. That kind of amplifier has its potential use in the modern automotive radar systems. In this design single-wire microstrip lines are employed as matching interconnects. The implemented interconnect devices were carefully designed and accurately modeled to allow their successful application in such a high-speed design. The 60 GHz low-noise amplifier (LNA) from Ref. [4] is another example of the extensive use of microstrip transmission line interconnects. At 60 GHz in the SiO2 dielectric a quarter wave length is about 617 mm. Therefore, the shunt-stub microstrip transmission line interconnects were used successfully as the input, interstage, and output matching devices. Figure 10.11 and Figure 10.12 show the 60 GHz LNA schematic view and the LNA chip microphotograph. Finally, we mention here the work described in Ref. [21]. It presents an interesting application of a single-wire on-chip microstrip line. The developed parameterized microstrip line device was employed


10-8


FIGURE 10.7

S-parameter comparison between two modeled microstrip lines.

to design the monolithic four-port 30 GHz branch line coupler. The availability of the accurate model and the well-defined transmission line structure enables for the designer to properly choose width and length of each arm so the branch line coupler device operates properly at the particular frequency of interest.

10.6

Summary

Due to increasing signal frequencies, the transmission line effects of interconnects are more prominent in modern digital, RF, and mixed-signal ICs. Therefore, there is a strong need for transmission line device support in modern IC (both analog and digital) design flows. Transmission lines, if properly designed, are well-defined waveguide structures with an explicit current return path. This allows for their successful design, accurate predictive modeling, design, manufacturing, and measurements. In multi-GHz design regimes, on-chip interconnects have a substantial impact on the IC performance. The main issues are impedance matching, loss control, time delay, coupling to other circuit elements and to silicon substrate. Even around 1 GHz inductance starts to impact longer lines. Therefore, simple RC interconnect models are not accurate anymore and frequency-dependent inductance has to be included in the model. In order to account for transmission line effects during the design process, critical interconnects should be properly designed and accurately modeled over a wide frequency range. The designed interconnect structures and developed models should be able to account for frequency-dependent


10-9


Resistance - R(f ) 15

⫻ 10-10 4.4

w = 12.5 mm, th = 4 mm w = 5.9 mm, th = 1.25 mm

4.2

Inductance - L(f ) w = 12.5 mm, th = 4 mm w = 5.9 mm, th = 1.25 mm

4 10

3.8 3.6 3.4

5

3.2 3 0 100

101 Frequency (GHz)

⫻ 10-13

100

Capacitance - C(f )

101 Frequency (GHz)

Characteristic Impedance - abs(Z(f )) 110

1.4

w = 12.5 mm, th = 4 mm w = 5.9 mm, th = 1.25 mm

100

1.3 1.2

90

1.1

80

1 70

0.9 w = 12.5 mm, th = 4 mm w = 5.9 mm, th = 1.25 mm

0.8 0.7 100

FIGURE 10.8

60 50 0 10

101 Frequency (GHz)

101 Frequency (GHz)

RLCZ parameter comparison between two modeled microstrip lines.

VCC = 2.5V

Quarter-wave RF-Choke

Out T2

In

T1

Bias2 Bias1

Input match

Inter-stage match

Microstrip transmission lines

Output match

FIGURE 10.9 The balanced 77 GHz power amplifier schematic diagram (half-circuit). (From UR Pfeiffer, SK Reynolds, and BA Floyd. Technical Digest IEEE Radio Frequency Integrated Circuits Conference, Fort Worth, 2004. With permission.)


10-10

page 10



Output matching

Balanced circuit

Bank of bypass caps

out− Supply-/Regulated-Voltages

out+

T2 T2 T1 T1

in−

in+ Inter-stage matching

Quarter-wave RF-choke T1 bias circuit Differential 100 Ohm

FIGURE 10.10 Chip microphotograph of the balanced 77 GHz power amplifier. (From UR Pfeiffer, SK Reynolds, and BA Floyd. Technical Digest IEEE Radio Frequency Integrated Circuits Conference, Fort Worth, 2004. With permission.)

Vcc R1

Cbyp

T7

T6

CUR

T4

R6

Q3 Cbyp T2

Q1

C3 OUT

Microstrip transmission lines (T1-T7)

T3

Q5

C2 Q2

IN

Q4

R2

T1

VB1 C1

R3

R4 T5

R5 Cbyp

FIGURE 10.11 The 60 GHz low-noise amplifier. (From SK Reynolds, BA Floyd, UR Pfeiffer, and T Zwick. Technical Digest IEEE International Solid State Circuit Conference, San Francisco, 2004. With permission.)

skin and proximity effects and be passive by construction. As a result, simple lumped RLC interconnect models (which might include dependent current or voltage sources) are easily netlisted and used in Spice-like simulators for time- and frequency-domain simulations (including harmonic balance and periodic steady-state analysis). Interaction between an interconnect and the lossy silicon substrate below has to be also well understood and accounted for in the interconnect model (especially for coplanar waveguides). The typical transmission line examples are microstrip interconnects over a finite width ground plane below and coplanar waveguide devices over a silicon substrate. The microstrip line interconnects are effectively shielded from the silicon substrate. At the same time, coplanar waveguides are opened to the silicon substrate below. The substrate losses in coplanar waveguides are minimized by using the side shield lines at the same level as signal ones.


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10-11


LNA OUT

IN

Microstrip transmission lines FIGURE 10.12 Chip microphotograph of the 60 GHz low-noise amplifier. (From SK Reynolds, BA Floyd, UR Pfeiffer, and T Zwick. Technical Digest IEEE International Solid State Circuit Conference, San Francisco, 2004. With permission.)

For nondense IC designs (usually SiGe BiCMOS) microstrip lines are a good choice. At the same time, in CMOSRFCMOS designs these structures may have to be different due to higher design density. This is where most of coplanar waveguides find their applications. To summarize this chapter, we just mention here that we attempted to provide a short review of most popular transmission line topologies, which are employed in modern IC designs. We also covered their modeling issues and challenges. In addition to that, we presented a few interconnect application examples.

Acknowledgments The author would like to thank R. Gordin, D. Goren of IBM Haifa (Israel); S. Venkatadri, W. Woods, R. Singh of IBM Burlington (USA); U. Pfeiffer, B. Floyd, T. Zwick, S. Reynolds of IBM Yorktown (USA); R. Groves, K. Vaed of IBM Fishkill (USA); M. Toupikov of Amgen Inc. (USA), and G. Pan of Arizona State University (USA), for their contributions and valuable discussions. In addition, I thank my wife, Marie Sackett, my mother, Valentina Tretiakova, my mother-in-law, Hedy Sackett, my brother-in-law, Nick Sackett, and my grandparents-in-law, Esther and Bob Solla, for their devotion and support in all my endeavors.

References 1. D Goren, M Zelikson, R Gordin, IA Wagner, A Amir, B Livshitz, A Sherman, R Groves, K Park, YV Tretiakov, D Jordan, S Strang, R Singh, C Dickey, and D Harame. On-chip interconnect-aware design and modeling methodology based on high bandwidth transmission line devices. Technical Digest Design Automation Conference, Anaheim, 2003, pp. 724–727. 2. GG Freeman, B Jagannathan, N Zamder, R Singh, YV Tretiakov, JP Plouchart, DR Greenberg, S Koester, and JD Shaub. Integrated SiGe and Si device capabilities and trends for >10 GHz applications. International Journal of High Speed Electronics and Systems 13:175–219, 2003. 3. R Singh, YV Tretiakov, J Johnson, S Sweeney, RL Barry, M Kumar, M Erturk, J Katzenstein, C Dickey, and D Harame. Parasitic modeling and noise mitigation in advanced RF/mixed-signal silicon germanium processes. IEEE Transactions on Electron Devices 50:700–717, 2003. 4. SK Reynolds, BA Floyd, UR Pfeiffer, and T Zwick. 60 GHz transceiver circuits in SiGe bipolar technology. Technical Digest IEEE International Solid State Circuit Conference, San Francisco, 2004.


10-12

page 12



5. UR Pfeiffer, SK Reynolds, and BA Floyd. A 77 GHz SiGe power amplifier for potential applications in automotive radar systems. Technical Digest IEEE Radio Frequency Integrated Circuits Conference, Fort Worth, 2004. 6. A Deutsch, PW Coteus, GV Kopcsay, HH Smith, CW Surovic, BL Krauter, DC Edelstein, and PJ Restle. On-chip wiring design challenges for gigahertz operation. Proceedings of the IEEE, 89:529– 555, 2001. 7. B Kleveland. CMOS Interconnects beyond 10 GHz. Ph.D. thesis, Stanford University, Stanford, CA, 2000. 8. W Woods, YV Tretiakov, K Vaed, D Ahlgren, J Rascoe, and R Singh. Vertically-stacked on-chip SiGe/ BiCMOS/RFCMOS coplanar waveguides. Technical Digest IEEE International Interconnect Technology Conference, San Francisco, 2004. 9. T Dhaene and D De Zutter. Selection of lumped element models for coupled lossy transmission line. IEEE Transactions on Computer-Aided Design 11:805–815, 1992. 10. D Goren, R Gordin, and M Zelikson. Modeling methodology for on-chip coplanar transmission lines over the lossy silicon substrate. Technical Digest IEEE Workshop on Signal Propagation in Interconnects, Hanover, 2003. 11. BK Sen and RL Wheeler. Skin effects models for transmission line structures using generic SPICE circuit simulators. Technical Digest IEEE Topical Meeting on Electrical Performance of Electronic Packaging, 1998, pp. 128–131. 12. R Gordin, D Goren, and M Zelikson. Modeling of on-chip transmission lines in high-speed A&MS design — the low frequency inductance calculation. Technical Digest IEEE Workshop on Signal Propagation in Interconnects, Pisa, 2002. 13. TE Kolding, OK Jensen, and T Larsen. Ground-shielded measuring technique for accurate on-wafer characterization of RF CMOS devices. Technical Digest International Conference on Microelectronic Test Structures, Monterey, 2000, pp. 246–251. 14. T Zwick, YT Tretiakov, and D Goren. On-chip SiGe transmission line measurements and model verification up to 110 GHz. IEEE Microwave and Wireless Components Letters, 15: 65–67, 2005. 15. DC Laney. Modulation, Coding and RF Components for Ultra-Wideband Impulse Radio. Ph.D. thesis, University of California, San Diego, CA, 2003. 16. M Koolen, J Geelen, and M Versleijen. An improved de-embedding technique for on-wafer high frequency characterization. Technical Digest BCTM Symposium, 1991, pp. 188–191. 17. LF Tiemeijer and RJ Havens. A calibrated lumped-element de-embedding technique for on-wafer RF characterization of high-quality inductors and high-speed transistors. IEEE Transactions on Electron Devices 50:823–829, 2003. 18. J Song, F Ling, G Flynn, W Blood, and E Demircan. A de-embedding technique for interconnects. Technical Digest Electrical Performance of Electronic Packaging Conference, 2001, pp. 129–132. 19. YV Tretiakov, J Rascoe, K Vaed, W Woods, S Venkatadri, and T Zwick. A new on-wafer deembedding technique for on-chip RF transmission line interconnect characterization. Technical Digest IEEE Automatic RF Techniques Group Conference, Fort Worth, 2004. 20. WR Eisenstadt and Y Eo. S-parameter-based IC interconnect transmission line characterization. IEEE Transactions on Components, Hybrids and Manufacturing Technology 15:483–490, 1992. 21. J Lee, YV Tretiakov, JD Cressler, and AJ Joseph. Monolithic 30 GHz branch line coupler design on Si/ SiGe with 3D simulations. Technical Digest Silicon Monolithic Integrated Circuits in RF Systems, Atlanta, 2004.




11 Improved De-Embedding Techniques 11.1 11.2

On-Wafer Parasitics and De-Embedding Techniques........................................................................ 11-1 Improved De-Embedding Technique ............................ 11-3 Four-Port Parasitics Model and Theory . De-Embedding Process . Validity and Layout Concerns

Qingqing Liang Georgia Institute of Technology

11.1

11.3 11.4

Comparison ..................................................................... 11-8 Noise De-Embedding Technique ................................. 11-11

On-Wafer Parasitics and De-Embedding Techniques

Precise measurement is a prerequisite to accurate device modeling and characterization. For accurate evaluation of high-frequency characteristics and models, S-parameter measurements are a widely used approach. As the operating frequency in measurement increases into the microwave range, the on-wafer parasitics, including the pad-substrate capacitance and wire impedance, become significant. Figure 11.1 shows the three-dimensional cross-section view of the on-wafer parasitics and the intrinsic device. As the pad-substrate admittances or wire impedances are comparable to the admittance or impedance of the intrinsic device, respectively, the measured S-parameters on the pads (p1 and p2 in Figure 11.1) misrepresent the device ac characteristics. In addition, the layout device size is normally several hundred micrometers, then the distributive nature of parasitics (coupling between wires and substrate) becomes apparent at the millimeter-wave band.

Intrinsic device Wire impedance

Wire impedance

p2

p1

Pad-sub capacitance

Pad-sub capacitance Substrate network

FIGURE 11.1

Three-dimensional cross-section view of the on-wafer parasitics and the intrinsic device.

11-1


11-2




G

G

INT

C2

P1 P1

P2

G

G

OPEN test structure

FIGURE 11.2

P2 C1

C3

OPEN

The parasitics model used in the "open" technique

The OPEN test structure and the equivalent circuit of parasitics model used in ‘‘open’’ technique.

The on-wafer parasitic effects increase as the operating frequency increases. Moreover, the parasitics correlate with the layout and device process (e.g., the properties of the substrate and insulator) and is hard to predict. Therefore, accurate microwave ac characterization requires de-embedding techniques that exclude the parasitic effects and retrieve the intrinsic device characteristics from the measured data. The standard ‘‘open’’ de-embedding method was first proposed in 1987 [1]. It employs a technique in which the pad-substrate and wire-substrate capacitance are accounted for and calibrated by using an OPEN test structure. The layout of OPEN test structure is same as the layout of deviceunder-test (DUT) except the transistor is removed. Figure 11.2 shows the OPEN test structure and the equivalent circuit of parasitics model. Note that in this model, the equivalent circuit of DUT can be viewed as the intrinsic device in parallel with the OPEN. Then the intrinsic device y-parameters YINT are derived as [1] Y INT ¼ Y DUT Y OPEN ,

(11:1)

where the YDUT and YOPEN are the measured y-parameters of the DUT and OPEN test structure, respectively. This approach assumes that the pad-substrate capacitances dominate the parasitics. The validity of this assumption depends on the process technology and layout. Usually, the approach is only accurate at a lower frequency range (i.e. f < 20 GHz). At high frequencies (i.e., f > 20 GHz), the wire impedance, especially the wire inductance, cannot be neglected. The industry standard ‘‘open-short’’ de-embedding method was then proposed to exclude the effects of the wires [2]. Beside the OPEN and DUT, a SHORT test structure is used to extract the parasitics in this method. The layout of SHORT test structure is similar as the layout of the OPEN except that the intrinsic ports are both connected to the intrinsic ground. Figure 11.3 shows the SHORT test structure and the equivalent circuit of parasitics model. Note that the distributive parasitics are modeled as lumped components in this method. The intrinsic y-parameters can be derived using the measured y-parameters of OPEN (Y OPEN), SHORT (Y SHORT), and DUT (Y DUT) [2] Y INT ¼

h 1 1 i1 Y DUT Y OPEN Y SHORT Y OPEN :

(11:2)

In millimeter-wave measurement, the parasitics becomes more distributive and the ‘‘open-short’’ method starts to lose accuracy. Some high-frequency de-embedding techniques, which use different lumped equivalent circuit to model the parasitics and different test structures for extraction, have been proposed [3,4]. The frequency range of valid ac measurement is extended using these methods, but the accuracy of the parasitics model depends on the process technology.




11-3

Improved De-Embedding Techniques

G

G

C2 L1

INT

L2

P1

C1

P2

P1

P2

OPEN

C3

SHORT

L3 G

G

SHORT test structure FIGURE 11.3 technique.

The parasitics model usedin the "open" technique

The SHORT test structure and the equivalent circuit of parasitics model used in ‘‘open-short’’

INT

OPEN

THRU1

THRU2

P2

P1

The parasitics model using cascade two-port networks FIGURE 11.4

An illustration of the parasitics model using cascade two-port networks.

Moreover, some methods that use cascade two-port networks instead of lumped equivalent circuit to model the parasitics are presented [5,6]. Figure 11.4 shows the parasitics model used in these techniques. The two-port networks capture the distributive effects. However, the model neglects the crosstalk between the two ports, and hence is not fit for devices with lossy substrate. All the de-embedding techniques introduced above use simplified versions of parasitics model. These approaches become problematic when the neglected terms in parasitics models are not negligible. To generalize the problem and avoid the potential inaccuracy, a four-port system calibration methodology is developed [7–9]. In this chapter, we will focus on the improved four-port de-embedding technique and its application.

11.2

Improved De-Embedding Technique

Four-Port Parasitics Model and Theory Figure 11.5 shows a DUT using a four-port network as parasitics model and a two-port network as the intrinsic device. The four ports include two extrinsic ports (1 and 2), which are the measured referenceplane, and two intrinsic ports (3 and 4), which represent the intrinsic device characteristics. Since only the I–V characteristics at the extrinsic ports and intrinsic ports are concerned, the four-port network is sufficient to model the parasitics effects. Furthermore, at small-signal level, the parasitics can be modeled as a linear four-port network, which is characterized by a 4 4 matrix. Then, the I–V relationships of the extrinsic and intrinsic ports can be written as a 4 4 y-matrix according to


11-4




DUT Parasitics I1

I2 I3

I4 V3

V1

V4

INT

V2

Parasitics

FIGURE 11.5

An illustration of the parasitics model using four-port networks.

0

1 2 Y11 I1 ) B I2 ) C 6 Y21 B C¼6 @ I3 ) A 4 Y31 Y41 I4

Y12 Y22 Y32 Y42

Y13 Y23 Y33 Y43

30 1 V1 Y14 B V2 C Y24 7 7B C: Y34 5@ V3 A Y44 V4

(11:3)

In some circumstances, Yij can be 1 (i.e., there is a short between various ports). In this case, let Yij be very large to avoid any singularities. Let Ve and Ie be the extrinsic voltage and current vectors, and Vi and Ii be the intrinsic voltage and current vectors [7]

Ve Vi

0

1 V1 B V2 C C ¼B @ V3 A and V4

Ie Ii

0

1 I1 B I2 C C ¼B @ I3 A: I4

(11:4)

Then we have [10]

Ie Ii

¼

Yee Yie

Yei Yii

Ve , Vi

(11:5)

where [Yee], [Yei], [Yie], and [Yii] are four 2 2 matrices. The extrinsic y-parameters and the intrinsic device y-parameters can then be related as Y DUT Ve ¼ Yee Ve þ Yei Vi ,

(11:6)

Y INT Vi ¼ Yie Ve þ Yii Vi ,

(11:7)

where YINT are the intrinsic device y-parameters, and YDUT are the 2-port y-parameters of the DUT. Note that the current directions of the intrinsic device are opposite to the current directions of the parasitics. It follows from Equation 11.6 and Equation 11.7 that Y DUT ¼ Yee Yei (Y INT þ Yii )1 Yie

(11:8)

Y INT ¼ Yie (Y DUT Yee )1 Yei Yii :

(11:9)

or




11-5


Once the 16 variables of the 4 4 matrix are known, one can build the appropriate one-to-one relationship between the extrinsic and intrinsic y-parameters. For each test structure, a 2 2 y-parameters can be obtained using the measured raw S-parameters. Given the intrinsic y-parameters of the test structure as well as the measured raw y-parameters, four equations are derived from one test structure. To solve for all 16 variables, one needs to measure at least four different test structures, unless approximations are made. For example, the ‘‘open-short’’ de-embedding method only uses two test structures. Apply this method in the four-port system, one gets Vi ¼ 0 for the short structure and Ii ¼ 0 for the open structure. Applying these two boundary conditions to Equation 11.5 yields Y SHORT ¼ Yee ,

(11:10)

Y OPEN ¼ Yee Yei (Yii )1 Yie :

(11:11)

Putting the above equations to Equation 11.8, after simplification, yields YX þ YB ¼ YX YB1 Yie YX1 Yei þ YX YB1 Yie YB1 Yei ,

(11:12)

YX ¼ Y DUT Y SHORT ,

(11:13)

YB ¼ Y SHORT Y OPEN :

(11:14)

Without loss of generality, YX can be any matrix, and thus the equalities above hold when Yie ¼ Yei ¼ Yii ¼ Y SHORT Y OPEN :

(11:15)

Equation 11.15 gives the condition (assumption) under which the ‘‘open-short’’ approach is valid. At high frequencies (e.g., f > 30 GHz), however, this assumption is clearly no longer valid because the distributed nature of the parasitics must be considered.

De-Embedding Process As discussed above, at least four test structures are required to solve all 16 elements. Therefore, besides the OPEN and SHORT, more test structures are designed to obtain more boundary conditions. The question is then to decide which test structures should be used. Observe in Equation 11.10 that Yee equals to the measured SHORT y-parameters: Y SHORT. To decouple the product term Yei(Y INT þ Yii)1 Yie in Equation 11.8 is the key to solve Yei, Yie, and Yii. Then, different test structures are chosen to obtain matrices in the form of 0 Y , a ie b 0 Y RO ¼ Yei Y , 0 0 ie c c Y TS ¼ Yei Y : c c ie Y LO ¼ Yei

0 0

(11:16) (11:17) (11:18)

where a, b, and c are constants. From Equation 11.16 to Equation 11.18, Yei, Yie can be calculated Yie ¼ k1 Yei0 ¼ k1

1 m1

RO RO y12 =y11 LO LO , m1 y12 =y11

(11:19)


11-6




Yei ¼ kr Yie0 ¼ kr

1 RO RO y21 =y11

m2 LO LO : m2 y21 =y11

(11:20)

And Yii is Yii ¼ k1 kr Yie0 (Y SHORT Y OPEN )1 Yei0 ,

(11:21)

where m1 ¼

TS TS RO RO y12 =y11 y12 =y11 , LO LO TS TS y12 =y11 y12 =y11

(11:22)

m2 ¼

TS TS RO RO y21 =y11 y21 =y11 , LO LO TS TS y21 =y11 y21 =y11

(11:23)

and kl and kr are scale-factors and will be determined below. To obtain the matrices discussed above, five test structures are used. Figure 11.6 shows the layout of the DUT and the required test structures. The Ytest,int þ Yii for OPEN, LEFT, RIGHT, THROUGH test structures are

Yii, 11 Yii, 12 , Yopen,int þ Yii ¼ Yii, 21 Yii, 22 Yii,11 þ g l Yii,12 Yleft,int þ Yii ¼ , Yii,21 Yii,22

(11:24) (11:25)

G

G

G

G

G

G

P1

P2

P1

P2

P1

P2

G

G

G

G

G

G

OPEN

DUT

SHORT

G

G

G

G

G

G

P1

P2

P1

P2

P1

P2

G

G

G

G

G

G

THROUGH FIGURE 11.6

LEFT

RIGHT

The layout of the DUT and the required test structures used in the four-port technique.




11-7


Yright,int þ Yii ¼ Ythrough,int þ Yii ¼

Yii,11 Yii,21

Yii,11 þ A Yii,21 A

Yii,12 , Yii,22 þ gr Yii,12 A , A ! 1, Yii,22 þ A

(11:26) (11:27)

where g1 ¼ 1/R1 and gr ¼ 1/Rr are conductances of the resistors in the LEFT and RIGHT structures, respectively. Using simple mathematics, one can prove that [9]

0 Y , a ie 0 Y , 0 ie c Y , c ie

0 Y xY (1 x)Y ¼ Yei 0 b Y RIGHT yY OPEN (1 y)Y SHORT ¼ Yei 0 c Y THRU zY OPEN (1 z)Y SHORT ¼ Yei c LEFT

OPEN

SHORT

(11:28) (11:29) (11:30)

where x, y, and z are the solutions of LEFT Y xY OPEN (1 x)Y SHORT ¼ 0,

(11:31)

RIGHT Y yY OPEN (1 y)Y SHORT ¼ 0,

(11:32)

THRU Y zY OPEN (1 z)Y SHORT ¼ 0,

(11:33)

and x 6¼ 1, y 6¼ 1, and z 6¼ 1. 0 0 0 Therefore, the normalized Yei , Yie , and Yii are derived. Take them into Equation 11.9, one gets 0

0

0

Y INT ¼ kr kl Yie (Y DUT Yee )1 Yei Yii :

(11:34)

The next step is to solve the scale factors kr and kl. Substituting Y DUT using Y LEFT yields Y

left,int

0

0

¼ kr kl (Yie (Y

DUT

0

1

0

0

Yee ) Yei Yii ) ¼ kr kl Y

LINT

g ¼ l 0

0 , 0

(11:35)

0

DUT Yee)1 Yei Yii . Thus kr kl ¼ gl/Y11LINT. Furthermore, if the parasitics are where Y LINT ¼ Yie (Yp ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi LINT . passive, then kr ¼ kl ¼ gl =Y11 As a summary, the improved four-port de-embedding process includes:

1. Measure the S-parameters of the DUT, OPEN, SHORT, THROUGH, LEFT, and RIGHT, and convert the S-parameters into y-parameters. 2. Solve for x, y, and z in Equation 11.28 to Equation 11.30, and choose the solution that x 6¼ 1, y 6¼ 1, and z 6¼ 1. 3. Calculate Y LO, Y RC, and Y TS using Equation 11.16 to Equation 11.18. 0 0 0 4. Obtain normalized [Yei ], [Yie ], and [Yii ] by using Equation 11.19 to Equation 11.21. 5. Calculate the scale factor k ¼ krkl using Equation 11.35. 6. Calculate the intrinsic y-parameters using Equation 11.9.


11-8




Validity and Layout Concerns In this method, it has been assumed that Equation 11.24 to Equation 11.27 and Yee þ Yei (Yshort,int þ Yii)1 Yie Yee hold, indicating that the intrinsic ac characteristics of test-structures should be ideal. It is necessary to check the validity of the de-embedding methodology using nonideal test structures. In ideality, one solution of x, y, and z should be 1, and the intrinsic RIGHT should be open at port 1 and a resistor at port 2. These equations are used for validity verification. In the current technology for RFIC applications, the intrinsic device layout size is smaller than a few tens of microns although the DUT size (including pads, etc.) is several hundreds of microns, and thus the assumptions made in this method are valid in the millimeter-wave band with optimized layout design. In higher frequency measurements (i.e., f > 300 GHz), if one can accurately model the nonideal intrinsic S-parameters of the test structures, the four-port methodology is feasible with a few modifications in the extraction equations.

11.3

Comparison

Both HP-ADS simulation and ac measurement in SiGe HBTs are performed here to fully verify and compare the accuracy of the improved four-port de-embedding methodology with other techniques (e.g., ‘‘open-short’’). In simulation, several equivalent circuits were chosen to determine how a given parasitic model impacts the four-port technique and ‘‘open-short’’ technique. Figure 11.7 shows three equivalent circuits of the parasitics. The parasitics model (from 1 to 3) becomes more distributive using more capacitors and inductors. The component values in each circuit were extracted and optimized from the measured

Model 1

Port 1

Port 3

Model 2

Port 4

Port 2 Port 1

Port 3

Model 3

1

FIGURE 11.7

3

4

2

Three equivalent circuits of the parasitics used in the simulation.

Port 4

Port 2




5

10

5

0 0.0

20.0

40.0 60.0 80.0 Frequency(GHz)

0 100.0

0.0

0.0

–0.5

–0.5

–1.0

HP–ADS simulation Intrinsic 4–port (this work) Open–Short 1 Open–Short 2 Open–Short 3

–1.5 0.0

–10 HP–ADS simulation Intrinsic 4–port (this work) Open–Short 1 Open–Short 2 Open–Short 3

0.0

20.0

40.0 60.0 80.0 Frequency (GHz)

–20

–30 100.0

Real(Y22) (mS)

30

Imag(Y21) (mS)

Real(Y21) (mS)

0

10


8

40

20

20.0

6 4

–1.0

–1.5 100.0

5 HP–ADS simulation Intrinsic 4–port (this work) Open–Short 1 Open–Short 2 Open–Short 3

4 3 2

2 0 0.0

Imag(Y22) (mS)

10

Real(Y12) (mS)

15 HP–ADS simulation Intrinsic 4–port (this work) Open–Short 1 Open–Short 2 Open–Short 3

Imag(Y11) (mS)

Real(Y11) (mS)

15

Imag(Y12) (mS)

11-9


1

20.0


0 100.0

FIGURE 11.8 The extracted de-embedded y-parameters using both the ‘‘open-short’’ and the new four-port method on each parasitic model.

S-parameters of parasitics. A device model carefully calibrated to measured data was used to simulate the S-parameters of the SiGe HBTs, both with and without the parasitics. The simulated frequency range was 1 to 100 GHz. Figure 11.8 shows the de-embedded y-parameters after applying both the ‘‘openshort’’ and the four-port method on each parasitic model. For equivalent circuit model 1, the intrinsic y-parameters are accurately de-embedded using both the four-port and ‘‘open-short’’ method. For equivalent circuit models 2 and 3, however, observe that the ‘‘open-short’’ method produces large deviations from the intrinsic y-parameters at frequencies above about 30 GHz. This clearly demonstrates the potential inaccuracy of the traditional ‘‘open-short’’ method at high frequencies. Observe as well that the accuracy of the new four-port method is not dependent on the choice of the equivalent circuit or the frequency. Both de-embedding techniques applied on actual 2 to 110 GHz S-parameter measurement data of state-of-the-art SiGe HBTs are also compared. The measured device is a 0.2 2.5 mm2 highperformance npn SiGe HBT with a peak fT of 110 GHz at JC ¼ 7.0 mA/mm2. Figure 11.9 shows the extracted fT and fmax as a function of current density. Figure 11.10 shows the raw DUT S-parameters and extracted S-parameters using the ‘‘open-short’’ and the four-port method. For a better comparison, we have plotted S21/6 and S11 0.75 instead of S21 and S11. Observe that there are large deviations between the un-deembedded and de-embedded data, indicating that the on-wafer parasitics are significant in this SiGe technology. Note that the deembedded S-parameters using the two methods are in close agreement, except in the high-frequency range, implying the validity of both two methods at low frequencies. To more closely examine the differences between the two methods, we plot the de-embedded Y21 as a function of frequency (as shown in Figure 11.11). The deviation of the results is negligible at frequencies lower than about 30 GHz. At frequency higher than 30 GHz, the ‘‘open-short’’ method overestimates the


11-10

page 10 17.10.2007



120

f T, fMAX (GHz)

100 80 60

SiGe HBT 0.2×2.5µm2 VCB = 1 V fT fMAX

40 20 0 0.1

FIGURE 11.9

1.0 JC (mA/µm2)

10.0

30.0

The extracted fT and fmax as a function of current density JC of the measured SiGe HBT. VBE = 0.9 V, VCB = 1 V DUT open–short four–port S21/6

S12

S11–0.75

FIGURE 11.10 method.

S22

The raw DUT S-parameters and extracted S-parameters using the ‘‘open-short’’ and the four-port

0⬚

200

–45⬚ 100

–135⬚

Angle (Y21)

Abs(Y21) (mS)

–90⬚

–180⬚

VBE = 0.9 V, VCB = 1 V open–short four–port

–225⬚ –270⬚

10 10.0

100.0

Frequency (GHz)

FIGURE 11.11

The extracted y21 as a function of frequency using the ‘‘open-short’’ and the four-port method.


page 11 17.10.2007


11-11


magnitude and underestimates the phase of Y21. This is caused by the distributive nature of the wire lines between the pads and the intrinsic device. As expected, the error increases as the frequency increases. These errors can severely distort the measured characteristics of the device (e.g., the gain) at high frequencies. Figure 11.12 shows the current gain H21 as a function of frequency at different bias points. Although the current gain extracted using the two methods nearly overlap at lower frequencies (the ‘‘open-short’’ de-embedded gain is slightly less than the ‘‘four-port’’ gain), at frequencies above 70 GHz, the current gain extracted with the ‘‘open-short’’ method ceases to decrease, which is clearly not the physical (real) behavior of the intrinsic device. Observe, however, that the current gain with the fourport method continues decreasing with a constant slope of about 20 dB per decade, indicating the accuracy of this technique.

11.4

Noise De-Embedding Technique

The four-port technique can also be applied to noise de-deembedding. A generalized noise system can be characterized by a noise current correlation matrix SY or noise voltage correlation matrix SV. Figure 11.13 shows the equivalent circuit of the noise current model for an n-port system [11,12]. The correlation matrix can be written as 2 6 SY ¼ 4

in,1 in*,1

in,1 in*,n

.. .

in,n in*,1

.. .

in,n in*,n

3 7 5,

(11:36)

40 VBE = 0.9 V 30 H21 (dB)

20dB/decade 20

VBE = 0.8 V

10 0

VCB = 1 V VBE = 0.8, 0.82, 0.84, 0.9 V open–short four–port

–10 1.0

FIGURE 11.12

10.0 Frequency (GHz)

100.0

The current gain H21 as a function of frequency at different bias points.

1

2

1

2 iN,2

iN,1 Noisy N-port System N-1

Noiseless N-port System N

N-1

N

iN,N-1 N+1

iN,N N+1

FIGURE 11.13 The equivalent circuit of the noise current model for an n-port system. (From F Bonani, G Ghione, MR Pinto, and RK Smith. IEEE Trans. Electron Dev. 45:261–269, 1998.)


11-12

page 12 17.10.2007



DUT Noiseless parasitics

INT iN,e1

iN,i1

iN,i2

iN,int1

FIGURE 11.14 device.

iN,e2

iN,int2

The equivalent circuit of noise model of the four-port parasitics network and two-port intrinsic

where in,j , j ¼ 1,2,3, . . . is the noise current source at port j. In a two-port system, the minimum noise figure Fmin, noise impedance Rn, and the optimum noise admittance Yopt can be directly converted into the noise current correlation matrix SY2 [11]. Once the 4 4 Y-matrix is obtained, the noise de-embedding method is thus straightforward [13]. Figure 11.14 shows the equivalent circuit of noise model of the four-port parasitics network and two-port intrinsic device. The noise current correlation matrix SY4 of the parasitics can be written as 2

SYn,11 6 SYn,21 SY4 ¼ 6 4 SYn,31 SYn,41

SYn,12 SYn,22 SYn,32 SYn,42

SYn,13 SYn,23 SYn,33 SYn,43

2 3 in,1 in*,1 SYn,14 6 * 6 SYn,24 7 7 ¼ 6 in,2 in,1 6 5 SYn,34 4 in,3 in*,1 SYn,44 in,4 in*,1

in,1 in*,2

in,1 in*,3

in,2 in*,2

in,2 in*,3

in,3 in*,2

in,3 in*,3

in,4 in*,2

in,4 in*,3

in,1 in*,4

3

7 in,2 in*,4 7 7¼~ in ~ in* , in,3 in*,4 7 5 in,4 in*,4

where SYn,ij, i, j ¼ 1,2,3,4 are the noise current correlation between port i and port j. For brevity, in and SY4 are also written as 0 1 in,1 B in,2 C ~ C ¼ in,e (11:37) in ¼ B @ in,3 A in,i in,4 and SY4 ¼

SYn,ee SYn,ie

SYn,ei SYn,ii

Yee ¼ 4kT Real Yie

Yei Yii

,

(11:38)

where in,e and in,i are extrinsic and intrinsic noise current sources, respectively. The four-port I–V relation of the DUT, considering noise currents, can then be written as

Ie þ in,e Ii þ in,i þ in,int

¼

Yee Yie

Yei Yii

Ve : Vi

(11:39)

One can thus calculate the intrinsic noise correlation matrix as [9] SYn,int ¼ (YT )1 (SYn,total SYn,ee )(YT* )1 SYn,ii þ (YT )1 SYn,ei þ SYn,ie (YT* )1 , where YT ¼ Yei (Y INT þ Yii)1.

(11:40)



page 13 17.10.2007


11-13

Acknowledgments We would like to thank D. Greenberg, J.-S. Rieh, A. Joseph, D. Herman, B. Meyerson, and the IBM SiGe team for their support and contributions. This work was supported by IBM, the Semiconductor Research Corporation, and the Georgia Electronic Design Center at Georgia Tech.

References 1. PJ van Wijnen, HR Claessen, and EA Wolsheimer. A new straightforward calibration and correction procedure for ‘‘on wafer’’ high-frequency s-parameter measurements (45 MHz–18 GHz). Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 1987, pp. 70–73. 2. MCAM Koolen, JAM Geelen, and MPJG Versleijen. An improved de-embedding technique for on-wafer high-frequency characterization. Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 1991, pp. 188–191. 3. H Cho and DE Burk. A three-step method for the de-embedding of high-frequency s-parameter measurements. IEEE Trans. Electron Dev. 38:1371–1375, 1991. 4. EP Vandamme, DMMP Schreurs, and CV Dinther. Improved three-step de-embedding method to accurately account for the influence of pad parasitics in silicon on-wafer RF test-structures. IEEE Trans. Electron Dev. 48:737–742, 2001. 5. J Grzyb, D Cottet, and G Tro¨ster. Systematic deembeding of the transmission line parameters on high-density substrates with probe-tip calibrations. Technical Digest of the IEEE Electronic Components and Technology Conference, 2002, pp. 1051–1057. 6. CH Chen and MJ Deen. A general noise and s-parameter deembedding procedure for on-wafer high-frequency noise measurements of MOSFETs. IEEE Trans. Micro. Theory Tech. 49:1004–1005, 2001. 7. RA Pucel, W Struble, R Hallgren, and UL Rohde. A general noise de-embedding procedure for packaged two-port linear active devices. IEEE Trans. Micro. Theory Tech. 40:2013–2024, 1992. 8. S Bousnina, C Falt, P Mandeville, AB Kouki, and FM Ghannouchi. An accurate on-wafer deembedding technique with application to HBT devices characterization. IEEE Trans. Micro. Theory Tech. 50:420–424, 2002. 9. Q Liang, JD Cressler, G Niu, Y Lu, G Freeman, DC Ahlgren, RM Malladi, K Newton, and DL Harame. A simple four-port parasitic deembedding methodology for high-frequency scattering parameter and noise characterization of SiGe HBTs. IEEE Trans. Micro. Theory Tech. 51:2165– 2174, 2003. 10. V Rizzoli, F Mastri, and C Cecchetti. Computer-aided noise analysis of MESFET and HEMT mixers. IEEE Trans. Micro. Theory Tech. 37:1401–1410, 1989. 11. H Hillbrand and PH Russer. An efficient method for computer-aided noise analysis of linear amplifier networks. IEEE Trans. Circ. Syst. CAS-23:235–238, 1976. 12. F Bonani, G Ghione, MR Pinto, and RK Smith. An efficient approach to noise analysis through multidimensional physics-based models. IEEE Trans. Electron Dev. 45:261–269, 1998. 13. S Lee, V Tilak, KJ Webb, and LF Eastman. Intrinsic noise characteristics of AlGaN/GaN HEMTs. Technical Digest of the IEEE MTT-S International Microwave Symposium, 2002, pp. 1415–1418.


page 14 17.10.2007


Cressler / Measurement and Modeling of Silicon Heterostructure Devices 66927_A001 Final Proof

page 1


A.1 Properties of Silicon and Germanium


The energy band structures of Si and Ge are depicted in Figure A.1.1, together with (1) their carrier effective mass parameters (Table A.1.1) and (2) their bulk structural, mechanical, optical, and electrical properties (Table A.1.2) [1–3].

Si

2

Ec

2

3

3

Ge

Eg

−1

Energy (eV) 0 1

1 0

Eg

−1

Energy (eV)

Ec

−2

Ev

L

[111]

Γ

[100]

X

−3

−3

−2

Ev

L

[111]

Γ

[100]

X

FIGURE A.1.1 Energy band structure, showing the principal conduction and valence bands of Si and Ge as a function of k-space direction. (From M Shur. Physics of Semiconductor Devices. Englewood Cliffs, NJ: Prentice-Hall, 1990. With permission.)

A.1-1


A.1-2

page 2



TABLE A.1.1

Carrier Effective Mass Parameters for Si and Ge

Parameter

Units

Effective electron mass (m n*) Longitudinal (4.2 K) Transverse (4.2 K) Density-of-states (4.2 K) Density-of-states (300 K)

(m o)

Effective hole mass (m p*) Heavy hole (4.2 K) Light hole (4.2 K) Density-of-states (4.2 K) Density-of-states (300 K)

(m o)

TABLE A.1.2

Silicon

Germanium

0.9163 0.1905 1.062 1.090

1.58 0.082 — —

0.537 0.153 0.59 1.15

0.28 0.044 — —

Properties of Bulk Si and Ge

Parameter

Units

Silicon

Germanium

Atomic number Atomic density Atomic weight Density Electronic orbital configuration Crystal structure Lattice constant (298 K) Dielectric constant Breakdown strength Electron affinity Specific heat Melting point Intrinsic Debye length (300 K) Index of refraction Transparency region Thermal conductivity (300 K) Thermal expansion coefficient (300 K) Young’s modulus Energy bandgap (low doping)

— (atoms/cm3) (g/mole) (g/cm3) — — (A˚) — (V/cm) (V) (J/g-8C) (8C) (mm) — (mm) (W/cm-8C) (8C 1) (dyne/cm2) (eV)

Equivalent conduction band minima Effective electron mass (300 K) Effective hole mass (300 K) Intrinsic carrier density (300 K) Effective conduction band DoS (300 K) Effective valence band DoS (300 K) Electron mobility (300 K) Hole mobility (300 K) Electron diffusivity (300 K) Hole diffusivity (300 K) Optical phonon energy Phonon mean free path length Intrinsic resistivity (300 K)

— (mo) (mo) (cm 3) (cm 3) (cm 3) (cm2/V-sec) (cm2/V-sec) (cm2/sec) (cm2/sec) (meV) A˚

14 5.021022 28.09 2.329 (Ne) 3s23p2 Diamond 5.43107 11.7 3105 4.05 0.7 1412 24 3.42 1.1–6.5 1.31 2.610 6 1.91012 1.12 (300 K) 1.17 (77 K) 6 1.18 0.81 1.021010 2.81019 1.041019 1450 500 37.5 13 63 76 3.16105

32 4.421022 72.6 5.323 (Ar) 3d104s24p2 Diamond 5.65791 16.2 1105 4.00 0.31 1240 0.68 3.98 1.8–15 0.60 5.910 6 — 0.664 (291 K) 0.741 (4.2 K) 8 — — 2.331013 1.041019 6.001018 3900 1900 100 49 37 105 47.62

(V cm)


Properties of Silicon and Germanium

page 3


A.1-3

References 1. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003. 2. M Shur. Physics of Semiconductor Devices. Englewood Cliffs, NJ: Prentice-Hall, 1990. 3. R. Hull, editor. Properties of Crystalline Silicon. London: EMIS Datareviews Series, Number 20, INPSEC, 1999.


page 4



page 1


A.2 The Generalized Moll–Ross Relations


The classical solution for the collector current density in a Si BJT, derived by Shockley, necessarily assumes a constant base doping profile. In this case, for low-injection conditions, the drift component of the minority carrier transport equation can be neglected, and the minority carrier diffusion equation solved under the Shockley boundary conditions. The resultant equation, under the assumptions of negligible neutral base recombination and forward-active bias, is the well-known expression JC ¼

qDnb 2 DEgbapp =kT qVBE =kT n e e 1 : io W Nab b

(A:2:1)

2 Here, Dnb is the minority electron diffusivity, Nab is the ionized base doping level, nio is the low-doping intrinsic carrier density, given by,

n2io ¼ NC NV eEgo =kT ,

(A:2:2)

and DEgbapp is the heavy-doping induced bandgap narrowing. The path to the generalization of this result to the ‘‘real-world’’ case of a nonconstant base doping profile (Figure A.2.1) is nonobvious, and even a cursory glance at the problem is enough to convince one that it cannot follow the original path in Shockley’s approach. The complexity of this problem results from the addition of the field-driven transport, which is now no longer negligible due to the dopinggradient-induced field. The clever solution to this problem was first presented in the classic paper by Moll and Ross in 1956, the so-called ‘‘Moll–Ross relation’’ [1]. Unfortunately, that solution made two undesirable assumptions: (1) that the minority electron mobility (hence, diffusivity) is constant across the quasineutral base and (2) that the intrinsic carrier density is constant across the quasineutral base. The latter assumption, in particular, fails in the presence of a heavily doped base (i.e., real life), since the apparent bandgap narrowing is inherently position dependent across the base, and hence the effective bandgap in the base is also position dependent.* In essence, then, the problem becomes one of solving for the collector current density in the presence of both nonconstant base doping and nonconstant base bandgap, and is particularly relevant to the graded-base SiGe HBT. This problem remained unsolved for *In fairness, Moll and Ross cannot be blamed for the second assumption since doping-induced bandgap narrowing had not yet been discovered.

A.2-1


A.2-2

page 2



Nab−(x)

Space charge n+

n−

p Wb

0 E

x C

B

FIGURE A.2.1 Schematic nonconstant base doping profile used in the derivations.

almost 30 years until the seminal paper by Kroemer in 1985 [2]. Since Kroemer’s ‘‘generalized Moll–Ross relations’’ are the starting point for both the dc and ac analysis of the graded-base SiGe HBT (Chapter 4, see Silicon Heterostructure Devices), we present that elegant derivation here (showing all of the mathematical steps that Kroemer neglected to include in his paper). The assumptions in Kroemer’s solution include: (1) 1-D transport, (2) transport by both drift and (x) for all x across the base), (4) negligible diffusion, (3) low-injection conditions (i.e., nb(x) Nab neutral base recombination, and (5) forward-active bias. Importantly, however, there are no assumptions on the position dependence of the base doping profile or the base bandgap.* We begin from the generalized drift–diffusion minority electron transport equation, as expressed in terms of the minority electron quasi-Fermi potential Jn ¼ qmn nrfn ,

(A:2:3)

which for our 1-D Si BJT problem reduces to JC ¼ qmnb (x)nb (x)

dfn (x) : dx

(A:2:4)

In the quasineutral base, the majority carrier (hole) quasi-Fermi potential (fp) in low-injection is constant, such that JC ¼ qmnb (x)nb (x)

d fn (x) fp , dx

(A:2:5)

and from the generalized Shockley boundary condition nb (x)pb (x) ¼ n2ib (x)eq(fn (x)fp )=kT ,

(A:2:6)

kT nb (x)pb (x) ln ¼ fn (x) fp : q n2ib (x)

(A:2:7)

which can be rewritten as

*Interestingly, additional generalizations to Kroemer’s result have been recently offered [3]. Let it never be said that the final word in device physics is ever in.


page 3


The Generalized Moll–Ross Relations

A.2-3

Taking the derivative of both sides we have kT q

n2ib (x) d nb (x)pb (x) d f ¼ (x) f p : n2ib (x) dx n nb (x)pb (x) dx

(A:2:8)

Substituting this result back into Equation A.2.5, we obtain kT n2ib (x) d nb (x)pb (x) JC ¼ qmnb (x)nb (x) q nb (x)pb (x) dx n2ib (x)

(A:2:9)

We now integrate this expression from some arbitrary point in the base profile to the neutral base boundary (Wb) to obtain ð Wb x

JC pb (x 0 ) 0 nb (x 0 )pb (x 0 )Wb dx ¼ n2ib (x 0 ) x qDnb (x 0 ) n2ib (x 0 )

(A:2:10)

Under the assumptions of negligible neutral base recombination (i.e., JC is a constant to the integration), and using the fact that in forward-active bias, pb (Wb )nb (Wb ) ’ n2ib (Wb )

(A:2:11)

pb (x 0 )dx 0 nb (x)pb (x) ¼1 n2ib (x) Dnb (x 0 )n2ib (x 0 )

(A:2:12)

we find JC q

ð Wb x

At the emitter–base boundary (x ¼ 0), we know from the generalized Shockley boundary condition that nb (0)pb (0) ¼ n2ib (0)eq(fn (0)fp (0) )=kT ,

(A:2:13)

fn (0) fp (0) ¼ VBE ,

(A:2:14)

pb (x)dx ¼ 1 e qVBE =kT , Dnb (x)n2ib (x)

(A:2:15)

and

so that we obtain JC q

ð Wb 0

and thus finally, q(e qVBE =kT 1) , JC ¼ W Ð b pb (x)dx 2 0 Dnb (x)nib (x)

(A:2:16)

This is the ‘‘generalized Moll–Ross relation’’* for the collector current density in a bipolar transistor with nonconstant base doping and arbitrary position-dependence of the base bandgap. Observe that if *I personally would have no problem calling this elegant result the ‘‘Kroemer relation.’’


A.2-4

page 4



we allow pb (x) ¼ Nab (x) ¼ Nab ¼ constant, then we obtain Equation A.2.1, as expected (the extra negative sign simply accounts for the fact that the electron flow is in the opposite direction of the positive current flow). As detailed in Chapter 4 (see Silicon Heterostructure Devices), this fundamental result is the starting point of the derivations for collector current density, the current gain, and the output conductance in a graded-base SiGe HBT. In this case, in addition to the bandgap-narrowing-induced position dependence in the base bandgap, we have an additional contribution from the Ge-strained layer (Figure A.2.2). This Ge contribution easily enters the generalized Moll–Ross relation via nib2 in Equation A.2.16. For more detail on the resultant derivations and the assumptions and approximations involved, the reader is referred to Ref. [4]. An additional desirable feature of Kroemer’s approach is that we can also easily obtain an analytical expression for the base transit time in a device with nonconstant base doping and bandgap. Under a quasistatic assumption we can generally define the base transit time as

q tb ¼ JC

W ðb

nb (x)dx:

(A:2:17)

0

From Equation A.2.12 and neglecting the unity factor, we can solve for nb (x) as

nb (x) ¼

JC n2ib (x) q pb (x)

W ðb x

pb (x 0 )dx 0 Dnb (x 0 )n2ib (x 0 )

(A:2:18)

Substituting this result into Equation A.2.17, we finally obtain

tb ¼

ð Wb 0

8W 9 ðb n2ib (x) < pb (y)dy = dx pb (x) : Dnb (y)n2ib (y);

(A:2:19)

x

Again, observe that if we allow pb(x) ¼ Nab (x) ¼ Nab ¼ constant, we obtain the classical result for a BJT with constant base doping

tb ¼

Wb2 , 2Dnb

(A:2:20)

Ge

Space charge

_ n+

Wb

0 E

n−

p B

x C

FIGURE A.2.2 Schematic drawing of a position-dependent, graded Ge base profile in a SiGe HBT.


The Generalized Moll–Ross Relations

page 5


A.2-5

as expected. This second generalized Moll–Ross relation is the starting point for the derivation of base transit in a graded-base SiGe HBT (Figure A.2.2), as detailed in Chapter 4 (see Silicon Heterostructure Devices) and Ref. [4].

References 1. J. Moll and I. Ross. The dependence of transistor parameters on the distribution of base layer resistivity. Proceedings of the Institute of Radio Engineers 44:72, 1956. 2. H Kroemer. Two integral relations pertaining to electron transport through a bipolar transistor with a nonuniform energy gap in the base region. Solid-State Electronics 28:1101–1103, 1985. 3. SN Mohammad. Generalization of the Moll–Ross relations for heterojunction bipolar transistors. Solid-State Electronics 46:589–591, 2002. 4. JD Cressler and G Niu. Silicon–Germanium Heterojunction Bipolar Transistors. Boston, MA: Artech House, 2003.


page 6



page 1


A.3 Integral ChargeControl Relations A.3.1 A.3.2 A.3.3 A.3.4

Introduction ................................................................. Derivation of a General Relationship ........................ Homojunction Transistors .......................................... Heterojunction Transistors .........................................

A.3-1 A.3-2 A.3-6 A.3-9

Box Ge Profile in the (Metallurgical) Base Region . Trapezoidal Profile in the (Metallurgical) Base Region

Michael Schro¨ter University of California at San Diego

A.3.1

A.3.5 A.3.6

Further Extensions..................................................... A.3-12 Summary .................................................................... A.3-13

Introduction

One of the most important requirements for compact models is an accurate description of the devices’ main current. In an npn bipolar transistor, this is the (generally time dependent) collector current iC which is given by the transport of electrons from emitter to collector. For time (and frequency) dependent quasistatic (q.s.) operation, which is the case in the vast majority of practical applications, the current flowing at the collector terminal can be partitioned into a q.s. transfer current iT and a charging current supplying all charge storage elements connected to the collector terminal. Since the latter elements are described and represented separately in a model, a formulation of iT, which equals IC under d.c. conditions, is of major interest. Before a general relation for iT is derived, a brief historical perspective of the respective theory is given below. The obvious starting point for such an equation is the transport and continuity equation. Since the time derivative term in the latter is taken into account separately by the charge storage elements, and the impact of recombination on iT in modern bipolar transistors is negligibly small, a spatially constant electron current density jnx results (and is observed in device simulation) throughout the structure of a one-dimensional (1D) transistor. This fact can be used to solve the transport equation first for the carrier density and associated charge at a given transfer current, and then reformulate the result to obtain the transfer current at a given charge. The first solution of this kind was published by Moll and Ross in 1956 [1, Equation (13)], exp (V 0 0 =VT ) iT ¼ qmnB n2iB VT R x u B E x l h(x)p(x)dx

(A:3:1)

with p(x) ¼ NB(x), h(x) ¼ 1, VB0 E0 as internal base–emitter voltage, and [xl, xu] as base region. The relation provided a great deal of insight into the dependence of iT (and also the transit time) on doping profile and material parameters in the base region. An improved and more complete expression was later used for one of the first TCAD papers by Ghosh et al. in 1967 [2]. Here, the 2 ) / (mnni2) was included for the first time, but the integral material dependent function h(x) ¼ (mnBniB A.3-1


A.3-2

page 2



was evaluated numerically, thus not providing a formulation suitable for compact modeling. Only shortly thereafter, in 1970 Gummel published his well-known paper about the integral charge-control relation (ICCR) [3]. For the first time, a compact formulation for iT was derived, that contained in a consistent relation between iT and stored charge and with all bias-dependent nonideal effects that were relevant for transistors at that time. In one way or the other, the ICCR has been used until today in any reasonably physics-based compact model. Note that the Scharfetter–Gummel discretization, which was first published and applied to a bipolar transistor, also assumes a constant current density between discrete points, which is the main reason for its numerical stability and wide use for device simulation. An extension of the Moll–Ross relation with special emphasis on a spatially variable bandgap in the base layer was derived by Kroemer in 1985 [4]. Here also the doping density was replaced by the biasdependent hole density as in Equation A.3.1, but no equation suitable for compact modeling was given. In 1993, for both the latter equation and the ICCR a generalization was presented in Ref. [5], with application to compact modeling. The respective generalized ICCR (GICCR) will be discussed in more detail in subsequent sections. During its derivation, the various results mentioned above will be obtained and be referred to again. Since the theories above all apply only to a 1D transistor structure with reasonably smooth material and bandgap changes, and to quasistatic operation, extensions for practical cases are of interest, which will be briefly discussed in A.3.5. The considerations in this chapter apply to Si and SiGe technologies. In the latter, two fundamentally different types of doping profiles can be distinguished which are presently being manufactured and illustrated schematically in Figure A.3.1. The conventional emitter doping (CED) type has a similar profile shape as BJTs, but contains in addition a Ge distribution that increases from the BE junction to the BC junction. In contrast, the low-emitter concentration (LEC) type contains a box Ge profile (or at least a sufficiently high step at the BE junction) that allows to significantly increase the base doping and to lower the emitter doping.

A.3.2

Derivation of a General Relationship

Although the GICCR can be derived for the 3D case, the considerations here will be restricted to the 1D case in order to demonstrate the concept. The assumptions required for the derivation are summarized below: (a) A one-dimensional transistor structure (cf. Figure A.3.1) is considered, with the emitter contact (x ¼ 0) at the mono-silicon surface and the collector contact (x ¼ xC) at the transition from the lightly-doped collector region to the buried layer. This 1D structure does not include the emitter and external collector series resistance. (b) Volume recombination within the above 1D transistor region is negligible. (c) The time derivative is negligible, which corresponds to quasistatic operation. (d) Effects such as thermionic emission and tunneling across the junctions are neglected. They can be accounted for though by separate terms and can be combined with the GICCR solution. Assumptions (a), (b), and (c) together with the electron continuity equation lead to a spatially independent electron current density, Jn ¼ const(x) ¼ JT ¼

IT , AE

(A:3:2)

which can be expressed by the transfer current and area (emitter) AE of the 1D-transistor. The derivation starts with the electron transport equation,


page 3


A.3-3

Integral Charge-Control Relations

0 xe0

N

NE

N

xc0 Wbm

x⬘

mx mGe

NB

NB mGe mp NC

0

xjC

xjE

NC

NE

xC x

xjC

xjE

0

(a)

xC

x

(b)

FIGURE A.3.1 Sketch of doping and Ge profiles for (a) CED transistors and (b) LEC transistors.

Jn ¼ qmn n

dwn dx

(A:3:3)

where mn, n and wn are the electron mobility, density, and quasifermi potential. Inserting n ¼ ni exp[(c wn) / VT] into (A.3.3) gives c wn dfn exp : Jn ¼ qmn ni exp VT VT dx

(A:3:4)

Note that the effective intrinsic carrier density ni accounts for bandgap differences caused by highdoping effects and bandgap-engineering. This topic will be discussed later. Using the transformation d exp (wn =VT ) 1 w dwn ¼ exp n dx VT VT dx

(A:3:5)

c d exp (wn =VT ) Jn ¼ qVT mn ni exp : VT dx

(A:3:6)

leads to

Separation of the differential variables and rearranging terms gives Jn c w exp dx ¼ d exp n : VT qVT mn ni VT

(A:3:7)

Extension of the l.h.s. by the product ni exp(wp/VT) allows to replace the inconvenient term exp(c/VT) by the hole density, yielding Jn p wn dx ¼ d exp : qVT mn n2i exp (wp =VT ) VT Integration of the above equation over the general spatial interval [xl, xu] gives

(A:3:8)


A.3-4

page 4



xðu xl

Jn exp (wp =VT ) p dx ¼ qVT mn n2i

exp (wnð (xu )=VT )

w d exp n : VT

(A:3:9)

exp (wn (xl )=VT )

The result for the r.h.s. is exp (wnð (xu )=VT )

w w (xu ) w (xl ) ¼ exp n exp n : d exp n VT VT VT

(A:3:10)

exp (wn (xl )=VT )

The exact value of wn on the r.h.s. depends on the choice of the integration limits and will be discussed later. First though, the left-hand-side of (A.3.9) is integrated, xðu xl

Jn exp (wp =VT ) JT exp (VB0 E0 =VT ) p dx ¼ 2 qVT mnr n2ir qVT mn ni

xðu

h(x)p(x)dx,

(A:3:11)

xl

with h ¼ hghihw as the normalized weighting function of the hole density, and its components hg ¼

mnr n2ir , mn (x)n2i (x)

hi ¼

Jn (x) , JT

VB0 E0 wp (x) : hw ¼ exp VT

(A:3:12)

mnr and nir are the mobility and intrinsic carrier density, respectively, of a reference material. Equating (A.3.10) with (A.3.11), and solving for the desired transfer current yields the ‘‘master’’ equation h i exp VVB0TE0 exp wnV(xT l ) exp wnV(xT u ) Ð xu , JT ¼ qVT2 mnr n2ir x l hg hi hw pdx

(A:3:13)

from which different analytical formulations can be derived. The choice of the reference material (or transistor region) and its associated values for mnr n2ir is arbitrary and will be discussed later. The integration interval is undefined yet, and so is the impact of the various weighting functions on the integral. An attractive choice for the integration limits is [0, xC], which corresponds to the entire 1D transistor region. As a result of this choice, the electron quasifermi potentials in the numerator assume their known internal terminal values (e.g., for common-emitter configuration), wn (xl ) ¼ wn (0) ¼ 0 and

wn (xu ) ¼ wn (xC ) ¼ VC0 E0 ,

(A:3:14)

with VC0 E0 as (internal) collector–emitter voltage. The denominator integral is more difficult to oversee. Thus, Figure A.3.2 shows the spatial dependence of the weighting functions with the hole density superimposed. Since the hole quasifermi potential equals VB0 E0 over the entire base and adjacent space–charge regions, hw equals 1 where p(x) is significant. Similarly, the electron current density is constant and equals JT even in a larger interval, except in a small region close to the emitter contact, where it increases slightly due to the back injection of holes and the corresponding recombination; the maximum deviation can be 1/Bf. Therefore, without introducing a significant error, it is possible for both BJT and HBT to assume an average value for the functions hi and hw that is very close to 1. According to Figure A.3.2, the main spatial dependence of the weighting function h is caused by hg via the bandgap variation of ni. A smaller contribution to the spatial dependence comes from the doping and field dependence of the mobility.


page 5


A.3-5


1.2 hi h, p (normal.), hp (normal.)

1

p

hϕ, hi

0.8 hg 0.6 hg*p

0.4

0.2

0 0 xje

0.05 xjc

(a)

0.1 x (µm)

0.15

0.2

1.2 hi h, p (normal.), hp (normal.)

1 hϕ, hi 0.8 p hg

0.6

hg*p 0.4

0.2

0 (b)

0

xje

0.05

xjc

0.1 x (µm)

0.15

0.2

FIGURE A.3.2 Spatial dependence of the weighting functions for a CED transistor with the same doping profile: (a) 70 GHz BJT without Ge; (b) 120 GHz HBT with Ge. Bias point (JC ¼ JT,VB0 C0 ) ¼ (0.1 mA/mm2, 0 V). The hole density p, weighting function hg, and their product hgp have been normalized to the respective maximum value. xje and xjc denote the emitter and base junction depth.

Inserting (A.3.14) and hg from (A.3.12) into (A.3.13), extension by q as well as using average values hi and hw yields the basic formulation m n2 exp (VB0 E0 =VT ) exp (VB0 C0 =VT ) Ðx JT ¼ q2 VT nr ir : q 0 C hg pdx hi hw

(A:3:15)

from which practically relevant equations can be derived as shown later. The denominator is not yet suitable for (compact) modeling, but at this point can be prepared for further evaluation by partitioning it into a bias-independent and a bias-dependent portion


A.3-6

page 6



ð xC q

hg pdx ¼ q

ð xC

0

hg p0 dx þ q

0

ð xC hg Dpdx,

(A:3:16)

0

where p0 is the hole density in equilibrium and Dp is the hole density change in the transistor with respect to equilibrium. Dp consists of depletion and minority components. While the latter density is distributed over the whole base region, the former densities are located around the junctions and related to the (ionized) base doping.

A.3.3

Homojunction Transistors

In homojunction transistors, the variation of hg is only caused by high-doping effects. Thus, hg is fairly constant in the region around the peak hole density (cf. Figure A.3.2a), which contributes most to the integral. Defining an average value 2

m n hg ¼ nr 2ir , mn ni

(A:3:17)

the denominator of (A.3.15) becomes ð xC q xE

mnr n2ir p p(x)dx ¼ hg Q mn n2i

(A:3:18)

with the hole charge per area stored in the 1D transistor structure, p ¼ q Q

ð xC p(x)dx:

(A:3:19)

0

Inserting (A.3.18) and (A.3.19) into (A.3.15) yields JT ¼ c

exp (VB0 E0 =VT ) exp (VB0 C0 =VT ) p Q

(A:3:20)

which has the same form as Gummel’s ICCR in Ref. [3], but a different definition of the integration region and, thus, of the charge and controlling voltages. The factor m n2ir c ¼ q2 VT nr ffi q2 VT mn n2i hi hw hg

(A:3:21)

is assumed to be constant over bias. Usually, the most right term is used only, which is obtained by setting hi ¼ hw ¼ 1 and is an excellent assumption for the 1D case. Since the hole density is concentrated mostly in the base, the value for hg and mn n2i is close to that for the base material. The charge in (A.3.19) can be divided into a bias-independent and a bias-dependent component, Q p ¼ Q p0 þ DQ p. The bias-independent charge Q p0 is defined at VB0 E0 ¼ VB0 C0 ¼ 0 and consists of holes stored mostly in the neutral base region 0 x 0 wB0 at equilibrium: p0 ¼ q Q

ð xC 0

p0 (x)dx ffi q

ð wB0 0

p0 (x 0 )dx 0 q

ð wB0

NB (x 0 )dx 0 :

(A:3:22)

0

(Note the use of a different coordinate x 0 in the neutral base region, cf. Figure A.3.1b.) The biasdependent charge component represents all holes, Dp, that for a nonequilibrium bias condition enter the


page 7



A.3-7

base region (i) to charge the depletion regions, (ii) to compensate the electrons injected into the (neutral) base, and (iii) for the injection into emitter and collector, p ¼ q DQ

ð xC

pE þ Q jE þ Q nB þ Q jC þ Q pC Dp(x)dx ¼ Q

(A:3:23)

0

Here, Q jE and QjC are the BE and BC depletion charge (per unit area), respectively, and the other components are the minority charges (per unit area) stored in E, B, and C. As a consequence of the choice of the chosen integration limits, DQp can actually be measured via the terminals. From a physicsbased point of view, the biggest advantage of the extended ICCR (A.3.20) is its firm link between the quasistatic transfer current and the total hole charge, which resembles the charge-controlled operation principle of a bipolar transistor in a very compact form. Examples for the accuracy of various solutions are shown in Figure A.3.3 for a typical Gummel plot. In all cases, the denominator integral (e.g. Q p in (A.3.20)) has been taken directly from device simulation. As expected, the basic Equation A.3.15 follows exactly the simulated behavior of JT (crosses). For the older generation profile (‘‘25 GHz transistor’’ in Figure A.3.3a), the practically interesting approximation (A.3.20) is very accurate at low and medium current densities, and shows only slight deviations at high current densities, which are tolerable though and typical for homo-junction bipolar processes (e.g. [6,7]). The reason for these small deviations is caused by the assumption of a biasindependent value for hg. However, if the minority charge contributions of emitter and collector, QpE and Q pC, are neglected in (A.3.20), the model current becomes far too large. Thus, including only the base charge is not a feasible approach. For the profile of a modern generation Si(Ge) transistor (‘‘70 GHz BJT’’ in Figure A.3.3b), Equation A.3.20 starts to deviate already at medium current densities, affecting the accuracy of the transconductance modeling. This is caused by the increased difference in doping and associated variation of hg across the base region, which requires a different weighting factor for Qp0 and QjE along the same lines as discussed in the next section on HBTs, applying the corresponding Equation A.3.28 gives again a much higher accuracy. The assumption of a bias-independent value for hg deserves some consideration. High-doping effects cause both ni and mn (which is also field dependent) to depend on x within the base region, with the change of ni partially being compensated by the change of mn. Obviously though, as long as the spatial distributions of p and mn n2i do not change with bias, hg remains bias independent. This holds quite well for low and medium current densities where p is concentrated in the base region, and the mobility depends only very slightly on bias. Toward high current densities, however, p spreads out into the collector and partially also into the emitter region. In the collector, for instance, high-doping effects can be neglected but the field (and thus bias) dependence of mn is significant, leading to a different weighting of the hole density in this region. As a consequence, the average value hg defined at low current densities is not quite correct anymore at high current densities and causes the observed small deviation from the exact current. Note though that the field dependence of the mobility around the BC junction decreases at high current densities. At this point, the choice of the integration limits shall be briefly discussed. Fundamentally, there is an infinite number of possible integration intervals. Besides the one selected above (i.e., entire 1D transistor), the other most important choice in literature (e.g., Refs. [3,4]) is the base region, i.e., x 2 [xjE,xjC]. In this case, hg is only a very weak function of bias, but there are serious disadvantages of this choice: (i) the unknown values for the electron quasi-fermi potentials at the base region boundaries, i.e., wn(xjE) and wn(xjC) in the numerator of (A.3.13), are not easily accessible by measurements; (ii) a separate determination (i.e., measurement) of the base hole charge, in particular the base minority charge, is difficult at medium to high current densities. The original and most famous expression of the ICCR as given by Gummel in Ref. [3], which has the same form as (A.3.20), is in fact based on considering only the base region for the integration and assuming contributions from outside that region to be negligible. Although this was a reasonable assumption at that time for the charge, it was not for the voltage drop toward the contacts.


A.3-8

page 8



102

(a)

101

JC (mA/µm2)

100 10−1 X XX X X X X

10−2

XX X X X XX X 10−4 X XX XX 10−5 0.6 0.65 0.7 0.75

XXX XXX X X X XX XXXX XX X X X X X X XXXX XXXX X X X X X X X

10−3

0.8 0.85 VBE (V)

0.9

0.95

1

102

(b)

101

X

X X X

JC (mA/µm2)

100 10−1 10−2 10−3 10−4 10−5 0.6

0.65

0.7

0.75

0.8 0.85 VBE (V)

0.9

0.95

1

FIGURE A.3.3 Transfer current density for (a) 25 GHz BJT and (b) 70 GHz BJT: comparison between device simulation (symbols) and analytical calculations from Equation A.3.15 (solid line), Equation A.3.24 (dotted line), Equation A.3.20 (dashed line), as well as Equation A.3.20 without QpE þ QpC as dash-dotted line in (a) and Equation A.3.28 as dash-dotted line in (b). The arrow indicates the current density at which the fT peak occurs.

An often found further simplification is to replace the hole density in (A.3.19) by the base doping density NB. As a consequence, the hole charge equals the expression on the most r.h.s. of (A.3.22) and does not contain any bias-dependent ‘‘nonideal’’ effects anymore. Neglecting the voltage drops toward the contacts, Moll and Ross [1] first derived the corresponding expression for the transfer current JT ¼ qVT mnB n2iB

exp (VB0 E =VT ) exp (VB0 C0 =VT ) Ð WB 0 0 NB dx

(A:3:24)

This is a more general relation compared to the classical transistor theory along the lines of Ebers and Moll [9], and aided the understanding that the transfer current is linked to the integral of the base


page 9


A.3-9


doping and not to some spot value. As shown in Figure A.3.2, Equation A.3.24 produces an almost ideal characteristic due to the missing bias-dependent charge components.

A.3.4

Heterojunction Transistors

A comparison for the weighting function hg between a SiGe and a Si transistor with the same doping profile was already shown in Figure A.3.2. While the spatial dependence of the hole QFP and electron current density and, thus, of hw and hi is still similar to BJTs, the intentional bandgap differences in HBTs lead to additional variations of ni2 within the integration interval [0,xC]. As a consequence, it is impossible to define a single average value hg over this whole interval. Thus, the denominator integral in (A.3.15) now has to be formulated in terms of charge components in separate transistor regions that are multiplied with an average value of the weighting function hg taken over the respective region. In HBTs the transition from one bandgap value to another usually takes place close to the junctions. Therefore, Ðxc partitioning of the respective integral q hg pdx into neutral and space–charge regions is one reasonable 0

choice in order to obtain separate expressions, in which the weighting function is sufficiently independent on location and bias. This leads generally to ð xC q

p0 þ hg,E Q pE þ hg,jE Q jE þ hg,B Q nB þ hg,jC Q jC þ hg,C Q pC hg pdx ¼ hg,B0 Q

(A:3:25)

0 2

with

m n hg,v ¼ n0r ir mnv n2iv

and

v ¼ {B0, E, jE, B, jC, C}:

(A:3:26)

Choosing the base region as reference and assuming hg,B ¼ hg,B0, all weighting factors can be divided by hg,B giving for the normalized remaining weighting factors hg,v m n2 hv ¼ ¼ nB iB hg,B mnv n2iv

with

v ¼ {E, jE, jC, C},

(A:3:27)

which are considered to be model parameters. Inserting the above expression and charge components into (A.3.15), and making again the valid assumption hi ¼ hw ¼ 1 yields the GICCR as the final expression for 1D-HBTs [5] JT ¼ q2 VT mnB n2iB

exp (VB0 E0 =VT ) exp (VB0 C0 =VT ) p,T Q

(A:3:28)

with the modified (‘‘transfer current related’’) charge density p,T ¼ Q pE þ hjE Q jE þ Q jC þ hC Q pC , p0 þ DQ p,T ¼ Q p0 þ hE Q nB þ hjC Q Q

(A:3:29)

in which—as for BJTs—still a bias-independent hole charge, Qp0, and a bias-dependent portion can be distinguished. According to Refs. [5,8], and also as Figure A.3.4 shows, (A.3.28) with (A.3.29) using bias-independent values for hn leads to a significant improvement over the conventional ICCR (A.3.20). Thus, the GICCR results in an accurate description of the transfer current characteristics and the respective derivatives over the entire bias range of interest (up to high current densities). Again, as in Figure A.3.3, the charges and weighting factors have been calculated directly from device simulation results to avoid any errors introduced by analytical approximations. For ‘‘ideal’’ doping profiles like in Figure A.3.1, the weighting factors hn in (A.3.2) can be calculated analytically using (A.3.15). This aids the physical understanding of the impact of the Ge profile on device characteristics and shall be demonstrated below for two Ge profile examples. However, the calculation can be extended to other profiles but just becomes more elaborate.


A.3-10

page 10 5.11.2007 12:17pm Compositor Name: JGanesan


101

JC (mA/µm2)

100

10−1

10−2

10−3 X X 0.6

X

X

X

X

X

0.65

X

X

X

X

X

0.7

X

X

X

X

X

X

XXXXXXXXXX XX XX XX XX

0.75 VBE (V)

0.8

0.85

FIGURE A.3.4 Transfer current density for the 120 GHz HBT: comparison between device simulation (symbols) and analytical calculations from Equation A.3.15 (solid line), Equation A.3.28 (dashed line), Equation A.3.24 (dotted line), and Equation A.3.28 without QpE þ QpC (dash-dotted line).

Box Ge Profile in the (Metallurgical) Base Region In this case, mn n2i is constant over the base region and the portion of the space–charge regions that are associated with the base. For the sake of simplicity, low injection is assumed first. Setting mnr n2ir ¼ mnB n2iB yields hg ¼ 1 already in the integral over the base region and, thus, hjE ¼ hjC ¼ 1. In the emitter and collector region, hE ¼ mnB n2iB =mnE n2iE >> 1 and hC ¼ mnB n2iB =mnC n2iC >> 1, respectively, due to the much larger bandgap in those regions. As a consequence of this bandgap, the hole charges Q pE and Q pC are very small and do not significantly impact the dynamic transistor behavior, regardless of the respective doping profile. However, according to (A.3.28) these charges can have a significant impact on the transfer current due to the large weighting factors hE and hC. The respective terms hE QpE and hC QpC in (A.3.28) actually cause the ‘‘saturation’’ of the IC(VBE) characteristics at high injection observed in Figure A.3.2b. In HBTs with a box Ge profile, Equation A.3.28 can be simplified to [5] exp (VB0 E0 =VT ) exp (VB0 C0 =VT ) JT ¼ q2 VT mnB n2iB pE þ (hC 1)Q pC , Qp þ (hE 1)Q

(A:3:30)

which contains the total hole charge as a lumped variable and correction factors in the denominator. In pC is described directly by a compact expression rather than separately by Ref. [8], the product (hC 1)Q the weighting factor and charge component.

Trapezoidal Profile in the (Metallurgical) Base Region Consider the Ge profile in Figure A.3.1b. For the sake of simplicity it is assumed that the Ge mole fraction mGe and the respective bandgap voltage increase over the width of the neutral base (x0 2 [xe0,xc0]) only, but stay constant across the space–charge regions. Choosing the Si-base without Ge contents as reference material, the bandgap voltage differences DVGp ¼ DVG(x0 ¼ xe0) and DVGx ¼ DVG(x0 ¼ xc0), respectively, can be defined. Hence, the intrinsic carrier density within the neutral base with the width wB0 ¼ xc0 xe0 can be written as



A.3-11


DVGp þ aG (x 0 xe0 ) n2i ¼ n2iB,Si exp VT

(A:3:31)

with the slope factor aG ¼ (DVGx DVGp)/wB0. Neglecting the (much smaller) dependence of the mobility on field and Ge contents, and applying the above relation to (A.3.16) with p0 ¼ NB yields for the bias-independent term xðC

q 0

mnr n2ir p0 dx 0 ffi q mn n2i

xðc0 xe0

DVGp þ aG (x 0 xe0 ) NB dx 0 exp VT

(A:3:32)

which gives after evaluating the r.h.s. integral xðC

q 0

mnr n2ir mn n2i

p0 dx 0 ffi

VT aG

h i DV Gx exp VTGp exp DV VT wB0

p0 ¼ hg,B0 Q p0 Q

(A:3:33)

p0 ¼ qNB wB0 . As can be seen, the average weighting factor depends exponentially on the bandgap with Q voltages at the beginning and the end of the neutral base. For the bias-dependent portion in (A.3.16), one can write at low current densities xðC

q

2 6 hg Dpdx ffi q4

xðe0 xe

0

exp

N B dx 0 þ DVGp VT

xðc xc0

xðjC

3

N n B dx 0 þ dx 0 7 5 ~xe0 ) DVGp þaG (x 0 n DVGx ~ exp n exp VT VT x

(A:3:34)

jE

The first two terms represent the depletion components that are only to be evaluated between the SCR boundary (i.e., xe, xc) at the given bias point and the respective equilibrium SCR boundaries (i.e., xe0, xc0); it also has been assumed that the bandgap (i.e., Ge mole) change within (xe0xe) and (xc0xc) is jC ¼ qNB (xc xc0 ). For jE ¼ qNB (xe0 xe ) and Q still negligible. The resulting depletion charges are Q the case that the electric field in the base due to Ge grading causes the electrons to travel with saturation drift velocity vs , i.e. n ¼ JT/(qvs) does not depend on x0 , the resulting base minority charge is then Q nB ¼ JT wB/vs. With these charge expressions, one obtains after evaluating all terms on the r.h.s. of (A.3.34) xðC

q 0

DVGp DVGx nB , QjE þ exp QjC þ hg,B0 Q hg Dpdx ffi exp VT VT

(A:3:35)

where the last term follows the same evaluation as (A.3.32). The final step is to insert the components in (A.3.33) and (A.3.35) back into (A.3.15) and to normalize the denominator to the base weighting factor, hgB0 given by Equation A.3.33. The resulting expression then reads mnB,Si n2iB,Si exp (VB0 E0 =VT ) exp (VB0 C0 =VT ) JT ¼ q2 VT jE þ hjC Q jC þ Q nB : p0 þ hjE Q hi hw hg ,B0 Q |fflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflffl} c10

(A:3:36)

which has the same form as (A.3.28), but for low current densities and with known analytical expressions of the weighting factors from the above analysis: DV exp VTGp v exp (v) , ¼ hjE ¼ exp (v) 1 hg,B0

Gx exp DV VT v hjC ¼ : ¼ exp (v) 1 hg,B0

(A:3:37)


A.3-12



with v ¼ [DVGX DVGP]/VT as normalized bandgap difference between beginning and end of the base region (cf. Figure A.3.1b) . The dependence of the weighting factors as a function of v is shown in Figure A.3.5 for a practically relevant range. From the above results, the forward Early voltage at low injection, can be calculated: VEf ¼

p p0 exp (v) 1 Q Q : v hjC CjCi CjCi

(A:3:38)

According to (A.3.37), a 20% difference in Ge across the base region corresponds to an about 40 times increase in Early voltage, which is a significant enhancement factor over a Si-BJT or a SiGe HBT with a Ge box profile (v ¼ 0). In addition to the strong variation in ni, the mobility varies within the transistor as a function of both doping and bias (via the electric field). The variation caused by the latter is most pronounced in the BC junction and collector region. In general, mn and ni possess an opposite dependence on doping, leading to a partial compensation within hg. However, the influence of ni still remains much stronger than that of mn. As a consequence, the weighting function hg always deviates strongly from 1 and has to be considered for all processes.

A.3.5

Further Extensions

All of the considerations so far apply to a 1D transistor structure and quasistatic operation. Extensions in both directions have been investigated and proposed. A solution of the time-dependent continuity equation led to the transient ICCR (TICC) [10], in which the ‘‘in-phase’’ component gives the same expression as the ICCR for the for q.s. transfer current, while the ‘‘out-of-phase’’ solution yields a physical definition of the charging currents flowing through the E and C contact. Hence, the out-ofphase solution defines a physics-based capacitance matrix associated with the E and C terminals, that includes the case of non-quasistatic operation. Extensions of the TICC towards including recombination and non-1D effects were presented in, for example, Ref. [11]. The application of the TICC results in a compact model, however, is quite challenging due to the bias-dependent weighting functions in the integrals defining the charging components.

6 5

hjE, hjC

4 hjE 3 2 1 hjC 0

0

1

2

3 v

4

5

6

FIGURE A.3.5 Weighting factors of the depletion charges according to Equation A.3.37 as a function of the normalized bandgap difference v ¼ (DVGx DVGp)/VT .



A.3-13


As shown in Ref. [7], it is possible to extend the GICCR to two- and three-dimensional transistor structures. The respective derivation is beyond the scope of this chapter, but the result shall be briefly discussed. For instance, the resulting 2D-GICCR reads h i Bcon ) exp (VB0 E0 =VT ) exp (VB0 C0 =VT 2(yBconbþb þ 2bbBcon E E , (A:3:39) IT ¼ c10 Qp0,T þ DQp,T where the constant c10 depends on an enlarged (effective) emitter width bE ¼ bE0 þ 2

ð yBcon bE0 =2

wn (x ¼ 0,y) dy: exp VT

(A:3:40)

bE0 is the emitter window width, yBcon is the edge of the base contact or polysilicon next to the emitter, and bBcon is the base contact or polysilicon width on mon-silicon. DQp,T is defined as in (A.3.29), but now includes, among others, the impact of electron current crowding. This also applies to Qp0,T, which introduces a bias-dependent geometry dependence at higher current densities. In practice, Qp0,T can be approximated by a constant value to first order.

A.3.6

Summary

A set of integral charge-control relations has been derived and put in perspective to the (classical) literature. It was shown that a ‘‘master’’ equation exists, from which integral charge-control relations of different complexity and accuracy can be derived. The most general form, that is suitable for accurately describing the transfer current in a compact model for HBTs and BJTs, is the GICCR, which includes bandgap differences in the various device regions and also contains the weakest assumptions among the known theories for the transfer current. The GICCR is a powerful tool to analytically derive the relationship between transfer current, stored charges, and physical as well as structural parameters of a transistor. The GICCR can be very accurate, provided that the respective weigthing factors as a function of device structure and the hole charge as a function of bias are accurately modeled. Notice that the latter is a prerequisite for the description of high-speed applications in any way. Also, since the hole charge has to be continuously differentiable with respect to bias, the transfer current is also automatically continuously differentiable over all bias regions and, hence, is modeled via a single-piece formulation. This is a very desirable feature of the (G)ICCR for compact models. Applying the ‘‘master’’ equation to compact modeling requires partitioning of the hole charge and analytical approximations for its various components. These measures as well as the determination of charge model parameters and appropriate weighting factor values introduce additional inaccuracies with respect to the results shown here, which are unavoidable though for any compact model equation.

Acknowledgment The author would like to thank H. Tran for performing simulations and model calculations.

References 1. J.L. Moll and J.M. Ross, The dependence of transistor parameters on the distribution of base layer resistivity, Proc. IRE, 44, 1956, S72–S78. 2. H.N. Ghosh, F.H. De La Moneda, and N.R. Dono, Computer-aided transistor design, characterization, and optimization, Proc. IEEE, 55, 1967, 1897–1912. 3. H.K. Gummel, A charge-control relation for bipolar transistors’’, Bell System Technical J., 49, 1970, S115–S120.


A.3-14



4. H. Kroemer, Two-Integral equations pertaining to the electron transport through a bipolar transistor with nonuniform energy gap in the base region, Solid-State Electron., 28, 1985, 1101–1103. 5. M. Schroter, M. Friedrich, and H.-M. Rein, A generalized integral charge-control relation and its application to compact models for silicon based HBTs, IEEE Trans. Electron Dev., 40, 1993, 2036– 2046. 6. H.-M. Rein, H. Stu¨bing, and M. Schroter, Verification of the integral charge-control relation for high-speed bipolar transistors at high current densities, IEEE Trans. Electron Dev., 32, 1985, 1070– 1076. 7. M. Schroter, A compact physical large-signal model for high-speed bipolar transistors with special regard to high current densities and two-dimensional effects, PhD thesis (in German), RuhrUniversity Bochum, Bochum, Germany, 1988. 8. M. Friedrich and H.-M. Rein, Analytical current–voltage relations for compact SiGe HBT models, IEEE Trans. Electron Dev., Vol. ED-46, 2001, 1384–1401. 9. J.J. Ebers and J.L. Moll, Large-signal behavior of junction transistors, Proc. IRE, 42, 1761–1772, 1954. 10. H. Klose and A. Wieder, The transient integral charge–control relation — a novel formulation of the currents in a bipolar transistor, IEEE Trans. Electron Dev., ED-34, 1090–1099, 1987. 11. J.S. Hamel and C.R. Selvakumar, The general transient charge–control relation: a new charge– control relation for semiconductor devices, IEEE Trans. Electron Dev., ED-38, 1467–1476, 1991.


page 1


A.4 Sample SiGe HBT Compact Model Parameters

Ramana M. Malladi IBM Microelectronics

This appendix contains a sample set of compact model parameters for a representative 0.3216.8 mm2 first-generation npn SiGe HBT with a peak fT of 50 GHz, for each of the three dominant higher-order SiGe compact models available in the public domain and in leading circuit simulators: HICUM, MEXTRAM, and VBIC. Each model was carefully calibrated to a comprehensive set of measured dc and ac data.

A.4-1

Parameter Description Constant for ICCR (= Is.qp0) Zero-bias hole charge in the base High-current correction to account for 2D and 3D effects BE depletion charge weighting factor for HBTs BC depletion charge weighting factor for HBTs Forward nonideality factor for transfer current for HBTs Emitter minority charge weighting factor for HBTs Collector minority charge weighting factor for HBTs Internal BE sauration current Internal BE non-ideality factor Peripheral BE saturation current Peripheral BE non-ideality factor Internal BE saturation current (recombination) Internal BE non-ideality factor (recombination) Peripheral BE saturation current (recombination) Peripheral BE non-ideality factor (recombination) Internal BC saturation current Internal BC saturation current ideality factor External BC saturation current External BC saturation current ideality factor BE tunneling saturation current BE tunneling factor Avalanche current factor Exponent for avalanche current Internal base resistance at zero bias Extrinsic base resistance Correction factor for modulation by BE and BC SCR Geometry factor for current crowding Ratio of internal to total minority charge Ratio of shunt capacitance (parallel to Rbi) to total internal capacitance Emitter series resistance Extrinsic collector series resistance CS diode saturation current

Name c10 qp0 ich hjei hjci mcf hfe hfc ibeis mbei ibeps mbep ireis mrei ireps mrep ibcis mbci ibcxs mbcx ibets abet favl qavl rbi0 rbx fdqr0 fgeo fqi fcrbi re rcx iscs

Group

Transfer current

Base–emitter currents

Base–collector currents

Base–emitter tunnelling current

Base–collector avalanche current

Series resistances — base, emitter, and collector

Emitter

Collector

Substrate transistor

TABLE A.4.1 HICUM (v 2.1) SiGe HBT Model Parameters

41021 A

23 V

3V

20 V 6V 0.2 0.67 1.0 0

page 2

19.3 V1 1501015 C

11021 A 36

1.51018 A 1.02 21019 A 2

A

A

A

A

A.4-2

71020 1.005 71022 1 11017 2 11020 2

8.51031 A2 S 1.41013 C 10 A 2 0.1 1 1 0.2

Value

Cressler / Measurement and Modeling of Silicon Heterostructure Devices 66927_A004 Final Proof 18.10.2007 3:41pm Compositor Name: JGanesan


401015 F 0.6 V 0.3 11010 V 2.61012 sec 0.91012 sec 0.71012 sec

Thermal resistance Thermal capacitance Internal zero-bias BE depletion capacitance Internal BE built-in voltage Internal BE grading coefficient Maximum internal depletion capacitance divided by cjei0 Peripheral zero-bias BE depletion capacitance Peripheral BE built-in voltage Peripheral BE grading coefficient Maximum peripheral depletion capacitance divided by cjep0 Emitter oxide (overlap) capacitance Internal zero-bias BC depletion capacitance Internal BC built-in voltage Internal BC grading coefficient Punch-through voltage of internal BC junction External zero-bias BC depletion capacitance External BC built-in voltage External BC grading coefficient Punch-through voltage of external BC junction BC overlap capacitance Partitioning factor for cjcx and ccox over rbx Zero-bias CS depletion capacitance CS built-in voltage CS grading coefficient Punch-through voltage of CS junction Low current forward transit time at Vcb ¼ 0 V Time constant for base and BC space charge layer width modulation Time constant for modeling carrier jam at low Vce Neutral emitter storage time Exponent for current dependence of neutral emitter storage time

rth cth cjei0 vdei zei aljei cjep0 vdep zep aljep ceox cjci0 vdci zci vptci cjcx0 vdcx zcx vptcx ccox fbc cjs0 vds zs vpts t0 dt0h tbvl tef0 gtfe

Self-heating

Base–emitter junction capacitance

Base–collector junction capacitance

Collector–substrate junction capacitance

Diffusion capacitances/transit times — low currents

High currents

Sample SiGe HBT Compact Model Parameters (Continued)

page 3

401015 sec 1.0

71015 F 0.7 V 0.3 2.5 V 301015 F 0.73 V 0.4 100 V 2.51015 F 0.8

351015 F 1.0 V 0.32 2.0 51015 F 1.0 V 0.32 2.2 181015 F

700 K/W 350 pJ/K

50 V (layout dependent) 31018 F

Substrate resistance Substrate capacitance

rsu csu

Substrate network

1 2.51019 A 1 1 21012 sec

CS diode non-ideality factor Transfer saturation current of substrate transistor Forward non-ideality factor of substrate transfer current Reverse non-ideality factor of substrate transfer current Transit time (forward operation) — substrate

msc itss msf msr tsf


A.4-3

Flicker noise factor Flicker noise exponent factor Noise factor for internal base resistance Measurement temperature Bandgap voltage Temperature coefficient of current gain Temperature coefficient of favl Temperature coefficient of qavl Temperature coefficient for mobility in epi-collector (i.e., for collector resitance) Relative temperature coefficient of saturation drift velocity Relative temperature coefficient of vces Temperature coefficient for mobility in internal base (i.e., for internal base resistance) Temperature coefficient for mobility in extrinsic base (i.e., for extrinsic base resistance) Temperature coefficient for mobility in extrinsic collector (i.e., for extrinsic collector resistance) Temperature coefficient for emitter resistance First-order temperature coefficient of t0 Second-order temperature coefficient of t0

kf af krbi tnom vgb alb alfav alqav zetaci alvs alces zetarbi zetarbx zetarcx zetare alt0 kt0

Noise parameters

Temperature effect parameters

Factor for additional delay time of minority charge Factor for additional delay time of transfer current

Saturation time constant at high current densities Smoothing factor for current dependence of base and collector transit time Factor for partitioning this into base and collector portion Internal C-E saturation voltage Internal collector resistance at low electric field Voltage separating ohmic (low field) and saturation velocity (high field) regime Collector punch-through voltage Storage time for inverse operation

thcs alhc fthc vces rci0 vlim vpt tr alqf alit

Parameter Description

Name

25 C 1.17 V 6103 5105 K1 2104 K1 1.6 1103 K1 0.4103 K1 0.6 0.2 0.2 0 1103 K1 1105 K2

22106 2.5 1

0.125 0.45

251012 sec 0.53 0.6 0.1 V 20 V 0.7 V 15 V 201012 sec

Value

A.4-4

Non-quasistatic effects

Group

TABLE A.4.1 HICUM (v 2.1) SiGe HBT Model Parameters (Continued)

Cressler / Measurement and Modeling of Silicon Heterostructure Devices 66927_A004 Final Proof page 4 18.10.2007 3:41pm Compositor Name: JGanesan


Parameter Description Transistor main saturation current Knee current for high-injection effects in the base Ideal forward current gain Saturation-current of the non-ideal forward base current Non-ideality factor of the non-ideal forward base current Sidewall component of ideal base current Ideal reverse current gain Saturation current of the non-ideal reverse base current Cross-over voltage of the non-ideal reverse base current Partitioning factor for the extrinsic region Reverse Early voltage Forward Early voltage Epilayer thickness used in weak-avalanche model Voltage determining curvature of avalanche current Current spreading factor of avalanche model (when exavl ¼ 1) Emitter resistance Constant part of the base resistance Zer-bias value of the bias-dependent base resistance Constant part of the collector resistance Resistance of the un-modulated epilayer Space charge resistance of the epilayer Critical current for velocity saturation in the epilayer Smoothness parameter for the onset of quasi-saturation Zero-bias emitter–base depletion capacitance Emitter–base diffusion voltage Emitter–base grading coefficient Fraction of the emitter–base depletion capacitance that belongs to the side-wall Emitter–base overlap capacitance Zero–bias collector–base depletion capacitance Collector–base diffusion voltage Colector–base grading coefficient Constant part of cjc

Name is ik bf ibf mlf xibi bri ibr vlr xext ver vef wavl vavl sfh re rbc rbv rcc rcv scrcv ihc axi cje vde pe xcje cbeo cjc vdc pc xp

Group

Forward and reverse currents

Early voltage

Weak avalanche

Resistances and quasisaturation



TABLE A.4.2 MEXTRAM 504 SiGe HBT Model Parameters


71015 F 0.75 V 0.28 1103

page 5

421015 F 0.9 V 0.23 0 181015 F

3.0 V 6V 20 V 17 V 52 V 54 V 3.56103 A 0.21

2.44107 M 0.63 V 1.7

4.8 V 65 V

51018 A 4.5102 A 95 21017 A 1.545 0 3.77 1.71015 A 1102 V 0.19

Value


A.4-5

0.34 0 1.22 1.88 8.7107 1 0.76 3.75102 V 4.38102 V 1.15 V 1.18 V 1.15V 0.236 V

Temperature coefficient of the zero-bias base charge Temperature coefficient of the resistivity of the emitter Temperature coefficient of the resistivity of the base Temperature coefficient of the resistivity of the epilayer Temperature coefficient of the resistivity of the extrinsic base Temperature coefficient of the resistivity of the buried layer Temperature coefficient for Iss and Iks (for a closed buried layer, as¼ac and for an open buried layer, as¼aepi) Bandgap voltage difference for forward current gain Bandgap voltage difference for reverse current gain Bandgap voltage of the base Bandgap voltage of the collector Bandgap voltage: recombination of the emitter–base junction Bandgap voltage difference of emitter stored charge Exponent of the flicker noise Flicker-noise coefficient of the ideal base current Flicker noise coefficient of the non-ideal base current Base-substrate saturation current Base-substrate high-injection knee current Thermal resistance Thermal capacitance

aqbo ae ab aepi aex ac as dvgbf dvgbr vgb vgc vgj dvgte af kf kfn iss iks rth cth

Temperature coeffcients

1/f Noise

Substrate transistor

Self-heating network

700 K/W 350 pJ/K

2.51019 A 50 A

A.4-6

page 6

2.5 22106 201012

0.03 eV 0

Bandgap difference over the base Pre-factor of the recombination part of ideal base current

deg xrec

Diffusion capacitances/transit times

HBT parameters

451015 F 0.6 V 0.3 1.17 V 0.388 521015 sec 1.441012 sec 14.41012 sec 201012 sec

Zero-bias collector–substrate depletion capacitance Collector–substrate diffusion voltage Collector–substrate grading coefficient Bandgap voltage of the substrate Non-ideality factor for the emitter stored charge Minimum transit time of stored emitter charge Transit time of stored base charge Transit time of stored epilayer charge Transit time of reverse extrinsic stored base charge

0.5 8.7102 2.51015 F

Coefficient for the current modulation of the collector–base depletion capacitance Fraction of the collector–base depletion capacitance under the emitter Collector–base overlap capacitance

mc xcjc cbco cjs vds ps vgs mtau taue taub tepi taur

Value


Name


Group

TABLE A.4.2 MEXTRAM 504 SiGe HBT Model Parameters (Continued)



Parameter Description Transport saturation current (collector) Ideal base–emitter saturation current Nonideal base–emitter saturation current Ideal base–collector saturation current Nonideal base–collector saturation current Parasitic transport saturation current Ideal parasitic base–collector saturation current Nonideal parasitic base–collector saturation current Ideal parasitic base–emitter saturation current Nonideal parasitic base–emitter saturation current Forward emission coefficient Ideal base–emitter emission coefficient Nonideal base–emitter emission coefficient Reverse emission coefficient Ideal base–collector emission coefficient Nonideal base–collector emission coefficient Parasitic forwad emission coefficent Ideal parasitic base–collector emission coefficient Nonideal parasitic base–collector emission coefficient Forward knee current Reverse knee current Parasitic knee current Base–collector weak avalanche parameter 1 Base–collector weak avalanche parameter 2 Intrinsic base resistance Extrinsic base resistance Parasitic base resistance Emitter resistance Extrinsic collector resistance Substrate resistance Thermal resistance Thermal capacitance

Name is ibei iben ibci ibcn isp ibcip ibcnp ibeip ibenp nf nei nen nr nci ncn nfp ncip ncnp ikf ikr ikp avc1 avc2 rbi rbx rbp re rcx rs rth cth

Group

Saturation currents and ideality factors

Knee currents

Avalanche breakdown

Series resistances

Self-heating

TABLE A.4.3 VBIC SiGe HBT Model Parameters


700 K/W 350 pJ/W

page 7

20 V 6V 1V 3V 23 V 50 V

19.2 23.6 V

4.5102 A 4.8103 A 10 A

11040 A 2.521018 A 11028 A 1.0003 1.026 2.5 1 1.02 1.00 1.00 1.00 2

4.851018 A 71020 A 11015 A 1.51018 A 11034 A 31019 A

Value


A.4-7

Intrinsic collector resistance Epi drift saturation voltage Epi doping parameter High-current RC factor Epi-charge parameter Forward Early voltage Reverse Early voltage Base–emitter zero-bias capacitance Base–emitter grading coefficient Base–emitter built-in potential Extrinsic base–emitter overlap capacitance Forward bias depletion capacitance limit Base–emitter capacitance switching parameter Base–collector intrinsic zero-bias capacitance Base–collector grading coefficient Base–collector built-in potential Extrinsic base–collector overlap capacitance Base–collector extrinsic zero bias capacitance Base–collector capacitance switching parameter Substrate–collector zero bias capacitance Substrate–collector grading coefficient Substrate–collector built-in potential Fixed collector–substrate capacitance Substrate–collector capacitance switching parameter Forward transit time Coefficient of tf dependence of ic Coefficient of tf dependence of Vbc Variation of tf with base-width modulation Forward excess-phase delay time Activation energy Activation energy Activation energy Activation energy Activation energy

rci vo gamm hrcf qco vef ver cje me pe cbeo fc aje cjc mc pc cbco cjep ajc cjcp ms ps ccso ajs tf itf vtf qtf td ea eaie eaic eais eanc

Quasi-saturation parameters

Early effect parameters




Transit times and their bias dependence

Temperature effect parameters

1.17 V 1.17 V 1.17 V 1.17 V 1.17 V

21012 sec 0.32 23.7 0 0.71012 sec

401015 F 0.3 0.6 V 3e18 F 0.9

71015 F 0.3 0.7 V 2.51015 F 301015 F 0.1

42 fF 1.0 0.3 V 181015 F 0.93 0.1

65 V 5.5 V

40 V 11010 V 51013 V 11013 1.41015

Value

A.4-8

page 8

for is for ibei for ibci and ibeip for ibcip for ibcn/ibenp


Name

Group

TABLE A.4.3 VBIC SiGe HBT Model Parameters (Continued)



eane eans xii xin xis xre xrb xrc xrs xvo tavc

Activation energy for iben Activation energy for ibcnp Temperature coefficient for ibei, ibci, ibeip, and ibcip Temperature coefficient for iben, ibcn, ibenp, and ibcnp Temperature coefficient for is Temperature coefficient for re Temperature coefficient for rbi Temperature coefficient for rc Temperature coefficient for rs Temperature coefficient for vo Temperature coefficient for avc2

1.17 V 1.17 V 2.0 2.0 1.9 0 0 0 0 0 250106 V


Sample SiGe HBT Compact Model Parameters


A.4-9


A.4-10



References 1. HICUM bipolar transistor model: http://www.iee.et.tu-dresden.de/iee/eb/comp_mod.html. 2. Mextram bipolar transistor model: http://www.semiconductors.phillips.com/acrobat/other/phillipsmodels/NLUR2000811_7.pdf. 3. VBIC bipolar transistor model: http://www.designers-guide.org/VBIC/references.html.


page 1

25.10.2007 6:09pm Compositor Name: BMani

Index A AC device measurement techniques, 4-1 AC extraction and calibration, 5-8 AC measurement techniques, 4-2–4-10 calibration, 4-5–4-7 instrumentation, 4-4–4-5 S-parameter, 4-2–4-6 Activation energy, boron, 5-5 Atmospheric pressure CVD (AP-CVD), 2-3 Avalanche current and curvature voltage, 7-10

B Bandgap engineering, 1-3–1-4, 2-2–2-4 Base transit time, A.2-4 BC depletion capacitance, 7-2 BC leakage diode, crossover voltage of, 7-9 BE junction, base current, 6-9 Bipolar complementary metal oxide semiconductor (BiCMOS) technology, 1-2 Bipolar junction transistor (BJT), 2-4, 7-1 current densities, 6-8 DC and AC characteristics, 5-3 geometry scaling equations for, 6-10 mextram equivalent circuit of, 7-1–7-2 structures, 5-2 technologies, 5-2

C Carrier mobilities, electrons and holes, 5-6 Chemical-mechanical polishing (CMP), 8-6–8-7 Chemical vapor deposition (CVD), 2-3 Chip design assembly, 8-10 chip finishing, 8-11 electrostatic discharge (ESD), 8-10 phase shift mask (PSM), 8-11 Chip interconnects cross section dimensions of, 10-5 electrical interconnects, 10-4 Circuit parasitic noise effects, 9-9–9-10 Code division multiple access (CDMA), 1-6 Collector resistance, lumped elements, 6-7

Collector-substrate region, distributed RC network, 6-6 Communication circuit design Communication circuit design, noise prediction, 6-8 Computer-aided design (CAD) tools, 8-1 chemical-mechanical polishing (CMP), 8-6 circuit simulators and layout versus schematic (LVS) tools, 8-4 design rule checking (DRC), 8-6 electrical rule check (ERC), 8-7 inductor layout in, 8-5 physical layout, 8-4 programmable cells and programmable devices, 8-5 Constant base resistance, ohmic part of base region, 7-7 Conventional emitter doping (CED) transistors, A.3-3 Crossover voltage, VLR, 7-9 Current-modulation coefficient, MC, 7-12

D De-embedding techniques improvements in, 11-3–11-4 noise, 11-11 open-short, 11-5 OPEN test structure, 11-2 S-parameters of, 4-8, 11-1 and structure, 10-6 on wafer, 4-7–4-10, 10-6, 11-1 Depletion capacitance parameters, 7-11–7-12 Depletion charge, 6-4 Design for manufacturing (DFM) approach, 8-7 Design rule checking (DRC), process layers, 8-6 Device under test (DUT) four-port error network, 4-6 four-port I–V relation of, 11-12 frequency-dependent behavior, 4-4 layout of, 11-6 network parameters, 4-8, 4-10 2-port y-parameters, 11-4 reference plane, 4-5 S-parameters of, 4-3, 4-4 terminal characteristics of, 4-5 test structure, de-embedding process S-parameters of, 11-7, 11-10 Y-parameter of, 11-3–11-6 transmission lines, 4-4 two-port networks, 4-2

I-1


I-2

page 2



Differential amplifier circuit, 8-3 Diffusion charges, epilayer transit time TEPI, 7-13 Diode partition factor, XIBI, 7-9 Direct conversion receiver, substrate coupling, 9-3 Distributed and non-quasi-static charges, 7-14 Drift-diffusion equation, one dimensional, 7-3

Gummel-Poon model integral charge, 7-2, 7-10 integral charge control relationship, 7-2, 7-4, 7-13 knee current parameter of, 7-5 transfer current, 7-1

H E EB recombination current prefactor, 7-8 Electric field distribution, 7-10 Electron quasi-Fermi potentials, 6-4, 7-3, 7-4, 7-5 Electrostatic discharge (ESD), 8-10 Emitter diffusion charge coefficient, 7-13 out-diffusion, 5-3–5-4 perimeter junction with BC junction, 6-6 transit time bandgap voltage difference, 7-13, 7-15 Emitter-base interface, 5-7 Emitter-base spacer process, transient frequency of, 5-10 Emitter-coupled-logic (ECL) ring oscillator, 2-4 Epilayer carrier concentrations distribution, 7-6 current, 7-7 diffusion charge, 7-13 effective width, WAVL, 7-10 electron current density, 7-6 permittivity of, 7-7 quasi-Fermi potential, 7-5 resistance, 7-6 space charge resistance, 7-7 transfer current, 7-12 External base-emitter region, 6-6 Extrinsic quasi-neutral regions, 7-9–7-10

F Four-port error network and DUT network(s), 4-6 Four-port method noise de-embedding, 11-11 S-parameter, 11-9, 11-10

G Ge content, valence and conduction bands, 5-6 effective mass parameters, A.1-2 energy band structure, A.1-1 properties of, A.1-2 related parameter, 7-15 Generalized ICCR (GICCR), A.3-2–A.3-6, A.3-13 Geometry partitioning factors, depletion capacitances, 7-12 Global positioning systems (GPS), 1-6 Global system for mobile communications (GSM), 1-6 Ground-signal-ground (GSG) microwave probes, 4-7 Gummel number, 7-4

HBT breakdown simulation models, 5-7 HBT devices characteristics geometry scaling equations for, 4-10 H-parameters, 4-2 forward Gummel curves, DC calibration, 5-7 Heterojunction transistors, charge control relation, A.3-9–A.3-12 HICUM technology, 6-2 base resistance, 6-9 charge storage, 6-4 collector current, 6-5 frequency-dependent current, 6-6 geometry scaling effects, 6-8 high-frequency transistor behavior, 6-11 internal transistor, 6-2 material parameters, 6-8 small-signal model (SSM), 6-11 substrate transistor parameter, 6-7 weak avalanche model, 6-6 HICUM (v 2.1) SiGe HBT model parameters, A.4-2–A.4-4 High electron mobility transistors (HEMTs), 1-8 High-injection parameters, extraction, 7-17 High-injection therm gBH, 7-5 High-level design language (HDL), 8-10 High-speed SiGe HBTs, 5-3 Homojunction transistors, charge control relation, A.3-6–A.3-9 H-parameters, 4-3–4-5

I Impedance mismatch, 4-3–4-4 Integral charge-control relation (ICCR), A.3-2 hetereojunction transistors, A.3-9–A.3-12 homojunction transistors, A.3-6–A.3-9 Integrated circuit design analog and digital PRML, 8-2 design simulation, 8-4 phases of, 8-2 process design kit (PDK), 8-1 Interconnect extraction modeling, 9-6 Interconnect parasitics inductance, 9-7 modeling versus extracting, 9-6–9-7 Internal BE and BC depletion charges, 6-3–6-4 Intrinsic device y-parameters, 11-2 Intrinsic transistor region, 7-8 Isolation capacitance, 6-7


page 3


I-3

Index

K Knee current (IK), 7-5 Kroemer’s approach, A.2-4

L LEFT test structure, de-embedding process S-parameters of, 11-7 Y-parameter, 11-5–11-7 Limited-reaction-processing CVD (LRP-CVD), 2-2–2-4 Linear-time-invariant (LTI) system, 4-2 Loop-based inductance, 9-8 Loss-less transmission line, 4-3, 4-4 Low-emitter concentration (LEC) transistors, A.3-3 Low-Injection Parameters extraction, 7-17 Low-noise amplifier (LNA), 6-8, 10-7, 10-10 circuit of, 10-10 microstrip lines of, 10-11 Low-temperature epitaxial process, emitter polysilicon, 5-3 Low-temperature Si epi growth techniques, 2-3 LRM/LRRM (Line-Reflect-Match, Line-ReflectReflect-Match), calibration, 4-7

M Metal interconnects design, 10-1 inductance estimation of, 9-8 Metal stack, parasitic capacitance, 8-10 MEXTRAM 504 model parameters, A.4-5–A.4-6 Mextram model, SiGe HBTs avalanche current Iavl, 7-10 base diffusion charge, 7-12 BE and BC depletion charges, 7-5 depletion capacitances, 7-11 equivalent circuit, 7-2 high-injection therm gBH, 7-5 nodal biases, 7-4 parameters, 7-2 substrate current, 7-10 transfer current, 7-1 Microstrip line interconnect RLCZ parameters, 10-7 S-parameter, 10-8–10-9 Microstrip transmission line, constant capacitance, 10-4 Model parameters, SiGe HBTs carrier mobility temperature, 6-15 methodology for, 6-10 physics-based model, 6-11 process-specific parameters, 6-13 test structures, 6-11– 6-15 VER and VEF, 7-5 Moll-Ross collector current density relation, A.2-3

Moll-Ross relation assumptions for, A.2-1 generalized, A.2-2 Moore’s law, 1-8 MOSFET layout cell representations for, 8-8 design practices, 8-8 parameters, 8-3

N Network parameters, linear network, 4-2–4-4, 4-9–4-10 Noise current model correlation matrix, 1-12 equivalent circuit of, 11-11 four-port parasitics, 1-12 Nonphysical parameters, passive elements, 8-4, 8-9 N-port networks, 4-2

O One-port S-parameters, 4-5 On-wafer parasitics equivalent circuits of, 11-3, 11-8 OPEN test structure, 11-2 operating frequency, 11-2 two-port networks, 11-3 Open- and short-circuit connections, passive elements of, 4-3 Open test structure, de-embedding process equivalent circuit of, 11-2 S-parameters of, 11-7, 11-10 Y-parameter, 11-2, 11-4, 11-5–11-6 Optical proximity correction (OPC), 8-11

P Parasitic extraction (PEX), 8-9–8-10 Parasitic inductance effects, 9-7 Parasitic RLC tools, 8-9 Parasitics model four port, 11-3, 11-4 I–V characteristic of, 11-3 y-parameters, 11-4 Partial equivalent electrical circuit (PEEC), 9-8 Passive devices, parasitic effects, 9-1 Pinch-in effect, 6-6 PNP transistor saturation current, ISS, 7-10 Poisson Equation, 7-6–7-7 Polysilicon emitter, 5-4 Power amplifier, 10-9 Predictive model extraction, TCAD process genetic algorithm (GA) model, 5-10 parameter optimization, 5-11


I-4

page 4



Q Quasi-neutral base (QNB), SiGe HBTs, 7-1, 7-3 BE space–charge region, 7-7 boundaries, 7-2 diffusion charges, 7-12 doping and bandgap distribution, 7-4 electron current density Jn, 7-3 Ge profile, 7-2 Gummel number, 7-4 modulation rate, 7-5 non-quasi-static effects, 7-14 recombination in, 7-8 transfer saturation current, 7-4 width modulation, 7-8 Quasi-neutral emitter (QNE) diffusion charges, 7-12, 7-13 hole injection, 7-7

R Recombination currents, 7-7 Reference temperature, TREF, 7-15–7-16 Reverse base transit time, TAUR, 7-14 Reverse Gummel plot, 7-18 RF-AMS IC design flow, 9-3 RF custom libraries, 8-2 RF MOSFET, model subcircuit, layout representation of, 8-4 RIGHT test structure, de-embedding process frequency behavior of, 10-4 S-parameters of, 11-7 Y-parameter, 11-5–11-7

S Saturation current, IBR, 7-9 Semi-automated S-parameter measurement system, 4-5 Shallow-trench isolation, 8-9 Shockley boundary condition, generelized, A.2-2, A.2-3 Shockley-Read-Hall (SRH) recombination, 7-9 Short-Open-Load-Reciprocal reciprocal standard, 4-6 Thru standard, 4-7 Short-Open-Load-Thru, 4-6 SHORT test structure, de-embedding process S-parameters of, 11-7, 11-10 Y-parameter, 11-2–11-6 Si effective mass parameters, A.1-2 energy band structure, A.1-1 properties of, A.1-2 Si-based high electron mobility transistors (HEMTs), 1-10 light emitters, 1-10 optoelectronic superchip, 1-10 transistor(s), 1-2, 1-9

SiGe alloys, 1-4, 2-1 device simulation AC extraction and calibration, 5-8 DC calibration, 5-7 RF simulations, 5-8 epitaxial layer boron diffusion, 5-4 diffusion coefficients, 5-3 simulated B profiles, 5-5–5-6 fabrication facilities, 1-6 ICs, applications, 1-7–1-8 integrated circuits, 9-2 process simulation, 5-2–5-3 wireless transceiver, 1-8 SiGe BiCMOS technology, 5-3 noise resistance versus frequency, 6-12 transit frequency fT versus collector current, 6-12 SiGe:C channel pMOSFET, 2-8 HBT technology, 2-6 silicidation of, 2-11 SiGe HBT BiCMOS technology, 2-5 generations, 1-5, 1-9–1-10 SiGe HBTs current density, 11-10 cutoff frequency versus collector current, 7-18–7-19 development of, 2-3–2-6 epitaxial base in, 5-4 graded Ge base profile, A.2-4 high-power, 2-6 model parameters VER and VEF, 7-5 performance of, 7-8 self-aligned emitter-base structures, 5-8 simulated fT and fmax characteristics, 5-9 S-parameter characteristics, 5-9, 11-9 static current gain versus collector current of, 7-17 technology generations, performance of, 1-9–1-10 temperature-scaling parameters, 7-15 thermal phenomena, 7-14–7-16 transfer current, 6-5 SiGe-Si strained layer epitaxy, development, 2-2–2-3 SiGe-strained Si FETs , development of, 2-6–2-8 Silicon Germanium RF designs, 9-1 Silicon heterostructures characterization of, 4-1, 4-2 devices, output characteristics, 7-18 S-parameters for, 4-10 Silicon process technology, 9-5 SIMS profiles, 5-5 Single-base transistor, 6-9 Si-SiGe bipolar transistor, 6-3 Si-strained layer epitaxy, 1-4 SOLR, See Short-Open-Load-Reciprocal


page 5


I-5

Index SOLT, See Short-Open-Load-Thru Space-charge layer, 6-4 regions, current injection, 7-8 S-parameter measurement, device under test (DUT) calibration, 4-5–4-7 C–V measurement, 4-10 instrumentation, 4-4–4-5 linear network, 4-3 load conditions in, 4-4 power-level selection, 4-10 two-port network, 4-2 SPICE Gummel-Poon model, 6-13 STI, See Shallow-trench isolation Strained Si CMOS, 1-2, 1-6, 1-8–1-10, 2-11 Strained Si fabrication facilities, 1-6 Strained Si nMOSFET, 2-8 Substrate coupling, floor planning, 9-10 current, 7-10–7-11 isolation, chip floor plans, 9-5 knee current, IKS, 7-10 Substrate noise components, DC and RF, 9-9 coupling, 9-2–9-3 guard ring structures, 9-9 injection, 9-2–9-3 modeling, 9-4–9-5 Switching functions, loading capacitance, 9-9 Synchronous optical network (SONET), 1-6

network, 10-3 on-chip interconnects, 10-6 skin depth, 10-4 S-parameters, 10-7 structures coplanar waveguides, 10-1, 10-2 microstrip lines, 10-1, 10-2 technology, 10-1 TRL (Thru-Reflect-Line), 4-7 Two-port network, H-parameters, 4-3

U Ultrahigh vacuum chemical vapor deposition (UHV/CVD), 2-3

V VBIC model, circuit design, 5-11 VBIC SiGe HBT model parameters, A.4-7–A.4-9 Vector network analyzer (VNA) four-port error network, 4-6 noise floor, 4-10 one-port S-parameters, 4-5 S-parameter, 4-4 voltage-wave measurement, 4-5 Voltage-controlled oscillators (VCOs), 8-4 Voltage wave, 4-3, 4-4, 4-5, 4-7

W T Technology computer-aided design (TCAD) numerical process and device simulation, 5-1 peak device optimizations performance, 5-10 simulated test structures, 9-6 Temperature-scaling parameter, 7-16 TRADICA program, operation principle of, 6-11 Transfer current, 7-2–7-3 Transient ICCR (TICC), A.3-2 Transmission line characteristic impedance of, 4-3, 4-4 interconnect, Y-parameters, 10-3, 10-4 measurements, 10-5

Wafer devices, 4-5 Weak avalanche current, 7-10 effects, 7-7

Y Y-elements modeling, 10-5 Y-parameters, 4-8

Z Z-elements, modeling, 10-3–10-4


page 6


Measurement and Modeling of Silicon Heterostructure Devices

Measurement and Modeling of Silicon Heterostructure Devices

Applications of silicon-germanium heterostructure devices

High-speed heterostructure devices

High Speed Heterostructure Devices

Silicon Quantum Integrated Circuits: Silicon-Germanium Heterostructure Devices: Basics and Realisations

Silicon Devices: Structures and Processing

Silicon Carbide Power Devices

Silicon carbide power devices

Modeling of photonic devices

Physics and Technology of Amorphous-Crystalline Heterostructure Silicon Solar Cells

Strained-Si Heterostructure Field Effect Devices

Instabilities in Silicon Devices : New Insulators Devices and Radiation Effects

Nanotechnology and Nanoelectronics: Materials, Devices, Measurement Techniques

Nanotechnology and Nanoelectronics: Materials, Devices, Measurement Techniques

Nanotechnology and Nanoelectronics: Materials, Devices, Measurement Techniques

Silicon Germanium : Technology, Modeling, and Design

Nanotechnology and Nanoelectronics: Materials, Devices, Measurement Techniques

Strained-Si Heterostructure Field Effect Devices (Material Science and Engineering)

Silicon VLSI technology: fundamentals, practice, and modeling

Silicon Germanium: Technology, Modeling, and Design

Measurement and Analysis of Radiation Effects in Devices and ICS

POWER HVMOS Devices Compact Modeling

Floating Gate Devices: Operation and Compact Modeling

Optoelectronic Devices: Design, Modeling, and Simulation

Optoelectronic Devices: Design, Modeling, and Simulation

Floating Gate Devices: Operation and Compact Modeling

Measurement Data Modeling and Parameter Estimation

Physics and modeling of tera-and nano-devices

Theory of Semiconductor Quantum Devices: Microscopic Modeling and Simulation Strategies

Measurement and Modeling of Silicon Heterostructure Devices